Image not available
Illustrative purposes only
ZY7120LG-T2
NON ISO- ADJUST O/P DC TO DC CONVERTERS
⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
- Manufacturer: BEL / PARTNER STOCK
- Product type: DC / DC Non Isolated Board Mount Converters - Adjustable Output
- SVHC: To Be Advised
- Product Range: -
| Delivery and price | |
|---|---|
| Units per pack | 15 |
| Price | 39.29 € |
| Current stock | 500+ |
| Lead time | 30 days |
Datasheet
_**ZY7120 20A DC-DC Intelligent POL Data Sheet**_ _**3V to 13.2V Input 0.5V to 5.5V Output**_
-
- \power-onAS Changing the Shape$$$ ofPower _**3V to 13.2V Input 0.5V to 5.5V Output**_
## _**Member of the Family**_
## **Features**
- RoHS lead free and lead-solder-exempt products are available
- Wide input voltage range: 3V–13.2V
- High continuous output current: 20A
- Wide programmable output voltage range: 0.5V–5.5V
- Active digital current share
- Single-wire serial communication bus for frequency synchronization, programming, and monitoring
- Optimal voltage positioning with programmable slope of the VI line
## **Applications**
- Low voltage, high density systems with Intermediate Bus Architectures (IBA)
- Point-of-load regulators for high performance DSP, FPGA, ASIC, and microprocessor applications
- Desktops, servers, and portable computing
- Broadband, networking, optical, and communications systems
- Active memory bus terminators
## **Benefits**
- Integrates digital power conversion with intelligent power management
- Eliminates the need for external power management components
- Completely programmable via industry-standard I[2] C communication bus
- One part that covers all applications
- Reduces board space, system cost and complexity, and time to market
- Overcurrent, overvoltage, undervoltage, and overtemperature protections with programmable thresholds and types
- Programmable fixed switching frequency 0.5-1.0MHz
- Programmable turn-on and turn-off delays
- Programmable turn-on and turn-off voltage slew rates with tracking protection
- Programmable feedback loop compensation
- Power Good signal with programmable limits
- Programmable fault management
- Start up into the load pre-biased up to 100%
- Full rated current sink
- Real time voltage, current, and temperature measurements, monitoring, and reporting
- Small footprint SMT package: 8x32mm
- Low profile of 14mm
- Compatible with conventional pick-and-place equipment
- Wide operating temperature range
- UL 60950-1/CSA 22.2 No. 60950-1-07 Second Edition, IEC 60950-1: 2005, and EN 60950-1:2006
## **Description**
Power-One‟s point-of-load converters are recommended for use with regulated bus converters in an Intermediate Bus Architecture (IBA). The ZY7120 is an intelligent, fully programmable step-down point-of-load DC-DC module integrating digital power conversion and intelligent power management. When used with ZM7300 Series Digital Power Managers, the ZY7120 completely eliminates the need for external components for sequencing, tracking, protection, monitoring, and reporting. All parameters of the ZY7120 are programmable via the industry-standard I[2] C communication bus and can be changed by a user at any time during product development and service.
Page 1 of 33
ZD-00194 Rev. 2.7, 5-May -2011
**www.power-one.com**
_**ZY7120 20A DC-DC Intelligent POL Data Sheet**_ _**3V to 13.2V Input 0.5V to 5.5V Output**_ ————————l ofTotPower
## **Reference Documents:**
- ZM7300 Digital Power Manager Data Sheet
- ZM7300 PrgManual - Digital Power Manager Programming Manual
- Power-One I2C GEN II Graphical User Interface
- ZM00056-KIT USB to I[2] C Adapter Kit. User Manual
**1. Ordering Information**
|**ZY**|**71**|**20**|**x**|**y**|**–**|**zz**|
|---|---|---|---|---|---|---|
|**Product**<br>**family:**<br>Z-One<br>Module|**Series:**<br>Intelligent<br>POL<br>Converter|**Output**<br>**Current:**<br>20A|**Output voltage setpoint**<br>**accuracy:**<br>**L**– 1.2% or 20mV,<br>whichever is greater.<br>**H1**– 1.0% or 10mV,<br>whichever isgreater|**RoHS compliance:**<br>**No suffix**- RoHS<br>compliant with Pb<br>solder exemption**2**<br>**G**- RoHS compliant<br>for all six substances|**Dash**|**Packaging Option3: **<br>**T1**– 500pcs T&R<br>**T2**– 100pcs T&R<br>**T3**– 50pcs T&R<br>**Q1**– 1pc sample for<br>evaluation only|
______________________________________
1 Contact factory for availability.
2 The solder exemption refers to all the restricted materials except lead in solder. These materials are Cadmium (Cd), Hexavalent chromium (Cr6+), Mercury (Hg), Polybrominated biphenyls (PBB), Polybrominated diphenylethers (PBDE), and Lead (Pb) used anywhere except in solder.
3 Packaging option is used only for ordering and not included in the part number printed on the POL converter label. 4 The evaluation board is available in only one configuration: ZM7300-KIT-HKS.
Example: **ZY7120HG-T2** : A 100-piece reel of RoHS compliant POL converters with the output voltage setpoint of 1.0% or 10mV, whichever is greater. Each POL converter is labeled ZY7120HG.
## **2. Absolute Maximum Ratings**
Stresses in excess of the absolute maximum ratings may cause performance degradation, adversely affect longterm reliability, and cause permanent damage to the converter.
|**Parameter**|**Conditions/Description**|**Min**|**Max**|**Units**|
|---|---|---|---|---|
|Operating Temperature|Controller case temperature|-40|105|C|
|Input Voltage|250ms Transient||15|VDC|
|Output Current|(See Output Current Derating Curves)|-20|20|ADC|
## **3. Environmental and Mechanical Specifications**
|**Parameter**|**Conditions/Description**|**Min**|**Nom**|**Max**|**Units**|
|---|---|---|---|---|---|
|Ambient Temperature Range||-40||85|C|
|Storage Temperature(Ts)||-55||125|C|
|Weight||||15|grams|
|MTBF|Calculated Per Telcordia Technologies SR-332|6.14|||MHrs|
|Peak Reflow Temperature|ZY7120<br>ZY7120G||245|220<br>260|C<br>C|
|Lead Plating|ZY7120 and ZY7120G|100% Matte Tin||||
|Moisture Sensitivity Level|ZY7120 and ZY7120G|3||||
Page 2 of 33
ZD-00194 Rev. 2.7, 5-May -2011
**www.power-one.com**
_**ZY7120 20A DC-DC Intelligent POL Data Sheet**_ power-one—SN $$$ _**3V to 13.2V Input**_ _**0.5V to 5.5V Output**_
## **4. Electrical Specifications**
Specifications apply at the input voltage from 3V to 13.2V, output load from 0 to 20A, ambient temperature from - 40°C to 85°C, 100F output capacitance, and default performance parameters settings unless otherwise noted.
## **4.1 Input Specifications**
|**4.1**<br>**Input Specifications**||||||
|---|---|---|---|---|---|
|**Parameter**|**Conditions/Description**|**Min**|**Nom**|**Max**|**Units**|
|Input voltage (VIN)|At VIN<4.75V, VLDO pin needs to be<br>connected to an external voltage source<br>higher than 4.75V|3||13.2|VDC|
|Input Current (at no load)|VIN4.75V, VLDO pin connected to VIN||50||mADC|
|Undervoltage Lockout (VLDO<br>connected to VIN)|Ramping Up<br>RampingDown||4.2<br>3.75||VDC<br>VDC|
|Undervoltage Lockout (VLDO<br>connected to VAUX=5V)|Ramping Up<br>RampingDown||3.0<br>2.5||VDC<br>VDC|
|External Low Voltage Supply|Connect to VLDO pin when VIN<4.75V|4.75||13.2|VDC|
|VLDO Input Current|Current drawn from the external low<br>voltage supplyat VLDO=5V||50||mADC|
|**4.2**<br>**Output Specifications**||||||
|---|---|---|---|---|---|
|**Parameter**<br>~~Ge~~|**Conditions/Description**<br>~~Ge~~|**Min**<br>~~Ge~~|**Nom**<br>~~Ge~~|**Max**<br>~~Ge~~|**Units**<br>~~Ge~~|
|Output Voltage Range (VOUT)<br>~~ee~~<br>~~es~~|Programmable1<br>Default(noprogramming)<br>~~ee~~<br>~~ee~~|0.5<br>~~ee~~<br>~~ee~~|0.5<br>~~ee~~<br>~~ee~~|5.5<br>~~ee~~|VDC<br>VDC<br>~~ee~~|
|Output Voltage Setpoint Accuracy<br>~~ee~~<br>~~es~~<br>~~ee~~|VIN=12V, IOUT=0.5*IOUT MAX,<br>FSW=500kHz,roomtemperature<br>~~ee~~<br>~~ee~~<br>~~er~~|(See Ordering Information)<br>~~ee~~<br>~~ee~~|||~~ee~~|
|Output Current (IOUT)<br>~~es~~<br>~~ee~~|VIN MINto VIN MAX<br>~~ee~~<br>~~er~~|-202<br>~~ee~~|~~ee~~|20|ADC|
|Line Regulation<br>~~ee ~~<br>~~ee~~<br>~~ee~~|VIN MINto VIN MAX<br> ~~er~~<br>~~ee~~|~~ee~~|±0.3<br>~~ee~~|~~ee~~|%VOUT<br>~~ee~~|
|Load Regulation<br>~~ee~~|0 to IOUT MAX||±0.2||%VOUT|
|Dynamic Regulation<br>Peak Deviation<br>SettlingTime<br>~~ee~~|Slew rate 1A/s, 50 -100% load step<br>COUT=330F, FSW=1MHz<br>to10% ofpeakdeviation||75<br>50||mV<br>s|
|Output Voltage Peak-to-Peak<br>Ripple and Noise<br>BW=20MHz<br>Full Load|VIN=5.0V, VOUT=0.5V<br>VIN=5.0V, VOUT=2.5V<br>VIN=13.2V, VOUT=0.5V<br>VIN=13.2V, VOUT=2.5V<br>VIN=13.2V, VOUT=5.0V||10<br>20<br>15<br>35<br>50||mV<br>mV<br>mV<br>mV<br>mV|
|Temperature Coefficient<br>~~es~~<br>~~es~~|VIN=12V, IOUT=0.5*IOUT MAX<br>~~es~~<br>~~ee~~<br>|~~es~~<br>~~ee~~|20<br>~~es~~<br>~~ee~~|~~es~~<br>~~ee~~|ppm/°C<br>~~es~~|
|Switching Frequency<br>~~ee~~<br>~~es~~|Default<br>Programmable,250kHzsteps<br>~~ee~~<br>~~ee~~<br>~~ee~~|500<br>~~ee~~<br>~~ee~~<br>~~ee~~|500<br>~~ee~~<br>~~ee~~<br>~~ee~~|1,000<br>~~ee~~<br>~~ee~~<br>~~ee~~|kHz<br>kHz<br>~~ee~~|
|Duty Cycle Limit<br>~~es~~|Default<br>Programmable,1.56% steps<br>~~ee~~<br>~~ee~~|0<br>~~ee~~<br>~~ee~~|90.5<br>~~ee~~<br>~~ee~~|95<br>~~ee~~<br>~~ee~~|%<br>%|
1 ZY7120 is a step-down converter, thus the output voltage is always lower than the input voltage as show in Figure 1.
2 At the negative output current (bus terminator mode) efficiency of the ZY7120 degrades resulting in increased internal power dissipation. Therefore maximum allowable negative current under specific conditions is 20% lower than the current determined from the derating curves shown in paragraph 5.5.
Page 3 of 33
ZD-00194 Rev. 2.7, 5-May -2011
**www.power-one.com**
_**ZY7120 20A DC-DC Intelligent POL Data Sheet**_ poer-one-— $$$ _**3V to 13.2V Input 0.5V to 5.5V Output**_
**==> picture [407 x 322] intentionally omitted <==**
**----- Start of picture text -----**<br>
VOUT<br>[V]<br>5.5<br>5.0<br>4.5<br>4.0<br>3.5<br>3.0<br>2.5<br>2.0<br>1.5<br>1.0<br>Min Load 0.2A<br>0.5<br>2.0 4.0 6.0 8.0 10.0 12.0 14.0<br>3.0 3.15 5.5 6.25 13.2 VIN [V]<br>**----- End of picture text -----**<br>
**Figure 1. Output Voltage as a Function of Input Voltage and Output Current**
## **4.3 Protection Specifications**
|**Parameter**|**Conditions/Description**|**Min**|**Nom**|**Nom**|**Max**|**Max**|**Units**|
|---|---|---|---|---|---|---|---|
|**Output Overcurrent Protection**||||||||
|Type|Default<br>Programmable|Non-Latching, 130ms period<br>Latching/Non-Latching||||||
|Threshold|Default<br>Programmable in 11 steps|50|140||140||%IOUT<br>%IOUT|
|Threshold Accuracy||-25|||25||%IOCP.SET|
|**Output Overvoltage Protection**||||||||
|Type|Default<br>Programmable|Non-Latching, 130ms period<br>Latching/Non-Latching||||||
|Threshold|Default<br>Programmable in 10% steps|1101|130|130||%VO.SET<br>%VO.SET||
|Threshold Accuracy|Measured at VO.SET=2.5V|-2||2||%VOVP.SET||
|Delay|From instant when threshold is exceeded until<br>the turn-off command isgenerated||6|||μs||
Page 4 of 33
ZD-00194 Rev. 2.7, 5-May -2011
**www.power-one.com**
_**ZY7120 20A DC-DC Intelligent POL Data Sheet**_ _**3V to 13.2V Input 0.5V to 5.5V Output**_ o£ { oo
|~~Cn~~|~~Cn~~|~~Cn~~|~~Cn~~|~~Cn~~|~~Cn~~|~~Cn~~|~~Cn~~|~~Cn~~|
|---|---|---|---|---|---|---|---|---|
|**Output Undervoltage Protection**<br>~~Cn~~|||||||||
|Type<br>~~Cn~~|Default<br>Programmable<br>~~Cn~~|Non-Latching, 130ms period<br>Latching/Non-Latching|||||||
|Threshold<br>~~ee~~|Default<br>Programmable in 5% steps|75|75||85||%VO.SET<br>%VO.SET||
|Threshold Accuracy<br>~~ee~~|Measured at VO.SET=2.5V|-2|||2||%VUVP.SET||
|Delay<br>~~ee~~<br>~~PC~~|From instant when threshold is exceeded until<br>the turn-off command isgenerated<br>||6<br>||||μs<br>||
|**Overtemperature Protection**<br>~~PC~~|||||||||
|Type<br>~~PC~~|Default<br>Programmable<br>|Non-Latching, 130ms period<br>Latching/Non-Latching<br>|||||||
|Turn Off Threshold<br>~~es~~|Temperature is increasing<br>~~es~~|~~es~~||130<br>~~es~~||~~es~~||C<br>~~es~~|
|Turn On Threshold<br>~~es~~<br>~~ee~~|Temperature is decreasing after the module was<br>shut down by OTP<br>~~es~~|~~es~~||120<br>~~es~~||~~es~~||C<br>~~es~~|
|Threshold Accuracy<br>~~ee~~||-5||||5||C|
|Delay<br>~~ee~~<br>~~Ce~~|From instant when threshold is exceeded until<br>the turn-offcommandis generated|||6||||μs|
|**Tracking Protection (when Enabled)**<br>~~Ce~~|||||||||
|Type<br>~~Ce~~<br>~~ee~~|Default<br>Programmable|Disabled<br>Latching/Non-Latching,130msperiod|||||||
|Threshold<br>~~ee~~<br>~~es~~|Enabled during output voltage ramping up<br>~~ee~~|~~ee~~||~~ee~~||250<br>~~ee~~||mVDC<br>~~ee~~|
|Threshold Accuracy<br>~~ee~~<br>~~es~~|~~ee~~|-50<br>~~ee~~||~~ee~~||50<br>~~ee~~||mVDC<br>~~ee~~|
|Delay<br>~~es~~|From instant when threshold is exceeded until<br>the turn-off command isgenerated<br>~~ee~~|~~ee~~||6<br>~~ee~~||~~ee~~||μs<br>~~ee~~|
|**Overtemperature Warning**<br>~~RC~~<br>~~esef~~|||||||||
|Threshold<br>~~es~~<br>~~es~~|Always enabled, reported in Status register<br>~~ef~~<br>~~ee~~|~~ef~~<br>~~ee~~||120<br>~~ef~~<br>~~ee~~||~~ef~~<br>~~ee~~||C<br>~~ef~~<br>~~ee~~|
|Threshold Accuracy<br>~~es~~<br>~~es~~<br>~~es~~|~~ef~~<br>~~ee~~|-5<br>~~ef~~<br>~~ee~~||~~ef~~<br>~~ee~~||5<br>~~ef~~<br>~~ee~~||C<br>~~ef~~<br>~~ee~~|
|Hysteresis<br>~~es~~<br>~~es~~|~~ee~~|~~ee~~||3<br>~~ee~~||~~ee~~||C<br>~~ee~~|
|Delay<br>~~es~~|From instant when threshold is exceeded until<br>thewarning signal is generated|||6||||μs|
|**Power Good Signal (PGOOD pin)**<br>~~|~~|||||||||
|Logic<br>~~|~~|VOUTis inside the PG window<br>VOUTis outside the PG window<br>~~|~~|High<br>Low<br>~~|~~||||||N/A<br>~~|~~|
|Lower Threshold|Default<br>Programmable in 5% steps|90||90||95||%VO.SET<br>%VO.SET|
|Upper Threshold<br>~~a~~|~~a~~|~~a~~||110<br>~~a~~||~~a~~||%VO.SET<br>~~a~~|
|Delay<br>~~a~~<br>~~Rs~~|From instant when threshold is exceeded until<br>status of PG signalchanges<br>~~a~~|~~a~~||6<br>~~a~~||~~a~~||μs<br>~~a~~|
|Threshold Accuracy<br>~~Rs~~|Measured at VO.SET=2.5V|-2||||2||%VO.SET|
___________________
> 1 Minimum OVP threshold is 1.0V
Page 5 of 33
( ZD-00194 Rev. 2.7, 5-May -2011 ~~2)~~ **www.power-one.com** Page 5 of 33
_**ZY7120 20A DC-DC Intelligent POL Data Sheet**_ _**3V to 13.2V Input 0.5V to 5.5V Output**_ o£ { oo
**4.4 Feature Specifications**
|**4.4**<br>**Feature Specifications**||||||
|---|---|---|---|---|---|
|**Parameter**<br>~~I~~|**Conditions/Description**<br>~~I~~|**Min**<br>~~I~~|**Nom**<br>~~I~~|**Max**<br>~~I~~|**Units**<br>~~I~~|
|**Current Share**<br>~~Ce~~||||||
|Type<br>~~Ce~~<br>~~ee~~|~~Ce~~<br>~~ee~~|Active, Single Line<br>~~Ce~~<br>~~ee~~||||
|Maximum Number of Modules<br>Connectedin Parallel|IOUT MIN≥20%*IOUT NOM|10||||
|Maximum Number of Modules<br>Connected in Parallel|IOUT MIN=0|4||||
|Current Share Accuracy<br>~~ss~~<br>~~Ce~~|IOUT MIN≥20%*IOUT NOM<br>~~ss~~|~~ss~~|~~ss~~|±20<br>~~ss~~|%IOUT<br>~~ss~~|
|**Interleave**<br>~~Ce~~||||||
|Interleave (Phase Shift)<br>~~Ce~~<br>~~Ce~~|Default<br>Programmable in 11.25steps<br>|0<br>|0<br>|348.75<br>|Degree<br>degree<br>|
|**Sequencing**<br>~~Ce~~||||||
|Turn ON Delay<br>~~Ce~~|Default<br>Programmable in 1ms steps<br>|0<br>|0<br>|255<br>|ms<br>ms<br>|
|Turn OFF Delay<br>|Default<br>Programmable in 1ms steps<br>|0<br>|0<br>|63<br>|ms<br>ms<br>|
|**Tracking**<br>~~Cn~~||||||
|Turn ON Slew Rate<br>~~Cn~~|Default<br>Programmablein 7steps<br>~~Cn~~|0.1<br>~~Cn~~|0.1<br>~~Cn~~|8.331<br>~~Cn~~|V/ms<br>V/ms<br>~~Cn~~|
|Turn OFF Slew Rate<br>~~Ce~~|Default<br>Programmable in 7 steps<br>|-0.1<br>|-0.1<br>|-8.331<br>|V/ms<br>V/ms<br>|
|**Optimal Voltage Positioning**<br>~~Ce~~||||||
|Load Regulation<br>~~Ce~~|Default<br>Programmablein 7steps<br>|0<br>|0<br>|6.02<br>|mV/A<br>mV/A<br>|
|**Feedback Loop Compensation**<br>~~Cn~~||||||
|Zero1 (Effects phase lead and<br>increases gain in mid-band)<br>~~Cn~~|Programmable<br>~~Cn~~|0.05<br>~~Cn~~|~~Cn~~|50<br>~~Cn~~|kHz<br>~~Cn~~|
|Zero 2 (Effects phase lead and<br>increases gain in mid-band)|Programmable|0.05||50|kHz|
|Pole 1 (Integrator Pole, effects<br>loop gain)|Programmable|0.05||50|kHz|
|Pole 2 (Effects phase lag and<br>limits gain in mid-band)|Programmable|1||1000|kHz|
|Pole 3 (High frequency low- pass<br>filter to limit PWM noise)<br>~~RO~~|Programmable|1||1000|kHz|
|**Monitoring**<br>~~RO~~||||||
|Voltage Monitoring Accuracy<br>~~RO~~|1 LSB=22mV|-2%VOUT<br>– 1 LSB||2%VOUT<br>+ 1 LSB|mV|
|Current Monitoring Accuracy<br>~~ee~~|20%*IOUT NOM< IOUT< IOUT NOM<br>~~ee~~|-20<br>~~ee~~|~~ee~~|+20<br>~~ee~~|%IOUT<br>~~ee~~|
|Temperature Monitoring Accuracy<br>~~ee~~|Junction temperature of POL controller<br>~~ee~~|-5<br>~~ee~~|~~ee~~|+5<br>~~ee~~|C<br>~~ee~~|
|**Remote Voltage Sense (+VS and –VS pins)**<br>~~ee~~<br>~~Cn~~||||||
|Voltage Drop Compensation<br>~~Cn~~<br>~~ee~~<br>~~ee~~|Between +VS and VOUT<br>~~Cn~~<br>~~ee~~<br>~~es~~|~~Cn~~<br>~~ee~~|~~Cn~~<br>~~ee~~|300<br>~~Cn~~<br>~~ee~~|mV<br>~~Cn~~<br>~~ee~~|
|Voltage Drop Compensation<br>~~ee~~|Between -VS and PGND<br>~~es~~|||100|mV|
___________________
1 Achieving fast slew rates under specific line and load conditions may require feedback loop adjustment
( ZD-00194 Rev. 2.7, 5-May -2011 ~~2)~~ **www.power-one.com** Page 6 of 33
_**ZY7120 20A DC-DC Intelligent POL Data Sheet**_ _**3V to 13.2V Input 0.5V to 5.5V Output**_ o£ { oo
|~~es~~||||||
|---|---|---|---|---|---|
|**Parameter**<br>~~es~~<br>~~ee~~|**Conditions/Description**|**Min**|**Nom**|**Max**|**Units**|
|VDD<br>~~es~~<br>~~ee~~|Internal supply voltage|3.15|3.3|3.45|V|
|**SYNC/DATA Line (SD pin)**<br>~~ee~~<br>~~Ce~~<br>~~es~~||||||
|ViL_sd<br>~~Ce~~<br>~~es~~|LOW level input voltage<br>~~Ce~~|-0.5<br>~~Ce~~|~~Ce~~|0.3 x VDD<br>~~Ce~~|V<br>~~Ce~~|
|ViH_sd<br>~~es~~|HIGH level input voltage|0.75 x<br>VDD||VDD + 0.5|V|
|Vhyst_sd<br>~~ee~~|Hysteresis of input Schmitt trigger|0.25 x<br>VDD||0.45 x<br>VDD|V|
|VoL<br>~~ee~~<br>~~ee~~|LOW level sink current @ 0.5V|14||60|mA|
|Tr_sd<br>~~ee~~<br>~~ee~~<br>~~es~~|Maximum allowed rise time 10/90%VDD|||300|ns|
|Cnode_sd<br>~~ee~~<br>~~es~~<br>~~es~~|Added node capacitance||5|10|pF|
|Ipu_sd<br>~~es~~<br>~~es~~|Pull-up current source at Vsd=0V|0.3||1.0|mA|
|Freq_sd<br>~~es~~<br>~~ee~~|Clock frequency of external SD line<br>~~ee~~|475<br>~~ee~~|~~ee~~|525<br>~~ee~~|kHz<br>~~ee~~|
|Tsynq<br>~~ee~~|Sync pulse duration<br>~~ee~~|22<br>~~ee~~|~~ee~~|28<br>~~ee~~|% of clock<br>cycle<br>~~ee~~|
|T0<br>~~pC~~|Data=0 pulse duration|72||78|% of clock<br>cycle|
|**Inputs: ADDR0…ADDR4, EN, IM**<br>~~pC~~<br>~~esee~~||||||
|ViL_x<br>~~pC~~<br>~~es~~<br>~~es~~|LOW level input voltage<br>~~ee~~|-0.5||0.3 x VDD|V|
|ViH_x<br>~~es~~<br>~~es~~|HIGH level input voltage<br>~~ee~~|0.7 x VDD||VDD+0.5|V|
|Vhyst_x<br>~~es~~<br>~~ee~~|Hysteresis of input Schmitt trigger<br>~~es~~|0.1 x VDD<br>~~es~~|~~es~~|0.3 x VDD<br>~~es~~|V<br>~~es~~|
|RdnL_ADDR<br>~~ee~~|External pull down resistance<br>ADDRX forced low<br>~~es~~|~~es~~|~~es~~|10<br>~~es~~|kOhm<br>~~es~~|
|**Power Good and OK Inputs/Outputs**<br>~~eees~~<br>~~Ce~~||||||
|Iup_PG<br>~~Ce~~<br>~~se~~<br>~~es~~|Pull-up current source input forced low PG<br>~~Ce~~<br>~~se~~|25<br>~~Ce~~<br>~~se~~|~~Ce~~<br>~~se~~|110<br>~~Ce~~<br>~~se~~|μA<br>~~Ce~~<br>~~se~~|
|Iup_OK<br>~~se~~<br>~~es~~<br>~~ee~~|Pull-up current source input forced low OK<br>~~se~~|175<br>~~se~~|~~se~~|725<br>~~se~~|μA<br>~~se~~|
|ViL_x<br>~~es~~<br>~~ee~~<br>~~ee~~|LOW level input voltage|-0.5||0.3 x VDD|V|
|ViH_x<br>~~ee~~<br>~~ee~~<br>~~es~~|HIGH level input voltage|0.7 x VDD||VDD+0.5|V|
|Vhyst_x<br>~~ee~~<br>~~es~~<br>~~es~~|Hysteresis of input Schmitt trigger<br>~~ee~~|0.1 x VDD||0.3 x VDD|V|
|IoL<br>~~es~~<br>~~es~~<br>~~Ce~~|LOW level sink current at 0.5V<br>~~ee~~<br>|4<br>||20<br>|mA<br>|
|**Current Share Bus (CS pin)**<br>~~esee~~<br>~~Ce~~||||||
|Iup_CS<br>~~Cese~~|Pull-up current source at VCS = 0V<br>~~se~~|0.84<br>~~se~~|~~se~~|3.1<br>~~se~~|mA<br>~~se~~|
|ViL_CS<br>~~se~~<br>~~ee~~|LOW level input voltage<br>~~se~~<br>~~ee~~|-0.5<br>~~se~~<br>~~ee~~|~~se~~<br>~~ee~~|0.3 x VDD<br>~~se~~<br>~~ee~~|V<br>~~se~~<br>~~ee~~|
|ViH_CS<br>~~ee~~|HIGH level input voltage<br>~~ee~~|0.75 x<br>VDD<br>~~ee~~|~~ee~~|VDD+0.5<br>~~ee~~|V<br>~~ee~~|
|Vhyst_CS<br>~~es~~|Hysteresis of input Schmitt trigger<br>~~ee~~|0.25 x<br>VDD||0.45 x<br>VDD|V|
|IoL<br>~~es~~<br>~~es~~|LOW level sink current at 0.5V<br>~~ee~~|14||60|mA|
|Tr_CS<br>~~es~~<br>~~es~~|Maximum allowed rise time 10/90% VDD<br>~~ee~~|||100|ns|
Page 7 of 33
( ZD-00194 Rev. 2.7, 5-May -2011 ~~2)~~ **www.power-one.com** Page 7 of 33
_**ZY7120 20A DC-DC Intelligent POL Data Sheet**_ _**3V to 13.2V Input 0.5V to 5.5V Output**_
## TtT > >»>————————[ of][Power]
## **5. Typical Performance Characteristics**
**==> picture [504 x 439] intentionally omitted <==**
**----- Start of picture text -----**<br>
5.1 Efficiency Curves 94<br>92<br>96 — 90 So¢e2=====<br>9492 |FSFETI EEL_|S 8886 nyI 77Ae=yf |<br>90 84<br>88 = 82 a<br>V a<br>86 oaeeec— n e 80 n/aeee<br>84 SEE 78 FATE<br>76<br>82<br>SESS 74 EEE<br>80<br>{| pop | ft tt 72 es<br>78 TA SEE 70 —p Vout=1.2V Vout=2.5V<br>76 Vout=3.3V Vout=5.0V<br>yA 68 Sp<br>74 a, Vout=0.5V Vout=1.2V Vout=2.5V SQ 0 2 4 6 8 10 12 14 16 18 20<br>72 _ _ Output Current, A<br>0 2 4 6 8 10 12 14 16 18 20<br>Output Current, A Figure 4. Efficiency vs. Load. Vin=12V, Fsw=500kHz<br>96 Figure 2. Efficiency vs. Load. Vin=3.3V, Fsw=500kHz 9590 CFLLrLr<br>94<br>i Zo<br>92 r WALL 85 La<br>90<br>88 PAEee 80 eTAA<br>86<br>SPSS 75 Ye<br>84<br>FYE SS f+<br>82 SERRE 7065 CeCPE<br>80<br>78 SSeS 65 CPE<br>7674 nynyoe 60 p> - - Vin=3.3V Vin=5.0V Vin=12V<br>72 Vout=0.5V Vout=1.2V 0.5 1.5 2.5 3.5 4.5 5.5<br>Vout=2.5V Vout=3.3V<br>70 fees Output Voltage, V<br>0 2 4 6 8 10 12 14 16 18 20<br>Output Current, A<br>Efficiency, %<br>Efficiency, %<br>Efficiency, %<br>Efficiency, %<br>**----- End of picture text -----**<br>
**==> picture [225 x 219] intentionally omitted <==**
**----- Start of picture text -----**<br>
CFLLrLr<br>909590<br>Zo<br>85 La<br>80 eTAA<br>75 Ye<br>f+<br>7065 CeCPE<br>Vin=3.3V Vin=5.0V Vin=12V<br>60 p> - -<br>0.5 1.5 2.5 3.5 4.5 5.5<br>Output Voltage, V<br>Figure 5. Efficiency vs. Output Voltage, Iout=20A,<br>Fsw=500kHz<br>Efficiency, %<br>**----- End of picture text -----**<br>
**Figure 3. Efficiency vs. Load. Vin=5V, Fsw=500kHz**
Page 8 of 33
ZD-00194 Rev. 2.7, 5-May -2011
**www.power-one.com**
_**ZY7120 20A DC-DC Intelligent POL Data Sheet**_ _**3V to 13.2V Input 0.5V to 5.5V Output**_
**==> picture [506 x 702] intentionally omitted <==**
**----- Start of picture text -----**<br>
Wer ape ofPo~<br>95 | | 9089 -<br>90 ee 88 4<br>85 — 87<br>86 TE<br>80 Serr = 85 =e ~<br>84<br>75 83<br>82<br>70 HH<br>81<br>65 acooaSEE_ 80 FSECR=s1—<br>Vout=0.5V Vout=1.2V Vout=2.5V 79 ia Fsw=500kHz Fsw=750kHz Fsw=1,000kHz<br>60 i 78<br>3 4 5 6 7 8 9 10 11 12 0 2 4 6 8 10 12 14 16 18 20<br>Input Voltage, V Output Current, A<br>Figure 6. Efficiency vs. Input Voltage. Iout=20A, Fsw=500kHz Figure 8. Efficiency vs. Load. Vin=5V, Vout=1.2V<br>96 9493 =<br>95 a<br>92<br>94 ~ 91 oe<br>90<br>93 89<br>88 “fe<br>92 [ee 87<br>86 fi<br>91 as<br>85<br>90 _ oP [Se] HS oe 84 f SECtEEeBEERSsoooit_<br>Fsw=500kHz Fsw=750kHz Fsw=1,000kHz 83 Fsw=500kHz Fsw=750kHz a Fsw=1,000kHz<br>89 titiARE 82 fae<br>0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20<br>Output Current, A Output Current, A<br>Figure 7. Efficiency vs. Load. Vin=3.3V, Vout=2.5V Figure 9. Efficiency vs. Load. Vin=12V, Vout=5V<br>ZD-00194 Rev. 2.7, 5-May -2011 www.power-one.com Page 9 of 33<br>oe<br>Efficiency, %<br>Efficiency, % Efficiency, %<br>Efficiency, %<br>**----- End of picture text -----**<br>
_**ZY7120 20A DC-DC Intelligent POL Data Sheet**_ _**3V to 13.2V Input 0.5V to 5.5V Output**_
**==> picture [226 x 184] intentionally omitted <==**
**----- Start of picture text -----**<br>
94<br>93<br>92<br>91<br>90<br>89 Vin=3.3V, Vout=2.5V<br>88 Vin=5V, Vout=1.2V<br>87 Vin=12V, Vout=5V<br>86<br>85<br>84<br>83<br>82<br>500 750 1000<br>Switching Frequency, kHz<br>Efficiency, %<br>**----- End of picture text -----**<br>
**Figure 10. Efficiency vs. Switching Frequency. Iout=20A**
**Figure 12. Turn-On with Different Rising Slew Rates. Rising Slew Rates are Programmed as follows: V11V/ms, V2-0.5V/ms, V3-0.2V/ms. Vin=12V, Ch1 – V1, Ch2 – V2, Ch3 – V3**
## **5.2 Turn-On Characteristics**
**Figure 11. Tracking Turn-On. Rising Slew Rate is Programmed at 0.5V/ms. Vin=12V, Ch1 – V1, Ch2 – V2, Ch3 – V3**
**Figure 13. Sequenced Turn-On. Rising Slew Rate is Programmed at 1V/ms. V2 Delay is 2ms, V3 delay is 4ms. Vin=12V, Ch1 – V1, Ch2 – V2, Ch3 – V3**
Page 10 of 33
ZD-00194 Rev. 2.7, 5-May -2011
**www.power-one.com**
_**ZY7120 20A DC-DC Intelligent POL Data Sheet**_ _**3V to 13.2V Input 0.5V to 5.5V Output**_
## **5.3 Turn-Off Characteristics**
**Figure 14. Turn On with Sequencing and Tracking. Rising Slew Rate Programmed at 0.2V/ms, V1 and V3 delays are programmed at 20ms.**
**Vin=12V, Ch1 – V1, Ch2 – V2, Ch3 – V3**
**Figure 16. Tracking Turn-Off. Falling Slew Rate is Programmed at 0.5V/ms. Vin=12V, Ch1 – V1, Ch2 – V2, Ch3 – V3**
**==> picture [25 x 15] intentionally omitted <==**
**----- Start of picture text -----**<br>
Tek Run<br>**----- End of picture text -----**<br>
**Figure 15. Turn On into Prebiased Load. V3 is Prebiased by V2 via a Diode. Vin=12V, Ch1 – V1, Ch2 – V2, Ch3 – V3**
**Figure 17. Turn-Off with Tracking and Sequencing. Falling Slew Rate is Programmed at 0.5V/ms. Vin=12V, Ch1 – V1, Ch2 – V2, Ch3 – V3**
Page 11 of 33
~~ee~~ ZD-00194 Rev. 2.7, 5-May -2011 **www.power-one.com** Page 11 of 33
_**ZY7120 20A DC-DC Intelligent POL Data Sheet**_ _**3V to 13.2V Input 0.5V to 5.5V Output**_ —_<_—o— “mmo “‘ ‘ _“@“Omm im
## **5.4 Transient Response**
The pictures below show the deviation of the output voltage in response to the 50-100-50% step load at 1A/μs. In all tests the ZY7120 converters were switching at 1MHz and had 5x22μF and 5x47μF ceramic capacitors connected across the output pins. Bandwidth of the feedback loop was programmed for faster transient response.
**==> picture [27 x 13] intentionally omitted <==**
**----- Start of picture text -----**<br>
Tek stop<br>**----- End of picture text -----**<br>
**Figure 20. Vin=5V, Vout=2.5V, BW~45kHz**
**Figure 18. Vin=12V, Vout=5V, BW~40kHz**
**==> picture [152 x 9] intentionally omitted <==**
**----- Start of picture text -----**<br>
Figure 21. Vin=5V, Vout=1V, BW~40kHz<br>**----- End of picture text -----**<br>
**Figure 19. Vin=12V, Vout=1V, BW~35kHz**
**==> picture [159 x 9] intentionally omitted <==**
**----- Start of picture text -----**<br>
Figure 22. Vin=3.3V, Vout=1V, BW~40kHz<br>**----- End of picture text -----**<br>
Page 12 of 33
~~ee~~ ZD-00194 Rev. 2.7, 5-May -2011 **www.power-one.com** Page 12 of 33
_**ZY7120 20A DC-DC Intelligent POL Data Sheet**_ _**3V to 13.2V Input 0.5V to 5.5V Output**_
## **5.5 Thermal Derating Curves**
**==> picture [478 x 463] intentionally omitted <==**
**----- Start of picture text -----**<br>
20<br>18<br>16<br>eS<br>14 Se<br>12 od<br>10<br>0 LFM 100 LFM 200 LFM 400 LFM 600 LFM<br>|__| __| _F’3~~~<br>pS<br>8<br>35 45 55 65 75 85<br>Temperature, 'C<br>Figure 23. Thermal Derating Curves. Vin=13.2V, Vout=5.0V, Fsw=500kHz<br>20<br>19<br>18<br>oS<br>17<br>eo SS<br>a<br>16<br>0 LFM 100 LFM 200 LFM 400 LFM 600 LFM<br>15<br>65 70 75 80 85<br>Temperature, 'C<br>Output Current, A<br>Output Current, A<br>**----- End of picture text -----**<br>
**Figure 24. Thermal Derating Curves. Vin=5.0V, Vout=2.5V, Fsw=500kHz**
Page 13 of 33 ———— @&
ZD-00194 Rev. 2.7, 5-May -2011
**www.power-one.com**
_**ZY7120 20A DC-DC Intelligent POL Data Sheet**_ _**3V to 13.2V Input 0.5V to 5.5V Output**_ O—<— _$§ —_eoi < s$ _ —_—m[Power]
## **6. Typical Application**
**==> picture [498 x 180] intentionally omitted <==**
**----- Start of picture text -----**<br>
Intermediate Voltage Bus<br>SD<br>I [2] C DPM OK_C<br>OK_B<br>OK_A<br>CS<br>ZY7120 ZY7120 ZY7120 ZY7120<br>ADDR ADDR ADDR ADDR<br>V1 V2 V3<br>**----- End of picture text -----**<br>
**Figure 25. Block Diagram of Typical Multiple Output Application with Digital Power Manager and I2C Interface**
The block diagram of a typical application of ZY7120 point-of-load converters (POL) is shown in Figure 25. The system includes multiple POLs and a ZM7300 series Digital Power Manager (DPM). All POLs are connected to the DPM and to each other via a single-wire SD (sync/data) line. The line provides synchronization of all POLs to the master clock generated by the DPM and simultaneously performs bidirectional data transfer between POLs and the DPM. Each POL has a unique 5-bit address programmed by grounding respective address pins. To enable the current share, CS pins of POLs connected in parallel are linked together.
There are three groups of POLs in the application, groups A, B, and group C. A group is defined as a number of POLs interconnected via OK pins. Grouping of POLs enables users to program, control, and monitor multiple POLs simultaneously and execute advanced fault management schemes.
The complete schematic of the application is shown in Figure 26.
Page 14 of 33
ZD-00194 Rev. 2.7, 5-May -2011
**www.power-one.com**
_**ZY7120 20A DC-DC Intelligent POL Data Sheet**_ _**3V to 13.2V Input 0.5V to 5.5V Output**_
**Figure 26. Complete Schematic of the Application Shown in Figure 25. Intermediate Bus Voltage is from 4.75V to 13.2V.**
~~ee~~ ZD-00194 Rev. 2.7, 5-May -2011 **www.power-one.com** Page 15 of 33
## _**ZY7120 20A DC-DC Intelligent POL Data Sheet**_ _**3V to 13.2V Input 0.5V to 5.5V Output**_ O—<—“c§¥q“Mmom ofPower _§_|]@_$_$Om ——
## **7. Pin Assignments and Description**
|**Pin**<br>**Name**|**Pin**<br>**Number**|**Pin**<br>**Type**|**Buffer**<br>**Type**|**Pin Description**|**Notes**|
|---|---|---|---|---|---|
|VLDO<br>~~a ~~|1<br> ~~a~~|P<br>a|~~ee~~|Low Voltage Dropout<br>~~ee~~|Connect to an external voltage source higher than<br>4.75V,if VIN<4.75V.Connect toVIN,if VIN≥4.75V<br>~~ee~~|
|IM<br>~~a~~|2<br>~~a~~<br>~~a~~|~~a~~<br>~~a~~<br>~~a~~|~~a~~<br>~~a~~|Not Used<br>~~a~~<br>~~a~~|Leave floating|
|NC<br>~~a~~|3<br>~~a~~<br>~~a ~~|~~a~~<br> ~~a~~||Not Used|Leave floating|
|NC<br>~~a~~<br>~~a~~|4<br>~~a ~~<br>~~a~~|~~es~~<br>~~ee~~|~~es~~|Not Used|Leave floating|
|NC<br>~~a~~<br>~~a~~|5<br>~~a~~<br>~~a~~|~~ee~~<br>~~a~~||Not Used<br>~~ee~~|Leave floating|
|NC<br>~~a~~<br>~~a~~|6<br>~~a~~<br>~~a~~|~~ee~~<br>~~a~~||Not Used<br>~~ee~~|Leave floating|
|NC<br>~~a~~<br>~~aa~~|7<br>~~a ~~<br>~~aa~~|~~a~~<br>~~aa~~|~~aa~~|Not Used<br>~~ee~~|Leave floating|
|NC<br>~~a~~|8<br>~~aa ~~|~~a~~||Not Used|Leave floating|
|VREF<br>~~a~~|9<br>~~a~~<br>~~a~~|~~a~~<br>~~a~~<br>~~a~~|~~a~~<br>~~a~~|Not Used<br>~~a~~<br>~~a~~|Leave floating|
|EN<br>~~a~~|10<br>~~a~~<br>~~a ~~|~~a~~<br> ~~a~~||Connect to PGND|Connect to PGND|
|OK<br>~~a~~|11|I/O|PU|Fault/Status Condition|Connect to OK pin of other Z-POL and/or DPM.<br>Leavefloating,if not used|
|SD<br>~~a~~|12<br>~~a ~~|I/O<br> ~~a~~|PU|Sync/Data Line|Connect to SD pin of DPM|
|PGOOD<br>~~a~~|13<br>~~a~~<br>~~a~~|I/O<br>~~a~~<br>~~a~~<br>~~a~~|PU<br>~~a~~<br>~~a~~|Power Good<br>~~a~~<br>~~a~~||
|TRIM<br>~~a~~|14<br>~~a~~<br>~~a ~~|~~a~~<br> ~~a~~||Not Used|Leave floating|
|CS<br>~~a~~|15|I/O|PU|Current Share|Connect to CS pin of other Z-POLs connected in<br>parallel|
|ADDR4<br>~~a~~|16<br>~~a ~~|I<br> ~~a~~|PU|POL Address Bit 4|Tie to PGND for 0 or leave floating for 1|
|ADDR3<br>~~a~~|17<br>~~a~~<br>~~a~~|I<br>~~a~~<br>~~a~~<br>~~a~~|PU<br>~~a~~<br>~~a~~|POL Address Bit 3<br>~~a~~<br>~~a~~|Tie to PGND for 0 or leave floating for 1|
|ADDR2<br>~~a~~|18<br>~~a~~<br>~~a ~~|I<br>~~a~~<br> ~~a~~|PU|POL Address Bit 2|Tie to PGND for 0 or leave floating for 1|
|ADDR1<br>~~a~~|19<br>~~a~~<br>~~a~~|I<br>~~a~~<br>~~a~~<br>~~a~~|PU<br>~~a~~<br>~~a~~|POL Address Bit 1<br>~~a~~<br>~~a~~|Tie to PGND for 0 or leave floating for 1|
|ADDR0<br>~~a~~|20<br>~~a~~<br>~~a ~~|I<br>~~a~~<br> ~~a~~|PU|POL Address Bit 0|Tie to PGND for 0 or leave floating for 1|
|-VS<br>~~a~~|21<br>~~a~~<br>~~a~~|I<br>~~a~~<br>~~a~~<br>~~a~~|PU<br>~~a~~<br>~~a~~|Negative Voltage Sense<br>~~a~~<br>~~a~~|Connect to the negative point close to the load|
|+VS<br>~~a~~<br>~~a~~|22<br>~~a~~<br>~~a~~<br>~~a~~|I<br>~~a~~<br>~~a~~<br>~~ee~~|PU<br>~~se~~|Positive Voltage Sense<br>~~se~~<br>~~ee~~|Connect to the positive point close to the load<br>~~se~~|
|VOUT<br>~~a~~<br>~~a~~|23<br>~~a~~<br>~~a~~|P<br>~~ee~~<br>~~a~~||Output Voltage<br>~~ee~~<br>~~ee~~||
|PGND<br>~~a ~~<br>~~a~~|24<br> ~~a~~<br>~~a~~|P<br>~~ee~~<br>~~a~~||Power Ground<br>~~ee~~<br>~~ee~~||
|VIN<br>~~a ~~<br>~~a~~|25<br> ~~a ~~<br>~~a~~|P<br> ~~a~~||Input Voltage<br>~~ee~~||
Legend: I=input, O=output, I/O=input/output, P=power, A=analog, PU=internal pull-up
Page 16 of 33
ZD-00194 Rev. 2.7, 5-May -2011 **www.power** ~~a~~ **-one.com**
_**ZY7120 20A DC-DC Intelligent POL Data Sheet**_ _**3V to 13.2V Input 0.5V to 5.5V Output**_
## **8. Programmable Features**
Performance parameters of ZY7120 POL converters can be programmed via the industry standard I[2] C communication bus without replacing any components or rewiring PCB traces. Each parameter has a default value stored in the volatile memory registers detailed in Table 1. The setup registers 00h through 14h are programmed at the system powerup. When the user programs new performance parameters, the values in the registers are overwritten. Upon removal of the input voltage, the default values are restored.
**Table 1. ZY7120 Memory Registers**
||**Table 1. ZY7120 Memory Registers**|**Table 1. ZY7120 Memory Registers**|
|---|---|---|
|**Register**|**Content**|**Address**|
|PC1|ProtectionConfiguration 1|00h|
|PC2<br>~~es~~|ProtectionConfiguration 2|01h|
|PC3<br>~~es~~|Protection Configuration 3|02h|
|DON<br>~~es~~|Turn-On Delay|05h|
|DOF|Turn-Off Delay|06h|
|TC<br>~~es~~|Tracking Configuration<br>~~oo~~|03h<br>~~oo~~|
|INT<br>~~es~~|Interleave Configuration and<br>Frequency Selection<br>~~oo~~|04h<br>~~oo~~|
|RUN<br>~~es~~|RUN Register<br>~~oo~~|15h<br>~~oo~~|
|ST<br>~~es~~|StatusRegister<br>~~oo~~|16h<br>~~oo~~|
|VOS|OutputVoltage Setpoint|07h|
|CLS|Current Limit Setpoint|08h|
|DCL<br>~~a~~|Duty Cycle Limit<br>~~-1~~<br>~~eee~~|09h<br>~~eee~~|
|B1<br>~~a~~|Dig Controller Denominator z~~-1~~<br>Coefficient<br>~~-2~~<br>~~eee~~|0Ah<br>~~eee~~|
|B2<br>~~a~~|Dig Controller Denominator z~~-2~~<br>Coefficient<br>~~-3~~<br>~~eee~~|0Bh<br>~~eee~~|
|B3|Dig Controller Denominator z~~-3~~<br>Coefficient<br>~~0~~|0Ch|
|C0L|Dig Controller Numerator z~~0~~<br>Coefficient, Low Byte<br>~~0~~|0Dh|
|C0H|Dig Controller Numerator z~~0~~<br>Coefficient,High Byte<br>~~-1~~|0Eh|
|C1L|Dig Controller Numerator z~~-1~~<br>Coefficient, Low Byte<br>~~-1~~|0Fh|
|C1H|Dig Controller Numerator z~~-1~~<br>Coefficient, High Byte<br>~~-2~~|10h|
|C2L|Dig Controller Numerator z~~-2~~<br>Coefficient,Low Byte<br>~~-2~~|11h|
|C2H|Dig Controller Numerator z~~-2~~<br>Coefficient,High Byte|12h|
|C3L|Dig Controller Numerator z~~-3~~<br>Coefficient, High Byte<br>~~-3~~|13h|
|C3H|Dig Controller Numerator z~~-3~~<br>Coefficient,Low Byte|14h|
|VOM|Output Voltage Monitoring|17h|
|IOM|Output Current Monitoring|18h|
|TMP|Temperature Monitoring|19h|
ZY7120 converters can be programmed using the Graphical User Interface or directly via the I[2] C bus by using high and low level commands as described in the ”ZM7300 Digital Power Manager Programming Manual”.
ZY7120 parameters can be reprogrammed at any time during the system operation and service except for the digital filter coefficients, the switching frequency and the duty cycle limit, that can only be changed when the POL is turned off.
## **8.1 Output Voltage**
The output voltage can be programmed in the GUI Output Configuration window shown in the Figure 27 or directly via the I[2] C bus by writing into the VOS register shown in Figure 28.
**Figure 27. POL Configure Output Window**
**==> picture [215 x 129] intentionally omitted <==**
**----- Start of picture text -----**<br>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0<br>VOS7 VOS6 VOS5 VOS4 VOS3 VOS2 VOS1 VOS0<br>Bit 7 Bit 0<br>Bit 7:0 VOS[7:0] , Output voltage setting<br>00h: corresponds to 0.5000V R = Readable bit<br>01h: corresponds to 0.5125V W = Writable bit<br>…77h: corresponds to 1.9875V U = Unimplemented bit,read as „0‟<br>78h: corresponds to 2.0000V - n = Value at POR reset<br>79h: corresponds to 2.025V<br>…<br>F9h: corresponds to 5.225V<br>FAh: corresponds to 5.250V<br>FBh: corresponds to 5.300V<br>…<br>FFh: corresponds to 5.500V<br>**----- End of picture text -----**<br>
**Figure 28. Output Voltage Setpoint Register VOS**
Page 17 of 33
ZD-00194 Rev. 2.7, 5-May -2011
**www.power-one.com**
_**ZY7120 20A DC-DC Intelligent POL Data Sheet**_ _**3V to 13.2V Input 0.5V to 5.5V Output**_
## **8.1.1 Output Voltage Setpoint**
The output voltage programming range is from 0.5V to 5.5V. Within this range, there are 256 predefined voltage setpoints. To improve resolution of the output voltage settings, the voltage range is divided into three sub-ranges as shown in Table 2.
**Table 2. Output Voltage Adjustment Resolution**
|**VOUT MIN, V**|**VOUT MAX, V**|**Resolution, mV**|
|---|---|---|
|0.500|2.000|12.5|
|2.025|5.25|25|
|5.3|5.5|50|
## **8.1.2 Output Voltage Margining**
If the output voltage needs to be varied by a certain percentage, the margining function can be utilized. The margining can be programmed in the POL Output Configuration window or directly via the I[2] C bus using high level commands as described in the "ZM7300 Digital Power Manager Programming Manual”.
In order to properly margin POLs that are connected in parallel, the POLs must be members of one of the Parallel Buses. Refer to the DPM Configure Devices window shown in Figure 55.
**==> picture [217 x 121] intentionally omitted <==**
**----- Start of picture text -----**<br>
VOUT<br>Upper Regulation<br>Limit<br>Operating VI Curve Without<br>Point Load Regulation<br>VI Curve With<br>Lower Regulation Load Regulation<br>Limit Headroom without<br>Load Regulation<br>Headroom with<br>Load Regulation<br>Light IOUT Heavy<br>Load Load<br>**----- End of picture text -----**<br>
**Figure 29. Concept of Optimal Voltage Positioning**
Increased headroom allows tolerating larger voltage deviations. For example, the step load change from light to heavy load will cause the output voltage to drop. If the optimal voltage positioning is utilized, the output voltage will stay within the regulation window. Otherwise, the output voltage will drop below the lower regulation limit. To compensate for the voltage drop external output capacitance will need to be added, thus increasing cost and complexity of the system.
The effect of optimal voltage positioning is shown in Figure 30 and Figure 31. In this case, switching output load causes large peak-to-peak deviation of the output voltage. By programming load regulation, the peak to peak deviation is dramatically reduced.
## **8.1.3 Optimal Voltage Positioning**
Optimal voltage positioning increases the voltage regulation window by properly positioning the output voltage setpoint. Positioning is determined by the load regulation that can be programmed in the POL Configure Output window shown in Figure 27 or directly via the I[2] C bus by writing into the CLS register shown in Figure 38.
Figure 29 illustrates optimal voltage positioning concept. If no load regulation is programmed, the headroom (voltage differential between the output voltage setpoint and a regulation limit) is approximately half of the voltage regulation window. When load regulation is programmed, the output voltage will decrease as the output current increases, so the VI characteristic will have a negative slope. Therefore, by properly selecting the operating point, it is possible to increase the headroom as shown in the picture.
**Figure 30. Transient Response without Optimal Voltage Positioning**
Page 18 of 33
~~ee~~ ZD-00194 Rev. 2.7, 5-May -2011 **www.power-one.com** Page 18 of 33
_**ZY7120 20A DC-DC Intelligent POL Data Sheet**_ _**3V to 13.2V Input 0.5V to 5.5V Output**_
**==> picture [219 x 70] intentionally omitted <==**
**----- Start of picture text -----**<br>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0<br>DON7 DON6 DON5 DON4 DON3 DON2 DON1 DON0<br>Bit 7 Bit 0<br>Bit 7:0 DON[7:0] : Turn-on delay time<br>00h: corresponds to 0ms delay after turn-on command has occurred<br>…<br>FFh: corresponds to 255ms delay after turn-on command has occurred<br>**----- End of picture text -----**<br>
**Figure 33. Turn-On Delay Register DON**
## **8.2.2 Turn-Off Delay**
**Figure 31. Transient Response with Optimal Voltage Positioning**
## **8.2 Sequencing and Tracking**
Turn-on delay, turn-off delay, and rising and falling output voltage slew rates can be programmed in the POL Configure Sequencing window shown in Figure 32 or directly via the I[2] C bus by writing into the DON, DOF, and TC registers, respectively. The registers are shown in Figure 33, Figure 34, and Figure 36.
**==> picture [219 x 80] intentionally omitted <==**
**----- Start of picture text -----**<br>
U U R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0<br>--- --- DOF5 DOF4 DOF3 DOF2 DOF1 DOF0<br>Bit 7 Bit 0<br>Bit 7:6 Unimplemented , read as „0‟<br>Bit 5:0 DOF[5:0] : Turn-off delay time<br>00h: corresponds to 0ms delay after turn-off command has occurred<br>…<br>3Fh: corresponds to 63ms delay after turn-off command has occurred<br>**----- End of picture text -----**<br>
**Figure 34. Turn-Off Delay Register DOF**
Turn-off delay is defined as an interval from the application of the Turn-Off command until the output voltage reaches zero (if the falling slew rate is programmed) or until both high side and low side switches are turned off (if the slew rate is not programmed). Therefore, for the slew rate controlled turn-off the ramp-down time is included in the turn-off delay as shown in Figure 35.
**==> picture [208 x 105] intentionally omitted <==**
**----- Start of picture text -----**<br>
User programmed turn-off delay, TDF<br>Turn-Off<br>i<br>Command<br>Calculated<br>Internal delay TD Ramp Ramp-down time, T down time T F<br>ramp-down<br>command<br>| | i<br>V OUT : Falling slew j<br>rate dVF/dT ;<br>}<br>: Time<br>**----- End of picture text -----**<br>
**Figure 35. Relationship between Turn-Off Delay and Falling Slew Rate**
**Figure 32. POL Configure Sequencing Window**
## **8.2.1 Turn-On Delay**
Turn-on delay is defined as an interval from the application of the Turn-On command until the output voltage starts ramping up.
As it can be seen from the figure, the internally calculated delay TD is determined by the equation below.
**==> picture [91 x 32] intentionally omitted <==**
For proper operation TD shall be greater than zero. The appropriate value of the turn-off delay needs to be programmed to satisfy the condition.
Page 19 of 33
ZD-00194 Rev. 2.7, 5-May -2011 ereer reer
**www.power-one.com**
_**ZY7120 20A DC-DC Intelligent POL Data Sheet**_ _**3V to 13.2V Input 0.5V to 5.5V Output**_
If the falling slew rate control is not utilized, the turnoff delay only determines an interval from the application of the Turn-Off command until both high side and low side switches are turned off. In this case, the output voltage ramp-down process is determined by load parameters.
## **8.2.3 Rising and Falling Slew Rates**
The output voltage tracking is accomplished by programming the rising and falling slew rates of the output voltage. To achieve programmed slew rates, the output voltage is being changed in 12.5mV steps where duration of each step determines the slew rate. For example, ramping up a 1.0V output with a slew rate of 0.5V/ms will require 80 steps duration of 25μs each.
Duration of each voltage step is calculated by dividing the master clock frequency generated by the DPM. Since all POLs in the system are synchronized to the master clock, the matching of voltage slew rates of different outputs is very accurate as it can be seen in Figure 11 and Figure 16.
During the turn on process, a POL not only delivers current required by the load (ILOAD), but also charges the load capacitance. The charging current can be determined from the equation below:
**==> picture [92 x 20] intentionally omitted <==**
Where, CLOAD is load capacitance, dVR/dt is rising voltage slew rate, and ICHG is charging current.
When selecting the rising slew rate, a user needs to ensure that
**==> picture [76 x 11] intentionally omitted <==**
Where IOCP is the overcurrent protection threshold of the ZY7120. If the condition is not met, then the overcurrent protection will be triggered during the turn-on process. To avoid this, dVR/dt and the overcurrent protection threshold should be programmed to meet the condition above.
**==> picture [219 x 208] intentionally omitted <==**
**----- Start of picture text -----**<br>
U R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0<br>--- R2 R1 R0 SC F2 F1 F0<br>Bit 7 Bit 0<br>Bit 7 Unimplemented , read as „0‟ R = Readable bit<br>Bit 6:4 R[2:0] : Value of Vo rising slope W = Writable bit<br>0: corresponds to 0.1V/ms (default) U = Unimplemented bit,<br>1: corresponds to 0.2V/ms read as „0‟<br>2: corresponds to 0.5V/ms - n = Value at POR reset<br>3: corresponds to 1.0V/ms<br>4: corresponds to 2.0V/ms<br>5: corresponds to 5.0V/ms<br>6: corresponds to 8.3V/ms<br>7: corresponds to 8.3V/ms<br>Bit 3 SC , Slew rate control at turn-off<br>0: Slew rate control is disabled<br>1: Slew rate control is enabled<br>Bit 2:0 F[2:0] : Value of Vo falling slope<br>0: corresponds to -0.1V/ms (default)<br>1: corresponds to -0.2V/ms<br>2: corresponds to -0.5V/ms<br>3: corresponds to -1.0V/ms<br>4: corresponds to -2.0V/ms<br>5: corresponds to -5.0V/ms<br>6: corresponds to –8.3V/ms<br>7: corresponds to –8.3V/ms<br>**----- End of picture text -----**<br>
**Figure 36. Tracking Configuration Register TC**
## **8.3 Protection**
ZY7120 Series converters have a comprehensive set of programmable protection functions. The set includes the output overand undervoltage protection, overcurrent protection, overtemperature protection, tracking protection, overtemperature warning, and Power Good signal. Status of protection functions is stored in the ST register shown in Figure 37.
**==> picture [217 x 136] intentionally omitted <==**
**----- Start of picture text -----**<br>
R-1 R-0 R-1 R-1 R-1 R-1 R-1 R-1<br>TP PG TR OT OC UV OV PV<br>Bit 7 Bit 0<br>Bit 7 TP : Temperature Warning R = Readable bit<br>Bit 6 PG : Power Good Warning W = Writable bit<br>Bit 5 TR : Tracking Fault U = Unimplemented bit,read as „0‟<br>Bit 4 OT : Overtemperature Fault - n = Value at POR reset<br>Bit 3 OC : Overcurrent Fault<br>Bit 2 UV : Undervoltage Fault<br>Bit 1 OV : Overvoltage Error<br>Bit 0 PV : Phase Voltage Error<br>Note:<br>- An activated warning/fault/error is encoded as „0‟<br>**----- End of picture text -----**<br>
**Figure 37. Protection Status Register ST**
Thresholds of overcurrent, over- and undervoltage protections, and Power Good limits can be programmed in the POL Configure Output window or directly via the I[2] C bus by writing into the CLS and PC2 registers shown in Figure 38 and Figure 39.
Page 20 of 33
ZD-00194 Rev. 2.7, 5-May -2011
**www.power-one.com**
_**ZY7120 20A DC-DC Intelligent POL Data Sheet**_ _**3V to 13.2V Input 0.5V to 5.5V Output**_
**==> picture [223 x 176] intentionally omitted <==**
**----- Start of picture text -----**<br>
R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-1 R/W-1<br>LR2 LR1 LR0 TCE CLS3 CLS2 CLS1 CLS0<br>| [ [| [ |<br>Bit 7 Bit 0<br>Bit 7:5 LR[2:0] , Load regulation configuration R = Readable bit<br>000: 0 V/A/Ohm W = Writable bit<br>001: 0.39 V/A/Ohm U = Unimplemented bit,<br>010: 0.78 V/A/Ohm read as „0‟<br>011: 1.18 V/A/Ohm - n = Value at POR reset<br>100: 1.57 V/A/Ohm<br>101: 1.96 V/A/Ohm<br>110: 2.35 V/A/Ohm<br>111: 2.75 V/A/Ohm<br>Bit 4 TCE , Temperature compensation enable<br>0: disabled<br>1: enabled<br>Bit 3:0 CLS[3:0] , Current limit setting<br>0h: corresponds to 37%<br>1h: corresponds to 47%<br>…<br>Bh: corresponds to 140%<br>Values higher than Bh are translated to Bh (140%)<br>**----- End of picture text -----**<br>
**Figure 38. Current Limit Setpoint Register CLS**
**==> picture [220 x 146] intentionally omitted <==**
**----- Start of picture text -----**<br>
U U U R/W-0 R/W-1 R/W-0 R/W-0 R/W-0<br>--- --- --- PGLL OVPL1 OVPL0 UVPL1 UVPL0<br>Bit 7 Bit 0<br>Bit 7:5 Unimplemented , read as „0‟ R = Readable bit<br>Bit 4 PGLL : Set Power Good Low Level W = Writable bit<br>1 = 95% of Vo U = Unimplemented bit,<br>0 = 90% of Vo (Default) read as „0‟<br>Bit 3:2 OVPL[1:0] : Set Over Voltage Protection - n = Value at POR reset<br>Level<br>00 = 110% of Vo<br>01 = 120% of Vo<br>10 = 130% of Vo (Default)<br>11 = 130% of Vo<br>Bit 1:0 UVPL[1:0] : Set Under Voltage Protection Level<br>00 = 75% of Vo (Default)<br>01 = 80% of Vo<br>10 = 85% of Vo<br>**----- End of picture text -----**<br>
**Figure 39. Protection Configuration Register PC2**
Note that the overvoltage and undervoltage protection thresholds and Power Good limits are defined as percentages of the output voltage. Therefore, the absolute levels of the thresholds change when the output voltage setpoint is changed either by output voltage adjustment or by margining.
In addition, a user can change type of protections (latching or non-latching) or disable certain protections. These settings are programmed in the POL Configure Fault window shown in Figure 40 or directly via the I[2] C by writing into the PC1 register shown in Figure 41.
**Figure 40. POL Configure Fault window**
**==> picture [219 x 234] intentionally omitted <==**
**----- Start of picture text -----**<br>
R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1<br>TRE PVE TRP OTP OCP UVP OVP PVP<br>Bit 7 Bit 0<br>Bit 7 TRE : Tracking fault enable R = Readable bit<br>1 = enabled W = Writable bit<br>0 = disabled U = Unimplemented bit,<br>Bit 6 PVE : Phase voltage error enable read as „0‟<br>1 = enabled - n = Value at POR reset<br>0 = disabled<br>Bit 5 TRP : Tracking fault protection<br>1 = latching<br>0 = non latching<br>Bit 4 OTP : Overtemperature protection configuration<br>1 = latching<br>0 = non latching<br>Bit 3 OCP : Overcurrent protection configuration<br>1 = latching<br>0 = non latching<br>Bit 2 UVP : Undervoltage protection configuration<br>1 = latching<br>0 = non latching<br>Bit 1 OVP : Overvoltage protection configuration<br>1 = latching<br>0 = non latching<br>Bit 0 PVP : Phase Voltage Protection<br>1 = latching<br>0 = non latching<br>**----- End of picture text -----**<br>
**Figure 41. Protection Configuration Register PC1**
If the non-latching protection is selected, a POL will attempt to restart every 130ms until the condition that triggered the protection is removed. When restarting, the output voltages follow tracking and sequencing settings.
If the latching type is selected, a POL will turn off and stay off. The POL can be turned on after 130ms, if the condition that caused the fault is removed and the respective bit in the ST register was cleared, or
Page 21 of 33
ZD-00194 Rev. 2.7, 5-May -2011
ZD-00194 Rev. 2.7, 5-May -2011 e reer
**www.power-one.com**
_**ZY7120 20A DC-DC Intelligent POL Data Sheet**_ _**3V to 13.2V Input 0.5V to 5.5V Output**_ o£ { oo
the Turn On command was recycled, or the input voltage was recycled.
All protections can be classified into three groups based on their effect on system operation: warnings, faults, and errors.
the status information from each POL on a continuous basis.
## **8.3.2 Faults**
This group includes overcurrent, overtemperature, undervoltage, and tracking protections. Triggering any protection in this group will turn off the POL.
## **8.3.1 Warnings**
This group includes Overtemperature Warning and Power Good Signal. The warnings do not turn off POLs but rather generate signals that can be transmitted to a host controller via the I[2] C bus.
## **8.3.1.1 Overtemperature Warning**
The Overtemperature Warning is generated when temperature of the controller exceeds 120°C. The Overtemperature Warning changes the PT bit of the status register ST to 0 and sends the signal to the DPM. Reporting is enabled in the POL Configuration Faults window or directly via the I[2] C by writing into the PC3 register shown in Figure 43. When the temperature falls below 117°C, the PT bit is cleared and the Overtemperature Warning is removed.
## **8.3.1.2 Power Good**
Power Good is an open collector output that is pulled low, if the output voltage is outside of the Power Good window. The window is formed by the Power Good High threshold that is equal to 110% of the output voltage and the Power Good Low threshold that can be programmed at 90 or 95% of the output voltage.
The Power Good protection is only enabled after the output voltage reaches its steady state level. The PG pin is pulled low during transitions of the output voltage from one level to other as shown in Figure 42.
The Power Good Warning pulls the Power Good pin low and changes the PG bit of the status register ST to 0. It sends the signal to the DPM, if the reporting is enabled. When the output voltage returns within the Power Good window, the PG pin is pulled high, the PG bit is cleared and the Power Good Warning is removed. The Power Good pin can also be pulled low by an external circuit to initiate the Power Good Warning.
**Note** : To retrieve status information, Status Monitoring in the DPM Configure Devices window should be enabled (refer to Digital Power Manager Data Sheet). The DPM will retrieve
## **8.3.2.1 Overcurrent Protection**
Overcurrent protection is active whenever the output voltage of the POL exceeds the pre-bias voltage (if any). When the output current reaches the OC threshold, the output voltage will start decreasing. As soon as the output voltage decreases below the undervoltage protection threshold, the OC fault signal is generated, the POL turns off and the OC bit in the register ST is changed to 0. Both high side and low side switches of the POL are turned off instantly (fast turn-off).
The temperature compensation is added to keep the OC threshold approximately constant at temperatures above room temperature. Note that the temperature compensation can be disabled in the POL Configure Output window or directly via the I[2] C by writing into the CLS register. However, it is recommended to keep the temperature compensation enabled.
## **8.3.2.2 Undervoltage Protection**
The undervoltage protection is only active during steady state operation of the POL to prevent nuisance tripping. If the output voltage decreases below the UV threshold and there is no OC fault, the UV fault signal is generated, the POL turns off, and the UV bit in the register ST is changed to 0. The output voltage is ramped down according to sequencing and tracking settings (regular turn-off).
## **8.3.2.3 Overtemperature Protection**
Overtemperature protection is active whenever the POL is powered up. If temperature of the controller exceeds 130°C, the OT fault is generated, POL turns off, and the OT bit in the register ST is changed to 0. The output voltage is ramped down according to sequencing and tracking settings (regular turn-off).
If non-latching OTP is programmed, the POL will restart as soon as the temperature of the controller decreases below the Overtemperature Warning threshold of 120°C.
Page 22 of 33
( ZD-00194 Rev. 2.7, 5-May -2011 ~~2)~~ **www.power-one.com** Page 22 of 33
_**ZY7120 20A DC-DC Intelligent POL Data Sheet**_ _**3V to 13.2V Input 0.5V to 5.5V Output**_ o£ { oo
## **8.3.2.4 Tracking Protection**
Tracking protection is active only when the output voltage is ramping up. The purpose of the protection is to ensure that the voltage differential between multiple rails being tracked does not exceed 250mV. This protection eliminates the need for external clamping diodes between different voltage rails which are frequently recommended by ASIC manufacturers.
When the tracking protection is enabled, the POL continuously compares actual value of the output voltage to its programmed value as defined by the output voltage and its rising slew rate. If absolute
value of the difference exceeds 250mV, the tracking fault signal is generated, the POL turns off, and the TR bit in the register ST is changed to 0. Both high side and low side switches of the POL are turned off instantly (fast turn-off).
The tracking protection can be disabled, if it contradicts requirements of a particular system (for example turning into high capacitive load where rising slew rate is not important). It can be disabled in the POL Configure Fault window or directly via the I[2] C bus by writing into the PC1 register.
**==> picture [476 x 190] intentionally omitted <==**
**----- Start of picture text -----**<br>
Vo<br>1<br>Enable command 0<br>OTP continuously enabled<br>1<br>OCP enabled 0<br>Power Good 1<br>Signal 0<br>OVP Threshold OVP Threshold<br>PG High=110%VOUT PG High=110%VOUT<br>OVP Threshold<br>Output Voltage Output Voltage<br>PG High=110%VOUT<br>PG Low Threshold Output Voltage PG Low Threshold<br>1.0V UVP Threshold PG Low Threshold UVP Threshold<br>prebiased output UVP Threshold<br>Tracking<br>Thresholds<br>Time<br>**----- End of picture text -----**<br>
**Figure 42. Protections Enable Conditions**
## **8.3.3 Errors**
The group includes overvoltage protection and the phase voltage error. The phase voltage error is not available in ZY7120.
## **8.3.3.1 Overvoltage Protection**
The overvoltage protection is active whenever the output voltage of the POL exceeds the pre-bias voltage (if any). If the output voltage exceeds the overvoltage protection threshold, the overvoltage error signal is generated, the POL turns off, and the OV bit in the register ST is changed to 0. The high side switch is turned off instantly, and simultaneously the low side switch is turned on to ensure reliable protection of sensitive loads. The low side switch provides low impedance path to quickly dissipate
energy stored in the output filter and achieve effective voltage limitation.
The OV threshold can be programmed from 110% to 130% of the output voltage setpoint, but not lower than 1.0V.
## **8.3.4 Faults and Errors Propagation**
The feature adds flexibility to the fault management scheme by giving users control over propagation of fault signals within and outside of the system. The propagation means that a fault in one POL can be programmed to turn off other POLs and devices in the system, even if they are not directly affected by the fault.
Page 23 of 33
ZD-00194 Rev. 2.7, 5-May -2011
**www.power-one.com**
_**ZY7120 20A DC-DC Intelligent POL Data Sheet**_ _**3V to 13.2V Input 0.5V to 5.5V Output**_
## **8.3.4.1 Grouping of POLs**
Z-Series POLs can be arranged in several groups to simplify fault management. A group of POLs is defined as a number of POLs with interconnected OK pins. A group can include from 1 to 32 POLs. If fault propagation within a group is desired, the propagation bit needs to be checked in the DPM Configure Faults window. The parameters can also be programmed directly via the I[2] C bus by writing into the PC3 register shown in Figure 43.
When propagation is enabled, the faulty POL pulls its OK pin low. A low OK line initiates turn-off of other POLs in the group.
**Figure 44. DPM Configure Faults Window**
|R/W-0|R/W-0|R/W-0|R/W-1|R/W-1|R/W-1||R/W-1|R/W-1|R/W-1|
|---|---|---|---|---|---|---|---|---|---|
|PTM||PGM|TRP|OTP|OCP||UVP|OVP|PVP|
|Bit 7|||||||||Bit 0|
|Bit 7|**PTM** : Temperature warning Message||||||R = Readable bit|||
||1 = enabled||||||W = Writable bit|||
||0 = disabled||||||U = Unimplemented bit,|||
|Bit 6|**PGM**: Power good message||||||read as „0‟|||
||1 = enabled||||||- n = Value at POR reset|||
||0 = disabled|||||||||
|Bit 5|**TRP** : Tracking fault propagation|||||||||
||1 = enabled|||||||||
||0 = disabled|||||||||
|Bit 4|**OTP**: Overtemperature fault propagation|||: Overtemperature fault propagation||||||
||1 = enabled|||||||||
||0 = disabled|||||||||
|Bit 3|**OCP** : Overcurrent fault propagation|||: Overcurrent fault propagation||||||
||1 = enabled|||||||||
||0 = disabled|||||||||
|Bit 2|**UVP**: Undervoltage fault propagation|||||||||
||1 = enabled|||||||||
||0 = disabled|||||||||
|Bit 1|**OVP** : Overvoltage error propagation|||||||||
||1 = enabled|||||||||
||0 = disabled|||||||||
|Bit 0|**PVP** : Phase voltage error propagation||: Phase voltage error propagation|||||||
||1 = enabled|||||||||
||0 = disabled|||||||||
**Figure 43. Protection Configuration Register PC3**
In addition, the OK lines can be connected to the DPM to facilitate propagation of faults and errors between groups. One DPM can control up to 4 independent groups. To enable fault propagation between groups, the respective bit needs to be checked in the DPM Configure Faults window, Group Fault Propagation sub window shown in Figure 44.
In this case low OK line will signal DPM to pull other OK lines low to initiate shutdown of other POLs as programmed in the Group Fault Propagation window. If an error is propagated, the DPM can also generate commands to turn off a front end (a DC-DC converter generating the intermediate bus voltage) and trigger an optional crowbar protection to accelerate removal of the IBV voltage.
## **8.3.4.2 Propagation Process**
Propagation of a fault (OCP, UVP, OTP, and TRP) initiates regular turn-off of other POLs. The faulty POL in this case performs either the regular or the fast turn-off depending on a specific fault as described in section 8.3.2.
Propagation of an error initiates fast turn-off of other POLs. The faulty POL performs the fast turn-off and turns on its low side switch.
Example of the fault propagation is shown in Figure 45 - Figure 46. In this three-output system (refer to the block diagram in Figure 25), the POL powering the output V3 (Ch 1 in the picture) encounters the undervoltage fault after the turn-on. When the fault propagation is not enabled, the POL turns off and generates the UV fault signal. Because the UV fault triggers the regular turn off, the POL meets its turnoff delay and falling slew rate settings during the turn-ff process as shown in Figure 45. Since the UV fault is programmed to be non-latching, the POL will attempt to restart every 130ms, repeating the process described above until the condition causing the undervoltage is removed.
Page 24 of 33
ZD-00194 Rev. 2.7, 5-May -2011
**www.power-one.com**
_**ZY7120 20A DC-DC Intelligent POL Data Sheet**_ _**3V to 13.2V Input 0.5V to 5.5V Output**_
If the fault propagation between groups is enabled, the POL powering the output V3 pulls its OK line low and the DPM propagates the signal to the POL powering the output V1 that belongs to other group. The POL powering the output V1 (Ch3 in the picture) executes the regular turn-off. Since both V1 and V3 have the same delay and slew rate settings they will continue to turn off and on synchronously every 130ms as shown in Figure 46 until the condition causing the undervoltage is removed. The POL powering the output V2 continues to ramp up until it reaches its steady state level.
130ms is the interval from the instant of time when the output voltage ramps down to zero until the output voltage starts to ramp up again. Therefore, the 130ms hiccup interval is guaranteed regardless of the turn-off delay setting.
**Figure 46. Turn-On into UVP on V3. The UV Fault Is Programmed To Be Non-Latching and Propagate From Group C to Group A. Ch1 – V3 (Group C), Ch2 – V2, Ch3 – V1 (Group A)**
Summary of protections, their parameters and features are shown in Table 3
**Figure 45. Turn-On into UVP on V3. The UV Fault Is Programmed To Be Non-Latching. Ch1 – V3 (Group C), Ch2 – V2, Ch3 – V1 (Group A)**
**Table 3. Summary of Protections Parameters and Features**
|**Code**|**Name**|**Type**|**When Active**|**Turn**<br>**Off**|**Low Side**<br>**Switch**|**Propagation**|**Disable**|
|---|---|---|---|---|---|---|---|
|PT|Temperature<br>Warning|Warning|Whenever VINis applied|No|N/A|Readable by<br>DPM|No|
|PG|Power Good|Warning|During steady state|No|N/A|Readable by<br>DPM|No|
|TR|Tracking|Fault|During ramp up|Fast|Off|Regular turn off|Yes|
|OT|Overtemperature|Fault|Whenever VINis applied|Regular|Off|Regular turn off|No|
|OC|Overcurrent|Fault|When VOUTexceeds prebias|Fast|Off|Regular turn off|No|
|UV|Undervoltage|Fault|During steady state|Regular|Off|Regular turn off|No|
|OV|Overvoltage|Error|When VOUTexceeds prebias|Fast|On|Fast turn off|No|
Page 25 of 33
~~ee~~ ZD-00194 Rev. 2.7, 5-May -2011 **www.power-one.com** Page 25 of 33
_**ZY7120 20A DC-DC Intelligent POL Data Sheet**_ _**3V to 13.2V Input 0.5V to 5.5V Output**_
## **8.4 PWM Parameters**
Z-Series POLs utilize the digital PWM controller. The controller enables users to program most of the PWM performance parameters, such as switching frequency, interleave, duty cycle, and feedback loop compensation.
## **8.4.1 Switching Frequency**
The switching frequency can be programmed in the PWM sub window in the POL Configuration Controller Compensation window shown in Figure 47 or directly via the I[2] C bus by writing into the INT register shown in Figure 48. Note that the content of the register can be changed only when the POL is turned off.
Switching for all POLs connected to the SD line are synchronized to the master clock generated by the DPM. Each POL is equipped with a PLL and a frequency divider so they can operate at multiples (including fractional) of the master clock frequency as programmed by a user. The converters can operate at 500 kHz, 750 kHz, and 1 MHz. Although synchronized, switching frequencies of different POLs are independent of each other. It is permissible to mix POLs operating at different frequencies in one system. This allows optimizing efficiency and transient response of each POL in the system individually. (Note: POLs assigned to the same power output bus are forced to use the same switching frequency)
**==> picture [221 x 176] intentionally omitted <==**
**----- Start of picture text -----**<br>
R/W-0 R/W-0 R/W-0 R/W-0 [1)] R/W-0 [1)] R/W-0 [1)] R/W-0 [1)] R/W-0 [1)]<br>FRQ2 FRQ1 FRQ0 INT4 INT3 INT2 INT1 INT0<br>Bit 7 Bit 0<br>Bit 7:5 FRQ[2:0] : PWM Frequency Selection R = Readable bit<br>000: 500kHz W = Writable bit<br>001: 750kHz U = Unimplemented bit,<br>010: 1000lHz read as „0‟<br>011: 1250kHz - n = Value at POR reset<br>100: 1250kHz<br>101: 1500kHz<br>110: 1750kHz<br>111: 2000kHz<br>Bit 4:0 INT[4:0] : Interleave position<br>00h: Ton starts with 0.0° Phase lag to SD Line<br>01h: Ton starts wi th 11.25° Phase lag to SD Line<br>02h: Ton starts with 22.50° Phase lag to SD Line<br>…<br>1Fh: Ton starts with 348.75° Phase lag to SD Line<br>1) Initial value depends on the state of the Interleave Mode ( IM ) Input:<br>IM=Open: At POR reset the 5 corresponding ADDRESS bits are loaded<br>IM=Low: At POR reset a 0 is loaded<br>**----- End of picture text -----**<br>
**Figure 48. Interleave Configuration Register INT**
## **8.4.2 Interleave**
Interleave is defined as a phase delay between the synchronizing slope of the master clock on the SD pin and PWM signal of a POL. The interleave can be programmed in the PWM section of the POL Controller Compensation window or directly via the I[2] C bus by writing into the INT register.
Every POL generates switching noise. If no interleave is programmed, all POLs in the system switch simultaneously and noise reflected to the input source from all POLs is added together as shown in Figure 49.
**Figure 47. POL Configure Controller Compensation Window**
**Figure 49. Input Voltage Noise, No Interleave**
Page 26 of 33
ZD-00194 Rev. 2.7, 5-May -2011 ereer reer
**www.power-one.com**
_**ZY7120 20A DC-DC Intelligent POL Data Sheet**_ _**3V to 13.2V Input 0.5V to 5.5V Output**_
Figure 50 shows the input voltage noise of the threeoutput system with programmed interleave. Instead of all three POLs switching at the same time as in the previous example, the POLs V1, V2, and V3 switch at 67.5°, 180°, and 303.75°, respectively. Noise is spread evenly across the switching cycle resulting in more than 1.5 times reduction. To achieve similar noise reduction without the interleave will require the addition of an external LC filter.
**==> picture [27 x 14] intentionally omitted <==**
**----- Start of picture text -----**<br>
Tek stop<br>**----- End of picture text -----**<br>
**Figure 52. Output Voltage Noise, Full Load, 180** **Interleave**
**Figure 50. Input Voltage Noise with Interleave**
Similar noise reduction can be achieved on the output of POLs connected in parallel. Figure 51 and Figure 52 show the output noise of two ZY7120s connected in parallel without and with 180° interleave, respectively. Resulting noise reduction is more than 2 times and is equivalent to doubling switching frequency or adding extra capacitance on the output of the POLs.
The ZY7120 interleave feature is similar to that of multiphase converters, however, unlike in the case of multiphase converters, interleave does not have to be equal to 360/N, where N is the number of POLs in a system. ZY7120 interleave is independent of the number of POLs in a system and is fully programmable in 11.25 steps. It allows maximum output noise reduction by intelligently spreading switching energy.
**Note** : Due to noise sensitivity issues that may occur in limited cases, it is recommended to avoid phase lag settings of 112.5 and 123.75 degrees, otherwise false PG and/or OV indications may occur.
## **8.4.3 Duty Cycle Limit**
The ZY7120 is a step-down converter therefore VOUT is always less than VIN. The relationship between the two parameters is characterized by the duty cycle and can be estimated from the following equation:
**==> picture [66 x 25] intentionally omitted <==**
Where, DC is the duty cycle, VOUT is the required maximum output voltage (including margining), VIN.MIN is the minimum input voltage.
**Figure 51. Output Voltage Noise, Full Load, No Interleave**
It is good practice to limit the maximum duty cycle of the controller's PWM to a somewhat higher value compared to the steady-state duty cycle as expressed by the above equation. This will further protect the output from excessive voltages. The duty cycle limit can be programmed in the POL Configure Controller Compensation window or directly via the I[2] C bus by writing into the DCL register shown in Figure 53.
Page 27 of 33
ZD-00194 Rev. 2.7, 5-May -2011
**www.power-one.com**
_**ZY7120 20A DC-DC Intelligent POL Data Sheet**_ _**3V to 13.2V Input 0.5V to 5.5V Output**_ o£ { oo
## **8.4.5 Feedback Loop Compensation**
**==> picture [223 x 123] intentionally omitted <==**
**----- Start of picture text -----**<br>
R/W-1 R/W-1 R/W-1 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0<br>DCL5 DCL4 DCL3 DCL2 DCL1 DCL0 HI LO<br>[| [ | T~T J J T J[ |<br>Bit 7 Bit 0<br>Bit 7:2 DCL[5:0] , Duty Cycle Limitation R = Readable bit<br>00h: 0 W = Writable bit<br>01h: 1/64 U = Unimplemented bit,<br>… 3Fh: 63/64 - n = Value at POR reset read as „0‟<br>Bit 1: HI , ADC high saturation feed-forward<br>0: disabled<br>1: enabled<br>Bit 0: LO , ADC low saturation feed-forward<br>0: disabled<br>1: enabled<br>**----- End of picture text -----**<br>
**Figure 53. Duty Cycle Limit Register**
## **8.4.4 ADC Saturation Feedforward**
To speed up the PWM response in case of heavy dynamic loads, the duty cycle can be forced either to 0 or the duty cycle limit depending on the polarity of the transient. This function is equivalent to having two comparators defining a window around the output voltage setpoint. When an error signal is inside the window, it will produce gradual duty cycle change proportional to the error signal. If the error signal goes outside the window (usually due to large output current steps), the duty cycle will change to its limit in one switching cycle. In most cases this will significantly improve transient response of the controller, reducing amount of required external capacitance.
Under certain circumstances, usually when the maximum duty cycle limit significantly exceeds its nominal value, the ADC saturation can lead to the overcompensation of the output error. The phenomenon manifests itself as low frequency oscillations on the output of the POL. It can usually be reduced or eliminated by disabling the ADC saturation or limiting the maximum duty cycle to 120140% of the calculated value. It is not recommended to use ADC saturation for output voltages higher than 2.0V.
The ADC saturation feedforward can be programmed in the PWM section of the POL Configure Controller Compensation window or directly via the I[2] C bus by writing into the DCL register.
Feedback loop compensation can be programmed in the POL Controller Compensation window by setting frequency of poles and zeros of the transfer function.
The transfer function of the POL converter is shown in Figure 54. It is a third order function with two zeros and three poles. Pole 1 is the integrator pole, Pole 2 is used in conjunction with Zero 1 and Zero 2 to adjust the phase lead and limit the gain increase in mid band. Pole 3 is used as a high frequency lowpass filter to limit PWM noise.
**==> picture [229 x 194] intentionally omitted <==**
**----- Start of picture text -----**<br>
Magnitude[dB]<br>50 Z1 P1 Z2 P2 P3<br>P1: Pole 1<br>40 P2: Pole 3<br>P3: Pole 3<br>Z1: Zero 1<br>30 Z2: Zero 2<br>20<br>10<br>Freq<br>N 0.1 \ 1 “> 10 100 1000 [kHz]<br>Phase<br>[°]<br>+45<br>0 Freq<br>0.1 1 10 100 1000 [kHz]<br>-45<br>-90<br>-135<br>-180<br>**----- End of picture text -----**<br>
**Figure 54. Transfer Function of PWM**
Positions of poles and zeroes are determined by coefficients of the digital filter. The filter is characterized by four numerator coefficients ( _C_ 0, _C_ 1, _C_ 2, _C_ 3) and three denominator coefficients ( _B_ 1, _B_ 2, _B_ 3). The coefficients are automatically calculated when desired frequency of poles and zeros is entered in the POL Configure Controller Compensation window. The coefficients are stored in the C0H, C0L, C1H, C1L, C2H, C2L, C3H, C3L, B1, B2, and B3 registers.
- **Note** : The GUI automatically transforms zero and pole frequencies into the digital filter coefficients. It is strongly recommended to use the GUI to determine the filter coefficients.
Programming feedback loop compensation allows optimizing POL performance for various application conditions. For example, increase in bandwidth can significantly improve dynamic response.
Page 28 of 33
ZD-00194 Rev. 2.7, 5-May -2011
**www.power-one.com**
_**ZY7120 20A DC-DC Intelligent POL Data Sheet**_ _**3V to 13.2V Input 0.5V to 5.5V Output**_ o£ { oo
## **8.6 Performance Parameters Monitoring**
## **8.5 Current Share**
The POL converters are equipped with the digital current share function. To activate the current share, interconnect the CS pins of the POLs connected in parallel. The digital signal transmitted over the CS line sets output currents of all POLs to the same level.
When POLs are connected in parallel, they must be included in the same parallel bus in the DPM Device Configuration window shown in Figure 55. In this case, the GUI automatically copies parameters of one POL onto all POLs connected to the parallel bus. It makes it impossible to configure different performance parameters for POLs connected in parallel except for interleave and load regulation settings that are independent. The interleave allows to reduce and move the output noise of the converters connected in parallel to higher frequencies as shown in Figure 51 and Figure 52. The load regulation allows controlling the current share loop gain in case of small signal oscillations. It is recommended to always add a small amount of load regulation to one of the converters connected in parallel to reduce loop gain and therefore improve stability.
The POL converters can monitor their own performance parameters such as output voltage, output current, and temperature.
The output voltage is measured at the output sense pins, output current is measured using the ESR of the output inductor and temperature is measured by the thermal sensor built into the controller IC. Output current readings are adjusted based on temperature readings to compensate for the change of ESR of the inductor with temperature.
An 8-Bit Analog to Digital Converter (ADC) converts the output voltage, output current, and temperature into a digital signal to be transmitted via the serial interface. The ADC allows a minimum sampling frequency of 1 kHz for all three values.
Monitored parameters are stored in registers (VOM, IOM, and TMON) that are continuously updated. If the Retrieve Monitoring bits for Parametric ( **PMonitor)** and Status ( **S-Monitor** ) in the DPM Configure Devices window shown in Figure 55 are checked, those registers are being copied into the ring buffer located in the DPM. Contents of the ring buffer can be displayed in the DPM Monitor Window shown in Figure 56 or it can be read directly via the I[2] C bus using high and low level commands as described in the ”ZM7300 Digital Power Manager Programming Manual”.
Page 29 of 33
( ZD-00194 Rev. 2.7, 5-May -2011 ~~2)~~ **www.power-one.com** Page 29 of 33
## _**ZY7120 20A DC-DC Intelligent POL Data Sheet**_ _**3V to 13.2V Input 0.5V to 5.5V Output**_
## **Figure 55. DPM Configure Devices Window**
Page 30 of 33
ZD-00194 Rev. 2.7, 5-May -2011
**www.power-one.com**
_**ZY7120 20A DC-DC Intelligent POL Data Sheet**_ _**3V to 13.2V Input 0.5V to 5.5V Output**_
**Figure 56. DPM Monitoring Window**
## **9. Safety**
The ZY7120 POL converters **do not provide isolation** from input to output. The input devices powering ZY7120 must provide relevant isolation requirements according to all IEC60950 based standards. Nevertheless, if the system using the converter needs to receive safety agency approval, certain rules must be followed in the design of the system. In particular, all of the creepage and clearance requirements of the end-use safety requirements must be observed. These requirements are included in UL60950 - CSA60950-00 and EN60950, although specific applications may have other or additional requirements.
The ZY7120 POL converters have no internal fuse. If required, the external fuse needs to be provided to protect the converter from catastrophic failure. Refer to the “Input Fuse Selection for DC/DC converters” application note on www.power-one.com for proper
selection of the input fuse. Both input traces and the chassis ground trace (if applicable) must be capable of conducting a current of 1.5 times the value of the fuse without opening. The fuse must not be placed in the grounded input line.
Abnormal and component failure tests were conducted with the POL input protected by a fastacting 65 V, 15 A, fuse. If a fuse rated greater than
## 15 A is used, additional testing may be required.
In order for the output of the ZY7120 POL converter to be considered as SELV (Safety Extra Low Voltage), according to all IEC60950 based standards, the input to the POL needs to be supplied by an isolated secondary source providing a SELV also.
Page 31 of 33
~~ee~~ ZD-00194 Rev. 2.7, 5-May -2011 **www.power-one.com** e Page 31 of 33
_**ZY7120 20A DC-DC Intelligent POL Data Sheet**_ _**3V to 13.2V Input 0.5V to 5.5V Output**_ LE the—————d Shape ofPower
## **10. Mechanical Drawings**
**==> picture [506 x 413] intentionally omitted <==**
**----- Start of picture text -----**<br>
All Dimensions are in mm<br>Tolerances:<br>0.5-10 0.1<br>10-100 0.2<br>Pin Coplanarity: 0.1 max<br>10<br>SMT Pickup Tab<br>14±0.3 13.4 Ee als oh b.<br>pe atlas<br>3.4 2.5<br>0.6<br>0.6 1.27 0.4 2.54 1.27 0.25<br>(x10) (x20) (x10) 1.5 4.3<br>ia am iii :<br>2.03 27.94<br>32±0.3 Tilt Specification:<br><5° from vertical,<br>9.75 12 10.25 after assembly<br>12 9.1<br>3.5<br>8.25±0.3 1.5±0.1<br>3.25<br>| SiNiMininiNin NTT TTT<br>Pin 1<br>15.75 SMT Pickup<br>Center Point<br>**----- End of picture text -----**<br>
**Figure 57. Mechanical Drawing**
**Figure 58. Pinout Diagram (Bottom View)**
Page 32 of 33
ZD-00194 Rev. 2.7, 5-May -2011
**www.power-one.com**
## _**ZY7120 20A DC-DC Intelligent POL Data Sheet**_ SN. _**3V to 13.2V Input**_ _**0.5V to 5.5V Output**_ Changing the Shape————————————— ofPower
**==> picture [12 x 7] intentionally omitted <==**
**----- Start of picture text -----**<br>
8.6<br>**----- End of picture text -----**<br>
**==> picture [506 x 431] intentionally omitted <==**
**----- Start of picture text -----**<br>
32<br>4<br>| 10 10 6<br>1.2<br>(x 3)<br>Unexposed thermal copper<br>area associated with each pad ! 6 9<br>must be free from other traces 1.8<br>a r oy<br>(x 22)<br>i Pin 1<br>2<br>1.27 2.54 1.27 2.03<br>(x 10) (x 10)<br>0.8<br>Figure 59. Recommended Pad Sizes<br>8.6 8.6 8.6<br>4 §COOCOCOCOO, OOCOOCCOOCO) |OOCOCOOCOO0O<br>__Y<br>10 10<br>Y yo OQOOOO0O00, = OQOOO0O0O<br>0.45mm Ø Thermal Via x 16 0.45mm Ø Thermal Via x 16 0.45mm Ø Thermal Via x 16<br>Recommended via diameter is 0.45mm Barrel wall plating of > 25um Pitch <1.00mm<br>6.4 4.0<br>**----- End of picture text -----**<br>
**Figure 60. Recommended PCB Layout for Multilayer PCBs**
## **Notes:**
1. NUCLEAR AND MEDICAL APPLICATIONS - Power-One products are not designed, intended for use in, or authorized for use as critical components in life support systems, equipment used in hazardous environments, or nuclear control systems without the express written consent of the respective divisional president of Power-One, Inc.
2. TECHNICAL REVISIONS - The appearance of products, including safety agency certifications pictured on labels, may change depending on the date manufactured. Specifications are subject to change without notice.
I2C is a trademark of Philips Corporation.
Page 33 of 33
ZD-00194 Rev. 2.7, 5-May -2011
**www.power-one.com**
Updated at June 9, 2026
About Novapart
Novapart is a B2B electronic component broker specialising in stock shortages and cost reduction. We source hard-to-find parts and identify compliant alternatives across a catalogue of 540,000+ components from 500+ manufacturers.
Learn more →Stock Shortage Specialist
When a component is unavailable, discontinued or has an unacceptable lead time, we tap into our network of vetted European and Asian distributors to source what you need — without compromising on quality or traceability.
Request a quote →Compliant Alternatives
We identify pin-to-pin, electrically equivalent substitutes that meet the same certifications (RoHS, AEC-Q100, REACH) as your original specification — validated against datasheets, not just part numbers. Often at a lower cost.
BOM Analysis service →