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XDPL8221XUMA1
LED Driver AC/DC, Flyback, 90V to 305V Input, 180 kHz, 2 Outputs, SOIC-16
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- Manufacturer: INFINEON
- Product type: AC / DC LED Driver ICs
- Device Topology:Flyback; Input Voltage Min:90V; Input Voltage Max:305V; Output Voltage Max:-; Output Current Max:-; Switching Frequency:180kHz; No. of Outputs:2Outputs; IC Mounting:S
- MSL: MSL 3 - 168 hours
- SVHC: No SVHC (25-Jun-2025)
- Topology: Flyback
- IC Mounting: Surface Mount
- No. of Pins: 16Pins
- Product Range: -
- Qualification: -
- No. of Outputs: 2Outputs
- Device Topology: Flyback
- LED Driver Type: Isolated
- Driver Case Style: SOIC
- IC Case / Package: SOIC
- Input Voltage Max: 305V
- Input Voltage Min: 90V
- Output Current Max: -
- Output Voltage Max: -
- Switching Frequency: 180kHz
- Switching Frequency Typ: 180kHz
- Operating Temperature Max: 125°C
- Operating Temperature Min: -40°C
- Automotive Qualification Standard: -
| Delivery and price | |
|---|---|
| Units per pack | 1000 |
| Price | 1.19 € |
| Current stock | 1000+ |
| Lead time | 7 days |
Datasheet
**XDPL822x Controller Family**
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## **XDPL8221 Digital PFC+Flyback Controller IC**
## **XDP[™] Digital Power**
**Data Sheet Revision 1.1**
## **Features**
- UART interface to control driver output and reading operating status
- Flicker-free output dimming by analog reduction of driving current down to 1%
- Integrated two stage digital controller allows a reduced number of external parts, optimizes _**Bill of Materials (BOM)**_ and form factor.
- Two-stage design eliminates AC ripple on output.
- Supports universal AC and DC input voltage (90 V rms to 305 V rms) nominal.
- High efficiency up to 90%
- Multi-control output ( _**Constant Current (CC)**_ / _**Constant Voltage (CV)**_ / _**Limited Power (LP)**_ )
- Performance and protection related driver parameters are configurable via UART interface allowing for design flexibility and optimization.
- Low harmonic distortion ( _**Total Harmonic Distortion (THD)**_ < 15%) down to 30% nominal load
- Integrated 600V high voltage start-up cell ensures fast time to light (< 250 ms)
- Configurable Adaptive Temperature Protection
- Automatic switching of the _**Power Factor Correction (PFC)**_ between _**Quasi-Resonant Mode (QRM)**_ and _**Discontinuous Conduction Mode (DCM)**_
- Automatic switching of the _**Flyback (FB)**_ between _**QRM**_ , _**DCM**_ and _**Active Burst Mode (ABM)**_
- _**Pulse Width Modulation (PWM)**_ dimming input
For safe operation, the XDPL8221 contains a comprehensive set of protection features with configurable reaction like auto-restart or latch:
- Output over-voltage protection (open load)
- Output under-voltage protection (output short)
- VCC over- and under-voltage lockout
- Input over- and under-voltage protection
- Bus over- and under-voltage protection
- Over-current protection for both _**PFC**_ and _**FB**_ stages
## **Applications**
- AC/DC LED Drivers for _**Light Emitting Diode (LED)**_ luminaires
Please read the Important Notice and Warnings at the end of this document
Data Sheet **www.infineon.com**
Revision 1.1 2018-10-31
**XDPL8221 Digital PFC+Flyback Controller IC XDP[™] Digital Power**
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## **Description**
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**----- Start of picture text -----**<br>
L<br>Input<br>voltage CoolMOS™<br>GDPFC<br>LED+<br>CSPFC<br>GDFB CoolMOS™<br>N<br>TEMP CSFB<br>LED-<br>XDPL8221<br>HV VCC<br>VS ZCD<br>GND<br>UART PWM PWM<br>UART GND Vsupply<br>**----- End of picture text -----**<br>
## **Figure 1 Typical Application for XDPL8221**
|**Figure 1**<br>**Typical Application for XDPL8221**||
|---|---|
|**Product Type**|**Package**|
|XDPL8221|PG-DSO-16|
## **Description**
XDPL8221 is a highly integrated next-generation device combining a multimode ( _**QRM**_ and _**DCM**_ ) _**PFC**_ plus a multimode ( _**QRM**_ , _**DCM**_ and _**ABM**_ ) _**FB**_ with primary-side regulation. The integration of _**PFC**_ and _**FB**_ into a single controller enables reduction of external parts and optimizes performance by harmonized operation of the two stages.
The two-stage approach divides the _**PFC**_ responsibilities from the output current regulations functions. This ensures low variation in the output current (flicker) to a non-visible level and allows for low _**THD**_ , high power factor and a greater ability to withstand AC line perturbations.
XDPL8221 _**PFC**_ comprises of constant on-time scheme with a _**THD**_ improvement algorithm to provide a high power factor and excellent performance down to 30% nominal load.
XDPL8221 _**FB**_ can be configured to operate in Constant Voltage (CV), Constant Current (CC) or Limited Power (LP) mode offering a large degree of flexibility.
The on-chip _**One Time Programmable Memory (OTP)**_ memory allows user to adjust electrical and performance parameters that control the behavior of the circuit. Examples of this include: output current limit or the maximum output power. This enables the user of the device to create a platform concept with significantly fewer different hardware versions while still covering the same application range.
The _**Universal Asynchronous Receiver Transmitter (UART)**_ command interface allows connecting XDPL8221 to any microcontroller, wireless interface or sensor for many different applications.
During low power mode, the XDPL8221 power consumption is less than 100mW.
Data Sheet
Revision 1.1 2018-10-31
2
**XDPL8221 Digital PFC+Flyback Controller IC XDP[™] Digital Power**
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## **Table of contents**
## **Table of contents**
||**Features**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1|
|---|---|
||**Applications**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1|
||**Description**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2|
||**Table of contents**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3|
|**1**|**Pin Configuration**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5|
|**2**|**Functional Block Diagram**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6|
|**3**|**Functional Description**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7|
|3.1|PFC Controller Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8|
|3.1.1|Shared CS/ZCD Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8|
|3.1.2|Quasi-resonant Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8|
|3.1.3|Bus Voltage Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9|
|3.1.4|Input Voltage Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10|
|3.1.5|Control Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11|
|3.1.5.1|Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11|
|3.1.6|Multimode Control Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11|
|3.1.6.1|Frequency Law . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12|
|3.1.6.2|THD Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12|
|3.1.6.3|Light Load Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13|
|3.1.7|Peak Current Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13|
|3.1.8|Protection Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14|
|3.1.8.1|Bus Under-voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14|
|3.1.8.2|Bus Over-voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14|
|3.1.8.3|Input Under-voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15|
|3.1.8.4|Input Over-voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15|
|3.1.8.5|Other PFC Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16|
|3.2|Flyback Controller Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17|
|3.2.1|Primary Side Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17|
|3.2.1.1|Primary Side Current Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18|
|3.2.1.2|Primary Side Output Voltage Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18|
|3.2.1.3|Output Current Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19|
|3.2.1.4|Output control scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19|
|3.2.1.5|Multimode Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22|
|3.2.1.6|Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23|
|3.2.2|Flyback Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24|
|3.2.3|Protection features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25|
|3.2.3.1|Primary Over-current Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25|
|3.2.3.2|Output Under-voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25|
|3.2.3.3|Output Over-voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25|
Data Sheet
Revision 1.1 2018-10-31
3
**XDPL8221 Digital PFC+Flyback Controller IC XDP[™] Digital Power**
**==> picture [105 x 47] intentionally omitted <==**
## **Table of contents**
|3.2.3.4|Output Over-current Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26|
|---|---|
|3.2.3.5|Output Over-power Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26|
|3.2.3.6|Other Flyback Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26|
|3.2.3.6.1|Flyback Bus Voltage Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26|
|3.3|General Controller Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27|
|3.3.1|Configurable Gate Driver Strengths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27|
|3.3.2|External Temperature Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27|
|3.3.3|Adaptive temperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27|
|3.3.4|PWM Dimming Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28|
|3.3.5|UART Command Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29|
|3.3.6|Protection features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33|
|3.3.6.1|Overtemperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33|
|3.3.6.2|VCC Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33|
|3.3.6.3|VCC Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34|
|3.3.6.4|VCC Undervoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34|
|3.3.6.5|Other General Controller Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34|
|3.3.7|Protection Reactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34|
|3.3.7.1|Auto restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36|
|3.3.7.2|Fast Auto Restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36|
|3.3.7.3|Latch Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36|
|3.3.7.4|Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36|
|**4**|**Electrical Characteristics and Parameters**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37|
|4.1|Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37|
|4.2|Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37|
|4.3|Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38|
|4.4|DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38|
|**5**|**Package Dimensions**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52|
|**6**|**References**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53|
||**Revision History**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53|
||**Glossary**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53|
||**Disclaimer**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57|
Data Sheet
Revision 1.1 2018-10-31
4
**XDPL8221 Digital PFC+Flyback Controller IC XDP[™] Digital Power**
**==> picture [105 x 47] intentionally omitted <==**
## **Pin Configuration**
## **1 Pin Configuration**
Pin assignments and basic pin description information are shown below.
|||||||||||
|---|---|---|---|---|---|---|---|---|---|
|GDFB<br>CSFB||||1<br>2|15<br>16||||N.C.<br>N.C.|
|VCC||||3|14||||UART|
|GND||||4|13||||GDPFC|
|ZCD||||5|12||||N.U.|
|VS||||6|11||||CSPFC|
|N.U.||||7|10||||TEMP|
|HV||||8|9||||PWM|
|||||||||||
|||PG-DSO-16|||(150mil)|||||
## **Figure 2 Pinning of XDPL8221**
|**Table 1**<br>**Pin Definitions and Functions**|**Table 1**<br>**Pin Definitions and Functions**|**Table 1**<br>**Pin Definitions and Functions**|**Table 1**<br>**Pin Definitions and Functions**|
|---|---|---|---|
|**Name**|**Pin**|**Type**|**Function**|
|_GDFB_|1|O|Gate driver for**_FB_**:<br>The_GDFB_pin is an output for directly driving a power MOSFET of the**_FB_**<br>stage.|
|_CSFB_|2|I|Current sensing for**_FB_**:<br>The_CSFB_pin is connected to an external shunt resistor and the source of the<br>power MOSFET of the**_FB_**stage.|
|_VCC_|3|I|Voltage supply|
|_GND_|4|-|Power and signal ground|
|_ZCD_|5|I|Zero-crossing detection of the**_FB_**:<br>The_ZCD_pin is connected to an auxiliary winding of the**_FB_**stage for zero-<br>crossing detection as well as primary-side output voltage and additional bus<br>voltage sensing for functional safety.|
|_VS_|6|I|Bus voltage sensing|
|N.U.|7|-|Not used. Externally to be connected to_GND_.|
|_HV_|8|I|High voltage:<br>The_HV_pin is connected to the rectified input voltage via an external resistor.<br>An internal 600 V HV startup-cell is used to initially charge_VCC_. In addition,<br>sampled high-voltage sensing is also used for synchronization with the input<br>frequency.|
|_PWM_|9|I|**_PWM_**dimming:<br>The_PWM_pin is used as a dimming input.|
|_TEMP_|10|I|External temperature sensor:<br>Measurement of external temperature using an**_Negative Temperature_**<br>**_Coeficient Thermistor (NTC)_**.|
|_CSPFC_|11|I|Current sensing for**_PFC_**:<br>The_CSPFC_pin is connected to an external shunt resistor and the source of<br>the power MOSFET of the**_PFC_**stage.|
Data Sheet
Revision 1.1 2018-10-31
5
**XDPL8221 Digital PFC+Flyback Controller IC XDP[™] Digital Power**
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## **Functional Block Diagram**
|**Table 1**<br>**Pin Definitions and Functions (continued)**|**Table 1**<br>**Pin Definitions and Functions (continued)**|**Table 1**<br>**Pin Definitions and Functions (continued)**|**Table 1**<br>**Pin Definitions and Functions (continued)**|
|---|---|---|---|
|**Name**|**Pin**|**Type**|**Function**|
|N.U.|12|-|Not used. Externally to be connected to_GND_.|
|_GDPFC_|13|O|Gate driver for**_PFC_**:<br>The_GDPFC_pin is an output for directly driving a power MOSFET of the**_PFC_**<br>stage.|
|_UART_|14|I/O|**_UART_**communication:<br>The_UART_pin is used for the**_UART_**interface to support parametrization and<br>for application commands during run-time.|
|N.U.|15|-|Not used. Externally to be connected to_GND_.|
|N.U.|16|-|Not used. Externally to be connected to_GND_.|
## **2 Functional Block Diagram**
The functional block diagram shows the basic data flow from input pins via signal processing to the output pins.
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**----- Start of picture text -----**<br>
Power Factor Correction Flyback<br>Input Voltage Output Voltage<br>HV Sensing and Sensing and Zero ZCD<br>Startup Crossing Detection<br>PFC Control Output Current<br>GDPFC CSFB<br>Loop Calculation<br>Current Sensing and<br>CSPFC Zero Crossing FB Control Loop GDFB<br>Detection<br>Bus Voltage<br>VS Adaptive<br>Sensing PWM Dimming<br>Temperature PWM<br>Sensing<br>Protection<br>VCC UART Command<br>VCC UART<br>Management Interface<br>External<br>TEMP Temperature<br>Sensing<br>**----- End of picture text -----**<br>
**Figure 3 XDPL8221 Simplified Functional Block Diagram**
Data Sheet
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**XDPL8221 Digital PFC+Flyback Controller IC XDP[™] Digital Power**
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## **Functional Description**
## **3 Functional Description**
This chapter provides a summary of the integrated functions and features, and describes the relationships between them. The parameters and equations are based on typical values at TA = 25 °C.
XDPL8221 is a digital dual-stage _**PFC**_ and _**FB**_ controller IC supporting _**PWM**_ dimming functionality. Both stages use configurable multi-mode operation to select the best mode of operation for every operation condition. Multi-mode operation automatically switches between _**QRM**_ , _**DCM**_ and _**ABM**_ (only for _**FB**_ )
XDPL8221 features a comprehensive set of configurable protection modes to detect fault conditions. XDPL8221 provides a high degree of flexibility in design-in of the application. A _**Graphic User Interface (GUI)**_ tool supports users in the configuration of the operational and protection parameters.
Data Sheet
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**XDPL8221 Digital PFC+Flyback Controller IC XDP[™] Digital Power**
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## **Functional Description**
## **3.1 PFC Controller Features**
The _**PFC**_ stage ensures high power quality by maximizing the power factor and minimizing harmonic distortion.
The _**PFC**_ stage operates in _**Quasi-Resonant Mode, switching in first valley (QRM1)**_ and _**Quasi-Resonant Mode, switching in valley n (QRMn)**_ , to support light load conditions and ensure efficient operation.
The _**PFC**_ stage is implemented as a boost converter and provides stabilized _**Direct Current (DC)**_ voltage rail.
## **3.1.1 Shared CS/ZCD Function**
The _**PFC**_ stage makes use of combined Current Sense and Zero-Crossing Detection (CS/ZCD) functionality at the CSPFC pin.
During the _**PFC**_ MOSFET on-time, the CSPFC pin has the function of sensing the _**PFC**_ inductor current ensuring inductor does not enter saturation, and the converter limits maximum switching current.
The CSPFC pin is connected to an external shunt resistors, which converts the inductor current to voltage. The sensed voltage at the CSPFC pin is compared with reference voltages on internal comparators to either limit the on-time cycle by cycle or enter the protection mode when over-current happens.
During the _**PFC**_ MOSFET off-time, the CSPFC pin has the function of current zero crossing detection (ZCD). This detection minimizes the turn-on losses of the _**PFC**_ MOSFET by ensuring the MOSFET turns-on during the resonant valley of the _**PFC**_ MOSFET drain-source voltage (VDS) ( _**QRM**_ ). The CSPFC pin is connected via an external resistor divider composed of RZCD,1,PFC and RZCD,2,PFC and a set of diodes to the auxiliary winding of the _**PFC**_ inductor.
Diode D1 allows positive voltage at the CSPFC pin as the valley detection is implemented by the internal hysteretic comparator with a positive reference of nominal THRHYS for falling edges.
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**----- Start of picture text -----**<br>
Vg L Vbus<br>RZCD,1,PFC<br>D1<br>GDPFC<br>CSPFC<br>RCS,PFC RZCD,2,PFC<br>VCC<br>**----- End of picture text -----**<br>
## **Figure 4 Shared CS/ZCD Schematic**
## **3.1.2 Quasi-resonant Mode**
The quasi-resonant mode maintains a high efficiency level.
XDPL8221 _**PFC**_ Quasi-resonant mode reduces _**PFC**_ MOSFET switching losses and ensures highest possible efficiency of the system. See Multi-mode Scheme description for detailed _**QRM**_ operation in section 3.1.6.
Data Sheet
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**XDPL8221 Digital PFC+Flyback Controller IC XDP[™] Digital Power**
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## **Functional Description**
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**----- Start of picture text -----**<br>
tsw tsw<br>iL<br>iL,pk<br>tw iL,ave<br>0<br>t on t 1stV t<br>t LEB<br>vCSPFC tosc<br>4<br>vL,pk<br>0<br>t disch t<br>QRM1 QRM2 QRM1<br>**----- End of picture text -----**<br>
## **Figure 5 PFC QRM2 Waveforms**
Equations for the quasi-resonant operation are shown below. Delay time tw is an additional delay realized in each switching cycle when _**PFC**_ MOSFET turn-on beyond first resonant valley and valley n (n>1) is selected ( _**QRMn**_ ).
_i V g_ · _ton L_ , _pk_ = _L i L tdisch_ = _V L_ , _pk_ · _V bus_ − _g t_ 1 _stV_ = _tdisch_ + _tosc_ /2 _t t n_ −1 _w_ = _osc_ · _tsw_ = _ton_ + _t_ 1 _stV_ + _tw t_ = _t t off_ 1 _stV_ + _w_
## **Equation 1**
## **3.1.3 Bus Voltage Sensing**
The _**PFC**_ output bus voltage is scaled down using a simple resistor divider and measured at the pin VS. A capacitor shall be added at the pin to ground to filter high-frequency switching noise.
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**----- Start of picture text -----**<br>
Vbus<br>RVS,1<br>VS<br>RVS,2<br>**----- End of picture text -----**<br>
## **Figure 6**
## **PFC Bus Voltage Sensing Circuit**
The _**Analog-to-Digital Converter (ADC)**_ input at the VS pin utilizes two voltage ranges. The wider voltage range from 0 to VREF results in lower resolution. The narrower voltage range from 5/6 VREF to 7/6 VREF gives better voltage resolution. Steady state operation therefore normally takes place in the high-resolution range and soft start operation in the low-resolution range.
Data Sheet
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**XDPL8221 Digital PFC+Flyback Controller IC XDP[™] Digital Power**
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## **Functional Description**
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**----- Start of picture text -----**<br>
VS<br>7/6 VREF<br>High<br>VREF resolution<br>range<br>5/6 VREF<br>Low<br>resolution<br>range<br>0 V<br>t<br>**----- End of picture text -----**<br>
**Figure 7 Sensing Ranges**
## **3.1.4 Input Voltage Sensing**
The input voltage is sensed at the HV pin for _**Alternating Current (AC)**_ zero-crossing detection and protection features.
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**----- Start of picture text -----**<br>
iac<br>vac<br>Input<br>voltage<br>RHV<br>Vin<br>HV<br>C1 C2<br>{<br>**----- End of picture text -----**<br>
**Figure 8**
**Input Voltage Sensing Schematic**
The RHV sense resistor is usually split into two or more resistors for redundancy and safety purposes. A RC filter structure to the HV pin is implemented as shown above to reduce the unwanted noise.
Data Sheet
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**XDPL8221 Digital PFC+Flyback Controller IC XDP[™] Digital Power**
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## **Functional Description**
## **3.1.5 Control Scheme**
The _**PFC**_ bus voltage controller embeds a controller that calculates a control output representing load and line conditions from the bus voltage error signal.
The bus voltage controller implements regulation during both soft start and steady states.
## **3.1.5.1 Startup**
At system startup, the _**PFC**_ initiates soft start to minimize the switching stress on the power MOSFET, diode and inductor.
_**PFC**_ soft start is executed once the _**PFC**_ bus voltage is charged due to rectified AC line to a voltage threshold Vbus,start,PFC but lower than Vbus,OVP1. The _**PFC**_ soft start is aborted if the input under- or over-voltage protections are triggered. During soft start, the _**PFC**_ operates in _**QRM1**_ mode. Once the Vbus,stdy,entr,UV threshold is reached, the steady state _**PFC**_ operation starts.
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**----- Start of picture text -----**<br>
Vbus<br>Vbus,set<br>Vbus,stdy,entr,UV<br>Vbus,start,PFC<br>t<br>VCC startup steady state<br>passive charging<br>charging<br>**----- End of picture text -----**<br>
**Figure 9 Vbus Soft Start and Regulation**
## **3.1.6 Multimode Control Scheme**
The XDPL8221 multi-mode control scheme provides an option to dynamically change the operating point by switching between the MOSFET Vds voltage valleys while following a frequency law and applying _**THD**_ optimization.
The multi-mode controller uses three different modes of operation:
- _**QRM1**_ : operation occurs during normal operation of the _**PFC**_ converter at nominal to heavy loads. This operation maximizes the efficiency by switching on at the 1st valley of the _**PFC**_ ZCD signal. This ensures zero current switching with a minimum switching losses. During _**QRM1**_ , the _**PFC**_ MOSFET is turned on with a constant on-time for a line and load condition, while the off- time varies within an AC half-cycle depending on the instantaneously rectified AC input voltage. Subsequently, the PFC switching frequency varies within each AC half-cycle with the lowest switching frequency at the peak of the AC input voltage and the highest switching frequency near the zero crossings of the input voltage.
- _**QRMn**_ : _**PFC**_ MOSFET on-time reduces as the load decreases, this results in higher switching frequencies, particularly near the zero-crossing of the input voltage. Higher switching frequencies will increase switching losses, resulting in poor efficiency at light loads. The XDPL8221 controller extends to the next switching valley after the 1st valley to control the bus voltage following a frequency law which limits the switching frequency to minimize the switching losses.
- _**DCM**_ : The controller regulates the power transfer by adjusting the switching frequency with fixed minimum on-time. This enables the light load optimization.
Data Sheet
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**XDPL8221 Digital PFC+Flyback Controller IC XDP[™] Digital Power**
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## **Functional Description**
The multimode optimization consists of the following:
- Frequency law
- THD optimization
- DC switching frequency dithering
- Light load optimization
## **3.1.6.1 Frequency Law**
A _**PFC**_ converter is used to emulate a resistive load re to the _**AC**_ input such that iac follows vac in both wave shape and phase. The output of the _**PFC**_ bus voltage controller ton,des,PFC is inversely proportional to the emulated resistive load re such that a smaller re or a higher Iac,rms will give a larger ton,des,PFC. Thus, ton,des,PFC varies as the _**AC**_ line voltage magnitude varies and is proportional to the RMS input current Iac,rms.
The rule for selecting _**QRMn**_ is based on the frequency law. A maximum switching frequency fswmax and a minimum switching frequency fswmin are defined for the complete ton,des,PFC/Iac,rms range. The frequency law ensures that the switching frequency is within the desired frequency range. The frequency law is depicted in the figure below.
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**----- Start of picture text -----**<br>
fsw<br>fswmax<br>fswmin<br>sample ton,des,PFC<br>operating / Iac,rms<br>point<br>QRM5QRM4QRM3QRM2QRM1<br>**----- End of picture text -----**<br>
## **Figure 10 PFC Frequency Law**
As long as the _**PFC**_ controller operating mode satisfies the frequency law, the operating mode does not change. The QR-valley is increased when the highest frequency limit is reached. The QR-valley is decremented when the lowest frequency limit is reached.
To ensure proper ZCD detection before the ZCD signal becomes too small in amplitude, only the first up to Nvalley,max,PFC valleys operations are supported.
## **3.1.6.2**
## **THD Optimization**
_**QRMn**_ selection beyond the first valley during light load and/or _**AC**_ high line reduces the switching frequency but distorts the input current waveform with constant on-time control and _**THD**_ may suffer. The multi-mode _**PFC**_ control consists of a _**THD**_ optimization algorithm that optimizes the applied on-time in order to ensure good input current shaping and improved _**PFC THD**_ performance.
Data Sheet
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**XDPL8221 Digital PFC+Flyback Controller IC XDP[™] Digital Power**
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## **Functional Description**
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**----- Start of picture text -----**<br>
Vin<br>t<br>ton<br>QRM3<br>QRM2<br>QRM1<br>BCM<br>t<br>**----- End of picture text -----**<br>
## **Figure 11 THD optimization on-time**
_**Figure 11**_ shows the on-time at different valley selection at the same line and load conditions.
_Note: Boundary Conduction Mode (BCM) is an operating mode where the switch turns on at the first occurrence of inductor zero current ._
## **3.1.6.3 Light Load Optimization**
This paragraph describes how the _**PFC**_ manages light load conditions.
## **DCM**
_**PFC**_ converter will eventually enter DCM operation as load decreases and/or _**AC**_ line increases to reduce the switching frequency and switching losses. XDPL8221 _**PFC**_ control enters _**DCM**_ when the internal on-time is less than ton,dcm. The _**PFC**_ leaves _**DCM**_ when the switching period is less than tsw,min,dcm. When the _**PFC**_ is operating in _**DCM**_ , the bus voltage controller regulates the switching period keeping the on-time constant. Due to the ontime dependency on the input voltage, the _**PFC**_ enters and exits _**DCM**_ at different power levels. This has the advantage to operate in _**QRM**_ for an extended power range at low line maintaining high efficiency.
## **3.1.7 Peak Current Limitation**
The peak current through the switching MOSFET is sensed via the _**PFC**_ shunt resistor RCS,PFC to limit the maximum current through the MOSFET, the choke, and freewheeling diode.
_**Overcurrent Protection Level 1 (OCP1)**_ is implemented by hardware. If the voltage VCS,PFC across the shunt resistor exceeds the over-current threshold VCS,OCP1, PFC for longer than the blanking time tblank,OCP1,PFC, the MOSFET is turned off. The MOSFET is turned on when ZCD occurs or the PFC maximum period time-out signal triggers the start of the next switching cycle. _**Overcurrent Protection Level 2 (OCP2)**_ is a second-level overcurrent protection implemented by hardware. The _**OCP2**_ overcurrent threshold is fixed. The _**OCP2**_ blanking time is tblank,OCP2,PFC.
Data Sheet
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**XDPL8221 Digital PFC+Flyback Controller IC XDP[™] Digital Power**
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## **Functional Description**
## **3.1.8 Protection Features**
Protections features are triggered if fault conditions are present longer than the blanking times for each protection.
_**Attention** :_ _**The controller may continue operation after exceeding protection thresholds because of blanking times as shown in Figure 12. All protection thresholds have to be set with respect to tolerances, blanking times and worst case transients.**_
_Note: The blanking time as specified in the csv file does not include the protection notification time._
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**----- Start of picture text -----**<br>
Sampled voltage Protection<br>or sampled current Sampled voltage<br>triggering<br>Overvoltage or Overcurrent<br>protection threshold<br>Protection<br>Undervoltage triggering<br>protection threshold<br>Time Time<br>tblank tblank<br>**----- End of picture text -----**<br>
## **Figure 12 Blanking Times cause Excess of Threshold**
## **3.1.8.1 Bus Under-voltage Protection**
Under-voltage detection of the _**PFC**_ bus voltage Vbus is sensed at the VS pin.
The _**PFC**_ bus voltage is sensed and compared to a configurable under-voltage protection threshold Vbus,UV. If the bus voltage is below the threshold for longer than the blanking time tblank,Vbus,UV, the protection will be triggered.
## **3.1.8.2 Bus Over-voltage Protection**
Over-voltage detection of the _**PFC**_ bus voltage Vbus is sensed at the VS pin.
The _**PFC**_ bus voltage is sensed and compared to a configurable over-voltage protection threshold Vbus,OVP1 in _**Firmware (FW)**_ . If this threshold is exceeded for longer than the blanking time tblank,Vbus,OVP1, the _**PFC**_ stops switching. The _**PFC**_ resumes operation when Vbus falls below Vbus,stdy,entr,OV.
Vbus,OVP2 is implemented in _**Hardware (HW)**_ and it is fixed at a voltage which is represented as 7/6 VREF at the bus voltage sensing pin (VS). The HW permits a blanking time tblank,Vbus,OVP2 to be programmed.
Data Sheet
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**XDPL8221 Digital PFC+Flyback Controller IC XDP[™] Digital Power**
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## **Functional Description**
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**----- Start of picture text -----**<br>
Vbus<br>Vbus,ovp2<br>Vbus,ovp1<br>Vbus,stdy,entr,OV<br>Vbus,set<br>Vbus,uv<br>t<br>**----- End of picture text -----**<br>
## **Figure 13 Vbus protections**
## **3.1.8.3 Input Under-voltage Protection**
Under-voltage detection of the input voltage Vin is sensed at the HV pin.
Values of Vin,rms are compared to a configurable input undervoltage protection threshold Vin,UV. If the input voltage is below the threshold for longer than the blanking time tblank,Vin,UV, the protection will be triggered. XDPL8221 features a configurable start-up threshold Vin,start,min to create hysteresis for flicker-free operation before the second stage starts switching.
## **3.1.8.4 Input Over-voltage Protection**
Over-voltage detection of the input voltage Vin is sensed at the HV pin.
Values of Vin,rms are compared to a configurable input over-voltage protection threshold Vin,OV. If the threshold is exceeded for longer than the blanking time tblank,Vin,OV, the protection will be triggered. XDPL8221 features a configurable start-up threshold Vin,start,max to create hysteresis for flicker-free operation before the second stage starts switching.
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**----- Start of picture text -----**<br>
Vin<br>Vin,OV<br>Vin,start,max<br>Vin,start,min<br>Vin,UV<br>t<br>tstart,delay,FB<br>**----- End of picture text -----**<br>
**Figure 14**
**Vin protections**
Data Sheet
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**XDPL8221 Digital PFC+Flyback Controller IC XDP[™] Digital Power**
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## **Functional Description**
## **3.1.8.5 Other PFC Protections**
## **Current Sense (CS) Resistor Short Protection**
The input fuse should be chosen appropriately to protect converter if current-sense resistor is shorted.
## **Current Sense (CS) Resistor Open Protection**
CS/ZCD external circuitry pulls the CSPFC pin high when CS resistor is open, OCP2 protection is triggered.
## **CSPFC Pin Short to GND Protection**
In case of CSPFC pin short to ground the missing of quasi-resonant oscillations will trigger the CCM Protection.
## **CCM Protection**
Continuous conduction mode (CCM) operation may occur during _**PFC**_ startup for a limited time and is allowed. In normal operation, extended CCM operation in the _**PFC**_ converter is considered a failure.
Circumstances where the _**PFC**_ converter may experience CCM operation:
- Shorted PFC bypass diode
- Heavy load step which is out of specification
- Low input voltage outside the normal operating range
During CCM operation, the magnetizing current in the _**PFC**_ choke does not decay to zero prior to MOSFET turnon. Quasi-resonant oscillation is missing in the ZCD signal before the maximum switching period time-out is reached that turns the MOSFET on. This turn-on event without ZCD oscillation is monitored to protect the _**PFC**_ converter from continuous CCM operation. Extended CCM operation protection is implemented within _**FW**_ .
If quasi-resonant oscillation is missing in the ZCD signal for longer than the blanking time tblank,CCM,PFC, the protection is triggered.
## **Soft Start Failure**
_**PFC**_ start-up time maybe extended due to abnormally heavy loads or a low input voltages. _**PFC**_ steady state operation may not be reached if tstart,PFC reaches tstart,max,PFC before the soft start has ended, and the protection is triggered.
Data Sheet
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**XDPL8221 Digital PFC+Flyback Controller IC XDP[™] Digital Power**
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## **Functional Description**
## **3.2 Flyback Controller Features**
The Flyback converter stage provides isolation and primary side control of the output current. Primary side regulation of the output current eliminates secondary side control feedback loop circuitry usually needed in isolated power converters. This feature reduces part count to reduce costs.
The Flyback stage features multi-mode operation ( _**QRM**_ , _**DCM**_ and _**ABM**_ ) which ensures efficiency and performance is optimized.
## **3.2.1 Primary Side Regulation**
The XDPL8221 _**FB**_ stage provides primary side control of output current and output voltage. No external feedback components are necessary for the current control.
_**Figure 15**_ shows typical current and voltage waveforms of the _**FB**_ application operating in _**QRM1**_ .
In _**DCM**_ , the MOSFET will not turn on at the first valley of the resonant oscillation seen at _V_ AUX, but instead delayed.
Primary side regulation of the average output current is accomplished by sensing the primary peak current _I_ p,pk, the period of conduction of the output diode _t_ demag and the switching period _t_ sw,FB.
The voltage signal _V_ AUX of the auxiliary winding of the transformer contains information on the reflected output voltage _V_ out. The reflected output voltage is measured at the _ZCD_ pin using a resistor divider.
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**----- Start of picture text -----**<br>
VAUX<br>Reflected output voltage sampling<br>Zero crossing detection<br>0 V<br>Bus voltage sampling<br>Valley switching<br>Ip Is<br>time<br>Vbus Vout<br>tCS,sample tZCD,sample<br>Itransformer Np Ns<br>tsw,FB Na<br>Ip,pk<br>VAUX<br>Ip Ip<br>Is<br>time<br>tdemag<br>VGD<br>time<br>**----- End of picture text -----**<br>
## **Figure 15**
**Typical Waveforms of a Flyback Converter**
Data Sheet
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**XDPL8221 Digital PFC+Flyback Controller IC XDP[™] Digital Power**
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## **Functional Description**
## **3.2.1.1 Primary Side Current Sensing**
The primary side peak current _I_ p,pk is controlled by the control loop using the _V_ CS,OCP1 level at the _CSFB_ pin. This control scheme ensures suppression of any variation in the bus voltage.
Several delays exist from the time at which the _**OCP1**_ level _V_ CS,OCP1 is exceeded at the _CSFB_ pin until the gate switches off and the transformer current finally reaches its peak value. For a higher accuracy, the primary peak current _V_ CS,SH is sampled a fixed time before turn-off of the gate. The primary side peak current is used to calculate the secondary side current and for protection. The propagation delay compensation parameter _t_ PDC allows optimization of the accuracy of the primary side peak current:
_V t_ + _t Ip_ , pk = _R_ CSCS, FB, SH[⋅] _t_ on, FB −on, FB _t_ CSFB, offsetPDC
## **Equation 2**
_Note: If an RC low pass filter is added in front of the CSFB pin, the related low pass filter delay has to be included in t_ PDC _._
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**----- Start of picture text -----**<br>
Ip<br>VCS,pk<br>Ip,pk =<br>RCS,FB<br>VCS,SH<br>RCS,FB<br>t<br>tPDC<br>VGD<br>tCSFB,offset<br>t<br>ton,FB<br>**----- End of picture text -----**<br>
## **Figure 16 Propagation Delay Compensation for accurate Primary Peak Current Calculation**
## **3.2.1.2 Primary Side Output Voltage Sensing**
The output voltage is determined by measuring the reflected output voltage on the auxiliary winding. A resistor divider adapts the voltage to the operating range of the _ZCD_ pin.
The output voltage is measured at the _ZCD_ pin using the voltage _V_ ZCD,SH at the end of the demagnetization time at the time _t_ ZCD,sample. The voltage measured at the _ZCD_ pin, the dimensioning of the resistor dividers _R_ ZCD,FB,1 and _R_ ZCD,FB,2, transformer turns _N_ s and _N_ a as well as an offset _V_ out,offset (caused by the secondary diode, for example) are used to calculate the output voltage _V_ out as follows:
_R R V_ out = _V_ ZCD, SH ZCD, FB _R_ , 1 + ZCD, FB, 2 _Ns_ ZCD, FB, 2 _Na_[+] _[ V]_[out, offset]
## **Equation 3**
_V_ out is used for _**Primary Side Regulated (PSR)**_ control loops in _**CV**_ and _**LP**_ modes as well as for output over- and undervoltage protections.
Data Sheet
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**XDPL8221 Digital PFC+Flyback Controller IC XDP[™] Digital Power**
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## **Functional Description**
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**----- Start of picture text -----**<br>
Vout,offset<br>Na Ns<br>RZCD,FB,1 VOut<br>ZCD<br>VZCD,SH RZCD,FB,2<br>**----- End of picture text -----**<br>
## **Figure 17 Primary Side Output Voltage Sensing using** _**ZCD**_ **S&H**
_Note: Any relation between VCC and ZCD in self-supplied applications can be decoupled – e.g. by adding a linear regulator for VCC._
- _**Attention** :_ _**Please note that the time (t**_ **demag** _**) has to be longer than 2.0**_ **μ** _**s to ensure that the reflected output voltage can be sensed correctly at the ZCD pin.**_
## **3.2.1.3 Output Current Calculation**
The output current is calculated based on the primary side peak current and the timing of the switching cycle.
The output current _I_ out is calculated using the duration of conduction of the output diode _t_ demag, the switching period _t_ sw,FB as well as the number of transformer turns _N_ p, _N_ s and the transformer coupling _K_ coupling. The following equation is valid in _**QRM1**_ and _**DCM**_ :
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## **Equation 4**
In _**ABM**_ the average output current depends on the number of pulses _N_ ABM,PI and the burst period _t_ burst,FB:
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## **Equation 5**
The coupling of the transformer can be approximated using the transformer primary inductance _L_ p and the transformer primary leakage inductance _L_ p,lk as follows:
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## **Equation 6**
The calculated current _I_ out is used for the control loop in the modes _**CC**_ and _**LP**_ . The calculated current is also used for output overcurrent protection.
## **3.2.1.4**
## **Output control scheme**
The XDPL8221 includes three different control schemes for a _**CC**_ , _**CV**_ or _**LP**_ output.
Different use cases require the controller to operate according to different operation schemes:
- In the case of typical LED strings, the forward voltage of the LED string determines the output voltage of the driver. XDPL8221 operates in _**CC**_ and drives a constant output current _I_ out,full to the load. The forward voltage of the connected LED string has to be below a configurable maximum value _V_ out,set.
Data Sheet
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**XDPL8221 Digital PFC+Flyback Controller IC XDP[™] Digital Power**
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## **Functional Description**
- In the case of LED loads including a power stage (e.g. Infineon BCR linear regulators or Infineon DC/DC buck ILD2111), XDPL8221 operates in _**CV**_ , ensuring a constant voltage _V_ out,set to the load. The total output current drawn by the load has to be below a configurable maximum value _I_ out,full.
- In the case of a high output current setpoint _I_ out,full and an overly long LED string which exceeds the configurable power limit _P_ out,set, XDPL8221 operates in _**LP**_ to ensure that the power limit of the driver is not exceeded. The controller reduces the output current automatically, ensuring light output without any interruption even for overly long LED strings. The forward voltage of the connected LED string has to be below a configurable maximum value _V_ out,set.
For every update of the control loop, the control scheme is selected on the basis of the current operation conditions (output voltage _V_ out and output current _I_ out) and their distance to the three limiting setpoints ( _V_ out,set, _P_ out,set and _I_ out,full):
- For _**CC**_ schemes, the internal reference current _I_ out,full is weighted according to thermal management and a dimming curve to yield Iout,set. The calculated output current _I_ out is compared with the weighted reference current _I_ out,set to generate an error signal for the output current.
- For _**CV**_ schemes, the sensed output voltage _V_ out at the _ZCD_ pin is compared to a reference voltage _V_ out,set to generate an error signal for the output voltage.
- For _**LP**_ schemes, the output current is limited to a maximum of _I_ out,set = _P_ out,set / _V_ out.
Out of these three schemes, for each step the most critical error is selected (see _**Figure 18**_ ):
**1.** If any setpoint is exceeded, the largest error for power decrease is selected to bring the controller back to the desired operating point as quickly as possible.
**2.** If the current operating conditions are below all three setpoints, the smallest error for power increase is selected to avoid overshooting any setpoint.
The selected error signal is fed into a compensator to control the gate driver switching parameters (i.e. duty cycle and frequency) for the power MOSFET of the _**FB**_ .
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Output<br>voltage Output<br>open<br>Vout,OV Pout,set<br>Vout,set Pout,OPP<br>Constant voltage<br>Limited<br>power<br>Constant<br>current<br>Vout,start Output<br>Vout,UV short<br>Output current<br>Iout,min Iout,full Iout,OCP<br>**----- End of picture text -----**<br>
## **Figure 18 Control scheme for CC/CV/LP modes (non-dimmed)**
In dimming cases, the output current setpoint _I_ out,set is located between _I_ out,min and _I_ out,full and varies according to the sensed _**PWM**_ duty cycle _D_ DIM. Dimming can be visualized by moving the vertical line for the output current setpoint in _**Figure 19**_ from right to left.
_Note: In the limited power mode, the maximum output current is limited to I_ out,set _= P_ out,set _/ V_ out _. which is smaller than I_ out,full _. It can be selected through parameter, whether I_ out,set _or I_ out,full _should be mapped to 100% dimming level. If the I_ out,full _is mapped to 100% dimming level in the limited power mode, the dimmer will experience the dead-travel between I_ out,set _and I_ out,full _(no current change while the dimming level is changing)._
Data Sheet
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**XDPL8221 Digital PFC+Flyback Controller IC XDP[™] Digital Power**
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## **Functional Description**
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Output<br>voltage Output<br>Legend:<br>open<br>Vout,OV Pout,set Operating range<br>Constant voltage<br>Vout,set<br>Limited<br>power<br>Dimming Constant<br>current<br>Vout,start Output<br>Vout,UV short<br>Dim-to-Off<br>Output current<br>Iout,min Iout,full<br>**----- End of picture text -----**<br>
## **Figure 19 Control scheme for CC/CV/LP modes (including dimming)**
One or more of the output control schemes can be deactivated by configuration of the setpoints. Some examples are given below:
- The _**LP**_ scheme is not active for _P_ out,set > _V_ out,set * _I_ out,full. For such a configuration, the controller will only select between a _**CC**_ and _**CV**_ scheme.
- The _**CV**_ scheme is not active for _V_ out,set = _V_ out,OV as the output overvoltage protection will be triggered.
- The _**CC**_ scheme is not active for _I_ out,full = _I_ out,OC as the output overcurrent protection will be triggered.
## **Compensation of output losses**
In case any output of flyback windings is not only supplying a current to LEDs, but also supplying other consumers (e.g. bleeders, CDM10VD, etc.), the primary side regulation of the output current will not be accurate. Parameter _G_ loss allows to compensate ohmic losses on the secondary side:
Iout,corrected = Iout,uncorrected + Gloss * Vout
## **Output current slew rate limitation**
As the transient response of the _**PFC**_ stage is rather slow (especially if the PFC is in low power mode), a fast increase of the flyback power can cause a significant undershoot of the bus voltage. To limit this undershoot, the rising slew rate of the flyback output current can be limited using parameter _I_ out,slew,rate,step as shown in _**Figure 20**_ .
Data Sheet
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## **Functional Description**
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Voltage or<br>current<br>Vbus,set<br>Vbus<br>Iout,corrected Iout,set<br>Iout,slew,rate,step / 160 µs<br>Time<br>**----- End of picture text -----**<br>
## **Figure 20 Output slew rate limitation**
## **3.2.1.5 Multimode Scheme**
The control loop of XDPL8221 uses three different switching modes: _**QRM1**_ is optimized for high efficiency at high loads, _**DCM**_ is used for medium loads and _**ABM**_ is used for very light load conditions.
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Power<br>VCS,max,FB<br>Peak-current controlled<br>QRM1<br>Pmax VCS,min,FB<br>tsw,min,FB<br>Frequency controlled<br>DCM<br>tsw,max,FB<br>Pulse number controlled<br>ABM<br>Pmin NABM,min<br>Bus Voltage<br>Vbus,UV Vbus,OVP1<br>**----- End of picture text -----**<br>
## **Figure 21 Flyback Multimode Operation Scheme**
- _**QRM1**_ : This mode maximizes the efficiency by switching on the 1st valley of the _V_ AUX signal. This ensures zero current switching with a minimum of switching losses. The power is controlled by regulating the primary peak current using _V_ CS,OCP1:
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Equation 7<br>**----- End of picture text -----**<br>
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## **Functional Description**
- _**DCM**_ : This mode is used if _V_ CS,OCP1has reached its minimum value _V_ CS,min,FB. To allow lower output power, the controller extends the switching period _t_ sw,FB later than the 1st valley:
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## **Equation 8**
- _**ABM**_ : This mode is used if _V_ CS,OCP1 cannot be reduced and _t_ sw,FB cannot be increased anymore. To reduce power transfer, the controller will stop switching for some time, causing bursts of pulses:
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## **Equation 9**
The frequency of the bursts is defined by 1/ _t_ burst,FB. The pulses of each burst have a peak current of _V_ CS,min,FB and a switching frequency of 1/ _t_ sw,max,FB. The number of pulses _N_ ABM,PI is regulated to control the average power transfer during one burst period _t_ burst,FB.
The minimum power in DCM is limited by the transformer primary inductance _L_ p, maximum switching period _t_ sw,max,FB, minimum primary peak voltage _V_ CS,min,FB, maximum bus voltage _V_ bus,OVP1 and two timing parameters:
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## **Equation 10**
The minimum power in ABM is limited by the transformer primary inductance _L_ p, burst period _t_ burst,FB, minimum number of pulses _N_ ABM,min, minimum primary peak voltage _V_ CS,min,FB, maximum bus voltage _V_ bus,OVP1 and two timing parameters:
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## **Equation 11**
_Note: If the load drops below the minimum load of P_ min _, the output voltage will rise up to the output overvoltage threshold V_ out,OV _and trigger the protection. An auto-restart can be used to keep the output voltage close to V_ out,OV _until the load increases again._
## **3.2.1.6 Active Burst Mode**
The sense and control scheme for the active burst mode of the _**FB**_ is described.
The typical waveform for the gate drivers, the secondary side flyback transformer current, the output voltage and the bus voltage are shown in the figure. The bursts are repeated with a configurable burst period _t_ burst,FB. It is advised to choose a burst frequency faster than 200 Hz to ensure a sufficient light quality and reduce output ripple. On the other hand, the burst frequency should not be too high as the human ear is more sensitive to higher frequencies.
Data Sheet
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## **Functional Description**
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**----- Start of picture text -----**<br>
GDFB<br>Vout<br>Isec<br>Burst Burst Pause<br>tburst,FB<br>**----- End of picture text -----**<br>
## **Figure 22 Example Waveforms in Active Burst Mode (not drawn to scale)**
The _**FB**_ switching pulses of each burst will boost the output voltage to a higher level. During the burst pause, the output voltage drops due to the load of the power converter.
To control the average output current or the average output voltage, the _**FB**_ controller calculates the average secondary current and measures the output voltage once at the beginning and once at the end of each burst. These measurements are used to calculate the average output current and average output voltage for the complete burst. Based on these average values, the control loop updates the number of pulses per burst.
## **3.2.2 Flyback Startup**
_**FB**_ After startup, the of the XDPL8221 initiates a soft start to minimize the switching stress for the power MOSFET and secondary diode.
The controller switches with a configurable switching frequency of _f_ sw,start,FB and increases the cycle-by-cycle current limit in steps of _V_ CS,step with a configurable duration _t_ softstart for each step. After the final _V_ CS,OCP1,start limit level has been reached, the output will be charged until the minimum output voltage _V_ out,start, which ensures self-supply has been reached. At this condition, _**Continuous Conduction Mode (CCM)**_ protection as well as output undervoltage protection are activated and the control loop takes over. The starting point for the control loop is to operate in _**ABM**_ at lowest number of pulses, lowest switching frequency and lowest primary peak-current. These switching parameters avoid an overshoot of output current for a LED string with low forward voltage when dimmed down to a low output current.
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Output voltage<br>Peak current<br>Soft Start Control loop<br>active<br>Vout<br>Vout,start<br>VCS,OCP1<br>VCS,OCP1,start<br>VCS,step<br>time<br>tsoftstart<br>**----- End of picture text -----**<br>
**Figure 23 Flyback Startup Sequence**
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## **Functional Description**
## **3.2.3**
## **Protection features**
Protections ensure the operation of the controller under restricted conditions. The protection monitoring signal(s) sampling rate, protection triggering condition(s) and protection reaction are described in this section.
- _**Attention** :_ _**The sampled protection monitoring signal accuracy is subjective to the digital quantization, tolerances of components (including Integrated Circuit (IC)) and estimations with indirect sensing (e.g. input and output voltage estimations based on ZCD, CS pin signals), while the protection level triggering accuracy is subjective to the sampled signal accuracy, sampling delay, indirect sensing delay (e.g. reflected output voltage signal cannot be sensed by ZCD pin near AC input phase angle of 0° and 180°) and blanking time.**_
## **3.2.3.1 Primary Over-current Protection**
The primary side over-current protection implemented in hardware covers fault conditions like a short in the transformer primary winding or an open _CS_ pin.
The primary side current is compared to an over-current protection threshold _V_ CS,OCP2. If the threshold is exceeded for longer than the blanking time _t_ OCP2,FB, the protection will be triggered.
## **3.2.3.2 Output Under-voltage Protection**
In case of a short of the output or an overload, the output voltage may drop to a low level. Detection of undervoltage in the output voltage _V_ out is enabled by measurement of the reflected voltage at the _ZCD_ pin.
During operation, the output voltage is compared to a configurable under-voltage protection threshold _V_ out,UV. If the threshold is exceeded for longer than the blanking time _t_ blank,out,UV, the protection will be triggered.
During startup,a shorted output or a strong capacitive loading may not allow the controller charging the output voltage to _V_ out,UV,start within a timeout of _t_ start,max,FB. If this timeout expires the protection will be triggered. The timeout starts when the controller starts switching.
_Note: The startup under-voltage threshold V_ out,UV,start _has to be configured sufficiently above the undervoltage threshold V_ out,UV _to allow undershoots at start-up which may occur, especially for resistive loads which already consume power from the beginning._
- _**Attention** :_ _**Output under-voltage protection is not available while the controller operates in ABM.**_
## **3.2.3.3 Output Over-voltage Protection**
In case of a open output, the output voltage may rise to a high level. Over-voltage detection of the output voltage _V_ out is provided by measurement at the _ZCD_ pin.
The output voltage is compared to an over-voltage protection threshold _V_ out,OV. If the threshold is exceeded for longer than the blanking time _t_ blank,out,OV, the protection will be triggered.
_Note: The blanking time t_ blank,Vout,OV _must be taken into account because overshoots of the output voltage above the protection threshold can occur due to this time._
_Note: This protection is usually triggered if the output is open or the output load drops below the minimum load P_ min _._
- _**Attention** :_ _**Output over-voltage protection is not available while the controller operates in ABM.**_
Data Sheet
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## **Functional Description**
## **3.2.3.4 Output Over-current Protection**
Over-current detection in the output current _I_ out is provided on the basis of the calculated output current.
The calculated output current is compared to a configurable over-current protection threshold _I_ out,OC. If the threshold is exceeded for longer than the blanking time _t_ blank,out,OC, the protection will be triggered.
## **3.2.3.5 Output Over-power Protection**
Over-power detection in the output power _P_ out is provided on the basis of the calculated output power.
The calculated output power is compared to a configurable over-power protection threshold _P_ out,OP. If the threshold is exceeded for longer than the blanking time _t_ blank,out,OP, the protection will be triggered.
## **3.2.3.6 Other Flyback Protections**
XDPL8221 includes additional protections to ensure the integrity and correct flow of the firmware.
- A hardware weak pull-up protects against an open _CSFB_ pin. The _CSFB_ OCP2 will be triggered for an open _CSFB_ pin.
- A firmware watchdog protects against the _CSFB_ pin becoming shorted to _GND_ . The protection triggers if the sampled _CSFB_ voltage is less than 97.6 mV for longer than the blanking time of _t_ softstart.
- A firmware state monitor supervises correct operation of the flyback in _**QRM1**_ , _**DCM**_ or _**ABM**_ . A protection is triggered if the flyback enters _**CCM**_ .
- A firmware plausibility check ensures that both bus voltage measurements using the _ZCD_ and _VS_ pins are consistent.
- A firmware watchdog supervises correct data handling of the flyback.
## **3.2.3.6.1 Flyback Bus Voltage Sensing**
The _**FB**_ can sense the bus voltage using the reflection of bus voltage on the auxiliary winding while the gate is turned on. A resistor divider adapts the negative voltage to the operating range of the _ZCD_ pin. This second measurement path is required to protect against component failures in the _VS_ measurement path (open loop protection for the _**PFC**_ stage).
The reflected bus voltage appears as a negative voltage at _V_ AUX. This negative voltage is internally clamped at the _ZCD_ pin to the negative voltage _V_ INPCLN. The internal clamping current _I_ ZCD is measured at the end of the ontime at the time _t_ CS,sample. The measured clamping current of the _ZCD_ pin, the dimensioning of the resistor dividers _R_ ZCD,FB,1 and _R_ ZCD,FB,2 as well as the number of transformer turns _N_ a and _N_ p are used to calculate the bus voltage _V_ bus,FB as follows:
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## **Equation 12**
_V_ bus,FB is used for a plausibility check with the bus voltage _V_ bus as measured using the _VS_ pin.
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Na Np<br>RZCD,FB,1 Vbus,FB<br>IZCD<br>ZCD<br>VINPCLN RZCD,FB,2<br>**----- End of picture text -----**<br>
## **Figure 24**
**Bus Voltage Sensing using ZCD Clamp Current**
Data Sheet
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**XDPL8221 Digital PFC+Flyback Controller IC XDP[™] Digital Power**
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## **Functional Description**
## **3.3 General Controller Features**
XDPL8221 provides general features using device level measurements (DLM) for firmware task scheduling, VCC control and temperature control which are independent of the target application.
## **3.3.1 Configurable Gate Driver Strengths**
The gate driver output signals can be configured with respect to their rising slopes for switching on the power MOSFET and with respect to their high voltage levels.
This feature can save BOM components (1 diode & 1 resistor per gate driver) which are conventionally added to achieve the same purpose to lower any _**Electro-Magnetic Interference (EMI)**_ .
## **3.3.2 External Temperature Sensing**
The external temperature is measured by measuring the voltage of an _**NTC**_ with respect to the internal _V_ REF voltage.
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Controller<br>VREF<br>RPU<br>TEMP<br>VTEMP RNTC<br>**----- End of picture text -----**<br>
## **Figure 25**
## **External Temperature Sensing using NTC**
The controller calculates the resistance of the _**NTC**_ based on the measured voltage _V_ Temp, the internal reference voltage _V_ REF and the internal pull-up resistance _R_ PU:
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## **Equation 13**
## **3.3.3 Adaptive temperature protection**
XDPL8221 offers adaptive temperature protection using the external temperature sensor. This feature reduces the output current according to temperature to protect the load and/or driver against overtemperature.
As long as the resistance of the NTC is lower than the temperature threshold _R_ NTC,hot of the NTC, the current is gradually reduced from the maximum current _I_ out,set, as shown in _**Figure 26**_ . If the resistance of the NTC is higher than threshold _R_ NTC,hot, the output current is gradually increased again. This allows the controller to ensure operation at or below a temperature matching to _R_ NTC,hot.
If a reduction down to a minimum current _I_ out,red is not able to compensate for any continued increase in temperature (causing a continuing reduction of NTC resistance), XDPL8221 will trigger external overtemperature protection if the external sensor exceeds _R_ NTC,critical.
Data Sheet
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**XDPL8221 Digital PFC+Flyback Controller IC XDP[™] Digital Power**
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## **Functional Description**
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Temperature reduced Temperature reduced<br>output current output current<br>Iout,full Iout,full<br>Iout,red Iout,red<br>R≥ RNTC,hot R<RNTC,hot R=RNTC,hot R≥ RNTC,hot R=RNTC,hot<br>NTC<br>Time<br>RNTC,hot resistance<br>RNTC,critical<br>**----- End of picture text -----**<br>
## **Figure 26 Adaptive temperature protection for external sensors**
## **3.3.4 PWM Dimming Interface**
The duty cycle sensed at the _PWM_ pin is used to determine the output current level. The XDPL8221 can be configured to use either a linear or a quadratic dimming curve. Either normal or inverted dimming curves can be selected.
_**Figure 27**_ shows the relationship of the _**PWM**_ duty cycle to the output current target value. Configurable levels _D_ DIM,min and _D_ DIM,max ensure that the minimum current _I_ out,min and maximum current _I_ out,set can always be achieved, thereby making the application robust against component tolerances. The dimming curve can be mirrored by changing its direction from normal to inverted _**PWM**_ duty cycle.
An optional hysteresis can be enabled for the sensing of the _**PWM**_ signal. This hysteresis can suppress jitter in the _**PWM**_ signal. Any change of the _**PWM**_ duty cycle within the hysteresis will not affect the output current.
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**----- Start of picture text -----**<br>
Output current Output current<br>Constant Constant<br>Iout,set Iout,set<br>current current<br>Limited Limited<br>power power<br>Iout,min Iout,min<br>PWM duty cycle PWM duty cycle<br>DDIM,off DDIM,min DDIM,max DDIM,off DDIM,min DDIM,max<br>DDIM,on DDIM,on<br>**----- End of picture text -----**<br>
## **Figure 27 Selectable Dimming Curves**
Using the optional Dim-to-Off feature, the light output can be stopped without removal of input voltage. In Dimto-Off, the controller will enter auto-restart operation to minimize power consumption. The auto-restart recharges the output voltage to a minimum output voltage of _V_ out,start to measure the _**PWM**_ duty cycle during a time of _t_ blank,DIM,off. After _t_ blank,DIM,off, the controller decides if it stays in Dim-to-off by triggering an auto-restart or if it starts the control loop. With the Dim-to-Off feature, the output voltage can be maintained in a specific range by configuration of the startup voltage _V_ out,start and auto-restart time _t_ AR, and by dimensioning of an active or passive output bleeder. If _V_ out,start is configured to be low enough below the minimum forward voltage of the _**LED**_ string, the _**LED**_ s will show no light in this state.
_Note: A sufficient output bleeder is required to allow the controller to maintain the output voltage if the Dim-to-Off feature is enabled._
Dim-to-Off is entered if the _**PWM**_ duty cycle exceeds the configurable threshold _D_ DIM,off (see purple line in _**Figure 27**_ ). As soon as the duty cycle exceeds _D_ DIM,on, the controller will start to continuously regulate output voltage or output current again.
Data Sheet
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**XDPL8221 Digital PFC+Flyback Controller IC XDP[™] Digital Power**
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## **Functional Description**
In case the product of output current and output voltage would exceed the power limit, the controller will automatically enter the _**LP**_ mode by reducing the output current to achieve the configured power limit (see light blue curve in _**Figure 27**_ ). As a consequence, the dimmer may show extended dead travel at the highest output level. When dimming down, as soon as the product of dimmed output current and output voltage drops below the power limit, the output current will follow the regular dimming curve (green curve).
## **3.3.5 UART Command Interface**
The _**UART**_ command interface allows to control the operation of the _**LED**_ driver as well as reading out status information from the controller. The electrical _**UART**_ interface and the protocol are described.
XDPL8221 uses a common half-duplex _**UART**_ interface with a baudrate of 57.600 baud. In half-duplex mode, both communication partners share one line to exchange data with a wired-AND structure. Therefore, both data transmit outputs (driver type: open-drain) are connected together to a common pull-up resistor to maximum 3.3 V. The value of the resistor define the rise time of the data signal at a 0-1 transition. The data receivers are connected to the same line and are always active to detect data collision. Each device also reads the data it is currently transmitting and checks the read data against the data that was intended to be written. In case of a mismatch, a data collision has occurred.
The _**UART**_ communication is based on data bytes with 8 bit width, LSB first as shown in _**Figure 28**_ . Each data transfer starts with a start bit at low level and stops with two stop bits at high level (STOP). The idle level of the transmit and receive signals is the high level.
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**----- Start of picture text -----**<br>
Start D0 D1 D2 D3 D4 D5 D6 D7 Stop<br>**----- End of picture text -----**<br>
## **Figure 28**
## **UART Byte Frame**
Before a command is send, sending one or multiple SYNC commands (0x7F) is recommended. If a _**UART**_ sync request occurs during a power saving state, the XDPL8221 will first recharge it's _VCC_ voltage before responding with an ACK (0x00). After the XDPL8221 answered one or more sync requests with ACK, the external master can send subsequent GET or SET commands. The _**UART**_ communication has to finish within a configurable timeout, otherwise a _VCC_ undervoltage can occur.
In case _**UART**_ communication is requested while the XDPL8221 is in power-saving state, a SYNC command will trigger a wakeup. In preparation of the communication, the XDPL8221 will first charge up the _VCC_ . This ensures a wakeup with full _VCC_ to be ready for communication. The XDPL8221 will be available for communication for a timeout of tUART which can be adjusted based on the _VCC_ capacitance. After the timeout, the XDPL8221 will continue with the protection reaction which was interrupted by the communication.
_Note: The_ _**UART** line is pulled low for typically 500 µs during an auto-restart of the XDPL8221. This must not be misinterpret as_ _**UART** frame error by other_ _**UART** devices._
A GET or SET command frame consists of 9 bytes as listed in _**Table 2**_ . The time between each byte must not exceed tUART,intra-byte. The checksum at the end of the command ensures that XDPL8221 does not react to any disturbed communication. The checksum is the XOR combination of the previous bytes of the command.
|A GET or SET command frame consists of 9 bytes as listed in**_Table 2_**. The time between each byte must not<br>exceed tUART,intra-byte. The checksum at the end of the command ensures that XDPL8221 does not react to any<br>disturbed communication. The checksum is the XOR combination of the previous bytes of the command.|A GET or SET command frame consists of 9 bytes as listed in**_Table 2_**. The time between each byte must not<br>exceed tUART,intra-byte. The checksum at the end of the command ensures that XDPL8221 does not react to any<br>disturbed communication. The checksum is the XOR combination of the previous bytes of the command.|A GET or SET command frame consists of 9 bytes as listed in**_Table 2_**. The time between each byte must not<br>exceed tUART,intra-byte. The checksum at the end of the command ensures that XDPL8221 does not react to any<br>disturbed communication. The checksum is the XOR combination of the previous bytes of the command.|A GET or SET command frame consists of 9 bytes as listed in**_Table 2_**. The time between each byte must not<br>exceed tUART,intra-byte. The checksum at the end of the command ensures that XDPL8221 does not react to any<br>disturbed communication. The checksum is the XOR combination of the previous bytes of the command.|A GET or SET command frame consists of 9 bytes as listed in**_Table 2_**. The time between each byte must not<br>exceed tUART,intra-byte. The checksum at the end of the command ensures that XDPL8221 does not react to any<br>disturbed communication. The checksum is the XOR combination of the previous bytes of the command.|A GET or SET command frame consists of 9 bytes as listed in**_Table 2_**. The time between each byte must not<br>exceed tUART,intra-byte. The checksum at the end of the command ensures that XDPL8221 does not react to any<br>disturbed communication. The checksum is the XOR combination of the previous bytes of the command.|A GET or SET command frame consists of 9 bytes as listed in**_Table 2_**. The time between each byte must not<br>exceed tUART,intra-byte. The checksum at the end of the command ensures that XDPL8221 does not react to any<br>disturbed communication. The checksum is the XOR combination of the previous bytes of the command.|A GET or SET command frame consists of 9 bytes as listed in**_Table 2_**. The time between each byte must not<br>exceed tUART,intra-byte. The checksum at the end of the command ensures that XDPL8221 does not react to any<br>disturbed communication. The checksum is the XOR combination of the previous bytes of the command.|A GET or SET command frame consists of 9 bytes as listed in**_Table 2_**. The time between each byte must not<br>exceed tUART,intra-byte. The checksum at the end of the command ensures that XDPL8221 does not react to any<br>disturbed communication. The checksum is the XOR combination of the previous bytes of the command.|A GET or SET command frame consists of 9 bytes as listed in**_Table 2_**. The time between each byte must not<br>exceed tUART,intra-byte. The checksum at the end of the command ensures that XDPL8221 does not react to any<br>disturbed communication. The checksum is the XOR combination of the previous bytes of the command.|
|---|---|---|---|---|---|---|---|---|---|
|**Table 2**<br>**UART Commands**||||||||||
|**Command**|**Class**|**Comm**<br>**and**|**ARG0**|**ARG1**|**ARG2**|**ARG3**|**ARG4**|**ARG5**|**Check**<br>**sum**|
|SYNC|0x7F|-|-|-|-|-|-|-|-|
|GET status|0x7C|0x04|0x41|ID|0x00|0x00|0x00|0x00|0xXX|
|GET internal temperature|0x7C|0x04|0x44|ID|0x00|0x00|0x00|0x00|0xXX|
|GET external NTC resistance|0x7C|0x04|0x45|ID|0x00|0x00|0x00|0x00|0xXX|
Data Sheet
Revision 1.1 2018-10-31
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**XDPL8221 Digital PFC+Flyback Controller IC XDP[™] Digital Power**
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## **Functional Description**
|**Table 2**<br>**UART Commands (continued)**|**Table 2**<br>**UART Commands (continued)**|**Table 2**<br>**UART Commands (continued)**|**Table 2**<br>**UART Commands (continued)**|**Table 2**<br>**UART Commands (continued)**|**Table 2**<br>**UART Commands (continued)**|**Table 2**<br>**UART Commands (continued)**|**Table 2**<br>**UART Commands (continued)**|**Table 2**<br>**UART Commands (continued)**|**Table 2**<br>**UART Commands (continued)**|
|---|---|---|---|---|---|---|---|---|---|
|**Command**|**Class**|**Comm**<br>**and**|**ARG0**|**ARG1**|**ARG2**|**ARG3**|**ARG4**|**ARG5**|**Check**<br>**sum**|
|GET output voltage|0x7C|0x04|0x64|ID|0x00|0x00|0x00|0x00|0xXX|
|GET RMS input voltage|0x7C|0x04|0x65|ID|0x00|0x00|0x00|0x00|0xXX|
|GET bus voltage|0x7C|0x04|0x66|ID|0x00|0x00|0x00|0x00|0xXX|
|GET output current|0x7C|0x04|0x6A|ID|0x00|0x00|0x00|0x00|0xXX|
|SET non-dimmed current|0x7C|0x84|0x68|ID|Current||0x00|0x00|0xXX|
|GET non-dimmed current|0x7C|0x04|0x68|ID|0x00|0x00|0x00|0x00|0xXX|
|SET dimming level|0x7C|0x84|0x84|ID|Dimming Level||0x00|0x00|0xXX|
|GET dimming level|0x7C|0x04|0x84|ID|0x00|0x00|0x00|0x00|0xXX|
|START|0x7C|0x00|0x00|0x00|0x00|0x00|0x00|0x00|0x7C|
|STOP**_1)_**|0x7C|0x01|0x00|0x00|0x00|0x00|0x00|0x00|0x7D|
|SET sleep**_2)_**|0x7C|0x84|0x4F|0x00|0x00|0x00|0x00|0x00|0xB7|
Restrictions apply to the non-dimmed current which can be set via _**UART**_ SET command:
- _I_ out,min < current set via _**UART**_ < _I_ out,full: This is the normal operation range. The current will be regulated according to the _**UART**_ command.
- Current set via _**UART**_ > _I_ out,full: This case would overload the design. The controller will limit the output current to _I_ out,full.
- Current set via _**UART**_ < _I_ out,min:
- This configuration is not allowed as it causes an invalid dimming curve. The _**UART**_ master must not program a current in this range.
A response frame can consist of either 1 byte or 9 bytes. As the power stage is a noisy environment, the _**UART**_ communication may occasionally be disturbed. In case of a mismatching checksum of the request or an incomplete frame, XDPL8221 will not provide any response. If a response to a command is missing, the _**UART**_ master must not send any new request within tUART,error.
|<br>communication may occasionally be disturbed. In case of a mismatching checksum of the request or an<br>incomplete frame, XDPL8221 will not provide any response. If a response to a command is missing, the**_UART_**<br>master must not send any new request within tUART,error.|<br>communication may occasionally be disturbed. In case of a mismatching checksum of the request or an<br>incomplete frame, XDPL8221 will not provide any response. If a response to a command is missing, the**_UART_**<br>master must not send any new request within tUART,error.|<br>communication may occasionally be disturbed. In case of a mismatching checksum of the request or an<br>incomplete frame, XDPL8221 will not provide any response. If a response to a command is missing, the**_UART_**<br>master must not send any new request within tUART,error.|<br>communication may occasionally be disturbed. In case of a mismatching checksum of the request or an<br>incomplete frame, XDPL8221 will not provide any response. If a response to a command is missing, the**_UART_**<br>master must not send any new request within tUART,error.|<br>communication may occasionally be disturbed. In case of a mismatching checksum of the request or an<br>incomplete frame, XDPL8221 will not provide any response. If a response to a command is missing, the**_UART_**<br>master must not send any new request within tUART,error.|<br>communication may occasionally be disturbed. In case of a mismatching checksum of the request or an<br>incomplete frame, XDPL8221 will not provide any response. If a response to a command is missing, the**_UART_**<br>master must not send any new request within tUART,error.|<br>communication may occasionally be disturbed. In case of a mismatching checksum of the request or an<br>incomplete frame, XDPL8221 will not provide any response. If a response to a command is missing, the**_UART_**<br>master must not send any new request within tUART,error.|<br>communication may occasionally be disturbed. In case of a mismatching checksum of the request or an<br>incomplete frame, XDPL8221 will not provide any response. If a response to a command is missing, the**_UART_**<br>master must not send any new request within tUART,error.|<br>communication may occasionally be disturbed. In case of a mismatching checksum of the request or an<br>incomplete frame, XDPL8221 will not provide any response. If a response to a command is missing, the**_UART_**<br>master must not send any new request within tUART,error.|<br>communication may occasionally be disturbed. In case of a mismatching checksum of the request or an<br>incomplete frame, XDPL8221 will not provide any response. If a response to a command is missing, the**_UART_**<br>master must not send any new request within tUART,error.|
|---|---|---|---|---|---|---|---|---|---|
|**Table 3**<br>**UART responses to commands**||||||||||
|**Response**|**ACK/**<br>**NACK**|**ARG0**|**ARG1**|**ARG2**|**ARG3**|**ARG4**|**ARG5**|**ARG6**|**Check**<br>**sum**|
|Successful answer to SYNC or SET<br>command|0x00<br>(ACK)|-|-|-|-|-|-|-|-|
|Successful response to a GET<br>command|0x00<br>(ACK)|Value (see<br>coding below)||00|00|00|00|00|0xXX|
|Generic Error Code for general<br>protocol purposes or used as a<br>non-contextualized generic NACK|0x01|-|-|-|-|-|-|-|-|
|One of the arguments in the<br>given command is not valid|0x02|-|-|-|-|-|-|-|-|
|The command is not known|0x03|-|-|-|-|-|-|-|-|
- 1 This command requires external VCC supply. Without external VCC supply, a VCC undervoltage protection will occur.
> 2 To wakeup from sleep by UART, the "UART during Latch" feature needs to be enabled.
Data Sheet
Revision 1.1 2018-10-31
30
**XDPL8221 Digital PFC+Flyback Controller IC XDP[™] Digital Power**
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## **Functional Description**
The ID field allows to address one out of multiple XDPL8221s on a shared _**UART**_ bus. Only devices with a matching ID will react to a _**UART**_ command. Commands can use the broadcast ID 0x00 to address any XDPL8221 on a shared bus. A broadcast GET command will cause a collision on the shared bus in case multiple devices are connected. It is advised to use only GET commands with a device ID to ensure a response from a single, unique device.
## _Note: All IDs of any XDPL8221s on a shared_ _**UART** bus must be unique!_
The coding of the electrical values to their digital number representation is listed in _**Table 4**_ . For all 16 bit values the lower byte is transferred first.
|The coding of the electrical values to their digital number representation is listed in**_Table 4_**. For all 16 bit values<br>the lower byte is transferred first.|The coding of the electrical values to their digital number representation is listed in**_Table 4_**. For all 16 bit values<br>the lower byte is transferred first.|The coding of the electrical values to their digital number representation is listed in**_Table 4_**. For all 16 bit values<br>the lower byte is transferred first.|The coding of the electrical values to their digital number representation is listed in**_Table 4_**. For all 16 bit values<br>the lower byte is transferred first.|The coding of the electrical values to their digital number representation is listed in**_Table 4_**. For all 16 bit values<br>the lower byte is transferred first.|
|---|---|---|---|---|
|**Table 4**<br>**Number Representation of Values**|||||
|**Value**|**Conversion Factor**|**Ofset**|**Minimum decimal**<br>**value**|**Maximum decimal**<br>**value**|
|Current|4096 LSB / A|0|1 (≡244 µA)|40960 (≡10 A)|
|Dimming Level|81.92 LSB / %|0|0 (≡0 %**_3)_**)|8192 (≡100%)|
|Voltage|16 LSB / V|0|1 (≡62.5 mV)|8000 (≡500 V)|
|NTC resistance|1 LSB / Ω|0|0 (≡0 Ω)|32768 (≡32.768 kΩ)|
|Temperature|1 LSB / °C|40|0 (≡-40°C)|190 (≡150°C)|
The status value of the controller answered to a "GET status" command is coded as listed in _**Table 5**_ .
|The status value of the controller answered to a "GET status" command is coded as listed in**_Table 5_**.|The status value of the controller answered to a "GET status" command is coded as listed in**_Table 5_**.|
|---|---|
|**Table 5**<br>**Coding of Status**||
|**Bit**|**Description**|
|15 to 14|The output current is determined by:<br>•<br>00: Dimming<br>•<br>01: Advanced temperature protection<br>•<br>10: Limited power|
|13|The flyback regulates in<br>•<br>0: CC or Limited Power mode<br>•<br>1: CV mode|
|12|The dimming level is determined by:<br>•<br>0: PWM<br>•<br>1: UART|
|11|AC or DC input voltage:<br>•<br>0: AC input voltage<br>•<br>1: DC input voltage|
|10 to 9|Current protection reaction is<br>•<br>00: Auto-restart<br>•<br>01: Fast Auto-restart<br>•<br>10: Latch<br>•<br>11: Stop Mode|
|8|The on-going protection requires a VCC charging for the restart (1) or not (0)|
|7|A protection reaction is on-going (1) or not (0)|
> 3 A UART dimming level of 0% triggers dim-to-off if it is enabled.
Data Sheet
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**XDPL8221 Digital PFC+Flyback Controller IC XDP[™] Digital Power**
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## **Functional Description**
|**Table 5**<br>**Coding of Status (continued)**|**Table 5**<br>**Coding of Status (continued)**|
|---|---|
|**Bit**|**Description**|
|6|A DLM protection was triggered (_Protection_DLM> 0)|
|5|A FB protection was triggered (_Protection_FB> 0)|
|4|A PFC protection was triggered (_Protection_PFC> 0)|
|3 to 0|Bit number of any bit set in either_Protection_PFC,_Protection_FBor_Protection_DLM **_4)_**|
The coding of system protections indicated by the value of the lowest 7 bits (bit 0-6) in the _**Table 5**_ is given in the following table :
|The coding of system protections indicated by the value of the lowest 7 bits (bit 0-6) in the**_Table 5_**is given in the<br>following table :|The coding of system protections indicated by the value of the lowest 7 bits (bit 0-6) in the**_Table 5_**is given in the<br>following table :|
|---|---|
|**Table 6**<br>**Coding of System Protections**||
|**Value (bit 6-0)**|**System Protections**|
|000 0000|No Protection|
|001 0001|Bus Over-voltage Protection Level 2|
|001 0010|Input Under-voltage Protection|
|001 0011|Input Over-voltage Protection|
|001 0100|PFC CCM Protection|
|001 0101|PFC Sof-start Failure Protection|
|001 0110|Bus Under-voltage Protection|
|001 0111|PFC Over-current Protection Level 2|
|010 0000|Flyback CS Pin Short to GND Protection|
|010 0001|Flyback Output Under-voltage Protection at Start-up|
|010 0010|Flyback Output Under-voltage Protection during Operation|
|010 0011|Flyback Output Over-voltage Protection|
|010 0100|Flyback Output Over-current Protection|
|010 0101|Flyback Over-current Protection Level 2|
|010 0110|Flyback CCM Protection|
|010 0111|Flyback Maximum TOSCExceeding Protection|
|010 1000|Dim-to-of at Start-up|
|010 1001|Dim-to-of during Operation|
|010 1010|Flyback Output Over-power Protection|
|010 1011|Flyback VbusPlausibility Check Failure Protection|
|010 1100|Flyback Data Missing Protection|
|100 0000|External Over-Temperature Protection|
|100 0001|Internal Over-Temperature Protection|
|100 0010|Task scheduler protection|
|100 0011|VCC Under-voltage Lock Out Protection|
|100 0100|VCC Out of Range Protection|
> 4 This assumes only one bit will be set in all three signals at a time. If multiple bits would be present, only the first error found will be chosen.
Data Sheet
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**XDPL8221 Digital PFC+Flyback Controller IC XDP[™] Digital Power**
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## **Functional Description**
|**Table 6**<br>**Coding of System Protections (continued)**|**Table 6**<br>**Coding of System Protections (continued)**|
|---|---|
|**Value (bit 6-0)**|**System Protections**|
|100 0101|RAM Parity Error Protection|
|100 0110|Watch Dog Error Protection|
|100 0111|Clock Check Error Protection|
## **3.3.6**
## **Protection features**
Protections ensure the operation of the controller under restricted conditions. The protection monitoring signal(s) sampling rate, protection triggering condition(s) and protection reaction are described in this section.
_**Attention** :_ _**The sampled protection monitoring signal accuracy is subjective to the digital quantization, tolerances of components (including IC) and estimations with indirect sensing (e.g. input and output voltage estimations based on ZCD, CS pin signals), while the protection level triggering accuracy is subjective to the sampled signal accuracy, sampling delay, indirect sensing delay (e.g. reflected output voltage signal cannot be sensed by ZCD pin near AC input phase angle of 0° and 180°) and blanking time.**_
## **3.3.6.1 Overtemperature Protection**
Overtemperature protection initiates a shutdown once the critical temperature level Tcritical or the critical NTC resistance R is exceeded. NTC,critical
If the internal temperature sensor exceeds _T_ critical or the external resistance drops below RNTC,critical, XDPL8221 will trigger internal or external overtemperature protection.
**==> picture [213 x 105] intentionally omitted <==**
**----- Start of picture text -----**<br>
Output current<br>Iout,full<br>Temperature<br>Tstart Tcritical<br>**----- End of picture text -----**<br>
## **Figure 29 Temperature protection**
If the controller is configured to react with auto-restart to internal or external overtemperature protection, it will only restart after the temperature drops below _T_ start and the NTC resistance exceeds _R_ NTC,hot. If latch mode is selected instead, the IC will turn off and only restart after recycling of input power with a temperature below Tcritical.
_Note: Please note that the internal temperature sensor can only protect external components which have sufficient thermal coupling to XDPL8221. The external temperature sensor can be used to protect the temperature of external components (e.g. transformer, power MOSFETs or linear regulators)._
## **3.3.6.2 VCC Undervoltage Lockout**
A _**Undervoltage Lockout (UVLO)**_ is implemented in hardware. It ensures defined enabling and disabling of the _**IC**_ operation depending on the supply voltage _V_ VCC at the _VCC_ pin in accordance with defined thresholds.
The _**UVLO**_ contains a hysteresis with the voltage thresholds _V_ VCCon for enabling the controller and _V_ UVoff for disabling the controller. Once the mains input voltage is applied, current flows through an external resistor into the _HV_ pin via the integrated depletion cell and diode to the _VCC_ pin. The controller is enabled once _V_ VCC
Data Sheet
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**XDPL8221 Digital PFC+Flyback Controller IC XDP[™] Digital Power**
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## **Functional Description**
exceeds the threshold _V_ VCCon and enters normal operation if no fault condition is detected. In this phase, _V_ VCC will drop until either external supply or the self-supply via the auxiliary winding takes over the supply at the _VCC_ pin.
_Note: The self-supply via the auxiliary winding must be in place before V_ VCC _falls below the V_ UVoff _threshold. Otherwise, the system will perform a fast restart._
_Note: It is possible to supply VCC externally from an auxiliary power supply. In this case, the VCC also needs initially to ramp to V_ VCCon _to enable the IC._
## **3.3.6.3 VCC Overvoltage Protection**
Overvoltage protection ensures that the voltage at the VCC pin is not exceeded.
The VCC voltage is compared to a configurable overvoltage protection threshold VVCC,OV. If the threshold is exceeded for longer than the blanking time tblank,VCC, the protection will be triggered.
_Note: The reaction to this protection is fixed to stop mode to ensure a discharge of VCC._
## **3.3.6.4 VCC Undervoltage Protection**
The _VCC_ voltage is compared to a configurable undervoltage protection threshold _V_ VCC,UV. If the threshold is exceeded for longer than the blanking time _t_ blank,VCC, the protection will be triggered.
## **3.3.6.5 Other General Controller Protections**
XDPL8221 includes several protections to ensure the integrity and correct flow of the firmware.
- A hardware watchdog checks correct execution of firmware. A protection is triggered in the event that the firmware does not service the watchdog within a defined period.
- A hardware _**Random Access Memory (RAM)**_ parity check triggers a protection if a bit in the memory changes unintentionally.
- A hardware clock check watchdog checks that no clock oscillator is failing.
- A firmware _**Cyclic Redundancy Check (CRC)**_ at each startup verifies the integrity of firmware code and its parameters.
- A firmware task execution watchdog triggers a protection if the firmware tasks are not executed as expected.
## **3.3.7**
## **Protection Reactions**
The reaction to each protection can be separately selected. Available reactions may include auto restart, fast auto restart, latch or stop mode.
_**Figure 30**_ depicts the timing of an auto-restart reaction:
**1.** If a protection threshold is exceeded for longer than the related blanking time _t_ blank, the protection is triggered.
**2.** Within a maximum _t_ 1 = 4 * 40 µs, the gate driver of the power stage related to the protection is disabled.
**3.** Within a maximum _t_ 2 = 4 * 40 µs, the gate drivers of other stages are disabled.
**4.** The reaction depends on the configuration of the protection:
- In case of latch mode, the application will enter latch mode at this time. No further steps are done, the reaction ends here.
- In case of stop mode, the application will stop and enter UART parametrization mode which allows to read out the error code. No further steps are done, the reaction ends here.
- In case of a (fast) auto-restart reaction, the controller will enter a power saving mode for the autorestart time _t_ AR or _t_ AR,fast respectively.
Data Sheet
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**XDPL8221 Digital PFC+Flyback Controller IC XDP[™] Digital Power**
**==> picture [105 x 47] intentionally omitted <==**
## **Functional Description**
**5.** The auto restart may include a new _VCC_ charging cycle. The time _t_ 3 typically depends on the input voltage.
**6.** The first power stage will enable its gate driver according to its startup sequence (soft start) again.
**7.** The second power stage will enable its gate driver according to its startup sequence (soft start) again. The startup of a subsequent power stage may be delayed by a time t4 depending on any startup condition for the subsequent stage.
**==> picture [426 x 290] intentionally omitted <==**
**----- Start of picture text -----**<br>
Threshold is exceeded<br>Protection is triggered<br>Related gate driver is disabled<br>Other gate drivers are disabled<br>Startup, charging of VCC<br>Restart of the first stage<br>Value Restart of the second stage<br>Threshold<br>Other gate driver<br>Related gate driver<br>Time<br>tblank t1 t2 tAR t3 t4<br>**----- End of picture text -----**<br>
## **Figure 30 Protection Reaction for auto-restart**
For some failures the system may eventually not be able to recover. These failures include:
- PFC OVP2
- PFC OCP2
- Bus voltage plausibility check
- Flyback _CSFB_ short to _GND_
- Flyback OCP2
- Flyback oscillation period too long
- Flyback CCM protection
- Flyback output overcurrent protection
- RAM parity
- Watchdog
- Clock check protection
- _VCC_ out-of-range protection
- Task Execution protection
For these cases, the controller features a limitation of auto-restarts. The controller will only restart a limited number of times _N_ AR,max. Afterward, the controller will latch. The counter for the limited number of restarts is reset whenever a restart due to a protection without limitation occurs.
Data Sheet
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**XDPL8221 Digital PFC+Flyback Controller IC XDP[™] Digital Power**
**==> picture [105 x 47] intentionally omitted <==**
## **Functional Description**
## **3.3.7.1 Auto restart**
When auto restart mode is activated, XDPL8221 stops switching at the GD pins. After a configurable auto restart time tAR, XDPL8221 initiates a new startup including recharging of VCC and a soft start.
During the time in which the gate is not switching, the internal HV startup cell is automatically enabled and disabled to keep the VCC voltage between the VUVLO and VOVLO thresholds for the supply of XDPL8221. Due to the recharging of VCC for a restart, the time between stopping and starting gate driver pulses is longer than tAR.
## **3.3.7.2 Fast Auto Restart**
When fast auto restart mode is activated, XDPL8221 stops switching at the GD pins. After a configurable fast auto restart time tAR,fast, XDPL8221 initiates a new startup including recharging of VCC and a soft start. During the time in which the gate is not switching, the internal HV startup cell is automatically enabled and disabled to keep the VCC voltage between the VUVLO and VOVLO thresholds for the supply of XDPL8221. Due to the recharging of VCC for a restart, the time between stopping and starting gate driver pulses is longer than tAR,fast.
## **3.3.7.3 Latch Mode**
When latch mode is activated, XDPL8221 stops switching at the GD pins. The device stays in this state until input voltage is completely removed and the VCC voltage drops below the VUVLO threshold. Only then can XDPL8221 be restarted by applying input voltage.
To maintain this state, the internal HV startup cell is automatically enabled and disabled to keep the VCC voltage between the VUVLO and VOVLO thresholds for the supply of XDPL8221. The current consumption is reduced to a minimum.
## **3.3.7.4**
## **Stop Mode**
When stop mode is activated, XDPL8221 stops switching at the GD pins. XDPL8221 enters _**UART**_ communication mode to allow debugging of the system state.
_Note: The VCC for XDPL8221 needs to be supplied by an external source. Without an external supply, VCC will drain to V_ UVLO _and XDPL8221 performs a restart._
Data Sheet
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**XDPL8221 Digital PFC+Flyback Controller IC XDP[™] Digital Power**
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## **Electrical Characteristics and Parameters**
## **4 Electrical Characteristics and Parameters**
All signals are measured with respect to the ground pin, GND. The voltage levels are valid provided other ratings are not violated.
## **4.1 Package Characteristics**
**Table 7**
## **Package Characteristics**
|**Parameter**|**Symbol**|**Limit Values**|**Limit Values**|**Unit**|**Remarks**|
|---|---|---|---|---|---|
|||**min**|**max**|||
|Thermal resistance for PG-<br>DSO-16|RthJA|—|119|K/W||
## **4.2**
## **Absolute Maximum Ratings**
_**Attention** :_ _**Stresses above the values listed below may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. These values are not tested during production test.**_
## **Table 8**
## **Absolute Maximum Ratings**
|**Parameter**|**Symbol**|**Limit Values**|**Limit Values**|**Unit**|**Remarks**|
|---|---|---|---|---|---|
|||**min**|**max**|||
|Voltage externally supplied<br>to pin VCC|VVCCEXT|–0.5|26|V|voltage that can be applied<br>to pin VCC by an external<br>voltage source|
|Voltage at pin GDx|VGDx|–0.5|VVCC+ 0.3|V|if gate driver is not<br>configured for digital I/O|
|Junction temperature|TJ|–40|125|°C|max. operating frequency<br>66 MHz fMCLK|
|Storage temperature|TS|–55|150|°C||
|Soldering temperature|TSOLD|—|260|°C|Wave Soldering**_5)_**|
|Latch-up capability|ILU|—|150|mA|**_6)_**Pin voltages acc. to abs.<br>max. ratings|
|ESD capability HBM|VHBM|—|2000|V|**_7)_**|
|ESD capability CDM|VCDM|—|500|V|**_8)_**|
|Input Voltage Limit|VIN|–0.5|3.6|V|Voltage externally supplied<br>to pins GPIO, MFIO, CS, ZCD,<br>GPIO, VS, GDx (if GDx is<br>configured as digital I/O). (If<br>not stated diferent)|
> 5 According to JESD22-A111 Rev A.
> 6 Latch-up capability according to JEDEC JESD78D, TA= 85°C.
> 7 ESD-HBM according to ANSI/ESDA/JEDEC JS-001-2012.
- 8 ESD-CDM according to JESD22-C101F.
Data Sheet
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## **Electrical Characteristics and Parameters**
|**Table 8**<br>**Absolute Maximum Ratings (continued)**|**Table 8**<br>**Absolute Maximum Ratings (continued)**|**Table 8**<br>**Absolute Maximum Ratings (continued)**|**Table 8**<br>**Absolute Maximum Ratings (continued)**|**Table 8**<br>**Absolute Maximum Ratings (continued)**|**Table 8**<br>**Absolute Maximum Ratings (continued)**|
|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Limit Values**||**Unit**|**Remarks**|
|||**min**|**max**|||
|Maximum permanent<br>negative clamping current<br>for ZCD and CS|–ICLN_DC|—|2.5|mA|RMS|
|Maximum transient negative<br>clamping current for ZCD<br>and CS|–ICLN_TR|—|10|mA|pulse < 500ns|
|Maximum negative transient<br>input voltage for ZCD|–VIN_ZCD|—|1.5|V|pulse < 500ns|
|Maximum negative transient<br>input voltage for CS|–VIN_CS|—|3.0|V|pulse < 500ns|
|Maximum permanent<br>positive clamping current for<br>CS|ICLP_DC|—|2.5|mA|RMS|
|Maximum transient positive<br>clamping current for CS|ICLP_TR|—|10|mA|pulse < 500ns|
|Maximum current into pin<br>VIN|IAC|—|10|mA|for charging operation|
|Maximum sum of input<br>clamping high currents for<br>digital input stages of device|ICLH_sum|—|300|µA|limits for each individual<br>digital input stage have to<br>be respected|
|Voltage at HV pin|VHV|-0.5|600|V||
## **4.3 Operating Conditions**
The recommended operating conditions are shown for which the DC Electrical Characteristics are valid.
|**Table 9**<br>**Operating Range**|**Table 9**<br>**Operating Range**|||||
|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Limit Values**||**Unit**|**Remarks**|
|||**min**|**max**|||
|Junction Temperature|TJ|–40|125|°C|max. 66 MHz fMCLK|
|Lower VCC limit|VVCC|VUVOFF|—|V|device is held in reset when<br>VVCC< VUVOFF|
|Voltage externally supplied<br>to VCC pin|VVCCEXT|—|24|V|maximum voltage that can<br>be applied to pin VCC by an<br>external voltage source|
|Gate driver pin voltage|VGD|–0.5|VVCC+ 0.3|V||
## **4.4 DC Electrical Characteristics**
The electrical characteristics provide the spread of values applicable within the specified supply voltage and junction temperature range, TJ from -40 °C to +125 °C.
Devices are tested in production at TA = 25 °C. Values have been verified either with simulation models or by device characterization up to 125 °C.
Data Sheet
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## **Electrical Characteristics and Parameters**
Typical values represent the median values related to TA = 25 °C. All voltages refer to GND, and the assumed supply voltage is VVCC = 18 V if not otherwise specified.
_Note: Not all values given in the tables are tested during production testing. Values not tested are explicitly marked._
_**Attention** :_ _**The Vcc pin voltage must be higher than 3.4V before the voltage of any other pins (except GND and HV pins) exceeds 1.2V.**_
**Table 10 Power Supply Characteristics**
|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|VCC_ON threshold|VVCCon|—|VSELF|—|V|Self-powered startup<br>(default)|
|VCC_ON_SELF threshold|VSELF|19|20.5|22|V|dVVCC/dt = 0.2 V/ms|
|VCC_ON_SELF delay|tSELF|—|—|2.1|µs|Reaction time of VVCC<br>monitor|
|VCC_UVOFF current|IVCCUVOFF|5|20|40|µA|VVCC< VSELF(min) - 0.3 V<br>or VVCC< VEXT(min) -<br>0.3 V**_9)_**|
|UVOFF threshold|VUVOFF|—|6.0|—|V|SYS_CFG0.SELUVTHR = 0<br>0B|
|UVOFF threshold<br>tolerance|ΔUVOFF|—|—|±5|%|This value defines the<br>tolerance of VUVOFF|
|UVOFF filter constant|tUVOFF|600|—|—|ns|1V overdrive|
|UVLO (UVWAKE)<br>threshold|VUVLO|—|VUVOFF·<br>1.25|—|V||
|UVWAKE threshold<br>tolerance|ΔUVLO|—|—|±5|%|This value defines the<br>tolerance of VUVLO|
|UVLO (UVWAKE) filter<br>constant|tUVLO|0.6|—|2.2|µs|1 V overdrive|
|OVLO (OVWAKE)<br>threshold|VOVLO|—|VSELF|—|V||
|OVLO (OVWAKE) filter<br>constant|tOVLO|0.6|—|2.4|µs|1 V overdrive|
|Nominal range 0% to<br>100%|VADCVCC|0|—|VREF|V|VADCVCC= 0.09 · VVCC**_10)_**|
|Reduced VCC range for<br>ADC measurement|RADCVCC|8|—|92|%|**_11)12)_**|
- 9 Tested at VVCC = 5.5 V
> 10 Theoretical minimum value, real minimum value is related to VUVOFF threshold.
> 11 Operational values.
> 12 Note that the system is turned off if VVCC < VUFOFF.
Data Sheet
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## **Electrical Characteristics and Parameters**
|**Table 10**<br>**Power Supply Characteristics (continued)**|**Table 10**<br>**Power Supply Characteristics (continued)**|**Table 10**<br>**Power Supply Characteristics (continued)**|**Table 10**<br>**Power Supply Characteristics (continued)**|**Table 10**<br>**Power Supply Characteristics (continued)**|**Table 10**<br>**Power Supply Characteristics (continued)**|**Table 10**<br>**Power Supply Characteristics (continued)**|
|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Values**|||**Unit**|**Note or Test Condition**|
|||**Min.**|**Typ.**|**Max.**|||
|Maximum error for ADC<br>measurement (8-bit<br>result)|TET0VCC|—|—|3.8|LSB8||
|Maximum error for ADC<br>measurement (8-bit<br>result)|TET256VCC|—|—|5.2|LSB8||
|Gate driver current<br>consumption excl. gate<br>charge current|IVCCGD|—|0.26|0.35|mA|Tj≤ 125°C|
|VCC quiescent current in<br>PMD0|IVCCPMD0|—|11|13|mA|All registers have reset<br>values, clock is active at<br>66 MHz, CPU is stopped,<br>Tj≤ 85 °C|
|VCC quiescent current in<br>PMD0|IVCCPMD0|—|—|14.5|mA|All registers have reset<br>values, clock is active at<br>66 MHz, CPU is stopped,<br>Tj≤ 125 °C|
|VCC quiescent current in<br>power saving mode<br>PSDM3 with standby<br>logic active|IVCCPSMD3|—|0.25|0.45|mA|Tj≤ 125 °C<br>WU_PWD_CFG = 28H|
|VCC quiescent current in<br>power saving mode<br>PSDM4 with standby<br>logic active|IVCCPSMD4|—|0.14|0.23|mA|Tj≤ 125 °C<br>WU_PWD_CFG = 00H|
## **Table 11 Electrical Characteristics of the GDFB Pin**
|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|APD low voltage (active<br>pull-down while device is<br>not powered or gate<br>driver is not enabled)|VAPD|—|—|1.6|V|IGD= 5 mA|
|RPPDvalue|RPPD|—|600|—|kΩ|Permanent pull-down<br>resistor inside gate<br>driver|
|RPPDtolerance|ΔPPD|—|—|±25|%|Permanent pull-down<br>resistor inside gate<br>driver|
|Driver output low<br>impedance for GD0|RGDL|—|—|4.4|Ω|TJ≤ 125 °C, IGD= 0.1 A|
Data Sheet
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## **Electrical Characteristics and Parameters**
## **Table 11 Electrical Characteristics of the GDFB Pin (continued)**
|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|Nominal output high<br>voltage in PWM mode|VGDH|—|10.5|—|V|GDx_CFG.VOL = 3,<br>IGDH= –1 mA|
|Output voltage tolerance|ΔVGDH|—|—|±5|%|Tolerance of<br>programming options if<br>VGDH> 10 V, IGDH= –1 mA|
|Rail-to-rail output high<br>voltage|VGDHRR|VVCC– 0.5|—|VVCC|V|If VVCC< programmed<br>VGDHand output at high<br>state|
|Output high current in<br>PWM mode for GD0|–IGDH|—|100|—|mA|GDx_CFG.CUR = 8|
|Output high current<br>tolerance in PWM mode|ΔIGDH|—||±15|%|Calibrated**_13)_**|
|Discharge current for<br>GD0|IGDDIS|800|—|—|mA|VGD= 4 V and driver at<br>low state|
|Output low reverse<br>current|–IGDREVL|—|—|100|mA|Applies if VGD< 0 V and<br>driver at low state|
|Output high reverse<br>current in PWM mode|IGDREVH|—|1/6 of IGDH|—||Applies if<br>VGD> VGDH+ 0.5 V (typ)<br>and driver at high state|
## **Table 12 Electrical Characteristics of the CSFB Pin**
|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|Input voltage operating<br>range|VINP|–0.5|—|3.0|V||
|OCP2 comparator<br>reference voltage,<br>derived from VVDDA, given<br>values assuming<br>VVDDA= VVDDA,typ|VOCP2|—|1.6|—|V|SYS_CFG0.OCP2 = 00B|
|Threshold voltage<br>tolerance|ΔVOCP2|—|—|±5|%|Voltage divider tolerance|
|Comparator propagation<br>delay|tOCP2PD|15|—|35|ns||
|Minimum comparator<br>input pulse width|tOCP2PW|—|—|30|ns||
|OCP2F comparator<br>propagation delay|tOCP2FPD|70|—|170|ns|dVCS/dt = 100 V/µs|
> 13 referred to GDx_CFG.CUR = 16
Data Sheet
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## **Electrical Characteristics and Parameters**
|**Table 12**<br>**Electrical Characteristics of the CSFB Pin (continued)**|**Table 12**<br>**Electrical Characteristics of the CSFB Pin (continued)**|**Table 12**<br>**Electrical Characteristics of the CSFB Pin (continued)**|**Table 12**<br>**Electrical Characteristics of the CSFB Pin (continued)**|**Table 12**<br>**Electrical Characteristics of the CSFB Pin (continued)**|**Table 12**<br>**Electrical Characteristics of the CSFB Pin (continued)**|**Table 12**<br>**Electrical Characteristics of the CSFB Pin (continued)**|
|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Values**|||**Unit**|**Note or Test Condition**|
|||**Min.**|**Typ.**|**Max.**|||
|Delay from VCScrossing<br>VCSOCP2to begin of GDx<br>turn-of (IGD0> 2mA)|tCSGDxOCP2|125|135|190|ns|dVCS/dt = 100 V/µs;<br>fMCLK= 66 MHz. GDx<br>driven by QR_GATE<br>FIL_OCP2.STABLE = 3|
|OCP1 operating range|VOCP1|0|—|VREF/2|V|RANGE =00B|
|OCP1 threshold at full<br>scale setting<br>(CS_OCP1LVL=FFH) for<br>CS0|VOCP1FS|1192|1229|1266|mV|RANGE =00B|
|Delay from VCScrossing<br>VCSOCP1to CS_OCP1<br>rising edge, 1.2 V range|tCSOCP1|90|170|250|ns|Input signal slope dVCS/<br>dt = 150 mV/µs. This<br>slope represents a use<br>case of a switch-mode<br>power supply with<br>minimum input voltage.|
|Delay from CS_OCP1<br>rising edge to QR_GATE<br>falling edge|tOCP1GATE|—|—|12|ns|STB_RET31.<br>OCP_ASM_SEL=0|
|Delay from QR_GATE<br>falling edge to start of<br>GDx turn-of|tGATEGDx|1|3|5|ns|GDx driven by QR_GATE.<br>Measured up to<br>IGDx> 2 mA|
|OCP1 comparator input<br>single pulse width filter|tOCP1PW|60|—|95|ns|Shorter pulses than min.<br>are suppressed, longer<br>pulses than max. are<br>passed|
|Nominal S&H operating<br>range 0% to 100%|VCSH|0|—|VREF/2|V|CS_ICR.RANGE =00B|
|Reduced S&H operating<br>range|RRCVSH|8|—|92|%|CS_ICR.RANGE =00B<br>Operational values|
|Maximum error of CS0<br>S&H for corrected<br>measurement (8-bit<br>result)|TET0CS0S|—|—|4.7|LSB|CS_ICR.RANGE =00B|
|Maximum error of CS0<br>S&H for corrected<br>measurement (8-bit<br>result)|TET256CS0S|—|—|6.0|LSB|CS_ICR.RANGE =00B|
|Nominal S&H operating<br>range 0% to 100%|VCSH|0|—|VREF/6|V|CS_ICR.RANGE =11B|
|Reduced S&H operating<br>range|RRCVSH|20|—|80|%|CS_ICR.RANGE =11B<br>Operational values|
Data Sheet
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## **Electrical Characteristics and Parameters**
|**Table 12**<br>**Electrical Characteristics of the CSFB Pin (continued)**|**Table 12**<br>**Electrical Characteristics of the CSFB Pin (continued)**|**Table 12**<br>**Electrical Characteristics of the CSFB Pin (continued)**|**Table 12**<br>**Electrical Characteristics of the CSFB Pin (continued)**|**Table 12**<br>**Electrical Characteristics of the CSFB Pin (continued)**|**Table 12**<br>**Electrical Characteristics of the CSFB Pin (continued)**|**Table 12**<br>**Electrical Characteristics of the CSFB Pin (continued)**|
|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Values**|||**Unit**|**Note or Test Condition**|
|||**Min.**|**Typ.**|**Max.**|||
|Maximum error of CS0<br>S&H for corrected<br>measurement (8-bit<br>result)|TET0CS0S|—|—|8.0|LSB|CS_ICR.RANGE =11B|
|Maximum error of CS0<br>S&H for corrected<br>measurement (8-bit<br>result)|TET256CS0S|—|—|8.7|LSB|CS_ICR.RANGE =11B|
|S&H delay of input bufer|tCSHST|—|—|510|ns|Referring to jump in<br>input voltage. Limits the<br>minimum gate driver Ton<br>time.|
||||||||
|**Table 13**<br>**Electrical Characteristics of the ZCD Pin**|||||||
|**Parameter**|**Symbol**|**Values**|||**Unit**|**Note or Test Condition**|
|||**Min.**|**Typ.**|**Max.**|||
|Input voltage operating<br>range|VINP|–0.5|—|3.3|V||
|Input clamping current,<br>high|ICLH|—|—|100|µA||
|Zero-crossing threshold|VZCTHR|15|40|70|mV||
|Comparator propagation<br>delay|tZCPD|30|50|70|ns|dVZCD/dt = 4 V/µs|
|Input voltage negative<br>clamping level|–VINPCLN|140|180|220|mV|Analog clamp activated|
|Nominal I/V-conversion<br>operating range 0% to<br>100%|–IIV|0|—|4|mA|CRNG =00BGain = 600<br>mV/mA|
|Reduced I/V-conversion<br>operating range|RRIV|5|—|80|%||
|Maximum error for<br>corrected ADC<br>measurement (8-bit<br>result)|TET0IV|—|—|4.1|LSB8|CRNG =00B|
|Maximum error for<br>corrected ADC<br>measurement (8-bit<br>result)|TET256IV|—|—|9.7|LSB8|CRNG =00B|
Data Sheet
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## **Electrical Characteristics and Parameters**
## **Table 13 Electrical Characteristics of the ZCD Pin (continued)**
|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|Maximum deviation<br>between ZCD clamp<br>voltage and trim result<br>stored in OTP|EZCDClp|—|—|±5|%|–IIV> 0.25 mA|
|IV-conversion delay of<br>input bufer|tIVST|—|—|900|ns|Refers to jump in input<br>current**_14)_**|
|Nominal S&H input<br>voltage range 0% to<br>100%|VZSH|0|—|2/3 · VREF|V|SHRNG =0B|
|Nominal S&H input<br>voltage range 0% to<br>100%|VZSH|VREF/2|—|7/6 · VREF|V|SHRNG =1B|
|Reduced S&H input<br>voltage range|RRZVSH|4|—|95|%||
|Maximum error for<br>corrected ADC<br>measurement (8-bit<br>result)|TET0ZVS0|—|—|3.7|LSB8|SHRNG =0B|
|Maximum error for<br>corrected ADC<br>measurement (8-bit<br>result)|TET256ZVS0|—|—|4.9|LSB8|SHRNG =0B|
|Maximum error for<br>corrected ADC<br>measurement (8-bit<br>result)|TET0ZVS1|—|—|4.2|LSB8|SHRNG =1B|
|Maximum error for<br>corrected ADC<br>measurement (8-bit<br>result)|TET256ZVS1|—|—|5.8|LSB8|SHRNG =1B|
|S&H delay of input bufer<br>referring to jump of input<br>voltage|tZSHST|—|—|1.0|µs|SHRNG =0BTj≤ 125 °C|
|S&H delay of input bufer<br>referring to jump of input<br>voltage|tZSHST|—|—|1.6|µs|SHRNG =1BTj≤ 125 °C|
> 14 Limits the minimum gate driver Ton time.
Data Sheet
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## **Electrical Characteristics and Parameters**
## **Table 14 Electrical Characteristics of the VS Pin**
|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|Nominal measurement<br>range 0% to 100%|VVS|0|—|VREF|V|Gain 1, no ofset|
|Nominal measurement<br>range 0% to 100%|VVS|5/6·VREF|—|7/6·VREF|V|Gain 3, with ofset|
|Reduced operating range|RRVVS|5|—|95|%|Gain 1, no ofset|
|Reduced operating range|RRVVS|10|—|90|%|Gain 3, with ofset|
|Maximum error for<br>corrected measurement<br>(8-bit result)|TET0VS|—|—|4.1|LSB8|Range 1, no ofset|
|Maximum error for<br>corrected measurement<br>(8-bit result)|TET256VS|—|—|5.6|LSB8|Range 1, no ofset|
|Maximum error for<br>corrected measurement<br>(8-bit result)|TET0VS|—|—|12.0|LSB8|Range 2, with ofset|
|Maximum error for<br>corrected measurement<br>(8-bit result)|TET256VS|—|—|12.9|LSB8|Range 2, with ofset|
|Overvoltage comparator<br>threshold|THROV|2.70|2.8|2.90|V||
|Overvoltage comparator<br>propagation delay|tPDOV|—|—|300|µs|Step at input|
## **Table 15 Electrical Characteristics of the HV Pin**
|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|Leakage current at HV<br>pin|IHVleak|—|—|10|µA|VHV= 600 V HV startup<br>cell disabled|
|Nominal current for<br>measurement path 0% to<br>100%|IMEAS|0|—|9.6|mA|CURRNG = 11B|
|Reduced measurement<br>range for current path|RRIMEAS|5|—|78|%|CURRNG = 11B.<br>Operational values.|
|Maximum error for<br>corrected ADC<br>measurement (8-bit<br>result, temperature gain<br>correction applied)|TET0DP|—|—|5.7|LSB8|CURRNG = 11B|
Data Sheet
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## **Electrical Characteristics and Parameters**
## **Table 15 Electrical Characteristics of the HV Pin (continued)**
|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|Maximum error for<br>corrected ADC<br>measurement (8-bit<br>result, temperature gain<br>correction applied)|TET256DP|—|—|6.3|LSB8|CURRNG = 11B|
## **Table 16 Electrical Characteristics of the PWM Pin**
|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|Input capacitance|CINPUT|—|—|10|pF||
|Input low voltage|VIL|—|—|1.0|V||
|Input high voltage|VIH|2.0|—|—|V||
|Input leakage current, no<br>pull device|ILK|–5|—|+1|µA|VMFIO= 0 V / 3 V|
|Input low current with<br>active weak pull-up WPU|–ILPU|30|—|90|µA|Measured at max. VIL|
|Input high current with<br>active weak pull-down<br>WPD|IHPD|90|—|300|µA|Measured at min. VIH|
|Pull-up resistor value|RPU|—|2.25|—|kΩ|RPU=1111B|
|Pull-up resistor tolerance|ΔRPU|—|—|±20|%|Overall tolerance|
|PWM input frequency|fPWM|500|—|2000|Hz||
|PWM duty cycle|DPWM|5|—|95|%||
## **Table 17 Electrical Characteristics of the TEMP Pin**
|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|MFIO reference voltage|VMFIOREF|—|VREF|—|V|Selection = VREF|
|Nominal range 0% to<br>100%|VMFIO|0|—|VREF|V|Gain = 1|
|Reduced operating range|RRVMFIO|4|—|96|%|Gain = 1. Operational<br>values.|
|Maximum error for<br>corrected measurement<br>(8-bit result)|TET0MFI0|—|—|4.0|LSB8|Gain = 1|
|Maximum error for<br>corrected measurement<br>(8-bit result)|TET256MFI0|—|—|4.8|LSB8|Gain = 1|
Data Sheet
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## **Electrical Characteristics and Parameters**
|**Table 17**<br>**Electrical Characteristics of the TEMP Pin (continued)**|**Table 17**<br>**Electrical Characteristics of the TEMP Pin (continued)**|**Table 17**<br>**Electrical Characteristics of the TEMP Pin (continued)**|**Table 17**<br>**Electrical Characteristics of the TEMP Pin (continued)**|**Table 17**<br>**Electrical Characteristics of the TEMP Pin (continued)**|**Table 17**<br>**Electrical Characteristics of the TEMP Pin (continued)**|**Table 17**<br>**Electrical Characteristics of the TEMP Pin (continued)**|
|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Values**|||**Unit**|**Note or Test Condition**|
|||**Min.**|**Typ.**|**Max.**|||
|Ofset calibration voltage|VCAL|—|VMFIOREF/8|—|V||
|Ofset calibration voltage<br>absolute tolerance|ΔVCAL|—|—|±3|LSB|Ref. to VMFIOREF=VREF,<br>Gain = 1|
|Ofset calibration voltage<br>variation over<br>temperature|ΔVCAL_TMP|—|—|±1|LSB|Ref. to VMFIOREF=VREF,<br>Gain = 1|
|Pull-up resistor value|RPU|—|11|—|kΩ|RPU=0110B|
|Pull-up resistor tolerance|ΔRPU|—|—|±20|%|Overall tolerance|
## **Table 18 Electrical Characteristics of the CSPFC Pin**
|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|Input voltage operating<br>range|VINP|–0.5|—|3.0|V||
|OCP1 operating range|VOCP1|0|—|VREF/2|V|RANGE =00B|
|OCP2 comparator<br>reference voltage,<br>derived from VVDDA, given<br>values assuming<br>VVDDA= VVDDA,typ|VOCP2|—|1.6|—|V|SYS_CFG0.OCP2 = 00B|
|Threshold voltage<br>tolerance|ΔVOCP2|—|—|±5|%|Voltage divider tolerance|
|Comparator propagation<br>delay|tOCP2PD|15|—|35|ns||
|Minimum comparator<br>input pulse width|tOCP2PW|—|—|30|ns||
|OCP2F comparator<br>propagation delay|tOCP2FPD|70|—|170|ns|dVCS/dt = 100 V/µs|
|Delay from VCScrossing<br>VCSOCP2to begin of GDx<br>turn-of (IGD0> 2mA)|tCSGDxOCP2|125|135|190|ns|dVCS/dt = 100 V/µs;<br>fMCLK= 66 MHz. GDx<br>driven by QR_GATE<br>FIL_OCP2.STABLE = 3|
|Nominal S&H operating<br>range 0% to 100%|VCSH|0|—|VREF/2|V|CS_ICR.RANGE =00B|
|Reduced S&H operating<br>range|RRCVSH|4|—|90|%|Operational values|
|Hysteretic comparator<br>threshold|THRHYS|—|0.54|—|V|1 → 0 transition|
Data Sheet
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## **Electrical Characteristics and Parameters**
## **Table 18 Electrical Characteristics of the CSPFC Pin (continued)**
|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|Hysteretic comparator<br>threshold|THRHYS|—|1.53|—|V|0 → 1 transition|
|Hysteretic comparator<br>threshold tolerance|ΔTHRHYS|—|—|±120|mV||
|Hysteretic comparator<br>propagation delay|tPDHYS|—|90|—|ns|Rising edge|
|Hysteretic comparator<br>propagation delay|tPDHYS|—|40|—|ns|Falling edge|
|Hysteretic comparator<br>minimum input pulse<br>width|tPWHYS|—|—|300|ns||
|**Table 19**<br>**Electrical Characteristics of the UART Pin**|**Table 19**<br>**Electrical Characteristics of the UART Pin**|**Table 19**<br>**Electrical Characteristics of the UART Pin**|**Table 19**<br>**Electrical Characteristics of the UART Pin**|**Table 19**<br>**Electrical Characteristics of the UART Pin**|**Table 19**<br>**Electrical Characteristics of the UART Pin**|**Table 19**<br>**Electrical Characteristics of the UART Pin**|
|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Values**|||**Unit**|**Note or Test Condition**|
|||**Min.**|**Typ.**|**Max.**|||
|Input clamping current,<br>low|–ICLL|—|—|100|µA|only digital input|
|Input clamping current,<br>high|ICLH|—|—|100|µA|only digital input|
|APD low voltage (active<br>pull-down while device is<br>not powered or gate<br>driver is not enabled)|VAPD|—|—|1.6|V|IGD= 5 mA|
|Input capacitance|CINPUT|—|—|25|pF||
|Input low voltage|VIL|—|—|1.0|V||
|Input high voltage|VIH|2.1|—|—|V||
|Input low current with<br>active weak pull-up WPU|–ILPU|30|—|90|µA|Measured at max. VIL|
|UART baudrate|fUART|-5%|57600|+5%|baud||
|Time between bytes<br>within a UART frame|tUART,intra-<br>byte|—|—|500|µs||
|Waiting time afer a<br>missing response|tUART,error|15|—|—|ms||
Data Sheet
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## **Electrical Characteristics and Parameters**
## **Electrical Characteristics of the GDPFC Pin**
||||||||
|---|---|---|---|---|---|---|
|**Table 20**<br>**Electrical Characte**||**ristics of the GDPFC Pin**|||||
|**Parameter**|**Symbol**|**Values**|||**Unit**|**Note or Test Condition**|
|||**Min.**|**Typ.**|**Max.**|||
|APD low voltage (active<br>pull-down while device is<br>not powered or gate<br>driver is not enabled)|VAPD|—|—|1.6|V|IGD= 5 mA|
|RPPDvalue|RPPD|—|600|—|kΩ|Permanent pull-down<br>resistor inside gate<br>driver|
|RPPDtolerance|ΔPPD|—|—|±25|%|Permanent pull-down<br>resistor inside gate<br>driver|
|Driver output low<br>impedance for GD1/2|RGDL|—|—|7.0|Ω|TJ≤ 125 °C, IGD= 0.1 A|
|Nominal output high<br>voltage in PWM mode|VGDH|—|10.5|—|V|GDx_CFG.VOL = 3,<br>IGDH= –1 mA|
|Output voltage tolerance|ΔVGDH|—|—|±5|%|Tolerance of<br>programming options if<br>VGDH> 10 V, IGDH= –1 mA|
|Rail-to-rail output high<br>voltage|VGDHRR|VVCC– 0.5|—|VVCC|V|If VVCC< programmed<br>VGDHand output at high<br>state|
|Output high current in<br>PWM mode for GD1/2|–IGDH|—|104|—|mA|GDx_CFG.CUR = 24|
|Output high current<br>tolerance in PWM mode|ΔIGDH|—||±15|%|Calibrated**_15)_**|
|Discharge current for<br>GD1/2|IGDDIS|500|—|—|mA|VGD= 4 V and driver at<br>low state|
|Output low reverse<br>current|–IGDREVL|—|—|100|mA|Applies if VGD< 0 V and<br>driver at low state|
|Output high reverse<br>current in PWM mode|IGDREVH|—|1/6 of IGDH|—||Applies if<br>VGD> VGDH+ 0.5 V (typ)<br>and driver at high state|
> 15 referred to GDx_CFG.CUR = 16
Data Sheet
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## **Electrical Characteristics and Parameters**
|**Table 21**<br>**Electrical Characteristics of the A/D Converter**|**Table 21**<br>**Electrical Characteristics of the A/D Converter**|**Table 21**<br>**Electrical Characteristics of the A/D Converter**|**Table 21**<br>**Electrical Characteristics of the A/D Converter**|**Table 21**<br>**Electrical Characteristics of the A/D Converter**|**Table 21**<br>**Electrical Characteristics of the A/D Converter**|**Table 21**<br>**Electrical Characteristics of the A/D Converter**|
|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Values**|||**Unit**|**Note or Test Condition**|
|||**Min.**|**Typ.**|**Max.**|||
|Integral non-linearity|INL|—|—|1|LSB8|**_16)_**|
|**Table 22**<br>**Electrical Characteristics of the Reference Voltage**|**Table 22**<br>**Electrical Characteristics of the Reference Voltage**|**Table 22**<br>**Electrical Characteristics of the Reference Voltage**|**Table 22**<br>**Electrical Characteristics of the Reference Voltage**|**Table 22**<br>**Electrical Characteristics of the Reference Voltage**|**Table 22**<br>**Electrical Characteristics of the Reference Voltage**|**Table 22**<br>**Electrical Characteristics of the Reference Voltage**|
|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Values**|||**Unit**|**Note or Test Condition**|
|||**Min.**|**Typ.**|**Max.**|||
|Reference voltage|VREF|—|2.428|—|V||
|VREF overall tolerance|ΔVREF|—|—|±1.5|%|Trimmed, Tj≤ 125 °C and<br>aging|
## **Table 23 Electrical Characteristics of the OTP Programming**
|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|OTP programming<br>voltage at the VCC pin for<br>range C000Hto CFFFH|VPP|7.35|7.5|7.65|V|Operational values|
|OTP programming<br>voltage at the VCC pin for<br>range D000Hto DFFFH|VPP|9.0|—|VVCC|V|Operational values|
|OTP programming<br>current|IPP|—|1.6|—|mA|Programming of 4 bits in<br>parallel|
## **Table 24 Electrical Characteristics of the Clock Oscillators**
|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|Master clock oscillation<br>period including all<br>variations|tMCLK|19.2|20.0|21.1|ns|In reference to 50 MHz<br>fMCLK|
|Main clock oscillator<br>frequency variation of<br>stored DPARAM<br>frequency|ΔMCLK|–3.2|—|+2.0|%|Temperature drif and<br>aging only, 50 MHz fMCLK|
|Standby clock oscillator<br>frequency|fSTBCLK|96|100|104|kHz|Trimming tolerance at<br>TA= 25 °C|
|Standby clock oscillator<br>frequency|fSTBCLK|90|100|110|kHz|Overall tolerance|
> 16 ADC capability measured via channel MFIO without errors due to switching of neighbouring pins, e.g. gate drivers, measured with STC = 5. MFIO buffer non-linearity masked out by taking ADC output values ≥ 30 only.
Data Sheet
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## **Electrical Characteristics and Parameters**
|**Table 25**<br>**Electrical Characteristics of the Temperature Sensor**|**Table 25**<br>**Electrical Characteristics of the Temperature Sensor**|**Table 25**<br>**Electrical Characteristics of the Temperature Sensor**|**Table 25**<br>**Electrical Characteristics of the Temperature Sensor**|**Table 25**<br>**Electrical Characteristics of the Temperature Sensor**|**Table 25**<br>**Electrical Characteristics of the Temperature Sensor**|**Table 25**<br>**Electrical Characteristics of the Temperature Sensor**|
|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Values**|||**Unit**|**Note or Test Condition**|
|||**Min.**|**Typ.**|**Max.**|||
|Temperature sensor ADC<br>output operating range|ADCTEMP|0|—|190|LSB|ADCTEMP= 40 +<br>temperature / °C)|
|Temperature sensor<br>tolerance|ΔTEMP|—|—|±6|K|Incl. ADC conversion<br>accuracy at 3 σ|
Data Sheet
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## **Package Dimensions**
## **5 Package Dimensions**
The package dimensions of PG-DSO-16 are provided.
**==> picture [120 x 89] intentionally omitted <==**
**==> picture [89 x 81] intentionally omitted <==**
**==> picture [39 x 98] intentionally omitted <==**
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## **Figure 31**
## **Package Dimensions for PG-DSO-16**
_Note: Dimensions in mm._
_Note: You can find all of our packages, packing types and other package information on our Infineon Internet page “Products”: http://www.infineon.com/products._
Data Sheet
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## **References**
## **6 References**
**1.** Infineon Technologies AG: _XDPL8221 Design Guide_
**2.** Infineon Technologies AG: _XDPL8221 Reference Board Test Report_
**3.** Infineon Technologies AG: _CoolMOS P7 power MOSFETs_ , _**http://www.infineon.com/P7**_
**4.** Infineon Technologies AG: _.dp Vision User Manual_
**5.** Infineon Technologies AG: _.dp Interface Gen2_ which can be ordered at _**http://ehitex.com/programmer/ 486/.dp-interface-board-gen2**_
**6.** Infineon Technologies AG: _.dp Interface Gen2 User Manual_
**7.** Infineon Technologies AG: _XDP Programming Manual_
## **Revision History**
Major changes since previous revision
|**7.**<br>Infineon Technologies AG:_XDP Programming Manual_<br>**Revision History**<br>Major changes since previous revision|**7.**<br>Infineon Technologies AG:_XDP Programming Manual_<br>**Revision History**<br>Major changes since previous revision|
|---|---|
|||
|**Revision History**||
|**Revision**|**Description**|
|1.1|•<br>Indication of ambient temperature for IC is deleted.<br>•<br>UART dimming changed from duty cycle to dimming level.<br>•<br>Minor Change of wording|
|1.0|•<br>Minor change of wording|
## **Glossary**
## **ABM**
## _Active Burst Mode (ABM)_
Active Burst Mode is an operating mode of a switched-mode power supply for very light load conditions. The controller switches in bursts of pulses with a pause between bursts in which no switching is done.
## **AC**
## _Alternating Current (AC)_
An Alternating Current is a form of power supply in which the flow of electric charge periodically reverses direction.
## **ADC**
## _Analog-to-Digital Converter (ADC)_
An analog-to-digital converter is a device that converts a continuous physical quantity (usually voltage) to a digital number that represents the quantity's amplitude.
## **BOM**
## _Bill of Materials (BOM)_
A bill of materials is a list of the raw materials, sub-assemblies, intermediate assemblies, sub-components, parts and the quantities of each needed to manufacture an end product.
## **CC**
## _Constant Current (CC)_
Constant Current is a mode of a power supply in which the output current is kept constant regardless of the load.
Data Sheet
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## **Glossary**
## **CCM**
_Continuous Conduction Mode (CCM)_
Continuous Conduction Mode is an operational mode of a switching power supply in which the current is continuously flowing and does not return to zero.
## **CRC**
_Cyclic Redundancy Check (CRC)_
A cyclic redundancy check is an error-detecting code commonly used to detect accidental changes to raw data.
## **CV**
_Constant Voltage (CV)_
Constant Voltage is a mode of a power supply in which the output voltage is kept constant regardless of the load.
## **DAC**
_Digital-to-Analog Converter (DAC)_
A digital-to-analog converter is a device that converts digital data into an analog signal (typically voltage).
## **DC**
_Direct Current (DC)_
A Direct Current is a form of power supply in which the flow of electric charge is only into one direction.
## **DCM**
_Discontinuous Conduction Mode (DCM)_
Discontinuous Conduction Mode is an operational mode of a switching power supply in which the current starts and returns to zero.
## **ECG**
_Electronic Control Gear (ECG)_
An electronic control gear is a power supply which provides one or more light module(s) with the appropriate voltage or current.
## **EMI**
_Electro-Magnetic Interference (EMI)_
Also called Radio Frequency Interference (RFI), this is a (usually undesirable) disturbance that affects an electrical circuit due to electromagnetic radiation emitted from an external source. The disturbance may interrupt, obstruct, or otherwise degrade or limit the effective performance of the circuit.
## **FB**
_Flyback (FB)_
A flyback converter is a power converter with the inductor split to form a transformer, so that the voltage ratios are multiplied with an additional advantage of galvanic isolation between the input and any outputs.
## **FW**
_Firmware (FW)_
A proprietary software exploiting a set of functions.
## **GUI**
_Graphic User Interface (GUI)_
A graphical user interface is a type of interface that allows users to interact with electronic devices through graphical icons and visual indicators.
## **HW**
_Hardware (HW)_
The collection of physical elements that comprise a computer system.
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## **Glossary**
## **IC**
## _Integrated Circuit (IC)_
A miniaturized electronic circuit that has been manufactured in the surface of a thin substrate of semiconductor material. An IC may also be referred to as micro-circuit, microchip, silicon chip, or chip.
## **IIR**
## _Infinite Impulse Response (IIR)_
Infinite impulse response is a property applying to many linear time-invariant systems. Common examples of linear time-invariant systems are most electronic and digital filters. Systems with this property have an impulse response which does not become exactly zero past a certain point, but continues indefinitely.
## **LED**
## _Light Emitting Diode (LED)_
A light-emitting diode is a two-lead semiconductor light source which emits light when activated.
## **LP**
## _Limited Power (LP)_
Limited Power is a mode of a power supply in which the output power is limited regardless of the load.
## **NTC**
## _Negative Temperature Coefficient Thermistor (NTC)_
A negative temperature coefficient thermistor is a type of resistor whose resistance declines over temperature.
## **OCP1**
_Overcurrent Protection Level 1 (OCP1)_
The Overcurrent Protection Level 1 is limiting the current in a switched-mode power supply to limit the power delivered to the output of the power supply.
## **OCP2**
## _Overcurrent Protection Level 2 (OCP2)_
The Overcurrent Protection Level 2 is protecting the current in a switched-mode power supply from exceeding a maximum threshold.
## **OTP**
_One Time Programmable Memory (OTP)_
A One-Time Programmable memory is a form of memory to which data can be written once. After writing, the data is stored permanently and cannot be further changed.
## **PF**
## _Power Factor (PF)_
Power factor is the ratio between the real power and the apparent power.
## **PFC**
_Power Factor Correction (PFC)_
Power factor correction increases the power factor of an AC power circuit closer to 1 which corresponds to minimizing the reactive power of the power circuit.
## **PSR**
_Primary Side Regulated (PSR)_
A Primary Side Regulated power supply controls its operation based on a property sensed on primary side of an isolated power supply.
## **PWM**
## _Pulse Width Modulation (PWM)_
Pulse-width modulation is a technique to encode an analog value into the duty cycle of a pulsing signal with arbitrary amplitude.
Data Sheet
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## **Glossary**
## **QRM**
## _Quasi-Resonant Mode (QRM)_
Quasi-Resonant Mode is an operating mode of a switched-mode power supply which maximizes efficiency. This is achieved by only switching at preferred times when switching losses are low.
## **QRM1**
_Quasi-Resonant Mode, switching in first valley (QRM1)_
Quasi-Resonant Mode is an operating mode of a switched-mode power supply which maximizes efficiency. This is achieved by switching at the occurrence of the first valley of a signal which corresponds to a time when switching losses are low.
## **QRMn**
_Quasi-Resonant Mode, switching in valley n (QRMn)_
Quasi-Resonant Mode is an operating mode of a switched-mode power supply which maximizes efficiency. This is achieved by switching at the occurence of an nth valley of a signal which corresponds to a time when switching losses are low.
## **RAM**
## _Random Access Memory (RAM)_
Random-access memory is a form of computer data storage which allows data items to be read and written regardless of the order in which data items are accessed.
## **THD**
## _Total Harmonic Distortion (THD)_
The total harmonic distortion of a signal is a measurement of the harmonic distortion present and is defined as the ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency.
## **UART**
_Universal Asynchronous Receiver Transmitter (UART)_
A universal asynchronous receiver transmitter is used for serial communications over a peripheral device serial port by translating data between parallel and serial forms.
## **USB**
## _Universal Serial Bus (USB)_
Universal Serial Bus is an industry standard that defines cables, connectors and communications protocols used in a bus for connection, communication, and power supply between computers and electronic devices.
## **UVLO**
## _Undervoltage Lockout (UVLO)_
The Undervoltage-Lockout is an electronic circuit used to turn off the power of an electronic device in the event of the voltage dropping below the operational value.
Data Sheet
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## **Trademarks**
All referenced product or service names and trademarks are the property of their respective owners.
**Edition 2018-10-31 IMPORTANT NOTICE Published by** The information given in this document shall in no event be regarded as a guarantee of conditions or **Infineon Technologies AG** characteristics (“Beschaffenheitsgarantie”) . **81726 Munich, Germany** With respect to any examples, hints or any typical values stated herein and/or any information regarding the **© 2018 Infineon Technologies AG** application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of **All Rights Reserved.** any kind, including without limitation warranties of non-infringement of intellectual property rights of any **Do you have a question about any** third party. **aspect of this document?** In addition, any information given in this document is **Email: erratum@infineon.com** subject to customer’s compliance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning **Document reference** customer’s products and any use of the product of **IFX-ddk1479303396071** Infineon Technologies in customer’s applications.
## **WARNINGS**
Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office.
Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury
The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer’s technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application.
Updated at March 15, 2026
Infineon Technologies is a globally recognized leader in semiconductor solutions, renowned for driving innovation in power management, energy efficiency, and modern mobility. With a strong legacy of engineering excellence, the company provides highly reliable components designed to meet the rigorous demands of industrial, automotive, and advanced commercial applications. The core of our Infineon portfolio is centered on their industry-leading discrete semiconductors. We offer an extensive selection of single and dual MOSFETs, alongside a robust range of single IGBTs and advanced IGBT modules. These flagship power transistors are essential for high-efficiency power conversion and motor control, providing engineers with superior thermal performance and minimized switching losses. Beyond advanced field-effect transistors, the selection includes a comprehensive array of diodes and rectifiers, heavily featuring Schottky diodes, as well as fast-recovery and RF/PIN diodes. This power foundation is further supported by bipolar transistors, intelligent power modules, and thyristor SCR modules, delivering the critical building blocks required for complex power system designs. To support broader system integration, the portfolio also encompasses specialized solutions such as solid-state relays, AC/DC LED driver ICs, and Bluetooth communications modules. From high-power industrial rectifiers to wireless connectivity adapters, Infineon equips designers with the precision components needed to build efficient, scalable, and fully connected electronic systems.
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