STK5F4U3C2D-E

Ordering number : EN*A2299 

## **STK5F4U3C2D-E** 

## _Advance Information_ 

## **Thick-Film Hybrid IC Inverter Power IPM for 3-phase Motor Drive** 

http://onsemi.com 

## **Overview** 

This “Inverter Power IPM” is highly integrated device containing all High Voltage (HV) control from HV-DC to 3-phase outputs in a single DIP module (Dual-In line Package). Output stage uses IGBT/FRD technology and implements Under Voltage Protection (UVP) and Over Current Protection (OCP) with a Fault Detection output flag. Internal Boost diodes are provided for high side gate boost drive. 

## **Function** 

- Single control power supply due to Internal bootstrap circuit for high side pre-driver circuit 

- All control inputs and status outputs are at low voltage levels directly compatible with microcontrollers. 

- A single power supply drive is enabled through the use of bootstrap circuits for upper power supplies 

- Built-in dead-time for shoot-thru protection 

- Having open emitter output for low side IGBTs; individual shunt resistor per phase for OCP 

- Externally accessible embedded thermistor for substrate temperature measurement 

- Shutdown function ‘ITRIP’ to disable all operations of the 6 phase output stage by external input 

## **Certification** 

 UL1557 (File number: E339285). 

## **Specifications** 

## **Absolute Maximum Ratings** at Tc = 25  C 

|**Absolute Maximum Ratingsgss **|**Absolute Maximum Ratingsgss **at Tc = 25|C|||
|---|---|---|---|---|
|Parameter|Symbol|Remarks|Ratings|Unit|
|Supplyvoltage|VCC|P to NU,NV,NW,surge < 500V *1|450|V|
|Collector-emitter voltage|VCE|P to U,V,W,U to NU,V toNV,or W to NW|600|V|
|Output current<br>~~ee~~|Io<br>~~ee~~<br>~~ee~~|P,NU,NV,NW,U,V,W terminal current.<br>~~ee~~|±30<br>~~ee~~|A<br>~~ee~~|
|||P,NU,NV,NW,U,V,W terminal current,Tc=100C<br>~~ee~~<br>~~ee~~|±15<br>~~ee~~||
|Output peak current<br>~~ee~~|Iop<br>~~ee~~<br>~~ee~~<br>~~rs ee~~|P, NU,NV,NW,U,V,W terminal current, PW=1ms.<br>~~ee~~<br>~~ee~~<br>~~ee~~|±45<br>~~ee~~|A<br>~~ee~~|
|Pre-driver supplyvoltage<br>~~es~~|VD1,2,3,4<br>~~ee ~~<br>~~es~~<br>~~rs ee~~|VB1-VS1,VB2-VS2,VB3-VS3,VDD-VSS  *2<br> ~~ee~~<br>~~es~~<br>~~ee~~|20<br>~~es~~|V<br>~~es~~|
|Input signal voltage|VIN<br>~~rs ee~~|HIN1,2,3,LIN1,2,3,terminal.<br>~~ee~~|0.3 to VDD|V|
|FAULT terminal voltage<br>~~a~~|VFAULT<br>~~a~~|FAULT terminal.<br>~~a~~|0.3 to VDD<br>~~a~~|V<br>~~a~~|
|Maximum loss<br>~~a~~|Pd<br>~~a~~|IGBTper channel<br>~~a~~|56.8<br>~~a~~|W<br>~~a~~|
|Junction temperature|Tj|IGBT,FRD|150|C|
|Storage temperature<br>~~a~~|Tstg<br>~~a~~|~~a~~|40 to +125<br>~~a~~|C<br>~~a~~|
|Operatingtemperature<br>~~a~~|Tc<br>~~a~~|IPM case<br>~~a~~|20 to +100<br>~~a~~|C<br>~~a~~|
|Tighteningtorque|MT|A screwpart at use M4 type screw   *3|1.17|Nm|
|Withstand Voltage|Vis|50Hz sine wave AC 1 minute   *4|2000|VRMS|



Reference voltage is “VSS” terminal voltage unless otherwise specified. 

- *1:  Surge voltage developed by the switching operation due to the wiring inductance between the P and N terminals. 

- *2:  Terminal voltage: VD1=VB1-VS1, VD2=VB2-VS2, VD3=VB3-VS3, VD4=VDD-VSS. 

- *3:  Flatness of the heat-sink should be 0.25mm and below. 

*4.  Test conditions:    AC   2500V, 1 second. 

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. ~~_~~ This document contains information on a new product. Specifications and information herein are subject to change without notice. 

## **ORDERING INFORMATION** 

See detailed ordering and shipping information on page 15 of this data sheet. 

Semiconductor Components Industries, LLC, 2014 **March, 2014** Ver.1402018DS 

30414HK  No.A2299-1/15 

**STK5F4U3C2D-E** 

## **Electrical Characteristics** at Tc= 25  C, VD1, VD2, VD3, VD4=15V 

|Parameter|Symbol|Conditions|Test<br>Circuit||Ratings||Unit|
|---|---|---|---|---|---|---|---|
|||||Min.|Typ.|Max.||
|**Power output section**||||||||
|Collector-to-emitter cut-off current|ICE|VCE=600V|Fig.1|-|-|1.0|mA|
|Boot-strap diode reverse current|IR(BD)|VR(BD)=600V|-|-|-|0.5|mA|
|Collector-to-emitter saturation voltage|VCE(sat)|Ic=30A, Tj=25C|Fig.2|-|1.7|2.5|V|
|||Ic=15A, Tj=100C||-|1.4|-||
|Diode forward voltage|VF|IF=30A,Tj=25C|Fig.3|-|1.8|2.7|V|
|||IF=15A,Tj=100C||-|1.5|-||
|Junction to case thermal resistance|θj-c(T)|IGBT|-|-|1.8|-|C/W|
||θj-c(D)|FWD|-|-|2.3|-|C/W|
|**Control (Pre-driver) section**||||||||
|Pre-drive power supply consumption<br>current|ID|VD1,2,3=15V|Fig.4|-|0.05|0.4|mA|
|||VD4=15V||-|1.0|4.0||
|High level input voltage|Vin H|HIN1,HIN2,HIN3,<br>LIN1,LIN2,LIN3|-|2.5|-|-|V|
|Low level input voltage|Vin L||-|-|-|0.8|V|
|**Protection section**||||||||
|ITRIP threshold voltage|VITRIP|ITRIP(17) to VSS(19)|Fig.5|0.44|0.49|0.54|V|
|Pre-drive low voltageprotection|UVLO||-|10|-|12|V|
|FAULT terminal input electric current|IOSD|VFAULT=0.1V|-|-|1.5|-|mA|
|FAULT clearance delay time|FLTCLR|From time fault condition<br>clear|-|1.0|-|3.0|ms|
|Thermistor for substrate temperature<br>monitor|Rt|Resistance between the<br>TH1 and TH2 terminals|-|90|-|110|kΩ|
|**Switching character**||||||||
|Switching time|tON|Io=30A, Inductive load|Fig.6|-|0.6|1.5|μs|
||tOFF|||-|1.2|2.2|μs|
|Turn-on switching loss|Eon|Io=30A, VCC=300V,<br>VD=15V, L=680μH||-|710|-|μJ|
|Turn-off switchingloss|Eoff|||-|570|-|μJ|
|Total switchingloss|Etot|||-|1280|-|μJ|
|Turn-on switchingloss|Eon|Io=15A,VCC=300V,<br>VD=15V,L=680μH,<br>Tc=100C||-|360|-|μJ|
|Turn-off switchingloss|Eoff|||-|460|-|μJ|
|Total switchingloss|Etot|||-|820|-|μJ|
|Diode reverse recovery energy|Erec|Io=15A,VCC=300V,<br>VD=15V,L=680μH,<br>Tc=100C||-|16|-|μJ|
|Diode reverse recovery time|Trr|||-|62|-|ns|



Reference Voltage is “VSS” terminal voltage unless otherwise specified. 

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 

No.A2299-2/15 

**STK5F4U3C2D-E** 

## Notes. 

1. Input ON voltage indicates the threshold of input signal voltage to turn on output stage IGBT. Input OFF voltage indicates the threshold of input signal voltage to turn off output stage IGBT. At the time of output ON, set the input signal voltage Vinth(MAX) to 15V. At the time of output OFF, set the input signal voltage 0V to Vinth(MIN). 

   - *1 The hysteresis voltage is a reference value based on the designed value of built-in pre-driver. 

2. When the internal protection circuit operates, a FAULT signal is turned ON (When the FAULT terminal is low level, FAULT signal is ON state : output form is open DRAIN) but the FAULT signal does not latch. After protection operation ends, it returns automatically within about 1ms to 3ms and resumes operation beginning condition. So, after FAULT signal detection, set all input signal to OFF (Low) at once.How ever, the operation of pre-drive power supply low voltage protection (UVLO:with  hysteresis about 0.2V) is as follows. 

## Upper side: 

- The gate is turned off and will return to regular operation when recovering to the normal voltage, but the latch will continue till the input signal will turn ‘low’ 

Lower side: 

   - The gate is turned off and will automatically reset when recovering to normal voltage. It does not depend on input signal voltage. 

3.  When assembling the IPM on the heat sink with M4 type screw, tightening torque range is 0.79Nm to 1.17Nm. 

4.  The pre-drive low voltage protection is the feature to protect a device when the pre-driver supply voltage falls due to an operating malfunction. 

5.  When use the over-current protection with external resistors, please set the current protection level to be equal or less than the rating of output peak current (Iop). 

## **Pin Assignment** 

|Pin No.|Name|Description|Pin No.|Name|Description|
|---|---|---|---|---|---|
|1|VB1|High side floating supply voltage 1|44|P|Positive bus input voltage|
|2|VS1|High side floating supply offset voltage|43|P|Positive bus input voltage|
|3|-|Without pin|42|P|Positive bus input voltage|
|4|VB2|High side floating supply voltage 2|41|-|Without pin|
|5|VS2|High side floating supply offset voltage|40|U|U+   phase output|
|6|-|Without pin|39|U|U+   phase output|
|7|VB3|High side floating supply voltage 3|38|U|U+   phase output|
|8|VS3|High side floating supply offset voltage|37|-|Without pin|
|9|-|Without pin|36|V|V+   phase output|
|10|HIN1|Logic input high side driver-Phase1|35|V|V+   phase output|
|11|HIN2|Logic input high side driver-Phase2|34|V|V+   phase output|
|12|HIN3|Logic input high side driver-Phase3|33|-|Without pin|
|13|LIN1|Logic input low side driver-Phase1|32|W|W+  phase output|
|14|LIN2|Logic input low side driver-Phase2|31|W|W+  phase output|
|15|LIN3|Logic input low side driver-Phase3|30|W|W+  phase output|
|16|FAULT|Fault out|29|-|Without pin|
|17|ITRIP|Over-current protection level setting pin|28|NU|U-    phase output|
|18|VDD|+15V main supply|27|NU|U-    phase output|
|19|VSS1|Negative main supply|26|NV|V-    phase output|
|20|VSS2|Negative main supply|25|NV|V-    phase output|
|21|TH1|Thermistor out|24|NW|W-   phase output|
|22|TH2|Thermistor out|23|NW|W-   phase output|



No.A2299-3/15 

**STK5F4U3C2D-E** 

## **Block Diagram** 

**==> picture [509 x 672] intentionally omitted <==**

**----- Start of picture text -----**<br>
U(38,39,40) V(34,35,36) W(30,31,32)<br>VB1(1)<br>VS1(2)<br>VB2(4)<br>VS2(5)<br>VB3(7)<br>VS3(8)<br>P(42,43,44)<br>DB  DB  DB  U.V. U.V. U.V.<br>RB<br>NU(27,28)<br>NV(25,26)<br>NW(23,24)<br>TH1(21)<br>Thermistor Level  Level  Level<br>Shifter  Shifter  Shifter<br>TH2(22)<br>HIN1(10)<br>HIN2(11)<br>HIN3(12) Logic  Logic  Logic<br>LIN1(13)<br>LIN2(14)<br>LIN3(15)<br>ITRIP(17) Shutdown<br>VDD(18)  Under voltage  +  S    Q<br>Detect  -<br>Timer  R<br>VSS1(19) Vref<br>VSS2(20) Latch time about 1 to 3ms<br>FAULT(16)<br>**----- End of picture text -----**<br>


No.A2299-4/15 

**STK5F4U3C2D-E** 

## **Test Circuit** 

(The tested phase: U+ shows the upper side of the U phase and U- shows the lower side of the U phase.) 

##  **ICE / IR(BD)** 

||U|V|W|NU|NV|NW|
|---|---|---|---|---|---|---|
|M|42|42|42|38|34|30|
|N|38|34|30|27|25|23|
||||||||
||U(BD)|V(BD)|W(BD)||||
|M|1|4|7||||
|N|19|19|19||||



**==> picture [203 x 152] intentionally omitted <==**

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ICE<br>1                    M               A<br>VD1=15V<br>2<br>4<br>VD2=15V<br>5                                                VCE<br>7<br>VD3=15V<br>8<br>18<br>VD4=15V<br>19,20              N<br>Fig.1<br>**----- End of picture text -----**<br>


##  **VCE(SAT)   (Test by pulse)** 

||U|V|W|NU|NV|NW|
|---|---|---|---|---|---|---|
|M|42|42|42|38|34|30|
|N|38|34|30|27|25|23|
|m|10|11|12|13|14|15|



##  **VF  (Test by pulse)** 

||U|V|W|NU|NV|NW|
|---|---|---|---|---|---|---|
|M|42|42|42|38|34|30|
|N|38|34|30|27|25|23|



**==> picture [203 x 304] intentionally omitted <==**

**----- Start of picture text -----**<br>
1                   M<br>VD1=15V<br>2<br>4<br>VD2=15V<br>5<br>V                            Ic<br>7<br>VD3=15V                                                         VCE(SAT)<br>8<br>18<br>VD4=15V<br>5V      m                   N<br>19,20<br>Fig.2<br>M<br>V      VF              IF<br>N<br>Fig.3<br>**----- End of picture text -----**<br>


##  **ID** 

||VD1|VD2|VD3|VD4|
|---|---|---|---|---|
|M|1|4|7|18|
|N|2|5|8|19|



**==> picture [143 x 92] intentionally omitted <==**

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ID<br>A               M<br>VD*<br>N<br>Fig.4<br>**----- End of picture text -----**<br>


No.A2299-5/15 

**STK5F4U3C2D-E** 

##  **ISD (The circuit is a representative example of the lower side U phase.)** 

**==> picture [410 x 152] intentionally omitted <==**

**----- Start of picture text -----**<br>
1  38<br>VD1=15V<br>2<br>Input signal  4<br>(0 to 5V)  VD2=15V<br>5<br>Io<br>ITRIP  7<br>VD3=15V<br>8<br>18<br>VD4=15V<br>Io<br>Input signal  13  27<br>19,20<br>**----- End of picture text -----**<br>


Fig.5 

##  **Switching time (The circuit is a representative example of the lower side U phase.)** 

**==> picture [164 x 114] intentionally omitted <==**

**----- Start of picture text -----**<br>
Input signal<br>(0 to 5V)<br>90%<br>Io<br>10%<br>tON tOFF<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
1  42<br>VD1=15V<br>2<br>4<br>VD2=15V<br>5  38<br>Vcc<br>7<br>CS<br>VD3=15V<br>8<br>18<br>Io<br>VD4=15V<br>13<br>Input signal  27<br>19,20<br>**----- End of picture text -----**<br>


Fig.6 

No.A2299-6/15 

**STK5F4U3C2D-E** 

## **Input  / Output Timing Chart** 

**==> picture [488 x 507] intentionally omitted <==**

**----- Start of picture text -----**<br>
VBS undervoltage protection reset signal<br>ON<br>HIN1,2,3<br>OFF<br>LIN1,2,3<br>VDD undervoltage protection reset voltage<br>*2<br>VDD<br>VBS undervoltage protection reset voltage<br>*3<br>VB1,2,3<br>VIT≥0.54V<br>*4<br>ITRIP terminal<br>Voltage  VIT<0.44V<br>FAULT terminal<br>Voltage<br>(at pulled-up)<br>ON<br>*1<br>Upper<br>U, V, W<br>OFF<br>*1<br>Lower<br>U ,V, W<br>Automatically reset after protection<br>Fig.7  (typ.2ms)<br>**----- End of picture text -----**<br>


Notes: 

- *1 : Diagram shows the prevention of shoot-thru via control logic, however, more dead time must be added to account for switching delay externally. 

- *2 : When VDD decreases all gate output signals will go low and cut off all 6 IGBT outputs. When VDD rises the operation will resume immediately. 

- *3 : When the upper side voltage at VB1, VB2 and VB3 drops only the corresponding upper side output is turned off. The outputs return to normal operation immediately after the upper side gate voltage rises. 

- *4 : When VITRIP exceeds threshold all IGBT’s are turned off and normal operation resumes 2ms (typ) after over current condition is removed. 

No.A2299-7/15 

**STK5F4U3C2D-E** 

## **Logic level table** 

**==> picture [252 x 201] intentionally omitted <==**

**----- Start of picture text -----**<br>
P(42,43,44)<br>Ho<br>HIN1,2,3<br>(10,11,12)<br>IC  U(38,39,40)<br>Driver  V(34,35,36)<br>LIN1,2,3  W(30,31,32)<br>(13,14,15)<br>Lo<br>NU(27,28)<br>Fig.8<br>NV(25,26)<br>NW(23,24)<br>**----- End of picture text -----**<br>


|FAULT*|Itrip|HIN1,2,3|LIN1,2,3|U,V,W|
|---|---|---|---|---|
|1|0|1|0|Vbus|
|1|0|0|1|0|
|1|0|0|0|Off|
|1|0|1|1|Off|
|0|1|X|X|Off|



*With pullup registor 

No.A2299-8/15 

**STK5F4U3C2D-E** 

## **Application Circuit Example** 

**==> picture [432 x 364] intentionally omitted <==**

**----- Start of picture text -----**<br>
CB<br>U<br>+  1  VB1 40<br>2  VS1 39<br>38<br>CB<br>V<br>+  4  VB2 36<br>5  VS2 35<br>34<br>CB<br>+5.0V<br>+  7  VB3 W  32<br>8  VS3 31<br>RFault  30<br>RP<br>Vcc<br>10 HIN1 P  44 +<br>43<br>11 HIN2<br>42 CS  +  CI<br>C o n t r o l   12 HIN3<br>C i r c u i t   13 LIN1 -<br>14 LIN2<br>15 LIN3<br>RSU<br>NU<br>16 FAULT 28<br>17 ITRIP  27<br>RS<br>Controler.<br>RSV<br>VDD=15V  Rpd  18 VDD  NV- 26<br>25<br>CD  19 VSS1<br>20 VSS2<br>RSW<br>21 TH1  NW- 24<br>22 TH2<br>23<br>Missing pin  Op-Amp.<br>3, 6, 9, 29, 33, 37, 41  Controler.<br>**----- End of picture text -----**<br>


Fig.9 

No.A2299-9/15 

**STK5F4U3C2D-E** 

## **Recommended Operating Conditions** at Tc = 25  C 

|Parameter|Symbol|Conditions||Ratings||Unit|
|---|---|---|---|---|---|---|
||||min|typ|max||
|Supply voltage|VCC|P to NU,NV,NW|0|280|450|V|
|Pre-driver supply voltage|VD1,2,3|VB1 –VS1,VB2 –VS2,VB3 –VS3|12.5|15|17.5|V|
||VD4|VDD – VSS  *1|13.5|15|16.5||
|Input ON voltage|VIN(ON)|HIN1,HIN2,HIN3,<br>LIN1,LIN2,LIN3|3.0|-|5.0|V|
|Input OFF voltage|VIN(OFF)||0|-|0.3||
|PWM frequency|fPWM||1.0|-|20|kHz|
|Dead time|DT|Turn-off to turn-on (external)|2|-|-|μs|
|Allowable input pulse width|PWIN|ON and OFF|1|-|-||
|Tightening torque|MT|‘M4’Type Screw|0.79|-|1.17|Nm|



*1   Pre-driver power supply (VD4=15±1.5V) must have the capacity of Io=20mA(DC), 0.5A(Peak). 

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 

## **Usage Precautions** 

1. This IPM includes internal bootstrap diodes and resistors. By adding a bootstrap capacitor “CB”, a high side drive voltage is generated; each phase requires an individual bootstrap capacitor. The recommended value of CB is in the range of 1 to 47μF (±20%), however this value needs to be verified prior to production. If selecting the capacitance more than 47μF (±20%), connect a resistor (about 40Ω) in series between each 3-phase upper side power supply terminals (VB1,2,3) and each bootstrap capacitor. When not using the bootstrap circuit, each upper side pre-drive power supply requires n external independent power supply. 

2. It is essential that wirning length between terminals in the snubber circuit be kept as short as possible to reduce the effect of surge voltages. Recommended value of “CS” is in the range of 0.1 to 10μF. 

3. ”FAULT”  (16pin) is open DRAIN output terminal (Active Low). Pull up resistor is recommended more than 5.6kΩ. 

4. Inside the IPM, a thermistor used as the temperature monitor for internal substrate is connected between “TH1” and “TH2” . Generally, one of terminals is connected to VSS, and the other is pulled up to external power supply with pull-up resistor (Rp) externally. The temperature monitor example application is as follows please refer the Fig.10 and Fig.11 below. 

5. The pull-down resistor 33kΩ is provided internally at the signal input terminals. An external resistor of 2.2kΩ to 3.3kΩ should be added to reduce the influence of external wiring noise. 

6. As protection of IPM to unusual current by a short circuit etc, it recommended installing shunt resistors and an over-current protection circuit outside. Moreover, for safety, a fuse on Vcc line is recommended. 

7.  Disconnection of terminals U, V, W, during normal motor operation will cause damage to IPM, use caution with this connections. 

8. The “ITRIP” terminal (17pin) is the input terminal to shut down. When VITRIP exceeds threshold  (0.44V to 0.54V), all IGBTs are turned off. And normal operation resumes 2ms(typ) after over current condition is removed. Therefore, please turn all the input signal off (Low) in case of detecting error at the “FAULT” terminal. 

9.  When input pulse width is less than 1us, an output may not react to the pulse. (Both ON signal and OFF signal) 

No.A2299-10/15 

**STK5F4U3C2D-E** 

## **The characteristic of thermistor** 

|Parameter|Symbol|Conditions|Min|Typ.|Max|Unit|
|---|---|---|---|---|---|---|
|Resistance|R25|Tc=25C|97|100|103|kΩ|
|Resistance|R100|Tc=100C|4.93|5.38|5.88|kΩ|
|B-Constant(25-50C)|B||4165|4250|4335|K|
|Temperature Range|||-40||+125|C|



Fig.10 Variation of thermistor resistance with temperature. 

**==> picture [109 x 24] intentionally omitted <==**

**----- Start of picture text -----**<br>
Condition<br>Pull-up resistor = 39kohm +/-1%<br>Pull-up voltage of TH = 5V +/-0.3V<br>**----- End of picture text -----**<br>


Fig.11 Variation of temperature sense voltage with thermistor temperature. 

No.A2299-11/15 

**STK5F4U3C2D-E** 

## **Io-f curve** 

**==> picture [255 x 179] intentionally omitted <==**

**----- Start of picture text -----**<br>
Motor Current vs. Frequency<br>(Sine wave oparation,Vcc=300V,cosθ=0.8,ON Duty=96%)<br>50<br>40<br>30<br>20<br>10<br>0<br>0 5 10 15 20<br>Switching Frequency : fc    (KHz)<br>Phase Current : Io  (A rms)<br>**----- End of picture text -----**<br>


Fig.12  Maximum sinusoidal phase current as function of switching frequency. at Tc=100C, Vcc=300V 

## **Switching waveform** 

**==> picture [40 x 8] intentionally omitted <==**

**----- Start of picture text -----**<br>
Turn on<br>**----- End of picture text -----**<br>


Fig. 13  IGBT Turn-on. Typical turn-on waveform.  at Tc=100C, Vcc=300V, Io=15A 

**==> picture [40 x 8] intentionally omitted <==**

**----- Start of picture text -----**<br>
Turn off<br>**----- End of picture text -----**<br>


Fig. 14  IGBT Turn-off. Typical turn-off waveform. at Tc=100C, Vcc=300V, Io=15A 

No.A2299-12/15 

**STK5F4U3C2D-E** 

## **CB capacitor value calculation for Boot strap circuit** 

## **Calculate condition** 

|**Calculate condition**||||
|---|---|---|---|
|Item|Symbol|Value|Unit|
|Upperside powersupply|VBS|15|V|
|Totalgate charge ofoutput power IGBTat15V.|Qg|0.266|μC|
|Upperside powersupplylow voltage protection.|UVLO|12|V|
|Upperside powerdissipation.|IDMAX|400|μA|
|ONtimerequiredforCB voltage tofall from 15Vto UVLO|TONMAX|-|s|



## **Capacitance calculation formula** 

Ton-max is upper arm maximum on time equal the time when the CB voltage falls from 15V to the upper limit of Low voltage protection level. 

“Ton-maximum" of upper side is the time that CB decreases 15V to the maximum low voltage protection of the upper side (12V). 

Thus, CB is calculated by the following formula. 

VD x CB – Qg – IDmax * Ton-max = UVLO * CB 

CB = (Qg + IDmax * Ton-max) / (VD – UVLO) 

The relationship between Ton-max and CB becomes as follows. Recommend Cb is approximately 3 times of above calculated value. Please make the decision by the evaluation with the set 

**==> picture [344 x 215] intentionally omitted <==**

**----- Start of picture text -----**<br>
CB vs Tonmax<br>100<br>10<br>1<br>0.1<br>0.01<br>0.1 1 10 100 1000<br>tonmax(ms)<br>Bootstrap capacitance Cb (uF)<br>**----- End of picture text -----**<br>


Fig.15 Ton-max vs CB characteristic. 

No.A2299-13/15 

**STK5F4U3C2D-E** 

## **Package Dimensions** 

unit : mm 

## **HYBRID INTEGRATED MODULE** 

CASE MODAW ISSUE O 

**==> picture [397 x 395] intentionally omitted <==**

**----- Start of picture text -----**<br>
4.6 6.0<br>R 2.3<br>22 23<br>1 44<br>3.2<br>45.0 8.0<br>10.8<br>+ 0.2<br>0.5 0.05<br>49.7<br>+ 0.2 0.05<br> 53.34 0.75<br>0). =<br>63.4<br>(68 76.0 21 x 2.54<br>2.54<br>**----- End of picture text -----**<br>


No.A2299-14/15 

**STK5F4U3C2D-E** 

## **ORDERING INFORMATION** 

|Device|Package|Shipping (Qty/ Packing)|
|---|---|---|
|STK5F4U3C2D-E|610AC-DIP4-UL<br>(Pb-Free)|6 / Tube|



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