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QN9080-001-M17AZ
Microcontroller Application Specific, QN908x Series, ARM Cortex-M4F, 32bit, 512KB, 32 MHz, LFLGA-54
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- Manufacturer: NXP
- Product type: Bluetooth Modules & Adaptors
- Product Range:QN908x Series Microcontrollers; Architecture:ARM Cortex-M4F; MCU Core Size:32bit; Program Memory Size:512KB; RAM Memory Size:128KB; CPU Speed:32MHz; No. of I/O's:32I/O's; MCU Ca
- MSL: MSL 3 - 168 hours
- SVHC: No SVHC (27-Jun-2018)
- Interfaces: I2C, SPI, USART, USB
- MCU Series: QN908x
- Device Core: ARM Cortex-M4F
- IC Mounting: Surface Mount
- No. of Pins: 54Pins
- ADC Channels: 8Channels
- No. of I/O's: 32I/O's
- Product Range: QN9080 Series Microcontrollers
- ADC Resolution: 16Bit
- Certifications: CE, FCC, IC, MIC
- Data Bus Width: 32 bit
- Bluetooth Class: -
- RAM Memory Size: 128KB
- Bluetooth Version: Bluetooth 5.0
- IC Case / Package: LFLGA
- Program Memory Size: 512KB
- Supply Voltage Range: 1.62 V to 3.6 V
- Operating Frequency Max: 32MHz
- Receiver Sensitivity Rx: -92.7dBm
- Operating Temperature Range: -40 °C to 85 °C
| Delivery and price | |
|---|---|
| Units per pack | 100 |
| Price | 12.29 € |
| Current stock | 10+ |
| Lead time | 30 days |
Datasheet
## **QN9080-001-M17**
**Ultra Low-Power Bluetooth Smart 5.0 SIP Rev. 1.0 — 5 December 2018**
**Objective data sheet**
## **1. General description**
The QN9080-001-M17 is a fully certified device supporting BLE and NFC. It has ultra-low power consumption, highly integrated with rich feature sets, fully FCC/CE/IC/MIC certified. The QN9080-001-M17 supports Bluetooth 5, and it is intended for ultra-small, portable connected wireless applications.
This ultra-small device is based on QN9080 die and NT3H2211 die. QN9080 is powered by an Arm[] Cortex[] -M4F, and has a dedicated fusion sensor co-processor (FSP) to further reduce power consumption by off-loading complex math computations to the hardware. 512 KB of on-board flash and 128 KB SRAM provide enough room and flexibility for complex applications. NT3H2211 is NFC Forum Type 2 Tag compliant IC with I2C interface, which supplies the fastest, least expensive way to add tap-and-go connectivity to just about any electronic applications.
The QN9080-001-M17 also integrates 32 MHz and 32.768 kHz crystals, a 2.4 GHz optimized antenna, and necessary components for QN9080 system to run. It offers a complete solution for applications requiring BLE wireless connectivity and fast pairing with NTAG as an option. Its low external component count reduces overall system size, complexity and shortens development time.
## **2. Features and benefits**
- Key features:
- Bluetooth 5.0 certified
- Integrated antenna
- Integrated 32 MHz and 32.768 kHz crystals
- 32-bit Arm Cortex-M4F core at 32 MHz
- 512 KB flash
- 128 KB RAM
- TX power: up to +2 dBm
- RX sensitivity: -92.7 dBm in 1 Mbps mode and -89 dBm in 2 Mbps mode
- True single-chip Bluetooth Low Energy (v5.0) SoC solution:
- Integrated Bluetooth LE radio, protocol stack and application profiles
- Support central and peripherals roles
- Support master/slave concurrency
- Support 16 simultaneous links
- Support secure connections
- Support data packet length extension
- 48-bit unique BD address
- -92.7 dBm in 1 Mbps mode and -89 dBm in 2 Mbps mode
**Ultra Low-Power Bluetooth Smart**
**NXP Semiconductors**
**QN9080-001-M17**
- TX output power from -20 dBm to +2 dBm
- Very low power consumption:
- Single 1.67 V ~3.6 V power supply
- 1 A power-down mode, to wake up by GPIO
- 2 A power-down mode, to wake up by 32 kHz sleep timer, RTC and GPIO
- 4 mA RX current at 3 V supply in 1 Mbps
- Ultra Low power Bluetooth Low Energy 5.0 module
- 3.5 mA TX current at 0 dBm TX power at 3 V supply in 1 Mbps mode
- Interface:
- 32 General-Purpose Input/Output (GPIO) pins, with configurable pull-up/pull-down resistors
- 8 external ADC inputs (shared with GPIO pins)
- 2 Analog Comparator input pins (share with GPIO pins)
- Single power supply 1.67 V to 3.6 V
- Operating temperature range -40 °C to +85 °C
- 6 x9.7x1.17 mm LFLGA package
## **2.1 Feature of QN9080**
- True single-chip Bluetooth Low Energy (v5.0) SoC solution
- Integrated Bluetooth LE radio, protocol stack and application profiles
- Supports central and peripherals roles
- Supports master/slave concurrency
- Supports 16 simultaneous links
- Supports secure connections
- Supports data packet length extension
- Wifi/Bluetooth LE coexistence interface
- 48-bit unique bluetooth device address
- RF
- Fast and reliable RSSI in 1 dB step
- TX output power from 20 dBm to 2 dBm
- Single-ended RF port with integrated balun
- Generic FSK modulation with programmed data rate from 250 Kbps to 2 Mbps
- Compatible with worldwide radio frequency regulations
- Very low power consumption
- Single 1.67 V to 3.6 V power supply
- Integrated DC-to-DC buck converter and LDO
- 1.0 A power-down 1 mode, to wake up by GPIO
- 2.5 A power-down 0 mode, to wake up by 32 kHz sleep timer, RTC and GPIO
- 3.5 mA RX current with DC-to-DC convertor enabled at 3 V supply in 1Mbps mode
- 4 mA TX current at 0 dBm TX power with DC-to-DC converter enabled at 3 V supply in 1 Mbps mode
- Arm Cortex-M4 core (version r0p1)
- Arm Cortex-M4 processor, running at a frequency of up to 32 MHz
- Floating Point Unit (FPU) and Memory Protection Unit (MPU)
QN9080-001-M17 **Objective data sheet**
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors B.V. 2018. All rights reserved.
**2 of 39**
**Rev. 1.0 — 5 December 2018**
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**QN9080-001-M17**
- Arm Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC)
- Serial Wire Debug (SWD) with six instruction breakpoints, two literal comparators, and four watch points, including serial wire output for enhanced debug capabilities
- System tick timer
- On-chip memory
- 512 KB on-chip flash program memory and 2 KB page erase and write
- 128 KB SRAM
- 256 KB ROM
- ROM API support
- Flash In-System Programming (ISP)
- Serial interfaces
- Four Flexcomm serial peripherals
- USART protocol supported by Flexcomm0, USART and I[2] C by Flexcomm1, SPI and I2C by Flexcomm2, and SPI by Flexcomm3
- Each Flexcomm includes a FIFO
- I[2] C-bus interfaces support fast mode and with multiple address recognition and monitor mode
- USB 2.0 (full speed) device interface
- Two quadrature decoders
- SPI Flash Interface (SPIFI) uses a SPI bus superset with four data lines to access off-chip quad SPI flash memory at a much higher rate than is possible using standard SPI or SSP interfaces
- Supports SPI memories with 1 or 4 data lines
- Digital peripherals
- DMA controller with 20 channels, able to access memories and DMA capable peripherals
- Up to 35 General Purpose Input Output (GPIO) pins, with configurable pull-up or pull-down resistors
- GPIO registers are located on the AHB for fast access
- 32 GPIOs can be selected as Pin INTerrupts (PINT), triggered by rising, or falling input edges
- AES-128 security coprocessor
- Random Number Generator (RNG)
- CRC engine
- Fusion Signal Processor (FSP) for data fusion and machine learning algorithms resulting in low power consumption compared to software processing
QN9080-001-M17 **Objective data sheet**
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors B.V. 2018. All rights reserved.
**3 of 39**
**Rev. 1.0 — 5 December 2018**
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**QN9080-001-M17**
- Analog peripherals
- 16-bit ADC with 8 external input channels, with sample rates of up to 32k sample per second, and with multiple internal and external trigger inputs
- Integrated temperature sensor, connected to one internal dedicated ADC channel
- Integrated battery monitor connected to one internal dedicated ADC channel
- General-purpose 8-bit 1M sample per second DAC
- Integrated capacitive sense up to 8 channels, able to wake up the MCU from low power states.
- Two ultra low-power analog comparators, able to wake up the MCU from low power states.
- Timers
- Four 32-bit general-purpose timers or counters, support capture inputs and compare outputs, PWM mode, and external count input
- Sleep timer, which can work in power-down mode and wake up MCU
- 32-bit Real Time Clock (RTC) with 1 second resolution running in the always-on power domain; can be used for wake-up from all low power modes including power-down
- Watchdog Timer.
- SC Timer or PWM.
- Clock generation
- 32 MHz internal RC oscillator, which can be used as a system clock
- 16 MHz or 32 MHz crystal oscillator, which can be used as a system and RF reference
- 32 kHz on-chip RC oscillator
- 32.768 kHz crystal oscillator
- Power control
- Programmable Power Management Unit (PMU) to minimize power consumption
- Reduced power modes: sleep, and power-down
- Power-On Reset (POR)
- Brown-Out Detection (BOD) with separate thresholds for interrupt and forced reset
- Single power supply 1.67 V to 3.6 V
- Operating temperature range 40 °C to +85 °C
See **QN908x data sheet** for more details.
## **2.2 Features of NTAG**
- Interoperability
- ISO/IEC 14443 Part 2 and 3 compliant
- NTAG I2C plus development board is certified as NFC Forum Type 2 Tag (Certification ID: 58514)
- Unique 7-byte UID
- GET_VERSION command for easy identification of chip type and supported features
- Input capacitance of 50 pF
- Host interface
- I[2] C slave
All information provided in this document is subject to legal disclaimers.
QN9080-001-M17 **Objective data sheet**
© NXP Semiconductors B.V. 2018. All rights reserved.
**4 of 39**
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**Ultra Low-Power Bluetooth Smart**
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**QN9080-001-M17**
- Configurable event detection pin to signal NFC or pass-through data events
- Memory
- 1912 bytes of EEPROM-based user memory
- 64 bytes SRAM buffer for transfer of data between NFC and I[2] C interfaces with
memory mirror or pass-through mode
- Clear arbitration between NFC and I[2] C memory access
- Data transfer
- Pass-through mode with 64-byte SRAM buffer
- FAST_WRITE and FAST_READ NFC commands for higher data throughput
- Security and memory-access management
- Full, read-only, or no memory access from NFC interface, based on 32-bit password
- Full, read-only, or no memory access from I[2] C interface
- NFC silence feature to disable the NFC interface
- Originality signature based on Elliptic Curve Cryptography (ECC) for simple, genuine authentication
- Power Management
- Configurable field-detection output signal for data-transfer synchronization and device wake-up
- Energy harvesting from NFC field, so as to power external devices (e.g. connected microcontroller)
## See **NT3H2111_2211 Product Data Sheet** for more details.
## **2.3 Features of integrated 2.4 GHz antenna**
- Monolithic SMD with small, low-profile and light-weight type.
- Wide bandwidth
- RoHS compliant
Note: When NFC function is required, the NFC tag antenna need to be connected externally.
## **3. Applications**
- Health and medical devices
- Sports and fitness trackers
- Building and home automation
- Retail and advertising beacons
## **4. Ordering information**
**Table 1. Ordering information**
|**Type number**|**Package**|**Package**|**Package**|
|---|---|---|---|
||**Name**|**Description**|**Version**|
|QN9080-001-M17|LFLGA54|SIP module in LGA package; body 69.71.17 mm|SOT1910 AA1|
QN9080-001-M17
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors B.V. 2018. All rights reserved.
**Objective data sheet**
**5 of 39**
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**Table 2. Ordering options**
|**Type number**|**Package**<br>**number**|**Flash (KB)**|**Total SRAM**<br>**(KB)**|**Cortex-M4**<br>**with FPU**|**FSP**|**USB FS**|**GPIO**|
|---|---|---|---|---|---|---|---|
|QN9080-001-M17|3322 960 18570|512|128|1|1|1|32|
## **5. Marking**
**QN9080-1-M17** XXXXX XXXXXXXXXXXX EtDYYWWXX
**Fig 1. QN9080-001-M17 package marking**
**Table 3. Marking codes**
|**Line**<br>**number**|**Content**|**Descriptions**|
|---|---|---|
|1|NXP|Logo|
|2|QN9080-1-M17|Product identifier|
|3|XXXXX|STR number request. It will be removed on production|
|4|XXXXXXXXXXXX|QN batch number|
|5|E|TSMC|
||t|ASE-K|
||D|RoHS indicator (Dark green)|
||YY|year; last two digits of year code of assembly|
||WW|week code of assembly|
||X|mask version|
||X|for SIP before CQS; it will be removed after|
QN9080-001-M17 has the following top-side marking:
## **Table 4. Device revision table**
|**Revision identifier (R)**|**Revision description**|
|---|---|
|001|Initial SIP module revision|
QN9080-001-M17 device has received FCC "Modular Approval", in compliance with CFR 47 FCC part 15 regulations and in accordance to FCC public notice DA00-1407. The modular approvals notice and test reports are available on request.
**Remark:** FCC, IC & Japan ID are not mentioned on the package due to the small device size.
QN9080-001-M17 **Objective data sheet**
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors B.V. 2018. All rights reserved.
**6 of 39**
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**QN9080-001-M17**
## **6. Block diagram**
**==> picture [483 x 324] intentionally omitted <==**
**----- Start of picture text -----**<br>
QN9080M Antenna Harmonic filter<br>L2 3.3 nH<br>C3 C4 C5 ANT IN<br>0.1 F 0.1 F 0.1 F C2 C1<br>1.8 pF 1.8 pF<br>DCDC<br>DVDD RVDD AVDD<br>L3 L1 XTAL_IN<br>10nH 10 H Y1<br>C6 IDC XTAL_OUT 32 MHz<br>1 F<br>VCC VCC<br>Y2 XTAL32_IN RF<br>32.768 kHz XTAL32_OUT QN9080 die RF OUT<br>PA31-PA00<br>CHIP_MODE SCL<br>CHRG_SCL NTAG_LA<br>SDA NTAG<br>RSTN CHRG_SDA NT3H2211 NTAG_LB<br>FD<br>NTAG_VOUT<br>VSS<br>GND GND<br>GND DAP<br>NTAG_FD NTAG_VCC<br>**----- End of picture text -----**<br>
**Fig 2. QN9080-001-M17 – high level HW block diagram**
QN9080-001-M17
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors B.V. 2018. All rights reserved.
**Objective data sheet**
**7 of 39**
**Rev. 1.0 — 5 December 2018**
**Ultra Low-Power Bluetooth Smart**
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**QN9080-001-M17**
**==> picture [490 x 269] intentionally omitted <==**
**----- Start of picture text -----**<br>
QN9080M Antenna Harmonic filter<br>L2 3.3 nH<br>C3 C4 C5 ANT IN<br>0.1 F 0.1 F 0.1 F C2 C1<br>1.8 pF 1.8 pF<br>DCDC<br>DVDD RVDD AVDD<br>C6 10nHL3 10 HL1 IDC XTALXTAL_IN_OUT 32 MHzY1<br>1 F<br>Designed and provided by customer<br>External<br>VCC VCC Antenna<br>Harmonic filter<br>Y2 XTAL32_IN RF RF OUT L2 3.3 nH<br>32.768 kHz XTAL32_OUT QN9080 die C1 C2<br>1.8 pF 1.8 pF<br>PA31-PA00<br>CHIP_MODE SCL<br>CHRG_SCL NTAG_LA<br>SDA NTAG<br>RSTN CHRG_SDA NT3H2211 NTAG_LB<br>FD<br>NTAG_VOUT<br>VSS<br>GND GND<br>GND DAP<br>NTAG_FD NTAG_VCC<br>**----- End of picture text -----**<br>
**Fig 3. QN9080-001-M17 block diagram using external antenna**
**Remark:** (1) QN9080-001-M17 is not certified with external antenna but only with its internal antenna. Customer using external antenna has to do new certification. (2) Harmonic filter is in adequacy with board.
QN9080-001-M17 **Objective data sheet**
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors B.V. 2018. All rights reserved.
**8 of 39**
**Rev. 1.0 — 5 December 2018**
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**QN9080-001-M17**
## **7. Pinning information**
## **7.1 Pinning**
**==> picture [222 x 343] intentionally omitted <==**
**----- Start of picture text -----**<br>
1 44 43 42 41 40 39 38 37 36 35<br>2 34<br>3 33<br>4 32<br>5 51 54 31<br>6 30<br>7 29<br>8 52 53 28<br>9 27<br>10 26<br>11 25<br>12 24<br>13 14 15 16 17 18 19 20 21 22 23<br>45 50<br>46 49<br>47 48<br>**----- End of picture text -----**<br>
**Fig 4. QN9080-001-M17 pinout diagram**
## **7.2 Pin description**
**Table 5. Pin description**
|**Symbol**|**LFLGA54**|**Reset**<br>**state**<br>**[1]**|**Alternate function**|**Type**|**Description**|
|---|---|---|---|---|---|
|PA30|1|PU|GPIOA30|I/O|general-purpose digital input output pin|
||||ACMP1P|AI|analog comparator 1 positive input|
||||ETM_TRACEDAT3|O|ETM trace data output bit 3|
||||CTIMER3_MAT1|O|timer 3 match output 1|
||||FC2_SCK|I/O|flexcomm 2: SPI clock|
||||FC3_MOSI|I/O|flexcomm 3: SPI MOSI|
||||SPIFI_IO3|I/O|data bit 3 for the SPI flash interface|
QN9080-001-M17
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors B.V. 2018. All rights reserved.
**Objective data sheet**
**9 of 39**
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**Table 5. Pin description** _…continued_
|**Symbol**|**LFLGA54**|**Reset**<br>**state**<br>**[1]**|**Alternate function**|**Type**|**Description**|
|---|---|---|---|---|---|
|PA29|2|PU|GPIOA29|I/O|general-purpose digital input output pin|
||||ACMP1N|AI|analog comparator 1 negative input|
||||ETM_TRACEDAT2|O|ETM trace data output bit 2|
||||CTIMER3_MAT0|O|timer 3 match output 0|
||||FC2_SCK|I/O|flexcomm 2: SPI clock|
||||FC3_MISO|I/O|flexcomm 3: SPI MISO|
||||SPIFI_IO2|I/O|data bit 2 for the SPI flash interface|
|PA28|3|PU|GPIOA28|I/O|general-purpose digital input output pin|
||||CLK_AHB|O|AHB clock output|
||||ETM_TRACECLK|O|ETM trace clock output|
||||RTC_CAP|I|RTC capture input|
||||FC1_SCK|I/O|flexcomm 1: USART clock|
||||SD_DAC|O|sigma-delta modulator DAC output|
||||SPIFI_CSN|O|active low chip select output for the SPI flash interface|
|PA27|4|PU|GPIOA27|I/O|general-purpose digital input output pin|
||||USB_DM|I/O|USB0 bidirectional D- line|
||||SCT0_IN1|I|SCTimer input 1|
||||CTIMER1_MAT2|O|32-bit CTimer 1 match output 2|
||||FC2_SCL_MISO|I/O|flexcomm 2: I2C SCL, SPI MISO|
||||QDEC0_B|I|quadrature decoder 0 input channel B|
||||BLE_IN_PROC|O|BLE event in process indicator for coexistence|
|PA26|5|PU|GPIOA26|I/O|general-purpose digital input output pin|
||||USB_DP|I/O|USB0 bidirectional D+ line|
||||SCT0_IN0|I|SCTimer input 0|
||||CTIMER1_MAT0|O|32-bit CTimer 1 match output 0|
||||FC2_SDA_MOSI|I/O|flexcomm 2: I2C SDA, SPI MOSI|
||||QDEC0_A|I|quadrature decoder 0 input channel A|
||||BLE_SYNC|O|BLE sync pulse|
|LB|6|||RF|NTAG antenna/coil terminal B|
|LA|7|||RF|NTAG antenna/coil terminal A|
|PA25|8|PU|GPIOA25|I/O|general-purpose digital input output pin|
||||ACMP0P/CS7|AI|analog comparator 0 positive input, or capacitive touch sense<br>button input 7|
||||ETM_TRACEDAT1|O|ETM trace data output bit 1|
||||CTIMER3_CAP1|I|timer 3 input capture 1|
||||RFE_TX_EN|O|TX enable for external RF front-end|
||||FC3_SSEL0|I/O|flexcomm 3: SPI SSEL0|
||||SPIFI_IO1|I/O|data bit 1 for the SPI flash interface|
QN9080-001-M17
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors B.V. 2018. All rights reserved.
**Objective data sheet**
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**Table 5. Pin description** _…continued_
|**Symbol**|**LFLGA54**|**Reset**<br>**state**<br>**[1]**|**Alternate function**|**Type**|**Description**|
|---|---|---|---|---|---|
|PA24|9|PU|GPIOA24|I/O|general-purpose digital input output pin|
||||ACMP0N/CS6|AI|analog comparator 0 negative input, or capacitive touch<br>sense button input 6|
||||ETM_TRACEDAT0|O|ETM trace data output bit 0|
||||CTIMER3_CAP0|I|timer 3 input capture 0|
||||RFE_RX_EN|O|RX enable for external RF front-end|
||||FC3_SSEL1|I/O|flexcomm 3: SPI SSEL1|
||||SPIFI_IO0|I/O|data bit 0 for the SPI flash interface|
|SWDIO/<br>PA23|10|PU|SWDIO|I/O|serial wire debug I/O; it is the default function after booting|
||||GPIOA23|I/O|general-purpose digital input output pin|
||||SCT0_IN3|I|SCTimer input 3|
||||CTIMER3_MAT1|O|32-bit CTimer 3 match output 1|
||||FC2_SCL_SSEL1|I/O|flexcomm 2: I2C SCL, SPI SSEL1|
||||FC3_SSEL2|I/O|flexcomm 3: SPI SSEL2|
||||QDEC1_B|I|quadrature decoder 1 input channel B|
|SWCLK<br>/PA22|11|PU|SWCLK|I/O|serial wire clock; it is the default function after reset|
||||GPIOA22|I/O|general-purpose digital input output pin|
||||SCT0_IN2|I|SCTimer input 2|
||||CTIMER3_MAT0|O|32-bit CTimer 3 match output 0|
||||FC2_SDA_SSEL0|I/O|flexcomm 2: I2C SDA, SPI SSEL0|
||||FC3_SSEL3|I/O|flexcomm 3: SPI SSEL3|
||||QDEC1_A|I|quadrature decoder 1 input channel A|
|PA21|12|PU|GPIOA21|I/O|general-purpose digital input output pin|
||||QDEC1_B|I|quadrature decoder 1 input channel B|
||||SCT0_OUT0|O|SCTimer output 0, PWM output 0|
||||CTIMER2_MAT1|O|32-bit CTimer 2 match output 1|
||||FC2_SSEL3|I/O|flexcomm 2: SPI SSEL3|
||||FC1_CTS_SDA|I/O|flexcomm 1: USART CTS, I2C SDA|
||||SPIFI_CSN|O|active low chip select output for the SPI flash interface|
|PA20|13|PU|GPIOA20|I/O|general-purpose digital input output pin|
||||QDEC1_A|I|quadrature decoder 1 input channel A|
||||SCT0_OUT1|O|SCTimer output 1, PWM output 1|
||||CTIMER2_MAT0|O|32-bit CTimer 2 match output 0|
||||SWO|I/O|serial wire trace output|
||||FC1_RTS_SCL|I/O|flexcomm 1: USART RTS, I2C SCL|
||||SPIFI_CLK|O|clock output for the SPI flash interface|
QN9080-001-M17 **Objective data sheet**
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors B.V. 2018. All rights reserved.
**11 of 39**
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**QN9080-001-M17**
**Table 5. Pin description** _…continued_
|**Symbol**|**LFLGA54**|**Reset**<br>**state**<br>**[1]**|**Alternate function**|**Type**|**Description**|
|---|---|---|---|---|---|
|PA19|14|PU|GPIOA19|I/O|general-purpose digital input output pin|
||||CS5|AI|capacitive touch sense button input 5|
||||SCT0_OUT2|O|SCTimer output 2, PWM output 2|
||||RFE_EN|O|enable for external RF front-end|
||||FC0_SCK|I/O|flexcomm 0: USART clock|
||||FC3_SSEL3|I/O|flexcomm 3: SPI SSEL3|
||||BLE_IN_PROC|O|BLE event in process indicator for coexistence|
|PA18|15|PU|GPIOA18|I/O|general-purpose digital input output pin|
||||CS4|AI|capacitive touch sense button input 4|
||||SCT0_OUT3|O|SCTimer output 3, PWM output 3|
||||CTIMER2_MAT2|O|32-bit CTimer 2 match output 2|
||||FC0_SCK|I/O|flexcomm 0: USART clock|
||||FC3_SSEL2|I/O|flexcomm 3: SPI SSEL2|
||||BLE_SYNC|O|BLE sync pulse|
|PA17|16|PU|GPIOA17|I/O|general-purpose digital input output pin|
||||CS3|AI|capacitive touch sense button input 3|
||||SD_DAC|O|sigma-delta modulator DAC output|
||||CTIMER2_MAT1|O|32-bit CTimer 2 match output 1|
||||FC0_RXD|I/O|flexcomm 0: USART RXD|
||||FC3_MISO|I/O|flexcomm 3: SPI MISO|
||||QDEC0_B|I|quadrature decoder 0 input channel B|
|PA16|17|PU|GPIOA16|I/O|general-purpose digital input output pin|
||||CS2|AI|capacitive touch sense button input 2|
||||SCT0_OUT1|O|SCTimer output 1, PWM output 1|
||||CTIMER2_MAT0|O|32-bit CTimer 2 match output 0|
||||FC0_TXD|I/O|flexcomm 0: USART TXD|
||||FC3_MOSI|I/O|flexcomm 3: SPI MOSI|
||||QDEC0_A|I|quadrature decoder 0 input channel A|
|PA15|18|PU|GPIOA15|I/O|general-purpose digital input output pin|
||||CS1|AI|capacitive touch sense button input 1|
||||SCT0_OUT0|O|SCTimer output 0, PWM output 0|
||||CTIMER2_CAP1|I|timer 2 input capture 1|
||||FC0_CTS|I/O|flexcomm 0: USART CTS|
||||FC3_SCK|I/O|flexcomm 3: SPI clock|
||||QDEC1_B|I|quadrature decoder 1 input channel B|
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**Table 5. Pin description** _…continued_
|**Symbol**|**LFLGA54**|**Reset**<br>**state**<br>**[1]**|**Alternate function**|**Type**|**Description**|
|---|---|---|---|---|---|
|PA14|19|PU|GPIOA14|I/O|general-purpose digital input output pin|
||||CS0|AI|capacitive touch sense button input 0|
||||ANT_SW|O|external antenna switch for diversity|
||||CTIMER2_CAP0|I|timer 2 input capture 0|
||||FC0_RTS|I/O|flexcomm 0: USART RTS|
||||FC3_SSEL0|I/O|flexcomm 3: SPI SSEL0|
||||QDEC1_A|I|quadrature decoder 1 input channel A|
|PA13|20|PU|GPIOA13|I/O|general-purpose digital input output pin|
||||R|I/O|reserved|
||||SCT0_OUT4|O|SCTimer output 4|
||||ACMP1_OUT|O|analog comparator 1 output|
||||FC1_RXD_SDA|I/O|flexcomm 1: USART RXD, I2C SDA|
||||FC3_SSEL1|I/O|flexcomm 3: SPI SSEL1|
||||RFE_EN|O|enable for external RF front-end|
|CHIP_M<br>ODE/PB<br>02|21|PU|CHIP_MODE|I|boot selection with pull-up by default; it should be pulled low<br>to go through the normal ISP process for firmware<br>programming, otherwise the ISP process is escaped to jump<br>to flash|
||||GPIOB02|I/O|general-purpose digital input output pin|
||||ANT_SW|O|external antenna switch for diversity|
|RSTN|22|PU||I|active low reset input|
|ANT_IN|23|||RF|Internal antenna|
|RF_OU<br>T|24|||RF|RF input output port with Tx or Rx switch integrated on chip|
|GND|25||||ground|
|PA12|26|PU|GPIOA12|I/O|general-purpose digital input output pin|
||||R|O|reserved|
||||SCT0_OUT5|O|SCTimer output 5|
||||ACMP0_OUT|O|analog comparator 0 output|
||||FC1_TXD_SCL|I/O|flexcomm 1: USART TXD, I2C SCL|
||||SD_DAC|O|sigma-delta modulator DAC output|
||||ANT_SW|O|external antenna switch for diversity|
|PA11|27|PU|GPIOA11|I/O|general-purpose digital input output pin|
||||ADC7|AI|ADC external input 7|
||||SCT0_IN3|I|SCTimer input 3|
||||CTIMER1_MAT2|O|32-bit CTimer 1 match output 2|
||||FC2_SSEL2|I/O|flexcomm 2: SPI SSEL2|
||||ACMP1_OUT|O|analog comparator 1 output|
||||BLE_RX|O|BLE reception indicator for coexistence|
QN9080-001-M17
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**Objective data sheet**
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**Table 5. Pin description** _…continued_
|**Symbol**|**LFLGA54**|**Reset**<br>**state**<br>**[1]**|**Alternate function**|**Type**|**Description**|
|---|---|---|---|---|---|
|PA10|28|PU|GPIOA10|I/O|general-purpose digital input output pin|
||||ADC6|AI|ADC external input 6|
||||SCT0_IN2|I|SCTimer input 2|
||||CTIMER1_MAT1|O|32-bit CTimer 1 match output 1|
||||FC1_SCK|I/O|flexcomm 1: USART clock|
||||ACMP0_OUT|O|analog comparator 0 output|
||||BLE_TX|O|BLE transmit indicator for coexistence|
|PA09|29|PU|GPIOA9|I/O|general-purpose digital input output pin|
||||ADC5|AI|ADC external input 5|
||||SCT0_IN1|I|SCTimer input 1|
||||CTIMER1_MAT0|O|32-bit CTimer 1 match output 0|
||||FC1_RXD_SDA|I/O|flexcomm 1: USART RXD, I2C SDA|
||||BLE_PTI3|O|BLE packet traffic information bit 3|
||||SPIFI_IO3|I/O|data bit 3 for the SPI flash interface|
|PA08|30|PU|GPIOA8|I/O|general-purpose digital input output pin|
||||ADC4|AI|ADC external input 4|
||||SCT0_IN0|I|SCTimer input 0|
||||CTIMER1_CAP1|I|timer 1 input capture 1|
||||FC1_TXD_SCL|I/O|flexcomm 1: USART TXD, I2C SCL|
||||BLE_PTI2|O|BLE packet traffic information 2|
||||SPIFI_IO2|I/O|data bit 2 for the SPI flash interface|
|PA07|31|PU|GPIOA7|I/O|general-purpose digital input output pin|
||||ADC_VREFI|AI|ADC external reference voltage input|
||||SCT0_OUT2|O|SCTimer output 2|
||||CTIMER1_CAP0|I|timer 1 input capture 0|
||||FC1_CTS_SDA|I/O|flexcomm 1: USART CTS, I2C SDA|
||||BLE_PTI1|O|BLE packet traffic information 1|
||||SPIFI_CSN|O|active low chip select output for the SPI flash interface|
|PA06|32|PU|GPIOA6|I/O|general-purpose digital input output pin|
||||ADC_EX_CAP|A|connected with ADC external capacitor|
||||SCT0_OUT3|O|SCTimer output 3|
||||CTIMER0_MAT2|O|32-bit CTimer 0 match output 2|
||||FC1_RTS_SCL|I/O|flexcomm 1: USART RTS, I2C SCL|
||||BLE_PTI0|O|BLE packet traffic information bit 0|
||||SPIFI_CLK|O|clock output for the SPI flash interface|
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**Table 5. Pin description** _…continued_
|**Symbol**|**LFLGA54**|**Reset**<br>**state**<br>**[1]**|**Alternate function**|**Type**|**Description**|
|---|---|---|---|---|---|
|PA05|33|PU|GPIOA5|I/O|general-purpose digital input output pin|
||||ADC3|AI|ADC external input 3|
||||SCT0_OUT5|O|SCTimer output 5|
||||CTIMER0_MAT1|O|32-bit CTimer 0 match output 1|
||||FC0_RXD|I/O|flexcomm 0: USART RXD|
||||FC2_SCL_MISO|I/O|flexcomm 2: SCL, SPI MISO|
||||SPIF_IO1|I/O|data bit 1 for the SPI flash interface|
|PA04|34|PU|GPIOA4|I/O|general-purpose digital input output pin|
||||ADC2|AI|ADC external input 2|
||||SCT0_OUT4|O|SCTimer output 4|
||||CTIMER0_MAT0|O|32-bit CTimer 0 match output 0|
||||FC0_TXD|I/O|flexcomm 0: USART TXD|
||||FC2_SDA_MOSI|I/O|flexcomm 2: I2C SDA, SPI MOSI|
||||SPIF_IO0|I/O|data bit 0 for the SPI flash interface|
|PA03|35|PU|GPIOA3|I/O|general-purpose digital input output pin|
||||QDEC0_B|I|quadrature decoder 0 input channel B|
||||SCT0_OUT3|O|SCTimer output 3|
||||CTIMER0_MAT1|O|32-bit CTimer 0 match output 1|
||||R|O|reserved|
||||FC2_SDA_SSEL0|I/O|flexcomm 2: I2C SDA, SPI SSEL0|
||||RFE_TX_EN|O|TX enable for external RF front-end|
|PA02|36|PU|GPIOA2|I/O|general-purpose digital input output pin|
||||QDEC0_A|I|quadrature decoder 0 input channel A|
||||SCT0_OUT2|O|SCTimer output 2|
||||CTIMER0_MAT0|O|32-bit CTimer 0 match output 0|
||||R|I/O|reserved|
||||FC2_SCL_SSEL1|I/O|flexcomm 2: I2C SCL, SPI SSEL1|
||||RFE_RX_EN|O|RX enable for external RF front-end|
|NTAG_<br>FD|37|||O|field detection|
|VCC|38||||power supply|
|NTAG_<br>VCC|39||||NTAG power supply|
|VOUT|40||||output supply voltage(energy harvesting)|
|VSS1|41||||ground|
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**Table 5. Pin description** _…continued_
|**Symbol**|**LFLGA54**|**Reset**<br>**state**<br>**[1]**|**Alternate function**|**Type**|**Description**|
|---|---|---|---|---|---|
|PA01|42|PU|GPIOA1|I/O|general-purpose digital input output pin|
||||ADC1|AI|ADC external input 1|
||||SCT0_OUT1|O|SCTimer output 1|
||||CTIMER0_CAP1|I|32-bit CTimer 0 capture input 1|
||||FC0_CTS|I/O|flexcomm 0: USART CTS|
||||FC2_SSEL2|I/O|flexcomm 2: SPI SSEL2|
||||WLAN_RX|I|WLAN active high RX active indicator for coexistence|
|PA00|43|PU|GPIOA0|I/O|general-purpose digital input output pin|
||||ADC0|AI|ADC external input 0|
||||SCT0_OUT0|O|SCTimer output 0|
||||CTIMER0_CAP0|I|32-bit CTimer 0 capture input 0|
||||FC0_RTS|I/O|flexcomm 0: USART RTS|
||||FC2_SSEL3|I/O|flexcomm 2: SPI SSEL3|
||||WLAN_TX|I|WLAN active high TX active indicator for coexistence|
|PA31|44|PU|GPIOA31|I/O|general-purpose digital input output pin|
||||DAC|AO|DAC analog output|
||||RTC_CAP|I|RTC capture input|
||||CTIMER3_MAT2|O|Timer 3 match output 2|
||||SWO|I/O|serial wire trace output|
||||FC3_SCK|I/O|flexcomm 3: SPI clock|
||||SPIFI_CLK|O|clock output for the SPI flash interface|
|GND|45||||ground|
|GND|46||||ground|
|GND|47||||ground|
|ANT_Pi<br>n3|48||||Internal antenna ground|
|ANT_Pi<br>n2|49||||Internal antenna ground|
|ANT_Pi<br>n1|50||||Internal antenna ground|
|GND|51||||ground|
|GND|52||||ground|
|GND|53||||ground|
|GND|54||||ground|
[1] PU = input mode, pull-up enabled (pull-up resistor pulls up pin to VCC). Z = high impedance; pull-up or pull-down disabled, AI = analog input, AO = analog output, I = input, O = output, F = floating. Reset state reflects the pin state at reset without boot code operation.
## **7.2.1 Termination of unused pins**
Table 6 shows how to terminate pins that are not used in the application. In many cases, unused pins should be connected externally or configured correctly by software to minimize the overall power consumption of the part.
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Unused pins with GPIO function should be configured as outputs LOW with their internal pull-up disabled. To configure a GPIO pin as output and drive it LOW, select the GPIO function in the IOCON register, select output in the GPIO DIR register, and write a 0 to the GPIO PORT register for that pin. Disable the pull-up in the pin's IOCON register.
In addition, it is recommended to configure all GPIO pins that are not bonded out on smaller packages as outputs driven LOW with their internal pull-up disabled.
## **Table 6. Termination of unused pins**
|**Pin**|**Default**<br>**stat**~~**e**~~<br>**[1]**|**Recommended termination of unused pins**|
|---|---|---|
|RSTN|I; PU|the RSTN pin can be left unconnected if the application does<br>not use it.|
|all PAnm|I; PU|can be left unconnected if driven LOW and configured as<br>GPIO output with pull-up disabled by software|
|CHIP_MODE|I; PU|can be left unconnected if driven LOW and configured as<br>GPIO output with pull-up disabled by software|
- [1] I = Input, IA = Inactive (no pull-up/pull-down enabled), PU = Pull-Up enabled.
## **7.2.2 Pin states in different power modes**
**Table 7. Pin states in different power modes Pin Active - Sleep - Power Down modes** all PAnm As configured in the SYSCON[1] ~~.~~ Default: internal pull-up enabled. RSTN Reset function enabled. Default: input, internal pull-up enabled —=<=_$ ~~_~~ [__——— [1] Default and programmed pin states are retained in sleep, and power-down mode.
## **8. Compliance statements and documentation**
- The FCC ID number of the QN9080-001-M17 is XXMQN9080M17
- The IC ID number of the QN9080-001-M17 is 8764A-QN9080M17
- The Japan ID number of the QN9080-001-M17 is
**==> picture [27 x 5] intentionally omitted <==**
**----- Start of picture text -----**<br>
207-990010<br>**----- End of picture text -----**<br>
## **8.1 FCC Statements and documentation**
This section contains the Federal Communication Commission (FCC) statements and documents.
## **8.1.1 FCC interference Statements**
- This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one of the following measures:
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- Reorient or relocate the receiving antenna
- Increase the separation between the equipment and receiver
- Connect the equipment into an outlet on a circuit different from that to which the receiver is connected
- Consult the dealer or an experienced radio/TV technician for help
- OEM integrators instructions
- The OEM integrators are responsible for ensuring that the end-user has no manual instructions to remove or install SIP
- The SIP is limited to installation in mobile or fixed applications, according to CFR 47 Part 2.1091(b)
- Separate approval is required for all other operating configurations, including portable configurations with respect to CFR 47 Part 2.1093 and different antenna configurations
- User guide mandatory statements
User's instructions of the host device must contain the following statements in addition to operation instructions:
* "This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions:
- (1) This device may not cause harmful interference, and
(2) This device must accept any interference received, including interference that may cause undesired operation"
* "Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment"
- FCC RF Exposure requirements
User's instructions of the host device must contain the following instructions in
addition to operation instructions:
Avoid direct contact to the antenna, or keep it to a 20cm minimum distance while using this equipment. This device must not be collocated or operating in conjunction with another antenna or transmitter.
This SIP has been designed to operate etheir with internal antenna or with external antennas having a maximum gain of 2 dBi. Antennas having a gain greater than 2 dBi are strictly prohibited for use with this device. The required antenna impedance is 50 ohms
## **8.1.2 FCC end product labelling**
The final 'end product' should be labelled in a visible area with the following: "Contains TX FCC ID: XXMQN9080M17 to reflect the SIP being used inside the product.
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## **8.2 Industry Canada Statement**
This device complies with Industry Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device.
This device complies with Industry Canada RF radiation exposure limits set forth for general population (uncontrolled exposure). This device must be installed to provide a separation distance of at least 20 cm from all persons and must not be collocated or operating in conjunction with any other antenna or transmitter.
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est autorisée aux deux conditions suivantes : (1) il ne doit pas produire de brouillage, et (2) l'utilisateur du dispositif doit être prêt à accepter tout brouillage radioélectrique re?u, même si ce brouillage est susceptible de compromettre le fonctionnement du dispositif.
Le présent appareil est conforme aux niveaux limites d'exigences d'exposition RF aux personnes définies par Industrie Canada. Cet appareil doit être installé afin d'offrir une distance de séparation d'au moins 20 cm avec l'utilisateur, et ne doit pas être installé à proximité ou être utilisé en conjonction avec une autre antenne ou un autre émetteur.
To reduce potential radio interference to other users, the antenna type and its gain should be so chosen that the equivalent isotropic radiated power (e.i.r.p.) is not more than that permitted for successful communication.
The Gain of SIP with internal antenna is -3dBi.
If customer wants, he can also use the SIP with external antenna with maximum gain of 2dbi. This feature is not certified by NXP and need to be done by the customer. Antennas having a gain greater than 2 dBi are strictly prohibited for use with this device. The required antenna impedance is 50 ohms.
As long as the above condition is met, further transmitter testing will not be required.
However, the OEM integrator is still responsible for testing their end-product for any additional compliance requirements required with this SIP installed (for example, digital device emissions, PC peripheral requirements, etc.).
## **8.2.1 Industry of Canada end product labelling**
For Industry Canada purposes the following should be used: "Contains Industry Canada ID IC: 8764A-QN9080M17
## **8.3 Japanese Radio Certification Statement**
This equipment has been tested and found to comply with the Japanese Radio Certification Rules
## **8.3.1 Radio Certification end product labelling**
For Japanese Radio Certification purposes, the following should be used:
"Contains Japanese Radio certificate product: Japan ID number is 207-990010
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## **9. Static characteristics**
## **9.1 General operating conditions**
## **Table 8. General operating conditions**
_Tamb =_ − _40_ ° _C to +85_ ° _C, unless otherwise specified._
|**Symbol**|**Parameter**|**Conditions**|**Min**|**Typ**<br>**[1]**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|fclk|Clock frequency||||32|MHz|
|VCC|Supply voltage||1.67|3|3.6|V|
|VESD|Electrostatic discharge<br>voltage|Human body mode~~l~~<br>[2]~~;~~all pins|||2|kV|
|||Charged device model; all pins|||300|V|
|TJ(max)|Maximum junction<br>temperature||||85|C|
- [1] Typical ratings are not guaranteed. The values listed are for room temperature (25 °C), nominal supply voltages.
- [2] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.
## **9.2 Power consumption**
Power measurements in active, sleep, power down modes were performed under the following conditions:
- All peripherals disabled
- Analog peripherals (ADC/DAC/ACMP/Capacitive Sense) powered down
- RF off
- Internal 32 MHz HFRCO powered down
**Table 9. Static characteristics: Power consumption in active modes** _Tamb =_ − _40_ ° _C to +85_ ° _C, unless otherwise specified._
|**Symbol**|**Parameter**|**Conditions**||**Min**|**Ty**~~**p**~~<br>**[1]**|**Max**|**Unit**|
|---|---|---|---|---|---|---|---|
|32 MHz HFXO; DC-DC converter||enabled, VCC= 3.0 V||||||
|ICC|Supply current|CoreMark code executed from flash||||||
|||CLK_AHB = 16 MHz|[2]||920||A|
- [1] Typical ratings are not guaranteed. Typical values listed are at room temperature (25 °C).
- [2] Characterized through bench measurements using typical samples.
**Table 10. Static characteristics: Bluetooth LE power consumption in active modes** _Tamb =_ − _40_ ° _C to +85_ ° _C, unless otherwise specified._
|**Symbol**|**Parameter**|**Conditions**||**Min**|**Ty**~~**p**~~<br>**[1]**<br>**[2]**|**Ma**~~**x**~~<br>**[3]**|**Unit**|
|---|---|---|---|---|---|---|---|
|32 MHz crystal oscillator, CLK_AHB = 16 MHz, transmitter mode: fc= 2440 MHz, 1 Mbps mode||||||||
|ICC|supply current|DC-to-DC converter enabled, Vcc= 3 V||||||
|||Tx power = 0 dBm|||3.5||mA|
|32 MHz crystal oscillator, CLK_AHB = 16 MHz, transmitter mode: fc= 2440 MHz, 1 Mbps mode||||||||
|ICC|supply current|DC-to-DC converter enabled, Vcc= 3 V||||||
|||-92.7 dBm RX sensitivity|||4||mA|
- [1] Typical ratings are not guaranteed. Typical values listed are at room temperature (25 °C).
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[2] Characterized through bench measurements using typical samples, with 50 loading on RF port. [3] Guaranteed by characterization, not tested in production.
**Table 11. Static characteristics: Power consumption in sleep, and power-down modes** _Tamb =_ − _40_ ° _C to +85_ ° _C; unless otherwise specified._
|**Symbol**<br>ICC|**Parameter**|**Conditions**|**Min**|**Typ**<br>**[1]**<br>**[2]**|**Ma**~~**x**~~<br>**[3]**|**Unit**|
|---|---|---|---|---|---|---|
||Supply current|Sleep mode:<br>all SRAM on. Flash in standby mode. DC-to-DC converter enabled, Vcc= 3 V.|||||
|||32 MHz crystal oscillator|||||
|||CLK_AHB = 16 MHz||470||A|
|||Power down mode; all clocks off.<br>Flash is powered down. DC-DC disabled, Vcc= 3 V. Tamb= 25C.|||||
|||8 KB SRAM powered||1.0||A|
|||Power down mode; 32.768 kHz LFXO on.<br>Flash is powered down. DC-DC disabled, Vcc= 3 V. Tamb= 25C.|||||
|||8 KB SRAM powered||2.5||A|
[1] Typical ratings are not guaranteed. Typical values listed are at room temperature (25 °C).
[2] Characterized through bench measurements using typical samples.
[3] Guaranteed by characterization, not tested in production.
## **9.3 Clock source**
## **Table 12. 32 MHz clock source characteristics**
|**Symbol**|**Parameter**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|fnom|Nominal frequency|||32||MHz|
||Frequency tolerance|at +25°C|-10||+10|ppm|
|CL|Load capacitance|||10||pF|
|Rr|Equivalent resistance||||60||
## **Table 13. 32.768 kHz clock source characteristics**
|**Symbol**|**Parameter**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|fnom|Nominal frequency|||32.768||kHz|
||Frequency tolerance|at +253°C, Not<br>include aging|-20||+20|ppm|
|CL|Load capacitance|||12.5||pF|
|Rr|Equivalent resistance||||120|k|
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## **10. RF characteristics**
## **10.1 Receiver**
**Table 14. Receiver characteristics** _Tamb = 25_ ° _C; based on characterization; not tested in production. VCC = 3 V; fc = 2440 MHz; BER < 0.1 %, 1 Mbps mod_
|**Symbol**|**Parameter**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|SRX|RX sensitivity|low power mode with<br>DC-to-DC converter||92.7||dBm|
|Pi(max)|maximum input<br>power|||0||dBm|
|C/~~I~~<br>[1]|carrier-to-interfere<br>nce ratio|co-channel||6||dB|
|||adjacent channel at1 MHz||4||dB|
|||alternate channel at2 MHz||41||dB|
|imag~~e~~<br>[1]|image rejection|||41||dB|
|sup(oob~~)~~<br>[1]|out-of-band<br>suppression|30 MHz to 2000 MHz|1|||dBm|
|||2003 MHz to 2399 MHz|10|||dBm|
|||2484 MHz to 2997 MHz|10|||dBm|
|||3 GHz to 12.75 GHz|10|||dBm|
[1] The values of these parameters are from QN9080 data sheet
## **10.2 Transmitter**
## **Table 15. Transmitter characteristics** _Tamb = 25_ ° _C; based on QN9080 characterization; not tested in production.VCC = 3 V; fc = 2440 MHz_
|**Symbol**|**Parameter**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|fo(RF)|RF output<br>frequency||2400||2483.5|MHz|
|CS|channel<br>separation|||2||MHz|
|Po|output power|TX power<br>20|||+2|dBm|
|Po(RF)step|RF output power<br>step|||1||dB|
|Po(acc)|TX power<br>accuracy||2||+2|dB|
**Remark:** The QN9080-001-M17 is a fully certified device supporting Bluetooth 5.0. There is a marginality (5% drift compare to the Min value of 185 kHz) on frequency deviation df2 99.9% at -40°C.
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## **11. Internal antenna characteristic**
**Table 16. BOD static characteristics** _Tamb = 25_ ° _C; based on characterization; not tested in production._
|**Parameter**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|
|Frequency range|2400||2480|MHz|
|Impedance||50|||
|Peak gain||0.5||dBi|
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## **12. Layout guideline**
## **12.1 Footprint information for reflow soldering**
**==> picture [460 x 369] intentionally omitted <==**
## **Fig 5. Footprint information for reflow soldering of SIPs**
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**12.2 Layout recommendation for ground plane implementation and clearance area for QN9080-001-M17 with integrated 2.4 GHz antenna**
**==> picture [363 x 242] intentionally omitted <==**
**----- Start of picture text -----**<br>
Antenna Clearance Module + Antenna<br>Physical View<br>On EVB(mm) Clearance(mm)<br>4.65<br>4<br>J<br>Scenario<br>#A<br>(Center 13.7<br>Edge)<br>0.55<br>6.55<br>6.55<br>4 x 4.65 mm 13.7x 6.55 mm<br>7.5<br>3.75<br>13.45<br>Scenario<br>#B 7.5<br>(Corner)<br>samecnnaal S vunnnomend |<br>7.5 x 3.75 mm 13.45 x 7.5 mm<br>**----- End of picture text -----**<br>
**Fig 6. QN9080-001-M17 chip with integrated 2.4 GHz antenna / SIP clearance size (top view)**
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## **12.2.1 Center edge PCB ground plane design**
## Integrated 2.4 GHz antenna function pin
**==> picture [53 x 13] intentionally omitted <==**
**----- Start of picture text -----**<br>
9.7mm<br>**----- End of picture text -----**<br>
**Fig 7. QN9080-001-M17 module on 36 mm x 31 mm PCB layout guide- center edge**
- Do not route signal trace across antenna clearance area
- Connect pin 49 to Upper GND, pin 50 to lower GND
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**==> picture [384 x 233] intentionally omitted <==**
**----- Start of picture text -----**<br>
10.5mm<br>Pin49<br>3.5mm Trace ≥ 36mm<br>Pin50<br>route<br>Trace<br>route<br>0.55mm<br>Trace<br>route Lower GND<br>≥ 31mm<br>Upper GND<br>**----- End of picture text -----**<br>
**Fig 8. QN9080-001-M17 module on 36 mm x 31 mm GND PCB layout guide - center edge - clearance area**
**==> picture [207 x 173] intentionally omitted <==**
**----- Start of picture text -----**<br>
A B<br>Parameter Units : mm<br>A 1.25<br>B 2.9<br>C 5.5<br>C D 0.38<br>E 0.55<br>D F 0.25<br>E<br>F<br>Layer 1<br>**----- End of picture text -----**<br>
**==> picture [186 x 171] intentionally omitted <==**
**----- Start of picture text -----**<br>
G<br>H<br>Antenna Clearance Area<br>I<br>Parameter Units : mm<br>G 0.5<br>H 0.5<br>I 3.5<br>Layer 1<br>Upper GND<br>Lower GND<br>**----- End of picture text -----**<br>
**Fig 9. QN9080-001-M17 module on 36 mm x 31 mm GND PCB layout guide - center edge - clearance area layer 1 dimensions**
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**==> picture [408 x 111] intentionally omitted <==**
**----- Start of picture text -----**<br>
J<br>Antenna Clearance Area<br>Parameter Units : mm<br>L<br>J 4.15<br>K K 2<br>L 5.5<br>**----- End of picture text -----**<br>
Layer 2,3,4
**Fig 10. QN9080-001-M17 module on 36 mm x 31 mm GND PCB layout guide - center edge - clearance area layers 2, 3, 4 dimensions**
QN9080-001-M17
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## **12.2.2 Corner EVB ground plane design**
**==> picture [159 x 12] intentionally omitted <==**
**----- Start of picture text -----**<br>
Antenna Function Pin<br>**----- End of picture text -----**<br>
**==> picture [165 x 168] intentionally omitted <==**
**----- Start of picture text -----**<br>
9.7mm<br>Dp<br>[J a<br>D<br>D<br>[J o<br>Dp<br>Dp<br>Dp<br>6 mm<br>**----- End of picture text -----**<br>
**Fig 11. QN9080-001-M17 module on 36 mm x 31 mm PCB layout guide - corner**
- Do not route signal trace across antenna clearance area
- Connect pin 48 to antenna trace
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**==> picture [324 x 232] intentionally omitted <==**
**----- Start of picture text -----**<br>
3.5mm<br>Ant. Trace<br>Trace<br>route<br>Trace<br>Pin48<br>route<br>≥ 31mm<br>0.25mm<br>Trace<br>route<br>≥ 36mm<br>Layer 1<br>**----- End of picture text -----**<br>
**Fig 12. QN9080-001-M17 module on 36 mm x 31 mm GND PCB layout guide - corner - clearance area**
**==> picture [474 x 203] intentionally omitted <==**
**----- Start of picture text -----**<br>
L<br>A C D<br>B<br>Antenna Clearance Area<br>Parameter Units : mm<br>I E A 0.5 O M Parameter Units : mm<br>F B 4.34 L 6.75<br>H C 0.5 N M 3.5<br>G D 1 N 2<br>E 1.5 O 2.9<br>F 1.5<br>G 2<br>J H 2.9<br>I 3.5<br>J 0.25<br>K<br>K 0.25<br>Layer 1 Layer 1<br>Fig 13. QN9080-001-M17 module on 36 mm x 31 mm GND PCB layout guide - corner - clearance area layer 1<br>dimensions<br>**----- End of picture text -----**<br>
QN9080-001-M17
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**==> picture [409 x 154] intentionally omitted <==**
**----- Start of picture text -----**<br>
P<br>Antenna Clearance Area<br>R<br>S<br>Parameter Units : mm<br>Q<br>P 6.75<br>Q 2<br>R 2.9<br>S 5.5<br>**----- End of picture text -----**<br>
Layer 2,3,4
**Fig 14. QN9080-001-M17 module on 36 mm x 31 mm GND PCB layout guide - corner - clearance area layers 2, 3, 4 dimensions**
## **12.3 Reflow profile**
QN9080-001-M17 is an MSL3 and PSL R5G product. PSL has been defined based on the standard J-STD-075. For reflow soldering, it is requested to follow the reflow profile and the paste manufacturer's guidelines on peak flow temperature, soak times, time above liquid and ramp rates.
## **12.4**
**Table 17. Recommended solder reflow profile Temperature range Time** Peak temperature: 255 C 10 s Max. Heating: 230 C or higher 30 s Max. Preheating: 150 C to 180 C 60-120 s ~~_—~~ **Soldering paste and cleaning** NXP does not recommend to use a solder paste that requires the module and PCB assembly to be cleaned (rinsed in water) for the following reasons:
- Solder flux residues and water can be trapped by the PCB, can or components and result in short circuits
NXP recommends to use a 'no clean' solder paste for all its module products.
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## **13. Package outline**
**==> picture [186 x 211] intentionally omitted <==**
**==> picture [182 x 173] intentionally omitted <==**
**Fig 15. Package outline LFLGA54 (SOT1910-1)**
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## **14. Abbreviations**
**Table 18. Abbreviations**
|**Acronym**|**Description**|
|---|---|
|ADC|Analog to Digital Converter|
|AES|Advanced Encryption Standard|
|API|Application Program Interface|
|CLK|CLocK|
|CRC|Cyclic redundancy Check|
|CTS|Clear-To-Send|
|DC|Direct current|
|DIO|Digital Input Output|
|DMA|Direct memory Access|
|EEPROM|Electrically-Erasable Programmable Read Only Memory|
|FIFO|First In First Out|
|GPIO|General Purpose Input Output|
|ID|IDentification|
|IF|Intermediate frequency|
|IO|Input Output|
|MSL|Moisture sensitivity level|
|NVIC|Nested Vector Interrupt Controller|
|PCB|Printed-Circuit Board|
|PHY|PHYsical|
|POR|Power-On Reset|
|PWM|Pulse Width Modulation|
|RAM|Random Access Memory|
|RC|Remote Control|
|RF|Radio Frequency|
|RoHS|Restriction of Hazardous Substances|
|RSSI|Receive Signal Strength Indication|
|RTS|Request-To-Send|
|RX|Received|
|SCL|Serial CLock|
|SDA|Serial DatA|
|SMDs|Surface Mount Devices|
|SPI-bus|Serial Peripheral Interface -bus|
|SysTick|System Tick timer|
|TX|Transmit|
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## **15. References**
- **[1] IEEE Std 802.15.4-2011 IEEE Standard for Information Technology Part 15.4 —** Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications for Low-Rate Wireless Personal Area Networks (LR-WPANs).
- **[2] Wireless Connectivity —** http://www.nxp.com/products/wireless-connectivity:WIRELESS-CONNECTIVITY
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## **16. Revision history**
|**Table 19.**<br>**Revision history**|**Table 19.**<br>**Revision history**|**Table 19.**<br>**Revision history**|**Table 19.**<br>**Revision history**|**Table 19.**<br>**Revision history**|
|---|---|---|---|---|
|**Document ID**|**Release date**|**Data sheet status**|**Change notice**|**Supersedes**|
|QN9080-001-M17 v1.0|20181205|Objective data sheet|Public release|-|
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## **17. Legal information**
## **17.1 Data sheet status**
|**Document status**<br>**[1]**<br>**[2]**|**Product status**<br>**[3]**|**Definition**|
|---|---|---|
|Objective [short] data sheet|Development|This document contains data from the objective specification for product development.|
|Preliminary [short] data sheet|Qualification|This document contains data from the preliminary specification.|
|Product [short] data sheet|Production|This document contains the product specification.|
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
## **17.2 Definitions**
**Draft —** The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.
**Short data sheet —** A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
**Product specification —** The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
## **17.3 Disclaimers**
**Limited warranty and liability —** Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the _Terms and conditions of commercial sale_ of NXP Semiconductors.
**Right to make changes —** NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.
**Suitability for use —** NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.
**Applications —** Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products.
NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect.
**Limiting values —** Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.
**Terms and conditions of commercial sale —** NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.
**No offer to sell or license —** Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
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## **NXP Semiconductors**
**Export control —** This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities.
**Quick reference data —** The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.
**Non-automotive qualified products —** Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.
**Translations —** A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.
## **17.4 Trademarks**
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
**I[2] C-bus —** logo is a trademark of NXP Semiconductors N.V.
## **18. Contact information**
For more information, please visit: **http://www.nxp.com**
For sales office addresses, please send an email to: **salesaddresses@nxp.com**
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## **19. Tables**
|Table|1.|Ordering information . . . . . . . . . . . . . . . . . . . . .5|
|---|---|---|
|Table|2.|Ordering options . . . . . . . . . . . . . . . . . . . . . . . .6|
|Table|3.|Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .6|
|Table|4.|Device revision table. . . . . . . . . . . . . . . . . . . . . .6|
|Table|5.|Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .9|
|Table|6.|Termination of unused pins. . . . . . . . . . . . . . . .17|
|Table|7.|Pin states in different power modes . . . . . . . . .17|
|Table|8.|General operating conditions . . . . . . . . . . . . . .20|
|Table|9.|Static characteristics: Power consumption in|
|||active modes. . . . . . . . . . . . . . . . . . . . . . . . . . .20|
|Table|10.|Static characteristics: Bluetooth LE power|
consumption in active modes. . . . . . . . . . . . . . 20 Table 11. Static characteristics: Power consumption in sleep, and power-down modes . . . . . . . . . . . . 21 Table 12. 32 MHz clock source characteristics . . . . . . . . 21 Table 13. 32.768 kHz clock source characteristics . . . . . 21 Table 14. Receiver characteristics. . . . . . . . . . . . . . . . . . 22 Table 15. Transmitter characteristics . . . . . . . . . . . . . . . . 22 Table 16. BOD static characteristics . . . . . . . . . . . . . . . . 23 Table 17. Recommended solder reflow profile. . . . . . . . . 31 Table 18. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 19. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 35
## **20. Figures**
- Fig 1. QN9080-001-M17 package marking . . . . . . . . . . .6 Fig 2. QN9080-001-M17 – high level HW block diagram7 Fig 3. QN9080-001-M17 block diagram using external antenna . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
- Fig 4. QN9080-001-M17 pinout diagram . . . . . . . . . . . . .9 Fig 5. Footprint information for reflow soldering of SIPs 24 Fig 6. QN9080-001-M17 chip with integrated 2.4 GHz antenna / SIP clearance size (top view). . . . . . . .25
- Fig 7. QN9080-001-M17 module on 36 mm x 31 mm PCB layout guide- center edge . . . . . . . . . . . . . . . . . .26
- Fig 8. QN9080-001-M17 module on 36 mm x 31 mm GND PCB layout guide - center edge - clearance area 27
- Fig 9. QN9080-001-M17 module on 36 mm x 31 mm GND PCB layout guide - center edge - clearance area layer 1 dimensions . . . . . . . . . . . . . . . . . . . . . . .27
- PCB layout guide - center edge - clearance area layers 2, 3, 4 dimensions. . . . . . . . . . . . . . . . . . . 28
- Fig 11. QN9080-001-M17 module on 36 mm x 31 mm PCB layout guide - corner . . . . . . . . . . . . . . . . . . . . . . 29
- Fig 12. QN9080-001-M17 module on 36 mm x 31 mm GND PCB layout guide - corner - clearance area . . . . 30
- Fig 13. QN9080-001-M17 module on 36 mm x 31 mm GND PCB layout guide - corner - clearance area layer 1 dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
- Fig 14. QN9080-001-M17 module on 36 mm x 31 mm GND PCB layout guide - corner - clearance area layers 2, 3, 4 dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . 31
- Fig 15. Package outline LFLGA54 (SOT1910-1) . . . . . . 32
- Fig 10. QN9080-001-M17 module on 36 mm x 31 mm GND
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© NXP Semiconductors B.V. 2018. All rights reserved.
**38 of 39**
**Rev. 1.0 — 5 December 2018**
**Ultra Low-Power Bluetooth Smart**
**NXP Semiconductors**
**QN9080-001-M17**
## **21. Contents**
|**1**|**General description . . . . . . . . . . . . . . . . . . . . . . 1**|
|---|---|
|**2**|**Features and benefits . . . . . . . . . . . . . . . . . . . . 1**|
|2.1|Feature of QN9080. . . . . . . . . . . . . . . . . . . . . . 2|
|2.2|Features of NTAG. . . . . . . . . . . . . . . . . . . . . . . 4|
|2.3|Features of integrated 2.4 GHz antenna . . . . . 5|
|**3**|**Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5**|
|**4**|**Ordering information. . . . . . . . . . . . . . . . . . . . . 5**|
|**5**|**Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6**|
|**6**|**Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 7**|
|**7**|**Pinning information. . . . . . . . . . . . . . . . . . . . . . 9**|
|7.1|Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9|
|7.2|Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 9|
|7.2.1|Termination of unused pins. . . . . . . . . . . . . . . 16|
|7.2.2|Pin states in different power modes . . . . . . . . 17|
|**8**|**Compliance statements and documentation 17**|
|8.1|FCC Statements and documentation . . . . . . . 17|
|8.1.1|FCC interference Statements . . . . . . . . . . . . . 17|
|8.1.2|FCC end product labelling . . . . . . . . . . . . . . . 18|
|8.2|Industry Canada Statement . . . . . . . . . . . . . . 19|
|8.2.1|. . . .Industry of Canada end product labelling 19|
|8.3|Japanese Radio Certification Statement . . . . 19|
|8.3.1|Radio Certification end product labelling . . . . 19|
|**9**|**Static characteristics. . . . . . . . . . . . . . . . . . . . 20**|
|9.1|General operating conditions . . . . . . . . . . . . . 20|
|9.2|Power consumption . . . . . . . . . . . . . . . . . . . . 20|
|9.3|Clock source. . . . . . . . . . . . . . . . . . . . . . . . . . 21|
|**10**|**RF characteristics . . . . . . . . . . . . . . . . . . . . . . 22**|
|10.1|Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22|
|---|---|
|10.2|Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . 22|
|**11**|**Internal antenna characteristic . . . . . . . . . . . 23**|
|**12**|**Layout guideline . . . . . . . . . . . . . . . . . . . . . . . 24**|
|12.1|Footprint information for reflow soldering. . . . 24|
|12.2|Layout recommendation for ground plane|
||implementation and clearance area for|
||QN9080-001-M17 with integrated 2.4 GHz|
||antenna . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25|
|12.2.1|Center edge PCB ground plane design . . . . . 26|
|12.2.2|Corner EVB ground plane design . . . . . . . . . 29|
|12.3|Reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . 31|
|12.4|Soldering paste and cleaning. . . . . . . . . . . . . 31|
|**13**|**Package outline. . . . . . . . . . . . . . . . . . . . . . . . 32**|
|**14**|**Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 33**|
|**15**|**References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 34**|
|**16**|**Revision history . . . . . . . . . . . . . . . . . . . . . . . 35**|
|**17**|**Legal information . . . . . . . . . . . . . . . . . . . . . . 36**|
|17.1|Data sheet status . . . . . . . . . . . . . . . . . . . . . . 36|
|17.2|Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 36|
|17.3|Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 36|
|17.4|Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 37|
|**18**|**Contact information . . . . . . . . . . . . . . . . . . . . 37**|
|**19**|**Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38**|
|**20**|**Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38**|
|**21**|**Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39**|
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.
**© NXP Semiconductors B.V. 2018.**
**All rights reserved.**
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
**Date of release: 5 December 2018 Document identifier: QN9080-001-M17**
Updated at April 28, 2026
NXP Semiconductors is a global leader in secure connectivity solutions, driving innovation across the automotive, industrial, IoT, mobile, and communications infrastructure markets. By developing advanced, purpose-built technologies, NXP enables devices to sense, think, connect, and act intelligently, delivering rigorously tested components that make the connected world safer and more efficient. Within the semiconductor space, NXP is highly regarded for its extensive range of high-performance integrated circuits and discrete devices. The brand's portfolio excels in drivers and interfaces, featuring a comprehensive selection of I/O expanders designed to streamline complex system architectures. For demanding high-frequency and wireless applications, NXP provides industry-leading RF FETs and RF/PIN diodes engineered to deliver exceptional signal integrity, efficiency, and reliability. The NXP product lineup further extends to essential discrete components, including versatile bipolar transistors, JFETs, and small signal diodes optimized for precision switching and amplification. Additionally, the portfolio supports advanced automation and smart applications with precision IC sensors, such as MEMS accelerometers, alongside specialized power management solutions like AC/DC LED driver ICs and single MOSFETs for cutting-edge electronics design.
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