PCA9575PW2,118

**16-bit I[2] C-bus and SMBus, level translating, low voltage GPIO with reset and interrupt Rev. 4.2 — 16 April 2015 Product data sheet** 

## **PCA9575** 

**Product data sheet** 

## **1. General description** 

The PCA9575 is a CMOS device that provides 16 bits of General Purpose parallel Input/Output (GPIO) expansion in low voltage processor and handheld battery powered mobile applications and was developed to enhance the NXP family of I[2] C-bus I/O expanders. The improvements include lower supply current, lower operating voltage of 1.1 V to 3.6 V, separate supply rails to allow voltage level translation anywhere between 1.1 V and 3.6 V, 400 kHz clock frequency, and smaller packaging. Any of the 16 I/O ports can be configured as an input or output independent of each other and default on start-up to inputs. 

I/O expanders provide a simple solution when additional I/Os are needed while keeping interconnections to a minimum; for example in battery powered mobile applications and clamshell devices for interfacing to sensors, push buttons, keypad, etc. In addition to providing a flexible set of GPIOs, it simplifies interconnection of a processor running at one voltage level to I/O devices operating at a different (usually higher) voltage level. PCA9575 has built-in level shifting feature that makes these devices extremely flexible in mixed signal environments where communication between incompatible I/Os is required. The core of PCA9575 can operate at a voltage as low as 1.1 V while each I/O bank can operate in the range 1.1 V to 3.6 V. Bus hold with programmable on-chip pull-up or pull-down feature for I/Os is also provided. 

The output stage consists of two banks each of 8-bit configuration registers, input registers, interrupt mask registers, output registers, bus-hold and pull-up/pull-down registers and polarity inversion registers. These registers allow the system master to program and configure 16 GPIOs through the I[2] C-bus. 

The system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration register bits. The data for each input or output is kept in the corresponding Input or Output register. The polarity of the read registers can be inverted with the Polarity Inversion register (active HIGH or active LOW operation). Either a bus-hold function or pull-up/pull-down feature can be selected by programming corresponding registers. The bus-hold provides a valid logic level when the I/O bus is not actively driven. When bus-hold feature is not selected, the I/O ports can be configured to have pull-up or pull-down by programming the pull-up/pull-down configuration register. 

An open-drain interrupt output pin (INT) allows monitoring of the input pins and is asserted each time a change occurs on an input port unless that port is masked (default = masked). A ‘GPIO All Call’ command allows programming multiple PCA9575s at the same time even if they have different individual I[2] C-bus addresses. This command allows optimal code programming when more than one device must be programmed with the same instruction or if all outputs must be turned on or off at the same time. The 

**==> picture [172 x 101] intentionally omitted <==**

**PCA9575** 

**NXP Semiconductors** 

**16-bit I[2] C-bus and SMBus, level translating, low voltage GPIO** 

internal Power-On Reset (POR) or hardware reset pin (RESET) initializes the two banks of 8 I/Os as inputs, sets the registers to their default values and initializes the device state machine. The I/O banks are held in its default state when the logic supply (VDD) is off. 

The PCA9575 is available in 24-pin TSSOP, 28-pin TSSOP and HWQFN24 packages, and is specified over the 40 C to +85 C industrial temperature range. 

The 28-pin package provides four address select pins, allowing up to 16 PCA9575 devices to be connected with 16 different addresses on the same I[2] C-bus. 

## **2. Features and benefits** 

- Separate supply rails for core logic and each of the two I/O banks provides voltage level shifting 

- 1.1 V to 3.6 V operation with level shifting feature 

- Very low standby current: < 2 A 

- 16 configurable I/O pins organized as 2 banks that default to inputs at power-up 

- Outputs: 

   - Totem pole: 1 mA source and 3 mA sink 

   - Independently programmable 100 k pull-up or pull-down for each I/O pin 

   - Open-drain active LOW interrupt (INT) output pin allows monitoring of logic level change of pins programmed as inputs 

- Inputs: 

   - Programmable bus hold provides valid logic level when inputs are not actively driven 

   - Programmable Interrupt Mask Control for input pins that do not require an interrupt when their states change or to prevent spurious interrupts default to mask at power-up 

   - Polarity Inversion register allows inversion of the polarity of the I/O pins when read 

- 400 kHz I[2] C-bus serial interface 

- Compliant with I[2] C-bus Standard-mode (100 kHz) 

- Active LOW reset (RESET) input pin resets device to power-up default state 

- GPIO All Call address allows programming of more than one device at the same time with the same parameters 

- 16 programmable slave addresses using 4 address pins (28-pin TSSOP only) 

- 40 C to +85 C operation 

- ESD protection exceeds 6000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101 

- Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA 

- Packages offered: TSSOP28, TSSOP24, HWQFN24 

© NXP Semiconductors N.V. 2015. All rights reserved. 

PCA9575 

All information provided in this document is subject to legal disclaimers. **Rev. 4.2 — 16 April 2015** 

**Product data sheet** 

**2 of 42** 

**PCA9575** 

**NXP Semiconductors** 

**16-bit I[2] C-bus and SMBus, level translating, low voltage GPIO** 

## **3. Applications** 

- Cell phones 

- Media players 

- Multi-voltage environments 

- Battery operated mobile gadgets 

- Motherboards 

- Servers 

- RAID systems 

- Industrial control 

- Medical equipment 

- PLCs 

- Gaming machines 

- Instrumentation and test measurement 

## **4. Ordering information** 

**Table 1. Ordering information** 

|**Type number**|**Topside**<br>**marking**|**Package**|**Package**|**Package**|
|---|---|---|---|---|
|||**Name**|**Description**|**Version**|
|PCA9575PW2|PA9575PW2|TSSOP28|plastic thin shrink small outline package; 28 leads;<br>body width 4.4 mm|SOT361-1|
|PCA9575PW1|PA9575PW1|TSSOP24|plastic thin shrink small outline package; 24 leads;<br>body width 4.4 mm|SOT355-1|
|PCA9575HF|575F|HWQFN24|plastic thermal enhanced very very thin quad flat package;<br>no leads; 24 terminals; body 440.75 mm|SOT994-1|



## **4.1 Ordering options** 

## **Table 2. Ordering options** 

|**Type number**|**Orderable**<br>**part number**|**Package**|**Packing method**|**Minimum**<br>**order**<br>**quantity**|**Temperature**|
|---|---|---|---|---|---|
|PCA9575PW2|PCA9575PW2,118|TSSOP28|Reel 13” Q1/T1<br>*Standard mark SMD|2500|Tamb=40C to +85C|
|PCA9575PW1|PCA9575PW1,118|TSSOP24|Reel 13” Q1/T1<br>*Standard mark SMD|2500|Tamb=40C to +85C|
|PCA9575HF|PCA9575HF,118|HWQFN24|Reel 13” Q1/T1<br>*Standard mark SMD|6000|Tamb=40C to +85C|



© NXP Semiconductors N.V. 2015. All rights reserved. 

PCA9575 

All information provided in this document is subject to legal disclaimers. 

**Product data sheet** 

**Rev. 4.2 — 16 April 2015** 

**3 of 42** 

**PCA9575** 

**NXP Semiconductors** 

**16-bit I[2] C-bus and SMBus, level translating, low voltage GPIO** 

## **5. Block diagram** 

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PCA9575 VDD(IO)1<br>P1_0<br>A0<br>P1_1<br>(1) A1 8-bit P1_2<br>A2 INPUT/<br>OUTPUT P1_3<br>A3 PORTS P1_4<br>write pulse BANK 1 P1_5<br>read pulse P1_6<br>P1_7<br>I [2] C-BUS/SMBus VDD(IO)0<br>CONTROL<br>P0_0<br>SCL INPUT P0_1<br>SDA FILTER 8-bit P0_2<br>INPUT/<br>OUTPUT P0_3<br>PORTS P0_4<br>VDD write pulse BANK 0 P0_5<br>POWER-ONRESET read pulse P0_6<br>RESET P0_7<br>VDD<br>VSS<br>LP INT<br>FILTER<br>002aad562<br>Remark:  All I/Os are set to inputs at power-up and RESET.<br>(1) PCA9575PW2 only.<br>Fig 1. Block diagram of PCA9575<br>**----- End of picture text -----**<br>


© NXP Semiconductors N.V. 2015. All rights reserved. 

PCA9575 **Product data sheet** 

All information provided in this document is subject to legal disclaimers. 

**Rev. 4.2 — 16 April 2015** 

**4 of 42** 

**PCA9575** 

**NXP Semiconductors** 

## **16-bit I[2] C-bus and SMBus, level translating, low voltage GPIO** 

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**----- Start of picture text -----**<br>
data from output port<br>shift register register data<br>configuration<br>register VDD(IO)<br>data from D Q Q1<br>shift register<br>FF<br>write<br>D Q<br>configuration CK Q<br>pulse FF<br>P0_0 to P0_7<br>write pulse CK Q2 ESD P1_0 to P1_7<br>protection<br>output port<br>diode<br>register input port<br>register VSS<br>D Q<br>input port<br>FF register data<br>read pulse CK INTERRUPT<br>to INT<br>MASK<br>VDD(IO)<br>BUS-HOLD<br>AND 100 k Ω<br>PULL-UP/PULL-DOWN<br>CONTROL<br>polarity<br>inversion<br>register<br>data from<br>D Q polarity<br>shift register inversion<br>FF register data<br>write polarity<br>CK<br>pulse<br>002aad566<br>**----- End of picture text -----**<br>


**Fig 2. Simplified schematic of the I/Os (P0_0 to P0_7, P1_0 to P1_7)** 

© NXP Semiconductors N.V. 2015. All rights reserved. 

PCA9575 **Product data sheet** 

All information provided in this document is subject to legal disclaimers. **Rev. 4.2 — 16 April 2015** 

**5 of 42** 

**PCA9575** 

**NXP Semiconductors** 

**16-bit I[2] C-bus and SMBus, level translating, low voltage GPIO** 

## **6. Pinning information** 

## **6.1 Pinning** 

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**----- Start of picture text -----**<br>
A0 1 28 SCL<br>VDD 2 27 SDA<br>VDD 1 24 SCL RESET 3 26 P1_0<br>RESET 2 23 SDA P0_0 4 25 P1_1<br>P0_0 3 22 P1_0 P0_1 5 24 P1_2<br>P0_1 4 21 P1_1 P0_2 6 23 P1_3<br>P0_2 5 20 P1_2 P0_3 7 PCA9575PW2 22 A3<br>P0_3 6 19 P1_3 A1 8 21 VDD(IO)1<br>VDD(IO)0 7 PCA9575PW1 18 VDD(IO)1 VDD(IO)0 9 20 P1_4<br>P0_4 8 17 P1_4 P0_4 10 19 P1_5<br>P0_5 9 16 P1_5 P0_5 11 18 P1_6<br>P0_6 10 15 P1_6 P0_6 12 17 P1_7<br>P0_7 11 14 P1_7 P0_7 13 16 VSS<br>INT 12 13 VSS INT 14 15 A2<br>002aad564 002aad563<br>Fig 3. Pin configuration for TSSOP24 Fig 4. Pin configuration for TSSOP28<br>**----- End of picture text -----**<br>


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terminal 1<br>index area<br>P0_1 1 18 P1_1<br>P0_2 2 17 P1_2<br>P0_3 3 16 P1_3<br>PCA9575HF<br>VDD(IO)0 4 15 VDD(IO)1<br>P0_4 5 14 P1_4<br>P0_5 6 13 P1_5<br>002aad575<br>Transparent top view<br>DD<br>P0_0 RESET V SCL SDA P1_0<br>24 23 22 21 20 19<br>7 8 9 10 11 12<br>INT VSS<br>P0_6 P0_7 P1_7 P1_6<br>**----- End of picture text -----**<br>


**Fig 5. Pin configuration for HWQFN24** 

© NXP Semiconductors N.V. 2015. All rights reserved. 

PCA9575 

All information provided in this document is subject to legal disclaimers. 

**Product data sheet** 

**Rev. 4.2 — 16 April 2015** 

**6 of 42** 

**PCA9575** 

**NXP Semiconductors** 

**16-bit I[2] C-bus and SMBus, level translating, low voltage GPIO** 

## **6.2 Pin description** 

**Table 3. Pin description** 

|**Symbol**|**Pin**|**Pin**|**Pin**|**Type**|**Description**|
|---|---|---|---|---|---|
||**TSSOP28**|**TSSOP24**|**HWQFN24**|||
|A0|1|-|-|I|address input 0|
|VDD|2|1|22|power supply|supply voltage|
|RESET|3|2|23|I|active LOW reset input|
|P0_0|4|3|24|I/O|port 0 input/output 0|
|P0_1|5|4|1|I/O|port 0 input/output 1|
|P0_2|6|5|2|I/O|port 0 input/output 2|
|P0_3|7|6|3|I/O|port 0 input/output 3|
|A1|8|-|-|I|address input 1|
|VDD(IO)0|9|7|4|power supply|I/O supply voltage for bank 0|
|P0_4|10|8|5|I/O|port 0 input/output 0|
|P0_5|11|9|6|I/O|port 0 input/output 1|
|P0_6|12|10|7|I/O|port 0 input/output 2|
|P0_7|13|11|8|I/O|port 0 input/output 3|
|INT|14|12|9|O|interrupt output (open-drain;<br>active LOW)|
|A2|15|-|-|I|address input 2|
|VSS|16|13|10[1]|ground|supply ground|
|P1_7|17|14|11|I/O|port 1 input/output 4|
|P1_6|18|15|12|I/O|port 1 input/output 5|
|P1_5|19|16|13|I/O|port 1 input/output 6|
|P1_4|20|17|14|I/O|port 1 input/output 7|
|VDD(IO)1|21|18|15|power supply|I/O supply voltage for bank 1|
|A3|22|-|-|I|address input 3|
|P1_3|23|19|16|I/O|port 1 input/output 3|
|P1_2|24|20|17|I/O|port 1 input/output 2|
|P1_1|25|21|18|I/O|port 1 input/output 1|
|P1_0|26|22|19|I/O|port 1 input/output 0|
|SDA|27|23|20|I/O|serial data line|
|SCL|28|24|21|I|serial clock line|



- [1] HWQFN24 package die supply ground is connected to both VSS pin and exposed center pad. VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad must be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias must be incorporated in the PCB in the thermal pad region. 

© NXP Semiconductors N.V. 2015. All rights reserved. 

PCA9575 **Product data sheet** 

All information provided in this document is subject to legal disclaimers. 

**Rev. 4.2 — 16 April 2015** 

**7 of 42** 

**PCA9575** 

**NXP Semiconductors** 

**16-bit I[2] C-bus and SMBus, level translating, low voltage GPIO** 

## **7. Functional description** 

## **7.1 I/O ports** 

The 16 I/O ports are organized as two banks of 8 ports each. The system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration register bits. The data for each input or output is kept in the corresponding Input or Output register. The polarity of the read register can be inverted with the Polarity Inversion register. Either a bus-hold function or pull-up/pull-down feature can be selected by programming corresponding registers. A bus-hold provides a valid logic level when the I/O bus is not actively driven. It consists of a pair of buffers, one being weak (low drive-strength), that latch the input at the last driven value. This prevents the input from floating while it is being driven by a 3-state output. Latching the last valid logic state of input prevents it from settling at a midpoint between VDD and ground that in turn consumes power. An active bus driver can easily override the logic level set by the bus-keeper. 

When bus-hold feature is not selected, the I/O ports can be configured to have pull-up or pull-down by programming the pull-up/pull-down configuration register. 

## **7.2 Device address** 

Following a START condition, the bus master must send the address of the slave it is accessing and the operation it wants to perform (read or write). Address configuration for the device depends on the package type chosen. The device offered in a 24-pin package has a fixed slave address for the PCA9575 as shown in Figure 6. 

**==> picture [138 x 50] intentionally omitted <==**

**----- Start of picture text -----**<br>
slave address<br>0 1 0 0 0 0 0 R/W<br>fixed 002aad567<br>**----- End of picture text -----**<br>


**Fig 6. PCA9575 device address for 24-pin version** 

The last bit of the first byte defines the operation to be performed. When set to logic 1 a read is selected, while logic 0 selects a write operation. 

The slave address for the 28-pin version of the PCA9575 is shown in Figure 7. 

**==> picture [138 x 54] intentionally omitted <==**

**----- Start of picture text -----**<br>
slave address<br>0 1 0 A3 A2 A1 A0 R/W<br>fixed hardware selectable<br>002aad583<br>**----- End of picture text -----**<br>


**Fig 7. PCA9575 device address for 28-pin version** 

© NXP Semiconductors N.V. 2015. All rights reserved. 

PCA9575 

All information provided in this document is subject to legal disclaimers. 

**Product data sheet** 

**Rev. 4.2 — 16 April 2015** 

**8 of 42** 

**PCA9575** 

**NXP Semiconductors** 

**16-bit I[2] C-bus and SMBus, level translating, low voltage GPIO** 

## **7.3 Command register** 

Following the successful acknowledgement of the slave address + R/W bit, the bus master sends a byte to the PCA9575, which is stored in the Command register. 

**==> picture [160 x 42] intentionally omitted <==**

**----- Start of picture text -----**<br>
AI 0 0 0 D3 D2 D1 D0<br>Auto-Increment flag register address<br>002aad568<br>**----- End of picture text -----**<br>


Reset state = 00h **Remark:** The Command register does not apply to Software Reset I[2] C-bus address. **Fig 8. Command register** 

The lowest 4 bits are used as a pointer to determine which register is accessed. Only a Command register code with the 4 least significant bits equal to the 16 allowable values as defined in Table 4 “Register summary” is acknowledged. Reserved or undefined command codes are not acknowledged. At power-up, this register defaults to 00h, with the AI bit set to logic 0, and the lowest 4 bits set to logic 0. 

If the Auto-Increment flag is set (AI = 1), the 4 least significant bits of the Command register are automatically incremented after a read or write. This allows the user to program and/or read the 16 command registers (listed in Table 4) sequentially. It will then roll over to register 00h after the last register is accessed and the selected registers are overwritten or re-read. 

If the Auto-Increment flag is cleared (AI = 0), the 4 least significant bits are not incremented after data is read or written, only one register will be repeatedly read or written. 

## **7.4 Register definitions** 

**Table 4. Register summary** 

|**Register number**|**D3**|**D2**|**D1**|**D0**|**Name**|**Type**|**Function**|
|---|---|---|---|---|---|---|---|
|00h|0|0|0|0|IN0|read only|Input port 0 register|
|01h|0|0|0|1|IN1|read only|Input port 1 register|
|02h|0|0|1|0|INVRT0|read/write|Polarity inversion port 0 register|
|03h|0|0|1|1|INVRT1|read/write|Polarity inversion port 1 register|
|04h|0|1|0|0|BKEN0|read/write|Bus-hold enable 0 register|
|05h|0|1|0|1|BKEN1|read/write|Bus-hold enable 1 register|
|06h|0|1|1|0|PUPD0|read/write|Pull-up/pull-down selector port 0 register|
|07h|0|1|1|1|PUPD1|read/write|Pull-up/pull-down selector port 1 register|
|08h|1|0|0|0|CFG0|read/write|Configuration port 0 register|
|09h|1|0|0|1|CFG1|read/write|Configuration port 1 register|
|0Ah|1|0|1|0|OUT0|read/write|Output port 0 register|
|0Bh|1|0|1|1|OUT1|read/write|Output port 1 register|
|0Ch|1|1|0|0|MSK0|read/write|Interrupt mask port 0 register|



© NXP Semiconductors N.V. 2015. All rights reserved. 

PCA9575 

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**Product data sheet** 

**Rev. 4.2 — 16 April 2015** 

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**PCA9575** 

**NXP Semiconductors** 

**16-bit I[2] C-bus and SMBus, level translating, low voltage GPIO** 

## **Table 4. Register summary** _…continued_ 

|**Register number**|**D3**|**D2**|**D1**|**D0**|**Name**|**Type**|**Function**|
|---|---|---|---|---|---|---|---|
|0Dh|1|1|0|1|MSK1|read/write|Interrupt mask port 1 register|
|0Eh|1|1|1|0|INTS0|read only|Interrupt status port 0 register|
|0Fh|1|1|1|1|INTS1|read only|Interrupt status port 1 register|



## **7.5 Writing to port registers** 

Data is transmitted to the PCA9575 by sending the device address and setting the least significant bit to logic 0 (see Figure 6 or Figure 7 for device address). The command byte is sent after the address and determines which register receives the data following the command byte. Each 8-bit register may be updated independently of the other registers. 

## **7.6 Reading the port registers** 

In order to read data from the PCA9575, the bus master must first send the PCA9575 address with the least significant bit set to a logic 0 (see Figure 6 or Figure 7 for device address). The command byte is sent after the address and determines which register is accessed. After a restart, the device address is sent again but this time, the least significant bit is set to logic 1. Data from the register defined by the command byte will then be sent by the PCA9575. Data is clocked into the register on the falling edge of the acknowledge clock pulse. After the first byte is read, additional bytes may be read using the auto-increment feature. 

## **7.6.1 Register 0 - Input port 0 register** 

This register is read-only. It reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration register. Writes to this register are acknowledged but have no effect. 

The default ‘X’ is determined by the externally applied logic level. 

## **Table 5. Register 0 - Input port 0 register (address 00h) bit description** 

|**Bit**|**Symbol**|**Access**|**Value**|**Description**|
|---|---|---|---|---|
|7|IO0.7|read only|X|determined by externally applied logic level|
|6|IO0.6|read only|X||
|5|IO0.5|read only|X||
|4|IO0.4|read only|X||
|3|IO0.3|read only|X||
|2|IO0.2|read only|X||
|1|IO0.1|read only|X||
|0|IO0.0|read only|X||



© NXP Semiconductors N.V. 2015. All rights reserved. 

PCA9575 

All information provided in this document is subject to legal disclaimers. **Rev. 4.2 — 16 April 2015** 

**Product data sheet** 

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**PCA9575** 

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**16-bit I[2] C-bus and SMBus, level translating, low voltage GPIO** 

## **7.6.2 Register 1 - Input port 1 register** 

This register is read-only. It reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration register. Writes to this register are acknowledged but have no effect. 

The default ‘X’ is determined by the externally applied logic level. 

**Table 6. Register 1 - Input port 1 register (address 01h) bit description** 

|**Bit**|**Symbol**|**Access**|**Value**|**Description**|
|---|---|---|---|---|
|7|IO1.7|read only|X|determined by externally applied logic level|
|6|IO1.6|read only|X||
|5|IO1.5|read only|X||
|4|IO1.4|read only|X||
|3|IO1.3|read only|X||
|2|IO1.2|read only|X||
|1|IO1.1|read only|X||
|0|IO1.0|read only|X||



## **7.6.3 Register 2 - Polarity inversion port 0 register** 

This register allows the user to invert the polarity of the Input port register data. If a bit in this register is set (written with ‘1’), the corresponding Input port data is inverted. If a bit in this register is cleared (written with a ‘0’), the Input port data polarity is retained. 

**Table 7. Register 2 - Polarity Inversion port 0 register (address 02h) bit description** _Legend: * default value._ 

|**Bit**|**Symbol**|**Access**|**Value**|**Description**|
|---|---|---|---|---|
|7|N0.7|R/W|0*|inverts polarity of Input port 0 register data<br>0 = Input port 0 register data retained (default value)<br>1 = Input port 0 register data inverted|
|6|N0.6|R/W|0*||
|5|N0.5|R/W|0*||
|4|N0.4|R/W|0*||
|3|N0.3|R/W|0*||
|2|N0.2|R/W|0*||
|1|N0.1|R/W|0*||
|0|N0.0|R/W|0*||



© NXP Semiconductors N.V. 2015. All rights reserved. 

PCA9575 **Product data sheet** 

All information provided in this document is subject to legal disclaimers. **Rev. 4.2 — 16 April 2015** 

**11 of 42** 

**PCA9575** 

**NXP Semiconductors** 

**16-bit I[2] C-bus and SMBus, level translating, low voltage GPIO** 

## **7.6.4 Register 3 - Polarity inversion port 1 register** 

This register allows the user to invert the polarity of the Input port register data. If a bit in this register is set (written with ‘1’), the corresponding Input port data is inverted. If a bit in this register is cleared (written with a ‘0’), the Input port data polarity is retained. 

**Table 8. Register 3 - Polarity Inversion port 1 register (address 03h) bit description** _Legend: * default value._ 

|**Bit**|**Symbol**|**Access**|**Value**|**Description**|
|---|---|---|---|---|
|7|N1.7|R/W|0*|inverts polarity of Input port 1 register data<br>0 = Input port 1 register data retained (default value)<br>1 = Input port 1 register data inverted|
|6|N1.6|R/W|0*||
|5|N1.5|R/W|0*||
|4|N1.4|R/W|0*||
|3|N1.3|R/W|0*||
|2|N1.2|R/W|0*||
|1|N1.1|R/W|0*||
|0|N1.0|R/W|0*||



## **7.6.5 Register 4 - Bus-hold/pull-up/pull-down enable 0 register** 

Bit 0 of this register allows the user to enable/disable the bus-hold feature for the I/O pins. Setting the bit 0 to logic 1 enables bus-hold feature for the I/O bank 0. In this mode, the pull-up/pull-downs are disabled for I/O bank 0. Setting the bit 0 to logic 0 disables bus-hold feature. 

Bit 1 of this register allows the user to enable/disable pull-up/pull-downs on the I/O pins. Setting the bit 1 to logic 1 enables selection of pull-up/pull-down using Register 6. Setting the bit 1 to logic 0 disables pull-up/pull-downs on the I/O bank 0 pins and contents of Register 6 have no effect on the I/O. 

**Table 9. Register 4 - Bus-hold/pull-up/pull-down enable 0 register (address 04h) bit description** _Legend: * default value._ 

|**Bit**|**Symbol**|**Access**|**Value**|**Description**|
|---|---|---|---|---|
|7|E0.7|R/W|X|not used|
|6|E0.6|R/W|X||
|5|E0.5|R/W|X||
|4|E0.4|R/W|X||
|3|E0.3|R/W|X||
|2|E0.2|R/W|X||
|1|E0.1|R/W|0*|allows the user to enable/disable pull-up/pull-downs on the<br>I/O bank 0 pins<br>0 = disables pull-up/pull-downs on the I/O bank 0 pins and<br>contents of Register 6 have no effect on the I/O bank 0<br>(default value)<br>1 = enables selection of pull-up/pull-down using Register 6|
|0|E0.0|R/W|0*|allows user to enable/disable the bus-hold feature for the<br>I/O bank 0 pins<br>0 = disables bus-hold feature (default value)<br>1 = enables bus-hold feature|



All information provided in this document is subject to legal disclaimers. 

© NXP Semiconductors N.V. 2015. All rights reserved. 

PCA9575 **Product data sheet** 

**Rev. 4.2 — 16 April 2015** 

**12 of 42** 

**PCA9575** 

**NXP Semiconductors** 

**16-bit I[2] C-bus and SMBus, level translating, low voltage GPIO** 

## **7.6.6 Register 5 - Bus-hold/pull-up/pull-down enable 1 register** 

Bit 0 of this register allows the user to enable/disable the bus-hold feature for the I/O pins. Setting the bit 0 to logic 1 enables bus-hold feature for the I/O bank 1. In this mode, the pull-up/pull-downs are disabled for I/O bank 1. Setting the bit 0 to logic 0 disables bus-hold feature. 

Bit 1 of this register allows the user to enable/disable pull-up/pull-downs on the I/O pins. Setting the bit 1 to logic 1 enables selection of pull-up/pull-down using Register 7. Setting the bit 1 to logic 0 disables pull-up/pull-downs on the I/O bank 1 pins and contents of Register 7 have no effect on the I/O. 

**Table 10. Register 5 - Bus-hold/pull-up/pull-down enable 1 register (address 05h) bit description** _Legend: * default value._ 

|**Bit**|**Symbol**|**Access**|**Value**|**Description**|
|---|---|---|---|---|
|7|E1.7|R/W|X|not used|
|6|E1.6|R/W|X||
|5|E1.5|R/W|X||
|4|E1.4|R/W|X||
|3|E1.3|R/W|X||
|2|E1.2|R/W|X||
|1|E1.1|R/W|0*|allows the user to enable/disable pull-up/pull-downs on the<br>I/O bank 1 pins<br>0 = disables pull-up/pull-downs on the I/O bank 1 pins and<br>contents of Register 7 have no effect on the I/O bank 0<br>(default value)<br>1 = enables selection of pull-up/pull-down using Register 7|
|0|E1.0|R/W|0*|allows user to enable/disable the bus-hold feature for the<br>I/O bank 1 pins<br>0 = disables bus-hold feature (default value)<br>1 = enables bus-hold feature|



© NXP Semiconductors N.V. 2015. All rights reserved. 

PCA9575 **Product data sheet** 

All information provided in this document is subject to legal disclaimers. **Rev. 4.2 — 16 April 2015** 

**13 of 42** 

**PCA9575** 

**NXP Semiconductors** 

**16-bit I[2] C-bus and SMBus, level translating, low voltage GPIO** 

## **7.6.7 Register 6 - Pull-up/pull-down select port 0 register** 

When bus-hold feature is not selected and bit 1 of Register 4 is set to logic 1, the I/O port 0 can be configured to have pull-up or pull-down by programming the pull-up/pull-down register. Setting a bit to logic 1 selects a 100 k pull-up resistor for that I/O pin. Setting a bit to logic 0 selects a 100 k pull-down resistor for that I/O pin. If the bus-hold feature is enabled, writing to this register has no effect on pull-up/pull-down selection. 

**Table 11. Register 6 - Pull-up/pull-down select port 0 register (address 06h) bit description** _Legend: * default value._ 

|**Bit**|**Symbol**|**Access**|**Value**|**Description**|
|---|---|---|---|---|
|7|P0.7|R/W|1*|configures I/O port 0 pin to have pull-up or pull-down when<br>bus-hold feature not selected and bit 1 of Register 4 is logic 1<br>0 = selects a 100 kpull-down resistor for that I/O pin<br>1 = selects a 100 kpull-up resistor for that I/O pin (default<br>value)|
|6|P0.6|R/W|1*||
|5|P0.5|R/W|1*||
|4|P0.4|R/W|1*||
|3|P0.3|R/W|1*||
|2|P0.2|R/W|1*||
|1|P0.1|R/W|1*||
|0|P0.0|R/W|1*||



## **7.6.8 Register 7 - Pull-up/pull-down select port 1 register** 

When bus-hold feature is not selected and bit 1 of Register 5 is set to logic 1, the I/O port 1 can be configured to have pull-up or pull-down by programming the pull-up/pull-down register. Setting a bit to logic 1 selects a 100 k pull-up resistor for that I/O pin. Setting a bit to logic 0 selects a 100 k pull-down resistor for that I/O pin. If the bus-hold feature is enabled, writing to this register has no effect on pull-up/pull-down selection. 

**Table 12. Register 7 - Pull-up/pull-down select port 1 register (address 07h) bit description** _Legend: * default value._ 

|**Bit**|**Symbol**|**Access**|**Value**|**Description**|
|---|---|---|---|---|
|7|P1.7|R/W|1*|configures I/O port 1 pin to have pull-up or pull-down when<br>bus-hold feature not selected and bit 1 of Register 5 is logic 1<br>0 = selects a 100 kpull-down resistor for that I/O pin<br>1 = selects a 100 kpull-up resistor for that I/O pin (default<br>value)|
|6|P1.6|R/W|1*||
|5|P1.5|R/W|1*||
|4|P1.4|R/W|1*||
|3|P1.3|R/W|1*||
|2|P1.2|R/W|1*||
|1|P1.1|R/W|1*||
|0|P1.0|R/W|1*||



© NXP Semiconductors N.V. 2015. All rights reserved. 

PCA9575 

All information provided in this document is subject to legal disclaimers. 

**Product data sheet** 

**Rev. 4.2 — 16 April 2015** 

**14 of 42** 

**PCA9575** 

**NXP Semiconductors** 

**16-bit I[2] C-bus and SMBus, level translating, low voltage GPIO** 

## **7.6.9 Register 8 - Configuration port 0 register** 

This register configures the direction of the I/O pins. If a bit in this register is set (written with logic 1), the corresponding port 0 pin is enabled as an input with high-impedance output driver. If a bit in this register is cleared (written with logic 0), the corresponding port 0 pin is enabled as an output. At reset, the device ports are inputs. 

**Table 13. Register 8 - Configuration port 0 register (address 08h) bit description** _Legend: * default value._ 

|**Bit**|**Symbol**|**Access**|**Value**|**Description**|
|---|---|---|---|---|
|7|C0.7|R/W|1*|configures the direction of the I/O pins<br>0 = corresponding port pin enabled as an output<br>1 = corresponding port pin configured as input<br>(default value)|
|6|C0.6|R/W|1*||
|5|C0.5|R/W|1*||
|4|C0.4|R/W|1*||
|3|C0.3|R/W|1*||
|2|C0.2|R/W|1*||
|1|C0.1|R/W|1*||
|0|C0.0|R/W|1*||



## **7.6.10 Register 9 - Configuration port 1 register** 

This register configures the direction of the I/O pins. If a bit in this register is set (written with logic 1), the corresponding port 1 pin is enabled as an input with high-impedance output driver. If a bit in this register is cleared (written with logic 0), the corresponding port 1 pin is enabled as an output. At reset, the device ports are inputs. 

**Table 14. Register 9 - Configuration port 1 register (address 09h) bit description** _Legend: * default value._ 

|**Bit**|**Symbol**|**Access**|**Value**|**Description**|
|---|---|---|---|---|
|7|C1.7|R/W|1*|configures the direction of the I/O pins<br>0 = corresponding port pin enabled as an output<br>1 = corresponding port pin configured as input<br>(default value)|
|6|C1.6|R/W|1*||
|5|C1.5|R/W|1*||
|4|C1.4|R/W|1*||
|3|C1.3|R/W|1*||
|2|C1.2|R/W|1*||
|1|C1.1|R/W|1*||
|0|C1.0|R/W|1*||



© NXP Semiconductors N.V. 2015. All rights reserved. 

PCA9575 **Product data sheet** 

All information provided in this document is subject to legal disclaimers. **Rev. 4.2 — 16 April 2015** 

**15 of 42** 

**PCA9575** 

**NXP Semiconductors** 

**16-bit I[2] C-bus and SMBus, level translating, low voltage GPIO** 

## **7.6.11 Register 10 - Output port 0 register** 

This register is an output-only port. It reflects the outgoing logic levels of the pins defined as outputs by Register 8. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, **not** the actual pin value. 

**Table 15. Register 10 - Output port 0 register (address 0Ah) bit description** _Legend: * default value._ 

|**Bit**|**Symbol**|**Access**|**Value**|**Description**|
|---|---|---|---|---|
|7|O0.7|R/W|0*|reflects outgoing logic levels of pins defined as<br>outputs by Register 8|
|6|O0.6|R/W|0*||
|5|O0.5|R/W|0*||
|4|O0.4|R/W|0*||
|3|O0.3|R/W|0*||
|2|O0.2|R/W|0*||
|1|O0.1|R/W|0*||
|0|O0.0|R/W|0*||



## **7.6.12 Register 11 - Output port 1 register** 

This register is an output-only port. It reflects the outgoing logic levels of the pins defined as outputs by Register 9. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, **not** the actual pin value. 

**Table 16. Register 11 - Output port 1 register (address 0Bh) bit description** _Legend: * default value._ 

|**Bit**|**Symbol**|**Access**|**Value**|**Description**|
|---|---|---|---|---|
|7|O1.7|R/W|0*|reflects outgoing logic levels of pins defined as<br>outputs by Register 9|
|6|O1.6|R/W|0*||
|5|O1.5|R/W|0*||
|4|O1.4|R/W|0*||
|3|O1.3|R/W|0*||
|2|O1.2|R/W|0*||
|1|O1.1|R/W|0*||
|0|O1.0|R/W|0*||



© NXP Semiconductors N.V. 2015. All rights reserved. 

PCA9575 **Product data sheet** 

All information provided in this document is subject to legal disclaimers. **Rev. 4.2 — 16 April 2015** 

**16 of 42** 

**PCA9575** 

**NXP Semiconductors** 

**16-bit I[2] C-bus and SMBus, level translating, low voltage GPIO** 

## **7.6.13 Register 12 - Interrupt mask port 0 register** 

All the bits of Interrupt mask port 0 register are set to logic 1 upon power-on or software reset, thus disabling interrupts. Interrupts may be enabled by setting corresponding mask bits to logic 0. 

**Table 17. Register 12 - Interrupt mask port 0 register (address 0Ch) bit description** _Legend: * default value._ 

|**Bit**|**Symbol**|**Access**|**Value**|**Description**|
|---|---|---|---|---|
|7|M0.7|R/W|1*|enable or disable interrupts<br>0 = enable interrupt<br>1 = disable interrupt (default value)|
|6|M0.6|R/W|1*||
|5|M0.5|R/W|1*||
|4|M0.4|R/W|1*||
|3|M0.3|R/W|1*||
|2|M0.2|R/W|1*||
|1|M0.1|R/W|1*||
|0|M0.0|R/W|1*||



## **7.6.14 Register 13 - Interrupt mask port 1 register** 

All the bits of Interrupt mask port 1 register are set to logic 1 upon power-on or software reset, thus disabling interrupts. Interrupts may be enabled by setting corresponding mask bits to logic 0. 

**Table 18. Register 13 - Interrupt mask port 1 register (address 0Dh) bit description** _Legend: * default value._ 

|**Bit**|**Symbol**|**Access**|**Value**|**Description**|
|---|---|---|---|---|
|7|M1.7|R/W|1*|enable or disable interrupts<br>0 = enable interrupt<br>1 = disable interrupt (default value)|
|6|M1.6|R/W|1*||
|5|M1.5|R/W|1*||
|4|M1.4|R/W|1*||
|3|M1.3|R/W|1*||
|2|M1.2|R/W|1*||
|1|M1.1|R/W|1*||
|0|M1.0|R/W|1*||



© NXP Semiconductors N.V. 2015. All rights reserved. 

PCA9575 

All information provided in this document is subject to legal disclaimers. **Rev. 4.2 — 16 April 2015** 

**Product data sheet** 

**17 of 42** 

**PCA9575** 

**NXP Semiconductors** 

**16-bit I[2] C-bus and SMBus, level translating, low voltage GPIO** 

## **7.6.15 Register 14 - Interrupt status port 0 register** 

This register is read-only. It is used to identify the source of interrupt. 

**Remark:** If the interrupts are masked, this register returns all zeros. 

**Table 19. Register 14 - Interrupt status port 0 register (address 0Eh) bit description** _Legend: * default value._ 

|**Bit**|**Symbol**|**Access**|**Value**|**Description**|
|---|---|---|---|---|
|7|S0.7|read only|0*|identifies source of interrupt|
|6|S0.6|read only|0*||
|5|S0.5|read only|0*||
|4|S0.4|read only|0*||
|3|S0.3|read only|0*||
|2|S0.2|read only|0*||
|1|S0.1|read only|0*||
|0|S0.0|read only|0*||



## **7.6.16 Register 15 - Interrupt status port 1 register** 

This register is read-only. It is used to identify the source of interrupt. 

**Remark:** If the interrupts are masked, this register returns all zeros. 

**Table 20. Register 15 - Interrupt status port 1 register (address 0Fh) bit description** _Legend: * default value._ 

|**Bit**|**Symbol**|**Access**|**Value**|**Description**|
|---|---|---|---|---|
|7|S1.7|read only|0*|identifies source of interrupt|
|6|S1.6|read only|0*||
|5|S1.5|read only|0*||
|4|S1.4|read only|0*||
|3|S1.3|read only|0*||
|2|S1.2|read only|0*||
|1|S1.1|read only|0*||
|0|S1.0|read only|0*||



## **7.7 Power-on reset** 

When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9575 in a reset condition until VDD has reached VPOR. At that point, the reset condition is released and the PCA9575 registers and state machine initialize to their default states. The power-on reset typically completes the reset and enables the part by the time the power supply is above VPOR. However, when it is required to reset the part by lowering the power supply, it is necessary to lower it below 0.2 V. 

## **7.8 RESET input** 

A reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst). The PCA9575 registers and I[2] C-bus state machine are held in their default state until the RESET input is once again HIGH. 

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**16-bit I[2] C-bus and SMBus, level translating, low voltage GPIO** 

## **7.9 Software reset** 

The Software Reset Call allows all the devices in the I[2] C-bus to be reset to the power-up state value through a specific formatted I[2] C-bus command. To be performed correctly, it implies that the I[2] C-bus is functional and that there is no device hanging the bus. 

The Software Reset sequence is defined as following: 

1. A START command is sent by the I[2] C-bus master. 

2. The reserved General Call I[2] C-bus address ‘0000 000’ with the R/W bit set to 0 (write) is sent by the I[2] C-bus master. 

3. The PCA9575 device(s) acknowledge(s) after seeing the General Call address ‘0000 0000’ (00h) only. If the R/W bit is set to logic 1 (read), no acknowledge is returned to the I[2] C-bus master. 

4. Once the General Call address has been sent and acknowledged, the master sends 1 byte. The value of the byte must be equal to 06h (1000 0011).The PCA9575 acknowledges this value only. If the byte is not equal to 06h, the PCA9575 does not acknowledge it. If more than 1 byte of data is sent, the PCA9575 does not acknowledge anymore. 

5. Once the right byte has been sent and correctly acknowledged, the master sends a STOP command to end the Software Reset sequence: the PCA9575 then resets to the default value (power-up value) and is ready to be addressed again within the specified bus free time. If the master sends a Repeated START instead, no reset is performed. The I[2] C-bus master must interpret a non-acknowledge from the PCA9575 (at any time) as a ‘Software Reset Abort’. The PCA9575 does not initiate a software reset. 

## **7.10 Interrupt output (INT)** 

The open-drain active LOW interrupt is activated when one of the port pins changes state and the port pin is configured as an input and the interrupt on it is not masked. The interrupt is deactivated when the port pin input returns to its previous state or the Input Port register is read. It is highly recommended to program the MSK register, and the CFG registers during the initialization sequence after power-up, since any change to them during Normal mode operation may cause undesirable interrupt events to happen. 

**Remark:** Changing an I/O from an output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the Input Port register. Only a Read of the Input Port register that contains the bit(s) image of the input(s) that generated the interrupt clears the interrupt condition. 

## **7.11 Standby** 

The PCA9575 goes into standby when the I[2] C-bus is idle. Standby supply current is lower than 2.0 A (typical). 

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PCA9575 

**Product data sheet** 

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**PCA9575** 

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**16-bit I[2] C-bus and SMBus, level translating, low voltage GPIO** 

## **8. Characteristics of the I[2] C-bus** 

The I[2] C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 

## **8.1 Bit transfer** 

One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time are interpreted as control signals (see Figure 9). 

**==> picture [241 x 87] intentionally omitted <==**

**----- Start of picture text -----**<br>
���<br>���<br>���������� �������<br>�������� ��������<br>���������� ������� ������<br>**----- End of picture text -----**<br>


**Fig 9. Bit transfer** 

## **8.1.1 START and STOP conditions** 

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Figure 10). 

**==> picture [320 x 76] intentionally omitted <==**

**----- Start of picture text -----**<br>
���<br>���<br>� �<br>��������������� ��������������<br>�������<br>**----- End of picture text -----**<br>


**Fig 10. Definition of START and STOP conditions** 

## **8.2 System configuration** 

A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see Figure 11). 

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PCA9575 

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**Product data sheet** 

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**PCA9575** 

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**16-bit I[2] C-bus and SMBus, level translating, low voltage GPIO** 

**Fig 11. System configuration** 

## **8.3 Acknowledge** 

The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of 8 bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. 

A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse; set-up time and hold time must be taken into account. 

A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. 

**Fig 12. Acknowledgement on the I[2] C-bus** 

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PCA9575 

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**Product data sheet** 

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**16-bit I[2] C-bus and SMBus, level translating, low voltage GPIO** 

## **9. Bus transactions** 

Data is transmitted to the PCA9575 registers using ‘Write Byte’ transfers (see Figure 13 and Figure 14). 

Data is read from the PCA9575 registers using ‘Read Byte’ transfers (see Figure 15 and Figure 16). 

**==> picture [422 x 134] intentionally omitted <==**

**----- Start of picture text -----**<br>
SCL 1 2 3 4 5 6 7 8 9<br>STOP<br>condition<br>slave address [(1)] command byte data to port<br>SDA S 0 1 0 0 0 0 0 0 A 0 0 0 0 1 0 1 0 A DATA 1 A P<br>START condition R/W acknowledge acknowledge acknowledge<br>from slave from slave from slave<br>write to port<br>tv(Q)<br>data out from port DATA 1 VALID<br>002aad569<br>**----- End of picture text -----**<br>


- (1) Slave address shown in this example is for the 24-pin version. 

**Fig 13. Write to Output port register** 

**==> picture [421 x 109] intentionally omitted <==**

**----- Start of picture text -----**<br>
SCL 1 2 3 4 5 6 7 8 9<br>STOP<br>condition<br>slave address [(1)] command byte data to register<br>SDA S 0 1 0 0 0 0 0 0 A 0 0 0 0 X X X X A DATA A P<br>START condition R/W acknowledge acknowledge acknowledge<br>from slave from slave from slave<br>data to register<br>002aad570<br>**----- End of picture text -----**<br>


- (1) Slave address shown in this example is for the 24-pin version. 

**Fig 14. Write to Polarity inversion, Bus-hold enable, Pull-up/pull-down select, Configuration, Interrupt mask and Interrupt status registers** 

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PCA9575 

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**Product data sheet** 

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**22 of 42** 

**PCA9575** 

**NXP Semiconductors** 

**16-bit I[2] C-bus and SMBus, level translating, low voltage GPIO** 

**==> picture [497 x 476] intentionally omitted <==**

**----- Start of picture text -----**<br>
slave address [(1)]<br>SDA S 0 1 0 0 0 0 0 0 A command byte A (cont.)<br>START condition R/W acknowledge<br>from slave<br>acknowledge<br>from slave<br>slave address [(1)] data from register data from register<br>(cont.) S 0 1 0 0 0 0 0 1 A DATA (first byte) A DATA (last byte) NA P<br>(repeated) R/W acknowledge no acknowledge STOP<br>START condition from master from master condition<br>acknowledge<br>from slave<br>at this moment master-transmitter becomes master-receiver<br>and slave-receiver becomes slave-transmitter<br>002aad571<br>(1) Slave address shown in this example is for the 24-pin version.<br>Fig 15. Read from register<br>DATA 2<br>data into<br>DATA 3 DATA 4<br>port<br>th(D) tsu(D)<br>INT<br>tv(INT) trst(INT)<br>SCL 1 2 3 4 5 6 7 8 9<br>no acknowledge<br>from master<br>slave address [(1)] data from port data from port<br>SDA S 0 1 0 0 0 0 0 1 A DATA 1 A DATA 4 1 P<br>START condition R/W acknowledge acknowledge STOP<br>from slave from master condition<br>read from<br>port<br>002aad572<br>This figure assumes the command byte has previously been programmed with 00h.<br>Transfer of data can be stopped at any moment by a STOP condition.<br>(1) Slave address shown in this example is for the 24-pin version.<br>Fig 16. Read Input port register<br>**----- End of picture text -----**<br>


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PCA9575 **Product data sheet** 

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**Rev. 4.2 — 16 April 2015** 

**23 of 42** 

**PCA9575** 

**NXP Semiconductors** 

**16-bit I[2] C-bus and SMBus, level translating, low voltage GPIO** 

## **10. Application design-in information** 

**==> picture [458 x 283] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDD = 1.1 V VDD(IO)1 = 3.6 V VDD(IO)0 = 3.6 V<br>to 3.6 V<br>SUBSYSTEM 4<br>1.6 k Ω 1.6 k Ω 1.1 k Ω 2 k Ω (e.g., RF module)<br>VDD VDD VDD(IO)1 VDD(IO)0 CTRL<br>MASTER<br>CONTROLLER PCA9575 SUBSYSTEM 1<br>SCL SCL P0_0 (e.g., temp. sensor)<br>SDA SDA P0_1 INT<br>INT INT P0_2<br>RESET RESET P0_3 RESET<br>P0_4 SUBSYSTEM 2<br>VSS P0_5 (e.g., counter)<br>P0_6 A<br>P0_7<br>enable controlled switch<br>P1_0 (e.g., CBT device)<br>P1_1<br>10 DIGIT<br>P1_2 B<br>NUMERIC<br>A0 P1_3 KEYPAD ALARM<br>P1_4<br>A1 SUBSYSTEM 3<br>P1_5<br>A2 (e.g., alarm system)<br>P1_6<br>A3 VSS P1_7 VDD(IO)0<br>002aad573<br>**----- End of picture text -----**<br>


Address pin connections shown are for the 28-pin version. 

Device address configured as 0100 101Xb for this example. 

P0_0, P0_2, P0_3 configured as outputs; P0_1, P0_4 to P0_7 and P1_0 to P1_7 configured as inputs. 

**Fig 17. Typical application** 

## **11. Limiting values** 

**Table 21. Limiting values** 

_In accordance with the Absolute Maximum Rating System (IEC 60134)._ 

|**Symbol**|**Parameter**|**Conditions**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|---|
|VDD|supply voltage||0.5|+4.0|V|
|VDD(IO)0|input/output supply voltage 0||VSS0.5|4.0 + 0.5|V|
|VDD(IO)1|input/output supply voltage 1||VSS0.5|4.0 + 0.5|V|
|II/O|input/output current||-|5|mA|
|II|input current||-|20|mA|
|IDD|supply current||-|90|mA|
|ISS|ground supply current||-|90|mA|
|Ptot|total power dissipation||-|75|mW|
|Tstg|storage temperature||65|+150|C|
|Tamb|ambient temperature||40|+85|C|



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**16-bit I[2] C-bus and SMBus, level translating, low voltage GPIO** 

## **12. Static characteristics** 

**Table 22. Static characteristics** _VDD = 1.1 V to 3.6 V; VDD(IO)0 = 1.1 V to 3.6 V; VDD(IO)1 = 1.1 V to 3.6 V; VSS = 0 V; Tamb =_  _40_  _C to +85_  _C; unless otherwise specified._ 

|**Symbol**|**Parameter**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|**Supplies**|||||||
|VDD|supply voltage||1.1|-|3.6|V|
|VDD(IO)0|input/output supply voltage 0||1.1|-|3.6 + 0.5|V|
|VDD(IO)1|input/output supply voltage 1||1.1|-|3.6 + 0.5|V|
|IDD|supply current|operating mode; VDD= 3.6 V;<br>no load; fSCL= 100 kHz; I/O = inputs|-|135|200|A|
|IstbL|LOW-level standby current|Standby mode; VDD= 3.6 V; no load;<br>VI= VSS; fSCL= 0 kHz; I/O = inputs|-|0.25|2|A|
|IstbH|HIGH-level standby current|Standby mode; VDD= 3.6 V; no load;<br>VI= VDD(IO)0= VDD(IO)1;<br>fSCL= 0 kHz; I/O = inputs|-|0.25|2|A|
|VPOR|power-on reset voltage|no load; VI= VDDor VSS(rising VDD)|-|0.7|1.0|V|
|**Input SCL; input/output SDA**|||||||
|VIL|LOW-level input voltage||0.5|-|+0.3VDD|V|
|VIH|HIGH-level input voltage||0.7VDD|-|3.6|V|
|IOL|LOW-level output current|VOL= 0.2 V; VDD= 1.1 V|1|-|-|mA|
|||VOL= 0.4 V; VDD= 2.3 V|3|-|-|mA|
|IL|leakage current|VI= VDDor VSS|1|-|+1|A|
|Ci|input capacitance|VI= VSS|-|6|10|pF|
|**I/Os**|||||||
|VIL|LOW-level input voltage||0.5|-|+0.3VDD(IO)|V|
|VIH|HIGH-level input voltage||0.7VDD(IO)|-|3.6|V|
|IOL|LOW-level output current|VOL= 0.2 V; VDD(IO)0= 1.1 V;<br>VDD(IO)1= 1.1 V|1|-|-|mA|
|||VOL= 0.5 V; VDD(IO)0= 3.6 V;<br>VDD(IO)1= 3.6 V|2|3|-|mA|
|VOH|HIGH-level output voltage|IOH=1 mA; VDD(IO)0= 1.1 V;<br>VDD(IO)1= 1.1 V|0.8|-|-|V|
|Rpu(int)|internal pull-up resistance||50|100|150|k|
|ILIH|HIGH-level input leakage<br>current|VDD(IO)0= 3.6 V; VDD(IO)1= 3.6 V;<br>VI= VDD(IO)0; VI= VDD(IO)1|-|-|1|A|
|IH|holding current|VI= 0.3 V; VDD(IO)0= 1.1 V;<br>VDD(IO)1= 1.1 V; VDD= 3.6 V|10|-|-|A|
|||VI= 0.8 V; VDD(IO)0= 1.1 V;<br>VDD(IO)1= 1.1 V; VDD= 3.6 V|10|-|-|A|
|ILIL|LOW-level input leakage<br>current|VDD(IO)0= 3.6 V; VDD(IO)1= 3.6 V;<br>VI= VSS|-|-|1|A|
|Ci|input capacitance||-|3.7|5|pF|
|Co|output capacitance||-|3.7|5|pF|



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**16-bit I[2] C-bus and SMBus, level translating, low voltage GPIO** 

**Table 22. Static characteristics** _…continued VDD = 1.1 V to 3.6 V; VDD(IO)0 = 1.1 V to 3.6 V; VDD(IO)1 = 1.1 V to 3.6 V; VSS = 0 V; Tamb =_  _40_  _C to +85_  _C; unless otherwise specified._ 

**==> picture [497 x 323] intentionally omitted <==**

**----- Start of picture text -----**<br>
Symbol Parameter Conditions Min Typ Max Unit<br>Interrupt INT<br>IOL LOW-level output current VOL = 0.4 V; VDD = 1.1 V 3 - - mA<br>Select inputs (reset and address)<br>VIL LOW-level input voltage - - +0.2 V<br>VIH HIGH-level input voltage VDD  0.2 - - V<br>ILI input leakage current 1 - +1 A<br>Ci input capacitance - 2 4 pF<br>002aae767 002aae768<br>3.0 4.0<br>VOH<br>VOH (V)<br>(V)<br>3.0<br>2.0<br>2.0<br>1.0<br>1.0<br>0 0<br>− 40 − 20 0 20 40 60 80 100 − 40 − 20 0 20 40 60 80 100<br>Tamb ( ° C) Tamb ( ° C)<br>Fig 18. VOH at VDD = 3.3 V, VDD(IO)n = 1.2 V, IOH =   1 mA Fig 19. VOH at VDD = 3.3 V, VDD(IO)n = 3.3 V, IOH =   1 mA<br>**----- End of picture text -----**<br>


**==> picture [234 x 186] intentionally omitted <==**

**----- Start of picture text -----**<br>
002aaf069<br>40<br>IOL<br>(mA)<br>30<br>Tamb =  − 40  ° C<br>+25  ° C<br>+85  ° C<br>20<br>10<br>0<br>0 200 400 600 800<br>VOL(typ) (V)<br>a. VDD(IO)0 or VDD(IO)1 = 1.8 V<br>Fig 20. IOL versus VOL<br>**----- End of picture text -----**<br>


**==> picture [233 x 149] intentionally omitted <==**

**----- Start of picture text -----**<br>
002aaf070<br>60<br>IOL<br>(mA)<br>40<br>Tamb =  − 40  ° C<br>+25  ° C<br>+85  ° C<br>20<br>0<br>0 200 400 600 800<br>VOL(typ) (V)<br>**----- End of picture text -----**<br>


b. VDD(IO)0 or VDD(IO)1 = 2.6 V 

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**==> picture [234 x 187] intentionally omitted <==**

**----- Start of picture text -----**<br>
002aaf071<br>24<br>IOH<br>(mA)<br>16<br>T amb = − 40  ° C<br>+25  ° C<br>+85  ° C<br>8<br>0<br>0 0.2 0.4 0.6 0.8<br>VDD −  VOH (V)<br>a. VDD(IO)0 or VDD(IO)1 = 1.8 V<br>Fig 21. IOH versus VOH<br>**----- End of picture text -----**<br>


**==> picture [233 x 149] intentionally omitted <==**

**----- Start of picture text -----**<br>
002aaf072<br>40<br>IOL<br>(mA)<br>30<br>Tamb =  − 40  ° C<br>+25  ° C<br>+85  ° C<br>20<br>10<br>0<br>0 0.2 0.4 0.6 0.8<br>VDD −  VOH (V)<br>**----- End of picture text -----**<br>


b. VDD(IO)0 or VDD(IO)1 = 2.6 V 

## **13. Dynamic characteristics** 

## **Table 23. Dynamic characteristics** 

_VDD = 1.1 V to 3.6 V; VDD(IO)0 = 1.1 V to 3.6 V; VDD(IO)1 = 1.1 V to 3.6 V; VSS = 0 V; Tamb =_  _40_  _C to +85_  _C; unless otherwise specified._ 

|**Symbol**|**Parameter**|**Conditions**|**Standard-mode**<br>**I2C-bus**|**Standard-mode**<br>**I2C-bus**|**Fast-mode I2C-bus**|**Fast-mode I2C-bus**|**Unit**|
|---|---|---|---|---|---|---|---|
||||**Min**|**Max**|**Min**|**Max**||
|fSCL|SCL clock frequency||0|100|0|400|kHz|
|tBUF|bus free time between a STOP and<br>START condition||4.7|-|1.3|-|s|
|tHD;STA|hold time (repeated) START<br>condition||4.0|-|0.6|-|s|
|tSU;STA|set-up time for a repeated START<br>condition||4.7|-|0.6|-|s|
|tSU;STO|set-up time for STOP condition||4.0|-|0.6|-|s|
|tVD;ACK|data valid acknowledge time|[1]|0.3|3.45|0.1|0.9|s|
|tHD;DAT|data hold time||0|-|0|-|ns|
|tVD;DAT|data valid time|[2]|300|-|50|-|ns|
|tSU;DAT|data set-up time||250|-|100|-|ns|
|tLOW|LOW period of the SCL clock||4.7|-|1.3|-|s|
|tHIGH|HIGH period of the SCL clock||4.0|-|0.6|-|s|
|tf|fall time of both SDA and SCL<br>signals||-|300|20 + 0.1C~~b~~[3]|300|ns|
|tr|rise time of both SDA and SCL<br>signals||-|1000|20 + 0.1C~~b~~[3]|300|ns|
|tSP|pulse width of spikes that must be<br>suppressed by the input filter||-|50|-|50|ns|



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PCA9575 

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**Product data sheet** 

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**16-bit I[2] C-bus and SMBus, level translating, low voltage GPIO** 

**Table 23. Dynamic characteristics** _…continued VDD = 1.1 V to 3.6 V; VDD(IO)0 = 1.1 V to 3.6 V; VDD(IO)1 = 1.1 V to 3.6 V; VSS = 0 V; Tamb =_  _40_  _C to +85_  _C; unless otherwise specified._ 

|**Symbol**|**Parameter**|**Conditions**|**Standard-mode**<br>**I2C-bus**|**Standard-mode**<br>**I2C-bus**|**Fast-mode I2C-bus**|**Fast-mode I2C-bus**|**Unit**|
|---|---|---|---|---|---|---|---|
||||**Min**|**Max**|**Min**|**Max**||
|**Port timing**||||||||
|tv(Q)|data output valid time|VDD(IO)0, VDD(IO)1=<br>VDD= 1.1 V|-|350|-|350|ns|
|||VDD(IO)0, VDD(IO)1=<br>VDD= 2.3 V to 3.6 V|-|300|-|300|ns|
|tsu(D)|data input set-up time||150|-|150|-|ns|
|th(D)|data input hold time||1|-|1|-|s|
|**Interrupt timing**||||||||
|tv(INT)|valid time on pin INT||-|4|-|4|s|
|trst(INT)|reset time on pin INT||-|4|-|4|s|
|**Reset**||||||||
|tw(rst)|reset pulse width|VDD(IO)0, VDD(IO)1=<br>VDD= 1.1 V|8|-|8|-|ns|
|||VDD(IO)0, VDD(IO)1=<br>VDD= 2.3 V to 3.6 V|4|-|4|-|ns|
|trec(rst)|reset recovery time||0|-|0|-|ns|
|trst(SDA)|SDA reset time|Figure 23|-|400|-|400|ns|
|trst(GPIO)|GPIO reset time|Figure 23|-|400|-|400|ns|



- [1] tVD;ACK = time for acknowledgement signal from SCL LOW to SDA (out) LOW. 

[2] tVD;DAT = minimum time for SDA data out to be valid following SCL LOW. 

- [3] Cb = total capacitance of one bus line in pF. 

**==> picture [479 x 126] intentionally omitted <==**

**----- Start of picture text -----**<br>
���������<br>���<br>���������<br>���� �� �� ������� ���<br>����<br>���������<br>���<br>���������<br>������� ������� �������<br>� � ������� ����� ������� �� �<br>���������<br>**----- End of picture text -----**<br>


**Fig 22. Definition of timing** 

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## **16-bit I[2] C-bus and SMBus, level translating, low voltage GPIO** 

**==> picture [411 x 162] intentionally omitted <==**

**----- Start of picture text -----**<br>
START ACK or read cycle<br>SCL<br>SDA<br>30 %<br>30 %<br>trst(SDA)<br>RESET 50 % 50 % 50 %<br>trec(rst)<br>tw(rst)<br>trst(GPIO)<br>P0_0 to P0_7 50 %<br>P1_0 to P1_7 output off<br>002aad574<br>**----- End of picture text -----**<br>


**Fig 23. Reset timing** 

## **14. Test information** 

**==> picture [215 x 91] intentionally omitted <==**

**----- Start of picture text -----**<br>
2VDD<br>open<br>VDD RL VSS<br>500  Ω<br>VI VO<br>PULSE<br>DUT<br>GENERATOR<br>RT CL 500  Ω [(1)]<br>50 pF<br>002aad582<br>**----- End of picture text -----**<br>


RL = load resistance. 

CL = load capacitance includes jig and probe capacitance. 

RT = termination resistance should be equal to the output impedance Zo of the pulse generators. 

(1) For SDA, no 500  pull-down. 

**Fig 24. Test circuitry for switching times** 

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## **15. Package outline** 

**Fig 25. Package outline SOT355-1 (TSSOP24)** 

PCA9575 

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**==> picture [198 x 27] intentionally omitted <==**

**----- Start of picture text -----**<br>
Fig 26. Package outline SOT361-1 (TSSOP28)<br>PCA9575 All information provided in this document is subject to legal disclaimers.<br>**----- End of picture text -----**<br>


All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. 

**Product data sheet** 

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**16-bit I[2] C-bus and SMBus, level translating, low voltage GPIO** 

**==> picture [201 x 10] intentionally omitted <==**

**----- Start of picture text -----**<br>
Fig 27. Package outline SOT994-1 (HWQFN24)<br>**----- End of picture text -----**<br>


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**16-bit I[2] C-bus and SMBus, level translating, low voltage GPIO** 

## **16. Handling information** 

All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in _JESD625-A_ or equivalent standards. 

## **17. Soldering of SMD packages** 

This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note _AN10365 “Surface mount reflow soldering description”_ . 

## **17.1 Introduction to soldering** 

Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 

## **17.2 Wave and reflow soldering** 

Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: 

- Through-hole components 

- Leaded or leadless SMDs, which are glued to the surface of the printed circuit board 

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. 

The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. 

Key characteristics in both wave and reflow soldering are: 

- Board specifications, including the board finish, solder masks and vias 

- Package footprints, including solder thieves and orientation 

- The moisture sensitivity level of the packages 

- Package placement 

- Inspection and repair 

- Lead-free soldering versus SnPb soldering 

## **17.3 Wave soldering** 

Key characteristics in wave soldering are: 

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**16-bit I[2] C-bus and SMBus, level translating, low voltage GPIO** 

- Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave 

- Solder bath specifications, including temperature and impurities 

## **17.4 Reflow soldering** 

Key characteristics in reflow soldering are: 

- Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 28) than a SnPb process, thus reducing the process window 

- Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board 

- Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 24 and 25 

## **Table 24. SnPb eutectic process (from J-STD-020D)** 

|**Package thickness (mm)**|**Package reflow temperature (****C)**|**Package reflow temperature (****C)**|
|---|---|---|
||**Volume (mm3)**||
||**< 350**|**350**|
|< 2.5|235|220|
|2.5|220|220|



## **Table 25. Lead-free process (from J-STD-020D)** 

|**Package thickness (mm)**|**Package reflow temperature (****C)**|**Package reflow temperature (****C)**|**Package reflow temperature (****C)**|
|---|---|---|---|
||**Volume (mm3)**|||
||**< 350**|**350 to 2000**|**> 2000**|
|< 1.6|260|260|260|
|1.6 to 2.5|260|250|245|
|> 2.5|250|245|245|



Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. 

Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 28. 

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## **16-bit I[2] C-bus and SMBus, level translating, low voltage GPIO** 

**==> picture [352 x 223] intentionally omitted <==**

**----- Start of picture text -----**<br>
maximum peak temperature<br>= MSL limit, damage level<br>temperature<br>minimum peak temperature<br>= minimum soldering temperature<br>peak<br> temperature<br>time<br>001aac844<br>MSL: Moisture Sensitivity Level<br>Fig 28. Temperature profiles for large and small components<br>**----- End of picture text -----**<br>


For further information on temperature profiles, refer to Application Note _AN10365 “Surface mount reflow soldering description”_ . 

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PCA9575 

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**16-bit I[2] C-bus and SMBus, level translating, low voltage GPIO** 

## **18. Soldering: PCB footprints** 

**==> picture [277 x 10] intentionally omitted <==**

**----- Start of picture text -----**<br>
Fig 29. PCB footprint for SOT355-1 (TSSOP24); reflow soldering<br>**----- End of picture text -----**<br>


PCA9575 

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**Product data sheet** 

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**16-bit I[2] C-bus and SMBus, level translating, low voltage GPIO** 

## **Fig 30. PCB footprint for SOT361-1 (TSSOP28); reflow soldering** 

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**16-bit I[2] C-bus and SMBus, level translating, low voltage GPIO** 

## **Fig 31.** 

## **PCB footprint for SOT994-1 (HWQFN24); reflow soldering** 

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**16-bit I[2] C-bus and SMBus, level translating, low voltage GPIO** 

## **19. Abbreviations** 

## **Table 26. Abbreviations** 

|**Acronym**|**Description**|
|---|---|
|CBT|Cross Bar Technology|
|CDM|Charged Device Model|
|CMOS|Complementary Metal Oxide Semiconductor|
|DUT|Device Under Test|
|ESD|ElectroStatic Discharge|
|GPIO|General Purpose Input/Output|
|HBM|Human Body Model|
|I/O|Input/Output|
|I2C-bus|Inter-Integrated Circuit bus|
|IC|Integrated Circuit|
|LED|Light Emitting Diode|
|LP|Low Pass|
|MM|Machine Model|
|PLC|Programmable Logic Controller|
|POR|Power-On Reset|
|RAID|Redundant Array of Independent Discs|
|RF|Radio Frequency|
|SMBus|System Management Bus|



## **20. Revision history** 

## **Table 27. Revision history** 

|**Document ID**|**Release date**|**Data sheet status**|**Change notice**|**Supersedes**|
|---|---|---|---|---|
|PCA9575 v.4.2|20150416|Product data sheet|-|PCA9575 v.4.1|
|Modifications:|**•** Table 22“<br>Static characteristics<br>”<br>:VDD(IO)0and VDD(IO)1, clarified max from “VDD+ 0.5” to “3.6 + 0.5”<br>**•** Table 21“<br>Limiting values<br>”<br>:VDD(IO)0and VDD(IO)1, clarified max from “VDD+ 0.5” to “4.0 + 0.5”||||
|PCA9575 v.4.1|20150407|Product data sheet|-|PCA9575 v.4|
|PCA9575 v.4|20140520|Product data sheet|-|PCA9575 v.3|
|PCA9575 v.3|20091109|Product data sheet|-|PCA9575 v.2|
|PCA9575 v.2|20090727|Product data sheet|-|PCA9575 v.1|
|PCA9575 v.1|20081002|Product data sheet|-|-|



© NXP Semiconductors N.V. 2015. All rights reserved. 

PCA9575 

All information provided in this document is subject to legal disclaimers. **Rev. 4.2 — 16 April 2015** 

**Product data sheet** 

**39 of 42** 

**PCA9575** 

**NXP Semiconductors** 

**16-bit I[2] C-bus and SMBus, level translating, low voltage GPIO** 

## **21. Legal information** 

## **21.1 Data sheet status** 

|**Document status[1]**<br>**[2]**|**Product statu**~~**s**~~**[3]**|**Definition**|
|---|---|---|
|Objective [short] data sheet|Development|This document contains data from the objective specification for product development.|
|Preliminary [short] data sheet|Qualification|This document contains data from the preliminary specification.|
|Product [short] data sheet|Production|This document contains the product specification.|



[1] Please consult the most recently issued document before initiating or completing a design. 

[2] The term ‘short data sheet’ is explained in section “Definitions”. 

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 

## **21.2 Definitions** 

**Suitability for use —** NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. 

**Draft —** The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 

**Short data sheet —** A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 

**Applications —** Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 

Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. 

**Product specification —** The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 

NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. 

## **21.3 Disclaimers** 

**Limited warranty and liability —** Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. 

**Limiting values —** Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. 

In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. 

**Terms and conditions of commercial sale —** NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. 

Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the _Terms and conditions of commercial sale_ of NXP Semiconductors. 

**Right to make changes —** NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 

**No offer to sell or license —** Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 

© NXP Semiconductors N.V. 2015. All rights reserved. 

PCA9575 All information provided in this document is subject to legal disclaimers. 

**Product data sheet** 

**Rev. 4.2 — 16 April 2015** 

**40 of 42** 

**PCA9575** 

**NXP Semiconductors** 

## **16-bit I[2] C-bus and SMBus, level translating, low voltage GPIO** 

**Export control —** This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 

**Non-automotive qualified products —** Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. 

In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s 

own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 

**Translations —** A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 

## **21.4 Trademarks** 

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. **I[2] C-bus  —** logo is a trademark of NXP Semiconductors N.V. 

## **22. Contact information** 

For more information, please visit: **http://www.nxp.com** 

For sales office addresses, please send an email to: **salesaddresses@nxp.com** 

© NXP Semiconductors N.V. 2015. All rights reserved. 

PCA9575 

All information provided in this document is subject to legal disclaimers. 

**Product data sheet** 

**Rev. 4.2 — 16 April 2015** 

**41 of 42** 

**PCA9575** 

**NXP Semiconductors** 

**16-bit I[2] C-bus and SMBus, level translating, low voltage GPIO** 

## **23. Contents** 

|**1**|**General description . . . . . . . . . . . . . . . . . . . . . .  1**|**9**|**Bus transactions. . . . . . . . . . . . . . . . . . . . . . .  22**|
|---|---|---|---|
|**2**|**Features and benefits . . . . . . . . . . . . . . . . . . . .  2**|**10**|**Application design-in information. . . . . . . . .  24**|
|**3**|**Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .  3**|**11**|**Limiting values . . . . . . . . . . . . . . . . . . . . . . . .  24**|
|**4**|**Ordering information. . . . . . . . . . . . . . . . . . . . .  3**|**12**|**Static characteristics  . . . . . . . . . . . . . . . . . . .  25**|
|4.1|Ordering options . . . . . . . . . . . . . . . . . . . . . . . .  3|**13**|**Dynamic characteristics. . . . . . . . . . . . . . . . .  27**|
|**5**|**Block diagram  . . . . . . . . . . . . . . . . . . . . . . . . . .  4**|**14**|**Test information  . . . . . . . . . . . . . . . . . . . . . . .  29**|
|**6**|**Pinning information. . . . . . . . . . . . . . . . . . . . . .  6**|**15**|**Package outline. . . . . . . . . . . . . . . . . . . . . . . .  30**|
|6.1|Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6|**16**|**Handling information . . . . . . . . . . . . . . . . . . .  33**|
|6.2|Pin description  . . . . . . . . . . . . . . . . . . . . . . . . .  7|**17**|**Soldering of SMD packages. . . . . . . . . . . . . .  33**|
|**7**|**Functional description  . . . . . . . . . . . . . . . . . . .  8**|17.1|Introduction to soldering. . . . . . . . . . . . . . . . .  33|
|7.1|I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8|17.2|Wave and reflow soldering. . . . . . . . . . . . . . .  33|
|7.2|Device address. . . . . . . . . . . . . . . . . . . . . . . . .  8|17.3|Wave soldering  . . . . . . . . . . . . . . . . . . . . . . .  33|
|7.3|Command register  . . . . . . . . . . . . . . . . . . . . . .  9|17.4|Reflow soldering  . . . . . . . . . . . . . . . . . . . . . .  34|
|7.4<br>7.5<br>7.6<br>7.6.1|Register definitions . . . . . . . . . . . . . . . . . . . . . .  9<br>Writing to port registers. . . . . . . . . . . . . . . . . .  10<br>Reading the port registers  . . . . . . . . . . . . . . .  10<br>Register 0 - Input port 0 register. . . . . . . . . . .  10|**18**<br>**19**<br>**20**|**Soldering: PCB footprints  . . . . . . . . . . . . . . .  36**<br>**Abbreviations  . . . . . . . . . . . . . . . . . . . . . . . . .  39**<br>**Revision history  . . . . . . . . . . . . . . . . . . . . . . .  39**|
|7.6.2|Register 1 - Input port 1 register. . . . . . . . . . .  11|**21**|**Legal information . . . . . . . . . . . . . . . . . . . . . .  40**|
|7.6.3|Register 2 - Polarity inversion port 0 register .  11|21.1|Data sheet status . . . . . . . . . . . . . . . . . . . . . .  40|
|7.6.4|Register 3 - Polarity inversion port 1 register .  12|21.2|Definitions  . . . . . . . . . . . . . . . . . . . . . . . . . . .  40|
|7.6.5|Register 4 - Bus-hold/pull-up/pull-down|21.3|Disclaimers  . . . . . . . . . . . . . . . . . . . . . . . . . .  40|
||enable 0 register. . . . . . . . . . . . . . . . . . . . . . .  12|21.4|Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .  41|
|7.6.6|Register 5 - Bus-hold/pull-up/pull-down|**22**|**Contact information  . . . . . . . . . . . . . . . . . . . .  41**|
||enable 1 register. . . . . . . . . . . . . . . . . . . . . . .  13|**23**|**Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  42**|
|7.6.7|Register 6 - Pull-up/pull-down select port 0|||
||register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  14|||
|7.6.8|Register 7 - Pull-up/pull-down select port 1|||
||register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  14|||
|7.6.9|Register 8 - Configuration port 0 register . . . .  15|||
|7.6.10|Register 9 - Configuration port 1 register . . . .  15|||
|7.6.11|Register 10 - Output port 0 register  . . . . . . . .  16|||
|7.6.12|Register 11 - Output port 1 register  . . . . . . . .  16|||
|7.6.13|Register 12 - Interrupt mask port 0 register . .  17|||
|7.6.14|Register 13 - Interrupt mask port 1 register . .  17|||
|7.6.15|Register 14 - Interrupt status port 0 register. .  18|||
|7.6.16|Register 15 - Interrupt status port 1 register. .  18|||
|7.7|Power-on reset . . . . . . . . . . . . . . . . . . . . . . . .  18|||
|7.8|RESET<br>input. . . . . . . . . . . . . . . . . . . . . . . . . .  18|||
|7.9|Software reset. . . . . . . . . . . . . . . . . . . . . . . . .  19|||
|7.10|Interrupt output (INT<br>)  . . . . . . . . . . . . . . . . . . .  19|||
|7.11|Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  19|||
|**8**|**Characteristics of the I2C-bus  . . . . . . . . . . . .  20**|||
|8.1|Bit transfer  . . . . . . . . . . . . . . . . . . . . . . . . . . .  20|||
|8.1.1|START and STOP conditions . . . . . . . . . . . . .  20|||
|8.2|System configuration  . . . . . . . . . . . . . . . . . . .  20|||
|8.3|Acknowledge  . . . . . . . . . . . . . . . . . . . . . . . . .  21|||



Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 

**© NXP Semiconductors N.V. 2015.** 

**All rights reserved.** 

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com **Date of release: 16 April 2015 Document identifier: PCA9575**