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PCA9555DB,118
I/O Expander, 16bit, 400 kHz, I2C, SMBus, 2.3 V, 5.5 V, SSOP
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- Manufacturer: NXP
- Product type: I/O Expanders
| Delivery and price | |
|---|---|
| Units per pack | 50 |
| Price | 2.45 € |
| Current stock | 1000+ |
| Lead time | 7 days |
Datasheet
**PCA9555** ## **16-bit I[2] C-bus and SMBus I/O port with interrupt** **Rev. 10 — 8 November 2017** **Product data sheet** ## **1. General description** The PCA9555 is a 24-pin CMOS device that provides 16 bits of General Purpose parallel Input/Output (GPIO) expansion for I[2] C-bus/SMBus applications and was developed to enhance the NXP Semiconductors family of I[2] C-bus I/O expanders. The improvements include higher drive capability, 5 V I/O tolerance, lower supply current, individual I/O configuration, and smaller packaging. I/O expanders provide a simple solution when additional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc. The PCA9555 consists of two 8-bit Configuration (Input or Output selection); Input, Output and Polarity Inversion (active HIGH or active LOW operation) registers. The system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each Input or Output is kept in the corresponding Input or Output register. The polarity of the read register can be inverted with the Polarity Inversion register. All registers can be read by the system master. Although pin-to-pin and I[2] C-bus address compatible with the PCF8575, software changes are required due to the enhancements, and are discussed in _Application Note AN469_ . The PCA9555 open-drain interrupt output is activated when any input state differs from its corresponding input port register state and is used to indicate to the system master that an input state has changed. The power-on reset sets the registers to their default values and initializes the device state machine. Three hardware pins (A0, A1, A2) vary the fixed I[2] C-bus address and allow up to eight devices to share the same I[2] C-bus/SMBus. The fixed I[2] C-bus address of the PCA9555 is the same as the PCA9554, allowing up to eight of these devices in any combination to share the same I[2] C-bus/SMBus. ## **2. Features and benefits** - Operating power supply voltage range of 2.3 V to 5.5 V - 5 V tolerant I/Os - Polarity Inversion register - Active LOW interrupt output - Low standby current - Noise filter on SCL/SDA inputs - No glitch on power-up - Internal power-on reset - 16 I/O pins which default to 16 inputs - 0 Hz to 400 kHz clock frequency - ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 **==> picture [173 x 100] intentionally omitted <==** **PCA9555** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus I/O port with interrupt** Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Five packages offered: SO24, SSOP24, TSSOP24, HVQFN24 and HWQFN24 ## **3. Ordering information** **Table 1. Ordering information** |**Type number**|**Topside mark**|**Package**|**Package**|**Package**| |---|---|---|---|---| |||**Name**|**Description**|**Version**| |PCA9555D<br>PCA9555D||SO24<br>plastic small outline package; 24 leads;<br>body width 7.5 mm<br>SOT137-1||| |PCA9555DB<br>PCA9555||SSOP24<br>plastic shrink small outline package; 24 leads;<br>bodywidth 5.3 mm<br>SOT340-1||| |PCA9555PW<br>PCA9555||TSSOP24<br>plastic thin shrink small outline package; 24 leads;<br>body width 4.4 mm<br>SOT355-1||| |PCA9555BS<br>9555||HVQFN24<br>plastic thermal enhanced very thin quad flat package;<br>no leads; 24 terminals; body 440.85 mm<br>SOT616-1||| |PCA9555HF<br>P55H||HWQFN24<br>plastic thermal enhanced very very thin quad flat<br>package; no leads; 24 terminals; body 440.75 mm<br>SOT994-1||| ## **3.1 Ordering options** **Table 2. Ordering options** |**Type number**|**Orderable**<br>**part number**|**Package**|**Packing method**|**Minimum**<br>**order**<br>**quantity**|**Temperature**| |---|---|---|---|---|---| |PCA9555D|PCA9555D,112|SO24|STANDARD MARKING * IC'S<br>TUBE - DSC BULK PACK|1200|Tamb=40C to +85C| ||PCA9555D,118|SO24|REEL 13" Q1/T1 *STANDARD<br>MARK SMD|1000|| |PCA9555DB|PCA9555DB,112|SSOP24|STANDARD MARKING * IC'S<br>TUBE - DSC BULK PACK|826|Tamb=40C to +85C| ||PCA9555DB,118|SSOP24|REEL 13" Q1/T1 *STANDARD<br>MARK SMD|1000|| |PCA9555PW|PCA9555PW,112|TSSOP24|STANDARD MARKING * IC'S<br>TUBE - DSC BULK PACK|1575|Tamb=40C to +85C| ||PCA9555PW,118|TSSOP24|REEL 13" Q1/T1 *STANDARD<br>MARK SMD|2500|| |PCA9555BS|PCA9555BS,118|HVQFN24|REEL 13" Q1/T1 *STANDARD<br>MARK SMD|6000|Tamb=40C to +85C| ||PCA9555BSHP|HVQFN24|REEL 13" Q2/T3 *STANDARD<br>MARK SMD|6000|| |PCA9555HF|PCA9555HF,118|HWQFN24|REEL 13" Q1/T1 *STANDARD<br>MARK SMD|6000|Tamb=40C to +85C| © NXP Semiconductors N.V. 2017. All rights reserved. PCA9555 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 10 — 8 November 2017** **2 of 34** **PCA9555** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus I/O port with interrupt** ## **4. Block diagram** **==> picture [371 x 321] intentionally omitted <==** **----- Start of picture text -----**<br> PCA9555<br>IO1_0<br>IO1_1<br>A0 8-bit IO1_2<br>A1 INPUT/ IO1_3<br>OUTPUT<br>A2 PORTS IO1_4<br>write pulse IO1_5<br>IO1_6<br>read pulse<br>IO1_7<br>I [2] C-BUS/SMBus<br>CONTROL<br>SCL INPUT IO0_0<br>FILTER IO0_1<br>SDA 8-bit IO0_2<br>INPUT/ IO0_3<br>OUTPUT<br>PORTS IO0_4<br>write pulse IO0_5<br>IO0_6<br>read pulse<br>VDD POWER-ON IO0_7<br>RESET<br>VSS VDD<br>LP filter<br>INT<br>002aac702<br>Remark: All I/Os are set to inputs at reset.<br>Fig 1. Block diagram of PCA9555<br>**----- End of picture text -----**<br> ## **5. Pinning information** ## **5.1 Pinning** **==> picture [144 x 162] intentionally omitted <==** **----- Start of picture text -----**<br> INT 1 24 VDD<br>A1 2 23 SDA<br>A2 3 22 SCL<br>IO0_0 4 21 A0<br>IO0_1 5 20 IO1_7<br>IO0_2 6 19 IO1_6<br>PCA9555D<br>IO0_3 7 18 IO1_5<br>IO0_4 8 17 IO1_4<br>IO0_5 9 16 IO1_3<br>IO0_6 10 15 IO1_2<br>IO0_7 11 14 IO1_1<br>VSS 12 13 IO1_0<br>002aac698<br>**----- End of picture text -----**<br> **Fig 2. Pin configuration for SO24** © NXP Semiconductors N.V. 2017. All rights reserved. PCA9555 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 10 — 8 November 2017** **3 of 34** **PCA9555** **NXP Semiconductors** ## **16-bit I[2] C-bus and SMBus I/O port with interrupt** **==> picture [396 x 394] intentionally omitted <==** **----- Start of picture text -----**<br> INT 1 24 VDD INT 1 24 VDD<br>A1 2 23 SDA A1 2 23 SDA<br>A2 3 22 SCL A2 3 22 SCL<br>IO0_0 4 21 A0 IO0_0 4 21 A0<br>IO0_1 5 20 IO1_7 IO0_1 5 20 IO1_7<br>IO0_2 6 19 IO1_6 IO0_2 6 19 IO1_6<br>PCA9555DB PCA9555PW<br>IO0_3 7 18 IO1_5 IO0_3 7 18 IO1_5<br>IO0_4 8 17 IO1_4 IO0_4 8 17 IO1_4<br>IO0_5 9 16 IO1_3 IO0_5 9 16 IO1_3<br>IO0_6 10 15 IO1_2 IO0_6 10 15 IO1_2<br>IO0_7 11 14 IO1_1 IO0_7 11 14 IO1_1<br>VSS 12 13 IO1_0 VSS 12 13 IO1_0<br>002aac699 002aac700<br>Fig 3. Pin configuration for SSOP24 Fig 4. Pin configuration for TSSOP24<br>terminal 1 terminal 1<br>index area index area<br>IO0_0 1 18 A0 IO0_0 1 18 A0<br>IO0_1 2 17 IO1_7 IO0_1 2 17 IO1_7<br>IO0_2 3 16 IO1_6 IO0_2 3 PCA9555HF 16 IO1_6<br>PCA9555BS<br>IO0_3 4 15 IO1_5 IO0_3 4 15 IO1_5<br>IO0_4 5 14 IO1_4 IO0_4 5 14 IO1_4<br>IO0_5 6 13 IO1_3 IO0_5 6 13 IO1_3<br>002aac881<br>002aac701<br>Transparent top view Transparent top view<br>Fig 5. Pin configuration for HVQFN24 Fig 6. Pin configuration for HWQFN24<br>A2 A1 INT VDD SDA SCL A2 A1 INT VDD SDA SCL<br>24 23 22 21 20 19<br>24 23 22 21 20 19<br>7 8 9 10 11 12 7 8 9 10 11 12<br>SS<br>SS V<br>V<br>IO0_6 IO0_7 IO1_0 IO1_1 IO1_2<br>IO0_6 IO0_7 IO1_0 IO1_1 IO1_2<br>**----- End of picture text -----**<br> © NXP Semiconductors N.V. 2017. All rights reserved. PCA9555 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 10 — 8 November 2017** **4 of 34** **PCA9555** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus I/O port with interrupt** ## **5.2 Pin description** |**Table 3.**<br>|**Pin description**|**Pin description**|**Pin description**| |---|---|---|---| |**Symbol**|**Pin**||**Description**| ||**SO24, SSOP24,**<br>**TSSOP24**|**HVQFN24,**<br>**HWQFN24**|| |INT|1|22|interrupt output (open-drain)| |A1|2|23|address input 1| |A2|3|24|address input 2| |IO0_0|4|1|port 0 input/output| |IO0_1|5|2|| |IO0_2|6|3|| |IO0_3|7|4|| |IO0_4|8|5|| |IO0_5|9|6|| |IO0_6|10|7|| |IO0_7|11|8|| |VSS|12|~~9~~[1]|supply ground| |IO1_0|13|10|port 1 input/output| |IO1_1|14|11|| |IO1_2|15|12|| |IO1_3|16|13|| |IO1_4|17|14|| |IO1_5|18|15|| |IO1_6|19|16|| |IO1_7|20|17|| |A0|21|18|address input 0| |SCL|22|19|serial clock line| |SDA|23|20|serial data line| |VDD|24|21|supply voltage| - [1] HVQFN and HWQFN package die supply ground is connected to both the VSS pin and the exposed center pad. The VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board-level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias need to be incorporated in the PCB in the thermal pad region. © NXP Semiconductors N.V. 2017. All rights reserved. PCA9555 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 10 — 8 November 2017** **5 of 34** **PCA9555** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus I/O port with interrupt** ## **6. Functional description** “ ” Refer to Figure 1 Block diagram of PCA9555 . ## **6.1 Device address** **==> picture [138 x 56] intentionally omitted <==** **----- Start of picture text -----**<br> slave address<br>0 1 0 0 A2 A1 A0 R/W<br>fixed programmable<br>002aac219<br>**----- End of picture text -----**<br> **Fig 7. PCA9555 device address** ## **6.2 Registers** ## **6.2.1 Command byte** The command byte is the first byte to follow the address byte during a write transmission. It is used as a pointer to determine which of the following registers will be written or read. ## **Table 4. Command byte** |**Command**|**Register**| |---|---| |0|Input port 0| |1|Input port 1| |2|Output port 0| |3|Output port 1| |4|Polarity Inversion port 0| |5|Polarity Inversion port 1| |6|Configuration port 0| |7|Configuration port 1| © NXP Semiconductors N.V. 2017. All rights reserved. PCA9555 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 10 — 8 November 2017** **6 of 34** **PCA9555** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus I/O port with interrupt** ## **6.2.2 Registers 0 and 1: Input port registers** This register is an input-only port. It reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by Register 3. Writes to this register have no effect. The default value ‘X’ is determined by the externally applied logic level. ## **Table 5. Input port 0 Register** |**Bit**|**7**|**6**|**5**|**4**|**3**|**2**|**1**|**0**| |---|---|---|---|---|---|---|---|---| |**Symbol**|I0.7|I0.6|I0.5|I0.4|I0.3|I0.2|I0.1|I0.0| |**Default**|X|X|X|X|X|X|X|X| |**Table 6.**<br>**Input port 1 register**||||||||| |**Bit**|**7**|**6**|**5**|**4**|**3**|**2**|**1**|**0**| |**Symbol**|I1.7|I1.6|I1.5|I1.4|I1.3|I1.2|I1.1|I1.0| |**Default**|X|X|X|X|X|X|X|X| ## **6.2.3 Registers 2 and 3: Output port registers** This register is an output-only port. It reflects the outgoing logic levels of the pins defined as outputs by Registers 6 and 7. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, **not** the actual pin value. ## **Table 7. Output port 0 register** |**Bit**|**7**|**6**|**5**|**4**|**3**|**2**|**1**|**0**| |---|---|---|---|---|---|---|---|---| |**Symbol**|O0.7|O0.6|O0.5|O0.4|O0.3|O0.2|O0.1|O0.0| |**Default**|1|1|1|1|1|1|1|1| |**Table 8.**<br>**Output port 1 register**||||||||| |**Bit**|**7**|**6**|**5**|**4**|**3**|**2**|**1**|**0**| |**Symbol**|O1.7|O1.6|O1.5|O1.4|O1.3|O1.2|O1.1|O1.0| |**Default**|1|1|1|1|1|1|1|1| ## **6.2.4 Registers 4 and 5: Polarity Inversion registers** This register allows the user to invert the polarity of the Input port register data. If a bit in this register is set (written with ‘1’), the Input port data polarity is inverted. If a bit in this register is cleared (written with a ‘0’), the Input port data polarity is retained. ## **Table 9. Polarity Inversion port 0 register** |**Bit**|**7**|**6**|**5**|**4**|**3**|**2**|**1**|**0**| |---|---|---|---|---|---|---|---|---| |**Symbol**|N0.7|N0.6|N0.5|N0.4|N0.3|N0.2|N0.1|N0.0| |**Default**|0|0|0|0|0|0|0|0| |**Table 10.**<br>**Polarity Inversion port 1 register**||||||||| |**Bit**|**7**|**6**|**5**|**4**|**3**|**2**|**1**|**0**| |**Symbol**|N1.7|N1.6|N1.5|N1.4|N1.3|N1.2|N1.1|N1.0| |**Default**|0|0|0|0|0|0|0|0| All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. PCA9555 **Product data sheet** **Rev. 10 — 8 November 2017** **7 of 34** **PCA9555** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus I/O port with interrupt** ## **6.2.5 Registers 6 and 7: Configuration registers** This register configures the directions of the I/O pins. If a bit in this register is set (written with ‘1’), the corresponding port pin is enabled as an input with high-impedance output driver. If a bit in this register is cleared (written with ‘0’), the corresponding port pin is enabled as an output. Note that there is a high value resistor tied to VDD at each pin. At reset, the device's ports are inputs with a pull-up to VDD. ## **Table 11. Configuration port 0 register** |**Bit**|**7**|**6**|**5**|**4**|**3**|**2**|**1**|**0**| |---|---|---|---|---|---|---|---|---| |**Symbol**|C0.7|C0.6|C0.5|C0.4|C0.3|C0.2|C0.1|C0.0| |**Default**|1|1|1|1|1|1|1|1| |**Table 12.**<br>**Configuration port 1 register**||||||||| |**Bit**|**7**|**6**|**5**|**4**|**3**|**2**|**1**|**0**| |**Symbol**|C1.7|C1.6|C1.5|C1.4|C1.3|C1.2|C1.1|C1.0| |**Default**|1|1|1|1|1|1|1|1| ## **6.3 Power-on reset** When power is applied to VDD, an internal power-on reset holds the PCA9555 in a reset condition until VDD has reached VPOR. At that point, the reset condition is released and the PCA9555 registers and SMBus state machine will initialize to their default states. The power-on reset typically completes the reset and enables the part by the time the power supply is above VPOR. However, when it is required to reset the part by lowering the power supply, it is necessary to lower it below 0.2 V. ## **6.4 I/O port** When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input with a weak pull-up to VDD. The input voltage may be raised above VDD to a maximum of 5.5 V. If the I/O is configured as an output, then either Q1 or Q2 is on, depending on the state of the Output Port register. Care should be exercised if an external voltage is applied to an I/O configured as an output because of the low-impedance path that exists between the pin and either VDD or VSS. © NXP Semiconductors N.V. 2017. All rights reserved. PCA9555 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 10 — 8 November 2017** **8 of 34** **PCA9555** **NXP Semiconductors** ## **16-bit I[2] C-bus and SMBus I/O port with interrupt** **==> picture [370 x 285] intentionally omitted <==** **----- Start of picture text -----**<br> data from output port<br>shift register register data<br>configuration<br>register VDD<br>data from<br>D Q Q1<br>shift register<br>FF 100 k Ω<br>write<br>D Q<br>configuration CK Q<br>pulse FF<br>I/O pin<br>write pulse CK Q2<br>output port input port VSS<br>register register<br>D Q<br>input port<br>FF register data<br>read pulse CK<br>to INT<br>polarity inversion<br>register<br>data from<br>D Q polarity<br>shift register inversion<br>FF register data<br>write polarity<br>CK<br>pulse<br>002aac703<br>At power-on reset, all registers return to default values.<br>**----- End of picture text -----**<br> **Fig 8. Simplified schematic of I/Os** ## **6.5 Bus transactions** ## **6.5.1 Writing to the port registers** Data is transmitted to the PCA9555 by sending the device address and setting the least significant bit to a logic 0 (see Figure 7 “PCA9555 device address”). The command byte is sent after the address and determines which register will receive the data following the command byte. The eight registers within the PCA9555 are configured to operate as four register pairs. The four pairs are Input Ports, Output Ports, Polarity Inversion Ports, and Configuration Ports. After sending data to one register, the next data byte will be sent to the other register in the pair (see Figure 9 and Figure 10). For example, if the first byte is sent to Output Port 1 (register 3), then the next byte will be stored in Output Port 0 (register 2). There is no limitation on the number of data bytes sent in one write transmission. In this way, each 8-bit register may be updated independently of the other registers. © NXP Semiconductors N.V. 2017. All rights reserved. PCA9555 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 10 — 8 November 2017** **9 of 34** **==> picture [534 x 176] intentionally omitted <==** **----- Start of picture text -----**<br> SCL 1 2 3 4 5 6 7 8 9<br>slave address command byte data to port 0 data to port 1<br>SDA S 0 1 0 0 A2 A1 A0 0 A 0 0 0 0 0 0 1 0 A 0.7 DATA 0 0.0 A 1.7 DATA 1 1.0 A P<br>START condition R/W acknowledge acknowledge acknowledge STOP<br>from slave from slave from slave condition<br>write to port<br>tv(Q)<br>data out<br>from port 0<br>tv(Q)<br>data out<br>from port 1 DATA VALID<br>002aac220<br>**----- End of picture text -----**<br> **Fig 9. Write to Output port registers** **==> picture [511 x 90] intentionally omitted <==** **----- Start of picture text -----**<br> SCL 1 2 3 4 5 6 7 8 9<br>data to register data to register<br>slave address command byte<br>MSB LSB MSB LSB<br>SDA S 0 1 0 0 A2 A1 A0 0 A 0 0 0 0 0 1 1 0 A DATA 0 A DATA 1 A P<br>START condition R/W acknowledge acknowledge acknowledge STOP<br>from slave from slave from slave condition<br>002aac221<br>**----- End of picture text -----**<br> ## **Fig 10. Write to Configuration registers** **PCA9555** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus I/O port with interrupt** ## **6.5.2 Reading the port registers** In order to read data from the PCA9555, the bus master must first send the PCA9555 address with the least significant bit set to a logic 0 (see Figure 7 “PCA9555 device address”). The command byte is sent after the address and determines which register will be accessed. After a restart, the device address is sent again, but this time the least significant bit is set to a logic 1. Data from the register defined by the command byte will then be sent by the PCA9555 (see Figure 11, Figure 12 and Figure 13). Data is clocked into the register on the falling edge of the acknowledge clock pulse. After the first byte is read, additional bytes may be read but the data will now reflect the information in the other register in the pair. For example, if you read Input Port 1, then the next byte read would be Input Port 0. There is no limitation on the number of data bytes received in one read transmission but the final byte received, the bus master must not acknowledge the data. **==> picture [434 x 165] intentionally omitted <==** **----- Start of picture text -----**<br> slave address<br>SDA S 0 1 0 0 A2 A1 A0 0 A COMMAND BYTE A (cont.)<br>START condition R/W acknowledge<br>acknowledge from slave<br>from slave<br>data from lower or data from upper or<br>upper byte of register lower byte of register<br>slave address<br>MSB LSB MSB LSB<br>(cont.) S 0 1 0 0 A2 A1 A0 1 A DATA (first byte) A DATA (last byte) NA P<br>(repeated) R/W acknowledge no acknowledge STOP<br>START condition acknowledge from master from master condition<br>from slave<br>at this moment master-transmitter becomes master-receiver<br>and slave-receiver becomes slave-transmitter<br>002aac222<br>**----- End of picture text -----**<br> **Remark:** Transfer can be stopped at any time by a STOP condition. **Fig 11. Read from register** © NXP Semiconductors N.V. 2017. All rights reserved. PCA9555 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 10 — 8 November 2017** **11 of 34** **==> picture [618 x 228] intentionally omitted <==** **----- Start of picture text -----**<br> data into port 0<br>data into port 1<br>INT<br>tv(INT_N) trst(INT_N)<br>SCL 1 2 3 4 5 6 7 8 9<br>R/W STOP condition<br>slave address I0.x I1.x I0.x I1.x<br>SDA S 0 1 0 0 A2 A1 A0 1 A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 1 P<br>START condition acknowledge acknowledge acknowledge acknowledge non acknowledge<br>from slave from master from master from master from master<br>read from port 0<br>read from port 1<br>002aac223<br>**----- End of picture text -----**<br> **Remark:** Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is assumed that the command byte has previously been set to ‘00’ (read Input Port register). **Fig 12. Read Input port register, scenario 1** **==> picture [618 x 220] intentionally omitted <==** **----- Start of picture text -----**<br> data into port 0 DATA 00 DATA 01 DATA 02 DATA 03<br>th(D) tsu(D)<br>data into port 1 DATA 10 DATA 11 DATA 12<br>th(D) tsu(D)<br>INT<br>tv(INT_N) trst(INT_N)<br>SCL 1 2 3 4 5 6 7 8 9<br>R/W STOP condition<br>slave address I0.x I1.x I0.x I1.x<br>SDA S 0 1 0 0 A2 A1 A0 1 A DATA 00 A DATA 10 A DATA 03 A DATA 12 1 P<br>START condition acknowledge acknowledge acknowledge acknowledge non acknowledge<br>from slave from master from master from master from master<br>read from port 0<br>read from port 1<br>002aac224<br>**----- End of picture text -----**<br> **Remark:** Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is assumed that the command byte has previously been set to ‘00’ (read Input Port register). **Fig 13. Read Input port register, scenario 2** **PCA9555** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus I/O port with interrupt** ## **6.5.3 Interrupt output** The open-drain interrupt output is activated when one of the port pins changes state and the pin is configured as an input. The interrupt is deactivated when the input returns to its previous state or the Input Port register is read (see Figure 12). A pin configured as an output cannot cause an interrupt. Since each 8-bit port is read independently, the interrupt caused by Port 0 will not be cleared by a read of Port 1 or the other way around. **Remark:** Changing an I/O from an output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the Input Port register. ## **7. Characteristics of the I[2] C-bus** The I[2] C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. ## **7.1 Bit transfer** One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 14). **==> picture [240 x 87] intentionally omitted <==** **----- Start of picture text -----**<br> SDA<br>SCL<br>data line change<br>stable; of data<br>data valid allowed mba607<br>**----- End of picture text -----**<br> **Fig 14. Bit transfer** ## **7.1.1 START and STOP conditions** Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Figure 15). **==> picture [318 x 76] intentionally omitted <==** **----- Start of picture text -----**<br> SDA<br>SCL<br>S P<br>START condition STOP condition<br>mba608<br>**----- End of picture text -----**<br> **Fig 15. Definition of START and STOP conditions** © NXP Semiconductors N.V. 2017. All rights reserved. PCA9555 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 10 — 8 November 2017** **14 of 34** **PCA9555** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus I/O port with interrupt** ## **7.2 System configuration** A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see Figure 16). **==> picture [432 x 109] intentionally omitted <==** **----- Start of picture text -----**<br> SDA<br>SCL<br>MASTER SLAVE SLAVE MASTER MASTER I [2] C-BUS<br>TRANSMITTER/ RECEIVER TRANSMITTER/ TRANSMITTER TRANSMITTER/ MULTIPLEXER<br>RECEIVER RECEIVER RECEIVER<br>SLAVE<br>002aaa966<br>**----- End of picture text -----**<br> **Fig 16. System configuration** ## **7.3 Acknowledge** The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse; set-up time and hold time must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. **==> picture [297 x 129] intentionally omitted <==** **----- Start of picture text -----**<br> data output<br>by transmitter<br>not acknowledge<br>data output<br>by receiver<br>acknowledge<br>SCL from master<br>1 2 8 9<br>S<br>clock pulse for<br>START acknowledgement<br>condition 002aaa987<br>**----- End of picture text -----**<br> **Fig 17. Acknowledgement on the I[2] C-bus** © NXP Semiconductors N.V. 2017. All rights reserved. PCA9555 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 10 — 8 November 2017** **15 of 34** **PCA9555** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus I/O port with interrupt** ## **8. Application design-in information** **==> picture [438 x 288] intentionally omitted <==** **----- Start of picture text -----**<br> VDD<br>(5 V) SUB-SYSTEM 1<br>10 k Ω 10 k Ω 10 k Ω 2 k Ω (e.g., temp sensor)<br>VDD VDD<br>INT<br>MASTER PCA9555<br>CONTROLLER<br>SCL SCL IO0_0<br>SUB-SYSTEM 2<br>SDA SDA IO0_1 (e.g., counter)<br>IO0_2 RESET<br>INT INT<br>IO0_3<br>A<br>GND<br>IO0_4 ENABLE controlled<br>switch<br>IO0_5 (e.g., CBT device)<br>B<br>IO0_6<br>IO0_7 SUB-SYSTEM 3<br>IO1_0 (e.g., alarm system)<br>IO1_1 10 DIGIT<br>IO1_2 NUMERIC ALARM<br>IO1_3 KEYPAD<br>IO1_4<br>A2 IO1_5 VDD<br>A1 IO1_6<br>A0 IO1_7<br>VSS<br>002aac704<br>**----- End of picture text -----**<br> Device address configured as 0100 000xb for this example. IO0_0, IO0_2, IO0_3 configured as outputs. IO0_1, IO0_4, IO0_5 configured as inputs. IO0_6, IO0_7, and IO1_0 to IO1_7 configured as inputs. **Fig 18. Typical application** © NXP Semiconductors N.V. 2017. All rights reserved. PCA9555 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 10 — 8 November 2017** **16 of 34** **PCA9555** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus I/O port with interrupt** ## **9. Limiting values** ## **Table 13. Limiting values** _In accordance with the Absolute Maximum Rating System (IEC 60134)._ |**Symbol**|**Parameter**|**Conditions**||**Min**|**Max**|**Unit**| |---|---|---|---|---|---|---| |VDD|supply voltage|||0.5|+6.0|V| |VI/O|voltage on an input/output pin|||VSS0.5|6|V| |IO|output current|on an I/O pin||-|50|mA| |II|input current|||-|20|mA| |IDD|supply current|||-|160|mA| |ISS|ground supply current|||-|200|mA| |Ptot|total power dissipation|||-|200|mW| |Tstg|storage temperature|||65|+150|C| |Tamb|ambient temperature|operating||40|+85|C| |Tj(max)|maximum junction<br>temperature|||-|125|C| © NXP Semiconductors N.V. 2017. All rights reserved. PCA9555 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 10 — 8 November 2017** **17 of 34** **PCA9555** **NXP Semiconductors** ## **16-bit I[2] C-bus and SMBus I/O port with interrupt** ## **10. Static characteristics** |**Table 14.**<br>**Static characteristics**| |---| |_VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb =__40__C to +85__C; unless otherwise specified._| |**Table 14.**<br>**Static characteristics**<br>_VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb =__40__C to +85__C; unless otherwise specified._|**Table 14.**<br>**Static characteristics**<br>_VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb =__40__C to +85__C; unless otherwise specified._|**Table 14.**<br>**Static characteristics**<br>_VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb =__40__C to +85__C; unless otherwise specified._|**Table 14.**<br>**Static characteristics**<br>_VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb =__40__C to +85__C; unless otherwise specified._|**Table 14.**<br>**Static characteristics**<br>_VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb =__40__C to +85__C; unless otherwise specified._|**Table 14.**<br>**Static characteristics**<br>_VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb =__40__C to +85__C; unless otherwise specified._|**Table 14.**<br>**Static characteristics**<br>_VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb =__40__C to +85__C; unless otherwise specified._|**Table 14.**<br>**Static characteristics**<br>_VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb =__40__C to +85__C; unless otherwise specified._| |---|---|---|---|---|---|---|---| |**Symbol**|**Parameter**|**Conditions**||**Min**|**Typ**|**Max**|**Unit**| |**Supplies**|||||||| |VDD|supply voltage|||2.3|-|5.5|V| |IDD|supply current|Operating mode; VDD= 5.5 V; no load;<br>fSCL= 100 kHz||-|135|200|A| |Istb|standby current|Standby mode; VDD= 5.5 V; no load;<br>VI= VSS; fSCL= 0 kHz; I/O = inputs||-|1.1|1.5|mA| |||Standby mode; VDD= 5.5 V; no load;<br>VI= VDD; fSCL= 0 kHz; I/O = inputs||-|0.25|1|A| |VPOR|power-on reset voltage[1]|no load; VI= VDDor VSS||-|1.7|2.2|V| |**Input SCL; input/output SDA**|||||||| |VIL|LOW-level input voltage|||0.5|-|+0.3VDD|V| |VIH|HIGH-level input voltage|||0.7VDD|-|5.5|V| |IOL|LOW-level output current|VOL= 0.4 V||3|-|-|mA| |IL|leakage current|VI= VDD= VSS||1|-|+1|A| |Ci|input capacitance|VI= VSS||-|6|10|pF| |**I/Os**|||||||| |VIL|LOW-level input voltage|||0.5|-|+0.3VDD|V| |VIH|HIGH-level input voltage|||0.7VDD|-|5.5|V| |IOL|LOW-level output current|VDD= 2.3 V to 5.5 V; VOL= 0.5 V|[2]|8|(8 to 20)|-|mA| |||VDD= 2.3 V to 5.5 V; VOL= 0.7 V|[2]|10|(10 to 24)|-|mA| |VOH|HIGH-level output voltage|IOH=8 mA; VDD= 2.3 V|[3]|1.8|-|-|V| |||IOH=10 mA; VDD= 2.3 V|[3]|1.7|-|-|V| |||IOH=8 mA; VDD= 3.0 V|[3]|2.6|-|-|V| |||IOH=10 mA; VDD= 3.0 V|[3]|2.5|-|-|V| |||IOH=8 mA; VDD= 4.75 V|[3]|4.1|-|-|V| |||IOH=10 mA; VDD= 4.75 V|[3]|4.0|-|-|V| |ILIH|HIGH-level input leakage<br>current|VDD= 5.5 V; VI= VDD||-|-|1|A| |ILIL|LOW-level input leakage<br>current|VDD= 5.5 V; VI= VSS||-|-|100|A| |Ci|input capacitance|||-|3.7|5|pF| |Co|output capacitance|||-|3.7|5|pF| |**Interrupt INT**|||||||| |IOL|LOW-level output current|VOL= 0.4 V||3|-|-|mA| |**Select inputs A0, A1, A2**|||||||| |VIL|LOW-level input voltage|||0.5|-|+0.3VDD|V| |VIH|HIGH-level input voltage|||0.7VDD|-|5.5|V| |ILI|input leakage current|||1|-|+1|A| [1] VDD must be lowered to 0.2 V for at least 5 s in order to reset part. © NXP Semiconductors N.V. 2017. All rights reserved. PCA9555 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 10 — 8 November 2017** **18 of 34** **PCA9555** **NXP Semiconductors** ## **16-bit I[2] C-bus and SMBus I/O port with interrupt** - [2] Each I/O must be externally limited to a maximum of 25 mA and each octal (IO0_0 to IO0_7 and IO1_0 to IO1_7) must be limited to a maximum current of 100 mA for a device total of 200 mA. - [3] The total current sourced by all I/Os must be limited to 160 mA. **==> picture [496 x 374] intentionally omitted <==** **----- Start of picture text -----**<br> 002aac706 002aac707<br>6.0 4.5<br>V(V)OH VOH<br>(V)<br>5.0 (1)<br>3.5<br>(2)<br>4.0<br>(1) 2.5<br>3.0<br>(2)<br>2.0 1.5<br>2.7 3.6 5.5 2.3 3.0 4.75<br>VDD (V) VDD (V)<br>(1) IOH = 8 mA (1) IOH = 8 mA<br>(2) IOH = 10 mA (2) IOH = 10 mA<br>Fig 19. VOH maximum Fig 20. VOH minimum<br>002aac705<br>1.6<br>IDD<br>(mA) (1)<br>1.2<br>(2)<br>(3)<br>0.8<br>0.4<br>0<br>all 1s one 0 three 0s all 0s<br>number of I/Os<br>**----- End of picture text -----**<br> VDD = 5.5 V; VI/O = 5.5 V; A2, A1, A0 set to logic 0. (1) Tamb = 40 C (2) Tamb = +25 C (3) Tamb = +85 C **Fig 21. IDD versus number of I/Os held LOW** © NXP Semiconductors N.V. 2017. All rights reserved. PCA9555 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 10 — 8 November 2017** **19 of 34** **PCA9555** **NXP Semiconductors** ## **16-bit I[2] C-bus and SMBus I/O port with interrupt** ## **11. Dynamic characteristics** ## **Table 15. Dynamic characteristics** |**Symbol**|**Parameter**|**Conditions**||**Standard-mode**<br>**I2C-bus**|**Standard-mode**<br>**I2C-bus**|**Fast-mode I2C-bus**|**Fast-mode I2C-bus**|**Unit**| |---|---|---|---|---|---|---|---|---| |||||**Min**|**Max**|**Min**|**Max**|| |fSCL|SCL clock frequency|||0|100|0|400|kHz| |tBUF|bus free time between a STOP and<br>START condition|||4.7|-|1.3|-|s| |tHD;STA|hold time (repeated) START condition|||4.0|-|0.6|-|s| |tSU;STA|set-up time for a repeated START<br>condition|||4.7|-|0.6|-|s| |tSU;STO|set-up time for STOP condition|||4.0|-|0.6|-|s| |tVD;ACK|data valid acknowledge time||[1]|0.3|3.45|0.1|0.9|s| |tHD;DAT|data hold time|||0|-|0|-|ns| |tVD;DAT|data valid time||[2]|300|-|50|-|ns| |tSU;DAT|data set-up time|||250|-|100|-|ns| |tLOW|LOW period of the SCL clock|||4.7|-|1.3|-|s| |tHIGH|HIGH period of the SCL clock|||4.0|-|0.6|-|s| |tf|fall time of both SDA and SCL signals|||-|300|20 + 0.1C~~b~~[3]|300|ns| |tr|rise time of both SDA and SCL signals|||-|1000|20 + 0.1C~~b~~[3]|300|ns| |tSP|pulse width of spikes that must be<br>suppressed by the input filter|||-|50|-|50|ns| |**Port timing**||||||||| |tv(Q)|data output valid time|||-|200|-|200|ns| |tsu(D)|data input set-up time|||150|-|150|-|ns| |th(D)|data input hold time|||1|-|1|-|s| |**Interrupt timing**||||||||| |tv(INT_N)|valid time on pin INT|||-|4|-|4|s| |trst(INT_N)|reset time on pin INT|||-|4|-|4|s| [1] tVD;ACK = time for acknowledgement signal from SCL LOW to SDA (out) LOW. [2] tVD;DAT = minimum time for SDA data out to be valid following SCL LOW. [3] Cb = total capacitance of one bus line in pF. © NXP Semiconductors N.V. 2017. All rights reserved. PCA9555 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 10 — 8 November 2017** **20 of 34** **PCA9555** **NXP Semiconductors** ## **16-bit I[2] C-bus and SMBus I/O port with interrupt** **==> picture [480 x 133] intentionally omitted <==** **----- Start of picture text -----**<br> 0.7 × VDD<br>SDA<br>0.3 × VDD<br>tBUF tr tf tHD;STA tSP<br>tLOW<br>0.7 × VDD<br>SCL<br>0.3 × VDD<br>tHD;STA tSU;STA tSU;STO<br>P S tHD;DAT tHIGH tSU;DAT Sr P<br>002aaa986<br>**----- End of picture text -----**<br> **Fig 22. Definition of timing on the I[2] C-bus** ## **12. Test information** **==> picture [348 x 136] intentionally omitted <==** **----- Start of picture text -----**<br> VDD<br>open<br>GND<br>VDD RL<br>500 Ω<br>VI VO<br>PULSE<br>DUT<br>GENERATOR<br>RT CL<br>50 pF<br>002aab284<br>RL = load resistor.<br>CL = load capacitance includes jig and probe capacitance.<br>RT = termination resistance should be equal to the output impedance of Zo of the pulse generators.<br>**----- End of picture text -----**<br> **==> picture [177 x 10] intentionally omitted <==** **----- Start of picture text -----**<br> Fig 23. Test circuitry for switching times<br>**----- End of picture text -----**<br> **==> picture [298 x 84] intentionally omitted <==** **----- Start of picture text -----**<br> RL S1 2VDD<br>from output under test open<br>500 Ω GND<br>CL RL<br>50 pF 500 Ω<br>002aac226<br>Fig 24. Load circuit<br>**----- End of picture text -----**<br> © NXP Semiconductors N.V. 2017. All rights reserved. PCA9555 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 10 — 8 November 2017** **21 of 34** **PCA9555** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus I/O port with interrupt** ## **13. Package outline** **==> picture [285 x 10] intentionally omitted <==** **----- Start of picture text -----**<br> SO24: plastic small outline package; 24 leads; body width 7.5 mm<br>**----- End of picture text -----**<br> **==> picture [43 x 8] intentionally omitted <==** **----- Start of picture text -----**<br> SOT137-1<br>**----- End of picture text -----**<br> **==> picture [478 x 570] intentionally omitted <==** **----- Start of picture text -----**<br> D E A<br>X<br>c<br>y HE v M A<br>Z<br>24 13<br>Q<br>A2 A<br>A1 (A )3<br>pin 1 index<br>θ<br>L p<br>L<br>1 12 detail X<br>e w M<br>b p<br>0 5 10 mm<br>scale<br>DIMENSIONS (inch dimensions are derived from the original mm dimensions)<br>UNIT max.A A1 A2 A3 bp c D [(1)] E [(1)] e HE L Lp Q v w y Z (1) θ<br>0.3 2.45 0.49 0.32 15.6 7.6 10.65 1.1 1.1 0.9<br>mm 2.65 0.1 2.25 0.25 0.36 0.23 15.2 7.4 1.27 10.00 1.4 0.4 1.0 0.25 0.25 0.1 0.4 8o<br>0.012 0.096 0.019 0.013 0.61 0.30 0.419 0.043 0.043 0.035 0o<br>inches 0.1 0.01 0.05 0.055 0.01 0.01 0.004<br>0.004 0.089 0.014 0.009 0.60 0.29 0.394 0.016 0.039 0.016<br>Note<br>1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.<br>OUTLINE REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION IEC JEDEC JEITA PROJECTION<br>99-12-27<br> SOT137-1 075E05 MS-013<br>03-02-19<br>**----- End of picture text -----**<br> ## **Fig 25. Package outline SOT137-1 (SO24)** All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. PCA9555 **Product data sheet** **Rev. 10 — 8 November 2017** **22 of 34** **PCA9555** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus I/O port with interrupt** ## **SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm** **==> picture [43 x 8] intentionally omitted <==** **----- Start of picture text -----**<br> SOT340-1<br>**----- End of picture text -----**<br> **==> picture [478 x 570] intentionally omitted <==** **----- Start of picture text -----**<br> D E A<br>X<br>c<br>y HE v M A<br>Z<br>24 13<br>Q<br>A2 A1 (A )3 A<br>pin 1 index<br>θ<br>L p<br>L<br>1 12 detail X<br>w M<br>e bp<br>0 2.5 5 mm<br>scale<br>DIMENSIONS (mm are the original dimensions)<br>UNIT max.A A1 A2 A3 bp c D [(1)] E [(1)] e HE L Lp Q v w y Z (1) θ<br>mm 2 0.210.05 1.801.65 0.25 0.380.25 0.200.09 8.48.0 5.45.2 0.65 7.97.6 1.25 1.030.63 0.90.7 0.2 0.13 0.1 0.80.4 80oo<br>Note<br>1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.<br>OUTLINE REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION IEC JEDEC JEITA PROJECTION<br>99-12-27<br> SOT340-1 MO-150<br>03-02-19<br>**----- End of picture text -----**<br> ## **Fig 26. Package outline SOT340-1 (SSOP24)** All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. PCA9555 **Product data sheet** **Rev. 10 — 8 November 2017** **23 of 34** **PCA9555** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus I/O port with interrupt** **TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm** **==> picture [43 x 8] intentionally omitted <==** **----- Start of picture text -----**<br> SOT355-1<br>**----- End of picture text -----**<br> **==> picture [478 x 570] intentionally omitted <==** **----- Start of picture text -----**<br> D E A<br>X<br>c<br>y HE v M A<br>Z<br>24 13<br>Q<br>A2 (A )3 A<br>pin 1 index A1<br>θ<br>L p<br>L<br>1 12<br>detail X<br>w M<br>e b p<br>0 2.5 5 mm<br>scale<br>DIMENSIONS (mm are the original dimensions)<br>UNIT max.A A1 A2 A3 bp c D [(1)] E [(2)] e HE L Lp Q v w y Z (1) θ<br>0.15 0.95 0.30 0.2 7.9 4.5 6.6 0.75 0.4 0.5 8o<br>mm 1.1 0.05 0.80 0.25 0.19 0.1 7.7 4.3 0.65 6.2 1 0.50 0.3 0.2 0.13 0.1 0.2 0o<br>Notes<br>1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.<br>2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.<br>OUTLINE REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION IEC JEDEC JEITA PROJECTION<br>99-12-27<br> SOT355-1 MO-153<br>03-02-19<br>**----- End of picture text -----**<br> ## **Fig 27. Package outline SOT355-1 (TSSOP24)** All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. PCA9555 **Product data sheet** **Rev. 10 — 8 November 2017** **24 of 34** **PCA9555** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus I/O port with interrupt** **HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.85 mm** **==> picture [43 x 8] intentionally omitted <==** **----- Start of picture text -----**<br> SOT616-1<br>**----- End of picture text -----**<br> **==> picture [478 x 559] intentionally omitted <==** **----- Start of picture text -----**<br> D B A<br>terminal 1<br>index area<br>A<br>A1<br>E c<br>detail X<br>e1 C<br>1/2 e<br>e b v M C A B y1 C y<br>7 12 w M C<br>L<br>13<br>6<br>e<br>Eh e2<br>1/2 e<br>1<br>18<br>terminal 1<br>index area 24 19<br>Dh X<br>0 2.5 5 mm<br>scale<br>DIMENSIONS (mm are the original dimensions)<br>A [(1)]<br>UNIT max. A1 b c D [(1)] Dh E [(1)] Eh e e1 e2 L v w y y1<br>0.05 0.30 4.1 2.25 4.1 2.25 0.5<br>mm 1 0.2 0.5 2.5 2.5 0.1 0.05 0.05 0.1<br>0.00 0.18 3.9 1.95 3.9 1.95 0.3<br>Note<br>1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.<br>OUTLINE REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION IEC JEDEC JEITA PROJECTION<br>01-08-08<br> SOT616-1 - - - MO-220 - - -<br>02-10-22<br>**----- End of picture text -----**<br> **Fig 28. Package outline SOT616-1 (HVQFN24)** All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. PCA9555 **Product data sheet** **Rev. 10 — 8 November 2017** **25 of 34** **PCA9555** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus I/O port with interrupt** ## **HWQFN24: plastic thermal enhanced very very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.75 mm** **==> picture [482 x 564] intentionally omitted <==** **----- Start of picture text -----**<br> 24 terminals; body 4 x 4 x 0.75 mm SOT994-1<br>D B A<br>terminal 1<br>index area<br>E A<br>A1<br>c<br>detail X<br>e1<br>1/2 e<br>C<br>∅ v M C A B<br>e b<br>∅ w M C y1 C y<br>7 12<br>L<br>13<br>6<br>e<br>Eh e2<br>1/2 e<br>1<br>18<br>terminal 1<br>index area 24 19<br>X<br>Dh<br>0 2.5 5 mm<br>scale<br>DIMENSIONS (mm are the original dimensions)<br>A [(1)]<br>UNIT max A1 b c D [(1)] Dh E [(1)] Eh e e1 e2 L v w y y1<br>0.05 0.30 4.1 2.25 4.1 2.25 0.5<br>mm 0.8 0.2 0.5 2.5 2.5 0.1 0.05 0.05 0.1<br>0.00 0.18 3.9 1.95 3.9 1.95 0.3<br>Note<br>1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.<br>OUTLINE REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION IEC JEDEC JEITA PROJECTION<br>07-02-07<br>SOT994-1 - - - MO-220 - - -<br>07-03-03<br>**----- End of picture text -----**<br> **Fig 29. Package outline SOT994-1 (HWQFN24)** © NXP Semiconductors N.V. 2017. All rights reserved. PCA9555 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 10 — 8 November 2017** **26 of 34** **PCA9555** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus I/O port with interrupt** ## **14. Handling information** All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in _JESD625-A_ or equivalent standards. ## **15. Soldering of SMD packages** This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note _AN10365 “Surface mount reflow soldering description”_ . ## **15.1 Introduction to soldering** Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. ## **15.2 Wave and reflow soldering** Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: - Through-hole components - Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: - Board specifications, including the board finish, solder masks and vias - Package footprints, including solder thieves and orientation - The moisture sensitivity level of the packages - Package placement - Inspection and repair - Lead-free soldering versus SnPb soldering ## **15.3 Wave soldering** Key characteristics in wave soldering are: © NXP Semiconductors N.V. 2017. All rights reserved. PCA9555 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 10 — 8 November 2017** **27 of 34** **PCA9555** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus I/O port with interrupt** - Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave - Solder bath specifications, including temperature and impurities ## **15.4 Reflow soldering** Key characteristics in reflow soldering are: - Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 30) than a SnPb process, thus reducing the process window - Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board - Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 16 and 17 **Table 16. SnPb eutectic process (from J-STD-020C)** |**Package thickness (mm)**|**Package reflow temperature (****C)**|**Package reflow temperature (****C)**| |---|---|---| ||**Volume (mm3)**|| ||**< 350**|**350**| |< 2.5|235|220| |2.5|220|220| ## **Table 17. Lead-free process (from J-STD-020C)** |**Package thickness (mm)**|**Package reflow temperature (****C)**|**Package reflow temperature (****C)**|**Package reflow temperature (****C)**| |---|---|---|---| ||**Volume (mm3)**||| ||**< 350**|**350 to 2000**|**> 2000**| |< 1.6|260|260|260| |1.6 to 2.5|260|250|245| |> 2.5|250|245|245| Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 30. © NXP Semiconductors N.V. 2017. All rights reserved. PCA9555 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 10 — 8 November 2017** **28 of 34** **PCA9555** **NXP Semiconductors** ## **16-bit I[2] C-bus and SMBus I/O port with interrupt** **==> picture [320 x 207] intentionally omitted <==** **----- Start of picture text -----**<br> maximum peak temperature<br>= MSL limit, damage level<br>temperature<br>minimum peak temperature<br>= minimum soldering temperature<br>peak<br> temperature<br>time<br>001aac844<br>MSL: Moisture Sensitivity Level<br>**----- End of picture text -----**<br> **==> picture [264 x 10] intentionally omitted <==** **----- Start of picture text -----**<br> Fig 30. Temperature profiles for large and small components<br>**----- End of picture text -----**<br> For further information on temperature profiles, refer to Application Note _AN10365 “Surface mount reflow soldering description”_ . ## **16. Soldering of through-hole mount packages** ## **16.1 Introduction to soldering through-hole mount packages** This text gives a very brief insight into wave, dip and manual soldering. Wave soldering is the preferred method for mounting of through-hole mount IC packages on a printed-circuit board. ## **16.2 Soldering by dipping or by solder wave** Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. ## **16.3 Manual soldering** Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 C and 400 C, contact may be up to 5 seconds. © NXP Semiconductors N.V. 2017. All rights reserved. PCA9555 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 10 — 8 November 2017** **29 of 34** **PCA9555** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus I/O port with interrupt** ## **16.4 Package related soldering information** **Table 18. Suitability of through-hole mount IC packages for dipping and wave soldering** |**Package**|**Soldering method**|**Soldering method**| |---|---|---| ||**Dipping**|**Wave**| |CPGA, HCPGA|-|suitable| |DBS, DIP, HDIP, RDBS, SDIP, SIL|suitable|suitable[1]| |PMFP[2]|-|not suitable| - [1] For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. - [2] For PMFP packages hot bar soldering or manual soldering is suitable. ## **17. Abbreviations** ## **Table 19. Abbreviations** |**Acronym**|**Description**| |---|---| |CMOS|Complementary Metal Oxide Semiconductor| |GPIO|General Purpose Input/Output| |I2C-bus|Inter-Integrated Circuit bus| |SMBus|System Management Bus| |I/O|Input/Output| |ACPI|Advanced Configuration and Power Interface| |LED|Light Emitting Diode| |ESD|ElectroStatic Discharge| |HBM|Human Body Model| |MM|Machine Model| |CDM|Charged Device Model| |PCB|Printed-Circuit Board| |FET|Field-Effect Transistor| |MSB|Most Significant Bit| |LSB|Least Significant Bit| © NXP Semiconductors N.V. 2017. All rights reserved. PCA9555 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 10 — 8 November 2017** **30 of 34** **PCA9555** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus I/O port with interrupt** ## **18. Revision history** ## **Table 20. Revision history** |**Document ID**|**Release date**|**Release date**|**Data sheet status**|**Change notice**|**Supersedes**| |---|---|---|---|---|---| |PCA9555 v.10|20171108||Product data sheet|201710002I|PCA9555_9| |Modifications:|**•** Table 14“<br>Static characteristics<br>”<br>:Corrected VPORtyp and max limit<br>**•** AddedSection 3.1“<br>Ordering options<br>”<br>**•** Obsolete part PCA9555N (DIP24, SOT101-1) removed||||| |PCA9555 v.9|20170510||Product data sheet|-|PCA9555_8| |Modifications:|**•** Table 13“<br>Limiting values<br>”<br>,added row for Tj(max)||||| |PCA9555_8|20091022||Product data sheet|-|PCA9555_7| |Modifications:|**•** <br>**•** <br>**•** <br>**•** <br>**•**|Table 2“Ordering options”<br>, Topside mark for TSSOP24 package, PCA9555PW, is changed from<br>“PCA9555PW” to “PCA9555”<br> Figure 12“<br>Read Input port register, scenario 1<br>”<br> modified<br> Figure 13“<br>Read Input port register, scenario 2<br>”<br> modified<br> Table 14“<br>Static characteristics<br>”<br>,Table note [1]<br> modified (added phrase “for at least 5s”)<br> updated soldering information|||| |PCA9555_7|20070605||Product data sheet|-|PCA9555_6| |PCA9555_6|20060825||Product data sheet|-|PCA9555_5| |PCA9555_5<br>(9397 750 14125)|20040930||Product data sheet|-|PCA9555_4| |PCA9555_4<br>(9397 750 13271)|20040727||Product data sheet|-|PCA9555_3| |PCA9555_3<br>(9397 750 10164)|20020726||Product data|853-2252 28672 of<br>2002 July 26|PCA9555_2| |PCA9555_2<br>(9397 750 09818)|20020513||Product data|-|PCA9555_1| |PCA9555_1<br>(9397 750 08343)|20010507||Product data|-|-| © NXP Semiconductors N.V. 2017. All rights reserved. PCA9555 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 10 — 8 November 2017** **31 of 34** **PCA9555** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus I/O port with interrupt** ## **19. Legal information** ## **19.1 Data sheet status** |**Document status[1]**<br>**[2]**|**Product statu**~~**s**~~**[3]**|**Definition**| |---|---|---| |Objective [short] data sheet|Development|This document contains data from the objective specification for product development.| |Preliminary [short] data sheet|Qualification|This document contains data from the preliminary specification.| |Product [short] data sheet|Production|This document contains the product specification.| - [1] Please consult the most recently issued document before initiating or completing a design. - [2] The term ‘short data sheet’ is explained in section “Definitions”. - [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. ## **19.2 Definitions** **Draft —** The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. **Short data sheet —** A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. **Product specification —** The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. ## **19.3 Disclaimers** **Limited warranty and liability —** Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the _Terms and conditions of commercial sale_ of NXP Semiconductors. **Right to make changes —** NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. **Suitability for use —** NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. **Applications —** Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. **Limiting values —** Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. **Terms and conditions of commercial sale —** NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. **No offer to sell or license —** Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. © NXP Semiconductors N.V. 2017. All rights reserved. PCA9555 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 10 — 8 November 2017** **32 of 34** **PCA9555** **NXP Semiconductors** ## **16-bit I[2] C-bus and SMBus I/O port with interrupt** **Export control —** This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. **Quick reference data —** The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. **Non-automotive qualified products —** Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. **Translations —** A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. ## **19.4 Trademarks** Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. **I[2] C-bus —** logo is a trademark of NXP Semiconductors N.V. ## **20. Contact information** For more information, please visit: **http://www.nxp.com** For sales office addresses, please send an email to: **salesaddresses@nxp.com** © NXP Semiconductors N.V. 2017. All rights reserved. PCA9555 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 10 — 8 November 2017** **33 of 34** **PCA9555** **NXP Semiconductors** ## **16-bit I[2] C-bus and SMBus I/O port with interrupt** ## **21. Contents** |**1**|**General description . . . . . . . . . . . . . . . . . . . . . . 1**| |---|---| |**2**|**Features and benefits . . . . . . . . . . . . . . . . . . . . 1**| |**3**|**Ordering information. . . . . . . . . . . . . . . . . . . . . 2**| |3.1|Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2| |**4**|**Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3**| |**5**|**Pinning information. . . . . . . . . . . . . . . . . . . . . . 3**| |5.1|Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3| |5.2|Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5| |**6**|**Functional description . . . . . . . . . . . . . . . . . . . 6**| |6.1|Device address. . . . . . . . . . . . . . . . . . . . . . . . . 6| |6.2|Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6| |6.2.1|Command byte . . . . . . . . . . . . . . . . . . . . . . . . . 6| |6.2.2|Registers 0 and 1: Input port registers . . . . . . . 7| |6.2.3|Registers 2 and 3: Output port registers. . . . . . 7| |6.2.4|Registers 4 and 5: Polarity Inversion registers . 7| |6.2.5|Registers 6 and 7: Configuration registers . . . . 8| |6.3|Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 8| |6.4|I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8| |6.5|Bus transactions . . . . . . . . . . . . . . . . . . . . . . . . 9| |6.5.1|Writing to the port registers. . . . . . . . . . . . . . . . 9| |6.5.2|Reading the port registers . . . . . . . . . . . . . . . 11| |6.5.3|Interrupt output . . . . . . . . . . . . . . . . . . . . . . . . 14| |**7**|**Characteristics of the I2C-bus . . . . . . . . . . . . 14**| |7.1|Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 14| |7.1.1|START and STOP conditions . . . . . . . . . . . . . 14| |7.2|System configuration . . . . . . . . . . . . . . . . . . . 15| |7.3|Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 15| |**8**|**Application design-in information . . . . . . . . . 16**| |**9**|**Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 17**| |**10**|**Static characteristics. . . . . . . . . . . . . . . . . . . . 18**| |**11**|**Dynamic characteristics . . . . . . . . . . . . . . . . . 20**| |**12**|**Test information. . . . . . . . . . . . . . . . . . . . . . . . 21**| |**13**|**Package outline . . . . . . . . . . . . . . . . . . . . . . . . 22**| |**14**|**Handling information. . . . . . . . . . . . . . . . . . . . 27**| |**15**|**Soldering of SMD packages . . . . . . . . . . . . . . 27**| |15.1|Introduction to soldering . . . . . . . . . . . . . . . . . 27| |15.2|Wave and reflow soldering . . . . . . . . . . . . . . . 27| |15.3|Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 27| |15.4|Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 28| |**16**|**Soldering of through-hole mount packages . 29**| |16.1|Introduction to soldering through-hole mount| ||packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29| |16.2|Soldering by dipping or by solder wave . . . . . 29| |16.3|Manual soldering . . . . . . . . . . . . . . . . . . . . . . 29| |16.4|Package related soldering information . . . . . . 30| |**17**|**Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 30**| |---|---| |**18**|**Revision history . . . . . . . . . . . . . . . . . . . . . . . 31**| |**19**|**Legal information . . . . . . . . . . . . . . . . . . . . . . 32**| |19.1|Data sheet status . . . . . . . . . . . . . . . . . . . . . . 32| |19.2|Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 32| |19.3|Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 32| |19.4|Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 33| |**20**|**Contact information . . . . . . . . . . . . . . . . . . . . 33**| |**21**|**Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34**| Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. **© NXP Semiconductors N.V. 2017.** **All rights reserved.** For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com **Date of release: 8 November 2017 Document identifier: PCA9555**
Updated at February 9, 2023
NXP Semiconductors is a global leader in secure connectivity solutions, driving innovation across the automotive, industrial, IoT, mobile, and communications infrastructure markets. By developing advanced, purpose-built technologies, NXP enables devices to sense, think, connect, and act intelligently, delivering rigorously tested components that make the connected world safer and more efficient. Within the semiconductor space, NXP is highly regarded for its extensive range of high-performance integrated circuits and discrete devices. The brand's portfolio excels in drivers and interfaces, featuring a comprehensive selection of I/O expanders designed to streamline complex system architectures. For demanding high-frequency and wireless applications, NXP provides industry-leading RF FETs and RF/PIN diodes engineered to deliver exceptional signal integrity, efficiency, and reliability. The NXP product lineup further extends to essential discrete components, including versatile bipolar transistors, JFETs, and small signal diodes optimized for precision switching and amplification. Additionally, the portfolio supports advanced automation and smart applications with precision IC sensors, such as MEMS accelerometers, alongside specialized power management solutions like AC/DC LED driver ICs and single MOSFETs for cutting-edge electronics design.
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