PCA9537DP,118

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## **PCA9537** 

**4-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** 

**Rev. 05 — 7 May 2009** 

**Product data sheet** 

## **1. General description** 

The PCA9537 is a 10-pin CMOS device that provides 4 bits of General Purpose parallel Input/Output (GPIO) expansion with interrupt and reset for I[2] C-bus/SMBus applications and was developed to enhance the NXP Semiconductors family of I[2] C-bus I/O expanders. I/O expanders provide a simple solution when additional I/O is needed for ACPI power switches, sensors, push-buttons, LEDs, fans, etc. 

4-bit Input Port register, 4-bit Output Port register and a 4-bit Polarity Inversion register (active HIGH or active LOW operation). The system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding Input Port or Output Port register. The polarity of the Input Port register can be inverted with the Polarity Inversion register. All registers can be read by the system master. 

The PCA9537 open-drain interrupt output (INT) is activated when any input state differs from its corresponding Input Port register state and is used to indicate to the system master that an input state has changed. The power-on reset sets the registers to their default values and initializes the device state machine. The RESET pin causes the same reset/initialization to occur without de-powering the device. 

The I[2][2] C-bus/SMBus. 

## **2. Features** 

- I 4-bit I[2] C-bus GPIO with interrupt and reset 

- I Operating power supply voltage range of 2.3 V to 5.5 V 

- I 5 V tolerant I/Os 

- I Polarity Inversion register 

- I Active LOW interrupt output 

- I Active LOW reset input 

- I Low standby current 

- I 

- I No glitch on power-up 

- I Internal power-on reset 

- I 4 I/O pins that default to 4 inputs 

- I 0 Hz to 400 kHz clock frequency 

- I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101 

**==> picture [211 x 101] intentionally omitted <==**

**PCA9537** 

**NXP Semiconductors** 

**4-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** 

I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA I Offered in TSSOP10 package 

## **3. Ordering information** 

|**formation**|**formation**|**formation**|**formation**|**formation**|
|---|---|---|---|---|
|**Table 1.**<br>**Ordering information**<br>Tamb=−40°C to +85°C|||||
|**Type number**|**Topside**<br>**mark**|**Package**|||
|||**Name**|**Description**|**Version**|
|PCA9537DP<br>9537||TSSOP10<br>plastic thin shrink small outline package;<br>10 leads; body width 3 mm<br>SOT552-1|||



## **4. Block diagram** 

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PCA9537<br>IO0<br>SCL INPUT<br>IO1<br>SDA FILTER<br>4-bit IO2<br>I [2] C-BUS/SMBus INPUT/ IO3<br>OUTPUT<br>CONTROL<br>PORTS<br>write pulse<br>VDD<br>RESET POWER-ONRESET read pulse VDD<br>VSS LP INT<br>FILTER<br>002aae634<br>**----- End of picture text -----**<br>


**Remark:** All I/Os are set to inputs at reset. 

**Fig 1. Block diagram of PCA9537** 

© NXP B.V. 2009. All rights reserved. 

PCA9537_5 **Product data sheet** 

**Rev. 05 — 7 May 2009** 

**2 of 24** 

**PCA9537** 

**NXP Semiconductors** 

**4-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** 

## **5. Pinning information** 

## **5.1 Pinning** 

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**----- Start of picture text -----**<br>
IO0 1 10 VDD<br>IO1 2 9 SDA<br>IO2 3 PCA9537DP 8 SCL<br>IO3 4 7 INT<br>VSS 5 6 RESET<br>002aae633<br>**----- End of picture text -----**<br>


**Fig 2.** 

## **5.2 Pin description** 

## **Table 2. Pin description** 

|**Symbol**|**Pin**|**Description**|
|---|---|---|
|IO0|1|input/output 0|
|IO1|2|input/output 1|
|IO2|3|input/output 2|
|IO3|4|input/output 3|
|VSS|5|supply ground|
|RESET|6|active LOW reset input|
|INT|7|interrupt output (open-drain)|
|SCL|8|serial clock line|
|SDA|9|serial data line|
|VDD|10|supply voltage|



© NXP B.V. 2009. All rights reserved. 

PCA9537_5 **Product data sheet** 

**Rev. 05 — 7 May 2009** 

**3 of 24** 

**PCA9537** 

**NXP Semiconductors** 

**4-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** 

## **6. Functional description** 

Refer to Figure 1 “Block diagram of PCA9537”. 

## **6.1 Device address** 

**==> picture [260 x 79] intentionally omitted <==**

**----- Start of picture text -----**<br>
slave address<br>1 0 0 1 0 0 1 R/W<br>fixed<br>002aae635<br>Fig 3. PCA9537 address<br>**----- End of picture text -----**<br>


## **6.2 Registers** 

## **6.2.1 Command byte** 

It is used as a pointer to determine which of the registers will be written or read. 

## **Table 3. Command byte** 

|**Command**|**Protocol**|**Function**|
|---|---|---|
|0|read byte|Input Port register|
|1|read/write byte|Output Port register|
|2|read/write byte|Polarity Inversion register|
|3|read/write byte|Confguration register|



## **6.2.2 Register 0 - Input Port register** 

of whether the pin is defined as an input or an output by Register 3. Writes to this register have no effect. 

The default value ‘X’ is determined by the externally applied logic level. 

**Table 4. Register 0 - Input Port register bit description** Legend: * default value. 

|**Bit**|**Symbol**|**Access**|**Value**|**Description**|
|---|---|---|---|---|
|7|I7|read only|1*|not used|
|6|I6|read only|1*||
|5|I5|read only|1*||
|4|I4|read only|1*||
|3|I3|read only|X*|value ‘X’ is determined by externally applied logic|
|2|I2|read only|X*|level|
|1|I1|read only|X*||
|0|I0|read only|X*||



© NXP B.V. 2009. All rights reserved. 

PCA9537_5 

**Product data sheet** 

**Rev. 05 — 7 May 2009** 

**4 of 24** 

**PCA9537** 

**NXP Semiconductors** 

**4-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** 

## **6.2.3 Register 1 - Output Port register** 

Bit values in this register have no effect on pins defined as inputs. Reads from this register return the value that is in the flip-flop controlling the output selection, **not** the actual pin value. 

|<br>return t<br>value.|<br>he value that is in the|<br>he value that is in the|<br>fip-fop controlling the output selection,**not**the actual pin|<br>fip-fop controlling the output selection,**not**the actual pin|
|---|---|---|---|---|
|**Table 5.**|**Register 1 - Output**||**Port register bit description**||
|Legend:|* default value.||||
|**Bit**|**Symbol**|**Access**|**Value**|**Description**|
|7|O7|R|1*|not used|
|6|O6|R|1*||
|5|O5|R|1*||
|4|O4|R|1*||
|3|O3|R|1*|refects outgoing logic levels of pins defned as outputs|
|2|O2|R|1*|by Register 3|
|1|O1|R|1*||
|0|O0|R|1*||



## **6.2.4 Register 2 - Polarity Inversion register** 

This register allows the user to invert the polarity of the Input Port register data. If a bit in this register is set (written with 1), the corresponding Input Port data is inverted. If a bit in this register is cleared (written with a 0), the Input Port data polarity is retained. 

**Table 6. Register 2 - Polarity Inversion register bit description** Legend: * default value. 

|**Bit**|**Symbol**|**Access**|**Value**|**Description**|
|---|---|---|---|---|
|7|N7|R/W|0*|not used|
|6|N6|R/W|0*||
|5|N5|R/W|0*||
|4|N4|R/W|0*||
|3|N3|R/W|0*|inverts polarity of Input Port register data|
|2|N2|R/W|0*|0 = Input Port register data retained (default value)|
|1|N1|R/W|0*|1 = Input Port register data inverted|
|0|N0|R/W|0*||



© NXP B.V. 2009. All rights reserved. 

PCA9537_5 **Product data sheet** 

**Rev. 05 — 7 May 2009** 

**5 of 24** 

**PCA9537** 

**NXP Semiconductors** 

**4-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** 

## **6.2.5** 

corresponding port pin is enabled as an input with high-impedance output driver. If a bit in this register is cleared, the corresponding port pin is enabled as an output. At reset, the I/Os are configured as inputs. 

**Table 7.** Legend: * default value. 

|**Bit**|**Symbol**|**Access**|**Value**|**Description**|
|---|---|---|---|---|
|7|C7|R/W|1*|not used|
|6|C6|R/W|1*||
|5|C5|R/W|1*||
|4|C4|R/W|1*||
|3|C3|R/W|1*|confgures the directions of the I/O pins|
|2|C2|R/W|1*|0 = corresponding port pin enabled as an output<br>|
|1|C1|R/W|1*|1 = corresponding port pin confgured as an input|
|0|C0|R/W|1*|(default value)|



## **6.3 Power-on reset** 

When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9537 in a reset condition until VDD has reached VPOR. At that point, the reset condition is released and the PCA9537 registers and state machine will initialize to their default states. Thereafter, VDD must be lowered below 0.2 V to reset the device. 

For a power reset cycle, VDD must be lowered below 0.2 V and then restored to the operating voltage. 

## **6.4 RESET input** 

A reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst). The PCA9537 registers and SMBus/I[2] C-bus state machine will be held in their default state until the RESET input is once again HIGH. This input requires a pull-up resistor to VDD if no active connection is used. 

## **6.5 Interrupt output** 

The open-drain interrupt output (INT) is activated when one of the port pins changes state and the pin is configured as an input. The interrupt is de-activated when the input returns to its previous state or the Input Port register is read. 

Note that changing an I/O from an output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the Input Port register. 

© NXP B.V. 2009. All rights reserved. 

PCA9537_5 

**Product data sheet** 

**Rev. 05 — 7 May 2009** 

**6 of 24** 

**PCA9537** 

**NXP Semiconductors** 

**4-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** 

## **6.6 I/O port** 

high-impedance input. The input voltage may be raised above VDD to a maximum of 5.5 V. 

state of the Output Port register. Care should be exercised if an external voltage is applied to an I/O configured as an output because of the low-impedance paths that exist between the pin and either VDD or VSS. 

**==> picture [370 x 290] intentionally omitted <==**

**----- Start of picture text -----**<br>
data from output port<br>shift register register data<br>configuration<br>register VDD<br>data from D Q Q1<br>shift register<br>FF<br>write<br>D Q<br>configuration CK Q<br>pulse FF<br>I/O pin<br>write pulse CK Q2<br>output port  input port  VSS<br>register register<br>D Q<br>input port<br>FF register data<br>read pulse CK<br>to INT<br>polarity inversion<br>register<br>data from<br>D Q polarity<br>shift register inversion<br>FF register data<br>write polarity<br>CK<br>pulse<br>002aad723<br>Remark:  At power-on reset, all registers return to default values.<br>**----- End of picture text -----**<br>


**Fig 4.** 

© NXP B.V. 2009. All rights reserved. 

PCA9537_5 **Product data sheet** 

**Rev. 05 — 7 May 2009** 

**7 of 24** 

**PCA9537** 

**NXP Semiconductors** 

**4-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** 

## **6.7 Bus transactions** 

Data is transmitted to the PCA9537 registers using the write mode as shown in Figure 5 and Figure 6. Data is read from the PCA9537 registers using the read mode as shown in Figure 7 and Figure 8. These devices do not implement an auto-increment function so once a command byte has been sent, the register which was addressed will continue to be accessed by reads until a new command byte has been sent. 

**==> picture [497 x 354] intentionally omitted <==**

**----- Start of picture text -----**<br>
SCL 1 2 3 4 5 6 7 8 9<br>STOP<br>condition<br>slave address command byte data to port<br>SDA S 1 0 0 1 0 0 1 0 A 0 0 0 0 0 0 0 1 A DATA 1 A P<br>START condition R/W acknowledge acknowledge acknowledge<br>from slave from slave from slave<br>write to port<br>tv(Q)<br>data out from port DATA 1 VALID<br>002aae636<br>Expanded diagram is shown in Figure 16.<br>Fig 5. Write to output port register<br>SCL 1 2 3 4 5 6 7 8 9<br>STOP<br>condition<br>slave address command byte data to register<br>SDA S 1 0 0 1 0 0 1 0 A 0 0 0 0 0 0 1 1/0 A DATA 1 A P<br>START condition R/W acknowledge acknowledge acknowledge<br>from slave from slave from slave<br>data to register<br>002aae637<br>Fig 6. Write to configuration or polarity inversion registers<br>**----- End of picture text -----**<br>


© NXP B.V. 2009. All rights reserved. 

PCA9537_5 **Product data sheet** 

**Rev. 05 — 7 May 2009** 

**8 of 24** 

**PCA9537** 

**NXP Semiconductors** 

**4-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** 

**==> picture [497 x 460] intentionally omitted <==**

**----- Start of picture text -----**<br>
slave address<br>SDA S 1 0 0 1 0 0 1 0 A COMMAND BYTE A (cont.)<br>START condition R/W acknowledge<br>acknowledge from slave<br>from slave<br>slave address data from register data from register<br>(cont.) S 1 0 0 1 0 0 1 1 A DATA (first byte) A DATA (last byte) NA P<br>(repeated) R/W acknowledge no acknowledge STOP<br>START condition acknowledge from master from master condition<br>from slave<br>at this moment master-transmitter becomes master-receiver<br>and slave-receiver becomes slave-transmitter<br>002aae638<br>Fig 7. Read from register<br>SCL 1 2 3 4 5 6 7 8 9<br>no acknowledge<br>from master<br>slave address data from port data from port<br>SDA S 1 0 0 1 0 0 1 1 A DATA 1 A DATA 4 1 P<br>START condition R/W acknowledge acknowledge STOP<br>from slave from master condition<br>read from<br>port<br>data into<br>DATA 1 DATA 2 DATA 3 DATA 4<br>port<br>th(D) tsu(D)<br>INT<br>tv(INT) trst(INT)<br>002aae639<br>This figure assumes the command byte has previously been programmed with 00h.<br>Transfer of data can be stopped at any moment by a STOP condition.<br>Expanded diagram is shown in Figure 15.<br>Fig 8. Read input port register<br>**----- End of picture text -----**<br>


© NXP B.V. 2009. All rights reserved. 

PCA9537_5 

**Product data sheet** 

**Rev. 05 — 7 May 2009** 

**9 of 24** 

**PCA9537** 

**NXP Semiconductors** 

**4-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** 

## **7. Application design-in information** 

**==> picture [462 x 230] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDD<br>(5 V) SUB-SYSTEM 1<br>10 kΩ 10 kΩ 10 kΩ 10 kΩ 2 kΩ 100 kΩ (e.g., temp sensor)<br>VDD VDD<br>MASTER INT<br>PCA9537<br>CONTROLLER<br>SCL SCL IO0<br>SUB-SYSTEM 2<br>SDA SDA IO1 (e.g., counter)<br>INT INT<br>IO2 RESET<br>RESET RESET<br>IO3<br>A<br>VSS VSS enable controlled<br>switch<br>(e.g., CBT device)<br>B<br>002aae640<br>Device address is 1001 001x for this example.<br>IO0, IO2, IO3 configured as outputs.<br>IO1 configured as input.<br>Fig 9. Typical application<br>**----- End of picture text -----**<br>


## **7.1 Minimizing IDD when the I/Os are used to control LEDs** 

When the I/Os are used to control LEDs, they are normally connected to VDD through a resistor as shown in Figure 9. Since the LED acts as a diode, when the LED is off the I/O VI is about 1.2 V less than VDD. The supply current, IDD, increases as VI becomes lower than VDD. 

Designs needing to minimize current consumption, such as battery power applications, should consider maintaining the I/O pins greater than or equal to VDD when the LED is off. Figure 10 shows a high value resistor in parallel with the LED. Figure 11 shows VDD less than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O VI at or above VDD and prevents additional supply current consumption when the LED is off. 

**==> picture [397 x 169] intentionally omitted <==**

**----- Start of picture text -----**<br>
3.3 V 5 V<br>VDD<br>VDD LED 100 kΩ VDD LED<br>IOn IOn<br>002aac660 002aac661<br>Fig 10. High value resistor in parallel with Fig 11. Device supplied by a lower voltage<br>the LED<br>**----- End of picture text -----**<br>


© NXP B.V. 2009. All rights reserved. 

PCA9537_5 

**Product data sheet** 

**Rev. 05 — 7 May 2009** 

**10 of 24** 

**PCA9537** 

**NXP Semiconductors** 

**4-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** 

## **8. Limiting values** 

## **Table 8. Limiting values** 

In accordance with the Absolute Maximum Rating System (IEC 60134). 

|**Symbol**|**Parameter**|**Conditions**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|---|
|VDD|supply voltage||−0.5|+6.0|V|
|II|input current||-|±20|mA|
|VI/O|voltage on an input/output pin||VSS−0.5|5.5|V|
|IO(IOn)|output current on pin IOn||-|±50|mA|
|IDD|supply current||-|85|mA|
|ISS|ground supply current||-|100|mA|
|Ptot|total power dissipation||-|200|mW|
|Tstg|storage temperature||−65|+150|°C|
|Tamb|ambient temperature|operating|−40|+85|°C|
|Tj(max)|maximum junction temperature||-|+125|°C|



## **9. Static characteristics** 

**Table 9. Static characteristics** VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified. 

|**Symbol**|**Parameter**|**Conditions**||**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|---|
|**Supplies**||||||||
|VDD|supply voltage|||2.3|-|5.5|V|
|IDD|supply current|operating mode; VDD= 5.5 V;||-|104|175|µA|
|||no load; fSCL= 100 kHz||||||
|IstbL|LOW-level standby current|Standby mode; VDD= 5.5 V;||-|0.25|1|µA|
|||no load; VI= VSS;||||||
|||fSCL= 0 kHz; I/O = inputs||||||
|IstbH|HIGH-level standby current|Standby mode; VDD= 5.5 V;||-|0.25|1|µA|
|||no load; VI= VDD;||||||
|||fSCL= 0 kHz; I/O = inputs||||||
|VPOR|power-on reset voltage|no load; VI= VDDor VSS|[1]|-|1.5|1.65|V|
|**Input SCL;**|**input/output SDA**|||||||
|VIL|LOW-level input voltage|||−0.5|-|+0.3VDD|V|
|VIH|HIGH-level input voltage|||0.7VDD|-|5.5|V|
|IOL|LOW-level output current|VOL= 0.4 V||3|7|-|mA|
|IL|leakage current|VI= VDD= VSS||−1|-|+1|µA|
|Ci|input capacitance|VI= VSS||-|5|10|pF|



© NXP B.V. 2009. All rights reserved. 

PCA9537_5 **Product data sheet** 

**Rev. 05 — 7 May 2009** 

**11 of 24** 

**PCA9537** 

**NXP Semiconductors** 

**4-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** 

**Table 9. Static characteristics** …continued VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified. 

|**Symbol**<br>**Parameter**|**Symbol**<br>**Parameter**|**Conditions**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**|
|---|---|---|
|**I/Os**|||
|VIL<br>LOW-level input voltage||−0.5<br>-<br>+0.8<br>V|
|VIH<br>HIGH-level input voltage||2.0<br>-<br>5.5<br>V|
|IOL<br>LOW-level output current||VOL= 0.5 V|
|||VDD= 2.3 V<br>[2] 8<br>10<br>-<br>mA|
|||VDD= 3.0 V<br>[2] 8<br>14<br>-<br>mA|
|||VDD= 4.5 V<br>[2] 8<br>17<br>-<br>mA|
|||VOL= 0.7 V|
|||VDD= 2.3 V<br>[2] 10<br>13<br>-<br>mA|
|||VDD= 3.0 V<br>[2] 10<br>19<br>-<br>mA|
|||VDD= 4.5 V<br>[2] 10<br>24<br>-<br>mA|
|VOH<br>HIGH-level output voltage||IOH=−8 mA|
|||VDD= 2.3 V<br>[3] 1.8<br>-<br>-<br>V|
|||VDD= 3.0 V<br>[3] 2.6<br>-<br>-<br>V|
|||VDD= 4.5 V<br>[3] 4.1<br>-<br>-<br>V|
|||IOH=−10 mA|
|||VDD= 2.3 V<br>[3] 1.7<br>-<br>-<br>V|
|||VDD= 3.0 V<br>[3] 2.5<br>-<br>-<br>V|
|||VDD= 4.5 V<br>[3] 4.0<br>-<br>-<br>V|
|IL<br>leakage current||VI= VDD= VSS<br>−1<br>-<br>+1<br>µA|
|Ci<br>input capacitance||-<br>5<br>10<br>pF|
|**Interrupt**<br>**INT**|||
|IOL<br>LOW-level output current||VOL= 0.4 V<br>3<br>13<br>-<br>mA|
|IOH<br>HIGH-level output current||VOL= 0.4 V<br>−1<br>-<br>+1<br>µA|
|**Select input**|**RESET**||
|VIL<br>LOW-level input voltage||−0.5<br>-<br>+0.8<br>V|
|VIH<br>HIGH-level input voltage||2.0<br>-<br>5.5<br>V|
|IL<br>leakage current||VI= VDD= VSS<br>−1<br>-<br>+1<br>µA|



[1] VDD must be lowered to 0.2 V in order to reset part. 

[2] Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 100 mA. 

[3] The total current sourced by all I/Os must be limited to 85 mA. 

© NXP B.V. 2009. All rights reserved. 

PCA9537_5 

**Product data sheet** 

**Rev. 05 — 7 May 2009** 

**12 of 24** 

**PCA9537** 

**NXP Semiconductors** 

**4-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** 

## **10. Dynamic characteristics** 

## **Table 10. Dynamic characteristics** 

|**Symbol**<br>**Parameter**<br>**Conditions**|**Standard-mode**<br>**I2C-bus**|**Standard-mode**<br>**I2C-bus**|**Fast-mode I2C-bus**|**Fast-mode I2C-bus**|**Unit**|
|---|---|---|---|---|---|
||**Min**|**Max**|**Min**|**Max**||
|fSCL<br>SCL clock frequency|0<br>100<br>0<br>400<br>kHz|||||
|tBUF<br>bus free time between a STOP and<br>START condition|4.7<br>-<br>1.3<br>-<br>µs|||||
|tHD;STA<br>hold time (repeated) START condition|4.0<br>-<br>0.6<br>-<br>µs|||||
|tSU;STA<br>set-up time for a repeated START<br>condition|4.7<br>-<br>0.6<br>-<br>µs|||||
|tSU;STO<br>set-up time for STOP condition|4.0<br>-<br>0.6<br>-<br>µs|||||
|tHD;DAT<br>data hold time|0<br>-<br>0<br>-<br>ns|||||
|tVD;ACK<br>data valid acknowledge time<br>[1]|0.3<br>3.45<br>0.1<br>0.9<br>µs|||||
|tVD;DAT<br>data valid time<br>[2]|300<br>-<br>50<br>-<br>ns|||||
|tSU;DAT<br>data set-up time|250<br>-<br>100<br>-<br>ns|||||
|tLOW<br>LOW period of the SCL clock|4.7<br>-<br>1.3<br>-<br>µs|||||
|tHIGH<br>HIGH period of the SCL clock|4.0<br>-<br>0.6<br>-<br>µs|||||
|tr<br>rise time of both SDA and SCL signals|-<br>1000<br>20 + 0.1C~~b~~<br>[3]<br>300<br>ns|||||
|tf<br>fall time of both SDA and SCL signals|-<br>300<br>20 + 0.1C~~b~~<br>[3]<br>300<br>ns|||||
|tSP<br>pulse width of spikes that must be<br>suppressed by the input flter|-<br>50<br>-<br>50<br>ns|||||
|**Port timing**||||||
|tv(Q)<br>data output valid time|-<br>200<br>-<br>200<br>ns|||||
|tsu(D)<br>data input set-up time|100<br>-<br>100<br>-<br>ns|||||
|th(D)<br>data input hold time|1<br>-<br>1<br>-<br>µs|||||
|**Interrupt timing**||||||
|tv(INT)<br>valid time on pin<br>INT|-<br>4<br>-<br>4<br>µs|||||
|trst(INT)<br>reset time on pin<br>INT|-<br>4<br>-<br>4<br>µs|||||
|**RESET**||||||
|tw(rst)<br>reset pulse width|4<br>-<br>4<br>-<br>ns|||||
|trec(rst)<br>reset recovery time|0<br>-<br>0<br>-<br>ns|||||
|trst<br>reset time|400<br>-<br>400<br>-<br>ns|||||



[1] tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW. 

[2] tVD;DAT = minimum time for the SDA data out to be valid following SCL LOW. 

[3] Cb = total capacitance of one bus line in pF. 

© NXP B.V. 2009. All rights reserved. 

PCA9537_5 

**Product data sheet** 

**Rev. 05 — 7 May 2009** 

**13 of 24** 

**PCA9537** 

**NXP Semiconductors** 

**4-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** 

**==> picture [497 x 630] intentionally omitted <==**

**----- Start of picture text -----**<br>
SDA<br>tBUF tr tf tHD;STA tSP<br>tLOW<br>SCL<br>tHD;STA tSU;STA tSU;STO<br>P S tHD;DAT tHIGH tSU;DAT Sr P<br>002aaa986<br>Fig 12. Definition of timing<br>START bit 7 STOP<br>protocol condition MSB bit 6 bit 1 bit 0 acknowledge condition<br>(A6) (D1) (D0) (A)<br>(S) (A7) (P)<br>tSU;STA tLOW tHIGH<br>1 / fSCL<br>SCL<br>tBUF tf<br>tr<br>SDA<br>tHD;STA tSU;DAT tHD;DAT tVD;DAT tVD;ACK tSU;STO<br>002aab285<br>Rise and fall times refer to VIL and VIH.<br>Fig 13. I [2] C-bus timing diagram<br>START ACK or read cycle<br>SCL<br>SDA<br>30 %<br>trst<br>RESET 50 % 50 % 50 %<br>trec(rst) tw(rst)<br>trst<br>after reset,<br>IOn 50 %<br>I/Os reconfigured<br>as inputs<br>002aad732<br>Fig 14. Definition of RESET timing<br>**----- End of picture text -----**<br>


**==> picture [28 x 5] intentionally omitted <==**

**----- Start of picture text -----**<br>
PCA9537_5<br>**----- End of picture text -----**<br>


© NXP B.V. 2009. All rights reserved. **14 of 24** 

**Product data sheet** 

**Rev. 05 — 7 May 2009** 

**PCA9537** 

**NXP Semiconductors** 

**4-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** 

**==> picture [228 x 163] intentionally omitted <==**

**----- Start of picture text -----**<br>
70 %<br>SCL 2 1 0 A P<br>30 %<br>SDA<br>tsu(D) th(D)<br>input 50 %<br>tv(INT) trst(INT)<br>INT<br>002aae641<br>**----- End of picture text -----**<br>


**Fig 15. Expanded view of read input port register** 

**==> picture [232 x 123] intentionally omitted <==**

**----- Start of picture text -----**<br>
70 %<br>SCL 2 1 0 A P<br>SDA<br>tv(Q)<br>output 50 %<br>002aad735<br>**----- End of picture text -----**<br>


**Fig 16. Expanded view of write to output port register** 

© NXP B.V. 2009. All rights reserved. 

PCA9537_5 **Product data sheet** 

**Rev. 05 — 7 May 2009** 

**15 of 24** 

**PCA9537** 

**NXP Semiconductors** 

**4-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** 

## **11. Test information** 

**==> picture [263 x 110] intentionally omitted <==**

**----- Start of picture text -----**<br>
6.0 V<br>open<br>VDD RL VSS<br>500 Ω<br>VI VO<br>PULSE<br>DUT<br>GENERATOR<br>RT CL<br>50 pF<br>002aab393<br>RL = load resistor.<br>**----- End of picture text -----**<br>


CL = load capacitance includes jig and probe capacitance. 

RT = termination resistance should be equal to the output impedance Zo of the pulse generators. 

**Fig 17. Test circuitry for switching times** 

**==> picture [298 x 84] intentionally omitted <==**

**----- Start of picture text -----**<br>
RL S1 2VDD<br>from output under test open<br>500 Ω GND<br>CL RL<br>50 pF 500 Ω<br>002aac226<br>Fig 18. Test circuit<br>**----- End of picture text -----**<br>


## **Table 11. Test data** 

|**Test**|**Load**|**Load**|**Switch**|
|---|---|---|---|
||**RL**|**CL**||
|tv(Q)|500Ω<br>50 pF<br>2×VDD|||



© NXP B.V. 2009. All rights reserved. 

PCA9537_5 **Product data sheet** 

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**16 of 24** 

**PCA9537** 

**NXP Semiconductors** 

**4-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** 

## **12. Package outline** 

**==> picture [345 x 10] intentionally omitted <==**

**----- Start of picture text -----**<br>
TSSOP10: plastic thin shrink small outline package; 10 leads; body width 3 mm<br>**----- End of picture text -----**<br>


**==> picture [43 x 8] intentionally omitted <==**

**----- Start of picture text -----**<br>
SOT552-1<br>**----- End of picture text -----**<br>


**==> picture [478 x 569] intentionally omitted <==**

**----- Start of picture text -----**<br>
D E A<br>X<br>c<br>y HE v M A<br>Z<br>10 6<br>A2 (A3) A<br>A1<br>pin 1 index<br>θ<br>Lp<br>L<br>1 5<br>detail X<br>e bp w M<br>0 2.5 5 mm<br>scale<br>DIMENSIONS (mm are the original dimensions)<br>A<br>UNIT max. A1 A2 A3 bp c D [(1)] E [(2)] e HE L Lp v w y Z [(1)] θ<br>mm 1.1 0.150.05 0.950.80 0.25 0.300.15 0.230.15 3.12.9 3.12.9 0.5 5.04.8 0.95 0.70.4 0.1 0.1 0.1 0.670.34 60°°<br>Notes<br>1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.<br>2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.<br>OUTLINE  REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION  IEC  JEDEC  JEITA PROJECTION<br>99-07-29<br> SOT552-1<br>03-02-18<br>**----- End of picture text -----**<br>


**Fig 19. Package outline SOT552-1 (TSSOP10)** PCA9537_5 

© NXP B.V. 2009. All rights reserved. 

**Product data sheet** 

**Rev. 05 — 7 May 2009** 

**17 of 24** 

**PCA9537** 

**NXP Semiconductors** 

**4-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** 

## **13. Handling information** 

All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards. 

## **14. Soldering of SMD packages** 

This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 

## **14.1 Introduction to soldering** 

Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 

## **14.2** 

Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: 

- Through-hole components 

- Leaded or leadless SMDs, which are glued to the surface of the printed circuit board 

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. 

component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. 

- 

- Package footprints, including solder thieves and orientation 

- The moisture sensitivity level of the packages 

- Package placement 

- Inspection and repair 

- Lead-free soldering versus SnPb soldering 

## **14.3 Wave soldering** 

Key characteristics in wave soldering are: 

© NXP B.V. 2009. All rights reserved. 

PCA9537_5 

**Product data sheet** 

**Rev. 05 — 7 May 2009** 

**18 of 24** 

**PCA9537** 

**NXP Semiconductors** 

**4-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** 

- transport, the solder wave parameters, and the time during which components are exposed to the wave 

- 

## **14.4** 

- higher minimum peak temperatures (see Figure 20) than a SnPb process, thus reducing the process window 

- Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board 

- heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 12 and 13 

## **Table 12. SnPb eutectic process (from J-STD-020C)** 

|**Package thickness (mm)**|**Package refow temperature (**°**C)**|**Package refow temperature (**°**C)**|
|---|---|---|
||**Volume (mm3)**||
||**< 350**|≥**350**|
|< 2.5|235<br>220||
|≥2.5|220<br>220||



## **Table 13. Lead-free process (from J-STD-020C)** 

|**Package thickness (mm)**|**Package refow temperature (**°**C)**|**Package refow temperature (**°**C)**|**Package refow temperature (**°**C)**|
|---|---|---|---|
||**Volume (mm3)**|||
||**< 350**|**350 to 2000**|**> 2000**|
|< 1.6|260<br>260<br>260|||
|1.6 to 2.5|260<br>250<br>245|||
|> 2.5|250<br>245<br>245|||



Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. 

soldering, see Figure 20. 

© NXP B.V. 2009. All rights reserved. 

PCA9537_5 

**Product data sheet** 

**Rev. 05 — 7 May 2009** 

**19 of 24** 

**PCA9537** 

**NXP Semiconductors** 

**4-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** 

**==> picture [352 x 225] intentionally omitted <==**

**----- Start of picture text -----**<br>
maximum peak temperature<br>= MSL limit, damage level<br>temperature<br>minimum peak temperature<br>= minimum soldering temperature<br>peak<br> temperature<br>time<br>001aac844<br>MSL: Moisture Sensitivity Level<br>Fig 20. Temperature profiles for large and small components<br>**----- End of picture text -----**<br>


“Surface mount reflow soldering description”. 

## **15. Abbreviations** 

**Table 14. Abbreviations** 

|**Acronym**|**Description**|
|---|---|
|ACPI|Advanced Confguration and Power Interface|
|CBT|Cross-Bar Technology|
|CDM|Charged-Device Model|
|CMOS|Complementary Metal-Oxide Semiconductor|
|DUT|Device Under Test|
|ESD|ElectroStatic Discharge|
|FET|Field-Effect Transistor|
|FF|Flip-Flop|
|GPIO|General Purpose Input/Output|
|HBM|Human Body Model|
|I2C-bus|Inter-Integrated Circuit bus|
|I/O|Input/Output|
|LED|Light Emitting Diode|
|LP|Low-Pass|
|MM|Machine Model|
|POR|Power-On Reset|
|SMBus|System Management Bus|



© NXP B.V. 2009. All rights reserved. 

PCA9537_5 **Product data sheet** 

**Rev. 05 — 7 May 2009** 

**20 of 24** 

**PCA9537** 

**NXP Semiconductors** 

**4-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** 

## **16. Revision history** 

## **Table 15. Revision history** 

|**Document ID**|**Release date**<br>**Data sheet status**<br>**Change notice**|**Release date**<br>**Data sheet status**<br>**Change notice**|**Supersedes**|||
|---|---|---|---|---|---|
|PCA9537_5|20090507<br>Product data sheet<br>-||PCA9537_4|||
|Modifcations:|**•**|The format of this data sheet has been redesigned to comply with|the new identity|guidelines of||
|||NXP Semiconductors.||||
||**•**|Legal texts have been adapted to the new company name where appropriate.||||
||**•**|Pin names changed from “I/O0, I/O1, I/O2, I/O3” to “IO0, IO1, IO2, IO3”, respectively||||
||**•**|Section6.4 “RESET input”, 1st sentence: changed symbol from “tW” to “tw(rst)”||||
||**•**|Figure 5“Wr<br>ite to output por<br>tregister”: changed symbol from “tpv”|to “tv(Q)”|||
||**•**|Figure 8“Readinput por<br>tregister”:||||
|||**–**<br>changed symbol from “tph” to “th(D)”||||
|||**–**<br>changed symbol from “tps” to “tsu(D)”||||
|||**–**<br>changed symbol from “tiv” to “tv(INT)”||||
|||**–**<br>changed symbol from “tir” to “trst(INT)”||||
||**•**|T<br>ab<br>le 8“Limitingv<br>alues”:||||
|||**–**<br>parameter description for symbol VI/Ochanged from “DC voltage on an I/O” to “voltage on an||||
|||input/output pin”||||
|||**–**<br>parameter description for symbol ISSchanged from “supply current” to “ground||supply current”||
|||**–**<br>symbol/parameter changed from “II/O, DC output current on an|I/O” to “IO(IOn), output current|||
|||on pin IOn”||||
||**•**|T<br>ab<br>le 9“Static char<br>acter<br>istics”,sub-section “Supplies”:||||
|||**–**<br>symbol/parameter changed from “Istbl, Standby current” to “IstbL, LOW-level standby current”||||
|||**–**<br>symbol/parameter changed from “Istbh, Standby current” to “IstbH, HIGH-level standby current”||||
||**•**|T<br>ab<br>le10“Dynamic char<br>acter<br>istics”,sub-section “Port timing”:||||
|||**–**<br>symbol/parameter changed from “tPV, Output data valid” to “tv(Q), data output valid time”||||
|||**–**<br>symbol/parameter changed from “tPS, Input data setup time” to|“tsu(D), data input set-up time”|||
|||**–**<br>symbol/parameter changed from “tPH, Input data hold time” to “th(D), data input hold time”||||
||**•**|T<br>ab<br>le10“Dynamic char<br>acter<br>istics”,sub-section “Interrupt timing”:||||
|||||||
|||**–**<br>symbol/parameter changed from “tIV, Interrupt valid” to “tv(INT), valid time on pin||INT”||
|||**–**<br>symbol/parameter changed from “tIR, Interrupt reset” to “trst(INT), reset time on pin|||INT”|
||**•**|T<br>ab<br>le10“Dynamic char<br>acter<br>istics”,sub-section “<br>RESET”:||||
|||**–**<br>symbol changed from “tW” to “tw(rst)”||||
|||**–**<br>symbol changed from “tREC” to “trec(rst)”||||
|||**–**<br>symbol/parameter changed from “tRESET, Time to reset” to “trst,|reset time”|||
||**•**|Figure14 “Def<br>nitionof RESETtiming”:||||
|||**–**<br>symbol changed from “tW” to “tw(rst)”||||
|||**–**<br>symbol changed from “tREC” to “trec(rst)”||||
|||**–**<br>symbol changed from “tRESET” to “trst”||||
||**•**|Figure15“Expandedvie<br>wof readinput por<br>tregister”:||||
|||**–**<br>changed symbol from “tPH” to “th(D)”||||
|||**–**<br>changed symbol from “tPS” to “tsu(D)”||||
|||**–**<br>changed symbol from “tIV” to “tv(INT)”||||
|||**–**<br>changed symbol from “tIR” to “trst(INT)”||||



© NXP B.V. 2009. All rights reserved. 

PCA9537_5 

**Product data sheet** 

**Rev. 05 — 7 May 2009** 

**21 of 24** 

**PCA9537** 

**NXP Semiconductors** 

**4-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** 

**Table 15. Revision history** …continued 

|**Document ID**|**Release date**<br>**Data sheet status**|**Release date**<br>**Data sheet status**||**Change notice**|**Supersedes**|
|---|---|---|---|---|---|
|Modifcations|**•**<br>Figure|16“Expandedvie<br>wof wr<br>ite to output por<br>tregister”: changed symbol from “tPV” to “tv(Q)”||||
|(continued):|**•** (Old) Figure 18, “Test circuit” split into||Figure18“T<br>est circuit”and||T<br>ab<br>le11 “T<br>est data”|
||**–**<br>symbol changed from “tpv” to “tv(Q)”|||||
||**•** Added|soldering information||||
||**•** Added|T<br>ab<br>le14 “Ab<br>bre<br>viations”||||
|PCA9537_4|20060921|Product data sheet||-|PCA9537_3|
|PCA9537_3|20041129|Product data sheet||-|PCA9537_2|
|(9397 750 14259)||||||
|PCA9537_2|20040930|Objective data sheet||-|PCA9537_1|
|(9397 750 14052)||||||
|PCA9537_1|20040820|Objective data sheet||-|-|
|(9397 750 12894)||||||



© NXP B.V. 2009. All rights reserved. 

PCA9537_5 **Product data sheet** 

**Rev. 05 — 7 May 2009** 

**22 of 24** 

**PCA9537** 

**NXP Semiconductors** 

**4-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** 

## **17. Legal information** 

## **17.1 Data sheet status** 

|**Document statu**|**s**<br>**[1]**<br>**[2]**<br>**Product status**<br>**[3]**<br>**Defnition**|
|---|---|
|Objective [short] data sheet<br>Development<br>This document contains data from the objective specifcation for product development.||
|Preliminary [short] data sheet<br>Qualifcation<br>This document contains data from the preliminary specifcation.||
|Product [short] data sheet<br>Production<br>This document contains the product specifcation.||



[1] Please consult the most recently issued document before initiating or completing a design. 

[2] 

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 

## **17.2** 

**Draft —** The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 

**Short data sheet —** A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 

## **17.3 Disclaimers** 

**General —** Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. 

**Right to make changes —** NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 

**Suitability for use —** NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental 

damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. 

**Applications —** Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 

**Limiting values —** the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. 

**Terms and conditions of sale —** NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. 

**No offer to sell or license —** Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 

**Export control —** This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 

## **17.4 Trademarks** 

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 

**I[2] C-bus  —** logo is a trademark of NXP B.V. 

## **18. Contact information** 

For more information, please visit: **http://www.nxp.com** 

**salesaddresses@nxp.com** 

© NXP B.V. 2009. All rights reserved. 

PCA9537_5 

**Product data sheet** 

**Rev. 05 — 7 May 2009** 

**23 of 24** 

**PCA9537** 

**NXP Semiconductors** 

**4-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** 

## **19. Contents** 

|**1**|**General description . . . . . . . . . . . . . . . . . . . . . .  1**|
|---|---|
|**2**|**Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  1**|
|**3**|**Ordering information . . . . . . . . . . . . . . . . . . . . .  2**|
|**4**|**Block diagram  . . . . . . . . . . . . . . . . . . . . . . . . . .  2**|
|**5**|**Pinning information. . . . . . . . . . . . . . . . . . . . . .  3**|
|5.1|Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3|
|5.2|Pin description  . . . . . . . . . . . . . . . . . . . . . . . . . 3|
|**6**|**Functional description  . . . . . . . . . . . . . . . . . . .  4**|
|6.1|Device address . . . . . . . . . . . . . . . . . . . . . . . . . 4|
|6.2|Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4|
|6.2.1|Command byte . . . . . . . . . . . . . . . . . . . . . . . . . 4|
|6.2.2|Register 0 - Input Port register . . . . . . . . . . . . . 4|
|6.2.3|Register 1 - Output Port register. . . . . . . . . . . . 5|
|6.2.4<br>6.2.5|Register 2 - Polarity Inversion register . . . . . . . 5<br>Register 3 - Confguration register . . . . . . . . . . 6|
|6.3|Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 6|
|6.4|RESET input. . . . . . . . . . . . . . . . . . . . . . . . . . . 6|
|6.5|Interrupt output . . . . . . . . . . . . . . . . . . . . . . . . . 6|
|6.6|I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7|
|6.7|Bus transactions . . . . . . . . . . . . . . . . . . . . . . . . 8|
|**7**|**Application design-in information . . . . . . . . .  10**|
|7.1|Minimizing IDDwhen the I/Os are used to|
||control LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . 10|
|**8**|**Limiting values. . . . . . . . . . . . . . . . . . . . . . . . .  11**|
|**9**|**Static characteristics. . . . . . . . . . . . . . . . . . . .  11**|
|**10**|**Dynamic characteristics . . . . . . . . . . . . . . . . .  13**|
|**11**|**Test information. . . . . . . . . . . . . . . . . . . . . . . .  16**|
|**12**|**Package outline . . . . . . . . . . . . . . . . . . . . . . . .  17**|
|**13**|**Handling information. . . . . . . . . . . . . . . . . . . .  18**|
|**14**|**Soldering of SMD packages . . . . . . . . . . . . . .  18**|
|14.1<br>14.2|Introduction to soldering . . . . . . . . . . . . . . . . . 18<br>Wave and refow soldering . . . . . . . . . . . . . . . 18|
|14.3<br>14.4|Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 18<br>Refow soldering . . . . . . . . . . . . . . . . . . . . . . . 19|
|**15**|**Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . .  20**|
|**16**|**Revision history. . . . . . . . . . . . . . . . . . . . . . . .  21**|
|**17**|**Legal information. . . . . . . . . . . . . . . . . . . . . . .  23**|
|17.1|Data sheet status . . . . . . . . . . . . . . . . . . . . . . 23|
|17.2|Defnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23|
|17.3|Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 23|
|17.4|Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 23|
|**18**|**Contact information. . . . . . . . . . . . . . . . . . . . .  23**|
|**19**|**Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  24**|



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Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 

**© NXP B.V. 2009.** 

**All rights reserved.** 

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 

**Date of release: 7 May 2009 Document identifier: PCA9537_5**