NVMFS5C404NT1G

**DATA SHEET** ~~a~~ **www.onsemi.com** 

## MOSFET ~~—~~ - Power, Single N-Channel 40 V, 0.7 m 378 A NVMFS5C404N 

## **Features** 

- Small Footprint (5x6 mm) for Compact Design 

- Low R to Minimize Conduction Losses DS(on) 

- Low QG and Capacitance to Minimize Driver Losses 

- NVMFS5C404NWF − Wettable Flank Option for Enhanced Optical Inspection 

**V(BR)DSS RDS(ON) MAX ID MAX** 40 V 0.7 m @ 10 V 378 A ~~rree~~ 

**==> picture [108 x 100] intentionally omitted <==**

**----- Start of picture text -----**<br>
D (5,6)<br>G (4)<br>S (1,2,3)<br>N−CHANNEL MOSFET<br>**----- End of picture text -----**<br>


- AEC−Q101 Qualified and PPAP Capable 

**==> picture [189 x 149] intentionally omitted <==**

**----- Start of picture text -----**<br>
MARKING<br>DIAGRAMS<br>DFN5 D<br>CASE 506EZ<br>S D<br>2 1 S XXXXXX<br>S AYWZZ<br>DFNW5 G D<br>CASE 507BA D<br>XXXXXX = Specific Device Code<br>A = Assembly Location<br>Y = Year<br>W = Work Week<br>ZZ = Lot Traceability<br>**----- End of picture text -----**<br>


 These Devices are Pb−Free and are RoHS Compliant 

## **MAXIMUM RATINGS** (TJ = 25C unless otherwise noted) **Parameter Symbol** ~~a~~ 

|These Devices are Pb−Free and are RoHS Compliant<br>**MAXIMUM RATINGS**(TJ = 25C unless otherwise noted)J = 25C unless otherwise noted)= 25C unless otherwise noted)C unless otherwise noted)C unless otherwise noted)<br>~~a~~||**DIAGRAMS**<br>S<br>D<br>D<br>**DFN5**<br>**CASE 506EZ**<br>2|
|---|---|---|
|**Parameter**<br>**Symbol**<br>**Value**<br>**Unit**<br>~~a~~||XXXXXX<br>S<br>S<br>D<br>1<br>2|
|Drain−to−Source Voltage<br>VDSS<br>40<br>V<br>Gate−to−Source Voltage<br>VGS<br>20<br>V<br>Continuous Drain<br>Current R JC<br>(Notes 1, 3)<br>Steady<br>State<br>TC= 25C<br>ID<br>378<br>A<br>TC= 100C<br>267<br>Power Dissipation<br>R JC(Note 1)<br>TC= 25C<br>PD<br>200<br>W<br>TC= 100C<br>100<br>Continuous Drain<br>Current R JA<br>(Notes 1, 2, 3)<br>Steady<br>State<br>TA= 25C<br>ID<br>53<br>A<br>TA= 100C<br>37<br>Power Dissipation<br>R JA(Notes 1, 2)<br>TA= 25C<br>PD<br>3.9<br>W<br>TA= 100C<br>1.9<br>Pulsed Drain Current<br>TA= 25C, tp= 10 s<br>IDM<br>900<br>A<br>Operating Junction and Storage Temperature<br>Range<br>TJ, Tstg<br>−55 to<br>+175<br>C<br>Source Current (Body Diode)<br>IS<br>191<br>A<br>Single Pulse Drain−to−Source Avalanche<br>Energy (IL(pk)= 38 A)<br>EAS<br>907<br>mJ<br>Lead Temperature for Soldering Purposes<br>(1/8from case for 10 s)<br>TL<br>260<br>C<br>Stresses exceeding those listed in the Maximum Ratings table may damage the<br>AYWZZ<br>S<br>G<br>D<br>D<br>See detailed ordering, marking and shipping information on<br>page 5 of this data sheet.<br>**ORDERING INFORMATION**<br>XXXXXX = Specific Device Code<br>A<br>= Assembly Location<br>Y<br>= Year<br>W<br>= Work Week<br>ZZ<br>= Lot Traceability<br>**DFNW5**<br>**CASE 507BA**<br>~~es~~<br>~~——e=8~~<br>~~oo~~<br>~~pe ———~~<br>~~a ee~~<br>~~Oe~~<br>~~a~~<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~aC~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~eeee~~|||



Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 

## **THERMAL RESISTANCE MAXIMUM RATINGS** 

|**Parameter**<br>~~a~~|**Symbol**<br>~~a~~|**Value**<br>~~a~~|**Unit**<br>~~a~~|
|---|---|---|---|
|Junction−to−Case − Steady State|R JC|0.75|C/W|
|Junction−to−Ambient − Steady State (Note 2)|R JA|39||



1. The entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. 

2. Surface−mounted on FR4 board using a 650 mm[2] , 2 oz. Cu pad. 

3. Maximum current for pulses as long as 1 second is higher but is dependent on pulse duration and duty cycle. 

Publication Order Number: **NVMFS5C404N/D** 

**1** 

 Semiconductor Components Industries, LLC, 2015 **December, 2022 − Rev. 8** 

## **NVMFS5C404N** 

## **ELECTRICAL CHARACTERISTICS** (TJ = 25C unless otherwise specified) 

|**Parameter**|**Symbol**|**Test Condition**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|---|
|**OFF CHARACTERISTICS**||||||||
|Drain−to−Source Breakdown Voltage|V(BR)DSS|VGS= 0 V, ID=|250�A|40|||V|
|Drain−to−Source Breakdown Voltage<br>Temperature Coefficient|V(BR)DSS/<br>TJ||||19.7||mV/C|
|Zero Gate Voltage Drain Current|IDSS|VGS= 0 V,<br>VDS= 40 V|TJ= 25C|||10|�A|
||||TJ= 125C|||250||
|Gate−to−Source Leakage Current|IGSS|VDS= 0 V, VGS= 20 V||||100|nA|
|**ON CHARACTERISTICS**(Note 4)||||||||
|Gate Threshold Voltage|VGS(TH)|VGS= VDS, ID= 250�A||2.0||4.0|V|
|Threshold Temperature Coefficient|VGS(TH)/TJ||||−6.2||mV/C|
|Drain−to−Source On Resistance|RDS(on)|VGS= 10 V|ID= 50 A||0.57|0.7|m�|
|Forward Transconductance|gFS|VDS=15 V, ID= 50 A|||210||S|
|**CHARGES, CAPACITANCES & GATE RESISTANCE**||||||||
|Input Capacitance|CISS|VGS= 0 V, f = 1 MHz, VDS= 25 V|||8400||pF|
|Output Capacitance|COSS||||4600|||
|Reverse Transfer Capacitance|CRSS||||120|||
|Total Gate Charge|QG(TOT)|VGS= 10 V, VDS= 20 V; ID= 50 A|||128||nC|
|Threshold Gate Charge|QG(TH)|VGS= 10 V, VDS= 20 V; ID= 50 A|||22|||
|Gate−to−Source Charge|QGS||||35|||
|Gate−to−Drain Charge|QGD||||26|||
|Plateau Voltage|VGP||||4.3||V|
|**SWITCHING CHARACTERISTICS**(Note 5)||||||||
|Turn−On Delay Time|td(ON)|VGS= 10 V, VDS= 20 V,<br>ID= 50 A, RG= 2.5�|||16||ns|
|Rise Time|tr||||113|||
|Turn−Off Delay Time|td(OFF)||||77|||
|Fall Time|tf||||109|||
|**DRAIN−SOURCE DIODE CHARACTERISTICS**||||||||
|Forward Diode Voltage|VSD|VGS= 0 V,<br>IS= 50 A|TJ= 25C||0.76|1.2|V|
||||TJ= 125C||0.63|||
|Reverse Recovery Time|tRR|VGS= 0 V, dIS/dt = 100 A/�s,<br>IS= 50 A|||96||ns|
|Charge Time|ta||||49|||
|Discharge Time|tb||||47|||
|Reverse Recovery Charge|QRR||||189||nC|



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 4. Pulse Test: pulse width � 300 � s, duty cycle � 2%. 

5. Switching characteristics are independent of operating junction temperatures. 

**www.onsemi.com** 

**2** 

**NVMFS5C404N** 

## **TYPICAL CHARACTERISTICS** 

**==> picture [491 x 593] intentionally omitted <==**

**----- Start of picture text -----**<br>
800 600<br>10 V<br>6.5 V VDS = 10 V<br>700 8 V<br>7 V 6 V 500<br>600<br>5.8 V 400<br>500<br>5.6 V<br>400 300<br>5.4 V TJ = 25C<br>300<br>5.2 V 200<br>200 5.0 V <br>T J  = 125 C<br>4.8 V 100<br>100 4.6 V<br>0 4.4 V 0 TJ = −55C<br>0 0.5 1.0 1.5 2.0 2.5 3.0 3.0 4.0 5.0 6.0<br>VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS, GATE−TO−SOURCE VOLTAGE (V)<br>Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics<br>4.5 0.64<br>4.0 T J = 25C<br>IDS = 25 A 0.62<br>3.5<br>0.60<br>3.0<br>2.5 0.58<br>2.0 0.56<br>1.5<br>0.54<br>1.0<br>0.52<br>0.5<br>0.0 0.50<br>3 4 5 6 7 8 9 10 0 100 200 300 400 500 600 700 800<br>VGS, GATE VOLTAGE (V) ID, DRAIN CURRENT (A)<br>Figure 3. On−Resistance vs. Gate−to−Source Figure 4. On−Resistance vs. Drain Current and<br>Voltage Gate Voltage<br>2.1 1.E−03<br>VGS = 10 V<br>1.9 ID = 50 A<br>1.7 1.E−04 TJ = 150C<br>1.5<br>1.E−05<br>1.3 TJ = 125C<br>1.1<br>1.E−06<br>0.9 TJ = 85C<br>0.7 1.E−07<br>−50 −25 0 25 50 75 100 125 150 175 0 5 10 15 20 25 30 35 40<br>TJ, JUNCTION TEMPERATURE (C) VDS, DRAIN−TO−SOURCE VOLTAGE (V)<br>, DRAIN CURRENT (A) , DRAIN CURRENT (A)<br>ID ID<br>) � ) �<br>, DRAIN−TO−SOURCE RESISTANCE (m , DRAIN−TO−SOURCE RESISTANCE (m<br>DS(on) DS(on)<br>R R<br>, LEAKAGE (A)<br>IDSS<br>, NORMALIZED DRAIN−TO−<br>SOURCE RESISTANCE<br>DS(on)<br>R<br>**----- End of picture text -----**<br>


**Figure 5. On−Resistance Variation with Temperature** 

**Figure 6. Drain−to−Source Leakage Current vs. Voltage** 

**www.onsemi.com** 

**3** 

**NVMFS5C404N** 

## **TYPICAL CHARACTERISTICS** 

**==> picture [240 x 173] intentionally omitted <==**

**----- Start of picture text -----**<br>
1E+5<br>CISS<br>1E+4<br>COSS<br>1E+3<br>1E+2<br>CRSS<br>1E+1<br>VGS = 0 V<br>TJ = 25C<br>f = 1 MHz<br>1E+0<br>0 5 10 15 20 25 30 35 40<br>VDS, DRAIN−TO−SOURCE VOLTAGE (V)<br>C, CAPACITANCE (pF)<br>**----- End of picture text -----**<br>


**==> picture [240 x 382] intentionally omitted <==**

**----- Start of picture text -----**<br>
10<br>QT<br>8<br>6<br>Q GS Q GD<br>4<br>2 VDS = 20 V<br>ID = 50 A<br>TJ = 25C<br>0<br>0 10 20 30 40 50 60 70 80 90 100 110 120130<br>QG, TOTAL GATE CHARGE (nC)<br>Figure 8. Gate−to−Source and<br>Drain−to−Source Voltage vs. Total Charge<br>50<br>10<br>5<br>TJ = 150CJ = 150C = 150CCC<br>TJ = 125CJ = 125C = 125CCC TJ = 25CJ = 25C = 25CCC TJ = −55CJ = −55C = −55CCC<br>1<br>0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0<br>VSD, SOURCE−TO−DRAIN VOLTAGE (V)SD, SOURCE−TO−DRAIN VOLTAGE (V), SOURCE−TO−DRAIN VOLTAGE (V)<br>, GATE−TO−SOURCE VOLTAGE (V)<br>GS<br>V<br>, SOURCE CURRENT (A)<br>ISS<br>**----- End of picture text -----**<br>


**Figure 7. Capacitance Variation** 

**==> picture [489 x 384] intentionally omitted <==**

**----- Start of picture text -----**<br>
1000 50<br>VGS = 10 V td(off)<br>VDS = 20 V t f<br>I D = 50 A tr<br>100 t d(on)<br>10<br>5<br>10<br>TJ = 150CJ = 150C = 150CCC<br>TJ = 125CJ = 125C = 125CCC TJ = 25CJ = 25C = 25CCC TJ = −55CJ = −55C = −55CCC<br>1 1<br>1 10 100 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0<br>RG, GATE RESISTANCE ( � ) VSD, SOURCE−TO−DRAIN VOLTAGE (V)SD, SOURCE−TO−DRAIN VOLTAGE (V), SOURCE−TO−DRAIN VOLTAGE (V)<br>Figure 9. Resistive Switching Time Variation Figure 10. Diode Forward Voltage vs. Current<br>vs. Gate Resistance<br>1000 1000<br>100<br>10  � s 100<br>TJ(initial) = 25C<br>10 TC = 25C TJ(initial) = 100C<br>0.5 ms<br>Single Pulse<br>1 ms 10<br>VGS  10 V<br>1 10 ms<br>RDS(on) Limit<br>Thermal Limit<br>Package Limit<br>0.1 1<br>0.1 1 10 100 1000 1E−04 1E−03 1E−02<br>VDS, DRAIN−TO−SOURCE VOLTAGE (V) TIME IN AVALANCHE (s)<br>t, TIME (ns)<br>, SOURCE CURRENT (A)<br>ISS<br> (A)<br>IPEAK<br>, DRAIN CURRENT (A)<br>IDS<br>**----- End of picture text -----**<br>


**Figure 11. Maximum Rated Forward Biased Safe Operating Area** 

**Figure 12. IPEAK vs. Time in Avalanche** 

**www.onsemi.com** 

**4** 

**NVMFS5C404N** 

**==> picture [491 x 173] intentionally omitted <==**

**----- Start of picture text -----**<br>
100<br>50% Duty Cycle<br>10 20%<br>10%<br>5%<br>1 2% NVMFS5C404N 650 mm [2] , 2 oz., Cu Single Layer Pad<br>1%<br>0.1<br>Single Pulse<br>0.01<br>1E−06 1E−05 1E−04 1E−03 1E−02 1E−01 1E+00 1E+01 1E+02 1E+03<br>PULSE TIME (sec)<br>C/W)<br><br>(t) (<br>JA<br>�<br>R<br>**----- End of picture text -----**<br>


## **Figure 13. Thermal Characteristics** 

## **DEVICE ORDERING INFORMATION** 

|**Device**|**Case**|**Marking**|**Package**|**Shipping**†|
|---|---|---|---|---|
|NVMFS5C404NT1G|506EZ|5C404N|DFN5<br>(Pb−Free)|1500 / Tape & Reel|
|NVMFS5C404NWFT1G|507BA|404NWF|DFNW5<br>(Pb−Free)|1500 / Tape & Reel|
|NVMFS5C404NT3G|506EZ|5C404N|DFN5<br>(Pb−Free)|5000 / Tape & Reel|
|NVMFS5C404NWFT3G|507BA|404NWF|DFNW5<br>(Pb−Free)|5000 / Tape & Reel|
|NVMFS5C404NAFT1G|506EZ|5C404N|DFN5<br>(Pb−Free)|1500 / Tape & Reel|
|NVMFS5C404NWFAFT1G|507BA|404NWF|DFNW5<br>(Pb−Free)|1500 / Tape & Reel|
|NVMFS5C404NWFET1G|507BA|404NWF|DFNW5<br>(Pb−Free)|1500 / Tape & Reel|
|NVMFS5C404NWFET3G|507BA|404NWF|DFNW5<br>(Pb−Free)|5000 / Tape & Reel|



†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 

**www.onsemi.com** 

**5** 

MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

**==> picture [481 x 583] intentionally omitted <==**

**----- Start of picture text -----**<br>
DFN5 5x6, 1.27P (SO−8FL)<br>CASE 506EZ<br>ISSUE A<br>1 DATE 25 AUG 2021<br>SCALE 2:1<br>D Al NOT ES:<br>D 1 A 12.. DCON I M ETN ROLLS I ON II NGNG D AIND M EN ST IOO LN: E RAM NIC LL INIMET G P E R SASM E Y14.5M,<br>3. D I M E NS I ONS D i A ND £1 DO NOT I NCLUD E MOLD F L ASH,<br>— — PROTRUS IO NS, OR G A T E BURRS.<br>| | MILLIMETERS<br>ID N E N T1 IFIE R b o g t ax 0 || pma [oso| min. || NOM.100 || 110Max. ||<br>L | | ar | ooo | --- | 005 |<br>Wi c | 6 =| 033 | o41 | ost_|<br>Z|} L t<br>ian A t Mi | pd | soo | sis _| 530 |<br>T OP V IE W D E T AI L A EAB<br>[SJ o . 10 [c] Fe) fe | 127 BSC<br>S I D E V IE W PL A N E G 0.51 0.575 | 071<br>8x b 0.575<br>amene I 0.125 REF<br>ooste | mM | 300 | 340 | 380 _|<br>| oe | o |---|°<br>4<br>| ‘ 2X 0.4950 4.56 ie |<br>Li 2x 1 53-4+-—|<br>P A CK A G E 2X 0.25‘ I fo H<br>E e M OU T L I N E \ , 3.20<br>1 453<br>P IN 5S {o u | |<br>XPOS E D P AD ? 2X 0.9 1 1 43<br>GENERIC<br>ol ud 0.97 |<br>MARKING DIAGRAM*<br>1 1<br>BO TT OM 1 — L gakt. _. - J<br>V IE W | , "T d a -<br>XXXXXX<br>AYWZZ<br>4X 1.00 4X. 0.75L | Phi<br>7 R E COMM E ND E D<br>XXXXXX = Specific Device Code MOUN TI NG F OO T PR I N T<br>A = Assembly Location * ® F or addi ti onal i nf orma ti on on our Pk -F ree<br>Y = Year s t he t ra t ONegySemiconducand soldering t or Solderingde ta ils, pleaseand Moundownload ti ng<br>W = Work Week Techniques Re f erence Manual, SOLD ER RM/D.<br>ZZ = Lot Traceability<br>*This information is generic. Please refer to<br>device data sheet for actual part marking.<br>Pb−Free indicator, “G” or microdot “ ”,<br>may or may not be present. Some products<br>may not follow the Generic Marking.<br>**----- End of picture text -----**<br>


## **DOCUMENT NUMBER: 98AON24855H** 

**DESCRIPTION: DFN5 5x6, 1.27P (SO−8FL)** 

Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. 

**PAGE 1 OF 1** 

ON Semiconductor and          are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 

www.onsemi.com 

© Semiconductor Components Industries, LLC, 2018 

MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

## **DFNW5 5x6 (FULL−CUT SO8FL WF)** CASE 507BA ISSUE A DATE 03 FEB 2021 

**==> picture [485 x 158] intentionally omitted <==**

**----- Start of picture text -----**<br>
GENERIC<br>MARKING DIAGRAM*<br>4X. 100 4X 0.75; a ee<br>1 I _<br>R E COMM E ND E D<br>| XXXXXX<br>MOUN TI NG F OO T PR I N T<br>AYWZZ<br>' ; * F or additional i nf ormation on our Pb -F ree strategy<br>= and soldering de ta ils, please download t he ON<br>Semiconduc t or Soldering and Moun ti ng Techniques<br>XXXXXX = Specific Device Code Re f erence Manual, SOLD ER RM/D.<br>*This information is generic. Please refer to<br>A = Assembly Location device data sheet for actual part marking.<br>Y = Year Pb−Free indicator, “G” or microdot “ ”,<br>W = Work Week may or may not be present. Some products<br>ZZ = Lot Traceability may not follow the Generic Marking.<br>Electronic versions are uncontrolled except when accessed directly from the Document Repository.<br>DOCUMENT NUMBER: 98AON26450H Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red.<br>DESCRIPTION: DFNW5 5x6 (FULL−CUT SO8FL WF) PAGE 1 OF 1<br>**----- End of picture text -----**<br>


**onsemi** and                     are trademarks of Semiconductor Components Industries, LLC dba onsemi **onsemi** or its subsidiaries in the United States and/or other countries. **onsemi** reserves the right to make changes without further notice to any products herein. **onsemi** makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. **onsemi** does not convey any license under its patent rights nor the rights of others. 

www.onsemi.com 

© Semiconductor Components Industries, LLC, 2018 

**onsemi** , , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “ **onsemi** ” or its affiliates and/or subsidiaries in the United States and/or other countries. **onsemi** owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of **onsemi** ’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. **onsemi** reserves the right to make changes at any time to any products or information herein, without notice. The information herein is provided “as−is” and **onsemi** makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using **onsemi** products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by **onsemi** . “Typical” parameters which may be provided in **onsemi** data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. **onsemi** does not convey any license under any of its intellectual property rights nor the rights of others. **onsemi** products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use **onsemi** products for any such unintended or unauthorized application, Buyer shall indemnify and hold **onsemi** and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that **onsemi** was negligent regarding the design or manufacture of the part. **onsemi** is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. 

## **ADDITIONAL INFORMATION** 

**TECHNICAL PUBLICATIONS** : **ONLINE SUPPORT** : www.onsemi.com/support **Technical Library:** www.onsemi.com/design/resources/technical−documentation **For additional information, please contact your local Sales Representative at onsemi Website:** www.onsemi.com www.onsemi.com/support/sales 

**==> picture [232 x 43] intentionally omitted <==**

