NFAQ0560R43T

Intelligent Power Module (IPM) 600 V, 5 A 

## NFAQ0560R43T 

The NFAQ0560R43T is a fully−integrated inverter power stage consisting of a high−voltage driver, six IGBTs (FS4 RC IGBT technology) and a thermistor, suitable for driving permanent magnet synchronous motors (PMSM), brushless−DC (BLDC) motors and AC asynchronous motors. The IGBTs are configured in a 3−phase bridge with separate emitter connections for the lower legs for maximum flexibility in the choice of control algorithm. The power stage has a full range of protection functions including cross−conduction protection, external shutdown and under−voltage lockout functions. An internal comparator and reference connected to the over−current protection circuit allows the designer to set the over−current protection level. 

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www.onsemi.com<br>DIP38 29.6x18.2<br>CASE 181AE<br>**----- End of picture text -----**<br>


## **Features** 

- Three−phase 5 A / 600 V IGBT Module with Integrated Drivers 

- Compact 29.6 mm x 18.2 mm Dual In−Line Package 

- Built−in Under Voltage Protection 

- Cross−conduction Protection 

- ITRIP Input to Shut Down All IGBTs 

- Integrated Bootstrap Diodes and Resistors 

- Thermistor for Substrate Temperature Measurement 

- Shut Down Pin 

- UL1557 Certification (File Number: E339285) 

## **Typical Applications** 

- Industrial Pumps 

- Industrial Fans 

- Industrial Automation 

- Home Appliances 

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HIN(U) HS1<br>LIN(U) LS1<br>HS1 HS2 HS3<br>HIN(V) Three channel HS2<br>half−bridge<br>LIN(V) driver LS2<br>with<br>HIN(W) protection HS3<br>circuits<br>LIN(W) LS3<br>LS1 LS2 LS3<br>VB(U) VB(V) VB(W) VDD VSS TH1 TH2 P VS(U),U VS(V),V VS(W),W<br>SD CFOD FAULT ITRIP NU NV NW<br>**----- End of picture text -----**<br>


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MARKING DIAGRAM<br>NFAQ0560R43T<br>ZZZATYWW<br>=<br>NFAQ0560R43T = Specific Device Code<br>ZZZ = Assembly Lot Code<br>A = Assembly Location<br>T = Test Location<br>Y = Year<br>WW = Work Week<br>**----- End of picture text -----**<br>


Device marking is on package top side 

## **ORDERING INFORMATION** 

**Shipping Device Package (Qty / Packing)** NFAQ0560R43T DIP38 400 / Box (Pb-Free) 

**Figure 1. Function Diagram** 

Publication Order Number: **NFAQ0560R43T/D** 

**1** 

© Semiconductor Components Industries, LLC, 2020 **February, 2021 − Rev. 1** 

**NFAQ0560R43T** 

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RC filtering for<br>HINxand LINx<br>VPN<br>not shown.<br>P:38<br>C1 + CS From Op−ampcircuit Recommendedin noisy<br>ITRIP:10 environments.<br>HV Ground<br>RSU<br>NU:17 HIN(U):3<br>From HV<br>Power HIN(V) :4<br>RSV<br>Source NV:18 HIN(W):5<br>LIN(U):6<br>RSW<br>NW:19 LIN(V) :7<br>To Op−amp LIN(W):8<br>circuit<br>Vctr<br>from external<br>VB(U):34 regulator RSD RP RTH<br>+ SD:11<br>Controller<br>VS(U),U:32 FAULT:9<br>TH2:14<br>VB(V):28<br>VDD:2 VDD= 15V<br>+<br>from external<br>Motor VS(V),V:26 RCLR regulator<br>CFOD:12<br>VB(W):22<br>+ +<br>TH1:13 CCLR<br>VS(W),W:20 VSS [:] 1<br>LV Ground<br>Star connection to HV Ground<br>**----- End of picture text -----**<br>


**Figure 2. Application Schematic** 

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**NFAQ0560R43T** 

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Bootstrap VB(U) (34)<br>Bootstrap VB(V) (28)<br>Bootstrap VB(W) (22)<br>VDD (2) P (38)<br>VSS (1)<br>Sets latch time.<br>For R=2M Ω , VS(W),W (20)<br>C=1nF, latch time VS(V),V (26)<br>is 1.65ms (typical).<br>VS(U),U (32)<br>CFOD(12)<br>NU (17)<br>NV (18)<br>NW (19)<br>Level Level Level<br>Shifter Shifter Shifter<br>HIN(U) (3)<br>HIN(V) (4)<br>HIN(W) (5)<br>Logic Logic Logic<br>LIN(U) (6)<br>LIN(V) (7)<br>LIN(W) (8)<br>TH1 (13)<br>TH2 (14) VDD<br>VDD undervoltage<br>shutdown FAULT (9)<br>ITRIP (10) Over current<br>Internal Voltage protection<br>reference<br>SD (11) Shutdown<br>**----- End of picture text -----**<br>


**Figure 3. Simplified Block Diagram** 

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**NFAQ0560R43T** 

## **PIN FUNCTION DESCRIPTION** 

|**Pin**|**Name**|**Description**|
|---|---|---|
|1|VSS|Low−Side Common Supply Ground|
|2|VDD|Low−Side Bias Voltage for IC and IGBTs Driving|
|3|HIN(U)|Signal Input for High−Side U Phase|
|4|HIN(V)|Signal Input for High−Side V Phase|
|5|HIN(W)|Signal Input for High−Side W Phase|
|6|LIN(U)|Signal Input for Low−Side U Phase|
|7|LIN(V)|Signal Input for Low−Side V Phase|
|8|LIN(W)|Signal Input for Low−Side W Phase|
|9|FAULT|Fault output|
|10|ITRIP|Input for Over Current Protection|
|11|SD|Shut Down Input|
|12|CFOD|Capacitor and Resistor for Fault Output Duration Selection|
|13|TH1|Thermistor Bias Voltage|
|14|TH2|Series Resistor for Thermistor|
|17|NU|Negative DC−Link Input for U Phase|
|18|NV|Negative DC−Link Input for V Phase|
|19|NW|Negative DC−Link Input for W Phase|
|20|VS(W), W|High−Side Bias Voltage GND for W phase IGBT Driving, Output for W Phase|
|22|VB(W)|High−Side Bias Voltage for W phase IGBT Driving|
|26|VS(V), V|High−Side Bias Voltage GND for V phase IGBT Driving, Output for V Phase|
|28|VB(V)|High−Side Bias Voltage for V phase IGBT Driving|
|32|VS(U), U|High−Side Bias Voltage GND for U phase IGBT Driving, Output for U Phase|
|34|VB(U)|High−Side Bias Voltage for U phase IGBT Driving|
|38|P|Positive DC−Link Input|



NOTE: Pins 15, 16, 21, 23, 24, 25, 27, 29, 30, 31, 33, 35, 36 and 37 are not present 

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## **NFAQ0560R43T** 

## **ABSOLUTE MAXIMUM RATINGS** at TC = 25 ° C (Note 1) 

|**Parameter**|**Symbol**|**Conditions**|**Rating**|**Unit**|
|---|---|---|---|---|
|Supply Voltage|VPN|P−NU,NV,NW, VPN (surge) < 500 V<br>(Note 2)|450|V|
|Collector−Emitter Voltage|VCES|P-U,V,W; U-NU; V-NV; W-NW|600|V|
|Each IGBT Collector Current|IC|P,U,V,W,NU,NV,NW terminal current|±5|A|
|||P,U,V,W,NU,NV,NW terminal current, Tc = 100°C|±2.5|A|
|Each IGBT Collector Current (Peak)|ICp|Tc = 25°C, Under 1 ms Pulse Width|±10|A|
|Corrector Dissipation|Pc|Tc = 25°C, Per One Chip (IGBT Part)|29|W|
|||Tc = 25°C, Per One Chip (FRD Part)|12.5|W|
|High−Side Control Bias voltage|VBS|VB(U)−VS(U), VB(V)−VS(V),<br>VB(W)−VS(W)<br>(Note 3)|−0.3 to +20.0|V|
|Control Supply Voltage|VDD|VDD−VSS|−0.3 to +20.0|V|
|Input Signal Voltage|VIN|HIN(U), HIN(V), HIN(W), LIN(U), LIN(V), LIN(W) −<br>VSS|−0.3 to VDD|V|
|FAULT Terminal Voltage|VFAULT|FAULT−VSS|−0.3 to VDD|V|
|CFOD Terminal Voltage|VCFOD|CFOD−VSS|−0.3 to VDD|V|
|SD Terminal Voltage|VSD|SD−VSS|−0.3 to VDD|V|
|Current Sensing Input Voltage|VITRIP|ITRIP−VSS|−0.3 to +10.0|V|
|Operating Junction Temperature|Tj||150|�C|
|Storage Temperature|Tstg||−40 to +125|�C|
|Module Case Operation Temperature|Tc||−40 to +125|�C|
|Tightening Torque|MT|Case mounting screws|0.6|Nm|
|Isolation Voltage|Viso|50 Hz sine wave AC 1 minute<br>(Note 4)|2000|Vrms|



Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 

1. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe Operating parameters 

2. This surge voltage developed by the switching operation due to the wiring inductance between P and NU, NV, NW terminal. 3. VBS = VB(U)−VS(U), VB(V)−VS(V), VB(W)−VS(W) 

4. Test conditions : AC2500V, 1 s 

## **RECOMMENDED OPERATING RANGES** 

|**Rating**|**Symbol**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|Supply Voltage|VPN|P − NU, NV, NW|0|280|450|V|
|High−Side Control Bias<br>Voltage|VBS|VB(U) − VS(U), VB(V) − VS(V), VB(W) −<br>VS(W)|13.0|15|17.5|V|
|Control Supply Voltage|VDD|VDD − VSS|14.0|15|16.5|V|
|ON−state Input Voltage|VIN(ON)|HIN(U), HIN(V), HIN(W), LIN(U), LIN(V),<br>LIN(W) − VSS|3.0|−|5.0|V|
|OFF−state Input Voltage|VIN(OFF)||0|−|0.3|V|
|PWM Frequency|fPWM||1|−|20|kHz|
|Dead Time|DT|Turn−off to Turn−on (external)|1|−|−|�s|
|Allowable Input Pulse Width|PWIN|ON and OFF|1|−|−|�s|
|Tightening Torque||‘M3’ Type Screw|0.4|−|0.6|Nm|



Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 

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## **NFAQ0560R43T** 

**ELECTRICAL CHARACTERISTICS** at TC = 25 � C, VBIAS (VBS, VDD) = 15 V unless otherwise noted. 

|**Parameter**|**Test Conditions**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|**POWER OUTPUT SECTION**|||||||
|Collector−Emitter Leakage Current|VCE= 600 V|ICES|−|−|100|�A|
|Collector−Emitter Saturation Voltage|IN = 5 V, IC = 5 A, Tj = 25�C|VCE(sat)|−|2.0|2.6|V|
||IN = 5 V, IC = 2.5 A, Tj = 100�C||−|1.5|−|V|
|FWDi Forward Voltage|IN = 0 V, IC = −5 A, Tj = 25�C|VF|−|2.2|2.7|V|
||IN = 0 V, IC = −2.5 A, Tj = 100�C||−|1.8|−|V|
|Junction to Case Thermal Resistance|Inverter IGBT Part (per 1/6 Module)|Rth(j−c)Q|−|−|4.3|�C/W|
||Inverter FRD Part(per 1/6 Module)|Rth(j−c)F|−|−|10|�C/W|
|**SWITCHING CHARACTER**|||||||
|Switching Time|IC = 5 A, VPN = 300 V, Tj = 25�C,<br>Inductive Switching|tON|−|0.5|1.1|�s|
|||tOFF|−|0.6|1.2|�s|
|Turn−on Switching Loss|IC = 5 A, VPN = 300 V, Tj = 25�C|EON|−|200|−|�J|
|Turn−off Switching Loss||EOFF|−|60|−|�J|
|Total Switching Loss||ETOT|−|260|−|�J|
|Turn−on Switching Loss|IC = 2.5 A, VPN = 300 V, Tj = 100�C|EON|−|110|−|�J|
|Turn−off Switching Loss||EOFF|−|50|−|�J|
|Total Switching Loss||ETOT|−|160|−|�J|
|Diode Reverse Recovery Energy|IC = 2.5 A, VPN = 300 V, Tj = 100�C,<br>(di/dt set by internal driver)|EREC|−|25|−|�J|
|Diode Reverse Recovery Time||tRR|−|180|−|ns|
|Reverse Bias Safe Operating Area|IC = 10 A, VCE= 450 V|RBSOA||Full Square|||
|Short Circuit Safe OperatingArea|VCE= 400 V, Tj= 100�C|SCSOA|4|−|−|�s|
|**DRIVER SECTION**|||||||
|Quiescent VBS Supply Current|VBS = 15 V, HIN = 0 V, per driver|IQBS|−|0.08|0.4|mA|
|Quiescent VDD Supply Current|VDD = 15 V, LIN = 0 V, VDD−VSS|IQDD|−|0.95|3.0|mA|
|ON Threshold Voltage|HIN(U), HIN(V), HIN(W), LIN(U), LIN(V),<br>LIN(W) − VSS|VIN(ON)|−|−|2.5|V|
|OFF Threshold Voltage||VIN(OFF)|0.8|−|−|V|
|Logic 1 Input Current|VIN = +3.3 V|IIN+|−|660|900|�A|
|Logic 0 Input Current|VIN = 0 V|IIN−|−|−|3|�A|
|Bootstrap ON Resistance|IB = 1 mA|RB|−|500|−|�|
|FAULT Terminal Sink Current|FAULT: ON / VFAULT = 0.1 V|IoSD|−|2|−|mA|
|Fault−Output Pulse Width|FAULT−VSS<br>From time fault condition clear<br>R = 2 M�, C = 1 nF|tFOD|1.1|1.65|2.2|ms|
|CFOD Threshold|CFOD−VSS|VCFOD|−|8|−|V|
|Shut Down Threshold|SD−VSS|VSD+|−|−|2.5|V|
|||VSD−|0.8|−|−|V|
|ITRIP Trip Level|ITRIP−VSS|VITRIP|0.44|0.49|0.54|V|
|ITRIP to Shutdown Propagation Delay||tITRIP|−|1.1|−|�s|
|ITRIP Blanking Time||tITRIPBL|250|350|−|ns|
|High−Side Control Bias Voltage<br>Under−Voltage Protection|Reset Level|UVBSR|10.3|11.1|11.9|V|
||Detection Level|UVBSD|10.1|10.9|11.7|V|
||Hysteresis|UVBSH|−|0.2|−|V|
|Supply Voltage Under−Voltage Protection|Reset Level|UVDDR|10.3|11.1|11.7|V|
||Detection Level|UVDDD|10.1|10.9|11.5|V|
||Hysteresis|UVDDH|−|0.2|−|V|



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 

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**NFAQ0560R43T** 

## **TYPICAL CHARACTERISTICS** 

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10 10<br>8 8<br>TJ = 25 ° C<br>6 6<br>TJ = 100 ° C<br>4 T J  = 100 ° C 4<br>TJ = 25 ° C<br>2 2<br>0<br>0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0<br>VCE, Collector−Emitter Voltage (V) VF, Forward Voltage (V)<br>, Forward Current (A)<br>, Collector Current (A)IC IF<br>**----- End of picture text -----**<br>


**Figure 4. VCE versus IC for Different Temperatures (VDD = 15 V)** 

**Figure 5. VF versus IF for Different Temperatures** 

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1,000<br>VPN = 300 V<br>VDD = 15 V<br>800<br>600<br>TJ = 100 ° C<br>400<br>TJ = 25 ° C<br>200<br>0<br>0 2 4 6 8 10<br>IC, Collector Current (A)<br>J)<br>�<br>, Switching Loss (<br>ON<br>E<br>**----- End of picture text -----**<br>


**Figure 6. EON versus IC for Different Temperatures** 

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1,000<br>VPN = 300 V<br>800 V DD = 15 V<br>600<br>400<br>TJ = 100 ° C<br>200<br>TJ = 25 ° C<br>0<br>0 2 4 6 8 10<br>IC, Collector Current (A)<br>J)<br>�<br>, Switching Loss (<br>OFF<br>E<br>**----- End of picture text -----**<br>


**Figure 7. EOFF versus IC for Different Temperatures** 

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1.0 1.0<br>0.8 0.8<br>0.6 0.6<br>0.4 0.4<br>0.2 0.2<br>0.0 0.0<br>0.000001 0.00001 0.0001 0.001 0.01 0.1 1 0.000001 0.00001 0.0001 0.001 0.01 0.1 1<br>ON−Pulse Width (s) ON−Pulse Width (s)<br>R(t) R(t)<br>Standardized Square−wave Peak, Standardized Square−wave Peak,<br>**----- End of picture text -----**<br>


**Figure 8. Thermal Impedance Plot (IGBT)** 

**Figure 9. Thermal Impedance Plot (FRD)** 

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**NFAQ0560R43T** 

## **TYPICAL CHARACTERISTICS** (Continued) 

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600 12 600 12<br>500 10 500 10<br>400 8 400 8<br>Vce<br>300 6 300 6<br>200 4 200 4<br>Ic<br>100 2 100 2<br>Ic Vce<br>0 0 0 0<br>0.0 0.5 1.0 1.5 2.0 0.0 0.5 1.0 1.5 2.0<br>Time ( � s) Time ( � s)<br>, Collector Current (A) , Collector Current (A)<br>IC IC<br>, Collector−Emitter Voltage (V) , Collector−Emitter Voltage (V)<br>CE CE<br>V V<br>**----- End of picture text -----**<br>


**Figure 10. Turn−on Waveform Tj = 25** � **C, VCC = 300 V** 

**Figure 11. Turn−off Waveform Tj = 25** � **C, VCC = 300 V** 

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**NFAQ0560R43T** 

## **APPLICATIONS INFORMATION** 

## **Input / Output Timing Chart** 

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HIN is disabled until LIN receives input (Note 5) VBS undervoltage protection reset signal<br>HIN<br>LIN<br>VDD undervoltage protection reset voltage (Note 2)<br>VDD VBS undervoltage protection reset voltage(Note 3)<br>VB(U), VB(V), VB(W)<br>VIT  � 0.54V<br>(Note4)<br>ITRIP VIT < 0.44V<br>FAULT driven output<br>(with pull−up)<br>SD driven input<br>(with pull−up)<br>Cross−conduction prevention period(Note 1)<br>Upper IGBT<br>Gate Drive<br>Lower IGBT<br>Gate Drive<br>Automatic reset after protection(Fault−Output Pulse Width )<br>**----- End of picture text -----**<br>


## NOTES: 

1. This section of the timing diagram shows the effect of cross−conduction prevention. 

2. This section of the timing diagram shows that when the voltage on VDD decreases sufficiently all gate output signals will go low, switching off all six IGBTs. When the voltage on VDD rises sufficiently, normal operation will resume. 

3. This section shows that when the bootstrap voltage on VB(U) (VB(V), VB(W)) drops, the corresponding high side output U (V, W) is switched off. When the voltage on VB(U) (VB(V), VB(W)) rises sufficiently, normal operation will resume. 

4. This section shows that when the voltage on ITRIP exceeds the threshold, all IGBTs are turned off. Normal operation resumes later after the over−current condition is removed. 

5. After VDD has risen above the threshold to enable normal operation, the driver waits to receive an input signal on the LIN input before enabling the driver for the HIN signal. 

## **Figure 12. Input / Output Timing Chart** 

**Table 1. INPUT / OUTPUT LOGIC TABLE** 

||**INPUT**|**INPUT**|||**OUTPUT**|**OUTPUT**||
|---|---|---|---|---|---|---|---|
|**HIN**|**LIN**|**ITRIP**|**SD**|**High side IGBT**|**Low side IGBT**|**U,V,W**|**FAULT**|
|H|L|L|H|ON (Note 5)|OFF|P|OFF|
|L|H|L|H|OFF|ON|NU,NV,NW|OFF|
|L|L|L|H|OFF|OFF|High Impedance|OFF|
|H|H|L|H|OFF|OFF|High Impedance|OFF|
|X|X|H|X|OFF|OFF|High Impedance|ON|
|X|X|L|L|OFF|OFF|High Impedance|OFF|



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**NFAQ0560R43T** 

**Table 2. THERMISTOR CHARACTERISTICS** 

|**Parameter**|**Parameter**|**Parameter**|**Symbol**|**Symbol**|**Symbol**|**Condition**|**Condition**|**Condition**|**Condition**|**Min**|**Min**|**Min**|**Min**|**Typ**|**Typ**|**Typ**|**Typ**|**Max**|**Max**|**Max**|**Unit**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Resistance|||R25|||Tth = 25�C||||99||||100||||101|||k�|
||||R100|||Tth = 100�C||||5.2||||5.4||||5.6|||k�|
|B−Constant (25 to 50�C)|||B|||||||4208||||4250||||4293|||K|
|Temperature Range||||||||||−40||||||−||+125|||�C|
|1<br>10<br>100<br>1000<br>10000<br>−40 −30 −20 −10<br>0<br><br>**Thermistor Resistance Value (k�)**||||||||||||||||||||||
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**Figure 13. Thermistor Resistance versus Thermistor Temperature** 

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6.0<br>5.0 max<br>typ<br>min<br>4.0<br>3.0<br>2.0<br>1.0<br>0.0<br>−40 −30 −20 −10 0 10 20 30 40 50 60 70 80 90 100 110 120 130<br>Tth, Thermistor Temperature ( � C)<br>) �<br>Thermistor Resistance Value (k<br>**----- End of picture text -----**<br>


**Figure 14. Thermistor Voltage versus Thermistor Temperature Conditions: RTH = 39 k � , Pull−up Voltage 5.0 V (see Figure 2)** 

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## **NFAQ0560R43T** 

## **FAULT Pin** 

The FAULT output is an open drain output requiring a pull−up resistor. If the pull−up voltage is 5 V, use a pull−up resistor with a value of 6.8 k� or higher. If the pull−up voltage is 15 V, use a pull−up resistor with a value of 20 k� or higher. The FAULT output is triggered if there is a VDD undervoltage or an overcurrent condition. 

## **Under−voltage Protection** 

If VDD goes below the VDD supply under−voltage lockout falling threshold, the FAULT output is switched on. The FAULT output stays on until VDD rises above the VDD supply under−voltage lockout rising threshold. After VDD has risen above the threshold to enable normal operation, the driver waits to receive an input signal on the LIN input before enabling the driver for the HIN signal. 

## **Calculation of Bootstrap Capacitor Value** 

The bootstrap capacitor value CB is calculated using the following approach. The following parameters influence the choice of bootstrap capacitor: 

- VBS: Bootstrap power supply. 15 V is recommended. 

- QG: Total gate charge of IGBT at VBS = 15 V. 8 nC. 

- UVLO: Falling threshold for UVLO. Specified as 12 V. 

- IDMAX: High side drive power dissipation. Specified as 0.4 mA. 

- TONMAX: Maximum ON pulse width of high side IGBT. 

Capacitance calculation formula: 

## **Overcurrent Protection** 

An over−current condition is detected if the voltage on the ITRIP pin is larger than the reference voltage. There is a blanking time of typically 350 ns to improve noise immunity. After a shutdown propagation delay of typically 1.1 �s, the FAULT output is switched on. The FAULT output is held on for a time determined by the resistor and capacitor connected to the CFOD pin. If RCLR = 2 M� and CCLR = 1 nF, the FAULT output is switched on for 1.65 ms (typ.) because the FAULT pin goes back to high impedance when CFOD is higher than 8 V (typ.). 

The over−current protection threshold should be set to be equal or lower to 2 times the module rated current (Io). 

An additional fuse is recommended to protect against system level or abnormal over−current fault conditions. 

CB = (QG + IDMAX * TONMAX)/(VBS − UVLO) 

CB is recommended to be approximately 3 times the value calculated above. The recommended value of CB is in the range of 1 to 47 �F, however, the value needs to be verified prior to production. When not using the bootstrap circuit, each high side driver power supply requires an external independent power supply. 

The internal bootstrap circuit uses a MOSFET. The turn on time of this MOSFET is synchronized with the turn on of the low side IGBT. The bootstrap capacitor is charged by turning on the low side IGBT. 

If the low side IGBT is held on for a long period of time (more than one second for example), the bootstrap voltage on the high side MOSFET will slowly discharge. 

## **Capacitors on High Voltage and VDD Supplies** 

Both the high voltage and VDD supplies require an electrolytic capacitor and an additional high frequency capacitor. The recommended value of the high frequency capacitor is between 100 nF and 10 �F. 

## **SD Pin** 

The SD terminal pin is used to enable or shut down the built−in driver. If the voltage on the SD pin rises above the VSD+ voltage, the output drivers are enabled. If the voltage on the SD pin falls below the VSD− voltage, the drivers are disabled. 

## **Minimum Input Pulse Width** 

When input pulse width is less than 1 �s, an output may not react to the pulse. (Both ON signal and OFF signal) 

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**----- Start of picture text -----**<br>
100<br>10<br>1<br>0.1<br>0.01<br>0.1 1 10 100 1000<br>Tonmax (ms)<br>F)<br>�<br>Boot strap capacitance Cb (<br>**----- End of picture text -----**<br>


**Figure 15. Bootstrap Capacitance versus Tonmax** 

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**11** 

**NFAQ0560R43T** 

## **TEST CIRCUITS** 

## • ICES 

|• ICES|||||||
|---|---|---|---|---|---|---|
||U+|V+|W+|U−|V−|W−|
|A|38|38|38|32|26|20|
|B|32|26|20|17|18|19|



U+, V+, W+ : High side phase U−, V−, W− : Low side phase 

## • VCE(sat)  (Test by pulse) 

||U+|V+|W+|U−|V−|W−|
|---|---|---|---|---|---|---|
|A|38|38|38|32|26|20|
|B|32|26|20|17|18|19|
|C|3|4|5|6|7|8|



**==> picture [230 x 353] intentionally omitted <==**

**----- Start of picture text -----**<br>
VBS=15V 34 ICE<br>32 A A<br>VBS=15V 28<br>26 VCE<br>VBS=15V 22<br>20<br>VDD=15V 2,9,11,12 B<br>1,10,17,18,19<br>Figure 16. Test Circuit for ICE<br>VBS=15V 34<br>32 A<br>VBS=15V 28<br>26<br>V IC<br>VBS=15V 22 VCE(sat)<br>20<br>VDD=15V 2,9,11,12<br>5V C B<br>1,10,17,18,19<br>**----- End of picture text -----**<br>


**Figure 17. Test Circuit for VCE(SAT)** 

## • VF  (Test by pulse) 

||U+|V+|W+|U−|V−|W−|
|---|---|---|---|---|---|---|
|A|38|38|38|32|26|20|
|B|32|26|20|17|18|19|



**==> picture [122 x 123] intentionally omitted <==**

**----- Start of picture text -----**<br>
A<br>V<br>VF<br>B<br>**----- End of picture text -----**<br>


**Figure 18. Test Circuit for VF** 

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**12** 

**NFAQ0560R43T** 

## • RB  (Test by pulse) 

||U+|V+|W+|
|---|---|---|---|
|A|2|2|2|
|B|34|28|22|
|C|6|7|8|



**==> picture [230 x 101] intentionally omitted <==**

**----- Start of picture text -----**<br>
A<br>V IB<br>VB<br>VDD=15V 2,9,11,12<br>(RB)<br>5V C<br>B<br>1,10,17,18,19<br>**----- End of picture text -----**<br>


**Figure 19. Test Circuit for RB** 

## • IQBS, IQDD 

||VBS U+|VBS V+|VBS W+|VDD|
|---|---|---|---|---|
|A|34|28|22|2|
|B|32|26|20|1|



**==> picture [174 x 137] intentionally omitted <==**

**----- Start of picture text -----**<br>
IQBS<br>A A<br>VBSx=15V<br>B<br>IQDD<br>A 2<br>VDD=15V 9,11,12<br>1,10<br>**----- End of picture text -----**<br>


**Figure 20. Test Circuit for ID** 

- Switching Time (The circuit is a representative example of the Inverter Low side U phase.) 

**==> picture [448 x 162] intentionally omitted <==**

**----- Start of picture text -----**<br>
VBS=15V 34<br>32 38<br>Input Signal<br>(0 to 5V) VBS=15V 28<br>26<br>CS<br>32<br>VBS=15V 22<br>90%<br>lo 10% 20<br>VDD=15V 2,9,11,12<br>tON tOFF Input Signal 6 17<br>1,10,17,18,19 Io<br>**----- End of picture text -----**<br>


**Figure 21. Test Circuit for Switching Time** 

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**13** 

MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

**DIP38 29.60x18.20 EP−5** CASE 181AE ISSUE A 

DATE 05 MAY 2021 

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**----- Start of picture text -----**<br>
GENERIC<br>MARKING DIAGRAM*<br>XXXXXXXXXXXXXXXXX<br>ZZZATYWW<br>XXX = Specific Device Code<br>ZZZ = Assembly Lot Code<br>AT = Assembly & Test Location<br>Y = Year<br>WW = Work Week<br>**----- End of picture text -----**<br>


*This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ a ”, may or may not be present. Some products may not follow the Generic Marking. 

**DOCUMENT NUMBER: 98AON28691H** 

**DESCRIPTION: DIP38 29.60x18.20 EP−5** 

Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. 

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