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NDM2Z-50HS-A-001
NON ISO- ADJUST O/P DC TO DC CONVERTERS
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- Manufacturer: BEL / PARTNER STOCK
- Product type: DC / DC Non Isolated Board Mount Converters - Adjustable Output
- SVHC: To Be Advised
- Product Range: Novum NDM2Z Series
| Delivery and price | |
|---|---|
| Units per pack | 6 |
| Price | 102.41 € |
| Current stock | 100+ |
| Lead time | 30 days |
Datasheet
- Additional Resources: Product Page | 3D Model **date** 12/21/2015 **page** 1 of 32 - Z| CuUIINc **SERIES** : NDM2Z-50 **DESCRIPTION** : AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER **GENERAL CHARACTERISTICS FEATURES** • 4.5~14 V input range • pin and function compatible with • 0.6~3.3 V programmable output Architects of Modern Power™ • voltage tracking product standards • voltage margining• active current sharing• active current sharing • compact package, horizontal: 30.85 x 20.0 x 8.2 mm 30.85 x 20.0 x 8.2 mm aigig y i " of nf of 4 nf of 4 of 4 4 e - _Snapshot_ ™ parametric capture • compact package, vertical: - • voltage/current/temperature monitoring 33.0 x 7.60 x 18.1 mm • synchronization and phase spreading • 50 A output • remote differential voltage sense • high efficiency ae “EF = id - • programmable soft start and soft stop • auto compensation a oo hy hy ~ 7 a= • fault management • SMBus interface is = Ss Ss • PMBus™ Compatible - . - if | \(> ModernArchitectsPowerofArchitectsPowerofPowerofof "=PP LE: RoHSa~~a~~~~ - **MODEL input voltage output voltage output current output wattage max max** - (Vdc) (Vdc) (A) (W) - NDM2Z-50 4.5~14 0.6~3.3 50 165 **PART NUMBER KEY - - -** - **NDM2Z 50 X X XXX** - Base Number Firmware Con guration: 000~ZZZ - Module Orientation and Pin Style: HS = horizontal, surface mount HT = horizontal, through hole mount V = vertical Pin Con guration: A = 3.56 mm pin length (HT) 4.0 mm pin length (V) B = 5.5 mm pin length (V) Example part number: **NDM2Z-50V-A-002** vertical module - 4.00 mm pin length - rmware con guration 002 - * HS and HT modules are delivered on tape and reel * V modules are delivered in trays **SERIES** : NDM2Z-50 **DESCRIPTION** : AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER ## **GENERAL CHARACTERISTICS** - 4.5~14 V input range - 0.6~3.3 V programmable output - voltage tracking • voltage margining• active current sharing• active current sharing • compact package, horizontal: 30.85 x 20.0 x 8.2 mm 30.85 x 20.0 x 8.2 mm aigig y i " • _Snapshot_ ™ parametric capture • compact package, vertical: of nf of 4 nf of 4 of 4 4 e • voltage/current/temperature monitoring 33.0 x 7.60 x 18.1 mm • synchronization and phase spreading • 50 A output • remote differential voltage sense • high efficiency ae “EF = • programmable soft start and soft stop • auto compensation a oo hy hy ~ 7 a= • fault management • SMBus interface is = Ss Ss • PMBus™ Compatible . if | \(> ModernArchitectsPowerofArchitectsPowerofPowerofof "=PP LE: RoHSa~~a~~~~ **MODEL input voltage output voltage output current output wattage max max** (Vdc) (Vdc) (A) (W) NDM2Z-50 4.5~14 0.6~3.3 50 165 - active current sharing - _Snapshot_ ™ parametric capture - voltage/current/temperature monitoring - synchronization and phase spreading - remote differential voltage sense - programmable soft start and soft stop - fault management ## **PART NUMBER KEY** **cui** .com Additional Resources: Product Page | 3D Model **CUI Inc � SERIES** : NDM2Z-50 **� DESCRIPTION** : AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER **date** 12/21/2015 **� page** 2 of 32 |**ABSOLUTE MAXIMUM RATINGS**|| |---|---| |**parameter**<br>**conditions/description**<br>**min**<br>**typ**<br>**max**<br>|**units**<br>| |operating temperature (see<br>thermal consideration section)<br>(TP1, TP2)<br>-40<br>125<br>|°C<br>| |storage temperature (TS)<br>-40<br>125<br>|°C<br>| |input voltage (see operating in-<br>formation section for input and<br>output voltage relations)(VI)<br>-0.3<br>16<br>|V<br>| |logic I/O voltage<br>CTRL, SA0, SA1, SALERT, SCL, SDA, VSET, SYNC,<br>DDC, PG<br>-0.3<br>6.5<br>|V<br>| |ground voltage differential<br>-S, PREF, GND<br>-0.3<br>0.3<br>|V<br>| |analog pin voltage<br>VO, +S, VTRK<br>-0.3<br>6.5<br>|V<br>| |Notes:<br>Stress in excess of Absolute Maximum Ratings may cause permanent damage. Absolute Maximum Ratings, sometimes referred to as no destruction limits, are<br>normally tested with one parameter at a time exceeding the limits in the Electrical Speci cation. If exposed to stress above these limits, function and performance<br>may degrade in an unspeci ed manner.<br>**Conf guration File**<br>This product is designed with a digital control circuit. The control circuit uses a con guration le which determines the<br>functionality and performance of the product. The Electrical Speci cation table shows parameter values of functionality<br>and performance with the default con guration le, unless otherwise speci ed. The default con guration le is designed<br>to t most application needs with focus on high ef ciency. If different characteristics are required it is possible to change<br>the con guration le to optimize certain performance characteristics. Note that current sharing operation requires changed<br>con guration le.<br>**PRODUCT ELECTRICAL SPECIFICATION, HORIZONTAL**<br>TP1= -30 to +95 °C, VI= 4.5 to 14 V, VI> VO+ 1.0 V<br>Typical values given at: TP1= +25 °C, VI= 12.0 V, max IO, unless otherwise speci ed under conditions.<br>External CIN= 470 �F/10 m�, COUT= 470 �F/10 m�. See Operating Information section for selection of capacitor types.<br>Sense pins are connected to the output pins.<br>NTIN|| |**parameter**<br>**conditions/description**<br>**min**<br>**typ**<br>**max**<br>**units**<br>|| |input voltage rise time (VI)<br>monotonic<br>2.4<br>V/ms<br>|| |output voltage without<br>pin-strap (VO)<br>1.2<br>V<br>|| |output voltage adjustment<br>range (VO)<br>0.60<br>3.3<br>V<br>|| |output voltage adjustment<br>including margining (VO)<br>see note 17<br>0.54<br>3.63<br>V<br>|| |output voltage set-point<br>resolution (VO)<br>±0.025<br>%FS<br>|| |output voltage accuracy (VO)<br>including line, load, temp see note 14<br>-1<br>1<br>%<br>current sharing operation see note 15<br>-2<br>2<br>%<br>|| |internal resistance +S/-S to<br>VOUT/GND (VO)<br>47<br>�<br>|| |line regulation (VO)<br>VO= 0.6 V<br>VO= 1.0 V<br>VO= 1.8 V<br>VO= 3.3 V<br>2<br>2<br>2<br>3<br>mV<br>mV<br>mV<br>mV<br>|| |load regulation (VO)<br>IO= 0~100%<br>VO= 0.6 V<br>VO= 1.0 V<br>VO= 1.8 V<br>VO= 3.3 V<br>2<br>2<br>2<br>2<br>mV<br>mV<br>mV<br>mV<br>|| |output ripple & noise (Voac)<br>CO= 470 �F (minimum external<br>capacitance) see note 11<br>VO= 0.6 V<br>VO= 1.0 V<br>VO= 1.8 V<br>VO= 3.3 V<br>20<br>25<br>30<br>35<br>mVp-p<br>mVp-p<br>mVp-p<br>mVp-p|| **cui** .com Additional Resources: Product Page | 3D Model **CUI Inc � SERIES** : NDM2Z-50 **� DESCRIPTION** : AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER **date** 12/21/2015 **� page** 3 of 32 |**PRODUCT ELECTRICAL SPECIFICATION, HORIZONTAL (CONTINUED)**|| |---|---| |**parameter**<br>**conditions/description**<br>**min**<br>**typ**<br>|**max**<br>**units**<br>| |output current (IO)<br>see note 18<br>0.001<br>|50<br>A<br>| |static input current at max IO<br>(IS)<br>VO= 0.6 V<br>VO= 1.0 V<br>VO= 1.8 V<br>VO= 3.3 V<br>3.10<br>4.80<br>8.19<br>14.53<br>|A<br>A<br>A<br>A<br>| |current limit threshold (Ilim)<br>52<br>|65<br>A<br>| |short circuit current(ISC)<br>RMS, hiccup mode,<br>see note 3<br>VO= 0.6 V<br>VO= 1.0 V<br>VO= 1.8 V<br>VO= 3.3 V<br>11<br>9<br>7<br>6<br>|A<br>A<br>A<br>A<br>| |ef ciency (�)<br>50% of max IO<br>VO= 0.6 V<br>VO= 1.0 V<br>VO= 1.8 V<br>VO= 3.3 V<br>85.6<br>90.4<br>93.7<br>95.7<br>max IO<br>VO= 0.6 V<br>VO= 1.0 V<br>VO= 1.8 V<br>VO= 3.3 V<br>80.5<br>86.9<br>91.6<br>94.6<br>NU|%<br>%<br>%<br>%<br>| ||%<br>%<br>%<br>%<br>| |power dissipation at max IO(Pd)<br>VO= 0.6 V<br>VO= 1.0 V<br>VO= 1.8 V<br>VO= 3.3 V<br>7.25<br>7.54<br>8.28<br>9.36<br>I|W<br>W<br>W<br>W<br>| |input idling power (no load)(Pli)<br>default con guration:<br>continues conduction<br>mode, CCM<br>VO= 0.6 V<br>VO= 1.0 V<br>VO= 1.8 V<br>VO= 3.3 V<br>0.90<br>0.90<br>1.10<br>1.67<br>|W<br>W<br>W<br>W<br>| |input standby power (PCTRL)<br>turned off with CTRL-pin<br>default con guration:<br>monitoring enabled,<br>precise timing enabled<br>170<br>|mW<br>| |internal input capacitance (Ci)<br>140<br>|�F<br>| |internal output capacitance (Co)<br>400<br>|�F<br>| |total external output<br>capacitance (COUT)<br>see note 9<br>470<br>|30,000<br>�F<br>| |ESR range of capacitors<br>(per single capacitor) (COUT)<br>see note 9<br>5<br>|30<br>m�<br>| |load transient peak voltage<br>deviation (L to H/H to L) load<br>step 25-75-25% of max IO(Vtr1)<br>default con guration<br>di/dt = 2 A/�s CO= 470<br>�F (minimum external<br>capacitance)<br>see note 12<br>VO= 0.6 V<br>VO= 1.0 V<br>VO= 1.8 V<br>VO= 3.3 V<br>79/256<br>127/298<br>144/324<br>210/327<br>S|mV<br>mV<br>mV<br>mV<br>| |load transient recovery time<br>note 5 (L to H/H to L) load step<br>25-75-25% of max IO(ttr1)<br>default con guration<br>di/dt = 2 A/�s CO= 470<br>�F (minimum external<br>capacitance)<br>see note 12<br>VO= 0.6 V<br>VO= 1.0 V<br>VO= 1.8 V<br>VO= 3.3 V<br>60/100<br>100/100<br>100/100<br>100/100<br>I|�s<br>�s<br>�s<br>�s<br>| |switching frequency (fs)<br>320<br>|kHz<br>| |switching frequency range (fs)<br>PMBus con gurable<br>200-640<br>|kHz<br>| |switching frequency set-point<br>accuracy (fs)<br>-5<br>|5<br>%<br>| |control circuit PWM duty cycle<br>5|95<br>%| |minimum sync pulse width<br>150|ns| |input clock frequency drift<br>tolerance<br>external clock source<br>-13|13<br>%| **cui** .com Additional Resources: Product Page | 3D Model **CUI Inc � SERIES** : NDM2Z-50 **� DESCRIPTION** : AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER **date** 12/21/2015 **� page** 4 of 32 |**PRODUCT ELECTRICAL**|**SPECIFICATION, HORIZONTAL (CONTINUED)**||| |---|---|---|---| |**parameter**<br>|**conditions/description**<br>**min**<br>**typ**<br>|**max**<br>|**units**<br>| |input under voltage lockout,<br>UVLO<br>|UVLO threshold<br>3.85<br>||V<br>| ||UVLO threshold range<br>PMBus con gurable<br>3.85-14<br>||V<br>| ||set point accuracy<br>-150<br>|150<br>|mV<br>| ||UVLO hysteresis<br>0.35<br>||V<br>| ||UVLO hysteresis range<br>PMBus con gurable<br>0-10.15<br>||V<br>| ||delay<br>2.5<br>||�s<br>| ||fault response<br>see note 3<br>automatic restart, 70 ms<br>||| |input over voltage protection,<br>IOVP<br>|IOVP threshold<br>16<br>||V<br>| ||IOVP threshold range<br>PMBus con gurable<br>4.2-16<br>||V<br>| ||set point accuracy<br>-150<br>|150<br>|mV<br>| ||IOVP hysteresis<br>1<br>||V<br>| ||IOVP hysteresis range<br>PMBus con gurable<br>0-11.8<br>||V<br>| ||delay<br>2.5<br>||�s<br>| ||fault response<br>see note 3<br>automatic restart, 70 ms<br>||| |power good, PG, see note 2<br>|PG threshold<br>90<br>||%Vo<br>| ||PG hysteresis<br>5<br>||%Vo<br>| ||PG delay<br>see note 19<br>direct after DLC<br>||ms<br>| ||PG delay range<br>PMBus con gurable<br>0-500<br>||s<br>| |output voltage over/under<br>voltage protection, OVP/UVP<br>|UVP threshold<br>85<br>||%Vo<br>| ||UVP threshold range<br>PMBus con gurable<br>0-100<br>||%Vo<br>| ||UVP hysteresis<br>5<br>||%Vo<br>| ||OVP threshold<br>115<br>||%Vo<br>| ||OVP threshold range<br>PMBus con gurable<br>100-115<br>||%Vo<br>| ||UVP/OVP response time<br>25<br>||�s<br>| ||UVP/OVP<br>response time range<br>PMBus con gurable<br>5-60<br>||�s<br>| ||fault response<br>see note 3<br>automatic restart, 70 ms<br>||| |over current protection, OCP<br>|OCP threshold<br>62<br>||A<br>| ||OCP threshold range<br>PMBus con gurable<br>0-62<br>||A<br>| ||protection delay<br>see note 4<br>32<br>||TSW<br>| ||protection delay range<br>PMBus con gurable<br>1-32<br>||TSW<br>| ||fault response<br>see note 3<br>automatic restart, 70 ms<br>||| |over temperature protection,<br>OTP at P2 see note 8<br>DI|OTP threshold<br>120<br>||°C<br>| ||OTP threshold range<br>PMBus con gurable<br>-40<br>125<br>||°C<br>| ||OTP hysteresis<br>25<br>||°C<br>| ||OTP hysteresis range<br>PMBus con gurable<br>0-165<br>||°C<br>| ||fault response<br>see note 3<br>automatic restart, 240 ms<br>||<br>| ||||| ||**cui**.com||| Additional Resources: Product Page | 3D Model **CUI Inc � SERIES** : NDM2Z-50 **� DESCRIPTION** : AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER **date** 12/21/2015 **� page** 5 of 32 |**PRODUCT ELECTRICAL**|**SPECIFICATION, HORIZONTAL (CONTINUED)**|**SPECIFICATION, HORIZONTAL (CONTINUED)**|**SPECIFICATION, HORIZONTAL (CONTINUED)**||| |---|---|---|---|---|---| |**parameter**<br>|**conditions/description**<br>**min**<br>**typ**<br>|||**max**<br>|**units**<br>| |logic input low threshold(VIL)<br>|SYNC, SA0, SA1, SCL, SDA, DDC, CTRL, VSET<br>|||0.8<br>|V<br>| |logic input high threshold (VIH)<br>|||2<br>||V<br>| |logic input low sink current(IIL)<br>|CTRL<br>|||0.6<br>|mA<br>| |logic output low signal level<br>(VOL)<br>|SYNC, SCL, SDA, SALERT, DDC, PG<br>|||0.4<br>|V<br>| |logic output high signal level<br>(VOH)<br>|||2.25<br>||V<br>| |logic output low sink current<br>(IOL)<br>||||4<br>|mA<br>| |logic output high source current<br>(IOH)<br>||||2<br>|mA<br>| |setup time, SMBus(tSET)<br>|see note 1<br>|300<br>|||ns<br>| |hold time, SMBus(thold)<br>|see note 1<br>|250<br>|||ns<br>| |bus free time, SMBus(tfree)<br>|see note 1<br>|2<br>|||ms<br>| |internal capacitance on logic<br>pins (CP)<br>||10<br>|||pF<br>| |initialization time<br>||see note 10<br>40<br>|||ms<br>| |output voltage delay time see<br>note 6<br>|delay duration<br>|see note 16<br>10<br>|||ms<br>| ||delay duration range<br>|PMBus con gurable<br>5-500,000<br>|||ms<br>| ||delay accuracy turn-on<br>|-0.25/+4<br>|||ms<br>| ||delay accuracy turn-off<br>|-0.25/+4<br>|||ms<br>| |output voltage ramp time<br>see note 13<br>|ramp duration<br>|10<br>|||ms<br>| ||ramp duration range<br>|PMBus con gurable<br>0-200<br>|||ms<br>| ||ramp time accuracy<br>|100<br>|||�s<br>| |||current sharing<br>operation<br>20<br>|||%<br>| |VTRK input bias current<br>|VVTRK= 5.5 V<br>|110<br>||200<br>|�A<br>| |VTRK tracking ramp accuracy<br>(VO- VVTRK)<br>|100% tracking, see note<br>|7<br>-100<br>||100<br>|mV<br>| ||current sharing operation<br>2 phases, 100% tracking<br>VO= 1.0 V, 10 ms ramp<br>±100<br>||||mV<br>| |VTRK regulation accuracy<br>(VO- VVTRK)<br>|100% Tracking<br>-1<br>|||1<br>|%<br>| ||current sharing operation<br>100% Tracking<br>-2<br>|||2<br>|%<br>| |current difference between<br>products in a current<br>sharing group<br>I|steady state operation<br>Max 2 x READ_IOUT monitoring<br>accuracy<br>||||| ||ramp-up<br>4<br>||||A<br>| |number of products in a current<br>sharing group<br>|7<br>||||| |monitoring accuracy<br>|READ_VIN vs VI<br>3<br>||||%<br>| ||READ_VOUT vs VO<br>1<br>||||%<br>| ||READ_IOUT vs IO<br>IO= 0-50 A, TP1= 0 to +95 °C<br>VI= 4.5-14 V, VO= 1.0 V<br>±3<br>||||A<br>| ||READ_IOUT vs IO<br>IO= 0-50 A, TP1= 0 to +95 °C<br>VI= 4.5-14 V, VO= 0.6-3.3 V<br>±5||||A| **cui** .com Additional Resources: Product Page | 3D Model **CUI Inc � SERIES** : NDM2Z-50 **� DESCRIPTION** : AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER **date** 12/21/2015 **� page** 6 of 32 ## **PRODUCT ELECTRICAL SPECIFICATION, HORIZONTAL (CONTINUED)** - Notes: 1: See section I[2] C/SMBus Setup and Hold Times – De nitions. 2: Monitorable over PMBus Interface. 3: Automatic restart ~70 or 240 ms after fault if the fault is no longer present. Continuous restart attempts if the fault reappear after restart. 4: T 5: Within +/-3% of VOsw is the switching period. 6: See section Soft-start Power Up. 7: Tracking functionality is designed to follow a VTRK signal with slew rate < 2.4 V/ms. For faster VTRK signals accuracy will depend on the regulator bandwidth. 8: See section Over Temperature Protection (OTP). 9: See section External Capacitors. 10: See section Initialization Procedure. 11: See graph Output Ripple vs External Capacitance and Operating information section Output Ripple and Noise. 12: See graph Load Transient vs. External Capacitance and Operating information section External Capacitors. 13: Time for reaching 100% of nominal Vout. 14: For Vout < 1.0 V accuracy is +/-10 mV. For further deviations see section Output Voltage Adjust using PMBus. 15: Accuracy here means deviation from ideal output voltage level given by con gured droop and actual load. Includes line, load and temperature variations. 16: For current sharing the Output Voltage Delay Time must be recon gured to minimum 15 ms. 17: For steady state operation above 1.05 x 3.3 V, please contact your local CUI sales representative. 18: A minimum load current is not required if Low Power mode is used (monitoring disabled). 19: See sections Dynamic Loop Compensation and Power Good. **cui** .com Additional Resources: Product Page | 3D Model **CUI Inc � SERIES** : NDM2Z-50 **� DESCRIPTION** : AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER **date** 12/21/2015 **� page** 7 of 32 **==> picture [564 x 655] intentionally omitted <==** **----- Start of picture text -----**<br> TYPICAL CHARACTERISTICS, HORIZONTAL<br>Efficiency vs. Output Current, VI = 5 V Power Dissipation vs. Output Current, VI = 5 V<br>[%] [W]<br>100 12<br>10<br>95<br>8<br>90 0.6 V 0.6 V<br>6<br>1.0 V 1.0 V<br>85<br>1.8 V 4 1.8 V<br>80 3.3 V 2 3.3 V<br>75 0<br>0 10 20 30 40 50 [A] 0 10 20 30 40 50 [A]<br>Efficiency vs. load current and output voltage: Dissipated power vs. load current and output voltage:<br>TP1 = +25 °C, VI = 5 V, fsw = 320 kHz, CO = 470 µF/10 mΩ. TP1 = +25 °C, VI = 5 V, fsw = 320 kHz, CO = 470 µF/10 mΩ.<br>Efficiency vs. Output Current, VI = 12 V Power Dissipation vs. Output Current, VI = 12 V<br>[%] [W]<br>100 12<br>10<br>95<br>8<br>90 0.6 V 0.6 V<br>6<br>1.0 V 1.0 V<br>85<br>1.8 V 4 1.8 V<br>80 3.3 V 2 3.3 V<br>75 0<br>0 10 20 30 40 50 [A] 0 10 20 30 40 50 [A]<br>Efficiency vs. load current and output voltage at Dissipated power vs. load current and output voltage:<br>TP1 = +25 °C, VI = 12 V, fsw = 320 kHz, CO = 470 µF/10 mΩ. TP1 = +25 °C, VI = 12 V, fsw = 320 kHz, CO = 470 µF/10 mΩ.<br>Efficiency vs. Output Current and Power Dissipation vs. Output Current and<br>Switching Frequency Switching frequency<br>[%] [W]<br>95 12<br>10<br>90<br>200 200<br>kHz 8 kHz<br>85 320 320<br>kHz 6 kHz<br>80 480 480<br>kHz 4 kHz<br>640 640<br>75 kHz 2 kHz<br>70 0<br>0 10 20 30 40 50 [A] 0 10 20 30 40 50 [A]<br>Efficiency vs. load current and switch frequency at Dissipated power vs. load current and switch frequency at<br>TP1 = +25 °C, VI = 12 V, VO = 1.0 V, CO = 470 µF/10 mΩ. TP1 = +25 °C, VI = 12 V, VO = 1.0 V, CO = 470 µF/10 mΩ.<br>Default configuration except changed frequency Default configuration except changed frequency<br>DISCONTINUED<br>**----- End of picture text -----**<br> **cui** .com Additional Resources: Product Page | 3D Model **CUI Inc � SERIES** : NDM2Z-50 **� DESCRIPTION** : AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER **date** 12/21/2015 **� page** 8 of 32 **==> picture [564 x 681] intentionally omitted <==** **----- Start of picture text -----**<br> TYPICAL CHARACTERISTICS, HORIZONTAL (CONTINUED)<br>Load Transient vs. External Capacitance, VO = 1.0 V Load Transient vs. External Capacitance, VO = 3.3 V<br>[mV] [mV]<br>500 500<br>Universal PID, Universal PID,<br>No NLR No NLR<br>400 DLC, 400 DLC,<br>No NLR No NLR<br>300 Universal PID, 300 Universal PID,<br>Default NLR Default NLR<br>200 DLC,Default NLR 200 DLC,Default NLR<br>Universal PID, Universal PID,<br>100 Opt. NLR 100 Opt. NLR<br>DLC, DLC,<br>0 Opt. NLR 0 Opt. NLR<br>0 1 2 3 4 5 0 1 2 3 4 5 [mF]<br>[mF]<br>Load transient peak voltage deviation vs. external capacitance. Load transient peak voltage deviation vs. external capacitance.<br>Step (12.5-37.5-12.5 A). Parallel coupling of capacitors with 470 µF/10 mΩ, Step (12.5-37.5-12.5 A). Parallel coupling of capacitors with 470 µF/10 mΩ,<br>TP1 = +25 °C, VI = 12 V, VO = 1.0 V, fsw = 320 kHz, di/dt = 2 A/µs TP1 = +25 °C, VI = 12 V, VO = 3.3 V, fsw = 320 kHz, di/dt = 2 A/µs<br>Load transient vs. Switch Frequency<br>[mV]<br>600<br>Universal PID,<br>No NLR<br>500<br>DLC,<br>No NLR<br>400<br>Universal PID,<br>Default NLR<br>300<br>DLC,<br>Default NLR<br>200<br>Universal PID,<br>100 Opt. NLR<br>DLC,<br>0 Opt. NLR<br>200 300 400 500 600 [kHz]<br>Load transient peak voltage deviation vs. frequency.<br>Step-change (12.5-37.5-12.5 A).<br>TP1 = +25 °C. VI = 12 V, VO = 1.0 V, CO = 470 µF/10 mΩ<br>Note 1: For Universal PID, see section Dynamic Loop Compensation (DLC).<br>Note 2: In the load transient graphs, the worst-case scenario (load step 37.5-12.5 A) has been<br>considered.<br>cui .com<br>DISCONTINUED<br>**----- End of picture text -----**<br> Additional Resources: Product Page | 3D Model **CUI Inc � SERIES** : NDM2Z-50 **� DESCRIPTION** : AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER **date** 12/21/2015 **� page** 9 of 32 **==> picture [564 x 630] intentionally omitted <==** **----- Start of picture text -----**<br> TYPICAL CHARACTERISTICS, HORIZONTAL (CONTINUED)<br>Output Current Derating, VO = 0.6 V Output Current Derating, VO = 1.0 V<br>[A] [A]<br>50 50<br>3.0 m/s 3.0 m/s<br>40 40<br>2.0 m/s 2.0 m/s<br>30 1.0 m/s 30 1.0 m/s<br>20 0.5 m/s 20 0.5 m/s<br>Nat. Conv. Nat. Conv.<br>10 10<br>0 0<br>20 40 60 80 100 120 [°C] 20 40 60 80 100 120 [°C]<br>Available load current vs. ambient air temperature and airflow at Available load current vs. ambient air temperature and airflow at<br>VO = 0.6 V, VI = 12 V. See Thermal Consideration section. VO = 1.0 V, VI = 12 V. See Thermal Consideration section.<br>Output Current Derating, VO = 1.8 V Output Current Derating, VO = 3.3 V<br>[A] [A]<br>50 50<br>3.0 m/s 3.0 m/s<br>40 40<br>2.0 m/s 2.0 m/s<br>30 1.0 m/s 30 1.0 m/s<br>20 0.5 m/s 20 0.5 m/s<br>10 Nat. Conv. 10 Nat. Conv.<br>0 0<br>20 40 60 80 100 120 [°C] 20 40 60 80 100 120 [°C]<br>Available load current vs. ambient air temperature and airflow at Available load current vs. ambient air temperature and airflow at<br>VO = 1.8 V, VI = 12 V. See Thermal Consideration section. VO = 3.3 V, VI = 12 V. See Thermal Consideration section.<br>Current Limit Characteristics, VO = 1.0 V Current Limit Characteristics, VO = 3.3 V<br>[V] [V]<br>1,2 4,0<br>VI = 5.0, 12 V VI = 4.5, 5 .0V<br>0,9 3,0<br>4.5 V<br>4.5 V<br>5.0 V<br>0,6 5.0 V 2,0<br>12 V<br>VI = 4.5,14 V 12 V VI = 12, 14 V<br>14 V<br>0,3 14 V 1,0<br>0,0 0,0<br>50 55 60 65 [A] 50 55 60 65 [A]<br>Output voltage vs. load current at TP1 = +25 °C, VO = 1.0 V. Output voltage vs. load current at TP1 = +25 °C, VO = 3.3 V.<br>Note: Output enters hiccup mode at current limit. Note: Output enters hiccup mode at current limit.<br>DISCONTINUED<br>**----- End of picture text -----**<br> **cui** .com Additional Resources: Product Page | 3D Model **CUI Inc � SERIES** : NDM2Z-50 **� DESCRIPTION** : AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER **date** 12/21/2015 **� page** 10 of 32 **==> picture [564 x 681] intentionally omitted <==** **----- Start of picture text -----**<br> TYPICAL CHARACTERISTICS, HORIZONTAL (CONTINUED)<br>Output Ripple vs. Input Voltage Output Ripple vs. Frequency<br>[mVpk-pk] [mVpk-pk]<br>40 70<br>60<br>30<br>50 0.6 V<br>0.6 V<br>1.0 V 40 1.0 V<br>20<br>1.8 V<br>1.8 V 30<br>3.3 V<br>3.3 V 20<br>10<br>10<br>0 0<br>5 7 9 11 13 [V] 200 300 400 500 600 [kHz]<br>Output voltage ripple Vpk-pk at: TP1 = +25 °C, CO = 470 µF/10 mΩ, IO = 50 A Output voltage ripple Vpk-pk at: TP1 = +25 °C, VI = 12 V, CO = 470 µF/10 mΩ,<br>IO = 50 A. Default configuration except changed frequency.<br>Output Ripple vs. External Capacitance Load regulation, VO = 1.0 V<br>[mV] [V]<br>40 1,010<br>30 0.6 V 1,005<br>4.5 V<br>1.0 V 5.0 V<br>20 1,000<br>1.8 V 12 V<br>14 V<br>10 3.3 V 0,995<br>0 0,990<br>0 1 2 3 4 5 [mF] 0 5 10 15 20 25 [A]<br>Output voltage ripple Vpk-pk at: TP1 = +25 °C, VI = 12 V. IO = 50 A. Load regulation at VO = 1.0 V, TP1 = +25 °C, CO = 470 µF/10 mΩ<br>Parallel coupling of capacitors with 470 µF/10 mΩ<br>cui .com<br>DISCONTINUED<br>**----- End of picture text -----**<br> Additional Resources: Product Page | 3D Model **date** 12/21/2015 **page** 11 of 32 **CUI Inc SERIES** : NDM2Z-50 **DESCRIPTION** : AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER **date** 12/21/2015 **page** 11 of 32 **TYPICAL CHARACTERISTICS, HORIZONTAL (CONTINUED) Start-up by input source Shut-down by input source** Start-up enabled by connecting VI at: Top trace: output voltage (0.5 V/div.). Shut-down enabled by disconnecting Top trace: output voltage (0.5 V/div.). TP1 = +25 °C, V HHEEEEEEEe| I = 12 V, VO = 1.0 V Bottom trace: input voltage (5 V/div.). | VI at: EEEeSee Bottom trace: input voltage (5 V/div.). CO = 470 µF/10 mΩ, IO = 50 A Time scale: (20 ms/div.). TP1 = +25 °C, VI = 12 V, VO = 1.0 V Time scale: (2 ms/div.). CO = 470 µF/10 mΩ, IO = 50 A ~~OB~~ **Start-up by CTRL signal Shut-down by CTRL signal** Start-up by enabling CTRL signal at: Top trace: output voltage (0.5 V/div.). Shut-down enabled by disconnecting Top trace: output voltage (0.5 V/div). TP1 = +25 °C, V poe I = 12 V, VO = 1.0 V Bottom trace: CTRL signal (2 V/div.). | VI at: Ee Bottom trace: CTRL signal (2 V/div.). CO = 470 µF/10 mΩ, IO = 50 A Time scale: (20 ms/div.). TP1 = +25 °C, VI = 12 V, VO = 1.0 V Time scale: (2 ms/div.). CO = 470 µF/10 mΩ, IO = 50 A **cui** .com Additional Resources: Product Page | 3D Model **CUI Inc � SERIES** : NDM2Z-50 **� DESCRIPTION** : AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER **date** 12/21/2015 **� page** 12 of 32 |**PRODUCT ELECTRICAL SPECIFICATION, VERTICAL**<br>TP1= -30 to +95 °C, VI= 4.5 to 14 V, VI> VO+ 1.0 V<br>Typical values given at: TP1= +25 °C, VI= 12.0 V, max IO, unless otherwise speci ed under conditions.<br>External CIN= 470 �F/10 m�, COUT= 470 �F/10 m�. See Operating Information section for selection of capacitor types.<br>Sense pins are connected to the output pins.<br>|**PRODUCT ELECTRICAL SPECIFICATION, VERTICAL**<br>TP1= -30 to +95 °C, VI= 4.5 to 14 V, VI> VO+ 1.0 V<br>Typical values given at: TP1= +25 °C, VI= 12.0 V, max IO, unless otherwise speci ed under conditions.<br>External CIN= 470 �F/10 m�, COUT= 470 �F/10 m�. See Operating Information section for selection of capacitor types.<br>Sense pins are connected to the output pins.<br>| |---|---| |**parameter**<br>**conditions/description**<br>**min**<br>**typ**<br>|**max**<br>**units**<br>| |input voltage rise time (VI)<br>monotonic<br>|2.4<br>V/ms<br>| |output voltage without<br>pin-strap (VO)<br>1.2<br>|V<br>| |output voltage adjustment<br>range (VO)<br>0.60<br>|3.3<br>V<br>| |output voltage adjustment<br>including margining (VO)<br>see note 17<br>0.54<br>|3.63<br>V<br>| |output voltage set-point<br>resolution (VO)<br>±0.025<br>|%FS<br>| |output voltage accuracy (VO)<br>including line, load, temp see note 14<br>-1<br>current sharing operation see note 15<br>-2<br>|1<br>%<br>| ||2<br>%<br>| |internal resistance +S/-S to<br>VOUT/GND (VO)<br>47<br>|�<br>| |line regulation (VO)<br>VO= 0.6 V<br>VO= 1.0 V<br>VO= 1.8 V<br>VO= 3.3 V<br>2<br>3<br>3<br>3<br>I|mV<br>mV<br>mV<br>mV<br>| |load regulation (VO)<br>IO= 0~100%<br>VO= 0.6 V<br>VO= 1.0 V<br>VO= 1.8 V<br>VO= 3.3 V<br>2<br>2<br>2<br>2<br>|mV<br>mV<br>mV<br>mV<br>| |output ripple & noise (Voac)<br>CO= 470 �F (minimum external<br>capacitance) see note 11<br>VO= 0.6 V<br>VO= 1.0 V<br>VO= 1.8 V<br>VO= 3.3 V<br>20<br>25<br>30<br>40<br>|mVp-p<br>mVp-p<br>mVp-p<br>mVp-p<br>| |output current (IO)<br>see note 18<br>0.001<br>|50<br>A<br>| |static input current at max IO<br>(IS)<br>VO= 0.6 V<br>VO= 1.0 V<br>VO= 1.8 V<br>VO= 3.3 V<br>3.12<br>4.81<br>8.22<br>14.59<br>|A<br>A<br>A<br>A<br>| |current limit threshold (Ilim)<br>52<br>|65<br>A<br>| |short circuit current(ISC)<br>RMS, hiccup mode,<br>see note 3<br>VO= 0.6 V<br>VO= 1.0 V<br>VO= 1.8 V<br>VO= 3.3 V<br>10<br>8<br>6<br>5<br>|A<br>A<br>A<br>A<br>| |ef ciency (�)<br>50% of max IO<br>VO= 0.6 V<br>VO= 1.0 V<br>VO= 1.8 V<br>VO= 3.3 V<br>85.2<br>90.2<br>93.3<br>95.3<br>max IO<br>VO= 0.6 V<br>VO= 1.0 V<br>VO= 1.8 V<br>VO= 3.3 V<br>80.2<br>86.6<br>91.2<br>94.2<br>DI|%<br>%<br>%<br>%<br>| ||%<br>%<br>%<br>%<br>| |power dissipation at max IO(Pd)<br>VO= 0.6 V<br>VO= 1.0 V<br>VO= 1.8 V<br>VO= 3.3 V<br>7.4<br>7.73<br>8.68<br>10.15<br>|W<br>W<br>W<br>W<br>| |input idling power (no load)(Pli)<br>default con guration:<br>continues conduction<br>mode, CCM<br>VO= 0.6 V<br>VO= 1.0 V<br>VO= 1.8 V<br>VO= 3.3 V<br>0.95<br>0.95<br>1.22<br>1.88|W<br>W<br>W<br>W| **cui** .com Additional Resources: Product Page | 3D Model **CUI Inc � SERIES** : NDM2Z-50 **� DESCRIPTION** : AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER **date** 12/21/2015 **� page** 13 of 32 |**PRODUCT ELECTRICAL**|**SPECIFICATION, VERTICAL (CONTINUED)**||| |---|---|---|---| |input standby power (PCTRL)<br>|turned off with CTRL-pin<br>default con guration:<br>monitoring enabled,<br>precise timing enabled<br>170<br>||mW<br>| |internal input capacitance (Ci)<br>|140<br>||�F<br>| |internal output capacitance (Co)<br>|400<br>||�F<br>| |total external output<br>capacitance (COUT)<br>|see note 9<br>470<br>|30,000<br>|�F<br>| |ESR range of capacitors<br>(per single capacitor) (COUT)<br>|see note 9<br>5<br>|30<br>|m�<br>| |load transient peak voltage<br>deviation (L to H/H to L) load<br>step 25-75-25% of max IO(Vtr1)<br>|default con guration<br>di/dt = 2 A/�s CO= 470<br>�F (minimum external<br>capacitance)<br>see note 12<br>VO= 0.6 V<br>VO= 1.0 V<br>VO= 1.8 V<br>VO= 3.3 V<br>90/300<br>120/300<br>160/305<br>230/315<br>||mV<br>mV<br>mV<br>mV<br>| |load transient recovery time<br>note 5 (L to H/H to L) load step<br>25-75-25% of max IO(ttr1)<br>|default con guration<br>di/dt = 2 A/�s CO= 470<br>�F (minimum external<br>capacitance)<br>see note 12<br>VO= 0.6 V<br>VO= 1.0 V<br>VO= 1.8 V<br>VO= 3.3 V<br>70/100<br>100/100<br>100/100<br>100/100<br>N||�s<br>�s<br>�s<br>�s<br>| |switching frequency (fs)<br>|320<br>||kHz<br>| |switching frequency range (fs)<br>|PMBus con gurable<br>200-640<br>||kHz<br>| |switching frequency set-point<br>accuracy (fs)<br>|-5<br>|5<br>|%<br>| |control circuit PWM duty cycle<br>|5<br>|95<br>|%<br>| |minimum sync pulse width<br>|150<br>||ns<br>| |input clock frequency drift<br>tolerance<br>|external clock source<br>-13<br>|13<br>|%<br>| |input under voltage lockout,<br>UVLO<br>|UVLO threshold<br>3.85<br>||V<br>| ||UVLO threshold range<br>PMBus con gurable<br>3.85-14<br>||V<br>| ||set point accuracy<br>-150<br>|150<br>|mV<br>| ||UVLO hysteresis<br>0.35<br>||V<br>| ||UVLO hysteresis range<br>PMBus con gurable<br>0-10.15<br>||V<br>| ||delay<br>2.5<br>||�s<br>| ||fault response<br>see note 3<br>automatic restart, 70 ms<br>||| |input over voltage protection,<br>IOVP<br>DIS|IOVP threshold<br>16<br>||V<br>| ||IOVP threshold range<br>PMBus con gurable<br>4.2-16<br>||V<br>| ||set point accuracy<br>-150<br>|150<br>|mV<br>| ||IOVP hysteresis<br>1<br>||V<br>| ||IOVP hysteresis range<br>PMBus con gurable<br>0-11.8<br>||V<br>| ||delay<br>2.5<br>||�s<br>| ||fault response<br>see note 3<br>automatic restart, 70 ms<br>||| |power good, PG, see note 2<br>|PG threshold<br>90<br>||%Vo<br>| ||PG hysteresis<br>5<br>||%Vo<br>| ||PG delay<br>see note 19<br>direct after DLC<br>||ms<br>| ||PG delay range<br>PMBus con gurable<br>0-500<br>||s<br>| **cui** .com Additional Resources: Product Page | 3D Model **CUI Inc � SERIES** : NDM2Z-50 **� DESCRIPTION** : AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER **date** 12/21/2015 **� page** 14 of 32 |**PRODUCT ELECTRICAL**|**SPECIFICATION, VERTICAL (CONTINUED)**|**SPECIFICATION, VERTICAL (CONTINUED)**|**SPECIFICATION, VERTICAL (CONTINUED)**|**SPECIFICATION, VERTICAL (CONTINUED)**|| |---|---|---|---|---|---| |**parameter**<br>|**conditions/description**<br>||**min**<br>**typ**<br>**max**<br>||**units**<br>| |output voltage over/under<br>voltage protection, OVP/UVP<br>|UVP threshold<br>||85<br>||%Vo<br>| ||UVP threshold range<br>PMBus con gurable<br>||0-100<br>||%Vo<br>| ||UVP hysteresis<br>||5<br>||%Vo<br>| ||OVP threshold<br>||115<br>||%Vo<br>| ||OVP threshold range<br>PMBus con gurable<br>||100-115<br>||%Vo<br>| ||UVP/OVP response time<br>||25<br>||�s<br>| ||UVP/OVP<br>response time range<br>PMBus con gurable<br>||5-60<br>||�s<br>| ||fault response<br>see note 3<br>||automatic restart, 70 ms<br>||| |over current protection, OCP<br>|OCP threshold<br>||60<br>||A<br>| ||OCP threshold range<br>PMBus con gurable<br>||0-60<br>||A<br>| ||protection delay<br>see note 4<br>||32<br>||TSW<br>| ||protection delay range<br>PMBus con gurable<br>||1-32<br>||TSW<br>| ||fault response<br>see note 3<br>||automatic restart, 70 ms<br>||| |over temperature protection,<br>OTP at P2 see note 8<br>|OTP threshold<br>||120<br>||°C<br>| ||OTP threshold range<br>PMBus con gurable<br>||-40<br>125<br>||°C<br>| ||OTP hysteresis<br>||25<br>||°C<br>| ||OTP hysteresis range<br>PMBus con gurable<br>||0-165<br>||°C<br>| ||fault response<br>see note 3<br>||automatic restart, 240 ms<br>||<br>| |logic input low threshold(VIL)<br>|SYNC, SA0, SA1, SCL, SDA, DDC, CTRL, VSET<br>|||0.8<br>|V<br>| |logic input high threshold (VIH)<br>|||2<br>||V<br>| |logic input low sink current(IIL)<br>|CTRL<br>|||0.6<br>|mA<br>| |logic output low signal level<br>(VOL)<br>|SYNC, SCL, SDA, SALERT, DDC, PG<br>O|||0.4<br>|V<br>| |logic output high signal level<br>(VOH)<br>|||2.25<br>||V<br>| |logic output low sink current<br>(IOL)<br>||||4<br>|mA<br>| |logic output high source current<br>(IOH)<br>||||2<br>|mA<br>| |setup time, SMBus(tSET)<br>|see note 1<br>||300<br>||ns<br>| |hold time, SMBus(thold)<br>|see note 1<br>||250<br>||ns<br>| |bus free time, SMBus(tfree)<br>|see note 1<br>||2<br>||ms<br>| |internal capacitance on logic<br>pins (CP)<br>|||10<br>||pF<br>| |initialization time<br>|see note 10<br>||40<br>||ms<br>| |output voltage delay time see<br>note 6<br>D|delay duration<br>see note 16<br>||10<br>||ms<br>| ||delay duration range<br>PMBus con gurable<br>||5-500,000<br>||ms<br>| ||delay accuracy turn-on<br>||-0.25/+4<br>||ms<br>| ||delay accuracy turn-off<br>||-0.25/+4<br>||ms<br>| |output voltage ramp time<br>see note 13<br>|ramp duration<br>||10<br>||ms<br>| ||ramp duration range|PMBus con gurable|0-200||ms| ||ramp time accuracy||100||�s| |||current sharing<br>operation|20||%| |VTRK input bias current|VVTRK= 5.5 V||110|200|�A| **cui** .com Additional Resources: Product Page | 3D Model **CUI Inc � SERIES** : NDM2Z-50 **� DESCRIPTION** : AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER **date** 12/21/2015 **� page** 15 of 32 |**PRODUCT ELECTRICAL**|**SPECIFICATION, VERTICAL (CONTINUED)**|| |---|---|---| |**parameter**<br>|**conditions/description**<br>**min**<br>**typ**<br>**max**<br>|**units**<br>| |VTRK tracking ramp accuracy<br>(VO- VVTRK)<br>|100% tracking, see note 7<br>-100<br>100<br>|mV<br>| ||current sharing operation<br>2 phases, 100% tracking<br>VO= 1.0 V, 10 ms ramp<br>±100<br>|mV<br>| |VTRK regulation accuracy<br>(VO- VVTRK)<br>|100% Tracking<br>-1<br>1<br>|%<br>| ||current sharing operation<br>100% Tracking<br>-2<br>2<br>|%<br>| |current difference between<br>products in a current<br>sharing group<br>|steady state operation<br>Max 2 x READ_IOUT monitoring<br>accuracy<br>|| ||ramp-up<br>4<br>|A<br>| |number of products in a current<br>sharing group<br>|<br>7<br>|| |monitoring accuracy<br>|READ_VIN vs VI<br>3<br>|%<br>| ||READ_VOUT vs VO<br>1<br>|%<br>| ||READ_IOUT vs IO<br>IO= 0-50 A, TP1= 0 to +95 °C<br>VI= 4.5-14 V, VO= 1.0 V<br>±3<br>|A<br>| ||READ_IOUT vs IO<br>IO= 0-50 A, TP1= 0 to +95 °C<br>VI= 4.5-14 V, VO= 0.6-3.3 V<br>±5<br>|A<br>| |Notes:<br>1: See section I2C/SMBus Setup and Hold Times – De nitions.<br>2: Monitorable over PMBus Interface.<br>3: Automatic restart ~70 or 240 ms after fault if the fault is no longer present. Continuous restart attempts if the fault reappear after restart.<br>4: Tswis the switching period.<br>5: Within +/-3% of VO<br>6: See section Soft-start Power Up.<br>7: Tracking functionality is designed to follow a VTRK signal with slew rate < 2.4 V/ms. For faster VTRK signals accuracy will depend on the regulator band<br>8: See section Over Temperature Protection (OTP).<br>9: See section External Capacitors.<br>10: See section Initialization Procedure.<br>11: See graph Output Ripple vs External Capacitance and Operating information section Output Ripple and Noise.<br>12: See graph Load Transient vs. External Capacitance and Operating information section External Capacitors.<br>13: Time for reaching 100% of nominal Vout.<br>14: For Vout < 1.0 V accuracy is +/-10 mV. For further deviations see section Output Voltage Adjust using PMBus.<br>15: Accuracy here means deviation from ideal output voltage level given by con gured droop and actual load. Includes line, load and temperature variations<br>16: For current sharing the Output Voltage Delay Time must be recon gured to minimum 15 ms.<br>17: For steady state operation above 1.05 x 3.3 V, please contact your local CUI sales representative.<br>18: A minimum load current is not required if Low Power mode is used (monitoring disabled).<br>19: See sections Dynamic Loop Compensation and Power Good.<br>DISCONT||width.<br>.<br>| |**cui**.com||| Additional Resources: Product Page | 3D Model **==> picture [564 x 709] intentionally omitted <==** **----- Start of picture text -----**<br> CUI Inc � SERIES : NDM2Z-50 � DESCRIPTION : AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER date 12/21/2015 � page 16 of 32<br>TYPICAL CHARACTERISTICS, VERTICAL<br>Efficiency vs. Output Current, VI = 5 V Power Dissipation vs. Output Current, VI = 5 V<br>[%] [W]<br>100 12<br>10<br>95<br>8<br>90 0.6 V 0.6 V<br>6<br>1.0 V 1.0 V<br>85<br>1.8 V 4 1.8 V<br>80 3.3 V 2 3.3 V<br>75 0<br>0 10 20 30 40 50 [A] 0 10 20 30 40 50 [A]<br>Efficiency vs. load current and output voltage: Dissipated power vs. load current and output voltage:<br>TP1 = +25 °C, VI = 5 V, fsw = 320 kHz, CO = 470 µF/10 mΩ. TP1 = +25 °C, VI = 5 V, fsw = 320 kHz, CO = 470 µF/10 mΩ.<br>Efficiency vs. Output Current, VI = 12 V Power Dissipation vs. Output Current, VI = 12 V<br>[%] [W]<br>100 12<br>10<br>95<br>8<br>90 0.6 V 0.6 V<br>6<br>1.0 V 1.0 V<br>85<br>1.8 V 4 1.8 V<br>80 3.3 V 2 3.3 V<br>75 0<br>0 10 20 30 40 50 [A] 0 10 20 30 40 50 [A]<br>Efficiency vs. load current and output voltage at Dissipated power vs. load current and output voltage:<br>TP1 = +25 °C, VI=12 V, fsw = 320 kHz, CO = 470 µF/10 mΩ. TP1 = +25 °C, VI=12 V, fsw = 320 kHz, CO = 470 µF/10 mΩ.<br>Efficiency vs. Output Current and Power Dissipation vs. Output Current and<br>Switching Frequency Switching frequency<br>[%] [W]<br>95 12<br>10<br>90<br>200 200<br>kHz 8 kHz<br>85 320 320<br>kHz 6 kHz<br>80 480 480<br>kHz 4 kHz<br>640 640<br>75 kHz 2 kHz<br>70 0<br>0 10 20 30 40 50 [A] 0 10 20 30 40 50 [A]<br>Efficiency vs. load current and switch frequency at Dissipated power vs. load current and switch frequency at<br>TP1 = +25 °C, VI = 12 V, VO = 1.0 V, CO = 470 µF/10 mΩ. TP1 = +25 °C, VI = 12 V, VO = 1.0 V, CO = 470 µF/10 mΩ.<br>Default configuration except changed frequency Default configuration except changed frequency<br>DISCONTINUED<br>**----- End of picture text -----**<br> **cui** .com Additional Resources: Product Page | 3D Model **CUI Inc � SERIES** : NDM2Z-50 **� DESCRIPTION** : AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER **date** 12/21/2015 **� page** 17 of 32 **==> picture [564 x 681] intentionally omitted <==** **----- Start of picture text -----**<br> TYPICAL CHARACTERISTICS, VERTICAL (CONTINUED)<br>Load Transient vs. External Capacitance, VO = 1.0 V Load Transient vs. External Capacitance, VO = 3.3 V<br>[mV] [mV]<br>500 500<br>Universal PID, Universal PID,<br>No NLR No NLR<br>400 DLC, 400 DLC,<br>No NLR No NLR<br>300 Universal PID, 300 Universal PID,<br>Default NLR Default NLR<br>DLC, DLC,<br>200 200<br>Default NLR Default NLR<br>Universal PID, Universal PID,<br>100 Opt. NLR 100 Opt. NLR<br>DLC, DLC,<br>0 Opt. NLR 0 Opt. NLR<br>0 1 2 3 4 5 [mF] 0 1 2 3 4 5 [mF]<br>Load transient peak voltage deviation vs. external capacitance. Load transient peak voltage deviation vs. external capacitance.<br>Step (12.5-37.5-12.5 A). Parallel coupling of capacitors with 470 µF/10 mΩ, Step (12.5-37.5-12.5 A). Parallel coupling of capacitors with 470 µF/10 mΩ,<br>TP1 = +25 °C. VI = 12 V, VO = 1.0 V, fsw = 320 kHz, di/dt = 2 A/µs TP1 = +25 °C. VI = 12 V, VO = 3.3 V, fsw = 320 kHz, di/dt = 2 A/µs<br>Load transient vs. Switch Frequency<br>[mV]<br>600<br>Universal PID,<br>No NLR<br>500<br>DLC,<br>No NLR<br>400<br>Universal PID,<br>Default NLR<br>300<br>DLC,<br>Default NLR<br>200<br>Universal PID,<br>100 Opt. NLR<br>DLC,<br>0 Opt. NLR<br>200 300 400 500 600 [kHz]<br>Load transient peak voltage deviation vs. frequency.<br>Step-change (12.5-37.5-12.5 A).<br>TP1 = +25 °C. VI = 12 V, VO = 1.0 V, CO = 470 µF/10 mΩ<br>Note 1: For Universal PID, see section Dynamic Loop Compensation (DLC).<br>Note 2: In these graphs, the worst-case scenario (load step 37.5-12.5 A) has been considered.<br>cui .com<br>DISCONTINUED<br>**----- End of picture text -----**<br> Additional Resources: Product Page | 3D Model **CUI Inc � SERIES** : NDM2Z-50 **� DESCRIPTION** : AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER **date** 12/21/2015 **� page** 18 of 32 **==> picture [564 x 623] intentionally omitted <==** **----- Start of picture text -----**<br> TYPICAL CHARACTERISTICS, VERTICAL (CONTINUED)<br>Output Current Derating, VO = 0.6 V Output Current Derating, VO = 1.0 V<br>[A] [A]<br>50 50<br>3.0 m/s 3.0 m/s<br>40 2.0 m/s 40 2.0 m/s<br>30 1.0 m/s 30 1.0 m/s<br>20 0.5 m/s 20 0.5 m/s<br>Nat. Conv. Nat. Conv.<br>10 10<br>0 0<br>20 40 60 80 100 120 [°C] 20 40 60 80 100 120 [°C]<br>Available load current vs. ambient air temperature and airflow at Available load current vs. ambient air temperature and airflow at<br>VO = 0.6 V, VI = 12 V. See Thermal Consideration section. VO = 1.0 V, VI = 12 V. See Thermal Consideration section.<br>Output Current Derating, VO = 1.8 V Output Current Derating, VO = 3.3 V<br>[A] [A]<br>50 50<br>3.0 m/s 3.0 m/s<br>40 40<br>2.0 m/s 2.0 m/s<br>30 1.0 m/s 30 1.0 m/s<br>20 0.5 m/s 20 0.5 m/s<br>Nat. Conv. Nat. Conv.<br>10 10<br>0 0<br>20 40 60 80 100 120 [°C] 20 40 60 80 100 120 [°C]<br>Available load current vs. ambient air temperature and airflow at Available load current vs. ambient air temperature and airflow at<br>VO = 1.8 V, VI = 12 V. See Thermal Consideration section. VO = 3.3 V, VI = 12 V. See Thermal Consideration section.<br>Current Limit Characteristics, VO = 1.0 V Current Limit Characteristics, VO = 3.3 V<br>[V] [V]<br>1,2 4,0<br>0,9 3,0<br>4.5 V<br>4.5 V<br>5.0 V<br>0,6 5.0 V 2,0<br>12 V<br>VI = 4.5, 5.0 V VI = 12, 14 V 12 V VI = 4.5, 14 V VI = 5.0, 12 V<br>14 V<br>0,3 14 V 1,0<br>0,0 0,0<br>50 55 60 65 [A] 50 55 60 65 [A]<br>Output voltage vs. load current at TP1 = +25 °C, VO = 1.0 V. Output voltage vs. load current at TP1 = +25 °C, VO = 3.3 V.<br>Note: Output enters hiccup mode at current limit. Note: Output enters hiccup mode at current limit.<br>DISCONTINUED<br>**----- End of picture text -----**<br> **cui** .com Additional Resources: Product Page | 3D Model **CUI Inc � SERIES** : NDM2Z-50 **� DESCRIPTION** : AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER **date** 12/21/2015 **� page** 19 of 32 **==> picture [564 x 681] intentionally omitted <==** **----- Start of picture text -----**<br> TYPICAL CHARACTERISTICS, VERTICAL (CONTINUED)<br>Output Ripple vs. Input Voltage Output Ripple vs. Frequency<br>[mVpk-pk] [mVpk-pk]<br>40 70<br>60<br>30<br>50 0.6 V<br>0.6 V<br>1.0 V 40 1.0 V<br>20<br>1.8 V<br>1.8 V 30<br>3.3 V<br>3.3 V 20<br>10<br>10<br>0 0<br>5 7 9 11 13 [V] 200 300 400 500 600 [kHz]<br>Output voltage ripple Vpk-pk at: TP1 = +25 °C, CO = 470 µF/10 mΩ, IO = 50 A. Output voltage ripple Vpk-pk at: TP1 = +25 °C, VI = 12 V, CO = 470 µF/10 mΩ,<br>IO = 50 A. Default configuration except changed frequency.<br>Output Ripple vs. External Capacitance Load regulation, VO = 1.0 V<br>[mV] [V]<br>40 1,010<br>30 0.6 V 1,005<br>4.5 V<br>1.0 V 5.0 V<br>20 1,000<br>1.8 V 12 V<br>14 V<br>10 3.3 V 0,995<br>0<br>0,990<br>0 1 2 3 4 5<br>[mF] 0 5 10 15 20 25 [A]<br>Output voltage ripple Vpk-pk at: TP1 = +25 °C, VI = 12 V, IO = 50 A. Load regulation at VO = 1.0 V, TP1 = +25 °C, CO = 470 µF/10 mΩ<br>Parallel coupling of capacitors with 470 µF/10 mΩ<br>cui .com<br>DISCONTINUED<br>**----- End of picture text -----**<br> Additional Resources: Product Page | 3D Model **date** 12/21/2015 **page** 20 of 32 **CUI Inc SERIES** : NDM2Z-50 **DESCRIPTION** : AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER **date** 12/21/2015 **page** 20 of 32 **TYPICAL CHARACTERISTICS, VERTICAL (CONTINUED) Start-up by input source Shut-down by input source** P| NS Start-up enabled by connecting VI at: Top trace: output voltage (0.5 V/div.). Shut-down enabled by disconnecting Top trace: output voltage (0.5 V/div). TP1 = +25 °C, VI = 12 V, VO = 1.0 V Bottom trace: input voltage (5 V/div.). VI at: Bottom trace: input voltage (5 V/div.). CO = 470 µF/10 mΩ, IO = 50 A Time scale: (20 ms/div.). TP1 = +25 °C, VI = 12 V, VO = 1.0 V Time scale: (2 ms/div.). CO = 470 µF/10 mΩ, IO = 50 A ~~|~~ **Start-up by CTRL signal Shut-down by CTRL signal** Som ACES Start-up by enabling CTRL signal at: Top trace: output voltage (0.5 V/div.). Shut-down enabled by disconnecting Top trace: output voltage (0.5 V/div). TP1 = +25 °C, VI = 12 V, VO = 1.0 V Bottom trace: CTRL signal (2 V/div.). VI at: Bottom trace: CTRL signal (2 V/div.). CO = 470 µF/10 mΩ, IO = 50 A Time scale: (20 ms/div.). TP1 = +25 °C, VI = 12 V, VO = 1.0 V Time scale: (2 ms/div.). CO = 470 µF/10 mΩ, IO = 50 A **cui** .com Additional Resources: Product Page | 3D Model **CUI Inc � SERIES** : NDM2Z-50 **� DESCRIPTION** : AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER **date** 12/21/2015 **� page** 21 of 32 ## **TYPICAL CHARACTERISTICS** **==> picture [560 x 643] intentionally omitted <==** **----- Start of picture text -----**<br> Efficiency vs. Output Current and Switching frequency Load transient vs. Switching frequency<br>[%] [mV]<br>95 600<br>Universal PID,<br>No NLR<br>500<br>90 200 DLC,<br>kHz 400 No NLR<br>85 320 Universal PID,<br>kHz 300 Default NLR<br>DLC,<br>80 480 Default NLR<br>kHz 200<br>Universal PID,<br>75 640kHz 100 Opt. NLR<br>DLC,<br>70 0 Opt. NLR<br>0 10 20 30 40 50 [A] 200 300 400 500 600 [kHz]<br>Efficiency vs. load current and switching frequency at Load transient peak voltage deviation vs. frequency.<br>TP1 = +25 °C, VI = 12 V, VO = 1.0 V, CO = 470 µF/10 mΩ Step-change (12.5-37.5-12.5 A).<br>Default configuration except changed frequency TP1 = +25 °C, VI = 12 V, VO =1.0 V, CO = 470 µF/10 mΩ<br>Power Dissipation vs. Output Current and Switching frequency Load Transient vs. Decoupling Capacitance, VO = 1.0 V<br>[W]<br>[mV]<br>12 500<br>Universal PID,<br>No NLR<br>10<br>200 400 DLC,<br>8 kHz No NLR<br>320 300 Universal PID,<br>6 kHz Default NLR<br>480 200 DLC,<br>4 kHz Default NLR<br>640 Universal PID,<br>2 kHz 100 Opt. NLR<br>DLC,<br>0 0 Opt. NLR<br>0 10 20 30 40 50 [A] 0 1 2 3 4 5 [mF]<br>Dissipated power vs. load current and switching frequency at Load transient peak voltage deviation vs. decoupling capacitance.<br>TP1 = +25 °C, VI = 12 V, VO = 1.0 V, CO = 470 µF/10 mΩ Step (12.5-37.5-12.5 A). Parallel coupling of capacitors with 470 µF/10 mΩ,<br>Default configuration except changed frequency TP1 = +25 °C. VI = 12 V, VO = 1.0 V, fsw = 320 kHz, di/dt = 2 A/µs<br>Output Ripple vs. Switching frequency Load Transient vs. Decoupling Capacitance, VO = 3.3 V<br>[mVpk-pk] [mV]<br>60 500<br>Universal PID,<br>No NLR<br>50<br>400 DLC,<br>0.6 V No NLR<br>40<br>300 Universal PID,<br>1.0 V Default NLR<br>30<br>1.8 V 200 DLC,<br>Default NLR<br>20 3.3 V Universal PID,<br>100 Opt. NLR<br>10 DLC,<br>0 Opt. NLR<br>0 0 1 2 3 4 5 [mF]<br>200 300 400 500 600 [kHz]<br>IOutput voltage ripple VO = 50 A resistive load. Default configuration except changed frequency. pk-pk at: TP1 = +25 °C, VI = 12 V, CO = 470 µF/10 mΩ, Load transient peak voltage deviation vs. decoupling capacitance. Step (12.5-37.5-12.5 A). Parallel coupling of capacitors with 470 µF/10 mΩ,<br>TP1 = +25 °C. VI = 12 V, VO = 3.3 V, fsw = 320 kHz, di/dt = 2 A/µs<br>DISCONTINUED<br>**----- End of picture text -----**<br> **cui** .com Additional Resources: Product Page | 3D Model |**CUI Inc� SERIES**: NDM2Z-50**�** **DESCRIPTION**: AUTO COMPENSATED, DIGITAL DC-DC POL CONV|**date**12/21/2015**�** **page**22 of 32<br>ERTER|**date**12/21/2015**�** **page**22 of 32<br>ERTER| |---|---|---| |**MECHANICAL DRAWING(HORIZONTAL, SURFACE MOUNT)**||| |units: mm [inches]<br>tolerance unless speci ed:<br>X.X ±0.50 [0.02]<br>X.XX ±0.25 [0.01]<br>(not applied on footprint or typical values)<br>**PIN**<br>**NUMBER**<br>**PIN**<br>**NAME**<br>**MATERIAL**<br>**PLATING**<br>1A, 1B<br>VIN<br>Copper Alloy<br>Min<br>0.1 �m Au<br>over<br>1~3 �m Ni<br>2A, 2B<br>GND<br>3A, 3B<br>VOUT<br>4A<br>VTRK<br>Brass<br>Min<br>0.1 �m Au<br>over<br>2 �m Ni<br>4B<br>PREF<br>5A<br>+S<br>5B<br>-S<br>6A<br>SA0<br>6B<br>DDC<br>7A<br>SCL<br>7B<br>SDA<br>8A<br>VSET<br>8B<br>SYNC<br>9A<br>SLRT<br>9B<br>CTRL<br>10A<br>PG<br>10B<br>SA1<br>DISCONTI||D| ||U|| |||| |||| |||| |||| |||| |**cui**.com||| Additional Resources: Product Page | 3D Model |**CUI Inc� SERIES**: NDM2Z-50**�** **DESCRIPTION**: AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER|**CUI Inc� SERIES**: NDM2Z-50**�** **DESCRIPTION**: AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER|**date**12/21/2015**�** **page**23 of 32| |---|---|---| |**MECHANICAL DRAWING(HORIZONTAL, THROUGH HOLE MOUNT)**||| |units: mm [inches]<br>tolerance unless speci ed:<br>X.X ±0.50 [0.02]<br>X.XX ±0.25 [0.01]<br>(not applied on footprint or typical values)<br>**PIN**<br>**NUMBER**<br>**PIN**<br>**NAME**<br>**MATERIAL**<br>**PLATING**<br>1A, 1B<br>VIN<br>Copper Alloy<br>Min<br>8~13 �m<br>matte tin<br>over<br>2.5~5 �m<br>Ni<br>2A, 2B<br>GND<br>3A, 3B<br>VOUT<br>4A<br>VTRK<br>Brass<br>Min<br>0.2 �m Au<br>over<br>1.27 �m Ni<br>4B<br>PREF<br>5A<br>+S<br>5B<br>-S<br>6A<br>SA0<br>6B<br>DDC<br>7A<br>SCL<br>7B<br>SDA<br>8A<br>VSET<br>8B<br>SYNC<br>9A<br>SLRT<br>9B<br>CTRL<br>10A<br>PG<br>10B<br>SA1<br>DISCO|NTIN|UED| ||**cui**.com|| Additional Resources: Product Page | 3D Model **CUI Inc � SERIES** : NDM2Z-50 **� DESCRIPTION** : AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER **date** 12/21/2015 **� page** 24 of 32 ## **MECHANICAL DRAWING (VERTICAL, THROUGH HOLE MOUNT)** |**PIN**<br>**NUMBER**<br>**PIN**<br>**NAME**<br>**MATERIAL**<br>**PLATING**<br>1A<br>VIN<br>Copper Alloy<br>Min<br>0.1 �m Au<br>over<br>1~3 �m Ni<br>1B<br>VIN<br>2A<br>GND<br>2B<br>GND<br>3A<br>VOUT<br>3B<br>VOUT<br>4A<br>+S<br>Min<br>0.1 �m Au<br>over<br>1 �m Ni<br>4B<br>-S<br>5A<br>VSET<br>5B<br>VTRK<br>6A<br>SALRT<br>6B<br>SDA<br>7A<br>SCL<br>7B<br>SA1<br>8A<br>SA0<br>8B<br>SYNC<br>9A<br>PG<br>9B<br>CTRL<br>10A<br>DDC<br>10B<br>PREF<br>units: mm [inches]<br>tolerance unless speci ed:<br>X.X ±0.50 [0.02]<br>X.XX ±0.25 [0.01]<br>(not applied on footprint or typical values)<br>DISCO|**PIN**<br>**NUMBER**<br>**PIN**<br>**NAME**<br>**MATERIAL**<br>**PLATING**<br>1A<br>VIN<br>Copper Alloy<br>Min<br>0.1 �m Au<br>over<br>1~3 �m Ni<br>1B<br>VIN<br>2A<br>GND<br>2B<br>GND<br>3A<br>VOUT<br>3B<br>VOUT<br>4A<br>+S<br>Min<br>0.1 �m Au<br>over<br>1 �m Ni<br>4B<br>-S<br>5A<br>VSET<br>5B<br>VTRK<br>6A<br>SALRT<br>6B<br>SDA<br>7A<br>SCL<br>7B<br>SA1<br>8A<br>SA0<br>8B<br>SYNC<br>9A<br>PG<br>9B<br>CTRL<br>10A<br>DDC<br>10B<br>PREF<br>units: mm [inches]<br>tolerance unless speci ed:<br>X.X ±0.50 [0.02]<br>X.XX ±0.25 [0.01]<br>(not applied on footprint or typical values)<br>DISCO|**PIN**<br>**NUMBER**<br>**PIN**<br>**NAME**<br>**MATERIAL**<br>**PLATING**<br>1A<br>VIN<br>Copper Alloy<br>Min<br>0.1 �m Au<br>over<br>1~3 �m Ni<br>1B<br>VIN<br>2A<br>GND<br>2B<br>GND<br>3A<br>VOUT<br>3B<br>VOUT<br>4A<br>+S<br>Min<br>0.1 �m Au<br>over<br>1 �m Ni<br>4B<br>-S<br>5A<br>VSET<br>5B<br>VTRK<br>6A<br>SALRT<br>6B<br>SDA<br>7A<br>SCL<br>7B<br>SA1<br>8A<br>SA0<br>8B<br>SYNC<br>9A<br>PG<br>9B<br>CTRL<br>10A<br>DDC<br>10B<br>PREF<br>units: mm [inches]<br>tolerance unless speci ed:<br>X.X ±0.50 [0.02]<br>X.XX ±0.25 [0.01]<br>(not applied on footprint or typical values)<br>DISCO|**PIN**<br>**NUMBER**<br>**PIN**<br>**NAME**<br>**MATERIAL**<br>**PLATING**<br>1A<br>VIN<br>Copper Alloy<br>Min<br>0.1 �m Au<br>over<br>1~3 �m Ni<br>1B<br>VIN<br>2A<br>GND<br>2B<br>GND<br>3A<br>VOUT<br>3B<br>VOUT<br>4A<br>+S<br>Min<br>0.1 �m Au<br>over<br>1 �m Ni<br>4B<br>-S<br>5A<br>VSET<br>5B<br>VTRK<br>6A<br>SALRT<br>6B<br>SDA<br>7A<br>SCL<br>7B<br>SA1<br>8A<br>SA0<br>8B<br>SYNC<br>9A<br>PG<br>9B<br>CTRL<br>10A<br>DDC<br>10B<br>PREF<br>units: mm [inches]<br>tolerance unless speci ed:<br>X.X ±0.50 [0.02]<br>X.XX ±0.25 [0.01]<br>(not applied on footprint or typical values)<br>DISCO||NTIN|UED| |---|---|---|---|---|---|---| |**PIN**<br>**NUMBER**<br>|**PIN**<br>**NAME**<br>|**MATERIAL**<br>|**PLATING**<br>|||| |1A<br>|VIN<br>|Copper Alloy<br>|Min<br>0.1 �m Au<br>over<br>1~3 �m Ni<br>|||| |1B<br>2A<br>|VIN<br>GND<br>|||||| |2B<br>|GND<br>|||||| |3A<br><br>|VOUT<br><br>|||||| |3B<br>|VOUT<br>|||||| |4A<br>|+S<br>||Min<br>0.1 �m Au<br>over<br>1 �m Ni<br>|||| |4B<br>|-S<br>|||||| |||||||| |5A<br>|VSET<br>|||||| |5B<br>|VTRK<br>|||||| |6A<br>|SALRT<br>|||||| |6B<br>7A<br>7B<br>|SDA<br>SCL<br>SA1<br>|||||| |8A<br>8B<br>|SA0<br>SYNC<br>|||||| |9A<br>9B<br>|PG<br>CTRL<br>|||||| |10A<br>|DDC<br>|||||| |10B<br>|PREF<br>|||||| |DIS||||||| |||||||| |||||||| |||||||| ||||||**cui**.com|| Additional Resources: Product Page | 3D Model **CUI Inc � SERIES** : NDM2Z-50 **� DESCRIPTION** : AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER **date** 12/21/2015 **� page** 25 of 32 **OPERATING INFORMATION** deviation as a result of load transients. The incorporation of DFM enhances the performance of CUI modules over that The Novum Z Products PMBus Commands application note available from conventional analog POL offerings. de nes the available PMBus™ commands. **Power Management Overview** The NDM2Z-50 module incorporates a wide range of power **REQUIRED CONFIGURATIONS** management features. All power management functions **NDM2Z-50 Module Pins** can be configured via the SMBus interface. The NDM2Z-50 can monitor and report many characteristics of the module Each NDM2Z-50 module should have a resistor placed including input voltage, output voltage, output current and between VSET and PREF to set the output voltage of the internal temperature. Additionally, the NDM2Z-50 includes module. The maximum output voltage which can be circuit protection features that protect the module and load con gured by PMBus commands can never exceed 110% of from damage due to system faults. Monitoring parameters the voltage set by the VSET pin. The SMBus address of each can also be configured to provide alerts for specific module is set by either pin-strap con guration or resistor conditions. The ability of CUI modules to digitally control, value associated with the SA0 and SA1 pins. More configure and monitor OS features provides significant information regarding setting the SMBus address for a module can be found in the section titled “SMBus”. benefits over traditional analog POL products. **PCB Layout** Good performance of any point of load voltage regulator **CONFIGURING THE MODULE** module can only be achieved with careful PCB layout considerations. Ground planes or very wide traces should **Pin Settings** be used for power and ground routing. Input capacitors Pins SA0 and SA1 are used to set the SMBus address should be placed close to the input voltage pins of the of the NDM2Z-50 module. Details of this feature are module and output capacitors should be placed close to the discussed in the section titled “SMBus”. Pin SYNC is used load. The module should also be placed as close as possible to synchronize the switching clock of the module to an to the load. external clock source. More information regarding synchronization can be found in the section titled **INPUT AND OUTPUT CAPACITORS** “SWITCHING FREQUENCY AND SYNCHRONIZATION”. Pin VSET is used to configure the output voltage of the **Input Capacitors** module. The voltage established by the VSET pin limits the Input capacitors are recommended to be used with the maximum output voltage that can be configured by SMBus NDM2Z-50 module in order to minimize input voltage ripple. commands. A 330 �F POSCAP or electrolytic and 3x 22 �F ceramic The SA0, SA1, SYNC and VSET pin configurations are read capacitors should be placed as close as possible to the input by the module when power is applied or whenever a SMBus pins of the module. Additional input capacitors may be RESTORE command is issued. used if less input voltage ripple is desired. The CTRL pin is active high and can be used to enable the module. Internal connections on the module will drive the **Output Capacitors** CTRL pin high if it is left floating. Output capacitors are recommended to be used with the Pins +S and -S are used for remote voltage sensing of the NDM2Z-50 module in order to improve transient response output voltage. and minimize output voltage ripple. A 330 �F POSCAP or electrolytic and 3x 22 �F ceramic capacitors should be placed as close as possible to the load. Additional output capacitors may be used to further improve the output voltage characteristics. **POWER CONVERSION AND MANAGEMENT Power Conversion Overview** The NDM2Z-50 module has several features to enable high power conversion efficiency. Non-linear loop response (NLR) improves the response time and reduces the output **cui** .com Additional Resources: Product Page | 3D Model **CUI Inc � SERIES** : NDM2Z-50 **� DESCRIPTION** : AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER **date** 12/21/2015 **� page** 26 of 32 ## **Unused Pins** Table 1 describes the required or allowed connections for unused pins on the NDM2Z-50 module. |Table 1: Unused Pins<br>**Con guration of Parameters Using the SMBus**<br>The NDM2Z-50 module is supplied with default settings. All module settings (except for module SMBus address,<br>con gured by pins SA0 and SA1) can be re-con gured via the SMBus interface. The output voltage can not be set to<br>greater than 110% of the voltage set by the VSET pin.<br>**START-UP PROCEDURE**<br>**Start-up Sequence**<br>The NDM2Z-50 module follows an internal start-up procedure after power is applied to pin VIN. Table 2 describes the<br>start-up sequence. If the module is to be synchronized to an external clock source, the clock frequency must be stable<br>prior to asserting CTRL (or applying input voltage to the module if CTRL is not used). Once this process is completed, the<br>module is ready to accept assertion of CTRL and commands via the SMBus interface.<br>Table 2: NDM2Z-50 Start-up sequence<br>VSET<br>Tie to PREF with 133 k� resistor, see VOUT_COMMAND PMBus command<br>VTRK, SA0, SA1, SYNC, CTRL, +S, -S<br>Float<br>DDC, SCL, SDA, SALRT<br>Pulled high with resistor, see "RECOMMENDED OPERATIN CONDITIONS"<br>INUED|Table 1: Unused Pins<br>**Con guration of Parameters Using the SMBus**<br>The NDM2Z-50 module is supplied with default settings. All module settings (except for module SMBus address,<br>con gured by pins SA0 and SA1) can be re-con gured via the SMBus interface. The output voltage can not be set to<br>greater than 110% of the voltage set by the VSET pin.<br>**START-UP PROCEDURE**<br>**Start-up Sequence**<br>The NDM2Z-50 module follows an internal start-up procedure after power is applied to pin VIN. Table 2 describes the<br>start-up sequence. If the module is to be synchronized to an external clock source, the clock frequency must be stable<br>prior to asserting CTRL (or applying input voltage to the module if CTRL is not used). Once this process is completed, the<br>module is ready to accept assertion of CTRL and commands via the SMBus interface.<br>Table 2: NDM2Z-50 Start-up sequence<br>VSET<br>Tie to PREF with 133 k� resistor, see VOUT_COMMAND PMBus command<br>VTRK, SA0, SA1, SYNC, CTRL, +S, -S<br>Float<br>DDC, SCL, SDA, SALRT<br>Pulled high with resistor, see "RECOMMENDED OPERATIN CONDITIONS"<br>INUED|Table 1: Unused Pins<br>**Con guration of Parameters Using the SMBus**<br>The NDM2Z-50 module is supplied with default settings. All module settings (except for module SMBus address,<br>con gured by pins SA0 and SA1) can be re-con gured via the SMBus interface. The output voltage can not be set to<br>greater than 110% of the voltage set by the VSET pin.<br>**START-UP PROCEDURE**<br>**Start-up Sequence**<br>The NDM2Z-50 module follows an internal start-up procedure after power is applied to pin VIN. Table 2 describes the<br>start-up sequence. If the module is to be synchronized to an external clock source, the clock frequency must be stable<br>prior to asserting CTRL (or applying input voltage to the module if CTRL is not used). Once this process is completed, the<br>module is ready to accept assertion of CTRL and commands via the SMBus interface.<br>Table 2: NDM2Z-50 Start-up sequence<br>VSET<br>Tie to PREF with 133 k� resistor, see VOUT_COMMAND PMBus command<br>VTRK, SA0, SA1, SYNC, CTRL, +S, -S<br>Float<br>DDC, SCL, SDA, SALRT<br>Pulled high with resistor, see "RECOMMENDED OPERATIN CONDITIONS"<br>INUED|Table 1: Unused Pins<br>**Con guration of Parameters Using the SMBus**<br>The NDM2Z-50 module is supplied with default settings. All module settings (except for module SMBus address,<br>con gured by pins SA0 and SA1) can be re-con gured via the SMBus interface. The output voltage can not be set to<br>greater than 110% of the voltage set by the VSET pin.<br>**START-UP PROCEDURE**<br>**Start-up Sequence**<br>The NDM2Z-50 module follows an internal start-up procedure after power is applied to pin VIN. Table 2 describes the<br>start-up sequence. If the module is to be synchronized to an external clock source, the clock frequency must be stable<br>prior to asserting CTRL (or applying input voltage to the module if CTRL is not used). Once this process is completed, the<br>module is ready to accept assertion of CTRL and commands via the SMBus interface.<br>Table 2: NDM2Z-50 Start-up sequence<br>VSET<br>Tie to PREF with 133 k� resistor, see VOUT_COMMAND PMBus command<br>VTRK, SA0, SA1, SYNC, CTRL, +S, -S<br>Float<br>DDC, SCL, SDA, SALRT<br>Pulled high with resistor, see "RECOMMENDED OPERATIN CONDITIONS"<br>INUED| |---|---|---|---| |**STEP**<br>|**STEP NAME**<br>|**DESCRIPTION**<br>|**TIME DURATION**<br>| |1<br>|Power applied or<br>RESTORE_FACTORY<br>|Input voltage is applied to NDM2Z-50 module pin VIN or RESTORE_FACTORY<br>PMBus command issued<br>|Depends on input<br>supply ramp time<br>| |2<br>|Factory con guration<br>settings<br>|Module loads factory con guration settings. This step is also performed after<br>using PMBus commands to restore the factory con guration le.<br>|Approximately 10<br>ms (module will<br>ignore a CTRL<br>signal and PMBus<br>commands during<br>this period)<br>| |3<br>|SA0, SA1, SYNC and<br>VSET pin settings<br>|Module loads values con gured by the SA0, SA1, SYNC and VSET pins.<br>|| |4<br>|Default con guration<br>settings<br>|Module loads default con guration settings. This data over-rides pin setting<br>data, except for maximum limit for VOUT_COMMAND. This step also performed<br>after using PMBus commands to restore the default con guration le.<br>|| |5<br>|User con guration<br>settings<br>|Module loads user con guration settings. This data over-rides pin setting and<br>default con guration data, except for maximum limit for VOUT_COMMAND. This<br>step also performed after using PMBus commands to restore the user<br>con guration le.<br>|| |6<br>|Module ready<br>|The module is ready to accept a CTRL signal.<br>|---<br>| |7<br>|Pre-ramp delay<br>|The module requires approximately 5 ms following a CTRL signal and prior to<br>ramping its output. Additional pre-ramp delay may be con gured using PMBus<br>commands.<br>|Approximately<br>5 ms<br>| |**Soft-start Delay Ramp Times**<br>Once CTRL is asserted the NDM2Z-50 module requires a<br>pre-ramp delay time before the output voltage may be<br>allowed to start the ramp-up process. After the delay period<br>has expired, the output will begin to ramp towards the<br>target voltage according to the pre-con gured soft-start<br>ramp time that has been set. It is recommended to set the<br>soft-start ramp time to a value greater than 500 �s in order<br>to prevent fault conditions due to excessive inrush current.<br>Soft start delay and ramp times may be set using PMBus<br>commands.<br>voltage is present on the NDM2Z-50 module output before<br>the module output voltage is enabled. If a pre-bias voltage<br>exists, the output voltage of the module is set to match the<br>existing pre-bias voltage. The output voltage is then ramped<br>to the final regulation value in the specified ramp time.<br>The pre-bias voltage can be higher or lower than the final<br>output voltage. Higher pre-bias output voltages will cause<br>energy to be pumped into the input voltage rail powering<br>the module. This condition could cause the module to report<br>an error condition if the input voltage exceeds the input<br>over voltage lock out threshold. The module will report an<br>DI|||| voltage is present on the NDM2Z-50 module output before the module output voltage is enabled. If a pre-bias voltage exists, the output voltage of the module is set to match the existing pre-bias voltage. The output voltage is then ramped to the final regulation value in the specified ramp time. The pre-bias voltage can be higher or lower than the final output voltage. Higher pre-bias output voltages will cause energy to be pumped into the input voltage rail powering the module. This condition could cause the module to report an error condition if the input voltage exceeds the input over voltage lock out threshold. The module will report an error condition if the pre-bias output voltage exceeds the output over voltage protection threshold. ## **Output Pre-Bias** An output pre-bias condition exists when a non-zero **cui** .com Additional Resources: Product Page | 3D Model **CUI Inc � SERIES** : NDM2Z-50 **� DESCRIPTION** : AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER **date** 12/21/2015 **� page** 27 of 32 ## **Power Good** Table 4: Resistor VOUT voltage settings The PG pin on the NDM2Z-50 module will assert if the **RESISTOR (k** � **) VOUT (V) RESISTOR (k** � **) VOUT (V)** output of the module is within tolerance of the target 10.0 0.60 38.3 1.30 voltage and no fault conditions exist. A PG delay period 11.0 0.65 42.2 1.40 is de ned as the time from when all conditions within the 12.1 0.70 46.4 1.50 module for asserting PG are met to when PG is actually 13.3 0.75 51.1 1.60 asserted. By default, PG delay is set equal to the soft-start 14.7 0.80 56.2 1.70 ramp time setting. The tolerance, polarity and delay of PG may be con gured via PMBus commands. 16.2 0.85 61.9 1.80 17.8 0.90 68.1 1.90 **Soft-stop Delay and Ramp Times** 19.6 0.95 75.0 2.00 After CTRL is de-asserted the NDM2Z-50 module utilizes 21.5 1.00 82.5 2.10 a pre-ramp delay time before the output starts the ramp23.7 1.05 90.9 2.20 down process. After the delay period has expired, the 26.1 1.10 100.0 2.30 output will begin to ramp towards ground according to the 28.7 1.15 110.0 2.50 pre-con gured soft-stop ramp time that has been set. It is 31.6 1.20 121.0 3.00 recommended to set the soft-start ramp down to a value greater than 500 �s in order to prevent voltage spikes in 34.8 1.25 133.0 3.30 the module input supply rail due the energy stored in the **SMBus Setting Method** output capacitors. There will be a delay after the output The voltage present at the VOUT pin of the NDM2Z-50 voltage has reached ground potential and then the output of module can be reconfigured using PMBus commands. A the module will be set to high impedance. Once the output voltage level reconfigured by a PMBus command overof the module is high impedance the output voltage may rides the voltage set by the VSET pin, but cannot be set to oat to a non-zero value if another source or leakage path greater than 110% of the voltage set by the VSET pin. is connected to the output. The soft-stop delay and ramp times may be con gured via PMBus commands. **Voltage Tracking** PMBus commands can be used to set the output of the The NDM2Z-50 module includes a feature that allows the NDM2Z-50 module to high impedance as soon as the output output ramp voltage to track the ramp of a reference voltage drops below a selectable threshold. voltage which is applied to the VTRK pin. The voltage ramp tracking capability can be configured so that member **OUTPUT VOLTAGE SETTING** modules track at either 50% or 100% of the reference voltage ramp rate. In addition, a member module can be **Pin-Strap and Resistor Setting Methods** configured so that the termination voltage either tracks Using the pin-strap method, the voltage on the VOUT pin or ignores perturbations on the reference voltage once it of the NDM2Z-50 module can be set to one of three default has stabilized. Tracking at 50% and tracking final voltage voltages as shown in Table 3. Table 4 lists the available perturbations is intended for DDR memory applications. All output voltage settings with a resistor connected between other applications which required voltage tracking should VSET and PREF. use 100% tracking and ignore final voltage perturbations. The reference voltage for tracking must have a target voltTable 3: Pin-strap VOUT voltage settings age which is equal to or greater than the target voltage of the member modules. The turn-on delay of the reference **VSET VOUT (V)** voltage must be at least 10 ms greater than that set for the LOW (< 0.8 V) 0.6 member modules. In voltage tracking mode, the turn-off OPEN (N/C) 1.2 delay of the member modules establishes the time duration HIGH (> 2.0 V) 2.5 which the member modules will track the reference voltage after CTRL is de-asserted. The turn-off delay of the member modules must be at least 5 ms greater than the sum of the turn-off delay and fall time of the reference voltage. **cui** .com Additional Resources: Product Page | 3D Model **CUI Inc � SERIES** : NDM2Z-50 **� DESCRIPTION** : AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER **date** 12/21/2015 **� page** 28 of 32 Current sharing modules which are also configured to track loop every time the output voltage ramps to the regulated a voltage must have all of the VTRK pins tied together. level. PMBus commands can be used to con gure when the All of the CTRL pins of the member modules must also be module re-compensates the loop. connected together and driven by a common source. The The user also has the option to manually con gure the loop rise and fall times of the member modules should be set compensation. between 5 ms and 10 ms to ensure current sharing while **Non-Linear Response (NLR) Settings** ramping. PMBus commands can be used to configure the The NDM2Z-50 module incorporates a non-linear response voltage tracking features. (NLR) loop that decreases the response time and the output **Voltage Margining** voltage deviation in the event of a sudden output load The NDM2Z-50 module offers a means to vary the output current step. This implementation results in a higher voltage higher or lower relative to the nominal voltage equivalent loop bandwidth than what would be possible setting. The rate of change of the output voltage during using a traditional linear loop. PMBus commands can be voltage margining is also configurable. The margin feature used to con gure the NLR response of the module. can be reconfigured through PMBus commands. **Adaptive Diode Emulation** Please contact CUI technical support regarding the **SWITCHING FREQUENCY AND SYNCHRONIZATION** implementation of adaptive diode emulation. **Switching Frequency Adaptive Frequency Control** The switching frequency of the NDM2Z-50 module can The NDM2Z-50 module includes adaptive frequency control be recon gured by PMBus commands or controlled by an to improve conversion ef ciency. Adaptive frequency control external clock source connected to the SYNC pin. If the is not available for current sharing groups and is not module is operated at a switching frequency of other than allowed when the module is placed in auto-detect mode the factory default setting, the compensation may need to and a clock source is present on the SYNC pin. be adjusted and the ripple, noise, transient response and Adaptive frequency control is only available while the ef ciency may be affected. module is operating within adaptive diode emulation mode. **SYNC Auto Detect** Adaptive frequency control can be enabled and disabled The NDM2Z-50 module will automatically check for a clock with PMBus commands. signal on the SYNC pin after CTRL is asserted (or applying input voltage to the module if CTRL is not used). If a clock **MULTI-MODULE CONFIGURATION** signal is present, the module will synchronize to the rising **Output Sequencing** edge of the external clock. The external clock signal must be stable and conform to the “RECOMMENDED OPERATING Multiple device sequencing of NDM2Z-50 modules may be achieved by issuing PMBus commands to assign the CONDITIONS” parameters when CTRL is asserted (or preceding device in the sequencing chain as well as the applying input voltage to the module if CTRL is not used). device that will follow in the sequencing chain. The CTRL In the event of a loss of the external clock signal, the pins of all devices in a sequencing group must be tied output voltage of the module may show transient overshoot together and driven high to initiate a sequenced turn-on of or undershoot and the module will automatically con gure the group. CTRL must be driven low to initiate a sequenced to switch at a frequency close to the previous incoming turnoff of the group. frequency. If no incoming clock signal is present when CTRL is asserted (or applying input voltage to the module if CTRL is not used), the module will switch at the frequency set by the con guration le. **CONTROL LOOP Adaptive Loop Compensation** The NDM2Z-50 module employs automatic adaptive loop compensation to increase the performance and stability of the module over a wide range of conditions. The default setting con gures the module to re-compensate the control **cui** .com Additional Resources: Product Page | 3D Model **CUI Inc � SERIES** : NDM2Z-50 **� DESCRIPTION** : AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER **date** 12/21/2015 **� page** 29 of 32 the phase offset of each module is controlled by the module addresses; phase offset = device address x 45°. For example: ## **Fault Spreading** NDM2Z-50 modules can be configured to broadcast a fault addresses; phase offset = device address x 45°. event over the DDC (Digital-DC Communication bus) to the For example: other modules in the group. When a nondestructive fault • A module address of 0x00 or 0x20 would con gure 0° of occurs and the module is configured to shut down on a phase offset fault, the module will shut down and broadcast the fault • A module address of 0x01 or 0x21 would con gure 45° of event over the DDC. The other modules on the DDC will phase offset shut down together if configured to do so, and will attempt • A module address of 0x02 or 0x22 would con gure 90° of to re-start in their prescribed order if configured to do so. phase offset PMBus commands can be used to configure the The phase offset of each module may also be set via the transmission and reception of faults. PMBus INTERLEAVE command. **Active Current Sharing POWER FAULT MANAGEMENT** Paralleling multiple NDM2Z-50 modules can be used to increase the output current capability of a single power rail. **Input Under and Over Voltage Lockout** By connecting the DDC of each module together and Input under voltage lockout (UVLO) and input over voltage con guring the modules as a current sharing rail, the units lockout (OVLO) indicate faults for the NDM2Z-50 module will share the load current. when the input voltage falls outside of preset thresholds. Upon system start-up, the module with the lowest SMBus The default response due to an input voltage fault is address is de ned as the reference module; the remaining an immediate shutdown of the module. The module will modules are members. The reference module broadcasts continuously check for the presence of the fault condition. the current over the DDC. The output voltages of the Once the fault condition is no longer present, the module member modules are controlled by the reference current will be re-enabled. PMBus commands can be used to information to balance the current loading of each module con gure the thresholds and response of the module to the in the system. fault condition. A current sharing rail can be part of a system sequencing group. For fault con guration, the current share rail is **Output Under and Over Voltage Protection** con gured in a quasi-redundant mode. In this mode, when The NDM2Z-50 module employs an output voltage a member module fails the remaining members will protection circuit that can be used to protect load circuitry continue to operate and attempt to maintain regulation. If from being subjected to voltages outside of prescribed fault spreading is enabled, the current share rail failure is limits. A hardware comparator is used to compare the broadcast only after the entire current share rail fails. voltage seen at the +S pin to voltage thresholds. If the +S Members of the current sharing rail can be disabled to pin voltage is outside of these thresholds the PG pin will improve system power conversion ef ciency. If the de-assert and the module will indicate a fault condition. reference module fails or is disabled then the remaining The default response to an output voltage fault is to module with the lowest SMBus address will become the new immediately shut down. The module will continuously check reference module. A change to the number of members of a for the presence of the fault condition, when the fault current sharing rail will cause automatic phase condition no longer exists the module will be re-enabled. re-distribution of the members of that current sharing rail. PMBus commands can be used to set the voltage If the members of a current sharing rail are forced to shut thresholds and con gure the response of the module to the down due to an observed fault, all members of the rail will fault condition. When operating from an external clock the attempt to re-start simultaneously after the fault has only allowed response to an output voltage fault is an cleared. PMBus commands can be used to con gure current immediate shutdown. sharing. A maximum of seven modules can be con gured in a single current share group. **Phase Spreading** When multiple NDM2Z-50 modules share a common DC input supply, it may be desirable to adjust the clock phase offset of each module. In order to enable phase spreading, all modules must be synchronized to the same switching clock. For modules driven by a common synchronizing clock **cui** .com Additional Resources: Product Page | 3D Model **CUI Inc � SERIES** : NDM2Z-50 **� DESCRIPTION** : AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER **date** 12/21/2015 **� page** 30 of 32 Table 5: Pin-strap SMBus Addressing ## **Output Over Current Protection** Output over current protection will protect the NDM2Z-50 module and load from damage if an overload condition is **SA0 ADDRESS** imposed on the output. The module will indicate a fault HIGH 0x22 condition when the output current limit threshold is OPEN 0x21 exceeded. The default response from an output current fault LOW 0x20 is an immediate shutdown of the module. The module will Table 6: Single Resistor SMBus Addressing continuously check for the presence of the fault condition, and if the fault condition no longer exists the module will be re-enabled. PMBus commands can be used to con gure the **RSA0 (k** � **) ADDRESS RSA0 (k** � **) ADDRESS** 10.0 0x00 34.8 0x0D current limit threshold and the response of the module to 11.0 0x01 38.3 0x0E the fault condition. 12.1 0x02 42.2 0x0F **Thermal Overload Protection** 13.3 0x03 46.4 0x10 The NDM2Z-50 module includes a thermal sensor that 14.7 0x04 51.1 0x11 measures the temperature of the module and indicates a 16.2 0x05 56.2 0x12 fault when the temperature exceeds a preset limit. The 17.8 0x06 61.9 0x13 default response from a temperature fault is an 19.6 0x07 68.1 0x14 immediate shutdown of the module. The module will 21.5 0x08 75.0 0x15 continuously check for the fault condition and once the fault 23.7 0x09 82.5 0x16 has cleared the module will be re-enabled. PMBus 26.1 0x0A 90.9 0x17 commands can be used to con gure the thermal protection threshold and the response of the module to the 28.7 0x0B 100.0 0x18 fault condition. Permanent damage to the module may 31.6 0x0C result if the thermal limit is set too high. When using only pin SA0 to set the SMBus address, pin SA1 **SMBUS** should be tied to PREF. If more than 25 unique module addresses are required or if **SMBus Communications** other SMBus address values are desired, pins SA0 and SA1 The NDM2Z-50 module provides a SMBus interface that can be con gured with a resistor to PREF as listed in enables the user to con gure the module operation as well Table 7. as monitor input and output parameters. The module can be used with any standard 2-wire I[[2]] C host device, accepts Using this method, the user can theoretically con gure up most standard PMBus commands, is compatible with SMBus to 625 unique SMBus addresses. However, the SMBus is version 2.0 and includes an SALRT line to help mitigate inherently limited to 128 modules so attempting to bandwidth limitations related to continuous fault con gure an address higher than 128 (0x80) will cause the monitoring. It is recommended that CTRL be pulled low module address to repeat (i.e, attempting to con gure a while con guring the module with PMBus commands. module address of 129 (0x81) would result in a module Pull-up resistors are required on the SMBus lines as address of 1). described in "RECOMMENDED OPERATING CONDITIONS". Therefore, the user should use index values 0-4 on pin SA1 and the full range of index values on pin SA0, which will **SMBus Addresses** provide 125 module address combinations. Note that the When communicating with multiple SMBus devices using the SMBus address 0x4B is reserved for module test and cannot SMBus interface, each device must have a unique address be used in the system. so the host can distinguish between the devices. The NDM2Z-50 module address can be set according to the pin-strap options listed in Table 5; address values are right-justi ed. The NDM2Z-50 module provides a SMBus interface that enables the user to con gure the module operation as well as monitor input and output parameters. The module can be used with any standard 2-wire I[[2]] C host device, accepts most standard PMBus commands, is compatible with SMBus version 2.0 and includes an SALRT line to help mitigate bandwidth limitations related to continuous fault monitoring. It is recommended that CTRL be pulled low while con guring the module with PMBus commands. Pull-up resistors are required on the SMBus lines as described in "RECOMMENDED OPERATING CONDITIONS". Therefore, the user should use index values 0-4 on pin SA1 and the full range of index values on pin SA0, which will provide 125 module address combinations. Note that the SMBus address 0x4B is reserved for module test and cannot be used in the system. If additional module addresses are required, a resistor can be connected to pin SA0 as shown in Table 6 to provide up to 25 unique module addresses. **cui** .com Additional Resources: Product Page | 3D Model |**CUI Inc� SERIES**: NDM2Z-50**�** **DESCRIPTION**: AUTO COMPENSATED, DIGITAL|**CUI Inc� SERIES**: NDM2Z-50**�** **DESCRIPTION**: AUTO COMPENSATED, DIGITAL|**date**12/21/2015**�** **page**31 of 32<br>DC-DC POL CONVERTER| |---|---|---| |Table 7: Dual Resistor SMBus Addressing||**SINGLE WIRE COMMUNICATIONS**| |**Monitoring Via SMBus**<br>A system controller can be used to monitor the NDM2Z-50<br>module system parameters through the SMBus. Fault<br>conditions can be detected by monitoring the SALRT pin,<br>which will be asserted when pre-con gured fault conditions<br>occur. Modules can also be monitored for power conversion<br>parameters including but not limited to the following:<br>• Input voltage<br>• Output voltage<br>• Output current<br>• Module temperature<br>• Switching frequency<br>**Digital-DC Bus**<br>The DDC (Digital-DC Communication Bus) is used to<br>communicate between NDM2Z modules. This dedicated bus<br>provides the communication channel between modules for<br>features such as sequencing, fault spreading, and current<br>sharing. A pull-up resistor is required on the DDC as<br>de ned in “RECOMMENDED OPERATING CONDITIONS”.<br>**Snapshot**™**Parameter Capture**<br>The NDM2Z-50 module offers features that enable the user<br>to capture parametric data during normal operation or<br>following a fault. The Snapshot feature enables the user to<br>read status and parameter values via a block read transfer<br>through the SMBus. This can be done during normal<br>operation, although it should be noted that reading the 22<br>bytes will occupy the SMBus for up to 1400 �s.<br>The SNAPSHOT_CONTROL command enables the user to<br>store the snapshot parameters to ash memory in<br>response to a pending fault as well as to read the stored<br>data from ash memory after a fault has occurred.<br>Automatic writes to ash memory following a fault are<br>triggered when any fault threshold level is exceeded,<br>provided that the speci c response to that fault is<br>to shut down (writing to ash memory is not allowed if the<br>module is con gured to re-try following the speci c fault<br>condition). It should also be noted that the input voltage to<br>the module must be maintained during the time when the<br>module is writing the data to ash memory; a process that<br>requires between 700 �s to 1400 �s depending on whether<br>the data is set up for a block write. Undesirable results may<br>be observed if the input voltage to the module drops too<br>low during this process. In the event that the module<br>experiences a fault and power is lost, the user can extract<br>the last SNAPSHOT parameters stored during the fault<br>by using the SMBus to transfer data from ash memory to<br>RAM and then using the SMBus to read data from RAM.<br>**THERMAL CONSIDERATIONS**<br>**Mounting**<br>Heat from the NDM2Z-50 module will be conducted through<br>the pins to the host board. Provisions must be made for the<br>host board to accommodate this additional heating.<br>**Air ow**<br> <br>10.0<br>11.0<br>12.1<br>13.3<br>14.7<br>RSA1 (k�)<br>10.0<br>0x00<br>0x19<br>0x32<br>0x4B<br>0x64<br>11.0<br>0x01<br>0x1A<br>0x33<br>0x4C<br>0x65<br>12.1<br>0x02<br>0x1B<br>0x34<br>0x4D<br>0x66<br>13.3<br>0x03<br>0x1C<br>0x35<br>0x4E<br>0x67<br>14.7<br>0x04<br>0x1D<br>0x36<br>0x4F<br>0x68<br>16.2<br>0x05<br>0x1E<br>0x37<br>0x50<br>0x69<br>17.8<br>0x06<br>0x1F<br>0x38<br>0x51<br>0x6A<br>19.6<br>0x07<br>0x20<br>0x39<br>0x52<br>0x6B<br>21.5<br>0x08<br>0x21<br>0x3A<br>0x53<br>0x6C<br>23.7<br>0x09<br>0x22<br>0x3B<br>0x54<br>0x6D<br>26.1<br>0x0A<br>0x23<br>0x3C<br>0x55<br>0x6E<br>28.7<br>0x0B<br>0x24<br>0x3D<br>0x56<br>0x6F<br>31.6<br>0x0C<br>0x25<br>0x3E<br>0x57<br>0x70<br>34.8<br>0x0D<br>0x26<br>0x3F<br>0x58<br>0x71<br>38.3<br>0x0E<br>0x27<br>0x40<br>0x59<br>0x72<br>42.2<br>0x0F<br>0x28<br>0x41<br>0x5A<br>0x73<br>46.4<br>0x10<br>0x29<br>0x42<br>0x5B<br>0x74<br>51.1<br>0x11<br>0x2A<br>0x43<br>0x5C<br>0x75<br>56.2<br>0x12<br>0x2B<br>0x44<br>0x5D<br>0x76<br>61.9<br>0x13<br>0x2C<br>0x45<br>0x5E<br>0x77<br>68.1<br>0x14<br>0x2D<br>0x46<br>0x5F<br>0x78<br>75.0<br>0x15<br>0x2E<br>0x47<br>0x60<br>0x79<br>82.5<br>0x16<br>0x2F<br>0x48<br>0x61<br>0x7A<br>90.9<br>0x17<br>0x30<br>0x49<br>0x62<br>0x7B<br>100.0<br>0x18<br>0x31<br>0x4A<br>0x63<br>0x7C<br>RSA0 (k�)<br>DISCONTINUED||| Air ow past the NDM2Z-50 module will assist in cooling the module. Factors affecting the ef ciency of the cooling include the rate, direction and temperature of the air ow. - Duty cycle **cui** .com Additional Resources: Product Page | 3D Model **CUI Inc � SERIES** : NDM2Z-50 **� DESCRIPTION** : AUTO COMPENSATED, DIGITAL DC-DC POL CONVERTER **date** 12/21/2015 **� page** 32 of 32 **REVISION HISTORY rev. date** 1.0 09/28/2015 1.1 12/16/2015 The revision history provided is for informational purposes only and is believed to be accurate. **Headquarters** 20050 SW 112th Ave. Fax 503.612.2383 Tualatin, OR 97062 **cui** .com **800.275.4899** techsupport@cui.com Architects of Modern Power and AMP Group are trademarks of CUI. Novum is a trademark of CUI. _PMBus_ is a trademark of SMIF, Inc. _Digital-DC is a trademark of Intersil Corporation. CUI Novum products use patented technology licensed from Power-One._ All other trademarks are the property of their respective owners. CUI offers a two (2) year limited warranty. Complete warranty information is listed on our website. CUI reserves the right to make changes to the product at any time without notice. Information provided by CUI is believed to be accurate and reliable. However, no responsibility is assumed by CUI for its use, nor for any infringements of patents or other rights of third parties which may result from its use. CUI products are not authorized or warranted for use as critical components in equipment that requires an extremely high level of reliability. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
Updated at April 26, 2026
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