NCL30030B2DR2G

LED Lighting Controller, 1 Output, Flyback, 9 V to 30 V in, 150 kHz switch, 210 V/4 A out, SOIC-16

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Manufacturer: ONSEMI
Product type: AC / DC LED Driver ICs
IC Mounting: Surface Mount
No. of Pins: 16Pins
No. of Outputs: 1Outputs
Device Topology: Flyback
Driver Case Style: SOIC
Input Voltage Max: 30V
Input Voltage Min: 9V
Output Current Max: 4A
Output Voltage Max: 210V
Switching Frequency: 150kHz
Operating Temperature Max: 125°C
Operating Temperature Min: -40°C
Delivery and price
Units per pack	500
Price	0.831 €
Current stock	1000+
Lead time	7 days
Datasheet
## NCL30030 

## Combination Power Factor Correction and Quasi-Resonant Flyback Controllers for LED Lighting 

This combination IC integrates power factor correction (PFC) and quasi−resonant flyback functionality necessary to implement a compact and highly efficient LED driver for high performance LED lighting applications. 

The PFC stage utilizes a proprietary multiplier architecture to achieve low harmonic distortion and near−unity power factor while operating in a Critical Conduction Mode (CrM). The circuit incorporates all the features necessary for building a robust and compact PFC stage while minimizing the number of external components. 

The quasi−resonant current−mode flyback stage features a proprietary valley−lockout circuitry, ensuring stable valley switching. This system works down to the 4[th] valley and toggles to a frequency foldback mode with a minimum frequency clamp beyond the 4[th] valley to eliminate audible noise. Skip mode operation allows excellent efficiency in light load conditions while consuming very low standby power consumption. 

## **Common General Features** 

- Wide VCC Range from 9 V to 30 V with Built−in Overvoltage Protection 

- High−Voltage Startup Circuit 

- Integrated High−Voltage Brown−Out Detector 

- Fault Input for Severe Fault Conditions, NTC Compatible (Latch and Auto−Recovery Options) 

- 0.5 A / 0.8 A Source / Sink Gate Drivers 

- Internal Temperature Shutdown 

## **www.onsemi.com** 

**SOIC−16 NB MISSING PIN 2 CASE 751DT** 

## **MARKING DIAGRAM** 

|1<br>16<br>PFB<br>BO/HV|
|---|
|NCL30030xy<br>AWLYWWG<br>GND<br>PCS/PZCD<br>PDRV<br>QDRV<br>QCS<br>VCC<br>QZCD<br>MULT<br>PControl<br>PONOFF<br>QCT<br>Fault<br>QFB|
|NCL30030 = Specific Device Code|
|x<br>= A or B<br>y<br>= 1, 2 or 3<br>A<br>= Assembly Location|
|WL<br>= Wafer Lot|
|Y<br>= Year<br>WW<br>= Work Week|
|G<br>= Pb−Free Package|



## **ORDERING INFORMATION** 

See detailed ordering and shipping information on page 31 of this data sheet. 

## **PFC Controller Features** 

- Critical Conduction Mode with a Multiplier 

- Accurate Overvoltage Protection 

- Optional Bi−Level Line−Dependent Output Voltage (2:1 / 1.77:1 Versions) 

- Fast Line / Load Transient Compensation 

- Boost Diode Short−Circuit Protection 

- Feed−Forward for Improved Operation across Line and Load 

- Adjustable PFC Disable Threshold Based on Output Power 

## **QR Flyback Controller Features** 

- Valley Switching Operation with Valley−Lockout for Noise−Free Operation 

- Frequency Foldback with Minimum Frequency Clamp for Highest Performance in Standby Mode 

- Minimum Frequency Clamp Eliminates Audible Noise 

- Timer−Based Overload Protection (Latched or Auto−Recovery options) 

- Adjustable Overpower Protection 

- Winding and Output Diode Short−Circuit Protection 

- 4 ms Soft−Start Timer 

- These are Pb−Free Devices 

## **Typical Applications** 

- High Power LED Drivers 

- Commercial LED ballasts 

- LED Signage Power Supplies 

- Adapters 

- Open Frame Power Supplies 

- LED Electronic Control Gear 

Publication Order Number: **NCL30030/D** 

**1** 

© Semiconductor Components Industries, LLC, 2015 **March, 2015 − Rev. 1** 

**NCL30030** 

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**----- Start of picture text -----**<br>
VZCD QCS<br>VCC<br>VZCD<br>PCS/PZCD PDRV QCS VCC<br>B<br>PF GND PCS/PZCD PDRV QDRV QCS VCC QZCD<br>BO/HV MULT PControl PONOFF QCT Fault QFB<br>U1 NCL30030<br>PDRV<br>PCS/PZCD<br>(Aux)<br>**----- End of picture text -----**<br>


**Figure 1. NCL30030 Typical Application Circuit** 

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**2** 

**NCL30030** 

**==> picture [481 x 651] intentionally omitted <==**

**----- Start of picture text -----**<br>
PUVP<br>Low/High Line<br>High Voltage BO/HV<br>PFB +− VPFB(disable) VPFB(HYS) Auto−recoveryVCC(reset)Latch QR_EN BrownoutVVCC_OKBO_BUF Detection, andStartupsLogic 1<br>16 PFC Central Reset<br>KPOVP(xL) OVP POVP Brownout Logic<br>� POVP(xL) Detection Low/High LineVCC_OK VCCOVPVCC_OK VCC Istart1/2 1 0 VCC<br>IPControl(boost) VCC(reset)VDD Management CCC<br>KLOW KLOW(HYS) QR_EN Soft−start VQILIM1<br>IEA<br>+ VQFB<br>VPREF(xL) − In Regulation QZCD<br>Soft−start<br>VPCONTROL(MAX) IPONOFF PONOFF<br>PControl<br>4 PUVP VCONTROL Disable PFC tPdisable 5<br>VPCONTROL(MIN) +<br>POVP VPONHYS −VPOFF<br>Disable PFC<br>PUVP<br>PSKIP Low/High Line QDRV<br>PSKIP PILIM1PILIM2 R Q QRDRV 12<br>+− � VPSKIPIn Regulation R DominantReset Q ton1x PFCDRV SDominantResetLatch Q t Q(toutx) Soft−startVQZCD<br>VPCONTROL S Latch Q QZCD<br>Low/High Line Multiplier Valley ZCD 9<br>VBO_BUF Detect<br>VQZCD(hys)<br>MULT<br>3 t delay(QSKIP) QSkip VQZCD(th)<br>Minimum VCO CT VQFB<br>Frequency Setpoint<br>LEB1 Oscillator QRDRV<br>PILIM1<br>+ IQCT QCT<br>VPILIM1 − VCO 6<br>PILIM2 tPFC(offx) QRDRV<br>PFCDRV Timer<br>ZCD PZCD QSkip IQFB RQFB<br>Detect Valley Valley QFB<br>+− VPZCD t onQR(MAX) QSkipVCO SelectLogic VQFB 8<br>PCS/PZCD QRDRV + /KQFB<br>14 LEB2<br>PILIM2<br>VPILIM2 + VQZCD GND<br>− TSD S 15<br>QOVLD S<br>PDRV nQILIM2 S<br>Latch<br>13 PFCDRV VCCOVPOVPOTP SSS LogicFault Auto−recovery QILIM1 LEB1<br>QOVLD t QOVLD<br>IOTP Brownout R<br>Fault OVP VCC(reset) R VQZCD +<br>7 VFault(OVP) Temperature TSD QILIM2 VQILIM1 IQCS QCS<br>OTP LEB2 11<br>nQILIM2 Counter<br>VFault(OTP_in)<br>VQILIM2<br>IPCS/PZCD<br>+<br>−<br>+<br>−<br>+<br>−<br>**----- End of picture text -----**<br>


**Figure 2. NCL30030 Functional Block Diagram** 

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**3** 

**NCL30030** 

## **Table 1. PIN FUNCTION DESCRIPTION** 

|**Pin Out**|**Name**|**Function**|
|---|---|---|
|1|BO/HV|Performs input brown−out detection and line voltage range detection.|
|2||Removed for creepage distance.|
|3|MULT|This is the output of the multiplication of the BO and Control signals. A capacitor should be put on this<br>pin for filtering. Suggested values from 1 nF − 20 nF.|
|4|PControl|Output of the PFC transconductance error amplifier. A compensation network is connected between<br>this pin and ground to set the loop bandwidth.|
|5|PONOFF|A resistor between this pin and ground sets the PFC turn off threshold. The voltage on this pin is<br>compared to an internal voltage signal proportional to the output power. The PFC disabled threshold<br>is determined by the resistor on this pin and the internal pull–up current source, IPONOFF.|
|6|QCT|An external capacitor sets the frequency in VCO mode for the QR flyback controller.|
|7|Fault|The controller enters fault mode if the voltage of this pin is pulled above or below the fault thresholds.<br>A precise pull up current source allows direct interface with an NTC thermistor. Fault detection trig-<br>gers a latch or auto−recovery depending on device option.|
|8|QFB|Feedback input for the QR Flyback controller. Allows direct connection to an optocoupler.|
|9|QZCD|Input to the demagnetization detection comparator for the QR Flyback controller. Also used to set the<br>overpower compensation.|
|10|VCC|Supply input.|
|11|QCS|Input to the cycle−by−cycle current limit comparator for the QR Flyback section.|
|12|QDRV|QR flyback controller switch driver.|
|13|PDRV|PFC controller switch driver.|
|14|PCS/PZCD|Input to the cycle−by−cycle current limit comparator for the PFC section. Also used to perform the<br>demagnetization detection for the PFC controller.|
|15|GND|Ground reference.|
|16|PFB|PFC feedback input from external resistor divider used to sense the PFC bulk voltage. This pin volt-<br>age is compared to an internal reference. There are three different reference voltage combinations<br>depending on ac mains voltage and version of the part.|



**Table 2. NCL30030 DEVICE OPTIONS** 

|**Device**|**Flyback Overload Protection**|**Fault OTP**|**PFC Reference Voltage**<br>**(High Line / Low Line)**|
|---|---|---|---|
|NCL30030B1DR2G|Auto−Recovery|Auto−Recovery|3.55 / 2 V|
|NCL30030B2DR2G|Auto−Recovery|Auto−Recovery|4 / 2 V|
|NCL30030B3DR2G|Auto−Recovery|Auto−Recovery|4 / 4 V|
|NCL30030A1DR2G*|Latch|Latch|3.55 / 2 V|
|NCL30030A2DR2G*|Latch|Latch|4 / 2 V|
|NCL30030A3DR2G*|Latch|Latch|4 / 4 V|



*Please contact local sales representative for availability 

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**4** 

**NCL30030** 

**Table 3. MAXIMUM RATINGS** (Notes 1 through 6 ) 

|**Table 3. MAXIMUM RATINGS**(Notes 1 through6)|||||
|---|---|---|---|---|
|**Rating**|**Pin**|**Symbol**|**Value**|**Unit**|
|High Voltage Brownout Detector Input Voltage|1|VBO/HV|−0.3 to 700|V|
|High Voltage Brownout Detector Input Current|1|IBO/HV|20|mA|
|PFC Low Voltage Feedback Input Voltage|16|VPFB|−0.3 to 9|V|
|PFC Low Voltage Feedback Input Current|16|IPFB|0.5|mA|
|PFC Zero Current Detection and Current Sense Input Voltage (Note 1)|14|VPCS/PZCD|−0.3 to VPCS/PZCD(MAX)|V|
|PFC Zero Current Detection and Current Sense Input Current|14|IPCS/PZCD|−2/+5|mA|
|PFC Control Input Voltage|4|VPControl|−0.3 to 5|V|
|PFC Control Input Current|4|IPControl|10|mA|
|Supply Input Voltage|10|VCC(MAX)|−0.3 to 30|V|
|Supply Input Current|10|ICC(MAX)|30|mA|
|Supply Input Voltage Slew Rate|10|dVCC/dt|1|V/�s|
|Fault Input Voltage|7|VFault|−0.3 to (VCC+ 1.25)|V|
|Fault Input Current|7|IFault|10|mA|
|PFC Multiplier pin|3|VMULT|−0.3 to 10|V|
|PFC Multiplier pin|3|IMULT|3|mA|
|QR Flyback Zero Current Detection Input Voltage|9|VQZCD|−0.9 to (VCC+ 1.25)|V|
|QR Flyback Zero Current Detection Input Current|9|IQZCD|−2/+5|mA|
|QR Feedback Input Voltage|6|VQCT|−0.3 to 10|V|
|QR Feedback Input Current|6|IQCT|10|mA|
|QR Flyback Current Sense Input Voltage|11|VQCS|−0.3 to 10|V|
|QR Flyback Current Sense Input Current|11|IQCS|10|mA|
|QR Flyback Feedback Input Voltage|8|VQFB|−0.3 to 10|V|
|QR Flyback Feedback Input Current|8|IQFB|10|mA|
|PFC Driver Maximum Voltage (Note 2)|13|VPDRV|−0.3 to VPDRV(high2)|V|
|PFC Driver Maximum Current|13|IPDRV(SRC)<br>IPDRV(SNK)|500<br>800|mA|
|Flyback Driver Maximum Voltage (Note 2)|12|VQDRV|−0.3 to VQDRV(high2)|V|
|Flyback Driver Maximum Current|12|IQDRV(SRC)<br>IQDRV(SNK)|500<br>800|mA|
|PFC ON/OFF Threshold Adjust Input Voltage|5|VPONOFF|−0.3 to 10|V|
|PFC ON/OFF Threshold Adjust Input Current|5|IPONOFF|10|mA|
|Operating Junction Temperature|N/A|TJ|−40 to 125|°C|
|Storage Temperature Range|N/A|TSTG|–60 to 150|°C|



Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 

1. VPCS/PZCD(MAX) is the maximum voltage of the pin shown in the electrical table. When the voltage on this pin exceeds 5 V, the pin sinks a current equal to (VPCS/PZCD − 5 V)/(2 k � ). A VPSC/PZCD of 7 V generates a sink current of approximately 1 mA. 

2. Maximum driver voltage is limited by the driver clamp voltage, VXDRV(high2), when VCC exceeds the driver clamp voltage. Otherwise, the maximum driver voltage is VCC. 

3. Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum–rated conditions is not implied. Functional operation should be restricted to the Recommended Operating Conditions. 

4. This device contains Latch−up protection and has been tested per JEDEC JESD78D, Class I and exceeds +100/−100 mA. 5. Low Conductivity Board. As mounted on 80 x 100 x 1.5 mm FR4 substrate with a single layer of 50 mm[2] of 2 oz copper traces and heat spreading area. As specified for a JEDEC51−1 conductivity test PCB. Test conditions were under natural convection of zero air flow. 

6. Pin 1 is rated to the maximum voltage of the part, or 700 V. 

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**5** 

**NCL30030** 

**Table 3. MAXIMUM RATINGS** (Notes 1 through 6 ) 

|**Table 3. MAXIMUM RATINGS**(Notes 1 through6)||||
|---|---|---|---|
|**Rating**|**Symbol**|**Value**|**Unit**|
|Power Dissipation (TA= 75°C, 1 Oz Cu, 0.155 Sq Inch Printed Circuit Copper<br>Clad) Plastic Package SOIC−16NB|PD|550|mW|
|Thermal Resistance, Junction to Ambient 1 Oz Cu Printed Circuit Copper Clad)<br>Plastic Package SOIC−16NB|R�JA|145|°C/W|
|ESD Capability (Note 6)<br>Human Body Model per JEDEC Standard JESD22−A114F.<br>Machine Model per JEDEC Standard JESD22−A115−A.<br>Charge Device Model per JEDEC Standard JESD22−C101E.|HBM<br>MM<br>CDM|3000<br>200<br>750|V|



Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 

1. VPCS/PZCD(MAX) is the maximum voltage of the pin shown in the electrical table. When the voltage on this pin exceeds 5 V, the pin sinks a current equal to (VPCS/PZCD − 5 V)/(2 k � ). A VPSC/PZCD of 7 V generates a sink current of approximately 1 mA. 

2. Maximum driver voltage is limited by the driver clamp voltage, VXDRV(high2), when VCC exceeds the driver clamp voltage. Otherwise, the maximum driver voltage is VCC. 

3. Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum–rated conditions is not implied. Functional operation should be restricted to the Recommended Operating Conditions. 

4. This device contains Latch−up protection and has been tested per JEDEC JESD78D, Class I and exceeds +100/−100 mA. 

5. Low Conductivity Board. As mounted on 80 x 100 x 1.5 mm FR4 substrate with a single layer of 50 mm[2] of 2 oz copper traces and heat spreading area. As specified for a JEDEC51−1 conductivity test PCB. Test conditions were under natural convection of zero air flow. 

6. Pin 1 is rated to the maximum voltage of the part, or 700 V. 

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**6** 

## **NCL30030** 

**Table 4. ELECTRICAL CHARACTERISTICS** : (VCC = 12 V, VBO/HV = 120 V, VFault = open, VPFB = 1.9 V, VPControl = 4 V, VPCS/PZCD = 0 V, VQFB = 3 V, VPONOFF = 4 V, VQCS = 0 V, VQZCD = 0 V, CMULT = 2 nF, CVCC = 100 nF , CQCT = 220 pF, CPDRV = 1 nF, CQDRV = 1 nF, for typical values TJ = 25 ° C, for min/max values, TJ is – 40 ° C to 125 ° C, unless otherwise noted) 

|CQDRV= 1 nF, for typical values TJ=|25°C, for min/max values, TJis – 40°|C to 125|°C, unless otherw|ise noted|)|||
|---|---|---|---|---|---|---|---|
|**Characteristics**|**Conditions**|**Pin**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|
|**STARTUP AND SUPPLY CIRCUITS**||||||||
|Supply Voltage<br>Startup Threshold<br>Minimum Operating Voltage<br>Operating Hysteresis<br>Internal Latch / Logic Reset Level<br>Transition from Istart1to Istart2|VCCincreasing<br>VCCdecreasing<br>VCC(on)− VCC(off)<br>VCCdecreasing<br>VCCincreasing, IHV/HV= 650�A|10|VCC(on)<br>VCC(off)<br>VCC(HYS)<br>VCC(reset)<br>VCC(inhibit)|16<br>8.2<br>7.7<br>4.5<br>0.3|17<br>8.8<br>–<br>5.5<br>0.7|18<br>9.4<br>–<br>7.5<br>0.95|V|
|Blanking Duration After VCC(off)||10|tUVLO(blank)|3|–|25|�s|
|Startup Current in Inhibit Mode|VCC= 0 V|10|Istart1A|0.20|0.50|0.65|mA|
|Startup Current<br>Operating Mode|VCC= VCC(on)– 0.5 V,<br>VBO/HV= 100 V|10|Istart2A|2.5|−|5|mA|
|Minimum Startup Voltage|Istart2A= 1 mA, VCC= VCC(on)– 0.5 V|1|VBO/HV(MIN)|–|–|40|V|
|VCCOvervoltage Protection Threshold||10|VCC(OVP)|27|28|29|V|
|VCCOvervoltage Protection Delay||10|tdelay(VCC_OVP)|20.0|30.0|40.0|�s|
|Supply Current<br>Before Startup, Fault or Latch<br>Flyback in Skip, PFC Disabled<br>Flyback in Skip, PFC in Skip<br>Flyback Enabled, QDRV Low, PFC<br>Disabled<br>Flyback Enabled, QDRV Low, PFC in<br>Skip<br>PFC and Flyback switching at 70 kHz<br>PFC and Flyback switching at 70 kHz|VCC= VCC(on)– 0.5 V<br>VQFB= 0.35 V<br>VQFB= 0.35 V, VPControl< VPSKIP<br>VQZCD= 1 V<br>VQZCD= 1 V, VPControl< VPSKIP<br>CQDRV= CPDRV= open|10|ICC2<br>ICC3a<br>ICC3b<br>ICC4<br>ICC5<br>ICC6<br>ICC7|−<br>−<br>−<br>−<br>−<br>−<br>−|0.15<br>0.3<br>0.5<br>0.85<br>1.1<br>1.5<br>2.8|0.28<br>0.43<br>1.03<br>1.38<br>1.83<br>4.03<br>5.23|mA|
|**BROWN−OUT DETECTION**||||||||
|System Startup Threshold|VBO/HVincreasing|1|VBO(start)|102|111|120|V|
|System Shutdown Threshold|VBO/HVdecreasing|1|VBO(stop)|86|101|116|V|
|Brown−out Hysteresis|VBO/HVincreasing|1|VBO(hys)|4|−|16|V|
|Brown−out Detection Blanking Time|VBO/HVdecreasing, duration below<br>VBO(stop)for a Brown−out fault|1|tBO(stop)|43|54|65|ms|
|Brown−out Drive Disable Threshold|VBO/HVdecreasing, threshold to<br>disable drive|1|VBO(DRV_disable)|20|30|40|V|
|Line Level Detection Threshold|VBO/HVincreasing|1|Vlineselect|216|240|264|V|
|High to Low Line Mode Selector Timer|VBO/HVdecreasing|1|thigh to low line|43|54|65|ms|
|Low to High Line Mode Selector Timer|VBO/HVincreasing|1|tlow to high line|200|350|450|�s|
|Brownout Pin Off State Leakage<br>Current|VBO/HV= 500 V|1|IBO/HV(off)|–|–|42|�A|
|**PFC MAXIMUM OFF TIME TIMER**||||||||
|Maximum Off Time|VPCS/PZCD> VPILIM2|13|tPFC(off1)<br>tPFC(off2)|100<br>700|200<br>1000|300<br>1300|�s|
|**PFC CURRENT SENSE**||||||||
|Fixed Cycle by Cycle Current Sense<br>Threshold||14|VPILIM1|1.35|1.5|1.65|V|
|Cycle by Cycle Leading Edge Blanking<br>Duration||14|tPCS(LEB1)|250|325|400|ns|
|Cycle by Cycle Current Sense<br>Propagation Delay||14|tPCS(delay1)|−|100|400|ns|
|Abnormal Overcurrent Fault Threshold||14|VPILIM2|1.8|2|2.2|V|
|Abnormal Overcurrent Fault Leading<br>Edge Blanking Duration||14|tPCS(LEB2)|100|175|250|ns|
|Abnormal Overcurrent Fault<br>Propagation Delay||14|tPCS(delay2)|−|100|200|ns|



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 

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**7** 

## **NCL30030** 

**Table 4. ELECTRICAL CHARACTERISTICS** : (VCC = 12 V, VBO/HV = 120 V, VFault = open, VPFB = 1.9 V, VPControl = 4 V, VPCS/PZCD = 0 V, VQFB = 3 V, VPONOFF = 4 V, VQCS = 0 V, VQZCD = 0 V, CMULT = 2 nF, CVCC = 100 nF , CQCT = 220 pF, CPDRV = 1 nF, CQDRV = 1 nF, for typical values TJ = 25 ° C, for min/max values, TJ is – 40 ° C to 125 ° C, unless otherwise noted) 

|CQDRV= 1 nF, for typical values TJ=|25°C, for min/max values, TJis – 40°|C to 125|°C, unless otherw|ise noted|)|||
|---|---|---|---|---|---|---|---|
|**Characteristics**|**Conditions**|**Pin**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|
|**PFC CURRENT SENSE**||||||||
|Multipler Cycle by Cycle Current Sense<br>Offset|BO = 180, PFB = 1.5 V|14|VPILIM_MULT|−12|−|10|mV|
|Multiplier Cycle by Cycle Current Sense<br>Propagation Delay|BO = 180 V, PFB = 1.5 V|14|tPCS(delay_mult)|10|100|200|ns|
|Pull−up Current Source|VPCS/PZCD= 2.5 V|14|IPCS/PZCD|0.7|1.0|1.3|�A|
|**PFC REGULATION BLOCK**||||||||
|PFC Reference Voltage<br>See Table 2 for Options|VBO/HV> VBO(lineselect)<br>VBO/HV< VBO(lineselect)|16|VPREF(HL)<br>VPREF(LL)|3.47<br>3.92<br>1.95<br>3.92|3.55<br>4.00<br>2<br>4|3.62<br>4.08<br>2.05<br>4.08|V|
|Error Amplifier Current<br>Source<br>Sink<br>Source<br>Sink|PFC Enabled<br>VPFB= 0.96 x VPREF(HL)<br>VPFB= 1.04 x VPREF(HL)<br>VPFB= 0.96 x VPREF(LL)<br>VPFB= 1.04 x VPREF(LL)|4|IEA(SRCHL)<br>IEA(SNKHL)<br>IEA(SRCLL)<br>IEA(SNKLL)|16<br>16<br>10<br>10|32<br>32<br>20<br>20|48<br>48<br>30<br>30|�A|
|Open Loop Error Amplifier<br>Transconductance|VPFB= VPREF(LL)+/− 4 %<br>VPFB= VPREF(HL)+/− 4 %|4|gm<br>gm_HL|100<br>100|200<br>200|300<br>300|�S|
|Maximum Control Voltage|VPFB* KLOW(PFCxL),<br>CPControl= 10 nF|4|VPControl(MAX)|–|4.5|–|V|
|Minimum Control Voltage (Lower<br>clamp)|VPFB* KPOVP(xL), CPControl= 10 nF|4|VPControl(MIN)|–|0.6|–|V|
|EA Output Control Voltage Range|VPControl(MAX)− VPControl(MIN)|4|�VPControl|3.7|3.9|4.1|V|
|Ratio between the VoutLow Detect<br>Threshold and the Regulation Level|VPFBdecreasing, VBOOST/ VPREF(HL)<br>VPFBdecreasing, VBOOST/ VPREF(LL)|16|KLOW(PFCHL)<br>KLOW(PFCLL)|0.940<br>0.940|0.945<br>0.945|0.950<br>0.950||
|Ratio between the VoutLow Exit<br>Threshold and the Regulation Level|VPFBincreasing|16|KLOW(HYSHL)<br>KLOW(HYSLL)|0.950<br>0.950|0.960<br>0.960|0.965<br>0.965||
|Source Current During VoutLow Detect||4|IPControl(boost)|190|240|290|�A|
|PFC In Regulation Threshold|VPControlincreasing|4|IIn_Regulation|−6.5|–|0|�A|
|Resistance of Internal Pull Down Switch|IPControl= 5 mA|4|RPControl|4|25|50|�|
|**PFC SKIP MODE**||||||||
|Delta Between Skip Level and Lower<br>Clamp PControl Voltages|VPControldecreasing, measured from<br>VPControl(MIN)|4|�VPSKIP|5|25|50|mV|
|PFC Skip Hysteresis|VPControlincreasing|4|VPSKIP(HYS)|25|50|75|mV|
|Delay Exiting Skip Mode|Apply 1 V step fromVPControl(MIN)|4|tdelay(PSKIP)|–|50|60|�s|
|**PFC FAULT PROTECTION**||||||||
|Ratio between the Hard Overvoltage<br>Protection Threshold and Regulation<br>Level|VPFBincreasing<br>KPOVP(LL)= VPFB/VPREF(LL)<br>KPOVP(HL)= VPFB/VPREF(HL)|16|KPOVP(LL)<br>KPOVP(HL)|1.06<br>1.05|1.08<br>1.06|1.10<br>1.08||
|Soft Overvoltage Protection Threshold|VPSOVP(LL)= soft overvoltage level<br>�POVP(LL)= KPOVP*VPREF(LL)−<br>VPSOVP(LL)<br>�POVP(HL)= KPOVP*VPREF(HL)−<br>VPSOVP(HL)|16|�POVP(LL)<br>�POVP(HL)|20<br>20|–<br>–|55<br>55|mV|
|PFC Feedback Pin Disable Threshold|VPFBdecreasing|16|VPFB(disable)|0.225|0.30|0.35|V|
|PFC Feedback Pin Enable Threshold|VPFBincreasing|16|VPFB(enable)|0.275|0.35|0.40|V|
|PFC Feedback Pin Hysteresis|VPFBincreasing|16|VPFB(HYS)|25|50|−|mV|
|PFC Feedback Disable Delay||16|tdelay(PFB)|20|30|40|�s|
|**PFC ON TIME CONTROL**||||||||
|PFC Maximum On|VPControl= VPControl(MAX)<br>VBO/HV= 163 V<br>VBO/HV= 325 V|13|ton1a<br>ton1b|12.5<br>4.25|15<br>5.00|17.5<br>5.75|�s|



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 

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**8** 

**NCL30030** 

**Table 4. ELECTRICAL CHARACTERISTICS** : (VCC = 12 V, VBO/HV = 120 V, VFault = open, VPFB = 1.9 V, VPControl = 4 V, VPCS/PZCD = 0 V, VQFB = 3 V, VPONOFF = 4 V, VQCS = 0 V, VQZCD = 0 V, CMULT = 2 nF, CVCC = 100 nF , CQCT = 220 pF, CPDRV = 1 nF, CQDRV = 1 nF, for typical values TJ = 25 ° C, for min/max values, TJ is – 40 ° C to 125 ° C, unless otherwise noted) 

|CQDRV= 1 nF, for typical values TJ=|25°C, for min/max values, TJis – 40°|C to 125|°C, unless otherw|ise noted|)|||
|---|---|---|---|---|---|---|---|
|**Characteristics**|**Conditions**|**Pin**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|
|**PFC DISABLE**||||||||
|Voltage to Current Conversion Ratio|VQFB= 3 V, Low Line<br>VQFB= 3 V, High Line|5|Iratio1(QFB/PON)<br>Iratio2(QFB/PON)|13<br>13|15<br>15|17<br>17|�A|
|PFC Disable Threshold|VPONOFFdecreasing|5|VPOFF|1.9|2.0|2.1|V|
|PFC Enable Hysteresis|VQFB= increasing|5|VPONHYS|0.135|0.160|0.185|V|
|PONOFF Operating Mode Voltage|tdemag/T = 70%,<br>RPONOFF= 191 k�, CPONOFF= 1 nF<br>VQFB= 1.8 V (decreasing)<br>VQFB= 3 V (decreasing)|5|VPONOFF1<br>VPONOFF2|1.08<br>1.8|1.20<br>2.0|1.32<br>2.2|V|
|PFC Disable Timer|Disable Timer|5|tPdisable|450|500|550|ms|
|PFC Enable Filter Delay||5|tPenable(filter)|50|100|150|�s|
|PFC Enable Timer|PONOFF Increasing|5|tPenable|200|–|500|�s|
|**PFC MULTIPLIER**||||||||
|Multiplier maximum BO=180V|PControl = open, BO = 180 V|3|MULT_max_180|0.85|1|1.15|V|
|Multiplier maximum BO = 360V|PControl = open, BO = 360 V|3|MULT_max_360|0.425|0.5|0.575|V|
|Multiplier output|PControl = 2.5 V, BO = 180 V|3|VmultLL|0.425|0.5|0.575|V|
|Multiplier output|PControl = 2.5 V, BO = 360 V|3|VmultHL|0.2125|0.25|0.2875|V|
|Multiplier linearity with respect to BO at<br>low line.<br>(VMULT180/180V)/(VMULT120/120V)|PControl = 2.5 V, BO = 180 V and<br>BO = 120 V|3|Mult_linearityLL|0.98|1|1.02||
|Multiplier linearity with respect to BO at<br>high line.<br>(VMULT360/360V)/VMULT300/300V)|PControl = 2.5 V, BO = 360 V and BO<br>= 300 V|3|Mult_linearityHL|0.99|1|1.01||
|**PFC GATE DRIVE**||||||||
|Rise Time (10−90%)|VPDRVfrom 10% to 90% of VCC|13|tPDRV(rise)|–|40|80|ns|
|Fall Time (90−10%)|90% to 10% of VPDRV|13|tPDRV(fall)|–|20|40|ns|
|Driver Resistance<br>Source<br>Sink||13|RPDRV(SRC)<br>RPDRV(SNK)|−<br>−|13<br>7|−<br>−|�|
|Current Capability<br>Source<br>Sink|VPDRV= 2 V<br>VPDRV= 10 V|13|IPDRV(SRC)<br>IPDRV(SNK)|–<br>–|500<br>800|–<br>–|mA|
|High State Voltage|VCC= VCC(off)+ 0.2 V, RPDRV= 10 k�<br>VCC= 26 V, RPDRV= 10 k�|13|VPDRV(high1)<br>VPDRV(high2)|8<br>10|–<br>12|–<br>14|V|
|Low State Voltage|VFault= 4 V|13|VPDRV(low)|–|–|0.25|V|
|**PFC ZERO CURRENT DETECTION**||||||||
|Zero Current Detection Threshold|VPCS/PZCDrising<br>VPCS/PZCDfalling|14|VPZCD(rising)<br>VPZCD(falling)|675<br>200|750<br>250|825<br>300|mV|
|Hysteresis on Voltage Threshold|VPZCD(rising)– VPZCD(falling)|14|VPZCD(HYS)|375|500|625|mV|
|Propagation Delay|Measure from VPCS/PZCD=<br>VPZCD(falling)to PDRV rising|14|tPZCD|50|100|170|ns|
|Input Voltage Excursion<br>Upper Clamp<br>Negative Clamp|IPCS/PZCD= 1 mA<br>IPCS/PZCD= −2 mA|14|VPCS/PZCD(MAX)<br>VPCS/PZCD(MIN)|6.5<br>−0.9|7<br>−0.7|7.5<br>0|V|
|Minimum detectable ZCD Pulse Width|BetweenVPZCD(rising)and<br>VPZCD(falling) to PDRV|14|tSYNC|–|70|200|ns|
|ZCD blanking time|Measured DRV off to DRV on|14|TPzcd_blank|450|700|1000|ns|
|**QR FLYBACK GATE DRIVE**||||||||
|Rise Time (10−90%)|VQDRVfrom 10 to 90%|12|tQDRV(rise)|–|40|80|ns|



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 

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**9** 

## **NCL30030** 

**Table 4. ELECTRICAL CHARACTERISTICS** : (VCC = 12 V, VBO/HV = 120 V, VFault = open, VPFB = 1.9 V, VPControl = 4 V, VPCS/PZCD = 0 V, VQFB = 3 V, VPONOFF = 4 V, VQCS = 0 V, VQZCD = 0 V, CMULT = 2 nF, CVCC = 100 nF , CQCT = 220 pF, CPDRV = 1 nF, CQDRV = 1 nF, for typical values TJ = 25 ° C, for min/max values, TJ is – 40 ° C to 125 ° C, unless otherwise noted) 

|CQDRV= 1 nF, for typical values TJ=|25°C, for min/max values, TJis – 40°|C to 125|°C, unless otherw|ise noted|)|||
|---|---|---|---|---|---|---|---|
|**Characteristics**|**Conditions**|**Pin**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|
|**QR FLYBACK GATE DRIVE**||||||||
|Fall Time (90−10%)|90 to 10% of VQDRV|12|tQDRV(fall)|–|20|40|ns|
|Driver Resistance<br>Source<br>Sink||12|RQDRV(SRC)<br>RQDRV(SNK)|−<br>−|13<br>7|−<br>−|�|
|Current Capability<br>Source<br>Sink|VQDRV= 2 V<br>VQDRV= 10 V|12|IQDRV(SRC)<br>IQDRV(SNK)|–<br>–|500<br>800|–<br>–|mA|
|High State Voltage|VCC= VCC(off)+ 0.2 V, RQDRV= 10 k�<br>VCC= 26 V, RQDRV= 10 k�|12|VQDRV(high1)<br>VQDRV(high2)|8<br>10|–<br>12|–<br>14|V|
|Low State Voltage|VFault= 4 V|12|VQDRV(low)|–|–|0.25|V|
|**QR FLYBACK FEEDBACK**||||||||
|Internal Pull−Up Current Source||8|IQFB|46.75|50|53.25|�A|
|Feedback Input Open Voltage||8|VQFB(open)|4.5|5.0|5.5|V|
|VQFBto Internal Current Setpoint<br>Division Ratio||8|KQFB|3.8|4.0|4.2||
|QFB Pull Up Resistor|VQFB= 0.4 V|8|RQFB|340|400|460|k�|
|Valley Thresholds<br>Transition from 1stto 2ndvalley<br>Transition from 2ndto 3rdvalley<br>Transition from 3rdto 4thvalley<br>Transition from 4thvalley to VCO<br>Transition from VCO to 4thvalley<br>Transition from 4thto 3rdvalley<br>Transition from 3rdto 2ndvalley<br>Transition from 2ndto 1stvalley|VQFBdecreasing<br>VQFBdecreasing<br>VQFBdecreasing<br>VQFBdecreasing<br>VQFBincreasing<br>VQFBincreasing<br>VQFBincreasing<br>VQFBincreasing|8|VH2D<br>VH3D<br>VH4D<br>VHVCOD<br>VHVCOI<br>VH4I<br>VH3I<br>VH2I|1.316<br>1.128<br>0.846<br>0.752<br>1.316<br>1.504<br>1.692<br>1.880|1.400<br>1.200<br>0.900<br>0.800<br>1.400<br>1.600<br>1.800<br>2.000|1.484<br>1.272<br>0.954<br>0.848<br>1.484<br>1.696<br>1.908<br>2.120|V|
|Skip Threshold|VQFBdecreasing|8|VQSKIP|0.35|0.40|0.45|V|
|Skip Hysteresis|VQFBincreasing|8|VQSKIP(HYS)|25|50|75|mV|
|Delay Exiting Skip Mode to 1stQDRV<br>Pulse|Apply 1 V step from VQSKIP|8|tdelay(QSKIP)|–|–|10|�s|
|Maximum On Time||12|tonQR(MAX)|26|32|38|�s|
|**QR FLYBACK TIMING CAPACITOR**||||||||
|QCT Operating Voltage Range|VQFB= 0.5 V|6|VQCT(peak)|3.815|4.000|4.185|V|
|On Time Control Source Current|VQCT= 0 V|6|IQCT|18|20|22|�A|
|Minimum voltage on QCT Input||6|VQCT(min)|–|–|90|mV|
|Minimum Operating Frequency in VCO<br>Mode|VQCT= VQCT(peak)+ 100 mV|6|fVCO(MIN)|23.5|27|30.5|kHz|
|**QR FLYBACK DEMAGNETIZATION INPUT**||||||||
|QZCD threshold voltage|VQZCDdecreasing|9|VQZCD(th)|35|55|90|mV|
|QZCD hysteresis|VQZCDincreasing|9|VQZCD(HYS)|15|35|55|mV|
|Demagnetization Propagation Delay|VQZCDstep from 4.0 V to −0.3 V|9|tDEM|–|150|250|ns|
|Input Voltage Excursion<br>Upper Clamp<br>Negative Clamp|IQZCD= 5.0 mA<br>IQZCD= −2.0 mA|9|VQZCD(MAX)<br>VQZCD(MIN)|12.4<br>−0.9|12.7<br>−0.7|13.5<br>0|V|
|Blanking Delay After Turn−Off||9|tZCD(blank)|2|3|4|�s|
|Timeout After Last Demagnetization<br>Detection|During soft−start<br>After soft−start|12|tQ(tout1)<br>tQ(tout2)|80<br>5.1|100<br>6|120<br>6.9|�s|
|**QR FLYBACK CURRENT SENSE**||||||||
|Current Sense Voltage Threshold|VQCSincreasing<br>VQCSincreasing, VQZCD= 1 V|11|VQILIM1a<br>VQILIM1b|0.760<br>0.760|0.800<br>0.800|0.840<br>0.840|V|



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 

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**10** 

## **NCL30030** 

**Table 4. ELECTRICAL CHARACTERISTICS** : (VCC = 12 V, VBO/HV = 120 V, VFault = open, VPFB = 1.9 V, VPControl = 4 V, VPCS/PZCD = 0 V, VQFB = 3 V, VPONOFF = 4 V, VQCS = 0 V, VQZCD = 0 V, CMULT = 2 nF, CVCC = 100 nF , CQCT = 220 pF, CPDRV = 1 nF, CQDRV = 1 nF, for typical values TJ = 25 ° C, for min/max values, TJ is – 40 ° C to 125 ° C, unless otherwise noted) 

|CQDRV= 1 nF, for typical values TJ=|25°C, for min/max values, TJis – 40°|C to 125|°C, unless otherw|ise noted|)|||
|---|---|---|---|---|---|---|---|
|**Characteristics**|**Conditions**|**Pin**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|
|**QR FLYBACK CURRENT SENSE**||||||||
|Cycle by Cycle Leading Edge Blanking<br>Duration|Minimum on time minus tdelay(ILIM_QR)|11|tQCS(LEB1)|220|275|350|ns|
|Cycle by Cycle Current Sense<br>Propagation Delay||11|tQCS(delay1)|–|125|175|ns|
|Immediate Fault Protection Threshold|VQCSincreasing, VQFB= 4 V|11|VQILIM2|1.125|1.200|1.275|V|
|Abnormal Overcurrent Fault Leading<br>Edge Blanking Duration||11|tQCS(LEB2)|90|120|150|ns|
|Abnormal Overcurrent Fault<br>Propagation Delay||11|tQCS(delay2)|–|125|175|ns|
|Number of Consecutive Abnormal<br>Overcurrent Detections to Enter Fault<br>Mode||11|nQILIM2|–|4|–||
|Minimum Peak Current Level in VCO<br>Mode|VQFB= 0.4 V, VQCSincreasing|11|Ipeak(VCO)|11|12.5|14|%|
|Set point decrease for VQZCD=<br>−250 mV|VQCSIncreasing, VQFB= 4 V|11|VOPP(MAX)|28|31.25|33|%|
|Overpower Protection Delay||11|tQOPP(delay)|–|125|175|ns|
|Pull−up Current Source|VQCS= 1.5 V|11|IQCS|0.7|1.0|1.3|�A|
|**QR FLYBACK FAULT PROTECTION**||||||||
|Soft−Start Period|Measured from 1stQDRV pulse to<br>VQCS= VQILIM1|11|tSSTART|2.8|4.0|5.0|ms|
|Flyback Overload Fault Timer|VQCS= VQILIM1|11|tQOVLD|60|80|100|ms|
|**COMMON FAULT PROTECTION**||||||||
|Overvoltage Protection (OVP)<br>Threshold|VFaultincreasing|7|VFault(OVP)|2.79|3.00|3.21|V|
|Delay Before Fault Confirmation<br>Used for OVP Detection<br>Used for OTP Detection|VFaultincreasing<br>VFaultdecreasing|7|tdelay(Fault_OVP)<br>tdelay(Fault_OTP)|22.5<br>22.5|30.0<br>30.0|37.5<br>37.5|�s|
|Overtemperature Protection (OTP)<br>Threshold (Note 7)|VFaultdecreasing|7|VFault(OTP_in)|0.38|0.40|0.42|V|
|Overtemperature Protection (OTP)<br>Exiting Threshold (Note 7)|VFaultincreasing,B version|7|VFault(OTP_out)|0.874|0.920|0.966|V|
|OTP Pull−up Current Source (Note 7)|VFault= VFault(OTP_in)+ 0.2 V|7|IFault(OTP)|42.5|45.5|48.5|�A|
|Fault Input Clamp Voltage|VFault= open|7|VFault(clamp)|1.5|1.75|2.0|V|
|Fault Input Clamp Series Resistor||7|RFault(clamp)|1.32|1.55|1.82|k�|
|7. NTC with R110= 8.8 k�(TTC03-474)]<br>**THERMAL PROTECTION**||||||||
|Thermal Shutdown|Temperature increasing|N/A|TSHDN|−|150|−|°C|
|Thermal Shutdown Hysteresis|Temperature decreasing|N/A|TSHDN(HYS)|−|40|−|°C|



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 

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**11** 

**NCL30030** 

## **DETAILED OPERATING DESCRIPTION** 

## **INTRODUCTION** 

The NCL30030 is a combination critical mode (CrM) power factor correction (PFC) and quasi−resonant (QR) flyback controller optimized for high performance LED driver applications. 

## **HIGH VOLTAGE STARTUP CIRCUIT** 

The NCL30030 integrates a high voltage startup circuit accessible by the BO/HV pin. The BO/HV input is also used for monitoring the ac line voltage and detecting brown−out faults. The startup circuit is rated at a maximum voltage of 700 V to support higher voltages used in commercial lighting such as 277 and 347 VAC. 

A startup regulator consists of a constant current source that supplies current from the ac input terminals (Vin) to the supply capacitor on the VCC pin (CCC). The startup circuit current (Istart2A) is typically 3.75 mA. Istart2A is disabled if the VCC pin is below VCC(inhibit). In this condition the startup current is reduced to Istart1A, typically 0.5 mA. The internal high voltage startup circuit eliminates the need for external startup components. In addition, the startup regulator helps increase the system efficiency as it uses negligible power in the normal operation mode. 

Once CCC is charged to the startup threshold, VCC(on), typically 17 V, the startup regulator is disabled and the controller is enabled. The startup regulator will remain disabled until VCC falls below the minimum operating voltage threshold, VCC(off), typically 8.8 V. Once reached, the PFC and flyback controllers are disabled reducing the bias current consumption of the IC. The startup circuit is then are then enabled allowing VCC to charge back up. 

A dedicated comparator monitors VCC when the QR stage is enabled and latches off the controller if VCC exceeds VCC(OVP), typically 28 V. 

The controller is disabled once a fault is detected. The controller will restart the next time VCC reaches VCC(on) and all non−latching faults have been removed. 

The supply capacitor provides power to the controller during power up. The capacitor must be sized such that a VCC voltage greater than VCC(off) is maintained while the auxiliary supply voltage is building up. Otherwise, VCC will collapse and the controller will turn off. The operating IC bias current, ICC4, and gate charge load at the drive outputs 

must be considered to correctly size CCC. The increase in current consumption due to external gate charge is calculated using Equation 1. 

**==> picture [160 x 13] intentionally omitted <==**

where f is the operating frequency and QG is the gate charge of the external MOSFETs. 

## **LINE VOLTAGE SENSE** 

The BO/HV pin provides access to the brown−out and line voltage detectors. The brown−out detector detects mains interruptions and the line voltage detector determines the presence of either 120 V or 230 V ac mains. Depending on the detected input voltage range device parameters are internally adjusted to optimize the system performance. 

This pin can connect after the rectifier bridge to achieve full wave rectification as shown in Figure 3. A diode is used to prevent the pin from going below ground. A low value resistor in series with the BO/HV pin can be used for protection. A low value resistor is needed to reduce the voltage offset while sensing the line voltage. 

**==> picture [229 x 132] intentionally omitted <==**

**----- Start of picture text -----**<br>
AC EMI<br>Input Filter<br>BO/HV<br>NCL30030<br>**----- End of picture text -----**<br>


**Figure 3. Brown−out and Line Voltage Detectors Configuration** 

The flyback stage is enabled once VBO/HV is above the brown−out threshold, VBO(start), typically 111 V, and VCC reaches VCC(on). The high voltage startup is immediately enabled when the voltage on VBO/HV crosses over the brown−out start threshold, VBO(start), to ensure that device is enabled quickly upon exiting a brown−out state. Figure 4 shows typical power up waveforms. 

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**12** 

**NCL30030** 

**Figure 4. Startup Timing Diagram** 

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**13** 

**NCL30030** 

A timer is enabled once VBO/HV drops below its stop threshold, VBO(stop), typically 101 V. If the timer, tBO, expires the device will begin monitoring the voltage on VBO/HV and disable the PFC and flyback stages when that voltage is below the Brown−out Drive Disable threshold, VBO(DRV_disable), typically 30 V. This ensures that device switching is stopped in a low energy state which minimizes inductive voltage kick from the EMI components and ac mains. The timer, tBO, typically 54 ms, is set long enough to ignore a single cycle drop−out. 

## **LINE VOLTAGE DETECTOR** 

The input voltage range is detected based on the peak voltage measured at the BO/HV pin. Discrete values are selected for the PFC stage gain (feedforward) depending on the input voltage range. The controller compares VBO/HV to an internal line select threshold, VBO(lineselect), typically 240 V. Once VBO/HV exceeds VBO(lineselect), the PFC stage operates in “high line” (Commercial US − 277 Vac) or “230 Vac” mode. In high line mode the maximum on time is 

reduced by a factor of 3, resulting in a maximum output power independent of input voltage. 

The default power−up mode of the controller is low line. The controller switches to “high line” mode if VBO/HV exceeds the line select threshold for longer than the low to high line timer, t(low to high line), typically 300 s, as long as u it was not previously in high line mode. If the controller has switched from “high line” to “low line” mode, the low to high line timer, t(low to high line), is inhibited until VBO/HV falls below VBO(stop). This prevents the controller from toggling back to “high line” until at least one VBO(stop) transition has occurred. The timer and logic is included to prevent unwanted noise from toggling the operating line level. 

In “high line” mode the high to low line timer, t(high to low line)[, (typically 54 ms) is enabled once V] BO/HV[ falls below] VBO(lineselect). It is reset once VBO/HV exceeds V . The controller switches back to “low line” BO(lineselect) mode if the high to low line timer expires. 

**Figure 5. Line Detector Waveforms** 

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**14** 

**NCL30030** 

## **FAULT INPUT** 

The NCL30030 includes a dedicated fault input accessible via the Fault pin. The controller will enter triple hiccup mode when the pin is pulled above the upper fault threshold, VFault(OVP), typically 3.0 V. The controller is disabled if the Fault pin voltage, VFault, is pulled below the lower fault threshold, VFault(OTP_in), typically 0.4 V. The lower threshold is normally used for detecting an overtemperature fault. The controller operates normally while the Fault pin voltage is maintained within the upper and lower fault thresholds. Figure 6 shows the architecture of the Fault input. 

The lower fault threshold is intended to be used to detect an overtemperature fault using an NTC thermistor. A pull up current source IFault(OTP), (typically 45.5 �A) generates a voltage drop across the thermistor. The resistance of the NTC thermistor decreases at higher temperatures resulting in a lower voltage across the thermistor. The controller detects a fault once the thermistor voltage drops below VFault(OTP_in). Part option A latches off the controller after an overtemperature fault is detected. For part option B the controller is re−enabled once the fault is removed such that VFault increases above VFault(OTP_out) and VCC reaches VCC(on). Figure 7 shows typical waveforms related to the latch option where as Figure 8 shows waveforms of the auto−recovery option. 

the upper threshold, the external pull−up current has to be higher than the pull−down capability of the clamp (set by RFault(clamp) at VFault(clamp)). The upper fault threshold is intended to be used for an overvoltage fault using a Zener diode and a resistor in series from the auxiliary winding voltage, VAUX. The controller goes into a triple hiccup once VFault exceeds VFault(OVP). 

The Fault input signal is filtered to prevent noise from triggering the fault detectors. Upper and lower fault detector blanking delays, tdelay(Fault_OVP) and tdelay(Fault_OTP) are both typically 30 �s. A fault is detected if the fault condition is asserted for a period longer than the blanking delay. 

A bypass capacitor is usually connected between the Fault and GND pins and it will take some time for VFault to reach its steady state value once IFault(OTP) is enabled. Therefore, a lower fault (i.e. overtemperature) is ignored during soft−start. In Option B, IFault(OTP) remains enabled while the lower fault is present independent of VCC in order to provide temperature hysteresis. The upper OVP fault detection is enabled and remains active as long as the QR flyback is enabled. 

Once the controller is latched, it is reset if a brown−out condition is detected or if VCC is cycled down to its reset level, VCC(reset). In the typical application these conditions occur only if the ac voltage is removed from the system. Prior to reaching VCC(reset), Vfault(clamp) is set at 0 V. 

An active clamp prevents the Fault pin voltage from reaching the upper latch threshold if the pin is open. To reach 

**==> picture [431 x 160] intentionally omitted <==**

**----- Start of picture text -----**<br>
VAUX<br>+ Blanking<br>VDD − tdelay(Fault_OTP) S Q Triple Hiccup<br>VFault(OVP) R<br>IFault(OTP)<br>Fault<br>+− Blanking S Q Latch<br>Vfault(OTP) tdelay(Fault_OTP)<br>NTC RFault(clamp) Soft−start R<br>Thermistor<br>end<br>VFault(clamp) Hysteresis Option<br>Control Auto−restart<br>Control Auto−restart<br>**----- End of picture text -----**<br>


**Figure 6. Fault Detection Schematic** 

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**15** 

**NCL30030** 

**Figure 7. Latch−off Function Timing Diagram** 

**Figure 8. OTP Auto−Recovery Timing Diagram** 

## **QR FLYBACK VALLEY LOCKOUT** 

The NCL30030 integrates a quasi−resonant (QR) flyback controller. The power switch turn−off of the QR converter is determined by the peak current set by the feedback loop. The switch turn−on is determined by the transformer demagnetization. The demagnetization is detected by monitoring the transformer auxiliary winding voltage. 

Turning on the power switch once the transformer is demagnetized or reset reduces switching losses. Once the transformer is demagnetized, the drain voltage starts ringing at a frequency determined by the transformer magnetizing inductance and the drain lump capacitance eventually settling at the input voltage. A QR controller takes advantage of the drain voltage ringing and turns on the power switch at the drain voltage minimum or “valley” to 

reduce switching losses and electromagnetic interference (EMI). 

The operating frequency of a traditional QR flyback controller is inversely proportional to the system load. That is, a load reduction increases the operating frequency. This traditionally requires a maximum frequency clamp to limit the operating frequency. This causes the controller to become unstable and jump (or hesitate) between two valleys generating audible noise. The NCL30030 incorporates a patent pending valley lockout circuitry to eliminate valley jumping. Once a valley is selected, the controller stays locked in this valley until the output power changes significantly. Like a traditional QR flyback controller, the frequency increases when the load decreases. Once a higher valley is selected the frequency decreases very rapidly. It 

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**NCL30030** 

will continue to increase if the load is further reduced. This technique extends QR operation over a wider output power range while maintaining good efficiency and limiting the maximum operating frequency. Figure 9 shows a qualitative frequency vs output power relationship. 

Figure 10 shows the internal arrangement of the valley detection circuitry. An internal counter increments each time a valley is detected. The operating valley (1[st] , 2[nd] , 3[rd] or 4[th] ) is determined by the QFB voltage. As VQFB decreases 

or increases, the valley comparators toggle one after another to select the proper valley. The activation of an “n” valley comparator blanks the “n−1” or “n+1” valley comparator output depending if VQFB decreases or increases, respectively. 

A valley is detected once VQZCD falls below the QR flyback demagnetization threshold, VQZCD(th), typically 55 mV. The controller will switch once the valley is detected or increment the valley counter depending on QFB voltage. 

**Figure 9. Valley Lockout Frequency vs Output Power Relationship** 

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**----- Start of picture text -----**<br>
| VDD<br>| IQFB RQFB<br>QFB<br>oF<br>|<br>Minimum<br>VDD CT Frequency<br>QCT P IQCT e tl Setpoint LL Oscillator QR Logic SDominantResetQ QDRV(internal)<br>2 0 8 Latch<br>R Q<br>QCT<br>Discharge QDRV(internal)<br>demag Timeout<br>QZCD QZCD Comparator<br>ROPPU +<br>r e a Tfii − VQZCD(th) |) =<br>RQCZD<br>| a<br>QDRV(internal) Blanking<br>LAUX (tblank)<br>f o<br>Overcurrent<br>**----- End of picture text -----**<br>


**Figure 10. Valley Detection Circuitry** 

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**NCL30030** 

Figure 11 shows the operating valley versus VQFB. Once a valley is asserted by the valley selection circuitry, the controller is locked in this valley until VQFB decreases or increases such that VQFB reaches the next valley threshold. A decrease in output power causes the controller to switch from “n” to “n+1” valley until reaching the 4[th] valley. 

A further reduction of output power causes the controller to enter the voltage control oscillator (VCO) mode once 

VQFB falls below VHVCOD. In VCO mode the peak current is set to VQILIM1*KIpeak(VCO) as shown in Figure 12. The operating frequency in VCO mode is adjusted to deliver to required output power. 

A hysteresis between valleys provides noise immunity and helps stabilize the valley selection in case of small perturbations on VQFB. 

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**----- Start of picture text -----**<br>
Valley<br>VCO<br>4th<br>3rd<br>2nd<br>1st<br>VQFB<br>VHVCOD VH4D VH3D VH2D VH4I VH3I VH2I VQILIM1*KQFB<br>VHVCOI<br>Figure 11. Selected Operating Valley versus VQFB<br>Peak current<br>Setpoint<br>VCO<br>Skip Mode QR Mode<br>VQILIM1 ÎÎÎÎÎÎ<br>ÎÎÎÎÎÎ<br>ÎÎÎÎÎÎ<br>1st ValleyÎÎÎÎÎÎ<br>2nd ÎÎÎÎÎÎ<br>3rd ÎÎÎÎÎÎ<br>Fault<br>4th ÎÎÎÎÎÎ<br>Ipeak(VCO)*VQILIM1 ÎÎÎÎÎÎ<br>ÎÎÎÎÎÎVQFB<br>VQFB(TH) VQSKIP VHVCOD VH4D VH3D VH2D VQILIM1*KQFB<br>**----- End of picture text -----**<br>


**Figure 12. Operating Valley versus VQFB** 

Figures 13 through 16 show drain voltage, VQFB and VQCT simulation waveforms for a reduction in output power. The transitions between 2[nd] to 3[rd] , 3[rd] to 4[th] and 4[th] 

valley to VCO mode are observed without any instabilities or valley jumping. 

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**NCL30030** 

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**----- Start of picture text -----**<br>
700 Zoom 1 Zoom 2 Zoom 3<br>Vdrain<br>500<br>300<br>100<br>−100<br>2.00<br>1.60<br>1.20<br>800m V QFB<br>400m<br>7.00 V QCT<br>5.00<br>3.00<br>1.00<br>−1.00<br>3.64m 4.91m 6.18m 7.45m 8.72m<br>time in seconds<br>Plot1<br>vdrain in volts<br>Plot2<br>feedback in volts<br>Plot3<br>vct in volts<br>**----- End of picture text -----**<br>


**Figure 13. Operating Mode Transitions Between 2[nd] to 3[rd] , 3[rd] to 4[th] and 4[th] Valley to VCO Mode** 

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**----- Start of picture text -----**<br>
1 vdrain 2 feedback 3 vct 1 vdrain 2 feedback 3 vct<br>700 Vdrain 700 V drain<br>500 1 500<br>300 300<br>100 100<br>−100 −100<br>2.15 VQFB 1.38<br>2.05 1.34<br>2<br>1.95 1.30<br>1.85 1.26<br>1.75 1.22 VQFB<br>6.00 4.00<br>4.00 V QCT 3.00 V QCT<br>2.00 2.00<br>0 1.00<br>−2.00 0<br>3.70m 3.78m 3.86m 3.94m 4.02m 5.90m 5.95m 6.00m 6.05m 6.11m<br>time in seconds time in seconds<br>Figure 14.  Zoom 1: 2 [nd]  to 3 [rd]  Valley Figure 15. Zoom 2: 3 [rd]  to 4 [th]  Valley<br>Transition Transition<br>1 vdrain 2 feedback 3 vct<br>700 V drain<br>500<br>300 1<br>100<br>−100<br>1.12<br>1.02<br>2<br>919m<br>819m719m VQFB<br>8.00 VQCT<br>6.00<br>4.00<br>2.00<br>0<br>7.10m 7.21m 7.32m 7.43m 7.55m<br>time in seconds<br>Figure 16. Zoom 3: 4 [th]  Valley to VCO Mode<br>Transition<br>Plot1 Plot1<br>vdrain in volts vdrain in volts<br>Plot2 Plot2<br>feedback in volts feedback in volts<br>Plot3 Plot3<br>vct in volts vct in volts<br>Plot1<br>vdrain in volts<br>Plot2<br>feedback in volts<br>Plot3<br>vct in volts<br>**----- End of picture text -----**<br>


## **VCO MODE** 

The controller enters VCO mode once V falls below QFB VHVCOD and remains in VCO until VQFB exceeds VHVCOI. In VCO mode the peak current is set to VQILIM1*Ipeak(VCO) and the operating frequency is linearly dependent on VQFB. The product of VQILIM1*Ipeak(VCO) is typically 12.5%. A minimum frequency clamp, fVCO(MIN), typically 27 kHz, prevents operation in the audible range. Further reduction in output power causes the controller to enter skip operation. The minimum frequency clamp is only enabled when operating in VCO mode. 

The VCO mode operating frequency is set by the timing capacitor connected between the QCT and GND pins. This 

capacitor is charged with a constant current source, IQCT, typically 20 �A. 

The capacitor voltage, VQCT, is compared to an internal voltage level, Vf(QFB), inversely proportional to VQFB The relationship between and Vf(QFB) and VQFB is given by Equation 2). 

**==> picture [162 x 12] intentionally omitted <==**

A drive pulse is generated once VQCT exceeds Vf(QFB) followed by the immediate discharge of the timing capacitor. The timing capacitor is also discharged once the minimum frequency clamp is reached. Figure 17 shows simulation waveforms of Vf(QFB), VQDRV and output current while operating in VCO mode. 

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800m<br>600m<br>400m IOUT<br>200m<br>0 1<br>7.00<br>5.00 32 VQCT<br>3.00<br>1.00 Vf(QFB)<br>−1.00<br>30.0<br>20.0<br>10.0 VQDRV<br>0<br>−10.0<br>7.57m 7.78m 7.99m 8.20m 8.40m<br>time in seconds<br>Plot1<br>iout in amperes<br> in volts<br>Plot2 vct<br>v(fbint:x1),<br>Plot3<br>drv in volts<br>**----- End of picture text -----**<br>


**Figure 17. VCO Mode Operating Waveforms** 

## **FLYBACK TIMEOUT** 

In case of extremely damped oscillations, the QZCD comparator may be unable to detect the valleys. In this condition, drive pulses will stop waiting for the next valley or ZCD event. The NCL30030 ensures continued operation by incorporating a maximum timeout period after the last demagnetization detection. The timeout signal is a substitute for the ZCD signal for the valley counter. Figure 18 shows the timeout period generator circuit schematic. The steady state timeout period, tQ(tout2), is set at 6 �s to limit the frequency step. 

During startup, the voltage offset added by the overpower compensation diode, DOPP, prevents the QZCD Comparator from accurately detecting the valleys. In this condition, the steady state timeout period will be shorter than the inductor demagnetization period causing continuous current mode (CCM) operation. CCM operation lasts for a few cycles until the voltage on the QZCD pin is high enough to detect the valleys. A longer timeout period, tQ(tout1), (typically 100 �s) is set during soft−start to limit CCM operation. Figures 19 and 20 show the timeout period generator related waveforms. 

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**----- Start of picture text -----**<br>
QZCD QZCD Comparator<br>demag<br>DOPP ROPPU +<br>− VQZCD(th) QR Logic<br>RQCZD Minimum<br>Frequency<br>LAUX QDRV(internal) tZCD(blank)Blanking Oscillator Timeout<br>Steady<br>State<br>QDRV(internal) Soft−start Timeout<br>Complete (tout2) R<br>Soft−Start<br>Timeout<br>(tout1)<br>R<br>**----- End of picture text -----**<br>


**Figure 18. Timeout Period Generator Circuit Schematic** 

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**----- Start of picture text -----**<br>
VQZCD<br>VQZCD(th)<br>34<br>The 3rd valley is<br>high validated 14<br>2 [nd] , 3 [rd]<br>low 12<br>The 2 [nd]  valley is detected The 3rd valley is not detected<br>by the QZCD Comparator by the QZCD Comparator<br>high QZCD<br>Comparator<br>low 15 Output<br>high<br>Timeout<br>low 16<br>Timeout adds a pulse to account for<br>the missing 3 [rd]  valley<br>high<br>Clk<br>low 17<br>Figure 19. Timeout Operation With a Missing 3 [rd]  Valley<br>VQZCD<br>VQZCD(th)<br>34<br>hig h The 4 [th]  valley is<br>validated 3 [rd] , 4 [th]<br>18<br>low<br>14<br>hig h QZCD<br>low C omparator<br>15 Output<br>hig h<br>Timeout<br>low 16<br>Timeout adds 2 pulses to account<br>for the missing 3 [rd]  and 4 [th]  valleys<br>high<br>Clk<br>low 17<br>**----- End of picture text -----**<br>


**Figure 20. Timeout Operation With Missing 3[rd] and 4[th] Valleys** 

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**NCL30030** 

## **QR FLYBACK CURRENT SENSE AND OVERLOAD** 

The power switch on time is modulated by comparing a ramp proportional to the switch current to VQFB/KQFB using the PWM Comparator. The switch current is sensed across a current sense resistor, RSENSE, and the resulting voltage is applied to the QCS pin. The current signal is blanked by a leading edge blanking (LEB) circuit. The blanking period eliminates the leading edge spike and high frequency noise during the switch turn−on event. The LEB period, tQCS(LEB1), is typically 275 ns. The drive pulse terminates once the current sense signal exceeds VQFB/KQFB. 

The Maximum Peak Current Comparator compares the current sense signal to a reference voltage to limit the maximum peak current of the system. The maximum peak current reference voltage, VQILIM1, is typically 0.8 V. The maximum peak current setpoint is reduced by the overpower compensation circuitry. An overload condition causes the output of the Maximum Peak Current Comparator to transition high and enable the overload timer. Figure 21 shows the implementation of the current sensing circuitry. 

**==> picture [298 x 256] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDD<br>VQFB IQFB RQFB<br>Skip QFB<br>VQSKIP<br>Ipeak(VCO) =<br>PWM VQZCD KQCS(VCO)<br>Comparator<br>+ /KQFB<br>Overload Timer<br>tQOVLD Peak Current LEB<br>Count Down Comparator tQCS(LEB1)<br>Count Up<br>+<br>VDD<br>Disable QDRV VQILIM1<br>Short−Circuit VQZCD<br>Comparator LEB QCS<br>nQILIM2 Counter tQCS(LEB2)<br>VQILIM2<br>IQCS<br>+<br>−<br>+<br>−<br>+<br>−<br>**----- End of picture text -----**<br>


**Figure 21. Current Sensing Circuitry Schematic** 

The overload timer integrates the duration of the overload fault. That is, the timer count increases while the fault is present and reduces its count once it is removed. The overload timer duration, tQOVLD, is typically 80 ms. If both the PWM and Maximum Peak Current Comparators toggle at the same time, the PWM Comparator takes precedence 

and the overload timer counts down. The controller can latch (option A) or allow for auto−recovery (option B) once the overload timer expires. Auto−recovery requires a VCC triple hiccup before the controller restarts. Figures 22 and 23 show operating waveforms for latched and auto−recovery overload conditions. 

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**Figure 22. Latched Overload Operation** 

**Figure 23. Auto−Recovery Overload Operation** 

A severe overload fault like a secondary side winding short−circuit causes the switch current to increase very rapidly during the on−time. The current sense signal significantly exceeds VQILIM1 . But, because the current sense signal is blanked by the LEB circuit during the switch turn on, the system current can get extremely high causing system damage. 

The NCL30030 protects against this fault by adding an additional comparator, Fault Overcurrent Comparator. The current sense signal is blanked with a shorter LEB duration, tQCS(LEB2), typically 120 ns, before applying it to the Fault Overcurrent Comparator. The voltage threshold of the comparator, VQILIM2 , typically 1.2 V, is set 50% higher than VQILIM1 , to avoid interference with normal operation. Four 

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**NCL30030** 

consecutive faults detected by the Fault Overcurrent Comparator causes the controller to enter triple−hiccup auto−recovery mode. The count to 4 provides noise immunity during surge testing. The counter is reset each time a QDRV pulse occurs without activating the Fault Overcurrent Comparator. A 1 u A (typically) pull−up current source, IQCS, pulls up the QCS pin to disable the controller if the pin is left open. 

## **QR FLYBACK SOFT−START** 

Soft−start is achieved by ramping up an internal reference, VSSTART, and comparing it to current sense signal. VSSTART ramps up from 0 V once the controller powers up. The soft−start duration, tSSTART, is typically 4 ms. 

During soft−start the timeout duration is extended and the lower latch or OTP Comparator signal (typically for 

overtemperature) is blanked. Soft−start ends once VSSTART exceeds the peak current sense signal threshold. 

## **QR FLYBACK OVERPOWER COMPENSATION** 

The input voltage of the QR flyback stage varies with the line voltage and operating mode of the PFC converter. At low line the PFC bulk voltage is 220 V and at high line it will be 390 V or 440 V, depending on the version of the part. Additionally, the PFC can be disabled at which point the PFC bulk voltage is set by the rectified peak line voltage. 

An integrated overpower circuit provides a relative constant output power across PFC bulk voltage, Vbulk. It also reduces the variation on VQFB during the PFC stage enable or disable transitions. Figure 24 shows the circuit schematic for the overpower detector. 

**==> picture [354 x 188] intentionally omitted <==**

**----- Start of picture text -----**<br>
QZCD<br>T<br>DOPP ROPPU + QZCD Comparator<br>: 3 | SS − VQZCD(th)<br>ROPPL | r<br>RQCZD | = = Peak Current<br>= | Comparator<br>LAUX QFB /4 + +<br>= − VQILIM1<br>|<br>| Disable<br>QDRV<br>+<br>| [|] . Other Faults )<br>| KQCS(VCO) + = PWM<br>−<br>QCS | | LEB L = Comparator<br>a tQCS(LEB1)<br>**----- End of picture text -----**<br>


**Figure 24. Overpower Compensation Circuit Schematic** 

The auxiliary winding voltage during the power switch on time is a reflection of the input voltage scaled by the primary to auxiliary winding turns ratio, NP,AUX, as shown in Figure 25. 

The voltage is scaled down using ROPPU and ROPPL. The negative voltage applied to the pin is referred to as VOPP. 

The internal current setpoint is the sum of VOPP and peak current sense threshold, VQILIM1. VOPP is also subtracted from VQFB to compensate for the PWM Comparator delay and improve the PFC on/off accuracy. 

The current setpoint is calculated using Equation 3. For example, a VOPP of −0.15 V results in a current setpoint of 0.65 V. 

Current setpoint = VQILIM1 + VOPP (eq. 3) 

To ensure optimal zero−crossing detection, a diode is needed to bypass ROPPU during the off−time. Equation 4 is used to calculate ROPPU and ROPPL. 

**==> picture [220 x 28] intentionally omitted <==**

**Figure 25. Auxiliary Winding Voltage Waveform** 

Overpower compensation is achieved by scaling down the on−time reflected voltage and applying it to the QZCD pin. 

ROPPU is selected once a value is chosen for ROPPL. ROPPL is selected large enough such that enough voltage is available for the zero crossing detection during the off−time. 

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It is recommended to have at least 8 V applied on the QZCD pin for good detection. The maximum voltage is internally clamped to VCC. The off−time voltage on the QZCD is given by Equation 5. 

**==> picture [216 x 27] intentionally omitted <==**

at the end of each switch cycle. Figure 26 shows the PFC inductor current while operating in CrM. High power factor and low harmonic distortion is achieved by shaping the input current, Iin(t), such that it is sinusoidal and in phase with the ac line voltage, Vin(t). 

Where VAUX is the voltage across the auxiliary winding and VF is the DOPP forward voltage drop. 

The ratio between RQZCD and ROPPL is given by Equation 6. It is obtained combining Equations 4 and 5. 

**==> picture [177 x 28] intentionally omitted <==**

A design example is shown below: System Parameters: VAUX = 18 V VF = 0.6 V NP,AUX = 0.18 

The ratio between RQZCD and ROPPL is calculated using Equation 6 for a minimum VQZCD of 8 V. 

**==> picture [121 x 28] intentionally omitted <==**

RQZCD is arbitrarily set to 1 k ROPPL is also set to 1 k because the ratio between the resistors is close to 1. 

The NCL30030 maximum overpower compensation or peak current setpoint reduction is 31.25% for a VOPP of −250 mV. We will use this value for the following example: 

Substituting values in Equation 4 and solving for ROPPU we obtain, 

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## **POWER FACTOR CORRECTION** 

The PFC stage operates in critical conduction mode (CrM). In CrM the PFC inductor current, IL(t), reaches zero 

**Figure 26. Inductor Current in CrM** 

To achieve unity power factor and low harmonic distortion the NCL30030 uses a peak current mode control architecture where the cycle−by−cycle current limit is set by a multiplier circuit. A block diagram of the control architecture is shown in Figure 27. The control works by generating a DC current proportional to the instantaneous AC line voltage and multiplying that current with the error voltage generated from the feedback error amplifier. 

The multiplication factor is determined by the output of a comparator which measures the error voltage against a high frequency ramping signal. As the error voltage approaches its maximum value, the multiplication factor approaches 1. The output of the comparator toggles a switch to modulate the DC current from the current generator. The modulated current then feeds a resistor to set the peak current limit and hence control the duty cycle for every switching period. An external capacitor on the MULT pin is used to filter ripple caused by the modulation. 

This control architecture is effectively a dual loop control method where the current generator shapes the peak current setpoint such that it follows the AC input while the error voltage adjusts the peak current to ensure that bulk voltage regulation is maintained. 

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**----- Start of picture text -----**<br>
BO/HV Low/High Line<br>Vbulk<br>IMULT<br>Ramp Error R1<br>Signal<br>Amplier<br>PFB<br>MULT<br>Multiplier + VPREF R2<br>Comparator −<br>PWM<br>Comparator<br>PControl<br>PCS/PZCD<br>Reset PDRV<br>LEB1<br>**----- End of picture text -----**<br>


**Figure 27. Multiplier Block Diagram** 

## **PFC FEEDBACK** 

The PFC feedback circuitry is shown in Figure 28. A resistor divider consisting of R1 and R2 scales down the PFC output voltage, Vbulk, to generate a PFC feedback signal. The feedback signal is applied to the inverting input of a transconductance error amplifier which regulates Vbulk by comparing the PFC feedback signal to an internal reference voltage, VPREF. The reference is connected to the non−inverting input of the error amplifier and is trimmed during manufacturing to achieve an accuracy of ±2% across temperature. 

**==> picture [227 x 222] intentionally omitted <==**

**----- Start of picture text -----**<br>
PFC OVP<br>POVP<br>Circuitry<br>Vbulk<br>PFC UVP<br>R1 PFB Comparator<br>PUVP<br>R2 +<br>− VPFB(disable)<br>Error VBOHV<br>PWM<br>Amplier<br>Multiplier Comparator<br>+ PDRV Reset<br>− VPREF VPCS<br>VDD<br>PControl VPControl(MAX)<br>VPControl(MIN) Disable PFC<br>PUVP<br>**----- End of picture text -----**<br>


**Figure 28. PFC Regulation Circuit Schematic** 

## **PFC ERROR AMPLIFIER** 

A transconductance amplifier has a voltage−to−current gain, gm. That is, the amplifier’s output current is controlled by the differential input voltage. The NCL30030 amplifier 

has a typical gm of 200 �S. The PControl pin provides access to the amplifier output for compensation. The compensation network is ground referenced allowing the PFC feedback signal to detect undervoltage and overvoltage conditions as shown in Figure 28. 

The compensation network on the PControl pin is selected to filter the bulk voltage ripple such that a constant control voltage is maintained across the ac line cycle. A capacitor between the PControl pin and ground sets a pole. A pole at or below 20 Hz is enough to filter the ripple voltage for a 50 and 60 Hz system. The low frequency pole, fp, of the system is calculated using Equation 7. 

**==> picture [147 x 25] intentionally omitted <==**

where, CPControl is the capacitor on the PControl pin to ground. 

The output of the error amplifier is held low when the PFC is disabled by means of an internal pull−down transistor. The pull down transistor is disabled once the PFC stage is enabled. An internal voltage clamp is then enabled to quickly raise VPControl to its minimum voltage, VPControl(min), typically 0.6 V. 

## **PFC TRANSIENT RESPONSE** 

The PFC bandwidth is set low enough to achieve good power factor. However, a low bandwidth system is slow and fast load transients can result in large output voltage excursions. The NCL30030 incorporates dedicated circuitry to help maintain regulation of the output voltage independent of load transients. 

An undervoltage detector monitors the ratio between VPFB and VPREF(xL). Once the ratio between VPFB and VPREF(xL) exceeds KLOW(PFCxL), typically 5.5%, a pull−up current source on the PControl pin, IPControl(boost), is enabled to speed up the charge of the compensation network. This results in an increased on−time and thus output power. IPControl(boost) is typically 240 �A. The boost current source 

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is disabled once the ratio between VPFB and VPREF(xL) drops below KLOW(PFCxL), typically 4%. 

The boost current source becomes active as soon as the PFC is enabled. Coupled with the lower control clamp, the boost current source assists in rapidly bringing VPControl to its set point to allow the bulk voltage to quickly reach regulation. Achieving regulation is detected by monitoring the error amplifier output current. The error amplifier output current drops to zero once the PFC output voltage reaches the target regulation level. 

The maximum PFC output voltage is limited by the overvoltage protection circuitry. The NCL30030 incorporates both soft and hard overvoltage protection. The hard overvoltage protection function immediately terminates and prevents further PFC drive pulses when 

VPFB exceeds the hard−OVP level, VPOVP (VPREF(xL)*KPOVP(xL)). Soft−OVP reduces the on−time proportional to the delta between VPFB and the hard−OVP level. Soft−OVP is enabled once the delta, �POVP(xL), between VPFB and the hard−OVP level is between 20 and 55 mV. Figure 29 shows a block diagram of the boost and Soft−OVP circuits. 

During power up, VPControl exceeds the regulation level due to the system’s inherently low bandwidth. This causes the bulk voltage to rapidly increase and exceed its regulation. The on time starts to decrease when soft−OVP is activated. Once the bulk voltage decreases to its regulation level the PFC on time is no longer controlled by the soft−OVP circuitry. 

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**----- Start of picture text -----**<br>
On−Time<br>PDRV RAMP Comparator<br>Low/High Line Generator<br>Fixed<br>R Q PDRV<br>Reference<br>Dominant<br>PCS/PZCD Reset<br>LEB1 Latch<br>S Q<br>MULT<br>PWM<br>Comparator<br>VDD<br>VBOHV VPOVP<br>PControl VPControl(MAX) A Soft OVP<br>Comparator<br>VPControl(MIN) MULTIPLIER Boost<br>VDD Comparator<br>Error V * KLOW<br>PFB Amplier IPControl(boost)<br>+<br>VPREF − Regulation<br>Detector<br>Regulation OK<br>+<br>−<br>**----- End of picture text -----**<br>


**Figure 29. Boost and Soft−OVP Circuit Schematics** 

## **PFC CURRENT SENSE AND ZERO CURRENT DETECTION** 

single input terminal. Figure 30 shows the circuit schematic of the current sense and ZCD detectors. 

The NCL30030 uses a novel architecture combining the PFC current sense and zero current detectors (ZCD) in a 

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**----- Start of picture text -----**<br>
tPFC(off) Timer<br>PDRV Reset<br>PILIM2<br>S Q<br>+<br>PFC Boost − VPZCD(rising)<br>PFC Inductor Diode R Q<br>PFC Switch<br>PDRV tPZCD_Blank To PDRV Set<br>RPsense<br>PDRV D Q<br>RPCS CLK<br>RPZCD +<br>PCS/PZCD − VPZCD(falling) PDRV R Q<br>Current Limit<br>LEB1 Comparator<br>tPCS(LEB1)<br>PILIM1<br>+ PDRV<br>VPILIM1<br>− Short Circuit<br>LEB2 Comparator PDRV<br>PILIM2<br>tPCS(LEB2)<br>+<br>VPILIM2<br>−<br>**----- End of picture text -----**<br>


**Figure 30. PFC Current Sense and ZCD Detectors Schematic** 

## **PFC CURRENT SENSE** 

The PFC Switch current is sensed across a sense resistor, RPsense, and the resulting voltage ramp is applied to the PCS/PZCD pin. The current signal is blanked by a leading edge blanking (LEB) circuit. The blanking period eliminates the leading edge spike and high frequency noise during the switch turn−on event. The LEB period, tPCS(LEB1), is typically 325 ns. The Current Limit Comparator disables the PFC driver once the current sense signal exceeds the PFC current sense reference, VPILIM1, typically 1.5 V. 

A severe overload fault like a PFC boost diode short circuit causes the switch current to increase very rapidly during the on−time. The current sense signal significantly exceeds VPILIM1. But, because the current sense signal is blanked by the LEB circuit during the switch turn on, the system current can get extremely high causing system damage. 

The NCL30030 protects against this fault by adding an additional comparator, PFC Short Circuit Comparator. The current sense signal is blanked with a shorter LEB duration, tPCS(LEB2), typically 175 ns, before applying it to the PFC Short Circuit Comparator. The voltage threshold of the 

comparator, VPILIM2, typically 2 V, is set 33% higher than VPILIM1, to avoid interference with normal operation. Whenever a fault is detected by the Short Circuit Comparator, the watchdog timer increases to 1 ms allowing the system time to recover from the excessive over current. The next PFC drive pulse is then initiated when the watchdog timer expires. 

## **PFC ZERO CURRENT DETECTION** 

The off−time in a CrM PFC topology varies with the instantaneous line voltage and is adjusted every switching cycle to allow the inductor current to reach zero before the next switching cycle begins. The inductor is demagnetized once its current reaches zero. Once the inductor is demagnetized the drain voltage of the PFC switch begins to drop. The inductor demagnetization is detected by sensing the voltage across the inductor using an auxiliary winding. This winding is commonly known as a zero crossing detector (ZCD) winding. This winding provides a scaled version of the inductor voltage. Figure 31 shows the ZCD winding arrangement. 

**www.onsemi.com** 

**29** 

**NCL30030** 

**==> picture [222 x 104] intentionally omitted <==**

**----- Start of picture text -----**<br>
PFC Inductor<br>Rectied PFC Switch PFC<br>ac line output<br>PDRV<br>voltage voltage<br>RPsense<br>RPCS<br>RPZCD<br>PCS/PZCD<br>**----- End of picture text -----**<br>


During startup there are no ZCD transitions to set the PFC PWM Latch and generate a PDRV pulse. A watchdog timer, tPFC(off1), starts the drive pulses in the absence of ZCD transitions. Its duration is typically 200 s. The timer is also useful if the line voltage transitions from low line to high line and while operating at light load because the amplitude of the ZCD signal may be too small to cross the ZCD arming threshold. The watchdog timer is reset at the beginning of a PFC drive pulse. It is disabled during a PFC hard overvoltage and feedback input short circuit condition. 

## **PFC ENABLE & DISABLE** 

**Figure 31. ZCD Winding Implementation** 

The ZCD voltage, VZCD, is positive while the PFC Switch is off and current flows through the PFC inductor. VZCD drops to and rings around zero volts once the inductor is demagnetized. The next switching cycle begins once a negative transition is detected on the PCS/PZCD pin. A positive transition (corresponding to the PFC switch turn off) arms the ZCD detector to prevent false triggering. The arming of the ZCD detector, VPZCD(rising), is typically 0.75 V. The trigger threshold, VPZCD(falling), is typically 0.25 V. The NCL30030 also incorporates a blanking period, TPZCD_Blank which prevents detection of a ZCD event for 700 ns after the PFC switch turn off. 

The PCS/PZCD pin is internally clamped to 5 V with a Zener diode and a 2 k resistor. A resistor in series with the PCS/PZCD pin is required to limit the current into pin. The Zener diode also prevents the voltage from going below ground. Figure 32 shows typical ZCD waveforms. 

**Figure 32. ZCD Winding Waveforms** 

In some applications it is desired to disable the PFC at lighter loads to increase the overall system efficiency. The NCL30030 integrates a novel architecture that allows the user to program the PFC disable threshold based on the percentage of QR output power. The PFC enable circuitry is inactive until the QR flyback soft start period has ended. A voltage to current (V−I) converter generates a current proportional to VQFB. This current is pulse width modulated by the demagnetization time of the flyback controller to generate a current, IPONOFF, proportional to the output power. An external resistor, RPONOFF, between the PONOFF and GND pins is used to scale the output power signal. A capacitor, CPONOFF, in parallel with RPONOFF is required to average the signal on this pin. A good compromise between voltage ripple and speed is achieved by setting the time constant of CPONOFF and RPONOFF to 160 s. 

The PONOFF pin voltage, VPONOFF, is compared to an internal reference, VPOFF (typically 2 V) to disable the PFC stage. In high power SSL applications it is often desired to control the PFC disable point from the secondary side. An optocoupler can be used as a logic disable to ground the PONOFF pin when the PFC needs to be disabled. 

Once VPONOFF decreases below VPOFF, the PFC disable timer, tPdisable, is enabled. The PFC disable timer is typically 500 ms. The PFC stage is disabled once the timer expires. The PFC stage is enabled once VPONOFF exceeds VPOFF by VPONHYS for a period longer than the PFC enable filter, tPenable(filter), typically 100 s. A shorter delay for the PFC enable threshold is used to reduce the bulk capacitor requirements during a step load response. Figure 33 shows the block diagram of the PFC disable circuit. 

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**NCL30030** 

**==> picture [448 x 190] intentionally omitted <==**

**----- Start of picture text -----**<br>
QFB V to I<br>Converter<br>PFC Disable<br>Demag QZCD  Timer<br>Time Soft−Start Complete<br>Enable<br>Calculator<br>QDRV tPdisable Release<br>PControl<br>Reset<br>S Q Disable PFC<br>IPONOFF Dominant<br>Reset<br>Latch PFC Enable<br>PONOFF R Q Timer<br>PONOFF −Comparator Filter Delay tPenable<br>CPONOFF + tPenable(filter)<br>RPONOFF VPOFF<br>Hysteresis Control<br>+<br>−<br>**----- End of picture text -----**<br>


**Figure 33. PFC On/Off Control Circuitry** 

## **PFC SKIP** 

The PFC stage incorporates skip cycle operation at light loads to reduce input power. Skip operation disables the PFC stage if the PControl voltage decreases below the skip threshold. The skip threshold voltage is typically 25 mV (�VPSKIP) above the PControl minimum voltage clamp, VPControl(MIN). The PFC stage is enabled once VPControl increases above the skip threshold by the skip hysteresis, VPSKIP(HYS). PFC skip is disabled during any initial PFC startup and when the PFC is in a UVP. Skip operation will become active after the PFC has reached regulation. 

## **PFC AND FLYBACK DRIVERS** 

The NCL30030 maximum supply voltage, VCC(MAX), is 30 V. Typical high voltage MOSFETs have a maximum gate voltage rating of 20 V. Both the PFC and flyback drivers incorporate an active voltage clamp to limit the gate voltage on the external MOSFETs. The PFC and flyback voltage clamps, VPDRV(high2) and VQDRV(high2), are typically 12 V with a maximum limit of 14 V. 

## **AUTO−RECOVERY** 

The controller is disabled and enters “triple−hiccup” mode if VCC drops below VCC(off). The controller will also enter “triple−hiccup” mode if an overload fault is detected on the non−latching version. A hiccup consists of VCC falling down to VCC(off) and charging up to VCC(on). The controller needs to complete 3 hiccups before restarting. 

## **TEMPERATURE SHUTDOWN** 

An internal thermal shutdown circuit monitors the junction temperature of the IC. The controller is disabled if the junction temperature exceeds the thermal shutdown threshold, TSHDN, typically 150°C. A continuous VCC hiccup is initiated after a thermal shutdown fault is detected. The controller restarts at the next V once the IC CC(on) temperature drops below below TSHDN by the thermal shutdown hysteresis, TSHDN(HYS), typically 40°C. 

The thermal shutdown fault is also cleared if VCC drops below VCC(reset), a brown−out fault is detected or if the line voltage is removed. A new power up sequences commences at the next V once all the faults are removed. CC(on) 

## **ORDERING INFORMATION** 

|**ORDERING INFORMATION**|||
|---|---|---|
|**Device**|**Package**|**Shipping**†|
|NCL30030B1DR2G|SOIC16 NB LESS PIN 2<br>(Pb−Free)|2500 / Tape & Reel|
|NCL30030B2DR2G|||
|NCL30030B3DR2G|||
|NCL30030A1DR2G*|||
|NCL30030A2DR2G*|||
|NCL30030A3DR2G*|||



†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 

*Please contact local sales representative for availability 

**www.onsemi.com** 

**31** 

**NCL30030** 

## **PACKAGE DIMENSIONS** 

**==> picture [485 x 434] intentionally omitted <==**

**----- Start of picture text -----**<br>
SOIC−16 NB MISSING PIN 2<br>CASE 751DT<br>ISSUE O<br>NOTE 5<br>D NOTES:<br>A 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.<br>16 9 2X 2. CONTROLLING DIMENSION: MILLIMETERS.<br>0.10 C D 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.<br>ALLOWABLE PROTRUSION SHALL BE 0.10 mm IN EXCESS OF<br>MAXIMUM MATERIAL CONDITION.<br>F 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH,<br>E E1 NOTE 4 NOTE 6 PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONSOR GATE BURRS SHALL NOT EXCEED 0.25 mm PER SIDE.<br>A1 DIMENSIONS D AND E ARE DETERMINED AT DATUM F.<br>5. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM F.<br>6. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM THE SEATING<br>0.20 C 1 B 8 15X b L2 DETAIL AL C SEATINGPLANE PLANE TO THE LOWEST POINT ON THE PACKAGE BODY. MILLIMETERS<br>2X 4 TIPS T NOTE 5 a TOP VIEW e  eo 0.25 M C A-B D - [OY] DIMA MIN 1.35 MAX 1.75<br>A1 0.10 0.25<br>2X b 0.35 0.49<br>0.10 C A-B DETAIL A c 0.17 0.25<br>D D 9.80 10.00<br>0.10 C E 6.00 BSC<br>0.10 C E1 3.90 BSC<br>e 1.27 BSC<br>L 0.40 1.27<br>L2 0.203 BSC<br>A = SIDE VIEWe C SEATINGPLANE [=] z END VIEW =<br>RECOMMENDED<br>SOLDERING FOOTPRINT*<br>15X<br>1.52<br>16 9<br>uoonooo0 )<br>7.00<br>—.{_.—<br>1 8<br>' wooo0n..<br>1.27 15X<br>aR IL 0.60<br>PITCH<br>DIMENSIONS: MILLIMETERS<br>*For additional information on our Pb−Free strategy and soldering<br>details, please download the ON Semiconductor Soldering and<br>Mounting Techniques Reference Manual, SOLDERRM/D.<br>**----- End of picture text -----**<br>


ON Semiconductor and the         are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf.  SCILLC reserves the right to make changes without further notice to any products herein.  SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.  “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time.  All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts.  SCILLC does not convey any license under its patent rights nor the rights of others.  SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.  Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.  SCILLC is an Equal Opportunity/Affirmative Action Employer.  This literature is subject to all applicable copyright laws and is not for resale in any manner. 

## **PUBLICATION ORDERING INFORMATION** 

**LITERATURE FULFILLMENT** : **N. American Technical Support** : 800−282−9855 Toll Free **ON Semiconductor Website** : **www.onsemi.com** Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 5163, Denver, Colorado 80217 USA **Europe, Middle East and Africa Technical Support: Order Literature** : http://www.onsemi.com/orderlit **Phone** : 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 **Fax** : 303−675−2176 or 800−344−3867 Toll Free USA/Canada **Japan Customer Focus Center** For additional information, please contact your local **Email** : orderlit@onsemi.com Phone: 81−3−5817−1050 Sales Representative 

## **LITERATURE FULFILLMENT** : 

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**NCL30030/D** 

**32**
Updated at February 9, 2023
onsemi is a premier global supplier of intelligent power and sensing technologies, driving disruptive innovations across the automotive, industrial, and cloud infrastructure markets. Recognized for their commitment to sustainability and reliable supply chains, the company accelerates advancements in vehicle electrification, industrial automation, and 5G networks by solving the industry's most complex design challenges. At the core of their portfolio is an industry-leading selection of discrete semiconductors. This extensive range features thousands of high-performance bipolar transistors, single and dual MOSFETs, and a comprehensive array of diodes, including Zener, Schottky, and fast-recovery rectifiers. Engineered for superior thermal performance and energy efficiency, these foundational components are critical for demanding power conversion, switching, and signal conditioning applications. Beyond essential discretes, onsemi provides a robust suite of advanced power management and circuit protection solutions. Their lineup includes intelligent power modules, single IGBTs, and transient voltage suppression (TVS) diodes designed to safeguard sensitive circuitry. Complimented by integrated passive filters, AC/DC LED driver ICs, and specialized sub-2.4GHz RF transceivers, onsemi equips engineers with the scalable, high-quality technologies needed to build a cleaner, smarter, and more connected world.
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