MUN12AD01-SG

## **1000mA, High Efficiency uPOL Module** 

## **uPOL MODULE MUN12AD01-SG** 

## **FEATURES:** 

- High Density Fully Integration Module 

- 1000mA Output Current 

- Input Voltage Range from 4.5V to 16.0V 

- ◼ Output Voltage Range from 0.8V to 6.0V 

- 94% Peak Efficiency at 5 Vin to 3.3 Vout 

- ◼ Force PWM mode 

- Enable Function 

- Protections (UVLO, OCP: Non-latching) 

- Internal Soft Start 

## **GENERAL DESCRIPTION:** 

The MUN12AD01-SG is non-isolated dc-dc converters. The PWM switching regulator, high frequency power inductor, and most of support components are integrated in one hybrid package. 

Other features include remote enable function, internal soft-start, non-latching over current protection, and input under voltage locked-out capability. 

- Compact Size: 3.9mm*2.6mm*1.7mm 

- Pb-free for RoHS compliant 

- MSL 2, 260°C Reflow 

## **APPLICATIONS:** 

- DSL Modem / LCD TV 

The low profile and compact size package (3.9mm × 2.6mm x 1.7mm) is suitable for automated assembly by standard surface mount equipment. The MUN12AD01-SG is Pb-free and RoHS compliance. 

- Portable TV / Access Point Router 

## **TYPICAL APPLICATION CIRCUIT & PACKAGE SIZE:** 

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FIG.1 TYPICAL APPLICATION CIRCUIT<br>**----- End of picture text -----**<br>


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1.7mm<br>2.6mm<br>3.9mm<br>Ww<br>FIG.2 HIGH DENSITY uPOL MODULE<br>**----- End of picture text -----**<br>


1 

Rev.A2 

**MUN12AD01-SG** 

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  ORDER INFORMATION:  Ce<br>**----- End of picture text -----**<br>


||**Ambient Temp. Range**|**Package**|||
|---|---|---|---|---|
|**Part Number**|||**MSL**|**Note**|
||**(°C)**|**(Pb-Free)**|||
|MUN12AD01-SG|-40 ~ +85|DFN|Level 2|-|
||||||
|**Order Code**||**Packing**||**Quantity**|
|MUN12AD01-SG||Tape and reel||1000|



## **PIN CONFIGURATION:** 

**==> picture [332 x 100] intentionally omitted <==**

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74<br>1  BS  Vout  6<br>4[|<br>4 4<br>2  GND  Vin  5<br>Lo _ Lo _ 4<br>4 CO<br>3  FB  EN  4<br>**----- End of picture text -----**<br>


## **TOP VIEW** 

|**Symbol**|**Pin No.**|**Description**|
|---|---|---|
|BS|1|Boot-Strap Pin. No need connection.|
|GND|2|Power ground pin for signal, input, and output return path. This pin needs to be<br>connected to one or moregroundplanes directly.|
|FB|3|Feedback input. Connect to output through a voltage dividing resistor between<br>this pin to GND for adjusting output voltage. Place this resistor as closely as<br>possible to thispin.|
|EN|4|On/Off control pin for module.|
|VIN|5|Input pin. Decouple this pin to GND pin with 10uF ceramic cap|
|VOUT|6|Power output pin. Connect to output for the load.|



2 

Rev.A2 

**MUN12AD01-SG** 

## **ELECTRICAL SPECIFICATIONS:** ~~Fe~~ 

CAUTION: Do not operate at or near absolute maximum rating listed for extended periods of time. This stress may adversely impact product reliability and result in failures not covered by warranty. 

|**Parameter**<br>~~es~~|**Description**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|
|◼<br>Absolute Maximum Ratings<br>~~es~~<br>~~|~~||||||
|VIN to GND<br>~~ee~~|(Note 3)<br>~~ee~~|-<br>~~ee~~|-<br>~~ee~~|+20<br>~~ee~~|V<br>~~ee~~|
|EN to GND<br>~~RG~~<br>~~es~~|(Note 1)<br>~~RG~~|-<br>~~RG~~|-<br>~~RG~~|VIN+0.3<br>~~RG~~|V<br>~~RG~~|
|Tc<br>~~es~~<br>~~ee~~|Case Temperature of Inductor(Note 2)|-40|-|+110|°C|
|Tj<br>~~es~~<br>~~ee~~<br>~~ee~~|Junction Temperature, Main IC(Note 2)|Junction Temperature, Main IC(Note 2)<br>-40|-|+125|°C|
|Tstg<br>~~ee~~<br>~~ee~~|Storage Temperature|-40|-|+125|°C|
|◼<br>Recommendation Operating Ratings<br>~~ee~~<br>~~|~~<br>~~ee~~||||||
|VIN<br>~~|~~<br>~~ee~~<br>~~es~~|Input Supply Voltage<br>~~|~~|+4.5<br>~~|~~|-<br>~~|~~|+16<br>~~|~~|V<br>~~|~~|
|VOUT<br>~~ee~~<br>~~es~~<br>~~es~~|Adjusted Output Voltage|+0.8|-|+6.0|V|
|Ta<br>~~es~~<br>~~es~~<br>~~en~~|Ambient Temperature (Note 2)|-40|-|+85|°C|
|◼<br>Thermal Information<br>~~es~~<br>~~en~~||||||
|Rth(jchoke-a)<br>~~en~~|Thermal resistance from junction to<br>ambient. (Note 1)|-|50|-|°C/W|



## NOTES: 

1. Rth(jchoke-a) is measured with the component mounted on an effective thermal conductivity test board on 0 LFM condition. The test board size is 30mm× 30mm× 1.6mm with 4 layers 2oz. The test condition is complied with JEDEC EIJ/JESD 51 Standards. 

2. Only for over stress test, the normal operation condition bases on recommedation operating ratings. Need to consider the thermal de-rating depend on application 

3. Absolute maximum rating of VIN is from IC datasheet, please consider to set de-rating for your application. 

3 

Rev.A2 

**MUN12AD01-SG** 

## **ELECTRICAL SPECIFICATIONS: (Cont.)** ~~Pe~~ 

Conditions: TA = 25 ºC, unless otherwise specified. Test Board Information: 30mm× 30mm× 1.6mm, 4 layers 2oz. The output ripple and transient response measurement is short loop probing and 20MegHz bandwidth limited. Vin = 12V, Vout = 3.3V, Cin =10uF/50V/1210/X7R, Cout = 22uF/16V/1210/X7R. 

|~~es~~|||||||
|---|---|---|---|---|---|---|
|**Symbol**<br>~~es~~|**Parameter**|**Conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|Switching<br>Frequency<br>~~es~~<br>~~CR~~|||**-**|1.2|-|MHz|
|◼<br>Input Characteristics<br>~~es~~<br>~~CR~~|||||||
|IIN<br>~~CR~~|Input supply bias<br>current|Input supply bias<br>Vin = 12V, Iout = 0A<br>EN = With pull-up 100kΩto VIN<br>Vout = 3.3V|to VIN<br>-|14|-|mA|
|IS|Input supply<br>current|Iout = 5mA<br>Vout = 3.3V|-<br>~~ee~~|14.3<br>~~ee~~|-<br>~~ee~~|mA<br>~~ee~~|
|||Iout = 100mA<br>Vout = 3.3V<br>~~ee~~|-<br>~~ee~~<br>~~ee~~<br>~~e~~|41.7<br>~~ee~~<br>~~ee~~<br>~~e~~|-<br>~~ee~~<br>~~ee~~<br>~~ee~~|mA<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|||Iout = 1000mA<br>Vout = 3.3V<br>~~e~~|-<br>~~ee~~<br>~~e~~~~**e**~~<br>~~e~~|319<br>~~ee ~~<br>~~**e**~~<br>~~e~~|-<br> ~~ee ~~<br>~~**e**~~<br>~~ee~~|mA<br> ~~ee~~<br>~~**e**~~<br>~~ee~~|
|◼<br>Output Characteristics<br>~~e~~<br>~~ee ee~~<br>~~ee~~|||||||
|IOUT(DC)|Output<br>continuous<br>current range|Vin=12V, Vout=3.3V|0|-|1000|mA|
|VO(SET)<br>~~>.~~|Ouput voltage<br>set point<br>~~>.~~|With 1% tolerance for external<br>resistor used to set output<br>voltage<br>~~>.~~|-3.0<br>~~es~~|-<br>~~ee~~|+3.0|% VO(SET)|
|ΔVOUT<br>/ΔVIN<br>~~a ees~~<br>~~>.~~|Line regulation<br>accuracy<br>~~ees~~<br>~~>.~~|Vin = 12V to 5.0V<br>Vout = 3.3V,Iout = 1000mA<br>~~ees~~<br>~~>.~~|-<br>~~ees~~<br>~~es~~|0.2<br>~~ees~~<br>~~ee~~|-<br>~~ees~~|% VO(SET)<br>~~ees~~|
|ΔVOUT<br>/ΔIOUT<br>~~>.~~|Load regulation<br>accuracy<br>~~>.~~|Iout = 0A to 1000mA<br>Vin = 12 V,Vout = 3.3V<br>~~>.~~|-<br>~~es~~<br>~~>~~|0.5<br>~~ee~~<br>~~>~~|-<br>~~>~~|% VO(SET)<br>~~>~~|
|VOUT(AC)<br>~~>.~~|Output ripple<br>voltage<br>~~>.~~|Vin = 12V, Vout = 1.2V<br>IOUT = 1000mA<br>~~>.~~|-<br>~~es~~<br>~~>~~|8<br>~~ee~~<br>~~>~~|-<br>~~>~~|mVp-p<br>~~>~~|
|||Vin = 12V, Vout = 5.0V<br>IOUT = 1000mA<br>~~>.~~|-<br>~~es~~|11<br>~~ee~~|-|mVp-p|
|◼<br>Dynamic Characteristics<br>~~Rs~~|||||||
|ΔVOUT-DP|Voltage change<br>for positive load<br>step|Iout = 0.5A to 1.0A<br>Current slew rate = 0.06A/uS<br>Vin = 12V, Vout = 3.3V|-|35|-|mVp-p|
|ΔVOUT-DN|Voltage change<br>for negative load<br>step|for negative load<br>Iout = 1.0A to 0.5A<br>Current slew rate = 0.06A/uS<br>Vin = 12V, Vout = 3.3V|-|35|-|mVp-p|



4 

Rev.A2 

**MUN12AD01-SG** 

> **ELECTRICAL SPECIFICATIONS: (Cont.)** ~~Fe~~ 

Conditions: TA = 25 ºC, unless otherwise specified. Test Board Information: 30mm× 30mm× 1.6mm, 4 layers 2oz. The output ripple and transient response measurement is short loop probing and 20MegHz bandwidth limited. Vin = 12V, Vout = 3.3V, Cin =10uF/50V/1210/X7R, Cout = 22uF/16V/1210/X7R. 

|**Symbol**|**Parameter**|**Conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|◼<br>Control Characteristics|||||||
|VEN_TH|Enable<br>threshold<br>voltage||1.5|-|-|V|
||Disable<br>threshold<br>voltage||-|-|0.4|V|
|◼<br>Fault Protection|||||||
|VUVLO_TH|Input under<br>voltage lockout<br>threshold|Falling|-|-|4.5|V|
|TOTP|Over temp<br>protection||-|150|-|°C|
|ILIMIT_TH|Current limit<br>threshold|Peak value of inductor current|1.8|-|3.0|A|



5 

Rev.A2 

**MUN12AD01-SG** 

## **TYPICAL PERFORMANCE CHARACTERISTICS: (1.2 VOUT)** 

Conditions: TA = 25 ºC, unless otherwise specified. Test Board Information: 30mm× 30mm× 1.6mm, 4 layers 2oz. The output ripple and transient response measurement is short loop probing and 20MegHz bandwidth limited. Cin =10uF/50V/1210/X7R, Cout = 22uF/16V/1210/X7R. 

The following figures provide the typical characteristic curves at 1.2Vout. 

**==> picture [405 x 346] intentionally omitted <==**

**----- Start of picture text -----**<br>
FIG.3 EFFICIENCY V.S. LOAD CURRENT  FIG.4 DE-RATING CURVE AT 12V VIN<br>Tek Stop<br>2.50GS/s @r; 2.50GS/s @r<br>G>~0.00000s__10k points___1.00mv G>~0.00000 s__10k points__1.60mv<br>Value Mean Min Max Std Dev Value Mean Min Max Std Dev<br>5.20mv 5.90m 4.40m 7.20m 536 @ Peak—Peak 7.60mvV 6.28m 4.40m 8.8om 932<br>FIG.5 OUTPUT RIPPLE  FIG.6 OUTPUT RIPPLE<br>(12V VIN, IOUT=0 A) (12V VIN, IOUT=1 A)<br>it = Tek Stop — =<br>| “|<br>ee<br>TOOus 10.0MS/s @sr u<br>@ 500mA 28% Gey255.000uNs 10k points 690mA<br>value Mean Min Max Std Dev<br>18.73mV-8.755m -351.9m —151.9m 45.91m 200ps 5.00MS/s @r<br>34.88mV.25.89m 0.000 127.7m 18.49m G>¥800.000Ns 10k points 7.40V<br>-16.15mV_-17.13m_— -351.9m___151.9m 43.64m<br>FIG.7 TRANSIENT RESPONSE  FIG.8 TURN-ON<br>(12V VIN, 50% to 100% LOAD STEP)  (12V VIN, IOUT=1 A)<br>**----- End of picture text -----**<br>


6 

Rev.A2 

**MUN12AD01-SG** 

## **TYPICAL PERFORMANCE CHARACTERISTICS: (1.8 VOUT)** 

Conditions: TA = 25 ºC, unless otherwise specified. Test Board Information: 30mm× 30mm× 1.6mm, 4 layers 2oz. The output ripple and transient response measurement is short loop probing and 20MegHz bandwidth limited. Cin =10uF/50V/1210/X7R, Cout = 22uF/16V/1210/X7R. The following figures provide the typical characteristic curves at 1.8Vout. 

**==> picture [407 x 346] intentionally omitted <==**

**----- Start of picture text -----**<br>
FIG.9 EFFICIENCY V.S. LOAD CURRENT  FIG.10 DE-RATING CURVE AT 12V VIN<br>Tek Stop<br>Eecececcas 1Eecececes<br>400ns 2.50GS/s @r 400ns 2.50GS/s @r<br>G>~0.00000s__10k points___1.60mv. G>~0.00000 s__10k points__1.60mv<br>Value Mean Min Max Std Dev Value Mean Min Max Std Dev<br>6.40mvV 6.31m 0.00 8.8om 979 @ Peak—Peak 8.40mv 6.50m 0.00 10.0m 1.13m<br>FIG.11 OUTPUT RIPPLE  FIG.12 OUTPUT RIPPLE<br>(12V VIN, IOUT=0 A) (12V VIN, IOUT=1 A)<br>it = Tek Stop =<br>. "<br>—— i<br>T00us 10.0MS/s a aee<br>@ 500mA 28% Gey255.000uNs 10k points 690mA<br>value Mean Min Max Std Dev<br>21.51mV-22.86m 20.84m 24.53m 775.94 200ys 5.00MS/s @r<br>42.83mV=21.32mV_-20.31m_— 43.17m —22.26m__——-18.20m___1.291m39.70m 45.95m 1.729m G+Y800.000us 10k points 7.40V<br>FIG.13 TRANSIENT RESPONSE  FIG.14 TURN-ON<br>(12V VIN, 50% to 100% LOAD STEP)  (12V VIN, IOUT=1 A)<br>**----- End of picture text -----**<br>


7 

Rev.A2 

**MUN12AD01-SG** 

## **TYPICAL PERFORMANCE CHARACTERISTICS: (3.3 VOUT)** 

Conditions: TA = 25 ºC, unless otherwise specified. Test Board Information: 30mm× 30mm× 1.6mm, 4 layers 2oz. The output ripple and transient response measurement is short loop probing and 20MegHz bandwidth limited. Cin =10uF/50V/1210/X7R, Cout = 22uF/16V/1210/X7R. The following figures provide the typical characteristic curves at 3.3Vout. 

**==> picture [411 x 346] intentionally omitted <==**

**----- Start of picture text -----**<br>
FIG.15 EFFICIENCY V.S. LOAD CURRENT  FIG.16 DE-RATING CURVE AT 12V VIN<br>Tek Stop<br>oei aa Sina re Aha2.50GS/s ee@r -we" aaoa ral ail Tew2.50GS/s a@r<br>G>~0.00000s__10k points___2.40mv G>~0.00000 s__10k points__2.40mv<br>Value Mean Min Max Std Dev Value Mean Min Max Std Dev<br>8.00mv 6.86m 0.00 10.0m 1.73m @ Peak—Peak 9.60mvV 6.96m 0.00 10.4m 1.80m<br>FIG.17 OUTPUT RIPPLE  FIG.18 OUTPUT RIPPLE<br>(12V VIN, IOUT=0 A) (12V VIN, IOUT=1 A)<br>it = Tek Stop =<br>50.0mvws T00us 10.0MS/s a aeo eeee<br>@ 500mA 28% Gey255.000uNs 10k points 690mA<br>value Mean Min Max Std Dev<br>34.93mV30.13m 5.344m 65.14m 21.47m 200ys 5.00MS/s @r<br>—34.84mV_-28.93m_69.77mV 59.06m — -63.94m_11.96m 937.5128.1m 44.17m22.88m G+Y800.000us 10k points 7.40V<br>FIG.19 TRANSIENT RESPONSE  FIG.20 TURN-ON<br>(12V VIN, 0% to 100% LOAD STEP)  (12V VIN, IOUT=1 A)<br>**----- End of picture text -----**<br>


8 

Rev.A2 

**MUN12AD01-SG** 

## **TYPICAL PERFORMANCE CHARACTERISTICS: (5.0 VOUT)** 

Conditions: TA = 25 ºC, unless otherwise specified. Test Board Information: 30mm× 30mm× 1.6mm, 4 layers 2oz. The output ripple and transient response measurement is short loop probing and 20MegHz bandwidth limited. Cin =10uF/50V/1210/X7R, Cout = 22uF/16V/1210/X7R. 

The following figures provide the typical characteristic curves at 5.0Vout. 

**==> picture [411 x 346] intentionally omitted <==**

**----- Start of picture text -----**<br>
FIG.21 EFFICIENCY V.S. LOAD CURRENT  FIG.22 DE-RATING CURVE AT 12V VIN<br>Tek Stop<br>Pp 1Eececeaces<br>Geena aeaee400ns 2.50GS/s @r  [ - -400ns Gaaee2.50GS/s @r<br>G>~0.00000s__10k points ___3.00mv G>~0.00000 s__10k points__2.60mv<br>Value Mean Min Max Std Dev Value Mean Min Max Std Dev<br>10.0mv 7.58m 0.00 11.6m 2.53m @ Peak—Peak 10.8mv 7.82m 0.00 11.6m 2.56m<br>FIG.23 OUTPUT RIPPLE  FIG.24 OUTPUT RIPPLE<br>(12V VIN, IOUT=0 A) (12V VIN, IOUT=1 A)<br>it = Tek Stop =<br>50.0mvws T00us 10.0MS/s a aeo<br>@ 500mA 28% Gey255.000uNs 10k points 690mA<br>Value Mean Min Max Std Dev<br>53.32mV 36.79m 5.344m 65.14m 23.89m 200ys 5.00MS/s @r<br>—52.84mvV_-34.55m106.2mVv71.34m — -63.94m_13.66m 937.5128.1m 49.32m25.52m G+Y800.000us 10k points 7.40V<br>FIG.25 TRANSIENT RESPONSE  FIG.26 TURN-ON<br>(12V VIN, 50% to 100% LOAD STEP)  (12V VIN, IOUT=1 A)<br>**----- End of picture text -----**<br>


9 

Rev.A2 

**MUN12AD01-SG** 

> **APPLICATIONS INFORMATION: (Cont.)** ~~CT~~ 

## **SAFETY CONSIDERATIONS:** 

Certain applications and/or safety agencies may require fuses at the inputs of power conversion components. Fuses should also be used when there is the possibility of sustained input voltage reversal which is not current limited. For greatest safety, we recommend a fast blow fuse installed in the ungrounded input supply line. The installer must observe all relevant safety standards and regulations. For safety agency approvals, install the converter in compliance with the end-user safety standard. 

## **INPUT FILTERING:** 

The module should be connected source with low AC impedance source supply and a highly inductive in which line inductance can affect the stability of the module. An input capacitance must be placed directly to the input pin of the module, to minimize input ripple voltage and ensure module stability. 

## **OUTPUT FILTERING:** 

To reduce output ripple and improve the dynamic response as step load changes, the additional capacitor at the output must be used. Low ESR polymer and ceramic capacitors are recommended to improve the output ripple and dynamic response of the module. 

## **PROGRAMMING OUTPUT VOLTAGE:** 

The module has an internal 0.6V ± 2% reference voltage. The output voltage can be programed by the dividing resistance RFB which respects to FB pin and GND pin. The output voltage can be calculated as shown in Equation 1.(R1 is integrated in Module :100K Ω +/-1%) 

Vout=0.6*(1+R1/RFB) 

|Vout (V)|1|1.2|1.5|1.8|2.5|3.3|5.0|
|---|---|---|---|---|---|---|---|
|RFB|150KΩ|100KΩ|66.67KΩ|50KΩ|31.58KΩ|22.22KΩ|13.64KΩ|



10 

Rev.A2 

**MUN12AD01-SG** 

## **APPLICATIONS INFORMATION: (Cont.)** LC 

## **LOAD TRANSIENT CONSIDERATIONS:** 

The MUN12AD01-SG integrates the compensation components to achieve good stability and fast transient responses. In some applications, adding a 100pF ceramic cap between Vout and FB may further speed up the load transient responses and is thus recommended for applications with large load transient step requirements. 

## **REFERENCE CIRCUIT FOR GENERAL APPLICATION:** 

Figure 27 shows the module application schematics for input voltage +12V and turn on by input voltage directly through enable resistor (R1). 

## **FIG.27 REFERENCE CIRCUIT FOR GENERAL APPLICATION** 

11 

Rev.A2 

**MUN12AD01-SG** 

## **APPLICATIONS INFORMATION: (Cont.)** 

## **RECOMMEND PCB LAYOUT:** 

Figure 28 shows recommendation PCB layout for using uPOL module, 

- ➢ C3/C4 are bypass filter for high frequency noise. 

- ➢ Design paths of main current wide and short as Make the traces of the main current paths as short and wide as possible. 

- ➢ Place the input/out capacitor as close as possible to the uPOL module pins. 

- ➢ Ensure all feedback network connections are short, direct and don’t close BS pin. 

- ➢ C5 and R2 must be placed as close as possible to the FB pin. 

- ➢ The GND pin and should be connected to a strong ground plane for heat dissipating. 

**==> picture [358 x 152] intentionally omitted <==**

**----- Start of picture text -----**<br>
The output capacitor must  ooo ooo C3: High Frequency Filter<br>ooo ooo OOo<br>be placed near the IC.  JB! Tz) el ooo<br>ehol |S) ll coe<br>oh) ie<br>_<br>N So aN<br>(3) x<br>N<br>rag ra 5<br>| oa<br>|g |<br>LjitLILI<br>eoo°0 | ea]<br>Input capacitor must be placed<br>ooo =<br>ooo as close to the IC as possible.<br>**----- End of picture text -----**<br>


**FIG.28 PCB LAYOUT** 

12 

Rev.A2 

**MUN12AD01-SG** 

> **APPLICATIONS INFORMATION: (Cont.)** ~~Lt~~ 

## **Thermal Considerations:** 

All of thermal testing condition is complied with JEDEC EIJ/JESD 51 Standards. Therefore, the test board size is 30mm× 30mm× 1.6mm with 4 layers. The case temperature of module sensing point is shown as Figure 29. Then Rth(jchoke-a) is measured with the component mounted on an effective thermal conductivity test board on 0 LFM condition. The MUN12AD01-SG module is designed for using when the case temperature is below 110°C regardless the change of output current, input/output voltage or ambient temperature. 

**FIG 29. Case Temperature Sensing Point** 

13 

Rev.A2 

**MUN12AD01-SG** 

> **REFLOW PARAMETERS:** ~~|~~ 

Lead-free soldering process is a standard of electronic products production. Solder alloys like Sn/Ag, Sn/Ag/Cu and Sn/Ag/Bi are used extensively to replace the traditional Sn/Pb alloy. Sn/Ag/Cu alloy (SAC) is recommended for this power module process. In the SAC alloy series, SAC305 is a very popular solder alloy containing 3% Ag and 0.5% Cu and easy to obtain. Figure 30 shows an example of the reflow profile diagram. Typically, the profile has three stages. During the initial stage from room temperature to 150°C, the ramp rate of temperature should not be more than 3°C/sec. The soak zone then occurs from 150°C to 200°C and should last for 60 to 120 seconds. Finally, keep at over 217°C for 60 seconds limit to melt the solder and make the peak temperature at the range from 240°C to 250°C. It is noted that the time of peak temperature should depend on the mass of the PCB board. The reflow profile is usually supported by the solder vendor and one should adopt it for optimization according to various solder type and various manufacturers’ formulae. 

**FIG.30 Recommendation Reflow Profile** 

14 

Rev.A2 

**MUN12AD01-SG** 

> **PACKAGE OUTLINE DRAW:** ~~Lt~~ 

**==> picture [49 x 8] intentionally omitted <==**

**----- Start of picture text -----**<br>
Unit:mm<br>**----- End of picture text -----**<br>


15 

Rev.A2 

## **MUN12AD01-SG** 

> **LAND PATTERN REFERENCE:** ~~ee~~ 

Unit:mm 

RECOMMENDED STENCIL PATTERN BASED ON 0.1mm THICKNESS STENCIL 

16 

Rev.A2 

**MUN12AD01-SG** 

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|---|---|---|---|---|---|---|---|
|**PACKING REFERENCE:**<br>~~|~~||||||||
|Unit: mm|||**Package In Tape Loading Orientation**|**Package In Tape Loading Orientation**||||
||||Sprocket|Hole|PIN1|||
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|||||**Tape Dimension**||||
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|||||<br>D1||pulling direction||Ka|
|carrier cavity||||||||
|||A0|2.9±|±0.10<br>E|1.75±|±0.10||
|||B0|4.2±|±0.10<br>K0|1.88±|±0.10||
|||F|5.50±0.05<br>P0||4.00±|±0.10||
|||W|12.00 ±0.30|12.00 ±0.30<br>P1|8.00±|±0.10||
|||D0|φ1.55 ±0.05|1.55 ±0.05<br>P2|2.00±|±0.05||
|||D1|φ1.50±0.10<br>t||0.25±|±0.10||



17 

Rev.A2 

**MUN12AD01-SG** 

**==> picture [197 x 12] intentionally omitted <==**

**----- Start of picture text -----**<br>
  PACKING REFERENCE: (Cont.)<br>**----- End of picture text -----**<br>


**==> picture [338 x 354] intentionally omitted <==**

**----- Start of picture text -----**<br>
Unit: mm<br>Reel Dimension<br>See Detail A<br>a<br>/ \<br>.<br>| \ \<br>{ | | VA<br>Detail A<br>TOP COVER TAPE .<br>\ a<br>400ae ’ Qe<br>a o e Me<br>Peel Strength of Top Cover Tape  a mo,iaxe<br>The peel speed shall be about 300mm/min.  é oe<br>The peel force of top cover tape is between 0.1N to 1.3N<br>**----- End of picture text -----**<br>


18 

Rev.A2 

**MUN12AD01-SG** 

> **REVISION HISTORY:** ~~Fe~~ 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|2014.08.01|00|Preliminary Spec. issued initially.|
|2014.08.07|01|Change Vout range.|
|2014.10.23|02|Changefigure of module; Add Load Transient Consideration.|
|2015.01.07|03|Add package information.|
|2015.06.29|04|Add reflow parameters.<br>Add reference circuit for general application.|
|2015.10.05|05|Add Temperature Information of page 2|
|2015.11.23|06|Update page 14 reflow parameters|
|2016.03.28|07|Change input voltage range from 18V to 16V<br>and output voltage range from 6V to 5V|
|2016.09.29|08|1. Change output voltage form 5V to 6V<br>2. Add Page 2 order information<br>3. Change Page 4~9 test condition and update test figures<br>4. Page 12 add matter needing attention for feedback network|
|2016.12.29|09|Correcting Page 2 package name from QFN to DFN|
|2024.12.16|A1|Synchronized with document management number|



19 

Rev.A2