MMA8652FCR1

MEMS Accelerometer, ± 2g, ± 4g, ± 8g, X, Y, Z, I2C, DFN, 10 Pins, 1024 LSB/g, 512LSB/g, 256LSB/g

⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
Manufacturer: NXP
Product type: MEMS Accelerometers
MEMS Sensor Output:Digital; Measurement Axis:X, Y, Z; Acceleration Range:± 2g, ± 4g, ± 8g; Supply Voltage Min:1.95V; Supply Voltage Max:3.6V; Sensor Case Style:DFN; No. of Pins:10P
MSL: -
SVHC: To Be Advised
No. of Pins: 10Pins
Sensing Axis: X, Y, Z
Product Range: -
Qualification: -
Sensitivity Max: 1024counts/g
Sensitivity Min: 256counts/g
Sensitivity Typ: 1024 LSB/g, 512LSB/g, 256LSB/g
Output Interface: I2C
Sensor Case Style: DFN
MEMS Sensor Output: Digital
Supply Voltage Max: 3.6V
Supply Voltage Min: 1.95V
Sensor Case / Package: DFN
Operating Temperature Max: 85°C
Operating Temperature Min: -40°C
Sensing Range - Accelerometer: ± 2g, ± 4g, ± 8g
Delivery and price
Units per pack	2500
Price	0.868 €
Current stock	1000+
Lead time	7 days
Datasheet
Ni 2) ~~ccc~~ **Freescale Semiconductor** Document Number: MMA8652FC Data Sheet: Technical Data Rev. 3.3, 10/2015 

Rev. 3.3, 10/2015 

An Energy-Efficient Solution by Freescale 

## **MMA8652FC, 3-Axis, 12-bit, Digital Accelerometer** 

## **MMA8652FC** 

The MMA8652FC is an intelligent, low-power, three-axis, capacitive micromachined accelerometer with 12 bits of resolution. This accelerometer is packed with embedded functions with flexible user-programmable options, configurable to two interrupt pins. Embedded interrupt functions enable overall power savings, by relieving the host processor from continuously polling data. There is access to either low-pass or high-pass filtered data, which minimizes the data analysis required for jolt detection and faster transitions. The device can be configured to generate inertial wake-up interrupt signals from any combination of the configurable embedded functions, enabling the MMA8652FC to monitor inertial events while remaining in a low-power mode during periods of inactivity. The MMA8652FC is available in a small 10-pin DFN package (2 mm x 2 mm x 1 mm). 

## **Features** 

- 1.95 V to 3.6 V supply voltage 

- 1.62 V to 3.6 V digital interface voltage 

**==> picture [92 x 144] intentionally omitted <==**

**----- Start of picture text -----**<br>
Top and Bottom View<br>10-pin DFN<br>2 mm x 2 mm x 1 mm<br>Case 98ASA00301D<br>**----- End of picture text -----**<br>


- ±2 g, ±4 g, and ±8 g dynamically selectable full-scale ranges 

- Output Data Rates (ODR) from 1.56 Hz to 800 Hz 

- 12-bit digital output 

- I[2] C digital output interface with programmable interrupts 

- Four embedded channels of configurable motion detection (Freefall, Motion, Pulse, Transient) 

- Orientation (Portrait/Landscape) detection with programmable hysteresis 

- Configurable automatic ODR change triggered by the Auto-Wake/Sleep state change 

- 32-sample FIFO 

- High-Pass Filter Data available per sample and through the FIFO 

- Self-Test 

**==> picture [134 x 132] intentionally omitted <==**

**----- Start of picture text -----**<br>
Top View<br>VDD 1 10 SDA<br>SCL 2 9 GND<br>INT1 3 8 VDDIO<br>BYP 4 7 GND<br>INT2 5 6 GND<br>Pin Connections<br>**----- End of picture text -----**<br>


## **Typical applications** 

- Tilt compensation in e-compass applications 

- Static orientation detection (Portrait/Landscape, Up/Down, Left/Right, Back/ Front position identification) 

- Notebook, tablet, e-reader, and laptop tumble and freefall detection 

- Real-time orientation detection (virtual reality and gaming 3D user orientation feedback) 

- Real-time activity analysis (pedometer step counting, freefall drop detection for HDD, dead-reckoning GPS backup) 

- Motion detection for portable product power saving (Auto-SLEEP and Auto-WAKE for cell phone, PDA, GPS, gaming) 

- Shock and vibration monitoring (mechatronic compensation, shipping and warranty usage logging) 

- User interface (tilt menu scrolling, tap detection for button replacement) 

|**ORDERING INFORMATION**|**ORDERING INFORMATION**|**ORDERING INFORMATION**|**ORDERING INFORMATION**|
|---|---|---|---|
|**Part Number**|**Temperature Range**|**Package Description**|**Shipping**|
|MMA8652FCR1|-40°C to +85°C|DFN-10|Tape and Reel|



Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © 2012–2015 Freescale Semiconductor, Inc. All rights reserved. ~~a~~ =freescale” 

**Table 1. Feature comparison of the MMA865xFC devices** 

|**Table 1. Feature comparison of the MMA865xFC devices**|||
|---|---|---|
|**Feature**<br>~~a~~|**MMA8652FC**<br>~~a~~|**MMA8653FC**<br>~~a~~|
|ADC Resolution (bits)<br>~~a~~<br>~~eC~~|12<br>~~a~~<br>~~eC~~|10<br>~~a~~<br>~~eC~~|
|Digital Sensitivity in 2 g mode (counts/g)<br>~~CO~~|1024<br>~~CO~~|256<br>~~CO~~|
|Low-Power Mode<br>~~CO~~|Yes<br>~~CO~~|Yes<br>~~CO~~|
|Auto-WAKE<br>~~CO~~<br>~~eC~~|Yes<br>~~CO~~<br>~~eC~~|Yes<br>~~CO~~<br>~~eC~~|
|Auto-SLEEP<br>~~CO~~|Yes<br>~~CO~~|Yes<br>~~CO~~|
|32-Level FIFO<br>~~CO~~|Yes<br>~~CO~~|No<br>~~CO~~|
|Low-Pass Filter<br>~~CO~~<br>~~eC~~|Yes<br>~~CO~~<br>~~eC~~|Yes<br>~~CO~~<br>~~eC~~|
|High-Pass Filter<br>~~CO~~|Yes<br>~~CO~~|No<br>~~CO~~|
|Transient Detection with High-Pass Filter<br>~~CO~~|Yes<br>~~CO~~|No<br>~~CO~~|
|Fixed Orientation Detection<br>~~a~~|No<br>~~a~~|Yes<br>~~a~~|
|Programmable Orientation Detection<br>~~CO~~|Yes<br>~~CO~~|No<br>~~CO~~|
|Data-Ready Interrupt<br>~~CO~~|Yes<br>~~CO~~|Yes<br>~~CO~~|
|Single-Tap Interrupt<br>~~a~~|Yes<br>~~a~~|No<br>~~a~~|
|Double-Tap Interrupt<br>~~CO~~|Yes<br>~~CO~~|No<br>~~CO~~|
|Directional Tap Interrupt<br>~~CO~~|Yes<br>~~CO~~|No<br>~~CO~~|
|Freefall Interrupt<br>~~CO~~<br>~~a~~|Yes<br>~~CO~~<br>~~a~~|Yes<br>~~CO~~<br>~~a~~|
|Motion Interrupt with Direction<br>~~CO~~|Yes<br>~~CO~~|No<br>~~CO~~|



**MMA8652FC** 

Sensors Freescale Semiconductor, Inc. 

2 

## **Contents** 

|**1**|**Block Diagram and Pin Descriptions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5**|**Block Diagram and Pin Descriptions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5**|
|---|---|---|
||1.1|Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5|
||1.2|Pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6|
||1.3|Typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6|
|**2**|**Mechanical and Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  7**||
||2.1|Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  7|
||2.2|Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8|
||2.3|Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  9|
||2.4|I2C interface characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  10|
|**3**|**Terminology  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  11**||
||3.1|Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  11|
||3.2|Zero-g offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  11|
||3.3|Self-Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  11|
|**4**|**Modes of Operation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  12**||
|**5**|**Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  13**||
||5.1|Device calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  13|
||5.2|8-bit or 12-bit  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  13|
||5.3|Internal FIFO data buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  14|
||5.4|Low power modes vs. high resolution modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  14|
||5.5|Auto-WAKE/SLEEP mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  15|
||5.6|Freefall and motion detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  15|
||5.7|Transient detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  15|
||5.8|Tap detection  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  16|
||5.9|Orientation detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  16|
||5.10|Interrupt register configurations  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  18|
||5.11|Serial I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  18|
|**6**|**Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  21**||
||6.1|Register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  21|
||6.2|Register bit map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  23|
||6.3|Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  25|
||6.4|FIFO registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  27|
||6.5|System status and ID registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  29|
||6.6|Data configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  31|
||6.7|Portrait/Landscape configuration and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  33|
||6.8|Freefall/Motion configuration and status registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  37|
||6.9|Transient configuration and status registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  42|
||6.10|Pulse configuration and status registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  45|
||6.11|Auto-WAKE/SLEEP detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  51|
||6.12|System and control registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  52|
||6.13|Data calibration registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  57|
|**7**|**Mounting Guidelines  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  58**||
||7.1|Overview of soldering considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  58|
||7.2|Halogen content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  58|
||7.3|PCB mounting/soldering recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  58|
|**8**|**Tape and Reel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  60**|**Tape and Reel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  60**|
||8.1|Tape dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  60|
||8.2|Device orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  60|
|**9**|**Package Dimensions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  61**||
|**10**|**Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  64**||



## **Related Documentation** 

The MMA8652FC device features and operations are described in a variety of reference manuals, user guides, and application notes. To find the most-current versions of these documents: 

1. Go to the Freescale homepage at: 

http://www.freescale.com/ 

2. In the Keyword search box at the top of the page, enter the device number MMA8652FC. 

3. In the Refine Your Result pane on the left, click on the Documentation link. 

**MMA8652FC** 

Sensors Freescale Semiconductor, Inc. 

3 

**MMA8652FC** 

Sensors Freescale Semiconductor, Inc. 

4 

## **1 Block Diagram and Pin Descriptions** 

## **1.1 Block diagram** 

**==> picture [499 x 209] intentionally omitted <==**

**----- Start of picture text -----**<br>
BYP XxX]<br>Voltage<br>VDDIOVDD Xx]ond Regulator InternalOSC ClockGEN x] INT1<br>INT2<br>X-axis<br>Transducer<br>Y-axis C-to-V Embedded I [2] C SDA<br>Gain AAF ADC<br>GND Xx Transducer Converter Functions Interface pammex ] SCL<br>Z-axis Anti-AliasingFilter<br>Transducer<br>_ — _— [—] _— — ~~ ™. ™<br>_—_ [—] _— — ~~ ™.<br>32 Data Point  Freefall Transient Enhanced Single, Double<br>Configurable Detection Orientation with<br>and Motion & Directional Tap<br>FIFO Buffer (i.e., fast motion, Hysteresis<br>Detection Detection<br>with Watermark jolt) and Z-lockout<br>A,2 2<br>Auto-WAKE/Auto-SLEEP Configurable with debounce counter and multiple motion interrupts for control<br>MUX<br>**----- End of picture text -----**<br>


**==> picture [342 x 43] intentionally omitted <==**

**----- Start of picture text -----**<br>
MODE Options<br>Low Power<br>ACTIVE Mode ACTIVE Mode<br>Low Noise + Power<br>High Resolution WAKE Auto-WAKE/SLEEP SLEEP<br>Normal<br>**----- End of picture text -----**<br>


**MODE Options** Low Power Low Noise + Power High Resolution Normal 

**Figure 1. MMA8652FC block diagram** 

**MMA8652FC** 

Sensors Freescale Semiconductor, Inc. 

5 

**1.2 Pin descriptions** 

**==> picture [142 x 76] intentionally omitted <==**

**----- Start of picture text -----**<br>
SDA 10 1 VDD<br>GND SCL<br>VDDIO INT1<br>GND BYP<br>GND 6 5 INT2<br>**----- End of picture text -----**<br>


**Figure 2. Pin connections (bottom view)** 

## **Table 1. Pin descriptions** 

|**Pin #**|**Pin Name**|**Description**|**Notes**|
|---|---|---|---|
|1|VDD|Power supply|Device power is supplied through the VDD line. Power supply decoupling capacitors<br>should be placed as close as possible to pin 1 and pin 8 of the device.|
|2|SCL(1)|I2C Serial Clock|7-bit I2C device address is 0x1D.|
|3|INT1|Interrupt 1 output|The interrupt source and pin settings are user-programmable through the I2C interface.|
|4|BYP|Internal regulator output<br>capacitor connection||
|5|INT2|Interrupt 2 output|See INT1.|
|6|GND|Ground||
|7|GND|Ground||
|8|VDDIO|Digital Interface Power supply||
|9|GND|Ground||
|10|SDA(1)|I2C Serial Data|See SCL.|



1. The control signals SCL and SDA are not tolerant of voltages higher than VDDIO + 0.3 V. If VDDIO is removed, then the control signals SCL and SDA will clamp any logic signals with their internal ESD protection diodes. The SDA and SCL I[2] C connections are open drain, and therefore require a pullup resistor to VDDIO. 

## **1.3 Typical application circuit** 

**==> picture [422 x 141] intentionally omitted <==**

**----- Start of picture text -----**<br>
Top View VDDIO<br>1 k Ω<br>VDD 1 10 SDA<br>O __| =<br>1  μ F 0.1  μ F 2 9<br>VDDIO<br>1 k Ω<br>SCL 3 8 VDDIO<br>BYP 0.1  μ F<br>4 7<br>INT1<br>0.1  μ F<br>5 6<br>INT2<br>**----- End of picture text -----**<br>


**Note:** 4.7 k Ω Pullup resistors on INT1/INT2 can be added for open-drain operation. 

## **Figure 3. Typical application circuit** 

**MMA8652FC** 

Sensors Freescale Semiconductor, Inc. 

6 

**2 Mechanical and Electrical Specifications** 

## **2.1 Absolute maximum ratings** 

Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. Exposure to maximum rating conditions for extended periods may affect device reliability. 

**Table 2. Maximum ratings** 

|**Table 2. Maximum ratings**|**Table 2. Maximum ratings**|**Table 2. Maximum ratings**|**Table 2. Maximum ratings**|
|---|---|---|---|
|**Rating**<br>**Symbol**<br>**Value**<br>**Unit**<br>Maximum acceleration (all axes, 100μs)<br>gmax<br>10,000<br>g<br>Supply voltage<br>VDD<br>–0.3 to +3.6<br>V<br>Input voltage on any control pin (SCL, SDA)<br>Vin<br>–0.3 to VDDIO + 0.3<br>V<br>Drop test<br>Ddrop<br>1.8<br>m<br>Operating temperature range<br>TOP<br>–40 to +85<br>°C<br>Storage temperature range<br>TSTG<br>–40 to +125<br>°C<br>~~ere~~||||
|**Table 3. ESD and latch-up protection characteristics**||||
|**Rating**|**Symbol**|**Value**|**Unit**|
|Human body model|HBM|±2000|V|
|Machine model|MM|±200|V|
|Charge device model|CDM|±500|V|
|Latch-up current at T = 85°C|ILU|±100|mA|



This device is sensitive to mechanical shock. Improper handling can cause permanent damage to the part. 

This part is ESD-sensitive. Improper handling can cause permanent damage to the part. 

**MMA8652FC** 

Sensors Freescale Semiconductor, Inc. 

7 

## **2.2 Mechanical characteristics** 

**Table 4. Mechanical characteristics at  VDD = 2.5 V, VDDIO = 1.8 V, TA = 25°C, unless otherwise noted** 

|**Parameter**<br>~~GO~~|**Symbol**<br>~~GO~~|**Test Conditions**<br>~~GO~~<br>~~ee~~|**Min**<br>~~GO~~<br>~~ee~~|**Typ**<br>~~GO~~<br>~~ee~~|**Max**<br>~~GO~~<br>~~ee~~|**Unit**<br>~~GO~~|
|---|---|---|---|---|---|---|
|Full-Scale measurement range|FS|FS[1:0] set to 00<br>±2 g mode<br>~~ee~~<br>~~ee~~|~~ee~~|±2<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|g|
|||FS[1:0] set to 01<br>±4 g mode<br>~~ee ~~<br>~~ee~~|~~ee~~|±4<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~||
|||FS[1:0] set to 10<br>±8 g mode<br>~~ee~~<br>~~TT~~<br>~~ee~~|~~TT~~|±8<br>~~ee~~<br>~~TT~~<br>~~ee~~|~~ee~~<br>~~TT~~<br>~~ee~~||
|Sensitivity|So|FS[1:0] set to 00<br>±2 g mode<br>~~TT~~<br>~~ee~~<br>~~ee~~|~~TT~~<br>~~ee~~|1024<br>~~TT~~<br>~~ee~~<br>~~ee~~|~~TT~~<br>~~ee~~<br>~~ee~~|LSB/g|
|||FS[1:0] set to 01<br>±4 g mode<br>~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~eee~~|512<br>~~ee~~<br>~~ee~~<br>~~eee~~|~~ee~~<br>~~ee~~<br>~~eee~~||
|||FS[1:0] set to 10<br>±8 g mode<br>~~ee ~~<br>~~ee~~|~~ee~~<br>~~eee~~|256<br>~~ee~~<br>~~eee~~|~~ee~~<br>~~eee~~||
|Sensitivity accuracy<br>~~nD~~|Soa<br>~~nD~~|~~ee ~~<br>~~nD~~|~~eee~~<br>~~nD~~|±2.5<br>~~eee~~<br>~~nD~~|~~eee~~<br>~~nD~~|%<br>~~nD~~|
|Sensitivity change vs. temperature<br>~~ee~~|TCS<br>~~ee~~|–40°C to 85°C<br>~~ee~~|~~ee~~|±0.0074<br>~~ee~~|~~ee~~|%/°C<br>~~ee~~|
|Zero-g level offset accuracy(1)<br>~~ee~~|TyOff<br>~~ee~~|~~ee~~|~~ee~~|±25<br>~~ee~~|~~ee~~|mg<br>~~ee~~|
|Zero-g level offset accuracy,<br>post-board mount(2)<br>~~ee~~|TyOffPBM<br>~~ee~~|~~ee~~|~~ee~~|±33.5<br>~~ee~~|~~ee~~|mg<br>~~ee~~|
|Zero-g level change vs. temperature<br>~~nD~~|TCO<br>~~nD~~|–40°C to 85°C<br>~~nD~~|~~nD~~|±0.27<br>~~nD~~|~~nD~~|mg/°C<br>~~nD~~|
|Self-Test output change (±2 g mode)<br>~~=~~|STOC<br>~~=~~|x<br>~~=~~|~~=——2~~|+90<br>~~=——2~~|~~=——2~~|LSB<br>~~=——2~~|
|||y<br>~~=~~|~~=——2~~<br>~~ee~~|+104<br>~~=——2~~|~~=——2~~||
|||z<br>~~=~~<br>~~ee~~|~~=——2~~<br>~~ee~~<br>~~ee~~|+782<br>~~=——2~~<br>~~ee~~|~~=——2~~<br>~~ee~~||
|ODR accuracy<br>~~ee~~|ODRa<br>~~ee~~|~~ee~~|~~ee~~<br>~~ee~~|±3.1<br>~~ee~~|~~ee~~|%<br>~~ee~~|
|Output data bandwidth<br>~~ee~~|BW<br>~~ee~~|~~ee~~|ODR/3<br>~~ee~~|~~ee~~|ODR/2<br>~~ee~~|Hz<br>~~ee~~|
|Output noise<br>~~ee~~|RMS<br>~~ee~~|Normal mode ODR = 400 Hz<br>~~ee~~|~~ee~~|182<br>~~ee~~|~~ee~~|µg/√Hz<br>~~ee~~|
|Operating temperature range<br>~~ee~~|TAGOC<br>~~ee~~|~~ee~~|–40<br>~~ee~~|~~ee~~|85<br>~~ee~~|°C<br>~~ee~~|



**MMA8652FC** 

Sensors Freescale Semiconductor, Inc. 

8 

**2.3 Electrical characteristics** 

**Table 5.  Electrical characteristics at VDD = 2.5 V, VDDIO = 1.8 V, T = 25°C, unless otherwise noted** 

|**Parameter**<br>~~a~~|**Symbol**<br>|**Test Conditions**<br>|**Min**<br>|**Typ**<br>|**Max**<br>|**Unit**<br>|
|---|---|---|---|---|---|---|
|Supply voltage<br>~~ht~~|VDD<br>~~ht~~|~~ht~~|1.95<br>~~ht~~|2.5<br>~~ht~~|3.6<br>~~ht~~|V<br>~~ht~~|
|Interface supply voltage<br>~~ht~~|VDDIO<br>~~ht~~|~~ht~~|1.62<br>~~ht~~|1.8<br>~~ht~~|3.6<br>~~ht~~|V<br>~~ht~~|
|Low Power mode|IddLP|ODR = 1.563 Hz<br>~~fp~~|~~fp~~|6.5<br>~~fp~~|~~fp~~|μA|
|||ODR = 6.25 Hz<br>~~fp~~|~~fp~~|6.5<br>~~fp~~|~~fp~~||
|||ODR = 12.5 Hz<br>~~jp~~|~~jp~~|6.5<br>~~jp~~|~~jp~~||
|||ODR = 50 Hz<br>~~jp~~|~~jp~~|15<br>~~jp~~|~~jp~~||
|||ODR = 100 Hz<br>~~jp~~|~~jp~~|26<br>~~jp~~|~~jp~~||
|||ODR = 200 Hz<br>~~jp~~|~~jp~~|49<br>~~jp~~|~~jp~~||
|||ODR = 400 Hz<br>~~fp~~|~~fp~~|94<br>~~fp~~|~~fp~~||
|||ODR = 800 Hz<br>~~fp~~|~~fp~~|184<br>~~fp~~|~~fp~~||
|Normal mode|Idd|ODR = 1.563 Hz<br>~~fp~~|~~fp~~|27<br>~~fp~~|~~fp~~|μA|
|||ODR = 6.25 Hz<br>~~fp~~|~~fp~~|27<br>~~fp~~|~~fp~~||
|||ODR = 12.5 Hz<br>~~jp~~|~~jp~~|27<br>~~jp~~|~~jp~~||
|||ODR = 50 Hz<br>~~jp~~|~~jp~~|27<br>~~jp~~|~~jp~~||
|||ODR = 100 Hz<br>~~jp~~|~~jp~~|49<br>~~jp~~|~~jp~~||
|||ODR = 200 Hz<br>~~jp~~|~~jp~~|94<br>~~jp~~|~~jp~~||
|||ODR = 400 Hz<br>~~fp~~|~~fp~~|184<br>~~fp~~|~~fp~~||
|||ODR = 800 Hz<br>~~fp~~|~~fp~~|184<br>~~fp~~|~~fp~~||
|Boot-Up current|IddBoot|VDD = 2.5 V, the current during<br>the Boot sequence is integrated<br>over 0.5 ms, using a<br>recommended bypass cap|||1|mA|
|Value of capacitor on BYP pin|Cap|–40°C to 85°C|75|100|470|nF|
|Standby current|IddStby<br>~~ee~~|25°C<br>~~ee~~|~~ee~~|1.4<br>~~ee~~|5<br>~~ee~~|μA|
|Digital high-level input voltage<br>SCL, SDA<br>~~ee~~|VIH<br>~~ee~~<br>~~ee~~<br>~~ee~~|VDD = 3.6 V, VDDIO = 3.6 V<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.7*VDDIO<br>~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|V<br>~~ee~~<br>~~ee~~|
|Digital low-level input voltage<br>SCL, SDA<br>~~ee~~<br>~~ee~~|VIL<br>~~ee~~<br>~~ee ~~<br>~~ee~~<br>~~ee~~|VDD = 1.95 V, VDDIO = 1.62 V<br>~~ee~~<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|~~ee~~<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|~~ee~~<br> ~~ee~~<br>~~ee~~<br>~~ee~~|0.3*VDDIO<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|V<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|High-level output voltage<br>INT1, INT2<br>~~ee~~<br>~~a~~|VOH<br>~~ee~~<br>~~ee~~<br>~~a~~|VDD = 3.6 V, VDDIO = 3.6 V,<br>IO= 500μA<br>~~ee~~<br>~~ee~~<br>~~a~~|0.9*VDDIO<br>~~ee~~<br>~~ee ~~<br>~~a~~|~~ee~~<br> ~~ee ~~<br>~~a~~|~~ee~~<br> ~~ee ~~<br>~~a~~|V<br>~~ee~~<br> ~~ee~~<br>~~a~~|
|Low-level output voltage<br>INT1, INT2<br>~~a~~<br>~~a~~|VOL<br>~~a~~<br>~~a~~<br>~~ee~~|VDD = 1.95 V, VDDIO = 1.62 V,<br>IO= 500μA<br>~~a~~<br>~~a~~<br>~~ee~~|~~a~~<br>~~a~~<br>~~ee~~|~~a~~<br>~~a~~|0.1*VDDIO<br>~~a~~<br>~~a~~<br>~~ee~~|V<br>~~a~~<br>~~a~~<br>~~ee~~|
|Low-level output voltage<br>SDA<br>~~ee~~|VOLS<br>~~ee~~<br>~~ee~~<br>~~ee~~|IO= 3 mA<br>~~ee~~<br>~~ee~~<br>~~ee ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|0.4<br>~~ee~~<br>~~ee~~<br>~~ee~~|V<br>~~ee~~<br>~~ee~~|
|Output source current INT1, INT2<br>~~ee~~|Isource<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|Voltage high level<br>VOUT = 0.9 x VDDIO<br> ~~ee~~<br>~~ee~~<br>~~ee ee~~<br>~~es~~|~~ee~~<br>~~ee~~<br>~~ee~~<br>~~es~~|2<br>~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|mA<br>~~ee~~<br>~~ee~~|
|Output sink current INT1, INT2<br>~~ee~~<br>~~ee~~|Isink<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~el~~|Voltage high level<br>VOUT = 0.9 x VDDIO<br>~~ee~~<br>~~ee ee~~<br>~~ee~~<br>~~es~~|~~ee~~<br>~~ee ~~<br>~~ee~~<br>~~es~~|3<br>~~ee~~<br> ~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|mA<br>~~ee~~<br>~~ee~~|
|Power-on ramp time<br>~~es~~|Tpr<br>~~ee~~<br>~~es~~<br>~~el~~|~~es~~<br>~~es~~|0.001<br>~~es ~~<br>~~es~~|~~ee~~<br>~~es~~|1000<br>~~es~~|ms<br>~~es~~|
|Boot time<br>~~es~~|Tbt<br>~~es~~<br>~~el~~<br>~~ee~~|Time from VDDIO on and<br>VDD > VDD min until I2C is<br>ready for operation,<br>Cbyp = 100 nf<br>~~es~~<br>~~ee~~|~~es~~<br>~~ee~~|350<br>~~es~~|500<br>~~es~~<br>~~ee~~|µs<br>~~es~~<br>~~ee~~|
|Turn-on time<br>~~ee~~|Ton1<br>~~el~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|Time to obtain valid data from<br>Standby mode to Active mode<br>~~ee~~<br>~~ee~~<br>~~ee ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|2/ODR + 1 ms<br>~~ee~~<br>~~ee~~<br>~~ee~~|-<br>~~ee~~<br>~~ee~~|
|Turn-on time<br>~~ee~~|Ton2<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~nnnD I~~|Time to obtain valid data from<br>valid voltage applied<br> ~~ee~~<br>~~ee~~<br>~~ee ee~~<br>~~I~~|~~ee~~<br>~~ee~~<br>~~ee~~<br>~~IS~~|~~ee~~<br>~~ee~~<br>~~IS~~|2/ODR + 2 ms<br>~~ee~~<br>~~ee~~<br>~~ee~~|-<br>~~ee~~<br>~~ee~~|
|Operating temperature range<br>~~ee~~<br>~~ns~~|TAGOC<br>~~ee~~<br>~~ee~~<br>~~ns~~<br>~~nnnD I~~|~~ee~~<br>~~ee ee~~<br>~~ns~~<br>~~I~~|–40<br>~~ee~~<br>~~ee ~~<br>~~ns~~<br>~~IS~~|~~ee~~<br> ~~ee~~<br>~~ns~~<br>~~IS~~|85<br>~~ee~~<br>~~ee~~<br>~~ns~~|°C<br>~~ee~~<br>~~ns~~|



**MMA8652FC** 

Sensors Freescale Semiconductor, Inc. 

9 

**2.4 I[2] C interface characteristic** 

## **Table 6. I[2] C slave timing values[(1)]** 

|**Table 6. I[2]C slave timing values[(1)]**|||||
|---|---|---|---|---|
|**Parameter**|**Symbol**|**I2C Fast Mode**||**Unit**|
|||**Min**|**Max**||
|SCL clock frequency|fSCL|0|400|kHz|
|Bus-free time between STOP and START condition|tBUF|1.3||μs|
|(Repeated) START hold time|tHD;STA|0.6||μs|
|Repeated START setup time|tSU;STA|0.6||μs|
|STOP condition setup time|tSU;STO|0.6||μs|
|SDA data hold time|tHD;DAT|0.05|0.9(2)|μs|
|SDA setup time|tSU;DAT|100||ns|
|SCL clock low time|tLOW|1.3||μs|
|SCL clock high time|tHIGH|0.6||μs|
|SDA and SCL rise time|tr|20 + 0.1 Cb (3)|300|ns|
|SDA and SCL fall time|tf|20 + 0.1 Cb (3)|300|ns|
|SDA valid time(4)|tVD;DAT||0.9(2)|μs|
|SDA valid acknowledge time(5)|tVD;ACK||0.9(2)|μs|
|Pulse width of spikes on SDA and SCL that must be suppressed by<br>internal input filter|tSP|0|50|ns|
|Capacitive load for each bus line|Cb||400|pF|



1. All values referred to VIH(min) (0.3 VDD) and VIL(max) (0.7 VDD) levels. 

2. This device does not stretch the LOW period (tLOW) of the SCL signal. 

3. Cb = total capacitance of one bus line in pF. 

4. tVD;DAT = time for data signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse). 

5. tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse). 

**==> picture [50 x 20] intentionally omitted <==**

**----- Start of picture text -----**<br>
VIL = 0.3 VDD<br>VIH = 0.7 VDD<br>**----- End of picture text -----**<br>


**Figure 4. I[2] C slave timing diagram** 

**MMA8652FC** 

Sensors Freescale Semiconductor, Inc. 

10 

## **3 Terminology** 

## **3.1 Sensitivity** 

The sensitivity is represented in counts/g. 

- In ±2 g mode, sensitivity = 1024counts/g. 

- In ±4 g mode, sensitivity = 512counts/g. 

- In ±8 g mode, sensitivity = 256counts/g. 

## **3.2 Zero-g offset** 

Zero-g Offset (TyOff) describes the deviation of an actual output signal from the ideal output signal if the sensor is stationary. A sensor stationary on a horizontal surface will measure 0 g in X-axis and 0 g in Y-axis, whereas the Z-axis will measure 1 g. The output is ideally in the middle of the dynamic range of the sensor (content of OUT Registers 0x00, data expressed as a 2's complement number). A deviation from ideal value in this case is called Zero-g offset. 

Offset is to some extent a result of stress on the MEMS sensor, and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or after exposing it to extensive mechanical stress. 

## **3.3 Self-Test** 

Self-Test can be used to verify the transducer and signal chain functionality without the need to apply external mechanical stimulus. 

When Self-Test is activated: 

- An electrostatic actuation force is applied to the sensor, simulating a small acceleration. In this case, the sensor outputs will exhibit a change in their DC levels which, are related to the selected full scale through the device sensitivity. 

- The device output level is given by the algebraic sum of the signals produced by the acceleration acting on the sensor and by the electrostatic test-force. 

**MMA8652FC** 

Sensors Freescale Semiconductor, Inc. 

11 

**4 Modes of Operation** 

**==> picture [282 x 123] intentionally omitted <==**

**----- Start of picture text -----**<br>
ACTIVE<br>y, y eo TSN<br>/ SLEEP<br>OFF STANDBY -—- —§_f_ — > WAKE<br>\<br>Cc)<br>**----- End of picture text -----**<br>


**Figure 5. Operating modes for MMA8652FC** 

**Table 7. Operating modes** 

|**Mode**|**I2C Bus State**|**VDD**|**VDDIO**|**Description**|
|---|---|---|---|---|
|OFF|Powered down|<1.8 V|VDDIO can be > VDD|• The device is powered off.<br>• All analog and digital blocks are shutdown.<br>• I2C bus inhibited.|
|STANDBY|I2C communication with<br>MMA8652FC is possible|ON|VDDIO = High<br>VDD = High<br>ACTIVE bit is cleared|• Only digital blocks are enabled.<br>• Analog subsystem is disabled.<br>• Internal clocks disabled.|
|ACTIVE<br>(WAKE/SLEEP)|I2C communication with<br>MMA8652FC is possible|ON|VDDIO = High<br>VDD = High<br>ACTIVE bit is set|All blocks are enabled (digital, analog).|



Some registers are reset when transitioning from STANDBY to ACTIVE. These registers are all noted in the device memory map register table. 

The SLEEP and WAKE modes are ACTIVE modes. For more information about how to use the SLEEP and WAKE modes and how to transition between these modes, see Section 5. 

**MMA8652FC** 

Sensors Freescale Semiconductor, Inc. 

12 

## **5 Functionality** 

The MMA8652FC is a low-power, digital output 3-axis linear accelerometer with a I[2] C interface with embedded logic used to detect events and notify an external microprocessor over interrupt lines. 

- 8-bit or 12-bit data, high-pass filtered data, 8-bit or 12-bit configurable 32-sample FIFO 

- Four different oversampling options that allow for the optimum resolution vs. current consumption trade-off to be made for a given application 

- Low-power and auto-WAKE/SLEEP modes for reducing current consumption 

- Single/double tap with directional information (one channel) 

- Motion detection with directional information or Freefall (one channel) 

- Transient/jolt detection based on a high-pass filter, with a settable threshold for detecting the change in acceleration above a threshold with directional information (one channel) 

- Flexible user-configurable portrait landscape detection algorithm, for addressing screen orientation 

- Two independent interrupt output pins that are programmable among seven interrupt sources (Data Ready, Motion/Freefall, Tap, Orientation, Transient, FIFO, Auto-WAKE) 

All functionality is available in ±2 g, ±4 g or ±8 g dynamic measurement ranges. There are many configuration settings for enabling all of the different functions. Separate application notes are available to help configure the device for each embedded functionality. 

## **5.1 Device calibration** 

The device is factory calibrated for sensitivity and Zero-g offset for each axis. The trim values are stored in Non-Volatile Memory (NVM). On power-up, the trim parameters are read from NVM and applied to the circuitry. In normal use, further calibration in the end application is not necessary. However, the MMA8652FC allows you to adjust the offset for each axis after power-up, by changing the default offset values. The user offset adjustments are stored in three volatile 8-bit registers (OFF_X, OFF_Y, OFF_Z). 

## **5.2 8-bit or 12-bit** 

The measured acceleration data is stored in the following registers as 2’s complement 12-bit: 

- OUT_X_MSB, OUT_X_LSB 

- OUT_Y_MSB, OUT_Y_LSB 

- OUT_Z_MSB, OUT_Z_LSB 

The most significant eight bits of each axis are stored in OUT_X (Y, Z)_MSB, so applications needing only 8-bit results can use these three registers (and ignore the OUT_X/Y/Z_LSB registers). To use only 8-bit results, the F_READ bit in CTRL_REG1 must be set. When the F_READ bit is cleared, the fast read mode is disabled. 

- **When the full-scale is set to ±2 g** , the measurement range is –2 g to +1.999 g, and each count corresponds to (1/1024) g (0.98 mg) at 12-bit resolution. 

- **When the full-scale is set to ±4 g** , the measurement range is –4 g to +3.998 g, and each count corresponds to (1/512) g 

- • (1.96 mg) at 12-bit resolution. 

- **When the full-scale is set to ±8 g** , the measurement range is –8 g to +7.996 g, and each count corresponds to (1/256) g (3.9 mg) at 12-bit resolution. 

- **If only the 8-bit results are used** , then the resolution is reduced by a factor of 16. 

For more information about the data manipulation between data formats and modes, see application note AN4083, _Data Manipulation and Basic Settings for Xtrinsic MMA865xFC Accelerometers_ . There is a device driver available that can be used with the Sensor Toolbox demo board (LFSTBEB865xFC) with this application note. 

**Table 8. Accelerometer 12-bit output data** 

|**12-bit data**<br>~~ooo~~|**Range ±2 g (1 mg/LSB)**<br>~~ooo~~|**Range ±4 g (2 mg/LSB)**<br>~~ooo~~|**Range ±8 g (4 mg/LSB)**<br>~~ooo~~|
|---|---|---|---|
|0111 1111 1111<br>~~ooo~~|1.999 g<br>~~ooo~~|+3.998 g<br>~~ooo~~|+7.996 g<br>~~ooo~~|
|0111 1111 1110<br>~~ooo~~|1.998 g<br>~~ooo~~|+3.996 g<br>~~ooo~~|+7.992 g<br>~~ooo~~|
|…<br>~~ooo~~|…<br>~~ooo~~|…<br>~~ooo~~|…<br>~~ooo~~|
|0000 0000 0001<br>~~ooo~~|0.001 g<br>~~ooo~~|+0.002 g<br>~~ooo~~|+0.004 g<br>~~ooo~~|
|0000 0000 0000<br>~~ooo~~|0.0000 g<br>~~ooo~~|0.0000 g<br>~~ooo~~|0.0000 g<br>~~ooo~~|
|1111 1111 1111<br>~~ooo~~|–0.001 g<br>~~ooo~~|–0.002 g<br>~~ooo~~|–0.004 g<br>~~ooo~~|



Sensors Freescale Semiconductor, Inc. 

13 

**Table 8. Accelerometer 12-bit output data (Continued)** 

|**12-bit data**|**Range ±2 g (1 mg/LSB)**|**Range ±4 g (2 mg/LSB)**|**Range ±8 g (4 mg/LSB)**|
|---|---|---|---|
|…|…|…|…|
|1000 0000 0001|–1.999 g|–3.998 g|–7.996 g|
|1000 0000 0000|–2.0000 g|–4.0000 g|–8.0000 g|



**Table 9. Accelerometer 8-bit output data** 

|**8-bit Data**|**Range ±2 g**<br>**(15.6 mg/LSB)**|**Range ±4 g**<br>**(31.25 mg/LSB)**|**Range ±8 g**<br>**(62.5 mg/LSB)**|
|---|---|---|---|
|0111 1111|1.9844 g|+3.9688 g|+7.9375 g|
|0111 1110|1.9688 g|+3.9375 g|+7.8750 g|
|…|…|…|…|
|0000 0001|+0.0156 g|+0.0313 g|+0.0625 g|
|0000 0000|0.000 g|0.0000 g|0.0000 g|
|1111 1111|–0.0156 g|–0.0313 g|–0.0625 g|
|…|…|…|…|
|1000 0001|–1.9844 g|–3.9688 g|–7.9375 g|
|1000 0000|–2.0000 g|–4.0000 g|–8.0000 g|



## **5.3 Internal FIFO data buffer** 

MMA8652FC contains a 32-sample internal FIFO data buffer, which helps minimize traffic across the I[2] C bus. The FIFO can also save system power, by allowing the host processor/MCU to go into a SLEEP mode while the accelerometer independently stores the data (up to 32 samples per axis). 

The FIFO can run at all output data rates. There are options for accessing the full 12-bit data or for accessing only the 8-bit data. When access speed is more important than high resolution, the 8-bit data read is a better option. 

The FIFO contains four modes (Fill Buffer mode, Circular Buffer mode, Trigger mode, and Disabled mode), which are described in F_SETUP Register 0x09. 

- **Fill Buffer mode** collects the first 32 samples and asserts the overflow flag when the buffer is full and another sample arrives. It does not collect any more data until the buffer is read. This benefits data logging applications where all samples must be collected. 

- **Circular Buffer mode** allows the buffer to be filled and then new data replaces the oldest sample in the buffer. The most recent 32 samples will be stored in the buffer. This benefits situations where the processor is waiting for an specific interrupt to signal that the data must be flushed to analyze the event. 

- **Trigger mode** will hold the last data up to the point when the trigger occurs, and can be set to keep a selectable number of samples after the event occurs. 

The MMA8652FC FIFO Buffer has a configurable watermark, allowing the processor to be triggered after a configurable number of samples has filled in the buffer (1 to 32). 

## **5.4 Low power modes vs. high resolution modes** 

The MMA8652FC can be optimized for lower power modes or for higher resolution of the output data. One of the oversampling schemes of the data can be activated when MODS = 10 in Register 0x2B, which will improve the resolution of the output data only. The highest resolution is achieved at 1.56 Hz. 

**There is a trade-off between low power and high resolution.** Low power can be achieved when the oversampling rate is reduced. When MODS = 11, the lowest power is achieved. The lowest power is achieved when the sample rate is set to 1.56 Hz. 

**MMA8652FC** 

Sensors Freescale Semiconductor, Inc. 

14 

## **5.5 Auto-WAKE/SLEEP mode** 

The MMA8652FC can be configured to transition between sample rates (with their respective current consumption) based on four of the interrupt functions of the device. The advantage of using the Auto-WAKE/SLEEP is that the system can automatically transition to a higher sample rate (higher current consumption) when needed, but spends the majority of the time in the SLEEP mode (lower current) when the device does not require higher sampling rates. 

- **Auto-WAKE** refers to the device being triggered by one of the interrupt functions to transition to a higher sample rate. This may also interrupt the processor to transition from a SLEEP mode to a higher power mode. 

- **SLEEP mode** occurs after the accelerometer has not detected an interrupt for longer than the user-definable timeout period. The device will transition to the specified lower sample rate. It may also alert the processor to go into a lower power mode, to save on current during this period of inactivity. 

The Interrupts that can WAKE the device from SLEEP are the following: Tap Detection, Orientation Detection, Motion/Freefall, and Transient Detection. The FIFO can be configured to hold the data in the buffer until it is flushed, if the FIFO Gate bit is set (in Register 0x2C) and if the FIFO cannot WAKE the device from SLEEP. 

The interrupts that can keep the device from falling asleep are the same interrupts that can wake the device—with the addition of the FIFO. If the FIFO interrupt is enabled and data is being accessed continually servicing the interrupt, then the device will remain in WAKE mode. 

## **5.6 Freefall and motion detection** 

MMA8652FC has a flexible interrupt architecture for detecting either a Freefall or a Motion. 

- Freefall can be enabled where the set threshold _must be less than_ the configured threshold. 

- Motion can be enabled where the set threshold _must be greater than_ the configured threshold. 

The motion configuration has the option of enabling or disabling a high-pass filter to eliminate tilt data (static offset); the freefall configuration does not use the high-pass filter. 

## **5.6.1 Freefall detection** 

The detection of “Freefall” involves the monitoring of the X, Y, and Z axes for the condition where the acceleration magnitude is _below a user-specified threshold for a user-definable amount of time_ . Usable threshold levels are typically between ±100 mg and ±500 mg. 

## **5.6.2 Motion detection** 

Motion is often used to simply alert the main processor that the device is currently in use. When the acceleration exceeds a set threshold, the motion interrupt is asserted. A motion can be a fast moving shake or a slow moving tilt. This will depend on the threshold and timing values configured for the event. 

- The motion detection function can analyze static acceleration changes or faster jolts. For example, to detect that an object is spinning, all three axes would be enabled with a threshold detection of > 2 g. This condition would need to occur for a minimum of 100 ms to ensure that the event was not just noise. The timing value is set by a configurable debounce counter. The debounce counter acts like a filter to determine whether the condition exists for configurable set of time (like 100 ms or longer). 

- To detect the direction of the motion, there is also directional data available in the source register. This is useful for applications such as directional shake or flick, which assists with the algorithm for various gesture detections. 

## **5.7 Transient detection** 

The MMA8652FC has a built-in, high-pass filter. Acceleration data goes through the high pass filter, eliminating the offset (DC) and low frequencies. The high-pass filter cutoff frequency can be set to four different frequencies, which depends on the Output Data Rate (ODR). A higher cutoff frequency ensures that the DC data (or slower moving data) will be filtered out, allowing only the higher frequencies to pass. The embedded transient detection function uses the high-pass filtered data, allowing you to set the threshold and debounce counter. The transient detection feature can be used in the same manner as the motion detection feature, by bypassing the high-pass filter. There is an option in the configuration register to do this, which adds more flexibility to accommodate various use cases. 

Many applications use the accelerometer’s **static acceleration readings** (like tilt), which measure the change in acceleration due to gravity only. These functions benefit from acceleration data being filtered with a low-pass filter where high frequency data is considered noise. However, there are many functions where the accelerometer must analyze **dynamic acceleration** . Functions such as tap, flick, shake and step counting are based on the analysis of the change in the acceleration. It is simpler to interpret these functions (which are dependent on dynamic acceleration data) when the static component has been removed. 

**MMA8652FC** 

Sensors Freescale Semiconductor, Inc. 

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The Transient Detection function can be routed to either interrupt pin through bit 5 in CTRL_REG5 register (0x2E). Registers 0x1D – 0x20 are the dedicated Transient Detection configuration registers. The source register contains directional data to determine the direction of the acceleration (either positive or negative). 

## **5.8** 

## **Tap detection** 

The MMA8652FC has embedded single/double and directional tap detection. 

- The tap detection function has various customizing timers, for setting the pulse time width and the latency time between pulses. There are programmable thresholds for all three axes. 

- The tap detection can be configured to run through the high-pass filter and also through a low-pass filter, which provides more customizing and tunable tap detection schemes. 

- The status register provides updates on the axes where the event was detected and the direction of the tap. 

## **5.9 Orientation detection** 

The MMA8652FC incorporates an advanced orientation detection algorithm with the ability to detect all six orientations shown in Figure 6. The embedded algorithm uses configurable trip points, allowing the selection of the desired midpoint and hysteresis value (see Figure 7). 

**==> picture [431 x 307] intentionally omitted <==**

**----- Start of picture text -----**<br>
Top View Side View<br>PORTRAIT UP BACK<br>Pin 1<br>Earth Gravity Xout @ 0 g<br>Yout @ 0 g<br>Zout @ –1 g<br>LANDSCAPE LEFT Xout @ 0 g LANDSCAPE RIGHT FRONT<br>Yout @ –1 g<br>Zout @ 0 g<br>Xout @ 0 g<br>Yout @ 0 g<br>Zout @ 1 g<br>ae<br>Xout @ –1 g PORTRAIT DOWN Xout @ 1 g<br>Z<br>Yout @ 0 g Yout @ 0 g<br>Zout @ 0 g Zout @ 0 g<br>Pin 1<br>X<br>Xout @ 0 g<br>Yout @ 1 g<br>Zout @ 0 g<br>Y<br>- 2><br>(Top View)<br>Direction of the<br>Detectable Accelerations<br>**----- End of picture text -----**<br>


**==> picture [152 x 10] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 6. Sensitive axes orientation<br>**----- End of picture text -----**<br>


**MMA8652FC** 

Sensors Freescale Semiconductor, Inc. 

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**==> picture [552 x 293] intentionally omitted <==**

**----- Start of picture text -----**<br>
PORTRAIT PORTRAIT<br>90 ° 90 °<br>Landscape-to-Portrait<br>Trip Angle = Midpoint + hysterisis value<br>Portrait-to-Landscape<br>Trip Angle = midpoint - hysteresis value<br>0° Landscape 0° Landscape<br>ie Ly<br>Figure 7. Landscape-to-Portrait transition trip angles<br>The MMA8652FC orientation detection algorithm confirms the reliability of the function with a configurable Z-lockout angle.<br>Based on the known functionality of linear accelerometers, it is not possible to rotate the device about the Z-axis, to detect change<br>in acceleration at slow angular speeds. The angle at which the device no longer detects the orientation change is referred to as<br>the “Z-lockout angle” (see Figure 8). The device operates down to 14° from the flat position.<br>.<br>UPRIGHT<br>When lifting the device upright from the  90 °<br>**----- End of picture text -----**<br>


When lifting the device upright from the flat position, orientation detection will be active for orientation angles greater than a user-configurable value. 

**==> picture [328 x 118] intentionally omitted <==**

**----- Start of picture text -----**<br>
active for orientation angles greater than<br>a user-configurable value.  NORMAL<br>DETECTION<br>The default angle is 29° from flat, but the  REGION<br>angle can be set as low as 14°. Z-LOCK<br>LOCKOUT<br>REGION<br>0° FLAT<br>S<br>**----- End of picture text -----**<br>


**Figure 8. Z-Tilt angle lockout transition** 

**MMA8652FC** 

Sensors Freescale Semiconductor, Inc. 

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## **5.10 Interrupt register configurations** 

There are seven configurable interrupts in the MMA8652FC: Data Ready, Motion/Freefall, Tap (Pulse), Orientation, Transient, FIFO events, and Auto-SLEEP events. 

These seven interrupt sources can be routed to one of two interrupt pins. 

The interrupt source must be enabled and configured. 

If the event flag is asserted because the event condition is detected, then the corresponding interrupt pin (INT1 or INT2) will assert. 

**==> picture [331 x 219] intentionally omitted <==**

**----- Start of picture text -----**<br>
Configurable interrupts<br>Data Ready<br>Motion/Freefall<br>INT1<br>Tap (Pulse)<br>Interrupt<br>Controller<br>Orientation<br>Transient<br>INT2<br>FIFO<br>Auto-SLEEP<br>7 7<br>INT ENABLE INT CFG<br>EE<br>**----- End of picture text -----**<br>


## **Figure 9. System interrupt generation** 

- The MMA8652FC features an interrupt signal that indicates when a new set of measured acceleration data is available, thus simplifying data synchronization in the digital system that uses the device. 

- The MMA8652FC may also be configured to generate _other interrupt signals_ accordingly, to the programmable embedded functions of the device for Motion, Freefall, Transient, Orientation, and Tap. 

## **5.11 Serial I[2] C interface** 

Acceleration data may be accessed through an I[2] C interface, thus making the device particularly suitable for direct interfacing to a microcontroller. The acceleration data and configuration registers embedded inside the MMA8652FC are accessed through the I[2] C serial interface (Table 10). 

- To enable the I[2] C interface, VDDIO line must be tied high (to the interface supply voltage). If VDD is not present and VDDIO is present, then the MMA8652FC is in OFF mode—and communications on the I[2] C interface are ignored. 

- The I[2] C interface may be used for communications between other I[2] C devices; the MMA8652FC does not affect the I[2] C bus. 

## **Table 10. Serial Interface pins** 

|**Pin Name**|**Pin Description**|**Notes**|
|---|---|---|
|SCL|I2C Serial Clock|**There are two signals associated with the I2C bus; the Serial Clock Line (SCL) and the**<br>**Serial Data line (SDA).**<br>• SDA is a bidirectional line used for sending and receiving the data to/from the interface.<br>• External pullup resistors connected to VDDIO are expected for SDA and SCL. When the bus<br>is free, both SCL and SDA lines are high.|
|SDA|I2C Serial Data||



The I[2] C interface is compliant with Fast mode (400 kHz), and Normal mode (100 kHz) I[2] C standards (Table 11). 

## **I[2] C operation:** 

1. The transaction on the bus is started through a start condition (START) signal. A START condition is defined as a high-tolow transition on the data line while the SCL line is held high. After START has been transmitted by the Master, the bus is considered busy. 

2. The next byte of data transmitted after START contains the slave address in the first seven bits. The eighth bit tells whether the Master is _receiving data from the slave_ or is _transmitting data to the slave_ . 

3. After a start condition and when an address is sent, each device in the system compares the first seven bits with its address. If the device’s address matches the sent address, then the device considers itself addressed by the Master. 

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Sensors Freescale Semiconductor, Inc. 

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4. The 9th clock pulse following the slave address byte (and each subsequent byte) is the acknowledge (ACK). The transmitter must release the SDA line during the ACK period. The receiver must then pull the data line low, so that it remains stable low during the high period of the acknowledge clock period. 

5. A Master may also issue a repeated START during a data transfer. The MMA8652FC expects repeated STARTs to be used to randomly read from specific registers. 

6. A low-to-high transition on the SDA line _while the SCL line is high_ is defined as a stop condition (STOP). A data transfer is always terminated by a STOP. 

The MMA8652FC's standard slave address is 0011101 or 0x01D. 

**Table 11. I[2] C Device address sequence** 

|**Command**|**[6:0]**<br>**Device address**|**[6:0]**<br>**Device address**|**R/W**|**8-bit final**<br>**value**|
|---|---|---|---|---|
|Read|0011101|0x1D|1|0x3B|
|Write|0011101|0x1D|0|0x3A|



## **5.11.1 Single-byte read** 

1. The transmission of an 8-bit command begins on the falling edge of SCL. After the eight clock cycles are used to send the command, note that _the data returned_ is sent with the MSB first after the data is received. Figure 10 shows the timing diagram for the accelerometer 8-bit I[2] C read operation. 

2. The Master (or MCU) transmits a start condition (ST) to the MMA8652FC [slave address (0x1D), with the R/W bit set to “0” for a write], and the MMA8652FC sends an acknowledgement. 

3. Next the Master (or MCU) transmits the address of the register to read, and the MMA8652FC sends an acknowledgement. 

4. The Master (or MCU) transmits a repeated start condition (SR) and then addresses the MMA8652FC (0x1D), with the R/W bit set to “1” for a read from the previously selected register. 

5. The Slave then acknowledges and transmits the data from the requested register. The Master does not acknowledge (NAK) the transmitted data, but transmits a stop condition to end the data transfer. 

**==> picture [495 x 45] intentionally omitted <==**

**----- Start of picture text -----**<br>
Register<br>Master ST Device Address[7:1] W SR Device Address[7:1] R NAK SP<br>Address[7:0]<br>Slave AK AK AK Data[7:0]<br>**----- End of picture text -----**<br>


**Figure 10. Single-Byte Read timing (I[2] C)** 

## **NOTE** 

For the following subsections, use the following legend. 

## **Legend** 

ST: Start Condition SP: Stop Condition NAK: No Acknowledge W: Write = 0 SR: Repeated Start Condition AK: Acknowledge R: Read = 1 

## **5.11.2 Multiple byte read** 

(See Table 11 for next auto-increment address.) 

1. When performing a multi-byte read or “burst read”, the MMA8652FC automatically increments the received register address commands after a read command is received. 

2. After following the steps of a single byte read, multiple bytes of data can be read from sequential registers after each MMA8652FC acknowledgment (AK) is received, 

3. Until a no acknowledge (NAK) occurs from the Master, 

4. Followed by a stop condition (SP), which signals the end of transmission. 

**MMA8652FC** 

Sensors Freescale Semiconductor, Inc. 

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**==> picture [483 x 126] intentionally omitted <==**

**----- Start of picture text -----**<br>
Master ST Device Address[7:1] W Register Address[7:0] SR Device Address[7:1] R AK<br>f|.DULULULUCUCUC CL LLCtC“‘iéiR“ LULULULULULUCUULUE<br>Slave AK AK AK Data[7:0]<br>eee eee eee CUD<br>Master AK AK NAK SP<br>—hE_ Th |<br>Slave Data[7:0] Data[7:0] Data[7:0]<br>[|COCO=slioC C/T]<br>Figure 11. Multiple Byte Read timing (I [2] C)<br>**----- End of picture text -----**<br>


## **5.11.3 Single byte write** 

1. To start a write command, the Master transmits a start condition (ST) to the MMA8652FC, slave address ($1D) with the R/W bit set to “0” for a write, 

2. The MMA8652FC sends an acknowledgement. 

3. Next the Master (MCU) transmits the address of the register to write to, and the MMA8652FC sends an acknowledgement. 

4. Then the Master (or MCU) transmits the 8-bit data to write to the designated register, and the MMA8652FC sends an acknowledgement that it has received the data. Because this transmission is complete, the Master transmits a stop condition (SP) to the data transfer. The data sent to the MMA8652FC is now stored in the appropriate register. 

**Master** ST Device Address[7:1] W Register Address[7:0] Data[7:0] SP ~~2 2D~~ **Slave** AK AK AK ~~eeEE eee~~ **Figure 12. Single Byte Write timing (I[2] C)** 

## **5.11.4 Multiple byte write** 

(See Table 11 for next auto-increment address.) 

1. After a write command is received, the MMA8652FC _automatically increments_ the received register address commands. 

2. Therefore, after following the steps of a single byte write, multiple bytes of data can be written to sequential registers after each MMA8652FC acknowledgment (ACK) is received. 

**Master** ST Device Address[7:1] W Register Address[7:0] Data[7:0] Data[7:0] SP ~~22 2~~ **Slave** AK AK AK AK ~~eeeoe eee eee~~ **Figure 13. Multiple Byte Write timing (I[2] C)** 

**MMA8652FC** 

Sensors Freescale Semiconductor, Inc. 

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**6 Register Descriptions** 

## **6.1 Register address map** 

**Table 12. MMA8652FC register address map** 

|**Name**<br>~~a~~<br>~~a~~|**Type **<br>~~ee~~<br>|**Register**<br>**Address**<br>~~ee~~<br>|**Auto-Increment Address**<br>~~Pe~~<br>~~ee~~<br>|**Auto-Increment Address**<br>~~Pe~~<br>~~ee~~<br>|**Auto-Increment Address**<br>~~Pe~~<br>~~ee~~<br>|**Auto-Increment Address**<br>~~Pe~~<br>~~ee~~<br>|**Default**<br>~~ee~~<br>|**Hex**<br>**Value**<br>~~ee~~<br>|**Comment**<br>~~ee~~<br>~~ee~~<br>|**Comment**<br>~~ee~~<br>~~ee~~<br>|
|---|---|---|---|---|---|---|---|---|---|---|
||||**FMODE = 0**<br>**F_READ = 0**<br>~~Pe~~<br>~~ee~~<br>|**FMODE > 0**<br>**F_READ = 0**<br>~~Pe~~<br>~~ee~~<br>|**FMODE = 0**<br>**F_READ = 1**<br>~~Pe~~<br>~~ee~~<br>|**FMODE > 0**<br>**F_READ = 1**<br>~~Pe~~<br>~~ee~~<br>|||||
|STATUS/<br>F_STATUS(1)(2)<br>~~a~~<br>~~a~~|R<br>~~ee~~<br>~~eee~~|0x00<br>~~ee~~<br>~~eee~~|0x01<br>~~Pe~~<br>~~ee~~<br>~~eee~~||||00000000<br>~~ee~~<br>~~eee~~|0x00<br>~~ee~~<br>~~eee~~|FMODE = 0, real time status<br>FMODE > 0, FIFO status<br>~~ee~~<br>~~ee~~<br>~~eee~~||
|OUT_X_MSB(1)(2)<br>~~eee~~|R<br>~~eee~~|0x01<br>~~eee~~|0x02<br>~~eee~~|0x01<br>~~eee~~|**0x03**<br>~~eee~~|**0x01**<br>~~eee~~<br>~~e~~|Output<br>~~eee~~|—<br>~~eee~~|[7:0] are 8 MSBs<br>of 12-bit sample.<br>~~eee~~<br>~~ee~~|Root pointer to<br>XYZ FIFO data.<br>~~eee~~<br>~~ee~~|
|OUT_X_LSB(1)(2)<br>~~e~~<br>~~ee~~|R<br>~~e~~<br>~~ee~~|0x02<br>~~e~~|0x03<br>~~e~~||**0x00**<br>~~e~~~~**e**~~<br>~~e~~<br>~~ee~~||Output<br>~~**e**~~|—<br>~~**e**~~|[7:4] are 4 LSBs of 12-bit real-time<br>sample<br>~~**e**~~<br>~~ee~~<br>~~eee~~||
|OUT_Y_MSB(1)(2)<br>~~e~~<br>~~ee~~<br>~~ee~~|R<br>~~e~~<br>~~ee~~<br>~~ee~~|0x03<br>~~e~~<br>~~ee~~|0x04<br>~~e~~<br>~~ee~~||**0x05**<br>~~e~~~~**e**~~<br>~~ee~~<br>~~ee~~|**0x00**<br>~~**e**~~<br>~~e~~<br>~~ee~~<br>~~ee~~|Output<br>~~**e**~~<br>~~ee~~|—<br>~~**e**~~<br>~~ee~~|[7:0] are 8 MSBs of 12-bit real-time<br>sample<br>~~**e**~~<br>~~ee~~<br>~~ee~~<br>~~eee~~||
|OUT_Y_LSB(1)(2)<br>~~ee~~|R<br>~~ee~~|0x04|0x05||**0x00**<br>~~ee~~<br>~~e~~||Output|—<br>~~eee~~|[7:4] are 4 LSBs of 12-bit real-time<br>sample<br>~~eee~~<br>~~eee~~||
|OUT_Z_MSB(1)(2)<br>~~e~~<br>~~PF~~|R<br>~~e~~|0x05<br>~~e~~|0x06<br>~~e~~||**0x00**<br>~~e~~~~**e**~~<br>~~e~~||Output<br>~~**e**~~|—<br>~~**e**~~<br>~~eee~~|[7:0] are 8 MSBs of 12-bit real-time<br>sample<br>~~**e**~~<br>~~eee~~<br>~~ee~~||
|OUT_Z_LSB(1)(2)<br>~~e~~<br>~~ee~~<br>~~PF~~<br>~~UE~~|R<br>~~e~~<br>~~ee~~<br>~~UETE~~|0x06<br>~~e~~<br>~~ee~~<br>~~TEEE~~|**0x00**<br>~~e~~~~**e**~~<br>~~e~~<br>~~ee~~<br>~~EE~~||||Output<br>~~**e**~~<br>~~ee~~|—<br>~~**e**~~<br>~~eee~~<br>~~ee~~|[7:4] are 4 LSBs of 12-bit real-time<br>sample<br>~~**e**~~<br>~~eee~~<br>~~ee~~<br>~~ee~~||
|Reserved<br>~~PF~~<br>~~UE~~<br>~~es~~|R<br>~~UETE~~<br>~~ee~~|0x07<br>0x08<br>~~TEEE~~<br>~~es en~~|—<br>~~EE~~<br>~~en~~|—<br>~~EE~~<br>~~en~~|—<br>~~en~~|—|—<br>~~ts~~|—<br>~~ns~~|Reserved. Read return 0x00.<br>~~ee~~||
|F_SETUP(1)(3)<br>~~PF~~<br>~~UE~~<br>~~es~~<br>~~a~~|R/W<br>~~UE TE~~<br>~~ee~~<br>~~es~~|0x09<br>~~TE EE~~<br>~~es en~~<br>~~ee~~|0x0A<br>~~EE~~<br>~~en~~<br>~~ns~~||||00000000<br>~~ts~~<br>~~ns~~|0x00<br>~~ns~~<br>~~ns~~|FIFO setup<br>~~ee~~<br>~~ns~~||
|TRIG_CFG(1)(4)<br>~~es ~~<br>~~a~~<br>~~ee~~<br>~~es~~|R/W<br> ~~ee~~<br>~~es~~<br>~~es~~<br>|0x0A<br>~~es en~~<br>~~ee~~<br>~~es~~<br>|0x0B<br>~~en~~<br>~~ns~~<br>~~rey~~<br>||||00000000<br>~~ts ~~<br>~~ns~~<br>~~rey~~<br>~~tI~~|0x00<br> ~~ns~~<br>~~ns~~<br>~~rey~~<br>~~ts~~|Map of FIFO data capture events<br>~~ns~~<br>~~rey~~||
|SYSMOD(1)(2)<br>~~a~~<br>~~ee~~<br>~~es~~<br>~~a~~|R<br>~~es ~~<br>~~es~~<br>~~ee~~|0x0B<br> ~~ee~~<br>~~es~~<br>~~es ee~~|0x0C<br>~~ns~~<br>~~rey~~<br>~~ee~~||||00000000<br>~~ns~~<br>~~rey~~<br>~~tI~~<br>~~ts~~|0x00<br>~~ns~~<br>~~rey~~<br>~~ts~~<br>~~ns~~|Current System mode<br>~~ns~~<br>~~rey~~||
|INT_SOURCE(1)(2)<br>~~ee ~~<br>~~es~~<br>~~a~~<br>~~ee~~|R<br> ~~es~~<br>~~ee~~<br>~~es~~<br>|0x0C<br>~~es~~<br>~~es ee~~<br>~~e~~~~**e**~~|0x0D<br>~~rey~~<br>~~ee~~<br>~~ns~~||||00000000<br>~~rey~~<br>~~tI~~<br>~~ts~~<br>~~ns~~|0x00<br>~~rey~~<br>~~ts~~<br>~~ns~~<br>~~ns~~|Interrupt status<br>~~rey~~<br>~~ns~~||
|WHO_AM_I(1)<br>~~es ~~<br>~~a~~<br>~~ee~~|R<br> ~~ee~~<br>~~es~~<br>~~es~~|0x0D<br>~~es ee~~<br>~~e~~~~**e**~~<br>~~s~~|0x0E<br>~~ee~~<br>~~ns~~<br>~~rey~~||||01001010<br>~~tI ~~<br>~~ts~~<br>~~ns~~<br>~~rey~~<br>~~tI~~|0x4A<br> ~~ts~~<br>~~ns~~<br>~~ns~~<br>~~rey~~<br>~~ts~~|Device ID (0x4A)<br>~~ns~~<br>~~rey~~||
|XYZ_DATA_CFG(1)(4)<br> <br>~~a~~<br>~~ee~~|R/W<br> ~~ee ~~<br>~~es~~<br>~~es~~|0x0E<br> ~~es ee~~<br>~~e~~~~**e**~~<br>~~s~~|0x0F<br>~~ee~~<br>~~ns~~<br>~~rey~~<br>~~ee~~||||00000000<br>~~ts ~~<br>~~ns~~<br>~~rey~~<br>~~tI~~<br>~~ee~~|0x00<br> ~~ns~~<br>~~ns~~<br>~~rey~~<br>~~ts~~|Dynamic Range Settings<br>~~ns~~<br>~~rey~~<br>~~ee~~||
|HP_FILTER_CUTOFF(1<br>)(4)<br>~~ee ~~<br>~~a~~|R/W<br>~~es ~~<br> ~~es~~<br>~~a~~|0x0F<br> ~~e~~~~**e**~~<br>~~s~~<br>~~a~~|0x10<br>~~ns~~<br>~~rey~~<br>~~a~~<br>~~ee~~||||00000000<br>~~ns~~<br>~~rey~~<br>~~tI ~~<br>~~a~~<br>~~ee~~|0x00<br>~~ns~~<br>~~rey~~<br> ~~ts~~<br>~~a~~|High-Pass Filter Selection<br>~~ns~~<br>~~rey~~<br>~~a~~<br>~~ee~~||
|PL_STATUS(1)(2)<br>~~ee~~<br>~~es~~|R<br>~~ee~~<br>~~ed~~|0x10<br>~~ee~~<br>~~ee~~|0x11<br>~~ee~~<br>~~ee~~<br>~~er~~||||00000000<br>~~ee~~<br>~~ee~~<br>~~tI~~|0x00<br>~~ee~~<br>~~tts~~|Landscape/Portrait orientation<br>status<br>~~ee~~<br>~~ee~~||
|PL_CFG(1)(4)<br>~~es~~|R/W<br>~~ed~~|0x11<br>~~ee~~|0x12<br>~~er~~||||10000000<br>~~tI~~|0x80<br>~~tts~~|Landscape/Portrait configuration.||
|PL_COUNT(1)(3)<br>~~es ~~<br>~~ee~~<br>~~es~~|R/W<br> ~~ed ~~<br>~~ee~~<br>~~es~~|0x12<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|0x13<br> ~~er~~<br>~~ee~~<br>~~errr~~||||00000000<br>~~tI~~<br>~~ee~~<br>~~errr~~<br>~~ts~~|0x00<br>~~tts~~<br>~~ee~~<br>~~errr~~<br>~~ts~~|Landscape/Portrait debounce<br>counter<br>~~ee~~<br>~~errr~~||
|PL_BF_ZCOMP(1)(4)<br>~~es~~|R/W<br>~~es~~|0x13<br>~~ee~~|0x14<br>~~errr~~||||01000100<br>~~errr~~<br>~~ts~~|0x44<br>~~errr~~<br>~~ts~~|Back/Front, Z-Lock Trip threshold<br>~~errr~~||
|P_L_THS_REG(1)(4)<br>~~es ~~<br>~~ee~~|R/W<br> ~~es ~~<br>~~ee~~|0x14<br> ~~ee~~<br>~~ee~~|0x15<br>~~errr~~<br>~~ee~~||||10000100<br>~~errr~~<br>~~ts ~~<br>~~ee~~<br>~~ee~~|0x84<br>~~errr~~<br> ~~ts~~<br>~~ee~~<br>~~ee~~|Portrait/Landscape Threshold and<br>Hysteresis<br>~~errr~~<br>~~ee~~<br>~~eee~~||
|FF_MT_CFG(1)(4)<br>~~a~~<br>~~es~~|R/W<br>~~ee~~|0x15<br>~~ee~~|0x16<br>~~ee~~<br>~~ee~~||||00000000<br>~~ee~~<br>~~ee~~<br>~~ee~~|0x00<br>~~ee~~<br>~~ee~~<br>~~ee~~|Freefall/Motion functional block<br>configuration<br>~~ee~~<br>~~eee~~||
|FF_MT_SRC(1)(2)<br>~~ee~~<br>~~es~~<br>~~-~~|R<br>~~ee~~<br>~~ee~~<br>|0x16<br>~~ee~~<br>~~es~~<br>|0x17<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>||||00000000<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ts~~<br>|0x00<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ns~~<br>|Freefall/Motion event source<br>register<br>~~eee~~<br>~~ee~~<br>||
|FF_MT_THS(1)(3)<br>~~es~~<br>~~-~~|R/W<br>~~ee~~<br>|0x17<br>~~es~~<br>|0x18<br>~~ee~~<br>~~ee~~<br>||||00000000<br>~~ee~~<br>~~ts~~<br>|0x00<br>~~ee~~<br>~~ns~~<br>|Freefall/Motion threshold register<br>||
|FF_MT_COUNT(1)(3)<br>~~es~~<br>~~-IfflTiTitiil.~~|R/W<br>~~ee~~<br>~~IfflTiTitiil.~~|0x18<br>~~es~~<br>~~IfflTiTitiil.~~|0x19<br>~~ee ~~<br>~~ee~~<br>~~IfflTiTitiil.~~||||00000000<br> ~~ee~~<br>~~ts~~<br>~~IfflTiTitiil.~~|0x00<br>~~ee~~<br>~~ns~~<br>~~IfflTiTitiil.~~|Freefall/Motion debounce counter<br>~~IfflTiTitiil.~~||
|Reserved<br>~~-IfflTiTitiil.~~|R<br>~~ee~~<br>~~IfflTiTitiil.~~|0x19<br>0x1A<br>0x1B<br>0x1C<br>~~es~~<br>~~IfflTiTitiil.~~|—<br>~~ee~~<br>~~IfflTiTitiil.~~|—<br>~~ee~~<br>~~IfflTiTitiil.~~|—<br>~~ee~~<br>~~IfflTiTitiil.~~|—<br>~~IfflTiTitiil.~~|—<br>~~ts~~<br>~~IfflTiTitiil.~~|—<br>~~ns~~<br>~~IfflTiTitiil.~~|Reserved. Read return 0x00.<br>~~IfflTiTitiil.~~||



## **Table 12. MMA8652FC register address map (Continued)** 

|**Name**|**Type **|**Register**<br>**Address**|**Auto-Increment Address**<br>~~po~~|**Auto-Increment Address**<br>~~po~~|**Auto-Increment Address**<br>~~po~~|**Auto-Increment Address**<br>~~po~~|**Default**|**Hex**<br>**Value**|**Comment**|
|---|---|---|---|---|---|---|---|---|---|
||||**FMODE = 0**<br>**F_READ = 0**|**FMODE > 0**<br>**F_READ = 0**|**FMODE = 0**<br>**F_READ = 1**|**FMODE > 0**<br>**F_READ = 1**||||
|TRANSIENT_CFG(1)(4)<br>~~a~~<br>~~ee~~|R/W<br>~~GO~~|0x1D<br>~~GO~~|0x1E<br>~~GO~~||||00000000<br>~~GO~~|0x00<br>~~GO~~|Transient functional block<br>configuration<br>~~GO~~|
|TRANSIENT_SRC(1)(2)<br>~~ee~~|R<br>~~GO~~|0x1E<br>~~GO~~|0x1F<br>~~GO~~||||00000000<br>~~GO~~|0x00<br>~~GO~~|Transient event status register<br>~~GO~~|
|TRANSIENT_THS(1)(3)<br>~~ee~~<br>~~ee~~<br>~~po~~|R/W<br>~~GO~~<br>~~ee~~|0x1F<br>~~GO~~|0x20<br>~~GO~~||||00000000<br>~~GO~~<br>~~O~~|0x00<br>~~GO~~|Transient event threshold<br>~~GO~~|
|TRANSIENT_COUNT(1)(3)<br>~~po~~<br>~~ee~~|R/W<br>~~eG~~|0x20<br>~~eG~~|0x21<br>~~eG~~||||00000000<br>~~eG~~|0x00<br>~~eG~~|Transient debounce counter<br>~~eG~~|
|PULSE_CFG(1)(4)<br>~~po~~<br>~~ee~~<br>~~ee~~|R/W<br>~~eG~~<br>~~GG~~|0x21<br>~~eG~~<br>~~GG~~|0x22<br>~~eG~~<br>~~GG~~||||00000000<br>~~eG~~<br>~~GG~~|0x00<br>~~eG~~<br>~~GG~~|Pulse enable configuration<br>~~eG~~<br>~~GG~~|
|PULSE_SRC(1)(2)<br>~~ee~~<br>~~ee~~|R<br>~~eG~~<br>~~GG~~|0x22<br>~~eG~~<br>~~GG~~|0x23<br>~~eG~~<br>~~GG~~||||00000000<br>~~eG~~<br>~~GG~~|0x00<br>~~eG~~<br>~~GG~~|Pulse detection source<br>~~eG~~<br>~~GG~~|
|PULSE_THSX(1)(3)<br>~~ee~~<br>~~GO~~<br>~~ee~~|R/W<br>~~GG~~<br>~~GO~~<br>~~GO~~|0x23<br>~~GG~~<br>~~GO~~<br>~~GO~~|0x24<br>~~GG~~<br>~~GO~~<br>~~GO~~||||00000000<br>~~GG~~<br>~~GO~~<br>~~GO~~|0x00<br>~~GG~~<br>~~GO~~<br>~~GO~~|X pulse threshold<br>~~GG~~<br>~~GO~~<br>~~GO~~|
|PULSE_THSY(1)(3)<br>~~ee~~|R/W<br>~~GO~~|0x24<br>~~GO~~|0x25<br>~~GO~~||||00000000<br>~~GO~~|0x00<br>~~GO~~|Y pulse threshold<br>~~GO~~|
|PULSE_THSZ(1)(3)<br>~~ee~~<br>~~ee~~<br>~~po~~|R/W<br>~~GO~~<br>~~ee~~|0x25<br>~~GO~~|0x26<br>~~GO~~||||00000000<br>~~GO~~<br>~~O~~|0x00<br>~~GO~~|Z pulse threshold<br>~~GO~~|
|PULSE_TMLT(1)(4)<br>~~po~~<br>~~ee~~|R/W<br>~~eG~~|0x26<br>~~eG~~|0x27<br>~~eG~~||||00000000<br>~~eG~~|0x00<br>~~eG~~|Time limit for pulse<br>~~eG~~|
|PULSE_LTCY(1)(4)<br>~~po~~<br>~~ee~~<br>~~ee~~|R/W<br>~~eG~~<br>~~GG~~|0x27<br>~~eG~~<br>~~GG~~|0x28<br>~~eG~~<br>~~GG~~||||00000000<br>~~eG~~<br>~~GG~~|0x00<br>~~eG~~<br>~~GG~~|Latency time for 2ndpulse<br>~~eG~~<br>~~GG~~|
|PULSE_WIND(1)(4)<br>~~ee~~<br>~~ee~~|R/W<br>~~eG~~<br>~~GG~~|0x28<br>~~eG~~<br>~~GG~~|0x29<br>~~eG~~<br>~~GG~~||||00000000<br>~~eG~~<br>~~GG~~|0x00<br>~~eG~~<br>~~GG~~|Window time for 2nd pulse<br>~~eG~~<br>~~GG~~|
|ASLP_COUNT(1)(4)<br>~~ee~~<br>~~GO~~<br>~~ee~~|R/W<br>~~GG~~<br>~~GO~~<br>~~GO~~|0x29<br>~~GG~~<br>~~GO~~<br>~~GO~~|0x2A<br>~~GG~~<br>~~GO~~<br>~~GO~~||||00000000<br>~~GG~~<br>~~GO~~<br>~~GO~~|0x00<br>~~GG~~<br>~~GO~~<br>~~GO~~|Counter setting for Auto-SLEEP<br>~~GG~~<br>~~GO~~<br>~~GO~~|
|CTRL_REG1(1)(4)<br>~~ee~~<br>~~PR~~|R/W<br>~~GO~~|0x2A<br>~~GO~~|0x2B<br>~~GO~~||||00000000<br>~~GO~~|0x00<br>~~GO~~|Data rates and modes setting<br>~~GO~~|
|CTRL_REG2(1)(4)<br>~~ee~~<br>~~PR~~<br>~~ee~~|R/W<br>~~GO~~<br>~~GG~~|0x2B<br>~~GO~~<br>~~GG~~|0x2C<br>~~GO~~<br>~~GG~~||||00000000<br>~~GO~~<br>~~GG~~|0x00<br>~~GO~~<br>~~GG~~|Sleep Enable, OS modes,<br>RST, ST<br>~~GO~~<br>~~GG~~|
|CTRL_REG3(1)(4)<br>~~PR~~<br>~~ee~~|R/W<br>~~GG~~|0x2C<br>~~GG~~|0x2D<br>~~GG~~||||00000000<br>~~GG~~|0x00<br>~~GG~~|Wake from Sleep, IPOL, PP_OD<br>~~GG~~|
|CTRL_REG4(1)(4)<br>~~ee~~<br>~~GO~~<br>~~ee~~|R/W<br>~~GG~~<br>~~GO~~<br>~~GO~~|0x2D<br>~~GG~~<br>~~GO~~<br>~~GO~~|0x2E<br>~~GG~~<br>~~GO~~<br>~~GO~~||||00000000<br>~~GG~~<br>~~GO~~<br>~~GO~~|0x00<br>~~GG~~<br>~~GO~~<br>~~GO~~|Interrupt enable register<br>~~GG~~<br>~~GO~~<br>~~GO~~|
|CTRL_REG5(1)(4)<br>~~GO~~<br>~~ee~~|R/W<br>~~GO~~<br>~~GO~~|0x2E<br>~~GO~~<br>~~GO~~|0x2F<br>~~GO~~<br>~~GO~~||||00000000<br>~~GO~~<br>~~GO~~|0x00<br>~~GO~~<br>~~GO~~|Interrupt pin (INT1/INT2) map<br>~~GO~~<br>~~GO~~|
|OFF_X(1)(4)<br>~~ee~~<br>~~ee~~<br>~~po~~|R/W<br>~~GO~~<br>~~ee~~|0x2F<br>~~GO~~|0x30<br>~~GO~~||||00000000<br>~~GO~~<br>~~O~~|0x00<br>~~GO~~|X-axis offset adjust<br>~~GO~~|
|OFF_Y(1)(4)<br>~~po~~<br>~~ee~~|R/W<br>~~ee~~|0x30<br>~~ee GO~~|0x31<br>~~GO~~||||00000000<br>~~GO~~|0x00<br>~~GO~~|Y-axis offset adjust<br>~~GO~~|
|OFF_Z(1)(4)<br>~~po~~<br>~~ee~~|R/W<br>~~ee~~|0x31<br>~~ee GO~~|**0x0D**<br>~~GO~~||||00000000<br>~~GO~~|0x00<br>~~GO~~|Z-axis offset adjust<br>~~GO~~|



1. Register contents are preserved when a transition from ACTIVE to STANDBY mode occurs. 

2. Register contents are reset when a transition from STANDBY to ACTIVE mode occurs. 

3. Register contents can be modified at any time in either STANDBY or ACTIVE mode. A write to this register will cause a reset of the corresponding internal system debounce counter. 

4. Register contents can only be modified while the device is in STANDBY mode; the only exceptions to this are the CTRL_REG1[ACTIVE] and CTRL_REG2[RST] bits. 

## **NOTE** 

Auto-increment addresses that are not a simple increment are highlighted in **bold** . The auto-increment addressing is only enabled when device registers are read using I[2] C _burst read mode_ . The _internally stored_ auto-increment address is cleared whenever an I[2] C STOP condition is detected. 

**MMA8652FC** 

Sensors Freescale Semiconductor, Inc. 

22 

## **6.2 Register bit map** 

**Table 13. MMA8652FC register bit map** 

|**Reg**<br>~~Pp~~<br>~~pp~~|**Name**<br>~~Pp~~<br>~~pp~~|**Definition**<br>~~Pp~~<br>|**Type**<br>~~Pp~~<br>|**Bit 7**<br>~~Pp~~<br>|**Bit 6**<br>~~Pp~~<br>|**Bit 5**<br>~~Pp~~<br>~~eG~~<br>|**Bit 4**<br>~~Pp~~<br>~~eG~~<br>|**Bit 3**<br>~~Pp~~<br>|**Bit 2**<br>~~Pp~~<br>|**Bit 1**<br>~~Pp~~<br>|**Bit 0**<br>~~Pp~~<br>|
|---|---|---|---|---|---|---|---|---|---|---|---|
|00<br>~~Od~~<br>~~pp~~|STATUS/F_STATUS<br>~~Od~~<br>~~pp~~|Data Status<br>~~Od~~<br>|R<br>~~Od~~<br>|ZYXOW<br>~~Od~~<br>|ZOW<br>~~Od~~<br>|YOW<br>~~Od~~<br>~~eG~~<br>|XOW<br>~~Od~~<br>~~eG~~<br>|ZYXDR<br>~~Od~~<br>|ZDR<br>~~Od~~<br>|YDR<br>~~Od~~<br>|XDR<br>~~Od~~<br>|
|01<br>~~Od~~<br>~~pp~~<br>~~pp~~|OUT_X_MSB<br>~~Od~~<br>~~pp~~<br>~~pp~~|12-bit X Data<br>~~Od~~<br><br>|R<br>~~Od~~<br><br>|XD11<br>~~Od~~<br><br>|XD10<br>~~Od~~<br><br>|XD9<br>~~Od~~<br>~~eG~~<br><br>~~eG~~<br>|XD8<br>~~Od~~<br>~~eG~~<br><br>~~eG~~<br>|XD7<br>~~Od~~<br><br>|XD6<br>~~Od~~<br><br>|XD5<br>~~Od~~<br><br>|XD4<br>~~Od~~<br><br>|
|02<br>~~ppOd~~<br>~~pp~~|OUT_X_LSB<br>~~ppOd~~<br>~~pp~~|12-bit X Data<br>~~Od~~<br>|R<br>~~Od~~<br>|XD3<br>~~Od~~<br>|XD2<br>~~Od~~<br>|XD1<br>~~eG~~<br>~~Od~~<br>~~eG~~<br>|XD0<br>~~eG~~<br>~~Od~~<br>~~eG~~<br>|0<br>~~Od~~<br>|0<br>~~Od~~<br>|0<br>~~Od~~<br>|0<br>~~Od~~<br>|
|03<br>~~Od~~<br>~~pp~~<br>~~pp~~|OUT_Y_MSB<br>~~Od~~<br>~~pp~~<br>~~pp~~|12-bit Y Data<br>~~Od~~<br><br>|R<br>~~Od~~<br><br>|YD11<br>~~Od~~<br><br>|YD10<br>~~Od~~<br><br>|YD9<br>~~Od~~<br>~~eG~~<br><br>~~eG~~<br>|YD8<br>~~Od~~<br>~~eG~~<br><br>~~eG~~<br>|YD7<br>~~Od~~<br><br>|YD6<br>~~Od~~<br><br>|YD5<br>~~Od~~<br><br>|YD4<br>~~Od~~<br><br>|
|04<br>~~ppOd~~<br>~~pp~~|OUT_Y_LSB<br>~~ppOd~~<br>~~pp~~|12-bit Y Data<br>~~Od~~<br>|R<br>~~Od~~<br>|YD3<br>~~Od~~<br>|YD2<br>~~Od~~<br>|YD1<br>~~eG~~<br>~~Od~~<br>~~eG~~<br>|YD0<br>~~eG~~<br>~~Od~~<br>~~eG~~<br>|0<br>~~Od~~<br>|0<br>~~Od~~<br>|~~Od~~<br>|0<br>~~Od~~<br>|
|05<br>~~Od~~<br>~~pp~~<br>~~pp~~|OUT_Z_MSB<br>~~Od~~<br>~~pp~~<br>~~pp~~|12-bit Z Data<br>~~Od~~<br><br>|R<br>~~Od~~<br><br>|ZD11<br>~~Od~~<br><br>|ZD10<br>~~Od~~<br><br>|ZD9<br>~~Od~~<br>~~eG~~<br><br>~~eG~~<br>|ZD8<br>~~Od~~<br>~~eG~~<br><br>~~eG~~<br>|ZD7<br>~~Od~~<br><br>|ZD6<br>~~Od~~<br><br>|ZD5<br>~~Od~~<br><br>|ZD4<br>~~Od~~<br><br>|
|06<br>~~ppOd~~<br>~~pp~~|OUT_Z_LSB<br>~~ppOd~~<br>~~pp~~|12-bit Z Data<br>~~Od~~<br>|R<br>~~Od~~<br>|ZD3<br>~~Od~~<br>|ZD2<br>~~Od~~<br>|ZD1<br>~~eG~~<br>~~Od~~<br>~~eG~~<br>|ZD0<br>~~eG~~<br>~~Od~~<br>~~eG~~<br>|0<br>~~Od~~<br>|0<br>~~Od~~<br>|0<br>~~Od~~<br>|0<br>~~Od~~<br>|
|09<br>~~Od~~<br>~~pp~~<br>~~pp~~|F_SETUP<br>~~Od~~<br>~~pp~~<br>~~pp~~|FIFO Setup<br>~~Od~~<br><br>|R/W<br>~~Od~~<br><br>|F_MODE1<br>~~Od~~<br><br>|F_MODE0<br>~~Od~~<br><br>|F_WMRK5<br>~~Od~~<br>~~eG~~<br><br>~~eG~~<br>|F_WMRK4<br>~~Od~~<br>~~eG~~<br><br>~~eG~~<br>|F_WMRK3<br>~~Od~~<br><br>|F_WMRK2<br>~~Od~~<br><br>|F_WMRK1<br>~~Od~~<br><br>|F_WMRK0<br>~~Od~~<br><br>|
|0A<br>~~ppOd~~<br>~~pp~~|TRIG_CFG<br>~~ppOd~~<br>~~pp~~|FIFO Triggers<br>~~Od~~<br>|R/W<br>~~Od~~<br>|—<br>~~Od~~<br>|—<br>~~Od~~<br>|Trig_TRANS<br>~~eG~~<br>~~Od~~<br>~~eG~~<br>|Trig_LNDPRT<br>~~eG~~<br>~~Od~~<br>~~eG~~<br>|Trig_PULSE<br>~~Od~~<br>|Trig_FF_MT<br>~~Od~~<br>|—<br>~~Od~~<br>|—<br>~~Od~~<br>|
|0B<br>~~Od~~<br>~~pp~~<br>~~pp~~|SYSMOD<br>~~Od~~<br>~~pp~~<br>~~pp~~|System mode<br>~~Od~~<br><br>|R<br>~~Od~~<br><br>|FGERR<br>~~Od~~<br><br>|FGT_4<br>~~Od~~<br><br>|FGT_3<br>~~Od~~<br>~~eG~~<br><br>~~eG~~<br>|FGT_2<br>~~Od~~<br>~~eG~~<br><br>~~eG~~<br>|FGT_1<br>~~Od~~<br><br>|FGT_0<br>~~Od~~<br><br>|SYSMOD1<br>~~Od~~<br><br>|SYSMOD0<br>~~Od~~<br><br>|
|0C<br>~~ppOd~~<br>~~pp~~|INT_SOURCE<br>~~ppOd~~<br>~~pp~~|Interrupt Status<br>~~Od~~<br>|R<br>~~Od~~<br>|SRC_ASLP<br>~~Od~~<br>|SRC_FIFO<br>~~Od~~<br>|SRC_TRANS<br>~~eG~~<br>~~Od~~<br>~~eG~~<br>|SRC_LNDPRT<br>~~eG~~<br>~~Od~~<br>~~eG~~<br>|SRC_PULSE<br>~~Od~~<br>|SRC_FF_MT<br>~~Od~~<br>|—<br>~~Od~~<br>|SRC_DRDY<br>~~Od~~<br>|
|0D<br>~~Od~~<br>~~pp~~<br>~~pp~~|WHO_AM_I<br>~~Od~~<br>~~pp~~<br>~~pp~~|ID Register<br>~~Od~~<br><br>|R<br>~~Od~~<br><br>|0<br>~~Od~~<br><br>|1<br>~~Od~~<br><br>|0<br>~~Od~~<br>~~eG~~<br><br>~~eG~~<br>|0<br>~~Od~~<br>~~eG~~<br><br>~~eG~~<br>|1<br>~~Od~~<br><br>|0<br>~~Od~~<br><br>|1<br>~~Od~~<br><br>|0<br>~~Od~~<br><br>|
|0E<br>~~ppOd~~<br>~~pp~~|XYZ_DATA_CFG<br>~~ppOd~~<br>~~pp~~|Data Config<br>~~Od~~<br>|R/W<br>~~Od~~<br>|—<br>~~Od~~<br>|—<br>~~Od~~<br>|—<br>~~eG~~<br>~~Od~~<br>~~eG~~<br>|HPF_Out<br>~~eG~~<br>~~Od~~<br>~~eG~~<br>|—<br>~~Od~~<br>|—<br>~~Od~~<br>|FS1<br>~~Od~~<br>|FS0<br>~~Od~~<br>|
|0F<br>~~Od~~<br>~~pp~~<br>~~pp~~|HP_FILTER_CUTOFF<br>~~Od~~<br>~~pp~~<br>~~pp~~|HP Filter Setting<br>~~Od~~<br><br>|R/W<br>~~Od~~<br><br>|—<br>~~Od~~<br><br>|—<br>~~Od~~<br><br>|Pulse_HPF_BYP<br>~~Od~~<br>~~eG~~<br><br>~~eG~~<br>|Pulse_LPF_EN<br>~~Od~~<br>~~eG~~<br><br>~~eG~~<br>|—<br>~~Od~~<br><br>|—<br>~~Od~~<br><br>|SEL1<br>~~Od~~<br><br>|SEL0<br>~~Od~~<br><br>|
|10<br>~~ppOd~~<br>~~pp~~|PL_STATUS<br>~~ppOd~~<br>~~pp~~|PL Status<br>~~Od~~<br>|R<br>~~Od~~<br>|NEWLP<br>~~Od~~<br>|LO<br>~~Od~~<br>|—<br>~~eG~~<br>~~Od~~<br>~~eG~~<br>|—<br>~~eG~~<br>~~Od~~<br>~~eG~~<br>|—<br>~~Od~~<br>|LAPO[1]<br>~~Od~~<br>|LAPO[0]<br>~~Od~~<br>|BAFRO<br>~~Od~~<br>|
|11<br>~~Od~~<br>~~pp~~<br>~~pp~~|PL_CFG<br>~~Od~~<br>~~pp~~<br>~~pp~~|PL Configuration<br>~~Od~~<br><br>|R/W<br>~~Od~~<br><br>|DBCNTM<br>~~Od~~<br><br>|PL_EN<br>~~Od~~<br><br>|—<br>~~Od~~<br>~~eG~~<br><br>~~eG~~<br>|—<br>~~Od~~<br>~~eG~~<br><br>~~eG~~<br>|—<br>~~Od~~<br><br>|—<br>~~Od~~<br><br>|—<br>~~Od~~<br><br>|—<br>~~Od~~<br><br>|
|12<br>~~ppOd~~<br>~~pp~~|PL_COUNT<br>~~ppOd~~<br>~~pp~~|PL DEBOUNCE<br>~~Od~~<br>|R/W<br>~~Od~~<br>|DBNCE[7]<br>~~Od~~<br>|DBNCE[6]<br>~~Od~~<br>|DBNCE[5]<br>~~eG~~<br>~~Od~~<br>~~eG~~<br>|DBNCE[4]<br>~~eG~~<br>~~Od~~<br>~~eG~~<br>|DBNCE[3]<br>~~Od~~<br>|DBNCE[2]<br>~~Od~~<br>|DBNCE[1]<br>~~Od~~<br>|DBNCE[0]<br>~~Od~~<br>|
|13<br>~~Od~~<br>~~pp~~<br>~~pp~~|PL_BF_ZCOMP<br>~~Od~~<br>~~pp~~<br>~~pp~~|PL Back/Front Z Comp<br>~~Od~~<br><br>|R/W<br>~~Od~~<br><br>|BKFR[1]<br>~~Od~~<br><br>|BKFR[0]<br>~~Od~~<br><br>|—<br>~~Od~~<br>~~eG~~<br><br>~~eG~~<br>|—<br>~~Od~~<br>~~eG~~<br><br>~~eG~~<br>|—<br>~~Od~~<br><br>|ZLOCK[2]<br>~~Od~~<br><br>|ZLOCK[1]<br>~~Od~~<br><br>|ZLOCK[0]<br>~~Od~~<br><br>|
|14<br>~~ppOd~~<br>~~pp~~|P_L_THS_REG<br>~~ppOd~~<br>~~pp~~|PL THRESHOLD<br>~~Od~~<br>|R/W<br>~~Od~~<br>|P_L_THS[4]<br>~~Od~~<br>|P_L_THS[3]<br>~~Od~~<br>|P_L_THS[2]<br>~~eG~~<br>~~Od~~<br>~~eG~~<br>|P_L_THS[1]<br>~~eG~~<br>~~Od~~<br>~~eG~~<br>|P_L_THS[0]<br>~~Od~~<br>|HYS[2]<br>~~Od~~<br>|HYS[1]<br>~~Od~~<br>|HYS[0]<br>~~Od~~<br>|
|15<br>~~Od~~<br>~~pp~~<br>~~pp~~|FF_MT_CFG<br>~~Od~~<br>~~pp~~<br>~~pp~~|Freefall/Motion Config<br>~~Od~~<br><br>|R/W<br>~~Od~~<br><br>|ELE<br>~~Od~~<br><br>|OAE<br>~~Od~~<br><br>|ZEFE<br>~~Od~~<br>~~eG~~<br><br>~~eG~~<br>|YEFE<br>~~Od~~<br>~~eG~~<br><br>~~eG~~<br>|XEFE<br>~~Od~~<br><br>|—<br>~~Od~~<br><br>|—<br>~~Od~~<br><br>|—<br>~~Od~~<br><br>|
|16<br>~~ppOd~~<br>~~pp~~|FF_MT_SRC<br>~~ppOd~~<br>~~pp~~|Freefall/Motion Source<br>~~Od~~<br>|R<br>~~Od~~<br>|EA<br>~~Od~~<br>|—<br>~~Od~~<br>|ZHE<br>~~eG~~<br>~~Od~~<br>~~eG~~<br>|ZHP<br>~~eG~~<br>~~Od~~<br>~~eG~~<br>|YHE<br>~~Od~~<br>|YHP<br>~~Od~~<br>|XHE<br>~~Od~~<br>|XHP<br>~~Od~~<br>|
|17<br>~~Od~~<br>~~pp~~<br>~~pp~~|FF_MT_THS<br>~~Od~~<br>~~pp~~<br>~~pp~~|Freefall/Motion Threshold<br>~~Od~~<br><br>|R/W<br>~~Od~~<br><br>|DBCNTM<br>~~Od~~<br><br>|THS6<br>~~Od~~<br><br>|THS5<br>~~Od~~<br>~~eG~~<br><br>~~eG~~<br>|THS4<br>~~Od~~<br>~~eG~~<br><br>~~eG~~<br>|THS3<br>~~Od~~<br><br>|THS2<br>~~Od~~<br><br>|THS1<br>~~Od~~<br><br>|THS0<br>~~Od~~<br><br>|
|18<br>~~ppOd~~<br>~~pp~~|FF_MT_COUNT<br>~~ppOd~~<br>~~pp~~|Freefall/Motion Debounce<br>~~Od~~<br>|R/W<br>~~Od~~<br>|D7<br>~~Od~~<br>|D6<br>~~Od~~<br>|D5<br>~~eG~~<br>~~Od~~<br>~~eG~~<br>|D4<br>~~eG~~<br>~~Od~~<br>~~eG~~<br>|D3<br>~~Od~~<br>|D2<br>~~Od~~<br>|D1<br>~~Od~~<br>|D0<br>~~Od~~<br>|
|1D<br>~~Od~~<br>~~pp~~<br>~~pp~~|TRANSIENT_CFG<br>~~Od~~<br>~~pp~~<br>~~pp~~|Transient Config<br>~~Od~~<br><br>|R/W<br>~~Od~~<br><br>|—<br>~~Od~~<br><br>|—<br>~~Od~~<br><br>|—<br>~~Od~~<br>~~eG~~<br><br>~~eG~~<br>|ELE<br>~~Od~~<br>~~eG~~<br><br>~~eG~~<br>|ZTEFE<br>~~Od~~<br><br>|YTEFE<br>~~Od~~<br><br>|XTEFE<br>~~Od~~<br><br>|HPF_BYP<br>~~Od~~<br><br>|
|1E<br>~~ppOd~~<br>~~pp~~|TRANSIENT_SRC<br>~~ppOd~~<br>~~pp~~|Transient Source<br>~~Od~~<br>|R<br>~~Od~~<br>|—<br>~~Od~~<br>|EA<br>~~Od~~<br>|ZTRANSE<br>~~eG~~<br>~~Od~~<br>~~eG~~<br>|Z_Trans_Pol<br>~~eG~~<br>~~Od~~<br>~~eG~~<br>|YTRANSE<br>~~Od~~<br>|Y_Trans_Pol<br>~~Od~~<br>|XTRANSE<br>~~Od~~<br>|X_Trans_Pol<br>~~Od~~<br>|
|1F<br>~~Od~~<br>~~pp~~<br>~~pp~~|TRANSIENT_THS<br>~~Od~~<br>~~pp~~<br>~~pp~~|Transient Threshold<br>~~Od~~<br><br>|R/W<br>~~Od~~<br><br>|DBCNTM<br>~~Od~~<br><br>|THS6<br>~~Od~~<br><br>|THS5<br>~~Od~~<br>~~eG~~<br><br>~~eG~~<br>|THS4<br>~~Od~~<br>~~eG~~<br><br>~~eG~~<br>|THS3<br>~~Od~~<br><br>|THS2<br>~~Od~~<br><br>|THS1<br>~~Od~~<br><br>|THS0<br>~~Od~~<br><br>|
|20<br>~~ppOd~~<br>~~pp~~|TRANSIENT_COUNT<br>~~ppOd~~<br>~~pp~~|Transient Debounce<br>~~Od~~<br>|R/W<br>~~Od~~<br>|D7<br>~~Od~~<br>|D6<br>~~Od~~<br>|D5<br>~~eG~~<br>~~Od~~<br>~~eG~~<br>|D4<br>~~eG~~<br>~~Od~~<br>~~eG~~<br>|D3<br>~~Od~~<br>|D2<br>~~Od~~<br>|D1<br>~~Od~~<br>|D0<br>~~Od~~<br>|
|21<br>~~Od~~<br>~~pp~~<br>~~pp~~|PULSE_CFG<br>~~Od~~<br>~~pp~~<br>~~pp~~|Pulse Config<br>~~Od~~<br><br>|R/W<br>~~Od~~<br><br>|DPA<br>~~Od~~<br><br>|ELE<br>~~Od~~<br><br>|ZDPEFE<br>~~Od~~<br>~~eG~~<br><br>~~eG~~<br>|ZSPEFE<br>~~Od~~<br>~~eG~~<br><br>~~eG~~<br>|YDPEFE<br>~~Od~~<br><br>|YSPEFE<br>~~Od~~<br><br>|XDPEFE<br>~~Od~~<br><br>|XSPEFE<br>~~Od~~<br><br>|
|22<br>~~ppOd~~<br>~~pp~~|PULSE_SRC<br>~~ppOd~~<br>~~pp~~|Pulse Source<br>~~Od~~<br>|R<br>~~Od~~<br>|EA<br>~~Od~~<br>|AxZ<br>~~Od~~<br>|AxY<br>~~eG~~<br>~~Od~~<br>~~eG~~<br>|AxX<br>~~eG~~<br>~~Od~~<br>~~eG~~<br>|DPE<br>~~Od~~<br>|Pol_Z<br>~~Od~~<br>|Pol_Y<br>~~Od~~<br>|Pol_X<br>~~Od~~<br>|
|23<br>~~Od~~<br>~~pp~~<br>~~pp~~|PULSE_THSX<br>~~Od~~<br>~~pp~~<br>~~pp~~|Pulse X Threshold<br>~~Od~~<br><br>|R/W<br>~~Od~~<br><br>|—<br>~~Od~~<br><br>|THSX6<br>~~Od~~<br><br>|THSX5<br>~~Od~~<br>~~eG~~<br><br>~~eG~~<br>|THSX4<br>~~Od~~<br>~~eG~~<br><br>~~eG~~<br>|THSX3<br>~~Od~~<br><br>|THSX2<br>~~Od~~<br><br>|THSX1<br>~~Od~~<br><br>|THSX0<br>~~Od~~<br><br>|
|24<br>~~ppOd~~<br>~~pp~~|PULSE_THSY<br>~~ppOd~~<br>~~pp~~|Pulse Y Threshold<br>~~Od~~<br>|R/W<br>~~Od~~<br>|—<br>~~Od~~<br>|THSY6<br>~~Od~~<br>|THSY5<br>~~eG~~<br>~~Od~~<br>~~eG~~<br>|THSY4<br>~~eG~~<br>~~Od~~<br>~~eG~~<br>|THSY3<br>~~Od~~<br>|THSY2<br>~~Od~~<br>|THSY1<br>~~Od~~<br>|THSY0<br>~~Od~~<br>|
|25<br>~~Od~~<br>~~pp~~<br>~~pp~~|PULSE_THSZ<br>~~Od~~<br>~~pp~~<br>~~pp~~|Pulse Z Threshold<br>~~Od~~<br><br>|R/W<br>~~Od~~<br><br>|—<br>~~Od~~<br><br>|THSZ6<br>~~Od~~<br><br>|THSZ5<br>~~Od~~<br>~~eG~~<br><br>~~eG~~<br>|THSZ4<br>~~Od~~<br>~~eG~~<br><br>~~eG~~<br>|THSZ3<br>~~Od~~<br><br>|THSZ2<br>~~Od~~<br><br>|THSZ1<br>~~Od~~<br><br>|THSZ0<br>~~Od~~<br><br>|
|26<br>~~ppOd~~<br>~~pp~~|PULSE_TMLT<br>~~ppOd~~<br>~~pp~~|Pulse First Timer<br>~~Od~~<br>|R/W<br>~~Od~~<br>|TMLT7<br>~~Od~~<br>|TMLT6<br>~~Od~~<br>|TMLT5<br>~~eG~~<br>~~Od~~<br>~~eG~~<br>|TMLT4<br>~~eG~~<br>~~Od~~<br>~~eG~~<br>|TMLT3<br>~~Od~~<br>|TMLT2<br>~~Od~~<br>|TMLT1<br>~~Od~~<br>|TMLT0<br>~~Od~~<br>|
|27<br>~~Od~~<br>~~pp~~<br>~~pp~~|PULSE_LTCY<br>~~Od~~<br>~~pp~~<br>~~pp~~|Pulse Latency<br>~~Od~~<br><br>|R/W<br>~~Od~~<br><br>|LTCY7<br>~~Od~~<br><br>|LTCY6<br>~~Od~~<br><br>|LTCY5<br>~~Od~~<br>~~eG~~<br><br>~~eG~~<br>|LTCY4<br>~~Od~~<br>~~eG~~<br><br>~~eG~~<br>|LTCY3<br>~~Od~~<br><br>|LTCY2<br>~~Od~~<br><br>|LTCY1<br>~~Od~~<br><br>|LTCY0<br>~~Od~~<br><br>|
|28<br>~~ppOd~~<br>~~pp~~|PULSE_WIND<br>~~ppOd~~<br>~~pp~~|Pulse 2nd Window<br>~~Od~~<br>|R/W<br>~~Od~~<br>|WIND7<br>~~Od~~<br>|WIND6<br>~~Od~~<br>|WIND5<br>~~eG~~<br>~~Od~~<br>~~eG~~<br>|WIND4<br>~~eG~~<br>~~Od~~<br>~~eG~~<br>|WIND3<br>~~Od~~<br>|WIND2<br>~~Od~~<br>|WIND1<br>~~Od~~<br>|WIND0<br>~~Od~~<br>|
|29<br>~~Od~~<br>~~pp~~|ASLP_COUNT<br>~~Od~~<br>~~pp~~|Auto-SLEEP Counter<br>~~Od~~<br>|R/W<br>~~Od~~<br>|D7<br>~~Od~~<br>|D6<br>~~Od~~<br>|D5<br>~~Od~~<br>~~eG~~<br><br>~~eG~~|D4<br>~~Od~~<br>~~eG~~<br><br>~~eG~~|D3<br>~~Od~~<br>|D2<br>~~Od~~<br>|D1<br>~~Od~~<br>|D0<br>~~Od~~<br>|
|2A<br>~~ppOd~~|CTRL_REG1<br>~~ppOd~~|Control Reg1<br>~~Od~~|R/W<br>~~Od~~|ASLP_RATE1<br>~~Od~~|ASLP_RATE0<br>~~Od~~|DR2<br>~~eG~~<br>~~Od~~<br>~~eG~~|DR1<br>~~eG~~<br>~~Od~~<br>~~eG~~|DR0<br>~~Od~~|**—**<br>~~Od~~|F_READ<br>~~Od~~|ACTIVE<br>~~Od~~|
|2B<br>~~Od~~|CTRL_REG2<br>~~Od~~|Control Reg2<br>~~Od~~|R/W<br>~~Od~~|ST<br>~~Od~~|RST<br>~~Od~~|—<br>~~Od~~<br>~~eG~~|SMODS1<br>~~Od~~<br>~~eG~~|SMODS0<br>~~Od~~|SLPE<br>~~Od~~|MODS1<br>~~Od~~|MODS0<br>~~Od~~|
|2C|CTRL_REG3|Control Reg3<br>(WAKE Interrupts from SLEEP)|R/W|FIFO_GATE|WAKE_TRANS|WAKE_LNDPRT|WAKE_PULSE|WAKE_FF_MT|—|IPOL|PP_OD|
|2D|CTRL_REG4|Control Reg4<br>(Interrupt Enable Map)|R/W|INT_EN_ASLP|INT_EN_FIFO|INT_EN_TRANS|INT_EN_LNDPRT|INT_EN_PULSE|INT_EN_FF_MT|—|INT_EN_DRDY|



**MMA8652FC** 

Sensors Freescale Semiconductor, Inc. 

23 

## **Table 13. MMA8652FC register bit map (Continued)** 

~~a~~ **Reg** ~~se~~ **Name Definition Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0** 2E CTRL_REG5 (Interrupt Configuration)Control Reg5 R/W INT_CFG_ASLP INT_CFG_FIFO INT_CFG_TRANS INT_CFG_LNDPRT INT_CFG_PULSE INT_CFG_FF_MT — INT_CFG_DRDY ~~fo}~~ 2F OFF_X X-axis 0 g offset R/W D7 ~~dG~~ D6 ~~GG~~ D5 D4 D3 D2 D1 D0 ~~OO~~ 30 OFF_Y Y-axis 0 g offset R/W D7 D6 ~~CO~~ D5 D4 D3 D2 D1 D0 ~~aOG~~ 31 OFF_Z Z-axis 0 g offset R/W D7 D6 D5 D4 D3 D2 D1 D0 ~~OC~~ 

**MMA8652FC** 

Sensors Freescale Semiconductor, Inc. 

24 

## **6.3 Data registers** 

The following are the data registers for the MMA8652FC device. For more information about data manipulation in the MMA8652FC, see application note AN4083, _Data Manipulation and Basic Settings for Xtrinsic MMA865xFC Accelerometers._ 

- When the F_MODE bits (F_SETUP register 0x09, bit 6 and 7) are cleared, the FIFO is not ON. Register 0x00 reflects the real-time status information of the X, Y and Z sample data. 

- When the F_MODE value is greater than zero, then the FIFO is ON (in either Fill, Circular, or Trigger mode). In this case, register 0x00 will reflect the status of the FIFO. It is expected that when the FIFO is ON, the user will access the data from register 0x01 (X_MSB) for either the 12-bit or 8-bit data. 

- When accessing the 8-bit data, the F_READ bit (register 0x2A) is set, which modifies the auto-incrementing to skip over the LSB data. 

- When the F_READ bit is cleared, the 12-bit data is read, accessing all 6 bytes sequentially (X_MSB, X_LSB, Y_MSB, Y_LSB, Z_MSB, Z_LSB). 

## **6.3.1 0x00: STATUS Data Status register (F_MODE = 00)** 

When F_MODE = 0, register 0x00 reflects the real-time status information of the X, Y and Z sample data; it contains the X, Y, and Z data overwrite and data ready flag. 

These registers contain the X-axis, Y-axis, and Z-axis 12-bit output sample data (expressed as 2's complement numbers). 

**Table 14. F_MODE = 00: 0x00 STATUS: Data Status register (Read-Only)** 

|**Table 14. F_MODE = 00: 0x00 STATUS: Data Status register (Read-Only)**|**Table 14. F_MODE = 00: 0x00 STATUS: Data Status register (Read-Only)**|**Table 14. F_MODE = 00: 0x00 STATUS: Data Status register (Read-Only)**|**Table 14. F_MODE = 00: 0x00 STATUS: Data Status register (Read-Only)**|**Table 14. F_MODE = 00: 0x00 STATUS: Data Status register (Read-Only)**||_Back to Register Address Map_|_Back to Register Address Map_|
|---|---|---|---|---|---|---|---|
|**Bit 7**|**Bit 6**|**Bit 5**|**Bit 4**|**Bit 3**|**Bit 2**|**Bit 1**|**Bit 0**|
|ZYXOW|ZOW|YOW|XOW|ZYXDR|ZDR|YDR|XDR|



## **Table 15. STATUS register bits** 

|**Bit(s)**|**Field**|**Description**|**Notes**|
|---|---|---|---|
|7|ZYXOW|**X, Y, Z-axis data overwrite**<br>• Set whenever a new acceleration data is produced_before completing the retrieval of the previous set_.<br>This event occurs when the content of at least one acceleration data register (i.e., OUT_X, OUT_Y, OUT_Z) has been<br>overwritten.<br>• Cleared when the high bytes of the acceleration data (OUT_X_MSB, OUT_Y_MSB, OUT_Z_MSB) of all the channels are<br>read.<br>0 No data overwrite has occurred (default)<br>1 Previous X, Y, or Z data was overwritten by new X, Y, or Z data before it (the previous X, Y, or Z data) was read||
|6|ZOW|**Z-axis data overwrite**|**_For # = Z, Y, or X:_**<br>• Set whenever a new acceleration sample_related to_<br>_the #-axis_is generated_before the retrieval of the_<br>_previous sample_. When this occurs, the previous<br>sample is overwritten.<br>• Cleared whenever the OUT#__MSB register is read.<br>0 No data overwrite has occurred (default)<br>1 Previous Z-axis data was overwritten by new_#-_axis<br>data before it (the previous_#_-axis data) was read|
|5|YOW|**Y-axis data overwrite**||
|4|XOW|**X-axis data overwrite**||
|3|ZYXDR|**X, Y, Z-axis new data ready**<br>• Set when a new sample for any of the enabled channels is available.<br>• Cleared when the high-bytes of the acceleration data (OUT_X_MSB, OUT_Y_MSB, OUT_Z_MSB) of all the channels<br>are read.<br>0 No new set of data ready (default)<br>1 A new set of data is ready||
|2|ZDR|**Z-axis new data available**|For_#_= Z, Y, or X<br>• Set whenever a new acceleration sample_related to_<br>_the #-axis_is generated.<br>• Cleared whenever the OUT#__MSB register is read.<br>0 No new_#_-axis data ready (default)<br>1 New_#_-axis data is ready|
|1|YDR|**Y-axis new data available**||
|0|XDR|**X-axis new data available**||



- OUT_X_MSB, OUT_X_LSB, OUT_Y_MSB, OUT_Y_LSB, OUT_Z_MSB, and OUT_Z_LSB are stored in the autoincrementing address range of 0x01 – 0x06, to reduce reading the status followed by 12-bit axis data to 7 bytes.  If the F_READ bit is set (0x2A bit 1), then auto-increment will skip over LSB registers (to access the MSB data only). This will shorten the data acquisition from seven bytes to four bytes. 

**MMA8652FC** 

Sensors Freescale Semiconductor, Inc. 

25 

- The LSB registers can only be read immediately following the read access of the corresponding MSB register. 

   - A random read access to the LSB registers is not possible. 

   - _Reading the MSB register and then the LSB register in sequence_ ensures that both bytes (LSB and MSB) belong to the same data sample, even if a new data sample arrives between reading the MSB and the LSB byte. 

- If the FIFO is enabled (F_MODE > 00), then Register 0x01 points to the FIFO read pointer, while Registers 0x02, 0x03, 0x04, 0x05, 0x06 return a value of zero when read. 

**MMA8652FC** 

Sensors Freescale Semiconductor, Inc. 

26 

## **6.4 FIFO registers** 

The following registers are used to configure the FIFO. For more information about the FIFO, see application note AN4083, _Data Manipulation and Basic Settings for Xtrinsic MMA865xFC Accelerometers._ 

## **6.4.1 0x00: F_STATUS FIFO Status register (F_MODE > 0)** 

When F_MODE > 0, Register 0x00 becomes the FIFO Status Register, which is used to retrieve information about the FIFO. The FIFO Status Register has a flag for the overflow and watermark, and also has a counter (which can be read to obtain the number of samples stored in the buffer when the FIFO is enabled). 

**Table 16. 0x00 F_STATUS: FIFO STATUS register (Read-Only)** 

|**Table 16. 0x00 F_STATUS: FIFO STATUS register (Read-Only)**|**Table 16. 0x00 F_STATUS: FIFO STATUS register (Read-Only)**|**Table 16. 0x00 F_STATUS: FIFO STATUS register (Read-Only)**|**Table 16. 0x00 F_STATUS: FIFO STATUS register (Read-Only)**|**Table 16. 0x00 F_STATUS: FIFO STATUS register (Read-Only)**|**Table 16. 0x00 F_STATUS: FIFO STATUS register (Read-Only)**|||_Back to Register Address Map_|_Back to Register Address Map_|
|---|---|---|---|---|---|---|---|---|---|
|**Bit 7**||**Bit 6**|**Bit 5**|**Bit 4**||**Bit 3**|**Bit 2**|**Bit 1**|**Bit 0**|
|F_OVF||F_WMRK_FLAG|F_CNT5|F_CNT4||F_CNT3|F_CNT2|F_CNT1|F_CNT0|



## **Table 17. FIFO Flag Event** 

|**F_OVF**|**F_WMRK_FLAG**|**Event Description**|
|---|---|---|
|0|—|No FIFO overflow events were detected.|
|1|—|FIFO event was detected; the FIFO has overflowed.|
|—|0|No FIFO watermark events were detected.|
|—|1|FIFO Watermark event was detected, which means that the FIFO sample count is greater than<br>watermark value.<br>If F_MODE = 11, then a Trigger Event was detected.|



The F_OVF and F_WMRK_FLAG flags remain asserted while the event source is still active, but you can clear the FIFO interrupt bit flag in the interrupt source register (INT_SOURCE) by reading the F_STATUS register. In this case, the SRC_FIFO bit in the INT_SOURCE register will be set again when the next data sample enters the FIFO. Therefore, the F_OVF bit flag will remain asserted while the FIFO has overflowed and the F_WMRK_FLAG bit flag will remain asserted while the F_CNT value is equal to or greater than then F_WMRK value. 

- If the FIFO overflow flag is cleared and F_MODE = 11, then the FIFO overflow flag will remain 0 before the trigger event (even if the FIFO is full and overflows). 

- If the FIFO overflow flag is set and F_MODE is = 11, then the FIFO has stopped accepting samples. 

**Table 18. FIFO Sample Count register** 

**Bit(s) Field Description FIFO sample counter** Indicates the number of acceleration samples currently stored in the FIFO buffer. 5–0 F_CNTX[5:0] • Count 00_0000 indicates that the FIFO is empty. (Default value) • 00_0001 to 10_0000 indicates that 1 to 32 samples are stored in the FIFO. ~~i~~ **6.4.2 0x09: F_SETUP FIFO Setup register** 

**Table 19. 0x09 F_SETUP: FIFO Setup register (Read/Write)** 

|**Table 19. 0x09 F_SETUP: FIFO Setup register (Read/Write)**|**Table 19. 0x09 F_SETUP: FIFO Setup register (Read/Write)**|**Table 19. 0x09 F_SETUP: FIFO Setup register (Read/Write)**|**Table 19. 0x09 F_SETUP: FIFO Setup register (Read/Write)**|||_Back to Register Address Map_|_Back to Register Address Map_|
|---|---|---|---|---|---|---|---|
|**Bit 7**|**Bit 6**|**Bit 5**|**Bit 4**|**Bit 3**|**Bit 2**|**Bit 1**|**Bit 0**|
|F_MODE1|F_MODE0|F_WMRK5|F_WMRK4|F_WMRK3|F_WMRK2|F_WMRK1|F_WMRK0|



**MMA8652FC** 

Sensors Freescale Semiconductor, Inc. 

27 

## **Table 20. F_SETUP register** 

|**Bit(s)**|**Field**|**Description**|
|---|---|---|
|7–6|F_MODE[1:0](1)(2)|**FIFO buffer overflow mode**<br>00 FIFO is disabled. (default)<br>01 FIFO contains the most recent samples when overflowed (circular buffer).<br>The oldest sample is discarded and replaced by a new sample.<br>10 FIFO stops accepting new samples when overflowed.<br>11 Trigger mode. The FIFO will be in a circular mode up to the number of samples in the watermark. The<br>FIFO will be in a circular mode until the trigger event occurs, after which the FIFO will continue to accept<br>samples for 32-WMRK samples and then stop receiving further samples. This allows data to be collected<br>both_before and after the trigger event,_and it is definable by the watermark setting.<br>• The FIFO is flushed whenever the FIFO is disabled, during an automatic ODR change (Auto-WAKE/<br>SLEEP), or transitioning from STANDBY mode to ACTIVE mode.<br>• Disabling the FIFO (F_MODE = 00) resets the F_OVF, F_WMRK_FLAG, F_CNT to zero.<br>• A FIFO overflow event (i.e., F_CNT = 32) will assert the F_OVF flag and a FIFO sample count equal to the<br>sample count watermark (i.e., F_WMRK) asserts the F_WMRK_FLAG event flag.|
|5–0|F_WMRK[5:0](2)|**FIFO Event Sample Count Watermark**<br>These bits set the number of FIFO samples required to trigger a watermark interrupt.<br>A FIFO watermark event flag is raised when FIFO sample count F_CNT[5:0]≥F_WMRK[5:0] watermark.<br>• Setting the F_WMRK[5:0] to 00_0000 will disable the FIFO watermark event flag generation.<br>• Also used to set the number of pre-trigger samples in Trigger mode.<br>00_0000<br>(default)|



## 1. Bit field can be written in ACTIVE mode. 

## 2. Bit field can be written in STANDBY mode. 

The FIFO mode can be changed while in the Active mode. The Active mode must first be disabled (F_MODE = 00), before the mode can be switched between Fill mode, Circular mode, and Trigger mode. 

A FIFO sample count exceeding the watermark event does not stop the FIFO from accepting new data. The FIFO update rate is dictated by the selected system ODR. 

- In ACTIVE mode, the ODR is set by the DR bits (CTRL_REG1 register). 

- When Auto-SLEEP is active, the ODR is set by the ASLP_RATE field (CTRL_REG1 register). 

When a byte is read from the FIFO buffer, the oldest sample data in the FIFO buffer is returned (and also deleted from the front of the FIFO buffer), while the FIFO sample count is decremented by one. It is assumed that the host application will use the I[2] C multibyte read transaction to empty the FIFO. 

## **6.4.3 0x0A: TRIG_CFG Trigger Configuration register** 

The Trigger Configuration register configures which interrupt(s) may trigger the FIFO. 

**Table 21. 0x0A: TRIG_CFG Trigger Configuration register (Read/Write)** 

|**Table 21. 0x0A: TRIG_CFG Trigger Configuration register (Read/Write)**|**Table 21. 0x0A: TRIG_CFG Trigger Configuration register (Read/Write)**|**Table 21. 0x0A: TRIG_CFG Trigger Configuration register (Read/Write)**|**Table 21. 0x0A: TRIG_CFG Trigger Configuration register (Read/Write)**|**Table 21. 0x0A: TRIG_CFG Trigger Configuration register (Read/Write)**||_Back to Register Address Map_|_Back to Register Address Map_|
|---|---|---|---|---|---|---|---|
|**Bit 7**|**Bit 6**|**Bit 5**|**Bit 4**|**Bit 3**|**Bit 2**|**Bit 1**|**Bit 0**|
|—|—|Trig_TRANS|Trig_LNDPRT|Trig_PULSE|Trig_FF_MT|—|—|



## **Table 22. Trigger Configuration register** 

|**Bit(s)**|**Field**|**Description**|**Default**<br>**value**|**Notes**|
|---|---|---|---|---|
|5|Trig_TRANS|**Transient Interrupt Trigger**|0|• These trigger bits set are rising-edge sensitive, and are set by a<br>low-to-high state change.<br>• Trigger bits are reset by reading the appropriate source register.<br>1 This function can trigger the FIFO at its (the function’s) interrupt<br>0 This function has not asserted its interrupt.|
|4|Trig_LNDPRT|**Landscape/Portrait**<br>**Orientation Interrupt**<br>**Trigger**|0||
|3|Trig_PULSE|**Pulse Interrupt Trigger**|0||
|2|Trig_FF_MT|**Freefall/Motion Trigger**|0||



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## **6.5 System status and ID registers** 

## **6.5.1 0x0B: SYSMOD System Mode register** 

The System mode register indicates the current device operating mode. Applications using the Auto-SLEEP/WAKE mechanism should use the SYSMOD register to synchronize the application with the device operating mode transitions. The SYSMOD register also indicates: 

- the status of the FIFO gate error 

- and the number of samples since the gate error occurred. 

**Table 23. 0x0B SYSMOD: System Mode register (Read-Only)** _Back to Register Address Map_ **Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0** ~~ee~~ FGERR FGT_4 FGT_3 FGT_2 FGT_1 FGT_0 SYSMOD1 SYSMOD0 

## **Table 24. SYSMOD register** 

|**Bit(s)**|**Field**|**Description**|
|---|---|---|
|7|FGERR|**FIFO Gate Error**<br>0 No FIFO Gate Error detected. (default)<br>1 FIFO Gate Error was detected.<br>Emptying the FIFO buffer clears the FGERR bit in the SYS_MOD register.<br>For more information about configuring the FIFO Gate function, seeSection 6.12.3, “0x2C: CTRL_REG3<br>Interrupt Control register”.|
|6–2|FGT[4:0]|**Number of ODR time units since FGERR was asserted**.<br>Reset when FGERR bit is cleared.<br>0_0000<br>(default)|
|1–0|SYSMOD[1:0]|**System Mode**<br>00 STANDBY mode (default)<br>01 WAKE mode<br>10 SLEEP mode|



## **6.5.2 0x0C: INT_SOURCE System Interrupt Status register** 

In the interrupt source register, the status of the various embedded features can be determined. 

- The bits that are set (logic ‘1’) indicate which function has asserted an interrupt. 

- The bits that are cleared (logic ‘0’) indicate which function has not asserted (or has deasserted) an interrupt. 

INT_SOURCE register bits are set by a low-to-high transition, and are cleared by reading the appropriate interrupt source register. For example, the SRC_DRDY bit is cleared when the ZYXDR bit (STATUS register) is cleared, but the SRC_DRDY bit is not cleared by simply reading the STATUS register (0x00), but is cleared by reading all the X, Y, and Z MSB data. 

**Table 25. 0x0C INT_SOURCE: System Interrupt Status register (Read Only)** _Back to Register Address Map_ **Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0** ~~ee~~ SRC_ASLP SRC_FIFO SRC_TRANS SRC_LNDPRT SRC_PULSE SRC_FF_MT — SRC_DRDY 

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## **Table 26. INT_SOURCE register** 

|**Table 26. INT_SOURCE register**|**Table 26. INT_SOURCE register**|**Table 26. INT_SOURCE register**|
|---|---|---|
|**Bit(s)**|**Field**|**Description**|
|7|SRC_ASLP|**Auto-SLEEP/WAKE interrupt status**bit<br>• **WAKE-to-SLEEP**transition occurs when no interrupt occurs for a time period that exceeds the user-<br>specified limit (ASLP_COUNT). This causes the system to transition to a user-specified low ODR setting.<br>• **SLEEP-to-WAKE**transition occurs when the user-specified interrupt event has woken the system; thus<br>causing the system to transition to a user-specified high ODR setting.<br>• Reading the SYSMOD register clears the SRC_ASLP bit.<br>1 An interrupt event_that can cause a WAKE-to-SLEEP or SLEEP-to-WAKE system mode transition_has<br>occurred.<br>0 No WAKE-to-SLEEP or SLEEP-to-WAKE system mode transition interrupt event has occurred. (default)|
|6|SRC_FIFO|**FIFO interrupt status**bit<br>• FIFO interrupt event generators: FIFO Overflow, or (Watermark: F_CNT = F_WMRK) and the interrupt has<br>been enabled.<br>• SRC_FIFO bit is cleared by reading the F_STATUS register.<br>1 A FIFO interrupt event (such as an overflow event or watermark) has occurred.<br>0 No FIFO interrupt event has occurred. (default)|
|5|SRC_TRANS|**Transient interrupt status**bit<br>• SRC_TRANS bit is asserted whenever the EA bit (TRANS_SRC register) is asserted andthe interrupthas<br>been enabled.<br>• SRC_TRANS bit is cleared by reading the TRANS_SRC register.<br>1 An_acceleration transient value greater than user-specifiedthreshold_ hasoccurred.<br>0 No transient event has occurred. (default)|
|4|SRC_LNDPRT|**Landscape/Portrait Orientation interrupt status**bit<br>• SRC_LNDPRT bit is asserted whenever the NEWLP bit (PL_STATUS register) is asserted and theinterrupt<br>hasbeen enabled.<br>• SRC_LNDPRT bit is cleared by reading the PL_STATUS register.<br>1 An interrupt was generated due to a change in the device orientation status.<br>0 No change in orientation status was detected. (default)|
|3|SRC_PULSE|**Pulse interrupt status**bit<br>• SRC_PULSE bit is asserted whenever the EA bit (PULSE_SRC register) is asserted and the interrupt has<br>been enabled.<br>• SRC_PULSE bit is cleared by reading the PULSE_SRC register.<br>1 An interrupt was generated due to single and/or double pulse event.<br>0 No pulse event was detected. (default)|
|2|SRC_FF_MT|**Freefall/Motion interrupt status**bit<br>• SRC_FF_MT bit is asserted whenever the EA bit (FF_MT_SRC register) is asserted and the FF_MT<br>interrupt has been enabled.<br>• SRC_FF_MT bit is cleared by reading the FF_MT_SRC register.<br>1 The Freefall/Motion function interrupt is active.<br>0 No Freefall or Motion event was detected. (default)|
|1|—|Could be 1 or 0.|
|0|SRC_DRDY|**Data Ready Interrupt bit status**bit<br>• SRC_DRDY bit is asserted when the ZYXOW and/or ZYXDR bit is set and the interrupt has been enabled.<br>• SRC_DRDY bit is cleared by reading the X, Y, and Z data.<br>1 The X, Y, Z data ready interrupt is active (indicating the presence of new data and/or data overrun).<br>0 The X, Y, Z interrupt is not active. (default)|



## **6.5.3 0x0D: WHO_AM_I Device ID register** 

The device identification register identifies the part. The default value is 0x4A (for MMA8652FC). 

This value is programmed by Freescale before the part leaves the factory. For custom alternate values, contact Freescale. 

**Table 27. 0x0D: WHO_AM_I  Device ID register (Read-Only)** 

|**Table 27. 0x0D: WHO_AM_I  Device ID register (Read-Only)**|**Table 27. 0x0D: WHO_AM_I  Device ID register (Read-Only)**|**Table 27. 0x0D: WHO_AM_I  Device ID register (Read-Only)**|**Table 27. 0x0D: WHO_AM_I  Device ID register (Read-Only)**|**Table 27. 0x0D: WHO_AM_I  Device ID register (Read-Only)**|||_Back to Register Address Map_|_Back to Register Address Map_|
|---|---|---|---|---|---|---|---|---|
|**Bit7**|**Bit6**|**Bit5**|**Bit4**||**Bit3**|**Bit2**|**Bit1**|**Bit0**|
|0|1|0|0||1|0|1|0|



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## **6.6 Data configuration registers** 

## **6.6.1 0x0E: XYZ_DATA_CFG register** 

The XYZ_DATA_CFG register sets the dynamic range and sets the high-pass filter for the output data. When the HPF_OUT bit is set, the FIFO and DATA registers both will contain high-pass filtered data. 

**Table 28. 0x0E: XYZ_DATA_CFG  register (Read/Write)** 

|**Table 28. 0x0E: XYZ_DATA_CFG  register (Read/Write)**|**Table 28. 0x0E: XYZ_DATA_CFG  register (Read/Write)**|**Table 28. 0x0E: XYZ_DATA_CFG  register (Read/Write)**|**Table 28. 0x0E: XYZ_DATA_CFG  register (Read/Write)**|||_Back to Register Address Map_|_Back to Register Address Map_|
|---|---|---|---|---|---|---|---|
|**Bit7**|**Bit6**|**Bit5**|**Bit4**|**Bit3**|**Bit2**|**Bit1**|**Bit0**|
|0|0|0|HPF_OUT|0|0|FS1|FS0|



**Table 29. XYZ Data Configuration register** 

|**Table 29. XYZ Data Configuration register**|**Table 29. XYZ Data Configuration register**|**Table 29. XYZ Data Configuration register**|**Table 29. XYZ Data Configuration register**|**Table 29. XYZ Data Configuration register**|
|---|---|---|---|---|
|**Bit(s)**<br>**Field**<br>**Description**<br>7–5<br>0<br>4<br>HPF_OUT<br>**Enable high-pass output data**<br>1 Output data is high-pass filtered.<br>0 Output data is not high-pass filtered. (default)<br>3–2<br>0<br>1–0<br>FS[1:0]<br>**Output buffer data format using full scale**<br>00 ±2 g (default)<br>The default full scale value range is<br>±2 g and the high-pass filter is<br>disabled.<br>~~ee~~|||||
||||**Table 30. Full-Scale Range**||
||||**FS1**<br>**FS0**<br>**Full-Scale Range**<br>0<br>0<br>±2 g<br>0<br>1<br>±4 g<br>1<br>0<br>±8 g<br>1<br>1<br>Reserved<br>~~===~~||



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## **6.6.2 0x0F: HP_FILTER_CUTOFF High-Pass Filter register** 

The High-Pass Filter register sets the high-pass filter cutoff frequency for removal of the offset and slower changing acceleration data. The output of this filter is logged in the data registers (0x01–0x06) when bit 4 (HPF_OUT) of Register 0x0E is set. The filter cutoff options change based on the data rate selected, as shown in Table 33. For more information about the high-pass filter, see application note AN4083, _Data Manipulation and Basic Settings for Xtrinsic MMA865xFC Accelerometers_ . 

**Table 31. 0x0F HP_FILTER_CUTOFF: High-Pass Filter register (Read/Write)** 

**==> picture [507 x 47] intentionally omitted <==**

**----- Start of picture text -----**<br>
|||||||||
|---|---|---|---|---|---|---|---|
|Table 31. 0x0F HP_FILTER_CUTOFF: High-Pass Filter register (Read/Write)|Back to Register Address Map|
|Bit 7|Bit 6|Bit 5|Bit 4|Bit 3|Bit 2|Bit 1|Bit 0|
|0|0|Pulse_HPF_BY|Pulse_LPF_EN|0|0|SEL1|SEL0|
|_—— |}|

**----- End of picture text -----**<br>


**Table 32. High-Pass filter cutoff register** 

**==> picture [365 x 131] intentionally omitted <==**

**----- Start of picture text -----**<br>
|||||
|---|---|---|---|
|Bit(s)|Field|Description|
|7–6|0|
|Bypass High-Pass Filter (HPF) for pulse processing function|
|5|Pulse_HPF_BYP|0|HPF is enabled for pulse processing (default)|
|1|HPF is bypassed for pulse processing|
|Enable Low-Pass Filter (LPF) for pulse processing function|
|4|Pulse_LPF_EN|0|LPF is disabled for pulse processing (default)|
|1|LPF is enabled for pulse processing|
|3–2|0|
|HPF cutoff frequency selection|
|1–0|SEL[1:0]|
|00|Default value, see Table 33|

**----- End of picture text -----**<br>


**Table 33. High-Pass filter cutoff options** 

**==> picture [504 x 300] intentionally omitted <==**

**----- Start of picture text -----**<br>
|||||||||||
|---|---|---|---|---|---|---|---|---|---|
|SEL1|SEL0|800 Hz|400 Hz|200 Hz|100 Hz|50 Hz|12.5 Hz|6.25 Hz|1.56 Hz|
|ee|ns|
|Oversampling Mode = Normal|
|0|0|16 Hz|16 Hz|8 Hz|4 Hz|2 Hz|2 Hz|2 Hz|2 Hz|
|0|1|8 Hz|8 Hz|4 Hz|2 Hz|1 Hz|1 Hz|1 Hz|1 Hz|
|es|
|1|0|4 Hz|4 Hz|2 Hz|1 Hz|0.5 Hz|0.5 Hz|0.5 Hz|0.5 Hz|
|1|1|2 Hz|2 Hz|1 Hz|0.5 Hz|0.25 Hz|0.25 Hz|0.25 Hz|0.25 Hz|
|ee|
|Oversampling Mode = Low Noise Low Power|
|0|0|16 Hz|16 Hz|8 Hz|4 Hz|2 Hz|0.5 Hz|0.5 Hz|0.5 Hz|
|0|1|8 Hz|8 Hz|4 Hz|2 Hz|1 Hz|0.25 Hz|0.25 Hz|0.25 Hz|
|————|
|1|0|4 Hz|4 Hz|2 Hz|1 Hz|0.5 Hz|0.125 Hz|0.125 Hz|0.125 Hz|
|1|1|2 Hz|2 Hz|1 Hz|0.5 Hz|0.25 Hz|0.063 Hz|0.063 Hz|0.063 Hz|
|Se|
|Oversampling Mode = High Resolution|
|0|0|16 Hz|16 Hz|16 Hz|16 Hz|16 Hz|16 Hz|16 Hz|16 Hz|
|0|1|8 Hz|8 Hz|8 Hz|8 Hz|8 Hz|8 Hz|8 Hz|8 Hz|
|==|
|1|0|4 Hz|4 Hz|4 Hz|4 Hz|4 Hz|4 Hz|4 Hz|4 Hz|
|1|1|2 Hz|2 Hz|2 Hz|2 Hz|2 Hz|2 Hz|2 Hz|2 Hz|
|ee|
|Oversampling Mode = Low Power|
|0|0|16 Hz|8 Hz|4 Hz|2 Hz|1 Hz|0.25 Hz|0.25 Hz|0.25 Hz|
|0|1|8 Hz|4 Hz|2 Hz|1 Hz|0.5 Hz|0.125 Hz|0.125 Hz|0.125 Hz|
|ee|
|1|0|4 Hz|2 Hz|1 Hz|0.5 Hz|0.25 Hz|0.063 Hz|0.063 Hz|0.063 Hz|
|1|1|2 Hz|1 Hz|0.5 Hz|0.25 Hz|0.125 Hz|0.031 Hz|0.031 Hz|0.031 Hz|
|ee|

**----- End of picture text -----**<br>


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## **6.7 Portrait/Landscape configuration and status registers** 

For more information about the different user-configurable settings and example code, see application note AN4083, _Data Manipulation and Basic Settings for Xtrinsic MMA865xFC Accelerometers_ . 

## **6.7.1 0x10: PL_STATUS Portrait/Landscape Status register** 

To get updated information on any change in orientation, read the Portrait/Landscape Status register (read Bit 7, or read the other bits for more orientation data). For more about Portrait Up, Portrait Down, Landscape Left, Landscape Right, Back, and Front orientations, see Figure 6. The interrupt is cleared when reading the PL_STATUS register. 

**Table 34. 0x10 PL_STATUS Register (Read-Only)** 

|**Table 34. 0x10 PL_STATUS Register (Read-Only)**|**Table 34. 0x10 PL_STATUS Register (Read-Only)**|**Table 34. 0x10 PL_STATUS Register (Read-Only)**|**Table 34. 0x10 PL_STATUS Register (Read-Only)**|||_Back to Register Address Map_|_Back to Register Address Map_|
|---|---|---|---|---|---|---|---|
|**Bit7**|**Bit6**|**Bit5**|**Bit4**|**Bit3**|**Bit2**|**Bit1**|**Bit0**|
|NEWLP|LO|—|—|—|LAPO[1]|LAPO[0]|BAFRO|



## **Table 35. PL_STATUS register** 

|**Bit(s)**|**Field**|**Description**|
|---|---|---|
|7|NEWLP|**Landscape/Portrait status change flag**<br>• NEWLP is set to 1 after the first orientation detection after a STANDBY-to-ACTIVE transition, and whenever a<br>change in LO, BAFRO, or LAPO occurs.<br>• NEWLP bit is cleared anytime PL_STATUS register is read.<br>0 No change (default)<br>1 BAFRO and/or LAPO and/or Z-Tilt lockout value has changed|
|6|LO|**Z-Tilt Angle Lockout**<br>0 Lockout condition has not been detected (default)<br>1 Z-Tilt lockout trip angle has been exceeded.<br>Lockout has been detected.|
|5–3|—|**Can be 0 or 1.**|
|2–1|LAPO[1:0](1)|**Landscape/Portrait orientation**<br>00 Portrait Up: Equipment standing vertically in the normal orientation (default)<br>01 Portrait Down: Equipment standing vertically in the inverted orientation<br>10 Landscape Right: Equipment is in landscape mode to the right<br>11 Landscape Left: Equipment is in landscape mode to the left.|
|0|BAFRO|**Back or Front orientation**<br>0 Front: Equipment is in the front-facing orientation (default)<br>1 Back: Equipment is in the back-facing orientation|



1. The default power-up state is BAFRO = 0, LAPO = 00, and LO = 0. 

- The orientation mechanism state change is limited to a maximum 1.25 g. The current position is locked if the absolute value of the acceleration experienced on any of the three axes is greater than 1.25 g. 

- LAPO, BAFRO, and LO continue to change when NEWLP is set. 

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## **6.7.2 0x11 Portrait/Landscape Configuration register** 

The Portrait/Landscape Configuration register enables the portrait/landscape function and sets the behavior of the debounce counter. 

**Table 36. 0x11 PL_CFG register (Read/Write)** 

**Table 36. 0x11 PL_CFG register (Read/Write)** _Back to Register Address Map_ **Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0** DBCNTM PL_EN — — — — — — ~~a~~ 

## **Table 37. PL_CFG register** 

|**Bit(s)**|**Field**|**Description**|
|---|---|---|
|7|DBCNTM|**Debounce counter mode selection**<br>0 Decrements debounce whenever the condition of interest is no longer valid.<br>1 Clears the counter whenever the condition of interest is no longer valid. (default)|
|6|PL_EN|**Portrait/Landscape detection enable**<br>0 Portrait/Landscape Detection is disabled. (default)<br>1 Portrait/Landscape Detection is enabled.|
|5–0|—|**Can be 0 or 1.**|



## **6.7.3 0x12 Portrait/Landscape Debounce register** 

The Portrait/Landscape Debounce register sets the debounce count for the orientation state transition. The minimum debounce latency is determined by the data rate (which is set by the product of the selected system ODR and PL_COUNT registers). Any transition from WAKE to SLEEP (or SLEEP to Wake) resets the internal Landscape/Portrait debounce counter. 

## **NOTE** 

The debounce counter weighting (time step) changes, based on the ODR and the Oversampling mode. Table 40 explains the time step value for all sample rates and all 

Oversampling modes. 

|**Table 38. 0x12 PL_COUNT register (Read/Write)**<br>_Back to Register Address Map_<br>**Bit7**<br>**Bit6**<br>**Bit5**<br>**Bit4**<br>**Bit3**<br>**Bit2**<br>**Bit1**<br>**Bit0**<br>DBNCE[7]<br>DBNCE[6]<br>DBNCE[5]<br>DBNCE[4]<br>DBNCE[3]<br>DBNCE[2]<br>DBNCE[1]<br>DBNCE[0]<br>~~a~~|**Table 38. 0x12 PL_COUNT register (Read/Write)**<br>_Back to Register Address Map_<br>**Bit7**<br>**Bit6**<br>**Bit5**<br>**Bit4**<br>**Bit3**<br>**Bit2**<br>**Bit1**<br>**Bit0**<br>DBNCE[7]<br>DBNCE[6]<br>DBNCE[5]<br>DBNCE[4]<br>DBNCE[3]<br>DBNCE[2]<br>DBNCE[1]<br>DBNCE[0]<br>~~a~~|**Table 38. 0x12 PL_COUNT register (Read/Write)**<br>_Back to Register Address Map_<br>**Bit7**<br>**Bit6**<br>**Bit5**<br>**Bit4**<br>**Bit3**<br>**Bit2**<br>**Bit1**<br>**Bit0**<br>DBNCE[7]<br>DBNCE[6]<br>DBNCE[5]<br>DBNCE[4]<br>DBNCE[3]<br>DBNCE[2]<br>DBNCE[1]<br>DBNCE[0]<br>~~a~~|**Table 38. 0x12 PL_COUNT register (Read/Write)**<br>_Back to Register Address Map_<br>**Bit7**<br>**Bit6**<br>**Bit5**<br>**Bit4**<br>**Bit3**<br>**Bit2**<br>**Bit1**<br>**Bit0**<br>DBNCE[7]<br>DBNCE[6]<br>DBNCE[5]<br>DBNCE[4]<br>DBNCE[3]<br>DBNCE[2]<br>DBNCE[1]<br>DBNCE[0]<br>~~a~~|**Table 38. 0x12 PL_COUNT register (Read/Write)**<br>_Back to Register Address Map_<br>**Bit7**<br>**Bit6**<br>**Bit5**<br>**Bit4**<br>**Bit3**<br>**Bit2**<br>**Bit1**<br>**Bit0**<br>DBNCE[7]<br>DBNCE[6]<br>DBNCE[5]<br>DBNCE[4]<br>DBNCE[3]<br>DBNCE[2]<br>DBNCE[1]<br>DBNCE[0]<br>~~a~~|**Table 38. 0x12 PL_COUNT register (Read/Write)**<br>_Back to Register Address Map_<br>**Bit7**<br>**Bit6**<br>**Bit5**<br>**Bit4**<br>**Bit3**<br>**Bit2**<br>**Bit1**<br>**Bit0**<br>DBNCE[7]<br>DBNCE[6]<br>DBNCE[5]<br>DBNCE[4]<br>DBNCE[3]<br>DBNCE[2]<br>DBNCE[1]<br>DBNCE[0]<br>~~a~~|**Table 38. 0x12 PL_COUNT register (Read/Write)**<br>_Back to Register Address Map_<br>**Bit7**<br>**Bit6**<br>**Bit5**<br>**Bit4**<br>**Bit3**<br>**Bit2**<br>**Bit1**<br>**Bit0**<br>DBNCE[7]<br>DBNCE[6]<br>DBNCE[5]<br>DBNCE[4]<br>DBNCE[3]<br>DBNCE[2]<br>DBNCE[1]<br>DBNCE[0]<br>~~a~~|**Table 38. 0x12 PL_COUNT register (Read/Write)**<br>_Back to Register Address Map_<br>**Bit7**<br>**Bit6**<br>**Bit5**<br>**Bit4**<br>**Bit3**<br>**Bit2**<br>**Bit1**<br>**Bit0**<br>DBNCE[7]<br>DBNCE[6]<br>DBNCE[5]<br>DBNCE[4]<br>DBNCE[3]<br>DBNCE[2]<br>DBNCE[1]<br>DBNCE[0]<br>~~a~~|**Table 38. 0x12 PL_COUNT register (Read/Write)**<br>_Back to Register Address Map_<br>**Bit7**<br>**Bit6**<br>**Bit5**<br>**Bit4**<br>**Bit3**<br>**Bit2**<br>**Bit1**<br>**Bit0**<br>DBNCE[7]<br>DBNCE[6]<br>DBNCE[5]<br>DBNCE[4]<br>DBNCE[3]<br>DBNCE[2]<br>DBNCE[1]<br>DBNCE[0]<br>~~a~~|**Table 38. 0x12 PL_COUNT register (Read/Write)**<br>_Back to Register Address Map_<br>**Bit7**<br>**Bit6**<br>**Bit5**<br>**Bit4**<br>**Bit3**<br>**Bit2**<br>**Bit1**<br>**Bit0**<br>DBNCE[7]<br>DBNCE[6]<br>DBNCE[5]<br>DBNCE[4]<br>DBNCE[3]<br>DBNCE[2]<br>DBNCE[1]<br>DBNCE[0]<br>~~a~~|**Table 38. 0x12 PL_COUNT register (Read/Write)**<br>_Back to Register Address Map_<br>**Bit7**<br>**Bit6**<br>**Bit5**<br>**Bit4**<br>**Bit3**<br>**Bit2**<br>**Bit1**<br>**Bit0**<br>DBNCE[7]<br>DBNCE[6]<br>DBNCE[5]<br>DBNCE[4]<br>DBNCE[3]<br>DBNCE[2]<br>DBNCE[1]<br>DBNCE[0]<br>~~a~~|**Table 38. 0x12 PL_COUNT register (Read/Write)**<br>_Back to Register Address Map_<br>**Bit7**<br>**Bit6**<br>**Bit5**<br>**Bit4**<br>**Bit3**<br>**Bit2**<br>**Bit1**<br>**Bit0**<br>DBNCE[7]<br>DBNCE[6]<br>DBNCE[5]<br>DBNCE[4]<br>DBNCE[3]<br>DBNCE[2]<br>DBNCE[1]<br>DBNCE[0]<br>~~a~~|**Table 38. 0x12 PL_COUNT register (Read/Write)**<br>_Back to Register Address Map_<br>**Bit7**<br>**Bit6**<br>**Bit5**<br>**Bit4**<br>**Bit3**<br>**Bit2**<br>**Bit1**<br>**Bit0**<br>DBNCE[7]<br>DBNCE[6]<br>DBNCE[5]<br>DBNCE[4]<br>DBNCE[3]<br>DBNCE[2]<br>DBNCE[1]<br>DBNCE[0]<br>~~a~~|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Table 39. PL_COUNT register**|||||||||||||
|**Bit(s)**<br>**Field**<br>**Description**<br>7–0<br>DBCNE[7:0]<br>**Debounce Count value**<br>0000_0000 (default)<br>~~i~~|||||||||||||
|**Table 40. PL_COUNT relationship with the ODR**||**Table 40. PL_COUNT relationship with the ODR**||**Table 40. PL_COUNT relationship with the ODR**|||||||||
||**ODR**||**Max Time Range (s)**|||||**Time Step (ms)**|||||
||**(Hz)**||**Normal**<br>**LPLN**<br>**HighRes**||**LP**|**Normal**||**LPLN**||**HighRes**|**LP**||
||800||0.319<br>0.319<br>0.319||0.319|1.25||1.25||1.25|1.25||
||400||0.638<br>0.638<br>0.638||0.638|2.5||2.5||2.5|2.5||
||200||1.28<br>1.28<br>0.638||1.28|5||5||2.5|5||
||100||2.55<br>2.55<br>0.638||2.55|10||10||2.5|10||
||50||5.1<br>5.1<br>0.638||5.1|20||20||2.5|20||
||12.5||5.1<br>20.4<br>0.638||20.4|20||80||2.5|80||
||6.25||5.1<br>20.4<br>0.638||40.8|20||80||2.5|160||
||1.56||5.1<br>20.4<br>0.638||40.8|20||80||2.5|160||



**MMA8652FC** 

Sensors Freescale Semiconductor, Inc. 

34 

## **6.7.4 0x13: PL_BF_ZCOMP Back/Front and Z Compensation register** 

The Z-Lock angle compensation bits allows you to adjust the Z-lockout region from 14° up to 43°.  On power-up, the default Z-lockout angle is set to the default value of 29°. The back-to-front trip angle is set by default to ±75°, and this angle can be adjusted from a range of 65° to 80° (with 5° step increments). 

**Table 41. 0x13: PL_BF_ZCOMP register (Read/Write)** 

**==> picture [485 x 37] intentionally omitted <==**

**----- Start of picture text -----**<br>
|||||||||
|---|---|---|---|---|---|---|---|
|Table 41. 0x13: PL_BF_ZCOMP register (Read/Write)|Back to Register Address Map|
|Bit 7|Bit 6|Bit 5|Bit 4|Bit 3|Bit 2|Bit 1|Bit 0|
|—|—|—|
|BKFR[1]|BKFR[0]|ZLOCK[2]|ZLOCK[1]|ZLOCK[0]|

**----- End of picture text -----**<br>


**Table 42. PL_BF_ZCOMP register** 

**==> picture [461 x 394] intentionally omitted <==**

**----- Start of picture text -----**<br>
Bit(s) Field Description Notes<br>Back/Front trip angle threshold [(1)]<br>7–6 BKFR[7:6] • Step size = 5° 01   ≥  ±75° (default)<br>• Range = ±(65° to 80°)<br>5–3 — Can be 0 or 1.<br>Z-lock angle threshold [(1)]<br>2–0 ZLOCK[2:0] • Step size is 4° 100  ≥  29° (default)<br>• Range is from 14° to 43° 111  ≥  43° (maximum)<br>——<br>1. All angles are accurate to ±2°.<br>Table 43. Z-lock threshold angles<br>Z-lock Value Threshold Angle<br>0x00 14°<br>0x01 18°<br>0x02 21°<br>0x03 25°<br>0x04 29°<br>0x05 33°<br>0x06 37°<br>0x07 42°<br>7<br>Table 44. Back/Front orientation definitions<br>BKFR Back/Front Transition Front/Back Transition<br>00 Z < 80° or Z > 280° Z > 100° and Z < 260°<br>01 Z < 75° or Z > 285° Z > 105° and Z < 255°<br>10 Z < 70° or Z > 290° Z > 110° and Z < 250°<br>—— 11 Z < 65° or Z > 295° Z > 115° and Z < 245°<br>6.7.5 0x14: P_L_THS_REG Portrait/Landscape Threshold and Hysteresis register<br>**----- End of picture text -----**<br>


This register represents the Portrait-to-Landscape trip threshold register used to set the trip angle for transitioning from Portrait to Landscape mode and from Landscape to Portrait mode. This register includes a value for the hysteresis. 

**Table 45. 0x14: P_L_THS_REG register (Read/Write)** 

_Back to Register Address Map_ 

**==> picture [477 x 20] intentionally omitted <==**

**----- Start of picture text -----**<br>
|||||||||
|---|---|---|---|---|---|---|---|
|Bit 7|Bit 6|Bit 5|Bit 4|Bit 3|Bit 2|Bit 1|Bit 0|
|P_L_THS[4]|P_L_THS[3]|P_L_THS[2]|P_L_THS[1]|P_L_THS[0]|HYS[2]|HYS[1]|HYS[0]|

**----- End of picture text -----**<br>


**Table 46. P_L_THS_REG register** 

**Bit(s) Field Description Notes** 

**MMA8652FC** 

Sensors Freescale Semiconductor, Inc. 

35 

## **Table 46. P_L_THS_REG register (Continued)** 

|7–3|P_L_THS[7:3]|**Portrait/Landscape trip threshold angle**(from 15° to 75°)<br>SeeTable 47, “Threshold angle thresholds look-up table,” on<br>page 36for the values with the corresponding approximate threshold<br>angle.<br>1_0000<br>(45°) (default)|For the landscape/portrait detection to work<br>correctly,<br>THS + HYS > 0<br>and THS + HYS < 32.<br>All angles are accurate to ±2°.|
|---|---|---|---|
|2–0|HYS[2:0]|**Hysteresis value**<br>This angle is added to the threshold angle, for a smoother transition<br>from portrait to landscape and landscape to portrait.<br>This angle ranges from 0° to ±24°.<br>100 (±14°) (default)||



Table 47, “Threshold angle thresholds look-up table,” on page 36 is a look-up table to set the threshold. This is the center value that will be set for the trip point from portrait to landscape and from landscape to portrait. The default trip angle is 45° (0x10). The default hysteresis is ±14°. 

**Table 47. Threshold angle thresholds look-up table** 

|**Threshold Angle**<br>**(approximately)**<br>~~=~~|**5-bit Register**<br>**Value**<br>~~=~~|
|---|---|
|15°<br>~~=~~|0x07<br>~~=~~|
|20°<br>~~=~~|0x09<br>~~=~~|
|30°<br>~~=~~|0x0C<br>~~=~~|
|35°<br>~~=~~|0x0D<br>~~=~~|
|40°<br>~~=~~|0x0F<br>~~=~~|
|45°<br>~~=~~|0x10<br>~~=~~|
|55°<br>~~=~~|0x13<br>~~=~~|
|60°<br>~~=~~|0x14<br>~~=~~|
|70°<br>~~=~~|0x17<br>~~=~~|
|75°<br>~~=~~|0x19<br>~~=~~|



**Table 48. Trip angles with hysteresis for 45° angle** 

**==> picture [324 x 138] intentionally omitted <==**

**----- Start of picture text -----**<br>
Hysteresis Hysteresis Landscape-to-Portrait Portrait-to-Landscape<br>Register Value ± Angle Range Trip Angle Trip Angle<br>0 ±0 45° 45°<br>1 ±4 49° 41°<br>2 ±7 52° 38°<br>3 ±11 56° 34°<br>4 ±14 59° 31°<br>5 ±17 62° 28°<br>6 ±21 66° 24°<br>7 ±24 69° 21°<br>a7<br>**----- End of picture text -----**<br>


**MMA8652FC** 

Sensors Freescale Semiconductor, Inc. 

36 

## **6.8 Freefall/Motion configuration and status registers** 

The freefall/motion function can be configured in either Freefall or Motion Detection mode via the **OAE** configuration bit (0x15: FF_MTG_CFG, bit 6). The freefall/motion detection block can be disabled by setting all three bits (ZEFE, YEFE, XEFE) to zero. 

Depending on the register bits **ELE** (0x15: FF_MTG_CFG, bit 7) and **OAE** (0x15: FF_MTG_CFG, bit 6), each of the freefall and motion detection block can operate in four different modes. 

## **6.8.1 Motion and freefall modes** 

## **6.8.1.1 Mode 1: Freefall detection with ELE = 0, OAE = 0** 

In this mode, the **EA** bit (0x16: FF_MTG_CFG, bit 7) indicates a freefall event after the debounce counter is complete. The ZEFE, YEFE, and XEFE control bits determine which axes are considered for the freefall detection. Once the EA bit is set, and DBCNTM = 0, the EA bit can get cleared only after the delay specified by FF_MT_COUNT. This is because the counter is in decrement mode. If DBCNTM = 1, then the EA bit is cleared as soon as the freefall condition disappears, and will not be set again before the delay specified by FF_MT_COUNT has passed. Reading the FF_MT_SRC register does not clear the EA bit. 

The event flags (0x16) ZHE, ZHP, YHE, YHP, XHE, and XHP reflect the motion detection status (i.e., a high g event) without any debouncing, provided that the corresponding bits ZEFE, YEFE, and/or XEFE are set. 

## **6.8.1.2 Mode 2: Freefall detection with ELE = 1, OAE = 0** 

In this mode, the **EA** event bit indicates a freefall event after the debounce counter. Once the debounce counter reaches the time value for the set threshold, the EA bit is set, and the EA bit remains set until the FF_MT_SRC register is read. When the FF_MT_SRC register is read, the EA bit and the debounce counter are cleared, and a new event can only be generated after the delay specified by FF_MT_CNT. The ZEFE, YEFE, and XEFE control bits determine which axes are considered for the freefall detection. While EA = 0, the event flags ZHE, ZHP, YHE, YHP, XHE, and XHP reflect the motion detection status (i.e., a high g event) without any debouncing, provided that the corresponding bits ZEFE, YEFE, and/or XEFE are set. 

The event flags ZHE, ZHP, YHE, YHP, XHE, and XHP are latched when the EA event bit is set. The event flags ZHE, ZHP, YHE, YHP, XHE, and XHP will start changing only after the FF_MT_SRC register has been read. 

## **6.8.1.3 Mode 3: Motion detection with ELE = 0, OAE = 1** 

In this mode, the EA bit indicates a motion event after the debounce counter time is reached. The ZEFE, YEFE, and XEFE control bits determine which axes are taken into consideration for motion detection. Once the EA bit is set and if DBCNTM = 0, the EA bit can get cleared only after the delay specified by FF_MT_COUNT. If DBCNTM = 1, then the EA bit is cleared as soon as the motion high g condition disappears. 

The event flags ZHE, ZHP, YHE, YHP, XHE, and XHP reflect the motion detection status (i.e., a high g event) without any debouncing, provided that the corresponding bits ZEFE, YEFE, and/or XEFE are set. Reading the FF_MT_SRC does not clear any flags, nor is the debounce counter reset. 

## **6.8.1.4 Mode 4: Motion detection with ELE = 1, OAE = 1** 

In this mode, the EA bit indicates a motion event after debouncing. The ZEFE, YEFE, and XEFE control bits determine which axes are taken into consideration for motion detection. Once the debounce counter reaches the threshold, the EA bit is set, and the EA bit remains set until the FF_MT_SRC register is read. When the FF_MT_SRC register is read, all register bits are cleared and the debounce counter are cleared and a new event can only be generated after the delay specified by FF_MT_CNT. 

While the bit EA is zero, the event flags ZHE, ZHP, YHE, YHP, XHE, and XHP reflect the motion detection status (i.e., a high g event) without any debouncing, provided that the corresponding bits ZEFE, YEFE, and/or XEFE are set. When the EA bit is set, these bits (ZHE, ZHP, YHE, YHP, XHE, XHP) keep their current value until the FF_MT_SRC register is read. 

**MMA8652FC** 

Sensors Freescale Semiconductor, Inc. 

37 

## **6.8.2 0x15: FF_MT_CFG Freefall/Motion Configuration register** 

This is the Freefall/Motion configuration register for setting up the conditions of the freefall or motion function. 

## **Table 49. 0x15 FF_MT_CFG register (Read/Write)** 

_Back to Register Address Map_ 

|**Table 49. 0x15 FF_MT_CFG register (Read/Write)**<br>_Back to Register Address Map_<br>**Bit7**<br>**Bit6**<br>**Bit5**<br>**Bit4**<br>**Bit3**<br>**Bit2**<br>**Bit1**<br>**Bit0**<br>ELE<br>OAE<br>ZEFE<br>YEFE<br>XEFE<br>—<br>—<br>—<br>~~ES~~<br>~~————————~~|
|---|



## **Table 50. FF_MT_CFG register** 

|**Bit(s)**|**Field**|**Description**|
|---|---|---|
|7|ELE|**Event Latch Enable**: Event flags are latched into FF_MT_SRC register.<br>ELE denotes whether the enabled event flag will to be latched into the FF_MT_SRC register or whether the event flag<br>status in the FF_MT_SRC will indicate the real-time status of the event.<br>• If ELE bit is set to 1, then the event flags are frozen when the EA bit gets set, and the event flags are cleared by<br>reading the FF_MT_SRC source register.<br>• Reading the FF_MT_SRC register clears the event flag EA and all FF_MT_SRC bits.<br>0 Event flag latch disabled (default)<br>1 Event flag latch enabled|
|6|OAE|**Motion detect / Freefall detect flag selection**<br>Selects between Motion (logical OR combination) and Freefall (logical AND combination) detection.<br>0 Freefall flag (Logical AND combination) (default)<br>1 Motion flag (Logical OR combination)|
|5|ZEFE|**Event flag enable on Z**<br>ZHFE enables the detection of a motion or freefall event when the measured acceleration data on Z channel is beyond<br>the threshold set in FF_MT_THS register.<br>• If ELE bit (FF_MT_CFG register) is set to 1, then new event flags are blocked from updating the FF_MT_SRC<br>register.<br>0 Event detection disabled (default)<br>1 Raise event flag on measured acceleration value beyond preset threshold|
|4|YEFE|**Event flag enable on Y event**<br>YEFE enables the detection of a motion or freefall event when the measured acceleration data on Y channel is beyond<br>the threshold set in FF_MT_THS register.<br>• If ELE bit (FF_MT_CFG register) is set to 1, then new event flags are blocked from updating the FF_MT_SRC<br>register.<br>0 Event detection disabled (default)<br>1 Raise event flag on measured acceleration value beyond preset threshold|
|3|XEFE|**Event flag enable on X event**<br>XEFE enables the detection of a motion or freefall event when the measured acceleration data on X channel is beyond<br>the threshold set in FF_MT_THS register.<br>• If ELE bit (FF_MT_CFG register) is set to 1, then new event flags are blocked from updating the FF_MT_SRC<br>register.<br>0 Event detection disabled (default)<br>1 Raise event flag on measured acceleration value beyond preset threshold|
|2–0|—||



**Figure 14. FF_MT_CFG high-g and low-g threshold** 

**MMA8652FC** 

Sensors Freescale Semiconductor, Inc. 

38 

## **6.8.3 0x16: FF_MT_SRC Freefall/Motion Source register** 

The Freefall/Motion Source register keeps track of the acceleration event that is triggering (or has triggered, if ELE bit in FF_MT_CFG register is set to 1) the event flag. In particular, EA is set to 1 when the logical combination of acceleration events flags specified in FF_MT_CFG register is true. This EA bit is used _in combination with the values in INT_EN_FF_MT and INT_CFG_FF_MT register bits_ to generate the freefall/motion interrupts. 

- An X,Y, or Z motion is true when the acceleration value of the X or Y or Z channel is higher than the preset threshold value defined in the FF_MT_THS register. 

- An X, Y, and Z low event is true when the acceleration value of the X and Y and Z channel is lower than or equal to the preset threshold value defined in the FF_MT_THS register. 

**Table 51. 0x16: FF_MT_SRC Freefall/Motion Source register (Read-Only)** 

|**Table 51. 0x16: FF_MT_SRC Freefall/Motion Source register (Read-Only)**|**Table 51. 0x16: FF_MT_SRC Freefall/Motion Source register (Read-Only)**|**Table 51. 0x16: FF_MT_SRC Freefall/Motion Source register (Read-Only)**|**Table 51. 0x16: FF_MT_SRC Freefall/Motion Source register (Read-Only)**|**Table 51. 0x16: FF_MT_SRC Freefall/Motion Source register (Read-Only)**||_Back to Register Address Map_|_Back to Register Address Map_|
|---|---|---|---|---|---|---|---|
|**Bit7**|**Bit6**|**Bit5**|**Bit4**|**Bit3**|**Bit2**|**Bit1**|**Bit0**|
|EA|—|ZHE|ZHP|YHE|YHP|XHE|XHP|



## **Table 52.  Freefall/Motion Source register** 

|**Bit(s)**|**Field**|**Description**|
|---|---|---|
|7|EA|**Event Active flag**<br>0 No event flag has been asserted (default)<br>1 One or more event flags has been asserted.<br>See the description of the OAE bit to determine the effect of the 3-axis event flags on the EA bit.|
|6|—||
|5|ZHE|**Z-Motion flag**<br>ZHE bit always reads zero if the ZEFE control bit is set to zero.<br>0 No Z motion event detected (default)<br>1 Z motion has been detected|
|4|ZHP|**Z-Motion Polarity Flag**<br>ZHP bit always reads zero if the ZEFE control bit is set to zero.<br>0 Z event was positive g (default)<br>1 Z event was negative g|
|3|YHE|**Y-Motion Flag**<br>YHE bit always reads zero if the YEFE control bit is set to zero.<br>0 No Y motion event detected (default)<br>1 Y motion has been detected|
|2|YHP|**Y-Motion Polarity Flag**<br>YHP bit always reads zero if the YEFE control bit is set to zero.<br>0 Y event detected was positive g (default)<br>1 Y event was negative g|
|1|XHE|**X-Motion Flag**<br>XHE bit always reads zero if the XEFE control bit is set to zero.<br>0 No X motion event detected (default)<br>1 X motion has been detected|
|0|XHP|**X-Motion Polarity Flag**<br>XHP bit always reads zero if the XEFE control bit is set to zero.<br>0 X event was positive g (default)<br>1 X event was negative g|



**MMA8652FC** 

Sensors Freescale Semiconductor, Inc. 

39 

## **6.8.4 0x17: FF_MT_THS Freefall and Motion Threshold register** 

FF_MT_THS is the threshold register used to detect freefall motion events. 

- The unsigned 7-bit FF_MT_THS threshold register holds the threshold for the freefall detection **where the magnitude of the X and Y and Z acceleration values is lower or equal than the threshold value** . 

- Conversely, the FF_MT_THS also holds the threshold for the motion detection **where the magnitude of the X or Y or Z acceleration value is higher than the threshold value** . 

**Table 53. 0x17 FF_MT_THS register (Read/Write)** 

_Back to Register Address Map_ 

**==> picture [484 x 41] intentionally omitted <==**

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|||||||||
|---|---|---|---|---|---|---|---|
|Bit 7|Bit 6|Bit 5|Bit 4|Bit 3|Bit 2|Bit 1|Bit 0|
|DBCNTM|THS6|THS5|THS4|THS3|THS2|THS1|THS0|
|es|es a|a|

**----- End of picture text -----**<br>


## **Table 54. FF_MT_THS register** 

**==> picture [320 x 69] intentionally omitted <==**

**----- Start of picture text -----**<br>
|||||
|---|---|---|---|
|Bit(s)|Field|Description|
|Debounce counter mode selection|
|7|DBCNTM|0|Increments or decrements debounce (default)|
|1|Increments or clears counter.|
|Freefall /Motion Threshold|
|6–0|THS[6:0]|
|000_0000|(default)|

**----- End of picture text -----**<br>


The threshold resolution is 0.063 g/LSB and the threshold register has a range of 0 to 127 counts. The maximum range is to ±8 g. Note that even when the full scale value is set to ±2 g or ±4 g, the motion still detects up to ±8 g. 

The DBCNTM bit configures the way in which the debounce counter is reset when the inertial event of interest is momentarily not true. 

- **When** the **DBCNTM bit is 1** , the debounce counter is cleared to 0 whenever the inertial event of interest is no longer true as shown in Figure 15, (b). 

- **While the DBCNTM bit is set to 0** , the debounce counter is decremented by 1 whenever the inertial event of interest is no longer true (Figure 15, (c)) until the debounce counter reaches 0 or until the inertial event of interest becomes active. 

Decrementing the debounce counter acts as a median enabling the system to filter out irregular spurious events (which might impede the detection of inertial events). 

## **6.8.5 0x18 FF_MT_COUNT Debounce register** 

The Debounce register sets the number of debounce sample counts for the event trigger. 

## **Table 55. 0x18 FF_MT_COUNT register (Read/Write)** 

_Back to Register Address Map_ 

**==> picture [504 x 139] intentionally omitted <==**

**----- Start of picture text -----**<br>
|||||||||
|---|---|---|---|---|---|---|---|
|Bit 7|Bit 6|Bit 5|Bit 4|Bit 3|Bit 2|Bit 1|Bit 0|
|D7|D6|D5|D4|D3|D2|D1|D0|
|SS|
|Table 56. FF_MT_COUNT register|
|Bit(s)|Field|Description|
|Count value|
|7–0|D[7:0]|
|0000_0000|(default)|
|a|
|The Debounce register sets the minimum number of debounce sample counts that continuously match the detection condition|
|selected by you for the freefall/motion event.|

**----- End of picture text -----**<br>


When the internal debounce counter reaches the FF_MT_COUNT value, a freefall/motion event flag is set. The debounce counter will never increase beyond the FF_MT_COUNT value. The time step used for the debounce sample count depends on the ODR chosen and the Oversampling mode, as shown in Table 57. 

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**Table 57. FF_MT_COUNT relationship with the ODR** 

|**ODR**<br>**(Hz)**<br>~~TT~~|**Max Time Range (s)**<br>~~|~~<br>~~TT~~|**Max Time Range (s)**<br>~~|~~<br>~~TT~~|**Max Time Range (s)**<br>~~|~~<br>~~TT~~|**Max Time Range (s)**<br>~~|~~<br>~~TT~~|**Time Step (ms)**<br>~~|~~<br>~~TT~~|**Time Step (ms)**<br>~~|~~<br>~~TT~~|**Time Step (ms)**<br>~~|~~<br>~~TT~~|**Time Step (ms)**<br>~~|~~<br>~~TT~~|
|---|---|---|---|---|---|---|---|---|
||**Normal**<br>~~TT~~|**LPLN**<br>~~TT~~|**HighRes**<br>~~TT~~|**LP**<br>~~TT~~<br>~~|~~|**Normal**<br>~~TT~~<br>~~|~~|**LPLN**<br>~~TT~~|**HighRes**<br>~~TT~~|**LP**<br>~~TT~~|
|800<br>~~es~~|0.319<br>~~es~~|0.319<br>~~es~~|0.319<br>~~es~~|0.319<br>~~es~~<br>~~|~~<br>~~|~~|1.25<br>~~es~~<br>~~|~~<br>~~|~~|1.25<br>~~es~~<br>~~|~~|1.25<br>~~es~~|1.25<br>~~es~~|
|400<br>~~Re~~<br>~~a~~|0.638<br>~~Re~~|0.638<br>~~Re~~|0.638<br>~~Re~~|0.638<br>~~|~~<br>~~Re~~<br>~~|~~<br>~~|e~~|2.5<br>~~|~~<br>~~Re~~<br>~~|~~<br>~~|e~~|2.5<br>~~Re~~<br>~~|~~|2.5<br>~~Re~~|2.5<br>~~Re~~|
|200<br>~~Re~~<br>~~ee~~<br>~~a~~|1.28<br>~~Re~~<br>~~ee~~|1.28<br>~~Re~~<br>~~ee~~|0.638<br>~~Re~~<br>~~ee~~|1.28<br>~~Re~~<br>~~|~~<br>~~ee~~<br>~~|e~~|5<br>~~Re~~<br>~~|~~<br>~~ee~~<br>~~|e~~|5<br>~~Re~~<br>~~|~~<br>~~ee~~|2.5<br>~~Re~~<br>~~ee~~|5<br>~~Re~~<br>~~ee~~|
|100<br>~~a~~|2.55<br>~~es~~|2.55<br>~~es~~|0.638<br>~~es~~|2.55<br>~~|e~~<br>~~|e~~<br>~~|~~|10<br>~~|e~~<br>~~|e~~<br>~~|~~|10<br>~~|~~|2.5|10|
|50<br>~~Re~~<br>~~a~~|5.1<br>~~Re~~<br>|5.1<br>~~Re~~<br>|0.638<br>~~Re~~<br>|5.1<br>~~Re~~<br>~~|~~<br>~~|e~~<br>|20<br>~~Re~~<br>~~|~~<br>~~|e~~<br>|20<br>~~Re~~<br>~~|~~<br>|2.5<br>~~Re~~<br>|20<br>~~Re~~<br>|
|12.5<br>~~Re~~<br>~~ee~~<br>~~a~~|5.1<br>~~Re~~<br>~~ee~~<br>|20.4<br>~~Re~~<br>~~ee~~<br>|0.638<br>~~Re~~<br>~~ee~~<br>|20.4<br>~~Re~~<br>~~|~~<br>~~ee~~<br>~~|e~~<br>|20<br>~~Re~~<br>~~|~~<br>~~ee~~<br>~~|e~~<br>|80<br>~~Re~~<br>~~|~~<br>~~ee~~<br>|2.5<br>~~Re~~<br>~~ee~~<br>|80<br>~~Re~~<br>~~ee~~<br>|
|6.25<br>~~a se~~<br>~~Rs~~|5.1<br>~~se~~<br>~~Rs~~|20.4<br>~~se~~<br>~~|~~|0.638<br>~~se~~<br>~~|~~|40.8<br>~~|e~~<br>~~se~~<br>~~|~~|20<br>~~|e~~<br>~~se~~<br>~~|~~|80<br>~~se~~<br>~~|~~|2.5<br>~~se~~<br>~~|~~|160<br>~~se~~<br>~~|~~|
|1.56<br>~~Rs~~|5.1<br>~~Rs~~|20.4<br>~~|~~|0.638<br>~~|~~|40.8<br>~~|~~|20<br>~~|~~|80<br>~~|~~|2.5<br>~~|~~|160<br>~~|~~|



**==> picture [380 x 362] intentionally omitted <==**

**----- Start of picture text -----**<br>
High g Event on<br>all 3-axis<br>(Motion Detect) i<br>Count Threshold<br>(a)<br>FF<br>Counter<br>Value<br>FFEA<br>High g Event on<br>all 3-axis<br>(Motion Detect)<br>DBCNTM = 1<br>Count Threshold<br>Debounce (b)<br>Counter<br>Value<br>EA<br>High g Event on<br>all 3-axis<br>(Motion Detect)<br>DBCNTM = 0<br>Count Threshold<br>Debounce<br>(c)<br>Counter<br>Value<br>EA<br>**----- End of picture text -----**<br>


**Figure 15. DBCNTM bit function** 

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## **6.9 Transient configuration and status registers** 

For more information about the uses of the transient function, see application note AN4083, _Data Manipulation and Basic Settings for Xtrinsic MMA865xFC Accelerometers_ . This Transient (HPF) acceleration detection function is similar to the motion detection function, except that high-pass filtered data is compared. 

There is an option to disable the high-pass filter through the function. In this case, the behavior is the same as the motion detection. This allows for the device to have two motion detection functions. 

## **6.9.1 0x1D: Transient_CFG register** 

The transient detection mechanism can be configured to raise an interrupt when the magnitude of the high-pass filtered acceleration threshold is exceeded. The TRANSIENT_CFG register is used to enable the transient interrupt generation mechanism for the three axes (X, Y, Z) of acceleration. There is also an option to bypass the high-pass filter. When the high-pass filter is bypassed, the function behaves similar to the motion detection. 

**Table 58. 0x1D TRANSIENT_CFG register (Read/Write)** 

|**Table 58. 0x1D TRANSIENT_CFG register (Read/Write)**|**Table 58. 0x1D TRANSIENT_CFG register (Read/Write)**|**Table 58. 0x1D TRANSIENT_CFG register (Read/Write)**|**Table 58. 0x1D TRANSIENT_CFG register (Read/Write)**|||_Back to Register Address Map_|_Back to Register Address Map_|
|---|---|---|---|---|---|---|---|
|**Bit7**|**Bit6**|**Bit5**|**Bit4**|**Bit3**|**Bit2**|**Bit1**|**Bit0**|
|—|—|—|ELE|ZTEFE|YTEFE|XTEFE|HPF_BYP|



## **Table 59. TRANSIENT_CFG register** 

|**Bit(s)**|**Field**|**Description**|**Notes**|
|---|---|---|---|
|7–5|—|Could be 0 or 1.||
|4|ELE|**Transient event flags are latched into the TRANSIENT_SRC**<br>**register**.<br>Reading of the TRANSIENT_SRC register clears the event flag.<br>0 Event flag latch disabled (default)<br>1 Event flag latch enabled||
|3|ZTEFE|**Event flag enable for Z-transient acceleration greater than a**<br>**transient threshold event**.|0 Event detection disabled (default)<br>1 Raise event flag on measured acceleration delta<br>value that is greater than a transient threshold.|
|2|YTEFE|**Event flag enable for Y-transient acceleration greater than a**<br>**transient threshold event**.||
|1|XTEFE|**Event flag enable for X-transient acceleration greater than**<br>**a transient threshold event**.||
|0|HPF_BYP|**Bypass high-pass filter**<br>0 Data to transient acceleration detection block is through HPF<br>(default)<br>1 Data to transient acceleration detection block is NOT through<br>HPF (similar to motion detection function)||



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## **6.9.2 0x1E TRANSIENT_SRC register** 

The transient source register provides the status of the enabled axes and the polarity (directional) information. When the TRANSIENT_SRC register is read, it clears the interrupt for the transient detection. 

When new events arrive while EA = 1, additional *TRANSE bits may get set, and the corresponding *_Trans_Pol flag become updated. However no *TRANSE bit may get cleared before the TRANSIENT_SRC register is read. 

## **Table 60. 0x1E TRANSIENT_SRC register (Read-Only)** 

_Back to Register Address Map_ 

|**Bit7**|**Bit6**|**Bit5**|**Bit4**|**Bit3**|**Bit2**|**Bit1**|**Bit0**|
|---|---|---|---|---|---|---|---|
|—|EA|ZTRANSE|Z_Trans_Pol|YTRANSE|Y_Trans_Pol|XTRANSE|X_Trans_Pol|



## **Table 61. TRANSIENT_SRC register** 

|**Bit(s)**|**Field**|**Description**|
|---|---|---|
|7|—|Could be 0 or 1.|
|6|EA|**Event Active Flag**<br>0 No event flag has been asserted (default)<br>1 One or more event flags has been asserted.|
|5|ZTRANSE|**Z-transient event**<br>0 No interrupt (default)<br>1 Z-transient acceleration greater than the value of TRANSIENT_THS event has occurred|
|4|Z_Trans_Pol|**Polarity of Z-Transient Event that triggered the interrupt**<br>0 Z-event was positive g (default)<br>1 Z-event was negative g|
|3|YTRANSE|**Y-transient event**<br>0 No interrupt (default)<br>1 Y-transient acceleration greater than the value of TRANSIENT_THS event has occurred|
|2|Y_Trans_Pol|**Polarity of Y-Transient Event that triggered the interrupt**<br>0 Y-event was Positive g (default)<br>1 Y-event was Negative g|
|1|XTRANSE|**X-transient event**<br>0 No interrupt (default)<br>1 X-transient acceleration greater than the value of TRANSIENT_THS event has occurred|
|0|X_Trans_Pol|**Polarity of X-Transient Event that triggered the interrupt**<br>0 X-event was Positive g (default)<br>1 X-event was Negative g|



- When the EA bit gets set while ELE = 1, all other status bits get frozen at their current state. 

- By reading the TRANSIENT_SRC register, all bits get cleared. 

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## **6.9.3 0x1F TRANSIENT_THS register** 

The Transient Threshold register sets the threshold limit for the detection of the transient acceleration. The value in the TRANSIENT_THS register corresponds to a g value, which is compared against the values of high-pass filtered data. If the high- 

pass filtered acceleration value exceeds the threshold limit, an event flag is raised and the interrupt is generated (if enabled). 

**Table 62. 0x1F TRANSIENT_THS register (Read/Write)** _Back to Register Address Map_ **Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0** DBCNTM THS6 THS5 THS4 THS3 THS2 THS1 THS0 ~~—~~ 

## **Table 63. TRANSIENT_THS register** 

|**Bit(s)**|**Field**|**Description**|**Notes**|
|---|---|---|---|
|7|DBCNTM|**Debounce counter mode selection**<br>0 Increments or decrements debounce (default)<br>1 Increments or clears counter||
|6–0|THS[6:0]|**Transient Threshold**<br>A 7-bit unsigned number, with 0.063 g/LSB.<br>The maximum threshold is ±8 g.<br>000_0000<br>(default)|Even if the part is set to full scale at ±2 g (or ±4 g), this<br>function will still operate up to ±8 g.|



## **6.9.4 0x20 TRANSIENT_COUNT register** 

The TRANSIENT_COUNT sets the minimum number of debounce counts continuously matching the condition where the unsigned value of high-pass filtered data is greater than the user-specified value of TRANSIENT_THS. 

**Table 64. 0x20 TRANSIENT_COUNT register (Read/Write)** _Back to Register Address Map_ 

|**Table 64. 0x20 TRANSIENT_COUNT register (Read/Write)**<br>_Back to Register Address Map_|**Table 64. 0x20 TRANSIENT_COUNT register (Read/Write)**<br>_Back to Register Address Map_|**Table 64. 0x20 TRANSIENT_COUNT register (Read/Write)**<br>_Back to Register Address Map_|**Table 64. 0x20 TRANSIENT_COUNT register (Read/Write)**<br>_Back to Register Address Map_|**Table 64. 0x20 TRANSIENT_COUNT register (Read/Write)**<br>_Back to Register Address Map_|**Table 64. 0x20 TRANSIENT_COUNT register (Read/Write)**<br>_Back to Register Address Map_|**Table 64. 0x20 TRANSIENT_COUNT register (Read/Write)**<br>_Back to Register Address Map_|**Table 64. 0x20 TRANSIENT_COUNT register (Read/Write)**<br>_Back to Register Address Map_|**Table 64. 0x20 TRANSIENT_COUNT register (Read/Write)**<br>_Back to Register Address Map_|**Table 64. 0x20 TRANSIENT_COUNT register (Read/Write)**<br>_Back to Register Address Map_|**Table 64. 0x20 TRANSIENT_COUNT register (Read/Write)**<br>_Back to Register Address Map_|**Table 64. 0x20 TRANSIENT_COUNT register (Read/Write)**<br>_Back to Register Address Map_|**Table 64. 0x20 TRANSIENT_COUNT register (Read/Write)**<br>_Back to Register Address Map_|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Bit7**<br>**Bit6**<br>**Bit5**<br>**Bit4**<br>**Bit3**<br>**Bit2**<br>**Bit1**<br>**Bit0**<br>D7<br>D6<br>D5<br>D4<br>D3<br>D2<br>D1<br>D0<br>~~=~~|||||||||||||
|**Table 65. TRANSIENT_COUNT register**|||||||||||||
|The time step for the transient detection debounce counter is set by the value of the system ODR and the Oversampling mode.<br>**Bit(s)**<br>**Field**<br>**Description**<br>7–0<br>D[7:0]<br>**Count value**<br>0000_0000<br>(default)<br>~~i~~<br>~~a~~|||||||||||||
|**Table 66. TRANSIENT_COUNT relationship with the ODR**|||||||||||||
|**ODR (Hz)**||**Max Time Range (s)**||||||**Time Step (ms)**|||||
||**Normal**|**LPLN**<br>**HighRes**||**LP**|||**Normal**|**LPLN**||**HighRes**|**LP**||
|800|0.319|0.319<br>0.319||0.319|||1.25|1.25||1.25|1.25||
|400|0.638|0.638<br>0.638||0.638|||2.5|2.5||2.5|2.5||
|200|1.28|1.28<br>0.638||1.28|||5|5||2.5|5||
|100|2.55|2.55<br>0.638||2.55|||10|10||2.5|10||
|50|5.1|5.1<br>0.638||5.1|||20|20||2.5|20||
|12.5|5.1|20.4<br>0.638||20.4|||20|80||2.5|80||
|6.25|5.1|20.4<br>0.638||40.8|||20|80||2.5|160||
|1.56|5.1|20.4<br>0.638||40.8|||20|80||2.5|160||



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## **6.10 Pulse configuration and status registers** 

For more information about of how to configure the tap detection and sample code, see application note AN4083, _Data Manipulation and Basic Settings for Xtrinsic MMA865xFC Accelerometers_ . The tap detection registers are referred to as “Pulse”. 

## **6.10.1 0x21: PULSE_CFG Pulse Configuration register** 

The PULSE_CFG register configures the event flag for tap detection, enabling/disabling the detection of a single and double pulse on each of the axes. 

## **Table 67. 0x21 PULSE_CFG register (Read/Write)** 

|**Table 67. 0x21 PULSE_CFG register (Read/Write)**|**Table 67. 0x21 PULSE_CFG register (Read/Write)**|**Table 67. 0x21 PULSE_CFG register (Read/Write)**|**Table 67. 0x21 PULSE_CFG register (Read/Write)**|||_Back to Register Address Map_|_Back to Register Address Map_|
|---|---|---|---|---|---|---|---|
|**Bit7**|**Bit6**|**Bit5**|**Bit4**|**Bit3**|**Bit2**|**Bit1**|**Bit0**|
|DPA|ELE|ZDPEFE|ZSPEFE|YDPEFE|YSPEFE|XDPEFE|XSPEFE|



## **Table 68. PULSE_CFG register** 

|**Bit(s)**|**Field**|**Description**|**Notes**|
|---|---|---|---|
|7|DPA|**Double Pulse Abort**<br>0 Double Pulse detection is not aborted if the start of a pulse is detected during<br>the time period specified by the PULSE_LTCY register. (default)<br>1 Setting the DPA bit momentarily suspends the double tap detection if the<br>start of a pulse is detected during the time period specified by the<br>PULSE_LTCY register, and the pulse ends before the end of the time period<br>specified by the PULSE_LTCY register.||
|6|ELE|**Pulse event flags are latched into the PULSE_SRC register**.<br>Reading of the PULSE_SRC register clears the event flag.|0 Event detection is disabled (default)<br>1 Event detection is enabled|
|5|ZDPEFE|**Event flag enable for a double pulse event on Z-axis**||
|4|ZSPEFE|**Event flag enable for a single pulse event on Z-axis**||
|3|YDPEFE|**Event flag enable for a double pulse event on Y-axis**||
|2|YSPEFE|**Event flag enable for a single pulse event on Y-axis**||
|1|XDPEFE|**Event flag enable for a double pulse event on X-axis**||
|0|XSPEFE|**Event flag enable for a single pulse event on X-axis**||



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## **6.10.2 0x22: PULSE_SRC Pulse Source register** 

The PULSE_SRC register indicates a double or single pulse event has occurred (and also which direction). The corresponding axis and event must be enabled in register 0x21 for the event flag to be asserted in the source register. 

**Table 69. 0x22 PULSE_SRC register (Read-Only)** 

_Back to Register Address Map_ 

|**Bit7**|**Bit6**|**Bit5**|**Bit4**|**Bit3**|**Bit2**|**Bit1**|**Bit0**|
|---|---|---|---|---|---|---|---|
|EA|AxZ|AxY|AxX|DPE|PolZ|PolY|PolX|



## **Table 70. PULSE_SRC register** 

|**Bit**|**Field**|**Description**|
|---|---|---|
|||**Event Active Flag**|
|7|EA|0 No interrupt has been generated (default)|
|||1 One or more interrupt events have been generated|
|||**Z-axis event**|
|6|AxZ|0 No interrupt (default)|
|||1 Z-axis event has occurred|
|||**Y-axis event**|
|5|AxY|0 No interrupt (default)|
|||1 Y-axis event has occurred)|
|||**X-axis event**|
|4|AxX|0 No interrupt (default)|
|||1 X-axis event has occurred|
|||**Double pulse on first event**|
|3|DPE|0 Single pulse event triggered interrupt (default)|
|||1 Double pulse event triggered interrupt|
|||**Pulse polarity of Z-axis event**|
|2|PolZ|0 Pulse event that triggered interrupt was positive (default)|
|||1 Pulse event that triggered interrupt was negative)|
|||**Pulse polarity of Y-axis event**|
|1|PolY|0 Pulse event that triggered interrupt was positive (default)|
|||1 Pulse event that triggered interrupt was negative|
|||**Pulse polarity of X-axis event**|
|0|PolX|0 Pulse event that triggered interrupt was positive (default)|
|||1 Pulse event that triggered interrupt was negative|



- When the EA bit gets set while ELE = 1, all status bits (AxZ, AxY, AxZ, DPE, and PolX, PolY, PolZ) are frozen. 

- Reading the PULSE_SRC register clears all bits. 

- Reading the source register will clear the interrupt. 

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## **6.10.3 0x23 – 0x25: PULSE_THSX, Y, Z Pulse Threshold for X, Y and Z registers** 

The pulse threshold can be set separately for the X, Y, and Z axes. The PULSE_THSX, PULSE_THSY and PULSE_THSZ registers define the threshold that is used by the system to start the pulse detection procedure. 

**Table 71. 0x23 PULSE_THSX register (Read/Write)** 

|**Table 71. 0x23 PULSE_THSX register (Read/Write)**|**Table 71. 0x23 PULSE_THSX register (Read/Write)**|||||
|---|---|---|---|---|---|
|**Table 71. 0x23 PULSE_THSX register (Read/Write)**<br>**Bit7**<br>0<br>~~es~~|**Table 71. 0x23 PULSE_THSX register (Read/Write)**<br>**Bit6**<br>**Bit5**<br>**Bit4**<br>THSX6<br>THSX5<br>THSX4<br>~~a~~|**Bit3**<br>THSX3|**Bit2**<br>THSX2|_Back to Register Address Map_<br>**Bit1**<br>**Bit0**<br>THSX1<br>THSX0||
|**Table 72. PULSE_THSX register**||||||
|**Bit(s)**<br>**Field**<br>6–0<br>THSX[6:0]<br>**Pulse threshold on X-axis**<br>000_0000<br>(default)<br>~~a~~||**Description**||||
|**Table 73. 0x24 PULSE_THSY register (Read/Write)**<br>**Bit7**<br>**Bit6**<br>**Bit5**<br>**Bit4**<br>0<br>THSY6<br>THSY5<br>THSY4<br>~~a a~~||**Bit3**<br>THSY3|**Bit2**<br>THSY2|_Back to Register Address Map_<br>**Bit1**<br>**Bit0**<br>THSY1<br>THSY0||
|**Table 74. PULSE_THSY register**||||||
|**Bit(s)**<br>**Field**<br>6–0<br>THSY[6:0]<br>**Pulse threshold on Y-axis**<br>000_0000<br>(default value)<br>~~a~~||**Description**||||
|**Table 75. 0x25 PULSE_THSZ register (Read/Write)**<br>**Bit7**<br>**Bit6**<br>**Bit5**<br>**Bit4**<br>0<br>THSZ6<br>THSZ5<br>THSZ4<br>~~a a a ~~||**Bit3**<br>THSZ3<br> ~~a ~~|**Bit2**<br>THSZ2<br> ~~a~~|_Back to Register Address Map_<br>**Bit1**<br>**Bit0**<br>THSZ1<br>THSZ0<br>~~a~~||
|**Table 76. PULSE_THSZ register**||||||
|**Bit(s)**<br>**Field**<br>6–0<br>THSZ[6:0]<br>**Pulse threshold on Z-axis**<br>000_0000<br>(default)<br>~~a~~||**Description**||||



• The threshold values range from 1 to 127, with steps of 0.63 g/LSB at a fixed ±8 g acceleration range, thus the minimum resolution is always fixed at 0.063 g/LSB. 

- The PULSE_THSX, PULSE_THSY and PULSE_THSZ registers define the threshold which is used by the system to start the pulse detection procedure. 

- The threshold value is expressed over seven bits as an unsigned number. 

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~~a~~ NO **6.10.4 0x26: PULSE_TMLT Pulse Time Window 1 register** 

**Table 77. 0x26 PULSE_TMLT register (Read/Write)** _Back to Register Address Map_ **Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0** TMLT7 TMLT6 TMLT5 TMLT4 TMLT3 TMLT2 TMLT1 TMLT0 ~~—~~ **Table 78. PULSE_TMLT register Bit(s) Field Description Pulse Time Limit** 7–0 TMLT[7:0] 0000_0000 (default) ~~i~~ Bits TMLT7 – TMLT0 define the maximum time interval that can elapse between the start of the acceleration on the selected axis exceeding the specified threshold, and the end when the acceleration on the selected axis must go below the specified threshold to be considered a valid pulse. 

The minimum time step for the pulse time limit is defined in Table 79 and Table 80. 

- Maximum time for a given ODR and Oversampling mode is the time step pulse multiplied by 255. 

- The time steps available are dependent on the Oversampling mode and whether the pulse low-pass filter option is enabled or not. 

- The pulse low-pass filter is set in Register 0x0F. 

## **Table 79. Time Step for PULSE time limit (Reg 0x0F) Pulse_LPF_EN = 1** 

|**ODR (Hz)**|**Max Time Range (s)**|**Max Time Range (s)**|**Max Time Range (s)**|**Max Time Range (s)**|**Time Step (ms)**|**Time Step (ms)**|**Time Step (ms)**|**Time Step (ms)**|
|---|---|---|---|---|---|---|---|---|
||**Normal**|**LPLN**|**HighRes**|**LP**|**Normal**|**LPLN**|**HighRes**|**LP**|
|800|0.319|0.319|0.319|0.319|1.25|1.25|1.25|1.25|
|400|0.638|0.638|0.638|0.638|2.5|2.5|2.5|2.5|
|200|1.28|1.28|0.638|1.28|5|5|2.5|5|
|100|2.55|2.55|0.638|2.55|10|10|2.5|10|
|50|5.1|5.1|0.638|5.1|20|20|2.5|20|
|12.5|5.1|20.4|0.638|20.4|20|80|2.5|80|
|6.25|5.1|20.4|0.638|40.8|20|80|2.5|160|
|1.56|5.1|20.4|0.638|40.8|20|80|2.5|160|



**Table 80. Time Step for PULSE Time Limit (Reg 0x0F) Pulse_LPF_EN = 0** 

|**ODR (Hz)**|**Max Time Range (s)**|**Max Time Range (s)**|**Max Time Range (s)**|**Max Time Range (s)**|**Time Step (ms)**|**Time Step (ms)**|**Time Step (ms)**|**Time Step (ms)**|
|---|---|---|---|---|---|---|---|---|
||**Normal**|**LPLN**|**HighRes**|**LP**|**Normal**|**LPLN**|**HighRes**|**LP**|
|800|0.159|0.159|0.159|0.159|0.625|0.625|0.625|0.625|
|400|0.159|0.159|0.159|0.319|0.625|0.625|0.625|1.25|
|200|0.319|0.319|0.159|0.638|1.25|1.25|0.625|2.5|
|100|0.638|0.638|0.159|1.28|2.5|2.5|0.625|5|
|50|1.28|1.28|0.159|2.55|5|5|0.625|10|
|12.5|1.28|5.1|0.159|10.2|5|20|0.625|40|
|6.25|1.28|5.1|0.159|10.2|5|20|0.625|40|
|1.56|1.28|5.1|0.159|10.2|5|20|0.625|40|



**MMA8652FC** 

Sensors Freescale Semiconductor, Inc. 

48 

## **6.10.5 0x27: PULSE_LTCY Pulse Latency Timer register** 

**Table 81. 0x27 PULSE_LTCY register (Read/Write)** 

|**Table 81. 0x27 PULSE_LTCY register (Read/Write)**|**Table 81. 0x27 PULSE_LTCY register (Read/Write)**|**Table 81. 0x27 PULSE_LTCY register (Read/Write)**|**Table 81. 0x27 PULSE_LTCY register (Read/Write)**|||_Back to Register Address Map_|_Back to Register Address Map_|
|---|---|---|---|---|---|---|---|
|**Bit7**|**Bit6**|**Bit5**|**Bit4**|**Bit3**|**Bit2**|**Bit1**|**Bit0**|
|LTCY7|LTCY6|LTCY5|LTCY4|LTCY3|LTCY2|LTCY1|LTCY0|



## **Table 82. PULSE_LTCY register** 

|**Bit(s)**|**Field**||**Description**|
|---|---|---|---|
|7–0|LTCY[7:0]|**Latency Time Limit**<br>0000_0000<br>(default)||



Bits LTCY7 – LTCY0 define the time interval that starts after the first pulse detection. During this time interval, all pulses are ignored. 

## **NOTE** 

This timer must be set for single pulse _and_ for double pulse. 

The minimum time step for the pulse latency is defined in Table 83 and Table 84. 

- The maximum time is the time step _at the ODR and Oversampling mode_ multiplied by 255. 

- The timing also changes when the Pulse LPF is enabled or disabled. 

**Table 83. Time Step for PULSE Latency at ODR and Power mode (Reg 0x0F) Pulse_LPF_EN = 1** 

|**ODR (Hz)**<br>~~ee~~|**Max Time Range (s)**<br>~~eeeesee~~|**Max Time Range (s)**<br>~~eeeesee~~|**Max Time Range (s)**<br>~~eeeesee~~|**Max Time Range (s)**<br>~~eeeesee~~|**Time Step (ms)**<br>~~eesesesee~~|**Time Step (ms)**<br>~~eesesesee~~|**Time Step (ms)**<br>~~eesesesee~~|**Time Step (ms)**<br>~~eesesesee~~|
|---|---|---|---|---|---|---|---|---|
||**Normal**<br>~~ee~~|**LPLN**<br>~~ee~~|**HighRes**<br>~~ees~~|**LP**<br>~~ee~~<br>~~|~~|**Normal**<br>~~ees~~<br>~~|~~|**LPLN**<br>~~es~~<br>~~GO~~|**HighRes**<br>~~es~~<br>~~GO~~|**LP**<br>~~ee~~|
|800<br>~~ee~~<br>~~eG~~|0.638<br>~~ee~~<br>~~eG~~|0.638<br>~~ee ~~<br>~~eG~~|0.638<br> ~~ees ~~<br>~~eG~~|0.638<br> ~~ee ~~<br>~~eG~~<br>~~|~~<br>~~|~~|2.5<br> ~~ees ~~<br>~~eG~~<br>~~|~~<br>~~|~~|2.5<br> ~~es ~~<br>~~eG~~<br>~~GO~~<br>~~|~~|2.5<br> ~~es~~<br>~~eG~~<br>~~GO~~|2.5<br>~~ee~~<br>~~eG~~|
|400<br>~~eG~~|1.276<br>~~eG~~|1.276<br>~~eG~~|1.276<br>~~eG~~|1.276<br>~~|~~<br>~~eG~~<br>~~|~~<br>~~|~~|5<br>~~|~~<br>~~eG~~<br>~~|~~<br>~~|~~|5<br>~~GO~~<br>~~eG~~<br>~~|~~<br>~~GO~~|5<br>~~GO~~<br>~~eG~~<br>~~GO~~|5<br>~~eG~~|
|200<br>~~eG~~<br>~~GO~~|2.56<br>~~eG~~<br>~~GO~~|2.56<br>~~eG~~<br>~~GO~~|1.276<br>~~eG~~<br>~~GO~~|2.56<br>~~eG~~<br>~~|~~<br>~~GO~~<br>~~|~~<br>~~|~~|10<br>~~eG~~<br>~~|~~<br>~~GO~~<br>~~|~~<br>~~|~~|10<br>~~eG~~<br>~~|~~<br>~~GO~~<br>~~GO~~<br>~~|~~|5<br>~~eG~~<br>~~GO~~<br>~~GO~~|10<br>~~eG~~<br>~~GO~~|
|100<br>~~GO~~<br>~~eG~~|5.1<br>~~GO~~<br>~~eG~~|5.1<br>~~GO~~<br>~~eG~~|1.276<br>~~GO~~<br>~~eG~~|5.1<br>~~GO~~<br>~~|~~<br>~~eG~~<br>~~|~~<br>~~|~~|20<br>~~GO~~<br>~~| ~~<br>~~eG~~<br>~~|~~<br>~~|~~|20<br>~~GO~~<br> ~~GO~~<br>~~eG~~<br>~~|~~<br>~~|~~|5<br>~~GO~~<br>~~GO~~<br>~~eG~~|20<br>~~GO~~<br>~~eG~~|
|50<br>~~eG~~|10.2<br>~~eG~~|10.2<br>~~eG~~|1.276<br>~~eG~~|10.2<br>~~|~~<br>~~eG~~<br>~~|~~<br>~~|~~|40<br>~~|~~<br>~~eG~~<br>~~|~~<br>~~|~~|40<br>~~|~~<br>~~eG~~<br>~~|~~<br>~~GO~~|5<br>~~eG~~<br>~~GO~~|40<br>~~eG~~|
|12.5<br>~~eG~~<br>~~GO~~|10.2<br>~~eG~~<br>~~GO~~|40.8<br>~~eG~~<br>~~GO~~|1.276<br>~~eG~~<br>~~GO~~|40.8<br>~~eG~~<br>~~|~~<br>~~GO~~<br>~~|~~<br>~~|~~|40<br>~~eG~~<br>~~|~~<br>~~GO~~<br>~~|~~<br>~~|~~|160<br>~~eG~~<br>~~|~~<br>~~GO~~<br>~~GO~~<br>~~|~~|5<br>~~eG~~<br>~~GO~~<br>~~GO~~|160<br>~~eG~~<br>~~GO~~|
|6.25<br>~~GO~~<br>~~eG~~|10.2<br>~~GO~~<br>~~eG~~|40.8<br>~~GO~~<br>~~eG~~|1.276<br>~~GO~~<br>~~eG~~|81.6<br>~~GO~~<br>~~|~~<br>~~eG~~<br>~~|~~<br>~~|G~~|40<br>~~GO~~<br>~~| ~~<br>~~eG~~<br>~~|~~<br>~~|G~~|160<br>~~GO~~<br> ~~GO~~<br>~~eG~~<br>~~|~~<br>~~|G~~|5<br>~~GO~~<br>~~GO~~<br>~~eG~~|320<br>~~GO~~<br>~~eG~~|
|1.56<br>~~GO~~|10.2<br>~~GO~~|40.8<br>~~GO~~|1.276<br>~~GO~~|81.6<br>~~|~~<br>~~GO~~<br>~~|G~~|40<br>~~|~~<br>~~GO~~<br>~~|G~~|160<br>~~|~~<br>~~GO~~<br>~~|G~~|5<br>~~GO~~|320<br>~~GO~~|



**Table 84. Time Step for PULSE Latency at ODR and Power Mode (Reg 0x0F) Pulse_LPF_EN = 0** 

|**ODR (Hz)**<br>~~ee~~|**Max Time Range (s)**<br>~~ee~~|**Max Time Range (s)**<br>~~ee~~|**Max Time Range (s)**<br>~~ee~~|**Max Time Range (s)**<br>~~ee~~|**Time Step (ms)**<br>~~eses~~|**Time Step (ms)**<br>~~eses~~|**Time Step (ms)**<br>~~eses~~|**Time Step (ms)**<br>~~eses~~|
|---|---|---|---|---|---|---|---|---|
||**Normal**<br>~~ee~~|**LPLN**<br>~~ee~~|**HighRes**<br>~~ee~~|**LP**<br>~~ee~~|**Normal**<br>~~es~~|**LPLN**<br>~~es~~|**HighRes**|**LP**|
|800<br>~~ee~~<br>~~|~~|0.318<br>~~ee~~<br>~~|~~|0.318<br>~~ee~~<br>~~|~~|0.318<br>~~ee~~<br>~~|~~|0.318<br>~~ee ~~<br>~~|~~|1.25<br> ~~es ~~<br>~~|~~|1.25<br> ~~es~~<br>~~|~~|1.25<br>~~|~~|1.25<br>~~|~~|
|400<br>~~po~~|0.318<br>~~po~~|0.318<br>~~po~~|0.318<br>~~po~~|0.638<br>~~po~~|1.25<br>~~po~~|1.25<br>~~po~~|1.25<br>~~po~~|2.5<br>~~po~~|
|200<br>~~se~~|0.638<br>~~se~~|0.638<br>~~se|G~~|0.318<br>~~|G~~|1.276<br>~~|G~~|2.5<br>~~|G~~|2.5<br>~~|G~~|1.25<br>~~|G~~|5<br>~~|G~~|
|100<br>~~se~~<br>~~po~~|1.276<br>~~se~~<br>~~po~~|1.276<br>~~se|G~~<br>~~po~~|0.318<br>~~|G~~<br>~~po~~|2.56<br>~~|G~~<br>~~po~~|5<br>~~|G~~<br>~~po~~|5<br>~~|G~~<br>~~po~~|1.25<br>~~|G~~<br>~~po~~|10<br>~~|G~~<br>~~po~~|
|50<br>~~po~~|2.56<br>~~po~~|2.56<br>~~po~~|0.318<br>~~po~~|5.1<br>~~po~~|10<br>~~po~~|10<br>~~po~~|1.25<br>~~po~~|20<br>~~po~~|
|12.5<br>~~se~~|2.56<br>~~se~~|10.2<br>~~se|G~~|0.318<br>~~|G~~|20.4<br>~~|G~~|10<br>~~|G~~|40<br>~~|G~~|1.25<br>~~|G~~|80<br>~~|G~~|
|6.25<br>~~se~~<br>~~po~~|2.56<br>~~se~~<br>~~po~~|10.2<br>~~se|G~~<br>~~po~~|0.318<br>~~|G~~<br>~~po~~|20.4<br>~~|G~~<br>~~po~~|10<br>~~|G~~<br>~~po~~|40<br>~~|G~~<br>~~po~~|1.25<br>~~|G~~<br>~~po~~|80<br>~~|G~~<br>~~po~~|
|1.56<br>~~po~~|2.56<br>~~po~~|10.2<br>~~po~~|0.318<br>~~po~~|20.4<br>~~po~~|10<br>~~po~~|40<br>~~po~~|1.25<br>~~po~~|80<br>~~po~~|



**MMA8652FC** 

Sensors Freescale Semiconductor, Inc. 

49 

## **6.10.6 0x28 PULSE_WIND register (Read/Write)** 

**Table 85. 0x28: PULSE_WIND Second Pulse Time Window register** 

_Back to Register Address Map_ 

|**Bit7**|**Bit6**|**Bit5**|**Bit4**|**Bit3**|**Bit2**|**Bit1**|**Bit0**|
|---|---|---|---|---|---|---|---|
|WIND7|WIND6|WIND5|WIND4|WIND3|WIND2|WIND1|WIND0|



## **Table 86. PULSE_WIND register** 

|**Bit(s)**|**Field**||**Description**|
|---|---|---|---|
|7–0|WIND[7:0]|**Second Pulse Time Window**<br>0000_0000<br>(default value)||



Bits WIND7 – WIND0 define the maximum interval of time that can elapse after the end of the latency interval, in which the start of the second pulse event must be detected (provided the device has been configured for double pulse detection). The detected second pulse width must be shorter than the time limit constraints specified by the PULSE_TMLT register, but the end of the double pulse need not finish within the time specified by the PULSE_WIND register. 

The minimum time step for the pulse window is defined in Table 87 and Table 88. The maximum time is the time step _at the ODR, oversampling mode and LPF filter option_ multiplied by 255. 

**Table 87. Time Step for PULSE Detection window at ODR and Power mode (Reg 0x0F) Pulse_LPF_EN = 1** 

|**ODR (Hz)**<br>~~ee~~<br>~~PR~~|**Max Time Range (s)**<br>~~eeeses~~|**Max Time Range (s)**<br>~~eeeses~~|**Max Time Range (s)**<br>~~eeeses~~|**Max Time Range (s)**<br>~~eeeses~~|**Time Step (ms)**<br>~~eseseseee~~|**Time Step (ms)**<br>~~eseseseee~~|**Time Step (ms)**<br>~~eseseseee~~|**Time Step (ms)**<br>~~eseseseee~~|
|---|---|---|---|---|---|---|---|---|
||**Normal**<br>~~ee~~<br>~~ee~~|**LPLN**<br>~~ee~~<br>~~ee~~|**HighRes**<br>~~es~~<br>~~eG~~|**LP**<br>~~es~~<br>~~eG~~|**Normal**<br>~~es~~<br>~~eG~~|**LPLN**<br>~~es~~|**HighRes**<br>~~es~~|**LP**<br>~~eee~~|
|800<br>~~ee~~<br>~~PR~~<br>~~po~~|0.638<br>~~ee~~<br>~~ee~~|0.638<br>~~ee ~~<br>~~ee~~|0.638<br> ~~es ~~<br>~~eG~~|0.638<br> ~~es ~~<br>~~eG~~|2.5<br> ~~es ~~<br>~~eG~~|2.5<br> ~~es ~~|2.5<br> ~~es ~~|2.5<br> ~~eee~~|
|400<br>~~PR~~<br>~~po~~<br>~~po~~|1.276<br>~~ee~~|1.276<br>~~ee ~~|1.276<br> ~~eG~~|1.276<br>~~eG~~|5<br>~~eG~~|5|5|5|
|200<br>~~po~~<br>~~po~~<br>~~po~~|2.56|2.56|1.276|2.56|10|10|5|10|
|100<br>~~po~~<br>~~po~~<br>~~po~~|5.1|5.1|1.276|5.1|20|20|5|20|
|50<br>~~po~~<br>~~po~~<br>~~po~~|10.2|10.2|1.276|10.2|40|40|5|40|
|12.5<br>~~po~~<br>~~po~~<br>~~po~~|10.2|40.8|1.276|40.8|40|160|5|160|
|6.25<br>~~po~~<br>~~po~~<br>~~po~~|10.2<br>~~po~~|40.8|1.276|81.6|40|160|5|320|
|1.56<br>~~po~~<br>~~po~~|10.2<br>~~po~~|40.8|1.276|81.6|40|160|5|320|



**Table 88. Time Step for PULSE Detection window at ODR and Power mode (Reg 0x0F) Pulse_LPF_EN = 0** 

|**ODR (Hz)**<br>~~eee~~|**Max Time Range (s)**<br>~~eeeESS~~|**Max Time Range (s)**<br>~~eeeESS~~|**Max Time Range (s)**<br>~~eeeESS~~|**Max Time Range (s)**<br>~~eeeESS~~|**Time Step (ms)**<br>~~ESSSS~~|**Time Step (ms)**<br>~~ESSSS~~|**Time Step (ms)**<br>~~ESSSS~~|**Time Step (ms)**<br>~~ESSSS~~|
|---|---|---|---|---|---|---|---|---|
||**Normal**<br>~~eee~~|**LPLN**<br>~~eee~~|**HighRes**<br>~~ESS~~|**LP**<br>~~ESS~~|**Normal**<br>~~ESS~~<br>~~GO~~|**LPLN**<br>~~SS~~<br>~~GO~~|**HighRes**<br>~~SS~~<br>~~GO~~|**LP**<br>~~SS~~|
|800<br>~~eee~~<br>~~eG~~<br>~~po~~|0.318<br>~~eee~~<br>~~eG~~|0.318<br>~~eee ~~<br>~~eG~~|0.318<br> ~~ESS~~<br>~~eG~~|0.318<br>~~ESS~~<br>~~eG~~|1.25<br>~~ESS ~~<br>~~eG~~<br>~~GO~~<br>~~GO~~|1.25<br> ~~SS~~<br>~~eG~~<br>~~GO~~<br>~~GO~~|1.25<br>~~SS~~<br>~~eG~~<br>~~GO~~<br>~~GO~~|1.25<br>~~SS~~<br>~~eG~~|
|400<br>~~eG~~<br>~~po~~|0.318<br>~~eG~~|0.318<br>~~eG~~|0.318<br>~~eG~~|0.638<br>~~eG~~|1.25<br>~~GO~~<br>~~eG~~<br>~~GO~~|1.25<br>~~GO~~<br>~~eG~~<br>~~GO~~|1.25<br>~~GO~~<br>~~eG~~<br>~~GO~~|2.5<br>~~eG~~|
|200<br>~~eG~~<br>~~po~~<br>~~po~~|0.638<br>~~eG~~<br>|0.638<br>~~eG~~<br>|0.318<br>~~eG~~<br>|1.276<br>~~eG~~<br>|2.5<br>~~eG~~<br>~~GO~~<br>|2.5<br>~~eG~~<br>~~GO~~<br>|1.25<br>~~eG~~<br>~~GO~~<br>|5<br>~~eG~~<br>|
|100<br>~~po~~<br>~~po~~<br>~~po~~|1.276<br>|1.276<br>|0.318<br>|2.56<br>|5<br>~~GO~~<br><br>~~GO~~|5<br>~~GO~~<br><br>~~GO~~|1.25<br>~~GO~~<br><br>~~GO~~|10<br>|
|50<br>~~poeG~~<br>~~po~~|2.56<br>~~eG~~|2.56<br>~~eG~~|0.318<br>~~eG~~|5.1<br>~~eG~~|10<br>~~eG~~<br>~~GO~~|10<br>~~eG~~<br>~~GO~~|1.25<br>~~eG~~<br>~~GO~~|20<br>~~eG~~|
|12.5<br>~~eG~~<br>~~po~~<br>~~po~~|2.56<br>~~eG~~<br>|10.2<br>~~eG~~<br>|0.318<br>~~eG~~<br>|20.4<br>~~eG~~<br>|10<br>~~eG~~<br>~~GO~~<br>|40<br>~~eG~~<br>~~GO~~<br>|1.25<br>~~eG~~<br>~~GO~~<br>|80<br>~~eG~~<br>|
|6.25<br>~~po~~<br>~~po~~|2.56<br>|10.2<br>|0.318<br>|20.4<br>|10<br>~~GO~~<br>|40<br>~~GO~~<br>|1.25<br>~~GO~~<br>|80<br>|
|1.56<br>~~poPo~~|2.56<br>~~Po~~|10.2<br>~~Po~~|0.318<br>~~Po~~|20.4<br>~~Po~~|10<br>~~Po~~|40<br>~~Po~~|1.25<br>~~Po~~|80<br>~~Po~~|



**MMA8652FC** 

Sensors Freescale Semiconductor, Inc. 

50 

## **6.11 Auto-WAKE/SLEEP detection** 

## **6.11.1 0x29: ASLP_COUNT, Auto-WAKE/SLEEP Detection register (Read/Write)** 

The ASLP_COUNT register sets the _minimum time period of inactivity required_ to switch the part between Wake and Sleep status. At the end of the time period, the device switches its ODR rate automatically when the Auto-WAKE /SLEEP function is enabled. 

- Wake ODR is set by **CTRL_REG1[DR]** bits. 

- Sleep ODR is set by **CTRL_REG1[ASLP_RATE]** bits. 

- Auto WAKE/SLEEP function is enabled by asserting the **CTRL_REG2[SLPE]** bit. 

**Table 89. 0x29 ASLP_COUNT register (Read/Write)** 

|**Table 89. 0x29 ASLP_COUNT register (Read/Write)**|**Table 89. 0x29 ASLP_COUNT register (Read/Write)**|**Table 89. 0x29 ASLP_COUNT register (Read/Write)**|**Table 89. 0x29 ASLP_COUNT register (Read/Write)**|||_Back to Register Address Map_|_Back to Register Address Map_|
|---|---|---|---|---|---|---|---|
|**Bit7**|**Bit6**|**Bit5**|**Bit4**|**Bit3**|**Bit2**|**Bit1**|**Bit0**|
|D7|D6|D5|D4|D3|D2|D1|D0|



## **Table 90. ASLP_COUNT register** 

|**Bit(s)**|**Field**||**Description**|
|---|---|---|---|
|7–0|D[7:0]|**Duration value**<br>0000_0000<br>(default)||



D7–D0 defines the minimum duration time needed to change the current ODR value from **DR** to **ASLP_RATE** . The time step and maximum value depend on the ODR chosen (as shown in Table 91). 

**Table 91. ASLP_COUNT relationship with ODR** 

**Output Data Rate Duration ODR Time Step ASLP_COUNT Step (ODR) (sec) (ms) (ms)** 800 Hz 0 to 81 1.25 320 400 Hz 0 to 81 2.5 320 200 Hz 0 to 81 5 320 100 Hz 0 to 81 10 320 50 Hz 0 to 81 20 320 12.5 Hz 0 to 81 80 320 6.25 Hz 0 to 81 160 320 1.56 Hz 0 to 162 640 640 ~~7~~ For functional blocks that may be monitored for inactivity (to trigger the “return to SLEEP” event), see Table 92. **Table 92. SLEEP/WAKE mode gates and triggers Will the event restart the timer Will the event Interrupt Source Notes and delay “Return to SLEEP”? WAKE from SLEEP?** FIFO_GATE Yes No SRC_TRANS Yes Yes * If the FIFO_GATE bit is set to 1, then the assertion of the SRC_LNDPRT Yes Yes SRC_ASLP interrupt does not prevent the system from transitioning to SLEEP or from WAKE mode; instead the SRC_PULSE Yes Yes assertion of the interrupt prevents the FIFO buffer from SRC_FF_MT Yes Yes accepting new sample data—until the host application flushes the FIFO buffer. SRC_ASLP No* No* SRC_DRDY No No ~~===~~ **MMA8652FC** Sensors Freescale Semiconductor, Inc. 51 

- Four interrupt sources can WAKE the device: Transient, Orientation, Tap, and the Motion/Freefall. One or more of these functions can be enabled. 

   - To WAKE the device, the desired function(s) must be enabled in CTRL_REG4 register and set to WAKE-to-SLEEP in CTRL_REG3 register. 

   - All enabled functions still run in SLEEP mode at the SLEEP ODR. 

      - Only the functions that have been selected for WAKE from SLEEP will actually WAKE the device (as configured in register 0x2C). 

   - The Auto-WAKE/SLEEP interrupt does not affect the WAKE/SLEEP, nor does the data ready interrupt. 

   - Note that the FIFO does not WAKE the device. 

   - When set to 1, the FIFO gate (bit 7 in Register 0x2C) will hold the last data in the FIFO, before transitioning to a different ODR. After the buffer is flushed, it will accept new sample data at the current ODR. See Register 0x2C for the WAKE-from-SLEEP interrupt enable bit definitions. 

- MMA8652FC has four functions that can be used to keep the sensor from falling asleep: Transient, Orientation, Tap and Motion/Freefall. 

- Auto-SLEEP bit: 

   - If the Auto-SLEEP bit is disabled, then the device can only toggle between STANDBY and WAKE mode. 

   - If Auto-SLEEP interrupt is enabled, then transitioning from ACTIVE mode to Auto-SLEEP mode (or vice versa) generates an interrupt. 

## **6.12 System and control registers** 

## **NOTE** 

Except for STANDBY mode selection, the device must be in STANDBY mode to change any of the fields within CTRL_REG1 (0x2A). 

## **6.12.1 0x2A: CTRL_REG1 System Control 1 register** 

CTRL_REG1 register configures the Auto-WAKE sample frequency, output data rate selection, and enables the fast-read mode and STANDBY/ACTIVE mode selection. 

**Table 93. 0x2A CTRL_REG1 register (Read/Write)** 

|**Table 93. 0x2A CTRL_REG1 register (Read/Write)**|**Table 93. 0x2A CTRL_REG1 register (Read/Write)**|**Table 93. 0x2A CTRL_REG1 register (Read/Write)**|**Table 93. 0x2A CTRL_REG1 register (Read/Write)**|**Table 93. 0x2A CTRL_REG1 register (Read/Write)**|||_Back to Register Address Map_|_Back to Register Address Map_|
|---|---|---|---|---|---|---|---|---|
|**Bit7**|**Bit6**||**Bit5**|**Bit4**|**Bit3**|**Bit2**|**Bit1**|**Bit0**|
|ASLP_RATE1|ASLP_RATE0||DR2|DR1|DR0|—|F_READ|ACTIVE|



**Table 94. CTRL_REG1 register** 

|**Bit(s)**|**Field**|**Description**|
|---|---|---|
|7–6|ASLP_RATE[1:0]|**Configures the Auto-WAKE sample frequency when the device is in SLEEP Mode**.<br>SeeTable 95.<br>00<br>(default)|
|5–3|DR[2:0]|**Data rate selection**<br>SeeTable 96.<br>000<br>(default)|
|2|—||
|1|F_READ|**Fast-read mode**: Data format is limited to single byte<br>0 Normal mode (default)<br>1 Fast Read Mode|
|0|ACTIVE|**Full-scale selection**<br>0 STANDBY mode (default)<br>1 ACTIVE mode|



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**Table 95. SLEEP mode rates** 

**ASLP_RATE1 ASLP_RATE0 Frequency (Hz) Notes** 0 0 50 0 1 12.5 When the device is in Auto-SLEEP mode, the system ODR and the data rate for all the system functional blocks are overridden by the data 1 0 6.25 rate set by the **ASLP_RATE** field. 1 1 1.56 DR[2:0] bits select the Output Data Rate (ODR) for acceleration samples in WAKE mode. The default value is 000 for a data rate ~~=———— ae~~ of 800 Hz. 

## **Table 96. System output data-rate selection** 

||**DR2**<br>**DR1**<br>**DR0**<br>**ODR**<br>**(Hz)**|**Period**<br>**(ms)**|**Notes**||
|---|---|---|---|---|
||0<br>0<br>0<br>800|1.25|default||
||0<br>0<br>1<br>400|2.5|||
||0<br>1<br>0<br>200|5|||
||0<br>1<br>1<br>100|10|||
||1<br>0<br>0<br>50|20|||
||1<br>0<br>1<br>12.5|80|||
|The ACTIVE bit selects between STANDBY mode and ACTIVE mode.|The ACTIVE bit selects between STANDBY mode and ACTIVE mode.<br>1<br>1<br>0<br>6.25<br>160<br>1<br>1<br>1<br>1.56<br>640<br>**Table 97. Full-Scale selection using ACTIVE bit**<br>**Active bit**<br>**Mode**<br>0<br>STANDBY (default)<br>1<br>ACTIVE<br>~~a~~||||
|•|The F_Read bit selects between normal and Fast Read mode.||||
||When selected, the auto-increment counter will skip over the LSB data bytes.||||
||Data read from the FIFO will skip over the LSB data, reducing the acquisition time.||||



- Note that F_READ can only be changed when FMODE = 00. 

- The F_READ bit applies for both the output registers and the FIFO. 

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## **6.12.2 0x2B: CTRL_REG2 System Control 2 register** 

CTRL_REG2 register is used to enable Self-Test, Software Reset, and Auto-SLEEP. In addition, it enables you to configure the SLEEP and WAKE mode power scheme selection (oversampling modes). 

**Table 98. 0x2B CTRL_REG2 register (Read/Write)** 

|**Table 98. 0x2B CTRL_REG2 register (Read/Write)**|**Table 98. 0x2B CTRL_REG2 register (Read/Write)**|**Table 98. 0x2B CTRL_REG2 register (Read/Write)**|**Table 98. 0x2B CTRL_REG2 register (Read/Write)**|||_Back to Register Address Map_|_Back to Register Address Map_|
|---|---|---|---|---|---|---|---|
|**Bit7**|**Bit6**|**Bit5**|**Bit4**|**Bit3**|**Bit2**|**Bit1**|**Bit0**|
|ST|RST|0|SMODS1|SMODS0|SLPE|MODS1|MODS0|



## **Table 99. CTRL_REG2 register** 

|**Bit(s)**|**Field**|**Description**|
|---|---|---|
|7|ST|**Self-Test Enable**<br>Activates the self-test function.<br>• When ST is set, the X, Y, and Z outputs will shift.<br>0 Self-Test disabled (default)<br>1 Self-Test enabled|
|6|RST|**Software Reset**<br>RST bit is used to activate the software reset.<br>• The reset mechanism is enabled in both STANDBY and ACTIVE modes.<br>0 Device reset disabled (default)<br>1 Device reset enabled.|
|5|0||
|4–3|SMODS[1:0]|**SLEEP mode power scheme selection**<br>SeeTable 100andTable 101<br>00 (default)|
|2|SLPE|**Auto-SLEEP enable**<br>0 Auto-SLEEP is not enabled (default)<br>1 Auto-SLEEP is enabled.|
|1–0|MODS[1:0]|**ACTIVE mode power scheme selection**<br>SeeTable 100andTable 101<br>00 (default)|



When the reset bit is enabled, all registers are reset and are loaded with default values. Writing ‘1’ to the RST bit immediately resets the device, no matter whether it is in ACTIVE/WAKE, ACTIVE/SLEEP, or STANDBY mode. 

The I[2] C communication system is reset to avoid accidental corrupted data access. 

At the end of the boot process the RST bit is deasserted to 0. Reading this bit will return a value of zero. 

The (S)MODS[1:0] bits select which Oversampling mode is to be used, as shown in Table 100. The Oversampling modes are available in both WAKE Mode MOD[1:0] and also in the SLEEP Mode SMOD[1:0]. 

**Table 100. (S)MODS Oversampling modes** 

|**(S)MODS1**|**(S)MODS0**|**Power Mode**|
|---|---|---|
|0|0|Normal|
|0|1|Low Noise Low Power|
|1|0|High Resolution|
|1|1|Low Power|



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**Table 101. MODS Oversampling modes averaging values at each ODR** 

|**ODR**<br>**(Hz)**|**Mode**|**Mode**|**Mode**|**Mode**|**Mode**|**Mode**|**Mode**|**Mode**|
|---|---|---|---|---|---|---|---|---|
||**Normal (00)**||**Low Noise Low Power (01)**||**High Resolution (10)**||**Low Power (11)**||
||**Current**μ**A**|**OS Ratio**|**Current**μ**A**|**OS Ratio**|**Current**μ**A**|**OS Ratio**|**Current**μ**A**|**OS Ratio**|
|1.56|27|128|9|32|184|1024|6.5|16|
|6.25|27|32|9|8|184|256|6.5|4|
|12.5|27|16|9|4|184|128|6.5|2|
|50|27|4|27|4|184|32|15|2|
|100|49|4|49|4|184|16|26|2|
|200|94|4|94|4|184|8|49|2|
|400|184|4|184|4|184|4|94|2|
|800|184|2|184|2|184|2|184|2|



## **6.12.3 0x2C: CTRL_REG3 Interrupt Control register** 

CTRL_REG3 register is used to control the Auto-WAKE/SLEEP function by setting the orientation or Freefall/Motion as an interrupt to wake. CTRL_REG3 register also configures the interrupt pins INT1 and INT2. 

## **Table 102. 0x2C CTRL_REG3 register (Read/Write)** 

|**Table 102. 0x2C CTRL_REG3 register (Read/Write)**|**Table 102. 0x2C CTRL_REG3 register (Read/Write)**|**Table 102. 0x2C CTRL_REG3 register (Read/Write)**|||_Back to Register Address Map_|_Back to Register Address Map_|_Back to Register Address Map_|
|---|---|---|---|---|---|---|---|
|**Bit7**|**Bit6**|**Bit5**|**Bit4**|**Bit3**|**Bit2**|**Bit1**|**Bit0**|
|FIFO_GATE|WAKE_TRANS|WAKE_LNDPRT|WAKE_PULSE|WAKE_FF_MT|0|IPOL|PP_OD|



## **Table 103. CTRL_REG3 register** 

|**Bit(s)**|**Field**|**Description**|
|---|---|---|
|7|FIFO_GATE|**FIFO Gate**<br>0 FIFO gate is bypassed. (default)<br>FIFO is flushed upon the system mode transitioning from WAKE to SLEEP mode or from SLEEP to WAKE<br>mode.<br>1 The FIFO input buffer is blocked when transitioning from WAKE to SLEEP mode or from SLEEP to WAKE<br>mode, until the FIFO is flushed. Although the system transitions from WAKE to SLEEP or from SLEEP to<br>WAKE—the contents of the FIFO buffer are preserved, and new data samples are ignored until the FIFO is<br>emptied by the host application.<br>If the FIFO_GATE bit is set to 1 and the FIFO buffer is not emptied before the arrival of the next sample,<br>then the FGERR bit in the SYS_MOD register (0x0B) will be asserted. The FGERR bit remains asserted as<br>long as the FIFO buffer remains un-emptied. Emptying the FIFO buffer clears the FGERR bit in the<br>SYS_MOD register.|
|6|WAKE_TRANS|**Wake from Transient interrupt**<br>0 Transient function is bypassed in SLEEP mode. (default)<br>1 Transient function interrupt can wake up system|
|5|WAKE_LNDPRT|**Wake from Orientation interrupt**<br>0 Orientation function is bypassed in SLEEP mode. (default)<br>1 Orientation function interrupt can wake up system|
|4|WAKE_PULSE|**Wake from Pulse interrupt**<br>0 Pulse function is bypassed in SLEEP mode. (default)<br>1 Pulse function interrupt can wake up system|
|3|WAKE_FF_MT|**Wake from Freefall/Motion interrupt**<br>0 Freefall/Motion function is bypassed in SLEEP mode. (default)<br>1 Freefall/Motion function interrupt can wake up|
|2|0||
|1|IPOL|**Interrupt polarity**<br>Selects the polarity of the interrupt signals.<br>When IPOL is 0 (default value), any interrupt event is signaled with a logical 0.<br>0 ACTIVE low (default)<br>1 ACTIVE high|



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**Table 103. CTRL_REG3 register (Continued)** 

|0|PP_OD|**Push-Pull/Open-Drain selection on interrupt pad**<br>Configures the interrupt pins to Push-Pull or to Open-Drain mode.<br>The Open-Drain configuration can be used for connecting multiple interrupt signals on the same interrupt line.<br>0 Push-Pull (default)<br>1 Open Drain|
|---|---|---|



## **6.12.4 0x2D: CTRL_REG4 Interrupt Enable register (Read/Write)** 

CTRL_REG4 register enables the following interrupts: Auto-WAKE/SLEEP, Orientation Detection, Freefall/Motion, and Data Ready. 

## **Table 104. 0x2D CTRL_REG4 Interrupt Enable register (Read/Write)** 

|**Table 104. 0x2D CTRL_REG4 Interrupt Enable register (Read/Write)**|**Table 104. 0x2D CTRL_REG4 Interrupt Enable register (Read/Write)**|**Table 104. 0x2D CTRL_REG4 Interrupt Enable register (Read/Write)**|**Table 104. 0x2D CTRL_REG4 Interrupt Enable register (Read/Write)**|**Table 104. 0x2D CTRL_REG4 Interrupt Enable register (Read/Write)**|**Table 104. 0x2D CTRL_REG4 Interrupt Enable register (Read/Write)**|_Back to Register Address Map_|_Back to Register Address Map_|_Back to Register Address Map_|
|---|---|---|---|---|---|---|---|---|
|**Bit7**|**Bit6**||**Bit5**|**Bit4**|**Bit3**|**Bit2**|**Bit1**|**Bit0**|
|INT_EN_ASLP|INT_EN_FIFO||INT_EN_TRANS|INT_EN_LNDPRT|INT_EN_PULSE|INT_EN_FF_MT|0|INT_EN_DRDY|



**Table 105. CTRL_REG4 register** 

|**Bit(s)**<br>~~po~~|**Field**<br>~~po~~|**Description**<br>~~po~~|**Description**<br>~~po~~|
|---|---|---|---|
|7<br>~~po~~|INT_EN_ASLP<br>~~po~~|**Descript**<br>Auto-SLEEP/WAKE Interrupt Enable<br>~~po~~|**Descript**<br>0 interrupt is disabled (default)<br>1 interrupt is enabled<br>**Note:** The corresponding functional block interrupt<br>enable bit enables the functional block to route<br>its event detection flags to the system’s interrupt<br>controller. The interrupt controller routes the<br>enabled functional block interrupt to the INT1 or<br>INT2 pin.<br>~~po~~|
|6<br>~~po~~|INT_EN_FIFO<br>~~po~~|FIFO Interrupt Enable<br>~~po~~||
|5<br>~~po~~|INT_EN_TRANS<br>~~po~~|Transient Interrupt Enable<br>~~po~~||
|4<br>~~po~~|INT_EN_LNDPRT<br>~~po~~|Orientation (Landscape/Portrait) Interrupt Enable<br>~~po~~||
|3<br>~~po~~|INT_EN_PULSE<br>~~po~~|Pulse Detection Interrupt Enable<br>~~po~~||
|2<br>~~po~~|INT_EN_FF_MT<br>~~po~~|Freefall/Motion Interrupt Enable<br>~~po~~||
|0<br>~~po~~|INT_EN_DRDY<br>~~po~~|Data Ready Interrupt Enable<br>~~po~~||



The system’s interrupt controller, shown in Figure 9, uses the corresponding bit field in the CTRL_REG5 register to determine the routing table for the INT1 and INT2 interrupt pins. 

- If the bit value is 0, then the functional block’s interrupt is routed to INT2. 

- If the bit value is 1, then the functional block’s interrupt is routed to INT1. 

One or more functions can assert an interrupt pin; therefore a host application responding to an interrupt should read the INT_SOURCE (0x0C) register, to determine the appropriate sources of the interrupt. 

**Table 106. 0x2E: CTRL_REG5 Interrupt Configuration register** 

|**Table 106. 0x2E: CTRL_REG5 Interrupt Configuration register**|**Table 106. 0x2E: CTRL_REG5 Interrupt Configuration register**|_Back to Register Address Map_|_Back to Register Address Map_|_Back to Register Address Map_|
|---|---|---|---|---|
|**Bit7**<br>**Bit6**|**Bit5**<br>**Bit4**|**Bit3**<br>**Bit2**|**Bit1**|**Bit0**|
|INT_CFG_ASLP<br>INT_CFG_FIFO|INT_CFG_TRANS<br>INT_CFG_LNDPRT|INT_CFG_PULSE<br>INT_CFG_FF_MT|0|INT_CFG_DRDY|
|**Table 107. 0x2E CTRL_REG5 register**|**Table 107. 0x2E CTRL_REG5 register**||||
|**Bit(s)**<br>**Field**<br>**Description**<br>7<br>INT_CFG_ASLP<br>Auto-SLEEP/WAKE INT1/INT2 Configuration<br>0 Interrupt is routed to INT2 pin (default)<br>1 Interrupt is routed to INT1 pin<br>6<br>INT_CFG_FIFO<br>FIFO INT1/INT2 Configuration<br>5<br>INT_CFG_TRANS<br>Transient INT1/INT2 Configuration<br>4<br>INT_CFG_LNDPRT<br>Orientation INT1/INT2 Configuration<br>3<br>INT_CFG_PULSE<br>Pulse INT1/INT2 Configuration<br>2<br>INT_CFG_FF_MT<br>Freefall/motion INT1/INT2 Configuration<br>1<br>0<br>0<br>INT_CFG_DRDY<br>Data Ready INT1/INT2 Configuration<br>~~=~~|||||
|**MMA8652FC**|||||



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## **6.13 Data calibration registers** 

The 2’s complement offset correction registers values are used to realign the Zero-g position of the X, Y, and Z-axis after the device is mounted on a board. The resolution of the offset registers is 1.96 mg/LSB. The 2’s complement 8-bit value would result in an offset compensation range ±250 mg for each axis. 

## **6.13.1 0x2F: OFF_X Offset Correction X register** 

**Table 108. 0x2F OFF_X register (Read/Write)** 

_Back to Register Address Map_ 

|**Table 108. 0x2F OFF_X register (Read/Write)**||||||_Back to Register Address Map_|_Back to Register Address Map_|
|---|---|---|---|---|---|---|---|
|**Bit7**<br>**Bit6**<br>**Bit5**<br>D7<br>D6<br>D5<br>~~_~~|**Bit4**<br>D4||**Bit3**<br>D3||**Bit2**<br>D2|**Bit1**<br>D1|**Bit0**<br>D0|
|**Table 109. OFF_X register**||||||||
|**Bit(s)**<br>**Field**<br>7–0<br>D[7:0]<br>**X-axis offset value**<br>0000_0000<br>(default)<br>~~a~~|||**Description**|||||
|**6.13.2**<br>**0x30: OFF_Y Offset Correction Y register**||||||||



**Table 110. 0x30 OFF_Y register (Read/Write)** _Back to Register Address Map_ **Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0** D7 D6 D5 D4 D3 D2 D1 D0 ~~[$f|~~ **Table 111. OFF_Y register Bit(s) Field Description Y-axis offset value** 7–0 D[7:0] 0000_0000 (default) ~~a~~ **6.13.3 0x31: OFF_Z Offset Correction Z register** 

**Table 112. 0x31 OFF_Z register (Read/Write)** 

_Back to Register Address Map_ 

|**Bit7**<br>~~[-~~|**Bit6**<br>~~|~~|**Bit5**<br>~~|~~|**Bit4**<br>~~|~~<br>~~|~~|**Bit3**<br>~~||}~~|**Bit2**<br>~~|}~~|**Bit1**<br>~~|}—}—_~~|**Bit0**<br>~~—}—_~~|
|---|---|---|---|---|---|---|---|
|D7<br>~~[-~~|D6<br>~~|~~|D5<br>~~|~~|D4<br>~~|~~<br>~~|~~|D3<br>~~||}~~|D2<br>~~|}~~|D1<br>~~|}—}—_~~|D0<br>~~—}—_~~|



**Table 113. OFF_Z register** 

**Bit(s) Field Description Z-axis offset value** 7–0 D[7:0] 0000_0000 (default) ~~a~~ 

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## **7 Mounting Guidelines** 

Surface mount printed circuit board (PCB) layout is a critical portion of the total design. The footprint for the surface mount packages must be the correct size to ensure proper solder connection interface between the PCB and the package. With the correct footprint, the packages will self-align when subjected to a solder reflow process. These guidelines are for soldering and mounting the Dual Flat No-Lead (DFN) package inertial sensors to PCBs. The purpose is to minimize the stress on the package after board mounting. The MMA865xFC digital output accelerometers use the DFN package platform. This section describes suggested methods of soldering these devices to the PCB for consumer applications. 

## **7.1 Overview of soldering considerations** 

Information provided here is based on experiments executed on DFN devices. They do not represent exact conditions present at a customer site. Therefore, this information should be used as guidance only and process and design optimizations are recommended to develop an application specific solution. It should be noted that with the proper PCB footprint and solder stencil designs, the package will self-align during the solder reflow process. 

## **7.2 Halogen content** 

This package is designed to be Halogen Free, exceeding most industry and customer standards. Halogen Free means that no homogeneous material within the assembly package shall contain chlorine (Cl) in excess of 700 ppm or 0.07% weight/weight or bromine (Br) in excess of 900 ppm or 0.09% weight/weight. 

## **7.3 PCB mounting/soldering recommendations** 

1. The PCB land should be designed as Non Solder Mask Defined (NSMD) as shown in Figure 16. 

2. No additional via pattern underneath package. 

3. PCB land pad is 0.6 mm x 0.225 mm as shown in Figure 16. 

4. Solder mask opening = PCB land pad edge + 0.125 mm larger all around = 0.725 mm x 1.950 mm 

5. Stencil opening = PCB land pad – 0.05 mm smaller all around = 0.55 mm x 0.175 mm. 6. Stencil thickness is 100 or 125 µm. 

7. Do not place any components or vias at a distance less than 2 mm from the package land area. This may cause additional package stress if it is too close to the package land area. 

8. Signal traces connected to pads are as symmetric as possible. Put dummy traces on NC pads, to have same length of exposed trace for all pads. 

9. Use a standard pick and place process and equipment. Do not use a hand soldering process. 

10. Use caution when putting an assembled PCB into an enclosure, noting where the screw-down holes are and if any press-fitting is involved. It is important that the assembled PCB remain flat after assembly, to ensure optimal electronic operation of the device. 

11. The PCB should be rated for the multiple lead-free reflow condition with max 260°C temperature. 

12. No copper traces on top layer of PCB under the package. This will cause planarity issues with board mount. Freescale DFN sensors are compliant with Restrictions on Hazardous Substances (RoHS), having halide free molding compound (green) and lead-free terminations. These terminations are compatible with tin-lead (Sn-Pb) as well as tin-silver-copper (Sn-Ag-Cu) solder paste soldering processes. Reflow profiles applicable to those processes can be used successfully for soldering the devices. 

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**==> picture [471 x 400] intentionally omitted <==**

**----- Start of picture text -----**<br>
0.200<br>2x2 DFN Package<br>1.950<br>All measurements<br>are in mm.<br>0.225<br>0.725 0.600<br>**----- End of picture text -----**<br>


**==> picture [26 x 9] intentionally omitted <==**

**----- Start of picture text -----**<br>
2.525<br>**----- End of picture text -----**<br>


## **PCB landing pad** 

**==> picture [102 x 11] intentionally omitted <==**

**----- Start of picture text -----**<br>
Solder mask opening<br>**----- End of picture text -----**<br>


**Package outline** 

**Figure 16. Package mounting measurements** 

**Table 114. Board mounting guidelines** 

|**Description**|**Value (mm)**|
|---|---|
|Landing Pad Width|0.225|
|Landing Pad Length|0.600|
|Solder Mask Pattern Width|0.725|
|Solder Mask Pattern Length|1.950|
|Landing Pad Extended Length|0.200|
|I/O Pads Extended Length|2.525|



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**8 Tape and Reel** 

## **8.1 Tape dimensions** 

**Figure 17. Carrier tape** 

## **8.2 Device orientation** 

**==> picture [358 x 130] intentionally omitted <==**

**----- Start of picture text -----**<br>
Reel Pin 1 location User direction of feed<br>Do [TTYTVYVddddIIJI-vJTTa] TT<br>Carrier tape Sprocket holes Cover tape<br>**----- End of picture text -----**<br>


**Figure 18. Device orientation on carrier tape** 

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**9 Package Dimensions** 

This drawing is located at http://cache.freescale.com/files/shared/doc/package_info/98ASA00301D.pdf. 

**Figure 19. Case 98ASA00301D, 10-Lead DFN—page 1** 

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**Figure 20. Case 98ASA00301D, 10-Lead DFN—page 2** 

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## **Figure 21. Case 98ASA00301D, 10-Lead DFN—page 3** 

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## **10 Revision History** 

## **Table 115. Revision history for MMA8652FC** 

|**Revision**<br>**number**|**Revision**<br>**date**|**Description of changes**|
|---|---|---|
|0|10/2012|• Initial release.|
|1.0|12/2012|• Classification changed to Technical Data.|
|2.0|02/2013|• Feature comparison table: Orientation Detection features (2) rewritten for clarification.<br>• Section 1: Topics reordered for clarification and consistency.|
|3.0|06/2014|• Section 1.2: Updated Descriptions for Pins 3 and 4.<br>• Section 6.6.2: Updated Description for Field SEL[1:0] in Table 32.<br>• Section 6.12.2: Replace contents in Table 101.|
|3.1|12/2014|• Section 6.8.4: Corrected value in paragraph following Table 54, was 0.63 to 0.063.|
|3.2|03/2014|• Section 5.11: Updated paragraph before Table 11.|
|3.3|10/2015|• No technical changes - corrected format on page 49.|



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## _**How to Reach Us:**_ 

**Home Page:** freescale.com 

**Web Support:** freescale.com/support 

Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. 

Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/salestermsandconditions. 

Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. All other product or service names are the property of their respective owners. 

© 2015 Freescale Semiconductor, Inc. 

Document Number: MMA8652FC Rev. 3.3 10/2015
Updated at March 17, 2026
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