LTM4712IY#PBF

LTM4712 

## 36VIN, 12A Step-Up/Step-Down Buck-Boost µModule Regulator 

## **FEATURES** 

## **DESCRIPTION** 

- n **Complete Buck-Boost Switch Mode Power Supply** 

- n **VOUT Equal, Greater, Less Than VIN** 

- n **Wide Input Voltage Range: 5V to 36V** 

- n **Wide Output Voltage Range: 1V to 36V** 

- n **12A in Buck and Buck-Boost Mode, 6A under 12VIN and 24VOUT** 

- n **Up to 98% Efficiency** 

- n **Peak Current Mode Control** 

- n **Adjustable Input or Output Average Current Limits** 

- n Input or Output Current Monitoring 

- n Power Good Output Signal 

- n Parallelable for Increased Output Current 

- n Phase-Lockable Fixed Frequency: 100kHz to 600kHz 

- n Selectable Forced Continuous/Pulse-Skipping Modes 

- n VOUT is Disconnected from VIN During Shutdown 

- n 16mm ×16mm × 8.34mm BGA Package 

## **APPLICATIONS** 

- n Telecom, Servers and Networking Equipment 

- n Industrial Control 

- n High Power Battery-Operated Devices 

The LTM[®] 4712 is a high efficiency buck-boost µModule[®] (micromodule) regulator. The switching controller, power switches, inductor and support components are included in the package. The complete design requires only a few external components, including a resistor to set frequency, a resistor to set output voltage, input, and output capacitors, a sensing resistor to achieve input or output average current regulation. The LTM4712 operates over a 5V to 36V input voltage range and can regulate output voltages between 1V and 36V. 

The LTM4712 supports selectable forced continuous mode (FCM)/pulse-skipping mode (PSM) operation. The current mode control enables a fast transient response to line and load changes without sacrificing stability. The SYNC input and CLKOUT output allow easy synchronization. It supports multi-phase parallel operation for high power applications. 

The LTM4712 is offered in a 16mm × 16mm × 8.34mm ball grid array (BGA) package suitable for automated assembly by standard surface mount equipment. The LTM4712 is RoHS-compliant. 

All registered trademarks and trademarks are the property of their respective owners. 

## **TYPICAL APPLICATION** 

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12VOUT from 5VIN to 36VIN Buck-Boost Regulator Efficiency and Power Loss vs VIN<br>98 18<br>VIN VIN VOUT VOUT VOUT = 12V 16<br>5V TO 36V 10µF×4 EXTVCC 100µF×3 12V, UP TO 97 EFFICIENCY 15<br>12A<br>96 13<br>RUN<br>FB<br>12<br>9.09k 95<br>SS 10<br>0.1µF MODE LTM4712 ISP 94 8<br>INTVCC ISN 93 POWER LOSS 7<br>2.2µF 5<br>92<br>COMPa 4<br>PINS NOT USED<br>FREQ COMPb IN THIS CIRCUIT: 91 8 12 16 20 24 28 32 362<br>140k CLKOUT<br>SYNC GND PHMODE INPUT VOLTAGE (V)<br>IMON 4712 TA01b<br>4712 TA01a ISET<br>PGOOD<br>EFFICIENCY (%)<br>POWER LOSS (W)<br>**----- End of picture text -----**<br>


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## LTM4712 

## **ABSOLUTE MAXIMUM RATINGS** 

## **PIN CONFIGURATION** 

## **(Note 1)** 

VIN, VOUT, ISP, ISN, EXTVCC ....................... –0.3V to 38V SW1, SW2 .................................................. –0.3V to 38V RUN ............................................................–0.3V to 12V INTVCC, PGOOD ........................................... –0.3V to 6V PHMODE, ISET, IMON, FB .....................–0.3V to INTVCC MODE, SS, COMPa, COMPb .................–0.3V to INTVCC FREQ, SYNC, CLKOUT...........................–0.3V to INTVCC Maximum Junction Temperature (Notes 2, 3) ........................................ –40°C to 125°C Storage Temperature.............................. –55°C to 125°C Peak Solder Reflow Body Temperature ................. 245°C 

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TOP VIEW<br>1 2 3 4 5 6 7 8 9 10 11 12<br>A<br>ISN ISP IMON CLKOUT FREQ PGOOD PHMODE MODE SS<br>B<br>INTVCC EXTVCC ISET SYNC SGND RUN FB COMPa COMPb<br>C<br>GND SGND SGND GND<br>D<br>SGND SGND<br>E<br>F<br>GND<br>G<br>H<br>J<br>VIN VOUT<br>K<br>GND SW1 GND SW2 GND<br>L<br>M<br>CSP_BGA PACKAGE<br>144-PIN (16mm × 16mm × 8.34mm)<br>θJCtop = 9°C/W, θJCbottom = 4.2°C/W, θJA = 9°C/W<br>θ VALUES DEFINED PER JESD 51-12,<br>WEIGHT = 7.4g (TYP.)<br>**----- End of picture text -----**<br>


## **ORDER INFORMATION** 

|**PART NUMBER**|**PAD OR BALL FINISH***|**PART MARKING**|**PART MARKING**|**PACKAGE**<br>**TYPE**|**MSL**<br>**RATING**|**TEMPERATURE RANGE**<br>**(SEE NOTE 2)**|
|---|---|---|---|---|---|---|
|||**DEVICE**|**FINISH CODE**||||
|LTM4712EY#PBF|SAC305(RoHS)|LTM4712Y|e1|BGA|4|–40°C to 125°C|
|LTM4712IY#PBF|SAC305(RoHS)|LTM4712Y|e1|BGA|4|–40°C to 125°C|



- Contact the factory for parts specified with wider operating temperature ranges. *Pad or ball finish code is per IPC/JEDEC J-STD-609. 

- This product is not recommended for second side reflow. 

- Recommended LGA and BGA PCB Assembly and Manufacturing Procedures 

- LGA and BGA Package and Tray Drawings 

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LTM4712 

## **ELECTRICAL CHARACTERISTICS The** l **denotes the specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C. RUN = 5V unless otherwise noted (Note 2).** 

|**PARAMETER**|**CONDITIONS**||**MIN**<br>**TYP**<br>**MAX**|**UNITS**|
|---|---|---|---|---|
|Input Voltage Range||l|5<br>36|V|
|Output Voltage Range|(Note 4)|l|1<br>36|V|
|Output DC Voltage|RFB= Open<br>RFB= 9.09k||1<br>12|V<br>V|
|Output DC Current Range (Note 5)|VIN= 5V, VOUT= 12V, 400kHz<br>VIN= 12V, VOUT= 12V, 400kHz||6<br>12|A<br>A|
|Quiescent Current Into VIN,<br>VIN= 12V, VOUT= 12V|RUN = 0V (Disabled)<br>RUN = 0.9V (Standby)<br>No load, MODE = OPEN (PSM)<br>No load, MODE=0V Forced Continuous Mode(FCM)||80<br>2.5<br>40<br>55|μA<br>mA<br>mA<br>mA|
|Voltage at FB Pin|Forced Continuous Mode (FCM)|l|0.99<br>0.98<br>1<br>1.01<br>1.02|V<br>V|
|Resistor Between VOUTand FB Pins|||100|kΩ|
|Output Voltage Line Regulation|5V ≤ VIN≤ 36V, VOUT= 12V, IOUT= 10mA, FCM , 400kHz|l|0.02<br>0.1|%/V|
|Output Voltage Load Regulation|VIN= 12V, VOUT= 12V, 10mA < IOUT< 12A, FCM , 400kHz||0.5|%|
|||l|0.8|%|
|Input Undervoltage Lockout|VINRising<br>VINFalling||4.6<br>4.4|V<br>v|
|INTVCCRegulation Voltage|VIN= 6V to 36V||4.8<br>5|V|
|INTVCCLoad Regulation|IINTVCC= 0mA to 10mA, VIN= 12V||0.3|%|
|Switching Frequency|RT= 58k<br>RT= 140k (Recommended)<br>RT= 200k||100<br>400<br>600|kHz<br>kHz<br>kHz|
|FREQ Pin Output Current|||9<br>10<br>11|μA|
|RUN Pin Falling Threshold|RUN Pin Threshold 1 (Shutdown to Standby)<br>RUN Pin Threshold 2(Standby to ON)|l|0.4<br>1.1<br>0.55<br>1.2<br>0.7<br>1.3|V<br>V|
|RUN Pin Current|RUN = 1V<br>RUN = 1.6V||2<br>6|µA<br>µA|
|Soft-Start Charging Current|||2.5|µA|
|ISP Pin Input Current|VISP= VISN= 12V, VISP– VISN= 50 mV||14|µA|
|ISN Pin Input Current|VISP= VISN= 12V, VISP– VISN= 50 mV||14|µA|
|Average Current Sense Amplifier Output|VISP–VISN= 0mV<br>VISP–VISN= 50mV||200<br>1200|mV<br>mV|
|ISET Pin Output Current|||14<br>15<br>16|µA|
|PGOOD Leakage Current|VPGOOD= 6.0V||±1|μA|
|PGOOD Trip Level, VFBRespect to Set<br>Regulated Voltage|VFBRamping Negative<br>VFBRamping Positive||–10<br>10|%<br>%|
|CLKOUT Output High|||4.8<br>5|V|
|CLKOUT Output Low|||0.2|V|
|EXTVCCThreshold|EXTVCCThreshold Rising<br>EXTVCCThreshold Falling||7.7<br>7.2|V<br>V|
|SYNC Input High Threshold|SYNC Pin Rising<br>SYNC Pin Falling||1.35<br>1|V<br>V|
|Synchronizable Frequency|SYNC = External Clock||100<br>600|kHz|



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LTM4712 

## **ELECTRICAL CHARACTERISTICS** 

**Note 1:** Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. 

**Note 2:** The LTM4712 is tested under pulsed-load conditions such that TJ ≈ TA. The LTM4712E is guaranteed to meet performance specifications from 0°C to 125°C internal operating temperature range. Specifications over the full –40°C to 125°C internal operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTM4712I is guaranteed to meet specifications over the full –40°C to 125°C internal operating temperature range. Note that the maximum internal temperature is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance. 

**Note 3:** The LTM4712 contains overtemperature protection that is intended to protect the device during momentary overload conditions. The internal temperature exceeds the maximum operating junction temperature when the overtemperature protection is active. 

Continuous operation above the specified maximum operating junction temperature may impair device reliability. 

**Note 4:** Output voltage lower than 7V requires minimum input voltage of 7V. 

**Note 5:** See output current derating curves for different VIN, VOUT, and TA, located in the Applications Information section. 

## **TYPICAL PERFORMANCE CHARACTERISTICS** 

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5VOUT Efficiency, 400kHz, FCM 12VOUT Efficiency, 400kHz, FCM 24VOUT Efficiency, 400kHz, FCM<br>97 98 99<br>94 See e 95 e 97<br>90 [Ae] 92 PETS 94<br>8783 tieWee} 8985 AAR 9290 YR<br>80 1 82 88<br>i 12VIN Poo 12VIN<br>76 12V24VININ 79 24V36VININ 85 24V36VININ<br>36VIN 5VIN 5VIN<br>73 aECC 76 oeCOO 83 ooEOE<br>0 2 4 6 8 10 12 0 2 4 6 8 10 12 0 2 4 6 8 10 12<br>LOAD CURRENT (A) LOAD CURRENT (A) LOAD CURRENT (A)<br>4712 G01 4712 G02 4712 G03<br>36VOUT Efficiency, 400kHz, FCM Transient Response, 5VIN to 12VOUT Transient Response, 12VIN to 12VOUT<br>99<br>97 =<br>VOUT (AC) VOUT (AC)<br>9492 atfe 500mV/DIV 500mV/DIV<br>IOUT  IOUT<br>9088 (caPO 2A/DIV 4712 G05 5A/DIV 4712 G06<br>12VIN 500μs/DIV 200μs/DIV<br>85 ro 24VIN fSW = 400kHz fSW = 400kHz<br>36VIN<br>5VIN<br>83 EC<br>0 2 4 6 8 10 12<br>LOAD CURRENT (A)<br>4712 G04<br>EFFICIENCY (%) EFFICIENCY (%) EFFICIENCY (%)<br>EFFICIENCY (%)<br>**----- End of picture text -----**<br>


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LTM4712 

## **TYPICAL PERFORMANCE CHARACTERISTICS** 

## **Transient Response, 36VIN to 12VOUT** 

**Two-Phase Parallel Operation Load Step (12VIN, 12VOUT)** 

**Two-Phase Parallel Operation Load Step (12VIN, 12VOUT)** 

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IMON1 IMON1<br>500mV/DIV 500mV/DIV<br>IMON2 IMON2<br>VOUT (AC) 500mV/DIV 500mV/DIV<br>500mV/DIV VOUT (AC) VOUT (AC)<br>500mV/DIV 500mV/DIV<br>IOUT  IOUT IOUT<br>5A/DIV 10A/DIV 10A/DIV<br>200μs/DIV 4712 G07 200μs/DIV 4712 G08 200μs/DIV 4712 G09<br>fSW = 400kHz fSW = 400kHz fSW = 400kHz<br>**----- End of picture text -----**<br>


## **Switching Waveforms (Buck Region)** 

## **Switching Waveforms (Buck-Boost Region)** 

## **Switching Waveforms (Boost Region)** 

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OUT (AC)(AC) VOUT (AC) VOUT (AC)<br>50mV/DIV 50mV/DIV<br>SW2 il SW2 SW2<br>20A/DIV i i 20A/DIV i 20A/DIV<br>SW1 SW1 SW1<br>20V/DIV 20V/DIV 20V/DIV<br>oN a SSeS<br>10μs/DIV 4712 G10 10μs/DIV 4712 G11 5μs/DIV 4712 G12<br>VIN = 24V, VOUT = 12V, IOUT = 12A, VIN = 12V, VOUT = 12V, IOUT = 12A, VIN = 10V, VOUT = 12V, IOUT = 6A,<br>fSW = 400kHz fSW = 400kHz fSW = 400kHz<br>Start-Up with 5VIN to 12VOUT, FCM Start-Up with 12VIN to 12VOUT, FCM Start-Up with 36VIN to 12VOUT, FCM<br>VRUN  VRUN  VRUN<br>5V/DIV 5V/DIV 5V/DIV<br>IIN  IIN  IIN<br>10A/DIV 10A/DIV 2A/DIV<br>VSS VSS VSS<br>1V/DIV 1V/DIV 1V/DIV<br>VOUT sesaesee==— VOUT saceccasen VOUT<br>10V/DIV 10V/DIV 10V/DIV<br>Se ee= soueaeene<br>1ms/DIV 4712 G13 1ms/DIV 4712 G14 1ms/DIV 4712 G15<br>IOUT = 6A IOUT = 12A IOUT = 12A<br>fSW = 400kHz fSW = 400kHz fSW = 400kHz<br>CSS = 10nF CSS = 10nF CSS = 10nF<br>**----- End of picture text -----**<br>


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VOUT (AC)(AC)<br>20mV/DIV<br>SW2<br>20A/DIV<br>SW1<br>20V/DIV<br>**----- End of picture text -----**<br>


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LTM4712 

## **TYPICAL PERFORMANCE CHARACTERISTICS** 

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Short-Circuit with 5VIN to 12VOUT,  Short-Circuit with 12VIN to 12VOUT,  Short-Circuit with 36VIN to 12VOUT,<br>No Load No Load No Load<br>IIN  IIN  IIN<br>5A/DIV 5A/DIV 5A/DIV<br>VOUT VOUT VOUT<br>5V/DIV 5V/DIV 5V/DIV<br>4712 G16 4712 G17 4712 G18<br>200μs/DIV 200μs/DIV 200μs/DIV<br>fSW = 400kHz fSW = 400kHz fSW = 400kHz<br>oes GS He<br>**----- End of picture text -----**<br>


## **PIN FUNCTIONS** 

**GND (Pins A1-G1, A2-G2, C3-M3, C4-M4, C5-J5, M5, E6-M6, E7-M7, C8-J8, M8, C9-M9, C10-M10, C11-G11, A12-G12):** Tie these GND pins to a local ground plane below the LTM4712 and the circuit components. In most applications, the bulk of the heat flow out of the LTM4712 is through these pads, so the printed circuit design has a large impact on the thermal performance of the part. See the PCB Layout and Thermal Considerations and Output Current Derating sections for more details. 

**ISP, ISN (Pins A3, A4):** Average Current Sensing Pins. The positive/negative inputs of the internal rail-to-rail average current sense amplifier. 

**IMON (Pin A5):** Input or Output Current Monitor. This feature is generally useful only if a current sense resistor is placed on input or output. ISP needs to be connected to the positive side, while ISN on the negative side. This pin produces a voltage that is proportional to the voltage across the sense resistor. IMON will equal 1.2V when VISP – VISN = 50mV. 

**CLKOUT (Pin A6):** Clock Output. Use this pin as a clock source when synchronizing other devices to the switching frequency of the LTM4712. When this function is not used, leave this pin open. See the Applications Information section for detailed parallel configuration. 

**FREQ (Pin A7):** Frequency Set Pin. A resistor between this pin and SGND sets the switching frequency. This pin sources 10μA current. 

**PGOOD (Pin A8):** Power Good Indicator Output for the Regulated Output Voltage. Open-drain logic out is pulled down to ground when the regulated output voltage exceeds ±10% regulation window with the internal 30μs delay. 

**PHMODE (Pin A9):** Phase Mode Program Pin. This pin sets the phase relationship between the internal oscillator clock and the output clock on the CLKOUT pin. Tying this pin to SGND sets 180 **°** phase shift, floating this pin sets 120 **°** phase shift and tying this pin to INTVCC sets 90 **°** phase shift. See the Applications Information section for details. 

**MODE (Pin A10):** Forced Continuous Mode (FCM) and Pulse-Skipping Mode. Tying this pin to GND enables FCM operation, otherwise the controller works in the pulse-skipping mode when MODE pin is floated. Do not tie to INTVCC or other voltage source. See the Applications Information section for details. 

**SS (Pin A11):** Soft-Start. Connect a capacitor from this pin to GND to increase the soft-start time. Soft-start reduces the input power source’s surge current by gradually increasing the controller’s current limit. Larger values of the soft-start capacitor result in longer soft-start times. See the Applications Information section. 

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LTM4712 

## **PIN FUNCTIONS** 

**INTVCC (Pin B3):** Internal 5V Regulator Output of the Switching Mode Regulator Channel. The internal control circuits are powered from this voltage. The LTM4712 has an internal 2.2μF decoupling capacitor connecting to SGND. 

**EXTVCC (Pin B4):** External Power Input to an Internal LDO powering the gate driver. When the voltage on this pin is greater than 8V and lower than the VIN pin voltage, this LDO bypasses the internal LDO powered from VIN. The LTM4712 has an internal 0.1μF decoupling capacitor. 

**ISET (Pin B5):** Average Current Regulation Pin. A resistor from this pin to SGND sets the maximum average input or output current sensed by the ISP and ISN pins. This pin sources 15μA current. See the Applications Information section. 

**SYNC (Pin B6):** External Synchronization Input. The SYNC pin has an internal pull-down resistor. See the Operating Frequency Selection and Phase-Locked Loop (FREQ, SYNC, PHMODE and CLKOUT Pins) section in Applications Information for details. Tie this pin to GND when not used. 

**RUN (Pin B8):** Enable Control Input. A voltage above 1.22V turns on the IC. There is a 2μA pull-up current on this pin. Once the RUN pin rises above the 1.22V threshold, the pull-up increases to 6μA. 

**COMPa (Pin B10):** Current control threshold and error amplifier compensation point of the switching mode regulator channel.  The internal current comparator threshold is linearly proportional to this voltage. Tie the COMPa pins from different channels together for parallel operation. The device is internally compensated. Connect to COMPb to use the internal compensation. Or connect to a Type-II C-R-C network to use customized compensation. 

**COMPb (Pin B11):** Internal Loop Compensation Network. Connect to COMPa to use the internal compensation in majority of applications. 

**SGND (Pins C6-D6, B7-D8):** Signal Ground Pin. Tie to GND with minimum distance. Connect all small signal components e.g., INTVCC, SS, FB, Comp, FREQ, etc. to SGND. 

**VIN (Pins H1-M1, H2-M2):** Power Input Pins. Apply input filter capacitors between these pins and GND pins. See the Applications Information section. 

**VOUT (Pins H11-M11, H12-M12):** Power Output Pins. Apply output filter capacitors between these pins and GND pins. See the Applications Information section. 

**SW1, SW2 (Pins K5-L5, K8-L8):** Switching Nodes of Buck Side or Boost Side that is Used for Testing Purposes. An R-C snubber network can be applied to reduce switch node ringing, or otherwise leave floating. 

**FB (Pin B9):** The Negative Input of the Error Amplifier for the Switching Mode Regulator. This pin is internally connected to VOUT with a 100k precision resistor. Output voltages can be programmed with an additional resistor between FB and SGND pins. 

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LTM4712 

## **BLOCK DIAGRAM** 

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SW1 4.7µH SW2<br>5V TOVIN CIN VIN M1 M2 M3 M4 VOUT COUT COUT V12VOUT<br>36V CIN 10µF 1µF 1µF 22μF 100µF<br>150µF ×4 ×3 ×2<br>RUN ISP<br>ISN<br>MODE<br>100k<br>INTVCC FB<br>C4.7uFINTVCC 2.2µF BUCK-BOOST CONTROLLER ISET 9.09kRFB<br>IMON<br>EXTVCC<br>FREQ<br>0.1µF<br>22nF RFREQ<br>140k<br>SS<br>CSS 100pF<br>10nF 6.04k<br>PGND SGND PGOOD SYNC PHMODE COMPa COMPb CLKOUT<br>4712 F01<br>**----- End of picture text -----**<br>


**Figure 1. LTM4712 Block Diagram** 

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LTM4712 

## **OPERATION** 

The LTM4712 is a standalone nonisolated buck-boost switching DC/DC power supply. The buck-boost topology allows the LTM4712 to regulate its output voltage for input voltages both above and below the magnitude of the output. The maximum output current depends upon the input voltage. Higher input voltages yield higher maximum output current. 

This converter provides a precisely regulated output voltage programmable via an external resistor divider from 1V to 36V. The input voltage range is 5V to 36V. See the Block Diagram (Figure 1). 

The LTM4712 contains a constant frequency, peak current mode controller, power switching elements, power inductor and a modest amount of input and output capacitance. The LTM4712 is a constant frequency PWM regulator. The operating frequency can be adjusted from 100kHz to 600kHz by connecting the appropriate resistor value from the FREQ pin to SGND. Alternatively, its frequency can be synchronized by an input clock signal on the SYNC pin. The typical switching frequency is 400kHz. 

The output voltage of the LTM4712 is set by connecting the FB pin to a resistor between FB pin and GND. 

In addition to regulating output voltage, the LTM4712 is equipped with average current control loops for either the input or output. Add a current sense resistor to limit the input or output current below maximum value. When the resistor is present, the IMON pin reflects the current flowing though the sense resistor between input or output. 

The LTM4712 features an integrated compensation network for most conditions. Some applications, however, benefit from a different compensation network. In such cases, apply an appropriate external compensation network for optimal and proper operation. 

If an external bias supply is applied on the EXTVCC pin, then an efficiency improvement occurs due to the reduced power loss in the internal linear regulator. This is especially true at the higher end of the input voltage range. 

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LTM4712 

## **APPLICATIONS INFORMATION** 

The typical LTM4712 application circuit is shown on the front page. External component selection is primarily determined by the input voltage, the output voltage, and the maximum load current. 

## **Output Voltage Programming** 

The PWM controller has an internal 1V reference voltage. A 100k internal feedback resistor connects VOUT and FB pins together. Adding a resistor RFB from the FB pin to GND programs the output voltage (see Equation 1). 

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## **Table 1. VFB Resistor Table vs Various Output Voltages** 

|**VOUT (V)**|**3.3**|**5**|**8**|**12**|**16**|**20**|**24**|**28**|
|---|---|---|---|---|---|---|---|---|
|RFB (k)|43.5|25|14.3|9.09|6.67|5.23|4.35|3.74|



For parallel operation of N-channels LTM4712, Equation 2 can be used to solve for RFB. 

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## **Operating Frequency Selection and Phase-Locked Loop (FREQ, SYNC, PHMODE and CLKOUT Pins)** 

The switching frequency of the LTM4712 can be selected using the FREQ pin. If the SYNC pin is not being driven by an external clock source, the FREQ pin is used to program the controller’s operating frequency from 100kHz to 600kHz. Switching frequency is determined by the voltage on the FREQ pin. Since there is a precision 10μA current flowing out of the FREQ pin, program the controller’s switching frequency with a single resistor to SGND (e.g., the FREQ pin voltage is 1.58V with 158k resistor from the FREQ pin to SGND). Table 2 provides a list of RT resistor values and their resultant frequencies. 

**Table 2. Switching Frequency vs RT Value** 

|**Table 2. Switching Frequency vs**|**RT Value**|
|---|---|
|**FREQUENCY**<br>**(kHz)**|**RT VALUE**<br>**(kΩ)**|
|100|58|
|200|80|
|300|120|
|400|140|
|500|170|
|600|200|



A phase-locked loop (PLL) is integrated to synchronize the internal oscillator to an external clock source driving the SYNC pin. The PLL is capable of locking to any frequency within the range of 100kHz to 600kHz. The frequency setting resistor at FREQ pin should always be present to set the controller’s initial switching frequency before locking to the external clock or in any cases the external clock is missing during the operation. The CLKOUT pin is a clock signal output with the same frequency as the internal oscillator with phase shift programmed by the PHMODE pin. It can be used in multi-IC parallel applications by passing the clock signal of the first IC to the SYNC pin of the second IC for frequency synchronization. The phase shift can be programmed based on Table 3. 

**Table 3. PHMODE Setting vs CLKOUT Phase Shift** 

|**PHMODE PIN**|**CLKOUT PHASE SHIFT REFERS TO**<br>**THE INTERNAL OSCILLATOR**|
|---|---|
|SGND|180**°**|
|FLOAT|120**°**|
|INTVCC|90**°**|



## **Input Decoupling Capacitors** 

In boost mode, since the input current is continuous, only minimum input capacitors are required. However, the input current is discontinuous in buck mode. So the selection of input capacitor CIN is driven by the need of filtering the input square wave current. 

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LTM4712 

## **APPLICATIONS INFORMATION** 

Without considering the inductor current ripple, the RMS current of the input capacitor can be estimated with Equation 3. 

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where η is the estimated efficiency of the power module. The formula has a maximum at D = 0.5 or VIN = 2VOUT, where IIN(RMS) = IOUT(MAX)/2. This simple worst-case condition is commonly used for design. 

## **Output Decoupling Capacitors** 

Discontinuous current shifts from the input to the output in the boost region. Make sure that the COUT capacitor network is capable of reducing the output voltage ripple. The effects of ESR and the bulk capacitance must be considered when choosing the right capacitor for a given output ripple voltage. The maximum steady state ripple due to charging and discharging the bulk capacitance is given by Equation 4. 

**==> picture [240 x 66] intentionally omitted <==**

The maximum steady ripple due to the voltage drop across the ESR is given by Equation 5. 

**==> picture [240 x 65] intentionally omitted <==**

The bulk output capacitors defined as COUT are chosen with low enough ESR to meet the output voltage ripple and transient requirements. COUT can be the low ESR tantalum capacitor, the low ESR polymer capacitor, or the ceramic capacitor. Multiple capacitors can be placed in parallel to meet the ESR and RMS current handling requirements. The typical capacitance is 10μF. Additional output filtering may be required by the system designer, if further reduction of output ripple or dynamic transient spike is required. 

## **Power Good (PGOOD Pin)** 

The PGOOD pin is connected to the open-drain of an internal N-channel MOSFET. When VFB is not within ±10% of the 1.0V reference voltage, the PGOOD pin is pulled low. The PGOOD pin is also pulled low when RUN is below 1.22V or when the LTM4712 is in the soft-start phase. There is an internal 30μs delay when VFB goes in or out of the ±10% window. The PGOOD pin can be pulled up by an external resistor to INTVCC or an external source of up to 6V. 

## **Low Current Operation (MODE Pin)** 

In applications where fixed frequency operation is more critical than low current efficiency, and where the lowest output ripple is desired, forced continuous operation should be used. Forced continuous operation is enabled by tying the MODE pin to GND. In this mode, inductor current is allowed to reverse during low output loads, the COMP voltage is in control of the current comparator threshold throughout. During start-up, forced continuous mode is disabled and inductor current is prevented from reversing until the LTM4712’s output voltage is in regulation. 

In applications where high efficiency at intermediate current are more important than output voltage ripple, pulse-skipping mode of operation can be selected by floating the MODE pin to improve light load efficiency. 

## **Constant Current Regulation (ISP, ISN, and ISET Pins)** 

The LTM4712 provides a constant-current regulation loop for either input or output average current. A sensing resistor close to the input or output capacitor can be used to sense the input or output current. Because the input or output current may be a pulse current in the different operation regions, an RC filter has to be applied on ISP and ISN pins for average current sensing. When the voltage on the current sensing resistor exceeds the programmed current limit, the voltage on the COMP pin is pulled low to decrease the inductor current and maintain the desired maximum input or output current. The current limit may be set by the voltage on the ISET pin from 0.2V to 1.2V corresponding to the linearly 0mV to 50mV across the sensing resistor. There is a 15µA current out of the 

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## **APPLICATIONS INFORMATION** 

ISET pin if the ISET pin is float or ISET pin voltage higher than 1.2V, the current limit is clamped at 50mV internally. The input current limit function prevents overloading the DC input source, while the output current limit provides - a building block for battery charger or LED driver applica tions. It can also serve as an extra current limit protection for a constant-voltage regulation application. The input/ output current limit function has an operating voltage range of GND to the absolute maximum VOUT/VIN (36V). 

## **Output Current Monitor (IMON)** 

The IMON pin produces a voltage proportional to the voltage of ISP–ISN. When VISP – VISN = 0mV, IMON is 0.2V. When VISP–VISN = 50mV, IMON is 1.2V. 

## **Soft-Start Function** 

When a capacitor is connected to the SS pin, a soft-start current of 2.5μA starts to charge the capacitor. A softstart function is achieved by controlling the output ramp voltage according to the ramp rate on the SS pin. Current foldback is disabled during this phase to ensure smooth soft-start. When the chip is in the shutdown state with its RUN pin voltage below 1.22V, the SS pin is actively pulled to ground. The soft-start range is defined to be the voltage range from 0V to 1.0V on the SS pin. The total soft-start time can be calculated with Equation 6. 

**==> picture [239 x 27] intentionally omitted <==**

Regardless of the mode selected by the MODE pin, the regulator always starts in pulse-skipping mode up to SS = 1.0V. 

## **Run Enable** 

The RUN pin is used to enable the power module. The pin can be driven with a logic input, not to exceed 12V. The RUN pin can also be used as an undervoltage lockout (UVLO) function by connecting a resistor from the input supply to the RUN pin. Increasing the RUN pin voltage above 1.22V turns on the entire chip. 

## **Stability Compensation** 

The LTM4712 has already been internally optimized and compensated for all output voltages and capacitor combinations including all ceramic capacitor applications when COMPb is tied to COMPa. For specific optimized requirement, disconnect COMPb from COMPa and apply a Type II C-R-C compensation network from COMPa to GND to achieve external compensation. The LTpowerCAD[®] design tool is available to download on-line to perform specific control loop optimization and analyze the control stability and load transient performance. 

## **Fault Conditions: Current Limit and Current Foldback** 

The maximum inductor current is inherently limited in a peak current mode controller with a 20A maximum current limit. 

To promote limit current in the event of a short-circuit to ground, the LTM4712 includes foldback current limiting. If the output falls by more than 40%, then the maximum current is progressively lowered to about 4A. 

## **Parallel Operations** 

For output loads that demand high current, multiple LTM4712s can be paralleled with interleaving to provide more output current without increasing input and output voltage ripple. The SYNC pin allows the LTM4712 to synchronize to the CLKOUT signal of another LTM4712. The CLKOUT signal can be connected to the SYNC pin of the following LTM4712 stage to line up both the frequency and the phase of the entire system. Tying the PHMODE pin to GND, floating or INTVCC generates a phase difference (between SW1 and CLKOUT) of 180°, 120° or 90°, respectively for 2, 3, or 4 ICs parallel operations. 

When designing multiple ICs parallel operations, always start from the single LTM4712 design and check the output current capability and load current transient stability. Then the LTM4712s can be paralleled by making the following connections: 

- Tie all VFB pins together 

- Tie all COMP pins together (assuming COMPa short to COMPb for initial debug) 

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## **APPLICATIONS INFORMATION** 

- Tie all SS pins together 

- Tie all RUN pins together 

- Tie all converter inputs together 

- Tie all converter outputs together 

- Route one IC’s CLKOUT to another IC’s SYNC pin 

Refer to the Figure 24 section for an example of a 2-phase parallel operation design. 

The LTM4712 can also be paralleled from different input voltages for a redundancy design. Do not tie SS and RUN pins of the LTM4712s together so each LTM4712 can start up with different input voltages to supply current to a single output. Any one input voltage failure does not affect the output voltage regulation as long as the other input sources supply enough load current. The peak inductor currents are shared among all the buck-boost converters by tying all the COMP pins together. In the redundancy design, it is suggested that each LTM4712 has its own compensation network and feedback resistor locally closed to the pin and then short the FB pins and COMP pins all together with PCB traces. 

## **Thermal Considerations and Output Current Derating** 

The thermal resistances reported in the Pin Configuration section are consistent with those parameters defined by JESD 51-9 and are intended for use with finite element analysis (FEA) software modeling tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation performed on a μModule package mounted to a hardware test board—also defined by JESD 51-9 (“Test Boards for Area Array Surface Mount Package Thermal Measurements”). The motivation for providing these thermal coefficients is found in JESD 51-12 (“Guidelines for Reporting and Using Electronic Package Thermal Information”). 

Many designers may opt to use laboratory equipment and a test vehicle such as the demo board to anticipate the μModule regulator’s thermal performance in their application at various electrical and environmental operating conditions to compliment any FEA activities. Without FEA software, the thermal resistances reported in the Pin Configuration section are not relevant to providing guidance of thermal performance; instead, the derating 

curves provided in the data sheet can be used in a manner that yields insight and guidance pertaining to application usage and can be adapted to correlate thermal performance to application itself. 

The Pin Configuration section typically gives four thermal coefficients explicitly defined in JESD 51-12; these coefficients are quoted or paraphrased below: 

1. θ JA, the thermal resistance from junction to ambient, is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclosure. This environment is sometimes referred to as “still air” although natural convection causes the air to move. This value is determined with the part mounted to a JESD 51-9 defined test board, which does not reflect an actual application or viable operating condition. 

2. θ JCbottom, the thermal resistance from junction to the bottom of the product case, is the junction-to-board thermal resistance with all of the component power dissipation flowing through the bottom of the package. In the typical μModule, the bulk of the heat flows out the bottom of the package, but there is always heat flow out into the ambient environment. As a result, this thermal resistance value may be useful for comparing packages, but the test conditions do not generally match the application. 

3. θ JCtop, the thermal resistance from junction to top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. As the electrical connections of the typical μModule are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. As in the case of θ JCbottom, this value may be useful for comparing packages, but the test conditions do not generally match the application. 

4. θ JB, the thermal resistance from junction to the printed circuit board, is the junction-to-board thermal resistance where almost all of the heat flows through the bottom of the μModule and into the board and is really the sum of the θ JCbottom and the thermal resistance of the bottom of the part through the solder joints and through a portion of the board. 

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## **APPLICATIONS INFORMATION** 

A graphical representation of the aforementioned thermal resistances is given in Figure 2; blue resistances are contained within the μModule regulator, whereas green resistances are external to the μModule. 

As a practical matter, it should be clear that no individual or sub-group of the four thermal resistance parameters defined by JESD 51-12 or provided in the Pin Configuration section replicates or conveys normal operating conditions of a μModule. For example, in normal board-mounted applications, never does 100% of the device’s total power loss (heat) thermally conduct exclusively through the top or exclusively through bottom of the μModule—as the standard defines for θ JCtop and θ JCbottom, respectively. In practice, power loss is thermally dissipated in both directions away from the package. Granted, in the absence of a heat sink and airflow, a majority of the heat flow is into the board. 

Within a SIP (system-in-package) module, be aware there are multiple power devices and components dissipating power, with a consequence that the thermal resistances relative to different junctions of components or die are not exactly linear with respect to total package power loss. To reconcile this complication without sacrificing modeling simplicity—but also, not ignoring practical realities—an approach has been taken using FEA software modeling along with laboratory testing in a controlled-environment chamber to reasonably define and correlate the thermal resistance values supplied in this data sheet: (1) Initially, FEA software is used to accurately build the mechanical geometry of the μModule and the specified PCB with all of the correct material coefficients along with accurate power loss source definitions; (2) this model simulates a software-defined JEDEC environment consistent with JSED 51-9 to predict power loss heat flow. 

**==> picture [502 x 154] intentionally omitted <==**

**----- Start of picture text -----**<br>
μModule DEVICE θJA, JUNCTION-TO-AMBIENT RESISTANCE<br>θJCtop, JUNCTION-TO-CASE (TOP) CASE (TOP)-TO-AMBIENT<br>RESISTANCE RESISTANCE<br>JUNCTION θJB, JUNCTION-TO-BOARD RESISTANCE AMBIENT<br>θJCbot, JUNCTION-TO-CASE CASE (BOTTOM)-TO-BOARD BOARD-TO-AMBIENT<br>(BOTTOM) RESISTANCE RESISTANCE RESISTANCE<br>4712 F02<br>**----- End of picture text -----**<br>


**Figure 2. Graphical Representation of Thermal Coefficients, Including JESD51-12 Terms** 

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## **APPLICATIONS INFORMATION** 

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6 6<br>5 5<br>4 4<br>3 3<br>2 2<br>12VIN<br>1 12VIN 1 24VIN<br>24VIN 36VIN<br>36VIN 5VIN<br>0 0<br>0 2 4 6 8 10 12 0 2 4 6 8 10 12<br>LOAD CURRENT (A) LOAD CURRENT (A)<br>4712 F03 4712 F04<br>Figure 3. Power Loss 5VOUT,  Figure 4. Power Loss 12VOUT,<br>400kHz, FCM 400kHz, FCM<br>8 11<br>7<br>9<br>6<br>5<br>7<br>4<br>4<br>3<br>2 12V IN 12VIN<br>24VIN 2 24V IN<br>1 36V IN 36VIN<br>5VIN 5VIN<br>0 0<br>0 2 4 6 8 10 12 0 2 4 6 8 10 12<br>LOAD CURRENT (A) LOAD CURRENT (A)<br>4712 F05 4712 F06<br>Figure 5. Power Loss  Figure 6. Power Loss 36VOUT,<br>24VOUT, 400kHz, FCM 400kHz, FCM<br>14 14 14<br>12 12 12<br>10 10 10<br>8 8 8<br>6 6 6<br>4 4 4<br>0LFM 0LFM 0LFM<br>2 2 2<br>200LFM 200LFM 200LFM<br>400LFM 400LFM 400LFM<br>0 0 0<br>25 45 65 85 105 125 25 45 65 85 105 125 25 45 65 85 105 125<br>AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)<br>4712 F07 4712 F08 4712 F09<br>Figure 7. 36VIN to 5VOUT,  Figure 8. 24VIN to 5VOUT, 400kHz,  Figure 9. 12VIN to 5VOUT,<br>400kHz, Derating Curve,   Derating Curve, No Heat Sink 400kHz, Derating Curve,<br>No Heat Sink No Heat Sink<br>Rev. 0<br>POWER LOSS (W) POWER LOSS (W)<br>POWER LOSS (W) POWER LOSS (W)<br>MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A)<br>**----- End of picture text -----**<br>


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## LTM4712 

## **APPLICATIONS INFORMATION** 

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14 14 14<br>12 12 12<br>10 10 10<br>8 8 8<br>6 6 6<br>4 4 4<br>0LFM 0LFM 0LFM<br>2 2 2<br>200LFM 200LFM 200LFM<br>400LFM 400LFM 400LFM<br>0 0 0<br>25 45 65 85 105 125 25 45 65 85 105 125 25 45 65 85 105 125<br>AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)<br>4712 F10 4712 F11 4712 F12<br>Figure 10. 36VIN to 12VOUT,  Figure 11. 24VIN to 12VOUT,  Figure 12. 12VIN to 12VOUT,<br>400kHz, Derating Curve,   400kHz, Derating Curve,   400kHz, Derating Curve,<br>No Heat Sink No Heat Sink No Heat Sink<br>8 14 14<br>12 12<br>6<br>10 10<br>8 8<br>4<br>6 6<br>4 4<br>2<br>0LFM 0LFM 0LFM<br>2 2<br>200LFM 200LFM 200LFM<br>400LFM 400LFM 400LFM<br>0 0 0<br>25 45 65 85 105 125 25 45 65 85 105 125 25 45 65 85 105 125<br>AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)<br>4712 F13 4712 F14 4712 F15<br>Figure 13. 5VIN to 12VOUT,  Figure 14. 36VIN to 24VOUT,  Figure 15. 24VIN to 24VOUT,<br>400kHz, Derating Curve,   400kHz, Derating Curve,   400kHz, Derating Curve,<br>No Heat Sink No Heat Sink No Heat Sink<br>8 4 14<br>12<br>6 3<br>10<br>8<br>4 2<br>6<br>4<br>2 1<br>0LFM 0LFM 0LFM<br>2<br>200LFM 200LFM 200LFM<br>400LFM 400LFM 400LFM<br>0 0 0<br>25 45 65 85 105 125 25 45 65 85 105 125 25 45 65 85 105 125<br>AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)<br>4712 F16 4712 F17 4712 F18<br>Figure 16. 12VIN to 24VOUT,  Figure 17. 5VIN to 24VOUT, 400kHz,  Figure 18. 36VIN to 36VOUT,<br>400kHz, Derating Curve,   Derating Curve, No Heat Sink 400kHz, Derating Curve,<br>No Heat Sink No Heat Sink<br>Rev. 0<br>MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A)<br>MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A)<br>MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A)<br>**----- End of picture text -----**<br>


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## **APPLICATIONS INFORMATION** 

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10 5 3<br>8 4<br>2<br>6 3<br>4 2<br>1<br>2 1<br>0LFM 0LFM 0LFM<br>200LFM 200LFM 200LFM<br>400LFM 400LFM 400LFM<br>0 0 0<br>25 45 65 85 105 125 25 45 65 85 105 125 25 45 65 85 105 125<br>AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)<br>4712 F19 4712 F20 4712 F21<br>MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A)<br>**----- End of picture text -----**<br>


**Figure 19. 24VIN to 36VOUT, 400kHz, Derating Curve, No Heat Sink** 

**Figure 20. 12VIN to 36VOUT, 400kHz, Derating Curve, No Heat Sink** 

**Figure 21. 5VIN to 36VOUT, 400kHz, Derating Curve, No Heat Sink** 

## **PCB Layout** 

The high integration of LTM4712 makes the PCB layout very simple and easy. However, to optimize its electrical and thermal performance, the following layout considerations are still necessary: 

- Use large PCB copper areas for high current path, including VIN, GND, and VOUT. It helps to minimize the PCB conduction loss and thermal stress. 

- Place high-frequency input and output ceramic capacitors next to the VIN, GND, and VOUT pins to minimize high frequency noise. 

- Place a dedicated power ground layer underneath the unit. 

- To minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between the top layer and other power layers. 

- Do not put vias directly on pads, unless the vias are capped. 

- Use a separated SGND ground copper area for components connected to the signal pins. Connect the SGND to PGND underneath the unit. 

Figure 22 gives a good example of the recommended PCB layout. 

**==> picture [522 x 155] intentionally omitted <==**

**----- Start of picture text -----**<br>
GND GND<br>GND GND<br>C26 C2 C5 C7 C1 C21 C31 C33 C19<br>C19 C20<br>C37 C28<br>C15 C29<br>VIN VOUT VIN C27 C30 VOUT<br>GND GND<br>4712 F22a 4712 F22b<br>(a) LTM4712 Top Layer (b) LTM4712 Bottom Layer<br>**----- End of picture text -----**<br>


**Figure 22. Recommended PCB Layout** 

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## **APPLICATIONS INFORMATION** 

## **Table 4. Bulk and Ceramic Capacitor Manufacturers** 

|**Table 4. Bulk and Ceramic Capacitor Manufacturers**|**Table 4. Bulk and Ceramic Capacitor Manufacturers**|**Table 4. Bulk and Ceramic Capacitor Manufacturers**||||
|---|---|---|---|---|---|
|**CIN (BULK)**|||**COUT (BULK)**|||
|**VENDORS**|**VALUE**|**PART NUMBER**|**VENDORS**|**VALUE**|**PART NUMBER**|
|Panasonic|150μF, 50V|EEEFK1H151P|Panasonic|100μF, 16V|16TQC100MYF|
|**CIN (CERAMIC)**|||**COUT (CERAMIC)**|||
|**VENDORS**|**VALUE**|**PART NUMBER**|**VENDORS**|**VALUE**|**PART NUMBER**|
|AVX|0.1μF, 50V, 0805, X7R|08055C104KAT2A|AVX|0.1μF, 50V, 0805, X7S|08055C104KAT2A|
|Murata|10μF, 50V, 1210, X7R|GRM32ER71H106KA12L|TDK|22μF, 100V, 1210, X7R|C3225X7R1C226K250AC|



**Table 5. Component Selection Table for Typical LTM4712 Applications** 

|**VIN**<br>**(V)**|**VOUT**<br>**(V)**|**CIN (BULK)**<br>**(μF)**|**CIN (CERAMIC)**<br>**(μF)**|**COUT (BULK)**<br>**(μF)**|**COUT (CERAMIC)**<br>**(μF)**|**RFB**<br>**(kΩ)**|**RFREQ**<br>**(kΩ)**|
|---|---|---|---|---|---|---|---|
|12|12|150|10 ×4|100|22 ×4|9.09|140|
|24|12|150|10 ×4|100|22 ×4|9.09|140|
|36|12|150|10 ×4|100|22 ×4|9.09|140|
|24|24|150|10 ×4|82|10 ×8|4.32|140|
|12|36|150|10 ×4|330 ×2|10 ×8|2.87|140|
|12|5|150|10 ×4|100|22 ×4|25|140|



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## **TYPICAL APPLICATIONS** 

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2mΩ<br>5V TO36VVIN + 150µF 10µF×4 VIN EXTVVOUTCC 100µF×2 100µF V12VOUT<br>RUN<br>FB<br>SS 9.09k 100Ω 100Ω<br>10nF<br>MODE LTM4712 ISP<br>1µF<br>INTVCC ISN<br>100k 2.2µF<br>PGOOD COMPa<br>FREQ COMPb PINS NOT USED IN THIS CIRCUIT:<br>IMON<br>140k SYNC GND PHMODE ISET<br>4712 F23 CLKOUT<br>Figure 23. 12VOUT with Wide Input Voltage Range, 12A IOUT for Buck/Buck-Boost, 6A IOUT for Boost<br>VIN VIN VOUT VOUT<br>5V TO 150µF 10µF 100µF 12V,<br>36V ×2 ×6 RUN EXTVCC ×6 UP TO<br>24A<br>SS FB<br>9.09k<br>10nF<br>MODE<br>ISP<br>LTM4712<br>ISN<br>INTVCC<br>2.2µF COMPa<br>COMPb<br>FREQ CLKOUT<br>140k SYNC GND PHMODE<br>VIN VOUT<br>RUN EXTVCC<br>SS FB<br>9.09k<br>MODE<br>ISP<br>LTM4712<br>ISN<br>INTVCC<br>2.2µF COMPa<br>COMPb<br>PINS NOT USED<br>FREQ CLKOUT IN THIS CIRCUIT:<br>140k SYNC GND PHMODE IMON<br>4712 F24 ISET<br>PGOOD<br>**----- End of picture text -----**<br>


**Figure 24. 2** × **LTM4712 Parallel to Provide Up to 24A Output Current** 

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2mΩ<br>VIN VIN VOUT VOUT<br>10V TO36V 150µF 10µF×4 RUN EXTVCC 1µF 22µF×6 100µF×2 12V,48A<br>IMON<br>FB VFB<br>VSS SS 2.26k<br>0.1µF<br>MODE LTM4712 ISP<br>1000pF<br>INTVCC ISN<br>100k 2.2µF COMPa COMP<br>COMPb<br>PGOOD<br>SYNC<br>FREQ<br>158k PHMODE GND CLKOUT<br>2mΩ<br>VIN VOUT<br>150µF 10µF×4 RUN EXTVCC 22µF×6 100µF×2<br>1µF<br>IMON<br>VSS SS FB VFB<br>0.1µF<br>MODE LTM4712 ISP 1000pF<br>ISN<br>INTVCC<br>100k 2.2µF COMPa COMP<br>COMPb<br>PGOOD<br>SYNC<br>FREQ<br>158k PHMODE GND CLKOUT<br>2mΩ<br>VIN VOUT<br>1 50µF 10µF×4 RUN EXTVCC 22µF×6 100µF×2<br>1µF<br>IMON<br>VSS SS FB VFB<br>0.1µF<br>ISP<br>MODE LTM4712<br>1000pF<br>ISN<br>INTVCC<br>100k 2.2µF COMPa COMP<br>COMPb<br>PGOOD<br>SYNC<br>FREQ<br>158k PHMODE GND CLKOUT<br>2mΩ<br>VIN VOUT<br>150µF 10µF×4 RUN EXTVCC 22µF×6 100µF×2<br>1µF<br>IMON<br>VSS SS FB VFB<br>0.1µF ISP<br>MODE LTM4712<br>ISN 1000pF<br>INTVCC<br>100k 2.2µF COMPa COMP<br>PGOOD COMPb PINS NOT USED<br>SYNC IN THIS CIRCUIT:<br>FREQ ISET<br>158k PHMODE GND CLKOUT SEE EVAL-LTM4712-AZ EVALUATION<br>4712 F25 KIT FOR DETAILED DESIGN.<br>**----- End of picture text -----**<br>


**Figure 25. 4** × **LTM4712 in Parallel to Provide Up to 48A Output Current** 

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## **TYPICAL APPLICATIONS** 

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VIN1 VIN VOUT VOUT<br>5V TO<br>36V 150µF 10µF×4 EXTVCC 100µF 12V,UP TO<br>RUN ×6<br>24A<br>FB<br>9.09k<br>SS<br>10nF<br>MODE LTM4712 ISP<br>ISN<br>INTVCC<br>2.2µF COMPa<br>COMPb<br>FREQ CLKOUT<br>140k SYNC GND PHMODE<br>VIN2 VIN VOUT<br>5V TO 10µF<br>36V 150µF ×4 RUN EXTVCC<br>FB<br>9.09k<br>SS<br>10nF<br>ISP<br>MODE LTM4712<br>ISN<br>INTVCC<br>2.2µF COMPa<br>COMPb<br>FREQ CLKOUT PINS NOT USED<br>IN THIS CIRCUIT:<br>140k SYNC GND PHMODE IMON<br>4712 F26 ISET<br>PGOOD<br>**----- End of picture text -----**<br>


**Figure 26. Input Redundancy Application Circuit** 

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## **TYPICAL APPLICATIONS** 

**==> picture [487 x 430] intentionally omitted <==**

**----- Start of picture text -----**<br>
2mΩ<br>VIN VIN VOUT<br>24V 150μF 10μF 0.1μF 22μF<br>×2 ×4 ×2 RUN EXTVCC 100μF ×6 OPTIONAL<br>IMON ×2 –VOUT<br>FB<br>–12V,<br>SS 9.09k 100k 100k 10A<br>10nF<br>MODE LTM4712 –VOUT<br>ISP<br>INTVCC 1μF<br>ISN<br>2.2μF<br>COMPa PINS NOT USED<br>IN THIS CIRCUIT:<br>FREQ COMPb PINS NOT USED IN THIS CIRCUIT: CLKOUT<br>ISET<br>ISET<br>140k SYNC GND PHMODE CLKOUT PGOOD<br>4712 F27<br>Figure 27. Inverting Configuration Example for 24VIN,  – 12VOUT<br>5mΩ<br>8V TO24VVIN + 150µF 10µF×4 VRUNIN EXTVVOUTCC 100µF×2 100µF 1Ω V10AOUT<br>IMON FB<br>SS 9.09k 100k 100k<br>10nF<br>MODE LTM4712 ISP<br>1µF<br>INTVCC ISN<br>100k 2.2µF<br>PGOOD COMPa<br>FREQ COMPb PINS NOT USED IN THIS CIRCUIT:<br>ISET<br>140k SYNC GND PHMODE CLKOUT<br>4712 F28<br>**----- End of picture text -----**<br>


**Figure 28. Application Circuit for 10A Constant Load Current** 

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LTM4712 

## **PACKAGE DESCRIPTION** 

**Table 6. LTM4712 Pin Assignment (Arranged by Pin Number)** 

|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|A1|GND|B1|GND|C1|GND|D1|GND|E1|GND|F1|GND|
|A2|GND|B2|GND|C2|GND|D2|GND|E2|GND|F2|GND|
|A3|ISN|B3|INTVCC|C3|GND|D3|GND|E3|GND|F3|GND|
|A4|ISP|B4|EXTVCC|C4|GND|D4|GND|E4|GND|F4|GND|
|A5|IMON|B5|ISET|C5|GND|D5|GND|E5|GND|F5|GND|
|A6|CLKOUT|B6|SYNC|C6|SGND|D6|SGND|E6|GND|F6|GND|
|A7|FREQ|B7|SGND|C7|SGND|D7|SGND|E7|GND|F7|GND|
|A8|PGOOD|B8|RUN|C8|GND|D8|GND|E8|GND|F8|GND|
|A9|PHMODE|B9|FB|C9|GND|D9|GND|E9|GND|F9|GND|
|A10|MODE|B10|COMPa|C10|GND|D10|GND|E10|GND|F10|GND|
|A11|SS|B11|COMPb|C11|GND|D11|GND|E11|GND|F11|GND|
|A12|GND|B12|GND|C12|GND|D12|GND|E12|GND|F12|GND|
|G1|GND|H1|VIN|J1|VIN|K1|VIN|L1|VIN|M1|VIN|
|G2|GND|H2|VIN|J2|VIN|K2|VIN|L2|VIN|M2|VIN|
|G3|GND|H3|GND|J3|GND|K3|GND|L3|GND|M3|GND|
|G4|GND|H4|GND|J4|GND|K4|GND|L4|GND|M4|GND|
|G5|GND|H5|GND|J5|GND|K5|SW1|L5|SW1|M5|GND|
|G6|GND|H6|GND|J6|GND|K6|GND|L6|GND|M6|GND|
|G7|GND|H7|GND|J7|GND|K7|GND|L7|GND|M7|GND|
|G8|GND|H8|GND|J8|GND|K8|SW2|L8|SW2|M8|GND|
|G9|GND|H9|GND|J9|GND|K9|GND|L9|GND|M9|GND|
|G10|GND|H10|GND|J10|GND|K10|GND|L10|GND|M10|GND|
|G11|GND|H11|VOUT|J11|VOUT|K11|VOUT|L11|VOUT|M11|VOUT|
|G12|GND|H12|VOUT|J12|VOUT|K12|VOUT|L12|VOUT|M12|VOUT|



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LTM4712 

## **PACKAGE DESCRIPTION** 

**==> picture [439 x 589] intentionally omitted <==**

**----- Start of picture text -----**<br>
2× aaa Z<br>PACKAGE TOP VIEW<br>6<br>3<br>SEE NOTES PIN 1<br>A B C D E F G H J K L M SEE NOTES<br>1<br>2<br>DETAIL A<br>3<br>e<br>4<br>5<br>6<br>G<br>7<br>8<br>9 PACKAGE BOTTOM VIEW LTMXXXX µModule<br>10<br>PACKAGE ROW AND COLUMN LABELING MAY VARY  AMONG µModule PRODUCTS. REVIEW EACH PACKAGE  LAYOUT CAREFULLY<br>11 b PACKAGE IN TRAY LOADING ORIENTATION<br>!<br>DETAILS OF PIN 1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN 1 IDENTIFIER MAY BE EITHER A MOLD OR  MARKED FEATURE<br>12<br>b e NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS 3        BALL DESIGNATION PER JEP95 4 5. PRIMARY DATUM -Z- IS SEATING PLANE 6 PIN 1 BEVEL<br>F TRAY PIN 1<br>COMPONENT<br>A2<br>DETAIL B<br>A NOTES BALL HT BALL DIMENSION PAD DIMENSION SUBSTRATE THK MOLD CAP HT INDUCTOR HT<br>H3 MAX 8.68  0.70 1.94 0.80 0.66 0.15 0.20 0.30 0.15 0.35<br>PACKAGE SIDE VIEW<br>DIMENSIONS NOM 8.34 0.60 1.84 0.75 0.63 16.00 16.00 1.27 13.97 13.97<br>Y 0.34 REF 1.50 REF 6.05 REF<br>X<br>Z Z<br>H1 M M MIN 8.00 0.50 1.74 0.70 0.60 TOTAL NUMBER OF BALLS: 144<br>A1 SUBSTRATE ddd eee<br>(16mm × 16mm × 8.34mm) (Reference DWG # 05-08-7078) ccc Z b1 MOLD CAP H2 DETAIL B DETAIL A SYMBOL A A1 A2 b b1 D E e F G H1 H2 H3 aaa ccc ddd eee fff<br>Øb (144 PLACES)<br>0.0000<br>6.9850 5.7150 4.4450 3.1750 1.9050 0.6350 0.6350 1.9050 3.1750 4.4450 5.7150 6.9850<br>144-Ball Chip Scale Package Ball Grid Array [CSP_BGA]<br>D<br>14.20 REF TOP VIEW<br>SUGGESTED PCB LAYOUT<br>13.20 REF X<br>aaa Z PIN 1 CORNER 4 E Y 0.630 REF Ø 144x<br>2×<br>07-20-2023-B<br>Z<br>// fff Z<br>Z<br>6.9850<br>5.7150<br>4.4450<br>3.1750<br>1.9050<br>0.6350<br>0.0000<br>0.6350<br>1.9050<br>3.1750<br>4.4450<br>5.7150<br>6.9850<br>PKG-007660<br>**----- End of picture text -----**<br>


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LTM4712 

## **REVISION HISTORY** 

|**REV**|**DATE**|**DESCRIPTION**|**PAGE NUMBER**|
|---|---|---|---|
|0|10/23|Initial Release.|—|



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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implicatiFor more informati **on** or otherwise under any patent or patent rights of Analog Devices.www.analog.com 

LTM4712 

## **PACKAGE PHOTOS** 

## **Part marking is either ink mark or laser mark** 

## **DESIGN RESOURCES** 

|**DESIGN RESOURCES**|||
|---|---|---|
|**SUBJECT**|**DESCRIPTION**||
|µModule Design and Manufacturing Resources|Design:<br>• Selector Guides<br>• Demo Boards and Gerber Files<br>• Free Simulation Tools|Manufacturing:<br>• Quick Start Guide<br>• PCB Design, Assembly and Manufacturing Guidelines<br>• Package and Board Level Reliability|
|µModule Regulator Products Search|1.  Sort table of products by parameters and download the result as a spread sheet.<br>2. Search using the Quick Power Search parametric table.<br>INPUT<br>|<br>Vin(Min)<br>Vv<br>Vin(Max)<br>Vv<br>OUTPUT |<br>Vout<br>Vv<br>Jout<br>A<br>FEATURES |<br>Low EMI<br>Ultrathin<br>Internal Heat Sink||
|Digital Power System Management|Analog Devices’ family of digital power supply management ICs are highly integrated solutions that<br>offer essential functions, including power supply monitoring, supervision, margining and sequencing,<br>and feature EEPROM for storing user configurations and fault logging.||



## **RELATED PARTS** 

|**RELATED PARTS**|**RELATED PARTS**||
|---|---|---|
|**PART NUMBER**|**DESCRIPTION**|**COMMENTS**|
|LTM4605|20VIN, 20VOUT, 12A Buck-Boost µModule Regulator<br>with External Inductor|4.5V ≤ VIN≤ 20V, 0.8V ≤ VOUT≤ 16V, 15mm × 15mm × 2.82mm LGA|
|LTM4607|36VIN, 24VOUT, 10A Buck-Boost µModule Regulator<br>with External Inductor|4.5V ≤ VIN≤ 36V, 0.8V ≤ VOUT≤ 24V, 15mm × 15mm × 2.82mm LGA|
|LTM4609|36VIN, 34VOUT, 10A Buck-Boost µModule Regulator<br>with External Inductor|4.5V ≤ VIN≤ 36V. 0.8V ≤ VOUT≤ 34V, 15mm × 15mm × 2.82mm LGA,<br>15mm × 15mm × 3.42mm BGA|
|LTM8054|36VIN, 36VOUT, 5.4A Buck-Boost µModule<br>Regulator with Integrated Inductor|5V ≤ VIN≤ 36V, 1.2V ≤ VOUT≤ 36V, 11.25mm × 15mm × 3.42mm BGA|
|LTM8055|36VIN, 36VOUT, 8.5A Buck-Boost µModule<br>Regulator with Integrated Inductor|5V ≤ VIN≤ 36V, 1.2V ≤ VOUT≤ 36V, 15mm × 15mm × 4.92mm BGA|
|LTM8056|58VIN, 48VOUTBuck-Boost µModule Regulator with<br>Integrated Inductor|5V ≤ VIN≤ 58V, 1.2V ≤ VOUT≤ 48V, 15mm × 15mm × 4.92mm BGA|
|LTM4656|36VOUT, 4A Boost µModule Regulator|4.5V ≤ VIN≤ 28V, 6V ≤ VOUT≤ 36V, 16mm × 16mm × 7.07mm BGA|



Rev. 0 

10/23 www.analog.com 

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 ANALOG DEVICES, INC. 2023 

For more information www.analog.com