LTM4650IY-2#PBF

LTM4650-2 

## Dual 25A or Single 50A µModule Regulator with Active Voltage Positioning 

## **FEATURES** 

- n Dual 25A or Single 50A Output 

- n 4.5V to 15V Input, 0.6V to 1.8V Output Voltage Range 

- n ±1.5% Maximum Total DC Output Error Over Line and Load 

- n Differential Remote Sense Amplifier 

- n Current Mode Control/Fast Transient Response 

- n Current Sharing Up to 300A 

- n AVP (Active Voltage Positioning) Compatible 

- n 16mm × 16mm × 5.01mm BGA Package 

## **APPLICATIONS** 

- n FPGA, ASIC, µProcessor Core Voltage Regulation 

- n Information, Communication Systems 

## **DESCRIPTION** 

The LTM[®] 4650-2 is a dual 25A or single 50A output stepdown µModule[®] (micromodule) regulator with ±1.5% total DC output error. The package includes the switching controller, power FETs, inductors, and all supporting components. External compensation allows for fast transient response to minimize output capacitance when powering FPGAs, ASICs, and processors. AVP can further improve transient response and reduce the output capacitance. With synchronized multiphase parallel current sharing, six LTM4650-2 devices can deliver up to 300A. 

The LTM4650-2 is offered in a 16mm × 16mm × 5.01mm BGA package with SnPb or RoHS-compliant terminal finish. 

All registered trademarks and trademarks are the property of their respective owners. 

## **TYPICAL APPLICATION** 

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1.0V Output Efficiency,<br>Dual 25A, 1.0V and 1.5V Outputs DC/DC μModule Regulator fSW = 500kHz<br>95<br>INTVCC INTVCC<br>C10 R2 90<br>4.7µF 10k<br>PGOOD1 85<br>MODE_PLLIN CLKOUT INTVCC EXTVCC PGOOD1<br>4.5V TO 15VVIN + C330µF25VIN C122µF25V R7100k VTEMPIN VVOUTS1OUT1SW1 C100µF6.3VOUT1 + C470µF1V, 25AVOUT2OUT1 8075<br>×4 RUN1 VFB1 VFB1 ×3 6.3V×2 70<br>TRACK1C5 RUN2TRACK1 LTM4650-2 VFB2 R40.2kFB2 R82.6kFB1 65 VVININ = 12V = 5V<br>VFB1 0.1µF TRACK2 TRACK2 0 10 20 30 40 50<br>R185M R19560k C90.1µF VOUT2 INTVCC COUT3 V1.5V, 25AOUT2 LOAD CURRENT (A) 46502 TA01b<br>INTVCC R1321k C12 R4 COMP1fPHASMDCOMP2SET PGOOD2VOUTS2SW2 R310kPGOOD2 100µF6.3V×5 + 470µF6.3V×2COUT4 50% (12.5A) Load Step Transient Response,<br>C13 47pF 121k SGND GND DIFFN DIFFP DIFFOUT 12VIN, 1VOUT (with AVP)<br>3300pF<br>VOUT (AC)<br>46502 TA01a 30mV/DIV<br>LOAD STEP<br>10A/DIV<br>100µs/DIV 46502 TA01c<br>EFFICIENCY (%)<br>**----- End of picture text -----**<br>


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## - LTM4650 2 

## **ABSOLUTE MAXIMUM RATINGS** 

## **PIN CONFIGURATION** 

## **(Note 1)** 

VIN ..............................................................–0.3V to 16V VSW1, VSW2 ....................................................–1V to 16V PGOOD1, PGOOD2, RUN1, RUN2, INTVCC, EXTVCC .......................................... –0.3V to 6V MODE_PLLIN, fSET, TRACK1, TRACK2, DIFFOUT, PHASMD ...............................–0.3V to INTVCC VOUT1, VOUT2, VOUTS1, VOUTS2 (Note 6) ........ –0.3V to 6V DIFFP, DIFFN .........................................–0.3V to INTVCC INTVCC Peak Output Current ................................100mA Internal Operating Junction Temperature Range (Note 2) ............................................. –40°C to 125°C Storage Temperature Range .................. –55°C to 125°C Peak Package Body Temperature .......................... 245°C 

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TOP VIEW<br>TEMP EXTVCC<br>M<br>L<br>VIN<br>K<br>J<br>CLKOUT H INTVCC<br>SW2<br>SW1<br>G PGOOD1<br>PHASMD RUN1 SGND PGOOD2<br>MODE_PLLIN F GND COMP1 COMP2 RUN2DIFFOUT<br>TRACK1VFB1 DE SGND VFB2 TRACK2 GND DIFFPDIFFN<br>fSET SGND VOUTS2<br>C<br>VOUTS1<br>B<br>VOUT1 GND VOUT2<br>A<br>1 2 3 4 5 6 7 8 9 10 11 12<br>BGA PACKAGE<br>144-PIN (16mm × 16mm × 5.01mm)<br>TJMAX = 125°C, θJA = 7°C/W, θJCbottom = 1.5°C/W,<br>θJCtop = 3.7°C/W, θJB + θJBA ≅ 7°C/W<br>θ VALUES DEFINED PER JESD 51-12<br>WEIGHT = 3.5g<br>**----- End of picture text -----**<br>


## **ORDER INFORMATION** 

|**PART NUMBER**|**PAD OR BALL FINISH***|**PART MARKING**|**PART MARKING**|**PACKAGE TYPE**|**MSL**<br>**RATING**|**TEMPERATURE**<br>**RANGE (Note 2)**|
|---|---|---|---|---|---|---|
|||**DEVICE**|**FINISH CODE**||||
|LTM4650EY-2#PBF|SAC305(RoHS)|LTM4650Y-2|e1|BGA|4|–40°C to 125°C|
|LTM4650IY-2#PBF|SAC305(RoHS)|LTM4650Y-2|e1|BGA|4|–40°C to 125°C|
|LTM4650IY-2|SnPb(63/37)|LTM4650Y-2|e0|BGA|4|–40°C to 125°C|



- Contact the factory for parts specified with wider operating temperature ranges. *Pad or ball finish code is per IPC/JEDEC J-STD-609. 

- Recommended LGA and BGA PCB Assembly and Manufacturing Procedures 

• LGA and BGA Package and Tray Drawings 

**ELECTRICAL CHARACTERISTICS The** l **denotes the specifications which apply over the specified internal operating junction temperature range. Specified as each individual output channel. TA = 25°C (Note 2), VIN = 12V and VRUN1, VRUN2 at 5V unless otherwise noted. Per the typical application in Figure 24.** 

|**SYMBOL**|**PARAMETER**|**CONDITIONS**|**CONDITIONS**|**MIN**<br>**TYP**<br>**MAX**|**UNITS**|
|---|---|---|---|---|---|
|VIN|Input DC Voltage||l|4.5<br>15|V|
|VOUT|Output DC Voltage||l|0.6<br>1.8|V|
|VOUT1(DC),<br>VOUT2(DC)|Output Voltage, Total Variation with<br>Line and Load|CIN= 22µF×3, COUT= 100µF×2 Ceramic,<br>470µF POSCAP, VIN= 12V, VOUT= 1.2V,<br>IOUT= 0A to 25A|l|1.182<br>1.218|V|
|**Input Specifications**||||||
|VRUN1, VRUN2|RUN Pin On/Off Threshold|RUN Rising||1.1<br>1.25<br>1.40|V|
|VRUN1HYS, VRUN2HYS|RUN Pin On Hysteresis|||150|mV|



Rev. 0 

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- LTM4650 2 

## **ELECTRICAL CHARACTERISTICS** 

**The** l **denotes the specifications which apply over the specified internal operating junction temperature range. Specified as each individual output channel. TA = 25°C (Note 2), VIN = 12V and VRUN1, VRUN2 at 5V unless otherwise noted. Per the typical application in Figure 24.** 

|**SYMBOL**|**PARAMETER**|**CONDITIONS**|**CONDITIONS**|**MIN**<br>**TYP**<br>**MAX**|**UNITS**|
|---|---|---|---|---|---|
|IINRUSH(VIN)|Input Inrush Current at Start-Up|IOUT= 0A, CIN= 22µF ×3, CSS= 0.01µF,<br>COUT= 100µF ×3, VOUT= 1.2V||1|A|
|IQ(VIN)|Input Supply Bias Current<br>(Both Channel Running)|VIN= 12V, VOUT= 1.2V, Burst Mode Operation<br>VIN= 12V, VOUT= 1.2V, Pulse-Skipping Mode<br>VIN= 12V, VOUT= 1.2V, Switching Continuous<br>Shutdown, RUN = 0, VIN= 12V||4.5<br>25<br>240<br>35|mA<br>mA<br>mA<br>µA|
|IS(VIN)|Input Supply Current|VIN= 4.5V, VOUT= 1.2V, IOUT= 25A<br>VIN= 12V, VOUT= 1.2V, IOUT= 25A||8.4<br>3.2|A<br>A|
|**Output Specifications**||||||
|IOUT1(DC), IOUT2(DC)|Output Continuous Current Range|VIN= 12V, VOUT= 1.2V(Note 6)||0<br>25|A|
|ΔVOUT1(LINE)/VOUT1<br>ΔVOUT2(LINE)/VOUT2|Line Regulation Accuracy|VOUT= 1.2V, VINfrom 4.5V to 15V,<br>IOUT= 0A for Each Output|l|0.01<br>0.1|%/V|
|ΔVOUT1/VOUT1<br>ΔVOUT2/VOUT2|Load Regulation Accuracy|For Each Output, VOUT= 1.2V, 0A to 25A,<br>VIN= 12V(Note 6)|l|0.2<br>0.75|%|
|VOUT1(AC), VOUT2(AC)|Output Ripple Voltage|For Each Output, IOUT= 0A, COUT= 100µF ×3<br>Ceramic, 470µF POSCAP, VIN= 12V,<br>VOUT= 1.2V, Frequency = 500kHz||15|mVP-P|
|fS (Each Channel)|Output Ripple Voltage Frequency|VIN= 12V, VOUT= 1.2V, fSET= 1.25V(Note 4)||500|kHz|
|fSYNC<br>(Each Channel)|SYNC Capture Range|||400<br>750|kHz|
|ΔVOUTSTART<br>(Each Channel)<br>(Note 7)|Turn-On Overshoot|COUT= 100µF Ceramic, 470µF POSCAP,<br>VOUT= 1.2V, IOUT= 0A VIN= 12V||10|mV|
|tSTART<br>(Each Channel)|Turn-On Time|COUT= 100µF Ceramic, 470µF POSCAP,<br>No Load, TRACK/SS with 0.01µF to GND,<br>VIN= 12V||5|ms|
|ΔVOUT(LS)<br>(Each Channel)<br>(Note 7)|Peak Deviation for Dynamic Load|Load: 0% to 50% to 0% of Full Load,<br>COUT= 22µF ×3 Ceramic, 470µF POSCAP,<br>VIN= 12V, VOUT= 1.2V||30|mV|
|tSETTLE<br>(Each Channel)<br>(Note 7)|Settling Time for Dynamic Load<br>Step|Load: 0% to 50% to 0% of Full Load,<br>VIN= 12V, COUT= 100µF, 470µF POSCAP||20|µs|
|IOUT(PK)<br>(Each Channel)|Output Current Limit|VIN= 12V, VOUT= 1.2V||35|A|
|**Control Section**||||||
|VFB1, VFB2|Voltage at VFBPins|IOUT= 0A, VOUT= 1.2V|l|0.594<br>0.600<br>0.606|V|
|IFB||(Note 5)||–5<br>–20|nA|
|VOVL|Feedback Overvoltage Lockout||l|0.64<br>0.66<br>0.68|V|
|TRACK1 (I),<br>TRACK2(I)|Track Pin Soft-Start Pull-Up Current|TRACK1 (I), TRACK2 (I) Start at 0V||1<br>1.3<br>1.5|µA|
|UVLO|Undervoltage Lockout(Falling)|||3.3|V|
|UVLO Hysteresis||||0.6|V|
|tON(MIN)|Minimum On-Time|(Note 5)||90|ns|
|RFBHI1, RFBHI2|Resistor Between VOUTS1, VOUTS2<br>and VFB1, VFB2Pins for Each Output|||60.05<br>60.4<br>60.75|kΩ|
|VPGOOD1, VPGOOD2<br>Low|PGOOD Voltage Low|IPGOOD= 2mA||0.1<br>0.3|V|



Rev. 0 

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## - LTM4650 2 

**ELECTRICAL CHARACTERISTICS The** l **denotes the specifications which apply over the specified internal operating junction temperature range. Specified as each individual output channel. TA = 25°C (Note 2), VIN = 12V and VRUN1, VRUN2 at 5V unless otherwise noted. Per the typical application in Figure 24.** 

|**SYMBOL**|**PARAMETER**|**CONDITIONS**|**CONDITIONS**|**MIN**<br>**TYP**<br>**MAX**|**UNITS**|
|---|---|---|---|---|---|
|IPGOOD|PGOOD Leakage Current|VPGOOD= 5V||±5|µA|
|VPGOOD|PGOOD Trip Level|VFBwith Respect to Set Output Voltage<br>VFBRamping Negative<br>VFBRamping Positive||–10<br>10|%<br>%|
|**INTVCC Linear Regulator**||||||
|VINTVCC|Internal VCCVoltage|6V < VIN< 15V||4.8<br>5<br>5.2|V|
|VINTVCC<br>Load Regulation|INTVCCLoad Regulation|ICC= 0mA to 50mA||0.75<br>2|%|
|VEXTVCC|EXTVCCSwitchover Voltage|EXTVCCRamping Positive||4.5<br>4.7|V|
|VEXTVCC(DROP)|EXTVCCDropout|ICC= 20mA, VEXTVCC= 5V||50<br>100|mV|
|VEXTVCC(HYST)|EXTVCCHysteresis|||220|mV|
|**Oscillator and Phase-Locked Loop**||||||
|Frequency Nominal|Nominal Frequency|fSET= 1.2V||450<br>500<br>550|kHz|
|Frequency Low|Lowest Frequency|fSET= 0.93V||400|kHz|
|Frequency High|Highest Frequency|fSET> 2.4V, Up to INTVCC||750|kHz|
|fSET|Frequency Set Current|||9<br>10<br>11|µA|
|RMODE_PLLIN|MODE_PLLIN Input Resistance|||250|kΩ|
|CLKOUT|Phase (Relative to VOUT1)|PHASMD = GND<br>PHASMD = Float<br>PHASMD = INTVCC||60<br>90<br>120|Deg<br>Deg<br>Deg|
|CLK High<br>CLK Low|Clock High Output Voltage<br>Clock Low Output Voltage|||2<br>0.4|V<br>V|
|**Differential Amplifier**||||||
|AVDifferential<br>Amplifier|Gain|||1|V/V|
|RIN|Input Resistance|Measured at DIFFP Input||80|kΩ|
|VOS|Input Offset Voltage|VDIFFP= VDIFFOUT= 1.5V, IDIFFOUT= 100µA||3|mV|
|PSRR Differential<br>Amplifier|Power Supply Rejection Ratio|5V < VIN< 15V||90|dB|
|ICL|Maximum Output Current|||2|mA|
|VOUT(MAX)|Maximum Output Voltage|IDIFFOUT= 300µA||INTVCC– 1.4|V|
|GBW(Note 8)|Gain Bandwidth Product|||3|MHz|
|VTEMP|Diode Connected PNP|I = 100µA||0.6|V|
|TC|Temperature Coefficient||l|–2.2|mV/°C|



**Note 1:** Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. 

**Note 2:** The LTM4650-2 is tested under pulsed load conditions such that TJ ≈ TA. The LTM4650-2E is guaranteed to meet specifications from 0°C to 125°C internal temperature. Specifications over the –40°C to 125°C internal operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTM4650-2I is guaranteed over the full –40°C to 125°C internal operating temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating 

conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. 

**Note 3:** Two outputs are tested separately, and the same testing condition is applied to each output. 

**Note 4:** The LTM4650-2 device is designed to operate from 400kHz to 750kHz. 

**Note 5:** These parameters are tested at wafer sort. 

**Note 6:** See Thermal Considerations and Output Current Derating for different VIN, VOUT and TA. 

**Note 7:** These typical parameters are based on bench measurements. **Note 8:** Guaranteed by design. 

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- LTM4650 2 

## **TYPICAL PERFORMANCE CHARACTERISTICS** 

**Dual-Phase Single Output Efficiency vs Output Current, VIN = 12V,  IN = 12V,   = 12V, fS = 500kHzS = 500kHz = 500kHz** 

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Efficiency vs Output Current,   Efficiency vs Output Current,   vs Output Current, VIN = 12V,  IN = 12V,   = 12V,<br>VIN = 5V VIN = 12V fS = 500kHzS = 500kHz = 500kHz<br>95 95 95<br>90 ee ee 90 el eeee 90 eee<br>85 85 85<br>4 SS<br>80 80 80<br>75 ee 0.8V e OUT, 400kHz 75 fo 0.8VOUT, 400kHz 75 fo 0.8V o OUT, 400kHz<br>1.0VOUT, 500kHz 1.0VOUT, 500kHz 1.0VOUT, 500kHz<br>70 1.2V OUT , 500kHz 70 1.2V OUT , 500kHz 70 1.2V OUT , 500kHz<br>1.5VOUT, 600kHz 1.5VOUT, 600kHz 1.5VOUT, 600kHz<br>1.8VOUT, 600kHz 1.8VOUT, 600kHz 1.8VOUT, 600kHz<br>65 f=i 65 iafl 65 a i |<br>0 5 10 15 20 25 0 5 10 15 20 25 0 10 20 30 40 50<br>LOAD CURRENT (A) LOAD CURRENT (A) LOAD CURRENT (A)<br>46502 G01 46502 G02<br>46502 G03<br>Burst Mode and Pulse-Skipping<br>Mode Efficiency VIN = 12V,   1V Dual-Phase Single Output  1.2V Dual-Phase Single Output<br>VOUT = 1.2V, fS = 500kHz Load Transient Response Load Transient Response<br>100<br>9080 — CCM Burst Mode OPERATION PULSE-SKIP MODE 20mV/DIVVOUT(AC) ee 20mV/DIVVOUT(AC)<br>70 eePeelean —-—F ee eee anepeerae<br>60<br>nae VA LOAD | LOAD ee<br>50 STEP STEP<br>40 ee) 10A/DIV 10A/DIV i<br>30 PA [a] ot 50µs/DIV 46502 G05 ee 50µs/DIV 46502 G06 —<br>20 ATA| PAI CUI 12V10A/µs STEP-UP AND STEP-DOWN IN, 1VOUT, 500kHz, 12.5A LOAD STEP,  12V10A/µs STEP-UP AND STEP-DOWN IN, 1.2VOUT, 500kHz, 12.5A LOAD STEP,<br>10 UIC COUT = 220µF ×6 CERAMIC COUT = 220µF ×6 CERAMIC<br>0 rooTC CTE CFF = 68pF CFF = 68pF<br>0.01 0.1 1 10<br>LOAD CURRENT (A)<br>46502 G04<br>EFFICIENCY (%) EFFICIENCY (%) EFFICIENCY (%)<br>EFFICIENCY (%)<br>**----- End of picture text -----**<br>


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1.5V Dual-Phase Single Output  1.8V Dual-Phase Single Output  Single-Phase Start-Up with No<br>Load Transient Response Load Transient Response load<br>VOUT(AC) 20mV/DIVVOUT(AC) 10V/DIVVSW<br>20mV/DIV<br>VOUT<br>0.5V/DIV<br>Te co eae<br>LOAD eS LOAD __<br>STEP STEP IIN<br>10A/DIV ee 10A/DIV 0.2A/DIV le ile<br>ee ee dad pins enananenn sanananana<br>50µs/DIV 46502 G07 a 50µs/DIV 46502 G08 es 20ms/DIV ee 46502 G09<br>12VIN, 1.5VOUT, 600kHz, 12.5A LOAD STEP,  12VIN, 1.8VOUT, 600kHz, 12.5A LOAD STEP,  12VIN, 1.2VOUT, 500kHz<br>10A/µs STEP-UP AND STEP-DOWN  10A/µs STEP-UP AND STEP-DOWN  COUT = 470µF ×1 POSCAP + 100µF ×2<br>COUT = 220µF ×6 CERAMIC COUT = 220µF ×6 CERAMIC CERAMIC, CSS = 0.1µF<br>CFF = 68pF CFF = 68pF<br>**----- End of picture text -----**<br>


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- LTM4650 2 

## **TYPICAL PERFORMANCE CHARACTERISTICS** 

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Single-Phase Short-Circuit  Single-Phase Short-Circuit<br>Single-Phase Start-Up with 25A Protection with No load Protection with 25A<br>VSW VSW VSW<br>10V/DIV 10V/DIV 10V/DIV<br>VOUT VOUT VOUT<br>0.5V/DIV 0.5V/DIV 0.5V/DIV<br>tet Pee FAY +<br>IIN<br>IIN 1A/DIV IIN<br>1A/DIV 2A/DIV<br>Po SSS RS<br>20ms/DIV 46502 G10 50μs/DIV 46502 G11 50µs/DIV 46502 G12<br>12VIN, 1.2VOUT, 500kHz 12VIN, 1.2VOUT, 500kHz 12VIN, 1.2VOUT, 500kHz<br>COUT = 470µF ×1 POSCAP + 100µF ×2  COUT = 470µF ×1 POSCAP + 100µF ×2  COUT = 470µF ×1 POSCAP + 100µF ×2 CERAMIC<br>CERAMIC, CSS = 0.1μF CERAMIC, CSS = 0.1µF<br>**----- End of picture text -----**<br>


**PIN FUNCTIONS (Recommended to use test points to monitor signal pin connections.)** 

**PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULLY.** 

– – – **VOUT1 (A1 A5, B1 B5, C1 C4):** Power Output Pins. Apply output load between these pins and GND pins. Recommend placing output decoupling capacitance directly between these pins and GND pins. See Table 4. 

– – – – – – **GND (A6 A7, B6 B7, D1 D4, D9 D12, E1 E4, E10 E12,** – – – – **F1 F3, F10 F12, G1, G3, G10, G12, H1 H7, H9 H12, J1, J5, J8, J12, K1, K5–K8, K12, L1, L12, M1, M12):** Power Ground Pins for Both Input and Output Returns. 

– – – **VOUT2 (A8 A12, B8 B12, C9 C12):** Power Output Pins. Apply output load between these pins and GND pins. Recommend placing output decoupling capacitance directly between these pins and GND pins. See Table 4. 

**VOUTS1, VOUTS2 (C5, C8):** This pin is connected to the top of the internal top feedback resistor for each output. The pin can be directly connected to its specific output, or connected to DIFFOUT when the remote sense amplifier is used. In paralleling modules, one of the VOUTS pins is connected to the DIFFOUT pin in remote sensing or directly to VOUT with no remote sensing. It is very important to connect these pins to either the DIFFOUT or VOUT since this is the feedback path and cannot be left open. See the Applications Information section. 

**fSET (C6):** Frequency Set Pin. A 10µA current is sourced from this pin. A resistor from this pin to ground sets a voltage that programs the operating frequency. Alternatively, this pin can be driven with a DC voltage that can set the operating frequency. See the Applications Information section. 

– – **SGND (C7, D6, G6 G7, F6 F7):** Signal Ground Pin. Return ground path for all analog and low-power circuitry. Tie a single connection to the output capacitor GND in the application. See the layout guidelines in Figure 23. 

**VFB1, VFB2 (D5, D7):** The Negative Input of the Error Amplifier for Each Channel. Internally, this pin is connected to VOUTS1 or VOUTS2 with a 60.4kΩ precision resistor. Different output voltages can be programmed with an additional resistor between VFB and GND pins. In PolyPhase[®] operation, tying the VFB pins together allows for parallel operation. See the Applications Information section for details. 

**TRACK1, TRACK2 (E5, D8):** Output Voltage Tracking Pin and Soft-Start Inputs. Each channel has a 1.3µA pull-up current source. When one channel is configured to be the main of the two channels, then a capacitor from this pin 

Rev. 0 

6 

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- LTM4650 2 

## **PIN FUNCTIONS (Recommended to use test points to monitor signal pin connections.)** 

to ground will set a soft-start ramp rate. The remaining channel can be set up as the subordinate and have the main’s output applied through a voltage divider to the subordinate output’s track pin. This voltage divider equals the subordinate output’s feedback divider for coincidental tracking. See the Applications Information section. 

**COMP1, COMP2 (E6, E7):** Current control threshold and error amplifier compensation point for each channel. The current comparator threshold increases with this control voltage. An external RC filter circuit is required for control loop compensation. See the  Applications Information section. Connect the COMP pins together for parallel operation. Do not drive this pin. 

**DIFFP (E8):** Positive input of the remote sense amplifier. This pin is connected to the remote sense point of the output voltage. See the Applications Information section. 

**DIFFN (E9):** Negative input of the remote sense amplifier. This pin is connected to the remote sense point of the output GND. See the Applications Information section. 

**MODE_PLLIN (F4):** Forced Continuous Mode, Burst Mode Operation, or Pulse-Skipping Mode Selection Pin and External Synchronization Input to Phase Detector Pin. Connect this pin to SGND to force both channels into the forced continuous mode of operation. Connect to INTVCC to enable the pulse-skipping mode of operation. Leaving the pin floating will enable Burst Mode operation. A clock on the pin will force both channels into continuous mode of operation and synchronized to the external clock applied to this pin. 

**RUN1, RUN2 (F5, F9):** Run Control Pin. A voltage above 1.25V will turn on each channel in the module. A voltage below 1.25V on the RUN pin will turn off the related channel. Each RUN pin has a 1µA pull-up current; once the RUN pin reaches 1.2V, an additional 4.5µA pull-up current is added to this pin. 

**DIFFOUT (F8):** Internal Remote Sense Amplifier Output. Connect this pin to VOUTS1 or VOUTS2 depending, on which output is using remote sense. In parallel operation, connect one of the VOUTS pin to DIFFOUT for remote sensing. 

**SW1, SW2 (G2, G11):** Switching node of each channel that is used for testing purposes. Also, an R-C snubber network can be applied to reduce or eliminate switch node ringing or otherwise leave floating. See the Applications Information section. 

**PHASMD (G4):** Connect this pin to SGND, INTVCC, or floating this pin to select the phase of CLKOUT to 60 degrees, 120 degrees, and 90 degrees respectively. 

**CLKOUT (G5):** Clock output with phase control using the PHASMD pin to enable multiphase operation between devices. See the Applications Information section. 

**PGOOD1, PGOOD2 (G9, G8):** Output Voltage Power Good Indicator. Open drain logic output that is pulled to ground when the output voltage is not within ±10% of the regulation point. 

**INTVCC (H8):** Internal 5V Regulator Output. The control circuits and internal gate drivers are powered from this voltage. Decouple this pin to PGND with a 4.7µF low ESR tantalum or ceramic. INTVCC is activated when either RUN1 or RUN2 is activated. 

**TEMP (J6):** Temperature Monitor. An internal diode connected the NPN transistor between this pin and SGND with a 10nF filtering capacitor. See the Applications Information section. 

**EXTVCC (J7):** External power input that is enabled through a switch to INTVCC whenever EXTVCC is greater than 4.7V. Do not exceed 6V on this input, and connect this pin to VIN when operating VIN on 5V. An efficiency increase will occur, which is a function of the (VIN – INTVCC) multiplied by the power MOSFET driver current. The typical current requirement is 30mA. VIN must be applied before EXTVCC, and EXTVCC must be removed before VIN. 

– – – – – – **VIN (M2 M11, L2 L11, J2 J4, J9 J11, K2 K4, K9 K11):** Power Input Pins. Apply input voltage between these pins and GND pins. Recommend placing input decoupling capacitance directly between VIN pins and GND pins. 

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## **SIMPLIFIED BLOCK DIAGRAM** 

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**----- Start of picture text -----**<br>
PGOOD1<br>VIN<br>TRACK1 VIN 4.5V TO 15V<br>SS CAP CIN1<br>1μF 22µF<br>25V<br>GND ×2<br>VRINT = 100µA VIN RT CLKOUTTEMP MTOP1 SW1<br>OR TEMP<br>MONITORS RUN1 0.12µH VOUT1 VOUT1<br>1.5V,<br>MODE_PLLIN + 25A<br>MBOT1 0.22µF COUT1<br>PHASMD GND<br>VOUTS1<br>COMP1 60.4k<br>VFB1<br>RTH1<br>RFB1<br>CTH1 SGND POWER 40.2k<br>CONTROL PGOOD2<br>TRACK2 VIN<br>SS CAP INTVCC 1μF C22µFIN2<br>4.7µF 0.22μF GND 25V<br>EXTVCC ×2<br>MTOP2<br>SW2<br>0.12µH VOUT2 VOUT2<br>1.2V,<br>RUN2 + 25A<br>MBOT2 0.22µF COUT2<br>GND<br>VOUTS2<br>60.4k<br>COMP2 VFB2<br>+ –<br>RFB2<br>60.4k<br>RTH2 fSET<br>CTH2 RFSET INTERNAL<br>FILTER<br>SGND<br>DIFFOUT<br>DIFFN<br>DIFFP<br>**----- End of picture text -----**<br>


**==> picture [18 x 4] intentionally omitted <==**

**----- Start of picture text -----**<br>
46502 F01<br>**----- End of picture text -----**<br>


**Figure 1. Simplified LTM4650-2 Block Diagram** 

## **DECOUPLING REQUIREMENTS TA = 25°C. Use Figure 1 configuration.** 

|**DECO**|**UPLING REQUIREMENTS**|<br>**TA = 25°C. Use Figure 1 configuration.**|||
|---|---|---|---|---|
|**SYMBOL**|**PARAMETER**|**CONDITIONS**|**MIN**<br>**TYP**<br>**MAX**|**UNITS**|
|CIN1,CIN2|External Input Capacitor Requirement<br>(VIN1= 4.5V to 15V, VOUT1= 1.5V)<br> (VIN2= 4.5V to 15V, VOUT2= 1.0V)|IOUT1= 25A<br>IOUT2= 25A|44<br>44<br>66<br>66|µF<br>µF|
|COUT1<br>COUT2|External Output Capacitor Requirement<br>(VIN1= 4.5V to 15V, VOUT1= 1.5V)<br> (VIN2= 4.5V to 15V, VOUT2= 1.0V)|IOUT1= 25A<br>IOUT2= 25A|600<br>600<br>800<br>800|µF<br>µF|
|Rev. 0|||||



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## **OPERATION** 

## **POWER MODULE DESCRIPTION** 

The LTM4650-2 is a dual-output standalone nonisolated switching mode DC/DC power supply with ±1.5% total DC output error over line, load and temperature variation. It can provide two 25A outputs with few external input and output capacitors and setup components. This module provides precisely regulated output voltages programmable via external resistors from 0.6VDC to 1.8VDC over 4.5V to 15V input voltages. The typical application schematic is shown in Figure 24. 

The LTM4650-2 has dual integrated constant-frequency current mode regulators and built-in power MOSFET devices with fast switching speed. The typical switching frequency is from 400kHz to 600kHz, depending on the output voltage. For switching-noise sensitive applications, it can be externally synchronized from 400kHz to 750kHz. A resistor can be used to program a free run frequency on the fSET pin. See the Applications Information section. 

With current mode control, the LTM4650-2 module has sufficient stability margins and good transient performance with a wide range of output capacitors, even with all ceramic output capacitors. 

Current mode control provides cycle-by-cycle fast current limit and foldback current limit in an overcurrent condition. Internal overvoltage and undervoltage comparators pull the open-drain PGOOD outputs low if the output feedback voltage exits a ±10% window around the regulation point. As the output voltage exceeds 10% above regulation, the bottom MOSFET will turn on to clamp the output voltage. The top MOSFET will be turned off. This overvoltage protect is feedback voltage referred. 

Pulling the RUN pins below 1.1V forces the regulators into a shutdown state by turning off both MOSFETs. The TRACK pins are used for programming the output voltage 

ramp and voltage tracking during start-up or for softstarting the regulator. See the Applications Information section. 

An external RC filtering circuit is required to achieve fast Type II control loop compensation. Table 4 provides a guideline for input, output capacitances and RC COMP values for several operating conditions. The Analog Devices µModule power design tool (LTpowerCAD) will be provided for transient and stability analysis. The VFB pin is used to program the output voltage with a single external resistor to ground. A differential remote sense amplifier is available for sensing the output voltage accurately on one of the outputs at the load point or in parallel operation sensing the output voltage at the load point. 

The multiphase operation can be easily employed with the MODE_PLLIN, PHASMD, and CLKOUT pins. Up to 12 phases can be cascaded to run simultaneously with respect to each other by programming the PHASMD pin to different levels. See the Applications Information section. 

High efficiency at light loads can be accomplished with selectable Burst Mode operation or pulse-skipping operation using the MODE_PLLIN pin. These light-load features will accommodate battery operation. Efficiency graphs are provided for light load operation in the Typical Performance Characteristics section. See the Applications Information section for details. 

A general-purpose temperature diode is included inside the module to monitor the temperature of the module. See the Applications Information section for details. 

The switch pins are available for functional operation monitoring, and a resistor-capacitor snubber circuit can be carefully placed on the switch pin to ground to dampen any high-frequency ringing on the transition edges. See the Applications Information section for details. 

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## **APPLICATIONS INFORMATION** 

The typical LTM4650-2 application circuit is shown in Figure 24. External component selection is primarily determined by the maximum load current and output voltage. See Table 4 for specific external capacitor requirements for particular applications. 

## **OUTPUT TOTAL DC ACCURACY AND AC TRANSIENT PERFORMANCE** 

In modern ASIC and FPGA power supply designs, a tight total voltage regulation window, ±3% for example, is required of the supply powering the core and periphery. To meet this requirement, the supply’s DC voltage variance plus any AC voltage variation that may occur during any load step transient must fall within this allowed window. The DC voltage variance is determined by the accuracies of the supply’s reference voltage, resistor divider, load regulation and line regulation over the operating temperature range. The AC voltage variance is determined by the supply’s output voltage overshoot and undershoots in response to a load transient condition for a given output capacitor network. 

Figure 2 shows a typical load step transient response waveform and DC voltage accuracy variance. For a given - allowable voltage regulation window, a tighter DC volt age accuracy allows more margin for the AC variation due to a load transient response. This increased margin for AC variation allows for a reduction in the total output capacitance required to meet the regulation window requirement. This allows for a reduced total solution cost and footprint area. 

**==> picture [253 x 104] intentionally omitted <==**

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LOAD STEP<br>AC OVERSHOOT<br>ALLOWABLE<br>REGULATION  DC ACCURACY<br>WINDOW<br>AC UNDERSHOOT<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
46502 F02<br>**----- End of picture text -----**<br>


**Figure 2. Typical Load Step Transient Response with DC Voltage Accuracy Variance** 

For example, in an FPGA core voltage application, for a 12V input, 0.9V output at 72A design, a total overall ±3% total voltage regulation window is required in responding to a 25% load step transient. Figure 3 illustrates the benefit of overall output capacitor reduction versus improved total DC accuracy by using 100µF ceramic output capacitors. 

**==> picture [160 x 160] intentionally omitted <==**

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5000<br>4700<br>4500<br>4000<br>3500<br>3200<br>3000<br>2600<br>2500<br>2200<br>2000<br>1500<br>1000<br>500<br>0<br>0.8 1.2 1.5 2.0<br>TOTAL DC ACCURACY (%)<br>46502 F03<br>REQUIRED OUTPUT CAPACITANCE (µF)<br>**----- End of picture text -----**<br>


**Figure 3. Overall Output Capacitor vs Total DC Accuracy** 

## **VIN to VOUT Step-Down Ratios** 

There are restrictions in the maximum VIN and VOUT stepdown ratio that can be achieved for a given input voltage. Each output of the LTM4650-2 is capable of a 98% duty cycle, but the VIN to VOUT minimum dropout is still shown as a function of its load current and will limit output current capability related to the high duty cycle on the top side switch. Minimum on-time t is another consid- ON(MIN) eration in operating at a specified duty cycle while operating at a certain frequency because tON(MIN) < D/fSW, where D is the duty cycle and fSW is the switching frequency. tON(MIN) is specified in the Electrical parameters as 90ns. 

## **Output Voltage Programming** 

The PWM controller has an internal 0.6V reference voltage. As shown in the Simplified Block Diagram, a 60.4k internal feedback resistor connects between the VOUTS1 to VFB1 and VOUTS2 to VFB2. These pins must be connected to their respective outputs for proper feedback regulation. Overvoltage can occur if these VOUTS1 and VOUTS2 pins are left floating when used as individual regulators, or at least one of them is used in paralleled regulators. The output voltage will default to 0.6V with no feedback resistor on 

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## **APPLICATIONS INFORMATION** 

either VFB1 or VFB2. Adding a resistor RFB from the VFB pin to GND programs the output voltage: 

**==> picture [121 x 28] intentionally omitted <==**

## **Table 1. VFB Resistor vs Various Output Voltages** 

|**VOUT**|0.6V|0.8V|0.9V|1.0V|1.2V|1.5V|1.8V|
|---|---|---|---|---|---|---|---|
|**RFB**|Open|182k|121k|90.9k|60.4k|40.2k|30.2k|



For parallel operation of multiple channels, the same feedback setting resistor can be used for the parallel design. This is done by connecting the VOUTS1 to the output, as shown in Figure 4, thus tying one of the internal 60.4k resistors to the output. All of the VFB pins tie together with one programming resistor, as shown in Figure 4. 

**==> picture [246 x 245] intentionally omitted <==**

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COMP1 LTM4650-2 VOUT1 4 PARALLELED OUTPUTS FOR 1.2V, 100A<br>COMP2 VOUT2<br>60.4k VOUTS1<br>VOUTS2<br>OPTIONAL CONNECTION<br>VFB1<br>60.4k<br>TRACK1<br>VFB2<br>TR ACK2<br>OPTIONAL<br>RFB<br>COMP1 LTM4650-2 VOUT1 60.4k<br>COMP2 VOUT2<br>RTH 60.4k VOUTS1 USE TO LOWERTOTAL EQUIVALENT<br>CTH VOUTS2 RESISTANCE TO LOWERIFB VOLTAGE ERROR<br>VFB1<br>60.4k<br>TRACK1<br>VFB2<br>0.1µF TRACK2<br>RFB<br>46502 F04 60.4k<br>**----- End of picture text -----**<br>


**Figure 4. 4-Phase Parallel Configurations** 

In parallel operation, the VFB pins have an IFB current of 20nA maximum for each channel. To reduce output voltage error due to this current, an additional VOUTS pin can be tied to VOUT, and an additional RFB resistor can be used to lower the total Thevenin equivalent resistance seen by this current. For example in Figure 4, the total Thevenin equivalent resistance of the VFB pin 

is (60.4k//RFB), which is 30.2k where RFB is equal to 60.4k for a 1.2V output. Four phases connected in parallel equates to a worse-case feedback current of 4 • IFB = 80nA maximum. The voltage error is 80nA • 30.2k = 2.4mV. If VOUTS2 is connected, as shown in Figure 4, to VOUT, and another 60.4k resistor is connected from VFB2 to ground, then the voltage error is reduced to 1.2mV. If the voltage error is acceptable, then no additional connections are necessary. The onboard 60.4k resistor is 0.5% accurate, and the VFB resistor can be chosen by the user to be as accurate as needed. All COMP pins are tied together for current sharing between the phases. The TRACK/SS pins can be tied together, and a single soft-start capacitor can be used to soft-start the regulator. The soft-start equation must have the soft-start current parameter increased by the number of paralleled channels. See the Output Voltage Tracking section. 

## **Input Capacitors** 

The LTM4650-2 module should be connected to a low AC-impedance DC source. For the regulator input, two 22µF input ceramic capacitors are required for each channel for RMS ripple current. A 47µF to 100µF surface mount aluminum electrolytic bulk capacitor can be used for more input bulk capacitance. This bulk input capacitor is only needed if the input source impedance is compromised by long inductive leads, traces or not enough source capacitance. If low-impedance power planes are used, then this bulk capacitor is not needed. 

For a buck converter, the switching duty cycle can be estimated as: 

**==> picture [44 x 28] intentionally omitted <==**

Without considering the inductor current ripple, for each output, the RMS current of the input capacitor can be estimated as: 

**==> picture [159 x 30] intentionally omitted <==**

In the above equation, η % is the estimated efficiency of the power module. The bulk capacitor can be a switcherrated electrolytic aluminum capacitor, Polymer capacitor. 

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## **APPLICATIONS INFORMATION** 

## **Output Capacitors** 

The LTM4650-2 is designed for low output voltage ripple noise and good transient response. The bulk output capacitors defined as COUT are chosen with low enough effective series resistance (ESR) to meet the output voltage ripple and transient requirements. COUT can be a low ESR tantalum capacitor, a low ESR polymer capacitor or a ceramic capacitor. The typical output capacitance range for each output is from 400µF to 600µF. Additional output filtering may be required by the system designer, if further reduction of output ripples or dynamic transient spikes is required. Table 4 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 12.5A (25%) and 25A (50%) load step transient. Table 4 optimizes total equivalent ESR and total bulk capacitance to optimize the transient performance. Stability criteria are considered in the Table 4 matrix, and the Analog Devices LTpowerCAD[®] design tool will be provided for stability analysis. In multi LTM4650-2 paralleling applications, Table 4 RC compensation value is still valid in terms of having one set of RC filters on each of the paralleling modules while connecting all the COMP, FB and VOUT pins together. See Figure 29 and the Multiphase Operation section. The multiphase operation will reduce effective output ripple as a function of the number of phases. Application Note 77 discusses this noise reduction versus output ripple current cancellation, but the output capacitance should be considered carefully as a function of stability and transient response. The Analog Devices LTpowerCAD design tool can calculate the output ripple reduction as the number of implemented phases increases by N times. A small value 10Ω to 50Ω resistor can be placed in series from VOUT to the VOUTS pin to allow for a bode plot analyzer to inject a signal into the control loop and validate the regulator stability. The same resistor could be placed in series from VOUT to DIFFP, and a bode plot analyzer could inject a signal into the control loop and validate the regulator stability. 

## **Burst Mode Operation** 

The LTM4650-2 is capable of Burst Mode operation on - each regulator in which the power MOSFETs operate inter mittently based on load demand, thus saving quiescent current. For applications where maximizing the efficiency at very light loads is a high priority, Burst Mode operation should be applied. Burst Mode operation is enabled with the MODE_PLLIN pin floating. During this operation, the peak current of the inductor is set to approximately one-third of the maximum peak current value in normal operation, even though the voltage at the COMP pin indicates a lower value. The voltage at the COMP pin drops when the inductor’s average current is greater than the load requirement. As the COMP voltage drops below 0.5V, the BURST comparator trips, causing the internal sleep line to go high and turn off both power MOSFETs. 

In sleep mode, the internal circuitry is partially turned off, reducing the quiescent current to about 450µA for each output. The load current is now being supplied from the output capacitors. When the output voltage drops, causing COMP to rise above 0.5V, the internal sleep line goes low, and the LTM4650-2 resumes normal operation. The next oscillator cycle will turn on the top power MOSFET, and the switching cycle repeats. Either regulator can be configured for Burst Mode operation. 

## **Pulse-Skipping Mode Operation** 

In applications where low output ripple and high efficiency at intermediate currents are desired, pulse-skipping mode should be used. Pulse-skipping operation allows the LTM4650-2 to skip cycles at low output loads, thus increasing efficiency by reducing switching loss. Tying the MODE_PLLIN pin to INTVCC enables pulse-skipping operation. At light loads, the internal current comparator may remain tripped for several cycles and force the top MOSFET to stay off for several cycles, thus skipping cycles. The inductor current does not reverse in this mode. This mode will maintain higher effective frequencies thus lower output ripple and lower noise than Burst Mode operation. Either regulator can be configured for pulse-skipping mode. 

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## **APPLICATIONS INFORMATION** 

## **Forced Continuous Operation** 

In applications where fixed frequency operation is more critical than low current efficiency, and where the lowest output ripple is desired, forced continuous operation should be used. Forced continuous operation can be enabled by tying the MODE_PLLIN pin to GND. In this mode, the inductor current is allowed to reverse during low output loads, the COMP voltage is in control of the current comparator threshold throughout, and the top MOSFET always turns on with each oscillator pulse. During start-up, the forced continuous mode is disabled, and the inductor current is prevented from reversing until the LTM4650-2’s output voltage is in regulation. Either regulator can be configured for forced continuous mode. 

## **Multiphase Operation** 

For output loads that demand more than 25A of current, two outputs in LTM4650-2 or even multiple LTM4650-2s can be paralleled to run out of phase to provide more 

output current without increasing input and output voltage ripples. The MODE_PLLIN pin allows the LTM4650-2 to synchronize to an external clock (between 400kHz and 750kHz), and the internal phase-lockedloop allows the LTM4650-2 to lock onto the incoming clock phase as well. The CLKOUT signal can be connected to the MODE_PLLIN pin of the following stage to line up both the frequency and the phase of the entire system. Tying the PHASMD pin to INTVCC, SGND, or floating generates a phase difference (between MODE_PLLIN and CLKOUT) of 120 degrees, 60 degrees, or 90 degrees respectively. A total of 12 phases can be cascaded to run simultaneously with respect to each other by programming the PHASMD pin of each LTM4650-2 channel to different levels. Figure 5 shows a 2-phase design, a 4-phase design and a 6-phase design example for clock phasing with the PHASMD table. 

**==> picture [473 x 263] intentionally omitted <==**

**----- Start of picture text -----**<br>
2-PHASE DESIGN<br>PHASMD SGND FLOAT INTVCC<br>FLOAT<br>CONTROLLER1 0 0 0<br>CLKOUT<br>CONTROLLER2 180 180 240<br>MODE_PLLIN<br>0-PHASE 180-PHASE CLKOUT 60 90 120<br>VOUT1 VO UT2<br>PHA SMD<br>4-PHASE DESIGN<br>90-DEGREE<br>CLKOUT CLKOUT<br>MODE_PLLIN MODE_PLLIN<br>0-PHASE 180-PHASE 90-PHASE 270-PHASE<br>VOUT1 VO UT2 VOUT1 VO UT2<br>FLOAT FLOAT<br>PHA SMD PHA SMD<br>6-PHASE DESIGN<br>60-DEGREE 60-DEGREE<br>CLKOUT CLKOUT CLKOUT<br>MODE_PLLIN MODE_PLLIN MODE_PLLIN<br>0-PHASE 180-PHASE 60-PHASE 240-PHASE 120-PHASE 300-PHASE<br>VOUT1 VO UT2 VOUT1 VO UT2 VOUT1 VO UT2<br>SGND SGND FLOAT<br>PHA SMD PHA SMD PHA SMD<br>46502 F05<br>**----- End of picture text -----**<br>


**Figure 5. Examples of 2-Phase, 4-Phase, and 6-Phase Operation with PHASMD Table** 

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## **APPLICATIONS INFORMATION** 

A multiphase power supply significantly reduces the amount of ripple current in both the input and output capacitors. The RMS input ripple current is reduced by, and the effective ripple frequency is multiplied by the number of phases used (assuming that the input voltage is greater than the number of phases used times the output voltage). The output ripple amplitude is also reduced by the number of phases used when all of the outputs are tied together to achieve a single high-output current design. 

In multi LTM4650-2s parallel applications, CTH and RTH values in Table 4 are still valid to achieve a ±3% transient response in a 25% load step. Connect one set of RC (RTH and CTH) networks to the COMP pin of each paralleling module. Then, connect the COMP pins, FB pins, TRACK/SS pin and VOUT pins from different modules together. See Figure 29 for an example of parallel operation. LTpowerCAD power design tool can also be used to optimize loop compensation and transient performance if only one set of RC (RTH and CTH) network is to be added to the common COMP pins. 

The LTM4650-2 device is an inherently current modecontrolled device so that the parallel modules will have very good current sharing. This will balance the thermals on the design. Figure 29 shows an example of parallel operation and pin connection. 

## **Input RMS Ripple Current Cancellation** 

Application Note 77 provides a detailed explanation of multiphase operation. The input RMS ripple current cancellation mathematical derivations are presented, and a graph is displayed representing the RMS ripple current reduction as a function of the number of interleaved phases. Figure 6 shows this graph. 

## **Frequency Selection and Phase-Lock Loop (MODE_PLLIN and fSET Pins)** 

The LTM4650-2 device is operated over a range of frequencies to improve power conversion efficiency. It is recommended to operate the module at 400kHz for output voltage below 1.0V, 500kHz for output voltage between 1.0V to 1.5V and 600kHz for output voltage above 1.5V for the best efficiency and inductor current ripple. 

The LTM4650-2 switching frequency can be set with an external resistor from the fSET pin to SGND. An accurate 10µA current source into the resistor will set a voltage that programs the frequency, or a DC voltage can be applied. Figure 7 shows a graph of frequency setting versus programming voltage. An external clock can be applied to the MODE_PLLIN pin from 0V to INTVCC over a frequency range of 400kHz to 750kHz. The clock input high threshold is 1.6V, and the clock input low threshold is 1V. The LTM4650-2 has the PLL loop filter components on board. The frequency setting resistor should always be present to set the initial switching frequency before locking to an external clock. Both regulators will operate in continuous mode while being externally clock. 

The output of the PLL phase detector has a pair of complementary current sources that charge and discharge the internal filter network. When the external clock is applied, the fSET frequency resistor is disconnected with an internal switch, and the current sources control the frequency adjustment to lock to the incoming external clock. When no external clock is applied, the internal switch is on, thus connecting the external fSET frequency set resistor for free-run operation. 

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## **APPLICATIONS INFORMATION** 

**==> picture [308 x 290] intentionally omitted <==**

**----- Start of picture text -----**<br>
0.60<br>1-PHASE<br>0.55 2-PHASE<br>3-PHASE<br>4-PHASE<br>0.50 6-PHASE<br>0.45<br>0.40<br>0.35<br>0.30<br>0.25<br>0.20<br>0.15<br>0.10<br>0.05<br>0<br>0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9<br>DUTY FACTOR (VOUT/VIN) 46502 F06<br>DC LOAD CURRENT<br>RMS INPUT RIPPLE CURRENT<br>**----- End of picture text -----**<br>


**Figure 6. Input RMS Current Ratios to DC Load Current as a Function of Duty Cycle** 

**==> picture [160 x 161] intentionally omitted <==**

**----- Start of picture text -----**<br>
900<br>800<br>700<br>600<br>500<br>400<br>300<br>200<br>100<br>0<br>0 0.5 1 1.5 2 2.5<br>fSET PIN VOLTAGE (V)<br>46502 F07<br>FREQUENCY (kHz)<br>**----- End of picture text -----**<br>


**Figure 7. Operating Frequency vs fSET Pin Voltage** 

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## **APPLICATIONS INFORMATION** 

## **Minimum On-Time** 

Minimum on-time tON is the smallest time duration that the LTM4650-2 is capable of turning on the top MOSFET on either channel. It is determined by internal timing delays, and the gate charge required turning on the top MOSFET. Low-duty cycle applications may approach this minimum on-time limit, and care should be taken to ensure that: 

**==> picture [99 x 28] intentionally omitted <==**

If the duty cycle falls below what can be accommodated by the minimum on time, the controller will begin to skip cycles. The output voltage will continue to be regulated, but the output ripple and current will increase. The on-time can be increased by lowering the switching frequency. A good rule of thumb is to keep on time longer than 110ns. 

## **Output Voltage Tracking** 

Output voltage tracking can be programmed externally using the TRACK pins. The output can be tracked up and down with another regulator. The main regulator’s output is divided down with an external resistor divider that is the same as the subordinate regulator’s feedback divider to implement coincident tracking. The LTM4650-2 uses an accurate 60.4k resistor internally for the top feedback resistor for each channel. Figure 8 shows an example of coincident tracking. The equation: 

**==> picture [167 x 28] intentionally omitted <==**

VTRACK is the track ramp applied to the subordinate’s track pin. VTRACK has a control range of 0V to 0.6V, or the internal reference voltage. When the main’s output is divided down with the same resistor values used to set the subordinate’s output, then the subordinate will coincident 

**==> picture [477 x 291] intentionally omitted <==**

**----- Start of picture text -----**<br>
INTVCC<br>C10 R2<br>4.7µF 10k<br>PGOOD<br>4V TO 15V INTERMEDIATE BUS MODE_PLLIN CLKOUT INTVCC EXTVCC PGOOD1<br>C4 C3 C2 C1 VIN VOUT1 C6 C8 V(MAIN)OUT1<br>22µF 22µF 22µF 22µF R6100k VOUTS1 100µF 470µF 1.5V, 25A<br>25V 25V 25V 25V TEMP SW1 6.3V 6.3V<br>RUN1<br>VFB1<br>RUN2 VFB2<br>MAIN LTM4650-2 COMP1 RFB 40.2k<br>TRACK1 60.4k<br>CSS COMP2<br>0.1µF TRACK2<br>4.02k 4.02k<br>RTB RTA<br>60.4k 60.4k 2200pF 2200pF<br>1.5V VOUTS2<br>fSET VOUT2 SUBORDINATE C5 C7 V(SUBORDINATE)OUT2<br>SW2 PGOOD 100µF 470µF 1.2V, 25A<br>R4 PHASMD PGOO D2 6.3V 6.3V<br>121k<br>SGND GND DIFFP DIFFN DIFFOUT INTVCC<br>R9<br>10k<br>RAMP TIME<br>tSOFTSTART = (CSS/1.3µA) • 0.6<br>46502 F08<br>**----- End of picture text -----**<br>


**Figure 8. Example of Output Tracking Application Circuit** 

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## **APPLICATIONS INFORMATION** 

track with the main until it reaches its final value. The main will continue to its final value from the subordinate’s regulation point. Voltage tracking is disabled when VTRACK is more than 0.6V. RTA in Figure 8 will be equal to the RFB for coincident tracking. Figure 9 shows the coincident tracking waveforms. 

**==> picture [148 x 132] intentionally omitted <==**

**----- Start of picture text -----**<br>
MAIN OUTPUT<br>SUBORDINATE OUTPUT<br>TIME<br>46502 F09<br>OUTPUT VOLTAGE<br>**----- End of picture text -----**<br>


**Figure 9. Output Coincident Tracking Waveform** 

The TRACK pin of the main can be controlled by a capacitor placed on the main regulator TRACK pin to ground. A 1.3µA current source will charge the TRACK pin up to the reference voltage and then proceed up to INTVCC. After the 0.6V ramp, the TRACK pin will no longer be in control, and the internal voltage reference will control output regulation from the feedback divider. The foldback current limit is disabled during this sequence of turn-on during tracking or soft-starting. The TRACK pins are pulled low when the RUN pin is below 1.2V. The total soft-start time can be calculated as: 

**==> picture [129 x 28] intentionally omitted <==**

Regardless of the mode selected by the MODE_PLLIN pin, the regulator channels will always start in pulseskipping mode up to TRACK = 0.5V. Between TRACK = 0.5V and 0.54V, it will operate in forced continuous mode and revert to the selected mode once TRACK > 0.54V. To track with another channel once in steady state operation, 

the LTM4650-2 is forced into continuous mode operation as soon as VFB is below 0.54V, regardless of the setting on the MODE_PLLIN pin. 

Ratiometric tracking can be achieved by a few simple calculations and the slew rate value applied to the main’s TRACK pin. As mentioned above, the TRACK pin has a control range from 0 to 0.6V. The main’s TRACK pin slew rate is directly equal to the main’s output slew rate in Volts/Time. The equation: 

**==> picture [82 x 26] intentionally omitted <==**

where MR is the main’s output slew rate, and SR is the subordinate’s output slew rate in Volts/Time. When coincident tracking is desired, then MR and SR are equal. Thus RTB is equal to the 60.4k. RTA is derived from the equation: 

**==> picture [135 x 43] intentionally omitted <==**

- where VFB is the feedback voltage reference of the regula tor, and VTRACK is 0.6V. Since RTB is equal to the 60.4k top feedback resistor of the subordinate regulator in equal slew rate or coincident tracking, then RTA is equal to RFB with VFB = VTRACK. Therefore, RTB = 60.4k, and RTA = 60.4k in Figure 8. 

In ratiometric tracking, a different slew rate may be desired for the subordinate regulator. RTB can be solved when SR is slower than MR. Make sure that the subordinate supply slew rate is chosen to be fast enough so that the subordinate output voltage will reach its final value before the main output. 

For example, MR = 1.5V/1ms, and SR = 1.2V/1ms. Then RTB = 76.8k. Solve for RTA to equal to 49.9k. 

Each of the TRACK pins will have the 1.3µA current source on when a resistive divider is used to implement tracking on that specific channel. This will impose an offset on the TRACK pin input. Smaller values resistors with the same ratios as the resistor values calculated from the above equation can be used. For example, where the 60.4k is used then a 6.04k can be used, to reduce the TRACK pin offset to a negligible value. 

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## **APPLICATIONS INFORMATION** 

## **Power Good** 

The PGOOD pins are open drain pins that can be used to monitor valid output voltage regulation. This pin monitors a 10% window around the regulation point. A resistor can be pulled up to a particular supply voltage no greater than 6V maximum for monitoring. 

## **Stability Compensation** 

An external RC filtering circuit is required to add from COMP to SGND to achieve fast Type II control loop compensation. Table 4 is provided for most application requirements. The Analog Devices µModule power design tool (LTpowerCAD) will be provided for other control loop optimization. 

## **Run Enable** 

The RUN pins have an enable threshold of 1.4V maximum, typically 1.25V, with 150mV of hysteresis. They control the turn on each of the channels and INTVCC. These pins can be pulled up to VIN for 5V operation, or a 5V Zener diode can be placed on the pins, and a 10k to 100k resistor can be placed up to higher than 5V input to enable the channels. The RUN pins can also be used for output voltage sequencing. In parallel operation, the RUN pins can be tied together and controlled from a single control. See the Typical Applications circuits in Figure 24. 

## **INTVCC and EXTVCC** 

The LTM4650-2 module has an internal 5V low dropout regulator that is derived from the input voltage. This regulator is used to power the control circuitry and the power MOSFET drivers. This regulator can source up to 70mA, and typically uses ~30mA for powering the device at the maximum frequency. This internal 5V supply is enabled by either RUN1 or RUN2. 

EXTVCC allows an external 5V supply to power the LTM4650-2 and reduces power dissipation from the internal low dropout 5V regulator. The power loss savings can be calculated by: 

## (VIN – 5V) • 30mA = PLOSS 

EXTVCC has a threshold of 4.7V for activation, and a maximum rating of 6V. When using a 5V input, connect this 

5V input to EXTVCC also to maintain a 5V gate drive level. EXTVCC must sequence on after VIN, and EXTVCC must sequence off before VIN. 

## **Differential Remote Sense Amplifier** 

An accurate differential remote sense amplifier is provided to sense low output voltages accurately at the remote load points. This is especially true for high current loads. The amplifier can be used on one of the two channels, or on a single parallel output. It is very important that the DIFFP and DIFFN are connected properly at the output, and DIFFOUT is connected to either VOUTS1 or VOUTS2. In parallel operation, the DIFFP and DIFFN are connected properly at the output, and DIFFOUT is connected to one of the VOUTS pins. See the parallel schematics in Figure 25 and see Figure 4. 

## **SW Pins** 

The SW pins are generally for testing purposes by monitoring these pins. These pins can also be used to dampen out switch node ringing caused by LC parasitic in the switched current paths. Usually a series R-C combination is used called a snubber circuit. The resistor will dampen the resonance, and the capacitor is chosen only to affect the high-frequency ringing across the resistor. If the stray inductance or capacitance can be measured or approximated, then a somewhat analytical technique can be used to select the snubber values. The inductance is usually easier to predict. It combines the power path board inductance in combination with the MOSFET interconnect bond wire inductance. 

First, the SW pin can be monitored with a wide bandwidth scope with a high-frequency scope probe. The ring frequency can be measured by its value. The impedance Z can be calculated: 

## ZL = 2πfL, 

where f is the resonant frequency of the ring, and L is the total parasitic inductance in the switch path. If a resistor is selected that is equal to Z, then the ringing should be dampened. The snubber capacitor value is chosen so that its impedance is equal to the resistor at the ring frequency. Calculated by: ZC = 1/(2πfC). These values are a good place to start with. Modifications to these components 

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## **APPLICATIONS INFORMATION** 

should be made to attenuate the ringing with the least amount of power loss. 

## **Temperature Monitoring** 

Measuring the absolute temperature of a diode is possible due to the relationship between current, voltage and temperature described by the classic diode equation: 

**==> picture [73 x 29] intentionally omitted <==**

**==> picture [11 x 7] intentionally omitted <==**

**==> picture [75 x 30] intentionally omitted <==**

where ID is the diode current, VD is the diode voltage, η is the ideality factor (typically close to 1.0) and IS (saturation current) is a process-dependent parameter. VT can be broken out into: 

**==> picture [43 x 28] intentionally omitted <==**

where T is the diode junction temperature in Kelvin, q is the electron charge, and k is Boltzmann’s constant. VT is approximately 26mV at room temperature (298K) and scales linearly with Kelvin temperature. It is this linear temperature relationship that makes diodes suitable temperature sensors. The IS term in the previous equation is the extrapolated current through a diode junction when the diode has zero volts across the terminals. The IS term varies from process to process, varies with temperature, and by definition must always be less than ID. Combining all of the constants into one term: 

**==> picture [45 x 28] intentionally omitted <==**

where KD = 8.62 • 10[−5] , and knowing ln(ID/IS) is always positive because ID is always greater than IS, leaves us with the equation that: 

where VD appears to increase with temperature. It is common knowledge that a silicon diode biased with a current - source has an approximate –2mV/°C temperature rela tionship (Figure 10), which is at odds with the equation. In fact, the IS term increases with temperature, reducing the ln(ID/IS) absolute value and yielding an approximate –2mV/°C composite diode voltage slope. 

**==> picture [162 x 156] intentionally omitted <==**

**----- Start of picture text -----**<br>
0.8<br>0.7<br>0.6<br>0.5<br>0.4<br>0.3<br>–50 –25 0 25 50 75 100 125<br>TEMPERATURE (°C) 46502 F10<br>DIODE VOLTAGE (V)<br>**----- End of picture text -----**<br>


**Figure 10. Diode Voltage VD vs Temperature T (°C)** 

To obtain a linear voltage proportional to temperature, we cancel the IS variable in the natural logarithm term to remove the IS dependency from the equation. This is accomplished by measuring the diode voltage at two currents I1, and I2, where I1 = 10 • I2) and subtracting, we get: 

**==> picture [255 x 62] intentionally omitted <==**

**==> picture [151 x 13] intentionally omitted <==**

and redefining constant 

**==> picture [115 x 26] intentionally omitted <==**

yields 

**==> picture [116 x 13] intentionally omitted <==**

**==> picture [119 x 29] intentionally omitted <==**

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## **APPLICATIONS INFORMATION** 

Solving for temperature: 

**==> picture [237 x 29] intentionally omitted <==**

where 

300°K = 27°C 

means that is we take the difference in voltage across the diode measured at two currents with a ratio of 10, the resulting voltage is 198μV per Kelvin of the junction with a zero intercept at 0 Kelvin. 

The diode-connected PNP transistor at the TEMP pin can be used to monitor the internal temperature of the LTM4650-2. See Figure 25 for an example. 

## **Improve Transient Response and Reduce Output Capacitance with AVP** 

Fast load transient response, limited board space and low cost are requirements of microprocessor power supplies. Active voltage positioning improves transient response and reduces the output capacitance required to power a microprocessor, where in this case, a typical load step can be from 0A to 12.5A in 1μs or 12.5A to 0A in 1μs. 

Active voltage positioning is a form of deregulation. It sets the output voltage high for light loads and low for heavy loads. When the load current suddenly increases, the output voltage starts from a level higher than the nominal, so the output voltage can drop more and stay within the specified voltage range. When the load current suddenly decreases, the output voltage starts at a level lower than the nominal, so the output voltage can have more overshoot and stay within the specified voltage range. Less output capacitance is required when voltage positioning is used because more voltage variation is allowed on the output capacitors. 

Figure 30 and Figure 32 show the voltage regulator without AVP and with AVP. The load transient response before and after AVP implementation are shown on Figure 31 and Figure 33. On the design with AVP, the output voltage swings from 1.05V at minimum load to 0.95V at full load. The transient performance has been improved, while using fewer output capacitors. 

The Analog Devices design tool (LTpowerCAD) will be provided for AVP applications. 

## **Thermal Considerations and Output Current Derating** 

The thermal resistances reported in the Pin Configuration section of the data sheet are consistent with those parameters defined by JESD51-9 and are intended for use with finite element analysis (FEA) software modeling tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation performed on a µModule package mounted to a hardware test board— also defined by JESD51-9 (Test Boards for Area Array Surface Mount Package Thermal Measurements). The motivation for providing these thermal coefficients is found in JESD 51-12 (Guidelines for Reporting and Using Electronic Package Thermal Information). 

Many designers may opt to use laboratory equipment and a test vehicle such as the demo board to anticipate the µModule regulator’s thermal performance in their application at various electrical and environmental operating conditions to compliment any FEA activities. Without FEA software, the thermal resistances reported in the Pin Configuration section are in-and-of themselves not relevant to providing guidance on thermal performance; instead, the derating curves provided in the data sheet can be used in a manner that yields insight and guidance pertaining to one’s application-usage, and can be adapted to correlate thermal performance to one’s own application. 

The Pin Configuration section typically gives four thermal coefficients explicitly defined in JESD 51-12; these coefficients are quoted or paraphrased as follows: 

1. θ JA, the thermal resistance from junction to ambient, is the natural convection junction-to-ambient air thermal resistance measured in one cubic foot sealed enclosure. This environment is sometimes referred to as “still air”, although natural convection causes the air to move. This value is determined with the part mounted to a JESD 51-9 defined test board, which does not reflect an actual application or viable operating condition. 

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## **APPLICATIONS INFORMATION** 

2. θ JCbottom, the thermal resistance from the junction to the bottom of the product case, is the junction-to-board thermal resistance with all of the component power dissipation flowing through the bottom of the package. In the typical µModule, the bulk of the heat flows out the bottom of the package, but there is always heat flow out into the ambient environment. As a result, this thermal resistance value may be useful for comparing packages, but the test conditions don’t generally match the user’s application. 

3. θ JCtop, the thermal resistance from the junction to the top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. As the electrical connections of the typical µModule are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. As in the case of θ JCbottom, this value may be useful for comparing packages, but the test conditions don’t generally match the user’s application. 

4. θ JB, the thermal resistance from the junction to the printed circuit board, is the junction-to-board thermal resistance where almost all of the heat flows through the bottom of the µModule and into the board, and is really the sum of the θ JCbottom and the thermal resistance of the bottom of the part through the solder joints and through a portion of the board. The board 

temperature is measured at a specified distance from the package using a two-sided, two-layered board. This board is described in JESD 51-9. 

A graphical representation of the aforementioned thermal resistances is shown in Figure 11; blue resistances are contained within the µModule regulator, whereas green resistances are external to the µModule. 

As a practical matter, it should be clear to the reader that no individual or sub-group of the four thermal resistance parameters defined by JESD 51-12 or provided in the Pin Configuration section replicates or conveys normal operating conditions of a µModule. For example, in normal board-mounted applications, never does 100% of the device’s total power loss (heat) thermally conducts exclusively through the top or exclusively through the bottom of the µModule—as the standard defines for θ JCtop and θ JCbottom, respectively. In practice, power loss is thermally dissipated in both directions away from the package—granted, in the absence of a heat sink and airflow, a majority of the heat flow is into the board. 

Within a SIP (system-in-package) module, be aware that there are multiple power devices and components dissipating power, with the consequence that the thermal resistances relative to different junctions of components or die are not exactly linear with respect to total package power loss. To reconcile this complication without sacrificing modeling simplicity—but also, not ignoring 

**==> picture [371 x 154] intentionally omitted <==**

**----- Start of picture text -----**<br>
JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)<br>JUNCTION-TO-CASE (TOP) CASE (TOP)-TO-AMBIENT<br>RESISTANCE RESISTANCE<br>JUNCTION-TO-BOARD RESISTANCE<br>JUNCTION AMBIENT<br>JUNCTION-TO-CASE CASE (BOTTOM)-TO-BOARD BOARD-TO-AMBIENT<br>(BOTTOM) RESISTANCE RESISTANCE RESISTANCE<br>46502 F11<br>µModule DEVICE<br>**----- End of picture text -----**<br>


**Figure 11. Graphical Representation of JESD51-12 Thermal Coefficients** 

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## **APPLICATIONS INFORMATION** 

practical realities—an approach has been taken using FEA software modeling along with laboratory testing in a controlled-environment chamber to reasonably define and correlate the thermal resistance values supplied in this data sheet: (1) Initially, FEA software is used to accurately build the mechanical geometry of the µModule and the specified PCB with all of the correct material coefficients along with accurate power loss source definitions; (2) this model simulates a software-defined JEDEC environment consistent with JSED51-9 to predict power loss heat flow and temperature readings at different interfaces that enable the calculation of the JEDEC-defined thermal resistance values; (3) the model and FEA software is used to evaluate the µModule with heat sink and airflow; (4) having solved for and analyzed these thermal resistance values and simulated various operating conditions in the software model, a thorough laboratory evaluation replicates the simulated conditions with thermocouples within a controlled-environment chamber while operating the device at the same power loss as that which was simulated. An outcome of this process and due diligence yields a set of derating curves provided in other sections of this data sheet. After these laboratory tests have been performed and correlated to the µModule model, then the θ JB and θ BA are summed together to correlate quite well with the µModule model with no airflow or heat sinking in a properly defined chamber. This θ JB + θ BA value is shown in the Pin Configuration section and should accurately equal the θ JA value because approximately 100% of power loss flows from the junction through the board into the ambient with no airflow or top-mounted heat sink. Each system has its own thermal characteristics, therefore thermal analysis must be performed by the user in a particular system. 

The LTM4650-2 module has been designed to effectively remove heat from both the top and bottom of the package. The bottom substrate material has very low thermal resistance to the printed circuit board. An external heat sink can be applied to the top of the device for excellent heat sinking with airflow. 

**Figure 12. Thermal Image 12V to 1V, 50A with No Airflow and No Heat Sink (Based on 4-Layer 101mm × 114mm PCB Board Containing 2oz Copper on the Top, Bottom and All Internal Layers)** 

## **Safety Considerations** 

The LTM4650-2 modules do not provide isolation from VIN to VOUT. There is no internal fuse. If required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure. The device does support over current protection. A temperature diode is provided for monitoring internal temperature, and can be used to detect the need for thermal shutdown that can be done by controlling the RUN pin. 

## **Power Derating** 

The 0.9V and 1.5V power loss curves in Figure 13 and Figure 14 can be used in coordination with the load current derating curves in Figure 15 to Figure 22 for calculating an approximate θ JA thermal resistance for the LTM4650-2 with various heat sinking and airflow conditions. The power loss curves are taken at room temperature, and are increased with a 1.2 multiplicative factor at 120°C. 

Figure 12 shows a temperature plot of the LTM4650-2 with 12V input, 1.0V output at 50A without a heat sink and a no airflow condition. 

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## **APPLICATIONS INFORMATION** 

The derating curves are plotted with CH1 and CH2 in parallel single output operation starting at 50A of load with low ambient temperature. The output voltages are 0.9V and 1.5V. These are chosen to include the lower and higher output voltage ranges for correlating the thermal resistance. Thermal models are derived from several temperature measurements in a controlled temperature chamber, along with thermal modeling analysis. 

The junction temperatures are monitored while ambient temperature is increased with and without airflow. The power loss increase with ambient temperature change is factored into the derating curves. The junctions are maintained at ~120°C maximum while lowering output 

current or power while increasing ambient temperature. The decreased output current will decrease the internal module loss as ambient temperature is increased. 

The monitored junction temperature of 120°C minus the ambient operating temperature specifies how much module temperature rise can be allowed. As an example in Figure 16, the load current is derated to ~35A at ~90°C with 200LFM air, but not heat sink and the power loss for the 12V to 0.9V at 35A output is a ~5.6W loss. The 5.6W loss is calculated with the ~4.7W room temperature loss from the 12V to 0.9V power loss curve at 35A, and the 1.20 multiplying factor at 120°C junction temperature. If the 90°C ambient temperature is subtracted from 

**==> picture [518 x 166] intentionally omitted <==**

**----- Start of picture text -----**<br>
10 10 60<br>VIN = 12V VIN = 12V<br>9 V IN  = 5V 9 V IN  = 5V<br>50<br>8 8<br>7 7<br>40<br>6 6<br>5 5 30<br>4 4<br>20<br>3 3<br>2 2 0LFM<br>10<br>200LFM<br>1 1<br>400LFM<br>0 0 0<br>0 10 20 30 40 50 0 10 20 30 40 50 25 35 45 55 65 75 85 95 105 115<br>LOAD CURRENT (A) LOAD CURRENT (A) AMBIENT TEMPERATURE (°C)<br>46502 F13 46502 F14 46502 F15<br>POWER LOSS (W) POWER LOSS (W)<br>OUTPUT CURRENT (A)<br>**----- End of picture text -----**<br>


**Figure 13. 0.9V Output Power Loss Curve** 

**Figure 14. 1.5V Output Power Loss Curve** 

**Figure 15. 5V to 0.9V Derating Curve, No Heat Sink** 

**==> picture [373 x 165] intentionally omitted <==**

**----- Start of picture text -----**<br>
60 60<br>50 50<br>40 40<br>30 30<br>20 20<br>0LFM 0LFM<br>10 10<br>200LFM 200LFM<br>400LFM 400LFM<br>0 0<br>25 35 45 55 65 75 85 95 105 115 25 35 45 55 65 75 85 95 105 115<br>AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)<br>46502 F16 46502 F17<br>OUTPUT CURRENT (A) OUTPUT CURRENT (A)<br>**----- End of picture text -----**<br>


**Figure 16. 12V to 0.9V Derating Curve, No Heat Sink** 

**Figure 17. 5V to 0.9V Derating Curve, BGA Heat Sink** 

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## **APPLICATIONS INFORMATION** 

**==> picture [519 x 405] intentionally omitted <==**

**----- Start of picture text -----**<br>
60 60 60<br>50 50 50<br>40 40 40<br>30 30 30<br>20 20 20<br>0LFM 0LFM 0LFM<br>10 10 10<br>200LFM 200LFM 200LFM<br>400LFM 400LFM 400LFM<br>0 0 0<br>25 35 45 55 65 75 85 95 105 115 25 35 45 55 65 75 85 95 105 115 25 35 45 55 65 75 85 95 105 115<br>AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)<br>46502 F18 46502 F19 46502 F20<br>Figure 18. 12V to 0.9V Derating  Figure 19. 5V to 1.5V Derating  Figure 20. 12V to 1.5V<br>Curve, BGA Heat Sink Curve, No Heat Sink Derating Curve, No Heat Sink<br>60 60<br>50 50<br>40 40<br>30 30<br>20 20<br>0LFM 0LFM<br>10 10<br>200LFM 200LFM<br>400LFM 400LFM<br>0 0<br>25 35 45 55 65 75 85 95 105 115 25 35 45 55 65 75 85 95 105 115<br>AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)<br>46502 F21 46502 F22<br>OUTPUT CURRENT (A) OUTPUT CURRENT (A) OUTPUT CURRENT (A)<br>OUTPUT CURRENT (A) OUTPUT CURRENT (A)<br>**----- End of picture text -----**<br>


**Figure 21. 5V to 1.5V Derating Curve, BGA Heat Sink** 

**Figure 22. 12V to 1.5V Derating Curve, BGA Heat Sink** 

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## **APPLICATIONS INFORMATION** 

the 120°C junction temperature, then the difference of 30°C divided by 5.5W equals a 5.4°C/W θ JA thermal resistance. Table 2 specifies a 5.5°C/W value, which is pretty close. Table 2 and Table 3 provide equivalent thermal resistances for 0.9V and 1.5V outputs with and without airflow and heat sinking. 

The derived thermal resistances in Table 2 and Table 3 for the various conditions can be multiplied by the calculated power loss as a function of ambient temperature to 

derive temperature rise above ambient, thus maximum junction temperature. Room temperature power loss can be derived from the efficiency curves and adjusted - with the above ambient temperature multiplicative fac tors. The printed circuit board is a 1.6mm thick 4-layer board with 2oz copper on each layer. The PCB dimensions are 101mm × 114mm. The BGA heat sinks are listed in Table 3. 

## **Table 2. 0.9V Output** 

|**Table 2. 0.9V Output**||||||
|---|---|---|---|---|---|
|**DERATING CURVE**|**VIN (V)**|**POWER LOSS CURVE**|**AIRFLOW(LFM)**|**HEAT SINK**|θ**JA (°C/W)**|
|Figure 15,Figure 16|5,12|Figure 13|0|None|7.5|
|Figure 15,Figure 16|5,12|Figure 13|200|None|5.5|
|Figure 15,Figure 16|5,12|Figure 13|400|None|5|
|Figure 17,Figure 18|5,12|Figure 13|0|BGA Heat Sink|7|
|Figure 17,Figure 18|5,12|Figure 13|200|BGA Heat Sink|4.5|
|Figure 17,Figure 18|5,12|Figure 13|400|BGA Heat Sink|4|



**Table 3. 1.5V Output** 

|**Table 3. 1.5V Output**||||||
|---|---|---|---|---|---|
|**DERATING CURVE**|**VIN (V)**|**POWER LOSS CURVE**|**AIRFLOW(LFM)**|**HEAT SINK**|θ**JA (°C/W)**|
|Figure 19,Figure 20|5,12|Figure 14|0|None|7.5|
|Figure 19,Figure 20|5,12|Figure 14|200|None|5.5|
|Figure 19,Figure 20|5,12|Figure 14|400|None|5|
|Figure 21,Figure 22|5,12|Figure 14|0|BGA Heat Sink|7|
|Figure 21,Figure 22|5,12|Figure 14|200|BGA Heat Sink|4.5|
|Figure 21,Figure 22|5,12|Figure 14|400|BGA Heat Sink|4|
|**HEAT SINK MANUFACTURER**<br>**PART NUMBER**<br>**WEBSITE**<br>Wakefield<br>LTN20069-T5<br>wakefield-vette.com||||||
|**HEAT SINK MANUFACTURER**||**PART NUMBER**|**WEBSITE**|||
|Wakefield||LTN20069-T5|wakefield-vette.com|||



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## **APPLICATIONS INFORMATION** 

|**COUT (BULK)**|**PART NUMBER**|**2-Phase Single Output Solution**|2R5TPF680M6L|EEFGX0E471R|||**25% Load Step (0A to 12.5A) Ceramic Output Capacitor Only Solutions**|**FREQ**<br>**(kHz)**|500|500|600|600|**25% Load Step (0A to 9A) Bulk plus Ceramic Output Capacitor Solutions**|500|500|600|600|**50% Load Step (0A to 25A) Ceramic Output Capacitor Only Solutions**|500|500|600|600|**50% Load Step (0A to 25A) Bulk + Ceramic Output Capacitor Solutions**|500|500|600|600|*Bulk input capacitor is only needed if the input source impedance is compromised by long inductive leads.|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|||||||||**RFB**<br>**(kΩ)**|90.9|60.4|40.2|30.2||90.9|60.4|40.2|30.2||90.9|60.4|40.2|30.2||90.9|60.4|40.2|30.2||
|||||||||**LOAD**<br>**STEP**<br>**SLEW**<br>**RATE**<br>**(A/μs)**|10|10|10|10||10|10|10|10||10|10|10|10||10|10|10|10||
||**VALUE**||680µF, 2.5V,<br>6mΩ|470µF, 2.5V,<br>3mΩ||||**LOAD**<br>**STEP**<br>**(A)**|12.5|12.5|12.5|12.5||12.5|12.5|12.5|12.5||25|25|25|25||25|25|25|25||
|||||||||**CTRL**<br>**LOOP**<br>**PHASE**<br>**MARGIN**<br>**(PM)**|47 Deg|49 Deg|58 Deg|65 Deg||68 Deg|73 Deg|53 Deg|58 Deg||45 Deg|50 Deg|45 Deg|50 Deg||57 Deg|65 Deg|49 Deg|46 Deg||
||**VENDOR**||Panasonic|Panasonic||||<br>**CTRL**<br>**LOOP**<br>**BAND-**<br>**WIDTH**<br>**BW (kHz)**|88|89|91|98||82|82|59|51||76|77|47|43||70|67|50|51||
|||||||||**SETTLING**<br>**TIME**<br>**tSETTLE**<br>**(μs)**|80|80|80|90||30|30|30|30||80|80|80|90||30|30|40|50||
|**COUT (CERAMIC)**|**PART NUMBER**||GRM32ER60J107ME20L|GRM31CR60G227M|JMK325BJ107MM-T|AMK325ABJ227MM-T||<br>**PEAK-PEAK**<br>**DEVIATION**<br>**VPK-PK**<br>**(mV)**|53|56|58|64||55|55|64|75||58|61|90|105||47|48|56|58||
|||||||||**FEED-**<br>**FORWARD**<br>**CAPACITOR**<br>**CFF (pF)**|68|68|68|68||68|68|None|None||100|100|None|None||47|47|None|None||
||**VALUE**||100µF, 6.3V, X5R, 1210|220µF, 4V, X5R, 1206|100µF, 6.3V, X5R, 1210|220µF, 4V, X5R, 1210||**COMP PIN**<br>**CAPACITOR**<br>**CTH**|10nF|10nF|10nF|10nF||3300pF|3300pF|3300pF|3300pF||4.7nF|4.7nF|4.7nF|4.7nF||3300pF|3300pF|3300pF|3300pF||
|||||||||<br>**COMP PIN**<br>**RESISTOR**<br>**RTH (kΩ)**|3.24|3.24|3.24|3.24||3.16|3.16|4.12|4.12||6.81|6.81|5.90|5.90||12.0k|12.0k|10.2k|14.5k||
||**VENDOR**||Murata|Murata|Taiyo<br>Yuden|Taiyo<br>Yuden||**COMP PIN**<br>**PARALLEL**<br>**CAPACITOR**<br>**CTHP(pF)**|33|33|33|33||33|33|82|82||33|33|33|33||33|33|68|82||
|**CIN (CERAMIC)**|**PART NUMBER**||GRM32ER61C226KE20L|GRM31CR61C226KE15K|C3225X5R1C226M250AA|||**COUT**<br>**CERAMIC**<br>**(μF)**|220 ×6|220 ×5|220 ×4|220 ×4||100 ×4|100 ×4|100 ×4|100 ×4||220 ×12|220 ×12|220 ×14|220 ×14||100 ×4|100 ×4|100 ×4|100 ×4||
|||||||||**COUT**<br>**BULK**<br>**(μF)**|None|None|None|None||470 ×2|470 ×2|470 ×2|470 ×2||None|None|None|None||470 ×6|470 ×6|470 ×6|470 ×6||
|||||||||**CIN**<br>**CERAMIC**<br>**(μF)**|22 ×2|22 ×2|22 ×2|22 ×2||22 ×2|22 ×2|22 ×2|22 ×2||22 ×2|22 ×2|22 ×2|22 ×2||22 ×2|22 ×2|22 ×2|22 ×2||
||**VALUE**||22µF, 16V, X5R,<br>1210|22µF, 16V, X5R,<br>1206|22µF, 16V, X5R,<br>1210|||**CIN* **<br>**BULK**<br>**(μF)**|150|150|150|150||150|150|150|150||150|150|150|150||150|150|150|150||
|||||||||**VOUT**<br>**(V)**|1|1.2|1.5|1.8||1|1.2|1.5|1.8||1|1.2|1.5|1.8||1|1.2|1.5|1.8||
|||||||||**VIN**<br>**(V)**|12|12|12|12||12|12|12|12||12|12|12|12||12|12|12|12||
||**VENDOR**||Murata|Murata|TDK|||**PEAK-PEAK**<br>**DEVIATION**<br>**PERCENTAGE**|±3% (<60mV)|±3% (<72mV)|±3% (<90mV)|±3% (<108mV)||±3% (<60mV)|±3% (<72mV)|±3% (<90mV)|±3% (<108mV)||±3% (<60mV)|±3% (<72mV)|±3% (<90mV)|±3% (<108mV)||±3% (<60mV)|±3% (<72mV)|±3% (<90mV)|±3% (<108mV)||



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## **APPLICATIONS INFORMATION** 

## **Layout Checklist/Example** 

The high integration of LTM4650-2 makes the PCB board layout very simple and easy. However, to optimize its electrical and thermal performance, some layout considerations are still necessary. 

- Use large PCB copper areas for high current paths, including VIN, GND, VOUT1 and VOUT2. It helps to minimize the PCB conduction loss and thermal stress. 

- Place high-frequency ceramic input and output capacitors next to the VIN, PGND and VOUT pins to minimize high-frequency noise. 

- Place a dedicated power ground layer underneath the unit. 

- To minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between the top layer and other power layers. 

- Do not put via directly on the pad, unless they are capped or plated over. 

- Use a separated SGND ground copper area for components connected to signal pins. Connect the SGND to the GND underneath the unit. 

- For parallel modules, tie the VOUT, VFB, and COMP pins together. Use an internal layer to closely connect these pins together. The TRACK pin can be tied to a common capacitor for regulator soft-start. 

- Bring out test points on the signal pins for monitoring. 

Figure 23 gives a good example of the recommended layout. LGA and BGA PCB layouts are identical, with the exception of circle pads for BGA (see Package Description section). 

**==> picture [265 x 266] intentionally omitted <==**

**----- Start of picture text -----**<br>
CIN1 CIN2<br>VIN<br>M<br>L<br>K<br>GND GND<br>J<br>H<br>G<br>SGND<br>F<br>COUT1 COUT2<br>E<br>CNTRL<br>D<br>C<br>B<br>A<br>1 2 3 4 5 6 7 8 9 10 11 12<br>VOUT1 GND VOUT2<br>46502 F23<br>**----- End of picture text -----**<br>


**Figure 23. Recommended PCB Layout** 

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## **TYPICAL APPLICATIONS** 

**==> picture [468 x 534] intentionally omitted <==**

**----- Start of picture text -----**<br>
INTVCC<br>INTVCC C10<br>R2<br>4.7µF 10k<br>PGOOD1<br>MODE_PLLIN CLKOUT INTVCC EXTVCC PGOOD1<br>4.5V TO 15VVIN + C(OPT)IN C122µF25V R7100k VTEMPIN VVOUTS1OUT1SW1 C100µF6.3VOUT1 + 470µFCOUT21.5V, 25AVOUT1<br>×4 RUN1 VFB1 6.3V<br>RUN2 VFB2<br>TRACK1 TRACK1 RFB2 RFB1<br>C5 LTM4650-2 60.4k 40.2k<br>0.1µF TRACK2 TRACK2<br>C9 VOUT2 VOUT2<br>0.1µF INTVCC COUT3 1.2V, 25A<br>COMP1 SW2 R3 100µF + COUT4<br>COMP2 10k 6.3V 470µF<br>6.49k 6.49k fSET PGOOD2 PGOOD2 6.3V<br>R4 PHASMD VOUTS2<br>4700pF 121k SGND GND DIFFN DIFFP DIFFOUT<br>4700pF<br>46502 F24<br>Figure 24. Typical 4.5VIN to 15VIN, 1.5V and 1.2V at 25A Outputs<br>INTVCC<br>INTVCC<br>C10 R2<br>4.7µF 10k<br>PGOOD<br>MODE_PLLIN CLKOUT INTVCC EXTVCC PGOOD1<br>4.5V TO 15VVIN C22µFIN VRUN1IN VVOUT1OUT2 C220µFOUT1 1V,50AVOUT<br>25V RUN RUN2 VOUTS1 4V<br>×4 ×6<br>TRACK T R ACK1 SW1<br>TR ACK2<br>VFB1<br>C90.1µF COMP1COMP2 LTM4650-2 VFB2 R590.9k<br>68pF<br>TEMP TEMP<br>MONITOR VOUT2<br>3.24k VOUTS2<br>33pF fSET S W2<br>10nF R4 PHASMD PGOO D2 PGOOD<br>121k<br>SGND GND DIFFN DIFFP DIFFOUT<br>46502 F25<br>**----- End of picture text -----**<br>


**==> picture [95 x 6] intentionally omitted <==**

**----- Start of picture text -----**<br>
SEE TABLE 4 FOR MORE DETAILS<br>**----- End of picture text -----**<br>


**Figure 25. 2-Phase, 1V at 50A Design** 

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## **TYPICAL APPLICATIONS** 

**==> picture [210 x 87] intentionally omitted <==**

**----- Start of picture text -----**<br>
VOUT(AC)<br>20mV/DIV {| | | Y_ 54mV<br>, | |<br>LOAD STEP a<br>10A/DIV ee ee eee<br>46502 F26<br>50µs/DIV<br>**----- End of picture text -----**<br>


**==> picture [249 x 29] intentionally omitted <==**

**----- Start of picture text -----**<br>
-40.000-2 0.000 -60.000-3 . 000. 0 0 0<br>PHASE<br>GAIN (dB)<br>**----- End of picture text -----**<br>


**==> picture [18 x 4] intentionally omitted <==**

**----- Start of picture text -----**<br>
46502 F27<br>**----- End of picture text -----**<br>


**Figure 26. 25%, 12.5A Load Step Transient Waveform of Figure 25 Circuit** 

**Figure 27. Bode Plot of Figure 25 Circuit** 

**==> picture [423 x 247] intentionally omitted <==**

**----- Start of picture text -----**<br>
INTVCC<br>INTVCC<br>C10 R2<br>LL 4.7µF 10k<br>PGOOD1<br>4.5V TO 15VVIN CIN R6 MODE_PLLINVIN CLKOUT INTVCC EXTVCC PGOOD1VOUT1 COUT1 + COUT2 V1.2V,25AOUT1<br>22µF 100k VOUTS1 100µF 470µF<br>25V TEMP SW 1 6.3V 6.3V<br>×4 ×2<br>RUN1 VFB1<br>Ld<br>RUN2 VFB2<br>TRACK1 LTM4650-2 R8 R5<br>C5 90.9k 60.4k<br>0.1µF TRACK2<br>R9<br>60.4k R790.9k VOUTS2 VOUT2<br>VOUT1 1V AT 25A<br>1.2V COMP1COMP2 VOUT2SW2 INTVR3CC C100µFOUT1 + C470µFOUT2<br>6.34k 6.34k fSET 10k 6.3V×2 6.3V<br>R4 PHASMD PGOO D2 PGOOD2<br>1500pF 121k SGND GND DIFFP DIFFN DIFFOUT<br>1500pF<br>46502 F28<br>**----- End of picture text -----**<br>


**Figure 28. 1.2V and 1V Output Tracking** 

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## **TYPICAL APPLICATION** 

**==> picture [481 x 463] intentionally omitted <==**

**----- Start of picture text -----**<br>
INTVCC INTVCC<br>C10 R2<br>4.7µF 5k<br>CLK1<br>PGOOD<br>MODE_PLLIN CLKOUT INTVCC EXTVCC PGOOD1<br>VIN<br>4.5V TO 15V CIN1 R6 VIN VOUT1 COUT1 + COUT2<br>22µF 100k VOUTS1 100µF 470µF<br>25V TEMP SW1 6.3V 6.3V<br>×3 VFB ×2<br>RUN RUN1 VFB1<br>RUN2 VFB2 R5<br>LTM4650-2 60.4k<br>TRACK TRACK1<br>68pF<br>TRACK2<br>COMP1 VOUT2<br>COMP COMP2 VOUTS2 C100µFOUT1 + C470µFOUT2<br>fSET S W2 6.3V×2 6.3V<br>33pF 3.16k PHASMD PGOO D2 PGOOD<br>3300pF R4121k SGND GND DIFFP DIFFN DIFFOUT<br>VOUT<br>1.2V,<br>100A<br>C16<br>4.7µF<br>CLK1 PGOOD<br>MODE_PLLIN CLKOUT INTVCC EXTVCC PGOOD1<br>CIN2 R9 VIN VOUT1 COUT1 + COUT2<br>22µF 100k VOUTS1 100µF 470µF<br>25V T E MP SW1 6.3V 6.3V<br>×3 ×2<br>RUN RUN1 VFB1 VFB<br>RUN2 VFB2<br>TRACK TRACK1 LTM4650-2<br>TRACK2<br>C19<br>0.22µF COMP1 VOUTS2<br>COMP2 VOUT2<br>fSET S W2 C100µFOUT1 + C470µFOUT2<br>33pF 3.16k PHASMD PGOO D2 PGOOD 6.3V 6.3V<br>×2<br>3300pF R10 SGND GND DIFFP DIFFN DIFFOUT<br>121k<br>46502 F29<br>INTVCC<br>**----- End of picture text -----**<br>


**Figure 29. 4-Phase, 1.2V at 100A** 

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## **TYPICAL APPLICATION** 

**==> picture [505 x 242] intentionally omitted <==**

**----- Start of picture text -----**<br>
INTVCC INTVCC<br>C10<br>R2<br>4.7µF 10k<br>PGOOD1<br>MODE_PLLIN CLKOUT INTVCC EXTVCC PGOOD1<br>4.5V TO 15VVIN + C330µFIN C122µF R7100k VIN VVOUTS1OUT1 C100µFOUT1 + COUT21V, 25AVOUT1<br>25V 25V TEMP SW1 6.3V 470µF<br>×4 RUN1 VFB1 VFB1 ×5 6.3V<br>×2<br>RUN2 VFB2<br>TRACK1C5 TRACK1 LTM4650-2 R40.2kFB2 R90.9kFB1<br>0.1µF TRACK2 TRACK2<br>C9 VOUT2 VOUT2<br>0.1µF INTVCC COUT3 1.5V, 25A<br>COMP1 SW2 R3 100µF + COUT4<br>COMP2 10k 6.3V 470µF<br>R16 R13 fSET PGOOD2 PGOOD2 ×5 6.3V<br>20k C15 21k C12 R4 PHASMD VOUTS2 ×2<br>C16 220pF C13 47pF 121k SGND GND DIFFN DIFFP DIFFOUT<br>4700pF 3300pF<br>46502 F30<br>**----- End of picture text -----**<br>


**Figure 30. Circuit without AVP, Typical 4.5VIN to 15VIN, 1VOUT and 1.5VOUT at 25A** 

**==> picture [192 x 118] intentionally omitted <==**

**----- Start of picture text -----**<br>
VOUT (AC)<br>30mV/DIV<br>LOAD STEP<br>10A/DIV<br>100µs/DIV 46502 F31<br>**----- End of picture text -----**<br>


**Figure 31. Load Transient Waveform of Figure 30 Circuit (without AVP), 12VIN, 1VOUT, 500kHz, 12.5A (50% of Full Load, Slew Rate 12.5A/μs), COUT1 = 100μF ×5 Ceramic, COUT2 = 470μF ×2 POSCAP** 

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## **TYPICAL APPLICATION** 

**==> picture [446 x 242] intentionally omitted <==**

**----- Start of picture text -----**<br>
INTVCC INTVCC<br>C10<br>R2<br>4.7µF 10k<br>PGOOD1<br>MODE_PLLIN CLKOUT INTVCC EXTVCC PGOOD1<br>4.5V TO 15VVIN + C330µFIN C122µF R7100k VIN VVOUTS1OUT1 C100µFOUT1 + C1V, 25AVOUT2OUT1<br>25V 25V TEMP SW1 6.3V 470µF<br>×4 RUN1 VFB1 VFB1 ×3 6.3V×2<br>RUN2 VFB2<br>TRACK1C5 TRACK1 LTM4650-2 R40.2kFB2 R82.6kFB1<br>VFB1 0.1µF TRACK2 TRACK2<br>R185M R19560k C90.1µF VOUT2 INTVCC COUT3 V1.5V, 25AOUT2<br>INTVCC COMP1COMP2 SW2 R310k 100µF6.3V + 470µFCOUT4<br>R1321k C12 R4 fPHASMDSET PGOOD2VOUTS2 PGOOD2 ×5 6.3V×2<br>C13 47pF 121k SGND GND DIFFN DIFFP DIFFOUT<br>3300pF<br>46502 F32<br>**----- End of picture text -----**<br>


**Figure 32. Circuit with AVP, Typical 4.5VIN to 15VIN, 1VOUT (with AVP) and 1.5VOUT at 25A with 12.5A Load Step Transient Response and 1VOUT (with AVP), 4.5VIN (78k RFB1) to 15VIN (84k RFB1)** 

**==> picture [192 x 118] intentionally omitted <==**

**----- Start of picture text -----**<br>
VOUT (AC)<br>30mV/DIV<br>LOAD STEP<br>10A/DIV<br>100µs/DIV 46502 F33<br>**----- End of picture text -----**<br>


**Figure 33. Load Transient Waveform of Figure 32 Circuit with AVP, 12VIN, 1VOUT, 500kHz, 12.5A (50% of Full Load, Slew Rate 12.5A/μs), COUT1 = 100μF ×3 Ceramic, COUT2 = 470μF ×2 POSCAP** 

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## **PACKAGE DESCRIPTION** 

**Table 5. LTM4650-2 Component BGA Pinout** 

|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|A1|VOUT1|B1|VOUT1|C1|VOUT1|D1|GND|E1|GND|F1|GND|
|A2|VOUT1|B2|VOUT1|C2|VOUT1|D2|GND|E2|GND|F2|GND|
|A3|VOUT1|B3|VOUT1|C3|VOUT1|D3|GND|E3|GND|F3|GND|
|A4|VOUT1|B4|VOUT1|C4|VOUT1|D4|GND|E4|GND|F4|MODE_PLLIN|
|A5|VOUT1|B5|VOUT1|C5|VOUTS1|D5|VFB1|E5|TRACK1|F5|RUN1|
|A6|GND|B6|GND|C6|fSET|D6|SGND|E6|COMP1|F6|SGND|
|A7|GND|B7|GND|C7|SGND|D7|VFB2|E7|COMP2|F7|SGND|
|A8|VOUT2|B8|VOUT2|C8|VOUTS2|D8|TRACK2|E8|DIFFP|F8|DIFFOUT|
|A9|VOUT2|B9|VOUT2|C9|VOUT2|D9|GND|E9|DIFFN|F9|RUN2|
|A10|VOUT2|B10|VOUT2|C10|VOUT2|D10|GND|E10|GND|F10|GND|
|A11|VOUT2|B11|VOUT2|C11|VOUT2|D11|GND|E11|GND|F11|GND|
|A12|VOUT2|B12|VOUT2|C12|VOUT2|D12|GND|E12|GND|F12|GND|
|||||||||||||
|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|
|G1|GND|H1|GND|J1|GND|K1|GND|L1|GND|M1|GND|
|G2|SW1|H2|GND|J2|VIN|K2|VIN|L2|VIN|M2|VIN|
|G3|GND|H3|GND|J3|VIN|K3|VIN|L3|VIN|M3|VIN|
|G4|PHASMD|H4|GND|J4|VIN|K4|VIN|L4|VIN|M4|VIN|
|G5|CLKOUT|H5|GND|J5|GND|K5|GND|L5|VIN|M5|VIN|
|G6|SGND|H6|GND|J6|TEMP|K6|GND|L6|VIN|M6|VIN|
|G7|SGND|H7|GND|J7|EXTVCC|K7|GND|L7|VIN|M7|VIN|
|G8|PGOOD2|H8|INTVCC|J8|GND|K8|GND|L8|VIN|M8|VIN|
|G9|PGOOD1|H9|GND|J9|VIN|K9|VIN|L9|VIN|M9|VIN|
|G10|GND|H10|GND|J10|VIN|K10|VIN|L10|VIN|M10|VIN|
|G11|SW2|H11|GND|J11|VIN|K11|VIN|L11|VIN|M11|VIN|
|G12|GND|H12|GND|J12|GND|K12|GND|L12|GND|M12|GND|



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## **PACKAGE DESCRIPTION** 

**==> picture [473 x 608] intentionally omitted <==**

**----- Start of picture text -----**<br>
6<br>3<br>SEE NOTES<br>PIN 1 SEE NOTES<br>1 2 3 4 5 6 7 8 9 10 11 12<br>A BGA 144 0517 REV A<br>B<br>DETAIL A<br>C<br>D<br>e<br>E<br>F<br>G<br>G<br>H<br>PACKAGE BOTTOM VIEW<br>J µModule<br>LTMXXXXXX<br>K b PACKAGE IN TRAY LOADING ORIENTATION<br>PACKAGE ROW AND COLUMN LABELING MAY VARY  AMONG µModule PRODUCTS. REVIEW EACH PACKAGE  LAYOUT CAREFULLY<br>L<br>!<br>DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR  MARKED FEATURE<br>M<br>b e NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS 3        BALL DESIGNATION PER JESD MS-028 AND JEP95 4 5. PRIMARY DATUM -Z- IS SEATING PLANE 6 PIN “A1” BEVEL<br>F COMPONENT TRAY PIN 1<br>A NOTES BALL HT BALL DIMENSION PAD DIMENSION SUBSTRATE THK MOLD CAP HT<br> 5.01mm) A2<br>× DETAIL B<br> 16mm  PACKAGE SIDE VIEW MAX 5.21 0.70 4.51 0.90 0.66 0.46 4.05 0.15 0.10 0.20 0.30 0.15<br>× Y<br>BGA Package A1 SUBSTRATE H1 MXZ MZ DIMENSIONS NOM 5.01 0.60 4.41 0.75 0.63 16.00 16.00 1.27 13.97 13.97 0.41 4.00<br>ddd eee<br>TOTAL NUMBER OF BALLS: 144<br>b1 MIN 4.81 0.50 4.31 0.60 0.60 0.36 3.95<br>ccc  Z MOLD CAP H2 DETAIL B DETAIL A<br>144-Lead (16mm  (Reference LTC DWG # 05-08-1523 Rev A) A A1 A2 b b1 D E e F G H1 H2 aaa bbb ccc ddd eee<br>Øb (144 PLACES) SYMBOL<br>aaa  Z<br>0.0000<br>D X Y 6.9850 5.7150 4.4450 3.1750 1.9050 0.6350 0.6350 1.9050 3.1750 4.4450 5.7150 6.9850<br>E<br>TOP VIEW<br>PACKAGE TOP VIEW<br>SUGGESTED PCB LAYOUT<br>4<br>PIN “A1” CORNER<br>0.630 ±0.025 Ø 144x<br>Z<br>Z<br>Z//  bbb<br>6.9850<br>5.7150<br>4.4450<br>3.1750<br>1.9050<br>0.6350<br>0.0000<br>0.6350<br>1.9050<br>3.1750<br>4.4450<br>5.7150<br>6.9850<br>aaa  Z<br>**----- End of picture text -----**<br>


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- LTM4650 2 

## **REVISION HISTORY** 

|**REV**|**DATE**|**DESCRIPTION**|**PAGE NUMBER**|
|---|---|---|---|
|0|02/24|Initial Release.|—|



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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implicatiFor more informati **on** or otherwise under any patent or patent rights of Analog Devices.www.analog.com 

## - LTM4650 2 

## **PACKAGE PHOTOS** 

## **DESIGN RESOURCES** 

|**DESIGN RESOURCES**|||
|---|---|---|
|**SUBJECT**|**DESCRIPTION**||
|µModule Design and Manufacturing Resources|Design:<br>• Selector Guides<br>• Demo Boards and Gerber Files<br>• Free Simulation Tools|Manufacturing:<br>• Quick Start Guide<br>• PCB Design, Assembly and Manufacturing Guidelines<br>• Package and Board Level Reliability|
|µModule Regulator Products Search|1.  Sort table of products by parameters and download the result as a spread sheet.<br>2. Search using the Quick Power Search parametric table.<br>Quick Power Search<br>INPUT<br>|<br>Vin(Min)<br>Vv<br>Vin(Max)<br>Vv<br>OUTPUT |<br>Vout<br>Vv<br>lout<br>A<br>FEATURES |<br>Low EMI<br>Ultrathin<br>Internal Heat Sink<br>Multiple Outputs||
|Digital Power System Management|Analog Devices’ family of digital power supply management ICs are highly integrated solutions that<br>offer essential functions, including power supply monitoring, supervision, margining and sequencing,<br>and feature EEPROM for storing user configurations and fault logging.||



## **RELATED PARTS** 

|**PART NUMBER**|**DESCRIPTION**|**COMMENTS**|
|---|---|---|
|LTM4650-1|LTM4650-2 without AVP, External Compensation, ±0.8%<br>(LTM4650-1A)or ±1.5%(LTM4650-1B)VOUTAccuracy|Dual 25A or Single 50A, 4.5V ≤ VIN≤ 15V. 0.6V ≤ VOUT≤ 1.8V,<br>16mm × 16mm × 5.01mm BGA|
|LTM4650|Internal Compensation, ±1.5% VOUTAccuracy.|Dual 25A or Single 50A, 4.5V ≤ VIN≤ 15V. 0.6V ≤ VOUT≤ 1.8V,<br>16mm × 16mm × 5.01mm BGA|
|LTM4650A|Internal Compensation, High VOUTUp to 5.5V. ±1% VOUTAccuracy|Dual 25A or Single 50A, 4.5V ≤ VIN≤ 16V, 0.6V ≤ VOUT≤ 5.5V,<br>16mm × 16mm × 4.41mm LGA and 5.01mm BGA|
|LTM4630|Lower Current than LTM4650, Dual 18A or Single 36A|Pin Compatible with LTM4650. 4.5V ≤ VIN≤ 15V, 0.6V ≤ VOUT≤ 1.8V,<br>16mm × 16mm × 4.41mm LGA and 5.01mm BGA|
|LTM4630-1|Lower Current than LTM4650-1, External Compensation and<br>±0.8%(LTM4630-1A)or ±1.5%(LTM4630-1B)VOUTAccuracy|Pin Compatible with LTM4650-1, 4.5V ≤ VIN≤ 15V, 0.6V ≤ VOUT≤ 1.8V,<br>16mm × 16mm × 5.01mm BGA|
|LTM4630A|Lower Current and Higher VOUTthan LTM4650A, Up to 8VOUT,<br>Dual 18A or Single 36A|Pin Compatible with LTM4650A, 4.5V ≤ VIN≤ 18V, 0.6V ≤ VOUT≤ 8V,<br>16mm × 16mm × 4.41mm LGA and 5.01mm BGA|
|LTM4681|Quad 31.25A or Single 125A with PMBus Interface|4.5V ≤ VIN≤ 16V, 0.5V ≤ VOUT≤ 3.3V, 15mm × 22mm × 8.17mm BGA|
|LTM4683|0.3VOUT(Mini), Quad 31.25A or Single 125A with PMBus Interface|4.5V ≤ VIN≤ 14V, 0.3V ≤ VOUT≤ 0.7V, 15mm × 22mm × 5.71mm BGA|
|LTM4700|Dual 50A or Single 100A with PMBus Interface|4.5V ≤ VIN≤ 16V, 0.5V ≤ VOUT≤ 1.8V, 15mm × 22mm × 7.87mm BGA|
|LTM4680|Dual 30A or Single 60A with PMBus Interface|4.5V ≤ VIN≤ 16V, 0.5V ≤ VOUT≤ 3.3V, 16mm × 16mm × 7.82mm BGA|
|LTM4678|Dual 25A or Single 50A with PMBus Interface|4.5V ≤ VIN≤ 16V, 0.5V ≤ VOUT≤ 3.4V, 16mm × 16mm × 5.86mm BGA|



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