LTM4641MPY

LTM4641 

## **FeaTures** 

- n **Wide Operating Input Voltage Range: 4.5V to 38V** n **10A DC Typical, 12A Peak Output Current** 

- n **Output Range: 0.6V to 6V** 

- n **±1.5% Maximum Total Output DC Voltage Error** 

- n **Differential Remote Sense Amplifier for POL Regulation** n **Internal Temperature, Analog Indicator Output** 

- n **Overcurrent Foldback and Overtemperature Protection** 1) 

- n **Current Mode Control/Fast Transient Response** 

- n **Parallelable for Higher Output Current** 

- n Selectable Pulse-Skipping Operation 

- n Soft-Start/Voltage Tracking/Pre-Bias Start-Up 

- n 15mm × 15mm × 5.01mm BGA Package 

- n SnPb or RoHS Compliant Finish 

## **Input Protection** 

n UVLO, Overvoltage Shutdown and Latchoff Thresholds n N-Channel Overvoltage Power-Interrupt MOSFET Driver n Surge Stopper Capable with Few External Components 

## **Load Protection** 

n Robust, Resettable Latchoff Overvoltage Protection n N-Channel Overvoltage Crowbar Power MOSFET Driver 

## **applicaTions** 

n Ruggedized Electronics n Avionics and Industrial Equipment 

## 38V, 10A DC/DC µModule Regulator with Advanced Input and Load Protection **DescripTion** 

The LTM[®] 4641 is a switch mode step-down DC/DC µModule[®] (micromodule) regulator with advanced input and load protection features. Trip detection thresholds for the following faults are customizable: input undervoltage, overtemperature, input overvoltage and output overvoltage. Select fault conditions can be set for latchoff or hysteretic restart response—or disabled. Included in the package are the switching controller and housekeeping ICs, power MOSFETs, inductor, overvoltage drivers, biasing circuitry and supporting components. Operating from input voltages of 4V to 38V (4.5V start-up), the device supports output voltages from 0.6V to 6V, set by an external resistor network remote sensing the point-of-load’s voltage. 

The LTM4641’s high efficiency design can deliver up to 10A continuous current with a few input and output capacitors. The regulator’s constant on-time current mode control architecture enables high step-down ratios and fast response to transient line and load changes. The LTM4641 is offered in a 15mm × 15mm × 5.01mm with SnPb or RoHS compliant terminal finish. 

L, LT, LTC, LTM, µModule, Burst Mode, Linear Technology and the Linear logo are registered trademarks and LTpowerCAD is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5481178, 5847554, 6100678, 6304066, 6580258, 6677210, 8163643. 

**Click to view associated TechClip Videos.** 

## **Typical applicaTion** 

**µModule Regulator with Input Disconnect and Fast Crowbar Output Overvoltage Protection** 

**==> picture [513 x 167] intentionally omitted <==**

**----- Start of picture text -----**<br>
4 1V Load Protected from MTOP<br>4V TO 38VVIN ~ MSP* Short-Circuit at 38VIN<br>4.5V START-UP + 100µF 10µF50V 3<br>50V ×2 1 SHORT-CIRCUIT APPLIED<br>VING VINGP VINH MTOP SW VOUT 4<br>1V<br>V INL VOUT 2 100µF 10A VINL, VINH (25V/DIV) 3<br>750k CROWBAR MCB** ×3 CROWBAR (5V/DIV) 2<br>fSET MBOT 5.49k 1.1VOUT PEAK<br>UVLO VOSNS [+]<br>I NTVCC LTM4641 5.49k LOAD<br>DRVCC VOSNS [–] VOUT<br>(200mV/DIV)<br>R UN GND<br>TRACK/SS OVPGM 4641 TA01a 1<br>10nF IOVRETRY OVLO FCB LATCH SGND 5.6M 4µs/DIV 4641 TA01b<br>TESTED AT WORST-CASE CONDITION: NO LOAD<br>SGND CONNECTS TO GND INTERNAL TO µMODULE REGULATOR<br>*MSP: (OPTIONAL) SERIES-PASS OVERVOLTAGE POWER INTERRUPT MOSFET, NXP PSMN014-60LS<br>**----- End of picture text -----**<br>


- **MCB: (OPTIONAL) OUTPUT OVERVOLTAGE CROWBAR MOSFET, NXP PH2625L 

4641fe 

1 

For more information www.linear.com/LTM4641 

## LTM4641 

## **Table oF conTenTs** 

**Features ..................................................... 1 Applications ................................................ 1 Typical Application  ........................................ 1 Description.................................................. 1 Absolute Maximum Ratings .............................. 3 Order Information .......................................... 3 Pin Configuration .......................................... 3 Electrical Characteristics ................................. 4 Typical Performance Characteristics ................... 8 Pin Functions ..............................................10 Simplified Block Diagram ...............................15 Decoupling Requirements ...............................15 Operation...................................................16** Introduction ............................................................16 Motivation ...............................................................16 Power µModule Regulator Reliability ......................16 Overview .................................................................16 **Applications Information—Power Supply Features .17** Power (VINH) and Bias (VINL) Input Pins ................. 17 Switching Frequency (On Time) Selection and Voltage Dropout Criteria (Achievable VIN-to-VOUT Step-Down Ratios).................................................. 18 Setting the Output Voltage; the Differential Remote Sense Amplifier .........................................21 Input Capacitors .....................................................23 Output Capacitors and Loop Stability/Loop Compensation .........................23 Pulse-Skipping Mode vs Forced Continuous Mode  .......................................24 Soft-Start, Rail-Tracking and Start-Up Into Pre-Bias ..................................................................24 INTVCC and DRVCC ...............................................................27 1VREF .........................................................................................28 TEMP, OTBH and Overtemperature Protection ........28 Input Monitoring Pins: UVLO, IOVRETRY, OVLO ....29 **Applications Information—Input Protection Features ....................................................29** Start-Up/Shutdown and Run Enable; Power-On Reset and Timeout Delay Time ...............31 

**Applications Information—Load Protection Features ....................................................32** Overcurrent Foldback Protection ............................32 Power Good Indicator and Latching Output Overvoltage Protection ...........................................32 Power-Interrupt MOSFET (MSP), CROWBAR Pin and Output CROWBAR MOSFET (MCB) ..................33 Fast Output Overvoltage Comparator Threshold .....34 The Switching Node: SW Pin ..................................35 **Applications Information—EMI Performance ........35 Applications Information—Multimodule Parallel Operation ........................................36 Applications Information—Thermal Considerations and Output Current Derating ............................38** Thermal Considerations and Output Current Derating .........................................38 **Applications Information—Output Capacitance Table ........................................................45 Applications Information—Safety and Layout Guidance ...................................................46** Safety Considerations .............................................46 Layout Checklist/Example ......................................46 **Typical Applications ......................................48 Appendices ................................................56** Appendix A. Functional Block Diagram and Features Quick Reference Guide .............................56 Appendix B. Start-Up/Shutdown State Diagram .....57 Appendix C. Switching Frequency Considerations and Usage of RfSET .................................................58 Appendix D. Remote Sensing in Harsh Environments ...............................................59 Appendix E. Inspiration For Pulse-Skipping Mode Operation ......................................................60 Appendix F. Adjusting the Fast Output Overvoltage Comparator Threshold ............................................60 **Package Description .....................................63 Package Photo ............................................63 Package Description .....................................64 Revision History ..........................................65 Typical Application .......................................66 Related Parts ..............................................66** 

4641fe 

2 

For more information www.linear.com/LTM4641 

LTM4641 

## **absoluTe MaxiMuM raTings** 

## **pin conFiguraTion** 

## **(Note 1)** 

Terminal Voltages 

VINL, VINH, SW, fSET ............................... –0.3V to 40V VOUT...................................................... –0.3V to 9.2V VING ............................................ –0.3V to VINH + 20V INTVCC, DRVCC, RUN, TRACK/SS, PGOOD, CROWBAR, HYST .................................... –0.3V to 6V FCB, TMR................................-0.3V to INTVCC + 0.3V COMP ................................................... –0.3V to 2.7V VOSNS[+] , VORB[+] ...................................... –0.6V to 9.7V VOSNS[–] , VORB[–] ..........VOSNS[+] – 2.7V to VOSNS[+] + 0.3V OTBH, UVLO, IOVRETRY, OVLO, LATCH ....................................................–0.3V to 7.5V TEMP, OVPGM ....................................... –0.3V to 1.5V Terminal Currents INTVCC (Continuous)....................................... –30mA INTVCC (Continuous; CROWBAR Sourcing 15mA) ...............................................–15mA CROWBAR (Continuous) ..................................–15mA VINGP (Continuous) ........................... –50mA to 15mA 1VREF (Continuous) ................................–1mA to 1mA Internal Operating Temperature Range (Note 2) E- and I-Grades .................................. –40°C to 125°C MP-Grade .......................................... –55°C to 125°C Storage Temperature Range .................. –55°C to 125°C Peak Package Body Temperature (SMT Reflow) ... 245°C 

**==> picture [237 x 272] intentionally omitted <==**

**----- Start of picture text -----**<br>
TOP VIEW<br>SGND INTVCC VING VINGP<br>M<br>TRACK/SSPGOOD VINH<br>L<br>SGND FCB<br>K<br>COMP DRVCC GND<br>J<br>fSET SW<br>VINL H<br>VOSNS [+] GND<br>VOSNS [–] G<br>GND<br>F<br>E<br>VORB [+] OTBH TMR RUN<br>D VOUT<br>VORB [–] LATCH<br>C<br>SGND 1VREF<br>B<br>GND<br>A<br>1 2 3 4 5 6 7 8 9 10 11 12<br>UVLO TEMP IOVRETRY CROWBAR OVPGM<br>HYST OVLO<br>BGA PACKAGE<br>144-LEAD (15mm × 15mm × 5.01mm)<br>TJMAX = 125°C, θJCtop = 11°C/W, θJCbottom = 2.5°C/W<br>θJB = 3°C/W, θJA = 10.4°C/W<br>θ VALUES DETERMINED PER JESD51-12<br>WEIGHT = 2.9 GRAMS<br>**----- End of picture text -----**<br>


## **orDer inForMaTion** 

|**PART NUMBER**|**PAD OR BALL FINISH**|**PART MARKING***|**PART MARKING***|**PACKAGE**<br>**TYPE**|**MSL**<br>**RATING**|**TEMPERATURE RANGE**<br>**(Note 2)**|
|---|---|---|---|---|---|---|
|||**DEVICE**|**FINISH CODE**||||
|LTM4641EY#PBF|SAC305(RoHS)|LTM4641Y|e1|BGA|4|–40°C to 125°C|
|LTM4641IY#PBF|SAC305(RoHS)|LTM4641Y|e1|BGA|4|–40°C to 125°C|
|LTM4641IY|SnPb(63/37)|LTM4641Y|e0|BGA|4|–40°C to 125°C|
|LTM4641MPY#PBF|SAC305(RoHS)|LTM4641Y|e1|BGA|4|–55°C to 125°C|
|LTM4641MPY|SnPb(63/37)|LTM4641Y|e0|BGA|4|–55°C to 125°C|



Consult Marketing for parts specified with wider operating temperature ranges. *Device temperature grade is indicated by a label on the shipping container. Pad or ball finish code is per IPC/JEDEC J-STD-609. 

- Pb-free and Non-Pb-free Part Markings: www.linear.com/leadfree 

- Recommended LGA and BGA PCB Assembly and Manufacturing Procedures: www.linear.com/umodule/pcbassembly 

- LGA and BGA Package and Tray Drawings: www.linear.com/packaging 

4641fe 

3 

For more information www.linear.com/LTM4641 

## LTM4641 

**elecTrical characTerisTics The** l **denotes the specifications which apply over the full internal operating temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = VINH = VINL = 28V, per the typical application shown in Figure 45, unless otherwise noted.** 

|<br>**shown in Figure 45,**|<br>**unless otherwise noted.**|||||
|---|---|---|---|---|---|
|**SYMBOL**|**PARAMETER**|**CONDITIONS**||**MIN**<br>**TYP**<br>**MAX**|**UNITS**|
|VIN|Input DC Voltage||l|4.5<br>38|V|
|VOUT|Output Voltage Range|Use RSET1A= RSET1B≤ 8.2kΩ. RfSETValues<br>Recommended in Table 1|l|0.6<br>6|V|
|VOUT(DC)|Output Voltage, Total Variation with<br>Line and Load, and Prior to UVLO|4.5V ≤ VIN≤ 38V, 0A ≤ IOUT≤ 10A<br>VIN= 4V(Ramped Down from 4.5V), IOUT= 0A|l<br>l|1.773<br>1.773<br>1.800<br>1.800<br>1.827<br>1.827|V<br>V|
|**Input Specifications**||||||
|VRUN(ON,OFF)|RUN On/Off Threshold|Run Rising, Turn On<br>Run Falling, Turn Off|l<br>l|0.8<br>1.25<br>1.15<br>2|V<br>V|
|IRUN(ON)|RUN Pull-Up Current|VRUN= 0V<br>VRUN= 3.3V|l<br>l|–580<br>–220<br>–520<br>–165<br>–460<br>–110|µA<br>µA|
|IRUN(OFF)|RUN Pull-Down Current, Switching<br>Inhibited|VRUN= 3.3V, UVLO = 0V (MHYSTOn)||1|nA|
|VINL(UVLO)|VINLUndervoltage Lockout|VINLRising<br>VINLFalling<br>Hysteresis|l<br>l<br>l|3.5<br>300<br>4.2<br>3.8<br>400<br>4.5<br>4|V<br>V<br>mV|
|IINRUSH(VINH)|Input Inrush Current Through VINH,<br>at Start-Up|CSS= Open||230|mA|
|IQ(VINH)|Power Stage Bias Current (IVINH) at<br>No Load|IOUT= 0A and:<br>FCB ≥ 0.84V (Pulse-Skipping Mode)<br>FCB ≤ 0.76V (Forced Continuous Mode)<br>Shutdown, RUN = 0||8<br>29<br>0.2|mA<br>mA<br>mA|
|IQ(VINL)|Control Bias Current (IVINL)|INTVCCConnected to DRVCCand:<br>VIN= 28V, IOUT= 0A<br>VIN= 28V, IOUT= 10A<br>VIN= 28V, Shutdown, RUN = 0||14.5<br>15.5<br>5|mA<br>mA<br>mA|
|IS(VINH)|Power Stage Input Current (IVINH) at<br>Full Load|IOUT= 10A and:<br>VIN= 4.5V<br>VIN= 28V<br>VIN= 38V||4.65<br>790<br>590|A<br>mA<br>mA|
|**Output Specifications**||||||
|IOUT(DC)|Output Continuous Current Range|(Note 3)|l|0<br>10|A|
|∆VOUT(LINE)/VOUT|Line Regulation Accuracy|VINfrom 4.5V to 38V, IOUT= 0A|l|0.02<br>0.15|%|
|∆VOUT(LOAD)/VOUT|Load Regulation Accuracy|IOUTfrom 0A to 10A(Note 3)|l|0.04<br>0.15|%|
|VOUT(AC)|Output Voltage Ripple Amplitude|IOUT= 0A||16|mVP-P|
|fS|Output Voltage Ripple Frequency|IOUT= 0A<br>IOUT= 10A||290<br>330|kHz<br>kHz|
|VOUT(START)|Turn-On Overshoot|IOUT= 0A||10|mV|
|tSTART|VIN-to-VOUTStart-Up Time|RUN Electrically Open Circuit, Time Between<br>Application of VINto VOUTBecoming Regulated,<br>OVPGM= 1.5V, CTMR= CSS= Open||3|ms|
|tRUN(ON-DELAY)|RUN-to-VOUTTurn-On Response<br>Time|VINEstablished, (TMR-Set POR Time Expired)<br>Time Between RUN Releasing from GND to<br>PGOOD Going Logic High, CSS= Open,<br>OVPGM= 1.5V||175<br>400|μs|
|∆VOUT(LS)|Peak Deviation for Dynamic Load<br>Step|IOUTfrom 0A to 5A at 5A/µs<br>IOUTfrom 5A to 0A at 5A/µs||40<br>40|mV<br>mV|
|tSETTLE(LS)|Settling Time for Dynamic Load Step|IOUTfrom 0A to 5A at 5A/µs<br>IOUTfrom 5A to 0A at 5A/µs||20<br>20|μs<br>µs|



4641fe 

4 

For more information www.linear.com/LTM4641 

LTM4641 

**elecTrical characTerisTics The** l **denotes the specifications which apply over the full internal operating temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = VINH = VINL = 28V, per the typical application shown in Figure 45, unless otherwise noted.** 

|<br>**shown in Figure 45,**|<br>**unless otherwise noted.**|||||
|---|---|---|---|---|---|
|**SYMBOL**|**PARAMETER**|**CONDITIONS**||**MIN**<br>**TYP**<br>**MAX**|**UNITS**|
|IOUT(PK)|Output Current Limit|5.1kΩ Pull-Up from PGOOD to 5V Source, IOUT<br>Ramped Up Until VOUTBelow PGOOD Lower<br>Threshold, PGOOD Pulls Logic Low||24|A|
|IVINH(IOUT_SHORT)|Power Stage Input Current During<br>Output Short Circuit|VOUTElectrically Shorted to GND||45|mA|
|**Control Section**||||||
|VFB|Differential Feedback Voltage from<br>VOSNS+to VOSNS–|IOUT= 0A|l|591<br>600<br>609|mV|
|ITRACK/SS|TRACK/SS Pull-Up Current|VTRACK/SS= 0V||–0.45<br>–1|μA|
|VFCB|FCB Threshold|||0.76<br>0.8<br>0.84|V|
|IFCB|FCB Pin Current|VFCB= 0.8V||0<br>±1|μA|
|tON(MIN)|Minimum On-Time|(Note 4)||43<br>75|ns|
|tOFF(MIN)|Minimum Off-Time|(Note 4)||220<br>300|ns|
|VOSNS(DM)|Remote Sense Pin-Pair Differential<br>Mode Input Range|Valid Differential VOSNS+-to- VOSNS–Range<br>(Use RSET1A= RSET1B≤ 8.2k)|l|0<br>2.7|V|
|VOSNS(CM)|Remote Sense Pin-Pair Common<br>Mode Input Range|Valid VOSNS–Common Mode Range<br>Valid VOSNS+Common Mode Range<br>(Use RSET1A= RSET1B≤ 8.2k)|l<br>l|–0.3<br>3|V<br>V|
|RIN(VOSNS+)|Input Resistance|VOSNS+to GND||16318<br>16400<br>16482|Ω|
|**INTVCC, DRVCC, 1VREF**||||||
|VINTVCC|Internal VCCVoltage|6V ≤ VIN≤ 38V, INTVCCNot Connected to DRVCC,<br>DRVCC= 5.3V|l|5.1<br>5.3<br>5.4|V|
|∆VINTVCC(LOAD)<br> VINTVCC|INTVCCLoad Regulation|RUN = 0V, INTVCCNot Connected to DRVCC,<br>DRVCC= 5.3V and:<br>IINTVCCVaried from 0mA to –20mA<br>IINTVCCVaried from 0mA to –30mA||–0.7<br>–1<br>±2<br>±3|%<br>%|
|VINTVCC(LOWLINE)|INTVCCVoltage at Low Line|VIN= 4.5V, RSET1A= RSET1B= 0Ω (~0.6VOUT,<br>RfSETValue Recommended in Table 1)|l|4.2<br>4.3|V|
|DRVCC(UVLO)|DRVCCUndervoltage Lockout|DRVCCRising<br>DRVCCFalling|l<br>l|3.9<br>3.2<br>4.05<br>3.35<br>4.2<br>3.5|V<br>V|
|IDRVCC|DRVCCCurrent|INTVCCNot Connected to DRVCC, DRVCC= 5.3V,<br>RSET1A, RSET1Band RSET2Setting VOUTto:<br>1.8VOUT, RfSET= 2MΩ, 0A ≤ IOUT≤ 10A<br>6.0VOUT, RfSET= Open, 0A ≤ IOUT≤ 10A<br>(Use RSET1A= RSET1B≤ 8.2k)||11<br>20<br>18<br>27|mA<br>mA|
|V1VREF(DC)|1VREFDC Voltage Regulation|I1VREF= 0mA<br>I1VREF= ±1mA|l<br>l|0.985<br>0.980<br>1.000<br>1.000<br>1.015<br>1.020|V<br>V|
|**PGOOD Output**||||||
|VPGOOD(TH)|Power Good Window, Logic State<br>Transition Thresholds|Ramping Differential VOSNS+– VOSNS–Voltage:<br>Up, PGOOD Goes Logic Low→High<br>Up, PGOOD Goes Logic High→Low<br>Down, PGOOD Goes Logic Low→High<br>Down, PGOOD Goes Logic High→Low||533<br>645<br>621<br>525<br>556<br>660<br>644<br>540<br>579<br>675<br>667<br>555|mV<br>mV<br>mV<br>mV|
|VPGOOD(HYST)|Hysteresis|Differential VOSNS+– VOSNS–Voltage Returning||8<br>16<br>24|mV|
|VPGOOD(VOL)|Logic-Low Output Voltage|IPGOOD= 5mA|l|75<br>400|mV|
|tPGOOD(DELAY)|PGOOD Logic-Low Blanking Time|Delay Between Differential VOSNS+– VOSNS–<br>Voltage Exiting PGOOD Valid Window to PGOOD<br>Going Logic Low(Note 4)||12|μs|



4641fe 

5 

For more information www.linear.com/LTM4641 

## LTM4641 

## **elecTrical characTerisTics** 

**The** l **denotes the specifications which apply over the full internal operating temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = VINH = VINL = 28V, per the typical application shown in Figure 45, unless otherwise noted.** 

|**SYMBOL**|**PARAMETER**|**CONDITIONS**|**CONDITIONS**|**MIN**<br>**TYP**<br>**MAX**|**UNITS**|
|---|---|---|---|---|---|
|**Power-Interrupt MOSFET Drive**||||||
|VVING|Gate Drive Voltage for Power-<br>Interrupt MOSFET, MSP|VIN= 4.5V, 0A ≤ IOUT≤ 10A, VINGSourcing 1µA<br>VIN= 28V, 0A ≤ IOUT≤ 10A, VINGSourcing 1µA<br>VIN= 38V, 0A ≤ IOUT≤ 10A, VINGSourcing 1µA<br>VIN= 4V (Ramped Down from 4.5V), IOUT= 0A,<br>VINGSourcing 1µA|l<br>l<br>l<br>l|11.5<br>35<br>45<br>10.5<br>13.3<br>38.4<br>48.4<br>11.5<br>15.5<br>41<br>51.5<br>14.2|V<br>V<br>V<br>V|
|IVING(UP)|VINGPull-Up Current|VINGTied to VINGP, and:<br>VIN= 4.5V, VINGPulled to 6.5V<br>VIN= 28V, VINGPulled to 30V|l<br>l|350<br>425<br>475<br>550<br>600<br>675|µA<br>µA|
|IVING_DOWN(CROWBAR<br>ACTIVE,CROWBAR<br>INACTIVE)|VINGPull-Down Current|VINGTied to VINGP, Pulled to 33V, and:<br>RUN Pulled to 0V (CROWBAR Inactive)<br>OVPGMPulled to 0V(CROWBAR Active)|l<br>l|3<br>24<br>20<br>27<br>30<br>30|mA<br>mA|
|tVING(OVP_DELAY)|VINGOVP Pull-Down Delay|OVPGMDriven from 650mV to 550mV, VING<br>Discharge Response Time|l|1.3<br>2.6|µs|
|IVINGP(LEAK)|Zener Diode Leakage Current|VINGPDriven to(VINH+ 10V)||1|nA|
|VINGP(CLAMP)|Zener Diode Breakdown Voltage|VINGP-to-VINHDifferential Voltage; IVINGP= 5mA||15|V|
|**Fault Pins and Functions**||||||
|VOVPGM|Default Output Overvoltage Program<br>Setting|OVPGMElectrically Open Circuit|l|650<br>666<br>680|mV|
|IOVPGM(UP)|OVPGMPull-Up Current|OVPGM= 0V|l|–2.07<br>–2<br>–1.91|μA|
|IOVPGM(DOWN)|OVPGMPull-Down Current|OVPGM= 1V|l|0.945<br>1<br>1.06|μA|
|OVPTH|Output Overvoltage Protection<br>Inception Threshold|Ramping Up Differential VOSNS+-to-VOSNS–<br>Voltage Until CROWBAR Outputs Logic High|l|647<br>666<br>683|mV|
|OVPERR|Output Overvoltage Protection<br>Inception Error|Difference Between OVPTHand VOVPGM<br>(OVPTH-VOVPGM)|l|–12<br>0<br>12|mV|
|tCROWBAR(OVP_DELAY)|CROWBAR Response Time|OVPGMDriven from 650mV to 550mV|l|400<br>500|ns|
|VCROWBAR(OH)|CROWBAR Output, Active High<br>Voltage|OVPGMPulled to 0V and:<br>ICROWBAR= –100μA, IINTVCC= –20mA<br>ICROWBAR= –4mA, IINTVCC= –20mA|l<br>l|4.3<br>4.2<br>4.65<br>4.55<br>5<br>4.9|V<br>V|
|VCROWBAR(OL)|CROWBAR Output, Passive Low<br>Voltage|ICROWBAR= 1μA|l|260<br>500|mV|
|VCROWBAR(OVERSHOOT)|CROWBAR Peak Voltage Overshoot<br>at VINLStart-Up and Shutdown|VINLRamped Up from/Down to 0V|l|550<br>900|mV|
|VCROWBAR(TH)|CROWBAR Latchoff Threshold|CROWBAR Ramped Up Until HYST Goes Logic<br>Low|l|1.4<br>1.5<br>1.6|V|
|VTEMP|TEMP Voltage|RUN = 0V, TA= 25°C<br>RUN = 0V, TA= 125°C<br>(See Figure 10 for Reference)||950<br>980<br>585<br>1010|mV<br>mV|
|OTTH(INCEPTION)|TEMP Overtemperature Inception<br>Threshold|Ramping TEMP Downward Until HYST Outputs<br>Logic Low|l|428<br>438<br>448|mV|
|OTTH(RECOVER)|TEMP Overtemperature Recovery<br>Threshold|Ramping TEMP Upward Until HYST Outputs<br>Logic High|l|501<br>514<br>527|mV|
|UVOVTH|UVLO/OVLO/IOVRETRY<br>Undervoltage/Overvoltage Inception<br>Thresholds|Ramping UVLO, OVLO or IOVRETRY Positive<br>Until HYST Toggles Its State|l|488<br>500<br>512|mV|



4641fe 

6 

For more information www.linear.com/LTM4641 

LTM4641 

## **elecTrical characTerisTics** 

**The** l **denotes the specifications which apply over the full internal operating temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = VINH = VINL = 28V, per the typical application shown in Figure 45, unless otherwise noted.** 

|**SYMBOL**|**PARAMETER**|**CONDITIONS**|**CONDITIONS**|**MIN**<br>**TYP**<br>**MAX**|**UNITS**|
|---|---|---|---|---|---|
|tUVOVD|UVLO/OVLO/IOVRETRY/ TEMP<br>Response Time|±50mV Overdrive (All Pins)<br>±5mV Overdrive, UVLO/OVLO/IOVRETRY Pins<br>Only(Note 4)|l|50<br>25<br>125<br>100<br>500|µs<br>µs|
|IUVOV|Input Current of UVLO, OVLO and<br>IOVRETRY|UVLO = 0.55V or OVLO = 0.45V or<br>IOVRETRY = 0.45V|l|±30|nA|
|VHOUSEKEEPING(UVLO)|Housekeeping Circuitry UVLO|Voltage on INTVCC, INTVCCRising (Note 4)<br>Hysteresis, INTVCCReturning(Note 4)||1.9<br>5<br>2<br>25<br>2.1<br>50|V<br>mV|
|VHYST(SWITCHING ON)|HYST Voltage (MHYSTOff, RUN<br>Logic High)|RUN Electrically Open Circuit<br>RUN = 1.8V|l<br>l|4.9<br>1.85<br>5.1<br>2.1<br>5.25<br>2.35|V<br>V|
|VHYST(SWITCHING OFF,<br>RUN)|HYST Voltage  (MHYSTOff, RUN<br>Logic Low)|RUN = 0V|l|170<br>350<br>480|mV|
|VHYST(SWITCHING OFF,<br>FAULT)|HYST Voltage, Switching Action<br>Inhibited (MHYSTOn)|UVLO < UVOVTHor OVLO > UVOVTHor<br>IOVRETRY > UVOVTHor TEMP < OTTH(INCEPTION)<br>or CROWBAR > VCROWBAR(TH)or<br>DRVCC< DRVCCUVLO(FALLING)<br>(See Figures 62, 63)|l|30<br>65|mV|
|TMRUOTO|Timeout and Power-On Reset Period|CTMR= 1nF, Time from Fault Clearing to HYST<br>Being Released by Internal Circuitry|l|5<br>9<br>14|ms|
|VLATCH(IH)|LATCHClear Threshold Input High||l|1.2|V|
|VLATCH(IL)|LATCHClear Threshold Input Low||l|0.8|V|
|ILATCH|LATCHInput Current|VLATCH= 7.5V|l|±1|μA|
|ITMR(UP)|TMR Pull-Up Current|VTMR= 0V|l|–1.2<br>–2.1<br>–2.8|μA|
|ITMR(DOWN)|TMR Pull-Down Current|VTMR= 1.6V|l|1.2<br>2.1<br>2.8|μA|
|VTMR(DIS)|Timer Disable Voltage|Referenced to INTVCC|l|–180<br>–270|mV|
|OTBHVIL|OTBH Low Level Input Voltage||l|0.4|V|
|OTBHVZ|OTBH Pin Voltage When Left<br>Electrically Open Circuit|–10μA ≤ IOTBH≤ 10μA|l|0.6<br>0.9<br>1.2|V|
|IOTBH(MAX)|Maximum OTBH Current|OTBH Electrically Shorted to SGND|l|30|μA|



**Note 1:** Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. 

The LTM4641 SW absolute maximum rating of 40V is verified in ATE by regulating VOUT while at 40VIN, in a controlled manner guaranteed to not affect device reliability or lifetime. Static testing  of SW leakage current at 40VIN is performed at control IC wafer level only. 

**Note 2:** The LTM4641 is tested under pulsed load conditions such that TJ ≈ TA. The LTM4641E is guaranteed to meet performance specifications from 0°C to 125°C junction temperature. Specifications over the 

–40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTM4641I is guaranteed over the –40°C to 125°C operating junction temperature range. The LTM4641MP is tested and guaranteed over the full –55°C to 125°C operating temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. 

**Note 3:** See output current derating curves for different VIN, VOUT and TA. **Note 4:** 100% tested at wafer level only. 

4641fe 

7 

For more information www.linear.com/LTM4641 

## LTM4641 

## **Typical perForMance characTerisTics** 

**(Figure 45 circuit with RfSET per Table 1 and RSET1A, RSET1B and RSET2 per Table 2, unless otherwise noted)** 

**==> picture [518 x 392] intentionally omitted <==**

**----- Start of picture text -----**<br>
Efficiency vs Load Current at 36VIN Efficiency vs Load Current at 24VIN Efficiency vs Load Current at 12VIN<br>95 95 95<br>90 90 90<br>LL TEE PET EEE | | ee<br>85 85 85<br>80 errr 80 SnpZeeeooe 80 [SEEPS<br>75 Wee) 75 ees 75 pes<br>70 |fAe tt - 6.0VOUT 1.5VOUT 70 fi fer 6.0V T OUT Y 1.5VOUT 70 H EE 6.0VOUT 1.5VOUT<br>5.0VOUT 1.2VOUT 5.0VOUT 1.2VOUT 5.0VOUT 1.2VOUT<br>65 WA S 3.3V2.5VOUTOUT = 1.0V0.9VOUTOUT 65 - 3.3V2.5VOUTOUT 1.0V0.9VOUTOUT 65 ian 3.3V2.5VOUTOUT 1.0V0.9VOUTOUT<br>60 ee| 1.8VOUT 60 EL 1.8VOUT 60 ian 1.8VOUT<br>0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10<br>OUTPUT CURRENT (A) OUTPUT CURRENT (A) OUTPUT CURRENT (A)<br>4641 G01 4641 G02 4641 G03<br>Pulse-Skipping vs Forced<br>Continuous Mode Efficiency,<br>Efficiency vs Load Current at 6VIN 28VIN to 3.3VOUT 1V Transient Response, 38VIN<br>95 90<br>90 fern ean 80 P| VOUT a ao<br>50mV/DIV<br>85 S45==2 sae 70 PF FCB = INTV | CC UL AIF AC-COUPLED | Nawevvennon<br>60 (PULSE-SKIPPING)<br>80 50 IOUT<br>2.5A/DIV<br>75 40<br>FCB = SGND<br>70 POs) 30 ee FORCED CONTINUOUS 20µs/DIV 4641 G06<br>3.3VOUT 1.2VOUT 20 0A TO 5A LOAD STEPS AT 5A/µs<br>65 HieR RR 2.5V1.8VOUTOUT 1.0V0.9VOUTOUT 10 ey oy 7 FRONT PAGE CIRCUIT WITH OVPGM = OPEN CIRCUIT |<br>1.5VOUT<br>60 HLL HEE 0 a  a4<br>0 1 2 3 4 5 6 7 8 9 10 0.001 0.01 0.1 1 10<br>OUTPUT CURRENT (A) OUTPUT CURRENT (A)<br>4641 G04 4641 G05<br>EFFICIENCY (%) EFFICIENCY (%) EFFICIENCY (%)<br>EFFICIENCY (%) EFFICIENCY (%)<br>**----- End of picture text -----**<br>


**==> picture [525 x 147] intentionally omitted <==**

**----- Start of picture text -----**<br>
3.3V Transient Response,<br>1V Transient Response, 4.5VIN 28VIN to 3.3VOUT Output Start-Up, No Load<br>VOUT VOUT 1V/DIVVOUT<br>50mV/DIV 50mV/DIV<br>AC-COUPLED AC-COUPLED<br>IIN<br>IOUT IOUT 200mA/DIV<br>2.5A/DIV 2.5A/DIV<br>RUN<br>5V/DIV<br>aac 20µs/DIV 4641 G07 om 20µs/DIV 4641 G08 ——— 800µs/DIV 4641 G09<br>0A TO 5A LOAD STEPS AT 5A/µs 0A TO 5A LOAD STEPS AT 5A/µs VIN = 24V<br>FRONT PAGE CIRCUIT WITH  FIGURE 46 CIRCUIT CIN(MLCC) = 2 × 10µF X7R<br>OVPGM = OPEN CIRCUIT<br>**----- End of picture text -----**<br>


4641fe 

8 

For more information www.linear.com/LTM4641 

LTM4641 

## **Typical perForMance characTerisTics** 

**(Figure 45 circuit with RfSET per Table 1 and RSET1A, RSET1B and RSET2 per Table 2, unless otherwise noted)** 

**Output Start-Up, Pre-Bias Condition** 

**==> picture [336 x 130] intentionally omitted <==**

**----- Start of picture text -----**<br>
Output Start-Up, 10A Load Pre-Bias Condition<br>VOUT 1V/DIVVOUT<br>1V/DIV<br>IIN ILOAD<br>1A/DIV 1mA/DIVIIN<br>200mA/DIV<br>RUN RUN<br>5V/DIV 5V/DIV<br>—— 800µs/DIV 4641 G10 800µs/DIV 4641 G11<br>VIN = 24V VIN = 24V<br>CIN(MLCC) = 2 × 10µF X7R CIN(MLCC) = 2 × 10µF X7R<br>**----- End of picture text -----**<br>


**==> picture [155 x 141] intentionally omitted <==**

**----- Start of picture text -----**<br>
Output Short-Circuit,<br>No Initial Load<br>VOUT<br>1V/DIV<br>IIN<br>1A/DIV<br>pots 20µs/DIV 4641 G12<br>VIN = 24V<br>CIN(MLCC) = 2 × 10µF X7R<br>**----- End of picture text -----**<br>


**Start-Up with VINH Shorted to SW Node, 1VOUT(NOM)** 

## **Output Short-Circuit, 10A Initial Load** 

**==> picture [335 x 126] intentionally omitted <==**

**----- Start of picture text -----**<br>
VIN<br>20V/DIV<br>VOUT VINH<br>1V/DIV 2V/DIV<br>VOUT<br>200mV/DIV<br>IIN<br>1A/DIV<br>CROWBAR<br>5V/DIV<br>20µs/DIV 4641 G13 400µs/DIV 4641 G14<br>VIN = 24V FRONT PAGE CIRCUIT WITH VINH SHORT<br>CIN(MLCC) = 2 × 10µF X7R CIRCUITED TO SW PRIOR TO POWER-UP.<br>APPLYING UP TO 38VIN. NO LOAD<br>**----- End of picture text -----**<br>


**Start-Up with VINH Shorted to SW Node, 3.3VOUT(NOM)** 

**==> picture [166 x 112] intentionally omitted <==**

**----- Start of picture text -----**<br>
VIN<br>10V/DIV<br>VINH<br>5V/DIV<br>VOUT<br>1V/DIV<br>CROWBAR<br>5V/DIV<br>800µs/DIV 4641 G15<br>FIGURE 46 CIRCUIT WITH VINH SHORT<br>CIRCUITED TO SW PRIOR TO POWER-UP.<br>APPLYING UP TO 38VIN. NO LOAD<br>**----- End of picture text -----**<br>


**Paralleled Modules, CurrentSharing Performance. cf. Figure 66 Circuit. 28VIN** 

**Autonomous Restart with VINH Shorted to SW Node, 3.3VOUT(NOM)** 

**Control IC Bandgap and 1VREF Voltages vs Temperature. 28VIN** 

**==> picture [523 x 170] intentionally omitted <==**

**----- Start of picture text -----**<br>
VIN 12 0.606 1.006<br>10V/DIV<br>10V/DIVVINH 10 0.604 1.004<br>8<br>0.602 1.002<br>VOUT U1 IOUT VFB<br>1V/DIV 6<br>CROWBAR Ty, 4 AAO U2 IOUT 0.600 V1VREF(DC) 1.000<br>5V/DIV<br>100ms/DIV = 4641 G16 |4 0.598 ONS 0.998<br>2<br>FIGURE 46 CIRCUIT, SHORT CIRCUITING VINH<br>we NO LOAD. TO SW IN SITU, OPERATING AT 38VLATCH CONNECTED TO INTVIN ANDCC AND 0 AA 0.596 ett 0.996<br>CTMR = 47nF<br>–2 ee ee 0.594 0.994<br>0 4 8 12 16 20 –75 –50 –25 0 25 50 75 100 125 150<br>TOTAL OUTPUT CURRENT (A) JUNCTION TEMPERATURE (°C)<br>4641 G17 4641 G18<br>1V<br>REF<br> BANDGAP VOLTAGE (V)  VOLTAGE (V)<br>FB<br>V<br>MODULE OUTPUT CURRENT (A)<br>**----- End of picture text -----**<br>


4641fe 

9 

For more information www.linear.com/LTM4641 

LTM4641 

## **pin FuncTions** 

**SGND (A1-A3; B1-B3; C1-C4; K1, K3; L3; M1-M3):** Signal Ground Pins. This is the return ground path for all analog control and low power circuitry. SGND is tied to GND internal to the µModule regulator in a manner that promotes the best internal signal integrity—therefore, SGND should not be connected to GND in the user’s PCB layout. See the Layout Checklist/Example section of the Applications Information section for more information pertaining to SGND and layout. All SGND pins are electrically connected to each other, internally. 

**HYST (A4):** Input Undervoltage Hysteresis Programming Pin. Normally used as an output, but can be used as an input. If the LTM4641’s inherent, default undervoltage lockout (UVLO) settings are satisfactory, 4.5VIN(RISING, MAX)[ and 4V] IN(FALLING, MAX)[, HYST can be left electrically ] open circuit. See the Applications Information section to customize the LTM4641’s UVLO thresholds. 

HYST is a logic-high output with moderate pull-up strength that commands LTM4641’s internal control IC to regulate the module’s output voltage when conditions on the RUN, UVLO, OVLO, IOVRETRY, TEMP, CROWBAR, INTVCC and DRVCC pins permit it (any recent latchoff events notwithstanding, otherwise OTBH and LATCH can also play a role). When a fault condition is detected, internal circuitry (MHYST; see Figure 1) drives HYST logic low and the LTM4641’s output is turned off. HYST can be used as a fault-indicator. See the Applications Information section. 

HYST is pulled low when the RUN pin is pulled low, via an internal Schottky diode. HYST can be driven low by external open-collector/open-drain circuitry directly—as an alternate to the RUN pin interface. However, external circuitry should never drive HYST high, since doing so (indiscriminately) could cause thermal overstress to MHYST, when MHYST is on. 

**TEMP (A5):** Power Stage Temperature Indicator and Overtemperature Detection Pin. When left electrically open circuit, TEMP’s voltage varies according to an internal NTC (negative temperature coefficient) thermistor, residing in close proximity to LTM4641’s power stage. When TEMP falls below 438mV (corresponding to a thermistor and power stage temperature of ~145°C), the LTM4641 pulls HYST low to inhibit regulation of its output voltage. HYST 

may be deasserted when TEMP subsequently exceeds 514mV (nominally corresponding to a cool-off hysteresis of ~10°C), depending on the OTBH setting. (See OTBH and the Applications Information section.) 

To disable the µModule regulator’s overtemperature shutdown feature, connect the TEMP and 1VREF pins. The thermal shutdown inception threshold can also be modified, see the Applications Information section. 

**IOVRETRY (A6):** Nonlatching Input Overvoltage Threshold Programming Pin. The LTM4641 pulls HYST low to inhibit regulation of its output voltage when IOVRETRY exceeds 0.5V. The LTM4641 can resume switching action when IOVRETRY is below 0.5V. If no nonlatching input overvoltage shutdown behavior is desired, connect this pin to SGND. Do not leave this pin open circuit. 

**GND (A7-A12; B6-B8, B11-B12; C7-C8; D6-D8; E1-E8; F1-F12; G1-G12; H3-H9, H11-H12; J5-J12; K5-K6, K11K12; L4-L6; M4-M6):** Power ground pins for input and output returns. See the Layout Checklist/Example section of the Applications Information section. All GND pins are electrically connected to each other, internally. 

**UVLO (B4):** Input Undervoltage Lockout Programming Pin. The LTM4641 pulls HYST low to inhibit regulation of its output voltage whenever UVLO is less than 0.5V. The LTM4641 can resume switching action when UVLO exceeds 0.5V. Do not leave this pin open circuit. 

If the LTM4641’s default UVLO settings are used, 4.5VIN(RISING, MAX) and 4VIN(FALLING, MAX), then the UVLO pin should be electrically connected to 1VREF or INTVCC. Otherwise, see HYST and the Applications Information section for using a resistor-divider network to implement personalized UVLO rising and UVLO falling settings. 

**OVLO (B5):** Input Overvoltage Latchoff Programming Pin. LTM4641 pulls HYST low to inhibit regulation of its output voltage when OVLO exceeds 0.5V. If OVLO subsequently falls below 0.5V, the module’s output remains latched off; the LTM4641 cannot resume regulation of the output voltage until either the LATCH pin is toggled high or VINL is power cycled. If input overvoltage latchoff behavior is not desired, electrically short this pin to SGND. Do not leave this pin open circuit. 

4641fe 

10 

For more information www.linear.com/LTM4641 

LTM4641 

## **pin FuncTions** 

**CROWBAR (B9):** Crowbar Output Pin. Normally logic low, with moderate pull-down strength to SGND. 

When an output overvoltage (OOV) condition is detected, the LTM4641’s fast OOV comparator pulls CROWBAR logic high through a series-connected internal diode. If utilizing LTM4641’s OOV feature, CROWBAR should connect to the gate of a logic-level N-channel MOSFET configured to crowbar the module’s output voltage (MCB, in Figure 1). 

Furthermore, the LTM4641 latches off its output when CROWBAR nominally exceeds 1.5V and latches HYST logic low (see HYST). 

If not using the OOV protection features of the LTM4641, leave CROWBAR electrically open circuit. 

**OVPGM (B10):** Output Overvoltage Threshold Programming Pin. The voltage on this pin sets the trip threshold for the inverting input pin of LTM4641’s fast OOV comparator. When left electrically open circuit, resistors internal to the LTM4641 nominally bias OVPGM to 666mV (OVPTH)—11% above the nominal VFB feedback voltage (600mV) that the control loop strives to present to the noninverting input pin of LTM4641’s fast OOV comparator. The aforementioned voltages correspond proportionally to the module’s OOV inception threshold and VOUT’s nominal voltage of regulation, respectively. Altering the OVPGM voltage provides a means to adjust the OOV threshold; its DC-bias setpoint can be tightened with simple connections to external components (see the Applications Information section). Trace route lengths and widths to this sensitive analog node should be minimized. Minimize stray capacitance to this node unless altering the OOV threshold as described in the Applications Information section and Appendix F. 

**LATCH (C5):** Latchoff Reset Pin. When a latchoff fault occurs, the LTM4641 turns off its output and latches MHYST on to indicate a fault condition has occurred (see HYST). To configure the LTM4641 for latched off response to latchoff faults, connect LATCH to SGND. As long as LATCH is logic low, the LTM4641 will not unlatch. Regulation can be resumed by cycling VINL or by toggling LATCH from logic low to high. It is also permissible to connect LATCH to INTVCC; this configures the LTM4641 for autonomous restart with a timeout delay (programmed by CTMR—see TMR). 

If no latchoff faults are present when LATCH transitions from logic low to logic high, the LTM4641 immediately unlatches. If any latchoff fault is present when LATCH is logic high, a timeout delay timing requirement is imposed: the LTM4641 will not unlatch until all latchoff fault-monitoring pins meet operationally valid states for the full duration of the timeout delay. If LATCH becomes logic low before that timeout delay has expired, the LTM4641 remains latched off and the timeout delay is reset. Unlatching the LTM4641 can be reattempted by pulling LATCH logic high at a later time. 

The following are latchoff fault conditions: 

- CROWBAR activates (see CROWBAR) 

- Input latchoff overvoltage fault (see OVLO) 

- Latchoff overtemperature fault (when OTBH is logic low; see TEMP and OTBH) 

LATCH is a high impedance input and must not be left electrically open circuit. LATCH can be driven by a μController in intelligent systems: a reasonable implementation for unlatching the LTM4641 is to pull LATCH logic high for the maximum anticipated timeout delay time—after which, HYST can be observed to indicate whether the LTM4641 has become unlatched. 

**1VREF (C6):** Buffered 1V Reference Output Pin. Minimize capacitance on this pin, to assure the OVPGM and TEMP pins are operational in a timely manner at power-up. 1VREF should never be externally loaded except as explained in the Applications Information section. 

**VOUT (C9-C12; D9-D12; E9-E12):** Power Output Pins of the LTM4641 DC/DC Converter Power Stage. All VOUT pins are electrically connected to each other, internally. Apply output load between these pins and the GND pins. It is recommended to place output decoupling capacitance directly between these pins and the GND pins. Review Table 9. See the Layout Checklist/Example section of the Applications Information section. 

**VORB[+] (D1):** VOSNS[+] Readback Pin. This pin connects to VOSNS[+] internal to the µModule regulator. It is recommended to route this pin (differentially with VORB[–] ) to a test point so as to allow the user a way to confirm the integrity 

4641fe 

11 

For more information www.linear.com/LTM4641 

LTM4641 

## **pin FuncTions** 

of the remote-sense connections prior to powering up the LTM4641. VORB[+] can also be connected as a redundant feedback connection to VOSNS[+] on the user’s motherboard. 

**VORB[–] (D2):** VOSNS[–] Readback Pin. This pin connects to VOSNS[– ] internal to the µModule regulator. It is recommended to route this pin (differentially with VORB[+] ) to a test point so as to allow the user a way to confirm the integrity of the remote-sense connections prior to powering up the LTM4641. VORB[–] can also be connected as a redundant feedback connection to VOSNS[–] on the user’s motherboard. 

**OTBH (D3):** Overtemperature Behavior Programming Pin. When an overtemperature condition is detected (see TEMP), HYST pulls logic low to inhibit switching. If OTBH is connected to SGND, the LTM4641 latches HYST low. If OTBH is left floating, output voltage regulation can resume when the overtemperature event clears. 

**TMR (D4):** Timeout Delay Timer and Power-On Reset (POR) Programming Pin. Connect a capacitor (CTMR) from TMR to SGND to program the POR and timeout delay time of the LTM4641; 9ms delay time per nanofarad of capacitance. The minimum delay time is ~90μs, when TMR is left electrically open circuit. Even though they use the same capacitor, the power-on reset and timeout delay timers operate independently of each other. Any nonlatching fault or latching fault will reset the respective timer to the full delay time without impacting the other timer. 

The timeout delay time programmed by a CTMR capacitor can be negated by pulling TMR to INTVCC. 

**RUN (D5):** Run (On/Off) Control Pin. A RUN pin voltage below 0.8V will turn off the module. A voltage above 2V will command the module to turn on, if HYST is not asserted low by MHYST. The LTM4641 contains a moderate (10k) pull-up resistor from HYST to INTVCC, and a pull-up Schottky diode from RUN to HYST (see Figure 1). When RUN is pulled logic low, HYST is pulled logic low via the internal Schottky diode. RUN is compatible with directdrive (totem-pole output drive) as well as open-collector/ open-drain interfaces. 

**VOSNS[+] (H1):** Positive Input to the Remote Sense Differential Amplifier. This pin connects to the positive side of the output voltage remote sense point (VOUT potential) via a resistor (RSET1A). When regulating the output voltage, 

the LTM4641 control loop drives the differential voltage between VOSNS[+] and VOSNS[–] to the lesser of TRACK/ SS and 0.6V. VOSNS[+] is connected to VORB[+] internal to the module (see VORB[+] ). A resistor may be needed from VOSNS[+] to VOSNS[–] for some output voltage settings. (See the Applications Information section: Setting the Output Voltage.) Minimize stray capacitance to this pin to protect the integrity of the output voltage feedback signal. 

**VOSNS[–] (H2):** Negative Input to the Remote Sense Differential Amplifier. This pin connects to the negative side of the output voltage remote sense point (GND potential) via a resistor (RSET1B). When switching action is on, the LTM4641 control loop drives the differential voltage between VOSNS[+] and VOSNS[–] to the lesser of TRACK/ SS and 0.6V. VOSNS[–] is connected to VORB[–] internal to the module (see VORB[–] ). A resistor may be needed from VOSNS[+] to VOSNS[–] for some output voltage settings. (See the Applications Information section.) Minimize stray capacitance to this pin to protect the integrity of the output voltage feedback signal. 

**SW (H10):** Switching Node of the Power Stage. Mainly used for testing purposes, however, one may optionally connect a snubber (series-configured capacitor CSW and resistor RSW) from SW to GND to reduce radiated EMI—in exchange for a minor compromise to power conversion efficiency. (See the Applications Information section.) 

**COMP (J1):** Current Control Threshold and Error Amplifier Compensation Point. The current comparator threshold of LTM4641’s valley current mode control loop—and correspondingly, the commanded trough of the power inductor current—increases as this control voltage increases. It can be useful to make COMP available for observation on a PCB via or test pad with an oscilloscope probe. However, stray capacitance and trace lengths to this sensitive analog node should be minimized. 

**fSET (J2):** Switching Frequency Setting and Adjustment Pin. This pin interfaces directly to the ION pin of LTM4641’s internal control IC. Current flow into the ION pin programs the on-time of the control loop’s one-shot timer and power control MOSFET, MTOP. Minimize stray capacitance and any tracelengths to this pin. 

For applications requiring regulated output voltages of 3V or less at any time including during voltage rail tracking, 

4641fe 

12 

For more information www.linear.com/LTM4641 

LTM4641 

## **pin FuncTions** 

an on-time adjustment with a resistor to fSET is required. Otherwise, fSET can be left open circuit. See the Applications Information section for details. 

**VINL (J3):** Input Voltage Pin, Low Current for Power Control and Logic Bias. Feeds LTM4641’s internal 5.3V LDO (see INTVCC). Apply input voltage bias between this pin and GND. Decouple to GND with a capacitor (0.1µF to 1µF). This pin powers the heart of LTM4641’s DC/DC controller and internal housekeeping ICs. VINL bias current is within ~5mA of the sum of INTVCC and CROWBAR loading currents. 

If using the advanced output overvoltage (OOV) protection features of the LTM4641, connect VINL to either the drain of the external power-interrupt power MOSFET, identified on the front page schematic as MSP, or a separate input bias supply. If not making use of the advanced OOV protection features, VINL and VINH can connect directly to the same input power source. 

LDO losses can be eliminated by connecting VINL, INTVCC, and DRVCC if a low power auxiliary ~5V rail is available to power the resulting node. (See the Applications Information section, Figure 47 and Figure 49.) 

**DRVCC (J4):** Power MOSFET Driver Input Power Pin. DRVCC is normally connected to INTVCC. It must be kept within two diode drops (2 • VBE or ~1.2V at 25°C) of INTVCC. DRVCC powers the internal MOSFET driver that interfaces to the switching MOSFETs (MTOP and MBOT) within LTM4641’s power stage. It is pinned out separately from INTVCC to allow gate-driver current to be observed, and to allow an auxiliary ~5V to 6V bias supply to optionally provide the MOSFET driver bias current. The INTVCC/DRVCC pin pair can be biased from up to 6V (absolute maximum) from an external supply with 50mA peak sourcing capability, to reduce the LTM4641’s INTVCC LDO losses (see Applications Information section and Figure 51). When DRVCC is connected directly to INTVCC, no bypass capacitance is needed except in rare applications where very fast output voltage ramp up is required (e.g., no soft-start capacitor on TRACK/SS, or rail-tracking rails with sub-60µs turn-on rise-time). Otherwise, ~2.2µF to 4.7μF X7R MLCC local bypassing to GND is recommended. Higher impedance sources may require higher bypass capacitance, to mitigate DRVCC sag during VOUT start-up. 

An undervoltage lockout detector monitors DRVCC. HYST is pulled low and switching action is inhibited if DRVCC is less than 4.2V rising (maximum) and 3.5V falling (maximum). 

**FCB (K2):** Forced Continuous/Pulse-Skipping Mode Operation Programming Pin. Connect this pin to SGND to force continuous mode operation of the synchronous power MOSFETs (MTOP and MBOT) at all output load conditions. Connect this pin to INTVCC to enable pulse-skipping mode operation: the freewheeling power switching MOSFET (MBOT) is turned off of to prevent reverse flow of output current (IOUT) at light loads. See Appendix E for more details. This is a high impedance input and must not be left electrically open circuit. 

**INTVCC (K4):** Internal 5.3V LDO Output. LDO operates off of VINL. The INTVCC rail biases low power control and housekeeping circuitry. INTVCC is usually connected to DRVCC to power the MOSFET drivers interfacing to the switching power MOSFETs. No decoupling capacitance is needed on this pin unless it is being used to bias external circuitry (not common); do not apply more than 4.7µF (±20% tolerance) of external decoupling capacitance. The INTVCC/DRVCC pin pair can be overdriven by an external supply, from up to 6V (absolute maximum) with 50mA peak sourcing capability, to eliminate power losses otherwise incurred by the LTM4641’s VINL-to-INTVCC linear regulator (see the Applications Information section and Figure 51). 

**VINH (K7-10; L7-12; M7-8, 11-12):** Input Voltage Pin, High Current to the Power Converter Stage of the LTM4641. All VINH pins are electrically connected to each other internally. Devote a large copper plane to connect as many of the VINH pins to each other as is feasible. This will help form a low impedance electrical connection between the input source and the LTM4641’s power stage. It will also provide a thermal path for removing heat from the BGA package and minimize junction temperature rise of the LTM4641 for a given application. 

If utilizing the advanced output overvoltage (OOV) protection features of the LTM4641, connect VINH to the source pin(s) of the external power-interrupt MOSFET, identified on the front page schematic as MSP, with a short wide trace, or preferably a small copper plane capable of adequately 

4641fe 

13 

For more information www.linear.com/LTM4641 

LTM4641 

## **pin FuncTions** 

handling the input current to LTM4641’s power stage. _Do not_ decouple the VINH pins with any bypass capacitance in this case. Instead, place all decoupling capacitance directly between the drain of MSP to GND. 

If not utilizing the advanced OOV protection features of the LTM4641, _do_ decouple the VINH pins to GND with local ceramic and bulk decoupling capacitance (see the Applications Information section). 

**PGOOD (L1):** Output Voltage Power Good Indicator. This is an open-drain logic output pin that is pulled to ground when the output voltage (and accordingly, the divided-down representation of the output voltage, VFB, as presented to the control loop) is outside ±10% of the nominal target for regulation. 

**TRACK/SS (L2):** Output Voltage Tracking and Soft-Start Programming Pin. This pin has a 1.0μA pull-up current source, typical. A capacitor can be placed from this pin to 

SGND to obtain an output voltage soft-start ramp-up rate whose turn-on time is 0.6ms per nanofarad of capacitance. Alternatively, when a voltage is applied to TRACK/SS through a resistor-divider network from another rail, the LTM4641 output is able to track the external voltage to satisfy coincident and ratiometric rail-voltage sequencing requirements. See the Applications Information section. 

**VING (M9):** Gate Drive Output Pin. If utilizing the advanced output overvoltage (OOV) protection features of the LTM4641, connect VING to VINGP and to the gate of the external power-interrupt N-channel MOSFET feeding VINH, identified on the front page schematic as MSP; otherwise, leave this pin electrically open circuit. 

**VINGP (M10):** Gate Drive Protection Pin. If utilizing the advanced OOV protection features of the LTM4641, connect VINGP to VING and to the gate of the external power-interrupt N-channel MOSFET feeding VINH, MSP; otherwise, leave this pin electrically open circuit. 

4641fe 

14 

For more information www.linear.com/LTM4641 

LTM4641 

## **siMpliFieD block DiagraM** 

**==> picture [524 x 440] intentionally omitted <==**

**----- Start of picture text -----**<br>
VIN VINL VIN<br>INTVCC 4V TO 38V<br>RTUV RHYST HYST 10k ION 0.1µF 1.3MfSET RfSET* CIN(MLCC)+ (4.5V START-UP)<br>ENABLE CIN(BULK)<br>UVLO SWITCHING<br>RBUV MHYST ACTION VING MSP<br>15V VINGP<br>VIN CONTROLPOWER ZENER VINH<br>2.2µF<br>MTOP<br>RTOV CONSTANT SW<br>RMOV IOVRETRYOVLO FAULT LATCHESCOMPARATORSPROTECTIONAND SYNCHRONOUSVALLEY MODEON-TIMEBUCK 0.8µH 10µFVOUT + COUT(BULK) V0.6V TO 6VUP TO 10AOUT<br>RBOV 1VREF CONTROLLER MBOT<br>COUT(MLCC)<br>3.48k GND<br>TEMP<br>NTC<br>SGND<br>VFB<br>OSC TO E/A<br>OTBH<br>TMR<br>CTMR LATCH<br>FCB<br>FAST OUTPUT<br>COMP OVERVOLTAGE CROWBAR<br>DRVCC COMPARATOR MCB<br>INTVCC ENABLE R C<br>PGOOD VORB [–]<br>8.2k<br>TRACK/SS 8.2k VOSNS [–] RSET1B<br>CSS 1VREF REF INTERNAL<br>4µF COMP 8.2k VOSNS [+] RSET2 RSET1A<br>RTOVPGM OVPGM 499k 8.2k VORB [+]<br>RBOVPGM COVPGM 1M VOUT = 0.61+ [R] 8.2k [SET1A] Ω + [2 •R] RSET2 [SET1A] <br>RUN USE RSET1A = RSET1B ≤8.2k<br>RSET2 REQUIRED FOR VOUT > 1.2V<br>4641 F01 RSET2 NOT NECESSARY FOR VOUT ≤ 1.2V<br>DASHED BOXES INDICATE OPTIONAL COMPONENTS<br>*RfSET REQUIRED FOR CERTAIN VIN/VOUT COMBINATIONS<br>  SEE APPLICATIONS INFORMATION SECTION<br>SGND CONNECTS TO GND INTERNAL TO MODULE, KEEP SGND<br>ROUTES/PLANES SEPARATE FROM GND, ON MOTHERBOARD<br>–<br>+<br>**----- End of picture text -----**<br>


**Figure 1. Simplified Block Diagram. cf. Functional Block Diagram in Appendix A, Figure 62** 

## **Decoupling requireMenTs** 

|**SYMBOL**|**PARAMETER**|**CONDITIONS**|**MIN**<br>**TYP**<br>**MAX**|**UNITS**|
|---|---|---|---|---|
|CIN(MLCC)+<br>CIN(BULK)|External Input Capacitor Requirement|IOUT= 10A, 2×10μF or 4×4.7μF|20|μF|
|COUT(MLCC)+<br>COUT(BULK)|External Output Capacitor Requirement|IOUT= 10A, 3×100μF or 6×47μF|300|μF|



4641fe 

15 

For more information www.linear.com/LTM4641 

LTM4641 

## **operaTion** 

## **Introduction** 

The LTM4641 contains a buck-topology regulator employing a constant on-time current mode control scheme, including built-in power MOSFET devices with fast switching speed and a power inductor. In its most basic configuration (see Figure 45), the module operates as a standalone nonisolated switching mode DC/DC step-down power supply. It can provide up to 10A of output current with a few external input and output capacitors and output feedback resistors. The supported output voltage range is from 0.6V DC to 6V DC. The supported input voltage range is 4V to 38V, with a maximum start-up voltage of 4.5V (over temperature). Power conversion from lower input voltages can be realized if an auxiliary bias supply is available to power LTM4641’s control and housekeeping bias input pin, VINL. The LTM4641 Simplified Block Diagram is found in Figure 1. For a more detailed look, the Functional Block Diagram is found in Appendix A, Figure 62. 

## **Motivation** 

Pulsed loading conditions and abnormal disturbances within the electrical systems found in industrial, vehicle, aeronautic, and military applications can induce wildly varying voltage transients (surges) on what is nominally a 24V DC to 28V DC distributed bus (28V DC bus). The duration of such disturbances can extend for periods of time between a millisecond to a minute in length, with excursions sometimes reaching (or exceeding) 40V and falling below 6V. 

While switching buck regulators are of universal interest due to their compact size and ability to deliver DC/ DC power conversion at high efficiency, FMEA (failure modes and effects analysis) leads one to believe that there is no way to reduce the severity rating and effects of an electrical short from the input source to the output load—however improbable. The LTM4641 challenges this notion by protecting the load from seeing excessive voltage stress, even when its high side switching MOSFET is short circuited. 

## **Power µModule Regulator Reliability** 

First and foremost, Linear Technology μModule products adhere to rigorous testing and high reliability control, fabrication, and manufacturing processes—as is required of all its products. Furthermore, as part of its commitment to excellence, the Linear Technology Quality Control program periodically updates its Reliability Data report for LTM4600 series products to include cumulative data obtained from ongoing and routine in-house testing relating to operational life, highly accelerated stress, power and temperature cycling, thermal and mechanical shock, and much more. To view the latest report visit http://www. linear.com/docs/13557. 

The LTM4641 easily supports high step-down ratios with few external components. The additional protection features when implemented provide an extra degree of insurance beyond other μModule regulators. 

## **Overview** 

When configured as shown in Figure 46, the LTM4641 can regulate an output voltage between 0.6V and 6V from an input voltage between 4V and 38V (4.5VIN start-up, maximum). 

If an optional N-channel power MOSFET, MSP, is placed between the input power source (VIN) and the power stage input pins (VINH), MSP’s role becomes that of a resettable electronic power-interrupt switch. The gate of MSP is operated by VING, and its gate-to-source voltage is assured to be clamped by a built-in 15V Zener diode accessed via VINGP. When switching action is engaged, VING charges the gate of MSP to nominally 10V above VINH potential—suitable for driving a standard-logic MOSFET—and MSP becomes enhanced to pull VINH up to the input source supply’s electrical potential. The switching regulator steps down VINH potential to VOUT when MSP is on. When switching action is inhibited by pulling the RUN pin low or when a fault condition is detected by LTM4641’s internal circuitry—such as an output overvoltage (OOV) condition—the gate of MSP is discharged and MSP turns off. The input source supply is thus disconnected from LTM4641’s power stage input (VINH). 

4641fe 

16 

For more information www.linear.com/LTM4641 

LTM4641 

## **applicaTions inForMaTion—power supply FeaTures** 

The operation of MSP as a power interrupter provides a critical element of robust OOV protection: it removes a means for input power to flow through a damaged power stage to any precious loads on the output voltage rail, even when input power is cycled. 

For even greater resilience to a short-circuit between VINH and the SW switching node of the power stage, an external logic-level N-channel power MOSFET, MCB, is optionally placed—in a crowbar configuration—on the output of the power module. When an OOV condition is detected, CROWBAR turns on MCB (within 500ns, maximum) to discharge the output capacitors and transform any residual energy in LTM4641’s power stage into a trivial amount of heat—energy which would otherwise have only served to inject charge into (further pump up the voltage on) the output capacitors, where precious loads reside. 

The control and monitoring circuitry within the LTM4641 power module provide the following: 

- Fast, accurate, latching output overvoltage detector (<500ns response time, <±12mv threshold error) 

- N-channel output overvoltage crowbar power MOSFET drive 

- Accurate (<±2.4%) nonlatching and resettable latching input overvoltage shutdown thresholds 

- N-channel overvoltage power-interrupt MOSFET drive 

- Accurate (<±2.4%) Input UVLO rising and UVLO falling thresholds 

- Built-in and adjustable overtemperature shutdown protection, programmable for resettable latching or nonlatching (hysteretic restart) response 

- Analog temperature indicator output pin 

- Adjustable power-on reset and timeout delay time 

- Latchoff behavior that can be altered to instead provide autonomous restart after timeout delay time expires 

- Parallelable for higher output power 

- Differential remote sensing of POL voltage 

- Internal loop compensation 

- Output current foldback protection 

- Selectable pulse-skipping mode operation 

- Output voltage soft-start and rail tracking 

- Power-up into pre-biased conditions without sinking current from the output capacitors 

- Adjustable switching frequency 

- Power good indicator 

- RUN enable pin 

Novel and simple circuit implementations with LTM4641 and a few external components enable surge ride-through protection and overtemperature detection of a powerinterrupt MOSFET. (See Figure 47, for example.) The aforementioned features enabled by LTM4641 are grouped by function and described in the remainder of the Applications Information section. 

## **Power (VINH) and Bias (VINL) Input Pins** 

LTM4641’s power stage (VINH) and control bias (VINL) input pins are brought out separately to allow freedom for implementing more sophisticated system configurations, such as: fully utilizing LTM4641’s advanced output overvoltage (OOV) protection features to protect the load (e.g., front page schematic or Figure 46); providing rudimentary input surge ride-through protection (Figure 47); performing DC/DC down conversion from a power rail below LTM4641’s inherent UVLO thresholds (from a 3.3V bus in Figure 49). 

If VINH and VINL are powered from separate rails, it is recommended to power up VINL prior to or concurrently with VINH. VINL should have a final value of at minimum 3.5V within 2ms of VINH exceeding 3.5V. The recommendation to sequence VINL ahead of or closely with VINH is not related at all to module device reliability but stems rather from a desire to assure that the control section of LTM4641 drives the MOSFETs in LTM4641’s power stage deterministically whenever any appreciable VINH voltage is present. It is always permissible for VINL voltage to be present—regardless of the state of VINH—however, realize that there is no UVLO detection on VINH. 

To prevent the control section from trying to regulate through a dropout condition or commencing switching activity in the absence of VINH potential, it is recommended 

4641fe 

17 

For more information www.linear.com/LTM4641 

LTM4641 

## **applicaTions inForMaTion—power supply FeaTures** 

to implement a custom UVLO falling setting above the dropout curve in Figure 4 (see also Figure 11). 

LT3010-5 is shown in Figure 47 to provide bias for VINL, to enable ride-through of 80V transients on VIN. UVLO detection of VIN is realized in this example by D2 creating a discharge path for VINL in the event of loss of VIN. 

VINH and VINL have no specific power-down sequencing requirement, only that VINL should stay above 3.5V whenever VINH is above 3.5V. 

VINL and VINH sequencing is inherently addressed by the LTM4641 in the Figure 45 and Figure 46 circuits. 

The VIN and VINL start-up and shutdown waveforms of the Figure 47 circuit—but with 1Ω output load and TMR tied to INTVCC—are shown in Figure 2. The effect of the timing capacitor, CTMR, that normally generates a power-on reset (POR) delay at start-up is negated by tying TMR to INTVCC. The ~3ms VIN-to-VOUT start-up delay time seen in Figure 2 is due to POR of the LTM4641’s fault-monitoring circuitry and soft-start ramp (CSS). 

**==> picture [192 x 94] intentionally omitted <==**

**----- Start of picture text -----**<br>
VIN<br>5V/DIV<br>VINL<br>5V/DIV<br>VOUT<br>500mV/DIV<br>2ms/DIV 4641 F02<br>**----- End of picture text -----**<br>


**Figure 2. Start-Up and Shutdown Waveforms of Figure 47 Circuit. TMR Tied to INTVCC to Highlight VIN and VINL Sequencing without POR Delay. 1Ω Load** 

## **Switching Frequency (On Time) Selection and Voltage Dropout Criteria (Achievable VIN-to-VOUT Step-Down Ratios)** 

The LTM4641 controller employs a current mode constant on-time architecture, in which the COMP voltage corresponds to the trough inductor current at which the internal high side power MOSFET (MTOP) is commanded on by the control loop—for a duration of time proportional to controller’s ION pin current (Refer to Figure 1). Regulation is maintained by a pulsed frequency modulation (PFM) 

scheme. During a load transient step-up, the control loop will command a higher inductor trough current to compensate for a deficiency in output voltage; the effective switching frequency will increase until the output voltage returns to normal (an overcurrent event, notwithstanding). During a load transient step-down, the control loop will command a lower inductor trough current to compensate for an excess of output voltage; the effective switching frequency will decrease until the output voltage returns to normal. The control loop perceives inductor current-sense information via the voltage signal that appears across the synchronous power MOSFET, MBOT, when MBOT is on (this is commonly referred to in the industry as RDS(ON) current sensing). 

The on-time of the one-shot timer—and hence the power control MOSFET, MTOP,—is given, in units of seconds, by: 

**==> picture [240 x 30] intentionally omitted <==**

where IION is in units of amperes. For output voltages greater than 3V, and for non-rail-tracking applications, no external RfSET resistor is needed, and the IION current (units: amperes) is set solely by the VINL voltage (units: volts) and the internal 1.3MΩ VINL-to-fSET resistor: 

**==> picture [241 x 27] intentionally omitted <==**

The switching frequency of operation of the LTM4641’s buck converter power stage at full load in this scenario is given, in Hz, by: 

**==> picture [240 x 29] intentionally omitted <==**

where VOUT is the desired nominal output voltage, in units of volts. 

An external RfSET resistor can be applied when setting VOUT greater than 3V, if desired, to obtain increased switching frequency. Usually, increasing switching frequency comes from a desire to reduce output voltage ripple and/or output capacitance requirement—but at a moderate penalty to DC/DC conversion efficiency. There are some limitations to how low an RfSET value can be applied in practice due 

4641fe 

18 

For more information www.linear.com/LTM4641 

LTM4641 

## **applicaTions inForMaTion—power supply FeaTures** 

to non-zero minimum off-time, dropout voltage, and maximum achievable switching frequency of operation. 

When an RfSET resistor external to the LTM4641 is connected between VINL and fSET to decrease the default on-time setting, the total ION current (units: amperes) is given by: 

**==> picture [240 x 30] intentionally omitted <==**

where VINL is in units of volts and RfSET is in units of ohms. RfSET is needed for output voltage settings less than or equal to 3VOUT, and for rail-tracking applications. 

The minimum on-time the LTM4641 supports is 43ns, typical, but guard banded conservatively to 75ns, maximum. Therefore, for a conservative design, tON should be larger than 75ns, typical. From Equation 1, it follows that IION should be designed to be less than 93.3μA. 

When an external RfSET resistor is applied between VINL and RfSET (and VINL and VINH are operating from the same rail—Figure 45 and Figure 46), the switching frequency of operation of the power stage at full load, in Hz, is given by: 

**==> picture [240 x 30] intentionally omitted <==**

where RfSET is in ohms, and VOUT is the desired nominal output voltage, in units of volts. 

In the general case, the switching frequency of the buck converter power stage at full load is given, in Hz, by: 

**==> picture [239 x 30] intentionally omitted <==**

See Appendix C for a detailed discussion on the following topics: 

- Why should the switching controller be operated at a higher switching frequency (i.e., programmed for a shorter on-time with RfSET) than that yielded by the internal 1.3MΩ VINL-to-fSET resistor alone… 

- When VINL and VINH are operated from separate supplies… 

- … why should RfSET ordinarily connect to the VIN power source rather than VINH (Figure 49)? 

- …when is it okay for RfSET to connect to VINH (Figure 47)? 

For application circuits of the form found in Figure 45, Figure 46, Figure 47 and Figure 51: see Figure 3 for the maximum recommended value of RfSET as a function of nominal target output voltage, and resulting full-load switching frequency corresponding to those RfSET values. 

Figure 3 can also be interpreted to provide the lowest recommended switching frequency for a given target output voltage. Table 1 summarizes nominal values of RfSET endorsed for some popular output voltages; use of commonly available ±5% tolerance resistors or better with ±100ppm/°C temperature coefficient or better is recommended. 

**==> picture [181 x 166] intentionally omitted <==**

**----- Start of picture text -----**<br>
100 700<br>50 RfSETREGION vs VOUT NEEDED FORRfSET NOT 600<br>TO AVOID VOUT > 3V<br>500<br>10<br>5 400<br>300<br>1<br>200<br>0.5<br>100<br>MAX RECOMMENDED RfSET<br>SWITCHING FREQUENCY<br>0.1 0<br>0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6<br>NOMINAL OUTPUT VOLTAGE (V)<br>4641 F03<br> VALUE (MΩ)<br>fSET TYPICAL f<br>SW<br> AT FULL LOAD (kHz)<br>MAXIMUM RECOMMENDED R<br>**----- End of picture text -----**<br>


**Figure 3. Maximum Recommended RfSET (Nominal Values) for Non-Tracking Applications, and Resulting Full-Load Operating Switching Frequency vs Nominal Output Voltage** 

- …for nominal output voltages of 3V and less? 

- …in rail-tracking applications? 

4641fe 

19 

For more information www.linear.com/LTM4641 

LTM4641 

## **applicaTions inForMaTion—power supply FeaTures** 

**Table 1. Endorsed RfSET Resistor Value vs Output Voltage for Non-Tracking Applications—and Resulting Full-Load Switching Frequency (cf. Figure 45, Figure 46, Figure 47, and Figure 51 Circuits)** 

|<br>**Frequency (cf. Figure**<br>**Circuits)**|<br>**45, Figure 46, Figure**|<br>**47, and Figure 51**|
|---|---|---|
|**VOUT(NOM) (V)**|**RfSET (MΩ) (Nearest**<br>**EIA-Standard Values)**|**fSW (kHz)**|
|0.6|0.787|175|
|0.7|0.825|200|
|0.8|0.887|215|
|0.9|0.931|235|
|1.0|1.00|255|
|1.2|1.13|285|
|1.5|1.43|315|
|1.8|2.00|325|
|2.0|2.55|330|
|2.5|5.76|335|
|Greater Than 3.0|∞(Not Used)|See Figure 2|
|3.3|∞(Not Used)|360|
|5.0|∞(Not Used)|550|
|6.0|∞(Not Used)|660|



In rail-tracking applications, it is recommended to use the RfSET value corresponding to the lowest voltage needed to be regulated during output voltage ramp down. For example: to ramp VOUT down to 0.5V requires RfSET to be not more than 750kΩ (nominal) per Figure 3. 

It is often permissible to use lower RfSET values than those indicated in Figure 3 and Table 1 if, for example, lower output ripple voltage and/or a lower output capacitance is desired. However, be aware of three guiding principles: 

- I. Minimum On-Time. Ensure IION < 93.3µA. See Equations 1 and 4. 

- II. Minimum Off-Time and Dropout Operation. The minimum off-time, tOFF(MIN), is the shortest time required for the LTM4641 to perform the following tasks: turn on its power synchronous MOSFET (MBOT), trip the control loop’s current comparator, and turn off MBOT. The minimum input voltage on VINH, in volts, that one can regulate the output at and still avoid dropout is given by: 

**==> picture [239 x 38] intentionally omitted <==**

where: 

- VOUT is nominal output voltage in volts. 

- tOFF(MIN) is the minimum length of time MBOT can be on, after MTOP turns off. For a conservative design, use a value of 300ns, taken from the Electrical Characteristics Table. 

- tON is the on-time of the power control MOSFET, MTOP, as programmed by the current flowing into the ION pin of LTM4641’s internal control IC. 

- RPS is the series resistance of the module’s power stage, from VINH to VOUT. For VIN ≥ 6V, this is less than 50mΩ, even at extreme temperatures (TJ ≈ 125°C). For VIN < 6V, the effective series resistance increases due to drop in INTVCC voltage and corresponding decreased gate-drive enhancement of MTOP. Printed circuit board (PCB) and/or cable resistance present in the copper planes and/or wires that physically connect the output of the module to the load adds to RPS’s effective value. 

- IOUT is the load current on VOUT in amperes. 

For applications of the form shown in Figure 45, Figure 46 and Figure 47: the minimum allowable VINH voltage of operation to avoid dropout for 3V < VOUT ≤ 6V is shown in Figure 4. The curves are a result of realizing that VIN(DROPOUT) equals VINH (neglecting MSP voltage drop) when dropout actually occurs, and that Equations 1 and 2 yield an expression for tON as a function of VINH. MTOP will be less fully enhanced during its on-time if DRVCC is less than its nominal value of 5.3V (for example, when VINL< 6V and when DRVCC bias is provided by INTVCC). DRVCC’s effect on RPS at low line is illustrated in Figure 4. 

- III. Maximum Attainable fSW. The maximum attainable switching frequency of operation (in units of Hz) for a given on-time (tON, in seconds) is governed simply by: 

**==> picture [234 x 32] intentionally omitted <==**

where a conservative value of 300ns can be used for t . OFF(MIN) 

4641fe 

20 

For more information www.linear.com/LTM4641 

LTM4641 

## **applicaTions inForMaTion—power supply FeaTures** 

**==> picture [190 x 199] intentionally omitted <==**

**----- Start of picture text -----**<br>
8.0<br>7.5<br>7.0<br>6.5<br>6.0<br>5.5<br>5.0<br>4.5<br>4.0<br>3.5<br>3.0<br>3 3.5 4 4.5 5 5.5 6<br>OUTPUT VOLTAGE SETTING (V) 4641 F04<br>10A OUTPUT, DRVCC BIASED FROM INTVCC (5.3VNOM)<br>10A OUTPUT, DRVCC BIASED TO 5.3V BY EXTERNAL SUPPLY<br>NO LOAD, DRVCC ≥ 4.2V(UVLO RISING) AND 3.5V<br>(UVLO FALLING)<br>LINE DROPOUT VOLTAGE (V)<br>**----- End of picture text -----**<br>


**Figure 4. Line Dropout Voltage vs Output Voltage at No Load and Full Load. Figure 45, Figure 46 and Figure 47 Circuit Applications. RfSET = Open and RSET1A, RSET1B, RSET2 Values Setting VOUT for Regulation at or Above 3V** 

Given that the PFM control scheme increases switching frequency (to as high as fMAX) to maintain regulation during a transient load step-up, the design guidance is: set the steady-state operating frequency fSW to be less than fMAX. Furthermore, when the LTM4641 is in dropout operation, the switching frequency of the converter _is_ fMAX. 

It is best to avoid operation in dropout scenarios, because the control loop will rail COMP high to command MTOP at highest possible duty cycle. If input voltage “snaps upwards” at a sufficiently high slew rate when COMP has railed, the control loop may be unable provide satisfactory line rejection. 

See Figure 11 to set the UVLO falling response of LTM4641 above the computed VIN(DROPOUT) voltage; this will inhibit switching action for VIN < VIN(DROPOUT). Input voltage ripple, and any line sag between the input source supply and the VINH pins—and voltage drop across the power interrupt MOSFET, MSP, if used—must be taken into account by the system designer. 

## **Setting the Output Voltage; the Differential Remote Sense Amplifier** 

A built-in differential remote-sense amplifier enables precision regulation at the point-of-load (POL), compensating for any voltage drops in the system’s output distribution path: the total variation of LTM4641’s output DC voltage over line, load, and temperature is better than ±1.5%. 

The basic feedback connection between the POL and the module’s feedback sense pins is shown in Figure 5. 

**==> picture [385 x 199] intentionally omitted <==**

**----- Start of picture text -----**<br>
CFFA, CFFB: FEEDFORWARD CAPACITORS YEILD IMPROVED TRANSIENT<br>RESPONSE WHEN FILTERING VOUT WITH ONLY MLCC OUTPUT CAPACITORS<br>(COUT(MLCC))<br>VOUT VOUT<br>+<br>LTM4641 CFFA COUT(BULK) COUT(MLCC)<br>ICT<br>TEST<br>VORB [+] POINT<br>TO ERRORVFB 8.2k8.2k VOSNS [+] RSET1A<br>AMPLIFIER<br>RSET2 LOAD<br>8.2k<br>RSET1B<br>VOSNS [–]<br>8.2k VORB [–] ICT CFFB 4641 F05<br>TRUE DIFFERENTIAL REMOTE TEST<br>SENSE AMPLIFIER SGND POINT ROUTE FEEDBACK SIGNAL AS<br>GND PLACE ALLFEEDBACK TWISTED PAIR IF USING WIRES).A DIFFERENTIAL PAIR (OR<br>SANDWICH BETWEEN GROUND<br>COMPONENTS<br>SGND CONNECTS TO GND INTERNAL TO MODULE. KEEP LOCAL TO THE PLANES TO FORM A PROTECTIVE SHIELD<br>MODULE SGND ROUTES/PLANES SEPARATE FROM GND LTM4641 GUARDING AGAINST STRAY NOISE<br>ON MOTHERBOARD<br>+<br>–<br>**----- End of picture text -----**<br>


**Figure 5. Basic Feedback Remote Sense Connections and Techniques; Setting the Output Voltage** 

4641fe 

21 

For more information www.linear.com/LTM4641 

LTM4641 

## **applicaTions inForMaTion—power supply FeaTures** 

The output voltage at the POL is differentially sensed via a symmetrical impedance-divider network. In Figure 1 and Figure 5, it is seen that the control loop regulates the output voltage such that the differential VOSNS[+] -to-VOSNS[– ] feedback signal voltage is the lesser of the TRACK/SS pin voltage or the regulator’s nominal bandgap voltage of 600mV. The arrangement and values of the resistors in the symmetrical impedance-divider network set the output voltage. 

The remote sense pins (VOSNS[+] , VOSNS[–] ) have redundant connections internal to the module to readback pins (VORB[+] , VORB[–] ). The readback pins provide a means to verify the integrity of the feedback signal connection during motherboard ICT (in circuit test). The importance of verifying the integrity of the connection of the feedback signal to the output voltage prior to powering up the input voltage cannot be understated. If one or both feedback pins are left electrically floating due to manufacturing assembly defect, for example, or if the remote-sense pins are short circuited to each other, the control loop and overvoltage-detector circuitry have no awareness of the actual output voltage condition. A compromised feedback connection presents a very real danger of (1) the control loop commanding on MTOP at the highest possible duty cycle—due to the lack of negative feedback—and (2) the LTM4641’s protection circuitry being unaware of any issue. In a production environment, modern day ICT can easily catch any such stuffing or assembly errors; in a lab or prototyping environment, an ohmmeter can do the job. 

For many applications that use a mixture of MLCC and bulk (low ESR tantalum or polymer) output capacitors, the symmetrical impedance-divider network that feeds back the POL’s voltage to the module need only be constructed with resistors RSET1A and RSET1B, for output voltages of 1.2VOUT and lower. RSET2 must be present for output voltages in excess of 1.2VOUT. RSET1A and RSET1B should always have the same nominal value. Applications with MLCC-only output capacitors (see Output Capacitors and Loop Stability in following pages) will demonstrate improved transient response when feedforward capacitors CFFA and CFFB, nominally equal in value, are installed electrically in parallel with RSET1A and RSET1B, respectively. 

Use of 0.1% tolerance resistors (or better) for RSET1A, RSET1B, and RSET2 are recommended—with temperature coefficients of resistance suitable for one’s operating range of PCB temperature—to assure that output voltage error introduced by resistor value variation is acceptable for the application. SMT resistors with T.C.R.s of ±25ppm/°C and better are readily available in the marketplace. 

For output voltage settings less than or equal to 1.2VOUT, RSET2 is not needed, and RSET1A and RSET1B are given by: 

**==> picture [240 x 33] intentionally omitted <==**

For output voltages above 1.2VOUT, RSET1A (and RSET1B) should be set equal to 8.2kΩ (or less, if 8.2kΩ is not a convenient value for the user), and RSET2 is then given by: 

**==> picture [241 x 42] intentionally omitted <==**

It is always permissible to select a value for RSET1A (and RSET1B) less than that given by Equation 9—and then calculate a valid value for RSET2 from Equation 10—as long as RSET1A and RSET1B are designed to withstand the higher resulting power dissipation. 

When VOUT is in regulation, the voltages at VOSNS[+] and VOSNS[–] are given by: 

**==> picture [242 x 58] intentionally omitted <==**

and 

**==> picture [254 x 13] intentionally omitted <==**

respectively. ∆VGND is the voltage drop between ground at the POL and LTM4641’s SGND pins in volts. This voltage drop is usually entirely a result of I • R drop in the output distribution path—largest when maximum load current is being drawn: 

**==> picture [252 x 15] intentionally omitted <==**

4641fe 

22 

For more information www.linear.com/LTM4641 

LTM4641 

## **applicaTions inForMaTion—power supply FeaTures** 

With RSET1A, RSET1B, and RSET2 determined, double-check the output voltage setting with: 

**==> picture [239 x 37] intentionally omitted <==**

Some recommended values for RSET1A, RSET1B, and RSET2 for popular output voltages are shown in Table 2. 

**Table 2. Recommended RSET1A, RSET1B and RSET2 Values for Some Popular Output Voltages, cf. Figure 5 Feedback Connections.** 

|<br>**Connections.**|||
|---|---|---|
|**VOUT**|**RSET1A, RSET1B**|**RSET2**|
|0.6V|0Ω|∞(Not Used)|
|0.7V|1.37kΩ|∞(Not Used)|
|0.8V|2.74kΩ|∞(Not Used)|
|0.9V|4.12kΩ|∞(Not Used)|
|1.0V|5.49kΩ|∞(Not Used)|
|1.2V|8.2kΩ|∞(Not Used)|
|1.5V|8.2kΩ|33.2kΩ|
|1.8V|8.2kΩ|16.5kΩ|
|2.0V|8.2kΩ|12.4kΩ|
|2.5V|8.2kΩ|7.5kΩ|
|3.3V|8.2kΩ|4.7kΩ|
|5.0V|8.2kΩ|2.61kΩ|
|6.0V|8.2kΩ|2.05kΩ|



See Appendix D for a detailed discussion on the following topics: 

- What is the rationale for using a symmetrical resistor network? 

- What should I do if I cannot shield the differential sense feedback lines with GND? (I anticipate differential mode noise in the feedback signal?) 

- What should I do if the module and the load(s) are separated by a significant distance (~50cm or more), or if the load current flows through a cable assembly or power connector? (I anticipate common mode noise in the feedback signal?) 

## **Input Capacitors** 

The LTM4641 module should be connected to a low AC impedance, nominally DC output voltage source. MLCC input bypass capacitors must be provided externally, as 

close in proximity to the module as possible (see Figure 43). If external MOSFET MSP is not used (Figure 45), two 10μF or four 4.7μF ceramic capacitors should be electrically connected directly between the VINH and GND pins. If MSP is used (Figure 46, Figure 47 and Figure 49), then MSP must be placed as close to the LTM4641’s VINH pins as possible, and two 10μF or four 4.7μF ceramic capacitors should be electrically connected directly between the drain of MSP and GND (see Figure 44). A 47μF to 100μF surface mount bulk capacitor can be used to supplement input power bypassing, and can share the burden of any local ceramic capacitors in filtering the power stage’s ripple current. If low impedance power planes are used to bring VIN to the vicinity of the module, input source impedance will be low enough that bulk capacitors will not be needed. A localized bulk input capacitor is needed when an underdamped LC-resonant tank is formed by routing long input leads or traces (low ESR inductance) bypassed only with MLCCs (ultralow ESR capacitance). 

Neglecting the inductor peak-to-peak current ripple, the RMS current of the input capacitor can be estimated as: 

**==> picture [241 x 31] intentionally omitted <==**

where η is the power conversion efficiency of the LTM4641 module and D is the duty cycle on-time of MTOP. The bulk capacitor can be a switcher-rated electrolytic aluminum capacitor or a polymer capacitor. 

For a buck converter, the switching duty cycle of MTOP can be estimated as: 

**==> picture [241 x 30] intentionally omitted <==**

## **Output Capacitors and Loop Stability/Loop Compensation** 

The current mode constant on-time architecture enables very high step-down input-to-output ratios with compelling transient response. It also enables cycle-by-cycle fast current limit and foldback current limit in an overcurrent condition. The LTM4641 is internally compensated to yield stability over all operating conditions. 

4641fe 

23 

For more information www.linear.com/LTM4641 

LTM4641 

## **applicaTions inForMaTion—power supply FeaTures** 

The output capacitors COUT(BULK) and COUT(MLCC) must be chosen with low enough effective series resistance (ESR) to meet the output voltage ripple requirements and provide localized bypassing for the load. Although the LTM4641 provides fast transient response, the output voltage at the POL is reliant on nearby charge stored in a reservoir of ceramic capacitors COUT(MLCC) to minimize sag and overshoot in the initial microseconds of a high dI/dt transient load step-up and step-down, respectively. If used, COUT(BULK) can be comprised of low ESR tantalum or low ESR polymer capacitor(s); these capacitors then serve as a local reservoir to replenish the MLCCs during transient load events. It is also possible to use COUT(MLCC) only, however, the use of feedforward capacitors, CFF, should then be installed in the remote-sense feedback path, to obtain an optimized transient response (see Figure 5 feedback connections). 

The COUT(MLCC) ceramic capacitors should be at least X5R-type material. X5R-type and X7R-type MLCCs are recommended when operating PCB temperatures are not more than 85°C and 125°C, respectively. Both materials are renown in the industry for having a relatively low capacitance change over their respective temperature range of operation (±15%). However, X5R and X7R MLCCs do exhibit significant loss of capacitance with applied DC voltage and are subject to aging effects, and this must be taken into account in any system design. Refer to the capacitor manufacturer’s specifications for details. 

The typical output capacitance range is between 200μF to 800μF. The system designer should use discretion in determining whether additional output filtering may be needed, if further reduction of output ripple—or output voltage deviation during dynamic load or line transient events—is required. 

In Table 9, guidelines are provided for output capacitor selection, for various operating conditions. The table optimizes total equivalent ESR and total bulk capacitance for the transient load step performance. Stability criteria is considered. The Linear Technology LTpowerCAD™ design tool is available for transient simulation and stability analysis, if desired. 

## **Pulse-Skipping Mode vs Forced Continuous Mode** 

In applications where high DC/DC conversion efficiency at light-load currents is highly desired—when the input voltage source is a battery, for example—pulse-skipping mode operation should be employed. Pulse-skipping mode operation prevents power flow from the output capacitors to the input source. Be aware, however, due to MBOT’s resulting asynchronous operation at light load, applications employing pulse-skipping mode may necessitate more output capacitance and/or a higher OVPGM setting than operation in forced continuous mode would. 

Pulse-skipping mode is activated by connecting FCB to INTVCC. Forced continuous operation is activated by connecting FCB to SGND. 

Be aware that in pulse-skipping mode and ultralight loads (say, less than 20mA out), the VING voltage may appear as a sawtooth waveform as a result of being charge-pumped at a slower rate, to conserve energy. 

See Appendix E for more information on how pulse-skipping mode works. 

## **Soft-Start, Rail-Tracking and Start-Up Into Pre-Bias** 

The TRACK/SS pin can be used to either soft-start the output of the LTM4641 regulator, or make LTM4641’s output voltage track another rail coincidentally or ratiometrically. When RUN or HYST is low, the TRACK/SS pin is discharged. When RUN and HYST are released, TRACK/SS sources a microamp of current. 

When a soft-start capacitor, CSS, is applied to the pin, the current source is responsible for generating an output voltage turn-on time of 0.6ms per nanofarad of capacitance. The power stage is high impedance (MTOP and MBOT are off) until the TRACK/SS pin voltage exceeds VFB, the remote-sense differential amplifier’s output voltage. This allows power-up into pre-biased output voltage conditions without sinking of current from the output capacitors. When TRACK/SS exceeds the control IC’s 600mV bandgap voltage, VFB is regulated at 600mV and VOUT reaches its nominal output voltage. 

4641fe 

24 

For more information www.linear.com/LTM4641 

LTM4641 

## **applicaTions inForMaTion—power supply FeaTures** 

Figure 6 shows idealized output voltage waveforms for applications in which LTM4641’s output (VOUT) tracks a master rail (VMASTER) coincidently and ratiometrically, respectively. 

**==> picture [165 x 316] intentionally omitted <==**

**----- Start of picture text -----**<br>
VMASTER<br>VOUT<br>TIME 4641 F06a<br>(6a) Coincident Tracking<br>VMASTER<br>VOUT<br>TIME 4641 F06b<br>(6b) Ratiometric Tracking<br>OUTPUT VOLTAGE<br>OUTPUT VOLTAGE<br>**----- End of picture text -----**<br>


**Figure 6. Two Different Modes of Output Voltage Tracking** 

To configure LTM4641 for coincident or ratiometric tracking, begin the design (initially) the same way as for nontracking applications: 

- (1) Determine the RSET1A , RSET1B, and RSET2 values appropriate for the final, “full-scale” (FS) output voltage. 

- (2) Determine the RfSET resistor needed to guarantee ramp down of the output voltage to the desired value. For example, if it is necessary for VOUT to ramp down to 0.8V while tracking the master rail, then RfSET is recommended from Table 1 to be ~887kΩ. If rampdown tracking is not needed, then RfSET can be chosen according to Table 1 (or Figure 3) and the FS output voltage of the LTM4641 generated rail. 

- (3) Choose output capacitors and input capacitors for the design in the same manner as is done for nontracking applications. 

To fulfill a coincident rail-tracking requirement, recognize that when the output voltage of the master rail reaches the tracking rail’s nominal FS voltage, the TRACK/SS pin of the LTM4641 (tracking slave) needs to be 600mV. This can be satisfied by forming a resistor-divider network composed of RTAC and RTBC, interfacing VOUT_MASTER to TRACK/SS of the LTM4641 tracking slave, and terminating to SGND of the LTM4641 tracking slave. In Figure 7 and Figure 8, U1 generates a master rail while U2 generates a coincident-tracking rail that follows U1’s output. Values of RTAC and RTBC are selected such that: 

**==> picture [239 x 37] intentionally omitted <==**

In the example circuit of Figure 7, the master rail generated by U1 ramps up its output to 1.8V. The coincident-tracking rail is generated by U2 and has a nominal FS output voltage of 1V. Values of RTAC and RTBC are determined such that when U1’s output reaches 1V, the TRACK/SS pin of U2 reaches ~600mV; choosing RTBC to be 10kΩ yields RTAC = (1V/0.6V – 1) • 10kΩ, or ~6.65kΩ. It is common to choose resistor values of 10k or less for this task, so that voltage offset errors introduced by the 1µA current source on TRACK/SS working into the RTAC/RTBC network are sufficiently small. 

To fulfill a ratiometric rail-tracking requirement, recognize that when the output voltage of the master rail reaches its final FS value, the TRACK/SS pin of the LTM4641 (tracking slave) needs to reach 600mV. This can be satisfied by forming a resistor-divider network composed of RTAR and RTBR, interfacing VOUT_MASTER to TRACK/SS of the LTM4641 tracking slave, and terminating to SGND of the LTM4641 tracking slave. In Figure 7 and Figure 8, U3 generates a ratiometric-tracking rail that follows U1’s output. Values of RTAR and RTBR are selected such that: 

**==> picture [240 x 37] intentionally omitted <==**

4641fe 

25 

For more information www.linear.com/LTM4641 

LTM4641 

## **applicaTions inForMaTion—power supply FeaTures** 

**==> picture [401 x 605] intentionally omitted <==**

**----- Start of picture text -----**<br>
VIN<br>4V TO 38V<br>(4.5V START-UP) + CINM(BULK) C10µFINM(MLCC)<br>50V 50V<br>×2 VING VINGP VINH SW VOUT_MASTER<br>R2MMfSET VINL VOUT C100µFOUTM(MLCC) 1.8VUP TO 10A<br>fSET CROWBA R 6.3V<br>LATCH ×3 CFFMA<br>VOR B [+] 1 220pF<br>UVLO<br>H YST RSETM1A<br>FCB U1 8.2k<br>1 INTVDRVCCCC LTM4641 VVOSNSOSNS [+][–] R16.4kSETM2 RSETM1B8.2k LOAD LOCAL HIGHFREQUENCYDECOUPLING<br>IOVRETRY VOR B [–] CFFMB<br>OVLO TE MP 220pF<br>1VR EF<br>1 OVPG M<br>OTB H<br>RUN R UN PGOO D<br>U1 VOUT RAMP TIME TRACK/SS TMR COMP SGND GND<br>t(CSOFTSTARTSS IN nF) = 0.6ms/nF • CSS C4.7nFSS 1<br>1<br>+ CINSC(BULK) C10µFINSC(MLCC) COINCEDENT TRACKING<br>50V 50V OF THE 1.8V RAIL<br>×2 VING VINGP VINH SW VOUT_SLAVE_C<br>R680kCfSET VINL VOUT C100µFOUTSC(MLCC) 1VUP TO 10A<br>fSET CROWBA R 6.3V<br>LATCH ×4<br>VOR B [+] 2<br>UVLO<br>H YST RSETC1A<br>FCB U2 5.49k<br>VOUT_MASTER 2 INTVDRVCCCC LTM4641 VVOSNSOSNS [+][–] R5.49kSETC1B LOAD LOCAL HIGHFREQUENCYDECOUPLING<br>R6.65kTAC IOVRETRYOVLO VTEOR MPB [–]<br>RTBC 2 OVPG1VR EFM<br>10k OTB H<br>2 RUN R UN PGOO D<br>TRACK/SS TMR COMP SGND GND<br>2<br>+ CINSR(BULK) C10µFINSR(MLCC) RATIOMETRIC TRACKING<br>50V 50V OF THE 1.8V RAIL<br>×2 VING VINGP VINH SW VOUT_SLAVE_R<br>R1MRfSET VINL VOUT 100µFCOUTSR(MLCC) 1.5VUP TO 10A<br>fSET CROWBA R 6.3V<br>LATCH ×4<br>VOR B [+] 3 220pFCFFRA<br>UVLO<br>H YST U3 RSETR1A<br>VOUT_MASTER 3 FCBINTVDRVCCCC LTM4641 VVOSNSOSNS [+][–] R33.2kSETR2 RSETR1B8.2k8.2k LOAD LOCAL HIGHFREQUENCYDECOUPLING<br>R20kTAR IOVRETRYOVLO VTEOR MPB [–] 220pFCFFRB<br>RTBR 3 OVPG1VR EFM<br>10k OTB H<br>3 RUN R UN PGOO D<br>TRACK/SS TMR COMP SGND GND 4641 F07<br>3<br>U1, U2 AND U3 SGND (                ) CONNECT TO GND INTERNAL TO THEIR RESPECTIVE MODULES.1 [,] 2 [,] 3<br>KEEP SGND ROUTES/PLANES OF MODULES SEPARATE FROM EACH OTHER AND FROM GND ON MOTHERBOARD<br>**----- End of picture text -----**<br>


**Figure 7. Examples of LTM4641 Performing Coincident and Ratiometric Rail-Tracking. cf. Figure 8 Waveforms** 

4641fe 

26 

For more information www.linear.com/LTM4641 

LTM4641 

## **applicaTions inForMaTion—power supply FeaTures** 

In the example circuit of Figure 7, the master rail generated by U1 ramps up its output to 1.8V. The ratiometric-tracking rail is generated by U3 and has a nominal FS output voltage of 1.5V. Values of RTAR and RTBR are determined such that when U1’s output reaches its final value, 1.8V, the TRACK/SS pin of U3 reaches ~600mV: choosing RTBR to be 10kΩ yields RTAR = (1.8V/0.6V – 1) • 10kΩ, or ~20kΩ. It is common to choose resistor values of 10k or less for this task, so that errors introduced by the 1µA current source on TRACK/SS are sufficiently small. 

Figure 8 shows an oscilloscope snapshot of the output voltage waveforms of the modules configured per the Figure 7 circuit, with 6Ω load on VOUT_MASTER and no load on the VOUT_SLAVE_C and VOUT_SLAVE_R outputs. 

**==> picture [198 x 84] intentionally omitted <==**

**----- Start of picture text -----**<br>
U1 VOUT<br>1V/DIV<br>U2 VOUT<br>1V/DIV<br>U3 VOUT<br>1V/DIV<br>RUN<br>5V/DIV<br>2ms/DIV 4641 F08<br>**----- End of picture text -----**<br>


**Figure 8. Output Voltage Waveforms of U1, U2 and U3. cf. Figure 7 Circuit.** 

For applications that do not require tracking or sequencing, applying at least 100pF on the TRACK/SS pin is recommended, corresponding to ~60μs output voltage start-up ramp time. The resulting soft-start period will limit start-up input surge current and output voltage overshoot. 

## **INTVCC and DRVCC** 

The LTM4641 module has an internal 5.3V low dropout regulator whose input is fed from the low current input voltage bias pin, VINL, through a Schottky diode. The output, INTVCC, is used to power control and housekeeping circuitry and the MOSFET drivers, and is up-and-running whenever bias on VINL is present. DRVCC is the power input 

pin to the MOSFET driver circuitry. In most cases, connect INTVCC to DRVCC. The INTVCC regulator can source up to 30mA, continuous, which is sufficient for powering DRVCC, even at the LTM4641’s highest recommended switching frequency (6VOUT condition). 

The power loss in the LDO can be considerable at high input voltage, given by: 

PLOSS(INTVCC_LDO) = (VINL – 5.3V) • (5mA + IDRVCC) (19) 

This power loss can be virtually eliminated when a ~5V to 6V rail is available to overdrive the INTVCC/DRVCC pins through a Schottky diode, as shown in the Figure 51 circuit. This is because the LDO can only pull INTVCC’s voltage in an upward direction—that is to say, the series-pass element turns off when INTVCC exceeds the LDO control loop’s regulation setpoint. Infrared thermal images in Figures 52 to 55 illustrate operating conditions in which up to ~5°C reduction in package surface temperature is obtained by employing this technique. Note the importance to provide a diode-ORed path from VIN to VINL and from INTVCC/DRVCC to VINL when INTVCC/DRVCC is overdriven by an auxiliary rail (or VOUT). This assures proper MOSFET driver behavior regardless of disappearance/appearance of VINL versus VAUX, in any combination or sequence of rail ramp-up/ramp-down events. The series-connected Schottky diode internal to the LTM4641 that feeds the LDO from VINL assures proper MOSFET driver and internal logic behavior, even in the event of rapid discharging and restoration of VINL. 

A housekeeping circuit that monitors DRVCC voltage inhibits switching action until DRVCC exceeds 4.05V. Once switching action commences, DRVCC is allowed to fall to 3.35V before switching action is inhibited. The DRVCC voltage monitor has glitch immunity characteristics as shown in Figure 12. 

DRVCC current is proportional to switching frequency. For applications with extremely fast output voltage start-up (e.g., CSS < 100pF on TRACK/SS, or rail tracking very fast rails with sub 60μs turn-on time), switching frequency may 

4641fe 

27 

For more information www.linear.com/LTM4641 

LTM4641 

## **applicaTions inForMaTion—power supply FeaTures** 

conceivably approach fMAX at start-up, however briefly (see Equation 8). When biasing DRVCC from INTVCC in such applications, INTVCC may require additional bypass capacitance to ride through the resulting current surge on DRVCC. INTVCC can by bypassed with up to 4.7μF (±20% tolerance) of external decoupling capacitance. 

## **1VREF** 

A housekeeping IC internal to the LTM4641 generates a 1V ±1.5% reference voltage. This voltage reference is generated independent of the control IC’s 600mV bandgap voltage. The 1VREF should only be used to alter the OVPGM threshold programming voltage for the fast OOV comparator (see Fast Output Overvoltage Comparator Threshold section) or to implement an auxiliary overtemperature detector with an NTC having ultrahigh resistance (470k at 25°C, B-value < 5000K)—in the manner shown in Figure 47. Loading 1VREF beyond ±100μA is not recommended. 

1VREF must become established quickly at start-up to properly bias OVPGM, and therefore no external capacitance should be applied to this pin. To minimize disturbance to the OVPGM voltage, dynamic step-loading of the 1VREF is not recommended. Figure 9 shows the step response of 1VREF to a 0μA to 100μA step load with 100A/s slew rates, and the resulting impact to OVPGM’s voltage waveform. 

**==> picture [198 x 107] intentionally omitted <==**

**----- Start of picture text -----**<br>
1VREF<br>100mV/DIV<br>AC-COUPLED<br>I1VREF<br>50µA/DIV<br>SoEaE=<br>OVPGM<br>10mV/DIV<br>AC-COUPLED<br>20µs/DIV 4641 F09<br>bau pies<br>**----- End of picture text -----**<br>


**Figure 9. Response of 1VREF to 0μA** ⇔ **100μA Load Steps Applied at 100A/s—and Resulting Disturbance and Recovery of OVPGM. Figure 45 Circuit at 28VIN. Do Not Load 1VREF Arbitrarily** 

## **TEMP, OTBH and Overtemperature Protection** 

As seen in Figure 1, a resistor-NTC-divider network formed between 1VREF and SGND generates TEMP, an analog temperature indicator pin. The pin nominally measures ~0.98V at 25°C and colder, and ~585mV at 125°C. A graph of the relationship between junction temperature, NTC resistance, and TEMP voltage is found in Figure 10. 

The TEMP pin also connects indirectly to a comparator input whose output can pull HYST low to inhibit switching action. If TEMP falls below 438mV, corresponding to a junction temperature of ~147°C, switching action is inhibited. If OTBH is logic low when TEMP falls below 438mV, a latchoff overtemperature event is registered. Restarting regulation after a latchoff event has occurred is explained in detail in the Start-Up/Shutdown section. If OTBH is open circuit when TEMP falls below 438mV, a nonlatching overtemperature event is registered: switching action can resume when the units cools off and the TEMP pin rises above 514mV, corresponding to a junction temperature of ~136°C. 

The LTM4641’s overtemperature protection feature is intended to protect the device during momentary overload conditions. Recognize that the LTM4641 is rated for 125°C junction, absolute maximum, and that junction temperature exceeds 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. 

The overtemperature protection circuit can be disabled by connecting TEMP to 1VREF. With moderate linear circuit analysis, the information in Figure 10 and Figure 62 (Appendix A) can be used to alter the overtemperature inception and recovery thresholds. If desired, the thresholds can be increased by applying a resistor from TEMP to 1VREF, or decreased by applying a resistor from TEMP to SGND. The overtemperature comparator contains built-in filtering, yielding glitch immunity characteristics shown in Figure 12. 

4641fe 

28 

For more information www.linear.com/LTM4641 

LTM4641 

## **applicaTions inForMaTion—inpuT proTecTion FeaTures** 

**==> picture [190 x 166] intentionally omitted <==**

**----- Start of picture text -----**<br>
1000000<br>0.95<br>0.85<br>100000 0.75<br>0.65<br>0.55<br>10000<br>0.45<br>0.35<br>1000 0.25<br>–55 –15 25 65 105 145 185<br>JUNCTION TEMPERATURE (°C)<br>4641 F10<br>NTC RESISTANCE (Ω) TEMP PIN VOLTAGE (V)<br>**----- End of picture text -----**<br>


**Figure 10. Relationship of NTC Resistance to Junction Temperature and Resulting TEMP Voltage. Curves for Nominal Values and Calculated Extreme Values Shown** 

## **Input Monitoring Pins: UVLO, IOVRETRY, OVLO** 

The UVLO pin feeds directly into the inverting input of a comparator whose trip threshold is 0.5V. The behavior of the UVLO pin is an example of a nonlatching fault: when the UVLO pin falls below 0.5V, HYST is pulled low and switching action is inhibited; when the UVLO pin exceeds 0.5V, HYST goes logic high and switching action can resume. The IOVRETRY and OVLO pins each feed directly into noninverting inputs of comparators whose trip thresholds are 0.5V. The behavior of the IOVRETRY pin is also an example of a nonlatching fault pin: when the IOVRETRY pin exceeds 0.5V, HYST is pulled low and switching action is inhibited; when IOVRETRY falls below 0.5V, switching action can resume. The behavior of the OVLO pin is an example of a latchoff fault pin: when the OVLO pin exceeds 0.5V, HYST is pulled low and switching action is inhibited; when OVLO subsequently falls below 0.5V, HYST remains latched low, and switching action cannot occur until the latch has been reset. Restarting regulation after a latchoff event has occurred is explained in detail in the Start-Up/Shutdown section. 

These three pins give added flexibility to tailor some behaviors of the LTM4641. The UVLO pin input is primarily used to set customized UVLO rising and UVLO falling thresholds, utilizing a high impedance connection to the HYST pin to obtain hysteresis. There are times when the LTM4641’s default UVLO rising and UVLO falling thresholds of 4.5VIN rising (maximum) and 4VIN falling (maximum) 

are not suitable. For example, it can be convenient to apply customized UVLO settings to inhibit switching prior to entering a region of possible dropout operation (Figure 51). It may be desirable to set a very large UVLO hysteresis, if line sag is problematic. UVLO is highly recommended to be customized to monitor the source supply feeding VINH when VINL is biased from an auxiliary rail (Figure 49). 

The UVLO pin input may also be used to provide novel circuit solutions such as one found in Figure 47: to detect an overtemperature event in MSP—sensed via an external NTC in close proximity to the power interrupt MOSFET, MSP; and to respond to MSP overtemperature by inhibiting switching action and turning off MSP until the MOSFET returns to normal temperatures. 

IOVRETRY is primarily used to set the input voltage (VIN) threshold above which switching action is inhibited, but not latch off. OVLO is primarily used to set the input voltage (VIN) threshold above which switching action latches off. Just as the UVLO pin can be used in versatile ways, so can IOVRETRY and OVLO. 

Consult Appendix A to see the UVLO/IOVRETRY/OVLO pins’ functions in greater detail. 

The most common arrangement of components connecting VIN to UVLO, HYST, IOVRETRY and OVLO is shown in Figure 11. 

**==> picture [209 x 203] intentionally omitted <==**

**----- Start of picture text -----**<br>
VIN + CIN(MLCC)<br>CIN(BULK) 10µF<br>×2<br>VINH<br>VINL<br>RTUV UVLO < 0.5V = OFF<br>UVLO<br>RBUV RHYST LTM4641<br>HYST<br>HYST PULLS UP WHEN<br>ON, HYST PULLS DOWN<br>WHEN OFF<br>RTOV<br>IOVRETRY > 0.5V = OFF<br>IOVRETRY<br>RMOV<br>OVLO > 0.5V = LATCHOFF<br>OVLO<br>RBOV SGND GND<br>4641 F11<br>SGND CONNECTS TO GND INTERNAL TO MODULE.<br>KEEP SGND ROUTES/PLANES SEPARATE FROM GND<br>ON MOTHERBOARD<br>**----- End of picture text -----**<br>


**Figure 11. Setting the LTM4641 Custom UVLO Rising and UVLO Falling Thresholds, Nonlatching Input Overvoltage Threshold, and Latching Input Overvoltage Threshold** 

4641fe 

29 

For more information www.linear.com/LTM4641 

LTM4641 

## **applicaTions inForMaTion—inpuT proTecTion FeaTures** 

Variables to define up-front are as follows: 

- VSU: VIN start-up voltage, in volts. This is the customized UVLO rising voltage. 

- VSD: VIN shutdown voltage, in volts. This is the customized UVLO falling voltage. 

- VHYST: The value of the voltage on the HYST pin (in volts) when switching action is on and just prior to the input voltage (VIN) falling below VSD. 

- RHYST: The hysteresis-setting resistor. If used, RHYST is recommended to take on a value of 1MΩ or higher, so that the HYST voltage is negligibly affected by external loading. 

- VOV: The input voltage above which a latchoff input overvoltage event occurs. 

- VRT: The input voltage above which a nonlatching input overvoltage event occurs. 

Then, RTUV and RBUV are given by: 

**==> picture [240 x 30] intentionally omitted <==**

and 

**==> picture [240 x 45] intentionally omitted <==**

UVOVTH is nominally 0.5V, from the Electrical Characteristics Table. The value of VHYST used in the above equations requires more careful consideration. Review Figure 1 and assess system details of the specific application in which the LTM4641 is being placed. It is known from the Electrical Characteristics table that when VINL ≥ 6V that INTVCC = 5.3V; and we see the voltage on the HYST pin, when switching action is on, is VHYST(SWITCHING_ON), 5.1V—nominally. Observe that if the RUN pin were driven high by 3.3V logic, however, that VHYST would be a Schottky diode forward-voltage drop above 3.3V—and VHYST in that instance would be 3.6V. If VSD is targeted below 6VIN, it is necessary to consider that VHYST’s pull-up voltage, INTVCC, is decreasing with VINL. For example, at VINL = 4.5V input, INTVCC is nominally 4.3V (VINTVCC(LOWLINE)), 

and it is inferred (in that scenario) that VHYST would be closer to 4.1V, when RUN is floating. 

It is the moderately weak pull-up strength of HYST (10kΩ pull-up to INTVCC), and the desire for any loading of the HYST signal to negligibly alter the HYST logic-high output voltage level (less than ~50mV), that motivates a high impedance (~1MΩ) hysteresis-setting resistor to interface between HYST and UVLO, when custom UVLO settings are desired. 

The customized UVLO start-up and shutdown input voltage settings can be double-checked with: 

**==> picture [239 x 38] intentionally omitted <==**

**==> picture [239 x 30] intentionally omitted <==**

To set the input overvoltage (latching and nonlatching) thresholds, choose first how much current, IDIV, to continually have drawn by the RTOV/RMOV/RBOV resistor-divider string for this function, at ultrahigh line. 10μA to 20µA is a normal amount to allocate. 

The total resistance of the divider string is then given by: 

**==> picture [241 x 30] intentionally omitted <==**

Then, the resistors in the input overvoltage divider are given by: 

**==> picture [241 x 30] intentionally omitted <==**

**==> picture [252 x 61] intentionally omitted <==**

It may be tempting to try rearranging these equations so that RTOV’s value is fixed, first, and to compute RMOV and RBOV subsequently. However, due to large divide-down ratio (usually) of ultrahigh line input voltage down to these pins with ~0.5V thresholds, the rounding off of RMOV and RBOV to nearest EIA standard values after fixing RTOV’s 

4641fe 

30 

For more information www.linear.com/LTM4641 

LTM4641 

## **applicaTions inForMaTion—inpuT proTecTion FeaTures** 

value in place often significantly alters one or both VIN referred overvoltage thresholds. It is more efficient to work through Equations 24 to 27 in the sequence shown and iterate (if necessary) towards finding convenient (EIA standard) resistor values. 

The latchoff input overvoltage threshold can be doublechecked with: 

**==> picture [239 x 38] intentionally omitted <==**

The nonlatching overvoltage threshold can be doublechecked with: 

**==> picture [238 x 40] intentionally omitted <==**

The UVLO, IOVRETRY and OVLO pins do not require any filter capacitance due to built-in filtering in the LTM4641’s housekeeping IC. This results in glitch immunity with characteristics shown in Figure 12. 

**==> picture [164 x 164] intentionally omitted <==**

**----- Start of picture text -----**<br>
700<br>600<br>RESPECTIVE<br>500 FAULT CONDITION<br>BECOMES DETECTED<br>400<br>300<br>200<br>100<br>GLITCH<br>IGNORED<br>0<br>0.1 1 10 100<br>COMPARATOR OVERDRIVE PAST THRESHOLD (%)<br>4641 F12<br>s)<br>µ<br>TYPICAL TRANSIENT DURATION (<br>**----- End of picture text -----**<br>


**Figure 12. Transient Duration vs Comparator Overdrive Glitch Immunity Characteristics. Monitored Signals: UVLO, IOVRETRY, OVLO, TEMP, CROWBAR and DRVCC** 

The LTM4641 powers up its output when the following conditions are met: 

- RUN exceeds 1.25V (nominal; 2V, overtemperature); power-on reset (POR) and timeout delay times do not apply to RUN. 

- All nonlatching fault-monitor pins have been in their operationally valid states for the full duration of the POR delay time, set optionally by CTMR (the capacitor on the TMR pin). Explicit pins and operationally valid thresholds follow: 

   - a. DRVCC > 4.05V. In the circuits of Figures 45 and 46, this is guaranteed for VINL ≥ 4.5V, minimum. In Figure 49, this requirement is met when the auxiliary bias supply exceeds 4.05V. 

   - b. UVLO > 500mV 

   - c. IOVRETRY < 500mV 

   - d. TEMP > 514mV (when OTBH is electrically open circuit) 

- No latchoff fault conditions are present, and the LTM4641 is not in a “latched off” state from any previously detected latchoff fault condition. If a latchoff fault condition occurs/occurred, the LTM4641 must be unlatched by a logic high LATCH signal: if all latchoff fault-monitoring pins are in operationally valid states when LATCH transitions from logic low to high, the LTM4641 becomes immediately unlatched; if, instead, any latchoff fault-monitoring pin is outside its operationally valid state when LATCH is logic high, the LTM4641 becomes unlatched if LATCH remains logic high after all latchoff fault-monitoring pins have been in their operationally valid states for the full duration of the timeout delay time (set optionally by CTMR). Explicit pins and operationally valid thresholds follow: 

   - a.  OVLO < 500mV 

## **Start-Up/Shutdown and Run Enable; Power-On Reset and Timeout Delay Time** 

The LTM4641 is a feature-rich and versatile self-contained DC/DC converter system, and includes multiple on-board supply monitors. The inputs to several monitors are available to the user for system customization (UVLO, OVLO, IOVRETRY and TEMP). 

- b.  TEMP > 514mV (when OTBH is logic low) 

- c.  CROWBAR < 1.5V 

The POR and timeout delay time is 9ms per nanofarad of CTMR capacitance. If CTMR is not used, the POR and timeout delay time is ~90μs. 

4641fe 

31 

For more information www.linear.com/LTM4641 

LTM4641 

## **applicaTions inForMaTion—loaD proTecTion FeaTures** 

If any nonlatching fault conditions occur, internal circuitry pulls HYST low and switching action is inhibited. The power stage will be high impedance until the aforementioned startup conditions are met. If any latchoff fault condition occurs, HYST is latched low and switching action is inhibited until the LTM4641 is unlatched (by pulling LATCH logic high) or VINL power is recycled (with INTVCC falling below 2V). 

The LTM4641 can be configured to restart autonomously after an adjustable timeout delay time—instead of exhibiting latchoff behavior—by leaving LATCH logic high (connected to INTVCC, for example) and setting the hiccup retry timeout delay time with CTMR (see Figure 47). Be reminded that use of CTMR also introduces POR behavior, yet the POR and timeout delay timers operate independently. The effect of CTMR can be negated by pulling the TMR pin to INTVCC. 

Switching action will be inhibited if any of the following occur: 

- RUN is less than 1.15V (nominal; 0.8V, overtemperature). Not a fault; no POR or timeout delay time is imposed. 

- Any nonlatching faults occur: 

   - a. DRVCC falls below 3.35V. In the Figure 45 and Figure 46 circuits, this happens at VINL < 4V, maximum. 

   - b. UVLO falls below 0.5V. 

   - c. IOVRETRY exceeds 0.5V. 

   - d. TEMP falls below 438mV when OTBH is electrically open circuit. 

- Any latchoff faults occur: 

   - a. OVLO exceeds 0.5V. 

   - b. CROWBAR exceeds 1.5V. 

   - c. TEMP falls below 438mV when OTBH is logic low. 

The LTM4641’s state diagram is provided in Appendix B. Start-up and shutdown mechanisms for any given operating scenario are identified in the state diagram. The TEMP and DRVCC pins have built-in hysteresis. The UVLO, IOVRETRY, OVLO, TEMP, CROWBAR and DRVCC pins connect to comparators with built-in glitch immunity, with characteristics indicated in Figure 12. 

## **Overcurrent Foldback Protection** 

The LTM4641 has overcurrent protection (OCP). In a short circuit from VOUT to GND, the internal current comparator threshold folds back during a short to reduce the output current, progressively down to about one-third of its normal value (down from 24A to 8A, typical). To recover from foldback current limit, the excessive load or low impedance short needs to be removed. Foldback current limiting action is disabled during soft-start and tracking start-up. 

## **Power Good Indicator and Latching Output Overvoltage Protection** 

Internal overvoltage and undervoltage comparators assert the open-drain PGOOD output logic low if the output voltage is outside ±10% of nominal, after a 12μs “blanking time”. The blanking time allows the output voltage to experience brief excursions (due to large load-step transients, for example) without nuisance-tripping PGOOD. The PGOOD output is deasserted without any deliberate blanking time when the output voltage returns to (or enters) the power good window, with ~2% to 3% of hysteresis. If the feedback voltage exceeds the upper PGOOD valid limit, the synchronous power MOSFET, MBOT, turns on (with no blanking time)—to try sinking current from the output to GND, through LTM4641’s power inductor—until the output voltage returns to the PGOOD valid region. If the output voltage exceeds an adjustable threshold set by OVPGM, whose default value corresponds to 11% above nominal, the LTM4641 pulls its CROWBAR output logic high immediately (500ns response time, maximum) and latches off its output voltage: the power stage becomes high impedance, with both MTOP and MBOT turning off and staying latched off; furthermore, MSP’s gate is pulled to VINH potential rapidly (<2.6μs response time, maximum), to disconnect the input source voltage from the module’s power stage. Restarting regulation after a latchoff event has occurred is explained in detail in the Start-Up/Shutdown section. 

The behavior of turning on the synchronous MOSFET during detection of an output overvoltage is a rudimentary and popular kind of output overvoltage protection scheme commonly found in the power supply and semiconductor control IC industry. It can provide mediocre overvoltage 

4641fe 

32 

For more information www.linear.com/LTM4641 

LTM4641 

## **applicaTions inForMaTion—loaD proTecTion FeaTures** 

protection during severe load current step-down events, but is not very effective at protecting loads from genuine fault conditions such as a short circuited high side power switching MOSFET. Furthermore, such schemes tend to be implemented with the overvoltage detector’s threshold dependent on the same bandgap voltage that the output is being regulated to. Applications needing superior output overvoltage and load protection require the performance achieved with the output crowbar MOSFET, MCB and power interrupt switch, MSP, and LTM4641’s use of an independent reference voltage(1VREF) to generate an OOV threshold. 

## **Power-Interrupt MOSFET (MSP), CROWBAR Pin and Output CROWBAR MOSFET (MCB)** 

Within 500ns (maximum) of the control-loop-referred feedback signal, VFB, exceeding the voltage on OVPGM (plus-or-minus OVPERR), an OOV event is detected, and the CROWBAR output swings high enough to turn on an optional crowbaring device (MCB) residing on VOUT. No more than 2.6µs after OOV detection, VING is discharged and an optional power interrupt switch, MSP, disconnects the LTM4641’s power stage from the input source supply. 

When MCB and MSP are used in conjunction as shown in the Figure 46 circuit, the LTM4641 is able to provide best-in-class output overvoltage protection against arguably the most despised failure mode high step-down buck converters can theoretically suffer: an electrical short between the input source to the output, via the switching node. Turning on MCB upon detection of OOV helps discharge the output capacitors and prevent any further positive excursion of output voltage by transforming residual energy in LTM4641’s power stage into heat; meanwhile, turning off MSP removes a path for current flow between the input power source and the output—preventing hazardous (input) voltage from reaching the precious load. 

It should be noted that when an OOV event is detected, CROWBAR is not held high (equivalently, MCB is not left turned on) indefinitely. The act of pulling CROWBAR high (above 1.5V nominal), whether due to internal or external circuitry, invokes a latchoff response and strong discharge of VING; HYST is latched low and switching action is inhibited after CROWBAR overcomes the glitch immunity requirement (see Figure 12). The fast OOV comparator’s output 

is fed through a blocking PN diode into a 10nF capacitor on the CROWBAR output; internal circuitry interfacing to CROWBAR presents itself as a ~10kΩ load (see Figure 62 in Appendix A). The use of the PN diode and 10nF capacitor creates a way for the CROWBAR output to stay logic high, even if the duration of OOV is very brief, and assures the glitch immunity of the latchoff detection circuitry is overcome. The 10kΩ load and 10nF capacitor provide an upper bound for the duration of time MCB might be on after CROWBAR activates: 400μs, or four time constants. Parasitic capacitance on the gate of MCB may increase this time, slightly. 

Observe that when HYST is low, the noninverting input to the fast OOV comparator (see Appendix A) is clamped by a Schottky diode. (When RUN is low, the noninverting input to the fast OOV comparator is clamped by two series Schottky diodes.) This differs from when switching action is engaged, where the noninverting input to the fast OOV comparator is normally the VFB signal. Therefore, be aware that the CROWBAR output is nominally inhibited when switching action is inhibited. 

Restarting regulation after a latchoff event has occurred is explained in detail in the Start-Up/Shutdown section. 

MCB should be placed close to the majority of the load(s)’s bulk and MLCC local bypass capacitors. CROWBAR should be connected to the gate of MCB with a generous signal trace width (20mils, or 0.5mm), to support driving the peak current needed to turn on MCB upon OOV detection. At the instant that MCB turns on, it typically draws hundreds of amps from the output capacitors which are mainly located near the load. When MCB turns off, the B-field that may have been built up in the parasitic inductance in the copper plane between the output capacitors and MCB cannot vanish instantaneously, and the collapsing of that B-field can induce a negative voltage across the output capacitors and load. Closer proximity of MCB to the majority of the output capacitors minimizes this parasitic inductance and hence the resulting magnitude of the negative voltage spike. 

MCB must be selected according to the following criteria: 

- MCB must be a logic-level N-channel MOSFET 

- The drain-to-source rating of MCB must be greater than the maximum output voltage, VOUT(PEAK,OOV_DETECTED) 

4641fe 

33 

For more information www.linear.com/LTM4641 

LTM4641 

## **applicaTions inForMaTion—loaD proTecTion FeaTures** 

- When CROWBAR goes logic high, the peak drain current in MCB will be given by VOUT(PEAK,OOV_DETECTED)/ RDS(ON). The peak drain current, and its duration, must not exceed the maximum safe operating area of the MOSFET; consult the MOSFET vendor’s data sheet. An upper bound for MCB’s on-time is 400μs. However, this worst-case conduction time can only happen if the output capacitance on VOUT is extraordinarily large. The length of time that MCB can possibly conduct ultrahigh drain current is also bounded by 4 • RDS(ON) • COUT(TOTAL). In a majority of applications, output capacitance is low enough that MCB does not conduct ultrahigh drain current for longer than a few microseconds, as seen on the front page. 

- MCB’s junction temperature must not exceed its specified maximum at any time. Consult the MOSFET vendor’s data sheet for device thermal characteristics for “single shot” thermal transients or “single pulse” power-handling capability. The peak power sustained by MCB is VOUT(PEAK,OOV_DETECTED)[2] /RDS(ON). 

If MCB is used and it is expected that LATCH will be toggled high (to unlatch the LTM4641) or held logic high continuously (for automatic LTM4641 restart after faultoff), recognize that peak power sustained by MCB during CROWBAR activity may not be single pulse anymore. Therefore, to prevent MCB thermal overstress in such applications, it is recommended to use CTMR to set a reasonable cool-down period for the MOSFET. Additionally, one may opt to implement a circuit that shuts down the LTM4641 when MCB temperature is detected to be too high: a minor modification to Figure 47, RT1 would be located as close in proximity to MCB as possible (instead of MSP), and R1, R2, and R3 would be experimentally determined. Consult the MOSFET vendor’s data sheet for maximum rated junction temperature and device thermal characteristics for repeated pulsed-power transients. 

When using MSP, connect VING to VINGP and to the gate of MSP. See the Input Capacitors section (earlier) for information on the input bypassing technique when MSP is used. 

MSP must be selected according to the following criteria: 

- MSP can be either a standard logic or a logic-level N-channel MOSFET. 

- The drain-to-source breakdown voltage of MSP must be greater than the maximum input source voltage. Consult the MOSFET vendor’s data sheet and consider temperature effects. 

- In order to support very fast turn-on of output voltage (e.g., sub 1ms ramp up), MSP should be turned on quickly to bring up VINH quickly. Therefore, a gate input capacitance (CISS) below 4.7nF is preferred (less is better). 

- MSP must be able to conduct the maximum input current to the LTM4641’s power stage without getting too hot. Choose a suitable MOSFET package size and RDS(ON) that results in reasonable MOSFET junction temperature rise. Be mindful that IQ(VINH) is highest during low line operation. 

Blowing a series-pass input fuse with a crowbaring SCR can be an effective overvoltage protection scheme for higher output voltages, e.g., 5V, but a crowbaring MOSFET on the output of the converter is more effective at clamping the output voltage. For the same current, the power MOSFET will have much less voltage drop than the PN-junction voltage drop of an SCR. SCR-based circuits involving the LTM4641 are not presented here. Evaluation of induced or simulated overvoltage events on a demo board (such as DC1543) is recommended to ensure the end result meets the user’s expectations. 

## **Fast Output Overvoltage Comparator Threshold** 

OVPGM is nominally biased by internal circuitry to 666mV, according to a 499kΩ and 1MΩ resistor-divider network internal to the LTM4641 driven from the 1VREF. This pin connects directly to the inverting input of the fast OOV comparator—setting the trip threshold that the control-loop-referred feedback voltage, VFB, would have to exceed to result in CROWBAR becoming logic high. Recall that the control-loop pulse frequency modulates MTOP such that VFB is driven to the lesser of the TRACK/SS pin or the bandgap reference voltage of 600mV. When TRACK/SS (and hence, the output voltage) has been fully ramped up, the 666mV on OVPGM represents an OOV setting 11% above nominal output voltage. To increase the OOV threshold, a resistor can be connected externally from 1VREF to OVPGM; to decrease the OOV threshold, a resistor can be connected externally from 

4641fe 

34 

For more information www.linear.com/LTM4641 

LTM4641 

## **applicaTions inForMaTion—eMi perForMance** 

OVPGM to SGND. Furthermore, the OVPGM trip voltage can be made more accurate than its default setting by paralleling the existing (internal) OVPGM resistor-divider with an external resistor divider comprised of low T.C.R. ±0.1%-tolerance resistors, for example. See Appendix F for details on how to adjust or tighten the fast OOV comparator trip threshold. 

## **The Switching Node: SW Pin** 

The SW pin provides access to the midpoint of the power MOSFETs in LTM4641’s power stage. 

Connecting an optional series RC network from SW to GND can dampen high frequency (~30MHz+) switch node ringing caused by parasitic inductances and capacitances in the switched-current paths. The RC network is called a snubber circuit because it dampens (or “snubs”) the resonance of the parasitics, at the expense of higher power loss. 

To use a snubber, choose first how much power to allocate to the task and how much PCB real estate is available to implement the snubber. For example, if PCB space allows a low inductance 1W resistor to be used—derated conservatively to 600mW (PSNUB)—then the capacitor in the snubber network (CSW) is computed by: 

**==> picture [240 x 214] intentionally omitted <==**

**----- Start of picture text -----**<br>
P<br>C = SNUB<br>SW (30)<br>V • f<br>INH(MAX) [2] SW<br>70<br>COCO<br>60 FEEEEC EEE<br>50<br>FEEEE EEE EN55022<br>40<br>CLASS B<br>SSS LIMIT<br>30<br>i WA,<br>2010 RCOPMTe<br>0<br>–10<br>30 226.2 422.4 618.6 814.8 1010<br>FREQUENCY (MHz)<br>4641 F13<br>SIGNAL AMPLITUDE (dB µV/m)<br>**----- End of picture text -----**<br>


**Figure 13. Radiated Emissions Scan of LTM4641 Producing 5VOUT at 10A, from 12VIN. DC1543 Hardware with No Snubber Network Installed. fSW = 550kHz. CIN(BULK) = 2** × **100μF, CIN(MLCC) = 4** × **10μF X7R + 2** × **4.7μF X7R. Measured in a 10 Meter Chamber. Quasi-Peak Detect Method** 

where VINH(MAX) is the maximum input voltage that the input to the power stage (VINH) will see in the application, and fSW is the DC/DC converter’s full load switching frequency of operation. CSW should be NPO, C0G or X7R-type (or better) material. 

The snubber resistor (RSW) value is then given by: 

**==> picture [240 x 31] intentionally omitted <==**

The snubber resistor should be low ESL and capable of withstanding the pulsed currents present in snubber circuits. A value between 0.7Ω and 4.2Ω is normal. 

EMI performance of LTM4641 (on DC1543) with and without a snubber is compared and contrasted in Figures 13 to 16. In the examples shown, the snubber networks reduce EMI signal amplitude by as much as ~5dB. 

Access to SW is also provided to make it possible to deliberately induce a short circuit between the input of LTM4641’s power stage (VINH) and its switch node—to evaluate, in hardware, the performance of the LTM4641 when a high side MOSFET fault condition is simulated. 

**==> picture [186 x 165] intentionally omitted <==**

**----- Start of picture text -----**<br>
70<br>60<br>50<br>EN55022<br>40<br>CLASS B<br>SEES LIMIT<br>30 SaReSRRHER<br>20 ROL<br>10 ATT<br>0 PEE EEE<br>–10 CEEEEEEEEE<br>30 226.2 422.4 618.6 814.8 1010<br>FREQUENCY (MHz)<br>4641 F13<br>SIGNAL AMPLITUDE (dB µV/m)<br>**----- End of picture text -----**<br>


**Figure 14. Radiated Emissions Scan of LTM4641 Producing 5VOUT at 10A, from 12VIN. DC1543 Hardware with Ad Hoc Snubber Network Installed Directly Between SW Probe Point and GND, CSW = 10nF, RSW = 1Ω (1W-Rated). fSW = 550kHz. CIN(BULK) = 2** × **100μF, CIN(MLCC) = 4** × **10μF X7R + 2** × **4.7μF X7R. Measured in a 10 Meter Chamber. Quasi-Peak Detect Method** 

4641fe 

35 

For more information www.linear.com/LTM4641 

LTM4641 

## **applicaTions inForMaTion—eMi perForMance** 

**==> picture [164 x 166] intentionally omitted <==**

**----- Start of picture text -----**<br>
7060 PTET ETT<br>50 PET TTT<br>4030 SERGRREEEECeres<br>20<br>10 AMIE PEP<br>0 PETE<br>–10 PTET TTTET ETT<br>30 226.2 422.4 618.6 814.8 1010<br>FREQUENCY (MHz)<br>4641 F15<br>SIGNAL AMPLITUDE (dB µV/m)<br>**----- End of picture text -----**<br>


**Figure 15. Radiated Emissions Scan of LTM4641 Producing 2.5VOUT at 10A, from 24VIN. DC1543 Hardware with No Snubber Network Installed. fSW = 335kHz. CIN(BULK) = 2** × **100μF, CIN(MLCC) = 4** × **10μF X7R + 2** × **4.7μF X7R. Measured in a 10 Meter Chamber. Quasi-Peak Detect Method** 

**==> picture [164 x 166] intentionally omitted <==**

**----- Start of picture text -----**<br>
7060 PTET ETT<br>50 PET [TTT]<br>40 ttt<br>30 PEPE|<br>20<br>10 y<br>0 eT<br>–10 P LT ETTETET ET TT<br>30 226.2 422.4 618.6 814.8 1010<br>FREQUENCY (MHz)<br>4641 F16<br>SIGNAL AMPLITUDE (dB µV/m)<br>**----- End of picture text -----**<br>


**Figure 16. Radiated Emissions Scan of LTM4641 Producing 2.5VOUT at 10A, from 24VIN. DC1543 Hardware with Ad Hoc Snubber Network Installed Directly Between SW Probe Point and GND, CSW = 2.2nF, RSW = 2.2Ω (1W Rated). fSW = 335kHz. CIN(BULK) = 2** × **100μF, CIN(MLCC) = 4** × **10μF X7R + 2** × **4.7μF X7R. Measured in a 10 Meter Chamber. Quasi-Peak Detect Method** 

## **applicaTions inForMaTion—MulTiMoDule parallel operaTion** 

For loads that demand more than 10A of load current, multiple LTM4641 devices can be paralleled to provide more output current. See Figures 56 and 66 for examples of four or two LTM4641 operating in parallel to deliver 40A or  20A load current, respectively, while providing robust output overvoltage protection. 

The LTM4641 does not support phase interleaving or clock synchronization, and therefore no ripple-current cancelation effect and no multiplication effect on the output voltage ripple frequency occurs when modules are paralleled. Therefore, it should be anticipated that paralleled applications contain beat frequencies in the output voltage waveform and are contained in the reflected input current. For example, if one module operates freely at 400kHz while its paralleled sibling operates freely at 410kHz, the conducted EMI content will include not only the switching fundamental frequencies—400kHz and 410kHz—but also a beat frequency at the difference of those frequencies, 10kHz. The system designer may be motivated to apply an external LC (or “pi”) filter on the input to each LTM4641 if attenuation of the reflected input currents is desired. 

The LTM4641 device is a current mode controlled device, so paralleled modules demonstrate good current sharing. This helps equilibrate power losses and reduce thermal differences between paralleled modules. 

The following pins should be connected to all corresponding LTM4641s’ pin(s) when paralleling LTM4641 outputs: 

- VOUT 

- GND 

- VINH 

- VINL 

- HYST (to synchronize start-up and shutdown) 

- TRACK/SS 

- COMP (to accomplish current sharing) 

- CROWBAR (to synchronize output overvoltage response) 

- LATCH (to reset all modules after a latchoff event) 

- VING, if MSP is used 

4641fe 

36 

For more information www.linear.com/LTM4641 

LTM4641 

## **applicaTions inForMaTion—MulTiMoDe parallel operaTion** 

- VOSNS[+] , differentially bussed with VOSNS[–] ; use GND shielding 

- VOSNS[–] , differentially bussed with VOSNS[+] ; use GND shielding 

- PGOOD, if used 

Pulling any one module’s RUN pin low will pull all module’s HYST pins low, to cease switching and output voltage regulation. When paralleling LTM4641 outputs, each module should have its own RfSET resistor locally (if needed) to set the on time (IION) consistent with the output voltage setting (cf. Table 1 and Figure 3). Customized UVLO settings, latching and nonlatching input overvoltage thresholds, and output overvoltage thresholds need only be configured on one LTM4641. INTVCC and DRVCC should be connected to each other, separately on each module (see Figures 56 and 66)—or, if powering DRVCC from an auxiliary bias rail, then by applying the technique of Figure 51 to each module. 

If MSP is used, only one VINGP need be connected to the gate of MSP. The routing of MSP’s source pins to the VINH of all modules may be difficult to accomplish in layout without introducing significant loop area; it may be necessary then to use one MSP MOSFET on the input to each LTM4641 power stage for practical routing. Also, the connections of VOSNS[+] and VOSNS[–] to multiple modules can be difficult to shield, in practice, so leaving provision for differential-mode filtering of the remote sense signal (CDM1, CDM2) local to each modules’ remote-sense input pins is advisable. 

Be aware that the loading of the paralleled remote sense amplifiers on the bussed feedback signal alters the equations for setting output voltage as follows. 

When paralleling n modules, for VOUT ≤1.2V, select RSET1A not larger than that given by: 

**==> picture [240 x 34] intentionally omitted <==**

For VOUT > 1.2V, select RSET1A not larger than that given by: 

**==> picture [239 x 26] intentionally omitted <==**

Then, determine RSET2 by: 

**==> picture [240 x 41] intentionally omitted <==**

The output voltage setting can be double-checked by: 

**==> picture [239 x 38] intentionally omitted <==**

The voltage on the VOSNS[+] pins of the modules during regulation become: 

**==> picture [238 x 95] intentionally omitted <==**

In multimodule parallel scenarios, VOSNS– and ∆VGND are still given by Equations 12 and 13, respectively. 

Lastly, be aware that the total charge current on the TRACK/SS net will be n • 1μA. 

4641fe 

37 

For more information www.linear.com/LTM4641 

LTM4641 

## **applicaTions inForMaTion—TherMal consiDeraTions anD ouTpuT currenT DeraTing** 

## **Thermal Considerations and Output Current Derating** 

The thermal resistances reported in the Pin Configuration section of the data sheet are consistent with those parameters defined by JESD51-12 and are intended for use with finite element analysis (FEA) software modeling tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation performed on a µModule package mounted to a hardware test board defined by JESD51-9 (“Test Boards for Area Array Surface Mount Package Thermal Measurements”). The motivation for providing these thermal coefficients is found in JESD 51-12 (“Guidelines for Reporting and Using Electronic Package Thermal Information”). 

Many designers may opt to use laboratory equipment and a test vehicle such as the demo board to predict the µModule regulator’s thermal performance in their application at various electrical and environmental operating conditions to compliment any FEA activities. Without FEA software, the thermal resistances reported in the Pin Configuration section are in-and-of themselves not relevant to providing guidance of thermal performance; instead, the derating curves provided later in this data sheet can be used in a manner that yields insight and guidance pertaining to one’s application-usage, and can be adapted to correlate thermal performance to one’s own application. 

The Pin Configuration section gives four thermal coefficients explicitly defined in JESD 51-12; these coefficients are quoted or paraphrased below: 

- 1 θJA, the thermal resistance from junction to ambient, is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclosure. This environment is sometimes referred to as “still air” although natural convection causes the air to move. This value is determined with the part mounted to a JESD 51-9 defined test board, which does not reflect an actual application or viable operating condition. 

- 2 θJCbottom, the thermal resistance from junction to the bottom of the product case, is determined with all of the component power dissipation flowing through the bottom of the package. In the typical µModule regulator, the bulk of the heat flows out the bottom of the package, but there is always heat flow out into the ambient environment. As a result, this thermal resistance value may be useful for comparing packages but the test conditions don’t generally match the user’s application. 

- 3 θJCtop, the thermal resistance from junction to top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. As the electrical connections of the typical µModule regulator are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. As in the case of θJCbottom, this value may be useful for comparing packages but the test conditions don’t generally match the user’s application. 

- 4 θJB, the thermal resistance from junction to the printed circuit board, is the junction-to-board thermal resistance where almost all of the heat flows through the bottom of the µModule regulator and into the board, and is really the sum of the θJCbottom and the thermal resistance of the bottom of the part through the solder joints and through a portion of the board. The board temperature is measured a specified distance from the package, using a two sided, two layer board. This board is described in JESD 51-9. 

A graphical representation of the aforementioned thermal resistances is given in Figure 17; blue resistances are contained within the µModule regulator, whereas green resistances are external to the µModule package. 

As a practical matter, it should be clear to the reader that no individual or sub-group of the four thermal resistance 

4641fe 

38 

For more information www.linear.com/LTM4641 

LTM4641 

## **applicaTions inForMaTion—TherMal consiDeraTions anD ouTpuT currenT DeraTing** 

parameters defined by JESD 51-12 or provided in the Pin Configuration section replicates or conveys normal operating conditions of a µModule regulator. For example, in normal board-mounted applications, never does 100% of the device’s total power loss (heat) thermally conduct exclusively through the top or exclusively through bottom of the µModule package—as the standard defines for θJCtop and θJCbottom, respectively. In practice, power loss is thermally dissipated in both directions away from the package—granted, in the absence of a heat sink and airflow, a majority of the heat flow is into the board. 

Within the LTM4641, be aware there are multiple power devices and components dissipating power, with a consequence that the thermal resistances relative to different junctions of components or die are not exactly linear with respect to total package power loss. To reconcile this complication without sacrificing modeling simplicity—but also, not ignoring practical realities—an approach has been taken using FEA software modeling along with laboratory testing in a controlled-environment chamber to reasonably define and correlate the thermal resistance values supplied in this data sheet: (1) Initially, FEA software is used to accurately build the mechanical geometry of the LTM4641 and the specified PCB with all of the correct 

material coefficients along with accurate power loss source definitions; (2) this model simulates a software-defined JEDEC environment consistent with JSED 51-9 and JESD 51-12 to predict power loss heat flow and temperature readings at different interfaces that enable the calculation of the JEDEC-defined thermal resistance values; (3) the model and FEA software is used to evaluate the LTM4641 with heat sink and airflow; (4) having solved for and analyzed these thermal resistance values and simulated various operating conditions in the software model, a thorough laboratory evaluation replicates the simulated conditions with thermocouples within a controlled environment chamber while operating the device at the same power loss as that which was simulated. The outcome of this process and due diligence yields the set of derating curves provided in later sections of this data sheet, along with well-correlated JESD51-12-defined θ values provided in the Pin Configuration section of this data sheet. 

The 6V, 3.3V and 1.5V power loss curves in Figures 18, 19 and 20 respectively can be used in coordination with the load current derating curves in Figures 21 to 42 for calculating an approximate θJA thermal resistance for the LTM4641 with various heat sinking and air flow conditions. These thermal resistances represent demonstrated 

**==> picture [396 x 164] intentionally omitted <==**

**----- Start of picture text -----**<br>
JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)<br>JUNCTION-TO-CASE (TOP) CASE (TOP)-TO-AMBIENT<br>RESISTANCE RESISTANCE<br>JUNCTION-TO-BOARD RESISTANCE<br>JUNCTION AMBIENT<br>JUNCTION-TO-CASE CASE (BOTTOM)-TO-BOARD BOARD-TO-AMBIENT<br>(BOTTOM) RESISTANCE RESISTANCE RESISTANCE<br>4641 F17<br>µMODULE DEVICE<br>**----- End of picture text -----**<br>


**Figure 17. Graphical Representation of JESD51-12 Thermal Coefficients** 

4641fe 

39 

For more information www.linear.com/LTM4641 

LTM4641 

## **applicaTions inForMaTion—TherMal consiDeraTions anD ouTpuT currenT DeraTing** 

performance of the LTM4641 on DC1543 hardware; a 4-layer FR4 PCB measuring 96mm × 87mm × 1.6mm using outer and inner copper weights of 2oz and 1oz, respectively. The power loss curves are taken at room temperature, and are increased with multiplicative factors with ambient temperature. These approximate factors are listed in Table 3. (Compute the factor by interpolation, for intermediate temperatures.) The derating curves are plotted with the output current starting at 10A and the ambient temperature at 40°C. The output voltages are 6V, 3.3V and 1.5V. These are chosen to include the lower and higher output voltage ranges for correlating the thermal resistance. Thermal models are derived from several temperature measurements in a controlled temperature chamber along with thermal modeling analysis. The junction temperatures are monitored while ambient temperature is increased with and without air flow, and with and without a heat sink attached with thermally conductive adhesive tape. The BGA heat sinks evaluated in Table 7 (and attached to the LTM4641 with thermally conductive adhesive tape listed in Table 8) yield very comparable performance in laminar airflow despite being visibly different in construction and form factor. The power loss increase with ambient temperature change is factored into the derating curves. The junctions are maintained at 120°C maximum while lowering output current or power while increasing ambient temperature. The decreased output current will decrease the internal module loss as ambient temperature is increased. The monitored junction temperature of 120°C minus the ambient operating temperature specifies how much module temperature rise can be allowed. As an example in Figure 38, the load current is derated to ~8A at ~81°C ambient with no air or heat sink and the power loss for this 36VIN to 1.5VOUT at 

8AOUT condition is ~3.1W. The 3.74W loss is calculated with the ~3.1W room temperature loss from the 36VIN to 1.5VOUT power loss curve at 8A (Figure 20), and the 1.205 multiplying factor at 81°C ambient (interpolating from Table 3). If the 81°C ambient temperature is subtracted from the 120°C junction temperature, then the difference of 39°C divided by 3.74W yields a thermal resistance, θJA, of 10.4°C/W—in good agreement with Table 6. Tables 4, 5 and 6 provide equivalent thermal resistances for 6V, 3.3V and 1.5V outputs with and without air flow and heat sinking. The derived thermal resistances in Tables 4, 5 and 6 for the various conditions can be multiplied by the calculated power loss as a function of ambient temperature to derive temperature rise above ambient, thus maximum junction temperature. Room temperature power loss can be derived from the efficiency curves in the Typical Performance Characteristics section and adjusted with the above ambient temperature multiplicative factors. 

**Table 3. Power Loss Multiplicative Factors vs Ambient Temperature** 

|<br>**Temperature**||
|---|---|
|**AMBIENT TEMPERATURE**|**POWER LOSS MULTIPLICATIVE**<br>**FACTOR**|
|Up to 40°C|1.00|
|50°C|1.05|
|60°C|1.10|
|70°C|1.15|
|80°C|1.20|
|90°C|1.25|
|100°C|1.30|
|110°C|1.35|
|120°C|1.40|



4641fe 

40 

For more information www.linear.com/LTM4641 

LTM4641 

## **applicaTions inForMaTion—TherMal consiDeraTions anD ouTpuT currenT DeraTing** 

**==> picture [520 x 375] intentionally omitted <==**

**----- Start of picture text -----**<br>
8 6 4.5<br>7 4.0<br>5<br>3.5<br>6<br>4 3.0<br>5<br>2.5<br>4 3<br>2.0<br>3<br>2 1.5<br>2 36VIN 1.0 36V IN<br>36VIN 1 24VIN 24VIN<br>1 24VIN 12VIN 0.5 12VIN<br>12VIN 6VIN 6VIN<br>0 0 0<br>0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10<br>OUTPUT CURRENT (A) OUTPUT CURRENT (A) OUTPUT CURRENT (A)<br>4641 F18 4146 F19 4641 F20<br>Figure 18. 6VOUT Power Loss,  Figure 19. 3.3VOUT Power Loss,  Figure 20. 1.5VOUT Power Loss,<br>fSW = 660kHz at Full Load,  fSW = 360kHz at Full Load,  fSW = 315kHz at Full Load,<br>FCB Tied to SGND FCB Tied to SGND FCB Tied to SGND<br>10 10 10<br>9 9 9<br>8 8 8<br>7 7 7<br>6 6 6<br>5 5 5<br>4 4 4<br>3 3 3<br>2 400LFM 2 400LFM 2 400LFM<br>1 200LFM 1 200LFM 1 200LFM<br>0LFM 0LFM 0LFM<br>0 0 0<br>40 50 60 70 80 90 100 110 120 40 50 60 70 80 90 100 110 120 40 50 60 70 80 90 100 110 120<br>AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)<br>4146 F21 4146 F22 4146 F23<br>POWER LOSS (W) POWER LOSS (W) POWER LOSS (W)<br>MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A)<br>**----- End of picture text -----**<br>


**Figure 21. 12VIN to 6VOUT, No Heat Sink, fSW = 660kHz at Full Load** 

**Figure 22. 24VIN to 6VOUT, No Heat Sink, fSW = 660kHz at Full Load** 

**Figure 23. 36VIN to 6VOUT, No Heat Sink, fSW = 660kHz at Full Load** 

**==> picture [520 x 167] intentionally omitted <==**

**----- Start of picture text -----**<br>
10 10 10<br>9 9 9<br>8 8 8<br>7 7 7<br>6 6 6<br>5 5 5<br>4 4 4<br>3 3 3<br>2 400LFM 2 400LFM 2 400LFM<br>1 200LFM 1 200LFM 1 200LFM<br>0LFM 0LFM 0LFM<br>0 0 0<br>40 50 60 70 80 90 100 110 120 40 50 60 70 80 90 100 110 120 40 50 60 70 80 90 100 110 120<br>AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)<br>4146 F24 4146 F25 4146 F26<br>MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A)<br>**----- End of picture text -----**<br>


**Figure 24. 12VIN to 6VOUT with Heat Sink, fSW = 660kHz at Full Load** 

**Figure 25. 24VIN to 6VOUT with Heat Sink, fSW = 660kHz at Full Load** 

**Figure 26. 36VIN to 6VOUT with Heat Sink, fSW = 660kHz at Full Load** 

4641fe 

41 

For more information www.linear.com/LTM4641 

LTM4641 

## **applicaTions inForMaTion—TherMal consiDeraTions anD ouTpuT currenT DeraTing** 

**==> picture [521 x 574] intentionally omitted <==**

**----- Start of picture text -----**<br>
10 10 10<br>9 9 9<br>8 8 8<br>7 7 7<br>6 6 6<br>5 5 5<br>4 4 4<br>3 3 3<br>2 400LFM 2 400LFM 2 400LFM<br>1 200LFM 1 200LFM 1 200LFM<br>0LFM 0LFM 0LFM<br>0 0 0<br>40 50 60 70 80 90 100 110 120 40 50 60 70 80 90 100 110 120 40 50 60 70 80 90 100 110 120<br>AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)<br>4146 F27 4146 F28 4146 F29<br>Figure 27. 6VIN to 3.3VOUT No Heat  Figure 28. 12VIN to 3.3VOUT No Heat  Figure 29. 24VIN to 3.3VOUT No Heat<br>Sink, fSW = 360kHz at Full Load Sink, fSW = 360kHz at Full Load Sink, fSW = 360kHz at Full Load<br>10 10 10<br>9 9 9<br>8 8 8<br>7 7 7<br>6 6 6<br>5 5 5<br>4 4 4<br>3 3 3<br>2 400LFM 2 400LFM 2 400LFM<br>1 200LFM 1 200LFM 1 200LFM<br>0LFM 0LFM 0LFM<br>0 0 0<br>40 50 60 70 80 90 100 110 120 40 50 60 70 80 90 100 110 120 40 50 60 70 80 90 100 110 120<br>AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)<br>4146 F30 4146 F31 4146 F32<br>Figure 30. 36VIN to 3.3VOUT, No Heat  Figure 31. 6VIN to 3.3VOUT, with Heat  Figure 32. 12VIN to 3.3VOUT, with Heat IN to 3.3VOUT, with Heat  to 3.3VOUT, with Heat OUT, with Heat , with Heat<br>Sink, fSW = 360kHz at Full Load Sink, fSW = 360kHz at Full Load Sink, fSW = 360kHz at Full LoadSW = 360kHz at Full Load = 360kHz at Full Load<br>10 10 10<br>9 9 9<br>8 8 8<br>7 7 7<br>6 6 6<br>5 5 5<br>4 4 4<br>3 3 3<br>2 400LFM 2 400LFM 2 400LFM<br>1 200LFM 1 200LFM 1 200LFM<br>0LFM 0LFM 0LFM<br>0 0 0<br>40 50 60 70 80 90 100 110 120 40 50 60 70 80 90 100 110 120 40 50 60 70 80 90 100 110 120<br>AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)<br>4146 F33 4146 F34 4146 F35<br>MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A)<br>MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A)<br>MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A)<br>**----- End of picture text -----**<br>


**Figure 32. 12VIN to 3.3VOUT, with Heat IN to 3.3VOUT, with Heat  to 3.3VOUT, with Heat OUT, with Heat , with Heat Sink, fSW = 360kHz at Full LoadSW = 360kHz at Full Load = 360kHz at Full Load** 

**Figure 33. 24VIN to 3.3VOUT with Heat Sink, fSW = 360kHz at Full Load** 

**Figure 34. 36VIN to 3.3VOUT with Heat Sink, fSW = 360kHz at Full Load** 

**Figure 35. 6VIN to 1.5VOUT No Heat Sink, fSW = 315kHz at Full Load** 

4641fe 

42 

For more information www.linear.com/LTM4641 

LTM4641 

## **applicaTions inForMaTion—TherMal consiDeraTions anD ouTpuT currenT DeraTing** 

**==> picture [523 x 575] intentionally omitted <==**

**----- Start of picture text -----**<br>
10<br>10 10<br>9<br>9 9<br>8<br>8 8<br>7<br>7 7<br>6<br>6 6<br>5<br>5 5<br>4<br>4 4<br>3<br>3 3<br>2 400LFM 2 400LFM 2 400LFM<br>1 200LFM 1 200LFM 1 200LFM0LFM<br>0LFM 0LFM<br>0<br>0 0 40 50 60 70 80 90 100 110 120<br>40 50 60 70 80 90 100 110 120 40 50 60 70 80 90 100 110 120<br>AMBIENT TEMPERATURE (°C)<br>AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)<br>4146 F38<br>4146 F36 4146 F37<br>Figure 38. 36VIN to 1.5VOUT No Heat<br>Figure 36. 12VIN to 1.5VOUT No Heat  Figure 37. 24VIN to 1.5VOUT No Heat  Sink, fSW = 315kHz at Full Load<br>Sink, fSW = 315kHz at Full Load Sink, fSW = 315kHz at Full Load<br>10 10<br>9 9<br>8 8<br>7 7<br>6 6<br>5 5<br>4 4<br>3 3<br>2 400LFM 2 400LFM<br>1 200LFM 1 200LFM<br>0LFM 0LFM<br>0 0<br>40 50 60 70 80 90 100 110 120 40 50 60 70 80 90 100 110 120<br>AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)<br>4146 F39 4146 F40<br>Figure 39. 6VIN to 1.5VOUT, with Heat  Figure 40. 12VIN to 1.5VOUT, with<br>Sink, fSW = 315kHz at Full Load Heat Sink, fSW = 315kHz at Full Load<br>10 10<br>9 9<br>8 8<br>7 7<br>6 6<br>5 5<br>4 4<br>3 3<br>2 400LFM 2 400LFM<br>1 200LFM 1 200LFM<br>0LFM 0LFM<br>0 0<br>40 50 60 70 80 90 100 110 120 40 50 60 70 80 90 100 110 120<br>AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)<br>4146 F41 4146 F42<br>MAXIMUM LOAD CURRENT (A)<br>MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A)<br>MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A)<br>MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A)<br>**----- End of picture text -----**<br>


**Figure 41. 24VIN to 1.5VOUT, with Heat Sink, fSW = 315kHz at Full Load** 

**Figure 42. 36VIN to 1.5VOUT with Heat Sink, fSW = 315kHz at Full Load** 

4641fe 

43 

For more information www.linear.com/LTM4641 

LTM4641 

## **applicaTions inForMaTion—TherMal consiDeraTions anD ouTpuT currenT DeraTing** 

**Table 4. 6V Output, Switching Frequency Nominally 660kHz at Full Load** 

|**DERATING CURVE**|**VIN**|**POWER LOSS CURVE**|**AIRFLOW (LFM)**|**HEAT SINK**|θ**JA (°C/W)**|
|---|---|---|---|---|---|
|Figure 21 to Figure 23|12V, 24V, 36V|Figure 18|0|None|10.1|
|Figure 21 to Figure 23|12V, 24V, 36V|Figure 18|200|None|8.2|
|Figure 21 to Figure 23|12V, 24V, 36V|Figure 18|400|None|6.8|
|Figure 24 to Figure 26|12V, 24V, 36V|Figure 18|0|BGA Heat Sink|8.1|
|Figure 24 to Figure 26|12V, 24V, 36V|Figure 18|200|BGA Heat Sink|6.5|
|Figure 24 to Figure 26|12V, 24V, 36V|Figure 18|400|BGA Heat Sink|5.5|



**Table 5. 3.3V Output, Switching Frequency Nominally 360kHz at Full Load** 

|**DERATING CURVE**|**VIN**|**POWER LOSS CURVE**|**AIRFLOW (LFM)**|**HEAT SINK**|θ**JA (°C/W)**|
|---|---|---|---|---|---|
|Figure 27 to Figure 30|6V, 12V, 24V, 36V|Figure 19|0|None|10.4|
|Figure 27 to Figure 30|6V, 12V, 24V, 36V|Figure 19|200|None|8.4|
|Figure 27 to Figure 30|6V, 12V, 24V, 36V|Figure 19|400|None|7.1|
|Figure 31 to Figure 34|6V, 12V, 24V, 36V|Figure 19|0|BGA Heat Sink|8.6|
|Figure 31 to Figure 34|6V, 12V, 24V, 36V|Figure 19|200|BGA Heat Sink|6.8|
|Figure 31 to Figure 34|6V, 12V, 24V, 36V|Figure 19|400|BGA Heat Sink|5.8|



**Table 6. 1.5V Output, Switching Frequency Nominally 315kHz at Full Load** 

|**DERATING CURVE**|**VIN**|**POWER LOSS CURVE**|**AIRFLOW (LFM)**|**HEAT SINK**|θ**JA (°C/W)**|
|---|---|---|---|---|---|
|Figure 35 to Figure 38|6V, 12V, 24V, 36V|Figure 20|0|None|10.3|
|Figure 35 to Figure 38|6V, 12V, 24V, 36V|Figure 20|200|None|8.4|
|Figure 35 to Figure 38|6V, 12V, 24V, 36V|Figure 20|400|None|7.2|
|Figure 39 to Figure 42|6V, 12V, 24V, 36V|Figure 20|0|BGA Heat Sink|9.0|
|Figure 39 to Figure 42|6V, 12V, 24V, 36V|Figure 20|200|BGA Heat Sink|7.0|
|Figure 39 to Figure 42|6V, 12V, 24V, 36V|Figure 20|400|BGA Heat Sink|5.8|



**Table 7. Heat Sink Vendors (with Thermally Conductive Adhesive Tape Pre-Attached)** 

|**HEAT SINK MANUFACTURER**|**PART NUMBER**|**WEBSITE**|
|---|---|---|
|Wakefield Engineering|LTN20069|www.wakefield.com|
|Aavid Thermalloy|375424B00034G|www.aavid.com|



## **Table 8. Thermally Conductive Adhesive Tape Vendor** 

|**THERMALLY CONDUCTIVE ADHESIVE**<br>**TAPE MANUFACTURER**|**PART NUMBER**|**WEBSITE**|
|---|---|---|
|Chomerics|T411|www.chomerics.com|



4641fe 

44 

For more information www.linear.com/LTM4641 

LTM4641 

## **applicaTions inForMaTion—ouTpuT capaciTance Table** 

**Table 9. Transient Performance (Typical Values) vs Recommended Output Capacitance. Figure 45 and Figure 46 Circuits** 

|||**COUT(MLCC)**|**COUT(MLCC)**|**COUT(MLCC)**|**COUT(MLCC)**|**COUT(MLCC)**|**COUT(MLCC)**|**COUT(MLCC)**|**COUT(MLCC)**|**COUT(BULK)**|**COUT(BULK)**|**COUT(BULK)**|**COUT(BULK)**|**COUT(BULK)**|**COUT(BULK)**|**COUT(BULK)**|**COUT(BULK)**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**VOUT**||**VENDOR**||**PART NUMBER**||||||**VENDOR**|||**PART NUMBER**|||||
|≤ 3.3V||AVX||12106D107MAT2A (100µF, 6.3V, 1210 Case Size)<br>12066D226MAT2A(22µF, 6.3V, 1206 Case Size)||||||Sanyo POSCAP|||6TPE680MI (680µF, 6.3V, 18mΩ ESR, D4 Case Size)|||||
|||Taiyo Yuden||JMK325BJ107MM-T (100µF, 6.3V, 1210 Case Size)<br>JMK316BJ226ML-T(22µF, 6.3V, 1206 Case Size)||||||||||||||
|||TDK||C3225X5R0J107MT (100µF, 6.3V, 1210 Case Size)<br>C3216X5R0J226MT(22µF, 6.3V, 1206 Case Size)||||||||||||||
|> 3.3V||AVX||1206YD226MAT2A(22µF, 16V, 1206 Case Size)||||||Sanyo POSCAP|||10TPF150ML (150µF, 10V, 15mΩ ESR, D3L Case Size)|||||
|||Taiyo Yuden||LMK316BJ476ML-T (47µF, 10V, 1206 Case Size)<br>EMK316BJ226ML-T(22µF, 16V, 1206 Case Size)||||||||||||||
|||TDK||C3216X5R1A476M (47µF, 10V, 1206 Case Size)<br>C3216X5R1C226M(22µF, 16V, 1206 Case Size)||||||||||||||
|||||||||||||||||||
|**VOUT**<br>**(V)**||**VIN(V)**|**RfSET**<br>**(MΩ)**||**RSET1A, **<br>**RSET1B**<br>**(kΩ)**|**RSET2**<br>**(kΩ)**|**CIN**<br>**(CERAMIC)**|**CIN* **<br>**(BULK)**|**COUT2**<br>**(CERAMIC)**||**COUT1**<br>**(BULK)**|**CFFA, **<br>**CFFB**||**LOAD**<br>**STEP**<br>**SLEW**<br>**RATE**<br>**(A/µs)**|**TRANSIENT**<br>**DROOP, 0A**<br>**TO 5A LOAD**<br>**STEP (mV)**|**TRANSIENT,**<br>**PEAK-TO-PEAK,**<br>**0A TO 5A TO 0A**<br>**STEP (mVPK-PK)**|**RECOVERY**<br>**TIME (µs)**|
|0.9|5, 12, 24, 36||0.931||4.12|–|2×10µF|100µF|3×22µF||680µF|–||5|60|130|25|
|0.9|5, 12, 24, 36||0.931||4.12|–|2×10µF|100µF|4×100µF||–|–||5|60|140|25|
|1|5, 12, 24, 36||1.00||5.49|–|2×10µF|100µF|3×22µF||680µF|–||5|65|135|25|
|1|5, 12, 24, 36||1.00||5.49|–|2×10µF|100µF|4×100µF||–|–||5|70|150|25|
|1.2|5, 12, 24, 36||1.13||8.2|–|2×10µF|100µF|3×22µF||680µF|–||5|70|140|25|
|1.2|5, 12, 24, 36||1.13||8.2|–|2×10µF|100µF|4×100µF||–|–||5|80|170|30|
|1.5|5, 12, 24, 36||1.43||8.2|33.2|2×10µF|100µF|3×22µF||680µF|–||5|75|155|30|
|1.5|5, 12, 24, 36||1.43||8.2|33.2|2×10µF|100µF|4×100µF||–|220pF||5|90|190|30|
|1.8|5, 12, 24, 36||2.00||8.2|16.5|2×10µF|100µF|3×22µF||680µF|–||5|80|170|40|
|1.8|5, 12, 24, 36||2.00||8.2|16.5|2×10µF|100µF|3×100µF||–|220pF||5|100|215|30|
|2.5|5, 12, 24, 36||5.76||8.2|7.5|2×10µF|100µF|3×22µF||680µF|–||5|100|230|50|
|2.5|5, 12, 24, 36||5.76||8.2|7.5|2×10µF|100µF|3×100µF||–|220pF||5|140|290|30|
|3.3|5, 12, 24, 36||–||8.2|4.7|2×10µF|100µF|3×22µF||680µF|–||5|140|275|60|
|3.3|5, 12, 24, 36||–||8.2|4.7|2×10µF|100µF|3×100µF||–|100pF||5|200|420|30|
|5|12, 24, 36||–||8.2|2.61|2×10µF|100µF|2×22µF||150µF|220pF||5|220|450|50|
|5|12, 24, 36||–||8.2|2.61|2×10µF|100µF|3×47µF||–|100pF||5|250|570|30|
|6|12, 24, 36||–||8.2|2.05|2×10µF|100µF|2×22µF||150µF|220pF||5|240|500|55|
|6|12, 24, 36||–||8.2|2.05|2×10µF|100µF|3×47µF||–|100pF||5|300|660|30|



*Bulk Capacitance is optional if VIN has very low input impedance. 

4641fe 

45 

For more information www.linear.com/LTM4641 

LTM4641 

## **applicaTions inForMaTion—saFeTy anD layouT guiDance** 

## **Safety Considerations** 

The LTM4641 modules do not provide galvanic isolation from VIN to VOUT. There is no internal fuse. If fusing is required, a slow blow fuse with a rating twice the maximum input current needs to be provided. The LTM4641 supports overcurrent protection and two kinds of overvoltage protection (see the Power Good Indicator and Latching Output Overvoltage Protection section). 

## **Layout Checklist/Example** 

The high integration of LTM4641 makes the PCB board layout very straightforward. To optimize its electrical and thermal performance, some layout considerations are necessary. Figure 43 and Figure 44 show recommended layouts for the circuits shown in Figure 45 and Figure 46, respectively. 

- Refer to the following document for device land pattern and stencil design: http://www.linear.com/docs/40146. 

- The gerber file for demo board DC1543 can be downloaded at http://www.linear.com/demo 

- Use a solid copper GND plane directly underneath the module. This will help form the return path electrical connections to the input source and output load. It will also provide a thermal path for removing heat from the BGA package and minimize junction temperature rise of the LTM4641 for a given application. For consistent ripple and noise from application to application, connect the output GND plane (the one that conducts load side return current back to the module) and the input GND plane (the one that conducts module return current back to the input source) underneath the module, only. 

- Use large PCB copper areas for high current paths, including VINH and VOUT. 

- Place high frequency ceramic input and output capacitors next to the VINH, GND and VOUT pins to minimize high frequency noise. VINH exception: If MSP is used, (1) place MSP as close to the VINH pins of the LTM4641 as possible and (2) bypass the drain of MSP—and _not_ VINH—to GND pins of the LTM4641. Only one or two high frequency MLCCs (COUT(MLCC)) need be placed directly next to the VOUT and GND pins of the LTM4641, to minimize high frequency noise close to the source. 

The majority of COUT(MLCC) should be located close to the load to provide high quality bypassing. 

- To minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers. 

- Do not put vias directly under any pads, unless they are capped or plated over. 

- Use a separated SGND ground copper area for components connecting to signal pins. Components connecting to SGND should be placed as close to the module as possible and routed with minimum trace lengths and trace widths, for best noise immunity. 

- Note that there are two clusters of SGND pins on the module: one, formed by Pins A1-A3, B1-B3, C1-C4 (A1-quadrant); and a second formed by Pins K1, K3, L3, and M1-M3 (M1-quadrant). It is good PCB design practice to provide a copper plane connecting all A1-quadrant SGND pins together and another plane connecting all M1-quadrant SGND pins together. It is _not_ necessary to connect these two clusters of SGND copper planes to each other in the PCB layout, because all SGND pins are electrically connected to each other internal to the module. 

- Do _not_ connect the any SGND pins or SGND plane(s) to the GND plane; the electrical star connection is made internal to the module. 

- For parallel module operation, see the Multimodule Parallel Operation section for a list of interconnecting pins across paralleled modules. Circuit Figures 56 and 66 show four and two LTM4641 devices operating in parallel, respectively. Route signal-level (non-power) nets on an internal layer, with GND planes overlapping signal routes to shield them from noise. It is even more effective to surround module-to-module signal connections on the internal layer containing the signal routes with adjacent GND planes or routes, and periodically “punching-through” GND via connections to GND plane shields on adjacent layers. This practice forms the equivalent of a “coaxial cable” structure within the PCB, and is highly effective at shielding sensitive signals from noise sources. Maintain differential routing of the VOSNS[+] /VOSNS[–] pin pair. 

4641fe 

46 

For more information www.linear.com/LTM4641 

LTM4641 

## **applicaTions inForMaTion—saFeTy anD layouT guiDance** 

- Place all feedback components as close to the module as possible, giving layout priority first to capacitors CFFA, CFFB, CCMA, CCMB and CDM (if used)—followed next by RSET1A, RSET1B and RSET2 (if used). See Figure 5 in the Applications Information section and Figure 64 in Appendix D for more details. Maintain differential routing of the remote-sense lines between the load and the module. Form a “coaxial cable” structure that surrounds the remote-sense lines with GND potential within the PCB, to the extent that layout permits. See 

an example of routing the VOUT/GND remote-sense pin pair in Layer 3 of DC1543. 

- To facilitate stuffing verification, and test and debug activities, consider routing control signals of the LTM4641 with short traces to localized test points, test pads or test vias—as PCB layout space permits. Both in-house and contract manufacturers enjoy gaining electrical access to all non low impedance (≥10Ω) pins of an IC or μModule regulator to improve in-circuit test (ICT) coverage. 

**Figure 43. Recommended PCB Layout, Figure 45 Circuit. View of the LTM4641 from Top of Package** 

**Figure 44. Recommended PCB Layout, Figure 46 Circuit. View of the LTM4641 from Top of Package** 

4641fe 

47 

For more information www.linear.com/LTM4641 

LTM4641 

## **Typical applicaTions** 

**==> picture [453 x 239] intentionally omitted <==**

**----- Start of picture text -----**<br>
VIN<br>4V TO 38V<br>(4.5V START-UP) + CIN(BULK) C10µFIN(MLCC)<br>50V<br>50V<br>×2 VING VINGP VINH SW VOUT<br>VINL VOUT 1.8V<br>RfSET COUT(MLCC) 10A<br>2M 47µF<br>fSET CROWBA R 10V<br>UVLO LATCH ×6<br>H FCBYST VOR B [+] R8.2kSET1A<br>LTM4641 VOSNS [+] LOCAL HIGH<br>INTVDRVCCCC VOSNS [–] R16.4kSET2 R8.2kSET1B LOAD FREQUENCYDECOUPLING<br>IOVRETRY VOR B [–]<br>OVLO TE MP<br>1VR EF<br>OVPG M<br>OTB H<br>R UN PGOO D<br>TRACK/SS TMR COMP SGND GND<br>CSS CTMR 4641 F45<br>4.7nF N/U<br>SGND CONNECTS TO GND INTERNAL TO MODULE. KEEP SGND<br>ROUTES/PLANES SEPARATE FROM GND ON MOTHERBOARD<br>**----- End of picture text -----**<br>


**Figure 45. 4VIN to 38VIN, LTM4641 Basic Configuration, 1.8V Output at 10A** 

**==> picture [460 x 249] intentionally omitted <==**

**----- Start of picture text -----**<br>
4.5V START-UP MSP<br>OPERATION<br>UP TO 38VIN + 100µFCIN(BULK) C10µFIN(MLCC)<br>50V 50V<br>×2<br>VING VINGP VINH SW VOUT<br>VINL VOUT 3.3V<br>CFFA 100µF 10A<br>100pF 6.3V<br>fSET CROWBA R MCB ×3<br>UVLO LATCH<br>H FCBYST VOR B [+] R8.2kSET1A<br>LTM4641 VOSNS [+] LOCAL HIGH<br>INTVDRVCCCC VOSNS [–] R4.7kSET2 R8.2kSET1B LOAD DECOUPLINGFREQUENCY<br>IOVRETRY VOR B [–] CFFB<br>OVLO TE MP 100pF<br>1VR EF<br>OVPG M<br>OTB H<br>R UN PGOO D<br>MCB: NXP PSMN5R0-30YL<br>TRACK/SS TMR COMP SGND GND<br>MSP: NXP PSMN7R0-60YS<br>CSS 4641 F46<br>22nF<br>SGND CONNECTS TO GND INTERNAL TO MODULE. KEEP SGND<br>ROUTES/PLANES SEPARATE FROM GND ON MOTHERBOARD<br>**----- End of picture text -----**<br>


**Figure 46. LTM4641 Delivering 3.3V Output at 10A, and Providing Robust Output Overvoltage Protection from up to 38VIN. Dropout Operation May Occur Below 4.8VIN. See Figure 11 to Implement Custom UVLO Rising/Falling Settings to Avoid Dropout Operation** 

4641fe 

48 

For more information www.linear.com/LTM4641 

LTM4641 

## **Typical applicaTions** 

**==> picture [487 x 548] intentionally omitted <==**

**----- Start of picture text -----**<br>
R1<br>20k<br>4.5V START-UP RT1 When VIN Exceeds ~36V, D1 Ensures MSP Is Operated<br>OPERATION UP TO 28VIN NTC in Its Linear Region and Provides Rudimentary Surge<br>CONTINUOUS, TRANSIENT  Ride-Through Protection for LTM4641.<br>PROTECTED TO 80VIN MSP Optional: RT1, R1, R2, R3.To Enable RT1’s Detection of<br>Thermal Overstress in MSP During Sustained Input Voltage<br>+ 100µFCIN(BULK) CIN(MLCC) Surge Events, Place RT1 in Extremely Close Proximity to<br>100V 10µF100V D1 MSP in PCB Layout. Experimentally Determine the Vaules of R1, R2 and R3 That Yield Desired Overtemperature<br>×2 R28.25k 36V2% Shutdown Inception and Restart Recovery Thresholds Consistent with MSP’s Rated Operating Junction<br>Temperature and Safe Operating Area<br>5V RfSET<br>1M VING VINGP VINH SW VOUT<br>— VINL VOUT 1V<br>D2 Enables Detection pob fSET CROWBA R MCB 100µF6.3V 10A<br>of VIN UVLO Falling UVLO ×4<br>D2 R3 LATC H 5V<br>2.7M HYST VOR B [+] R5.49kSET1A<br>FCB LTM4641 VOSNS [+] LOCAL HIGH<br>VIN OUT RSET1B LOAD FREQUENCY<br>RROV ae SHDN LT [®] GND3010-5 SENSE E v INTVDRVIOVRETRYCCCC VVOSNSTEOR MPB [–][–] i 5.49k Eo DECOUPLING<br>4.7M 1VREF<br>Ss7 OVLO OVPG M MSP and Switching Action Are Temporarily<br>29.4kRBOV Switching Action Is Temporarily Latched Off if  R UN PGOOOTBH D Latched Off When a Module Overtemperature or Output Overvoltage (OOV) Condition is<br>VIN Exceeds 80V; Autonomous  TRACK/SS TMR COMP SGND GND Detected--Additionally, the Crowbar MOSFET MCB<br>Restart Attemps Occur in  is Turned On to Protect the Load Upon OOV Detection.<br>9 Second Intervals When Input  CSS CTMR 7 4641 F47 Autonomous Restart Attempts Occur in 9 Second<br>Voltage Returns Below 80V. Note 1nF 1µF Intervals When Conditions Return to Normal<br>LT3010-5 is Rated for 80V, Absolute  3 o><br>Maximum. See Note 1.<br>© TechClip Available (Click to View)<br>D2: CENTRAL SEMI CMMSH1-100G<br>MCB: NXP PSMN5R0-30YL<br>MSP: NXP PSMN028-100YS SGND CONNECTS TO GND INTERNAL TO MODULE. KEEP SGND<br>RT1: MURATA NCP15WM474J03RC ROUTES/PLANES SEPARATE FROM GND ON MOTHERBOARD<br>Figure 47. LTM4641 Generating 1V Output at 10A, Surge Protected up to 80VIN Transients.<br>Start-Up and Shutdown Waveforms with TMR = INTVCC Shown In Figure 2<br>VIN<br>20V/DIV<br>VINH<br>20V/DIV<br>SE<br>VOUT 20mV/DIV<br>AC-COUPLED<br>VINL/INTVCC/DRVCC/LATCH<br>5V/DIV<br>2ms/DIV 4641 F48<br>**----- End of picture text -----**<br>


**Figure 48. Oscilloscope Snap-Shot of Figure 47 Circuit Riding Through 80VIN Transient While Delivering 1VOUT at 10A to the Load** 

4641fe 

49 

For more information www.linear.com/LTM4641 

LTM4641 

## **Typical applicaTions** 

**==> picture [509 x 252] intentionally omitted <==**

**----- Start of picture text -----**<br>
3.3VIN NOMINAL MSP<br>2.3VIN3V FALLING SHUTDOWNIN RISING START-UP + CIN(MLCC)<br>CIN(BULK) 47µF<br>6.3V<br>×2<br>5V VING VINGP VINH SW VOUT<br>LOW POWER BIAS VINL VOUT 0.9V<br><50mA PEAK RTUV R360kfSET 100µF6.3V 10A<br>150k fSET CROWBA R MCB ×4<br>UVLO LATCH<br>30.9kRBUV RHYST1M VOR B [+] R4.12kSET1A<br>= HYSTFCB LTM4641 VOSNS [+] = RSET1B LOAD LOCAL HIGHFREQUENCY<br>INTVCC VOSNS [–] 4.12k DECOUPLING<br>ry DRVCC VOR B [–] os<br>TE MP<br>IOVRETRY<br>OVLO OVPG1VR EFM MCB: NXP PH2625L<br>MSP: NXP PSMN013-30LL<br>OTB H<br>100k<br>R UN PGOOD<br>TRACK/SS TMR COMP SGND GND<br>CSS<br>4.7nF<br>4641 F49<br>SGND CONNECTS TO GND INTERNAL TO MODULE, KEEP SGND<br>ROUTES/PLANES SEPARATE FROM GND ON MOTHERBOARD<br>**----- End of picture text -----**<br>


**Figure 49. LTM4641 Producing 0.9VOUT at 10A, from 3.3VIN, and Providing Advanced Output Overvoltage Protection. VINL, INTVCC, and DRVCC Biased from a Low Power Auxiliary 5V Rail** 

**==> picture [204 x 110] intentionally omitted <==**

**----- Start of picture text -----**<br>
VIN<br>1V/DIV<br>VOUT<br>1V/DIV<br>HYST<br>5V/DIV<br>PGOOD<br>5V/DIV =<br>4ms/DIV 4641 F50<br>**----- End of picture text -----**<br>


**Figure 50. Oscilloscope Snap-Shot of Figure 49 Circuit, 2Ω Load on VOUT. 3.3VIN Applied Briefly to Highlight UVLO Rising and Falling Thresholds** 

4641fe 

50 

For more information www.linear.com/LTM4641 

LTM4641 

## **Typical applicaTions** 

VAUX LDO Losses in the LTM4641 Can Be Greatly Reduced When an Auxilliary ~5V to 6V Source (VDrive DRVCC Through a Schottky Diode as Shown (D1c). When LTM4641 Is Configured to Produce ~5VAUX) Is Available toOUT to 6VOUT, its Output Can Be VAUX. Provide a Current Path to VINL from VIN and INTVCC/DRVCC Whenever Overdriving INTVCC/DRVCC with VAUX–Accomplished Here with D1a and D1b 

**==> picture [549 x 190] intentionally omitted <==**

**----- Start of picture text -----**<br>
VIN<br>8.5V TO 38V<br>(10V START-UP) + CIN(MLCC)<br>CIN(BULK) 10µF<br>= | R294kTUVD1 ce, ab c C0.1µF  F VINL50V50V×2 UVLOVfSET I NL e VING VINGP VINH SW CROWBALATCHVOUT R = C150µF10VOUT(BULK) 47µF10V×C2OUT(MLCC) ~5VTO 6VUP TO 10A OUTOUT<br>R15.8kBUV RHYST1M VOR B [+] R8.2kSET1A<br>HYST VOSNS [+]<br>D2 FCB LTM4641 R~2.05k TO 2.61kSET2 R8.2kSET1B LOAD<br>INTVCC VOSNS [–]<br>DRVCC VOR B [–]<br>a> 2.2µFCDRVCC V = IOVRETRYOVLO OVPG1VTEOTB MP R EFMH<br>D1, D2: CENTRAL SEMI CMKSH2-4LR R UN PGOO D<br>             SOT-363 PACKAGE<br>TRACK/SS TMR COMP SGND GND 4641 F51<br>CSS<br>47nF<br>SGND CONNECTS TO GND INTERNAL TO MODULE, KEEP SGND<br>TF ROUTES/PLANES SEPARATE FROM GND ON MOTHERBOARD V —<br>**----- End of picture text -----**<br>


**Figure 51. Over-Driving INTVCC/DRVCC to Reduce VINL-to-INTVCC Linear Regulator Losses (cf. Figures 52 to 54)** 

**Figure 52. Thermal Image of U1 from Figure 51 Circuit. Delivering 5VOUT at 10A from 36VIN, with INTVCC Connected to DRVCC and D1c = Open and D2 = Open. TA = 25°C, Bench Testing, No Airflow** 

**Figure 54. Thermal Image of U1 from Figure 51 Circuit. Delivering 5VOUT at 10A from 36VIN, with 5VOUT Feeding INTVCC/ DRVCC Through D1c Diode. TA = 25°C, Bench Testing, No Airflow** 

**Figure 53. Thermal Image of U1 from Figure 51 Circuit. Delivering 6VOUT at 10A from 36VIN, with INTVCC Connected to DRVCC and D1c = Open and D2 = Open. TA = 25°C, Bench Testing, No Airflow** 

**Figure 55. Thermal Image of U1 from Figure 51 Circuit. Delivering 6VOUT at 10A from 36VIN, with 6VOUT Feeding INTVCC/ DRVCC Through D1c Diode. TA = 25°C, Bench Testing, No Airflow** 

4641fe 

51 

For more information www.linear.com/LTM4641 

LTM4641 

## **Typical applicaTions** 

**==> picture [374 x 606] intentionally omitted <==**

**----- Start of picture text -----**<br>
4.5VIN START-UP<br>OPERATION UP TO 38V<br>AND DOWN TO 4V MSP<br>CIN(BULK) CIN(MLCC)<br>100µF 10µF<br>50V 50V<br>×2 ×4<br>VING VINGP VINH SW VOUT<br>R750kfSET1 VfSETINL CROWBAVOUT R MCB 100pFCFF1 C100µFMLCC(OUT)1V40A<br>UVLO LATCH 6.3V<br>HYSTFCB VOR B [+] R1.37kSET1A ×12<br>1 INTVDRVCCCC LTM4641U1 VVOSNSOSNS [+][–] C10pFDM1 R1.37kSET1B LOAD LOCAL HIGHFREQUENCYDECOUPLING<br>IOVRETRYOVLO VTEOR MPB [–] 100pFCFF2<br>1VR EF<br>1 OVPG M<br>RUN ENABLE OTBH<br>R UN PGOO D 1<br>TRACK/SS TMR COMP SGND GND<br>TO SYSTEM µP(OPTIONAL) FAULT INDICATOR 22nFCSS CTMR1N/U 1<br>1 1<br>LATCHOFF RESET<br>PULL LATCH NORMALLY LOW FOR<br>LATCHOFF RESPONSE TO OUTPUTOVERVOLTAGE AND OVER- VING VINGP VINH SW<br>TEMPERATURE EVENTS. PULL VINL VO UT<br>LATCH HIGH TO RESTART 1V OUTPUT RfSET2<br>750k CROWBA R<br>ALTERNATIVELY, CONNECT TO INTVCTMR2, CCCTMR3 AND INSTALL C AND CTMR4 TMR1TO SET LATCH, UVLOHYSTFCBfSET LATCHVOR B [+]<br>1V OUTPUT FOR TIMEDAUTONOMOUS RESTART AFTERFAULT SHUTDOWN EVENTSMCB: NXP PSMN5R0-30YL 2 INTVDRVCCCC LTM4641U2 VVOSNSOSNS [+][–] C10pFDM2<br>MSP: NXP PSMN3R0-60BS IOVRETRY VOR B [–]<br>OVLO TE MP<br>1VR EF<br>2 OVPG M<br>OTBH<br>R UN PGOO D 2<br>TRACK/SS TMR COMP SGND GND<br>CTMR2N/U 2<br>2<br>VING VINGP VINH SW<br>VINL VO UT<br>RfSET3<br>750k CROWBA R<br>fSET<br>UVLO LATCH<br>HYSTFCB VOR B [+]<br>3 INTVDRVCCCC LTM4641U3 VVOSNSOSNS [+][–] C10pFDM3<br>IOVRETRY VOR B [–]<br>OVLO TE MP<br>1VR EF<br>3 OVPG M<br>OTBH<br>R UN PGOO D 3<br>TRACK/SS TMR COMP SGND GND<br>CTMR3N/U 3<br>3<br>VING VINGP VINH SW<br>VINL VOUT<br>RfSET4<br>750k CROWBAR<br>fSET<br>UVLO LATCH<br>HYSTFCB VOR B [+]<br>4 INTVDRVCCCC LTM4641U4 VVOSNSOSNS [+][–] C10pFDM4<br>IOVRETRY VOR B [–]<br>OVLO TE MP<br>1VR EF<br>4 OVPG M<br>OTBH<br>R UN PGOO D 4<br>TRACK/SS TMR COMP SGND GND<br>CTMR4N/U 4<br>4 4641 F56<br>U1, U2, U3 AND U4 SGND (    1,     2,     3,    4) CONNECT TO GND INTERNAL TO THEIR RESPECTIVE MODULES. KEEP MODULE<br>SGND ROUTES/PLANES SEPARATE FROM OTHER MODULES AND FROM GND ON MOTHERBOARD<br>**----- End of picture text -----**<br>


**Figure 56: 1V, 40A Fault-Protected Load Powered by Four Parallel LTM4641—from Up to 38VIN. cf. Figure 57** 

4641fe 

52 

For more information www.linear.com/LTM4641 

LTM4641 

## **Typical applicaTions** 

**==> picture [490 x 474] intentionally omitted <==**

**----- Start of picture text -----**<br>
12<br>10<br>8<br>6<br>4<br>2<br>U1 OUTPUT CURRENT<br>U2 OUTPUT CURRENT<br>0<br>U3 OUTPUT CURRENT<br>U4 OUTPUT CURRENT<br>–2<br>0 8 16 24 32 40<br>TOTAL OUTPUT CURRENT (A)<br>4641 F57<br> Figure 57: Current-Sharing Performance of Four Paralleled LTM4641. Figure 56 Circuit, Operating at 28VIN<br>OPERATION FOR MORE INFORMATION ABOUT CONFIGURING STEP-DOWN BUCK<br>4.5V START-UPUP TO 32.8VIN + CIN(BULK) C10µFIN(MLCC) CONVERTERS AS BUCK-BOOST CONVERTERS, FOR GENERATING NEGATIVE VOUT, SEE http://www.linear.com/docs/39881<br>50V<br>50V VING VINGP VINH SW<br>×4<br>VINL VOUT<br>CROWBA R<br>f S ET<br>UVLO LATCH<br>H FCBYST VOR B [+] R8.2kSET1A<br>VOSNS [+]<br>INTVCC LTM4641U1 R2.46kSET2 R8.2kSET1B LOAD LOCAL HIGHFREQUENCYDECOUPLING D1<br>DRVCC VOSNS [–]<br>IOVRETRY VOR B [–]<br>OVLO TE MP<br>1VR EF<br>OVPG M<br>OTB H<br>R UN PGOOD<br>100k TRACK/SS TMR COMP SGND GND<br>CSS COUT(MLCC)<br>10nF 47µF<br>10V<br>×4 VOUT<br>–5.2V AT<br>D1: CENTRAL SEMI CMPSH1-4LE SGND CONNECTS TO GND INTERNAL TO MODULE, KEEP SGND UP TO 10A<br>ROUTES/PLANES SEPARATE FROM GND ON MOTHERBOARD 4641 F58<br>MODULE OUTPUT CURRENT (A)<br>**----- End of picture text -----**<br>


**Figure 58. Negative Output Application. Delivering –5.2VOUT at Up to 10A, from Up to 32.8VIN. cf. Figure 59** 

4641fe 

53 

For more information www.linear.com/LTM4641 

LTM4641 

## **Typical applicaTions** 

**==> picture [277 x 131] intentionally omitted <==**

**----- Start of picture text -----**<br>
VIN 10V/DIV<br>HYST 2V/DIV<br>ta uitacans PGOOD 2V/DIV<br>[p] | [i] * VOUT 2V/DIV<br>20ms/DIV 4641 F59<br>Figure 59. Pulsed Application of VIN. Figure 58 Circuit with 500Ω Load.<br>*Ultralow VF of D1 Minimizes VOUT Overshoot Upon Energization<br>**----- End of picture text -----**<br>


**==> picture [509 x 332] intentionally omitted <==**

**----- Start of picture text -----**<br>
MSP<br>4.5V < VIN < 15V + CIN(BULK) CIN(MLCC)<br>100µF 22µF<br>25V 25V<br>×2<br>VING VINGP VINH SW VOUT<br>VINL VOUT 1.2V NOMINAL<br>RfSET UP TO 10A OUTPUT<br>1.13M CR OWBAR MCB 100µF<br>fSET LATCHOFF 6.3V<br>FAULT INDICATORADDITIONAL TE UVLO H FCBYST LATCHVOR B [+] RESET R8.2kSET1A Y ×4<br>INTVCC LTM4641* VOSNS [+] R8.2kSET1B LOAD LOCAL HIGHFREQUENCYDECOUPLING<br>DRVCC VOSNS [–]<br>IOVRETRY VOR B [–]<br>OVLO TE MP R30<br>1VR EF 35.7k MSP: NXP PSMN017-30LL<br>OVPG M MCB: NXP PSMN5R0-30YL<br>VPWR VIN_SNS OTB H<br>3.3V [†] VDD33 BE. VOUT _ EN0 RU N PGOO D Tue<br>TO UPSTREAM TRACK/SS TMR COMP SGND GND<br>SYSTEM ENABLE VIN_EN<br>CSS<br>SDA LTC2978** 4.7nF<br>PMBus SCL<br>INTERFACE ALERT VDACPO<br>CONTROL0 VSENSEPO ry L .<br>WRITE PROTECT WP VSENSEMO<br>TO/FROM VDACMO *LTM4641 SGND CONNECTS TO GND INTERNAL TO MODULE.<br>LTC2978sOTHER FAULTOOSHARE_CLK WDI/PWRGDRESET WATCHDOG TIMER INTERRUPTTO µP RESET INPUT **ONLY ONE OF EIGHT LTC2978 CHANNELS SHOWN. LTC2978 PULL-UPS,KEEP SGND ROUTES/PLANES SEPARATE FROM GND ON MOTHERBOARD<br>BYPASSING COMPONENTS, AND SOME PINS NOT SHOWN. FOR DETAILS<br>| | GND ASELO ASEL1 OF LTC2978 IMPLEMENTATION, SEE LTC2978 DATA SHEET<br>†LTC2978 MAY BE POWERED FROM EITHER AN EXTERNAL 3.3V<br>SUPPLY OR THE SYSTEM BUS<br>Figure 60. Fault-Protected Load with Power Supply Management. LTM4641’s Fast Output Overvoltage Latchoff Trip<br>Threshold Remains Consistently 11% Above LTC2978-Commanded Target VOUT, Even as VOUT is Margined Via I [2] C<br>**----- End of picture text -----**<br>


4641fe 

54 

For more information www.linear.com/LTM4641 

LTM4641 

## **Typical applicaTions** 

**==> picture [172 x 89] intentionally omitted <==**

**----- Start of picture text -----**<br>
VOUT<br>200mV/DIV —T pt eei}yt t ey<br>Jip | ee<br>VDACPO<br>500mV/DIV Sere |<br>SDA, SCL<br>a|e<br>2V/DIV<br>a<br>20ms/DIV 4641 F61a<br>**----- End of picture text -----**<br>


**(61a) PMBus OPERATION (Reg. 0x01): 0x80** → **0xA8 (Margin High)** 

**==> picture [114 x 89] intentionally omitted <==**

**----- Start of picture text -----**<br>
VOUT<br>eerrryt te 200mV/DIV<br>VDACPO<br>2a 500mV/DIV<br>SDA, SCL<br>2V/DIV<br> CECee<br>20ms/DIV 4641 F61b<br>**----- End of picture text -----**<br>


**(61b) PMBus OPERATION (Reg. 0x01): 0xA8** → **0x80 (Margin Off)** 

**==> picture [476 x 89] intentionally omitted <==**

**----- Start of picture text -----**<br>
VOUT VOUT<br>200mV/DIV —T pt ee yt te — T———pt ee yt|,te 200mV/DIV<br>VDACPO VDACPO<br>500mV/DIV Seer | ft |) 500mV/DIV<br>SDA, SCL SDA, SCL<br>2V/DIV 2V/DIV<br>=ee TTT a | er<br>20ms/DIV 4641 F61c = i tri 20ms/DIV ttt tl 4641 F61d<br>**----- End of picture text -----**<br>


**(61c) PMBus OPERATION (Reg. 0x01): 0x80** → **0x98 (Margin Low)** 

**(61d) PMBus OPERATION (Reg. 0x01): 0x98** → **0x80 (Margin Off)** 

**Figure 61. LTM4641’s VOUT Margined High/Low by LTC2978 Via I[2] C Commands. Figure 60 Circuit. 12VIN. VOUT_COMMAND (0x21) = 1.20V, VOUT_MARGIN_HIGH (0x25) = 1.32V, VOUT_MARGIN_LOW (0x26) = 1.08V** 

4641fe 

55 

For more information www.linear.com/LTM4641 

LTM4641 

## **appenDices** 

## **Appendix A. Functional Block Diagram and Features Quick Reference Guide** 

**==> picture [409 x 604] intentionally omitted <==**

**----- Start of picture text -----**<br>
VIN 4V TO 38V (4.5V START-UP) VOUT 0.6V TO 6V UP TO 10A<br> ≤ 3V,<br>OUT <br>CIN(BULK) 4641 F62 SET1A SET2<br>+ COUT(MLCC) 2•R +R  ≤ 1.2V<br>On-Time and Switching Frequency Adjustment REQUIRED for V Rail Tracking Applications and When  ≠ VVINHINL CIN(MLCC) Optional Series Pass Electronic “Circuit Breaker”MSPN-Ch Protection MOSFET ) Charge Pump and10V Bias (VGS Discharge Path for Optional External Series Pass N-Ch FET High Current Path: Input to SMPS DC/DC Converter Stage Optional Power RCRSnubber for ReducedSW EMI + COUT(BULK) Optional Output Protection Crowbar N-ChMCBLogic-Level MOSFET RSET1B RSET2 RSET1A nRSET1A1 0.6VV+ =OUT8.2kΩ Use R ≤ 8.2k = RSET1SET1A  Required for VR > 1.2VOUTSET2  Not Necessary for VROUTSET2 n = number of modules operaing in parallel (See Figure 66 for example of n = 2 and Figure 56  for example of n = 4.)<br>RfSET CSW IOUT<br>VINL VING VINGP VINH SW VOUT GND SGND VORB– VOSNS– OSNS+V ORB+V<br>CROWBAR<br>2.2µF<br>1.3M Readback Pins<br>Low Current Path: Power<br>Control and Logic Bias Input<br>1.5M<br>15V 10µF 10k<br>ZENER  Pull-Down<br>0.1µF MBOT To VING 8.2k 8.2k 8.2k<br> Turn-on Charge PumpVING And Fault/Shutdown Discharge Circuitry MTOP 0.8µH OOV * 10nF – * +<br>+ – 100pF 8.2k<br>ION Comparator Differential Amplifier Differential Sense Feedback Path with Redundant<br>Remote Sense<br>Fast Output Overvoltage<br>47pF<br>POWER CONTROL CONSTANT ON-TIME REF )FB 1k<br>VALLEY MODE SYNCHRONOUS TO E/A (V<br>ENABLE SWITCHING ACTION BUCK CONTROLLER 600mV<br>CC 10k<br>INTV<br>HYST Q<br>M RST *<br>* SETQ * RST QSET * RST SET<br>POR/Timeout Circuit Output<br>IUV COMP<br>* IOVR * IOV * OT * DRUV * POR/Timeout INTERNAL<br>+ – + – + – + – + – Delay Timer Circuit<br>0.5V 499k 10k OSC* 4µF /SGND RAILSCC<br>1M 66.5k NOM<br>REF*<br>3.48k 12.1k NTC 499k 666mV 1M<br>REF<br>1V CC CC REF PGM<br>UVLO HYST IOVRETRY OVLO TEMP OTBH TMR LATCH FCB COMP DRV INTV PGOOD SS/TRACK 1V OV RUN<br>*OSC, REF, COMPARATORS, OP AMPS AND DIGITAL GATES SHOWN   OPERATE FROM INTV SGND CONNECTS TO GND INTERNAL TO MODULE, KEEP SGND ROUTES/PLANES SEPARATE FROM GND ON MOTHERBOARD<br>HYST<br>R<br>VIN RTUV RBUV (OT) Protection Restart  Efficiency CSS RTOVPGM COVPGM Nominal) Output Enable Pin >2V or Floating = On <0.8V = Off<br>VIN RTOV RMOV RBOV Analog Temperature Output Indicator and Overtemperature Programmable OT Shutdown Behavior: Latchoff vs Hysteretic Input and Output  OV and OT Latch Reset  Optional Pulse-Skipping Operation for Light Load FET Driver Bias Input CC INL Recommended  Soft-Start or Rail Tracking  RBOVPGM Optional Adjustment of Output Overvoltage Threshold (Default Internal Setting: 11% Above<br>CTMR<br>Thresholds  Internal Control 5.3V Internal V LDO Off of V<br> of Nonlatching Loop Compensation Output Voltage<br>Optional Programming of Input Undervoltage Lockout and Hystersis Optional Programming and Latching Input  Overvoltage (OV) Optional Programmable Power-On Reset and Timeout Delay Time Power Good Indicator<br>**----- End of picture text -----**<br>


4641fe 

56 

For more information www.linear.com/LTM4641 

LTM4641 

## **appenDices** 

**==> picture [419 x 636] intentionally omitted <==**

**----- Start of picture text -----**<br>
Appendix B. Start-Up/Shutdown State Diagram<br>)TH )TH<br>) , ~0.5V )<br> < UVOV), ~0.5VULVOTHTH  > UVOV), ~0.5VIOVRETRYTHTH ), ~3.9V < DRVCC(UVLO_RISING)DRVCCTH  < OT), ~514mVTH(RECOVER)THTEMP  < UVOV), ~0.5VOVLOTHTH ), ~1.5V < VCROWBAR(TH)CROWBARTH  > OT), ~514mVTH(RECOVER)THTEMP  > UVOV), ~0.5VUVLOTHTH  < UVOV), ~0.5V AND VOVLOTHTHTH ), ~1.5V < VCROWBAR(TH)CROWBARTH  > OT), ~514mVTH(RECOVER)THTEMP ), ~4.05VTH LTM4641 VERIFICATION OF TIMEOUT PERIOD EXPIRATION:  HOUSEKEEPING CIRCUITRY HOLDS HYST LOW  IS ON) UNTIL AND (MHYST UNLESS THE UVLO/IOVRETRY/ OVLO/CROWBAR/TEMP/DRVCC MONITOR OUTPUTS REMAIN CLEAR FOR THE FULL DURATION OF THE TIMEOUT PERIOD, AS SET  ); POWER BY TMR PIN (CTMR  IS DISCHARGEDSTAGE IS OFF; VING MONITOR CC  4641 F63  OF THE FOLLOWING NONLATCHING CONDITONS APPEAR:  < UVOV, ~0.5VUVLOTHTH  > UVOVIOVRETRYTH  TOO LOW (V, ~3.35V < DRVCC(UVLO_FALLING)DRVCCTH  < OT, ~438mVTH(INCEPTION)TEMP LATCHOFF FAULTS ARE PRESENT:  < UVOV), ~0.5VOVLOTHTH ), ~1.5V < VCROWBAR(TH)CROWBARTH  > OT), ~438mVTH(INCEPTION)THTEMP<br>CC(UVLO_RISING) CC<br> < UVOV<br>)TH  OF THE FOLLOWING NONLATCHING CONDITONS APPEAR:  TOO LOW (VCC NO  LATCHOFF FAULTS ARE PRESENT:  OF THE FOLLOWING FAULT FREE CONDITIONS IOVRETRY  ABOVE ITS UVLOCC  > DRVDRVCC INTVCC > 2V, NOM; AND ANY 1. CUSTOM UVLO INPUT TOO LOW (V 2. NONLATCHING INPUT OVERVOLTAGE (V 3. DRV 4. NONLATCHING OVERTEMPERATURE     (OTBH = OPEN CIRCUIT AND V AND NO  1. INPUT VOLTAGE O.K. (V 2. CROWBAR O.K. (V 3. TEMPERATURE O.K.     (OTBH = LOW AND V<br>INTVCC > 2V, NOM; AND ANY 1. CUSTOM UVLO INPUT TOO LOW (V 2. NONLATCHING INPUT OVERVOLTAGE (V 3. DRV 4. NONLATCHING OVERTEMPERATURE     (OTBH = OPEN CIRCUIT AND V AND 1. INPUT VOLTAGE O.K. (V 2. CROWBAR O.K. (V 3. TEMPERATURE O.K.     (OTBH = LOW AND V INTVCC > 2V, NOM; AND ALL ARE PRESENT (OR RECENTLY APPEARED, EXITING LATCHOFF): 1. CUSTOM UVLO INPUT O.K. (V 2. NO INPUT OVERVOLTAGE(S)     (V 3. CROWBAR INACTIVE (V 4. TEMPERATURE O.K. (V 5. DRV     (V INTVCC < 2V, NOM UVLO/IOVRETRY/OVLO/CROWBAR/TEMP/DRV OUTPUTS HAVE REMAINED CLEAR FOR THE FULL DURATION  OF THE TIMEOUT PERIOD ;<br>, ~514mV<br>= HIGH  IS NOM  IS OFF);<br>LATCH  > 2V, NOM  AND  CC , ~0.5V<)TH ), ~1.5VTH  > OTTH(RECOVER)TEMP LTM4641 HOUSEKEEPING ALIVE AND INHIBITING SWITCHING ACTION: HYST IS PULLED LOW  IS ON); POWER(MHYST STAGE IS OFF; VING DISCHARGED  > 2V, NOM  ), ~0.5VTHTH ), ~1.5VTH ), ~514mVTH ), ~0.5VTH )TH ) TH LTM4641 PRIMED TO REGULATE:  WAITING ONLY FOR RUN PIN TO TRANSISTION HIGH AND  TO EXCEED 3.6VINTVCC SWITCHING ACTION NOT INHIBITED BY HOUSEKEEPING CIRCUITRY (MHYST POWER STAGE IS OFF;  IS DISCHARGEDVING<br> < UVOVOVLO  < VCROWBAR(TH)  IS ON)  CC  < UVOVOVLO  < VCROWBAR(TH)  > OTTH(RECOVER)  > UVOVTH , ~1.5V , ~514mV<br>CROWBAR HYST CROWBAR TEMP OVLO  > VCROWBAR(TH) TH(RECOVER)<br>AND INTVCC < 2V, NOM  TOGGLES FROM LOGIC LOW   < OT )<br>LATCHOFF IS CLEARED WHEN INTV ALL LATCHOFF FAULT-MONITOR OUTPUTS REMAIN OPERATIONALLY  AND  VALID FOR THE FULL DURATION OF THE TIMEOUT PERIOD: 1. INPUT VOLTAGE O.K. (V 2. CROWBAR O.K. (V 3. TEMPERATURE O.K. (OTBH = LOW AND V )TMR = LOW LATCHOFF IS CLEARED WHEN INTV LATCH AND TO HIGH AND NO LATCHOFF FAULTS ARE PRESENT: 1. INPUT VOLTAGE O.K. (V 2. CROWBAR O.K. (V 3. TEMPERATURE O.K.     (OTBH = LOW AND V CROWBAR TEMP INTVCC < 2V, NOM , MIN)—TH )TH )TH , ~1.5VTH )TH<br>INTVCC > 2V, NOM LATCH  TIMEOUT PERIOD BECOMES RESET  IS  LATCHOFF FAULTS ARE PRESENT: , ~0.5VTH , ~0.5VTH , ~514mV )<br>ING TH<br>CROWBAR(TH)<br>INTVCC > 2V, NOM AND ANY 1. LATCHOFF INPUT OVERVOLTAGE (V 2. CROWBAR ACTIVE (V 3. LATCHOFF OVERTEMPERATURE     (OTBH = LOW AND V  > UVOV  < UVOV  < V TH(RECOVER) , ~3.35V<br>INTVCC < 2V, NOM LTM4641 LATCHOFF CONDITION DETECTED:  HYST IS LATCHED LOW  IS ON); POWER(MHYST STAGE IS OFF; V DISCHARGED  RUN = LOW (0.8V AND AND ADDITIONALLY,  UVLO  AND VOVLO CROWBAR  > OTTEMP<br>LTM4641 TIMEOUT DELAY IMPOSED DURING LATCHOFF: HOUSEKEEPING CIRCUITRY HOLDS HYST LOW (M UNTIL AND UNLESS ALL LATCHOFF FAULT-MONITOR OUTPUTS  REMAIN CLEAR FOR THE FULL DURATION OF THE TIMEOUT  PERIOD, AS SET BY TMR PIN (C = LOW  OF THE FOLLOWING FAULT FREE  TH<br>CC(UVLO_FALLING)<br>)TH )TH INTVCC > 2V, NOMLATCH  AND )  > 3.2V NOM CC  < 3.2V, NOM— CC  < UVOV  ABOVE ITS UVLO  > DRV<br>) TH )  INTV CC<br>TH , ~1.5V , ~514mV )TH )TH , ~1.5V TH EITHER OR  2V < INTV IN EITHER CASE, ALL CONDITIONS EXIST: 1. CUSTOM UVLO INPUT O.K. (V 2. NO INPUT OVERVOLTAGE(S)     (VIOVRETRY 3. CROWBAR INACTIVE (V 4. TEMPERATURE O.K. (V 5. DRV     (VDRVCC<br>, ~0.5V<br>LATCH = HIGH AND  LATCHOFF FAULT IS PRESENT:  > UVOVOVLOTH  > VCROWBAR(TH)CROWBAR  < OTTH(RECOVER)TEMP INTVCC < 2V, NOM  > UVOV), ~0.5VOVLOTHTH ), ~1.5V > VCROWBAR(TH)TH ) , ~438mVTH(INCEPTION)TH  > UVOV, ~0.5VUVLOTH  < UVOV, ~0.5V AND VOVLOTHTH  < VCROWBAR(TH)CROWBAR  > OT, ~514mVTH(RECOVER)TEMP ), ~4.05VCC(UVLO_RISING)TH , MAX)  (2VTH ), ~0.5VTHTH ), ~0.5VTHTH ), ~1.5VTH ), ~438mVTH )TH<br> > 2V, NOM INTVCC AND ANY 1. INPUT OVERVOLTAGE (V 2. CROWBAR ACTIVE (V 3. LATCHOFF OVERTEMPERATURE     (OTBH = LOW AND V INTVCC > 2V, NOM CROWBAR  < OTTEMP INTVCC > 3.9V, NOM  OF THE FOLLOWING  AND ALL FAULT FREE CONDITIONS ARE PRESENT: 1. CUSTOM UVLO INPUT O.K. (V 2. NO INPUT OVERVOLTAGE(S)  < UVOV    (VIOVRETRY 3. CROWBAR INACTIVE (V 4. TEMPERATURE O.K. (V  ABOVE ITS UVLO5. DRVCC  > DRV    (VDRVCC 6. RUN > VRUN(ON)  > UVOVUVLO  < UVOV AND VOVLOTH  < VCROWBAR(TH)CROWBAR  > OTTH(INCEPTION)TEMP , ~3.35V , MAX) TH<br> OF THE FOLLOWING LATCHOFF FAULTS ARE PRESENT: OUT  < UVOV CC(UVLO_FALLING) (2V<br> IS INTVCC > 2V, NOM AND ANY 1. LATCHOFF INPUT OVERVOLTAGE (V 2. CROWBAR ACTIVE (V 3. LATCHOFF OVERTEMPERATURE     (OTBH = LOW AND V  IS OFF; ; CONTROL  OF THE FOLLOWING   ABOVE ITS UVLO  > DRV RUN(ON)<br>ING MHYST INH IOVRETRY CC DRVCC<br>INTVCC < 2V, NOM  IS CHARGE PUMPED INTVCC > 3.2V, NOM AND ALL FAULT FREE CONDITIONS ARE PRESENT: 1. CUSTOM UVLO INPUT O.K. (V 2. NO INPUT OVERVOLTAGE(S)     (V 3. CROWBAR INACTIVE (V 4. TEMPERATURE O.K. (V 5. DRV     (V 6. RUN > V<br>DISCHARGED LTM4641 POWER STAGE SWITCHING ACTION IS ON:  VING ABOVE V LOOP REGULATES V<br>LTM4641 SHUT DOWN: HOUSEKEEPING AND CONTROL SECTIONS ARE UNBIASED; POWER STAGE IS OFF; V<br>**----- End of picture text -----**<br>


## **Appendix B. Start-Up/Shutdown State Diagram** 

4641fe 

57 

For more information www.linear.com/LTM4641 

LTM4641 

## **appenDices** 

## **Appendix C. Switching Frequency Considerations and Usage of RfSET** 

There exist many scenarios in which a resistor, RfSET, should be connected externally to LTM4641’s fSET pin—to decrease the on-time of MTOP: most commonly, when the output voltage setting is less than or equal to 3V, and in rail-tracking applications; and less commonly, when VINL and VINH are operating from different source supplies. In the former cases, RfSET is usually applied from fSET to VINL (Figure 45 and front page application circuit); in the latter, RfSET is usually applied from fSET to the voltage source feeding LTM4641’s power stage—upstream of MSP, if a power-interrupt input MOSFET is used (Figure 49). There are several motivations and considerations behind this guidance: 

- (1) Inherent to LTM4641’s constant on-time architecture, the switching frequency of LTM4641 decreases as output voltage decreases. In order to maintain a reasonable output capacitor value solution size and output voltage ripple—even at lower output voltages (≤3VOUT)—RfSET should be applied, so that the controller’s ION pin current and the resulting nominal switching frequency is higher than the on-time dictated by the internal VINL-to-fSET-connected 1.3MΩ resistor. 

- (2) The PFM control scheme employed by LTM4641 yields a switching frequency at zero load current (“no-load operation”) that is typically 20% to 25% lower than what it is at full load. As a result, inductor ripple current is proportionally higher at no load than what it is at heavy load. Recall that LTM4641 employs RDS(ON) current sensing; furthermore, realize that it is essential for the controller’s current-sense amplifier to be able to perceive and command sufficiently negative inductor trough current, enough to maintain a maximum average inductor current of 0A, so that output voltage can be properly regulated down to no load. A value of RfSET should be used to assure that switching frequency is high enough (or on-time is small enough) at no load so that the current-sense information representing the trough of choke current is never too large in amplitude. Figure 3 provides conservative guidance on the maximum value of RfSET (or equivalently, the minimum ION current) that assures proper no-load operation. 

- (3) In rail-tracking applications, LTM4641’s output voltage must track a reference voltage not only during VOUT ramp up but also during VOUT ramp down; fulfilling the latter requires LTM4641 to sink current from the output capacitors. A value of RfSET should be used that assures the output voltage can be ramped down to one’s minimum desired output voltage of regulation—not just the intended nominal output voltage. Figure 3 provides this guidance. 

- (4) In order to maintain a relatively constant switching frequency for a given output voltage (across the full line voltage), the on-time of MTOP should be inversely proportional to the voltage source feeding the VINH power stage—upstream of MSP, if a power-interrupt MOSFET is used (Figure 46). When VINL and VINH are operated from different rails, this goal can be accomplished satisfactorily by placing RfSET between fSET and the power VIN input source (see Figure 49: the connection is to VIN and not VINL, and usually not VINH, but see a counterexample in Figure 47 and explanation in item number 5 of this list). A minor error term to the on-time is introduced by the internal 1.3MΩ VINL-to-fSET-connected resistor in such scenarios, so calculation of IION at all operating input voltage corner cases (power, VINH and control bias, VINL extremes) and the resulting switching frequency range of operation, given by Equation 6, should be considered. 

- (5) When MSP is used, and when VINL and VINH are operated from different rails—here is the reason it is recommended to connect RfSET from fSET to the drain of MSP rather than VINH: prior to start-up, MSP is off, and VINH is discharged. Connecting RfSET to VINH would set the on-time at the instant switching activity commenced to be much lower than intended. The on-time would not reach its final settling value until VING circuitry had turned on MSP enough for VINH to become pulled up to VIN potential. It should become apparent that a mechanism may exist for dynamic interaction between how rapidly the output voltage ramps up (depending on TRACK/SS pin usage) versus how rapidly MSP might turn on. We know from item number 2 of this list that on-time should not be arbitrarily large. In general, to avoid any undesirable 

4641fe 

58 

For more information www.linear.com/LTM4641 

LTM4641 

## **appenDices** 

interactions—which might at worst result in excessive output voltage ripple or non-monotonic output voltage ramp-up, a sufficiently slow output voltage ramp-up time can eliminate the danger of VINH and on-time settling interactions influencing output voltage ripple—but properly, this requires investigation and hardware evaluation on a case-by-case basis. Figure 47 shows an example where RfSET connects between fSET and VINH—rather than the input source supply. Because MSP limits the VINH voltage during the input voltage surge, the correct ION programming current can only be made with a resistor interface to VINH, in that example. 

## **Appendix D. Remote Sensing in Harsh Environments** 

The rationale for using the symmetrical resistor network is to provide a consistent feedback structure that enables fully differential remote-sense of output voltages between 0.6V and 6V with the flexibility to filter differential and common mode noise in harsh environments. See Figure 64. The use of not greater than 8.2kΩ nominal resistors for RSET1A (and RSET1B) assures that the remote-sense signal is not attenuated at frequencies of interest by the pole formed by the feedback resistors and parasitic capacitances. 

Furthermore, using an RSET1A (and RSET1B) value of 8.2kΩ for 1.2VOUT and larger assures that the common mode range of the remote-sense pins is within their valid range of –0.3V, minimum, to 3V, maximum—even if voltage drop between the module’s ground deviates from the POL’s ground by as much as ±0.6V. 

The differential remote-sense feedback signal is routed from the load as a differential pair on PCB traces (or twisted pair, if wires are used) to RSET1A/RSET1B feedback components. It is very important to place RSET1A/ RSET1B and all other components forming the feedback impedance-divider network as close to LTM4641 as is possible. Ground shielding of the differential remote-sense signal is strongly recommended, to prevent stray noise from contaminating the feedback information. 

If good shielding of the feedback signals cannot be provided, it is proactive to leave space in one’s layout for a small filter capacitor, CDM, placed directly between VOSNS[+] and VOSNS[–] , as close to the pins of the module as possible—in anticipation of the possible need to attenuate differential mode noise. 

Finally, if the POL is very far from the LTM4641, such as: the output power connection (VOUT and GND) is made 

**==> picture [432 x 254] intentionally omitted <==**

**----- Start of picture text -----**<br>
CCMA, CCMB: If Appreciable Cable Length Connects the LTM4641’s Output<br>to the Load (e.g., Through Several Feet of Wire), Leave Provision<br>for High Frequency Decoupling of Common Mode Ground Noise with<br>These Capacitors. These Are Not Needed in Purely PCB-Based Designs,<br>Where the LTM4641 Is Close to the Load CFFA, CFFB: Feedforward Capacitors<br>Yeild  Improved Transient Response<br>When Filtering VOUT with Only MLCC<br>Output Capacitors (COUT(MLCC))<br>VOUT VOUT<br>+<br>LTM4641 CFFA COUT(BULK) COUT(MLCC)<br>ICT<br>TEST<br>TO ERRORVFB 8.2k8.2k VVOSNSORB [+][+] POINT CCMA RSET1A<br>AMPLIFIER<br>CDM RSET2 LOAD<br>8.2k<br>RSET1B<br>VOSNS [–]<br>8.2k VORB [–] ICT CCMB CFFB 4641 F064<br>TRUE DIFFERENTIAL REMOTE TEST<br>SENSE AMPLIFIER SGND POINT Route Feedback Signals as<br>GND Place All Feedback Twisted Pair if Using Wires).a Differential Pair (or<br>Components Local  Sandwich Between Ground<br>To The LTM4641<br>Planes to Form a Protective Shield,<br>SGND CONNECTS TO GND INTERNAL TO MODULE. KEEP SGND Guarding Against Stray Noise<br>ROUTES/PLANES SEPARATE FROM GND ON MOTHERBOARD<br>If Effective Ground Shielding of the Feedback Signals Cannot<br>Be Implemented, Leave Provision for a Small Capacitor (CDM)<br>To Attenuate Differential Mode Noise if Necessary<br>+<br>–<br>**----- End of picture text -----**<br>


**Figure 64. Feedback Remote Sense Connections and Techniques for Harshest Operating Environments** 

4641fe 

59 

For more information www.linear.com/LTM4641 

LTM4641 

## **appenDices** 

through a board-to-board connector; an inductive length of cable (say, 50cm in length, or more); or, if the load is highly inductive—then it is proactive to leave provision in one’s layout for a pair of small filter capacitors, CCMA and CCMB. CCMA and CCMB should be placed directly from VOSNS[+] to SGND and VOSNS[–] to SGND, respectively—as close to the pins of the module as possible. Configured in this manner, CCMA and CCMB can be used to attenuate common mode noise in the remote-sense signal pin pair. 

## **Appendix E. Inspiration For Pulse-Skipping Mode Operation** 

When MTOP is turned on—for a duration of time proportional to IION current—inductor current is ramped upwards, and energy is built up in the inductor’s B-field. Ultimately, a “packet” of energy is transferred from the input capacitors to the output capacitors. In forced continuous mode operation (FCB logic low), MTOP and MBOT are operated in a purely synchronous fashion, meaning: when MTOP is on, MBOT is off—and vice versa. Observe that when MTOP is turned off, the B-field in the inductor cannot instantaneously vanish: the collapsing B-field forces inductor current to flow through MBOT’s on-die Schottky diode—resulting in unwanted freewheeling diode power loss; MBOT is turned on for lower power loss, instead. With MBOT on, inductor current ramps downward as energy in its B-field wanes. 

In steady-state forced continuous mode operation, the inductor ripple current appears as a triangle waveform whose average value equates to the load’s current. Forced continuous mode operation (forcing synchronous operation of MTOP and MBOT) provides a mechanism for consistent output voltage ripple, regardless of the load current. However, in this mode of operation, at light load currents (say, less than 2A out), observe that the inductor current is periodically negative—which means some packets of energy that are transferred from the input capacitors to the output are recirculated and transferred back to the input capacitors. This is a source of inefficiency that brings about the motivation for pulse-skipping mode operation, to turn off MBOT when the inductor current ramps down to 0A. This concept is also described in the industry as “diode emulation”, because MBOT is made to mimic the behavior of a Schottky rectifier. In pulse-skipping mode 

operation (FCB logic high), the inductor ripple current at light loads appears as an asymmetrical truncated triangle waveform; inductor current does not go below 0A. 

## **Appendix F. Adjusting the Fast Output Overvoltage Comparator Threshold** 

The output overvoltage inception threshold (OVPGM voltage) can be adjusted or tightened from its default value. The following guidelines must be followed, however: 

- It is not recommended to change the OVPGM voltage dynamically because the fast OOV comparator has no glitch immunity beyond what is provided by OVPGM’s internal 47pF capacitor, and routing of OVPGM can make it vulnerable to electrostatic noise. 

- The 15.6μs time constant filter formed by OVPGM’s internal 47pF capacitor and default 499kΩ||1MΩ resistordivider network should be maintained for practical values of OVPGM voltage: 0.6V < VOVPGM < 0.9V. Capacitive filtering of OVPGM must not be applied indiscriminately. The OVPGM voltage must come up very rapidly with the 1VREF at start-up, to prevent a race condition that would otherwise result in nuisance OOV detection and a faulty latchoff event—so any externally applied capacitance cannot be arbitrarily high. On the other hand, OVPGM must have some filtering from switching noise sources and should be sufficiently insulated from any possible dynamic activity on 1VREF. (See Figure 9.) 

- External resistor(s) applied between OVPGM and 1VREF/ SGND should be relatively high impedance, to minimize loading on the 1VREF output. Then, small values of COVPGM achieve a consistent time constant as OVPGM’s resistance-divider network is altered. 

Figure 65 shows the optional network one can apply to alter or tighten the OVPGM setpoint. 

**==> picture [138 x 69] intentionally omitted <==**

**----- Start of picture text -----**<br>
1VREF<br>LTM4641 RTOVPGM<br>OVPGM<br>COVPGM RBOVPGM<br>SGND<br>4641 F65<br>**----- End of picture text -----**<br>


**Figure 65. Optional OVPGM Network to Alter or Tighten VOVPGM** 

4641fe 

60 

For more information www.linear.com/LTM4641 

LTM4641 

## **appenDices** 

To nudge the OVPGM setpoint downward, to a new OOV inception threshold voltage at OVPGM(NEW)—using an RBOVPGM resistor, only—calculate: 

**==> picture [241 x 43] intentionally omitted <==**

The new OVPGM threshold can then be double-checked by 

**==> picture [240 x 29] intentionally omitted <==**

When lowering the OVPGM setpoint with application of RBOVPGM only, it is not necessary to apply a COVPGM capacitor, because: for an extreme OVPGM(NEW) setting of 600mV, which is not practical since that is the voltage of VFB during normal regulation, the time-constant of the OVPGM network would have changed by less than 2μs from its default value. 

To nudge the OVPGM trip threshold upward to set a new OOV inception threshold voltage at OVPGM(NEW)—using an RTOVPGM resistor only—calculate: 

**==> picture [240 x 44] intentionally omitted <==**

The new OVPGM setting can then be double-checked by: 

**==> picture [240 x 27] intentionally omitted <==**

If RTOVPGM is computed in Equation 39 to be smaller than 10kΩ, connect OVPGM to 1VREF and do not apply any COVPGM capacitor; this will yield an OOV setting of 167% of nominal. Otherwise, use the next smallest standard value of COVPGM available, computed by: 

**==> picture [239 x 28] intentionally omitted <==**

The default VOVPGM setpoint is 665mV ±2.26%, over temperature. To tighten the OVPGM setpoint, begin by choosing RBOVPGM to be a commonly available precision 

100kΩ, low T.C.R. resistor. Using tolerances of ±0.1% and a T.C.R. of ±25ppm/°C can provide a considerable improvement in accuracy over the default divider network, over temperature. Next, decide the new value of VOVPGM desired—OVPGM(NEW)—within a practical window of 0.6V < OVPGM(NEW) < 0.9V. Then, compute RTOVPGM according to: 

**==> picture [240 x 55] intentionally omitted <==**

The new OVPGM setting can be double-checked by: 

**==> picture [239 x 28] intentionally omitted <==**

Then, use the next smallest standard value of COVPGM available, computed by: 

**==> picture [240 x 40] intentionally omitted <==**

For example, the OVPGM(NEW) setpoint can be kept at its nominal value of 666mV—but with better accuracy—by using ±0.1% precision resistors with ±25ppm/°C T.C.R. for RBOVPGM = 100k and RTOVPGM = 49.9k, and bypassing OVPGM to SGND with COVPGM = 470pF. The resulting VOVPGM OOV setpoint threshold becomes better than ±1.8%, over temperature. The vast majority of the remaining variation in the threshold setting comes variation of the 1VREF—a ±1.5% reference, over temperature. 

The extreme values of the OOV setpoint voltage, plus the OVPERR term—which is the offset voltage of the fast comparator (±12mV maximum, over temperature)—gives guidance on what the minimum and maximum voltage VFB can be at which the CROWBAR output would swing logic high and invoke latchoff overvoltage protection. 

One must take care to set the OVPGM voltage to a practical level and not too aggressively. If OVPGM is set too low, the system will demonstrate nuisance output overvoltage latchoff behavior. The output voltage of any switching 

4641fe 

61 

For more information www.linear.com/LTM4641 

LTM4641 

## **appenDices** 

regulator can witnesses transient excursions above its ideal DC voltage operating point routinely, owing to: 

- Control IC bandgap reference accuracy 

- Output voltage ripple and noise 

- Load current step-down transient events—including recovery from a short-circuit condition 

- Steep line voltage step-up 

- Start-up overshoot (little or no soft-starting of VOUT), or rail-tracking a fast master rail 

The Linear Technology LTpowerCAD design tool can help quantify some of these dynamic values; LTM4641’s total DC error (including bandgap reference variation) is better than ±1.5%, over temperature. 

If OVPGM has been decreased to its lowest practical level and output voltage overshoot during high side MOSFET 

short-circuit testing (shorting VINH to SW on evaluation hardware  such as DC1543, for example) does not clamp the output voltage to one’s satisfaction, be aware that increasing output capacitance can reduce the maximum output voltage excursion. The reason follows: the larger the output capacitance, the longer it takes for the output voltage to be ramped up, even in the extreme case of deliberately short circuiting VINH to SW. The capacitance on VOUT is mainly what prevents the output voltage from shooting up to VINH—until CROWBAR turns on MCB. 

Multimodule parallel applications also have better output voltage overshoot during high side MOSFET short-circuit testing, owing to the fact that the sibling modules whose high side MOSFETs are not short circuited are able to help pull the output voltage down by turning on their low side power MOSFETs. Examples of paralleled LTM4641 powering and protecting loads are shown in Figures 56 and 66. 

4641fe 

62 

For more information www.linear.com/LTM4641 

LTM4641 

LTM4641 

## **package DescripTion** 

**Table 10. LTM4641 Component BGA Pinout** 

|**PIN ID**|**FUNCTION**<br>~~a~~|**PIN ID**||**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|A1|SGND<br>~~a~~|B1||SGND|C1|SGND|D1|VORB+|E1|GND|F1|GND|
|A2|SGND<br>~~a~~|B2||SGND|C2|SGND|D2|VORB–|E2|GND|F2|GND|
|A3|SGND<br>B3<br>~~aa~~|||SGND|C3|SGND|D3|OTBH|E3|GND|F3|GND|
|A4|HYST<br>~~a ~~|B4<br> ~~a CG~~|UVLO<br>C4<br>SGND<br>D4<br>TMR<br>E4<br>GND<br>F4<br>~~CG~~|||||||||GND|
|A5|TEMP<br>~~a ~~|B5<br> ~~a~~||OVLO<br>~~a ~~|C5<br>LATCH<br>D5<br>RUN<br>E5<br>GND<br>F5<br> ~~CG~~|||||||GND|
|A6|IOVRETRY<br>~~a~~|B6||GND|C6|1VREF|D6|GND|E6|GND|F6|GND|
|A7|GND<br>~~a~~|B7||GND|C7|GND|D7|GND|E7|GND|F7|GND|
|A8|GND<br>~~a~~|B8|~~A~~|GND|C8|GND|D8|GND|E8|GND|F8|GND|
|A9|GND<br>~~a~~|B9||CROWBAR|C9|VOUT|D9|VOUT|E9|VOUT|F9|GND|
|A10|GND<br>~~a~~|B10||OVPGM|C10|VOUT|D10|VOUT|E10|VOUT|F10|GND|
|A11|GND<br>~~a~~|B11||GND|C11|VOUT|D11|VOUT|E11|VOUT|F11|GND|
|A12|GND<br>~~a ~~|B12<br> ~~a~~||GND|C12|VOUT|D12|VOUT|E12|VOUT|F12|GND|
||||||||||||||
|**PIN ID**|**FUNCTION**<br>**PIN ID**<br>**FUNCTION**<br>~~aa~~||||**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|**PIN ID**|**FUNCTION**|
|G1|GND<br>H1<br>~~a~~<br>~~a CG~~||VOSNS+<br>J1<br>COMP<br>K1<br>SGND<br>L1<br>PGOOD<br>M1<br>~~CG~~|||||||||SGND|
|G2|GND<br>~~a ~~|H2<br> ~~a~~||VOSNS–<br>~~a ~~|J2<br>fSET<br>K2<br>FCB<br>L2<br>TRACK/SS<br>M2<br> ~~CG~~|||||||SGND|
|G3|GND<br>~~a~~|H3||GND|J3|VINL|K3|SGND|L3|SGND|M3|SGND|
|G4|GND<br>~~a~~|H4||GND|J4|DRVCC|K4|INTVCC|L4|GND|M4|GND|
|G5|GND<br>~~a~~|H5|~~A~~|GND|J5|GND|K5|GND|L5|GND|M5|GND|
|G6|GND<br>~~a~~|H6||GND|J6|GND|K6|GND|L6|GND|M6|GND|
|G7|GND<br>~~a~~|H7||GND|J7|GND|K7|VINH|L7|VINH|M7|VINH|
|G8|GND<br>~~a~~|H8||GND|J8|GND|K8|VINH|L8|VINH|M8|VINH|
|G9|GND<br>~~a~~|H9||GND|J9|GND|K9|VINH|L9|VINH|M9|VING|
|G10|GND<br>~~a ~~|H10<br> ~~a OG~~|SW<br>J10<br>GND<br>K10<br>VINH<br>L10<br>VINH<br>M10<br>~~OG~~|||||||||VINGP|
|G11|GND<br>~~a ~~|H11<br> ~~a CS~~|GND<br>J11<br>GND<br>K11<br>GND<br>L11<br>VINH<br>M11<br>~~CS~~|||||||||VINH|
|G12|GND<br>~~a~~|H12<br>~~a~~||GND|J12|GND|K12|GND|L12|VINH|M12|VINH|



## **package phoTo** 

4641fe 

63 

For more information www.linear.com/LTM4641 

LTM4641 

## **package DescripTion** 

## **Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.** 

**==> picture [482 x 598] intentionally omitted <==**

**----- Start of picture text -----**<br>
7<br>SEE NOTES<br>PIN 1<br>M L K J H G F E D C B A<br>1<br>BGA 144 1112 REV A<br>2<br>3<br>4<br>5<br>e<br>6<br>G<br>7<br>8<br>PACKAGE BOTTOM VIEW<br>9<br>LTMXXXXXX µModule<br>10 PACKAGE IN TRAY LOADING ORIENTATION<br>11 b PACKAGE ROW AND COLUMN LABELING MAY VARY  AMONG µModule PRODUCTS. REVIEW EACH PACKAGE  LAYOUT CAREFULLY<br>!<br>12 DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR  MARKED FEATURE<br>DETAIL A b e NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS 3        BALL DESIGNATION PER JESD MS-028 AND JEP95 4 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. SOLDER BALL COMPOSITION IS 96.5% Sn/3.0% Ag/0.5% Cu 7 PIN “A1” TRAY PIN 1 BEVEL<br>3 COMPONENT<br>F<br>SEE NOTES<br>Z<br>NOTES<br>A A2<br>DETAIL B<br>MAX 5.21 0.70 4.51 0.90 0.66 0.46 4.05 0.15 0.10 0.20 0.30 0.15<br>PACKAGE SIDE VIEW<br>b1<br>Y NOM 5.01 0.60 4.41 0.75 0.63 15.00 15.00 1.27 13.97 13.97 0.41 4.00<br>H1 X<br>A1 SUBSTRATE MZ MZ DIMENSIONS<br>BGA Package<br>ddd eee MIN 4.81 0.50 4.31 0.60 0.60 0.36 3.95<br>TOTAL NUMBER OF BALLS: 144<br>ccc  Z MOLD CAP H2 DETAIL B DETAIL A<br>A A1 A2 b b1 D E e F G H1 H2 aaa bbb ccc ddd eee<br>SYMBOL<br>Øb (144 PLACES)<br>144-Lead (15mm × 15mm × 5.01mm) (Reference LTC DWG # 05-08-1914 Rev A)<br>aaa  Z<br>0.0000<br>D X Y 6.9850 5.7150 4.4450 3.1750 1.9050 0.6350 0.6350 1.9050 3.1750 4.4450 5.7150 6.9850<br>E<br>TOP VIEW<br>PACKAGE TOP VIEW<br>SUGGESTED PCB LAYOUT<br>0.0<br>4<br>PIN “A1” CORNER<br>0.630 ±0.025 Ø 144x<br>Z<br>Z//  bbb<br>6.9850<br>5.7150<br>4.4450<br>3.1750<br>1.9050<br>0.6350<br>0.0000<br>0.6350<br>1.9050<br>3.1750<br>4.4450<br>5.7150<br>6.9850<br>aaa  Z<br>**----- End of picture text -----**<br>


4641fe 

64 

For more information www.linear.com/LTM4641 

LTM4641 

## **revision hisTory (Revision history begins at Rev B)** 

|**re**|**isio**|**n hisTory**<br>**(Revision history begins at Rev B)**||
|---|---|---|---|
|**REV**|**DATE**|**DESCRIPTION**|**PAGE NUMBER**|
|B|02/13|Updated Figure 1.|15|
|C|05/13|Updated video play buttons.|1, 49|
|D|10/13|Added patent number 8163643.<br>Changed Figure 9 title from "Figure 43 Circuit” to "Figure 45 Circuit at 28VIN."|1<br>28|
|E|02/14|Added SnPb BGA package option|1, 3|



4641fe 

65 

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.For more information www.linear.com/LTM4641 

LTM4641 

## **Typical applicaTion** 

**==> picture [458 x 399] intentionally omitted <==**

**----- Start of picture text -----**<br>
4.5VIN START-UP<br>OPERATION UP TO 38V<br>AND DOWN TO 4V MSP<br>CIN(BULK) CIN(MLCC)<br>100µF 10µF<br>50V 50V<br>×2 ×4<br>VING VINGP VINH SW VOUT<br>VINL VOUT 1V<br>RfSET1 CFF1 20A<br>750k fSET CROWBA R MCB 100pF 100µFCMLCC(OUT)<br>UVLO LATCH 6.3V<br>HYSTFCB VOR B [+] R2.74kSET1A ×6<br>1 INTVDRVCCCC LTM4641U1 VVOSNSOSNS [+][–] C22pFDM1 R2.74kSET1B LOAD LOCAL HIGHFREQUENCYDECOUPLING<br>IOVRETRY VOR B [–] CFF2<br>OVLO TE MP 100pF<br>1VR EF<br>1 OVPG M<br>RUN ENABLE OTBH<br>R UN PGOO D 1<br>TRACK/SS TMR COMP SGND GND<br>TO SYSTEM µP(OPTIONAL) FAULT INDICATOR 22nFCSS CTMR1N/U 1<br>1 1<br>LATCHOFF RESET<br>PULL LATCH NORMALLY LOW FOR<br>LATCHOFF RESPONSE TO OUTPUT<br>OVERVOLTAGE AND OVER- VING VINGP VINH SW<br>TEMPERATURE EVENTS. PULL VINL VOUT<br>LATCH HIGH TO RESTART 1V OUTPUT RfSET2<br>750k CROWBAR<br>ALTERNATIVELY, CONNECT LATCH UVLOfSET LATCH<br>TO INTVCTMR2 TO SET 1V OUTPUT FOR TIMEDCC AND INSTALL CTMR1 AND HYSTFCB VOR B [+]<br>AUTONOMOUS RESTART AFTERFAULT SHUTDOWN EVENTS 2 INTVCC LTM4641U2 VOSNS [+] C22pFDM2<br>MCB: NXP PSMN5R0-30YL DRVCC VOSNS [–]<br>MSP: NXP PSMN7R0-60YS IOVRETRY VOR B [–]<br>OVLO TE MP<br>1VR EF<br>2 OVPG M<br>OTBH<br>R UN PGOO D 2<br>TRACK/SS TMR COMP SGND GND<br>CTMR2N/U 2<br>2 4641 F66<br>U1 AND U2 SGND (           ) CONNECT TO GND INTERNAL TO THEIR RESPECTIVE MODULES. KEEP MODULE 1 [,] 2<br>SGND ROUTES/PLANES SEPARATE FROM OTHER MODULES AND FROM GND ON MOTHERBOARD<br>**----- End of picture text -----**<br>


**Figure 66. 1V, 20A Fault-Protected Load Powered by Paralleled LTM4641—from Up to 38VIN. cf. Typical Performance Characteristics** 

## **relaTeD parTs** 

|**PART NUMBER**|**DESCRIPTION**|**COMMENTS**|
|---|---|---|
|LTM4620|Dual 13A, Single 26A µModule<br>Regulator|Up to 100A with Four Devices; 4.5V ≤ VIN≤ 16V; 0.6V ≤ VOUT≤ 2.5V. See LTM4620A for<br>Higher VOUT;15mm×15mm×4.41mm LGA|
|LTM4613|EN55022B Certified 36V, 8A<br>Step-DownµModule Regulator|5V ≤ VIN≤ 36V; 3.3V ≤ VOUT≤ 15V; Synchronizable, Parallelable,<br>15mm×15mm×4.32mm LGA|
|LTM4627|20V, 15A Step-Down µModule<br>Regulator|4.5V ≤ VIN≤ 20V; 0.6V ≤ VOUT≤ 5V; Synchronizable, Parallelable,<br>Remote Sensing,15mm×15mm×4.32mm LGA or 15mm×15mm×4.92mm BGA|
|LTM8027|60V, 4A Step-Down µModule<br>Regulator|4.5V ≤ VIN≤ 60V; 2.5V ≤ VOUT≤ 24V; Synchronizable,<br>15mm×15mm×4.32mm LGA|
|LTM4609|36V, 4A Buck-Boost µModule<br>Regulator|4.5V ≤ VIN≤ 36V; 0.8V ≤ VOUT≤ 34V; Synchronizable, Parallelable, Up to 4A in Boost Mode<br>and 10A in Buck Mode,15mm×15mm×2.82mm LGA or 15mm×15mm×3.42mm BGA|
|LT4356|High Voltage Surge Stopper|100VINOvervoltage and Overcurrent Protection,Latchoff and Auto-RetryOptions|



4641fe 

LT 0214 REV E • PRINTED IN USA 

66 Linear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7417For more information www.linear.com/LTM4641 (408) 432-1900[●] FAX: (408) 434-0507[●] www.linear.com/LTM4641 

 LINEAR TECHNOLOGY CORPORATION 2012