LTM4612MPV#PBF

LTM4612 

EN55022B Compliant 36VIN, 15VOUT, 5A, DC/DC µModule Regulator 

## **FEATURES** 

- n **Complete Low EMI Switch Mode Power Supply** n **EN55022 Class B Compliant** 

- n **Wide Input Voltage Range: 5V to 36V** 

- n **3.3V to 15V Output Voltage Range** 

- n **5A DC, 7A Peak Output Current** 

- n **Low Input and Output Referred Noise** 

- n **Output Voltage Tracking and Margining** 

- n **Power Good Tracks with Margining** 

- n **PLL Frequency Synchronization** 

- n ± **1.5% Set Point Accuracy** 

- n **Current Foldback Protection (Disabled at Start-Up)** 

- n **Parallel/Current Sharing** 

- n Ultrafast Transient Response 

- n Current Mode Control 

- n Programmable Soft-Start 

- n Output Overvoltage Protection 

- n –55°C to 125°C Operating Temperature Range (LTM4612MPV) 

- n Small Surface Mount Footprint, Low Profile (15mm × 15mm × 2.8mm) LGA Package 

## **APPLICATIONS** 

- n Telecom and Networking Equipment 

- n Industrial and Avionic Equipment 

- n RF Systems 

## **DESCRIPTION** 

The LTM[®] 4612 is a EN55022 Class B certified high voltage input and output, 5A switching mode DC/DC power supply. Included in the package are the switching controller, power FETs, inductor and all support components. Operating over an input voltage range of 5V to 36V, the LTM4612 supports an output voltage range of 3.3V to 15V, set by a single resistor. Only bulk input and output capacitors are needed to finish the design. 

High switching frequency and an adaptive on-time current mode architecture enables a very fast transient response to line and load changes without sacrificing stability. 

The onboard input filter and noise cancellation circuits achieve low noise coupling, thus effectively reducing the electromagnetic interference (EMI)—see Figures 4 and 8. Furthermore, the DC/DC µModule[®] regulator can be synchronized with an external clock to reduce undesirable frequency harmonics and allow PolyPhase[®] operation for high load currents. 

The LTM4612 is offered in a space saving and thermally enhanced 15mm × 15mm × 2.8mm LGA package, which enables utilization of unused space on the bottom of PC boards for high density point-of-load regulation. The LTM4612 is Pb-free and RoHS compliant. 

L, LT, LTC, LTM, Linear Technology, the Linear logo, PolyPhase and µModule are registered trademarks and LTpowerCAD is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. 

## **TYPICAL APPLICATION** 

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5V/5A Ultralow Noise µModule with 7V to 36V Input<br>**----- End of picture text -----**<br>


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VIN CLOCK SYNC<br>7V<br>TO 36V 2M 100k VIN PLLIN VOUT<br>PGOOD VOUT 5V<br>RUN LTM4612 100pF 5A<br>COMP VFB COUT<br>INTVCC 13.7k<br>CIN DRVCC FCB an<br>j<br>fSET MARG0 MARGIN<br>TRACK/SS MARG1 CONTROL<br>0.01µF VD MPGM<br>10µF SGND PGND 392k<br>rs 5% MARGIN<br>4612 TA01<br>**----- End of picture text -----**<br>


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Radiated Emission Scan at 24VIN, 5VOUT/5A<br>**----- End of picture text -----**<br>


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70<br>60 PTT TTT TTT<br>50 PTETTT TTL<br>40 coe EN55022 CLASS B LIMIT<br>30<br>20 nent<br>|| Foo<br>10 iii<br>0 PETET TT TL<br>–10<br>30 PTET 226.2 422.4 TTT 618.6 TTT 814.8 1010<br>128.1 324.3 520.5 716.7 912.9<br>FREQUENCY (MHz) 4612 TA01b<br>dBµV/m<br>**----- End of picture text -----**<br>


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## LTM4612 

## **ABSOLUTE MAXIMUM RATINGS** 

## **PIN CONFIGURATION** 

## **(Note 1)** 

INTVCC, DRVCC .............................................–0.3V to 6V VOUT ........................................................... –0.3V to 16V PLLIN, FCB, TRACK/SS, MPGM, MARG0, MARG1, PGOOD ....................–0.3V to INTVCC + 0.3V RUN .............................................................–0.3V to 5V VFB, COMP ................................................ –0.3V to 2.7V VIN, VD .......................................................–0.3V to 36V Internal Operating Temperature Range (Note 2) E and I Grades ...................................–40°C to 125°C MP Grade ........................................... –55°C to 125°C Junction Temperature ........................................... 125°C Storage Temperature Range .................. –55°C to 125°C 

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TOP VIEW<br>A<br>BANK 1VIN BC VDSGND MARG0fSET<br>D MARG1<br>E DRVCC<br>PGND<br>BANK 2 F VFB<br>G PGOOD<br>H SGND<br>J NC<br>VOUT K NC<br>BANK 3 L NC<br>M FCB<br>1 2 3 4 5 6 7 8 9 10 11 12<br>LGA PACKAGE<br>133-LEAD (15mm × 15mm × 2.8mm)<br>TJMAX = 125°C, θJA = 15°C/W, θJC = 6°C/W<br>θJA DERIVED FROM 95mm × 76mm PCB WITH 4 LAYERS<br>WEIGHT = 1.7g<br>CC<br>INTV PLLIN TRACK/SS RUN COMP MPGM<br>**----- End of picture text -----**<br>


## **ORDER INFORMATION http://www.linear.com/product/LTM4612#orderinfo** 

|**LEAD FREE FINISH**|**TRAY**|**PART MARKING***|**PACKAGE DESCRIPTION**|**TEMPERATURE RANGE**|
|---|---|---|---|---|
|LTM4612EV#PBF|LTM4612EV#PBF|LTM4612V|133-Lead (15mm×15mm×2.8mm) LGA|–40°C to 125°C|
|LTM4612IV#PBF|LTM4612IV#PBF|LTM4612V|133-Lead (15mm×15mm×2.8mm) LGA|–40°C to 125°C|
|LTM4612MPV#PBF|LTM4612MPV#PBF|LTM4612MPV|133-Lead (15mm×15mm×2.8mm) LGA|–55°C to 125°C|



Consult LTC Marketing for parts specified with wider operating temperature ranges.  *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ This product is only offered in trays. For more information go to: http://www.linear.com/packaging/ 

**ELECTRICAL CHARACTERISTICS The** l **denotes the specifications which apply over the specified internal operating temperature range, otherwise specifications are at TA = 25°C, VIN = 24V, unless otherwise noted (Note 2). Per Typical Application (front page) configuration.** 

|**SYMBOL**|**PARAMETER**|**CONDITIONS**|**CONDITIONS**|**MIN**<br>**TYP**<br>**MAX**|**UNITS**|
|---|---|---|---|---|---|
|VIN(DC)|Input DC Voltage||l|5<br>36|V|
|VOUT(DC)|Output Voltage|CIN= 10µF×3, COUT= 300µF; FCB = 0<br>VIN= 24V, VOUT= 12V, IOUT= 0A<br>VIN= 36V, VOUT=12V, IOUT= 0A|l<br>l|11.83<br>11.83<br>12.07<br>12.07<br>12.31<br>12.31|V<br>V|
|**Input Specifications**||||||
|VIN(UVLO)|Undervoltage Lockout Threshold|IOUT= 0A||3.2<br>4.8|V|
|IINRUSH(VIN)|Input Inrush Current at Start-Up|IOUT= 0A; CIN= 10µF×2, COUT= 200µF;<br>VOUT= 12V<br>VIN= 24V<br>VIN= 36V||0.6<br>0.7|A<br>A|



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LTM4612 

**ELECTRICAL CHARACTERISTICS The** l **denotes the specifications which apply over the specified internal operating temperature range, otherwise specifications are at TA = 25°C, VIN = 24V, unless otherwise noted (Note 2). Per Typical Application (front page) configuration.** 

|**SYMBOL**|**PARAMETER**|**CONDITIONS**|**CONDITIONS**|**MIN**<br>**TYP**<br>**MAX**|**UNITS**|
|---|---|---|---|---|---|
|IQ(VIN)|Input Supply Bias Current|VIN= 36V, VOUT= 12V, Switching Continuous<br>VIN= 24V, VOUT= 12V, Switching Continuous<br>Shutdown, RUN = 0, VIN= 36V||57<br>48<br>50|mA<br>mA<br>µA|
|IS(VIN)|Input Supply Current|VIN= 36V, VOUT= 12V, IOUT= 5A<br>VIN= 24V, VOUT= 12V, IOUT= 5A||1.85<br>2.72|A<br>A|
|VINTVCC|Internal VCCVoltage|VIN= 36V, RUN > 2V, IOUT= 0A||4.7<br>5<br>5.5|V|
|**Output Specifications**||||||
|IOUT(DC)|Output Continuous Current Range|VIN= 24V, VOUT= 12V (Note 4)||0<br>5|A|
|DVOUT(LINE)<br>VOUT|Line Regulation Accuracy|VOUT= 12V, FCB = 0V, VIN= 22V to 36V,<br>IOUT= 0A|l|0.05<br>0.3|%|
|DVOUT(LOAD)<br>VOUT|Load Regulation Accuracy|VOUT= 12V, FCB = 0V, IOUT= 0A to 5A (Note 4)<br>VIN= 36V<br>VIN= 24V|l<br>l|0.3<br>0.3<br>0.6<br>0.6|%<br>%|
|VIN(AC)|Input Ripple Voltage|IOUT= 0A,<br>CIN= 2×10µF X5R Ceramic and 1×100µF<br>Electrolytic, 1×10µF X5R Ceramic on VDPins<br>VIN= 24V, VOUT= 5V<br>VIN= 24V, VOUT= 12V||7.2<br>3.4|mVP-P<br>mVP-P|
|VOUT(AC)|Output Ripple Voltage|IOUT= 0A,<br>COUT= 2×22µF, 2×47µF X5R Ceramic<br>VIN= 24V, VOUT= 5V<br>VIN= 24V, VOUT= 12V||17.5<br>12.5|mVP-P<br>mVP-P|
|fS|Output Ripple Voltage Frequency|IOUT= 1A, VIN= 24V, VOUT= 12V||940|kHz|
|DVOUT(START)|Turn-On Overshoot,<br>TRACK/SS = 10nF|COUT= 200µF, VOUT= 12V, IOUT= 0A<br>VIN= 36V<br>VIN= 24V||20<br>20|mV<br>mV|
|tSTART|Turn-On Time, TRACK/SS = Open|COUT= 300µF, VOUT= 12V, IOUT= 1A<br>Resistive Load<br>VIN= 36V<br>VIN= 24V||0.5<br>0.5|ms<br>ms|
|DVOUT(LS)|Peak Deviation for Dynamic Load|Load: 0% to 50% to 0% of Full Load<br>COUT= 2×22µF Ceramic, 150µF Bulk<br>VIN= 24V, VOUT= 12V||153|mV|
|tSETTLE|Settling Time for Dynamic Load Step|Load: 0% to 50% to 0% of Full Load, VIN= 24V||37|µs|
|IOUT(PK)|Output Current Limit|COUT= 200µF<br>VIN= 36V, VOUT= 12V<br>VIN= 24V, VOUT= 12V||9<br>9|A<br>A|
|**Control Section**||||||
|VFB|Voltage at VFBPin|IOUT= 0A, VOUT= 12V|l|0.591<br>0.6<br>0.609|V|
|VRUN|RUN Pin On/Off Threshold|||1<br>1.5<br>1.9|V|
|ISS/TRACK|Soft-Start Charging Current|VSS/TRACK= 0V||–1<br>–1.5<br>–2|µA|
|VFCB|Forced Continuous Threshold|||0.57<br>0.6<br>0.63|V|
|IFCB|Forced Continuous Pin Current|VFCB= 0V||–1<br>–2|µA|
|tON(MIN)|Minimum On-Time|(Note 3)||50<br>100|ns|
|tOFF(MIN)|Minimum Off-Time|(Note 3)||250<br>400|ns|
|RPLLIN|PLLIN Input Resistor|||50|kW|



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## LTM4612 

**ELECTRICAL CHARACTERISTICS The** l **denotes the specifications which apply over the specified internal operating temperature range, otherwise specifications are at TA = 25°C, VIN = 24V, unless otherwise noted (Note 2). Per Typical Application (front page) configuration.** 

|<br>**Application (front**|<br>**page) configuration.**|||||
|---|---|---|---|---|---|
|**SYMBOL**|**PARAMETER**|**CONDITIONS**||**MIN**<br>**TYP**<br>**MAX**|**UNITS**|
|IDRVCC|Current into DRVCCPin|VOUT= 12V, IOUT= 1A||22<br>30|mA|
|RFBHI|Resistor Between VOUTand VFBPins|||99.5<br>100<br>100.5|kW|
|VMPGM|Margin Reference Voltage|||1.18|V|
|VMARG0, VMARG1|MARG0, MARG1 Voltage Thresholds|||1.4|V|
|**PGOOD**||||||
|DVFBH|PGOOD Upper Threshold|VFBRising||7<br>10<br>13|%|
|DVFBL|PGOOD Lower Threshold|VFBFalling||–7<br>–10<br>–13|%|
|DVFB(HYS)|PGOOD Hysteresis|VFBReturning||1.5|%|
|VPGL|PGOOD Low Voltage|IPGOOD= 5mA||0.15<br>0.4|V|



**Note 1:** Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. 

**Note 2:** The LTM4612E is guaranteed to meet performance specifications over the 0°C to 125°C internal operating temperature range. Specifications over the –40°C to 125°C internal operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTM4612I is guaranteed to meet specifications over the 

–40°C to 125°C internal operating temperature range. The LTM4612MP is guaranteed and tested over the full –55°C to 125°C internal operating temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. 

**Note 3:** 100% tested at die level only. 

**Note 4:** See the Output Current Derating curves for different VIN, VOUT and TA. 

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LTM4612 

## **TYPICAL PERFORMANCE CHARACTERISTICS (Refer to Figure 18)** 

**Efficiency vs Load Current with** 

**Efficiency vs Load Current with Efficiency vs Load Current with 5VOUT (FCB = 0) 12VOUT (FCB = 0)** 

**3.3VOUT (FCB = 0)** 

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100 95 100<br>95 Oe 90 95<br>90 85 90<br>a<br>85 85<br>80<br>80 80<br>75<br>75 Pe —_ fe e Zann 75 aoe<br>A 70<br>70 70<br>65 aetT 65 ee 65 ><br>60 rit 5V12VININ 3.3V 3.3VOUTOUT 60 pF i | | 12V | IN 5VOUT | 60 Pt 20V24VININ 12V 12VOUTOUT<br>55 24V IN  3.3V OUT 55 24VIN 5VOUT 55 28V IN  12V OUT<br>50 Pere 36VIN 3.3VOUT 50 36VIN 5VOUT 50 36VIN 12VOUT<br>0 1 2 3 4 5 0 - 1 2 3 4 5 0 -T 1 2 3 4 5<br>[Tt | ERPS] Eee<br>LOAD CURRENT (A) 4612 G01 LOAD CURRENT (A) 4612 G02 LOAD CURRENT (A) 4612 G03<br>Efficiency vs Load Current with   Transient Response from 12VIN Transient Response from 12VIN<br>15VOUT (FCB = 0, Refer to Figure 20)  to 3.3VOUT to 5VOUT<br>100<br>95 Pf |tT<br>90 ee<br>85<br>80 fe | 2A/DIV , 2A/DIV |<br>75<br>70 AS 100mV/DIV 100mV/DIV<br>28VIN 15VOUT<br>65 32V IN  15V OUT<br>36VIN 15VOUT<br>60<br>0 1 2 3 4 5 50µs/DIV 4612 G05 50µs/DIV 4612 G06<br>LOAD CURRENT (A) 4612 G04 LOAD STEP: 0A to 3A  LOAD STEP: 0A to 3A<br>COUT = 2 × 22µF CERAMIC CAPACITORS AND  COUT = 2 × 22µF CERAMIC CAPACITORS AND OUT = 2 × 22µF CERAMIC CAPACITORS AND  = 2 × 22µF CERAMIC CAPACITORS AND × 22µF CERAMIC CAPACITORS AND  22µF CERAMIC CAPACITORS AND<br>2 × 47µF CERAMIC CAPACITORS 2 × 47µF CERAMIC CAPACITORS× 47µF CERAMIC CAPACITORS 47µF CERAMIC CAPACITORS<br>EFFICIENCY (%) EFFICIENCY (%) EFFICIENCY (%)<br>EFFICIENCY (%)<br>**----- End of picture text -----**<br>


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2A/DIV<br>100mV/DIV<br>50µs/DIV 4612 G06<br>LOAD STEP: 0A to 3A<br>COUT = 2 × 22µF CERAMIC CAPACITORS AND OUT = 2 × 22µF CERAMIC CAPACITORS AND  = 2 × 22µF CERAMIC CAPACITORS AND × 22µF CERAMIC CAPACITORS AND  22µF CERAMIC CAPACITORS AND<br>2 × 47µF CERAMIC CAPACITORS× 47µF CERAMIC CAPACITORS 47µF CERAMIC CAPACITORS<br>**----- End of picture text -----**<br>


**Transient Response from 24VIN to 12VOUT** 

**Start-Up with 24VIN to 12VOUT at IOUT = 0A** 

**Start-Up with 24VIN to 12VOUT at IOUT = 5A** 

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2A/DIV<br>200mV/<br>DIV<br>50µs/DIV 4612 G07<br>LOAD STEP: 0A to 3A<br>COUT = 2 × 22µF CERAMIC CAPACITORS AND<br>2 × 47µF CERAMIC CAPACITORS<br>**----- End of picture text -----**<br>


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IIN<br>0.2A/DIV<br>VOUT<br>5V/DIV<br>500µs/DIV 4612 G08<br>SOFT-START CAPACITOR: 3.9nF<br>CIN = 3 × 10µF CERAMIC CAPACITORS AND<br>1 × 47µF OSCON CAPACITOR<br>**----- End of picture text -----**<br>


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IIN<br>1A/DIV<br>VOUT<br>5V/DIV<br>500µs/DIV 4612 G09<br>SOFT-START CAPACITOR: 3.9nF<br>CIN = 3 × 10µF CERAMIC CAPACITORS AND<br>1 × 47µF OSCON CAPACITOR<br>**----- End of picture text -----**<br>


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LTM4612 

## **TYPICAL PERFORMANCE CHARACTERISTICS** 

**Start-Up with 24VIN to 12VOUT at IOUT = 5A, TA = –55°C** 

**Short-Circuit with 24VIN to 12VOUT at IOUT = 0A** 

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VOUT 0.2A/DIVIIN<br>5V/DIV<br>VOUT<br>5V/DIV<br>IIN<br>1A/DIV<br>ae 500µs/DIV 4612 G10 50µs/DIV 4612 G11<br>SOFT-START CAPACITOR: 3.9nF  COUT = 2 × 22µF CERAMIC CAPACITORS AND<br>CIN = 3 × 10µF CERAMIC CAPACITORS AND  2 × 47µF CERAMIC CAPACITORS<br>1 × 47µF OSCON CAPACITOR<br>**----- End of picture text -----**<br>


## **VIN to VOUT Step-Down Ratio** 

**Input Ripple** 

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36<br>SEE FREQUENCY ADJUSTMENT SECTION<br>FOR OPERATIONS OUTSIDE THIS REGION<br>30<br>OPERATING REGION<br>24<br>WITH DEFAULT FREQUENCY<br>18<br>12<br>6<br>0<br>3.3 4 6 8 10 12 14 15<br>VOUT (V)<br>4612 G13<br> (V)<br>IN<br>V<br>**----- End of picture text -----**<br>


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50mV/DIV IV VV VV<br>PET tT TT tT<br>PET PLT TT TT 1µs/DIV TT TT TT 4612 G14 |<br>VIN = 24V<br>VOUT = 12V AT 5A RESISTIVE LOAD<br>CIN = 3 × 10µF 50V CERAMIC 1 × 100µF BULK<br>**----- End of picture text -----**<br>


**Short-Circuit with 24VIN to 12VOUT at IOUT = 5A** 

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IIN<br>2A/DIV<br>VOUT<br>5V/DIV<br>20µs/DIV 4612 G12<br>COUT = 2 × 22µF CERAMIC CAPACITORS AND<br>2 × 47µF CERAMIC CAPACITORS<br>Output Ripple<br>PETEPET [TTT] TTT ytTTTT<br>PETE TTT TTT<br>10mV/DIV CARRAVAVAVAVAVAVAVAVAYA AKAMA<br>PETE TTT TT<br>PETEPTT 1µs/DIV T T TTT TTL 4612 G15<br>VIN = 24V<br>VOUT = 12V AT 5A RESISTIVE LOAD<br>COUT = 2 × 22µF 16V CERAMIC AND<br>2 × 47µF 16V CERAMIC<br>**----- End of picture text -----**<br>


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LTM4612 

## **PIN FUNCTIONS (See Package Description for Pin Assignments)** 

**VIN (Bank 1):** Power Input Pins. Apply input voltage between these pins and PGND pins. Recommend placing input decoupling capacitance directly between VIN pins and PGND pins. 

**PGND (Bank 2):** Power Ground Pins for Both Input and Output Returns. 

**VOUT (Bank 3):** Power Output Pins. Apply output load between these pins and PGND pins. Recommend placing output decoupling capacitance directly between these pins and GND pins (see the LTM4612 Pin Configuration below). 

**VD (Pins B7, C7):** Top FET Drain Pins. Add more capacitors between VD and ground to handle the input RMS current and reduce the input ripple further. 

**DRVCC (Pins C10, E11, E12):** These pins normally connect to INTVCC for powering the internal MOSFET drivers. They can be biased up to 6V from an external supply with about 50mA capability. This improves efficiency at higher input voltages by reducing power dissipation in the module. 

**INTVCC (Pin A7):** This pin is for additional decoupling of the 5V internal regulator. 

**PLLIN (Pin A8):** External Clock Synchronization Input to the Phase Detector. This pin is internally terminated to SGND with a 50k resistor. Apply a clock above 2V and below INTVCC. See the Applications Information section. 

**FCB (Pin M12):** Forced Continuous Input. Connect this pin to SGND to force continuous synchronization operation at low load, to INTVCC to enable discontinuous mode operation at low load or to a resistive divider from a secondary output when using a secondary winding. 

**TRACK/SS (Pin A9):** Output Voltage Tracking and Soft-Start Pin. When the module is configured as a master output, then a soft-start capacitor is placed on this pin to ground to control the master ramp rate. A soft-start capacitor can be used for soft-start turn-on as a standalone regulator. Slave operation is performed by putting a resistor divider from the master output to the ground, and connecting the center point of the divider to this pin. See the Applications Information section. 

**MPGM (Pins A12, B11):** Programmable Margining Input. A resistor from these pins to ground sets a current that is equal to 1.18V/R. This current multiplied by 10k will equal a value in millivolts that is a percentage of the 0.6V reference voltage. May be left open if margining is not desired. See the Applications Information section. To parallel LTM4612s, each requires an individual MPGM resistor. Do not tie MPGM pins together. 

**fSET (Pin B12):** Frequency Set Internally to ~850kHz to 900kHz at 12V Output. An external resistor can be placed from this pin to ground to increase frequency. See the Applications Information section for frequency adjustment. 

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TOP VIEW<br>A<br>BANK 1VIN BC VDSGND MARG0fSET<br>D MARG1<br>E DRVCC<br>PGND<br>BANK 2 F VFB<br>G PGOOD<br>H SGND<br>J NC<br>VOUT K NC<br>BANK 3 L NC<br>M FCB<br>1 2 3 4 5 6 7 8 9 10 11 12<br>LGA PACKAGE<br>133-LEAD (15mm × 15mm × 2.8mm)<br>CC<br>INTV PLLIN TRACK/SS RUN COMP MPGM<br>**----- End of picture text -----**<br>


**LTM4612 Pin Configuration** 

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LTM4612 

## **PIN FUNCTIONS** 

**VFB (Pin F12):** The Negative Input of the Error Amplifier. Internally, this pin is connected to VOUT with a 100k 0.5% precision resistor. Different output voltages can be programmed with an additional resistor between the VFB and SGND pins. See the Applications Information section. 

**MARG0 (Pin C12):** LSB Logic Input for the Margining Function. Together with the MARG1 pin, the MARG0 pin will determine if a margin high, margin low, or no margin state is applied. The pin has an internal pull-down resistor of 50k. See the Applications Information section. 

**MARG1 (Pins C11, D12):** MSB Logic Input for the Margining Function. Together with the MARG0 pin, the MARG1 pin will determine if a margin high, margin low, or no margin state is applied. The pins have an internal pull-down resistor of 50k. See the Applications Information section. 

**COMP (Pins A11, D11):** Current Control Threshold and Error Amplifier Compensation Point. The current comparator threshold increases with this control voltage. The voltage ranges from 0V to 2.4V with 0.7V corresponding to zero sense voltage (zero current). 

**PGOOD (Pin G12):** Output Voltage Power Good Indicator. Open-drain logic output that is pulled to ground when the output voltage is not within ±10% of the regulation point, after a 25µs power bad mask timer expires. 

**RUN (Pins A10, B9):** Run Control Pins. A voltage above 1.9V will turn on the module, and below 1V will turn off the module. A programmable UVLO function can be accomplished with a resistor from VIN to this pin that is has a 5.1V zener to ground. Maximum pin voltage is 5V. 

**NC (Pins J12, K12, L12):** No Connect Pins. Leave floating. 

**SGND (Pins D9, H12):** Signal Ground Pins. These pins connect to PGND at output capacitor point. 

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LTM4612 

## **BLOCK DIAGRAM** 

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> 1.9V = ON<br>< 1V = OFF VOUT<br>MAX = 5V RUN INPUT VIN<br>PGOOD 5.1V FILTER + 20V TO 36V<br>ZENER 1µF CIN<br>COMP<br>100k<br>VD<br>INTERNAL<br>COMP CD<br>POWER CONTROL M1<br>SGND<br>2.7µH VOUT<br>MARG1 12V<br>AT 4A<br>MARG0<br>NOISE<br>VFB 50k 50k CANCEL- 10µF<br>+<br>RFB fSET M2 LATION COUT<br>5.23k<br>93.1k<br>PGND<br>FCB<br>10k<br>MPGM<br>TRACK/SS<br>CSS PLLIN<br>4.7µF 50k<br>INTVCC<br>DRVCC 4612 F01<br>**----- End of picture text -----**<br>


**Figure 1. Simplified Block Diagram** 

**DECOUPLING REQUIREMENTS Specifications are at TA = 25°C. Use Figure 1 configuration.** 

|**SYMBOL**|**PARAMETER**|**CONDITIONS**|**CONDITIONS**|**MIN**<br>**TYP**<br>**MAX**|**UNITS**|
|---|---|---|---|---|---|
|CIN|External Input Capacitor Requirement<br>(VIN= 20V to 36V, VOUT= 12V)|IOUT= 4A||20|µF|
|COUT|External Output Capacitor Requirement<br>(VIN= 20V to 36V, VOUT= 12V)|IOUT= 4A||100<br>150|µF|



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LTM4612 

## **OPERATION** 

## **Power Module Description** 

The LTM4612 is a standalone nonisolated switching mode DC/DC power supply. It can deliver 5A of DC output current with some external input and output capacitors. This module provides precisely regulated output voltage programmable via one external resistor from 3.3VDC to 15VDC over a 5V to 36V wide input voltage. The typical application schematic is shown in Figure 18. 

The LTM4612 has an integrated constant on-time current mode regulator, ultralow RDS(ON) FETs with fast switching speed and integrated Schottky diodes. The typical switching frequency is 850kHz at full load at 12V output. With current mode control and internal feedback loop compensation, the LTM4612 module has sufficient stability margins and good transient performance under a wide range of operating conditions and with a wide range of output capacitors, even all ceramic output capacitors. 

Current mode control provides cycle-by-cycle fast current limiting. Moreover, foldback current limiting is provided in an overcurrent condition while VFB drops. Internal overvoltage and undervoltage comparators pull the open-drain PGOOD output low if the output feedback voltage exits a ±10% window around the regulation point. Furthermore, in an overvoltage condition, internal top FET M1 is turned off and bottom FET M2 is turned on and held on until the overvoltage condition clears. 

Input filter and noise cancellation circuitry reduce the noise coupling to I/O sides, and ensure the electromagnetic interference (EMI) meets the limits of EN55022 Class B. 

Pulling the RUN pin below 1V forces the controller into its shutdown state, turning off both M1 and M2. At light load currents, discontinuous mode (DCM) operation can be enabled to achieve higher efficiency compared to continuous mode (CCM) by setting FCB pin higher than 0.6V. 

When the DRVCC pin is connected to INTVCC, an integrated 5V linear regulator powers the internal gate drivers. If a 5V external bias supply is applied on DRVCC pin, then an efficiency improvement will occur due to the reduced power loss in the internal linear regulator. This is especially true at higher input voltages. 

The MPGM, MARG0, and MARG1 pins are used to support output voltage margining, where the percentage of margin is programmed by the MPGM pin, and the MARG0 and MARG1 select margining. The PLLIN pin provides frequency synchronization of the device to an external clock. The TRACK/SS pin is used for power supply tracking and soft-start programming. 

## **APPLICATIONS INFORMATION** 

The typical LTM4612 application circuit is shown in Figure 18. External component selection is primarily determined by the maximum load current and output voltage. Refer to Table 2 for specific external capacitor requirements for a particular application. 

## **VIN to VOUT Stepdown Ratios** 

There are restrictions in the maximum VIN and VOUT step down ratio that can be achieved for a given input voltage. These constraints are shown in the Typical Performance Characteristic curve labeled “VIN to VOUT Step-Down Ratio.” Note that additional thermal derating may be applied. See the Thermal Considerations and Output Current Derating section in this data sheet. 

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LTM4612 

## **APPLICATIONS INFORMATION** 

## **Output Voltage Programming and Margining** 

The PWM controller has an internal 0.6V reference voltage. As shown in the Block Diagram, a 100k internal feedback resistor connects the VOUT and VFB pins together. Adding a resistor, RFB, from the VFB pin to the SGND pin programs the output voltage. 

**==> picture [117 x 30] intentionally omitted <==**

or equivalently, 

**==> picture [72 x 42] intentionally omitted <==**

**Table 1. RFB Standard 1% Resistor Values vs VOUT** 

|**VOUT(V)**|3.3|5|6|8|10|12|14|15|
|---|---|---|---|---|---|---|---|---|
|**RFB (k**W**)**|22.1|13.7|11|8.06|6.34|5.23|4.42|4.12|



The MPGM pin programs a current that when multiplied by an internal 10k resistor sets up the 0.6V reference ± offset for margining. A 1.18V reference divided by the 

RPGM resistor on the MPGM pin programs the current. Calculate V : OUT(MARGIN) 

**==> picture [136 x 26] intentionally omitted <==**

Where %VOUT is the percentage of VOUT to be margined, and VOUT(MARGIN) is the margin quantity in volts: 

**==> picture [158 x 31] intentionally omitted <==**

Where RPGM is the resistor value to place on the MPGM pin to ground. 

The output margining will be ± margining of the value. This is controlled by the MARG0 and MARG1 pins. See the truth table below: 

|**MARG1**|**MARG0**|**MODE**|
|---|---|---|
|LOW|LOW|NO MARGIN|
|LOW|HIGH|MARGIN UP|
|HIGH|LOW|MARGIN DOWN|
|HIGH|HIGH|NO MARGIN|



**Table 2. Output Voltage Response vs Component Matrix (Refer to Figure 20)** 

|**Table 2. Output Voltage Response vs Component Matrix(Refer to Figure 20)**|**Table 2. Output Voltage Response vs Component Matrix(Refer to Figure 20)**|**Table 2. Output Voltage Response vs Component Matrix(Refer to Figure 20)**|**Table 2. Output Voltage Response vs Component Matrix(Refer to Figure 20)**|**Table 2. Output Voltage Response vs Component Matrix(Refer to Figure 20)**|**Table 2. Output Voltage Response vs Component Matrix(Refer to Figure 20)**|**Table 2. Output Voltage Response vs Component Matrix(Refer to Figure 20)**|**Table 2. Output Voltage Response vs Component Matrix(Refer to Figure 20)**|**Table 2. Output Voltage Response vs Component Matrix(Refer to Figure 20)**|**Table 2. Output Voltage Response vs Component Matrix(Refer to Figure 20)**|**Table 2. Output Voltage Response vs Component Matrix(Refer to Figure 20)**|**Table 2. Output Voltage Response vs Component Matrix(Refer to Figure 20)**|**Table 2. Output Voltage Response vs Component Matrix(Refer to Figure 20)**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**TYPICAL MEASURED VALUES**|||||||||||||
|**VENDORS**|||**PART NUMBER**||||**VENDORS**|||**PART NUMBER**|||
|Murata|||GRM32ER61C476KEI5L (47µF, 16V)||||Murata|||GRM32ER71H106K (10µF, 50V)|||
|Murata|||GRM32ER61C226KE20L (22µF, 16V)||||TDK|||C3225X5RIC226M (22µF, 16V)|||
||||||||||||||
|**VOUT**<br>**(V)**|**CIN**<br>**(CERAMIC)**|**CIN**<br>**(BULK)**||**COUT1**<br>**(CERAMIC)**|**COUT2**<br>**(BULK)**|**VIN**<br>**(V)**||**DROOP**<br>**(mV)**|**PEAK-TO-**<br>**PEAK (mV)**|**RECOVERY**<br>**TIME (µs)**|**LOAD STEP**<br>**(A/µs)**|**RFB**<br>**(kΩ)**|
|5|2×10µF 50V|100µF 50V||2×22µF 16V|150µF 25V|12||86|156|26|3|13.7|
|5|2×10µF 50V|100µF 50V||4×47µF 16V|None|12||86|178|14.8|3|13.7|
|5|2×10µF 50V|100µF 50V||2×22µF 16V|150µF 25V|24||83|166|27|3|13.7|
|5|2×10µF 50V|100µF 50V||4×47µF 16V|None|24||86|169|14.8|3|13.7|
|5|2×10µF 50V|100µF 50V||2×22µF 16V|150µF 25V|36||86|178|25|3|13.7|
|5|2×10µF 50V|100µF 50V||4×47µF 16V|None|36||86|172|15.2|3|13.7|
|10|2×10µF 50V|100µF 50V||2×22µF 16V|150µF 25V|24||111|209|30|3|6.34|
|10|2×10µF 50V|100µF 50V||4×47µF 16V|None|24||171|325|35|3|6.34|
|10|2×10µF 50V|100µF 50V||2×22µF 16V|150µF 25V|36||108|197|35|3|6.34|
|10|2×10µF 50V|100µF 50V||4×47µF 16V|None|36||153|288|39|3|6.34|
|12|2×10µF 50V|100µF 50V||2×22µF 16V|150µF 25V|24||153|281|37|3|5.23|
|12|2×10µF 50V|100µF 50V||4×47µF 16V|None|36||184|375|34.4|3|5.23|
|15|2×10µF 50V|100µF 50V||2×22µF 16V|150µF 25V|28||178|338|70|3|4.12|
|15|2×10µF 50V|100µF 50V||4×47µF 16V|None|36||134|250|70|3|4.12|



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LTM4612 

## **APPLICATIONS INFORMATION** 

## **Operating Frequency** 

The operating frequency of the LTM4612 is optimized to achieve the compact package size and the minimum output ripple voltage while still providing high efficiency. As shown in Figure 2, the frequency is linearly increased with larger output voltages to keep the low output current ripple. Figure 3 shows the inductor current ripple DI with different output voltages. In most applications, no additional frequency adjusting is required. 

If lower output ripple is required, the operating frequency f can be increased by adding a resistor RfSET between fSET pin and SGND, as shown in Figure 19. 

**==> picture [138 x 34] intentionally omitted <==**

**==> picture [163 x 150] intentionally omitted <==**

**----- Start of picture text -----**<br>
1200<br>1000<br>800<br>600<br>400<br>200<br>2 4 6 8 10 12 14 16<br>VOUT (V) 4612 F02<br>FREQUENCY (kHz)<br>**----- End of picture text -----**<br>


**Figure 2. Operating Frequency vs Output Voltage** 

For output voltages more than 12V, the frequency can be higher than 1MHz, thus reducing the efficiency significantly. Additionally, the 500ns minimum off time (400ns + 100ns for margin) normally limits the operation when the input voltage is close to the output voltage. Therefore, it is recommended to lower the frequency in these conditions by connecting a resistor (RfSET) from the fSET pin to VIN, as shown in Figure 20. 

**==> picture [146 x 50] intentionally omitted <==**

The load current can affect the frequency due to its constant on-time control. If constant frequency is a necessity, the PLLIN pin can be used to synchronize the frequency of the LTM4612 to an external clock, as shown in Figures 21 to 23. 

**==> picture [153 x 148] intentionally omitted <==**

**----- Start of picture text -----**<br>
3.5<br>3.0<br>VIN = 36V<br>2.5<br>2.0<br>VIN = 28V<br>VIN = 20V<br>1.5<br>1.0<br>0.5<br>2 4 6 8 10 12 14 16<br>VOUT (V) 4612 F03<br>INDUCTOR CURRENT RIPPLE ∆I (A)<br>**----- End of picture text -----**<br>


**Figure 3. Inductor Current Ripple vs Output Voltage** 

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LTM4612 

## **APPLICATIONS INFORMATION** 

## **Input Capacitors** 

LTM4612 is designed to achieve the low input radiated EMI noise due to the fast switching of turn-on and turn-off. In the LTM4612, a high-frequency inductor is integrated into the input line for noise attenuation. VD and VIN pins are available for external input capacitors to form a high frequency π filter. As shown in Figure 18, the ceramic capacitor C1 on the VD pins is used to handle most of the RMS current into the converter, so careful attention is needed for capacitor C1 selection. 

For a buck converter, the switching duty cycle can be estimated as: 

**==> picture [42 x 31] intentionally omitted <==**

Without considering the inductor current ripple, the RMS current of the input capacitor can be estimated as: 

**==> picture [158 x 36] intentionally omitted <==**

In this equation, h is the estimated efficiency of the power module. Note the capacitor ripple current ratings are often based on temperature and hours of life. This makes it advisable to properly derate the input capacitor, or choose a capacitor rated at a higher temperature than required. Always contact the capacitor manufacturer for derating requirements. 

To attenuate the high frequency noise, extra input capacitors should be connected to the VIN pads and placed before the high frequency inductor to form the π filter. One of these low ESR ceramic input capacitors is recommended to be close to the connection into the system board. A large bulk 100µF capacitor is only needed if the input source impedance is compromised by long inductive leads or traces. Figure 4 shows the radiated EMI test results to meet the EN55022 Class B limit. For different applications, input capacitance may be varied to meet different radiated EMI limits. 

**==> picture [163 x 164] intentionally omitted <==**

**----- Start of picture text -----**<br>
70<br>60<br>50<br>40 cece EN55022 CLASS B LIMIT<br>30 P|Pr<br>20<br>EPLaeeess<br>10<br>Wid | ET |<br>0<br>–10<br>30 226.2 422.4 618.6 814.8 1010<br>128.1 324.3 520.5 716.7 912.9<br>FREQUENCY (MHz) 4612 F04<br>dBµV/m<br>**----- End of picture text -----**<br>


**Figure 4. Radiated Emission Scan with 24VIN to 5VOUT at 5A (2** × **10µF Ceramic Capacitors on VIN Pads and 1** × **10µF Ceramic Capacitor on VD Pads)** 

In a typical 5A output application, one very low ESR, X5R or X7R, 10µF ceramic capacitor is recommended for C1. This decoupling capacitor should be placed directly adjacent to the module VD pins in the PCB layout to minimize the trace inductance and high frequency AC noise. Each 10µF ceramic is typically good for 2A to 3A of RMS ripple current. Refer to your ceramics capacitor catalog for the RMS current ratings. 

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LTM4612 

## **APPLICATIONS INFORMATION** 

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**----- Start of picture text -----**<br>
1.00<br>0.95 1-PHASE<br>2-PHASE<br>0.90<br>3-PHASE<br>0.85 4-PHASE<br>6-PHASE<br>0.80<br>0.75<br>0.70<br>0.65<br>0.60<br>0.55<br>0.50<br>0.45<br>0.40<br>0.35<br>0.30<br>0.25<br>0.20<br>0.15<br>0.10<br>0.05<br>0<br>0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9<br>DUTY CYCLE (VO/VIN) 4612 F05<br>DIr<br>PEAK-TO-PEAK OUTPUT RIPPLE CURRENT<br>RATIO =<br>**----- End of picture text -----**<br>


**Figure 5. Normalized Output Ripple Current vs Duty Cycle, Dlr = VOT/LI** 

## **Output Capacitors** 

The LTM4612 is designed for low output voltage ripple. The bulk output capacitors defined as COUT are chosen with low enough effective series resistance (ESR) to meet the output voltage ripple and transient requirements. COUT can be low ESR tantalum capacitor, low ESR polymer capacitor or ceramic capacitor. The typical capacitance is 150µF if all ceramic output capacitors are used. Additional output filtering may be required by the system designer, if further reduction of output ripple or dynamic transient spike is required. Table 2 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 2A/µs transient. The table optimizes total equivalent ESR and total bulk capacitance to maximize transient performance. 

Multiphase operation with multiple LTM4612 devices in parallel will also lower the effective output ripple current due to the phase interleaving operation. Refer to Figure 5 for the normalized output ripple current versus the duty 

cycle. Figure 5 provides a ratio of peak-to-peak output ripple current to the inductor ripple current as functions of duty cycle and the number of paralleled phases. Pick the corresponding duty cycle and the number of phases to get the correct output ripple current value. For example, each phase’s inductor ripple current DIr at zero duty cycle is ~4.3A for a 36V to 12V design. The duty cycle is about 0.33. The 2-phase curve has a ratio of ~0.33 for a duty cycle of 0.33. This 0.33 ratio of output ripple current to the inductor ripple current DIr at 4.3A equals 1.4A of the output ripple current (DIL). 

The output voltage ripple has two components that are related to the amount of bulk capacitance and effective series resistance (ESR) of the output bulk capacitance. The equation is: 

**==> picture [255 x 67] intentionally omitted <==**

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LTM4612 

## **APPLICATIONS INFORMATION** 

## **Fault Conditions: Current Limit and Overcurrent Foldback** 

LTM4612 has a current mode controller, which inherently limits the cycle-by-cycle inductor current not only in steady state operation, but also in transient. 

To further limit current in the event of an overload condition, the LTM4612 provides foldback current limiting. If the output voltage falls by more than 50%, then the maximum output current is progressively lowered to about one sixth of its full current limit value. 

## **Soft-Start and Tracking** 

The TRACK/SS pin provides a means to either soft-start the regulator or track it to a different power supply. A capacitor on this pin will program the ramp rate of the output voltage. A 1.5µA current source will charge up the external soft-start capacitor to 80% of the 0.6V internal voltage reference plus or minus any margin delta. This will control the ramp of the internal reference and the output voltage. The total soft-start time can be calculated as: 

tSOFTSTART ≅ 0.8 • (0.6 ± 0.6 • VOUT Margin %)[•][C][SS] 1.5µA 

If the RUN pin falls below 2.5V, then the soft-start pin is reset to allow for the proper soft-start again. Current foldback and force continuous mode are disabled during the soft-start process. The soft-start function can also be used to control the output ramp rising time, so that another regulator can be easily tracked. 

**==> picture [252 x 169] intentionally omitted <==**

**----- Start of picture text -----**<br>
VIN<br>100k 10µF<br>VD VIN PLLIN SLAVE<br>PGOOD VOUT OUTPUT<br>RUN VFB COUT<br>CIN COMP FCB<br>LTM4612<br>INTVCC MARG0<br>MASTER<br>OUTPUT DRVCC MARG1<br>R2<br>100k fSET MPGM<br>TRACK TRACK/SS RFB<br>CONTROL R1 SGND PGND 5.23k<br>5.23k<br>4612 F06<br>**----- End of picture text -----**<br>


**Figure 6. Coincident Tracking** 

## **Output Voltage Tracking** 

Output voltage tracking can be programmed externally using the TRACK/SS pin. The output can be tracked up and down with another regulator. Figure 6 shows an example of coincident tracking where the master regulator’s output is divided down with an external resistor divider that is the same as the slave regulator’s feedback divider. Ratiometric modes of tracking can be achieved by selecting different resistor values to change the output tracking ratio. The master output must be greater than the slave output for the tracking to work. Figure 7 shows the coincident output tracking. 

Tracking can be achieved by a few simple calculations and the slew rate value applied to the master’s TRACK pin. The TRACK pin has a control range from 0 to 0.6V. The master’s TRACK pin slew rate is directly equal to the master’s output slew rate in Volts/Time. The equation: 

**==> picture [75 x 28] intentionally omitted <==**

where MR is the master’s output slew rate and SR is the slave’s output slew rate in Volts/Time. When coincident tracking is desired, then MR and SR are equal, thus R2 is equal the 100k. R1 is derived from equation: 

**==> picture [179 x 242] intentionally omitted <==**

**Figure 7. Coincident Output Tracking** 

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LTM4612 

## **APPLICATIONS INFORMATION** 

where VFB is the feedback voltage reference of the regulator, and VTRACK is 0.6V. Since R2 is equal to the 100k top feedback resistor of the slave regulator in equal slew rate or coincident tracking, then R1 is equal to RFB with VFB = VTRACK. Therefore R2 = 100k, and R1 = 5.23k in Figure 6. 

In ratiometric tracking, a different slew rate maybe desired for the slave regulator. R2 can be solved for when SR is slower than MR. Make sure that the slave supply slew rate is chosen to be fast enough so that the slave output voltage will reach it final value before the master output. 

For example, MR = 1.5V/1ms, and SR = 1.2V/1ms. Then R2 = 125k. Solve for R1 to equal to 5.18k. 

Each of the TRACK pins will have the 1.5µA current source on when a resistive divider is used to implement tracking on that specific channel. This will impose an offset on the TRACK pin input. Smaller values resistors with the same ratios as the resistor values calculated from the above equation can be used. For example, where the 100k is used then a 10k can be used to reduce the TRACK pin offset to a negligible value. 

## **RUN Enable** 

The RUN pin is used to enable the power module. The pin has an internal 5.1V Zener to ground. The pin can be driven with 5V logic levels. 

The RUN pin can also be used as an undervoltage lockout (UVLO) function by connecting a resistor divider from the input supply to the RUN pin. The equation for UVLO threshold: 

**==> picture [110 x 30] intentionally omitted <==**

where RA is the top resistor, and RB is the bottom resistor. 

## **Power Good** 

The PGOOD pin is an open-drain pin that can be used to monitor valid output voltage regulation. This pin monitors a ±10% window around the regulation point, and tracks with margining. 

## **COMP Pin** 

The pin is the external compensation pin. The module has already been internally compensated for most output voltages. LTpowerCAD™ from Linear Technology is available for more control loop optimization. 

## **FCB Pin** 

The FCB pin determines whether the bottom MOSFET remains on when current reverses in the inductor. Tying this pin above its 0.6V threshold enables discontinuous operation where the bottom MOSFET turns off when inductor current reverses. FCB pin below the 0.6V threshold forces continuous synchronous operation, allowing current to reverse at light loads and maintaining high frequency operation. 

## **PLLIN Pin** 

The power module has a phase-locked loop comprised of an internal voltage controlled oscillator and a phase detector. This allows the internal top MOSFET turn-on to be locked to the rising edge of the external clock. The frequency range is ±30% around the set operating frequency. A pulse detection circuit is used to detect a clock on the PLLIN pin to turn on the phase-locked loop. The pulse width of the clock has to be at least 400ns. The clock high level must be greater than 1.7V and clock low level below 0.3V. During the start-up of the regulator, the phase-locked loop function is disabled. 

## **INTVCC and DRVCC Connection** 

An internal low dropout regulator produces an internal 5V supply that powers the control circuitry and DRVCC for driving the internal power MOSFETs. Therefore, if the system does not have a 5V power rail, the LTM4612 can be directly powered by VIN. The gate driver current through the LDO is about 20mA. The internal LDO power dissipation can be calculated as: 

PLDO_LOSS = 20mA • (VIN – 5V) 

The LTM4612 also provides the external gate driver voltage pin DRVCC. If there is a 5V rail in the system, it is recommended to connect the DRVCC pin to the external 5V rail. This is especially true for higher input voltages. Do not apply more than 6V to the DRVCC pin. 

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LTM4612 

## **APPLICATIONS INFORMATION** 

## **Parallel Operation** 

The LTM4612 device is an inherently current mode controlled device. This allows the paralleled modules to have very good current sharing and balanced thermal on the design. Figure 21 shows a schematic of the parallel design. The voltage feedback equation changes with the variable N as modules are paralleled. The equation: 

**==> picture [73 x 56] intentionally omitted <==**

N is the number of paralleled modules. 

## **Radiated EMI Noise** 

High radiated EMI noise is a disadvantage for switching regulators by nature. Fast switching turn-on and turn-off make the large di/dt change in the converters, which act as the radiation sources in most systems. LTM4612 integrates the feature to minimize the radiated EMI noise to meet the most applications with low noise requirements. An optimized gate driver for the MOSFET and a noise cancellation network are installed inside the LTM4612 to achieve the low radiated EMI noise. Figure 8 shows a typical example for the LTM4612 to meet the Class B of EN55022 radiated emission limit. 

**==> picture [163 x 163] intentionally omitted <==**

**----- Start of picture text -----**<br>
70<br>60<br>PT [TTT] TT yt<br>50 SRREREEEee<br>40 SERRaReaae EN55022 CLASS B LIMIT<br>30 ||Po<br>20<br>BPaeeess<br>10 vie<br>0 Pitt<br>–10<br>PLT [TET] eT T TY t<br>30 226.2 422.4 618.6 814.8 1010<br>128.1 324.3 520.5 716.7 912.9<br>FREQUENCY (MHz) 4612 F08<br>dBµV/m<br>**----- End of picture text -----**<br>


## **Thermal Considerations and Output Current Derating** 

In different applications, LTM4612 operates in a variety of thermal environments. The maximum output current is limited by the environment thermal condition. Sufficient cooling should be provided to help ensure reliable operation. When the cooling is limited, proper output current derating is necessary, considering ambient temperature, airflow, input/output condition, and the need for increased reliability. 

The power loss curves in Figures 9 and 10 can be used in coordination with the load current derating curves in Figures 11 to 16 for calculating an approximate θJA for the module. Graph designation delineates between no heat sink, and a BGA heat sink. Each of the load current derating curves will lower the maximum load current as a function of the increased ambient temperature to keep the maximum junction temperature of the power module at 125°C maximum. This will maintain the maximum operating temperature below 125°C. Each of the derating curves and the power loss curve that corresponds to the correct output voltage can be used to solve for the approximate θJA of the condition. Each figure has three curves that are taken at three different air flow conditions. Each of the derating curves in Figures 11 to 16 can be used with the appropriate power loss curve in either Figure 9 or Figure 10 to derive an approximate θJA. Table 3 provides the approximate θJA for Figures 11 to 16. A complete explanation of the thermal characteristics is provided in the thermal application note, AN110. 

**Figure 8. Radiated Emission Scan with 24VIN to 5VOUT at 5A Measured in 10 Meter Chamber** 

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## LTM4612 

## **APPLICATIONS INFORMATION** 

**==> picture [517 x 597] intentionally omitted <==**

**----- Start of picture text -----**<br>
6 6 5.0<br>200<br>4.5 LFM<br>5 5<br>4.0<br>36VIN TO 15VOUT 0LFM 400LFM<br>3.5<br>4 4<br>3.0<br>36VIN TO 5VOUT<br>3 3 2.5<br>24VIN TO 12VOUT 2.0<br>2 2<br>1.5<br>1.0<br>1 1<br>0.5<br>0 0 0<br>0 1 2 3 4 5 0 1 2 3 4 5 25 35 45 55 65 75 85 95 105<br>LOAD CURRENT (A) 4612 F09 LOAD CURRENT (A) 4612 F10 AMBIENT TEMPERATURE (°C)<br>4612 F11<br>Figure 9. Power Loss at  Figure 10. Power Loss at 5VOUT Figure 11. No Heat Sink<br>12VOUT and 15VOUT with 36VIN to 5VOUT<br>5.0 5.0 5.0<br>200 200 200<br>4.5 LFM 4.5 LFM 4.5 LFM<br>4.0 4.0 4.0<br>0LFM 400LFM 0LFM 400LFM 0LFM 400LFM<br>3.5 3.5 3.5<br>3.0 3.0 3.0<br>2.5 2.5 2.5<br>2.0 2.0 2.0<br>1.5 1.5 1.5<br>1.0 1.0 1.0<br>0.5 0.5 0.5<br>0 0 0<br>25 35 45 55 65 75 85 95 105 25 35 45 55 65 75 85 95 105 25 35 45 55 65 75 85 95 105<br>AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)<br>4612 F12 4612 F13 4612 F14<br>Figure 12. BGA Heat Sink  Figure 13. No Heat Sink  Figure 14. BGA Heat Sink<br>with 36VIN to 5VOUT with 24VIN to 12VOUT with 24VIN to 12VOUT<br>5.0 5.0<br>4.5 4.5<br>4.0 4.0<br>0LFM 200LFM 400LFM 0LFM 200LFM 400LFM<br>3.5 3.5<br>3.0 3.0<br>2.5 2.5<br>2.0 2.0<br>1.5 1.5<br>1.0 1.0<br>0.5 0.5<br>0 0<br>25 35 45 55 65 75 85 95 25 35 45 55 65 75 85 95<br>AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)<br>4612 F15 4612 F16<br>POWER LOSS (W) POWER LOSS (W) LOAD CURRENT (A)<br>LOAD CURRENT (A) LOAD CURRENT (A) LOAD CURRENT (A)<br>LOAD CURRENT (A) LOAD CURRENT (A)<br>**----- End of picture text -----**<br>


**Figure 15. No Heat Sink with 36VIN to 15VOUT** 

**Figure 16. BGA Heat Sink with 36VIN to 15VOUT** 

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LTM4612 

## **APPLICATIONS INFORMATION** 

**Table 3. 12V and 15V Outputs** 

|**DERATING CURVE**|**VIN (V)**|**POWER LOSS CURVE**|**AIR FLOW (LFM)**|**HEAT SINK**|θ**JA (°C/W)**|
|---|---|---|---|---|---|
|Figures 11, 13, 15|24, 36|Figure 9|0|None|13|
|Figures 11, 13, 15|24, 36|Figure 9|200|None|9.3|
|Figures 11, 13, 15|24, 36|Figure 9|400|None|8.3|
|Figures 12, 14, 16|24, 36|Figure 9|0|BGA Heat Sink|12.2|
|Figures 12, 14, 16|24, 36|Figure 9|200|BGA Heat Sink|8.6|
|Figures 12, 14, 16|24, 36|Figure 9|400|BGA Heat Sink|7.7|



**Table 4. 5V Output** 

|**Table 4. 5V Output**||||||
|---|---|---|---|---|---|
|**DERATING CURVE**|**VIN (V)**|**POWER LOSS CURVE**|**AIR FLOW (LFM)**|**HEAT SINK**|θ**JA (°C/W)**|
|Figure 11|36|Figure 10|0|None|14.9|
|Figure 11|36|Figure 10|200|None|11.1|
|Figure 11|36|Figure 10|400|None|10|
|Figure 12|36|Figure 10|0|BGA Heat Sink|14|
|Figure 12|36|Figure 10|200|BGA Heat Sink|10.4|
|Figure 12|36|Figure 10|400|BGA Heat Sink|9.3|



## **Heat Sink Manufacturer** 

Wakefield Engineering Part No: LTN20069 Phone: 603-635-2800 

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LTM4612 

## **APPLICATIONS INFORMATION** 

## **Safety Considerations** 

The LTM4612 modules do not provide isolation from VIN to VOUT. There is no internal fuse. If required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure. 

## **Layout Checklist/Example** 

The high integration of LTM4612 makes the PCB board layout very simple and easy. However, to optimize its electrical and thermal performance, some layout considerations are still necessary. 

- Use large PCB copper areas for high current path, including VIN, PGND and VOUT. It helps to minimize the PCB conduction loss and thermal stress. 

- Place high frequency ceramic input and output capacitors next to the VD, PGND and VOUT pins to minimize high frequency noise. 

- Place a dedicated power ground layer underneath the unit. 

- Use round corners for the PCB copper layer to minimize the radiated noise. 

- To minimize the EMI noise and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers. 

- Do not put vias directly on pads. 

- If vias are placed onto the pads, the the vias must be capped. 

- Interstitial via placement can also be used if necessary. 

- Use a separated SGND ground copper area for components connected to signal pins. Connect the SGND to PGND underneath the unit. 

- Place one or more high frequency ceramic capacitors close to the connection into the system board. 

Figure 17 gives a good example of the recommended layout. 

**==> picture [239 x 142] intentionally omitted <==**

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VIN CIN CIN<br>GND<br>SIGNAL<br>GND<br>COUT COUT<br>VOUT<br>4612 F17<br>**----- End of picture text -----**<br>


**Figure 17. Recommended PCB Layout** 

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LTM4612 

## **APPLICATIONS INFORMATION** 

**==> picture [434 x 437] intentionally omitted <==**

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PULL-UP SUPPLY ≤ 5V<br>VIN CLOCK SYNC<br>22V TO 36V C1<br>10µF<br>50V<br>R5 R4 R3<br>2M 100k 100k VD VIN PLLIN VOUT<br>PGOOD VOUT 12V<br>C3<br>ON/OFF RUN LTM4612 22pF COUT1 + COUT2 5A<br>COMP VFB 22µF 220µF<br>RFB 16V 16V<br>INTVCC 5.23k<br>DRVCC FCB<br>10µFCIN fTRACK/SSSET MARG0MARG1 MARGINCONTROL REFER TO TABLE 2<br>50V CERAMIC MPGM<br>C4 SGND PGND R1<br>0.01µF 392k<br>5% MARGIN<br>4612 F18<br>Figure 18. Typical 22V to 36VIN, 12V at 5A Design<br>PULL-UP SUPPLY ≤ 5V<br>VIN CLOCK SYNC<br>5V TO 36V<br>C1<br>10µF<br>50V<br>R4 R3<br>100k 100k VD VIN PLLIN VOUT<br>PGOOD VOUT 3.3V<br>RUN C322pF COUT1 + COUT2 5A<br>CIN ON/OFF C OMP LTM4612 VFB RFB 22µF6.3V 220µF6.3V<br>10µF IN TVCC 22.1k<br>50V CERAMIC FCB<br>EXTERNAL 5V SUPPLY DRVCC<br>IMPROVES EFFICIENCY— fSET MARG0 MARGIN REFER TO TABLE 2<br>ESPECIALLY FOR HIGHINPUT VOLTAGES RfSET TRACK/SS MARG1 CONTROL<br>191k MPGM<br>1% SGND PGND R1<br>C4<br>392k<br>0.01µF 5% MARGIN<br>4612 F19<br>**----- End of picture text -----**<br>


**Figure 19. Typical 5V to 36VIN, 3.3V at 5A Design with 400kHz Frequency** 

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LTM4612 

## **APPLICATIONS INFORMATION** 

**==> picture [395 x 184] intentionally omitted <==**

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PULL-UP SUPPLY ≤ 5V<br>VIN CLOCK SYNC<br>26V TO 36V C1<br>10µF<br>50V<br>R4 R3<br>100k 100k VD VIN PLLIN VOUT<br>PGOOD VOUT 15V<br>ON/OFF RUN LTM4612 C322pF COUT1 + COUT2 4A<br>COMP VFB 22µF 220µF<br>RFB 16V 16V<br>RfSET INTVCC 4.12k<br>806k, 1% DRVCC FCB<br>fSET MARG0 MARGIN<br>TRACK/SS MARG1 CONTROL<br>CIN MPGM<br>10µF<br>50V  C4 SGND PGND R1<br>CERAMIC 392k<br>0.01µF 5% MARGIN<br>4612 F20<br>**----- End of picture text -----**<br>


**Figure 20. 26V to 36VIN, 15V at 4A Design with Reduced Frequency** 

**==> picture [529 x 338] intentionally omitted <==**

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PULL-UP SUPPLY ≤ 5V<br>VIN<br>20V TO 36V<br>C1<br>10µF CLOCK SYNC<br>R4100k R2100k VD 50V VIN PLLIN0° PHASE V12V, 10AOUT<br>PGOOD VOUT<br>LTM4612 C6<br>RUN<br>47pF C3 + C4<br>COMP VFB 22µF 220µF<br>INTVCC FCB 16V 16V<br>C2 DRVCC<br>10µF<br>50V fSET MARG0 MARGIN<br>TRACK/SS MARG1 CONTROL<br>+ C5 C7 MPGM<br>100µF 0.33µF SGND PGND R1 RFB<br>2-PHASE 50V 392k 2.61k<br>OSCILLATOR<br>5% MARGIN<br>V [+] OUT1<br>100k/N<br>124kR5 C110.1µF GNDSET OUT2MOD C11 RFB = V0.6VOUT [– 1]<br>LTC6908-1 10µF CLOCK SYNC<br>50V 180° PHASE<br>VD VIN PLLIN<br>PGOOD VOUT<br>LTM4612<br>RUN<br>C9 + C10<br>COMP VFB 22µF 220µF<br>C8 INTVCC FCB 16V 16V<br>10µF<br>50V<br>DRVCC MARG0<br>fSET MARG1<br>TRACK/SS MPGM<br>SGND PGND R6<br>392k<br>4612 F21<br>**----- End of picture text -----**<br>


**Figure 21. 2-Phase, Parallel 12V at 10A Design** 

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LTM4612 

## **APPLICATIONS INFORMATION** 

**==> picture [510 x 352] intentionally omitted <==**

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PULL-UP SUPPLY ≤ 5V<br>VIN<br>22V TO 36V<br>C1<br>10µF CLOCK SYNC<br>50V 0° PHASE<br>R4 R2<br>100k 100k VD VIN PLLIN<br>12V AT 5A<br>PGOOD VOUT<br>RUN LTM4612 C622pF C322µF + C4<br>COMP VFB 16V 220µF<br>16V<br>INTVCC FCB<br>C2 DRVCC<br>10µF fSET MARG0 MARGIN<br>+ C5 50V TRACK/SS MARG1 CONTROL<br>100µF MPGM<br>50V C7 SGND PGND R1 RFB1<br>0.15µF 392k 5.23k<br>2-PHASE<br>OSCILLATOR 5% MARGIN<br>V [+] OUT1 PULL-UP SUPPLY ≤ 5V<br>R5 C11 GND OUT2<br>118k 0.1µF SET MOD<br>C11<br>LTC6908-1 10µF CLOCK SYNC<br>R7 50V 180° PHASE<br>R3100k 100k VD VIN PLLIN 10V AT 5A<br>PGOOD VOUT<br>RUN LTM4612 C1 C9 + C10<br>22pF 22µF<br>COMP VFB 16V 220µF<br>16V<br>12V TRACK INTVCC FCB<br>C8 R8 DRVCC MARG0 MARGIN<br>10µF 100k fSET MARG1 CONTROL<br>50V TRACK/SS MPGM<br>R9 SGND PGND R6 RFB2<br>6.34k 392k 6.34k<br>4612 F22<br>**----- End of picture text -----**<br>


**Figure 22. 2-Phase, 12V and 10V at 5A Design** 

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LTM4612 

## **APPLICATIONS INFORMATION** 

**==> picture [482 x 361] intentionally omitted <==**

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5V<br>VIN<br>7V TO 36V<br>C1<br>10µF CLOCK SYNC<br>50V 0° PHASE<br>R4 R2<br>100k 100k VD VIN PLLIN 5V AT 5A<br>PGOOD VOUT<br>C6<br>RUN LTM4612 22pF C3 + C4<br>COMP VFB 22µF 220µF<br>INTVCC 6.3V 6.3V<br>C2<br>FCB<br>10µF<br>50V DRVCC<br>fSET MARG0 MARGIN<br>+ C5 TRACK/SS MARG1 CONTROL<br>100µF R150kfSET1 MPGM<br>50V C7 SGND PGND R1 RFB1<br>0.15µF 392k 13.7k<br>2-PHASE<br>OSCILLATOR 5% MARGIN<br>V [+] OUT1 3.3V<br>R5 C11 GND OUT2<br>200k 0.1µF SET MOD<br>C11<br>LTC6908-1 10µF CLOCK SYNC<br>R7 50V 180° PHASE<br>R3100k 100k VD VIN PLLIN 3.3V AT 5A<br>PGOOD VOUT<br>C1<br>RUN 22pF C9 + C10<br>COMP LTM4612 VFB 22µF 220µF<br>5V TRACK INTVCC FCB 6.3V 6.3V<br>C8 R8 DRVCC MARG0 MARGIN<br>10µF 100k fSET MARG1 CONTROL<br>50V TRACK/SS MPGM<br>R9 RfSET2 SGND PGND R6 RFB2<br>22.1k 100k 392k 22.1k<br>4612 F23<br>**----- End of picture text -----**<br>


**Figure 23. 2-Phase, 5V and 3.3V at 5A Design with 500kHz Frequency** 

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LTM4612 

## **PACKAGE DESCRIPTION** 

## **Pin Assignment Tables (Arranged by Pin Function)** 

|**PIN NAME**<br>A1<br>A2<br>A3<br>A4<br>A5<br>A6<br>VIN<br>VIN<br>VIN<br>VIN<br>VIN<br>VIN<br>B1<br>B2<br>B3<br>B4<br>B5<br>B6<br>VIN<br>VIN<br>VIN<br>VIN<br>VIN<br>VIN<br>C1<br>C2<br>C3<br>C4<br>C5<br>C6<br>VIN<br>VIN<br>VIN<br>VIN<br>VIN<br>VIN|**PIN NAME**<br>D1<br>D2<br>D3<br>D4<br>D5<br>D6<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>E1<br>E2<br>E3<br>E4<br>E5<br>E6<br>E7<br>E8<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>F1<br>F2<br>F3<br>F4<br>F5<br>F6<br>F7<br>F8<br>F9<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>G1<br>G2<br>G3<br>G4<br>G5<br>G6<br>G7<br>G8<br>G9<br>G10<br>G11<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>H1<br>H2<br>H3<br>H4<br>H5<br>H6<br>H7<br>H8<br>H9<br>H10<br>H11<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND|**PIN NAME**<br>D1<br>D2<br>D3<br>D4<br>D5<br>D6<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>E1<br>E2<br>E3<br>E4<br>E5<br>E6<br>E7<br>E8<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>F1<br>F2<br>F3<br>F4<br>F5<br>F6<br>F7<br>F8<br>F9<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>G1<br>G2<br>G3<br>G4<br>G5<br>G6<br>G7<br>G8<br>G9<br>G10<br>G11<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>H1<br>H2<br>H3<br>H4<br>H5<br>H6<br>H7<br>H8<br>H9<br>H10<br>H11<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND|**PIN NAME**<br>J1<br>J2<br>J3<br>J4<br>J5<br>J6<br>J7<br>J8<br>J9<br>J10<br>J11<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>K1<br>K2<br>K3<br>K4<br>K5<br>K6<br>K7<br>K8<br>K9<br>K10<br>K11<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>L1<br>L2<br>L3<br>L4<br>L5<br>L6<br>L7<br>L8<br>L9<br>L10<br>L11<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>M1<br>M2<br>M3<br>M4<br>M5<br>M6<br>M7<br>M8<br>M9<br>M10<br>M11<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT<br>VOUT|**PIN NAME**|**PIN NAME**|
|---|---|---|---|---|---|
||D1<br>D2<br>D3<br>D4<br>D5<br>D6|PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND||A7<br>A8<br>A9<br>A10<br>A11<br>A12|INTVCC<br>PLLIN<br>TRACK/SS<br>RUN<br>COMP<br>MPGM|
||E1<br>E2<br>E3<br>E4<br>E5<br>E6<br>E7<br>E8|PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND||B7<br>B8<br>B9<br>B10<br>B11<br>B12|VD<br>-<br>RUN<br>-<br>MPGM<br>fSET|
|||||C7<br>C8<br>C9<br>C10<br>C11<br>C12|VD<br>-<br>-<br>DRVCC<br>MARG1<br>MARG0|
||F1<br>F2<br>F3<br>F4<br>F5<br>F6<br>F7<br>F8<br>F9|PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND||||
|||||D7<br>D8<br>D9<br>D10<br>D11<br>D12|-<br>-<br>SGND<br>-<br>COMP<br>MARG1|
||G1<br>G2<br>G3<br>G4<br>G5<br>G6<br>G7<br>G8<br>G9<br>G10<br>G11|PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND||||
|||||E9<br>E10<br>E11<br>E12|-<br>-<br>DRVCC<br>DRVCC|
|||||F10<br>F11<br>F12|-<br>-<br>VFB|
|||||G12|PGOOD|
|||||H12|SGND|
||H1<br>H2<br>H3<br>H4<br>H5<br>H6<br>H7<br>H8<br>H9<br>H10<br>H11|PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND<br>PGND||||
|||||J12|NC|
|||||K12|NC|
|||||L12|NC|
|||||M12|FCB|
|||||||



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LTM4612 

## **PACKAGE DESCRIPTION** 

## **Please refer to http://www.linear.com/product/LTM4612#packaging for the most recent package drawings.** 

**==> picture [470 x 613] intentionally omitted <==**

**----- Start of picture text -----**<br>
7<br>SEE NOTES<br>C(0.30) PAD 1<br>12 11 10 9 8 7 6 5 4 3 2 1<br>DETAIL A BA<br>LGA 133 1212 REV A<br>C<br>D<br>E<br>13.97 BSC F<br>G<br>H µModule<br>LTMXXXXXX<br>PACKAGE BOTTOM VIEW<br>J PACKAGE IN TRAY LOADING ORIENTATION<br>K<br>L<br>M COMPONENT PIN “A1” TRAY PIN 1 BEVEL<br>1.27 BSC<br>13.97 BSC PADS 3<br>0.12 – 0.28 SEE NOTES<br> 2.82mm)<br>× 2.72 – 2.92 DETAIL B<br> 15mm<br>×<br>0.27 – 0.37 Y<br>X<br>LGA Package SUBSTRATE S<br>eee<br>MOLD CAP DETAIL B 0.10 0.10 0.05<br>DETAIL A TOLERANCE<br>PACKAGE ROW AND COLUMN LABELING MAY VARY  AMONG µModule PRODUCTS. REVIEW EACH PACKAGE  LAYOUT CAREFULLY<br>133-Lead (15mm  (Reference LTC DWG # 05-08-1766 Rev A) !<br>DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR  MARKED FEATURE aaa bbb eee<br>0.630 ±0.025 SQ. 133x<br>2.45 – 2.55 aaa  Z NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS 3        LAND DESIGNATION PER JESD MO-222, SPP-010 4 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. THE TOTAL NUMBER OF PADS: 133 7 SYMBOL<br>Y 15 BSC<br>X<br>15 BSC<br>TOP VIEW<br>PACKAGE TOP VIEW<br>SUGGESTED PCB LAYOUT<br>aaa  Z PAD 1 CORNER 4 6.9850 5.7150 4.4450 3.1750 1.9050 0.6350 0.0000 0.6350 1.9050 3.1750 4.4450 5.7150 6.9850<br>Z<br>Zbbb<br>6.9850<br>5.7150<br>4.4450<br>3.1750<br>1.9050<br>0.6350<br>0.0000<br>0.6350<br>1.9050<br>3.1750<br>4.4450<br>5.7150<br>6.9850<br>**----- End of picture text -----**<br>


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LTM4612 

## **REVISION HISTORY** 

|**REV**|**DATE**|**DESCRIPTION**|**PAGE NUMBER**|
|---|---|---|---|
|A|03/10|Changes to Title and Description<br>Changes to Absolute Maximum Ratings<br>Changes to Electrical Characteristics<br>Text Changes to Operation Section<br>Text Changes to Applications Information Section<br>Changes to Figures 18, 19, 20, 21, 22<br>Changes to Related Parts|1<br>1<br>2, 3<br>10<br>12, 14<br>19, 20, 21, 22<br>26|
|B|05/11|Changes to the Title, Description, Features and Typical Application sections.<br>Changes to “Theldenotes...” statement and Note 2.<br>Changes to the Pin Functions.<br>Changes to the Block Diagram.<br>Text changes to the Operation section.<br>Text changes to the Applications Information section.<br>Changes to Figures 17, 19, 21, 22.<br>Changes to the Related Parts.|1<br>2, 3, 4<br>7, 8<br>9<br>10<br>10–20<br>20, 21, 22, 23<br>28|
|C|09/16|Changed Max value of VINTVCCfrom 5.3V to 5.5V|3|



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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits s described herFor more inform **a** tion www.lin **e** in will not infringe on existing patent rights.ar.com/LTM4612 

27 

LTM4612 

## **PACKAGE PHOTOGRAPH** 

**==> picture [147 x 68] intentionally omitted <==**

**----- Start of picture text -----**<br>
k———_ 15mm _——— ~ | 2.8mm<br>BEE[REEHREEos |<br>15mm<br>**----- End of picture text -----**<br>


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## **DESIGN RESOURCES** 

|**DESIGN RESOURCES**|||
|---|---|---|
|**SUBJECT**|**DESCRIPTION**||
|µModule Design and Manufacturing Resources|Design:<br>• Selector Guides<br>• Demo Boards and Gerber Files<br>• Free Simulation Tools|Manufacturing:<br>• Quick Start Guide<br>• PCB Design, Assembly and Manufacturing Guidelines<br>• Package and Board Level Reliability|
|µModule Regulator Products Search|1.  Sort table of products by parameters and download the result as a spread sheet.<br>2. Search using the Quick Power Search parametric table.<br>Quick Power Search<br>Input<br>Vin (Min)<br>V_<br>Vin<br>(M<br>Output<br>V out<br>Vv<br>_<br>;<br>lout<br>A||
|TechClip Videos|Quick videos detailing how to bench test electrical and thermal performance of µModule products.||
|Digital Power System Management|Linear Technology’s family of digital power supply management ICs are highly integrated solutions that<br>offer essential functions, including power supply monitoring, supervision, margining and sequencing,<br>and feature EEPROM for storing user configurations and fault logging.||



## **RELATED PARTS** 

|**PART NUMBER**|**DESCRIPTION**|**COMMENTS**|
|---|---|---|
|LTM4606|EN55022B Compliant 6A, DC/DC µModule<br>Regulator|EN55022B Compliant with PLL, Output Tracking and Margining,<br>LTM4612 Pin Compatible|
|LTM4613|EN55022B Compliant 36V, 8A, Step-Down µModule<br>Regulator with PLL, Output Tracking|5V ≤ VIN≤ 36V, 3.3V ≤ VOUT≤ 15V, 15mm × 15mm × 4.3mm LGA Package|
|LTM4601/LTM4601A<br>~~Pe~~|12A DC/DC µModule Regulator with PLL, Output<br>Tracking/Margining and Remote Sensing<br>~~Pe~~|Synchronizable, PolyPhase Operation, LTM4601-1/LTM4601A-1 Version Has<br>No Remote Sensing, LGA Package|
|LTM4604A<br>~~Pe~~|Low VIN4A DC/DC µModule Regulator<br>~~Pe~~|2.375V ≤ VIN≤ 5.5V, 0.8V ≤ VOUT≤ 5V, 9mm×15mm×2.3mm LGA Package|
|LTM4608A<br>~~Pe~~|Low VIN8A DC/DC µModule Regulator<br>~~PePo~~|2.7V ≤ VIN≤ 5.5V, 0.6V ≤ VOUT≤ 5V, 9mm×15mm×2.8mm LGA Package|
|LTM8022/LTM8023|36VIN, 1A and 2A DC/DC µModule Regulator<br>~~Po~~|Pin Compatible, 4.5V ≤ VIN≤ 36V; 9mm×11.25mm×2.8mm LGA Package|
|LTM4627|20VIN, 15A DC/DC Step-Down µModule Regulator<br>~~Pt~~|4.5V ≤ VIN≤ 20V, 0.6V ≤ VOUT≤ 5V, 15mm × 15mm × 4.3mm LGA Package|
|LTM4618|26VIN, 6A DC/DC Step-Down µModule Regulator<br>with PLL, Output Tracking|4.5V ≤ VIN≤ 26.5V, 0.8V ≤ VOUT≤ 5V, Synchronizable,<br>9mm × 15mm × 4.3mm LGA Package|
|LTM8033|EN55022B Compliant 36VIN, 3A DC/DC Step-Down<br>µModule Regulator|3.6V ≤ VIN≤ 36V, 0.8V ≤ VOUT≤ 24V, Synchronizable,<br>11.25mm × 15mm × 4.3mm LGA Package|



LT 0916 REV C • PRINTED IN USA 

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Linear Technology Corporation 28 1630 McCarthy Blvd., Milpitas, CA 95035-7417For more information www.linear.com/LTM4612 (408) 432-1900[●] FAX: (408) 434-0507[●] www.linear.com/LTM4612 

 LINEAR TECHNOLOGY CORPORATION 2008