Image not available
Illustrative purposes only
IIS3DWBG1TR
MEMS Accelerometer, ± 2g, ± 4g, ± 8g, ± 16g, X, Y, Z, I2C, SPI, LGA, 14 Pins
⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
- Manufacturer: STMICROELECTRONICS
- Product type: MEMS Accelerometers
- SVHC: No SVHC (25-Jun-2025)
- No. of Pins: 14Pins
- Sensing Axis: X, Y, Z
- Product Range: -
- Qualification: -
- Sensitivity Typ: 0.061mg/LSB, 0.122mg/LSB, 0.244mg/LSB, 0.488mg/LSB
- Output Interface: I2C, SPI
- Supply Voltage Max: 3.6V
- Supply Voltage Min: 2.1V
- Sensor Case / Package: LGA
- Operating Temperature Max: 125°C
- Operating Temperature Min: -40°C
- Sensing Range - Accelerometer: ± 2g, ± 4g, ± 8g, ± 16g
| Delivery and price | |
|---|---|
| Units per pack | 100 |
| Price | 13.19 € |
| Current stock | 50+ |
| Lead time | 30 days |
Datasheet
**IIS3DWBG1** Datasheet ## Ultrawide bandwidth, low-noise, 3-axis digital vibration sensor with extended temperature range ## **Features** - 3-axis vibration sensor with digital output - User-selectable full scale: ±2/±4/±8/±16 _g_ - Ultrawide and flat frequency response range: from dc to 6 kHz (±3 dB point) - • Ultralow noise density: down to 75 µ _g_ /√Hz in 3-axis mode / 60 µ _g_ /√Hz in single-axis mode **LGA-14L (2.5 x 3.0 x 0.83 mm) typ.** - High stability of the sensitivity over temperature and against mechanical shocks - Extended temperature range from -40 to +125°C - Low power: 1.1 mA with all 3 axes delivering full performance - SPI serial interface - Low-pass or high-pass filter with selectable cutoff frequency - Interrupts for wake-up / activity - inactivity / FIFO thresholds ## **Product status link** IIS3DWBG1 - Embedded FIFO: 3 KB - Embedded temperature sensor - Embedded self-test - Supply voltage: 2.1 V to 3.6 V |**Product summary**|**Product summary**| |---|---| |**Order code**|IIS3DWBG1TR| |**Temp. range [°C]**|-40 to +125| |**Package**|LGA-14L| |**Packing**|Tape and reel| - Compact package: LGA-14L, 2.5 x 3 x 0.83 mm - ECOPACK and RoHS compliant ## **Applications** - Vibration monitoring in industrial equipment and electric or hybrid vehicles - • Condition monitoring ## **Product resources** TN0018 (handling, mounting, and soldering guidelines) - Predictive maintenance - Test and measurements ## **Description** ## **Product label** The IIS3DWBG1 is a system-in-package featuring a 3-axis digital vibration sensor with low noise over an ultrawide and flat frequency range. The wide bandwidth, low noise, very stable and repeatable sensitivity, together with the capability of operating over an extended temperature range (up to +125°C), make the device particularly suitable for vibration monitoring in industrial applications and electric or hybrid vehicles. The high performance delivered at low power consumption together with the digital output and the embedded digital features like the FIFO and the interrupts are enabling features for battery-operated industrial wireless sensor nodes. The IIS3DWBG1 has a selectable full-scale acceleration range of ±2/±4/±8/±16 _g_ and is capable of measuring accelerations with a bandwidth up to 6 kHz with an output data rate of 26.7 kHz. A 3 KB first-in, first-out (FIFO) buffer is integrated in the device to avoid any data loss and to limit intervention from the host processor. **DS15022** - **Rev 1** - **July 2025** For further information, contact your local STMicroelectronics sales office. www.st.com **IIS3DWBG1** The MEMS sensor module family from ST leverages the robust and mature manufacturing processes already used for the production of micromachined accelerometers and gyroscopes to serve automotive, industrial, and consumer markets. The sensing elements are manufactured using ST’s proprietary micromachining process, while the embedded IC interfaces are developed using CMOS technology. The IIS3DWBG1 has a self-test capability, which allows checking the functioning of the sensor in the final application. The IIS3DWBG1 is available in a 14-lead plastic, land grid array (LGA) package and is guaranteed to operate over an extended temperature range from -40°C to +125°C. **DS15022** - **Rev 1** **page 2/59** **IIS3DWBG1 Pin description** **1** ## **Pin description** **Figure 1. Pin connections** **==> picture [349 x 196] intentionally omitted <==** **----- Start of picture text -----**<br> Z<br>12 14<br>Y<br>RES 11 1 SDO/TA0<br>RES == BOTTOM RES<br>INT2 = VIEW RES<br>VDD 8 Oo 4 INT1<br>oO oO<br>7 5<br>X HOU<br>Direction of detectable<br>acceleration (top view)<br>CS SPC/SCL SDI/SDO/SDA<br>GND GND VDDIO<br>**----- End of picture text -----**<br> **Table 1. Pin desription** |**Pin #**<br>~~SS~~|**Name**<br>~~SS~~|**Function**<br>~~SSCS~~| |---|---|---| |1|SDO/TA0|SPI 4-wire interface serial data output (SDO)<br>I²C(1)least significant bit of the device address (TA0)| |2|RES|Connect to VDDIO or GND| |3|RES|Connect to VDDIO or GND| |4|INT1|Programmable interrupt #1| |5|VDDIO(2)|Power supply for I/O pins| |6|GND|Connect to GND| |7|GND|Connect to GND| |8|VDD(2)|Power supply| |9|INT2|Programmable interrupt #2| |10|RES|Connect to VDDIO or leave unconnected(3)| |11|RES|Connect to VDDIO or leave unconnected(3)| |12|CS|I²C/SPI(1)mode selection<br>(1: SPI idle mode / I²C(1)communication enabled;<br>0: SPI communication mode / I²C(1)disabled)| |13|SPC/SCL|SPI serial port clock (SPC)<br>I²C serial clock (SCL)| |14|SDI/SDO/SDA|SPI serial data input (SDI)<br>3-wire interface serial data output (SDO)<br>I²C serial data (SDA)| _1. Only the SPI interface supports all the device features and capabilities. Due to limited throughput, the I²C interface can be used only in single-axis mode and it is not recommended._ _2. Recommended 100 nF filter capacitor._ _3. Leave pin electrically unconnected and soldered to PCB._ **DS15022** - **Rev 1** **page 3/59** **IIS3DWBG1 Pin description** ## **1.1 Default pin configuration** The IIS3DWBG1 default pin configuration and behavior is given in the table below. ## **Table 2. Default pin status** |**Pin#**|**Name**|**Function**|**Default status**|**Recommended connection**| |---|---|---|---|---| |1|SDO/TA0|SPI 4-wire interface serial data output (SDO)<br>I²C least significant bit of the device address (TA0)|Input without pull-up<br>Pull-up is enabled if bit SDO_PU_EN = 1 in reg<br>02h|Application specific| |2|RES|Reserved|Input without pull-up|Connect to VDDIO or GND| |3|RES|Reserved|Input without pull-up|Connect to VDDIO or GND| |4|INT1|Programmable interrupt #1|Input with pull-down|Must be set to 0 or left unconnected during<br>device power-up.<br>After device power-up, connection is application<br>specific.| |5|VDDIO|Power supply for I/O pin|-|| |6|GND|Ground|-|| |7|GND|Ground|-|| |8|VDD|Power supply|-|| |9|INT2|Programmable interrupt #2|Output forced to GND|Application specific| |10|RES|Reserved|Input with pull-up|Connect to VDDIO or leave pin electrically<br>unconnected and soldered to PCB| |11|RES|Reserved|Input with pull-up|Connect to VDDIO or leave pin electrically<br>unconnected and soldered to PCB| |12|CS|I²C/SPI mode selection<br>(1: SPI idle mode / I²C communication enabled;<br>0: SPI communication mode / I²C disabled)|Input with pull-up<br>Pull-up is disabled if bit I2C_DISABLE = 1 in reg<br>13h|Application specific| |13|SPC/SCL|SPI serial port clock (SPC)<br>I²C serial clock (SCL)|Input without pull-up|Application specific| |14|SDI/SDO/SDA|SPI serial data input (SDI)<br>3-wire interface serial data output (SDO)<br>I²C serial data (SDA)|Input without pull-up|Application specific| **DS15022** - **Rev 1** **page 4/59** **IIS3DWBG1 Module specifications** **2 Module specifications** ## **2.1 Mechanical characteristics** @VDD = 3.0 V, T = +25°C unless otherwise noted. The product is factory calibrated at 3.0 V. The operational power supply range is from 2.1 V to 3.6 V. **Table 3. Mechanical characteristics** |**Symbol**|**Parameter**|**Test conditions**|**Min.(1)**|**Typ.(2)**|**Max.(1)**|**Unit**| |---|---|---|---|---|---|---| |FS|Linear acceleration measurement range|||±2||_g_| |||||±4||| |||||±8||| |||||±16||| |So|Linear acceleration sensitivity(3)|@FS = ±2_g_|-2%|0.061|+2%|m_g_/LSB| |||@FS = ±4_g_||0.122||| |||@FS = ±8_g_||0.244||| |||@FS = ±16_g_||0.488||| |SoDr|Linear acceleration sensitivity change vs. temperature(4)|from -40°C to +125°C<br>delta from T = +25°C||±1||%| |TyOff|Linear acceleration zero-_g_level offset accuracy(5)|T = 25°C|-180|±60|+180|m_g_| |TCOff|Linear acceleration zero-_g_level change vs. temperature(4)|||±1||m_g_/°C| |An|Acceleration noise density 3 axes enabled(6)|X-axis||75|110|µ_g_/√Hz| |||Y-axis||75|110|| |||Z-axis||110|190|| ||Acceleration noise density only 1 axis enabled(6)|X-axis||60|90|| |||Y-axis||60|90|| |||Z-axis||80|130|| |BW|Signal bandwidth|±3 dB point|5|6.3||kHz| |ODR|Linear acceleration output data rate|||26.667||kHz| |ODR_ACC|ODR accuracy|Error wrt 26667 Hz<br>@VDD 3.0 V, T = +25°C||±1|±2|%| |ODR_TC|ODR change vs. temperature|Error wrt 26667 Hz<br>@VDD 3.0 V,<br>from -40°C to +125°C<br>delta from T = +25°C|||±0.03|%/°C| |F0|Sensor resonant frequency|X-axis||6.9||kHz| |||Y-axis||6.9||| |||Z-axis||7.0||| |Vst|Linear acceleration self-test output change(7)(8)(9)|FS = ±4_g_|800||3200|m_g_| |Top|Operating temperature range||-40||+125|°C| _1. Min/Max values are based on characterization results at 3σ on a limited number of samples, not tested in production and not guaranteed._ _2. Typical specifications are not guaranteed._ _3. Sensitivity values after factory calibration test and trimming._ **DS15022** - **Rev 1** **page 5/59** **IIS3DWBG1 Module specifications** _4. Measurements are performed in a uniform temperature setup and they are based on characterization data in a limited number of samples. Not measured in production and not guaranteed._ _5. Values after factory calibration test and trimming._ _6. Frequency range 100 Hz - 6.3 kHz. Noise density is independent of the FS selected._ _7. The sign of the linear acceleration self-test output change is defined by the STx_XL bits in a dedicated register for all axes._ _8. The linear acceleration self-test output change is defined with the device in stationary condition as the absolute value of: OUTPUT[LSb] (self-test enabled) - OUTPUT[LSb] (self-test disabled). 1LSb =0.122 mg at ±4 g full scale._ _9. Accelerometer self-test limits are full-scale independent. The self-test should be executed with FS setting ≥4 g._ ## **2.2 Electrical characteristics** @VDD = 3.0 V, T = 25°C unless otherwise noted. ## **Table 4. Electrical characteristics** |**Symbol**|**Parameter**|**Test conditions**|**Min.(1)**|**Typ.(2)**|**Max.(1)**|**Unit**| |---|---|---|---|---|---|---| |VDD|Supply voltage||2.1||3.6|V| |VDDIO|Power supply for I/O||1.62||VDD + 0.1|V| |Idd|Accelerometer supply current|ODR = 26.667 kHz||1.1|1.3|mA| |IddPD|Accelerometer supply current during power-down|||5|16|µA| |Ton|Turn-on time(3)|||10||ms| |VIH(4)|Digital high-level input voltage||0.7 * VDDIO|||V| |VIL(4)|Digital low-level input voltage||||0.3 * VDDIO|V| |VOH(4)|High-level output voltage|IOH= 4 mA(5)|VDDIO - 0.2|||V| |VOL(4)|Low-level output voltage|IOL= 4 mA(5)|||0.2|V| |Top|Operating temperature range||-40||+125(6)|°C| _1. Min/Max values are based on characterization results at 3σ, not tested in production and not guaranteed._ _2. Typical specifications are not guaranteed._ _3. Time to obtain valid data switching from power-down to normal operation._ _4. Guaranteed by design characterization and not tested in production._ _5. 4 mA is the maximum driving capability, i.e. the maximum DC current that can be sourced/sunk by the digital pad in order to guarantee the correct digital output voltage levels VOH and VOL._ _6. The IIS3DWBG1 has been qualified with HTOL@125°C for 1000h. In case, in the application, the IIS3DWBG1 has to be operated frequently at high temperature (>50°C), it is recommended, in order to maximize its lifetime, to switch off the sensor, by setting its power supplies to 0 V, when the sensor is not needed to perform measurements. The lower the duty cycle of the IIS3DWBG1 in powered condition, the longer the lifetime of the device which can be extrapolated based on the results of reliability trials._ **DS15022** - **Rev 1** **page 6/59** **IIS3DWBG1 Module specifications** ## **2.3 Temperature sensor characteristics** @VDD = 3.0 V, T = 25°C unless otherwise noted. The product is factory calibrated at 3.0 V. |**Symbol**|**Parameter**|**Test condition**|**Min.(1)**|**Typ.(2)**|**Max.(1)**|**Unit**| |---|---|---|---|---|---|---| |TODR|Temperature refresh rate|||104||Hz| |Toff|Temperature offset(3)||-15||+15|°C| |TSen|Temperature sensitivity|||256||LSB/°C| |T_delta_Acc|Delta temperature accuracy(4)|from 25°C to 125°C|||4|°C| |TST|Temperature stabilization time(5)|||10||ms| |T_ADC_res|Temperature ADC resolution|||16||bit| |Top|Operating temperature range||-40||+125|°C| _1. Min/Max values are based on characterization results at 3σ on a limited number of samples, not tested in production and not guaranteed._ _2. Typical specifications are not guaranteed._ _3. The output of the temperature sensor is 0 LSB (typ.) at 25°C. Absolute temperature accuracy can be improved (reducing the effect of temperature offset) by performing OPC (one-point calibration) at room temperature (25°C)._ _4. Applicable if temperature offset is removed with OPC (one-point calibration) at room temperature (25°C)._ _5. Time from power ON to valid output data._ **DS15022** - **Rev 1** **page 7/59** **IIS3DWBG1 Module specifications** ## **2.4 Communication interface characteristics** ## **2.4.1 SPI - serial peripheral interface** Subject to general operating conditions for VDD and Top. **Table 5. SPI target timing values** |**Symbol**|**Parameter**|**Value(1)**|**Value(1)**|**Unit**| |---|---|---|---|---| |||**Min**|**Max**|| |tc(SPC)|SPI clock cycle|100||ns| |fc(SPC)|SPI clock frequency||10|MHz| |tsu(CS)|CS setup time|5||ns| |th(CS)|CS hold time|20||| |tsu(SI)|SDI input setup time|5||| |th(SI)|SDI input hold time|15||| |tv(SO)|SDO valid output time||50|| |th(SO)|SDO output hold time|5||| |tdis(SO)|SDO output disable time||50|| _1. Values are evaluated at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not tested in production._ **Figure 2. SPI target timing diagram** _Note: Measurement points are done at 0.3·VDDIO and 0.7·VDDIO for both input and output ports._ **DS15022** - **Rev 1** **page 8/59** **IIS3DWBG1 Module specifications** ## **2.5 Absolute maximum ratings** Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. **Table 6. Absolute maximum ratings** |**Symbol**<br>~~a~~|**Ratings**<br>~~ee~~|**Maximum value**<br>~~ee~~<br>~~ee~~|**Unit**<br>~~ee~~| |---|---|---|---| |VDD|Supply voltage|-0.3 to +4.8<br>~~ee~~|V| |TSTG|Storage temperature range|-40 to +125|°C| |Sg|Acceleration_g_for 0.2 ms|10,000|_g_| |ESD|Electrostatic discharge protection (HBM)|2|kV| |Vin|Input voltage on any control pin<br>(including CS, SCL/SPC, SDA/SDI/SDO, SDO/TA0)|-0.3 to VDDIO +0.3|V| _Note:_ _Supply voltage on any pin should never exceed 4.8 V._ This device is sensitive to mechanical shock, improper handling can cause permanent damage to the part. This device is sensitive to electrostatic discharge (ESD), improper handling can cause permanent damage to the part. **DS15022** - **Rev 1** **page 9/59** **IIS3DWBG1 Module specifications** ## **2.6 Terminology** ## **2.6.1 Sensitivity** Linear acceleration sensitivity can be determined, for example, by applying 1 _g_ acceleration to the device. Because the sensor can measure DC accelerations, this can be done easily by pointing the selected axis towards the ground, noting the output value, rotating the sensor 180 degrees (pointing towards the sky), and noting the output value again. By doing so, ±1 _g_ acceleration is applied to the sensor. Subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This value changes very little over temperature and over time. The sensitivity tolerance describes the range of sensitivities of a large number of sensors (see Table 3). ## **2.6.2 Zero-** _**g**_ **level** Linear acceleration zero- _g_ level offset (TyOff) describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. A sensor in a steady state on a horizontal surface measures 0 _g_ on both the X-axis and Y-axis, whereas the Z-axis measures 1 _g_ . Ideally, the output is in the middle of the dynamic range of the sensor (content of OUT registers 00h, data expressed as two’s complement number). A deviation from the ideal value in this case is called zero- _g_ offset. Offset is to some extent a result of stress to the MEMS sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. Offset changes little over temperature, see “Linear acceleration zero- _g_ level change vs. temperature” in Table 3. The zero- _g_ level tolerance (TyOff) describes the standard deviation of the range of zero- _g_ levels of a group of sensors. **DS15022** - **Rev 1** **page 10/59** **IIS3DWBG1 Digital interface** **3 Digital interface** ## **3.1 SPI interface** The registers embedded inside the IIS3DWBG1 may be accessed through the SPI serial interface that can be software configured to operate either in 3-wire or 4-wire interface mode. The device is compatible with SPI modes 0 and 3. The SPI interface is mapped to the same pins as an I²C interface. However, since it is only with the throughput of the SPI interface that all the device features and capabilities are supported, the I²C interface is not described. To select/exploit the I²C interface, the CS line must be tied high (that is, connected to VDDIO). **Table 7. Serial interface pin description** |**Pin name**|**Pin description**| |---|---| |CS|Enable SPI<br>I²C(1)/SPI mode selection<br>(1: SPI idle mode / I²C(1)communication enabled;<br>0: SPI communication mode / I²C(1)disabled)| |SPC/SCL|SPI serial port clock (SPC)<br>I²C(1)serial clock (SCL)| |SDI/SDO/SDA|SPI serial data input (SDI)<br>3-wire interface serial data output (SDO)<br>I²C(1)serial data (SDA)| |SDO/TA0|SPI 4-wire interface serial data output (SDO)<br>I²C(1)least significant bit of the device address (TA0)| _1. Only the SPI interface supports all the device features and capabilities. Due to limited throughput, the I²C interface can be used only in single-axis mode and it is not recommended._ **DS15022** - **Rev 1** **page 11/59** **IIS3DWBG1 Digital interface** ## **3.2 SPI bus interface** The IIS3DWBG1 SPI is a bus target. The SPI allows writing to and reading from the registers of the device. The serial interface communicates with the application using four wires: **CS** , **SPC** , **SDI** , and **SDO** . ## **Figure 3. Read and write protocol (in mode 3)** **==> picture [305 x 96] intentionally omitted <==** **----- Start of picture text -----**<br> CS<br>SPC<br>SDI<br>RW DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0<br>AD6 AD5 AD4 AD3 AD2 AD1 AD0<br>SDO<br>DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0<br>**----- End of picture text -----**<br> **CS** enables the serial port and it is controlled by the SPI controller. It goes low at the start of the transmission and goes back high at the end. **SPC** is the serial port clock and it is controlled by the SPI controller. It is stopped high when **CS** is high (no transmission). **SDI** and **SDO** are, respectively, the serial port data input and output. Those lines are driven at the falling edge of **SPC** and should be captured at the rising edge of **SPC** . Both the read register and write register commands are completed in 16 clock pulses or in multiples of 8 in case of multiple read/write bytes. Bit duration is the time between two falling edges of **SPC** . The first bit (bit 0) starts at the first falling edge of **SPC** after the falling edge of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of **SPC** just before the rising edge of **CS** . **bit 0** : RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from the device is read. In latter case, the chip drives **SDO** at the start of bit 8. **bit 1-7** : address AD(6:0). This is the address field of the indexed register. **bit 8-15** : data DI(7:0) (write mode). This is the data that is written into the device (MSb first). **bit 8-15** : data DO(7:0) (read mode). This is the data that is read from the device (MSb first). In multiple read/write commands further blocks of 8 clock periods are added. When the CTRL3_C (12h) (IF_INC) bit is 0, the address used to read/write data remains the same for every block. When the CTRL3_C (12h) (IF_INC) bit is 1, the address used to read/write data is increased at every block. The function and the behavior of **SDI** and **SDO** remain unchanged. **DS15022** - **Rev 1** **page 12/59** **IIS3DWBG1 Digital interface** ## **3.2.1 SPI read** **Figure 4. SPI read protocol (in mode 3)** **==> picture [277 x 88] intentionally omitted <==** **----- Start of picture text -----**<br> CS<br>SPC<br>SDI<br>RW<br>AD6 AD5 AD4 AD3 AD2 AD1 AD0<br>SDO<br>DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0<br>**----- End of picture text -----**<br> The SPI read command is performed with 16 clock pulses. A multiple byte read command is performed by adding blocks of 8 clock pulses to the previous one. **bit 0** : READ bit. The value is 1. **bit 1-7** : address AD(6:0). This is the address field of the indexed register. **bit 8-15** : data DO(7:0) (read mode). This is the data that is read from the device (MSb first). **bit 16-...** : data DO(...-8). Further data in multiple byte reads. **Figure 5. Multiple byte SPI read protocol (2-byte example) (in mode 3)** **==> picture [351 x 96] intentionally omitted <==** **----- Start of picture text -----**<br> CS<br>SPC<br>SDI<br>RW<br>AD6 AD5 AD4AD3 AD2 AD1 AD0<br>SDO<br>DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DO15 DO14 DO13 DO12 DO11DO10 DO9 DO8<br>**----- End of picture text -----**<br> **DS15022** - **Rev 1** **page 13/59** **IIS3DWBG1 Digital interface** ## **3.2.2 SPI write** **Figure 6. SPI write protocol (in mode 3)** **==> picture [301 x 68] intentionally omitted <==** **----- Start of picture text -----**<br> CS<br>SPC<br>SDI<br>RW DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0<br>AD6 AD5 AD4 AD3 AD2 AD1 AD0<br>**----- End of picture text -----**<br> The SPI write command is performed with 16 clock pulses. A multiple byte write command is performed by adding blocks of 8 clock pulses to the previous one. **bit 0** : WRITE bit. The value is 0. **bit 1-7** : address AD(6:0). This is the address field of the indexed register. **bit 8-15** : data DI(7:0) (write mode). This is the data that is written inside the device (MSb first). **bit 16-...** : data DI(...-8). Further data in multiple byte writes. ## **Figure 7. Multiple byte SPI write protocol (2-byte example) (in mode 3)** **==> picture [374 x 82] intentionally omitted <==** **----- Start of picture text -----**<br> CS<br>SPC<br>SDI<br>DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8<br>RW<br>AD6 AD5 AD4 AD3 AD2 AD1 AD0<br>**----- End of picture text -----**<br> ## **3.2.3 SPI read in 3-wire mode** 3-wire mode is entered by setting the CTRL3_C (12h) (SIM) bit equal to 1 (SPI serial interface mode selection). **Figure 8. SPI read protocol in 3-wire mode (in mode 3)** **==> picture [323 x 72] intentionally omitted <==** **----- Start of picture text -----**<br> CS<br>SPC<br>SDI/O<br>RW DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0<br>AD6 AD5 AD4 AD3 AD2 AD1 AD0<br>**----- End of picture text -----**<br> The SPI read command is performed with 16 clock pulses: **bit 0** : READ bit. The value is 1. **bit 1-7** : address AD(6:0). This is the address field of the indexed register. **bit 8-15** : data DO(7:0) (read mode). This is the data that is read from the device (MSb first). A multiple read command is also available in 3-wire mode. **DS15022** - **Rev 1** **page 14/59** **IIS3DWBG1 Functionality** ## **4 Functionality** ## **4.1 Operating modes** The IIS3DWBG1 has two operating modes: - 3-axis mode: all three axes (X, Y, Z) are simultaneously active and acceleration data can be read from the sensor concurrently for the 3-axis (using registers OUTX_L_A (28h) and OUTX_H_A (29h); OUTY_L_A (2Ah) and OUTY_H_A (2Bh); OUTZ_L_A (2Ch) and OUTZ_H_A (2Dh) or the FIFO registers: FIFO_DATA_OUT (79h – 7Eh). - Single-axis mode: only one axis is active. The active axis, among X or Y or Z, can be selected when the device is in power-down mode. Acceleration data can be read from the registers associated with the active axis or from the corresponding registers of the FIFO. In single-axis mode, while the power consumption of IIS3DWBG1 remains the same as 3-axis mode, the resolution (noise density) of the active axis significantly improves. To change the configuration of the active axis, the device should be in power-down mode. An example of the procedure that can be applied is: Set the device in power-down mode: CTRL1_XL (10h) XL_EN[2:0] = 000b Enable the axis: CTRL6_C (15h) XL_AXIS_SEL[1:0] = xxb (00 = 3 axes; 01 = X-axis; 10 = Y-axis; 11 = Z-axis) Enable the device: CTRL1_XL (10h) XL_EN[2:0] = 101b **DS15022** - **Rev 1** **page 15/59** **IIS3DWBG1 Functionality** ## **4.2 Block diagrams** The IIS3DWBG1 architecture is composed of the following functional blocks: - MEMS mechanical element - ADC - Low-pass digital filter (LPF1) - Composite filter **Figure 9. Accelerometer architecture** **==> picture [430 x 189] intentionally omitted <==** **----- Start of picture text -----**<br> X A2D<br>CS<br>I [2] C/SPI SCL/SPC<br>Interface SDA/SDIO<br>ME NSE converterdC/dV A2D Low Pass(LPF1) Filter CompositeFilter SDO<br>M S<br>Digital<br>S O<br>ZA2D Processing INT1<br>R and Interrupt<br>functions Mgmt<br>INT2<br>Temperature<br>A2D<br>sensor<br>Voltage and<br>current Trimming Circuit Clock & Phase Power NVM Memory<br>& Test Interface Generator Management<br>reference<br>**----- End of picture text -----**<br> **Figure 10. Accelerometer composite filter** **==> picture [415 x 195] intentionally omitted <==** **----- Start of picture text -----**<br> 0<br>0<br>User<br>1<br>Offset<br>LPF2 1<br>USR_OFF_W<br>OFS_USR[7:0]<br>USR_OFF_ON_OUT<br>HPCF_XL_[2:0]<br>LPF2_XL_EN SPI/I [2] C<br>1 1 Wake-up 0<br>ADC LPF1 0 0 InactiivityActivity / 1<br>FIFO<br>USR_OFF_ON_WU SLOPE_FDS<br>HPF FDS<br>HPCF_XL_[2:0]<br>Slope<br>Filter<br>HPCF_XL_[2:0]<br>**----- End of picture text -----**<br> **DS15022** - **Rev 1** **page 16/59** **IIS3DWBG1 Functionality** ## **4.3** ## **FIFO** The presence of a FIFO allows consistent power saving for the system since the host processor does not need to continuously poll data from the sensor, but it can wake up only when needed and burst the significant data out from the FIFO. The IIS3DWBG1 embeds 3 KB of data in FIFO to store the following data: - Accelerometer - Timestamp - Temperature Writing data in the FIFO is triggered by the accelerometer data-ready signal. It is possible to select decimation for timestamp batching in FIFO with a factor of 1, 8, or 32 compared to the accelerometer BDR (batch data rate). The reconstruction of a FIFO stream is a simple task thanks to the FIFO_DATA_OUT_TAG byte that allows recognizing the meaning of a word in FIFO. FIFO allows correct reconstruction of the timestamp information for each sensor stored in FIFO. If a change in the BDR configuration is performed, the application can correctly reconstruct the timestamp and know exactly when the change was applied without disabling FIFO batching. FIFO stores information of the new configuration and timestamp in which the change was applied in the device. The programmable FIFO watermark threshold can be set in FIFO_CTRL1 (07h) and FIFO_CTRL2 (08h) using the WTM[8:0] bits. To monitor the FIFO status, dedicated registers (FIFO_STATUS1 (3Ah), FIFO_STATUS2 (3Bh)) can be read to detect FIFO overrun events, FIFO full status, FIFO empty status, FIFO watermark status, and the number of unread samples stored in the FIFO. To generate dedicated interrupts on the INT1 and INT2 pins of these status events, the configuration can be set in INT1_CTRL (0Dh) and INT2_CTRL (0Eh). The FIFO buffer can be configured according to six different modes: - Bypass mode - FIFO mode - Continuous mode - Continuous-to-FIFO mode - Bypass-to-continuous mode - Bypass-to-FIFO mode Each mode is selected by the FIFO_MODE_[2:0] bits in the FIFO_CTRL4 (0Ah) register. ## **4.3.1** ## **Bypass mode** In bypass mode (FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0] = 000), the FIFO is not operational and it remains empty. Bypass mode is also used to reset the FIFO when in FIFO mode. ## **4.3.2 FIFO mode** In FIFO mode (FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0] = 001) data from the output channels are stored in the FIFO until it is full. To reset FIFO content, bypass mode should be selected by writing FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0]) to 000. After this reset command, it is possible to restart FIFO mode by writing FIFO_CTRL4 (0Ah) (FIFO_MODE_[2:0]) to 001. The FIFO buffer memorizes up to 3 KB of data but the depth of the FIFO can be resized by setting the WTM[8:0] bits in FIFO_CTRL1 (07h) and FIFO_CTRL2 (08h). If the STOP_ON_WTM bit in FIFO_CTRL2 (08h) is set to 1, FIFO depth is limited up to the WTM[8:0] bits in FIFO_CTRL1 (07h) and FIFO_CTRL2 (08h). **DS15022** - **Rev 1** **page 17/59** **IIS3DWBG1 Functionality** **4.3.3 Continuous mode** Continuous mode (FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0] = 110) provides a continuous FIFO update: as new data arrives, the older data is discarded. A FIFO threshold flag FIFO_STATUS2 (3Bh)(FIFO_WTM_IA) is asserted when the number of unread samples in FIFO is greater than or equal to FIFO_CTRL1 (07h) and FIFO_CTRL2 (08h)(WTM[8:0]). It is possible to route the FIFO_WTM_IA flag to the INT1 pin by writing in register INT1_CTRL (0Dh) (INT1_FIFO_TH) = 1 or to the INT2 pin by writing in register INT2_CTRL (0Eh)(INT2_FIFO_TH) = 1. A full-flag interrupt can be enabled, INT1_CTRL (0Dh)(INT1_FIFO_FULL) = 1 or INT2_CTRL (0Eh) (INT2_FIFO_FULL) = 1, in order to indicate FIFO saturation and eventually read its content all at once. If an overrun occurs, at least one of the oldest samples in FIFO has been overwritten and the FIFO_OVR_IA flag in FIFO_STATUS2 (3Bh) is asserted. In order to empty the FIFO before it is full, it is also possible to pull from FIFO the number of unread samples available in FIFO_STATUS1 (3Ah) and FIFO_STATUS2 (3Bh)(DIFF_FIFO_[9:0]). **4.3.4 Continuous-to-FIFO mode** In continuous-to-FIFO mode (FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0] = 011), FIFO behavior changes according to the trigger event (wake-up) detected. When the selected trigger bit is equal to 1, FIFO operates in FIFO mode. When the selected trigger bit is equal to 0, FIFO operates in continuous mode. **4.3.5 Bypass-to-continuous mode** In bypass-to-continuous mode (FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0] = 100), data measurement storage inside FIFO operates in continuous mode when selected triggers are equal to 1, otherwise FIFO content is reset (bypass mode). FIFO behavior changes according to the trigger event detected (wake-up). **4.3.6 Bypass-to-FIFO mode** In bypass-to-FIFO mode FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0] = 111), data measurement storage inside FIFO operates in FIFO mode when selected triggers (wake-up) are equal to 1, otherwise FIFO content is reset (bypass mode) **4.3.7 FIFO reading procedure** The data stored in FIFO are accessible from dedicated registers and each FIFO word is composed of 7 bytes: one tag byte (FIFO_DATA_OUT_TAG (78h), in order to identify the sensor, and 6 bytes of fixed data (FIFO_DATA_OUT registers from (79h) to (7Eh)). The DIFF_FIFO_[9:0] field in the FIFO_STATUS1 (3Ah) and FIFO_STATUS2 (3Bh) registers contains the number of words (1 byte TAG + 6 bytes DATA) collected in FIFO. In addition, it is possible to configure a counter of the batch events of the sensor. The flag COUNTER_BDR_IA in FIFO_STATUS2 (3Bh) alerts that the counter has reached a selectable threshold (CNT_BDR_TH_[10:0] field in COUNTER_BDR_REG1 (0Bh) and COUNTER_BDR_REG2 (0Ch)). This allows triggering the reading of FIFO with the desired latency of one single sensor. The sensor is selectable using the TRIG_COUNTER_BDR bit in COUNTER_BDR_REG1 (0Bh). As for the other FIFO status events, the flag COUNTER_BDR_IA can be routed on the INT1 or INT2 pins by asserting the corresponding bits (INT1_CNT_BDR of INT1_CTRL (0Dh) and INT2_CNT_BDR of INT2_CTRL (0Eh)). **DS15022** - **Rev 1** **page 18/59** **IIS3DWBG1 Frequency response** ## **5 Frequency response** The IIS3DWBG1 has been specifically designed to provide a wide bandwidth with very flat frequency response in the pass band and a very high attenuation in the stop band so to virtually eliminate any frequency aliasing. The following figure illustrates the filtering chain and its components. **Figure 11. Filtering chain** **==> picture [368 x 63] intentionally omitted <==** **----- Start of picture text -----**<br> Analog 26.7 kHz<br>Low- Pass Composite<br>Front-end+<br>f0=7kHz ADC Filter Filter<br>MEMS ADC LPF1 Composite Filter<br>**----- End of picture text -----**<br> The output of the ADC converter is filtered with a digital low-pass filter to ensure the intended sensor’s frequency response. The frequency response at the output of the LPF1 filter is indicated in the following figure. **Figure 12. Frequency response at the output of LPF1 filter** ## _Note:_ _Frequency response determined by CAD simulation – at the output of LPF1._ After the LPF1 filter, it is possible to enable another level of digital filtering through the digital composite filter (refer to Figure 10. Accelerometer composite filter). The digital composite filter could be: - High-pass filter - Low-pass filter **DS15022** - **Rev 1** **page 19/59** **IIS3DWBG1 Frequency response** **Figure 13. Frequency response with LPF2 enabled** _Note: Frequency response determined by CAD simulation._ **Figure 14. Frequency response with HPF enabled** _Note: Frequency response determined by CAD simulation._ **DS15022** - **Rev 1** **page 20/59** **IIS3DWBG1 Typical performance characteristics** ## **6 Typical performance characteristics** ## **6.1 Frequency response measurements** The frequency response of the IIS3DWBG1, measured on a mechanical shaker, is indicated in the following figures. Measurements have been performed with the IIS3DWBG1 configured with the digital composite filter bypassed. **Figure 15. Frequency response - X-axis** _Note: Characterization data on 10 parts. Not measured in production and not guaranteed._ **Figure 16. Frequency response - Y-axis** _Note: Characterization data on 10 parts. Not measured in production and not guaranteed._ **DS15022** - **Rev 1** **page 21/59** **IIS3DWBG1 Typical performance characteristics** **Figure 17. Frequency response - Z-axis** _Note: Characterization data on 10 parts. Not measured in production and not guaranteed._ **DS15022** - **Rev 1** **page 22/59** **IIS3DWBG1 Typical performance characteristics** ## **6.2 Sensitivity change versus temperature** **Figure 18. Sensitivity change versus temperature** _Note: Characterization data. Not measured in production and not guaranteed._ ## **6.3 ODR change versus temperature** **Figure 19. ODR change versus temperature** _Note: Characterization data. Not measured in production and not guaranteed._ **DS15022** - **Rev 1** **page 23/59** **IIS3DWBG1 Application hints** ## **7 Application hints** ## **7.1 IIS3DWBG1 electrical connections** ## **Figure 20. IIS3DWBG1 electrical connections** **==> picture [433 x 268] intentionally omitted <==** **----- Start of picture text -----**<br> HOST<br>14 12<br>I [2] C/SPI (3/4-w)<br>SDO/TA0 1 11 RES [(1)]<br>TOP RES [(1)] IIS3DWBG1<br>VIEW<br>GND or VDDIO INT2<br>4 8 VDD<br>INT1 VDD I [2] C configuration<br>C1<br>100nF<br>5 7 VDDIO<br>GND<br>Rpu Rpu<br>SCL<br>C2<br>VDDIO SDA<br>100nF<br>GND<br>Pull-up to be added<br>Rpu=10kOhm<br>SDI/SDO/SDA SPC/SCL CS<br>GND GND<br>VDDIO<br>**----- End of picture text -----**<br> The device core is supplied through the VDD line while the I/O pads are supplied through the VDDIO line. Power supply decoupling capacitors (C1, C2 = 100 nF ceramic) should be placed as near as possible to the supply pin of the device (common design practice). The functionality of the device and the measured acceleration data are selectable and accessible through the I²C or SPI interfaces. When using the I²C protocol, CS must be tied high. Every time the CS line is set to low level, the I²C bus is internally reset. All the functions, the threshold, and the timing of the two interrupt pins can be completely programmed by the user through the I²C/SPI interface. _Note:_ _Only the SPI interface supports all the device features and capabilities. The I²C interface can be used only in single-axis mode and it is not recommended._ **DS15022** - **Rev 1** **page 24/59** **IIS3DWBG1 Application hints** ## **7.2 Measuring the actual ODR** For applications requiring higher ODR accuracy, it is possible to configure the device to generate an interrupt signal on the INT1/2 pin each time new data is generated. By using an accurate timer (that is, with a microcontroller) it is possible to measure the time interval between consecutive interrupt signals obtaining a very accurate value of the actual ODR of the device. In order to enable the generation of the data_ready interrupt on the INT1 or INT2 pin: - The dataready_pulsed bit of the COUNTER_BDR_REG1 (0Bh) register should be set to 1 (optional). - The INTx_ DRDY_XL bit of the INT1_CTRL (0Dh) / INT2_CTRL (0Eh) register has to be set to 1. **Figure 21. Accurately measuring ODR** **==> picture [224 x 74] intentionally omitted <==** **----- Start of picture text -----**<br> SPI<br>IIS3DWBG1 µC<br>INT1/2 pin<br>**----- End of picture text -----**<br> **DS15022** - **Rev 1** **page 25/59** **IIS3DWBG1 Register mapping** ## **8 Register mapping** The table given below provides a list of the 8/16-bit registers embedded in the device and the corresponding addresses. **Table 8. Register address map** |**Name**|**Te**|**Register address**|**Register address**|**Defalt**|**Comment**| |---|---|---|---|---|---| ||**yp**|**Hex**|**Binary**|**u**|| |RESERVED|-|01|||| |PIN_CTRL|R/W|02|00000010|00111111|| |RESERVED|-|03-06|||| |FIFO_CTRL1|R/W|07|00000111|00000000|| |FIFO_CTRL2|R/W|08|00001000|00000000|| |FIFO_CTRL3|R/W|09|00001001|00000000|| |FIFO_CTRL4|R/W|0A|00001010|00000000|| |COUNTER_BDR_REG1|R/W|0B|00001011|00000000|| |COUNTER_BDR_REG2|R/W|0C|00001100|00000000|| |INT1_CTRL|R/W|0D|00001101|00000000|| |INT2_CTRL|R/W|0E|00001110|00000000|| |WHO_AM_I|R|0F|00001111|01111011|| |CTRL1_XL|R/W|10|00010000|00000000|| |RESERVED|-|11|||| |CTRL3_C|R/W|12|00010010|00000100|| |CTRL4_C|R/W|13|00010011|00000000|| |CTRL5_C|R/W|14|00010100|00000000|| |CTRL6_C|R/W|15|00010101|00000000|| |CTRL7_C|R/W|16|00011100|00000000|| |CTRL8_XL|R/W|17|00010111|00000000|| |RESERVED|-|18|||| |CTRL10_C|R/W|19|00011001|00000000|| |ALL_INT_SRC|R|1A|00011010|output|| |WAKE_UP_SRC|R|1B|00011011|output|| |RESERVED|-|1C-1D|||| |STATUS_REG|R|1E|00011110|output|| |RESERVED|-|1F|00011111||| |OUT_TEMP_L|R|20|00100000|output|| |OUT_TEMP_H|R|21|00100001|output|| |RESERVED|-|22-27|||| |OUTX_L_A|R|28|00101000|output|| |OUTX_H_A|R|29|00101001|output|| |OUTY_L_A|R|2A|00101010|output|| |OUTY_H_A|R|2B|00101011|output|| |OUTZ_L_A|R|2C|00101100|output|| **DS15022** - **Rev 1** **page 26/59** **IIS3DWBG1 Register mapping** |**Name**|**Te**|**Register address**|**Register address**|**Defalt**|**Comment**| |---|---|---|---|---|---| ||**yp**|**Hex**|**Binary**|**u**|| |OUTZ_H_A|R|2D|00101101|output|| |RESERVED|-|2E-39|||| |FIFO_STATUS1|R|3A|00111010|output|| |FIFO_STATUS2|R|3B|00111011|output|| |RESERVED|-|3C-3F|||| |TIMESTAMP0|R|40|01000000|output|| |TIMESTAMP1|R|41|01000001|output|| |TIMESTAMP2|R|42|01000010|output|| |TIMESTAMP3|R|43|01000011|output|| |RESERVED|-|44-55|||| |SLOPE_EN|R/W|56|01010111|00000000|| |RESERVED|-|57|||| |INTERRUPTS_EN|R/W|58|01011000|00000000|| |RESERVED|-|59-5A|||| |WAKE_UP_THS|R/W|5B|01011011|00000000|| |WAKE_UP_DUR|R/W|5C|01011100|00000000|| |RESERVED|-|5D|||| |MD1_CFG|R/W|5E|01011110|00000000|| |MD2_CFG|R/W|5F|01011111|00000000|| |RESERVED|-|60-62|||| |INTERNAL_FREQ_FINE|R|63|01100011|output|| |RESERVED|-|64-72|||| |X_OFS_USR|R/W|73|01110011|00000000|| |Y_OFS_USR|R/W|74|01110100|00000000|| |Z_OFS_USR|R/W|75|01110101|00000000|| |RESERVED|-|76-77|||| |FIFO_DATA_OUT_TAG|R|78|01111000|output|| |FIFO_DATA_OUT_X_L|R|79|01111001|output|| |FIFO_DATA_OUT_X_H|R|7A|01111010|output|| |FIFO_DATA_OUT_Y_L|R|7B|01111011|output|| |FIFO_DATA_OUT_Y_H|R|7C|01111100|output|| |FIFO_DATA_OUT_Z_L|R|7D|01111101|output|| |FIFO_DATA_OUT_Z_H|R|7E|01111110|output|| Reserved registers must not be changed. Writing to those registers may cause permanent damage to the device. The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered up. **DS15022** - **Rev 1** **page 27/59** **IIS3DWBG1 Register description** ## **9 Register description** ## **9.1 PIN_CTRL (02h)** Enable/disable SDO pin pull-up register (R/W) ## **Table 9. PIN_CTRL register** |0|SDO_PU_EN|SDO_PU_EN|1|1|1|1|1|1| |---|---|---|---|---|---|---|---|---| |**Table 10.PIN_CTRL register description**||||||||| |SDO_PU_EN||Enables pull-up on SDO pin<br>(0: SDO pin pull-up disconnected (default); 1: SDO pin with pull-up)||||||| ## **9.2 FIFO_CTRL1 (07h)** FIFO control register 1 (R/W) ## **Table 11. FIFO_CTRL1 register** |WTM7|WTM7|WTM6|WTM5|WTM4|WTM3|WTM2|WTM1|WTM0| |---|---|---|---|---|---|---|---|---| |**Table 12.FIFO_CTRL1 register description**||||||||| |WTM[7:0]|FIFO watermark threshold, in conjunction with WTM8 inFIFO_CTRL2 (08h).<br>1 LSB = 1 sensor (6 bytes) + TAG (1 byte) written in FIFO<br>Watermark flag rises when the number of bytes written in the FIFO is greater than or equal to the threshold level.|||||||| ## **9.3 FIFO_CTRL2 (08h)** FIFO control register 2 (R/W) **Table 13. FIFO_CTRL2 register** |STOP_ON<br>_WTM|0(1)|0(1)|0(1)|0(1)|0(1)|0(1)|WTM8| |---|---|---|---|---|---|---|---| |_1._<br>_This bit must be set to 0 for the correct operation of the device._|||||||| **Table 14. FIFO_CTRL2 register description** ||**Table 14.FIFO_CTRL2 register description**| |---|---| |STOP_ON_WTM|Sensing chain FIFO stop values memorization at threshold level<br>(0: FIFO depth is not limited (default);<br>1: FIFO depth is limited to threshold level, defined inFIFO_CTRL1 (07h)and FIFO_CTRL2 (08h))| |WTM8|FIFO watermark threshold, in conjunction with WTM_FIFO[7:0] inFIFO_CTRL1 (07h)<br>1 LSB = 1 sensor (6 bytes) + TAG (1 byte) written in FIFO<br>Watermark flag rises when the number of bytes written in the FIFO is greater than or equal to the threshold<br>level.| **DS15022** - **Rev 1** **page 28/59** **IIS3DWBG1 Register description** ## **9.4 FIFO_CTRL3 (09h)** FIFO control register 3 (R/W) ## **Table 15. FIFO_CTRL3 register** 0[(1)] 0[(1)] 0[(1)] 0[(1)] BDR_XL_3 BDR_XL_2 BDR_XL_1 BDR_XL_0 _1. This bit must be set to 0 for the correct operation of the device._ ## **Table 16. FIFO_CTRL3 register description** BDR_XL_[3:0] Selects batch data rate (write frequency in FIFO) for accelerometer data. (0000: accelerometer not batched in FIFO (default); 1010: 26667 Hz; 1011 - 1111: not allowed) ## **9.5 FIFO_CTRL4 (0Ah)** FIFO control register 4 (R/W) ## **Table 17. FIFO_CTRL4 register** |DEC_TS_<br>BATCH_1|DEC_TS_<br>BATCH_0|ODR_T_<br>BATCH_1|ODR_T_<br>BATCH_0|0(1)|FIFO_<br>MODE_2|FIFO_<br>MODE_1|FIFO_<br>MODE_0| |---|---|---|---|---|---|---|---| _1. This bit must be set to 0 for the correct operation of the device._ ## **Table 18. FIFO_CTRL4 register description** ||**Table 18.FIFO_CTRL4 register description**| |---|---| |DEC_TS_ BATCH[1:0]|Selects decimation for timestamp batching in FIFO.<br>The write rate is the rate between the accelerometer BDR divided by the decimation decoder.<br>(00: timestamp not batched in FIFO (default);<br>01: decimation 1: BDR_XL[Hz];<br>10: decimation 8: BDR_XL[Hz]/8;<br>11: decimation 32: BDR_XL[Hz]/32)| |ODR_T_ BATCH[1:0]|Selects batch data rate (write frequency in FIFO) for temperature data<br>(00: temperature not batched in FIFO (default);<br>11: 104 Hz)| |FIFO_ MODE[2:0]|FIFO mode selection<br>(000: bypass mode: FIFO disabled;<br>001: FIFO mode: stops collecting data when FIFO is full;<br>010: reserved;<br>011: continuous-to-FIFO mode: continuous mode until the trigger is deasserted, then FIFO mode;<br>100: bypass-to-continuous mode: bypass mode until the trigger is deasserted, then continuous mode;<br>101: reserved;<br>110: continuous mode: if the FIFO is full, the new sample overwrites the older one;<br>111: bypass-to-FIFO mode: bypass mode until the trigger is deasserted, then FIFO mode.)| **DS15022** - **Rev 1** **page 29/59** **IIS3DWBG1 Register description** ## **9.6 COUNTER_BDR_REG1 (0Bh)** Counter batch data rate register 1 (R/W) ## **Table 19. COUNTER_BDR_REG1 register** |dataready<br>_pulsed|RST_<br>COUNTER<br>_BDR|0(1)|0(1)|0(1)|CNT_BDR<br>_TH_10|CNT_BDR<br>_TH_9|CNT_BDR<br>_TH_8| |---|---|---|---|---|---|---|---| _1. This bit must be set to 0 for the correct operation of the device._ ## **Table 20. COUNTER_BDR_REG1 register description** ||**Table 20.COUNTER_BDR_REG1 register description**| |---|---| |dataready_pulsed|Enables pulsed data-ready mode<br>(0: data-ready latched mode (returns to 0 only after an interface reading) (default); 1: data-ready<br>pulsed mode (the data ready pulses are 18.75 µs long)| |RST_<br>COUNTER_BDR|Resets the internal counter of batch events. This bit is automatically reset to zero if it was set to 1.| |CNT_BDR_TH_<br>[10:8]|In conjunction with CNT_BDR_TH[7:0] inCOUNTER_BDR_REG2 (0Ch), sets the threshold for the<br>internal counter of batch events. When this counter reaches the threshold, the counter is reset and the<br>COUNTER_BDR_IA flag inFIFO_STATUS2 (3Bh)is set to 1.| ## **9.7 COUNTER_BDR_REG2 (0Ch)** Counter batch data rate register 2 (R/W) ## **Table 21. COUNTER_BDR_REG2 register** |CNT_BDR<br>_TH_7|CNT_BDR<br>_TH_6|CNT_BDR<br>_TH_5|CNT_BDR<br>_TH_4|CNT_BDR<br>_TH_3|CNT_BDR<br>_TH_2|CNT_BDR<br>_TH_1|CNT_BDR<br>_TH_0| |---|---|---|---|---|---|---|---| ## **Table 22. COUNTER_BDR_REG2 register description** In conjunction with CNT_BDR_TH[10:8] in COUNTER_BDR_REG1 (0Bh), sets the threshold for the CNT_BDR_TH_ internal counter of batch events. When this counter reaches the threshold, the counter is reset and the [7:0] COUNTER_BDR_IA flag in FIFO_STATUS2 (3Bh) is set to 1. **DS15022** - **Rev 1** **page 30/59** **IIS3DWBG1 Register description** ## **9.8 INT1_CTRL (0Dh)** INT1 pin control register (R/W) Each bit in this register enables a signal to be carried over INT1. ## **Table 23. INT1_CTRL register** |0(1)|INT1_<br>CNT_BDR|INT1_<br>FIFO _FULL|INT1_<br>FIFO_ OVR|INT1_<br>FIFO_TH|INT1_<br>BOOT|0(1)|INT1_<br>DRDY_XL| |---|---|---|---|---|---|---|---| _1. This bit must be set to 0 for the correct operation of the device._ **Table 24. INT1_CTRL register description** ||**Table 24.INT1_CTRL register description**| |---|---| |INT1_CNT_BDR|Enables COUNTER_BDR_IA interrupt on INT1.| |INT1_ FIFO _FULL|Enables FIFO full flag interrupt on INT1 pin.| |INT1_ FIFO_ OVR|Enables FIFO overrun interrupt on INT1 pin.| |INT1_FIFO_TH|Enables FIFO threshold interrupt on INT1 pin.| |INT1_BOOT|Enables boot status on INT1 pin| |INT1_ DRDY_XL|Enables accelerometer data-ready interrupt on INT1 pin.| ## **9.9** ## **INT2_CTRL (0Eh)** INT2 pin control register (R/W) Each bit in this register enables a signal to be carried over INT2. **Table 25. INT2_CTRL register** |0(1)|INT2_<br>CNT_BDR|INT2_<br>FIFO _FULL|INT2_<br>FIFO_ OVR|INT2_<br>FIFO_TH|INT2_<br>DRDY_TEMP|0(1)|INT2_<br>DRDY_XL| |---|---|---|---|---|---|---|---| _1. This bit must be set to 0 for the correct operation of the device._ **Table 26. INT2_CTRL register description** ||**Table 26.INT2_CTRL register description**| |---|---| |INT2_CNT_BDR|Enables COUNTER_BDR_IA interrupt on INT2.| |INT2_ FIFO _FULL|Enables FIFO full flag interrupt on INT2 pin.| |INT2_ FIFO_ OVR|Enables FIFO overrun interrupt on INT2 pin.| |INT2_FIFO_TH|Enables FIFO threshold interrupt on INT2 pin.| |INT2_DRDY_TEMP|Enables temperature sensor data-ready interrupt on INT2 pin.| |INT2_ DRDY_XL|Enables accelerometer data-ready interrupt on INT2 pin.| ## **9.10 WHO_AM_I (0Fh)** Device identification register **Table 27. WHO_AM_I register** 0 1 1 1 1 0 1 1 **DS15022** - **Rev 1** **page 31/59** **IIS3DWBG1 Register description** ## **9.11 CTRL1_XL (10h)** Accelerometer control register 1 (R/W) ## **Table 28. CTRL1_XL register** XL_EN_2 XL_EN_1 XL_EN_0 0[(1)] FS1_XL FS0_XL LPF2_XL_EN 0[(1)] _1. This bit must be set to 0 for the correct operation of the device._ **Table 29. CTRL1_XL register description** ||**Table 29.CTRL1_XL register description**| |---|---| |XL_EN[2:0]|Enables accelerometer:<br>(000: power-down (default);<br>101: accelerometer enabled;)<br>All other configurations are not allowed.| |FS[1:0]_XL|Selects accelerometer full-scale (seeTable 30).| |LPF2_XL_EN|Selects accelerometer high-resolution.<br>(0: output from first stage digital filtering selected (default);<br>1: output from LPF2 second filtering stage selected)| **Table 30. Accelerometer full-scale selection** |**FS[1:0]_XL**|**Full scale**| |---|---| |00 (default)|±2_g_| |01|±16_g_| |10|±4_g_| |11|±8_g_| **DS15022** - **Rev 1** **page 32/59** **IIS3DWBG1 Register description** ## **9.12 CTRL3_C (12h)** Control register 3 (R/W) ## **Table 31. CTRL3_C register** BOOT BDU H_LACTIVE PP_OD SIM IF_INC 0[(1)] SW_RESET _1. This bit must be set to 0 for the correct operation of the device._ ## **Table 32. CTRL3_C register description** ||**Table 32.CTRL3_C register description**| |---|---| |BOOT|Reboots memory content. Default value: 0<br>(0: normal mode; 1: reboot memory content)<br>_Note:_<br>_The accelerometer must be ON. This bit is automatically cleared._| |BDU|Block data update. Default value: 0<br>(0: continuous update;<br>1: output registers are not updated until MSB and LSB have been read)| |H_LACTIVE|Interrupt activation level. Default value: 0<br>(0: interrupt output pins active high; 1: interrupt output pins active low)| |PP_OD|Push-pull/open-drain selection on INT1 and INT2 pins. Default value: 0<br>(0: push-pull mode; 1: open-drain mode)| |SIM|SPI serial interface mode selection. Default value: 0<br>(0: 4-wire interface; 1: 3-wire interface)| |IF_INC|Register address automatically incremented during a multiple byte access with a serial interface (I²C or SPI).<br>Default value: 1<br>(0: disabled; 1: enabled)| |SW_RESET|Software reset. Default value: 0<br>(0: normal mode; 1: reset device)<br>This bit is automatically cleared.| **DS15022** - **Rev 1** **page 33/59** **IIS3DWBG1 Register description** ## **9.13 CTRL4_C (13h)** Control register 4 (R/W) ## **Table 33. CTRL4_C register** |0(1)|0(1)|INT2_<br>on_INT1|0(1)|DRDY_<br>MASK|I2C_disable|0(1)|1AX_TO_<br>3REGOUT| |---|---|---|---|---|---|---|---| _1. This bit must be set to 0 for the correct operation of the device._ ## **Table 34. CTRL4_C register description** ||**Table 34.CTRL4_C register description**| |---|---| |INT2_on_INT1|Enables bit to route all interrupt signals available on INT1 pin. Default value: 0<br>(0: interrupt signals divided between INT1 and INT2 pins;<br>1: all interrupt signals in logic OR on INT1 pin)| |DRDY_MASK|Enables data available<br>(0: disabled;<br>1: mask DRDY on pin until filter settling ends.| |I2C_disable|Disables I²C interface. Default value: 0<br>(0: SPI and I²C interfaces enabled (default); 1: I²C interface disabled)| |1AX_TO_3REGOUT|In single-axis mode, uses the output of the XYZ registers to give 3 consecutive samples of the selected<br>single axis.| ## **9.14 CTRL5_C (14h)** Control register 5 (R/W) ## **Table 35. CTRL5_C register** 0[(1)] ROUNDING1 ROUNDING0 0[(1)] 0[(1)] 0[(1)] ST1_XL ST0_XL _1. This bit must be set to 0 for the correct operation of the device._ ## **Table 36. CTRL5_C register description** ||**Table 36.CTRL5_C register description**| |---|---| |ROUNDING[1:0]|Circular burst mode (wraparound) read from the output registers. Default value: 00<br>(00: no wraparound;<br>01: wraparound enabled)| |ST[1:0]_XL|Enables linear acceleration sensor self-test. Default value: 00<br>(00: self-test disabled; other: refer toTable 37)| ## **Table 37. Linear acceleration sensor self-test mode selection** |**ST1_XL**|**ST0_XL**|**Self-test mode**| |---|---|---| |0|0|Normal mode| |0|1|Positive sign self-test| |1|0|Negative sign self-test| |1|1|Not allowed| **DS15022** - **Rev 1** **page 34/59** **IIS3DWBG1 Register description** ## **9.15 CTRL6_C (15h)** Control register 6 (R/W) ## **Table 38. CTRL6_C register** |0(1)|0(1)|0(1)|0(1)|USR_<br>OFF_W|0(1)|XL_AXIS_<br>SEL_1|XL_AXIS_<br>SEL_0| |---|---|---|---|---|---|---|---| _1. This bit must be set to 0 for the correct operation of the device._ ## **Table 39. CTRL6_C register description** ||**Table 39.CTRL6_C register description**| |---|---| |USR_OFF_W|Weight of accelerometer user offset bits of registersX_OFS_USR (73h),Y_OFS_USR (74h),<br>Z_OFS_USR (75h)<br>(0 = 2-10 _g_/LSB;<br>1 = 2-6 _g_/LSB)| |XL_AXIS_SEL[1:0]|Selects the active axis of the accelerometer in single-axis mode. Refer toTable 40<br>The selection or the switching of the active axis (3 axes or 1 axis among X, Y, Z) should be performed<br>when the device is in power-down condition| **Table 40. Accelerometer active axis** |**XL_AXIS_ SEL[1:0]**|**Active axis**| |---|---| |00 (default)|3 axes (XYZ)| |01|X-axis| |10|Y-axis| |11|Z-axis| ## **9.16** ## **CTRL7_C (16h)** Control register 7 (R/W) ## **Table 41. CTRL7_C register** |0(1)|0(1)|0(1)|0(1)|0(1)|0(1)|USR_OFF_<br>ON_OUT|0(1)| |---|---|---|---|---|---|---|---| _1. This bit must be set to 0 for the correct operation of the device._ ## **Table 42. CTRL7_C register description** Enables the accelerometer user offset correction block; it is valid for the low-pass path - see Figure 10. Accelerometer composite filter. Default value: 0 USR_OFF_ON_OUT (0: accelerometer user offset correction block bypassed; (1: accelerometer user offset correction block enabled) **DS15022** - **Rev 1** **page 35/59** **IIS3DWBG1 Register description** ## **9.17 CTRL8_XL (17h)** Control register 8 (R/W) ## **Table 43. CTRL8_XL register** |HPCF_XL_2|HPCF_XL_1|HPCF_XL_0|HP_REF_<br>MODE_XL|FASTSETTL_<br>MODE_XL|FDS|0(1)|0(1)| |---|---|---|---|---|---|---|---| _1. This bit must be set to 0 for the correct operation of the device._ ## **Table 44. CTRL8_XL register description** ||**Table 44.CTRL8_XL register description**| |---|---| |HPCF_XL_[2:0]|Accelerometer LPF2 and HP filter configuration and cutoff setting. Refer toTable 45.| |HP_REF_MODE_XL|Enables accelerometer high-pass filter reference mode (valid for high-pass path - FDS bit must be 1<br>and HPCF_XL_[2:0] must be set to 111). Default value: 0(1)<br>(0: disabled, 1: enabled)| |FASTSETTL_MODE_XL|Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the second samples after<br>writing this bit. Default value: 0<br>(0: disabled, 1: enabled)| |FDS|Accelerometer low-pass / high-pass filter selection. Refer toFigure 10.| _1. When enabled, the first output data have to be discarded._ **Table 45. Accelerometer bandwidth configurations** |**Filter type**|**FDS**|**LPF2_XL_EN**|**HPCF_XL_[2:0]**|**Bandwidth**| |---|---|---|---|---| |Low pass|0|0|-|6.3 kHz| |||1|000|ODR/4| ||||001|ODR/10| ||||010|ODR/20| ||||011|ODR/45| ||||100|ODR/100| ||||101|ODR/200| ||||110|ODR/400| ||||111|ODR/800| |High pass|1|--|000|SLOPE (ODR/4)| ||||001|ODR/10| ||||010|ODR/20| ||||011|ODR/45| ||||100|ODR/100| ||||101|ODR/200| ||||110|ODR/400| ||||111|ODR/800| **DS15022** - **Rev 1** **page 36/59** **IIS3DWBG1 Register description** ## **9.18 CTRL10_C (19h)** Control register 10 (R/W) ## **Table 46. CTRL10_C register** |0(1)|0(1)|TIMESTAMP<br>_EN|0(1)|0(1)|0(1)|0(1)|0(1)| |---|---|---|---|---|---|---|---| _1. This bit must be set to 0 for the correct operation of the device._ ## **Table 47. CTRL10_C register description** Enables timestamp counter. Default value: 0 (0: disabled; 1: enabled) TIMESTAMP_EN The counter is readable in TIMESTAMP0 (40h), TIMESTAMP1 (41h), TIMESTAMP2 (42h), and TIMESTAMP3 (43h). ## **9.19 ALL_INT_SRC (1Ah)** Source register for all interrupts (R) ## **Table 48. ALL_INT_SRC register** |TIMESTAMP<br>_ENDCOUNT|0|SLEEP_<br>CHANGE_IA|0|0|0|WU_IA|0| |---|---|---|---|---|---|---|---| **Table 49. ALL_INT_SRC register description** |TIMESTAMP_ENDCOUNT|Alerts timestamp overflow within 6.4 ms| |---|---| |SLEEP_CHANGE_IA|Detects change event in activity/inactivity status. Default value: 0<br>(0: change status not detected; 1: change status detected)| |WU_IA|Wake-up event status. Default value: 0<br>(0: event not detected, 1: event detected)| **DS15022** - **Rev 1** **page 37/59** **IIS3DWBG1 Register description** ## **9.20 WAKE_UP_SRC (1Bh)** Wake-up interrupt source register (R) ## **Table 50. WAKE_UP_SRC register** |0|SLEEP_<br>CHANGE_IA|0|SLEEP_<br>STATE_IA|WU_IA|X_WU|Y_WU|Z_WU| |---|---|---|---|---|---|---|---| ## **Table 51. WAKE_UP_SRC register description** Detects change event in activity/inactivity status. Default value: 0 SLEEP_CHANGE_IA (0: change status not detected; 1: change status detected) Sleep event status. Default value: 0 SLEEP_STATE_IA (0: sleep event not detected; 1: sleep event detected) Wake-up event detection status. Default value: 0 WU_IA (0: wake-up event not detected; 1: wake-up event detected.) Wake-up event detection status on X-axis. Default value: 0 X_WU (0: wake-up event on X-axis not detected; 1: wake-up event on X-axis detected) Wake-up event detection status on Y-axis. Default value: 0 Y_WU (0: wake-up event on Y-axis not detected; 1: wake-up event on Y-axis detected) Wake-up event detection status on Z-axis. Default value: 0 Z_WU (0: wake-up event on Z-axis not detected; 1: wake-up event on Z-axis detected) ## **9.21 STATUS_REG (1Eh)** Status register (R) ## **Table 52. STATUS_REG register** 0 0 0 0 0 TDA 0 XLDA ## **Table 53. STATUS_REG register description** ||**Table 53.STATUS_REG register description**| |---|---| |TDA|Temperature new data available. Default: 0<br>(0: no set of data is available at temperature sensor output;<br>1: a new set of data is available at temperature sensor output)| |XLDA|Accelerometer new data available. Default value: 0<br>(0: no set of data available at accelerometer output;<br>1: a new set of data is available at accelerometer output)| **DS15022** - **Rev 1** **page 38/59** **IIS3DWBG1 Register description** ## **9.22 OUT_TEMP_L (20h), OUT_TEMP_H (21h)** Temperature data output register (R). L and H registers together express a 16-bit word in two’s complement. ## **Table 54. OUT_TEMP_L register** |Temp7|Temp6|Temp5|Temp4|Temp3|Temp2|Temp1|Temp0| |---|---|---|---|---|---|---|---| |**Table 55.OUT_TEMP_H register**|||||||| |Temp15|Temp14|Temp13|Temp12|Temp11|Temp10|Temp9|Temp8| ## **Table 56. OUT_TEMP register description** Temperature sensor output data Temp[15:0] The value is expressed as two’s complement sign extended on the MSB. ## **9.23** ## **OUTX_L_A (28h) and OUTX_H_A (29h)** Linear acceleration sensor X-axis output register (R). The value is expressed as a 16-bit word in two’s complement. ## **Table 57. OUTX_L_A register** |D7|D6|D6|D5|D5|D4|D4|D3|D3|D2|D2|D1|D1|D0|D0| |---|---|---|---|---|---|---|---|---|---|---|---|---|---|---| |**Table 58.OUTX_H_A register**||||||||||||||| |D15||D14||D13||D12||D11||D10||D9||D8| ## **Table 59. OUTX_H_A register description** X-axis linear acceleration value D[15:0] D[15:0] expressed in two’s complement **DS15022** - **Rev 1** **page 39/59** **IIS3DWBG1 Register description** ## **9.24 OUTY_L_A (2Ah) and OUTY_H_A (2Bh)** Linear acceleration sensor Y-axis output register (R). The value is expressed as a 16-bit word in two’s complement. ## **Table 60. OUTY_L_A register** |D7|D6|D6|D5|D5|D4|D4|D3|D3|D2|D2|D1|D1|D0|D0| |---|---|---|---|---|---|---|---|---|---|---|---|---|---|---| |**Table 61.OUTY_H_A register**||||||||||||||| |D15||D14||D13||D12||D11||D10||D9||D8| ## **Table 62. OUTY_H_A register description** Y-axis linear acceleration value D[15:0] D[15:0] expressed in two’s complement ## **9.25** ## **OUTZ_L_A (2Ch) and OUTZ_H_A (2Dh)** Linear acceleration sensor Z-axis output register (R). The value is expressed as a 16-bit word in two’s complement. ## **Table 63. OUTZ_L_A register** |D7|D6|D6|D5|D5|D4|D4|D3|D3|D2|D2|D1|D1|D0|D0| |---|---|---|---|---|---|---|---|---|---|---|---|---|---|---| |**Table 64.OUTZ_H_A register**||||||||||||||| |D15||D14||D13||D12||D11||D10||D9||D8| ## **Table 65. OUTZ_H_A register description** Z-axis linear acceleration value D[15:0] D[15:0] expressed in two’s complement **DS15022** - **Rev 1** **page 40/59** **IIS3DWBG1 Register description** ## **9.26 FIFO_STATUS1 (3Ah)** FIFO status register 1 (R) ## **Table 66. FIFO_STATUS1 register** |DIFF_<br>FIFO_7|DIFF_<br>FIFO_6|DIFF_<br>FIFO_5|DIFF_<br>FIFO_4|DIFF_<br>FIFO_3|DIFF_<br>FIFO_2|DIFF_<br>FIFO_1|DIFF_<br>FIFO_0| |---|---|---|---|---|---|---|---| ## **Table 67. FIFO_STATUS1 register description** DIFF_FIFO_[7:0] Number of unread sensor data (TAG + 6 bytes) stored in FIFO In conjunction with DIFF_FIFO[9:8] in FIFO_STATUS2 (3Bh). ## **9.27 FIFO_STATUS2 (3Bh)** FIFO status register 2 (R) ## **Table 68. FIFO_STATUS2 register** |FIFO_<br>WTM_IA|FIFO_<br>OVR_IA|FIFO_<br>FULL_IA|COUNTER_<br>BDR_IA|FIFO_OVR_<br>LATCHED|0|DIFF_<br>FIFO_9|DIFF_<br>FIFO_8| |---|---|---|---|---|---|---|---| ## **Table 69. FIFO_STATUS2 register description** ||**Table 69.FIFO_STATUS2 register description**| |---|---| |FIFO_WTM_IA|FIFO watermark status. Default value: 0<br>(0: FIFO filling is lower than WTM;<br>1: FIFO filling is equal to or greater than WTM)<br>Watermark is set through bits WTM[8:0] inFIFO_CTRL2 (08h)andFIFO_CTRL1 (07h).| |FIFO_OVR_IA|FIFO overrun status. Default value: 0<br>(0: FIFO is not completely filled; 1: FIFO is completely filled)| |FIFO_FULL_IA|Smart FIFO full status. Default value: 0<br>(0: FIFO is not full; 1: FIFO is full at the next ODR)| |COUNTER_BDR_IA|Counter BDR reaches the CNT_BDR_TH_[10:0] threshold set inCOUNTER_BDR_REG1 (0Bh)and<br>COUNTER_BDR_REG2 (0Ch). Default value: 0<br>This bit is reset when these registers are read.| |FIFO_OVR_LATCHED|Latched FIFO overrun status. Default value: 0<br>This bit is reset when this register is read.| |DIFF_FIFO_[9:8]|Number of unread sensor data (TAG + 6 bytes) stored in FIFO. Default value: 00<br>In conjunction with DIFF_FIFO[7:0] inFIFO_STATUS1 (3Ah)| **DS15022** - **Rev 1** **page 41/59** **IIS3DWBG1 Register description** ## **9.28 TIMESTAMP0 (40h), TIMESTAMP1 (41h), TIMESTAMP2 (42h), and TIMESTAMP3 (43h)** Timestamp first data output register (R). The value is expressed as a 32-bit word and the bit resolution is 12.5 µs. **Table 70. TIMESTAMP output registers** |D31|D30|D30|D29|D29|D28|D28|D27|D27|D26|D26|D25|D25|D24|D24| |---|---|---|---|---|---|---|---|---|---|---|---|---|---|---| |||||||||||||||| |D23|D22||D21||D20||D19||D18||D17||D16|| |||||||||||||||| |D15||D14||D13||D12||D11||D10||D9||D8| |||||||||||||||| |D7|D6||D5||D4||D3||D2||D1||D0|| ## **Table 71. TIMESTAMP output register description** D[31:0] Timestamp output registers: 1LSB = 12.5 µs The formula below can be used to calculate a better estimation of the actual timestamp resolution: TS_Res = 1 / (80000 + (0.0015 * INTERNAL_FREQ_FINE * 80000)) where INTERNAL_FREQ_FINE is the content of INTERNAL_FREQ_FINE (63h). ## **9.29 SLOPE_EN (56h)** Slope enable (R/W) ## **Table 72. SLOPE_EN register** |0(1)|0(1)|SLEEP_STATUS<br>_ON_INT|SLOPE_FDS|0(1)|0(1)|0(1)|LIR| |---|---|---|---|---|---|---|---| _1. This bit must be set to 0 for the correct operation of the device._ ## **Table 73. SLOPE_EN register description** ||**Table 73.SLOPE_EN register description**| |---|---| |SLEEP_STATUS_ON_INT|Activity/inactivity interrupt mode configuration. If the INT1_SLEEP_CHANGE or<br>INT2_SLEEP_CHANGE bits are enabled, drives the sleep status or sleep change on the INT<br>pins. Default value: 0<br>(0: sleep change notification on INT pins; 1: sleep status reported on INT pins)| |SLOPE_FDS|HPF or slope filter selection on wake-up and activity/inactivity functions. Default value: 0<br>(0: slope filter applied; 1: HPF applied)| |LIR|Latched interrupt. Default value: 0<br>(0: interrupt request not latched; 1: interrupt request latched)| **DS15022** - **Rev 1** **page 42/59** **IIS3DWBG1 Register description** ## **9.30 INTERRUPTS_EN (58h)** Enables interrupt functions (R/W) ## **Table 74. INTERRUPTS_EN register** |INTERRUPTS<br>_ENABLE|0(1)|0(1)|0(1)|0(1)|0(1)|0(1)|0(1)| |---|---|---|---|---|---|---|---| _1. This bit must be set to 0 for the correct operation of the device._ ## **Table 75. INTERRUPTS_EN register description** INTERRUPTS_ENABLE Enables wake-up and activity/inactivity interrupt logic. Default value: 0 (0: interrupt disabled; 1: interrupt enabled) ## **9.31 WAKE_UP_THS (5Bh)** Wake-up configuration (R/W) ## **Table 76. WAKE_UP_THS register** |0(1)|USR_OFF_<br>ON_WU|WK_THS5|WK_THS4|WK_THS3|WK_THS2|WK_THS1|WK_THS0| |---|---|---|---|---|---|---|---| _1. This bit must be set to 0 for the correct operation of the device._ ## **Table 77. WAKE_UP_THS register description** USR_OFF_ON_WU[Drives the low-pass filtered data with user offset correction (instead of high-pass filtered data) to the ] wake-up function. Threshold for wake-up: 1 LSB weight depends on WAKE_THS_W in WAKE_UP_DUR (5Ch). Default WK_THS[5:0] value: 000000 ## **9.32 WAKE_UP_DUR (5Ch)** Wake-up and sleep mode functions duration setting register (R/W) ## **Table 78. WAKE_UP_DUR register** |0(1)|WAKE_<br>DUR1|WAKE_<br>DUR0|WAKE_<br>THS_W|SLEEP_<br>DUR3|SLEEP_<br>DUR2|SLEEP_<br>DUR1|SLEEP_<br>DUR0| |---|---|---|---|---|---|---|---| _1. This bit must be set to 0 for the correct operation of the device._ ## **Table 79. WAKE_UP_DUR register description** ||**Table 79.WAKE_UP_DUR register description**| |---|---| |WAKE_DUR[1:0]|Wake-up duration event. Default: 00<br>1LSB = 1 ODR_time| |WAKE_THS_W|Weight of 1 LSB of wake-up threshold. Default: 0<br>(0: 1 LSB = FS_XL / (26);<br>1: 1 LSB = FS_XL / (28))| |SLEEP_DUR[3:0]|Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR)<br>1 LSB = 512 ODR| **DS15022** - **Rev 1** **page 43/59** **IIS3DWBG1 Register description** ## **9.33 MD1_CFG (5Eh)** Functions routing to INT1 register (R/W) ## **Table 80. MD1_CFG register** |INT1_SLEEP<br>_CHANGE|0(1)|INT1_WU|0(1)|0(1)|0(1)|0(1)|0(1)| |---|---|---|---|---|---|---|---| _1. This bit must be set to 0 for the correct operation of the device._ ## **Table 81. MD1_CFG register description** ||**Table 81.MD1_CFG register description**| |---|---| |INT1_SLEEP_CHANGE(1)|Routing activity/inactivity recognition event to INT1. Default: 0<br>(0: routing activity/inactivity event to INT1 disabled;<br>1: routing activity/inactivity event to INT1 enabled)| |INT1_WU|Routing wake-up event to INT1. Default value: 0<br>(0: routing wake-up event to INT1 disabled;<br>1: routing wake-up event to INT1 enabled)| _1. Activity/inactivity interrupt mode (sleep change or sleep status) depends on the SLEEP_STATUS_ON_INT bit in the SLOPE_EN (56h) register._ ## **9.34 MD2_CFG (5Fh)** Functions routing to INT2 register (R/W) ## **Table 82. MD2_CFG register** |INT2_SLEEP<br>_CHANGE|0(1)|INT2_WU|INT2_WU|0(1)|0(1)|0(1)|0(1)|INT2_<br>TIMESTAMP| |---|---|---|---|---|---|---|---|---| |_1._<br>_This bit must be set to 0 for the correct operation of the device._||||||||| |INT2_SLEEP_CHANGE(1)|||Routing activity/inactivity recognition event to INT2. Default: 0<br>(0: routing activity/inactivity event to INT2 disabled;<br>1: routing activity/inactivity event to INT2 enabled)|||||| |INT2_WU|||Routing wake-up event to INT2. Default value: 0<br>(0: routing wake-up event to INT2 disabled;<br>1: routing wake-up event to INT2 enabled)|||||| |INT2_TIMESTAMP|||Enables routing the alert for timestamp overflow within 6.4 ms to the INT2 pin|||||| _1. Activity/inactivity interrupt mode (sleep change or sleep status) depends on the SLEEP_STATUS_ON_INT bit in the SLOPE_EN (56h) register._ **DS15022** - **Rev 1** **page 44/59** **IIS3DWBG1 Register description** ## **9.35 INTERNAL_FREQ_FINE (63h)** Internal frequency register (R) ## **Table 83. INTERNAL_FREQ_FINE register** |FREQ_<br>FINE7|FREQ_<br>FINE6|FREQ_<br>FINE5|FREQ_<br>FINE4|FREQ_<br>FINE3|FREQ_<br>FINE2|FREQ_<br>FINE1|FREQ_<br>FINE0| |---|---|---|---|---|---|---|---| ## **Table 84. INTERNAL_FREQ_FINE register description** FREQ_FINE[7:0][Difference in percentage of the effective ODR (and timestamp rate) with respect to the typical. Step: 0.15%. ] 8-bit format, two's complement. The formula below can be used to calculate a better estimation of the actual ODR: ODR_Actual = (26667 + ((0.0015 * INTERNAL_FREQ_FINE) * 26667)) ## **9.36** ## **X_OFS_USR (73h)** Accelerometer X-axis user offset correction (R/W). The offset value set in the X_OFS_USR offset register is internally subtracted from the acceleration value measured on the X-axis. **Table 85. X_OFS_USR register** |X_OFS_<br>USR_7|X_OFS_<br>USR_6|X_OFS_<br>USR_5|X_OFS_<br>USR_4|X_OFS_<br>USR_3|X_OFS_<br>USR_2|X_OFS_<br>USR_1|X_OFS_<br>USR_0| |---|---|---|---|---|---|---|---| ## **Table 86. X_OFS_USR register description** X_OFS_USR_[7:0][Accelerometer X-axis user offset correction expressed in two’s complement, weight depends on ] USR_OFF_W in CTRL6_C (15h). The value must be in the range [-127 127]. ## **9.37** ## **Y_OFS_USR (74h)** Accelerometer Y-axis user offset correction (R/W). The offset value set in the Y_OFS_USR offset register is internally subtracted from the acceleration value measured on the Y-axis. ## **Table 87. Y_OFS_USR register** |Y_OFS_<br>USR_7|Y_OFS_<br>USR_6|Y_OFS_<br>USR_5|Y_OFS_<br>USR_4|Y_OFS_<br>USR_3|Y_OFS_<br>USR_2|Y_OFS_<br>USR_1|Y_OFS_<br>USR_0| |---|---|---|---|---|---|---|---| ## **Table 88. Y_OFS_USR register description** Y_OFS_USR_[7:0][Accelerometer Y-axis user offset calibration expressed in two’s complement, weight depends on ] USR_OFF_W in CTRL6_C (15h). The value must be in the range [-127, +127]. **DS15022** - **Rev 1** **page 45/59** **IIS3DWBG1 Register description** ## **9.38 Z_OFS_USR (75h)** Accelerometer Z-axis user offset correction (R/W). The offset value set in the Z_OFS_USR offset register is internally subtracted from the acceleration value measured on the Z-axis. ## **Table 89. Z_OFS_USR register** |Z_OFS_<br>USR_7|Z_OFS_<br>USR_6|Z_OFS_<br>USR_5|Z_OFS_<br>USR_4|Z_OFS_<br>USR_3|Z_OFS_<br>USR_2|Z_OFS_<br>USR_1|Z_OFS_<br>USR_0| |---|---|---|---|---|---|---|---| ## **Table 90. Z_OFS_USR register description** Z_OFS_USR_[7:0][Accelerometer Z-axis user offset calibration expressed in two’s complement, weight depends on ] USR_OFF_W in CTRL6_C (15h). The value must be in the range [-127, +127]. ## **9.39 FIFO_DATA_OUT_TAG (78h)** FIFO tag register (R) ## **Table 91. FIFO_DATA_OUT_TAG register** |TAG_<br>SENSOR_4|TAG_<br>SENSOR_3|TAG_<br>SENSOR_2|TAG_<br>SENSOR_1|TAG_<br>SENSOR_0|TAG_CNT_1|TAG_CNT_0|TAG_<br>PARITY| |---|---|---|---|---|---|---|---| ## **Table 92. FIFO_DATA_OUT_TAG register description** ||**Table 92.FIFO_DATA_OUT_TAG register description**| |---|---| |TAG_SENSOR_[4:0]|FIFO tag: identifies the sensor in:<br>FIFO_DATA_OUT_X_L (79h) and FIFO_DATA_OUT_X_H (7Ah),FIFO_DATA_OUT_Y_L (7Bh) and<br>FIFO_DATA_OUT_Y_H (7Ch), andFIFO_DATA_OUT_Z_L (7Dh) and FIFO_DATA_OUT_Z_H (7Eh)<br>For details, refer toTable 93.| |TAG_CNT_[1:0]|2-bit counter that identifies sensor time slot| |TAG_PARITY|Parity check of TAG content| **Table 93. FIFO tag** |**TAG_SENSOR_[4:0]**|**Sensor name**| |---|---| |0x02|Accelerometer| |0x03|Temperature| |0x04|Timestamp| **DS15022** - **Rev 1** **page 46/59** **IIS3DWBG1 Register description** ## **9.40 FIFO_DATA_OUT_X_L (79h) and FIFO_DATA_OUT_X_H (7Ah)** FIFO data output X (R) **Table 94. FIFO_DATA_OUT_X_H and FIFO_DATA_OUT_X_L registers** |D15|D14|D13|D12|D11|D10|D9|D8| |---|---|---|---|---|---|---|---| ||||||||| |D7|D6|D5|D4|D3|D2|D1|D0| ## **Table 95. FIFO_DATA_OUT_X_H and FIFO_DATA_OUT_X_L register description** D[15:0] FIFO X-axis output ## **9.41 FIFO_DATA_OUT_Y_L (7Bh) and FIFO_DATA_OUT_Y_H (7Ch)** FIFO data output Y (R) |**Table 96.FIFO_DATA_OUT_Y_H and FIFO_DATA_OUT_Y_L registers**|**Table 96.FIFO_DATA_OUT_Y_H and FIFO_DATA_OUT_Y_L registers**|**Table 96.FIFO_DATA_OUT_Y_H and FIFO_DATA_OUT_Y_L registers**|**Table 96.FIFO_DATA_OUT_Y_H and FIFO_DATA_OUT_Y_L registers**|**Table 96.FIFO_DATA_OUT_Y_H and FIFO_DATA_OUT_Y_L registers**|**Table 96.FIFO_DATA_OUT_Y_H and FIFO_DATA_OUT_Y_L registers**|**Table 96.FIFO_DATA_OUT_Y_H and FIFO_DATA_OUT_Y_L registers**|**Table 96.FIFO_DATA_OUT_Y_H and FIFO_DATA_OUT_Y_L registers**| |---|---|---|---|---|---|---|---| |D15|D14|D13|D12|D11|D10|D9|D8| ||||||||| |D7|D6|D5|D4|D3|D2|D1|D0| **Table 97. FIFO_DATA_OUT_Y_H and FIFO_DATA_OUT_Y_L register description** D[15:0] FIFO Y-axis output ## **9.42 FIFO_DATA_OUT_Z_L (7Dh) and FIFO_DATA_OUT_Z_H (7Eh)** FIFO data output Z (R) **Table 98. FIFO_DATA_OUT_Z_H and FIFO_DATA_OUT_Z_L registers** |D15|D14|D13|D12|D11|D10|D9|D8| |---|---|---|---|---|---|---|---| ||||||||| |D7|D6|D5|D4|D3|D2|D1|D0| **Table 99. FIFO_DATA_OUT_Z_H and FIFO_DATA_OUT_Z_L register description** D[15:0] FIFO Z-axis output **DS15022** - **Rev 1** **page 47/59** **IIS3DWBG1 Soldering information** **10 Soldering information** The LGA package is compliant with the ECOPACK and RoHS standard. It is qualified for soldering heat resistance according to JEDEC J-STD-020. For land pattern and soldering recommendations, consult technical note TN0018 available on www.st.com. **DS15022** - **Rev 1** **page 48/59** **IIS3DWBG1 Package information** ## **11 Package information** To meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions, and product status are available at: www.st.com. ECOPACK is an ST trademark. ## **11.1 LGA-14L package information** ## **Figure 22. LGA-14L 2.5 x 3.0 x 0.86 mm package outline and mechanical data** **==> picture [427 x 163] intentionally omitted <==** **----- Start of picture text -----**<br> Pin1 indicator<br>W C H 0.5 4x (0.1)<br>Pin 1 indicator<br>14x 0.25±0.05<br>1 14x 0.475±0.05<br>0.05 C<br>TOP VIEW BOTTOM VIEW<br>L<br>1.5<br>0.5<br>**----- End of picture text -----**<br> Dimensions are in millimeter unless otherwise specified General tolerance is +/-0.1mm unless otherwise specified ## OUTER DIMENSIONS |ITEM|DIMENSION [mm]|TOLERANCE [mm]| |---|---|---| |]<br>L<br>[<br>h<br>t<br>g<br>n<br>e<br>L|0<br>5<br>.<br>2|1<br>.<br>0<br>±| |]<br>W<br>[<br>h<br>t<br>di<br>W|0<br>0<br>.<br>3|1<br>.<br>0<br>±| |]<br>H<br>[ t<br>h<br>gie<br>H|6<br>8<br>.<br>0|X<br>A<br>M| |||| **DS15022** - **Rev 1** **page 49/59** **IIS3DWBG1 Package information** ## **11.2 LGA-14L packing information** **Figure 23. Carrier tape information for LGA-14L package** **Figure 24. LGA-14L package orientation in carrier tape** USER DIRECTION OF FEED **DS15022** - **Rev 1** **page 50/59** **IIS3DWBG1 Package information** **Figure 25. Reel information for carrier tape of LGA-14L package** **==> picture [363 x 213] intentionally omitted <==** **----- Start of picture text -----**<br> T<br>40mm min.<br>Access hole at<br>slot location<br>B<br>C<br>D N<br>A<br>G measured at hub<br>Full radius<br>Tape slot<br>in core for<br>tape start<br>2.5mm min. width<br>**----- End of picture text -----**<br> **Table 100. Reel dimensions for carrier tape of LGA-14L package** |**Reel dimensions (mm)**|**Reel dimensions (mm)**| |---|---| |A (max)|330| |B (min)|1.5| |C|13 ±0.25| |D (min)|20.2| |N (min)|60| |G|12.4 +2/-0| |T (max)|18.4| **DS15022** - **Rev 1** **page 51/59** **IIS3DWBG1** ## **Revision history** ## **Table 101. Document revision history** |**Date**|**Version**|**Changes**| |---|---|---| |02-Jul-2025|1|Initial release| **DS15022** - **Rev 1** **page 52/59** **IIS3DWBG1 Contents** |**Contents**|**Contents**|| |---|---|---| |**1**|**Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3**|| ||**1.1**|Default pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4| |**2**|**Module specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5**|| ||**2.1**|Mechanical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5| ||**2.2**|Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6| ||**2.3**|Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7| ||**2.4**|Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8| |||**2.4.1**<br>SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8| ||**2.5**|Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9| ||**2.6**|Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10| |||**2.6.1**<br>Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10| |||**2.6.2**<br>Zero-_g_level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10| |**3**|**Digital interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11**|| ||**3.1**|SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11| ||**3.2**|SPI bus interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12| |||**3.2.1**<br>SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13| |||**3.2.2**<br>SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14| |||**3.2.3**<br>SPI read in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14| |**4**|**Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15**|| ||**4.1**|Operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15| ||**4.2**|Block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16| ||**4.3**|FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17| |||**4.3.1**<br>Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17| |||**4.3.2**<br>FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17| |||**4.3.3**<br>Continuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18| |||**4.3.4**<br>Continuous-to-FIFO mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18| |||**4.3.5**<br>Bypass-to-continuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18| |||**4.3.6**<br>Bypass-to-FIFO mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18| |||**4.3.7**<br>FIFO reading procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18| |**5**|**Frequency response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19**|| |**6**|**Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21**|| ||**6.1**|Frequency response measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21| ||**6.2**|Sensitivity change versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23| ||**6.3**|ODR change versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23| |**7**|**Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24**|| **DS15022** - **Rev 1** **page 53/59** **IIS3DWBG1 Contents** ||**7.1**|IIS3DWBG1 electrical connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24| |---|---|---| ||**7.2**|Measuring the actual ODR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25| |**8**|**Register mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26**|| |**9**|**Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28**|| ||**9.1**|PIN_CTRL (02h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28| ||**9.2**|FIFO_CTRL1 (07h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28| ||**9.3**|FIFO_CTRL2 (08h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28| ||**9.4**|FIFO_CTRL3 (09h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29| ||**9.5**|FIFO_CTRL4 (0Ah). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29| ||**9.6**|COUNTER_BDR_REG1 (0Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30| ||**9.7**|COUNTER_BDR_REG2 (0Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30| ||**9.8**|INT1_CTRL (0Dh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31| ||**9.9**|INT2_CTRL (0Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31| ||**9.10**|WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31| ||**9.11**|CTRL1_XL (10h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32| ||**9.12**|CTRL3_C (12h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33| ||**9.13**|CTRL4_C (13h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34| ||**9.14**|CTRL5_C (14h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34| ||**9.15**|CTRL6_C (15h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35| ||**9.16**|CTRL7_C (16h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35| ||**9.17**|CTRL8_XL (17h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36| ||**9.18**|CTRL10_C (19h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37| ||**9.19**|ALL_INT_SRC (1Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37| ||**9.20**|WAKE_UP_SRC (1Bh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38| ||**9.21**|STATUS_REG (1Eh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38| ||**9.22**|OUT_TEMP_L (20h), OUT_TEMP_H (21h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39| ||**9.23**|OUTX_L_A (28h) and OUTX_H_A (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39| ||**9.24**|OUTY_L_A (2Ah) and OUTY_H_A (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40| ||**9.25**|OUTZ_L_A (2Ch) and OUTZ_H_A (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40| ||**9.26**|FIFO_STATUS1 (3Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41| ||**9.27**|FIFO_STATUS2 (3Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41| ||**9.28**|TIMESTAMP0 (40h), TIMESTAMP1 (41h), TIMESTAMP2 (42h), and TIMESTAMP3 (43h) 42| ||**9.29**|SLOPE_EN (56h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42| ||**9.30**|INTERRUPTS_EN (58h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43| ||**9.31**|WAKE_UP_THS (5Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43| ||**9.32**|WAKE_UP_DUR (5Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43| **DS15022** - **Rev 1** **page 54/59** **IIS3DWBG1 Contents** ||**9.33**|MD1_CFG (5Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44| |---|---|---| ||**9.34**|MD2_CFG (5Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44| ||**9.35**|INTERNAL_FREQ_FINE (63h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45| ||**9.36**|X_OFS_USR (73h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45| ||**9.37**|Y_OFS_USR (74h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45| ||**9.38**|Z_OFS_USR (75h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46| ||**9.39**|FIFO_DATA_OUT_TAG (78h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46| ||**9.40**|FIFO_DATA_OUT_X_L (79h) and FIFO_DATA_OUT_X_H (7Ah) . . . . . . . . . . . . . . . . . . . . . 47| ||**9.41**|FIFO_DATA_OUT_Y_L (7Bh) and FIFO_DATA_OUT_Y_H (7Ch) . . . . . . . . . . . . . . . . . . . . . 47| ||**9.42**|FIFO_DATA_OUT_Z_L (7Dh) and FIFO_DATA_OUT_Z_H (7Eh) . . . . . . . . . . . . . . . . . . . . . 47| |**10**|**Soldering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48**|| |**11**|**Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49**|| ||**11.1**|LGA-14L package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49| ||**11.2**|LGA-14L packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50| |**Revision**||**history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52**| |**List**|**of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56**|| |**List**|**of figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58**|| **DS15022** - **Rev 1** **page 55/59** **IIS3DWBG1 List of tables** ## **List of tables** |**Table**|**1.**|Pin desription . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3| |---|---|---| |**Table**|**2.**|Default pin status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4| |**Table**|**3.**|Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5| |**Table**|**4.**|Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6| |**Table**|**5.**|SPI target timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8| |**Table**|**6.**|Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9| |**Table**|**7.**|Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11| |**Table**|**8.**|Register address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26| |**Table**|**9.**|PIN_CTRL register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28| |**Table**|**10.**|PIN_CTRL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28| |**Table**|**11.**|FIFO_CTRL1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28| |**Table**|**12.**|FIFO_CTRL1 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28| |**Table**|**13.**|FIFO_CTRL2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28| |**Table**|**14.**|FIFO_CTRL2 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28| |**Table**|**15.**|FIFO_CTRL3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29| |**Table**|**16.**|FIFO_CTRL3 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29| |**Table**|**17.**|FIFO_CTRL4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29| |**Table**|**18.**|FIFO_CTRL4 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29| |**Table**|**19.**|COUNTER_BDR_REG1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30| |**Table**|**20.**|COUNTER_BDR_REG1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30| |**Table**|**21.**|COUNTER_BDR_REG2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30| |**Table**|**22.**|COUNTER_BDR_REG2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30| |**Table**|**23.**|INT1_CTRL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31| |**Table**|**24.**|INT1_CTRL register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31| |**Table**|**25.**|INT2_CTRL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31| |**Table**|**26.**|INT2_CTRL register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31| |**Table**|**27.**|WHO_AM_I register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31| |**Table**|**28.**|CTRL1_XL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32| |**Table**|**29.**|CTRL1_XL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32| |**Table**|**30.**|Accelerometer full-scale selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32| |**Table**|**31.**|CTRL3_C register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33| |**Table**|**32.**|CTRL3_C register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33| |**Table**|**33.**|CTRL4_C register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34| |**Table**|**34.**|CTRL4_C register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34| |**Table**|**35.**|CTRL5_C register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34| |**Table**|**36.**|CTRL5_C register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34| |**Table**|**37.**|Linear acceleration sensor self-test mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34| |**Table**|**38.**|CTRL6_C register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35| |**Table**|**39.**|CTRL6_C register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35| |**Table**|**40.**|Accelerometer active axis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35| |**Table**|**41.**|CTRL7_C register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35| |**Table**|**42.**|CTRL7_C register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35| |**Table**|**43.**|CTRL8_XL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36| |**Table**|**44.**|CTRL8_XL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36| |**Table**|**45.**|Accelerometer bandwidth configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36| |**Table**|**46.**|CTRL10_C register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37| |**Table**|**47.**|CTRL10_C register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37| |**Table**|**48.**|ALL_INT_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37| |**Table**|**49.**|ALL_INT_SRC register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37| |**Table**|**50.**|WAKE_UP_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38| |**Table**|**51.**|WAKE_UP_SRC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38| |**Table**|**52.**|STATUS_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38| |**Table**|**53.**|STATUS_REG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38| **DS15022** - **Rev 1** **page 56/59** **IIS3DWBG1 List of tables** **Table 54.** OUT_TEMP_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 **Table 55.** OUT_TEMP_H register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 **Table 56.** OUT_TEMP register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 **Table 57.** OUTX_L_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 **Table 58.** OUTX_H_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 **Table 59.** OUTX_H_A register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 **Table 60.** OUTY_L_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 **Table 61.** OUTY_H_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 **Table 62.** OUTY_H_A register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 **Table 63.** OUTZ_L_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 **Table 64.** OUTZ_H_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 **Table 65.** OUTZ_H_A register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 **Table 66.** FIFO_STATUS1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 **Table 67.** FIFO_STATUS1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 **Table 68.** FIFO_STATUS2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 **Table 69.** FIFO_STATUS2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 **Table 70.** TIMESTAMP output registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 **Table 71.** TIMESTAMP output register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 **Table 72.** SLOPE_EN register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 **Table 73.** SLOPE_EN register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 **Table 74.** INTERRUPTS_EN register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 **Table 75.** INTERRUPTS_EN register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 **Table 76.** WAKE_UP_THS register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 **Table 77.** WAKE_UP_THS register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 **Table 78.** WAKE_UP_DUR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 **Table 79.** WAKE_UP_DUR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 **Table 80.** MD1_CFG register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 **Table 81.** MD1_CFG register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 **Table 82.** MD2_CFG register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 **Table 83.** INTERNAL_FREQ_FINE register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 **Table 84.** INTERNAL_FREQ_FINE register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 **Table 85.** X_OFS_USR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 **Table 86.** X_OFS_USR register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 **Table 87.** Y_OFS_USR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 **Table 88.** Y_OFS_USR register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 **Table 89.** Z_OFS_USR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 **Table 90.** Z_OFS_USR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 **Table 91.** FIFO_DATA_OUT_TAG register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 **Table 92.** FIFO_DATA_OUT_TAG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 **Table 93.** FIFO tag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 **Table 94.** FIFO_DATA_OUT_X_H and FIFO_DATA_OUT_X_L registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 **Table 95.** FIFO_DATA_OUT_X_H and FIFO_DATA_OUT_X_L register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 **Table 96.** FIFO_DATA_OUT_Y_H and FIFO_DATA_OUT_Y_L registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 **Table 97.** FIFO_DATA_OUT_Y_H and FIFO_DATA_OUT_Y_L register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 **Table 98.** FIFO_DATA_OUT_Z_H and FIFO_DATA_OUT_Z_L registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 **Table 99.** FIFO_DATA_OUT_Z_H and FIFO_DATA_OUT_Z_L register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 **Table 100.** Reel dimensions for carrier tape of LGA-14L package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 **Table 101.** Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 **DS15022** - **Rev 1** **page 57/59** **IIS3DWBG1 List of figures** ## **List of figures** |**Figure**|**1.**|Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3| |---|---|---| |**Figure**|**2.**|SPI target timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8| |**Figure**|**3.**|Read and write protocol (in mode 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12| |**Figure**|**4.**|SPI read protocol (in mode 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13| |**Figure**|**5.**|Multiple byte SPI read protocol (2-byte example) (in mode 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13| |**Figure**|**6.**|SPI write protocol (in mode 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14| |**Figure**|**7.**|Multiple byte SPI write protocol (2-byte example) (in mode 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14| |**Figure**|**8.**|SPI read protocol in 3-wire mode (in mode 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14| |**Figure**|**9.**|Accelerometer architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16| |**Figure**|**10.**|Accelerometer composite filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16| |**Figure**|**11.**|Filtering chain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19| |**Figure**|**12.**|Frequency response at the output of LPF1 filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19| |**Figure**|**13.**|Frequency response with LPF2 enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20| |**Figure**|**14.**|Frequency response with HPF enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20| |**Figure**|**15.**|Frequency response - X-axis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21| |**Figure**|**16.**|Frequency response - Y-axis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21| |**Figure**|**17.**|Frequency response - Z-axis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22| |**Figure**|**18.**|Sensitivity change versus temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23| |**Figure**|**19.**|ODR change versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23| |**Figure**|**20.**|IIS3DWBG1 electrical connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24| |**Figure**|**21.**|Accurately measuring ODR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25| |**Figure**|**22.**|LGA-14L 2.5 x 3.0 x 0.86 mm package outline and mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49| |**Figure**|**23.**|Carrier tape information for LGA-14L package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50| |**Figure**|**24.**|LGA-14L package orientation in carrier tape. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50| |**Figure**|**25.**|Reel information for carrier tape of LGA-14L package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51| **DS15022** - **Rev 1** **page 58/59** **IIS3DWBG1 List of figures** ## **IMPORTANT NOTICE – READ CAREFULLY** STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgment. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2025 STMicroelectronics – All rights reserved **DS15022** - **Rev 1** **page 59/59**
Updated at April 22, 2026
STMicroelectronics is a global leader in the semiconductor industry, recognized for developing highly integrated, energy-efficient solutions that power modern electronics. With a strong focus on innovation, ST provides a comprehensive portfolio of microelectronics that address the demanding requirements of industrial, automotive, communications, and consumer applications. Our extensive selection of STMicroelectronics components is built around a robust lineup of discrete semiconductors and circuit protection devices. We offer a wide variety of single MOSFETs, Schottky diodes, and fast and ultrafast recovery rectifier diodes, designed to deliver exceptional efficiency and thermal performance in power management and conversion systems. For robust circuit protection, our inventory features hundreds of transient voltage suppressors and TVS diodes that safeguard sensitive electronic components against destructive voltage spikes. In addition to core power discretes like TRIACs, SCRs, bipolar transistors, and single IGBTs, our STMicroelectronics range includes specialized integrated passive filters and MEMS sensors. Furthermore, ST offers advanced integrated passive devices, such as baluns and RF filters, which utilize high-quality monolithic RF IPD processes on glass or high-resistance silicon substrates. These components provide competitive cost structures, reduced power losses, and simplified RFIC-to-antenna matching, ensuring optimal system performance and delivering the reliability required for next-generation wireless and power designs.
About Novapart
Novapart is a B2B electronic component broker specialising in stock shortages and cost reduction. We source hard-to-find parts and identify compliant alternatives across a catalogue of 410,000+ components from 500+ manufacturers.
Learn more →Stock Shortage Specialist
When a component is unavailable, discontinued or has an unacceptable lead time, we tap into our network of vetted European and Asian distributors to source what you need — without compromising on quality or traceability.
Request a quote →Compliant Alternatives
We identify pin-to-pin, electrically equivalent substitutes that meet the same certifications (RoHS, AEC-Q100, REACH) as your original specification — validated against datasheets, not just part numbers. Often at a lower cost.
BOM Analysis service →