ICM-45605

MEMS Module, MEMS, X, Y, Z (Accelerometer, Gyroscope), 1.71 V, 3.6 V, LGA, 14 Pins

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Manufacturer: TDK INVENSENSE
Product type: MEMS Modules
SVHC: No SVHC (25-Jun-2025)
No. of Pins: 14Pins
Sensing Axis: X, Y, Z (Accelerometer, Gyroscope)
Product Range: -
Supply Voltage Max: 3.6V
Supply Voltage Min: 1.71V
Operating Temperature Max: 85°C
Operating Temperature Min: -40°C
Delivery and price
Units per pack	500
Price	2.99 €
Current stock	10+
Lead time	30 days
Datasheet
**High Performance 6-Axis MEMS MotionTracking Device** 

## _**ICM-45605 Datasheet**_ 

## **ICM-45605 HIGHLIGHTS** 

The ICM-45605 is a high performance 6-axis MEMS MotionTracking device. It has a configurable host interface that supports I3C[SM] , I[2] C and SPI serial communication, and an I[2] C master mode interface for connection to external sensors. The device features up to 8Kbytes FIFO and 2 programmable interrupts. 

The ICM-45605 supports the lowest gyro and accel sensor noise in this IMU class, and has the highest stability against temperature, shock (up to 20,000g) or SMT/bend induced offset as well as immunity against out-of-band vibration induced noise. Other industryleading features include InvenSense on-chip APEX Motion Processing engine for gesture recognition, activity classification, and pedometer, along with programmable digital filters, and an embedded temperature sensor. 

## **FEATURES** 

- Gyroscope Noise: 3.8 mdps/Hz & Accelerometer Noise: 70 µg/Hz 

   - Low-Noise mode 6-axis current consumption of 0.42 mA at 1600Hz 

- User selectable Gyro Full-scale range (dps): ±15.625/±31.25/±62.5/±125/±250/±500/±10 00/±2000 

- User selectable Accelerometer Full-scale range (g): ±2/±4/±8/±16 

- User configurable internal pull-up/pull-downs included on I/O interfaces to reduce system costs associated with external pull-ups/pulldowns 

- User configurable Output Data Rate (ODR) and FIFO Data Rate (FDR) 

- User-programmable digital filters for gyro, accel, and temp sensor 

- APEX Motion Functions: 

   - Pedometer, Tilt Detection, Single/Double Tap Detection, Raise to Wake, Wake on Motion 

   - Free-Fall Detection, Significant Motion Detection, Low-G Detection, High-G Detection 

- Host interface: 12.9 MHz I3C[SM] , 1 MHz I[2] C, 24 MHz SPI 

## **APPLICATIONS** 

- Game Controllers, Cameras, IoT, Drones, Non-OIS SmartPhones, Wearables, Hearables 

## **BLOCK DIAGRAM** 

## **ORDERING INFORMATION** 

**PART TEMP RANGE PACKAGE** 2.5x3mm ICM-45605† −40°C to +85°C ~~a~~ 14-Pin LGA †Denotes RoHS and Green-Compliant Package ~~a~~ 

**InvenSense, a TDK Group Company** 1745 Technology Drive, San Jose, CA 95110 U.S.A +1(408) 988–7339 invensense.tdk.com 

InvenSense Inc. reserves the right to change specifications and information herein without notice unless the product is in mass production and the datasheet has been designated by InvenSense in writing as subject to a specified Product / Process Change Notification Method regulation. 

Document Number: DS-000576 Revision: 1.0 Rev. Date: 07/25/2024 

_**ICM-45605**_ 

## **TABLE OF CONTENTS** 

||ICM-45605 Highlights ......................................................................................................................................... 1|ICM-45605 Highlights ......................................................................................................................................... 1|
|---|---|---|
||Features .............................................................................................................................................................. 1||
||Applications ........................................................................................................................................................ 1||
||Block Diagram ..................................................................................................................................................... 1|Block Diagram ..................................................................................................................................................... 1|
||Ordering Information ......................................................................................................................................... 1||
|1|Introduction ...................................................................................................................................................... 14||
||1.1|Purpose and Scope ................................................................................................................................ 14|
||1.2|Product Overview .................................................................................................................................. 14|
||1.3|Applications ........................................................................................................................................... 14|
|2|Features ............................................................................................................................................................ 15||
||2.1|Gyroscope Features ............................................................................................................................... 15|
||2.2|Accelerometer Features ........................................................................................................................ 15|
||2.3|Motion Features .................................................................................................................................... 15|
||2.4|Additional Features ................................................................................................................................ 16|
|3|Electrical Characteristics ................................................................................................................................... 17||
||3.1|Gyroscope Specifications ....................................................................................................................... 17|
||3.2|Accelerometer Specifications ................................................................................................................ 18|
||3.3|Electrical Specifications ......................................................................................................................... 19|
||3.4|I2C Timing Characterization ................................................................................................................... 21|
||3.5|SPI Timing Characterization – 4-Wire SPI Mode .................................................................................... 23|
||3.6|SPI Timing Characterization – 3-Wire SPI Mode .................................................................................... 24|
||3.7|Absolute Maximum Ratings ................................................................................................................... 25|
|4|Applications Information .................................................................................................................................. 26||
||4.1|Pin Out Diagram and Signal Description ................................................................................................ 26|
||4.2|Typical Operating Circuit (Dual Interface I2C Master Mode) ................................................................. 29|
||4.3|Typical Operating Circuit (Single Interface Mode) ................................................................................. 30|
||4.4|Bill of Materials for External Components ............................................................................................. 31|
||4.5|System Block Diagram ........................................................................................................................... 32|
||4.6|Overview ................................................................................................................................................ 32|
||4.7|Three-Axis MEMS Gyroscope with 16-bit ADCs and Signal Conditioning .............................................. 33|
||4.8|Three-Axis MEMS Accelerometer with 16-bit ADCs and Signal Conditioning ....................................... 33|
||4.9|I3CSM, I2C and SPI Host Interface ............................................................................................................ 33|
||4.10|I2C Master Interface for Connection To External Sensors ................................................................. 33|
||4.11|Self-Test ............................................................................................................................................. 33|
||4.12|Clocking ............................................................................................................................................. 34|
||4.13|Sensor Data Registers ........................................................................................................................ 34|



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|---|---|---|
||4.14|Interrupts ........................................................................................................................................... 34|
||4.15|Digital-Output Temperature Sensor .................................................................................................. 34|
||4.16|Bias and LDOs .................................................................................................................................... 34|
||4.17|Charge Pump ..................................................................................................................................... 34|
||4.18|Standard Power Modes ..................................................................................................................... 35|
|5|Signal Path ........................................................................................................................................................ 36||
|6|FIFO ................................................................................................................................................................... 37||
||6.1|Packet Structure .................................................................................................................................... 37|
||6.2|FIFO Header ........................................................................................................................................... 38|
|7|Programmable Interrupts ................................................................................................................................. 40||
|8|EDMP ................................................................................................................................................................ 41||
|9|APEX Motion Functions .................................................................................................................................... 42|APEX Motion Functions .................................................................................................................................... 42|
|10|Digital Interface ................................................................................................................................................ 43||
||10.1|I3CSM, I2C and SPI Serial Interfaces .................................................................................................... 43|
||10.2|I3CSMInterface ................................................................................................................................... 43|
||10.3|I2C Interface ....................................................................................................................................... 46|
||10.4|I2C Master Interface .......................................................................................................................... 46|
||10.5|SPI Interface ...................................................................................................................................... 47|
|11|Assembly........................................................................................................................................................... 48||
||11.1|Orientation of Axes ........................................................................................................................... 48|
||11.2|Package Dimensions .......................................................................................................................... 49|
|12|Device Package In Tape And Reel ..................................................................................................................... 51||
|13|Part Number Package Marking ......................................................................................................................... 52||
|14|Indirect Register Access .................................................................................................................................... 53||
||14.1|Host Indirect Access Register (IREG) ................................................................................................. 53|
||14.2|General Rules for Accessing IREG ...................................................................................................... 53|
||14.3|Minimum Wait Time-Gap .................................................................................................................. 53|
||14.4|IREG Write ......................................................................................................................................... 53|
||14.5|IREG READ ......................................................................................................................................... 54|
|15|Device Configuration for Data Endianness ....................................................................................................... 55||
|16|Register Map .................................................................................................................................................... 56||
||16.1|User Bank 0 Register Map ................................................................................................................. 56|
||16.2|User Bank IMEM_SRAM Register Map .............................................................................................. 58|
||16.3|User Bank IPREG_BAR Register Map ................................................................................................. 61|
||16.4|User Bank IPREG_TOP1 Register Map ............................................................................................... 61|
||16.5|User Bank IPREG_SYS1 Register Map ................................................................................................ 63|
||16.6|User Bank IPREG_SYS2 Register Map ................................................................................................ 63|



Page 3 of 191 

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_**ICM-45605**_ 

||<br>**_ICM-45605_**|<br>**_ICM-45605_**|
|---|---|---|
|17|User Bank 0 Register Map – Descriptions......................................................................................................... 64||
||17.1|ACCEL_DATA_X1_UI .......................................................................................................................... 64|
||17.2|ACCEL_DATA_X0_UI .......................................................................................................................... 64|
||17.3|ACCEL_DATA_Y1_UI .......................................................................................................................... 64|
||17.4|ACCEL_DATA_Y0_UI .......................................................................................................................... 64|
||17.5|ACCEL_DATA_Z1_UI .......................................................................................................................... 64|
||17.6|ACCEL_DATA_Z0_UI .......................................................................................................................... 65|
||17.7|GYRO_DATA_X1_UI ........................................................................................................................... 65|
||17.8|GYRO_DATA_X0_UI ........................................................................................................................... 65|
||17.9|GYRO_DATA_Y1_UI ........................................................................................................................... 65|
||17.10|GYRO_DATA_Y0_UI ........................................................................................................................... 65|
||17.11|GYRO_DATA_Z1_UI ........................................................................................................................... 66|
||17.12|GYRO_DATA_Z0_UI ........................................................................................................................... 66|
||17.13|TEMP_DATA1_UI ............................................................................................................................... 66|
||17.14|TEMP_DATA0_UI ............................................................................................................................... 66|
||17.15|TMST_FSYNCH ................................................................................................................................... 67|
||17.16|TMST_FSYNCL .................................................................................................................................... 67|
||17.17|PWR_MGMT0 .................................................................................................................................... 67|
||17.18|FIFO_COUNT_0 .................................................................................................................................. 68|
||17.19|FIFO_COUNT_1 .................................................................................................................................. 68|
||17.20|FIFO_DATA......................................................................................................................................... 68|
||17.21|INT1_CONFIG0 ................................................................................................................................... 69|
||17.22|INT1_CONFIG1 ................................................................................................................................... 71|
||17.23|INT1_CONFIG2 ................................................................................................................................... 72|
||17.24|INT1_STATUS0 ................................................................................................................................... 73|
||17.25|INT1_STATUS1 ................................................................................................................................... 74|
||17.26|ACCEL_CONFIG0 ................................................................................................................................ 75|
||17.27|GYRO_CONFIG0 ................................................................................................................................. 76|
||17.28|FIFO_CONFIG0 ................................................................................................................................... 77|
||17.29|FIFO_CONFIG1_0 ............................................................................................................................... 77|
||17.30|FIFO_CONFIG1_1 ............................................................................................................................... 78|
||17.31|FIFO_CONFIG2 ................................................................................................................................... 78|
||17.32|FIFO_CONFIG3 ................................................................................................................................... 79|
||17.33|FIFO_CONFIG4 ................................................................................................................................... 80|
||17.34|TMST_WOM_CONFIG........................................................................................................................ 81|
||17.35|FSYNC_CONFIG0 ................................................................................................................................ 82|
||17.36|DMP_EXT_SEN_ODR_CFG ................................................................................................................. 83|



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|---|---|---|
||17.37|ODR_DECIMATE_CONFIG .................................................................................................................. 84|
||17.38|EDMP_APEX_EN0 .............................................................................................................................. 85|
||17.39|EDMP_APEX_EN1 .............................................................................................................................. 85|
||17.40|APEX_BUFFER_MGMT ....................................................................................................................... 86|
||17.41|INTF_CONFIG0 ................................................................................................................................... 87|
||17.42|INTF_CONFIG1_OVRD ....................................................................................................................... 87|
||17.43|IOC_PAD_SCENARIO .......................................................................................................................... 88|
||17.44|IOC_PAD_SCENARIO_AUX_OVRD ..................................................................................................... 88|
||17.45|DRIVE_CONFIG0 ................................................................................................................................ 89|
||17.46|DRIVE_CONFIG1 ................................................................................................................................ 90|
||17.47|DRIVE_CONFIG2 ................................................................................................................................ 90|
||17.48|REG_MISC1 ........................................................................................................................................ 91|
||17.49|INT_APEX_CONFIG0 .......................................................................................................................... 92|
||17.50|INT_APEX_CONFIG1 .......................................................................................................................... 93|
||17.51|INT_APEX_STATUS0 ........................................................................................................................... 93|
||17.52|INT_APEX_STATUS1 ........................................................................................................................... 94|
||17.53|INT2_CONFIG0 ................................................................................................................................... 95|
||17.54|INT2_CONFIG1 ................................................................................................................................... 97|
||17.55|INT2_CONFIG2 ................................................................................................................................... 98|
||17.56|INT2_STATUS0 ................................................................................................................................... 99|
||17.57|INT2_STATUS1 ................................................................................................................................. 100|
||17.58|WHO_AM_I ..................................................................................................................................... 100|
||17.59|REG_HOST_MSG .............................................................................................................................. 101|
||17.60|IREG_ADDR_15_8 ............................................................................................................................ 101|
||17.61|IREG_ADDR_7_0 .............................................................................................................................. 101|
||17.62|IREG_DATA ...................................................................................................................................... 101|
||17.63|REG_MISC2 ...................................................................................................................................... 102|
|18|User Bank IMEM_SRAM Register Map – Descriptions ................................................................................... 103||
||18.1|IMEM_SRAM_REG_0 ....................................................................................................................... 103|
||18.2|IMEM_SRAM_REG_1 ....................................................................................................................... 103|
||18.3|IMEM_SRAM_REG_2 ....................................................................................................................... 103|
||18.4|IMEM_SRAM_REG_3 ....................................................................................................................... 103|
||18.5|IMEM_SRAM_REG_4 ....................................................................................................................... 104|
||18.6|IMEM_SRAM_REG_5 ....................................................................................................................... 104|
||18.7|IMEM_SRAM_REG_6 ....................................................................................................................... 104|
||18.8|IMEM_SRAM_REG_7 ....................................................................................................................... 104|
||18.9|IMEM_SRAM_REG_8 ....................................................................................................................... 105|



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||<br>**_ICM-45605_**|
|---|---|
|18.10|IMEM_SRAM_REG_9 ....................................................................................................................... 105|
|18.11|IMEM_SRAM_REG_10 ..................................................................................................................... 105|
|18.12|IMEM_SRAM_REG_11 ..................................................................................................................... 105|
|18.13|IMEM_SRAM_REG_56 ..................................................................................................................... 106|
|18.14|IMEM_SRAM_REG_57 ..................................................................................................................... 106|
|18.15|IMEM_SRAM_REG_64 ..................................................................................................................... 107|
|18.16|IMEM_SRAM_REG_68 ..................................................................................................................... 107|
|18.17|IMEM_SRAM_REG_92 ..................................................................................................................... 108|
|18.18|IMEM_SRAM_REG_96 ..................................................................................................................... 108|
|18.19|IMEM_SRAM_REG_97 ..................................................................................................................... 108|
|18.20|IMEM_SRAM_REG_98 ..................................................................................................................... 108|
|18.21|IMEM_SRAM_REG_99 ..................................................................................................................... 109|
|18.22|IMEM_SRAM_REG_100 ................................................................................................................... 109|
|18.23|IMEM_SRAM_REG_101 ................................................................................................................... 109|
|18.24|IMEM_SRAM_REG_102 ................................................................................................................... 109|
|18.25|IMEM_SRAM_REG_103 ................................................................................................................... 109|
|18.26|IMEM_SRAM_REG_104 ................................................................................................................... 110|
|18.27|IMEM_SRAM_REG_105 ................................................................................................................... 110|
|18.28|IMEM_SRAM_REG_106 ................................................................................................................... 110|
|18.29|IMEM_SRAM_REG_107 ................................................................................................................... 110|
|18.30|IMEM_SRAM_REG_136 ................................................................................................................... 111|
|18.31|IMEM_SRAM_REG_137 ................................................................................................................... 111|
|18.32|IMEM_SRAM_REG_138 ................................................................................................................... 111|
|18.33|IMEM_SRAM_REG_139 ................................................................................................................... 111|
|18.34|IMEM_SRAM_REG_141 ................................................................................................................... 112|
|18.35|IMEM_SRAM_REG_142 ................................................................................................................... 112|
|18.36|IMEM_SRAM_REG_143 ................................................................................................................... 112|
|18.37|IMEM_SRAM_REG_144 ................................................................................................................... 112|
|18.38|IMEM_SRAM_REG_146 ................................................................................................................... 113|
|18.39|IMEM_SRAM_REG_154 ................................................................................................................... 113|
|18.40|IMEM_SRAM_REG_155 ................................................................................................................... 113|
|18.41|IMEM_SRAM_REG_156 ................................................................................................................... 113|
|18.42|IMEM_SRAM_REG_157 ................................................................................................................... 114|
|18.43|IMEM_SRAM_REG_159 ................................................................................................................... 114|
|18.44|IMEM_SRAM_REG_160 ................................................................................................................... 114|
|18.45|IMEM_SRAM_REG_182 ................................................................................................................... 114|
|18.46|IMEM_SRAM_REG_185 ................................................................................................................... 115|



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|18.47|IMEM_SRAM_REG_186 ................................................................................................................... 115|IMEM_SRAM_REG_186 ................................................................................................................... 115|IMEM_SRAM_REG_186 ................................................................................................................... 115|
|---|---|---|---|
|18.48|IMEM_SRAM_REG_196 ................................................................................................................... 115|IMEM_SRAM_REG_196 ................................................................................................................... 115|IMEM_SRAM_REG_196 ................................................................................................................... 115|
|18.49|IMEM_SRAM_REG_197 ................................................................................................................... 115|IMEM_SRAM_REG_197 ................................................................................................................... 115|IMEM_SRAM_REG_197 ................................................................................................................... 115|
|18.50|IMEM_SRAM_REG_198 ................................................................................................................... 116|IMEM_SRAM_REG_198 ................................................................................................................... 116|IMEM_SRAM_REG_198 ................................................................................................................... 116|
|18.51|IMEM_SRAM_REG_199 ................................................................................................................... 116|IMEM_SRAM_REG_199 ................................................................................................................... 116|IMEM_SRAM_REG_199 ................................................................................................................... 116|
|18.52|IMEM_SRAM_REG_288 ................................................................................................................... 116|IMEM_SRAM_REG_288 ................................................................................................................... 116|IMEM_SRAM_REG_288 ................................................................................................................... 116|
|18.53|IMEM_SRAM_REG_289 ................................................................................................................... 117|IMEM_SRAM_REG_289 ................................................................................................................... 117|IMEM_SRAM_REG_289 ................................................................................................................... 117|
|18.54|IMEM_SRAM_REG_290 ................................................................................................................... 117|IMEM_SRAM_REG_290 ................................................................................................................... 117|IMEM_SRAM_REG_290 ................................................................................................................... 117|
|18.55|IMEM_SRAM_REG_291 ................................................................................................................... 117|IMEM_SRAM_REG_291 ................................................................................................................... 117|IMEM_SRAM_REG_291 ................................................................................................................... 117|
|18.56|IMEM_SRAM_REG_292 ................................................................................................................... 117|IMEM_SRAM_REG_292 ................................................................................................................... 117|IMEM_SRAM_REG_292 ................................................................................................................... 117|
|18.57|IMEM_SRAM_REG_293 ................................................................................................................... 118|IMEM_SRAM_REG_293 ................................................................................................................... 118|IMEM_SRAM_REG_293 ................................................................................................................... 118|
|18.58|IMEM_SRAM_REG_294 ................................................................................................................... 118|IMEM_SRAM_REG_294 ................................................................................................................... 118|IMEM_SRAM_REG_294 ................................................................................................................... 118|
|18.59|IMEM_SRAM_REG_295 ................................................................................................................... 118|IMEM_SRAM_REG_295 ................................................................................................................... 118|IMEM_SRAM_REG_295 ................................................................................................................... 118|
|18.60|IMEM_SRAM_REG_296 ................................................................................................................... 118|IMEM_SRAM_REG_296 ................................................................................................................... 118|IMEM_SRAM_REG_296 ................................................................................................................... 118|
|18.61|IMEM_SRAM_REG_297 ................................................................................................................... 119|IMEM_SRAM_REG_297 ................................................................................................................... 119|IMEM_SRAM_REG_297 ................................................................................................................... 119|
|18.62|IMEM_SRAM_REG_298 ................................................................................................................... 119|IMEM_SRAM_REG_298 ................................................................................................................... 119|IMEM_SRAM_REG_298 ................................................................................................................... 119|
|18.63|IMEM_SRAM_REG_299 ................................................................................................................... 119|IMEM_SRAM_REG_299 ................................................................................................................... 119|IMEM_SRAM_REG_299 ................................................................................................................... 119|
|18.64|IMEM_SRAM_REG_304 ................................................................................................................... 120|IMEM_SRAM_REG_304 ................................................................................................................... 120|IMEM_SRAM_REG_304 ................................................................................................................... 120|
|18.65|IMEM_SRAM_REG_305 ................................................................................................................... 120|IMEM_SRAM_REG_305 ................................................................................................................... 120|IMEM_SRAM_REG_305 ................................................................................................................... 120|
|18.66|IMEM_SRAM_REG_306 ................................................................................................................... 120|IMEM_SRAM_REG_306 ................................................................................................................... 120|IMEM_SRAM_REG_306 ................................................................................................................... 120|
|18.67|IMEM_SRAM_REG_307 ................................................................................................................... 120|IMEM_SRAM_REG_307 ................................................................................................................... 120|IMEM_SRAM_REG_307 ................................................................................................................... 120|
|18.68|IMEM_SRAM_REG_308 ................................................................................................................... 121|IMEM_SRAM_REG_308 ................................................................................................................... 121|IMEM_SRAM_REG_308 ................................................................................................................... 121|
|18.69|IMEM_SRAM_REG_309 ................................................................................................................... 121|IMEM_SRAM_REG_309 ................................................................................................................... 121|IMEM_SRAM_REG_309 ................................................................................................................... 121|
|18.70|IMEM_SRAM_REG_316 ................................................................................................................... 121|IMEM_SRAM_REG_316 ................................................................................................................... 121|IMEM_SRAM_REG_316 ................................................................................................................... 121|
|18.71|IMEM_SRAM_REG_317 ................................................................................................................... 121|IMEM_SRAM_REG_317 ................................................................................................................... 121|IMEM_SRAM_REG_317 ................................................................................................................... 121|
|18.72|IMEM_SRAM_REG_318 ................................................................................................................... 122|IMEM_SRAM_REG_318 ................................................................................................................... 122|IMEM_SRAM_REG_318 ................................................................................................................... 122|
|18.73|IMEM_SRAM_REG_319 ................................................................................................................... 122|IMEM_SRAM_REG_319 ................................................................................................................... 122|IMEM_SRAM_REG_319 ................................................................................................................... 122|
|18.74|IMEM_SRAM_REG_320 ................................................................................................................... 122|IMEM_SRAM_REG_320 ................................................................................................................... 122|IMEM_SRAM_REG_320 ................................................................................................................... 122|
|18.75|IMEM_SRAM_REG_321 ................................................................................................................... 122|IMEM_SRAM_REG_321 ................................................................................................................... 122|IMEM_SRAM_REG_321 ................................................................................................................... 122|
|18.76|IMEM_SRAM_REG_392 ................................................................................................................... 123|IMEM_SRAM_REG_392 ................................................................................................................... 123|IMEM_SRAM_REG_392 ................................................................................................................... 123|
|18.77|IMEM_SRAM_REG_393 ................................................................................................................... 123|IMEM_SRAM_REG_393 ................................................................................................................... 123|IMEM_SRAM_REG_393 ................................................................................................................... 123|
|18.78|IMEM_SRAM_REG_400 ................................................................................................................... 123|IMEM_SRAM_REG_400 ................................................................................................................... 123|IMEM_SRAM_REG_400 ................................................................................................................... 123|
|18.79|IMEM_SRAM_REG_401 ................................................................................................................... 124|IMEM_SRAM_REG_401 ................................................................................................................... 124|IMEM_SRAM_REG_401 ................................................................................................................... 124|
|18.80|IMEM_SRAM_REG_402 ................................................................................................................... 124|IMEM_SRAM_REG_402 ................................................................................................................... 124|IMEM_SRAM_REG_402 ................................................................................................................... 124|
|18.81|IMEM_SRAM_REG_403 ................................................................................................................... 124|IMEM_SRAM_REG_403 ................................................................................................................... 124|IMEM_SRAM_REG_403 ................................................................................................................... 124|
|18.82|IMEM_SRAM_REG_404 ................................................................................................................... 125|IMEM_SRAM_REG_404 ................................................................................................................... 125|IMEM_SRAM_REG_404 ................................................................................................................... 125|
|18.83|IMEM_SRAM_REG_405 ................................................................................................................... 125|IMEM_SRAM_REG_405 ................................................................................................................... 125|IMEM_SRAM_REG_405 ................................................................................................................... 125|



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||<br>**_ICM-45605_**|
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|18.84|IMEM_SRAM_REG_406 ................................................................................................................... 125|
|18.85|IMEM_SRAM_REG_540 ................................................................................................................... 126|
|18.86|IMEM_SRAM_REG_541 ................................................................................................................... 126|
|18.87|IMEM_SRAM_REG_542 ................................................................................................................... 126|
|18.88|IMEM_SRAM_REG_543 ................................................................................................................... 127|
|18.89|IMEM_SRAM_REG_544 ................................................................................................................... 127|
|18.90|IMEM_SRAM_REG_545 ................................................................................................................... 127|
|18.91|IMEM_SRAM_REG_546 ................................................................................................................... 128|
|18.92|IMEM_SRAM_REG_547 ................................................................................................................... 128|
|18.93|IMEM_SRAM_REG_548 ................................................................................................................... 128|
|18.94|IMEM_SRAM_REG_549 ................................................................................................................... 129|
|18.95|IMEM_SRAM_REG_550 ................................................................................................................... 129|
|18.96|IMEM_SRAM_REG_551 ................................................................................................................... 129|
|18.97|IMEM_SRAM_REG_556 ................................................................................................................... 130|
|18.98|IMEM_SRAM_REG_557 ................................................................................................................... 130|
|18.99|IMEM_SRAM_REG_558 ................................................................................................................... 130|
|18.100|IMEM_SRAM_REG_559 .............................................................................................................. 131|
|18.101|IMEM_SRAM_REG_560 .............................................................................................................. 131|
|18.102|IMEM_SRAM_REG_561 .............................................................................................................. 131|
|18.103|IMEM_SRAM_REG_562 .............................................................................................................. 132|
|18.104|IMEM_SRAM_REG_563 .............................................................................................................. 132|
|18.105|IMEM_SRAM_REG_564 .............................................................................................................. 132|
|18.106|IMEM_SRAM_REG_565 .............................................................................................................. 133|
|18.107|IMEM_SRAM_REG_566 .............................................................................................................. 133|
|18.108|IMEM_SRAM_REG_567 .............................................................................................................. 133|
|18.109|IMEM_SRAM_REG_568 .............................................................................................................. 134|
|18.110|IMEM_SRAM_REG_569 .............................................................................................................. 134|
|18.111|IMEM_SRAM_REG_570 .............................................................................................................. 134|
|18.112|IMEM_SRAM_REG_571 .............................................................................................................. 135|
|18.113|IMEM_SRAM_REG_572 .............................................................................................................. 135|
|18.114|IMEM_SRAM_REG_573 .............................................................................................................. 135|
|18.115|IMEM_SRAM_REG_574 .............................................................................................................. 136|
|18.116|IMEM_SRAM_REG_575 .............................................................................................................. 136|
|18.117|IMEM_SRAM_REG_576 .............................................................................................................. 136|
|18.118|IMEM_SRAM_REG_577 .............................................................................................................. 137|
|18.119|IMEM_SRAM_REG_578 .............................................................................................................. 137|
|18.120|IMEM_SRAM_REG_579 .............................................................................................................. 137|



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|||<br>**_ICM-45605_**|
|---|---|---|
||18.121|IMEM_SRAM_REG_580 .............................................................................................................. 138|
||18.122|IMEM_SRAM_REG_581 .............................................................................................................. 138|
||18.123|IMEM_SRAM_REG_582 .............................................................................................................. 138|
||18.124|IMEM_SRAM_REG_583 .............................................................................................................. 139|
||18.125|IMEM_SRAM_REG_584 .............................................................................................................. 139|
||18.126|IMEM_SRAM_REG_585 .............................................................................................................. 139|
||18.127|IMEM_SRAM_REG_586 .............................................................................................................. 140|
||18.128|IMEM_SRAM_REG_587 .............................................................................................................. 140|
||18.129|IMEM_SRAM_REG_988 .............................................................................................................. 140|
||18.130|IMEM_SRAM_REG_989 .............................................................................................................. 141|
||18.131|IMEM_SRAM_REG_990 .............................................................................................................. 141|
||18.132|IMEM_SRAM_REG_991 .............................................................................................................. 141|
||18.133|IMEM_SRAM_REG_994 .............................................................................................................. 142|
||18.134|IMEM_SRAM_REG_995 .............................................................................................................. 142|
||18.135|IMEM_SRAM_REG_1000 ............................................................................................................ 142|
||18.136|IMEM_SRAM_REG_1001 ............................................................................................................ 143|
||18.137|IMEM_SRAM_REG_1002 ............................................................................................................ 143|
||18.138|IMEM_SRAM_REG_1003 ............................................................................................................ 143|
||18.139|IMEM_SRAM_REG_1004 ............................................................................................................ 144|
||18.140|IMEM_SRAM_REG_1008 ............................................................................................................ 144|
||18.141|IMEM_SRAM_REG_1009 ............................................................................................................ 144|
||18.142|IMEM_SRAM_REG_1010 ............................................................................................................ 145|
||18.143|IMEM_SRAM_REG_1011 ............................................................................................................ 145|
||18.144|IMEM_SRAM_REG_1016 ............................................................................................................ 145|
||18.145|IMEM_SRAM_REG_1017 ............................................................................................................ 146|
||18.146|IMEM_SRAM_REG_1018 ............................................................................................................ 146|
||18.147|IMEM_SRAM_REG_1019 ............................................................................................................ 146|
||18.148|IMEM_SRAM_REG_1042 ............................................................................................................ 147|
||18.149|IMEM_SRAM_REG_1168 to IMEM_SRAM_REG_1203 ............................................................... 147|
|19|User Bank IPREG_BAR Register Map – Descriptions ...................................................................................... 148||
||19.1|IPREG_BAR_REG_57 ........................................................................................................................ 148|
||19.2|IPREG_BAR_REG_58 ........................................................................................................................ 149|
||19.3|IPREG_BAR_REG_59 ........................................................................................................................ 150|
||19.4|IPREG_BAR_REG_60 ........................................................................................................................ 151|
||19.5|IPREG_BAR_REG_61 ........................................................................................................................ 152|
||19.6|IPREG_BAR_REG_62 ........................................................................................................................ 153|
|20|User Bank IPREG_TOP1 Register Map – Descriptions .................................................................................... 154||



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_**ICM-45605**_ 

||<br>**_ICM-45605_**|
|---|---|
|20.1|I2CM_COMMAND_0 ....................................................................................................................... 154|
|20.2|I2CM_COMMAND_1 ....................................................................................................................... 155|
|20.3|I2CM_COMMAND_2 ....................................................................................................................... 156|
|20.4|I2CM_COMMAND_3 ....................................................................................................................... 157|
|20.5|I2CM_DEV_PROFILE0 ...................................................................................................................... 158|
|20.6|I2CM_DEV_PROFILE1 ...................................................................................................................... 158|
|20.7|I2CM_DEV_PROFILE2 ...................................................................................................................... 158|
|20.8|I2CM_DEV_PROFILE3 ...................................................................................................................... 158|
|20.9|I2CM_CONTROL ............................................................................................................................... 159|
|20.10|I2CM_STATUS .................................................................................................................................. 159|
|20.11|I2CM_EXT_DEV_STATUS ................................................................................................................. 160|
|20.12|I2CM_RD_DATA0 ............................................................................................................................. 160|
|20.13|I2CM_RD_DATA1 ............................................................................................................................. 161|
|20.14|I2CM_RD_DATA2 ............................................................................................................................. 161|
|20.15|I2CM_RD_DATA3 ............................................................................................................................. 161|
|20.16|I2CM_RD_DATA4 ............................................................................................................................. 162|
|20.17|I2CM_RD_DATA5 ............................................................................................................................. 162|
|20.18|I2CM_RD_DATA6 ............................................................................................................................. 162|
|20.19|I2CM_RD_DATA7 ............................................................................................................................. 163|
|20.20|I2CM_RD_DATA8 ............................................................................................................................. 163|
|20.21|I2CM_RD_DATA9 ............................................................................................................................. 163|
|20.22|I2CM_RD_DATA10 ........................................................................................................................... 164|
|20.23|I2CM_RD_DATA11 ........................................................................................................................... 164|
|20.24|I2CM_RD_DATA12 ........................................................................................................................... 164|
|20.25|I2CM_RD_DATA13 ........................................................................................................................... 165|
|20.26|I2CM_RD_DATA14 ........................................................................................................................... 165|
|20.27|I2CM_RD_DATA15 ........................................................................................................................... 165|
|20.28|I2CM_RD_DATA16 ........................................................................................................................... 166|
|20.29|I2CM_RD_DATA17 ........................................................................................................................... 166|
|20.30|I2CM_RD_DATA18 ........................................................................................................................... 166|
|20.31|I2CM_RD_DATA19 ........................................................................................................................... 167|
|20.32|I2CM_RD_STATUS20 ....................................................................................................................... 167|
|20.33|I2CM_WR_DATA0 ............................................................................................................................ 167|
|20.34|I2CM_WR_DATA1 ............................................................................................................................ 167|
|20.35|I2CM_WR_DATA2 ............................................................................................................................ 168|
|20.36|I2CM_WR_DATA3 ............................................................................................................................ 168|
|20.37|I2CM_WR_DATA4 ............................................................................................................................ 168|



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|||<br>**_ICM-45605_**|
|---|---|---|
||20.38|I2CM_WR_DATA5 ............................................................................................................................ 168|
||20.39|SIFS_IXC_ERROR_STATUS ................................................................................................................ 169|
||20.40|EDMP_PRGRM_IRQ0_0 ................................................................................................................... 169|
||20.41|EDMP_PRGRM_IRQ0_1 ................................................................................................................... 169|
||20.42|EDMP_PRGRM_IRQ1_0 ................................................................................................................... 170|
||20.43|EDMP_PRGRM_IRQ1_1 ................................................................................................................... 170|
||20.44|EDMP_PRGRM_IRQ2_0 ................................................................................................................... 170|
||20.45|EDMP_PRGRM_IRQ2_1 ................................................................................................................... 170|
||20.46|EDMP_SP_START_ADDR .................................................................................................................. 171|
||20.47|SMC_CONTROL_0 ............................................................................................................................ 171|
||20.48|SMC_CONTROL_1 ............................................................................................................................ 172|
||20.49|STC_CONFIG .................................................................................................................................... 172|
||20.50|SREG_CTRL ...................................................................................................................................... 173|
||20.51|SIFS_I3C_STC_CFG ........................................................................................................................... 173|
||20.52|INT_PULSE_MIN_ON_INTF0 ............................................................................................................ 174|
||20.53|INT_PULSE_MIN_ON_INTF1 ............................................................................................................ 174|
||20.54|INT_PULSE_MIN_OFF_INTF0 ........................................................................................................... 174|
||20.55|INT_PULSE_MIN_OFF_INTF1 ........................................................................................................... 175|
||20.56|ISR_0_7 ............................................................................................................................................ 175|
||20.57|ISR_8_15 .......................................................................................................................................... 176|
||20.58|ISR_16_23 ........................................................................................................................................ 176|
||20.59|STATUS_MASK_PIN_0_7 ................................................................................................................. 177|
||20.60|STATUS_MASK_PIN_8_15 ............................................................................................................... 178|
||20.61|STATUS_MASK_PIN_16_23 ............................................................................................................. 179|
||20.62|INT_I2CM_SOURCE .......................................................................................................................... 179|
||20.63|ACCEL_WOM_X_THR....................................................................................................................... 179|
||20.64|ACCEL_WOM_Y_THR ....................................................................................................................... 180|
||20.65|ACCEL_WOM_Z_THR ....................................................................................................................... 180|
||20.66|SELFTEST .......................................................................................................................................... 181|
||20.67|IPREG_MISC ..................................................................................................................................... 181|
||20.68|SW_PLL1_TRIM ................................................................................................................................ 182|
||20.69|FIFO_SRAM_SLEEP .......................................................................................................................... 182|
|21|User Bank IPREG_SYS1 Register Map – Descriptions ..................................................................................... 183||
||21.1|IPREG_SYS1_REG_42 ....................................................................................................................... 183|
||21.2|IPREG_SYS1_REG_43 ....................................................................................................................... 183|
||21.3|IPREG_SYS1_REG_56 ....................................................................................................................... 183|
||21.4|IPREG_SYS1_REG_57 ....................................................................................................................... 183|



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_**ICM-45605**_ 

|||<br>**_ICM-45605_**|
|---|---|---|
||21.5|IPREG_SYS1_REG_70 ....................................................................................................................... 184|
||21.6|IPREG_SYS1_REG_71 ....................................................................................................................... 184|
||21.7|IPREG_SYS1_REG_166 ..................................................................................................................... 184|
||21.8|IPREG_SYS1_REG_170 ..................................................................................................................... 185|
||21.9|IPREG_SYS1_REG_172 ..................................................................................................................... 185|
|22|User Bank IPREG_SYS2 Register Map – Descriptions ..................................................................................... 186||
||22.1|IPREG_SYS2_REG_24 ....................................................................................................................... 186|
||22.2|IPREG_SYS2_REG_25 ....................................................................................................................... 186|
||22.3|IPREG_SYS2_REG_32 ....................................................................................................................... 186|
||22.4|IPREG_SYS2_REG_33 ....................................................................................................................... 186|
||22.5|IPREG_SYS2_REG_40 ....................................................................................................................... 187|
||22.6|IPREG_SYS2_REG_41 ....................................................................................................................... 187|
||22.7|IPREG_SYS2_REG_123 ..................................................................................................................... 187|
||22.8|IPREG_SYS2_REG_129 ..................................................................................................................... 188|
||22.9|IPREG_SYS2_REG_131 ..................................................................................................................... 188|
|23|Reference ....................................................................................................................................................... 189||
|24|Revision History .............................................................................................................................................. 190||



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_**ICM-45605**_ 

## **TABLE OF FIGURES** 

|Figure 1. I|Figure 1. I2C Bus Timing Diagram ................................................................................................................................. 22|
|---|---|
|Figure 2. 4-Wire SPI Bus Timing Diagram .................................................................................................................... 23|Figure 2. 4-Wire SPI Bus Timing Diagram .................................................................................................................... 23|
|Figure 3. 3-Wire SPI Bus Timing Diagram .................................................................................................................... 24|Figure 3. 3-Wire SPI Bus Timing Diagram .................................................................................................................... 24|
|Figure 4. Pin Out Diagram for ICM-45605 2.5x3.0x0.81 mm LGA ............................................................................... 29|Figure 4. Pin Out Diagram for ICM-45605 2.5x3.0x0.81 mm LGA ............................................................................... 29|
|Figure 5. ICM-45605 Application Schematic Dual Interface I|Figure 5. ICM-45605 Application Schematic Dual Interface I2C Master Mode (I3CSM/ I2C Interface to Host) ............ 29|
|Figure 6. ICM-45605 Application Schematic Dual Interface I|Figure 6. ICM-45605 Application Schematic Dual Interface I2C Master Mode (SPI Interface to Host) ........................ 30|
|Figure 7. ICM-45605 Application Schematic Single Interface Mode (I3C|Figure 7. ICM-45605 Application Schematic Single Interface Mode (I3CSM/ I2C Interface to Host) ............................ 30|
|Figure 8. ICM-45605 Application Schematic Single Interface Mode (SPI Interface to Host) ....................................... 31|Figure 8. ICM-45605 Application Schematic Single Interface Mode (SPI Interface to Host) ....................................... 31|
|Figure 9. ICM-45605 System Block Diagram ................................................................................................................ 32|Figure 9. ICM-45605 System Block Diagram ................................................................................................................ 32|
|Figure 10. ICM-45605 Signal Path ................................................................................................................................ 36|Figure 10. ICM-45605 Signal Path ................................................................................................................................ 36|
|Figure 11. Typical SPI Master/Slave Configuration ...................................................................................................... 47|Figure 11. Typical SPI Master/Slave Configuration ...................................................................................................... 47|
|Figure 12. Orientation of Axes of Sensitivity and Polarity of Rotation ........................................................................ 48|Figure 12. Orientation of Axes of Sensitivity and Polarity of Rotation ........................................................................ 48|
|Figure 13. ICM-45605 Device Package in Tape and Reel ............................................................................................. 51|Figure 13. ICM-45605 Device Package in Tape and Reel ............................................................................................. 51|
|Figure 14. Tape Dimensions with ICM-45605 Device Package .................................................................................... 51|Figure 14. Tape Dimensions with ICM-45605 Device Package .................................................................................... 51|



## **TABLE OF TABLES** 

|Table 1. Gyroscope Specifications ............................................................................................................................... 17|Table 1. Gyroscope Specifications ............................................................................................................................... 17|
|---|---|
|Table 2. Accelerometer Specifications ........................................................................................................................ 18|Table 2. Accelerometer Specifications ........................................................................................................................ 18|
|Table 3. D.C. Electrical Characteristics ......................................................................................................................... 19|Table 3. D.C. Electrical Characteristics ......................................................................................................................... 19|
|Table 4. A.C. Electrical Characteristics ......................................................................................................................... 20|Table 4. A.C. Electrical Characteristics ......................................................................................................................... 20|
|Table 5. I|Table 5. I2C Host Interface Timing Characteristics ....................................................................................................... 21|
|Table 6. I|Table 6. I2C Master Interface Timing Characteristics ................................................................................................... 21|
|Table 7. 4-Wire SPI Timing Characteristics .................................................................................................................. 23|Table 7. 4-Wire SPI Timing Characteristics .................................................................................................................. 23|
|Table 8. 3-Wire SPI Timing Characteristics .................................................................................................................. 24|Table 8. 3-Wire SPI Timing Characteristics .................................................................................................................. 24|
|Table 9. Absolute Maximum Ratings ........................................................................................................................... 25|Table 9. Absolute Maximum Ratings ........................................................................................................................... 25|
|Table 10. Signal Descriptions ....................................................................................................................................... 28|Table 10. Signal Descriptions ....................................................................................................................................... 28|
|Table 11. Bill of Materials ............................................................................................................................................ 31|Table 11. Bill of Materials ............................................................................................................................................ 31|
|Table 12. Standard Power Modes for ICM-45605 ....................................................................................................... 35|Table 12. Standard Power Modes for ICM-45605 ....................................................................................................... 35|
|Table 13. I3C|Table 13. I3CSMCCC Commands................................................................................................................................... 46|



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_**ICM-45605**_ 

## _**1 INTRODUCTION**_ 

## **1.1 PURPOSE AND SCOPE** 

This document is a product specification, providing a description, specifications, and design related information on the ICM-45605 Dual-Interface MotionTracking device. The device is housed in a small 2.5x3x0.81 mm 14-pin LGA package. 

## **1.2 PRODUCT OVERVIEW** 

The ICM-45605 is a 6-axis MotionTracking device with a configurable host interface that supports I3C[SM] , I[2] C and SPI serial communication, and an I[2] C master mode interface for connection to external sensors. It combines a 3-axis gyroscope, and a 3-axis accelerometer in a small 2.5x3x0.81 mm (14-pin LGA) package. 

ICM-45605 also features up to 8Kbytes FIFO that can lower the traffic on the serial bus interface, and reduce power consumption by allowing the system processor to burst read sensor data and then go into a low-power mode. ICM-45605, with its 6-axis integration, enables manufacturers to eliminate the costly and complex selection, qualification, and system level integration of discrete devices, guaranteeing optimal motion performance for consumers. 

The gyroscope supports independently programmable full-scale range settings from ±15.625dps to ±2000dps for the UI path, and the accelerometer supports independently programmable full-scale range settings from ±2g to ±16g for the UI path. 

Other industry-leading features include on-chip 16-bit ADCs, programmable digital filters, an embedded temperature sensor, and programmable interrupts. The device features I3C[SM] , I[2] C and SPI serial interfaces, a VDD operating range of 1.71V to 3.6V, and a separate VDDIO operating range of 1.08V to 3.6V. 

The host interface can be configured to support I3C[SM] slave, I[2] C slave, or SPI slave modes.  The I3C[SM] interface supports speeds up to 12.9MHz (data rates up to 12.9Mbps in SDR mode, 25.8Mbps in DDR mode), the I[2] C interface supports speeds up to 1MHz, and the SPI interface supports speeds up to 24MHz. 

User configurable internal pull-up/pull-downs are included on I/O interfaces to reduce system costs associated with external pull-ups/pull-downs. 

By leveraging its patented and volume-proven CMOS-MEMS fabrication platform, which integrates MEMS wafers with companion CMOS electronics through wafer-level bonding, TDK InvenSense has driven the package size down to a footprint and thickness of 2.5x3x0.81 mm (14-pin LGA), to provide a very small yet high performance low cost package. The device provides high robustness by supporting 20,000 _g_ shock reliability. 

## **1.3 APPLICATIONS** 

- Game Controllers 

- Cameras 

- IoT 

- Drones 

- Non-OIS SmartPhones 

- Wearables 

- Hearables 

Page 14 of 191 

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_**ICM-45605**_ 

## _**2 FEATURES**_ 

## **2.1 GYROSCOPE FEATURES** 

The triple-axis MEMS gyroscope in the ICM-45605 includes a wide range of features: 

- Digital-output X-, Y-, and Z-axis angular rate sensors (gyroscopes) with independently programmable fullscale range of ±15.625, ±31.25, ±62.5, ±125, ±250, ±500, ±1000, and ±2000 degrees/sec for UI and auxiliary paths 

- Low Noise (LN) and Low Power (LP) power modes support 

- Digitally-programmable low-pass filters 

- Self-test 

## **2.2 ACCELEROMETER FEATURES** 

The triple-axis MEMS accelerometer in ICM-45605 includes a wide range of features: 

- Digital-output X-, Y-, and Z-axis accelerometer with independently programmable full-scale range of ±2 _g_ , ±4 _g_ , ±8 _g_ and ±16 _g_ for UI and auxiliary paths 

- Low Noise (LN) and Low Power (LP) power modes support 

- User-programmable interrupts 

- Wake-on-motion interrupt for low power operation of applications processor 

- Self-test 

## **2.3 MOTION FEATURES** 

ICM-45605 includes the following motion features, also known as APEX ( **A** dvanced **P** edometer and **E** vent Detection – ne **X** t gen) 

- Pedometer: Tracks Step Count, also issues Step Detect interrupt. 

- Tilt Detection: Issues an interrupt when the Tilt angle exceeds 35 for more than a programmable time. 

- Raise to Wake/Sleep: Gesture detection for wake and sleep events.  Interrupt is issued when either of these two events are detected. 

- Single Tap / Double Tap Detection: Issues an interrupt when a tap is detected, along with the tap type. 

- Wake on Motion: Detects motion when accelerometer data exceeds a programmable threshold. 

- Freefall Detection: Triggers an interrupt when device freefall is detected and outputs freefall duration. 

- Significant Motion Detection: Detects significant motion based on accelerometer data. 

- Low-G Detection: Triggers an interrupt when absolute value of accelerometer combined axis falls below a programmable threshold and stays below the threshold for a programmable time. 

- High-G Detection: Triggers an interrupt when absolute value of accelerometer goes above a programmable threshold and stays above the threshold for a programmable time. 

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_**ICM-45605**_ 

## **2.4 ADDITIONAL FEATURES** 

ICM-45605 includes the following additional features: 

- Up to 8Kbytes FIFO buffer enables the applications processor to read the data in bursts, default FIFO size is 2Kbytes, user can extend it up to 8kByte by disabling APEX functions 

- EDMP Enhanced Digital Motion Processor for implementing motion algorithms 

- 20-bits data format support in FIFO for high-data resolution 

- User-programmable digital filters for gyroscope, accelerometer, and temperature sensor 

- Main interface: 12.5MHz I3C[SM] (data rates up to 12.5Mbps in SDR mode, 25Mbps in DDR mode) / 1 MHz I[2] C / 24 MHz SPI slave host interface 

- Auxiliary interface: 400 kHz I[2] C master 

- User configurable internal pull-up/pull-downs included on I/O interfaces to reduce system costs associated with external pull-ups/pull-downs 

- User configurable Output Data Rate (ODR) and FIFO Data Rate (FDR) 

- Digital-output temperature sensor 

- Smallest and thinnest LGA package for portable devices: 2.5x3x0.81 mm (14-pin LGA) 

- 20,000 _g_ shock tolerant 

- MEMS structure hermetically sealed and bonded at wafer level 

- RoHS and Green compliant 

Page 16 of 191 

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_**ICM-45605**_ 

## _**3 ELECTRICAL CHARACTERISTICS**_ 

## **3.1 GYROSCOPE SPECIFICATIONS** 

Typical Operating Circuit of section 4.2, VDD = 1.8 V, VDDIO = 1.8V, TA=25°C, unless otherwise noted. 

|**PARAMETER**<br>~~Ce~~|**CONDITIONS**<br>||**MIN**|**TYP**|**MAX**|**UNITS**|**NOTES**|
|---|---|---|---|---|---|---|
|**GYROSCOPE SENSITIVITY**<br>|<br>~~Ce~~|||||||
|Full-Scale Range<br>~~Ce~~|GYRO_UI_FS_SEL =1<br>|<br>~~Rs~~|~~Rs~~<br>~~QO~~|±2000<br>~~Rs~~<br>~~QO~~|~~Rs~~|º/s<br>~~Rs~~|3<br>~~Rs~~|
||GYRO_UI_FS_SEL =2<br>~~Rs~~|~~Rs~~<br>~~QO~~<br>~~QO~~|±1000<br>~~Rs~~<br>~~QO~~<br>~~QO~~|~~Rs~~|º/s<br>~~Rs~~|3<br>~~Rs~~|
||GYRO_UI_FS_SEL =3<br>~~Rs~~|~~QO~~<br>~~Rs~~<br>~~QO~~<br>~~QO~~|±500<br>~~QO~~<br>~~Rs~~<br>~~QO~~<br>~~QO~~|~~Rs~~|º/s<br>~~Rs~~|3<br>~~Rs~~|
||GYRO_UI_FS_SEL =4<br>~~Rs~~|~~QO~~<br>~~Rs~~<br>~~QO~~<br>~~QO~~|±250<br>~~QO~~<br>~~Rs~~<br>~~QO~~<br>~~QO~~|~~Rs~~|º/s<br>~~Rs~~|3<br>~~Rs~~|
||GYRO_UI_FS_SEL =5<br>~~Rs~~|~~QO~~<br>~~Rs~~<br>~~QO~~<br>~~QO~~|±125<br>~~QO~~<br>~~Rs~~<br>~~QO~~<br>~~QO~~|~~Rs~~|º/s<br>~~Rs~~|3<br>~~Rs~~|
||GYRO_UI_FS_SEL =6<br>~~Rs~~|~~QO~~<br>~~Rs~~<br>~~QO~~<br>~~QO~~|±62.5<br>~~QO~~<br>~~Rs~~<br>~~QO~~<br>~~QO~~|~~Rs~~|º/s<br>~~Rs~~|3<br>~~Rs~~|
||GYRO_UI_FS_SEL =7<br>~~Rs~~|~~QO~~<br>~~Rs~~<br>~~QO~~|±31.25<br>~~QO~~<br>~~Rs~~<br>~~QO~~|~~Rs~~|º/s<br>~~Rs~~|3<br>~~Rs~~|
||GYRO_UI_FS_SEL =8<br>~~rs~~|~~QO~~<br>~~rs~~|±15.625<br>~~QO~~<br>~~rs~~|~~rs~~|º/s<br>~~rs~~|3<br>~~rs~~|
|Gyroscope ADC Word Length<br>~~Rf~~|Output in two’s complement format<br>~~Rf~~|~~Rf~~<br>~~rs~~|16<br>~~Rf~~|~~Rf~~|bits<br>~~Rf~~|3, 6<br>~~Rf~~|
|Sensitivity Scale Factor<br>~~Rf~~|GYRO_UI_FS_SEL =1<br>~~Rf~~<br>~~Rs~~|~~Rf~~<br>~~Rs~~<br>~~rs~~<br>~~rs~~|16.4<br>~~Rf~~<br>~~Rs~~|~~Rf~~<br>~~Rs~~|LSB/(º/s)<br>~~Rf~~<br>~~Rs~~|3<br>~~Rf~~<br>~~Rs~~|
||GYRO_UI_FS_SEL =2<br>~~Rs~~<br>~~Rs~~|~~Rs~~<br>~~rs~~<br>~~Rs~~<br>~~rs~~<br>~~rs~~|32.8<br>~~Rs~~<br>~~Rs~~|~~Rs~~<br>~~Rs~~|LSB/(º/s)<br>~~Rs~~<br>~~Rs~~|3<br>~~Rs~~<br>~~Rs~~|
||GYRO_UI_FS_SEL =3<br>~~Rs~~<br>~~Rs~~|~~Rs~~<br>~~rs~~<br>~~Rs~~<br>~~rs~~<br>~~rs~~|65.5<br>~~Rs~~<br>~~Rs~~|~~Rs~~<br>~~Rs~~|LSB/(º/s)<br>~~Rs~~<br>~~Rs~~|3<br>~~Rs~~<br>~~Rs~~|
||GYRO_UI_FS_SEL =4<br>~~Rs~~<br>~~Rs~~|~~Rs~~<br>~~rs~~<br>~~Rs~~<br>~~rs~~<br>~~rs~~|131<br>~~Rs~~<br>~~Rs~~|~~Rs~~<br>~~Rs~~|LSB/(º/s)<br>~~Rs~~<br>~~Rs~~|3<br>~~Rs~~<br>~~Rs~~|
||GYRO_UI_FS_SEL =5<br>~~Rs~~<br>~~Rs~~|~~Rs~~<br>~~rs~~<br>~~Rs~~<br>~~rs~~<br>~~rs~~|262<br>~~Rs~~<br>~~Rs~~|~~Rs~~<br>~~Rs~~|LSB/(º/s)<br>~~Rs~~<br>~~Rs~~|3<br>~~Rs~~<br>~~Rs~~|
||GYRO_UI_FS_SEL =6<br>~~Rs~~<br>~~Rs~~|~~Rs~~<br>~~rs~~<br>~~Rs~~<br>~~rs~~<br>~~rs~~|524.3<br>~~Rs~~<br>~~Rs~~|~~Rs~~<br>~~Rs~~|LSB/(º/s)<br>~~Rs~~<br>~~Rs~~|3<br>~~Rs~~<br>~~Rs~~|
||GYRO_UI_FS_SEL =7<br>~~Rs~~<br>~~Rs~~|~~Rs~~<br>~~rs~~<br>~~Rs~~<br>~~rs~~<br>~~rs~~|1048.6<br>~~Rs~~<br>~~Rs~~<br>~~rs~~|~~Rs~~<br>~~Rs~~|LSB/(º/s)<br>~~Rs~~<br>~~Rs~~|3<br>~~Rs~~<br>~~Rs~~|
||GYRO_UI_FS_SEL =8<br>~~Rs~~<br>~~es~~|~~Rs~~<br>~~rs~~<br>~~es~~<br>~~rs~~|2097.2<br>~~Rs~~<br>~~es~~<br>~~rs~~|~~Rs~~<br>~~es~~|LSB/(º/s)<br>~~Rs~~<br>~~es~~|3<br>~~Rs~~<br>~~es~~|
|Sensitivity Scale Factor Initial Tolerance<br>~~Rs~~|Component-level, 25°C<br>~~es~~<br>~~Rs~~|~~es~~<br>~~rs~~<br>~~Rs~~|±0.5<br>~~es~~<br>~~rs~~<br>~~Rs~~|~~es~~<br>~~Rs~~|%<br>~~es~~<br>~~Rs~~|2<br>~~es~~<br>~~Rs~~|
|Sensitivity Change vs. Temperature<br>~~Rs~~<br>~~Rs~~|-40°C to +85°C, board-level<br>~~Rs~~<br>~~Rs~~|~~Rs~~<br>~~Rs~~|±0.01<br>~~Rs~~<br>~~Rs~~|~~Rs~~<br>~~Rs~~|%/ºC<br>~~Rs~~<br>~~Rs~~|1, 8<br>~~Rs~~<br>~~Rs~~|
|Nonlinearity<br>~~Rs~~<br>~~Rs~~|Best fit straight line; board-level, 25°C<br>~~Rs~~<br>~~Rs~~|~~Rs~~<br>~~Rs~~|±0.1<br>~~Rs~~<br>~~Rs~~|~~Rs~~<br>~~Rs~~|%<br>~~Rs~~<br>~~Rs~~|1, 8<br>~~Rs~~<br>~~Rs~~|
|Cross-Axis Sensitivity<br>~~Rs~~<br>~~es~~|Board-level<br>~~Rs~~<br>~~es~~|~~Rs~~<br>~~es~~|±1<br>~~Rs~~<br>~~es~~|~~Rs~~<br>~~es~~|%<br>~~Rs~~<br>~~es~~|1, 8<br>~~Rs~~<br>~~es~~|
|**ZERO-RATE OUTPUT (ZRO)**<br>~~es~~<br>~~Cn~~|||||||
|Initial ZRO Tolerance<br>~~Cn~~<br>~~Rs~~|Component-level, 25°C<br>~~Cn~~<br>~~Rs~~|~~Cn~~<br>~~Rs~~|±0.5<br>~~Cn~~<br>~~Rs~~|~~Cn~~<br>~~Rs~~|º/s<br>~~Cn~~<br>~~Rs~~|2<br>~~Cn~~<br>~~Rs~~|
|ZRO Change vs. Temperature<br>~~Rs~~<br>~~rs~~|-40°C to +85°C, board-level<br>~~Rs~~<br>~~rs~~|~~Rs~~<br>~~rs~~|±0.015<br>~~Rs~~<br>~~rs~~|~~Rs~~<br>~~rs~~|º/s/ºC<br>~~Rs~~<br>~~rs~~|1, 8<br>~~Rs~~<br>~~rs~~|
|**OTHER PARAMETERS**<br>~~rs~~<br>~~Cn~~|||||||
|Rate Noise Spectral Density<br>~~Cn~~<br>~~Rs~~|@ 10 Hz, 25°C<br>~~Cn~~<br>~~Rs~~|~~Cn~~<br>~~Rs~~|0.0038<br>~~Cn~~<br>~~Rs~~|~~Cn~~<br>~~Rs~~|º/s /√Hz<br>~~Cn~~<br>~~Rs~~|2, 4<br>~~Cn~~<br>~~Rs~~|
|Total RMS Noise<br>~~Rs~~<br>~~rs~~|Bandwidth = 100 Hz<br>~~Rs~~<br>~~rs~~|~~Rs~~<br>~~rs~~|0.038<br>~~Rs~~<br>~~rs~~|~~Rs~~<br>~~rs~~|º/s-rms<br>~~Rs~~<br>~~rs~~|4, 5<br>~~Rs~~<br>~~rs~~|
|Gyroscope Mechanical Frequencies<br>~~rs~~<br>~~rs~~|~~rs~~<br>~~rs~~|~~rs~~<br>~~rs~~|29.7<br>~~rs~~<br>~~rs~~|~~rs~~<br>~~rs~~|kHz<br>~~rs~~<br>~~rs~~|2<br>~~rs~~<br>~~rs~~|
|Gyroscope Start-UpTime<br>~~rs~~<br>~~Re~~|Time fromgyro enable togyro drive ready<br>~~rs~~<br>~~]~~|~~rs~~<br>~~]~~|35<br>~~rs~~<br>~~—}~~|45<br>~~rs~~<br>~~—}~~|ms<br>~~rs~~|1,7<br>~~rs~~|
|Output Data Rate<br>~~Re~~|Low Noise Mode(LNM)<br>~~]~~|12.5<br>~~]~~|~~—}~~|6400<br>~~—}~~|Hz|3|
||Low Power Mode(LPM)<br>~~]~~|1.5625<br>~~]~~|~~—}~~|400<br>~~—}~~|Hz|3|



## **Table 1. Gyroscope Specifications** 

## **Notes:** 

1. Derived from validation or characterization of parts, not tested in production. 

2. Tested in production. 

3. Guaranteed by design. 

4. Noise specifications shown are for low-noise mode. 

5. Calculated from Rate Noise Spectral Density. 

6. 20-bits data format supported in FIFO, see section 6. 

7. Measurement conditions: Gyroscope ODR = 6400Hz; Register field GYRO_UI_LPFBW_SEL set to 000 (low pass filter bypassed. 

8. Board-level specs performance depends on specific board design of TDK-InvenSense test boards and may not be directly reproducible with other board designs. 

Page 17 of 191 

Document Number: DS-000576 Revision: 1.0 

_**ICM-45605**_ 

## **3.2 ACCELEROMETER SPECIFICATIONS** 

Typical Operating Circuit of section 4.2, VDD = 1.8 V, VDDIO = 1.8V, TA=25°C, unless otherwise noted. 

|**PARAMETER**|**CONDITIONS**|**MIN**|**TYP**|**MAX**|**UNITS**|**NOTES**|
|---|---|---|---|---|---|---|
|**ACCELEROMETER SENSITIVITY**<br>~~Re~~<br>~~ee~~~~**e**e~~|||||||
|Full-Scale Range<br>~~ee~~|ACCEL_UI_FS_SEL = 1<br>~~ee~~|~~**e**~~|±16<br>~~**e**~~|~~**e**e~~|_g_<br>~~e~~|3<br>~~e~~|
||ACCEL_UI_FS_SEL = 2<br>~~ee~~|~~**e**~~|±8<br>~~**e**~~|~~**e**e~~<br>~~ee~~|_g_<br>~~e~~|3<br>~~e~~|
||ACCEL_UI_FS_SEL = 3<br>~~ee~~<br>~~e~~|~~**e**~~<br>~~e~~|±4<br>~~**e**~~|~~**e**e~~<br>~~ee~~|_g_<br>~~e~~|3<br>~~e~~|
||ACCEL_UI_FS_SEL = 4<br>~~ee~~<br>~~e~~|~~**e**~~<br>~~e~~|±2<br>~~**e**~~|~~**e**e~~<br>~~ee~~|_g_<br>~~e~~|3<br>~~e~~|
|ADC Word Length<br>~~ee~~<br>~~SSS~~|Output in two’s complement format<br>~~ee ~~<br>~~SSS~~|~~**e**~~<br>~~SSS ====~~|16<br>~~**e**~~<br>~~====~~|~~**e**e~~<br>~~ee~~<br>~~====~~|bits<br>~~e~~<br>~~====~~|3, 6<br>~~e~~<br>~~====~~|
|Sensitivity Scale Factor<br>~~SSS~~<br>~~a~~|ACCEL_UI_FS_SEL = 1<br>~~SSS~~|~~SSS ====~~|2,048<br>~~====~~|~~====~~|LSB/_g_<br>~~====~~|3<br>~~====~~|
||ACCEL_UI_FS_SEL = 2<br>~~a~~<br>~~SSS~~|~~a~~<br>~~SSS ====~~|4,096<br>~~a~~<br>~~====~~|~~a~~<br>~~====~~|LSB/_g_<br>~~a~~<br>~~====~~|3<br>~~a~~<br>~~====~~|
||ACCEL_UI_FS_SEL = 3<br>~~SSS~~|~~SSS ====~~|8,192<br>~~====~~|~~====~~|LSB/_g_<br>~~====~~|3<br>~~====~~|
||ACCEL_UI_FS_SEL = 4<br>~~SSS~~<br>~~ee~~|~~SSS ====~~<br>~~ee~~|16,384<br>~~====~~<br>~~ee~~|~~====~~<br>~~ee~~|LSB/_g_<br>~~====~~<br>~~ee~~|3<br>~~====~~|
|Sensitivity Scale Factor<br>Initial Tolerance<br>~~SSS~~<br>~~a~~<br>~~a~~|Component-level, 25°C<br>~~SSS~~<br>~~ee~~<br>~~ee~~|~~SSS ====~~<br>~~ee~~|±0.5<br>~~====~~<br>~~ee~~|~~====~~<br>~~ee~~|%<br>~~====~~<br>~~ee~~|2<br>~~====~~|
|Sensitivity Change vs.<br>Temperature<br>~~a~~<br>~~a~~|-40°C to +85°C, board-level<br>~~ee ~~<br>~~ee~~|~~ee ~~|±0.01<br> ~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|%/ºC<br>~~ee~~|1, 8|
|Nonlinearity<br>~~a~~<br>~~ee~~|Best fit straight line, ±2g; board-level, 25°C<br>~~ee~~<br>~~ee~~|~~ee~~|±0.1<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|%<br>~~ee~~|1, 8<br>~~ee~~|
|Cross-Axis Sensitivity<br>~~ee~~|Board-level<br>~~ee~~|~~ee~~|±1<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|%<br>~~ee~~|1, 8<br>~~ee~~|
|**ZERO-G OUTPUT**<br>~~ee~~<br>~~ee~~<br>~~es~~|||||||
|Initial Tolerance<br>~~es~~<br>~~a~~|Component-level, 25°C<br>~~es~~<br>~~ee~~|~~es~~<br>~~ee~~|±15<br>~~es~~<br>~~ee ee~~|~~es~~<br>~~ee ee~~|m_g_<br>~~es~~|2<br>~~es~~|
|Zero-G Level Change<br>vs. Temperature<br>~~es~~<br>~~a~~|-40°C to +85°C, board-level<br>~~es~~<br>~~ee~~|~~es~~<br>~~ee~~|±0.15<br>~~es~~<br>~~ee ee~~|~~es~~<br>~~ee ee~~|m_g/_ºC<br>~~es~~|1, 8<br>~~es~~|
|**OTHER PARAMETERS**<br>~~a~~<br>~~ee ee ee ee~~<br>~~NE~~<br>~~eeee~~|||||||
|Noise Spectral Density<br>~~NE~~<br>~~a~~|@ 10 Hz; Upto ±8gFSR<br>~~ee~~|~~ee~~|70<br>~~ee~~|~~ee~~|µ_g_/√Hz<br>~~ee~~|2, 4<br>~~ee~~|
||@ 10 Hz; ±16gFSR<br>~~ee~~<br>|~~ee~~<br>~~ee eee~~<br>|80<br>~~ee~~<br>~~eee~~<br>|~~ee~~<br>~~eee~~<br>|µ_g_/√Hz<br>~~ee~~<br>~~eee~~<br>|2, 4<br>~~ee~~<br>~~ee~~<br>|
|RMS Noise<br>~~NE~~<br>~~es~~<br>~~a~~|Bandwidth = 100 Hz; Upto ±8gFSR<br>~~ee~~<br>~~es~~<br>|~~ee~~<br>~~es~~<br>~~ee eee~~<br>|0.7<br>~~ee~~<br>~~es~~<br>~~eee~~<br>|~~ee~~<br>~~es~~<br>~~eee~~<br>|mg-rms<br>~~ee~~<br>~~es~~<br>~~eee~~<br>|4, 5<br>~~ee~~<br>~~es~~<br>~~ee~~<br>|
||Bandwidth = 100 Hz; ±16gFSR<br>~~es~~<br>|~~es~~<br>~~ee eee~~<br>|0.8<br>~~es~~<br>~~eee~~<br>|~~es~~<br>~~eee~~<br>|mg-rms<br>~~es~~<br>~~eee~~<br>|4, 5<br>~~es~~<br>~~ee~~<br>|
|Accelerometer Startup<br>Time<br>~~a~~|From sleep mode to valid data<br>|~~ee eee~~<br>|10<br>~~eee~~<br>|~~eee~~<br>|ms<br>~~eee~~<br>|1, 7<br>~~ee~~<br>|
|Output Data Rate<br>~~aet~~|Low Noise Mode(LNM)<br>~~et~~|12.5<br>~~ee eee~~<br>~~et~~|~~eee~~<br>~~et~~|6400<br>~~eee~~<br>~~et~~|12.5<br>~~eee~~<br>~~et~~|3<br>~~ee~~<br>~~et~~|
||Low Power Mode(LPM)<br>~~et~~|1.5625<br>~~et~~|~~et~~|400<br>~~et~~|1.5625<br>~~et~~|3<br>~~et~~|



## **Notes:** 

2. Tested in production. 

3. Guaranteed by design. 

4. Noise specifications shown are for low-noise mode. 

5. Calculated from Rate Noise Spectral Density. 

6. 20-bits data format supported in FIFO, see section 6. 

7. Measurement conditions: Gyroscope ODR = 6400Hz; Register field GYRO_UI_LPFBW_SEL set to 000 (low pass filter bypassed. 

8. Board-level specs performance depends on specific board design of TDK-InvenSense test boards and may not be directly reproducible with other board designs. 

Page 18 of 191 

Document Number: DS-000576 Revision: 1.0 

_**ICM-45605**_ 

## **3.3 ELECTRICAL SPECIFICATIONS** 

## **3.3.1 D.C. Electrical Characteristics** 

Typical Operating Circuit of section 4.2, VDD = 1.8 V, VDDIO = 1.8V, TA=25°C, unless otherwise noted. 

|**PARAMETER**<br>~~|~~|**CONDITIONS**<br>~~|~~|**MIN**<br>~~|~~|**TYP**<br>~~|~~|**MAX**<br>~~|~~|**UNITS**<br>~~|~~|**NOTES**<br>~~|~~|
|---|---|---|---|---|---|---|
|**SUPPLY VOLTAGES**<br>~~|~~|||||||
|VDD||1.71|1.8|3.6|V|1|
|VDDIO<br>~~PO~~|~~PO~~|1.08*<br>~~PO~~|1.8<br>~~PO~~|3.6<br>~~PO~~|V<br>~~PO~~|1<br>~~PO~~|
|**SUPPLY CURRENTS**<br>~~|~~|||||||
|Low-Noise Mode<br>~~2~~|6-Axis Gyroscope + Accelerometer (1600Hz ODR)<br>~~eG~~<br>~~G~~|~~eG~~<br>~~G~~~~**e**~~|420<br>~~eG~~<br>~~**e**~~|~~eG~~<br>~~**e**~~|µA<br>~~eG~~<br>~~**e**~~|2<br>~~eG~~<br>~~**e**~~|
||6-Axis Gyroscope + Accelerometer (6400Hz ODR)<br>~~eG~~<br>~~G~~|~~eG~~<br>~~G~~~~**e**~~|440<br>~~eG~~<br>~~**e**~~|~~eG~~<br>~~**e**~~|µA<br>~~eG~~<br>~~**e**~~|2<br>~~eG~~<br>~~**e**~~|
||3-Axis Accelerometer (1600Hz ODR)<br>~~es~~<br>~~G~~|~~es~~<br>~~G~~~~**e**~~|120<br>~~es~~<br>~~**e**~~|~~es~~<br>~~**e**~~|µA<br>~~es~~<br>~~**e**~~|2<br>~~es~~<br>~~**e**~~|
||3-Axis Accelerometer (6400Hz ODR)<br>~~G~~|~~G~~~~**e**~~|130<br>~~**e**~~|~~**e**~~|µA<br>~~**e**~~|2<br>~~**e**~~|
||3-Axis Gyroscope (1600Hz ODR)<br>~~G~~<br>~~EES~~|~~G~~~~**e**~~<br>~~EES~~|360<br>~~**e**~~<br>~~EES~~|~~**e**~~<br>~~EES~~|µA<br>~~**e**~~<br>~~EES~~|2<br>~~**e**~~<br>~~EES~~|
||3-Axis Gyroscope (6400Hz ODR)<br>~~G~~<br>~~e~~<br>~~ee~~|~~G~~~~**e**~~<br>~~e~~<br>|370<br>~~**e**~~<br>~~ee~~<br>|~~**e**~~<br>~~ee~~<br>|µA<br>~~**e**~~|2<br>~~**e**~~|
|Low-Power Mode|6-Axis Gyroscope + Accelerometer<br>(50Hz ODR; Gyro 10x AVG; Accel 4x AVG)<br>~~ee~~<br>~~ee~~|~~ee~~<br>|220<br>~~ee~~<br>~~ee~~<br>|~~ee~~<br>~~ee~~<br>|µA<br>~~ee~~|2<br>~~ee~~|
||6-Axis Gyroscope + Accelerometer<br>(200Hz ODR; Gyro 10x AVG; Accel 4x AVG)<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|325<br>~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|µA<br>~~ee~~|2<br>~~ee~~|
||3-Axis Accelerometer (50Hz ODR; 4x AVG)<br>~~ee ~~<br>~~ee~~|~~ee~~<br>~~ee~~|67<br>~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|µA<br>~~ee~~|2<br>~~ee~~|
||3-Axis Gyroscope (50Hz ODR; 10x AVG)<br>~~ee~~<br>~~eG~~|~~ee~~<br>~~eG~~|210<br>~~ee~~<br>~~eG~~|~~ee~~<br>~~eG~~|µA<br>~~ee~~<br>~~eG~~|2<br>~~ee~~<br>~~eG~~|
|Ultra Low-Power Mode<br>~~ee~~|3-Axis Accelerometer (50Hz ODR; 1x AVG)<br>~~ee~~|~~ee~~|15<br>~~ee~~|~~ee~~|µA<br>~~ee~~|2<br>~~ee~~|
|Full-ChipSleepMode<br>~~GF~~<br>~~Cn~~|At 25ºC<br>~~GF~~|~~GF~~|2.2<br>~~GF~~|~~GF~~|µA<br>~~GF~~|2<br>~~GF~~|
|**TEMPERATURE RANGE**<br>~~Cn~~<br>~~ee~~|||||||
|Specified Temperature Range<br>~~Cn~~<br>~~ee~~|Performance parameters are not applicable beyond<br>Specified Temperature Range|-40||+85|°C|1|



**Table 3. D.C. Electrical Characteristics** 

## **Notes:** 

   1. Guaranteed by design. 2. Derived from validation or characterization of parts, not tested in production. 

- Important Note: When using I3C[SM] interface the minimum VDDIO value is 1.1V. 

Page 19 of 191 

Document Number: DS-000576 Revision: 1.0 

_**ICM-45605**_ 

## **3.3.2 A.C. Electrical Characteristics** 

Typical Operating Circuit of section 4.2, VDD = 1.8 V, VDDIO = 1.8V, TA=25°C, unless otherwise noted. 

|**PARAMETER**<br>||**CONDITIONS**<br>||**MIN**|**TYP**|**MAX**|**UNITS**|**NOTES**|
|---|---|---|---|---|---|---|
|**SUPPLIES**<br>~~ee~~<br>~~es~~<br>~~rserrr~~<br>~~rsrs~~<br>~~es~~|||||||
|Supply Ramp Time<br>~~es~~<br>~~ee~~|Valid power-on RESET Monotonic ramp. Ramp<br>rate is 10% to 90% of the final value<br>~~rs~~<br>~~rs Grr~~|0.01<br>~~errr~~<br>~~Grr~~|~~rs~~<br>~~rs~~|1<br>~~rs~~|ms<br>~~es~~|1|
|Power Supply Noise<br>~~es~~<br>~~ee~~|VDD=1.8V or 3.6V, up to 1MHz<br>~~rs ~~<br>~~rs Grr~~|~~errr~~<br>~~Grr~~|10<br>~~rs ~~<br>~~rs~~|50<br> ~~rs~~|mV<br>peak-peak<br>~~es~~|1|
|**TEMPERATURE SENSOR**<br>~~ee~~<br>~~rs Grr~~<br>~~rs~~<br>~~|~~<br>~~OO~~|||||||
|OperatingRange<br>~~GC~~|Ambient<br>~~GC~~|-40<br>~~GC~~|~~GC~~<br>~~OO~~<br>~~GG~~|85<br>~~GC~~<br>~~OO~~<br>~~GG~~|°C<br>~~GC~~<br>~~GG~~|1<br>~~GC~~|
|25°C Output<br>~~GG~~|Output in two’s complement format<br>~~GG~~|~~GG~~|0<br>~~OO~~<br>~~GG~~<br>~~GG~~|~~OO~~<br>~~GG~~<br>~~GG~~|LSB<br>~~GG~~<br>~~GG~~|3<br>~~GG~~|
|ADC Resolution<br>~~GO~~|~~GO~~|~~GO~~<br>~~OO~~|16<br>~~GG~~<br>~~GO~~<br>~~OO~~|~~GG~~<br>~~GO~~<br>~~OG~~|bits<br>~~GG~~<br>~~GO~~<br>~~OG~~|2<br>~~GO~~|
|ODR<br>~~RG~~|With Filter<br>~~RG~~|1.5625<br>~~RG~~<br>~~OO~~|~~RG~~<br>~~OO~~|3200<br>~~RG~~<br>~~OG~~|Hz<br>~~RG~~<br>~~OG~~|2,4<br>~~RG~~|
|Room Temperature Offset<br>~~OO~~<br>~~ee~~|25°C<br>~~OO~~<br>~~errs~~|-5<br>~~OO~~<br>~~OO~~<br>~~errs~~<br>~~rs~~|~~OO~~<br>~~OO~~<br>~~errs~~<br>~~rs~~|5<br>~~OG~~<br>~~OO~~<br>~~errs~~<br>~~ee~~|°C<br>~~OG~~<br>~~OO~~<br>~~errs~~<br>~~es~~|3<br>~~OO~~<br>~~errs~~|
|Stabilization Time (fixed number of clock<br>cycles)<br>~~ee~~<br>~~a~~|~~errs~~|~~errs~~<br>~~rs~~|~~errs~~<br>~~rs~~<br>~~**Q**O~~|0.014<br>~~errs~~<br>~~ee~~<br>~~O~~|sec<br>~~errs~~<br>~~es~~<br>~~O~~|2<br>~~errs~~|
|Sensitivity<br>~~ee~~<br>~~QO~~<br>~~a~~|Trimmed<br>~~errs~~<br>~~QO~~|~~errs~~<br>~~rs~~<br>~~QO~~|128<br>~~errs~~<br>~~rs ~~<br>~~QO~~<br>~~**Q**O~~|~~errs~~<br> ~~ee~~<br>~~QO~~<br>~~O~~<br>~~OG~~|LSB/°C<br>~~errs~~<br>~~es~~<br>~~QO~~<br>~~O~~<br>~~OG~~|1<br>~~errs~~<br>~~QO~~|
|Sensitivityfor FIFO data<br>~~QO~~<br>~~a~~|Trimmed<br>~~QO~~<br>~~Q~~|~~QO~~<br>~~Q~~|2<br>~~QO~~<br>~~**Q**O~~|~~QO~~<br>~~O~~<br>~~OG~~|LSB/°C<br>~~QO~~<br>~~O~~<br>~~OG~~|1<br>~~QO~~|
|**POWER-ON RESET**<br>~~**Q**O~~<br>~~a~~<br>~~Q~~<br>~~OG~~<br>~~OOOO~~<br>~~RQ~~<br>~~GQ~~<br>~~GO~~|||||||
|Start-uptime for register read/write<br>~~RQ~~|Frompower-up<br>~~RQ~~|~~GQ~~|~~GQ~~|1<br>~~GQ~~|ms<br>~~GO~~|1|
|**I2C ADDRESS**<br>~~RQ~~<br>~~GQ~~<br>~~GO~~<br>~~es~~<br>~~rserrrrs~~<br>~~es~~<br>~~es~~|||||||
|**I2C ADDRESS**<br>~~es~~<br>~~Ce~~|AP_AD0 = 0<br>AP_AD0 = 1<br>~~rs~~|~~errr~~|1101000<br>1101001<br>~~rs~~|~~es~~|~~es~~||
|**DIGITAL INPUTS(FSYNC, SCLK, SDI, CS)**<br>~~es~~<br>~~rs errr rs~~<br>~~es~~<br>~~es~~<br>~~CeSS~~<br>~~eeee~~|||||||
|VIH, High Level Input Voltage<br>~~CeSS~~<br>~~Rs~~|~~ee~~<br>~~GG~~|0.7*VDDIO<br>~~ee~~<br>~~GG~~|~~ee~~|VDDIO +<br>0.5V<br>~~ee~~|V<br>~~ee~~|1|
|VIL, Low Level Input Voltage<br>~~SS~~<br>~~Rs~~<br>~~Rs~~|~~ee~~<br>~~GG~~<br>~~GQ~~|-0.5V<br>~~ee~~<br>~~GG~~<br>~~GQ~~|~~ee~~<br>~~GQ~~|0.3*VDDIO<br>~~ee~~<br>~~GQ~~|V<br>~~ee~~||
|CI, Input Capacitance<br>~~SS~~<br>~~Rs~~<br>~~Rs~~|~~ee~~<br>~~GG~~<br>~~GQ~~|~~ee~~<br>~~GG~~<br>~~GQ~~|<10<br>~~ee~~<br>~~GQ~~|~~ee~~<br>~~GQ~~|pF<br>~~ee~~||
|**DIGITAL OUTPUT(SDO, INT1, INT2)**<br>~~SS~~<br>~~ee ee~~<br>~~Rs~~<br>~~GQ~~<br>~~ee~~<br>~~——~~|||||||
|VOH, High Level Output Voltage<br>~~sO~~<br>~~——~~|RLOAD=1 MΩ;<br>~~sO~~|0.9*VDDIO<br>~~sO~~|~~sO~~|~~sO~~|V<br>~~sO~~|1|
|VOL1, LOW-Level Output Voltage<br>~~sO~~<br>~~——~~|RLOAD=1 MΩ;<br>~~sO~~|~~sO~~|~~sO~~|0.1*VDDIO<br>~~sO~~|V<br>~~sO~~||
|VOL.INT, INT Low-Level Output Voltage<br>~~——~~<br>~~Rs~~|OPEN=1, 0.3 mA sink<br>Current<br>~~GO~~|~~GO~~|~~GO~~|0.1|V||
|Output Leakage Current<br>~~——~~<br>~~Rs~~<br>~~ee~~|OPEN=1<br>~~GO~~<br>~~Pr es~~|~~GO~~<br>~~es en~~|100<br>~~GO~~<br>~~en~~|~~es~~|nA||
|tINT, INT Pulse Width<br>~~——~~<br>~~Rs~~<br>~~ee~~|int0_tpulse_duration= 0 , 1 (100µs, 8µs)<br>int1_tpulse_duration= 0,1(100µs,8µs)<br>~~GO~~<br>~~Pr es~~|~~GO~~<br>~~es en~~|100 or 8<br>~~GO~~<br>~~en~~|100<br>~~es~~|µs||
|**I2C I/O (SCL, SDA)**<br>~~——~~<br>~~eePr es en~~<br>~~es~~<br>~~Ge~~|||||||
|VIL, LOW-Level Input Voltage<br>~~Rs~~|~~Rs~~<br>~~Ge~~<br>~~e~~|-0.5V<br>~~Rs~~<br>~~Ge~~<br>~~es Gs~~|~~Rs~~<br>~~Gs~~|0.3*VDDIO<br>~~Rs~~|V<br>~~Rs~~|1|
|VIH, HIGH-Level Input Voltage<br>~~Rs~~<br>~~e~~|~~Rs~~<br>~~Ge~~<br>~~e~~~~**s**~~<br>~~e~~|0.7*VDDIO<br>~~Rs~~<br>~~Ge~~<br>~~**s**~~<br>~~es Gs~~|~~Rs~~<br>~~**s**~~<br>~~Gs~~|VDDIO +<br>0.5V<br>~~Rs~~<br>~~**s**~~|V<br>~~Rs~~<br>~~**s**~~||
|Vhys, Hysteresis<br>~~sO~~|~~e~~<br>~~sO~~|~~es Gs~~<br>~~sO~~|0.1*VDDIO<br>~~Gs~~<br>~~sO~~|~~sO~~|V<br>~~sO~~||
|VOL, LOW-Level Output Voltage<br>~~sO~~<br>~~es~~|3 mA sink current<br>~~sO~~<br>~~es~~|0<br>~~sO~~<br>~~es es~~|~~sO~~<br>~~es~~|0.4<br>~~sO~~|V<br>~~sO~~||
|IOL, LOW-Level Output Current<br>~~es~~|VOL=0.4 V<br>VOL=0.6 V<br>~~es~~|~~es es~~|3<br>6<br>~~es~~||mA<br>mA||
|Output Leakage Current<br>~~es~~<br>~~sO~~|~~es~~<br>~~sO~~|~~es es~~<br>~~sO~~|100<br>~~es~~<br>~~sO~~|~~sO~~|nA<br>~~sO~~||
|tof, Output Fall Time from VIHmaxto VILmax<br>~~dG~~<br>~~Cn~~|Cbbus capacitance in pf<br>~~dG~~<br>|20+0.1Cb<br>~~dG~~<br>|~~dG~~<br>|300<br>~~dG~~<br>|ns<br>~~dG~~||
|**INTERNAL CLOCK SOURCE**<br>~~Cnpp~~|||||||
|Clock Frequency Initial Tolerance<br>~~Cnpp~~<br>~~ee~~|Gyro inactive; 25°C<br>~~pp~~|-1.25<br>~~pp~~|~~pp~~|+1.25<br>~~pp~~|%|1|
||Gyro active; 25°C<br>~~pp~~<br>~~Rf~~<br>~~ee~~|-1.25<br>~~pp~~<br>~~Rf~~|~~pp~~<br>~~Rf~~|+1.25<br>~~pp~~<br>~~Rf~~<br>~~eee~~|%<br>~~Rf~~<br>~~eee~~|1<br>~~Rf~~<br>~~eee~~|
|Frequency Variation over Temperature<br>~~pp~~<br>~~ee~~|Gyro inactive; -40°C to +85°C<br>~~pp~~<br>~~Rf~~<br>~~ee~~|~~pp~~<br>~~Rf~~|~~pp~~<br>~~Rf~~|±3<br>~~pp~~<br>~~Rf~~<br>~~eee~~|%<br>~~Rf~~<br>~~eee~~|1<br>~~Rf~~<br>~~eee~~|
||Gyro active; -40oC to +85oC<br>~~ee~~|||±1<br>~~eee~~|%<br>~~eee~~|1<br>~~eee~~|



## **Table 4. A.C. Electrical Characteristics** 

## **Notes:** 

1. Based on design. Not tested in production. 

2. Guaranteed by design. 

3. Production tested. 

4. Temperature sensor ODR is the higher value between gyroscope and accelerometer ODR. 

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## **3.4 I[2] C TIMING CHARACTERIZATION** 

Typical Operating Circuit of section 4.2, VDD = 1.8 V, VDDIO = 1.8V, TA=25°C, unless otherwise noted. 

|**Parameters**<br>~~a~~|**Conditions**<br>||**Min**|**Typical**|**Max**<br>~~OO~~|**Units**<br>~~GO~~|**Notes**|
|---|---|---|---|---|---|---|
|**I2C TIMING(Host Interface)**<br>~~a~~<br>~~a~~|**I2C FAST-MODE PLUS**<br>~~GOO~~|~~GOO~~|~~GOO~~|~~GOO~~<br>~~OO~~|~~GOO~~<br>~~GO~~|~~GOO~~|
|fSCL, SCL Clock Frequency<br>~~a~~<br>~~ee~~|~~QQ~~|~~QQ~~|~~QQ~~|1<br>~~OO~~<br>~~QQ~~|MHz<br>~~GO~~<br>~~QQ~~|1<br>~~QQ~~|
|tHD.STA, (Repeated) START Condition Hold Time<br>~~ee~~|~~QQ~~<br>~~GG~~|0.26<br>~~QQ~~<br>~~GG~~|~~QQ~~<br>~~GG~~<br>~~GQ~~|~~QQ~~<br>~~GG~~<br>~~GQ~~|µs<br>~~QQ~~|1<br>~~QQ~~|
|tLOW, SCL Low Period<br>~~ee~~<br>~~DQ~~|~~QQ~~<br>~~DQ~~|0.50<br>~~QQ~~<br>~~DQ~~|~~QQ~~<br>~~DQ~~<br>~~GQ~~<br>~~GQ~~|~~QQ~~<br>~~DQ~~<br>~~GQ~~<br>~~GQ~~|µs<br>~~QQ~~<br>~~DQ~~|1<br>~~QQ~~<br>~~DQ~~|
|tHIGH, SCL High Period<br>~~DQ~~|~~DQ~~|0.26<br>~~DQ~~<br>~~QQ~~|~~GQ~~<br>~~DQ~~<br>~~GQ~~<br>~~QQ~~|~~GQ~~<br>~~DQ~~<br>~~GQ~~|µs<br>~~DQ~~|1<br>~~DQ~~|
|tSU.STA, Repeated START Condition Setup Time<br>~~GO~~<br>~~a~~|~~GO~~|0.26<br>~~GO~~<br>~~QQ~~|~~GQ~~<br>~~GO~~<br>~~QQ~~|~~GQ~~<br>~~GO~~<br>~~OO~~|µs<br>~~GO~~|1<br>~~GO~~|
|tHD.DAT, SDA Data Hold Time<br>~~QQ~~<br>~~a~~|~~QQ~~|0<br>~~QQ~~<br>~~QQ~~|~~QQ~~<br>~~QQ~~|~~QQ~~<br>~~OO~~|µs<br>~~QQ~~|1<br>~~QQ~~|
|tSU.DAT, SDA Data SetupTime<br>~~a~~|~~QQ~~<br>~~GR~~|50<br>~~QQ~~|~~QQ~~|~~OO~~<br>~~QQ~~|ns<br>~~QQ~~|1<br>~~QQ~~|
|tr, SDA and SCL Rise Time<br>~~PD~~|Cbbus cap. from 30 to 130pF<br>~~PD~~<br>~~GR~~|~~PD~~|~~PD~~|120<br>~~PD~~|ns<br>~~PD~~|1, 2<br>~~PD~~|
|tf, SDA and SCL Fall Time<br>~~es~~|Cbbus cap. from 30 to 130 pF<br>~~GR~~<br>~~es~~|20 x<br>(VDD/5.5 V)<br>~~es~~|~~es~~|120<br>~~es~~|ns<br>~~es~~|1, 2<br>~~es~~|
|tSU.STO, STOP Condition Setup Time<br>~~ee~~|~~ee~~<br>~~ee~~|0.26<br>~~ee~~<br>~~es~~|~~ee~~|~~ee~~|µs<br>~~ee~~|1<br>~~ee~~|
|tBUF, Bus Free Time Between STOP and START<br>Condition<br>~~ee~~|~~ee~~<br>~~ee~~|0.50<br>~~ee~~<br>~~es~~|~~ee~~<br>~~GO~~|~~ee~~|µs<br>~~ee~~|1<br>~~ee~~|
|Cb, Capacitive Load for each Bus Line<br>~~QO~~|~~ee~~<br>~~QO~~|30<br>~~es~~<br>~~QO~~|~~QO~~<br>~~GO~~<br>~~GO~~|130<br>~~QO~~|pF<br>~~QO~~|1<br>~~QO~~|
|tVD.DAT, Data Valid Time<br>~~QO~~|~~QO~~|~~QO~~|~~GO~~<br>~~QO~~<br>~~GO~~<br>~~QO~~|0.45<br>~~QO~~|µs<br>~~QO~~<br>~~GO~~|1<br>~~QO~~|
|tVD.ACK, Data Valid Acknowledge Time<br>~~QO~~|~~QO~~|~~QO~~|~~GO~~<br>~~QO~~<br>~~QO~~|0.45<br>~~QO~~|µs<br>~~QO~~<br>~~GO~~|1<br>~~QO~~|



**Table 5. I[2] C Host Interface Timing Characteristics** 

## **Notes:** 

1. Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets. 

2. Transition times are defined between thresholds: 0.3*VDDIO, 0.7*VDDIO. 

Typical Operating Circuit of section 4.2, VDD = 1.8 V, VDDIO = 1.8V, TA=25°C, unless otherwise noted. 

|**Parameters**<br>~~a~~|**Conditions**<br>||**Min**|**Typical**|**Max**|**Units**<br>~~GO~~|**Notes**|
|---|---|---|---|---|---|---|
|**I2C TIMING(Master Interface)**<br>~~a~~<br>~~a~~|**I2C FAST-MODE**<br>~~GOO~~<br>~~QO~~|~~GOO~~<br>~~QO~~|~~GOO~~<br>~~GO~~|~~GOO~~|~~GOO~~<br>~~GO~~|~~GOO~~|
|fSCL, SCL Clock Frequency<br>~~a~~|~~QO~~<br>~~Qs~~|~~QO~~<br>~~Gs~~|~~GO~~<br>~~Od~~|400<br>~~Od~~|kHz<br>~~GO~~|1|
|tHD.STA, (Repeated) START Condition Hold Time<br>~~es~~|~~QO~~<br>~~es~~<br>~~Qs~~|0.60<br>~~QO~~<br>~~es~~<br>~~Gs~~|~~GO~~<br>~~es~~<br>~~Od~~|~~es~~<br>~~Od~~<br>~~OO~~|µs<br>~~es~~<br>~~OO~~|1<br>~~es~~|
|tLOW, SCL Low Period<br>~~es~~<br>~~GG~~|~~es~~<br>~~Qs~~<br>~~GG~~|1.30<br>~~es~~<br>~~Gs~~<br>~~GG~~|~~es~~<br>~~Od~~<br>~~GG~~|~~es~~<br>~~Od~~<br>~~GG~~<br>~~OO~~<br>~~OO~~|µs<br>~~es~~<br>~~GG~~<br>~~OO~~<br>~~OO~~|1<br>~~es~~<br>~~GG~~|
|tHIGH, SCL High Period<br>~~GG~~<br>~~GG~~<br>~~a~~|~~GG~~<br>~~GG~~|0.60<br>~~GG~~<br>~~GG~~<br>~~QQ~~|~~GG~~<br>~~GG~~<br>~~QQ~~|~~GG~~<br>~~OO~~<br>~~GG~~<br>~~OO~~|µs<br>~~GG~~<br>~~OO~~<br>~~GG~~<br>~~OO~~|1<br>~~GG~~<br>~~GG~~|
|tSU.STA, Repeated START Condition Setup Time<br>~~GG~~<br>~~Gn~~<br>~~a~~<br>~~a~~|~~GG~~<br>~~Gn~~<br>~~**QO**~~|0.60<br>~~GG~~<br>~~Gn~~<br>~~QQ~~<br>~~**QO**~~|~~GG~~<br>~~Gn~~<br>~~QQ~~<br>~~GO~~|~~GG~~<br>~~OO~~<br>~~Gn~~|µs<br>~~GG~~<br>~~OO~~<br>~~Gn~~|1<br>~~GG~~<br>~~Gn~~|
|tHD.DAT, SDA Data Hold Time<br>~~a~~<br>~~a~~|~~**QO**~~|0<br>~~QQ~~<br>~~**QO**~~|~~QQ~~<br>~~GO~~<br>~~GO~~||µs|1|
|tSU.DAT, SDA Data SetupTime<br>~~a~~|~~**QO**~~|100<br>~~**QO**~~<br>~~GG~~|~~GO~~<br>~~GO~~<br>~~GG~~||ns|1|
|tr, SDA and SCL Rise Time<br>~~GO~~|Cbbus cap. from 30 to 200pF<br>~~GO~~<br>~~es~~|20<br>~~GO~~<br>~~GG~~|~~GO~~<br>~~GO~~<br>~~GG~~|300<br>~~GO~~|ns<br>~~GO~~|1, 2<br>~~GO~~|
|tf, SDA and SCL Fall Time<br>~~GO~~<br>~~es~~|Cbbus cap. from 30 to 200 pF<br>~~GO~~<br>~~es~~<br>~~es~~<br>~~OD~~|20 x<br>(VDD/5.5 V)<br>~~GO~~<br>~~GG~~<br>~~es~~<br>~~OD~~|~~GO~~<br>~~GG~~<br>~~es~~<br>~~QO~~|300<br>~~GO~~<br>~~es~~<br>~~GO~~|ns<br>~~GO~~<br>~~es~~|1, 2<br>~~GO~~<br>~~es~~|
|tSU.STO, STOP Condition Setup Time<br>~~re~~<br>~~a~~|~~es~~<br>~~re~~<br>~~OD~~<br>~~ee~~|~~re~~<br>~~OD~~<br>~~es~~|~~re~~<br>~~QO~~<br>~~ee~~|0.60<br>~~re~~<br>~~GO~~<br>~~ee~~|µs<br>~~re~~|1<br>~~re~~|
|tBUF, Bus Free Time Between STOP and START<br>Condition<br>~~ee~~<br>~~a~~|~~OD~~<br>~~ee~~<br>~~ee~~<br>~~GO~~|1.30<br>~~OD~~<br>~~ee~~<br>~~es~~<br>~~GO~~|~~QO~~<br>~~ee~~<br>~~ee~~<br>~~GO~~|~~GO~~<br>~~ee~~<br>~~ee~~|µs<br>~~ee~~|1<br>~~ee~~|
|Cb, Capacitive Load for each Bus Line<br>~~ee~~<br>~~a~~|~~ee~~<br>~~ee~~<br>~~GO~~|30<br>~~ee~~<br>~~es~~<br>~~GO~~|~~ee~~<br>~~ee~~<br>~~GO~~|200<br>~~ee~~<br>~~ee~~|pF<br>~~ee~~|1<br>~~ee~~|
|tVD.DAT, Data Valid Time<br>~~DQ~~|~~GO~~<br>~~DQ~~|~~GO~~<br>~~DQ~~|~~GO~~<br>~~DQ~~|0.90<br>~~DQ~~|µs<br>~~DQ~~|1<br>~~DQ~~|
|tVD.ACK, Data Valid Acknowledge Time<br>~~DF~~|~~DF~~|~~DF~~|~~DF~~|0.90<br>~~DF~~|µs<br>~~DF~~|1<br>~~DF~~|



## **Table 6. I[2] C Master Interface Timing Characteristics** 

## **Notes:** 

1. Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets. 

2. Transition times are defined between thresholds: 0.3*VDDIO, 0.7*VDDIO. 

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**==> picture [472 x 143] intentionally omitted <==**

**----- Start of picture text -----**<br>
tf tr tSU.DAT<br>SDA 70% 70%<br>30% : 30% \ “<br>tf Eww wn nnne! +. continued below at  a oO A<br>tr tVD.DAT<br>SCL 70% tHD.DAT 70%<br>30% 30%<br>tHD.STA 1/fSCL tLOW 9th clock cycle<br>S 1st clock cycle tHIGH<br>tBUF<br>SDA 70%<br>A 30%<br>tSU.STA tHD.STA tVD.ACK tSU.STO<br>SCL 70%<br>30%<br>Sr 9th clock cycle P S<br>**----- End of picture text -----**<br>


**Figure 1. I[2] C Bus Timing Diagram** 

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## **3.5 SPI TIMING CHARACTERIZATION – 4-WIRE SPI MODE** 

Typical Operating Circuit of section 4.2, VDD = 1.8 V, VDDIO = 1.8V, TA=25°C, unless otherwise noted. 

|**PARAMETERS**|**CONDITIONS**|**VDDIO < 1.71V**|**VDDIO < 1.71V**|**VDDIO ≥ 1.71V**|**VDDIO ≥ 1.71V**|||
|---|---|---|---|---|---|---|---|
|||**MIN**|**MAX**|**MIN**|**MAX**|**UNITS**|**NOTES**|
|**SPI TIMING**||||||||
|fSPC, SCLK Clock Frequency|Default||20||24|MHz|1|
|tLOW, SCLK Low Period||23.5||17||ns|1|
|tHIGH, SCLK High Period||22.5||17||ns|1|
|tSU.CS, CS Setup Time||17||17||ns|1|
|tHD.CS, CS Hold Time||5||5||ns|1|
|tSU.SDI, SDI Setup Time||13||13||ns|1|
|tHD.SDI, SDI Hold Time||8||8||ns|1|
|tVD.SDO, SDO Valid Time|Cload= 20 pF||18.5||18.5|ns|1|
|tHD.SDO, SDO Hold Time|Cload= 20 pF|3.5||3.5||ns|1|
|tDIS.SDO, SDO Output Disable Time|||28||28|ns|1|



**Table 7. 4-Wire SPI Timing Characteristics** 

## **Notes:** 

1. Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets 

**==> picture [470 x 147] intentionally omitted <==**

**----- Start of picture text -----**<br>
CS 70%<br>30%<br>tFall tRise tHD;CS<br>ee tSU;CS tHIGH 1/fCLK<br>SCLK 70%<br>30%<br>tSU;SDI tHD;SDI tLOW<br>SDI 70% MSB IN LSB IN<br>30%<br>22-228 tVD;SDO tHD;SDO tDIS;SDO<br>SDO 70%<br>MSB OUT LSB OUT<br>30%<br>$FO—E—<br>**----- End of picture text -----**<br>


**Figure 2. 4-Wire SPI Bus Timing Diagram** 

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## **3.6 SPI TIMING CHARACTERIZATION – 3-WIRE SPI MODE** 

Typical Operating Circuit of section 4.2, VDD = 1.8 V, VDDIO = 1.8V, TA=25°C, unless otherwise noted. 

|**PARAMETERS**|**CONDITIONS**|**VDDIO < 1.71V**|**VDDIO < 1.71V**|**VDDIO ≥ 1.71V**|**VDDIO ≥ 1.71V**|||
|---|---|---|---|---|---|---|---|
|||**MIN**|**MAX**|**MIN**|**MAX**|**UNITS**|**NOTES**|
|**SPI TIMING**||||||||
|fSPC, SCLK Clock Frequency|Default||20||24|MHz|1|
|tLOW, SCLK Low Period||23.5||17||ns|1|
|tHIGH, SCLK High Period||22.5||17||ns|1|
|tSU.CS, CS Setup Time||17||17||ns|1|
|tHD.CS, CS Hold Time||5||5||ns|1|
|tSU.SDIO, SDIO Input Setup Time||13||13||ns|1|
|tHD.SDIO, SDIO Input Hold Time||8||8||ns|1|
|tVD.SDIO, SDIO Output Valid Time|Cload= 20 pF||18.5||18.5|ns|1|
|tHD.SDIO, SDIO Output Hold Time|Cload= 20 pF|3.5||3.5||ns|1|
|tDIS.SDIO, SDIO Output Disable Time|||28||28|ns|1|



**Table 8. 3-Wire SPI Timing Characteristics** 

## **Notes:** 

1. Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets 

**==> picture [470 x 164] intentionally omitted <==**

**----- Start of picture text -----**<br>
CS 70%<br>30%<br>tFall tRise tHD;CS<br>ee tSU;CS tHIGH 1/fCLK<br>SCLK 70%<br>30%<br>tSU;SDIO tHD;SDIO tLOW<br>I 70% MSB IN LSB IN<br>30%<br>22 tVD;SDIO  -2-28 tHD;SDIO tDIS;SDIO<br>O 70%<br>MSB OUT LSB OUT<br>30%<br>a a) Ss Ss CS<br>Figure 3. 3-Wire SPI Bus Timing Diagram<br>SDIO<br>**----- End of picture text -----**<br>


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## **3.7 ABSOLUTE MAXIMUM RATINGS** 

Stress above those listed as “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to the absolute maximum ratings conditions for extended periods may affect device reliability. 

|**Parameter**|**Rating**|
|---|---|
|Supply Voltage, VDD|-0.5 V to +4 V|
|Supply Voltage, VDDIO|-0.5 V to +4 V|
|Input Voltage Level (FSYNC, SCL, SDA)|-0.5 V to VDDIO + 0.5 V|
|Acceleration (Any Axis, unpowered)|20,000g for 0.2 ms|
|Operating Temperature Range|-40°C to +85°C|
|Storage Temperature Range|-40°C to +125°C|
|Electrostatic Discharge (ESD) Protection|2 kV (HBM);<br>500 V (CDM)|
|Latch-up|JEDEC Class II (2) for VDDIO<br>≤ 1.98V, JEDEC Class I (1) for<br>VDDIO > 1.98V, ±100 mA|



**Table 9. Absolute Maximum Ratings** 

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## _**4 APPLICATIONS INFORMATION**_ 

## **4.1 PIN OUT DIAGRAM AND SIGNAL DESCRIPTION** 

|**Pin Number**|**Pin Name**|**Single Interface Mode**|**Dual Interface I2C Master**<br>**Mode**|**Notes**|
|---|---|---|---|---|
|1|AP_SDO /<br>AP_AD0|AP_SDO: AP SPI serial data<br>output (4-wire mode);<br>AP_AD0: AP I3CSM/ I2C<br>slave address LSB|AP_SDO: AP SPI serial data<br>output (4-wire mode);<br>AP_AD0: AP I3CSM/ I2C slave<br>address LSB|By default, internal pull-up is enabled. The internal weak pull-<br>up is not strong enough to replace a pull-up resistor usually<br>used on an open-drain bus. This pin supports both internal<br>pull up and pull-down functionality. Internal pull up/down is<br>controlled by two registers pads_ap_sdo_pe_trim_d2a[0] and<br>pads_ap_sdo_pud_trim_d2a[0]. Internal pull-up can be<br>disabled (enabled) by configuring<br>pads_ap_sdo_pe_trim_d2a[0] = 0 (1) and internal pull<br>direction down (up) can be set by<br>pads_ap_sdo_pud_trim_d2a[0] = 0 (1).<br>If the AP interface is active, the internal pull-up should be<br>disabled bysetting pads_ap_sdo_pe_trim_d2a[0]= 0.|
|2|RESV /<br>MAS_DA|RESV: No Connect or<br>Connect to VDDIO or<br>Connect to GND|MAS_DA: I2C serial master<br>data|By default, internal pull-up is enabled. The internal weak pull-<br>up is not strong enough to replace a pull-up resistor usually<br>used on an open-drain bus. This pin supports both internal<br>pull up and pull-down functionality. Internal pull up/down is<br>controlled by two registers<br>pads_aux1_sdi_pe_trim_d2a[0]<br>and<br>pads_aux1_sdi_pud_trim_d2a[0].<br>Internal pull-up can be disabled (enabled) by configuring<br>pads_aux1_sdi_pe_trim_d2a[0] = 0 (1) and internal pull<br>direction down (up) can be set by<br>pads_aux1_sdi_pud_trim_d2a[0] = 0 (1).<br>If the AUX1 interface is active, the internal pull-up should be<br>disabled by setting pads_aux1_sdi_pe_trim_d2a[0] = 0.<br>If pin2 is no connect, leave pads_aux1_sdi_pe_trim_d2a[0] =<br>1. If pin2 is connected to VDDIO or GND, disable internal pull-<br>upbysetting pads_aux1_sdi_pe_trim_d2a[0]= 0.|
|3|RESV /<br>MAS_CLK|RESV: No Connect or<br>Connect to VDDIO or<br>Connect to GND|MAS_CLK: I2C serial master<br>clock|By default, internal pull-up is enabled. The internal weak pull-<br>up is not strong enough to replace a pull-up resistor usually<br>used on an open-drain bus. This pin supports both internal<br>pull up and pull-down functionality. Internal pull up/down is<br>controlled by two registers<br>pads_aux1_sclk_pe_trim_d2a[0]<br>and<br>pads_aux1_sclk_pud_trim_d2a[0]<br>Internal pull-up can be disabled (enabled) by configuring<br>pads_aux1_sclk_pe_trim_d2a[0] = 0 (1) and internal pull<br>direction down (up) can be set by<br>pads_aux1_sclk_pud_trim_d2a[0] = 0 (1).<br>If the AUX1 interface is active, the internal pull-up should be<br>disabled by setting pads_aux1_sclk_pe_trim_d2a[0] = 0.<br>If pin3 is no connect, leave pads_aux1_sclk_pe_trim_d2a[0] =<br>1. If pin3 is connected to VDDIO or GND, disable internal pull-<br>upbysetting pads_aux1_sclk_pe_trim_d2a[0]= 0.|
|4|INT1 / INT|INT1: Interrupt 1 (Note:<br>INT1 can be push-pull or<br>open drain); INT: All|INT1: Interrupt 1 (Note: INT1<br>can be push-pull or open<br>drain); INT: All interrupts<br>mapped topin 4|By default, internal pull-up is disabled. The internal weak pull-<br>up is not strong enough to replace a pull-up resistor usually<br>used on an open-drain bus. This pin supports both internal|



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|{TDK|{TDK|{TDK InvenSense|<br>InvenSense|**_ICM-45605_**|
|---|---|---|---|---|
|||interrupts mapped to pin<br>4||pull up and pull-down functionality. Internal pull up/down is<br>controlled by two registers<br>pads_int1_pe_trim_d2a[0] and<br>pads_int1_pud_trim_d2a[0]. Internal pull can be disabled<br>(enabled) by configuring pads_int1_pe_trim_d2a[0] = 0 (1)<br>and internal pull direction down (up) can be set by<br>pads_int1_pud_trim_d2a[0]= 0(1).|
|5|VDDIO|VDDIO: IO power supply<br>voltage|VDDIO: IO power supply<br>voltage||
|6|GND|GND: Power supply<br>ground|GND: Power supply ground||
|7|RESV|RESV: No Connect or<br>Connect to VDDIO or<br>Connect to GND|RESV: No Connect or Connect<br>to VDDIO or Connect to GND|By default, internal pull-up is enabled. The internal weak pull-<br>up is not strong enough to replace a pull-up resistor usually<br>used on an open-drain bus. This pin supports both internal<br>pull up and pull-down functionality. Internal pull up/down is<br>controlled by two registers<br>pads_pin7_pe_trim_d2a[0]<br>and pads_pin7_cs_pud_trim_d2a[0]. Internal pull can be<br>disabled (enabled) by configuring pads_pin7_pe_trim_d2a[0]<br>= 0 (1) and internal pull direction down (up) can be set by<br>pads_pin7_cs_pud_trim_d2a[0] = 0 (1).<br>If pin7 is no connect, leave pads_pin7_pe_trim_d2a[0] = 1. If<br>pin7 is connected to VDDIO or GND, disable internal pull-up<br>bysetting pads_pin7_pe_trim_d2a[0]= 0.|
|8|VDD|VDD: Power supply<br>voltage|VDD: Power supply voltage||
|9|INT2 /<br>FSYNC|INT2: Interrupt 2 (Note:<br>INT2 can be push-pull or<br>open drain); FSYNC: Frame<br>sync input; If pin not used,<br>can be No Connect or<br>Connect to VDDIO|INT2: Interrupt 2 (Note: INT2<br>can be push-pull or open<br>drain); FSYNC: Frame sync<br>input; If pin not used, can be<br>No Connect or Connect to<br>VDDIO|By default, internal pull-up is enabled. The internal weak pull-<br>up is not strong enough to replace a pull-up resistor usually<br>used on an open-drain bus. This pin supports both internal<br>pull up and pull-down functionality. Internal pull up/down is<br>controlled by two registers pads_int2_pe_trim_d2a[0] and<br>pads_int2_pud_trim_d2a[0]. Internal pull-up can be disabled<br>(enabled) by configuring pads_int2_pe_trim_d2a[0] = 0 (1)<br>and internal pull direction down (up) can be set by<br>pads_int2_pud_trim_d2a[0] = 0 (1).<br>If pin9 is no connect, leave pads_int2_pe_trim_d2a[0] = 1. If<br>pin9 is connected as an I/O, disable internal pull-up by setting<br>pads_int2_pe_trim_d2a[0]= 0.|
|10|RESV|RESV: No Connect or<br>Connect to VDDIO or<br>Connect to GND|RESV: No Connect or Connect<br>to VDDIO or Connect to GND|By default, internal pull-up is enabled. The internal weak pull-<br>up is not strong enough to replace a pull-up resistor usually<br>used on an open-drain bus. This pin supports both internal<br>pull up and pull-down functionality. Internal pull up/down is<br>controlled by two registers<br>pads_aux1_cs_pe_trim_d2a[0]<br>and pads_aux1_cs_pud_trim_d2a[0]. Internal pull-up can be<br>disabled (enabled) by configuring<br>pads_aux1_cs_pe_trim_d2a[0] = 0 (1) and internal pull<br>direction down (up) can be set by<br>pads_aux1_cs_pud_trim_d2a[0] = 0 (1).<br>If the AUX1 interface is active, the internal pull-up should be<br>disabled by setting pads_aux1_cs_pe_trim_d2a[0] = 0. If<br>pin10 is no connect, leave pads_aux1_cs_pe_trim_d2a[0] = 1.<br>If pin10 is connected to VDDIO or GND, disable internal pull-<br>upbysetting pads_aux1_cs_pe_trim_d2a[0]= 0.|
|11|RESV|RESV: No Connect or<br>Connect to VDDIO or<br>Connect to GND|RESV: No Connect or Connect<br>to VDDIO or Connect to GND|By default, internal pull-up is enabled. The internal weak pull-<br>up is not strong enough to replace a pull-up resistor usually<br>used on an open-drain bus. This pin supports both internal<br>pull up and pull-down functionality. Internal pull up/down is<br>controlled bytwo registers|



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|||||pads_aux1_sdo_pe_trim_d2a[0]<br>and<br>pads_aux1_sdo_pud_trim_d2a[0]. Internal pull-up can be<br>disabled (enabled) by configuring<br>pads_aux1_sdo_pe_trim_d2a[0] = 0 (1) and internal pull<br>direction down (up) can be set by<br>pads_aux1_sdo_pud_trim_d2a[0] = 0 (1).<br>If AUX1 interface is active, the internal pull-up should be<br>disabled by setting pads_aux1_sdo_pe_trim_d2a[0] = 0. If<br>pin11 is no connect, leave pads_aux1_sdo_pe_trim_d2a[0] =<br>1. If pin11 is connected to VDDIO or GND, disable internal<br>pull-upbysetting pads_aux1_sdo_pe_trim_d2a[0]= 0.|
|---|---|---|---|---|
|12|AP_CS|AP_CS: AP SPI Chip select<br>(AP SPI interface); Connect<br>to VDDIO if using AP I3CSM<br>/ I2C interface|AP_CS: AP SPI Chip select (AP<br>SPI interface); Connect to<br>VDDIO if using AP I3CSM/ I2C<br>interface|By default, internal pull-up is enabled. The internal weak pull-<br>up is not strong enough to replace a pull-up resistor usually<br>used on an open-drain bus. This pin supports both internal<br>pull up and pull-down functionality. Internal pull up/down is<br>controlled by two registers pads_ap_cs_pe_trim_d2a[0] and<br>pads_ap_cs_pud_trim_d2a[0]. Internal pull can be disabled<br>(enabled) by configuring pads_ap_cs_pe_trim_d2a[0] = 0 (1)<br>and internal pull direction down (up) can be set by<br>pads_ap_cs_pud_trim_d2a[0] = 0 (1).<br>If the AP interface is active, the internal pull-up should be<br>disabled bysetting pads_ap_cs_pe_trim_d2a[0]= 0.|
|13|AP_SCL /<br>AP_SCLK|AP_SCL: AP I3CSM/ I2C<br>serial clock; AP_SCLK: AP<br>SPI serial clock|AP_SCL: AP I3CSM/ I2C serial<br>clock; AP_SCLK: AP SPI serial<br>clock|By default, internal pull-up is enabled. The internal weak pull-<br>up is not strong enough to replace a pull-up resistor usually<br>used on an open-drain bus. This pin supports both internal<br>pull up and pull-down functionality. Internal pull up/down is<br>controlled by two registers pads_ap_sclk_pe_trim_d2a[0]<br>and pads_ap_sclk_pud_trim_d2a[0]. Internal pull can be<br>disabled (enabled) by configuring<br>pads_ap_sclk_pe_trim_d2a[0] = 0 (1) and internal pull<br>direction down (up) can be set by<br>pads_ap_sclk_pud_trim_d2a[0] = 0 (1).<br>If the AP interface is active, the internal pull-up should be<br>disabled by setting pads_ap_sclk_pe_trim_d2a[0] = 0.|
|14|AP_SDA /<br>AP_SDIO /<br>AP_SDI|AP_SDA: AP I3CSM/ I2C<br>serial data; AP_SDIO: AP<br>SPI serial data I/O (3-wire<br>mode); AP_SDI: AP SPI<br>serial data input (4-wire<br>mode)|AP_SDA: AP I3CSM/ I2C serial<br>data; AP_SDIO: AP SPI serial<br>data I/O (3-wire mode);<br>AP_SDI: AP SPI serial data<br>input (4-wire mode)|By default, internal pull-up is enabled. The internal weak pull-<br>up is not strong enough to replace a pull-up resistor usually<br>used on an open-drain bus. This pin supports both internal<br>pull up and pull-down functionality. Internal pull up/down is<br>controlled by two registers pads_ap_sdi_pe_trim_d2a[0] and<br>pads_ap_sdi_pud_trim_d2a[0]. Internal pull can be disabled<br>(enabled) by configuring pads_ap_sdi_pe_trim_d2a[0] = 0 (1)<br>and internal pull direction down (up) can be set by<br>pads_ap_sdi_pud_trim_d2a[0] = 0 (1).<br>If the AP interface is active, the internal pull-up should be<br>disabled by setting pads_ap_sdi_pe_trim_d2a[0] = 0.|



**Table 10. Signal Descriptions** 

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**==> picture [397 x 239] intentionally omitted <==**

**----- Start of picture text -----**<br>
+Z<br>AP_SDO / AP_AD0 1 11 RESV<br>+Z +Y<br>RESV / MAS_DA 2 10 RESV<br>ICM-45605<br>+Y<br>RESV / MAS_CLK 3 9 INT2 / FSYNC<br>INT1 / INT 4 8 VDD<br>—<br>+X +X<br>AP_SCL / AP_SCLK AP_CS<br>14 13 12<br>5 6 7<br>VDDIO GND RESV<br>AP_SDA / AP_SDIO / AP_SDI<br>**----- End of picture text -----**<br>


**Figure 4. Pin Out Diagram for ICM-45605 2.5x3.0x0.81 mm LGA** 

## **4.2 TYPICAL OPERATING CIRCUIT (DUAL INTERFACE I[2] C MASTER MODE)** 

**==> picture [269 x 183] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDDIO<br>14 13 12<br>AP_AD0 1 11 RESV<br>MAS_DA 2 10 RESV<br>MAS_CLK 3 ICM-45605 9 INT2 / FSYNC<br>     – 3.6VDC<br>INT1 / INT 4 8 VDD<br>5 6 7<br>C1, 0.1 mF<br>      – 3.6VDC<br>C2, 0.1 µ F<br>AP_SDA<br>RESV<br>AP<br>_<br>SCL<br>VDDIO GND<br>**----- End of picture text -----**<br>


* Important Note: When using I3C[SM] interface the minimum VDDIO value is 1.1V. 

**Figure 5. ICM-45605 Application Schematic Dual Interface I[2] C Master Mode (I3C[SM] / I[2] C Interface to Host)** 

Note: I[2] C lines are open drain and pull-up resistors (e.g. 10 kΩ) are required. 

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**==> picture [275 x 213] intentionally omitted <==**

**----- Start of picture text -----**<br>
AP_CS<br>14 13 12<br>AP_SDO 1 11 RESV<br>MAS_DA 2 10 RESV<br>MAS_CLK 3 ICM-45605 9 INT2 / FSYNC<br>     – 3.6VDC<br>INT1 / INT 4 8 VDD<br>5 6 7<br>C1, 0.1 mF<br>      – 3.6VDC<br>r C2, 0.1 µ F<br>* Important Note: When using I3CSM interface the minimum VDDIO value is 1.1V.<br>AP_SDI<br>AP<br>_<br>AP_SDIO /  SCLK<br>VDDIO GND RESV<br>**----- End of picture text -----**<br>


**Figure 6. ICM-45605 Application Schematic Dual Interface I[2] C Master Mode (SPI Interface to Host)** 

## **4.3 TYPICAL OPERATING CIRCUIT (SINGLE INTERFACE MODE)** 

**==> picture [265 x 183] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDDIO<br>14 13 12<br>AP_AD0<br>1 11 RESV<br>RESV 2 10 RESV<br>ICM-45605 INT2 / FSYNC<br>RESV 3 9<br>     – 3.6VDC<br>INT1 / INT 4 8 VDD<br>5 6 7<br>C1, 0.1 mF<br>      – 3.6VDC<br>C2, 0.1 µ F<br>AP<br>_<br>AP_SDA SCL<br>VDDIO GND RESV<br>**----- End of picture text -----**<br>


**==> picture [166 x 6] intentionally omitted <==**

**----- Start of picture text -----**<br>
* Important Note: When using I3C [SM]  interface the minimum VDDIO value is 1.1V.<br>**----- End of picture text -----**<br>


**Figure 7. ICM-45605 Application Schematic Single Interface Mode (I3C[SM] / I[2] C Interface to Host)** 

Note: I[2] C lines are open drain and pull-up resistors (e.g. 10 kΩ) are required. 

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**==> picture [270 x 222] intentionally omitted <==**

**----- Start of picture text -----**<br>
AP_CS<br>14 13 12<br>AP_SDO 1 11 RESV<br>RESV 2 10 RESV<br>ICM-45605 INT2 / FSYNC<br>RESV 3 9<br>     – 3.6VDC<br>INT1 / INT 4 8 VDD<br>5 6 7<br>C1, 0.1 mF<br>      – 3.6VDC<br>|<br>A, C2, 0.1 µ F<br>* Important Note: When using I3CSM interface the minimum VDDIO value is 1.1V.<br>AP<br>_<br>AP_SDIO /  SCLK<br>VDDIO GND<br>AP_SDI<br>RESV<br>**----- End of picture text -----**<br>


**Figure 8. ICM-45605 Application Schematic Single Interface Mode (SPI Interface to Host)** 

## **4.4 BILL OF MATERIALS FOR EXTERNAL COMPONENTS** 

|**Component**|**Label**|**Specification**|**Quantity**|
|---|---|---|---|
|VDD Bypass Capacitor|C1|X7R, 0.1µF ±10%|1|
|VDDIO Bypass Capacitor|C2|X7R, 0.1µF ±10%|1|



**Table 11. Bill of Materials** 

Note: Use larger bypass capacitor than 0.1µF if power supply ripple exceeds 50mV peak-to-peak. 

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## **4.5 SYSTEM BLOCK DIAGRAM** 

**Figure 9. ICM-45605 System Block Diagram** 

Note: The above block diagram is an example. Please refer to the pin-out (section 4.1) for other configuration options. 

## **4.6 OVERVIEW** 

The ICM-45605 is comprised of the following key blocks and functions: 

- Three-axis MEMS rate gyroscope sensor with 16-bit ADCs and signal conditioning 

   - 20-bits data format support in FIFO for high-data resolution (see section 5 for details) 

- Three-axis MEMS accelerometer sensor with 16-bit ADCs and signal conditioning 

   - 20-bits data format support in FIFO for high-data resolution (see section 5 for details) 

- I3C[SM] , I[2] C and SPI Host Interface 

- I[2] C Master Interface for connection to external sensors 

- Self-Test 

- Clocking 

- Sensor Data Registers 

- FIFO 

- Interrupts 

- Digital-Output Temperature Sensor 

- Bias and LDOs 

- Charge Pump 

- Standard Power Modes 

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## **4.7 THREE-AXIS MEMS GYROSCOPE WITH 16-BIT ADCS AND SIGNAL CONDITIONING** 

The ICM-45605 includes a vibratory MEMS rate gyroscope, which detects rotation about the X-, Y-, and Z- Axes. When the gyroscope is rotated about any of the sense axes, the Coriolis Effect causes a vibration that is detected by a capacitive pickoff. The resulting signal is amplified, demodulated, and filtered to produce a voltage that is proportional to the angular rate.  This voltage is digitized using on-chip Analog-to-Digital Converters (ADCs) to sample each axis.  The full-scale range of the gyro sensors may be digitally programmed to ±15.625, ±31.25, ±62.5, ±125, ±250, ±500, ±1000, and ±2000degrees per second (dps). 

## **4.8 THREE-AXIS MEMS ACCELEROMETER WITH 16-BIT ADCS AND SIGNAL CONDITIONING** 

The ICM-45605 includes a 3-Axis MEMS accelerometer. Acceleration along a particular axis induces displacement of a proof mass in the MEMS structure, and capacitive sensors detect the displacement. The ICM-45605 architecture reduces the accelerometers’ susceptibility to fabrication variations as well as to thermal drift. When the device is placed on a flat surface, it will measure 0 _g_ on the X- and Y-axes and +1 _g_ on the Z-axis. The accelerometers’ scale factor is calibrated at the factory and is nominally independent of supply voltage. The fullscale range of the digital output can be adjusted to ±2 _g_ , ±4 _g_ , ±8 _g,_ and ±16 _g_ . 

## **4.9 I3C[SM] , I[2] C AND SPI HOST INTERFACE** 

The ICM-45605 communicates to the application processor using an I3C[SM] , I[2] C, or SPI serial interface. The ICM45605 always acts as a slave when communicating to the application processor. 

## **4.10 I[2] C MASTER INTERFACE FOR CONNECTION TO EXTERNAL SENSORS** 

The ICM-45605 has an I[2] C master interface for connection to external sensors. 

Up to 2 external sensors can be connected on this interface and their data read into the ICM-45605. I[2] C speed up to 400kHz is supported on the master interface. After I[2] C master finishes reading sensor data from the external sensor(s), the received sensor data is then reformatted by the internal processor (eDMP). The reformatted external sensor data is then moved into FIFO along with other internal sensor data. The external host reads the FIFO to retrieve both the external sensor data and the internal sensor data. 

- Independent of the number of external devices on the I[2] C bus, the I[2] C master automatically executes up to 4 I[2] C transactions per trigger. 

- The 4 I[2] C transactions are fully independent to each other. 

- Each I[2] C transaction can be targeting any external I[2] C device (capped at 2 external I[2] C devices). 

- Each I[2] C transaction can be a read or a write access transaction. 

- Each I[2] C transaction can be a burst or a non-burst access transaction. 

- A read transaction can be from an auto-incremented address location, or from a new address location. 

- A read operation with a new address location consumes one of the 4 I[2] C transactions per trigger. 

## **4.11 SELF-TEST** 

Self-test allows for the testing of the mechanical and electrical portions of the sensors. The self-test for each measurement axis can be activated by means of the gyroscope and accelerometer self-test registers. 

When the self-test is activated, the electronics cause the sensors to be actuated and produce an output signal. The output signal is used to observe the self-test response. 

The self-test response is defined as follows: 

Self-test response = Sensor output with self-test enabled – Sensor output with self-test disabled 

When the value of the self-test response is within the specified min/max limits of the product specification, the part has passed self-test.  When the self-test response exceeds the min/max values, the part is deemed to have failed self-test. 

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## **4.12 CLOCKING** 

The ICM-45605 has a flexible clocking scheme, allowing internal clock sources to be used for the internal synchronous circuitry.  This synchronous circuitry includes the signal conditioning and ADCs, and various control circuits and registers. 

Allowable internal sources for generating the internal clock are: 

- a) An internal relaxation oscillator 

- b) Auto-select between internal relaxation oscillator and gyroscope MEMS oscillator to use the best available source 

For internal sources, the only setting supporting specified performance in all modes is option b).  It is recommended that option b) be used when using internal clock source. 

## **4.13 SENSOR DATA REGISTERS** 

The sensor data registers contain the latest gyroscope, accelerometer, and temperature measurement data.  They are read-only registers and are accessed via the serial interface.  Data from these registers may be read anytime. 

## **4.14 INTERRUPTS** 

Interrupt functionality is configured via the Interrupt Configuration register. Items that are configurable include the interrupt pins configuration, the interrupt latching and clearing method, and triggers for the interrupt.  Items that can trigger an interrupt are (1) Clock generator locked to new reference oscillator (used when switching clock sources); (2) new data is available to be read (from the FIFO and Data registers); (3) accelerometer event interrupts; (4) FIFO watermark; (5) FIFO overflow.  The interrupt status can be read from the Interrupt Status register. 

## **4.15 DIGITAL-OUTPUT TEMPERATURE SENSOR** 

An on-chip temperature sensor and ADC are used to measure the ICM-45605 die temperature.  The readings from the ADC can be read from the FIFO or the Sensor Data registers. 

Temperature sensor register data TEMP_DATA is updated with new data at max (Accelerometer ODR, Gyroscope ODR). 

## **4.16 BIAS AND LDOS** 

The bias and LDO section generates the internal supply and the reference voltages and currents required by the ICM-45605. 

## **4.17 CHARGE PUMP** 

An on-chip charge pump generates the high voltage required for the MEMS oscillator. 

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## **4.18 STANDARD POWER MODES** 

The following table lists the user-accessible power modes for ICM-45605. 

|**Name**|**Gyro**|**Accel**|
|---|---|---|
|SleepMode|Off|Off|
|StandbyMode|Drive On|Off|
|Accelerometer Low-Power Mode|Off|Duty-Cycled|
|Accelerometer Ultra Low-Power Mode|Off|Duty-Cycled|
|Gyroscope Low-Power Mode|Duty-Cycled|Off|
|6-Axis Low-Power Mode|Duty-Cycled|Duty-Cycled|
|Accelerometer Low-Noise Mode|Off|On|
|Gyroscope Low-Noise Mode|On|Off|
|6-Axis Low-Noise Mode|On|On|



**Table 12. Standard Power Modes for ICM-45605** 

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## _**5 SIGNAL PATH**_ 

The following figure shows a block diagram of the signal path for ICM-45605. 

**==> picture [475 x 195] intentionally omitted <==**

**----- Start of picture text -----**<br>
Low-Noise Mode<br>Anti-Alias<br>ADC Interpolator FSR Selection<br>Filter (AAF)<br>f H}<br>LPF & ODR Sensor<br>UI Interface<br>Selection Registers<br>Low-Power Mode<br>Average<br>Ee +o<br>ACCEL_MODE<br>Figure 10. ICM-45605 Signal Path<br>The signal path starts with ADCs for the gyroscope and accelerometer. Low-Noise Mode and Low-Power Mode<br>options are available for the gyroscope and accelerometer and are selectable using register fields GYRO_MODE<br>and ACCEL_MODE respectively.<br>**----- End of picture text -----**<br>


In Low-Noise Mode, the ADC output is sent through an Anti-Alias Filter (AAF). The AAF is an FIR filter with fixed coefficients (not user configurable). The AAF can be enabled or disabled by the user using GYRO_SRC_CTRL and ACCEL_SRC_CTRL. 

The AAF is followed by an Interpolator. Sensor data can be re-timed using an interpolator when the user applies an external clock for higher ODR accuracy or operates the ICM-45605 in I3C[SM] synchronous mode. The Interpolator can be enabled or disabled by the user using GYRO_SRC_CTRL and ACCEL_SRC_CTRL. 

In Low-Power Mode, the gyroscope and accelerometer ADC outputs are sent through Average filters, with user configurable average filter setting using register fields GYRO_LP_AVG_SEL and ACCEL_LP_AVG_SEL. 

The output of Interpolator in Low-Noise Mode, or Average filter in Low-Power Mode is subject to UI LPF and ODR selection. The UI LPF BW is set by register bit field GYRO_UI_LPFBW_SEL and ACCEL_UI_LPFBW_SEL for gyroscope and accelerometer respectively. User selectable ODR is set using register fields GYRO_ODR and ACCEL_ODR. This is followed by Full Scale Range (FSR) selection based on user configurable settings for register fields GYRO_UI_FS_SEL and ACCEL_UI_FS_SEL. 

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## _**6 FIFO**_ 

The ICM-45605 contains up to 8Kbytes FIFO (default FIFO size is 2Kbytes, user can extend it up to 8Kbytes by disabling APEX functions) that is accessible via the serial interface. The FIFO configuration register determines which data is written into the FIFO. Possible choices include gyroscope data, accelerometer data, temperature readings, and FSYNC input. A FIFO counter keeps track of how many bytes of valid data are contained in the FIFO. 

ICM-45605 includes FIFO Compression algorithm that allows storing compressed sensor data in FIFO frames, thus virtually providing more FIFO space. It allows to store up to 4 times the number of frames with respect to noncompressed data. Frame decompression must be performed on the Host which reads the FIFO. Compression algorithm uses a hardware lossless algorithm, based on data variation analysis of each axis. Compression ratios x2, x3, x4 are supported, providing up to 32kByte data storage capability. 

A 20-bit data format support is included in one of the FIFO packets structures. When the 20-bit data format is used, the gyroscope data consists of 20-bit of actual data, the accelerometer data consists of 19-bit of actual data and the LSB is always set to 0. Irrespective of the user-full scale selection, this high-resolution 20-bit data format is always scaled to ±4000dps (131.1 LSB/dps) for gyroscope and ±32g (16384 LSB/g) for accelerometer. 

FIFO packet decimation capability is provided for additional storage optimization. User can configure the FIFO Data Rate (FDR) to control the decimation rate for writing packets to the FIFO.  User must disable sensors when initializing FDR control value or making changes to it. 

## **6.1 PACKET STRUCTURE** 

FIFO packets are assembled in different packet sizes based on the enabled sensors. When internal sensors Accel and Gyro are enabled, the following packets are available: 

- 8 bytes packet: Contains Accel-only or Gyro-only data and Temperature data (1 byte) 

- 16 bytes packet: Contains Accel data, Gyro data, Temperature data (1 byte), Timestamp 

- 20 bytes packet: Contains high-resolution Accel data, Gyro data, Temperature data (2 bytes), Timestamp 

The following figure shows packets organization for each format (big endian mode). 

**==> picture [385 x 200] intentionally omitted <==**

**----- Start of picture text -----**<br>
Accel+Gyro<br>Accel-only Gyro-only Accel+Gyro<br>High Resolution<br>(8 bytes) (8 bytes) (16 bytes)<br>(20 bytes)<br>7 0 7 0 7 0 7 0<br>0 Header 0 Header 0 Header 0 Header<br>1 Ax H 1 Gx H 1 Ax H 1 Ax H<br>2 Ax L 2 Gx L 2 Ax L 2 Ax L<br>3 Ay H 3 Gy H 3 Ay H 3 Ay H<br>4 Ay L 4 Gy L 4 Ay L 4 Ay L<br>5 Az H 5 Gz H 5 Az H 5 Az H<br>6 Az L 6 Gz L 6 Az L 6 Az L<br>7 Temp (1 byte) 7 Temp (1 byte) 7 Gx H 7 Gx H<br>8 Gx L 8 Gx L<br>9 Gy H 9 Gy H<br>10 Gy L 10 Gy L<br>11 Gz H 11 Gz H<br>12 Gz L 12 Gz L<br>13 Temp (1 byte) 13 Temp H<br>14 Timestamp H 14 Temp L<br>15 Timestamp L 15 Timestamp H<br>16 Timestamp L<br>17 Ax LSB Gx LSB<br>18 Ay LSB Gy LSB<br>19 Az LSB Gz LSB<br>**----- End of picture text -----**<br>


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When external sensors ES0 and ES1 are enabled, the following packets are available: 

- 16 bytes packet: Contains 6/9 bytes ES0-only or ES1-only data 

- 20 bytes frame: Contains 6/9 bytes ES0 data and ES1 data 

- 32 bytes frame: Contains Accel data, Gyro data, 6/9 bytes ES0 data, ES1 data, Temperature data (1 byte), Timestamp. The 32 bytes format is always selected when at least one internal sensor and one external sensor are enabled 

The following figure shows packets organization for each format (big endian mode). 

**==> picture [545 x 532] intentionally omitted <==**

**----- Start of picture text -----**<br>
Accel + Gyro + Accel + Gyro +<br>6b Ext Sensor 0 + 9b Ext Sensor 0 + 6b Ext Sensor 0 + 9b Ext Sensor 0 +<br>6b Ext Sensor 0 9b Ext Sensor 0 Ext Sensor 1<br>(16 bytes) (16 bytes) (16 bytes) Ext Sensor 1 Ext Sensor 1 Ext Sensor 1 Ext Sensor 1<br>7 0 7 0 7 0 7 (20 bytes) 0 7 (20 bytes) 0 7 (32 bytes) 0 7 (32 bytes) 0<br>0 Header 0 Header 0 Header 0 Header 0 Header 0 Header 0 Header<br>1 Header 2 1 Header 2 1 Header 2 1 Header 2 1 Header 2 1 Header 2 1 Header 2<br>2 ES0_B0 2 ES0_B0 2 ES1_B0 2 ES0_B0 2 ES0_B0 2 Ax H 2 Ax H<br>3 ES0_B1 3 ES0_B1 3 ES1_B1 3 ES0_B1 3 ES0_B1 3 Ax L 3 Ax L<br>4 ES0_B2 4 ES0_B2 4 ES1_B2 4 ES0_B2 4 ES0_B2 4 Ay H 4 Ay H<br>5 ES0_B3 5 ES0_B3 5 ES1_B3 5 ES0_B3 5 ES0_B3 5 Ay L 5 Ay L<br>6 ES0_B4 6 ES0_B4 6 ES1_B4 6 ES0_B4 6 ES0_B4 6 Az H 6 Az H<br>7 ES0_B5 7 ES0_B5 7 ES1_B5 7 ES0_B5 7 ES0_B5 7 Az L 7 Az L<br>8 Reserved 8 ES0_B6 8 Reserved 8 Reserved 8 ES0_B6 8 Gx H 8 Gx H<br>9 Reserved 9 ES0_B7 9 Reserved 9 Reserved 9 ES0_B7 9 Gx L 9 Gx L<br>10 Reserved 10 ES0_B8 10 Reserved 10 Reserved 10 ES0_B8 10 Gy H 10 Gy H<br>11 Reserved 11 Reserved 11 Reserved 11 ES1_B0 11 ES1_B0 11 Gy L 11 Gy L<br>12 Reserved 12 Reserved 12 Reserved 12 ES1_B1 12 ES1_B1 12 Gz H 12 Gz H<br>13 Reserved 13 Reserved 13 Reserved 13 ES1_B2 13 ES1_B2 13 Gz L 13 Gz L<br>14 Reserved 14 Reserved 14 Reserved 14 ES1_B3 14 ES1_B3 14 ES0_B0 14 ES0_B0<br>15 Reserved 15 Reserved 15 Reserved 15 ES1_B4 15 ES1_B4 15 ES0_B1 15 ES0_B1<br>16 ES1_B5 16 ES1_B5 16 ES0_B2 16 ES0_B2<br>17 Reserved 17 Reserved 17 ES0_B3 17 ES0_B3<br>18 Reserved 18 Reserved 18 ES0_B4 18 ES0_B4<br>19 Reserved 19 Reserved 19 ES0_B5 19 ES0_B5<br>20 Reserved 20 ES0_B6<br>21 Reserved 21 ES0_B7<br>22 Reserved 22 ES0_B8<br>23 ES1_B0 23 ES1_B0<br>24 ES1_B1 24 ES1_B1<br>25 ES1_B2 25 ES1_B2<br>26 ES1_B3 26 ES1_B3<br>27 ES1_B4 27 ES1_B4<br>28 ES1_B5 28 ES1_B5<br>29 Temp (1 byte) 29 Temp (1 byte)<br>30 Timestamp H 30 Timestamp H<br>sel) 31 Timestamp L | 31 Timestamp L<br>6.2 FIFO HEADER<br>The following table shows the structure of the first byte of the FIFO header.<br>Bit Field  Item  Description<br>1: FIFO header length is extended to 2 bytes. The second byte is used for<br>7  EXT_HEADER  compressed frame decoding fields or external sensors information<br>0: FIFO header length is 1 byte<br>1: Accel is enabled or high resolution is enabled<br>6  ACCEL_EN<br>0: Accel is not enabled and high resolution is not enabled<br>1: Gyro is enabled or high resolution is enabled<br>5  GYRO_EN<br>0: Gyro is not enabled and high resolution is not enabled<br>1: High-resolution is enabled (20-bytes format)<br>4  HIRES_EN<br>0: High-resolution is not enabled<br>1: Timestamp field is included in the packet. This requires that: a) high-resolution is<br>enabled, or b) both Accel and Gyro are enabled, or c) either Accel or Gyro are<br>enabled, and either ES0 or ES1 are enabled<br>3  TMST_FIELD_EN<br>The timestamp field contains the timestamp value or FSYNC-ODR delay depending<br>on configuration<br>0: Timestamp field is not included in the packet<br>1: FSYNC is triggered and the Timestamp field contains the FSYNC-ODR delay<br>2  FSYNC_TAG_EN  0: FSYNC is not triggered and the Timestamp field does not contain the FSYNC-ODR<br>delay<br>**----- End of picture text -----**<br>


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|{TDK|{TDK InvenSense|<br>**_ICM-45605_**<br>InvenSense|
|---|---|---|
|1|ACCEL_ODR|1: The ODR for accel is different for this accel data packet compared to the previous<br>accel packet<br>0: The ODR for accel is the same as thepreviouspacket with accel|
|0|GYRO_ODR|1: The ODR for gyro is different for this gyro data packet compared to the previous<br>gyro packet<br>0: The ODR forgyro is the same as thepreviouspacket withgyro|



When External Sensors are enabled, an additional header byte is used. The second byte of the header is described below. 

|**Bit Field**|**Item**|**Description**|
|---|---|---|
|7:5|-|Reserved|
|4|ES0_6b_9b|Indicates how many bytes sensor ES0 provides<br>1: Sensor ES0 provides 9 bytes data<br>0: Sensor ES0provides 6 bytes data|
|3|ES1_VLD|1: ES1 data is valid<br>0: ES1 data is not valid|
|2|ES0_VLD|1: ES0 data is valid<br>0: ES0 data is not valid|
|1|ES1_EN|1: Sensor ES1 is enabled<br>0: Sensor ES1 is not enabled|
|0|ES0_EN|1: Sensor ES0 is enabled<br>0: Sensor ES0 is not enabled|



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## _**7 PROGRAMMABLE INTERRUPTS**_ 

The ICM-45605 has a programmable interrupt system that can generate an interrupt signal on the INT pins. Status flags indicate the source of an interrupt. Interrupt sources may be enabled and disabled individually. There are two interrupt outputs. Any interrupt may be mapped to either interrupt pin as explained in the register section.  The following configuration options are available for the interrupts: 

- INT1 and INT2 can be push-pull or open drain 

- Level or pulse mode 

- Active high or active low 

Additionally, ICM-45605 includes In-band Interrupt (IBI) support for the I3C[SM] interface. 

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## _**8 EDMP**_ 

The on-chip Enhanced Digital Motion Processor (EDMP) is designed for motion processing of next-gen sensor products. It enables ultra-low power run-time and offloads computation of motion processing and sensor fusion algorithms from the host processor. It enables the host system to execute custom algorithms and issue software interrupts to the external environment. The EDMP can be deployed in the system to minimize system level power, simplify the software architecture, and save valuable MIPS on the host processor. The EDMP implements a motion sensor optimized custom ISA with special motion processing instructions. 

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## _**9 APEX MOTION FUNCTIONS**_ 

The APEX ( **A** dvanced **P** edometer and **E** vent Detection – ne **X** t gen) features of ICM-45605 consist of: 

- Pedometer: Tracks Step Count, also issues Step Detect interrupt. 

- Tilt Detection: Issues an interrupt when the Tilt angle exceeds 35 for more than a programmable time. 

- Raise to Wake/Sleep: Gesture detection for wake and sleep events.  Interrupt is issued when either of these two events are detected. 

- Single Tap / Double Tap Detection: Issues an interrupt when a tap is detected, along with the tap type. 

- Wake on Motion: Detects motion when accelerometer data exceeds a programmable threshold. This motion event can be used to enable chip operation from sleep mode. 

- Freefall Detection: Triggers an interrupt when device freefall is detected and outputs freefall duration. 

- Significant Motion Detection: Detects significant motion based on accelerometer data. 

- Low-G Detection: Triggers an interrupt when absolute value of accelerometer combined axis falls below a programmable threshold and stays below the threshold for a programmable time. 

- High-G Detection: Triggers an interrupt when absolute value of accelerometer goes above a programmable threshold and stays above the threshold for a programmable time. 

These functions are run as software on EDMP. 

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## _**10 DIGITAL INTERFACE**_ 

## **10.1 I3C[SM] , I[2] C AND SPI SERIAL INTERFACES** 

The internal registers and memory of the ICM-45605 can be accessed using I3C[SM] at 12.5 MHz (data rates up to 12.5 Mbps in SDR mode, 25 Mbps in DDR mode), I[2] C at 1 MHz or SPI at 24 MHz. SPI operates in 3-wire or 4-wire mode. Pin assignments for serial interfaces are described in section 4. 

## **10.2 I3C[SM] INTERFACE** 

I3C[SM] is a new 2-wire digital interface comprised of the signals serial data (SDA) and serial clock (SCLK). I3C[SM] is intended to improve upon the I[2] C interface, while preserving backward compatibility. The I3C[SM] capability of this device is compliant with Version 1.1.1 of the MIPI Alliance Specification for I3C[SM] . Please refer to the corresponding MIPI I3C[SM] specification for I3C[SM] timing information for this device. 

I3C[SM] carries the advantages of I²C in simplicity, low pin count, easy board design, and multi-drop (vs. point to point), but provides the higher data rates, simpler pads, and lower power of SPI. I3C[SM] adds higher throughput for a given frequency, in-band interrupts (from slave to master), dynamic addressing. 

ICM-45605 supports the following features of I3C[SM] : 

- SDR data rate up to 12.5 Mbps 

- DDR data rate up to 25 Mbps 

- Dynamic address allocation 

- In-band Interrupt (IBI) support 

- Support for asynchronous timing control mode 0 

- Error detection (CRC and/or Parity) 

- Common Command Code (CCC) 

The ICM-45605 always operates as an I3C[SM] slave device when communicating to the system processor, which thus acts as the I3C[SM] master. I3C[SM] master controls an active pullup resistance on SDA, which it can enable and disable. The pullup resistance may be a board level resistor controlled by a pin, or it may be internal to the I3C[SM] master. 

The following table shows I3C[SM] Common Command Code (CCC) commands supported by the device. 

|**CCC Description**|**CCC Description**|**CCC Description**|**Required or Optional**<br>**per I3C v1.0**|**Supported by**<br>**ICM-45605 Host**<br>**Interface**|
|---|---|---|---|---|
||1|ENEC, broadcast mode. (Enable Events).|Required|Yes|
||2|DISEC, broadcast mode. (Disable Events)|Required|Yes|
||3|ENTAS0, broadcast mode. (Enter Activity State 0)|Required|Yes|
||4|ENTAS1, broadcast mode. (Enter Activity State 1)|Optional|No|
||5|ENTAS2, broadcast mode. (Enter Activity State 0)|Optional|No|
||6|ENTAS3, broadcast mode. (Enter Activity State 0)|Optional|No|
||7|RSTDAA, broadcast mode. (Reset dynamic address<br>assignment).|Required|Yes|
||8|ENTDAA, broadcast mode. (Enter dynamic address<br>assignment).|Required|Yes|



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||9|DEFSLVS, broadcast mode. (Define list of slaves).|DEFSLVS, broadcast mode. (Define list of slaves).|Optional|No|
|---|---|---|---|---|---|
||10|SETMWL, broadcast mode. (Set Max Write Length).||Required|Yes|
||11|SETMRL, broadcast mode. (Set Max Read Length).||Required|Yes|
||12|ENTTM, broadcast mode. (Enter Test Mode).||Optional|No|
||13|ENTHDR0, broadcast mode. (Enter HDR DDR mode)||Optional|Yes|
||14|ENTHDR1, broadcast mode. (Enter HDR TSP mode)||Optional|No|
|~~ee~~|15<br>~~a~~|ENTHDR2, broadcast mode. (Enter HDR TSL mode)||Optional|No|
|~~ee~~<br>~~a~~|16<br>~~a~~<br>~~a~~|SETXTIME, broadcast mode. (Exchange Timing Information).<br>~~ee~~<br>~~tr Ge~~||||
|~~ee ~~<br>~~a~~|~~a~~<br>~~a~~|16.1<br>~~ee~~|Defining byte = 0x7F (ST)<br>~~tr Ge~~|Optional<br>~~Ge~~|Yes|
|~~a~~<br>~~a~~|~~a~~|16.2<br>~~ee~~|Definingbyte = 0xBF (DT)<br>~~tr Ge~~|Optional<br>~~Ge~~|Yes|
|~~a~~||16.3|Defining byte = 0xDF (Enter Async Mode 0)|Optional|Yes|
|~~a~~||16.4|Defining byte = 0xEF (Enter Async Mode 1)|Optional|No|
|||16.5|Defining byte = 0xF7 (Enter Async Mode 2)|Optional|No|
|||16.6|Defining byte = 0xFB (Enter Async Mode 3)|Optional|No|
|~~a~~|~~a~~|16.7|Defining byte = 0xFD (Async Trigger for Async<br>Mode 3).|Optional<br>~~es~~|No|
|~~es~~<br>~~a~~|~~es~~<br>~~a~~|16.8<br>~~es~~<br>~~ee~~|Definingbyte = 0x3F (TPH)<br>~~es~~<br>~~en De~~|Optional<br>~~es~~<br>~~es~~<br>~~De~~|Yes<br>~~es~~|
|~~es~~<br>~~a~~|~~es~~<br>~~a~~|16.9<br>~~es~~<br>~~ee~~|Definingbyte = 0x9f (TU)<br>~~es~~<br>~~en De~~|Optional<br>~~es~~<br>~~es~~<br>~~De~~<br>~~ey~~|Yes<br>~~es~~|
|~~te~~<br>~~a~~|~~te~~<br>~~a~~|16.10<br>~~ee~~<br>~~te~~<br>|Definingbyte = 0x8F (ODR)<br>~~en De~~<br>~~te~~<br>|Optional<br>~~De~~<br>~~te~~<br>~~ey~~<br>~~ny~~<br>|Yes<br>~~te~~<br>|
|~~te~~<br>~~ts~~<br>~~a~~|17<br>~~te~~<br>~~ts~~<br>~~a~~|ENEC, direct mode. (Enable Events).<br>~~te~~<br>~~ts~~<br>||Required<br>~~te~~<br>~~ey~~<br>~~ts~~<br>~~ny~~<br><br>~~GR~~|Yes<br>~~te~~<br>~~ts~~<br>|
|~~ts~~<br>~~a~~<br>~~a~~|18<br>~~ts~~<br>~~a~~<br>~~a~~|DISEC, direct mode. (Disable Events).<br>~~ts~~<br>~~rn~~<br>||Required<br>~~ts~~<br>~~ny~~<br>~~rn~~<br>~~GR~~<br>~~ey~~<br>|Yes<br>~~ts~~<br>~~rn~~<br>|
|~~es~~<br>~~a~~<br>~~a~~|19<br>~~es~~<br>~~a~~<br>|ENTAS0, direct mode. (Enter Activity State 0).<br>~~es~~<br><br>||Required<br>~~GR~~<br>~~es~~<br>~~ey~~<br><br>~~GR~~<br>|Yes<br>~~es~~<br><br>|
|~~es~~<br>~~a~~<br>~~a~~|20<br>~~es~~<br>~~a~~<br>|ENTAS1, direct mode. (Enter ActivityState 1).<br>~~es~~<br>~~rn~~<br>||Optional<br>~~es~~<br>~~ey~~<br>~~rn~~<br>~~GR~~<br>|No<br>~~es~~<br>~~rn~~<br>|
|~~a~~|21<br>~~ty~~|ENTAS2, direct mode. (Enter ActivityState 2).<br>~~ty~~||Optional<br>~~GR~~<br>~~ty~~<br>~~Ge~~|No<br>~~ty~~|
|~~a~~<br>~~a~~|22<br>~~ty~~<br>~~a~~|ENTAS3, direct mode. (Enter ActivityState 3).<br>~~ty~~<br>~~en~~||Optional<br>~~GR~~<br>~~ty~~<br>~~en~~<br>~~Ge~~|No<br>~~ty~~<br>~~en~~|
|~~tt~~|23<br>~~tt~~|RSTDAA, direct mode. (Reset dynamic address<br>assignment).<br>~~tt~~||Required<br>~~Ge~~<br>~~tt~~|Yes<br>~~tt~~|
|~~tt~~|24<br>~~tt~~|SETDASA, direct mode. (Set Dynamic address from static<br>address).<br>~~tt~~||Optional<br>~~tt~~|Yes<br>~~tt~~|



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||25|SETNEWDA, direct mode. (Set new dynamic address)|SETNEWDA, direct mode. (Set new dynamic address)|Required|Yes|
|---|---|---|---|---|---|
||26|SETMWL, direct mode. (Set Max Write Length).||Required / Conditional|Yes|
||27|SETMRL, direct mode. (Set Max Read length).||Required / Conditional|Yes|
||28|GETMWL, direct mode. (Get Max write length).||Required / Conditional|Yes|
||29|GETMRL, direct mode. (Get Max Read length).||Required / Conditional|Yes|
||30|GETPID, direct mode. (Get provisional ID).||Required|Yes|
||31|GETBCR, direct mode. (Get Bus Characteristics Register).||Required|Yes|
||32|GETDCR, direct mode. (Get Device Characteristics<br>Register).||Required|Yes|
||33|GETSTATUS, direct mode. (Get Device Status).||Required|Yes|
||34|GETACCMST, direct mode. (Get Accept Mastership).||Optional|No|
||35|SETBRGTGT, direct mode. (Set Bridge Targets).||Optional|No|
||36|GETMXDS, direct mod. (Get Max Data Speed).||Optional|Yes|
||37|GETHDRCAP, direct mode. (Get HDR capability).||Optional|Yes|
|~~aa~~<br>|38<br>~~aa~~<br>~~a~~|SETXTIME, direct mode. (Set Exchange Timinginformation).<br>~~aa~~<br>~~ee~~||||
|~~aa~~<br>~~a~~|~~aa~~<br>~~aa~~|38.1<br>~~aa~~<br>~~ee~~|Defining byte = 0x7F (ST)|Optional|Yes|
|~~a~~<br>~~ss~~|~~aa~~<br>~~ss~~|38.2<br>~~ee~~|Defining byte = 0xBF (DT)|Optional|Yes|
|~~ss~~|~~ss~~|38.3|Defining byte = 0xDF (Enter Async Mode 0)|Optional|Yes|
|||38.4|Defining byte = 0xEF (Enter Async Mode 1)|Optional|No|
|||38.5|Defining byte = 0xF7 (Enter Async Mode 2)|Optional|No|
|||38.6|Defining byte = 0xFB (Enter Async Mode 3)|Optional|No|
|~~a~~|~~a~~|38.7<br>~~ee~~|Defining byte = 0xFD (Async Trigger for Async<br>Mode 3).<br>~~eG~~|Optional<br>~~eG~~|No<br>~~eG~~|
|~~a~~|~~a~~|38.8<br>~~ee~~|Defining byte = 0x3F (TPH)<br>~~eG~~|Optional<br>~~eG~~|Yes<br>~~eG~~|
|~~a ~~<br>~~a~~|~~a~~<br>~~a~~|38.9<br>~~ee~~<br>~~ee~~|Defining byte = 0x9f (TU)<br>~~eG~~<br>~~ee~~|Optional<br>~~eG~~<br>~~ee~~|Yes<br>~~eG~~<br>~~ee~~|
|~~a ~~<br>~~a ~~|~~a~~<br> ~~a~~|38.10<br>~~ee~~<br>~~ee~~|Defining byte = 0x8F (ODR)<br>~~ee~~<br>~~ee~~|Optional<br>~~ee~~<br>~~ee~~|Yes<br>~~ee~~<br>~~ee~~|



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|39|GETXTIME, direct mode. (Get Exchange Timing<br>Information).|Optional|Yes|
|---|---|---|---|



**Table 13. I3C[SM] CCC Commands** 

## **10.3 I[2] C INTERFACE** 

I[2] C is a two-wire interface comprised of the signals serial data (SDA) and serial clock (SCL). In general, the lines are open-drain and bi-directional. In a generalized I[2] C interface implementation, attached devices can be a master or a slave. The master device puts the slave address on the bus, and the slave device with the matching address acknowledges the master. 

The ICM-45605 always operates as a slave device when communicating to the system processor, which thus acts as the master. SDA and SCL lines typically need pull-up resistors to VDDIO. The maximum bus speed is 1 MHz. 

The slave address of the ICM-45605 is b110100X, which is 7 bits long. The LSB bit of the 7-bit address is determined by the logic level on pin AP_AD0. This allows two ICM-45605s to be connected to the same I[2] C bus. When used in this configuration, the address of one of the devices should be b1101000 (pin AP_AD0 is logic low) and the address of the other should be b1101001 (pin AP_AD0 is logic high). 

## **10.4 I[2] C MASTER INTERFACE** 

I[2] C master is compliant with the I[2] C standard-Mode (max 100kbps), and I[2] C Fast-Mode (max 400kbps). It supports 8-bit I[2] C static address. It does not support multi-master on the I[2] C bus. Clock-stretching by external I[2] C devices is not supported. 

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## **10.5 SPI INTERFACE** 

The ICM-45605 supports 3-wire or 4-wire SPI for the host interface. The ICM-45605 always operates as a Slave device during standard Master-Slave SPI operation. 

With respect to the Master, the Serial Clock output (SCLK), the Serial Data Output (SDO), the Serial Data Input (SDI), and the Serial Data IO (SDIO) are shared among the Slave devices. Each SPI slave device requires its own Chip Select (CS) line from the master. 

CS goes low (active) at the start of transmission and goes back high (inactive) at the end. Only one CS line is active at a time, ensuring that only one slave is selected at any given time. The CS lines of the non-selected slave devices are held high, causing their SDO lines to remain in a high-impedance (high-z) state so that they do not interfere with any active devices. 

_SPI Operational Features_ 

1. Data is delivered MSB first and LSB last 

2. Data is latched on the rising edge of SCLK 

3. Data should be transitioned on the falling edge of SCLK 

4. The maximum frequency of SCLK is 24 MHz (it is 20MHz at VDDIO 1.2V) 

5. SPI read and write operations are completed in 16 or more clock cycles (two or more bytes). The first byte contains the Register Address, and the following byte(s) contain(s) the SPI data. The first bit of the first byte contains the Read/Write bit and indicates the Read (1) operation. The following 7 bits contain the Register Address. In cases of multiple-byte Reads, data is two or more bytes: 

**==> picture [194 x 96] intentionally omitted <==**

**----- Start of picture text -----**<br>
Register Address format<br>MSB  LSB<br>oe R/W  A6  A5  A4  A3  A2  A1  A0<br>SPI Data format<br>MSB  LSB<br>D7  D6  D5  D4  D3  D2  D1  D0<br>a<br>**----- End of picture text -----**<br>


## 6. Supports Single or Burst Read/Writes. 

**==> picture [190 x 119] intentionally omitted <==**

**----- Start of picture text -----**<br>
SCLK<br>SDIO<br>SPI Master SPI Slave 1<br>CS1 nCS<br>CS2<br>SCLK<br>SDIO<br>SPI Slave 2<br>nCS<br>**----- End of picture text -----**<br>


**Figure 11. Typical SPI Master/Slave Configuration** 

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## _**11 ASSEMBLY**_ 

This section provides general guidelines for assembling InvenSense Micro Electro-Mechanical Systems (MEMS) devices packaged in LGA package. 

## **11.1 ORIENTATION OF AXES** 

The diagram below shows the orientation of the axes of sensitivity and the polarity of rotation. Note the pin 1 identifier (•) in the figure. 

**==> picture [78 x 105] intentionally omitted <==**

**----- Start of picture text -----**<br>
+Z<br>+Z +Y<br>RY +Y<br>+X +X<br>**----- End of picture text -----**<br>


**Figure 12. Orientation of Axes of Sensitivity and Polarity of Rotation** 

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_**ICM-45605**_ 

## **11.2 PACKAGE DIMENSIONS** 

14 Lead LGA (2.5x3x0.81) mm NiAu pad finish 

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_**ICM-45605**_ 

|||**DIMENSIONS IN MILLIMETERS**|**DIMENSIONS IN MILLIMETERS**|**DIMENSIONS IN MILLIMETERS**|
|---|---|---|---|---|
|~~a~~<br>~~QO~~|**SYMBOLS**<br>~~QO~~|**MIN**<br>~~QO~~|**NOM**<br>~~QO~~|**MAX**<br>~~QO~~|
|**Total Thickness**<br>~~a~~<br>~~QO~~|**A**<br>~~QO~~|0.76<br>~~QO~~|0.81<br>~~QO~~|0.86<br>~~QO~~|
|**Substrate Thickness**<br>~~a~~<br>~~se~~|**A1**<br>~~se~~|0.105                       REF<br>~~se~~|||
|**Mold Thickness**<br>~~se~~<br>~~a~~|**A2**<br>~~se~~<br>~~es~~|0.7                        REF<br>~~se~~<br>~~eeseeee~~|||
|**Body Size**<br>~~a~~|**D**<br>~~es~~|~~ees~~|2.5<br>~~ee~~|BSC<br>~~ee~~|
||**E**<br>~~es~~|~~ees~~|3<br>~~ee~~|BSC<br>~~ee~~|
|**Lead Width**<br>~~a~~<br>~~a~~|**W**<br>~~es ~~<br>~~ee~~|0.2<br> ~~ees ~~<br>~~ee~~|0.25<br> ~~ee ~~|0.3<br> ~~ee~~|
|**Lead Length**<br>~~a~~<br>~~a~~|**L**<br>~~ee~~<br>~~a~~|0.425<br>~~ee~~|0.475|0.525|
|**Lead Pitch**<br>~~ee~~<br>~~a~~|**e**<br>~~ee~~<br>~~a~~|0.5                         BSC<br>~~ee~~|||
|**Lead Count**<br>~~ee~~<br>~~a~~<br>~~i~~|**n**<br>~~ee~~<br>~~a~~<br>~~cen~~|14<br>~~ee~~<br>~~eee~~|||
|**Edge Ball Center to Center**<br>~~a~~<br>~~i~~|**D1**<br>~~a~~<br>~~cen~~|1.5                         BSC<br>~~eee~~|||
||**E1**<br>~~a~~<br>~~cen~~<br>~~es~~|1                           BSC<br>~~eee~~|||
|**Body Center to Contact Ball**<br>~~i~~|**SD**<br>~~cen~~<br>~~es~~|0.25                        BSC<br>~~eee~~|||
||**SE**<br>~~cen~~<br>~~es~~|---                           BSC<br>~~eee~~|||
|**Package Edge Tolerance**<br>~~ee~~|**aaa**<br>~~es~~<br>~~ee~~|0.1<br>~~ee~~|||
|**Mold Flatness**<br>~~eT~~|**bbb**<br>~~eT~~|0.2<br>~~eT~~|||
|**Coplanarity**<br>~~eT~~|**ddd**<br>~~eT~~|0.08<br>~~eT~~|||



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_**ICM-45605**_ 

## _**12 DEVICE PACKAGE IN TAPE AND REEL**_ 

ICM-45605 devices are packaged in the tape and reel as shown in the figures below. 

**Figure 13. ICM-45605 Device Package in Tape and Reel** 

**Figure 14. Tape Dimensions with ICM-45605 Device Package** 

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_**ICM-45605**_ 

## _**13 PART NUMBER PACKAGE MARKING**_ 

The part number package marking for ICM-45605 devices is summarized below: 

**==> picture [470 x 216] intentionally omitted <==**

**----- Start of picture text -----**<br>
Part Number  Part Number Package Marking<br>ICM-45605  I4565<br>axe|<br>TOP VIEW<br>Part Number I4565<br>Lot Traceability Code X X X X X X<br>  YYWW<br>Y Y = Year Code<br>W W = Work Week<br>**----- End of picture text -----**<br>


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_**ICM-45605**_ 

## _**14 INDIRECT REGISTER ACCESS**_ 

## **14.1 HOST INDIRECT ACCESS REGISTER (IREG)** 

An IREG is a register or a memory storage element that is not addressed directly by a 7-bit address. IREGs can only be addressed using an internal 16-bit address. Indirect register access procedures described in this section must be used to access all IREGs. 

The host configures the internal 16-bit address by programming following registers: {ireg_addr_15_8[7:0], ireg_addr_7_0[7:0]}. 

## **14.2 GENERAL RULES FOR ACCESSING IREG** 

1. Burst-write and burst-read operations are not supported when accessing IREGs from the host. 

2. Reading of an IREG is done on a read-pre-fetch basis (details in IREG READ section below). 

3. A minimum wait time (refer to section MINIMUM WAIT TIME GAP below for details) is required between two consecutive read/write access to an IREG. 

## **14.3 MINIMUM WAIT TIME-GAP** 

The minimum time gap between two consecutive IREG accesses for various IREG components is 4µs. 

## **14.4 IREG WRITE** 

Procedure for writing to an IREG. 

1. The host specifies the destination address of an IREG by programming IREG_ADDR_7_0, IREG_ADDR_15_8. 

   - a. If host wants to access a register in IMEM_SRAM, it should add base address 0x0000 to the address of that register shown in the IMEM_SRAM registers section, and then use that resulting value in registers IREG_ADDR_7_0, IREG_ADDR_15_8. 

   - b. If host wants to access a register in IPREG_BAR, it should add base address 0xA000 to the address of that register shown in the IPREG_BAR registers section, and then use that resulting value in registers IREG_ADDR_7_0, IREG_ADDR_15_8. 

   - c. If host wants to access a register in IPREG_SYS1, it should add base address 0xA400 to the address of that register shown in the IPREG_SYS1 registers section, and then use that resulting value in registers IREG_ADDR_7_0, IREG_ADDR_15_8. 

   - d. If host wants to access a register in IPREG_SYS2, it should add base address 0xA500 to the address of that register shown in the IPREG_SYS2 registers section, and then use that resulting value in registers IREG_ADDR_7_0, IREG_ADDR_15_8. 

   - e. If host wants to access a register in IPREG_TOP1, it should add base address 0xA200 to the address of that register shown in the IPREG_TOP1 registers section, and then use that resulting value in registers IREG_ADDR_7_0, IREG_ADDR_15_8. 

2. The host programs the write data to the IREG_DATA register. 

3. The above programming steps must be performed in a single burst-write transaction to prevent an unintended read-pre-fetch operation. 

4. After the IREG_DATA register is written, an internal operation is triggered to pass the contents from the IREG_DATA register to a register pointed by {IREG_ADDR_7_0, IREG_ADDR_15_8}. 

5. After the contents from the IREG_DATA register is written to the selected register, the internal 16-bit address is auto-incremented. 

6. After a minimum wait time-gap, the host can write to the IREG_DATA register again, which is effectively writing to the register pointed by the post-auto-incremented address. 

7. Or, after a minimum wait time-gap, the host can program a new destination address for the next write operation. 

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_**ICM-45605**_ 

## **14.5 IREG READ** 

Procedure for reading from an IREG. 

1. The host specifies the destination address of an IREG by programming IREG_ADDR_7_0, IREG_ADDR_15_8. 

   - a. If host wants to access a register in IMEM_SRAM, it should add base address 0x0000 to the address of that register shown in the IMEM_SRAM registers section, and then use that resulting value in registers IREG_ADDR_7_0, IREG_ADDR_15_8. 

   - b. If host wants to access a register in IPREG_BAR, it should add base address 0xA000 to the address of that register shown in the IPREG_BAR registers section, and then use that resulting value in registers IREG_ADDR_7_0, IREG_ADDR_15_8. 

   - c. If host wants to access a register in IPREG_SYS1, it should add base address 0xA400 to the address of that register shown in the IPREG_SYS1 registers section, and then use that resulting value in registers IREG_ADDR_7_0, IREG_ADDR_15_8. 

   - d. If host wants to access a register in IPREG_SYS2, it should add base address 0xA500 to the address of that register shown in the IPREG_SYS2 registers section, and then use that resulting value in registers IREG_ADDR_7_0, IREG_ADDR_15_8. 

   - e. If host wants to access a register in IPREG_TOP1, it should add base address 0xA200 to the address of that register shown in the IPREG_TOP1 registers section, and then use that resulting value in registers IREG_ADDR_7_0, IREG_ADDR_15_8. 

2. Upon the CSB=1 (SPI) or STOP (I2C) after the above programming, an internal read-pre-fetch operation is triggered. 

3. The internal read-pre-fetch operation returns the desired data, which is saved to the IREG_DATA register. 

4. After a minimum wait time-gap, the host reads the IREG_DATA register to retrieve the read-data. 

5. After the host reads the IREG_DATA register, the internal 16-bit address is auto-incremented, and another internal read-pre-fetch is automatically triggered, to fetch data from the IREG register pointed to by the post-auto-incremented address. 

6. After a minimum wait time-gap, the host can either read the IREG_DATA register to get the read-data from the next address location, or it can program a new read address. 

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_**ICM-45605**_ 

## _**15 DEVICE CONFIGURATION FOR DATA ENDIANNESS**_ 

By default the device data endianness is Little Endian, for data in Sensor Data Registers and FIFO, and for FIFO Count. User must set register field SREG_DATA_ENDIAN_SEL in register SREG_CTRL to 1, to enable Big Endian data format for data in Sensor Data Registers and FIFO, and for FIFO Count. 

Data descriptions in the register map for Sensor Data Registers, FIFO data, and FIFO Count are for the commonly used Big Endian format. 

Page 55 of 191 

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_**ICM-45605**_ 

## _**16 REGISTER MAP**_ 

This section lists the register map for the ICM-45605, for user bank 0, IMEM_SRAM, IPREG_BAR, IPREG_TOP1, IPREG_SYS1, IPREG_SYS2. 

Please refer to the procedure in Section 14 for configuring device data endianness before using the register map. 

## **16.1 USER BANK 0 REGISTER MAP** 

|**Addr**<br>**(Hex)**|**Addr**<br>**(Dec.)**|**Register Name**|**Serial**<br>**I/F**|**Bit7**|**Bit6**|**Bit5**|**Bit4**|**Bit3**|**Bit2**|**Bit1**|**Bit0**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|00<br>~~eT~~|00<br>~~eT~~|ACCEL_DATA_X1_UI<br>~~eT~~|SYNCR<br>~~eT~~|ACCEL_DATA_X_UI[15:8]<br>~~eT~~||||||||
|01<br>~~eT~~|01<br>~~eT~~|ACCEL_DATA_X0_UI<br>~~eT~~|SYNCR<br>~~eT~~|ACCEL_DATA_X_UI[7:0]<br>~~eT~~||||||||
|02<br>~~ee~~|02<br>~~ee~~|ACCEL_DATA_Y1_UI<br>~~ee~~|SYNCR<br>~~ee~~|ACCEL_DATA_Y_UI[15:8]<br>~~ee~~||||||||
|03<br>~~ee~~|03<br>~~ee~~|ACCEL_DATA_Y0_UI<br>~~ee~~|SYNCR<br>~~ee~~|ACCEL_DATA_Y_UI[7:0]<br>~~ee~~||||||||
|04<br>~~eT~~|04<br>~~eT~~|ACCEL_DATA_Z1_UI<br>~~eT~~|SYNCR<br>~~eT~~|ACCEL_DATA_Z_UI[15:8]<br>~~eT~~||||||||
|05<br>~~eT~~|05<br>~~eT~~|ACCEL_DATA_Z0_UI<br>~~eT~~|SYNCR<br>~~eT~~|ACCEL_DATA_Z_UI[7:0]<br>~~eT~~||||||||
|06<br>~~I~~|06<br>~~I~~|GYRO_DATA_X1_UI<br>~~I~~|SYNCR<br>~~I~~|GYRO _DATA_X_UI[15:8]<br>~~I~~||||||||
|07<br>~~I~~|07<br>~~I~~|GYRO _DATA_X0_UI<br>~~I~~|SYNCR<br>~~I~~|GYRO _DATA_X_UI[7:0]<br>~~I~~||||||||
|08<br>~~I~~|08<br>~~I~~|GYRO _DATA_Y1_UI<br>~~I~~|SYNCR<br>~~I~~|GYRO _DATA_Y_UI[15:8]<br>~~I~~||||||||
|09<br>~~I~~|09<br>~~I~~|GYRO _DATA_Y0_UI<br>~~I~~|SYNCR<br>~~I~~|GYRO _DATA_Y_UI[7:0]<br>~~I~~||||||||
|0A<br>~~I~~|10<br>~~I~~|GYRO _DATA_Z1_UI<br>~~I~~|SYNCR<br>~~I~~|GYRO_DATA_Z_UI[15:8]<br>~~I~~||||||||
|0B<br>~~I~~|11<br>~~I~~|GYRO _DATA_Z0_UI<br>~~I~~|SYNCR<br>~~I~~|GYRO_DATA_Z_UI[7:0]<br>~~I~~||||||||
|0C<br>~~ee~~|12<br>~~ee~~|TEMP_DATA1_UI<br>~~ee~~|SYNCR<br>~~ee~~|TEMP_DATA_UI[15:8]<br>~~ee~~||||||||
|0D<br>~~ee~~|13<br>~~ee~~|TEMP_DATA0_UI<br>~~ee~~|SYNCR<br>~~ee~~|TEMP_DATA_UI[7:0]<br>~~ee~~||||||||
|0E<br>~~ee~~<br>~~eT~~|14<br>~~ee~~<br>~~eT~~|TMST_FSYNCH<br>~~ee~~<br>~~eT~~|SYNCR<br>~~ee~~<br>~~eT~~|TMST_FSYNC_DATA_UI[15:8]<br>~~ee~~<br>~~eT~~||||||||
|0F<br>~~eT~~|15<br>~~eT~~|TMST_FSYNCL<br>~~eT~~|SYNCR<br>~~eT~~|TMST_FSYNC_DATA_UI[7:0]<br>~~eT~~||||||||
|10<br>~~eT~~<br>~~ee~~|16<br>~~eT~~<br>~~ee~~|PWR_MGMT0<br>~~eT~~<br>~~ee~~|R/W<br>~~eT~~<br>~~ee~~|-<br>~~eT~~<br>~~ee~~||||GYRO_MODE<br>~~eT~~<br>~~ee~~||ACCEL_MODE<br>~~eT~~<br>~~ee~~||
|12<br>~~ee~~|18<br>~~ee~~|FIFO_COUNT_0<br>~~ee~~|R<br>~~ee~~|FIFO_DATA_CNT[15:8]<br>~~ee~~||||||||
|13<br>~~ee~~<br>~~eT~~|19<br>~~ee~~<br>~~eT~~|FIFO_COUNT_1<br>~~ee~~<br>~~eT~~|R<br>~~ee~~<br>~~eT~~|FIFO_DATA_CNT[7:0]<br>~~ee~~<br>~~eT~~||||||||
|14<br>~~eT~~|20<br>~~eT~~|FIFO_DATA<br>~~eT~~|R<br>~~eT~~|FIFO_DATA<br>~~eT~~||||||||
|16<br>~~eT~~<br>~~re~~<br>~~ee~~|22<br>~~eT~~<br>~~re~~<br>~~ee~~|INT1_CONFIG0<br>~~eT~~<br>~~re~~<br>~~ee~~|R/W<br>~~eT~~<br>~~eee~~<br>~~eee~~|INT1_STATUS<br>_EN_RESET_<br>DONE<br>~~eT~~<br>~~eee~~<br>~~eee~~|INT1_STATUS<br>_EN_AUX1_A<br>GC_RDY<br>~~eT~~<br>~~eee~~<br>~~eee~~|INT1_STATUS<br>_EN_AP_AGC<br>_RDY<br>~~eT~~<br>~~eee~~<br>~~eee~~|INT1_STATUS<br>_EN_AP_FSY<br>NC<br>~~eT~~<br>~~eee~~<br>~~eee~~|INT1_STATUS<br>_EN_AUX1_D<br>RDY<br>~~eT~~<br>~~eee~~<br>~~eee~~|INT1_STATUS<br>_EN_DRDY<br>~~eT~~<br>~~eee~~<br>~~eee~~|INT1_STATUS<br>_EN_FIFO_TH<br>S<br>~~eT~~<br>~~eee~~<br>~~eee~~|INT1_STATUS<br>_EN_FIFO_FU<br>LL<br>~~eT~~<br>~~eee~~<br>~~eee~~|
|17<br>~~ee~~|23<br>~~ee~~|INT1_CONFIG1<br>~~ee~~|R/W<br>~~eee~~|-<br>~~eee~~|INT1_STATUS<br>_EN_APEX_E<br>VENT<br>~~eee~~|INT1_STATUS<br>_EN_I2CM_D<br>ONE<br>~~eee~~|INT1_STATUS<br>_EN_I3C_PR<br>OTOCOL_ERR<br>~~eee~~|INT1_STATUS<br>_EN_WOM_Z<br>~~eee~~|INT1_STATUS<br>_EN_WOM_Y<br>~~eee~~|INT1_STATUS<br>_EN_WOM_X<br>~~eee~~|INT1_STATUS<br>_EN_PLL_RD<br>Y<br>~~eee~~|
|18<br>~~ee~~<br>~~a~~<br>~~pf~~|24<br>~~ee~~<br>~~a~~<br>~~pf pt~~|INT1_CONFIG2<br>~~ee~~<br>~~pt~~|R/W<br>~~eee~~<br>~~pt~~|-<br>~~eee~~|||||INT1_DRIVE<br>~~eee~~|INT1_MODE<br>~~eee~~|INT1_POLARI<br>TY<br>~~eee~~|
|19<br>~~a~~<br>~~pf~~<br>~~ee~~|25<br>~~a~~<br>~~pf pt~~<br>~~ee~~|INT1_STATUS0<br>~~pt~~<br>~~ee~~|R/C<br>~~pt~~<br>~~eee~~|INT1_STATUS<br>_RESET_DON<br>E<br>~~eee~~|INT1_STATUS<br>_AUX1_AGC_<br>RDY<br>~~eee~~|INT1_STATUS<br>_AP_AGC_RD<br>Y<br>~~eee~~|INT1_STATUS<br>_AP_FSYNC<br>~~eee~~|INT1_STATUS<br>_AUX1_DRDY<br>~~eee~~|INT1_STATUS<br>_DRDY<br>~~eee~~|INT1_STATUS<br>_FIFO_THS<br>~~eee~~|INT1_STATUS<br>_FIFO_FULL<br>~~eee~~|
|1A<br>~~pf~~<br>~~ee~~|26<br>~~pf pt~~<br>~~ee~~|INT1_STATUS1<br>~~pt~~<br>~~ee~~|R/C<br>~~pt~~<br>~~eee~~|-<br>~~eee~~|INT1_STATUS<br>_APEX_EVEN<br>T<br>~~eee~~|INT1_STATUS<br>_I2CM_DONE<br>~~eee~~|INT1_STATUS<br>_I3C_PROTO<br>COL_ERR<br>~~eee~~|INT1_STATUS<br>_WOM_Z<br>~~eee~~|INT1_STATUS<br>_WOM_Y<br>~~eee~~|INT1_STATUS<br>_WOM_X<br>~~eee~~|INT1_STATUS<br>_PLL_RDY<br>~~eee~~|
|1B<br>~~ee~~<br>~~a~~|27<br>~~ee~~<br>~~a~~|ACCEL_CONFIG0<br>~~ee~~<br>|R/W<br>~~eee~~<br>|-<br>~~eee~~<br>|ACCEL_UI_FS_SEL<br>~~eee~~<br>|||ACCEL_ODR<br>~~eee~~<br>||||
|1C<br>~~en~~|28<br>~~en~~|GYRO_CONFIG0<br>~~en~~|R/W<br>~~en~~|GYRO_UI_FS_SEL<br>~~en~~||||GYRO_ODR<br>~~en~~||||
|1D<br>~~en~~|29<br>~~en~~|FIFO_CONFIG0<br>~~en~~|R/W<br>~~en~~|FIFO_MODE<br>~~en~~||FIFO_DEPTH<br>~~en~~||||||
|1E<br>~~eT~~|30<br>~~eT~~|FIFO_CONFIG1_0<br>~~eT~~|R/W<br>~~eT~~|FIFO_WM_TH[7:0]<br>~~eT~~||||||||
|1F<br>~~eT~~|31<br>~~eT~~|FIFO_CONFIG1_1<br>~~eT~~|R/W<br>~~eT~~|FIFO_WM_TH[15:8]<br>~~eT~~||||||||
|20<br>~~a~~<br>~~a~~|32<br>~~a~~<br>~~a~~|FIFO_CONFIG2<br>~~ee~~<br>~~a~~|R/W<br>~~ee~~|FIFO_FLUSH<br>~~ee~~|-<br>~~ee~~|||FIFO_WR_W<br>M_GT_TH<br>~~ee~~<br>~~ee~~|-<br>~~ee~~<br>~~ee~~|||
|21<br>~~ee~~<br>~~a~~|33<br>~~ee~~<br>~~a~~|FIFO_CONFIG3<br>~~ee~~<br>~~a~~|R/W<br>~~ee~~|-<br>~~ee~~||FIFO_ES1_EN<br>~~ee~~|FIFO_ES0_EN<br>~~ee~~|FIFO_HIRES_<br>EN<br>~~ee~~<br>~~ee~~|FIFO_GYRO_<br>EN<br>~~ee~~<br>~~ee~~|FIFO_ACCEL_<br>EN<br>~~ee~~|FIFO_IF_EN<br>~~ee~~|
|22<br>~~ee~~<br>~~a~~|34<br>~~ee~~<br>~~a~~|FIFO_CONFIG4<br>~~ee~~<br>~~a~~|R/W<br>~~ee~~|-<br>~~ee~~||FIFO_COMP_NC_FLOW_CFG<br>~~ee~~<br>~~ee~~|||FIFO_COMP_<br>EN<br>~~ee~~<br>~~ee~~|FIFO_TMST_F<br>SYNC_EN<br>~~ee~~|FIFO_ES0_6B<br>_9B<br>~~ee~~|
|23<br>~~a~~<br>~~a~~|35<br>~~a~~<br>~~a~~|TMST_WOM_CONFIG<br>~~a~~|R/W|-|TMST_DELTA<br>_EN|TMST_RESOL|WOM_EN|WOM_MODE<br>~~ee~~|WOM_INT_<br>MODE<br>~~ee~~|WOM_INT_DUR||



Page 56 of 191 

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_**ICM-45605**_ 

|**Addr**<br>**(Hex)**<br>||**Addr**<br>**(Dec.)**<br>|**Register Name**<br>|**Serial**<br>**I/F**<br>|**Bit7**<br>|**Bit6**<br>|**Bit5**<br>|**Bit4**<br>|**Bit3**<br>|**Bit2**<br>|**Bit1**<br>|**Bit0**<br>|
|---|---|---|---|---|---|---|---|---|---|---|---|
|24<br>~~ee~~<br>~~a~~|36<br>~~ee~~<br>~~a~~|FSYNC_CONFIG0<br>~~ee~~<br>~~ee~~|R/W<br>~~ee~~<br>~~ee~~|-<br>~~ee~~<br>~~ee~~<br>~~esee~~||||AP_FSYNC_FL<br>AG_CLEAR_S<br>EL<br>~~ee~~|AP_FSYNC_SEL<br>~~ee~~|||
|27<br>~~a~~|39<br>~~a~~|DMP_EXT_SEN_ODR_CFG<br>~~ee~~|R/W<br>~~ee~~|-<br>~~ee~~|EXT_SENSOR<br>_EN<br>~~es~~<br>~~ee~~|EXT_ODR<br>~~ee~~<br>~~ee~~|||APEX_ODR|||
|28<br>~~a~~<br>~~a~~|40<br>~~a~~<br>~~a~~|ODR_DECIMATE_CONFIG<br>~~ee ~~<br>~~a~~|R/W<br> ~~ee ~~<br>~~a~~|GYRO_FIFO_ODR_DEC<br> ~~ee~~<br>~~esee~~<br>~~a~~<br>~~ee~~||||ACCEL_FIFO_ODR_DEC<br>~~a~~||||
|29<br>~~a~~|41<br>~~a~~|EDMP_APEX_EN0<br>~~a~~|R/W<br>~~a~~|SMD_EN<br>~~a~~|R2W_EN<br>~~a~~<br>~~ee~~|FF_EN<br>~~a~~<br>~~ee~~|PEDO_EN<br>~~a~~|TILT_EN<br>~~a~~|-<br>~~a~~||TAP_EN<br>~~a~~|
|2A<br>~~eee~~<br>~~a~~|42<br>~~eee~~<br>~~es~~|EDMP_APEX_EN1<br>~~eee~~<br>~~es ns~~|R/W<br>~~eee~~<br>~~ns~~|-<br>~~eee~~|EDMP_ENAB<br>LE<br>~~ee~~<br>~~eee~~|FEATURE3_E<br>N<br>~~ee~~<br>~~eee~~|-<br>~~eee~~<br>~~(~~||POWER_SAV<br>E_EN<br>~~eee~~|INIT_EN<br>~~eee~~|SOFT_HARD_<br>IRON_CORR_<br>EN<br>~~eee~~|
|2B<br>~~a~~<br>~~ee~~|43<br>~~es~~|APEX_BUFFER_MGMT<br>~~es ns~~<br>~~re~~|R/W<br>~~ns~~<br>~~ee~~|FF_DURATION_HOST_RPTR<br>~~ee~~||FF_DURATION_EDMP_WPTR<br>~~ee~~||STEP_COUNT_HOST_RPTR<br>~~(~~<br>~~ee~~||STEP_COUNT_EDMP_WPTR<br>~~ee~~||
|2C<br>~~a~~<br>~~ee~~<br>~~a~~|44<br>~~es ~~<br>|INTF_CONFIG0<br> ~~es ns~~<br>~~re~~<br>|R/W<br>~~ns~~<br>~~ee~~<br>|-<br>~~(~~<br>~~ee~~<br>~~ee~~||||||AP_SPI_34_<br>MODE<br>~~ee~~<br>~~ee~~|AP_SPI_MOD<br>E<br>~~ee~~|
|2D<br>~~ee~~<br>~~a~~<br>~~a~~<br>~~ee~~|45<br>~~a~~<br>~~e~~<br>|INTF_CONFIG1_OVRD<br>~~re ~~<br>~~ee~~<br>~~e~~~~**e**~~|R/W<br> ~~ee~~<br>~~ee~~<br>~~re~~|-<br>~~ee~~<br>~~ee~~||||AP_SPI_34_<br>MODE_OVRD<br>~~ee~~<br>~~ee~~<br>~~ee~~|AP_SPI_34_<br>MODE_OVRD<br>_VAL<br>~~ee~~<br>~~ee~~<br>~~ee~~|AP_SPI_MOD<br>E_OVRD<br>~~ee~~<br>~~ee~~<br>~~ee~~|AP_SPI_MOD<br>E_OVRD_VAL<br>~~ee~~<br>~~ee~~|
|2F<br>~~a~~<br>~~ee~~|47<br>~~e~~<br>~~a~~|IOC_PAD_SCENARIO<br>~~e~~~~**e**~~<br>~~e~~|R<br>~~re~~<br>~~ee es~~|-<br>~~ee~~<br>~~es~~|||||AUX1_MODE<br>~~eeee~~||AUX1_ENABL<br>E|
|30<br>~~a ~~<br>~~ee~~|48<br> ~~e~~<br>~~a~~|IOC_PAD_SCENARIO_AUX_O<br>VRD<br>~~e~~~~**e**~~<br>~~e~~|R/W<br>~~re~~<br>~~ee es~~|-<br>~~es~~|||AUX1_MODE<br>_OVRD|AUX1_ENABLE_OVRD_VAL<br>~~ee ~~||AUX1_ENABL<br>E_OVRD<br> ~~ee~~|AUX1_ENABL<br>E_OVRD_VAL|
|32<br> <br>~~ee ~~|50<br> ~~e~~<br> ~~a~~|DRIVE_CONFIG0<br>~~e~~~~**e** ~~<br>~~e ~~|R/W<br> ~~re~~<br> ~~ee es~~|-<br>~~es~~|PADS_I2C_SLEW<br>~~es~~|||PADS_SPI_SLEW|||-|
|33<br>~~-FAP~~|51<br>~~-FAP~~|DRIVE_CONFIG1<br>~~-FAP~~|R/W<br>|-<br>||PADS_I3C_DDR_SLEW<br>|||PADS_I3C_SDR_SLEW<br>|||
|34<br>~~-FAP~~|52<br>~~-FAP~~|DRIVE_CONFIG2<br>~~-FAPFAP~~|R/W<br>~~FAP~~|-<br>~~FAP~~|||||PADS_SLEW<br>~~FAP~~|||
|35<br>~~-FAP~~|53<br>~~-FAP~~|REG_MISC1<br>~~-FAPFAP~~|R/W<br>~~FAP~~|-<br>~~FAP~~||||OSC_ID_OVRD<br>~~FAP~~||||
|39<br>~~-FAP~~|57<br>~~-FAP~~|INT_APEX_CONFIG0<br>~~-FAPFAP~~|R/W<br>~~FAP~~|INT_STATUS_<br>MASK_PIN_R<br>2W_WAKE_D<br>ET<br>~~FAP~~|INT_STATUS_<br>MASK_PIN_F<br>F_DET<br>~~FAP~~|INT_STATUS_<br>MASK_PIN_S<br>TEP_DET<br>~~FAP~~|INT_STATUS_<br>MASK_PIN_S<br>TEP_CNT_OV<br>FL<br>~~FAP~~|INT_STATUS_<br>MASK_PIN_TI<br>LT_DET<br>~~FAP~~|INT_STATUS_<br>MASK_PIN_L<br>OW_G_DET<br>~~FAP~~|INT_STATUS_<br>MASK_PIN_H<br>IGH_G_DET<br>~~FAP~~|INT_STATUS_<br>MASK_PIN_T<br>AP_DET<br>~~FAP~~|
|3A<br>~~-FAP~~|58<br>~~-FAP~~|INT_APEX_CONFIG1<br>~~-FAPFAP~~|R/W<br>~~FAP~~|-<br>~~FAP~~|||INT_STATUS_<br>MASK_PIN_S<br>A_DONE<br>~~FAP~~|-<br>~~FAP~~|INT_STATUS_<br>MASK_PIN_S<br>ELFTEST_DO<br>NE<br>~~FAP~~|INT_STATUS_<br>MASK_PIN_S<br>MD_DET<br>~~FAP~~|INT_STATUS_<br>MASK_PIN_R<br>2W_SLEEP_D<br>ET<br>~~FAP~~|
|3B<br>~~a~~<br>~~ee~~|59<br>~~ee~~|INT_APEX_STATUS0<br>~~ee~~|R/C<br>~~ee~~<br>~~ee~~|INT_STATUS_<br>R2W_WAKE_<br>DET<br>~~ee~~<br>|INT_STATUS_<br>FF_DET<br>~~ee~~<br>|INT_STATUS_<br>STEP_DET<br>~~ee~~<br>|INT_STATUS_<br>STEP_CNT_O<br>VFL<br>~~ee~~|INT_STATUS_<br>TILT_DET<br>~~eee~~|INT_STATUS_<br>LOW_G_DET<br>~~eee~~|INT_STATUS_<br>HIGH_G_DET<br>~~eee~~|INT_STATUS_<br>TAP_DET<br>~~eee~~|
|3C<br>~~ee~~<br>~~ee~~|60<br>~~ee~~<br>~~ee~~|INT_APEX_STATUS1<br>~~ee~~<br>~~ee~~|R/C<br>~~ee~~<br>~~ee~~|-<br>~~ee~~<br>|||INT_STATUS_<br>SA_DONE<br>~~ee~~<br>~~ee~~|-<br>~~ee~~|INT_STATUS_<br>SELFTEST_DO<br>NE<br>~~ee~~|INT_STATUS_<br>SMD_DET<br>~~ee~~|INT_STATUS_<br>R2W_SLEEP_<br>DET<br>~~ee~~|
|56<br>~~ee~~<br>~~ee~~<br>~~a~~|86<br>~~ee~~<br>~~ee~~<br>~~a~~|INT2_CONFIG0<br>~~ee~~<br>~~ee~~<br>|R/W<br>~~ee~~<br>~~ee ~~<br>~~ee~~<br>|INT2_STATUS<br>_EN_RESET_<br>DONE<br>~~ee~~<br> ~~ee~~<br>~~ee~~|INT2_STATUS<br>_EN_AUX1_A<br>GC_RDY<br>~~ee~~<br>~~ee~~<br>~~ee~~|INT2_STATUS<br>_EN_AP_AGC<br>_RDY<br>~~ee~~<br>~~ee~~<br>~~ee~~|INT2_STATUS<br>_EN_AP_FSY<br>NC<br>~~ee~~<br>~~ee~~<br>~~ee~~|INT2_STATUS<br>_EN_AUX1_D<br>RDY<br>~~ee~~<br>~~eee~~<br>~~ee~~|INT2_STATUS<br>_EN_DRDY<br>~~ee~~<br>~~eee~~|INT2_STATUS<br>_EN_FIFO_TH<br>S<br>~~ee~~<br>~~eee~~<br>~~ee~~|INT2_STATUS<br>_EN_FIFO_FU<br>LL<br>~~ee~~<br>~~eee~~<br>~~ee~~|
|57<br>~~ee~~<br>~~a~~<br>~~a~~|87<br>~~ee~~<br>~~a~~<br>~~a~~|INT2_CONFIG1<br>~~ee~~<br>~~ae~~<br>|R/W<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|-<br>~~ee~~<br>~~ee~~<br>|INT2_STATUS<br>_EN_APEX_E<br>VENT<br>~~ee~~<br>~~ee~~<br>|INT2_STATUS<br>_EN_I2CM_D<br>ONE<br>~~ee~~<br>~~ee~~<br>~~ts~~<br>|INT2_STATUS<br>_EN_I3C_PR<br>OTOCOL_ERR<br>~~ee~~<br>~~ee~~<br>~~ts~~<br>|INT2_STATUS<br>_EN_WOM_Z<br>~~ee~~<br>~~ee~~<br>~~ts~~<br>|INT2_STATUS<br>_EN_WOM_Y<br>~~ee~~<br>~~tn~~<br>|INT2_STATUS<br>_EN_WOM_X<br>~~ee~~<br>~~ee~~<br>~~es~~<br>|INT2_STATUS<br>_EN_PLL_RD<br>Y<br>~~ee~~<br>~~ee~~<br>|
|58<br>~~a~~<br>~~a~~|88<br>~~a ~~<br>~~a~~|INT2_CONFIG2<br> ~~ae~~<br>|R/W<br>~~ee~~<br>~~ee~~<br>|-<br>~~ee ee ee~~<br>~~ts~~<br><br>~~eeee~~|||||INT2_DRIVE<br>~~tn~~<br><br>~~ee~~|INT2_MODE<br>~~ee~~<br>~~es~~<br><br>~~ee~~|INT2_POLARI<br>TY<br>~~ee~~<br><br>~~ee~~|
|59<br><br>~~a~~<br>~~a~~|89<br> <br>~~a~~|INT2_STATUS0<br> ~~ae~~<br>~~ee~~|R/C<br>~~ee~~<br>~~ee~~|INT2_STATUS<br>_RESET_DON<br>E<br>~~ee~~|INT2_STATUS<br>_AUX1_AGC_<br>RDY<br>~~ee~~|INT2_STATUS<br>_AP_AGC_RD<br>Y<br>~~ts~~<br>~~ee~~|INT2_STATUS<br>_AP_FSYNC<br>~~ts~~<br>~~ee~~<br>~~ee~~|INT2_STATUS<br>_AUX1_DRDY<br>~~ts~~<br>~~ee~~<br>~~ee~~|INT2_STATUS<br>_DRDY<br>~~tn~~<br>~~ee~~<br>~~ee~~<br>~~eee~~|INT2_STATUS<br>_FIFO_THS<br>~~es~~<br>~~ee~~<br>~~ee~~<br>~~eee~~|INT2_STATUS<br>_FIFO_FULL<br>~~ee~~<br>~~ee~~<br>~~eee~~|
|5A<br><br>~~a~~<br>~~ee~~<br>~~a~~|90<br> <br>~~a~~<br>~~ee~~<br>~~es~~|INT2_STATUS1<br> ~~ae ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|R/C<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~rs~~|-<br>~~ee~~<br>~~ee~~|INT1_STATUS<br>_APEX_EVEN<br>T<br>~~ee~~<br>~~ee~~|INT1_STATUS<br>_I2CM_DONE<br>~~ts~~<br>~~ee~~<br>~~ee~~|INT1_STATUS<br>_I3C_PROTO<br>COL_ERR<br>~~ts~~<br>~~ee~~<br>~~ee ~~<br>~~ee~~|INT1_STATUS<br>_WOM_Z<br>~~ts ~~<br>~~ee~~<br> ~~ee~~<br>~~ee~~|INT1_STATUS<br>_WOM_Y<br> ~~tn ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~eee~~|INT1_STATUS<br>_WOM_X<br> ~~es~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~eee~~|INT1_STATUS<br>_PLL_RDY<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~eee~~|
|72<br>~~a~~<br>~~a~~|114<br>~~es~~<br>~~a~~|WHO_AM_I<br>~~ee~~<br>~~ae~~|R<br>~~rs~~<br>~~ee~~|WHOAMI<br>~~eee~~<br>~~ee es ee~~||||||||
|73<br>~~a~~<br>~~a~~|115<br>~~es ~~<br>~~a~~|REG_HOST_MSG<br> ~~ee~~<br>~~ae~~|R/W<br>~~rs~~<br>~~ee~~|-<br>~~ee es~~||EDMP_ON_D<br>EMAND_EN<br>~~es ee~~|-<br>~~eee~~<br>~~ee~~<br>~~—~~||||TESTOPENAB<br>LE<br>~~eee~~<br>~~—~~|
|7C<br>~~a~~<br>~~OL~~|124<br>~~a ~~<br>~~OL~~|IREG_ADDR_15_8<br> ~~ae ~~<br>~~OL~~|R/W<br> ~~ee ~~<br>~~OL~~|IREG_ADDR_15_8<br> ~~ee es ee~~<br>~~OL~~<br>~~—~~||||||||
|7D<br>~~OL~~|125<br>~~OL~~|IREG_ADDR_7_0<br>~~OL~~|R/W<br>~~OL~~|IREG_ADDR_7_0<br>~~OL~~<br>~~—~~||||||||
|7E<br>~~OL~~<br>~~Cn~~|126<br>~~OL~~<br>~~Cn~~|IREG_DATA<br>~~OL~~<br>~~Cn~~|R/W<br>~~OL~~<br>~~Cn~~|IREG_DATA<br>~~OL~~<br>~~—~~<br>~~Cn~~||||||||
|7F<br>~~Cn~~|127<br>~~Cn~~|REG_MISC2<br>~~Cn~~|R/W<br>~~Cn~~|-<br>~~Cn~~||||||SOFT_RST<br>~~Cn~~|IREG_DONE<br>~~Cn~~|



Page 57 of 191 

Document Number: DS-000576 Revision: 1.0 

_**ICM-45605**_ 

## **16.2 USER BANK IMEM_SRAM REGISTER MAP** 

|**Addr**<br>**(Hex)**<br>~~||~~|**Addr**<br>**(Dec.)**<br>~~||~~|**Register Name**|**Serial**<br>**I/F**|**Bit7**|**Bit6**|**Bit5**|**Bit4**|**Bit3**|**Bit2**|**Bit1**|**Bit0**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|00<br>~~a ~~<br>~~a~~|00<br> ~~a~~|IMEM_SRAM_REG_0<br>~~es~~|R/W<br>~~rs~~|GYRO_X_STR_FT[7:0]||||||||
|01<br> <br>~~a~~<br>~~a~~|01<br> ~~a~~<br>~~ss~~|IMEM_SRAM_REG_1<br>~~es ~~<br>~~ss~~<br>~~ss es~~|R/W<br> ~~rs~~<br>~~ss~~<br>~~es~~|GYRO_X_STR_FT[15:8]||||||||
|02<br>~~a~~|02<br>~~ss~~|IMEM_SRAM_REG_2<br>~~ss es~~|R/W<br>~~es~~|GYRO_Y_STR_FT[7:0]||||||||
|03<br>~~a ~~<br>~~a~~<br>~~a~~|03<br> ~~ss~~<br>~~ss~~|IMEM_SRAM_REG_3<br>~~ss es~~<br>~~ss~~<br>~~ss es~~|R/W<br>~~es~~<br>~~ss~~<br>~~es~~|GYRO_Y_STR_FT[15:8]||||||||
|04<br>~~a~~|04<br>~~ss~~|IMEM_SRAM_REG_4<br>~~ss es~~|R/W<br>~~es~~|GYRO_Z_STR_FT[7:0]||||||||
|05<br>~~a ~~<br>~~a~~<br>~~a~~|05<br> ~~ss~~<br>~~ss~~|IMEM_SRAM_REG_5<br>~~ss es~~<br>~~ss~~<br>~~ss es~~|R/W<br>~~es~~<br>~~ss~~<br>~~es~~|GYRO_Z_STR_FT[15:8]||||||||
|06<br>~~a~~|06<br>~~ss~~|IMEM_SRAM_REG_6<br>~~ss es~~|R/W<br>~~es~~|GYRO_X_CMOS_GAIN_FT[7:0]||||||||
|07<br>~~a ~~<br>~~a~~<br>~~a~~|07<br> ~~ss~~<br>~~ss~~|IMEM_SRAM_REG_7<br>~~ss es~~<br>~~ss~~<br>~~ss es~~|R/W<br>~~es~~<br>~~ss~~<br>~~es~~|-||||GYRO_X_CMOS_GAIN_FT[11:8]||||
|08<br>~~a~~|08<br>~~ss~~|IMEM_SRAM_REG_8<br>~~ss es~~|R/W<br>~~es~~|GYRO_Y_CMOS_GAIN_FT[7:0]||||||||
|09<br>~~a ~~<br>~~a~~<br>~~a~~|09<br> ~~ss~~<br>~~a~~|IMEM_SRAM_REG_9<br>~~ss es~~<br>~~ss~~<br>~~es rs~~|R/W<br>~~es~~<br>~~ss~~<br>~~rs~~|-||||GYRO_Y_CMOS_GAIN_FT[11:8]||||
|0A<br>~~a~~<br>~~a~~|10<br>~~a~~<br>~~a~~|IMEM_SRAM_REG_10<br>~~es rs~~<br>~~ee~~|R/W<br>~~rs~~<br>~~eG~~|GYRO_Z_CMOS_GAIN_FT[7:0]<br>~~eG~~||||||||
|0B<br>~~a~~<br>~~a~~<br>~~ee~~|11<br>~~a~~<br>~~a~~<br>~~ee~~|IMEM_SRAM_REG_11<br>~~es rs~~<br>~~ee~~<br>~~ee~~|R/W<br>~~rs~~<br>~~eG~~|-<br>~~eG~~||||GYRO_Z_CMOS_GAIN_FT[11:8]||||
|38<br>~~a ~~<br>~~ee~~<br>~~a~~|56<br> ~~a~~<br>~~ee~~<br>|IMEM_SRAM_REG_56<br>~~ee ~~<br>~~ee~~<br>|R/W<br> ~~eG~~<br>~~es~~<br>|ST_AVG_TIM<br>E[0]<br>~~eG~~<br>|-<br>~~eG~~<br>||||ST_GYRO_EN<br>|ST_ACCEL_E<br>N<br>|STC_INIT_EN<br>|
|39<br>~~ee~~<br>~~es~~<br>~~a~~<br>~~a~~|57<br>~~ee~~<br>~~es~~<br>~~a~~|IMEM_SRAM_REG_57<br>~~ee~~<br>~~es~~<br>~~ee~~|R/W<br>~~es~~<br>~~es~~<br>~~eG~~|ST_GYRO_LIMIT<br>~~es~~<br>~~eG~~|||ST_ACCEL_LIMIT<br>~~es~~<br>~~eG~~|||ST_AVG_TIME[2:1]<br>~~es~~<br>~~eG~~||
|40<br>~~a~~<br>~~a~~<br>~~a~~|64<br>~~a~~<br>|IMEM_SRAM_REG_64<br>~~ee~~<br>~~es~~<br>|R/W<br>~~es~~<br>~~eG~~<br>~~rs~~<br>|ST_DEBUG_EN<br>~~eG~~<br>~~eG~~<br>||||||||
|44<br>~~a ~~<br>~~a~~<br>~~a~~<br>~~a~~|68<br> ~~a ~~<br>~~a~~|IMEM_SRAM_REG_68<br> ~~ee~~<br>~~es~~<br>~~ee~~|R<br>~~es~~<br>~~eG~~<br>~~rs~~<br>~~eG~~|ST_STATUS<br>~~eG~~<br>~~eG~~<br>~~eG~~||GZ_ST_PASS<br>~~eG~~<br>~~eG~~<br>~~eG~~|GY_ST_PASS<br>~~eG~~<br>~~eG~~<br>~~eG~~|GX_ST_PASS<br>~~eG~~<br>~~eG~~<br>~~eG~~|AZ_ST_PASS<br>~~eG~~<br>~~eG~~<br>~~eG~~|AY_ST_PASS<br>~~eG~~<br>~~eG~~<br>~~eG~~|AX_ST_PASS<br>~~eG~~<br>~~eG~~<br>~~eG~~|
|5C<br>~~a~~<br>~~a~~|92<br>~~a~~|IMEM_SRAM_REG_92<br>~~es~~<br>~~ee~~|R/W<br>~~rs~~<br>~~eG~~|QUAT_RESET_EN<br>~~eG~~<br>~~eG~~||||||||
|60<br>~~a ~~<br>~~a~~|96<br> ~~a ~~|IMEM_SRAM_REG_96<br>~~es~~<br> ~~ee~~<br>~~ss~~|R/W<br>~~rs~~<br>~~eG~~<br>~~ss~~|STC_GAIN_GX[7:0]<br>~~eG~~<br>~~eG~~||||||||
|61<br>~~a~~|97<br>~~a~~|IMEM_SRAM_REG_97<br>~~ee~~|R/W<br>~~ee~~|STC_GAIN_GX[15:8]||||||||
|62<br>~~a ~~<br>~~a~~|98<br> ~~a~~|IMEM_SRAM_REG_98<br>~~ee~~<br>~~ss~~|R/W<br>~~ee~~<br>~~ss~~|STC_GAIN_GX[23:16]||||||||
|63<br>~~a~~|99<br>~~a~~|IMEM_SRAM_REG_99<br>~~ee~~|R/W<br>~~ee~~|STC_GAIN_GX[31:24]||||||||
|64<br>~~a ~~<br>~~a~~|100<br> ~~a~~|IMEM_SRAM_REG_100<br>~~ee~~<br>~~ss~~|R/W<br>~~ee~~<br>~~ss~~|STC_GAIN_GY[7:0]||||||||
|65<br>~~a~~|101<br>~~a~~|IMEM_SRAM_REG_101<br>~~ee~~|R/W<br>~~ee~~|STC_GAIN_GY[15:8]||||||||
|66<br>~~a ~~<br>~~a~~|102<br> ~~a~~|IMEM_SRAM_REG_102<br>~~ee~~<br>~~ss~~|R/W<br>~~ee~~<br>~~ss~~|STC_GAIN_GY[23:16]||||||||
|67<br>~~a~~<br>~~a~~|103<br>~~a~~|IMEM_SRAM_REG_103<br>~~ee~~<br>~~es rs~~|R/W<br>~~ee~~<br>~~rs~~|STC_GAIN_GY[31:24]||||||||
|68<br>~~a ~~<br>~~a~~|104<br> ~~a~~|IMEM_SRAM_REG_104<br>~~ee~~<br>~~es rs~~|R/W<br>~~ee~~<br>~~rs~~|STC_GAIN_GZ[7:0]||||||||
|69<br>~~a~~<br>~~a~~<br>~~a~~|105<br>~~a~~|IMEM_SRAM_REG_105<br>~~es rs~~<br>~~ee~~<br>~~es es~~|R/W<br>~~rs~~<br>~~ee~~<br>~~es~~|STC_GAIN_GZ[15:8]||||||||
|6A<br>~~a ~~<br>~~a~~|106<br> ~~a~~|IMEM_SRAM_REG_106<br>~~ee~~<br>~~es es~~|R/W<br>~~ee~~<br>~~es~~|STC_GAIN_GZ[23:16]||||||||
|6B<br>~~a~~<br>~~a~~<br>~~a~~|107<br>~~a~~|IMEM_SRAM_REG_107<br>~~es es~~<br>~~ee~~<br>~~es es~~|R/W<br>~~es~~<br>~~ee~~<br>~~es~~|STC_GAIN_GZ[31:24]||||||||
|88<br>~~a ~~<br>~~a~~|136<br> ~~a~~|IMEM_SRAM_REG_136<br>~~ee~~<br>~~es es~~|R/W<br>~~ee~~<br>~~es~~|FF_DURATION_BUF1[7:0]||||||||
|89<br>~~a~~<br>~~a~~<br>~~a~~|137<br>~~a~~|IMEM_SRAM_REG_137<br>~~es es~~<br>~~ee~~<br>~~es es~~|R/W<br>~~es~~<br>~~ee~~<br>~~es~~|FF_DURATION_BUF1[15:8]||||||||
|8A<br>~~a ~~<br>~~a~~|138<br> ~~a~~|IMEM_SRAM_REG_138<br>~~ee~~<br>~~es es~~|R/W<br>~~ee~~<br>~~es~~|FF_DURATION_BUF2[7:0]||||||||
|8B<br>~~a~~<br>~~a~~<br>~~a~~|139<br>~~a~~|IMEM_SRAM_REG_139<br>~~es es~~<br>~~ee~~<br>~~es es~~|R/W<br>~~es~~<br>~~ee~~<br>~~es~~|FF_DURATION_BUF2[15:8]||||||||
|8D<br>~~a ~~<br>~~a~~|141<br> ~~a~~|IMEM_SRAM_REG_141<br>~~ee~~<br>~~es es~~|R/W<br>~~ee~~<br>~~es~~|TAP_NUM||||||||
|8E<br>~~a~~<br>~~a~~<br>~~a~~|142<br>~~a~~|IMEM_SRAM_REG_142<br>~~es es~~<br>~~ee~~<br>~~es es~~|R/W<br>~~es~~<br>~~ee~~<br>~~es~~|TAP_AXIS||||||||
|8F<br>~~a ~~<br>~~a~~|143<br> ~~a~~|IMEM_SRAM_REG_143<br>~~ee~~<br>~~es es~~|R/W<br>~~ee~~<br>~~es~~|TAP_DIR||||||||
|90<br>~~a~~<br>~~a~~<br>~~a~~|144<br>~~a~~|IMEM_SRAM_REG_144<br>~~es es~~<br>~~ee~~<br>~~es es~~|R/W<br>~~es~~<br>~~ee~~<br>~~es~~|DOUBLE_TAP_TIMING||||||||
|92<br>~~a ~~<br>~~a~~<br>~~a~~|146<br> ~~a~~<br>~~a~~|IMEM_SRAM_REG_146<br>~~ee~~<br>~~es es~~<br>~~ee~~|R/W<br>~~ee~~<br>~~es~~<br>~~eG~~|TILT_RESET_EN<br>~~eG~~||||||||
|9A<br>~~a~~<br>~~a~~<br>~~a~~|154<br>~~a~~<br>~~a~~|IMEM_SRAM_REG_154<br>~~es es~~<br>~~ee~~<br>~~ee~~|R/W<br>~~es~~<br>~~eG~~<br>~~ee~~|PED_STEP_CNT_BUF1[7:0]<br>~~eG~~||||||||
|9B<br>~~a ~~<br>~~a~~<br>~~a~~|155<br> ~~a~~<br>~~a~~|IMEM_SRAM_REG_155<br>~~ee~~<br>~~ee~~<br>~~es es~~|R/W<br>~~eG~~<br>~~ee~~<br>~~es~~|PED_STEP_CNT_BUF1[15:8]<br>~~eG~~||||||||
|9C<br>~~a ~~<br>~~a~~|156<br> ~~a~~|IMEM_SRAM_REG_156<br>~~ee ~~<br>~~es es~~|R/W<br> ~~ee~~<br>~~es~~|PED_STEP_CNT_BUF2[7:0]||||||||
|9D<br>~~a~~<br>~~a~~<br>~~a~~|157<br>~~a~~|IMEM_SRAM_REG_157<br>~~es es~~<br>~~ss~~<br>~~es es~~|R/W<br>~~es~~<br>~~ss~~<br>~~es~~|PED_STEP_CNT_BUF2[15:8]||||||||
|9F<br>~~a ~~<br>~~a~~|159<br> ~~a~~|IMEM_SRAM_REG_159<br>~~ss~~<br>~~es es~~|R/W<br>~~ss~~<br>~~es~~|PED_STEP_CADENCE||||||||
|A0<br>~~a~~<br>~~a~~<br>~~a~~|160<br>~~a~~|IMEM_SRAM_REG_160<br>~~es es~~<br>~~ss~~<br>~~es es~~|R/W<br>~~es~~<br>~~ss~~<br>~~es~~|POWER_ACTIVITY_CLASS||||||||
|B6<br>~~a ~~<br>~~a~~|182<br> ~~a~~|IMEM_SRAM_REG_182<br>~~ss~~<br>~~es es~~|R/W<br>~~ss~~<br>~~es~~|ES_RAM_IMAGE_EN||||||||
|B9<br>~~a~~<br>~~a~~<br>~~a~~|185<br>~~a~~|IMEM_SRAM_REG_185<br>~~es es~~<br>~~ss~~<br>~~es es~~|R/W<br>~~es~~<br>~~ss~~<br>~~es~~|ES0_COMPASS_EN||||||||
|BA<br>~~a ~~<br>~~a~~|186<br> ~~a~~|IMEM_SRAM_REG_186<br>~~ss~~<br>~~es es~~|R/W<br>~~ss~~<br>~~es~~|ES_POWER_MODE||||||||
|C4<br>~~a~~<br>~~a~~|196<br>~~a~~|IMEM_SRAM_REG_196<br>~~es es~~<br>~~ss~~|R/W<br>~~es~~<br>~~ss~~|POWER_SAVE_TIME[7:0]||||||||
|C5<br>~~a ~~<br>~~a ~~|197<br> ~~a~~<br> ~~a~~|IMEM_SRAM_REG_197<br>~~ss~~<br>~~ss~~|R/W<br>~~ss~~<br>~~ss~~|POWER_SAVE_TIME[15:8]||||||||



Page 58 of 191 

Document Number: DS-000576 Revision: 1.0 

_**ICM-45605**_ 

|**Addr**<br>**(Hex)**<br>~~||~~|**Addr**<br>**(Dec.)**<br>~~||~~|**Register Name**|**Serial**<br>**I/F**|**Bit7**|**Bit6**|**Bit5**|**Bit4**|**Bit3**|**Bit2**|**Bit1**|**Bit0**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|C6<br>~~a ~~<br>~~a~~|198<br> ~~a~~|IMEM_SRAM_REG_198<br>~~es~~|R/W<br>~~rs~~|POWER_SAVE_TIME[23:16]||||||||
|C7<br> <br>~~a~~<br>~~a~~|199<br> ~~a~~<br>~~ss~~|IMEM_SRAM_REG_199<br>~~es ~~<br>~~ss~~<br>~~ss es~~|R/W<br> ~~rs~~<br>~~ss~~<br>~~es~~|POWER_SAVE_TIME[31:24]||||||||
|120<br>~~a~~|288<br>~~ss~~|IMEM_SRAM_REG_288<br>~~ss es~~|R/W<br>~~es~~|FF_MIN_DURATION[7:0]||||||||
|121<br>~~a ~~<br>~~a~~<br>~~a~~|289<br> ~~ss~~<br>~~ss~~|IMEM_SRAM_REG_289<br>~~ss es~~<br>~~ss~~<br>~~ss es~~|R/W<br>~~es~~<br>~~ss~~<br>~~es~~|FF_MIN_DURATION[15:8]||||||||
|122<br>~~a~~|290<br>~~ss~~|IMEM_SRAM_REG_290<br>~~ss es~~|R/W<br>~~es~~|FF_MIN_DURATION[23:16]||||||||
|123<br>~~a ~~<br>~~a~~<br>~~a~~|291<br> ~~ss~~<br>~~ss~~|IMEM_SRAM_REG_291<br>~~ss es~~<br>~~ss~~<br>~~ss es~~|R/W<br>~~es~~<br>~~ss~~<br>~~es~~|FF_MIN_DURATION[31:24]||||||||
|124<br>~~a~~|292<br>~~ss~~|IMEM_SRAM_REG_292<br>~~ss es~~|R/W<br>~~es~~|FF_MAX_DURATION[7:0]||||||||
|125<br>~~a ~~<br>~~a~~<br>~~a~~|293<br> ~~ss~~<br>~~ss~~|IMEM_SRAM_REG_293<br>~~ss es~~<br>~~ss~~<br>~~ss es~~|R/W<br>~~es~~<br>~~ss~~<br>~~es~~|FF_MAX_DURATION[15:8]||||||||
|126<br>~~a~~|294<br>~~ss~~|IMEM_SRAM_REG_294<br>~~ss es~~|R/W<br>~~es~~|FF_MAX_DURATION[23:16]||||||||
|127<br>~~a ~~<br>~~a~~<br>~~a~~|295<br> ~~ss~~<br>~~ss~~|IMEM_SRAM_REG_295<br>~~ss es~~<br>~~ss~~<br>~~ss es~~|R/W<br>~~es~~<br>~~ss~~<br>~~es~~|FF_MAX_DURATION[31:24]||||||||
|128<br>~~a~~|296<br>~~ss~~|IMEM_SRAM_REG_296<br>~~ss es~~|R/W<br>~~es~~|FF_DEBOUNCE_DURATION[7:0]||||||||
|129<br>~~a ~~<br>~~a~~<br>~~a~~|297<br> ~~ss~~<br>~~a~~|IMEM_SRAM_REG_297<br>~~ss es~~<br>~~ss~~<br>~~es~~|R/W<br>~~es~~<br>~~ss~~<br>~~es~~|FF_DEBOUNCE_DURATION[15:8]||||||||
|12A<br>~~a~~<br>~~a~~|298<br>~~a~~<br>~~a~~|IMEM_SRAM_REG_298<br>~~es~~<br>~~ee~~|R/W<br>~~es~~<br>~~eG~~|FF_DEBOUNCE_DURATION[23:16]<br>~~eG~~||||||||
|12B<br>~~a ~~<br>~~a~~|299<br> ~~a ~~<br>~~a~~|IMEM_SRAM_REG_299<br> ~~es ~~<br>~~ee~~|R/W<br> ~~es~~<br>~~eG~~|FF_DEBOUNCE_DURATION[31:24]<br>~~eG~~||||||||
|130<br>~~a ~~<br>~~a~~|304<br> ~~a ~~|IMEM_SRAM_REG_304<br> ~~ee~~<br>~~ss~~|R/W<br>~~eG~~<br>~~ss~~|HIGHG_PEAK_TH[7:0]<br>~~eG~~||||||||
|131<br>~~a~~|305<br>~~a~~|IMEM_SRAM_REG_305<br>~~ee~~|R/W<br>~~ee~~|HIGHG_PEAK_TH[15:8]||||||||
|132<br>~~a ~~<br>~~a~~|306<br> ~~a~~|IMEM_SRAM_REG_306<br>~~ee~~<br>~~ss~~|R/W<br>~~ee~~<br>~~ss~~|HIGHG_PEAK_TH_HYST[7:0]||||||||
|133<br>~~a~~|307<br>~~a~~|IMEM_SRAM_REG_307<br>~~ee~~|R/W<br>~~ee~~|HIGHG_PEAK_TH_HYST[15:8]||||||||
|134<br>~~a ~~<br>~~a~~|308<br> ~~a~~|IMEM_SRAM_REG_308<br>~~ee~~<br>~~ss~~|R/W<br>~~ee~~<br>~~ss~~|HIGHG_TIME_TH[7:0]||||||||
|135<br>~~a~~|309<br>~~a~~|IMEM_SRAM_REG_309<br>~~ee~~|R/W<br>~~ee~~|HIGHG_TIME_TH[15:8]||||||||
|13C<br>~~a ~~<br>~~a~~|316<br> ~~a~~|IMEM_SRAM_REG_316<br>~~ee~~<br>~~ss~~|R/W<br>~~ee~~<br>~~ss~~|LOWG_PEAK_TH[7:0]||||||||
|13D<br>~~a~~|317<br>~~a~~|IMEM_SRAM_REG_317<br>~~ee~~|R/W<br>~~ee~~|LOWG_PEAK_TH[15:8]||||||||
|13E<br>~~a ~~<br>~~a~~|318<br> ~~a~~|IMEM_SRAM_REG_318<br>~~ee~~<br>~~ss~~|R/W<br>~~ee~~<br>~~ss~~|LOWG_PEAK_TH_HYST[7:0]||||||||
|13F<br>~~a~~|319<br>~~a~~|IMEM_SRAM_REG_319<br>~~ee~~|R/W<br>~~ee~~|LOWG_PEAK_TH_HYST[15:8]||||||||
|140<br>~~a ~~<br>~~a~~|320<br> ~~a~~|IMEM_SRAM_REG_320<br>~~ee~~<br>~~ss~~|R/W<br>~~ee~~<br>~~ss~~|LOWG_TIME_TH[7:0]||||||||
|141<br>~~a~~|321<br>~~a~~|IMEM_SRAM_REG_321<br>~~ee~~|R/W<br>~~ee~~|LOWG_TIME_TH[15:8]||||||||
|188<br>~~a ~~<br>~~a~~<br>~~a~~|392<br> ~~a~~<br>~~a~~|IMEM_SRAM_REG_392<br>~~ee~~<br>~~ss~~<br>~~ee~~|R/W<br>~~ee~~<br>~~ss~~<br>~~eG~~|TILT_WAIT_TIME[7:0]<br>~~eG~~||||||||
|189<br>~~a~~<br>~~a~~|393<br>~~a~~|IMEM_SRAM_REG_393<br>~~ee~~<br>~~es es~~|R/W<br>~~eG~~<br>~~es~~|TILT_WAIT_TIME[15:8]<br>~~eG~~||||||||
|190<br>~~a ~~<br>~~a~~|400<br> ~~a ~~|IMEM_SRAM_REG_400<br> ~~ee~~<br>~~es es~~|R/W<br>~~eG~~<br>~~es~~|TAP_TMAX[7:0]<br>~~eG~~||||||||
|191<br>~~a~~<br>~~a~~<br>~~a~~|401<br>~~a~~|IMEM_SRAM_REG_401<br>~~es es~~<br>~~ee~~<br>~~es es~~|R/W<br>~~es~~<br>~~ee~~<br>~~es~~|TAP_TMAX[15:8]||||||||
|192<br>~~a ~~<br>~~a~~|402<br> ~~a~~|IMEM_SRAM_REG_402<br>~~ee~~<br>~~es es~~|R/W<br>~~ee~~<br>~~es~~|TAP_TMIN||||||||
|193<br>~~a~~<br>~~a~~<br>~~a~~|403<br>~~a~~|IMEM_SRAM_REG_403<br>~~es es~~<br>~~ee~~<br>~~es es~~|R/W<br>~~es~~<br>~~ee~~<br>~~es~~|TAP_MIN_JERK||||||||
|194<br>~~a ~~<br>~~a~~|404<br> ~~a~~|IMEM_SRAM_REG_404<br>~~ee~~<br>~~es es~~|R/W<br>~~ee~~<br>~~es~~|TAP_SMUDGE_REJECT_THR||||||||
|195<br>~~a~~<br>~~a~~<br>~~a~~|405<br>~~a~~|IMEM_SRAM_REG_405<br>~~es es~~<br>~~ee~~<br>~~es es~~|R/W<br>~~es~~<br>~~ee~~<br>~~es~~|TAP_MAX_PEAK_TOL||||||||
|196<br>~~a ~~<br>~~a~~|406<br> ~~a~~|IMEM_SRAM_REG_406<br>~~ee~~<br>~~es es~~|R/W<br>~~ee~~<br>~~es~~|TAP_TAVG||||||||
|21C<br>~~a~~<br>~~a~~<br>~~a~~|543<br>~~a~~|IMEM_SRAM_REG_540<br>~~es es~~<br>~~ee~~<br>~~es es~~|R/W<br>~~es~~<br>~~ee~~<br>~~es~~|R2W_SLEEP_TIME_OUT[7:0]||||||||
|21D<br>~~a ~~<br>~~a~~|543<br> ~~a~~|IMEM_SRAM_REG_541<br>~~ee~~<br>~~es es~~|R/W<br>~~ee~~<br>~~es~~|R2W_SLEEP_TIME_OUT[15:8]||||||||
|21E<br>~~a~~<br>~~a~~<br>~~a~~|543<br>~~a~~|IMEM_SRAM_REG_542<br>~~es es~~<br>~~ee~~<br>~~es es~~|R/W<br>~~es~~<br>~~ee~~<br>~~es~~|R2W_SLEEP_TIME_OUT[23:16]||||||||
|21F<br>~~a ~~<br>~~a~~|543<br> ~~a~~|IMEM_SRAM_REG_543<br>~~ee~~<br>~~es es~~|R/W<br>~~ee~~<br>~~es~~|R2W_SLEEP_TIME_OUT[31:24]||||||||
|220<br>~~a~~<br>~~a~~<br>~~a~~|544<br>~~a~~|IMEM_SRAM_REG_544<br>~~es es~~<br>~~ee~~<br>~~es es~~|R/W<br>~~es~~<br>~~ee~~<br>~~es~~|R2W_SLEEP_GESTURE_DELAY[7:0]||||||||
|221<br>~~a ~~<br>~~a~~<br>~~a~~|545<br> ~~a~~<br>~~ee~~|IMEM_SRAM_REG_545<br>~~ee~~<br>~~es es~~<br>~~ee~~|R/W<br>~~ee~~<br>~~es~~<br>~~eG~~|R2W_SLEEP_GESTURE_DELAY[15:8]<br>~~eG~~||||||||
|222<br>~~a~~<br>~~a~~<br>~~a~~|546<br>~~ee~~<br>~~a~~|IMEM_SRAM_REG_546<br>~~es es~~<br>~~ee~~<br>~~ee~~|R/W<br>~~es~~<br>~~eG~~|R2W_SLEEP_GESTURE_DELAY[23:16]<br>~~eG~~||||||||
|223<br>~~a~~<br>~~a~~<br>~~a~~|547<br>~~ee ~~<br>~~a~~|IMEM_SRAM_REG_547<br> ~~ee~~<br>~~ee~~<br>~~es es~~|R/W<br>~~eG~~<br>~~es~~|R2W_SLEEP_GESTURE_DELAY[31:24]<br>~~eG~~||||||||
|224<br>~~a ~~<br>~~a~~|548<br> ~~a~~|IMEM_SRAM_REG_548<br>~~ee~~<br>~~es es~~|R/W<br>~~es~~|R2W_MOUNTING_MATRIX[7:0]||||||||
|225<br>~~a~~<br>~~a~~<br>~~a~~|549<br>~~a~~|IMEM_SRAM_REG_549<br>~~es es~~<br>~~ss~~<br>~~es es~~|R/W<br>~~es~~<br>~~ss~~<br>~~es~~|R2W_MOUNTING_MATRIX[15:8]||||||||
|226<br>~~a ~~<br>~~a~~|550<br> ~~a~~|IMEM_SRAM_REG_550<br>~~ss~~<br>~~es es~~|R/W<br>~~ss~~<br>~~es~~|R2W_MOUNTING_MATRIX[23:16]||||||||
|227<br>~~a~~<br>~~a~~<br>~~a~~|551<br>~~a~~|IMEM_SRAM_REG_551<br>~~es es~~<br>~~ss~~<br>~~es es~~|R/W<br>~~es~~<br>~~ss~~<br>~~es~~|R2W_MOUNTING_MATRIX[31:24]||||||||
|22C<br>~~a ~~<br>~~a~~|556<br> ~~a~~|IMEM_SRAM_REG_556<br>~~ss~~<br>~~es es~~|R/W<br>~~ss~~<br>~~es~~|R2W_GRAVITY_FILTER_GAIN[7:0]||||||||
|22D<br>~~a~~<br>~~a~~|557<br>~~a~~|IMEM_SRAM_REG_557<br>~~es es~~<br>~~ss~~|R/W<br>~~es~~<br>~~ss~~|R2W_GRAVITY_FILTER_GAIN[15:8]||||||||
|22E<br>~~a ~~<br>~~a~~<br>~~a~~|558<br> ~~a~~<br>~~a~~<br>~~a~~|IMEM_SRAM_REG_558<br>~~ss~~<br>~~ss~~<br>~~ee~~|R/W<br>~~ss~~<br>~~ss~~|R2W_GRAVITY_FILTER_GAIN[23:16]||||||||
|22F<br>~~a~~|559<br>~~a~~|IMEM_SRAM_REG_559<br>~~ee~~|R/W|R2W_GRAVITY_FILTER_GAIN[31:24]||||||||



Page 59 of 191 

Document Number: DS-000576 Revision: 1.0 

_**ICM-45605**_ 

|**Addr**<br>**(Hex)**<br>~~||~~|**Addr**<br>**(Dec.)**<br>~~||~~|**Register Name**|**Serial**<br>**I/F**|**Bit7**|**Bit6**|**Bit5**|**Bit4**|**Bit3**|**Bit2**|**Bit1**|**Bit0**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|230<br>~~a ~~<br>~~a~~|560<br> ~~a~~|IMEM_SRAM_REG_560<br>~~es~~|R/W<br>~~rs~~|R2W_MOTION_THR_ANGLE_COSINE[7:0]||||||||
|231<br> <br>~~a~~<br>~~a~~|561<br> ~~a~~<br>~~ss~~|IMEM_SRAM_REG_561<br>~~es ~~<br>~~ss~~<br>~~ss es~~|R/W<br> ~~rs~~<br>~~ss~~<br>~~es~~|R2W_MOTION_THR_ANGLE_COSINE[15:8]||||||||
|232<br>~~a~~|562<br>~~ss~~|IMEM_SRAM_REG_562<br>~~ss es~~|R/W<br>~~es~~|R2W_MOTION_THR_ANGLE_COSINE[23:16]||||||||
|233<br>~~a ~~<br>~~a~~<br>~~a~~|563<br> ~~ss~~<br>~~ss~~|IMEM_SRAM_REG_563<br>~~ss es~~<br>~~ss~~<br>~~ss es~~|R/W<br>~~es~~<br>~~ss~~<br>~~es~~|R2W_MOTION_THR_ANGLE_COSINE[31:24]||||||||
|234<br>~~a~~|564<br>~~ss~~|IMEM_SRAM_REG_564<br>~~ss es~~|R/W<br>~~es~~|R2W_MOTION_THR_TIMER_FAST[7:0]||||||||
|235<br>~~a ~~<br>~~a~~<br>~~a~~|565<br> ~~ss~~<br>~~ss~~|IMEM_SRAM_REG_565<br>~~ss es~~<br>~~ss~~<br>~~ss es~~|R/W<br>~~es~~<br>~~ss~~<br>~~es~~|R2W_MOTION_THR_TIMER_FAST[15:8]||||||||
|236<br>~~a~~|566<br>~~ss~~|IMEM_SRAM_REG_566<br>~~ss es~~|R/W<br>~~es~~|R2W_MOTION_THR_TIMER_FAST[23:16]||||||||
|237<br>~~a ~~<br>~~a~~<br>~~a~~|567<br> ~~ss~~<br>~~ss~~|IMEM_SRAM_REG_567<br>~~ss es~~<br>~~ss~~<br>~~ss es~~|R/W<br>~~es~~<br>~~ss~~<br>~~es~~|R2W_MOTION_THR_TIMER_FAST[31:24]||||||||
|238<br>~~a~~|568<br>~~ss~~|IMEM_SRAM_REG_568<br>~~ss es~~|R/W<br>~~es~~|R2W_MOTION_THR_TIMER_SLOW[7:0]||||||||
|239<br>~~a ~~<br>~~a~~<br>~~a~~|569<br> ~~ss~~<br>~~ss~~|IMEM_SRAM_REG_569<br>~~ss es~~<br>~~ss~~<br>~~ss es~~|R/W<br>~~es~~<br>~~ss~~<br>~~es~~|R2W_MOTION_THR_TIMER_SLOW[15:8]||||||||
|23A<br>~~a~~|570<br>~~ss~~|IMEM_SRAM_REG_570<br>~~ss es~~|R/W<br>~~es~~|R2W_MOTION_THR_TIMER_SLOW[23:16]||||||||
|23B<br>~~a ~~<br>~~a~~<br>~~a~~|571<br> ~~ss~~<br>~~a~~|IMEM_SRAM_REG_571<br>~~ss es~~<br>~~ss~~<br>~~es~~|R/W<br>~~es~~<br>~~ss~~<br>~~es~~|R2W_MOTION_THR_TIMER_SLOW[31:24]||||||||
|23C<br>~~a~~<br>~~a~~|572<br>~~a~~<br>~~a~~|IMEM_SRAM_REG_572<br>~~es~~<br>~~ee~~|R/W<br>~~es~~<br>~~eG~~|R2W_MOTION_PREV_GRAVITY_TIMEOUT[7:0]<br>~~eG~~||||||||
|23D<br>~~a ~~<br>~~a~~|573<br> ~~a ~~<br>~~a~~|IMEM_SRAM_REG_573<br> ~~es ~~<br>~~ee~~|R/W<br> ~~es~~<br>~~eG~~|R2W_MOTION_PREV_GRAVITY_TIMEOUT[15:8]<br>~~eG~~||||||||
|23E<br>~~a ~~<br>~~a~~|574<br> ~~a ~~|IMEM_SRAM_REG_574<br> ~~ee~~<br>~~ss~~|R/W<br>~~eG~~<br>~~ss~~|R2W_MOTION_PREV_GRAVITY_TIMEOUT[23:16]<br>~~eG~~||||||||
|23F<br>~~a~~|575<br>~~a~~|IMEM_SRAM_REG_575<br>~~ee~~|R/W<br>~~ee~~|R2W_MOTION_PREV_GRAVITY_TIMEOUT[31:24]||||||||
|240<br>~~a ~~<br>~~a~~|576<br> ~~a~~|IMEM_SRAM_REG_576<br>~~ee~~<br>~~ss~~|R/W<br>~~ee~~<br>~~ss~~|R2W_LAST_GRAVITY_MOTION_TIMER[7:0]||||||||
|241<br>~~a~~|577<br>~~a~~|IMEM_SRAM_REG_577<br>~~ee~~|R/W<br>~~ee~~|R2W_LAST_GRAVITY_MOTION_TIMER[15:8]||||||||
|242<br>~~a ~~<br>~~a~~|578<br> ~~a~~|IMEM_SRAM_REG_578<br>~~ee~~<br>~~ss~~|R/W<br>~~ee~~<br>~~ss~~|R2W_LAST_GRAVITY_MOTION_TIMER[23:16]||||||||
|243<br>~~a~~|579<br>~~a~~|IMEM_SRAM_REG_579<br>~~ee~~|R/W<br>~~ee~~|R2W_LAST_GRAVITY_MOTION_TIMER[31:24]||||||||
|244<br>~~a ~~<br>~~a~~|580<br> ~~a~~|IMEM_SRAM_REG_580<br>~~ee~~<br>~~ss~~|R/W<br>~~ee~~<br>~~ss~~|R2W_LAST_GRAVITY_TIMEOUT[7:0]||||||||
|245<br>~~a~~|581<br>~~a~~|IMEM_SRAM_REG_581<br>~~ee~~|R/W<br>~~ee~~|R2W_LAST_GRAVITY_TIMEOUT[15:8]||||||||
|246<br>~~a ~~<br>~~a~~|582<br> ~~a~~|IMEM_SRAM_REG_582<br>~~ee~~<br>~~ss~~|R/W<br>~~ee~~<br>~~ss~~|R2W_LAST_GRAVITY_TIMEOUT[23:16]||||||||
|247<br>~~a~~|583<br>~~a~~|IMEM_SRAM_REG_583<br>~~ee~~|R/W<br>~~ee~~|R2W_LAST_GRAVITY_TIMEOUT[31:24]||||||||
|248<br>~~a ~~<br>~~a~~|584<br> ~~a~~|IMEM_SRAM_REG_584<br>~~ee~~<br>~~ss~~|R/W<br>~~ee~~<br>~~ss~~|R2W_GESTURE_VALIDITY_TIMEOUT[7:0]||||||||
|249<br>~~a~~|585<br>~~a~~|IMEM_SRAM_REG_585<br>~~ee~~|R/W<br>~~ee~~|R2W_GESTURE_VALIDITY_TIMEOUT[15:8]||||||||
|24A<br>~~a ~~<br>~~a~~<br>~~a~~|586<br> ~~a~~<br>~~a~~|IMEM_SRAM_REG_586<br>~~ee~~<br>~~ss~~<br>~~ee~~|R/W<br>~~ee~~<br>~~ss~~<br>~~eG~~|R2W_GESTURE_VALIDITY_TIMEOUT[23:16]<br>~~eG~~||||||||
|24B<br>~~a~~<br>~~a~~|587<br>~~a~~|IMEM_SRAM_REG_587<br>~~ee~~<br>~~es es~~|R/W<br>~~eG~~<br>~~es~~|R2W_GESTURE_VALIDITY_TIMEOUT[31:24]<br>~~eG~~||||||||
|3DC<br>~~a ~~<br>~~a~~|988<br> ~~a ~~|IMEM_SRAM_REG_988<br> ~~ee~~<br>~~es es~~|R/W<br>~~eG~~<br>~~es~~|PED_STEP_CNT_TH[7:0]<br>~~eG~~||||||||
|3DD<br>~~a~~<br>~~a~~<br>~~a~~|989<br>~~a~~|IMEM_SRAM_REG_989<br>~~es es~~<br>~~ee~~<br>~~es es~~|R/W<br>~~es~~<br>~~ee~~<br>~~es~~|PED_STEP_CNT_TH[15:8]||||||||
|3DE<br>~~a ~~<br>~~a~~|990<br> ~~a~~|IMEM_SRAM_REG_990<br>~~ee~~<br>~~es es~~|R/W<br>~~ee~~<br>~~es~~|PED_STEP_DET_TH[7:0]||||||||
|3DF<br>~~a~~<br>~~a~~<br>~~a~~|991<br>~~a~~|IMEM_SRAM_REG_991<br>~~es es~~<br>~~ee~~<br>~~es es~~|R/W<br>~~es~~<br>~~ee~~<br>~~es~~|PED_STEP_DET_TH[15:8]||||||||
|3E2<br>~~a ~~<br>~~a~~|994<br> ~~a~~|IMEM_SRAM_REG_994<br>~~ee~~<br>~~es es~~|R/W<br>~~ee~~<br>~~es~~|PED_SB_TIMER_TH[7:0]||||||||
|3E3<br>~~a~~<br>~~a~~<br>~~a~~|995<br>~~a~~|IMEM_SRAM_REG_995<br>~~es es~~<br>~~ee~~<br>~~es es~~|R/W<br>~~es~~<br>~~ee~~<br>~~es~~|PED_SB_TIMER_TH[15:8]||||||||
|3E8<br>~~a ~~<br>~~a~~|1000<br> ~~a~~|IMEM_SRAM_REG_1000<br>~~ee~~<br>~~es es~~|R/W<br>~~ee~~<br>~~es~~|PED_LOW_EN_AMP_TH[7:0]||||||||
|3E9<br>~~a~~<br>~~a~~<br>~~a~~|1001<br>~~a~~|IMEM_SRAM_REG_1001<br>~~es es~~<br>~~ee~~<br>~~es es~~|R/W<br>~~es~~<br>~~ee~~<br>~~es~~|PED_LOW_EN_AMP_TH[15:8]||||||||
|3EA<br>~~a ~~<br>~~a~~|1002<br> ~~a~~|IMEM_SRAM_REG_1002<br>~~ee~~<br>~~es es~~|R/W<br>~~ee~~<br>~~es~~|PED_LOW_EN_AMP_TH[23:16]||||||||
|3EB<br>~~a~~<br>~~a~~<br>~~a~~|1003<br>~~a~~|IMEM_SRAM_REG_1003<br>~~es es~~<br>~~ee~~<br>~~es es~~|R/W<br>~~es~~<br>~~ee~~<br>~~es~~|PED_LOW_EN_AMP_TH[31:24]||||||||
|3EC<br>~~a ~~<br>~~a~~|1004<br> ~~a~~|IMEM_SRAM_REG_1004<br>~~ee~~<br>~~es es~~|R/W<br>~~ee~~<br>~~es~~|PED_SENSITIVITY_MODE||||||||
|3F0<br>~~a~~<br>~~a~~<br>~~a~~|1008<br>~~a~~|IMEM_SRAM_REG_1008<br>~~es es~~<br>~~ee~~<br>~~es es~~|R/W<br>~~es~~<br>~~ee~~<br>~~es~~|PED_AMP_TH[7:0]||||||||
|3F1<br>~~a ~~<br>~~a~~<br>~~a~~|1009<br> ~~a~~<br>~~ee~~|IMEM_SRAM_REG_1009<br>~~ee~~<br>~~es es~~<br>~~ee~~|R/W<br>~~ee~~<br>~~es~~<br>~~eG~~|PED_AMP_TH[15:8]<br>~~eG~~||||||||
|3F2<br>~~a~~<br>~~a~~<br>~~a~~|1010<br>~~ee~~<br>~~a~~|IMEM_SRAM_REG_1010<br>~~es es~~<br>~~ee~~<br>~~ee~~|R/W<br>~~es~~<br>~~eG~~|PED_AMP_TH[23:16]<br>~~eG~~||||||||
|3F3<br>~~a~~<br>~~a~~<br>~~a~~|1011<br>~~ee ~~<br>~~a~~|IMEM_SRAM_REG_1011<br> ~~ee~~<br>~~ee~~<br>~~es es~~|R/W<br>~~eG~~<br>~~es~~|PED_AMP_TH[31:24]<br>~~eG~~||||||||
|3F8<br>~~a ~~<br>~~a~~|1016<br> ~~a~~|IMEM_SRAM_REG_1016<br>~~ee~~<br>~~es es~~|R/W<br>~~es~~|PED_HI_EN_TH[7:0]||||||||
|3F9<br>~~a~~<br>~~a~~<br>~~a~~|1017<br>~~a~~|IMEM_SRAM_REG_1017<br>~~es es~~<br>~~ss~~<br>~~es es~~|R/W<br>~~es~~<br>~~ss~~<br>~~es~~|PED_HI_EN_TH[15:8]||||||||
|3FA<br>~~a ~~<br>~~a~~|1018<br> ~~a~~|IMEM_SRAM_REG_1018<br>~~ss~~<br>~~es es~~|R/W<br>~~ss~~<br>~~es~~|PED_HI_EN_TH[23:16]||||||||
|3FB<br>~~a~~<br>~~a~~<br>~~a~~|1019<br>~~a~~|IMEM_SRAM_REG_1019<br>~~es es~~<br>~~ss~~<br>~~es es~~|R/W<br>~~es~~<br>~~ss~~<br>~~es~~|PED_HI_EN_TH[31:24]||||||||
|412<br>~~a ~~<br>~~a~~<br>~~a~~|1042<br> ~~a~~|IMEM_SRAM_REG_1042<br>~~ss~~<br>~~es es~~<br>~~ee~~|R/W<br>~~ss~~<br>~~es~~|SMD_SENSITIVITY||||||||
|490<br>to<br>4B3<br>~~a~~<br>~~a~~|1168 to<br>1203|IMEM_SRAM_REG_1168 to<br>IMEM_SRAM_REG_1203<br>~~es es~~<br>~~ee~~|R/W<br>~~es~~|SOFT_IRON_SENSITIVITY_MATRIX[287:0]||||||||



Page 60 of 191 

Document Number: DS-000576 Revision: 1.0 

_**ICM-45605**_ 

## **16.3 USER BANK IPREG_BAR REGISTER MAP** 

|**Addr**<br>**(Hex)**<br>~~||~~|**Addr**<br>**(Dec.)**<br>~~||~~|**Register Name**|**Serial**<br>**I/F**|**Bit7**|**Bit6**|**Bit5**|**Bit4**|**Bit3**|**Bit2**|**Bit1**|**Bit0**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|39<br>~~a ~~|57<br> ~~ss~~|IPREG_BAR_REG_57<br>~~ss es~~|R/W<br>~~es~~|-<br>~~GQ~~|IO_OPT0<br>~~GQ~~<br>~~ee~~|IO_OPT1<br>~~GQ~~<br>~~ee~~|-<br>~~GQ~~<br>~~eee~~|||||
|3A<br> <br>~~ee~~|58<br> ~~ss~~<br>~~ee~~|IPREG_BAR_REG_58<br>~~ss es~~<br>~~ee~~|R/W<br>~~es~~<br>~~ee~~|PADS_AP_SC<br>LK_PUD_TRI<br>M_D2A<br>~~GQ~~<br>~~ee~~|PADS_AP_SC<br>LK_PE_TRIM_<br>D2A<br>~~GQ~~<br>~~ee~~<br>~~ee~~|-<br>~~GQ~~<br>~~ee~~<br>~~ee~~|PADS_AP_CS<br>_PUD_TRIM_<br>D2A<br>~~GQ~~<br>~~ee~~<br>~~eee~~|PADS_AP_CS<br>_PE_TRIM_D<br>2A<br>~~GQ~~<br>~~ee~~<br>~~eee~~|-<br>~~GQ~~<br>~~ee~~<br>~~eee~~||IO_OPT2<br>~~GQ~~<br>~~ee~~<br>~~eee~~|
|3B|59|IPREG_BAR_REG_59|R/W|PADS_PIN7_<br>PE_TRIM_D2<br>A|-<br>~~ee~~|PADS_AP_SD<br>O_PUD_TRIM<br>_D2A<br>~~ee ~~|PADS_AP_SD<br>O_PE_TRIM_<br>D2A<br> ~~eee~~|-<br>~~eee~~|PADS_AP_SD<br>I_PUD_TRIM<br>_D2A<br>~~eee~~|PADS_AP_SD<br>I_PE_TRIM_D<br>2A<br>~~eee~~|-<br>~~eee~~|
|3C|60|IPREG_BAR_REG_60|R/W|-|PADS_AUX1_<br>SCLK_PUD_T<br>RIM_D2A|PADS_AUX1_<br>SCLK_PE_TRI<br>M_D2A|PADS_AUX_S<br>CLK_TP2_FR<br>OM_PAD_DIS<br>ABLE_TRIM_<br>D2A|PADS_AUX1_<br>CS_PUD_TRI<br>M_D2A|PADS_AUX1_<br>CS_PE_TRIM<br>_D2A|-|PADS_PIN7_<br>CS_PUD_TRI<br>M_D2A|
|3D<br>~~eee~~|61<br>~~eee~~|IPREG_BAR_REG_61<br>~~eee~~|R/W<br>~~eee~~|PADS_INT1_P<br>UD_TRIM_D2<br>A<br>~~eee~~|PADS_INT1_P<br>E_TRIM_D2A<br>~~eee~~|-<br>~~eee ee~~|PADS_AUX1_<br>SDO_PUD_TR<br>IM_D2A<br>~~ee~~|PADS_AUX1_<br>SDO_PE_TRI<br>M_D2A<br>~~ee~~|-<br>~~ee~~|PADS_AUX1_<br>SDI_PUD_TRI<br>M_D2A<br>~~ee~~|PADS_AUX1_<br>SDI_PE_TRIM<br>_D2A<br>~~ee~~|
|3E<br>~~a~~|62<br>~~a~~|IPREG_BAR_REG_62<br>~~a~~|R/W<br>~~ee~~|-<br>~~ee~~|||||PADS_INT2_P<br>UD_TRIM_D2<br>A<br>~~ee~~|PADS_INT2_P<br>E_TRIM_D2A<br>~~ee~~|-<br>~~ee~~|



## **16.4 USER BANK IPREG_TOP1 REGISTER MAP** 

|**Addr**<br>**(Hex)**|**Addr**<br>**(Dec.)**|**Register Name**|**Serial**<br>**I/F**|**Bit7**|**Bit6**|**Bit5**|**Bit4**|**Bit3**|**Bit2**|**Bit1**|**Bit0**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|06<br>~~a~~<br>~~a~~|06<br>~~a~~<br>~~a~~|I2CM_COMMAND_0<br>~~ss~~<br>~~ee~~|R/W<br>~~ss~~<br>~~eG~~|ENDFLAG_0<br>~~QO~~<br>~~eG~~|CH_SEL_0<br>~~QO~~<br>~~DQ~~|R_W_0<br>~~DQ~~||BURSTLEN_0||||
|07<br>~~a~~<br>~~a~~|07<br>~~a~~|I2CM_COMMAND_1<br>~~ee~~<br>~~es rs~~|R/W<br>~~eG~~<br>~~rs~~|ENDFLAG_1<br>~~eG~~<br>~~rs~~|CH_SEL_1<br>~~DQ~~<br>~~GG~~|R_W_1<br>~~DQ~~<br>~~GG~~||BURSTLEN_1<br>~~GG~~||||
|08<br>~~a ~~<br>~~a~~<br>~~a~~|08<br> ~~a ~~<br>~~a~~|I2CM_COMMAND_2<br> ~~ee ~~<br>~~es rs~~<br>~~ee~~|R/W<br> ~~eG~~<br>~~rs~~<br>~~eG~~|ENDFLAG_2<br>~~eG~~<br>~~rs~~<br>~~eG~~|CH_SEL_2<br>~~DQ~~<br>~~GG~~<br>~~DG~~|R_W_2<br>~~DQ~~<br>~~GG~~<br>~~DG~~||BURSTLEN_2<br>~~GG~~||||
|09<br>~~a~~<br>~~a~~<br>~~a~~|09<br>~~a~~|I2CM_COMMAND_3<br>~~es rs~~<br>~~ee~~<br>~~es rs~~|R/W<br>~~rs ~~<br>~~eG~~<br>~~rs~~|ENDFLAG_3<br> ~~rs~~<br>~~eG~~|CH_SEL_3<br>~~GG~~<br>~~DG~~|R_W_3<br>~~GG~~<br>~~DG~~||BURSTLEN_3<br>~~GG~~||||
|0E<br>~~a ~~<br>~~a~~<br>~~a~~|14<br> ~~a ~~<br>~~a~~|I2CM_DEV_PROFILE0<br> ~~ee ~~<br>~~es rs~~<br>~~ee~~|R/W<br> ~~eG~~<br>~~rs~~<br>~~eG~~|RD_ADDRESS_0<br>~~eG~~<br>~~DG~~<br>~~eG~~||||||||
|0F<br>~~a~~<br>~~a~~<br>~~a~~|15<br>~~a~~|I2CM_DEV_PROFILE1<br>~~es rs~~<br>~~ee~~<br>~~es~~|R/W<br>~~rs~~<br>~~eG~~<br>~~rs~~|-<br>~~eG~~|DEV_ID_0|||||||
|10<br>~~a ~~<br>~~a~~<br>~~a~~|16<br> ~~a ~~<br>~~a~~|I2CM_DEV_PROFILE2<br> ~~ee ~~<br>~~es~~<br>~~ee~~|R/W<br> ~~eG~~<br>~~rs~~<br>~~eG~~|RD_ADDRESS_1<br>~~eG~~<br>~~eG~~||||||||
|11<br>~~a~~<br>~~a~~|17<br>~~a~~|I2CM_DEV_PROFILE3<br>~~es ~~<br>~~ee~~|R/W<br> ~~rs~~<br>~~eG~~|-<br>~~eG~~|DEV_ID_1|||||||
|16<br>~~a ~~<br>~~a~~<br>~~a~~|22<br> ~~a ~~<br>~~i~~<br>~~a~~|I2CM_CONTROL<br> ~~ee ~~<br>~~i~~<br>~~es~~|RWS<br> ~~eG~~<br>~~ee~~<br>~~es ee~~|-<br>~~eG~~<br>~~ee~~<br>~~ee~~|I2CM_RESTA<br>RT_EN<br>~~ee~~|-<br>~~ee~~||I2CM_SPEED|-||I2CM_GO|
|18<br>~~a ~~<br>~~a~~<br>~~a~~|24<br> ~~i~~<br>~~a~~<br>~~a~~|I2CM_STATUS<br>~~i~~<br>~~es~~<br>~~ee~~|R<br>~~ee~~<br>~~es ee~~<br>~~eG~~|-<br>~~ee~~<br>~~ee~~<br>~~eG~~||I2CM_SDA_E<br>RR<br>~~ee~~<br>~~eG~~|I2CM_SCL_E<br>RR|I2CM_SRST_E<br>RR|I2CM_TIMEO<br>UT_ERR|I2CM_DONE|I2CM_BUSY|
|1A<br>~~a~~<br>~~a~~<br>~~a~~|26<br>~~a~~<br>~~a~~<br>~~es~~|I2CM_EXT_DEV_STATUS<br>~~es~~<br>~~ee~~<br>~~es es~~|~~es ee~~<br>~~eG~~<br>~~es~~|-<br>~~ee~~<br>~~eG~~||||I2CM_EXT_DEV_STATUS||||
|1B<br>~~a ~~<br>~~a~~|27<br> ~~a ~~<br>~~es~~|I2CM_RD_DATA0<br> ~~ee ~~<br>~~es es~~|RWS<br> ~~eG~~<br>~~es~~|I2CM_RD_DATA0<br>~~eG~~||||||||
|1C<br>~~a ~~<br>~~a~~<br>~~a~~|28<br> ~~es~~<br>~~a~~|I2CM_RD_DATA1<br>~~es es~~<br>~~ee~~<br>~~es es~~|RWS<br>~~es~~<br>~~ee~~<br>~~es~~|I2CM_RD_DATA1||||||||
|1D<br>~~a ~~<br>~~a~~|29<br> ~~a~~|I2CM_RD_DATA2<br>~~ee~~<br>~~es es~~|RWS<br>~~ee~~<br>~~es~~|I2CM_RD_DATA2||||||||
|1E<br>~~a~~<br>~~a~~<br>~~a~~|30<br>~~a~~|I2CM_RD_DATA3<br>~~es es~~<br>~~ee~~<br>~~es es~~|RWS<br>~~es~~<br>~~ee~~<br>~~es~~|I2CM_RD_DATA3||||||||
|1F<br>~~a ~~<br>~~a~~|31<br> ~~a~~|I2CM_RD_DATA4<br>~~ee~~<br>~~es es~~|RWS<br>~~ee~~<br>~~es~~|I2CM_RD_DATA4||||||||
|20<br>~~a~~<br>~~a~~<br>~~a~~|32<br>~~a~~|I2CM_RD_DATA5<br>~~es es~~<br>~~ee~~<br>~~es es~~|RWS<br>~~es~~<br>~~ee~~<br>~~es~~|I2CM_RD_DATA5||||||||
|21<br>~~a ~~<br>~~a~~|33<br> ~~a~~|I2CM_RD_DATA6<br>~~ee~~<br>~~es es~~|RWS<br>~~ee~~<br>~~es~~|I2CM_RD_DATA6||||||||
|22<br>~~a~~<br>~~a~~<br>~~a~~|34<br>~~a~~|I2CM_RD_DATA7<br>~~es es~~<br>~~ee~~<br>~~es es~~|RWS<br>~~es~~<br>~~ee~~<br>~~es~~|I2CM_RD_DATA7||||||||
|23<br>~~a ~~<br>~~a~~<br>~~a~~|35<br> ~~a~~<br>~~ee~~|I2CM_RD_DATA8<br>~~ee~~<br>~~es es~~<br>~~ee~~|RWS<br>~~ee~~<br>~~es~~<br>~~eG~~|I2CM_RD_DATA8<br>~~eG~~||||||||
|24<br>~~a~~<br>~~a~~<br>~~a~~|36<br>~~ee~~|I2CM_RD_DATA9<br>~~es es~~<br>~~ee~~<br>~~es es~~|RWS<br>~~es~~<br>~~eG~~<br>~~es~~|I2CM_RD_DATA9<br>~~eG~~||||||||
|25<br>~~a~~<br>~~a~~|37<br>~~ee ~~|I2CM_RD_DATA10<br> ~~ee~~<br>~~es es~~|RWS<br>~~eG~~<br>~~es~~|I2CM_RD_DATA10<br>~~eG~~||||||||
|26<br>~~a~~<br>~~a~~<br>~~a~~|38<br>~~a~~|I2CM_RD_DATA11<br>~~es es~~<br>~~ss~~<br>~~es es~~|RWS<br>~~es~~<br>~~ss~~<br>~~es~~|I2CM_RD_DATA11||||||||
|27<br>~~a ~~<br>~~a~~|39<br> ~~a~~|I2CM_RD_DATA12<br>~~ss~~<br>~~es es~~|RWS<br>~~ss~~<br>~~es~~|I2CM_RD_DATA12||||||||
|28<br>~~a~~<br>~~a~~<br>~~a~~|40<br>~~a~~|I2CM_RD_DATA13<br>~~es es~~<br>~~ss~~<br>~~es es~~|RWS<br>~~es~~<br>~~ss~~<br>~~es~~|I2CM_RD_DATA13||||||||
|29<br>~~a ~~<br>~~a~~|41<br> ~~a~~|I2CM_RD_DATA14<br>~~ss~~<br>~~es es~~|RWS<br>~~ss~~<br>~~es~~|I2CM_RD_DATA14||||||||
|2A<br>~~a~~<br>~~a~~|42<br>~~a~~|I2CM_RD_DATA15<br>~~es es~~<br>~~ss~~|RWS<br>~~es~~<br>~~ss~~|I2CM_RD_DATA15||||||||
|2B<br>~~a ~~<br>~~a~~<br>~~a~~|43<br> ~~a~~<br>~~a~~<br>~~a~~|I2CM_RD_DATA16<br>~~ss~~<br>~~ss~~<br>~~ee~~|RWS<br>~~ss~~<br>~~ss~~<br>~~eG~~|I2CM_RD_DATA16<br>~~eG~~||||||||
|2C<br>~~a~~<br>~~a~~|44<br>~~a~~<br>~~ss~~|I2CM_RD_DATA17<br>~~ee~~<br>~~ss~~|RWS<br>~~eG~~<br>~~es~~|I2CM_RD_DATA17<br>~~eG~~||||||||
|2D<br>~~a ~~<br>~~a~~|45<br> ~~a ~~<br>~~ss~~|I2CM_RD_DATA18<br> ~~ee~~<br>~~ss~~|RWS<br>~~eG~~<br>~~es~~|I2CM_RD_DATA18<br>~~eG~~||||||||



Page 61 of 191 

Document Number: DS-000576 Revision: 1.0 

_**ICM-45605**_ 

|**Addr**<br>**(Hex)**|**Addr**<br>**(Dec.)**|**Register Name**|**Serial**<br>**I/F**|**Bit7**|**Bit6**|**Bit5**|**Bit4**|**Bit3**|**Bit2**|**Bit1**|**Bit0**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|2E<br>~~eT~~|46<br>~~eT~~|I2CM_RD_DATA19<br>~~eT~~|RWS<br>~~eT~~|I2CM_RD_DATA19<br>~~eT~~||||||||
|2F<br>~~eT~~|47<br>~~eT~~|I2CM_RD_DATA20<br>~~eT~~|RWS<br>~~eT~~|I2CM_RD_DATA20<br>~~eT~~||||||||
|33<br>~~ee~~|51<br>~~ee~~|I2CM_WR_DATA0<br>~~ee~~|R/W<br>~~ee~~|I2CM_WR_DATA0<br>~~ee~~||||||||
|34<br>~~ee~~|52<br>~~ee~~|I2CM_WR_DATA1<br>~~ee~~|R/W<br>~~ee~~|I2CM_WR_DATA1<br>~~ee~~||||||||
|35<br>~~ee~~|53<br>~~ee~~|I2CM_WR_DATA2<br>~~ee~~|R/W<br>~~ee~~|I2CM_WR_DATA2<br>~~ee~~||||||||
|36<br>~~ee~~|54<br>~~ee~~|I2CM_WR_DATA3<br>~~ee~~|R/W<br>~~ee~~|I2CM_WR_DATA3<br>~~ee~~||||||||
|37<br>~~eT~~|55<br>~~eT~~|I2CM_WR_DATA4<br>~~eT~~|R/W<br>~~eT~~|I2CM_WR_DATA4<br>~~eT~~||||||||
|38<br>~~eT~~|56<br>~~eT~~|I2CM_WR_DATA5<br>~~eT~~|R/W<br>~~eT~~|I2CM_WR_DATA5<br>~~eT~~||||||||
|4B<br>~~a~~|75<br>~~a~~|SIFS_IXC_ERROR_STATUS<br>~~a ee~~|R/C<br>~~ee~~|-<br>~~ee~~||||||AUX1_SIFS_I<br>XC_TIMEOUT<br>_ERR<br>~~ee~~|SIFS_IXC_TIM<br>EOUT_ERR<br>~~ee~~|
|4F<br>~~Ge~~|79<br>~~Ge~~|EDMP_PRGRM_IRQ0_0<br>~~Ge~~|R/W<br>~~Ge~~|PRGRM_STRT_ADDR_IRQ_0[7:0]<br>~~Ge~~||||||||
|50<br>~~eT~~|80<br>~~eT~~|EDMP_PRGRM_IRQ0_1<br>~~eT~~|R/W<br>~~eT~~|PRGRM_STRT_ADDR_IRQ_0[15:8]<br>~~eT~~||||||||
|51<br>~~eT~~|81<br>~~eT~~|EDMP_PRGRM_IRQ1_0<br>~~eT~~|R/W<br>~~eT~~|PRGRM_STRT_ADDR_IRQ_1[7:0]<br>~~eT~~||||||||
|52<br>~~eT~~|82<br>~~eT~~|EDMP_PRGRM_IRQ1_1<br>~~eT~~|R/W<br>~~eT~~|PRGRM_STRT_ADDR_IRQ_1[15:8]<br>~~eT~~||||||||
|53<br>~~eT~~|83<br>~~eT~~|EDMP_PRGRM_IRQ2_0<br>~~eT~~|R/W<br>~~eT~~|PRGRM_STRT_ADDR_IRQ_2[7:0]<br>~~eT~~||||||||
|54<br>~~eT~~<br>~~eT~~|84<br>~~eT~~<br>~~eT~~|EDMP_PRGRM_IRQ2_1<br>~~eT~~<br>~~eT~~|R/W<br>~~eT~~<br>~~eT~~|PRGRM_STRT_ADDR_IRQ_2[15:8]<br>~~eT~~<br>~~eT~~||||||||
|55<br>~~eT~~<br>~~ee~~<br>~~a~~|85<br>~~eT~~<br>~~ee~~<br>~~a~~|EDMP_SP_START_ADDR<br>~~eT~~<br>~~ee~~<br>~~a~~|R/W<br>~~eT~~<br>~~ee~~<br>|EDMP_SP_START_ADDR<br>~~eT~~<br>~~ee~~<br>~~ee~~<br>||||||||
|58<br>~~eT~~<br>~~ee~~<br>~~a~~|88<br>~~eT~~<br>~~ee~~<br>~~a~~|SMC_CONTROL_0<br>~~eT~~<br>~~ee~~<br>~~a~~|R/W<br>~~eT~~<br>~~ee~~<br>|-<br>~~eT~~<br>~~ee~~<br>|||ACCEL_LP_CL<br>K_SEL<br>~~eT~~<br>~~ee~~<br>|TEMP_DIS<br>~~eT~~<br>~~ee~~<br>|TMST_FORCE<br>_AUX_FINE_E<br>N<br>~~eT~~<br>~~ee~~<br>~~ee~~<br>|TMST_FSYNC<br>_EN<br>~~eT~~<br>~~ee~~<br>~~ee~~<br>|TMST_EN<br>~~eT~~<br>~~ee~~<br>~~ee~~<br>|
|59<br>~~ee~~<br>~~a~~|89<br>~~ee~~<br>~~a~~|SMC_CONTROL_1<br>~~ee~~<br>~~a ee~~|R/W<br>~~ee~~<br>~~ee~~|-<br>~~ee~~<br>~~ee~~||||SREG_AUX_A<br>CCEL_ONLY_<br>EN<br>~~ee~~<br>~~ee~~|-<br>~~ee~~<br>~~ee~~<br>~~ee~~|||
|63<br>~~a~~<br>~~a~~|99<br>~~a~~<br>~~a~~|STC_CONFIG<br>~~a ee~~<br>~~a~~|R/W<br>~~ee~~|-<br>~~ee~~||||STC_SENSOR_SEL<br>~~ee~~<br>~~ee~~||-<br>~~ee~~<br>~~ee~~||
|67<br>~~a~~|103<br>~~a~~|SREG_CTRL<br>~~a~~|R/W|-||||||SREG_DATA_<br>ENDIAN_SEL|-|
|68<br>~~a~~|104<br>~~a~~|SIFS_I3C_STC_CFG<br>~~a~~|R/W|-|||||I3C_STC_MO<br>DE|-||
|69<br>~~es~~|105<br>~~es~~|INT_PULSE_MIN_ON_INTF0<br>~~es~~|R/W<br>~~es~~|-<br>~~es~~|||||INT0_TPULSE_DURATION<br>~~es~~|||
|6A<br>~~es~~|106<br>~~es~~|INT_PULSE_MIN_ON_INTF1<br>~~es~~|R/W<br>~~es~~|-<br>~~es~~|||||INT1_TPULSE_DURATION<br>~~es~~|||
|6B<br>~~es~~|107<br>~~es~~|INT_PULSE_MIN_OFF_INTF0<br>~~es~~|R/W<br>~~es~~|-<br>~~es~~|||||INT0_TDEASSERT_DISABLE<br>~~es~~|||
|6C<br>~~es~~<br>~~ee~~|108<br>~~es~~<br>~~ee~~|INT_PULSE_MIN_OFF_INTF1<br>~~es~~<br>~~ee~~|R/W<br>~~es~~<br>~~ee~~|-<br>~~es~~<br>~~ee~~|||||INT1_TDEASSERT_DISABLE<br>~~es~~<br>~~ee~~|||
|6E<br>~~ee~~<br>~~re~~|110<br>~~ee~~<br>~~re~~|ISR_0_7<br>~~ee~~<br>~~re~~|R/C<br>~~ee~~|-<br>~~ee~~<br>~~eee~~||INT_STATUS_<br>ON_DEMAN<br>D_PIN_0<br>~~ee~~<br>~~eee~~|-<br>~~ee~~<br>~~ee~~|INT_STATUS_<br>EXT_ODR_DR<br>DY_PIN_0<br>~~ee~~<br>~~ee~~|-<br>~~ee~~<br>~~eee~~||INT_STATUS_<br>ACCEL_DRDY<br>_PIN_0<br>~~ee~~<br>~~eee~~|
|6F<br>~~ee~~<br>~~re~~<br>~~ee~~|111<br>~~ee~~<br>~~re~~<br>~~ee~~|ISR_8_15<br>~~ee~~<br>~~re~~<br>~~ee~~|R/C<br>~~ee~~<br>~~eee~~|-<br>~~ee~~<br>~~eee~~<br>~~eee~~||INT_STATUS_<br>ON_DEMAN<br>D_PIN_1<br>~~ee~~<br>~~eee~~<br>~~eee~~|-<br>~~ee~~<br>~~ee~~<br>~~eee~~|INT_STATUS_<br>EXT_ODR_DR<br>DY_PIN_1<br>~~ee~~<br>~~ee~~<br>~~eee~~|-<br>~~ee~~<br>~~eee~~<br>~~eee~~||INT_STATUS_<br>ACCEL_DRDY<br>_PIN_1<br>~~ee~~<br>~~eee~~<br>~~eee~~|
|70<br>~~re~~<br>~~ee~~|112<br>~~re~~<br>~~ee~~|ISR_16_23<br>~~re~~<br>~~ee~~|R/C<br>~~eee~~|-<br>~~eee~~<br>~~eee~~||INT_STATUS_<br>ON_DEMAN<br>D_PIN_2<br>~~eee ~~<br>~~eee~~|-<br> ~~ee~~<br>~~eee~~|INT_STATUS_<br>EXT_ODR_DR<br>DY_PIN_2<br>~~ee ~~<br>~~eee~~|-<br> ~~eee~~<br>~~eee~~||INT_STATUS_<br>ACCEL_DRDY<br>_PIN_2<br>~~eee~~<br>~~eee~~|
|71<br>~~ee~~<br>~~a~~<br>~~re~~|113<br>~~ee~~<br>~~a~~<br>~~re~~|STATUS_MASK_PIN_0_7<br>~~ee~~<br>~~a~~<br>~~re~~|R/W<br>~~eee~~<br>~~ee~~|-<br>~~eee~~<br>~~ee~~<br>~~eee~~||INT_ON_DE<br>MAND_PIN_<br>0_DIS<br>~~eee~~<br>~~ee~~<br>~~eee~~|-<br>~~eee~~<br>~~ee~~<br>~~ee~~|INT_EXT_OD<br>R_DRDY_PIN<br>_0_DIS<br>~~eee~~<br>~~ee~~<br>~~ee~~|-<br>~~eee~~<br>~~ee~~<br>~~eee~~||INT_ACCEL_D<br>RDY_PIN_0_<br>DIS<br>~~eee~~<br>~~ee~~<br>~~eee~~|
|72<br>~~a~~<br>~~re~~<br>~~ee~~|114<br>~~a~~<br>~~re~~<br>~~ee~~|STATUS_MASK_PIN_8_15<br>~~a ~~<br>~~re~~<br>~~ee~~|R/W<br> ~~ee~~<br>~~eee~~|-<br>~~ee~~<br>~~eee~~<br>~~eee~~||INT_ON_DE<br>MAND_PIN_<br>1_DIS<br>~~ee~~<br>~~eee~~<br>~~eee~~|-<br>~~ee~~<br>~~ee~~<br>~~eee~~|INT_EXT_OD<br>R_DRDY_PIN<br>_1_DIS<br>~~ee~~<br>~~ee~~<br>~~eee~~|-<br>~~ee~~<br>~~eee~~<br>~~eee~~||INT_ACCEL_D<br>RDY_PIN_1_<br>DIS<br>~~ee~~<br>~~eee~~<br>~~eee~~|
|73<br>~~re~~<br>~~ee~~|115<br>~~re~~<br>~~ee~~|STATUS_MASK_PIN_16_23<br>~~re~~<br>~~ee~~|R/W<br>~~eee~~|-<br>~~eee~~<br>~~eee~~||INT_ON_DE<br>MAND_PIN_<br>2_DIS<br>~~eee ~~<br>~~eee~~|-<br> ~~ee~~<br>~~eee~~|INT_EXT_OD<br>R_DRDY_PIN<br>_2_DIS<br>~~ee ~~<br>~~eee~~|-<br> ~~eee~~<br>~~eee~~||INT_ACCEL_D<br>RDY_PIN_2_<br>DIS<br>~~eee~~<br>~~eee~~|
|74<br>~~ee~~<br>~~ee~~|116<br>~~ee~~<br>~~ee~~|INT_I2CM_SOURCE<br>~~ee~~<br>~~ee ee~~|R/W<br>~~eee~~<br>~~ee~~|-<br>~~eee~~<br>~~ee~~||||||INT_STATUS_<br>I2CM_SMC_E<br>XT_ODR_EN<br>~~eee~~<br>~~ee~~|-<br>~~eee~~<br>~~ee~~|
|7E<br>~~a~~|126<br>~~a~~|ACCEL_WOM_X_THR<br>~~a~~|R/W<br>~~a~~|WOM_X_TH<br>~~a~~||||||||
|7F<br>~~a~~|127<br>~~a~~|ACCEL_WOM_Y_THR<br>~~a~~|R/W<br>~~a~~|WOM_Y_TH<br>~~a~~||||||||
|80<br>~~ee~~|128<br>~~ee~~|ACCEL_WOM_Z_THR<br>~~ee~~|R/W<br>~~ee~~|WOM_Z_TH<br>~~ee~~||||||||
|90<br>~~ee~~|144<br>~~ee~~|SELFTEST<br>~~ee~~|~~ee~~|-<br>~~ee~~||EN_GZ_ST<br>~~ee~~|EN_GY_ST<br>~~ee~~|EN_GX_ST<br>~~ee~~|EN_AZ_ST<br>~~ee~~|EN_AY_ST<br>~~ee~~|EN_AX_ST<br>~~ee~~|
|97|151|IPREG_MISC|R|-||||||EDMP_IDLE|-|
|A2|162|SW_PLL1_TRIM|R|SW_PLL1_TRIM||||||||



Page 62 of 191 

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_**ICM-45605**_ 

|**Addr**<br>**(Hex)**|**Addr**<br>**(Dec.)**|**Register Name**|**Serial**<br>**I/F**|**Bit7**|**Bit6**|**Bit5**|**Bit4**|**Bit3**|**Bit2**|**Bit1**|**Bit0**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|A7|167|FIFO_SRAM_SLEEP|R/W|-||||||FIFO_GSLEEP_SHARED_SRAM||



## **16.5 USER BANK IPREG_SYS1 REGISTER MAP** 

|**Addr**<br>**(Hex)**<br>~~|~~|**Addr**<br>**(Dec.)**|**Register Name**|**Serial**<br>**I/F**|**Bit7**|**Bit6**|**Bit5**|**Bit4**|**Bit3**|**Bit2**|**Bit1**|**Bit0**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|2A<br>~~a ~~<br>~~a~~<br>~~a~~|42<br> ~~a~~<br>~~ss~~|IPREG_SYS1_REG_42<br>~~es~~<br>~~ss~~|R/W<br>~~es~~<br>~~es~~|GYRO_X_OFFUSER[7:0]||||||||
|2B<br> <br>~~a ~~<br>~~a~~|43<br> ~~a ~~<br> ~~ss~~|IPREG_SYS1_REG_43<br> ~~es~~<br>~~ss~~|R/W<br>~~es~~<br>~~es~~|-||GYRO_X_OFFUSER[13:8]||||||
|38<br> <br>~~a~~<br>~~a~~|56<br> ~~ss~~<br>~~a~~<br>~~ss~~|IPREG_SYS1_REG_56<br>~~ss~~<br>~~ss~~<br>~~ss es~~|R/W<br>~~es~~<br>~~ss~~<br>~~es~~|GYRO_Y_OFFUSER[7:0]||||||||
|39<br>~~a~~|57<br>~~ss~~|IPREG_SYS1_REG_57<br>~~ss es~~|R/W<br>~~es~~|-||GYRO_Y_OFFUSER[13:8]||||||
|46<br>~~a ~~<br>~~a~~<br>~~a~~|70<br> ~~ss~~<br>~~a~~<br>~~ss~~|IPREG_SYS1_REG_56<br>~~ss es~~<br>~~ss~~<br>~~ss es~~|R/W<br>~~es~~<br>~~ss~~<br>~~es~~|GYRO_Z_OFFUSER[7:0]||||||||
|47<br>~~a~~|71<br>~~ss~~|IPREG_SYS1_REG_57<br>~~ss es~~|R/W<br>~~es~~|-||GYRO_Z_OFFUSER[13:8]||||||
|A6<br>~~a ~~<br>~~a~~<br>~~a~~|166<br> ~~ss~~<br>~~a~~|IPREG_SYS1_REG_166<br>~~ss es~~<br>~~ss~~<br>~~es es~~|R/W<br>~~es~~<br>~~ss~~<br>~~es~~|-<br>~~De~~|GYRO_SRC_CTRL<br>~~De~~||-<br>~~De~~|||||
|AA<br>~~a~~<br>~~a~~|170<br>~~a~~<br>~~a~~|IPREG_SYS1_REG_170<br>~~es es~~<br>~~ee es~~|R/W<br>~~es~~<br>~~es~~|-<br>~~De~~<br>~~me~~|||GYRO_LP_AVG_SEL<br>~~De~~||||-<br>~~De~~|
|AC<br>~~a~~<br>~~a~~|172<br>~~a~~<br>~~a~~|IPREG_SYS1_REG_172<br>~~es es~~<br>~~ee es~~|R/W<br>~~es~~<br>~~es~~|-<br>~~De~~<br>~~me~~|||||GYRO_UI_LPFBW_SEL<br>~~De~~|||



## **16.6 USER BANK IPREG_SYS2 REGISTER MAP** 

|**Addr**<br>**(Hex)**<br>~~|~~|**Addr**<br>**(Dec.)**|**Register Name**|**Serial**<br>**I/F**|**Bit7**|**Bit6**|**Bit5**|**Bit4**|**Bit3**|**Bit2**|**Bit1**|**Bit0**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|18<br>~~a ~~<br>~~a~~<br>~~a~~|24<br> ~~a~~<br>~~a~~|IPREG_SYS2_REG_24<br>~~es~~<br>~~es~~|R/W<br>~~es~~<br>~~es~~|ACCEL_X_OFFUSER[7:0]||||||||
|19<br> <br>~~a ~~<br>~~a~~<br>~~a~~|25<br> ~~a ~~<br> ~~a~~|IPREG_SYS2_REG_25<br> ~~es~~<br>~~es~~<br>~~es~~|R/W<br>~~es~~<br>~~es~~<br>~~es~~|-||ACCEL_X_OFFUSER[13:8]||||||
|20<br> <br>~~a~~<br>~~a~~<br>~~a~~|32<br> ~~a~~|IPREG_SYS2_REG_32<br>~~es~~<br>~~es~~<br>~~es~~|R/W<br>~~es~~<br>~~es~~<br>~~es~~|ACCEL_Y_OFFUSER[7:0]||||||||
|21<br>~~a~~<br>~~a~~<br>~~a~~|33|IPREG_SYS2_REG_33<br>~~es~~<br>~~es~~<br>~~es~~|R/W<br>~~es~~<br>~~es~~<br>~~es~~|-||ACCEL_Y_OFFUSER[13:8]||||||
|28<br>~~a~~<br>~~a~~|40|IPREG_SYS2_REG_40<br>~~es~~<br>~~es~~|R/W<br>~~es~~<br>~~es~~|ACCEL_Z_OFFUSER[7:0]||||||||
|29<br>~~a~~<br>~~a~~|41|IPREG_SYS2_REG_41<br>~~es~~<br>~~ss~~<br>~~es~~|R/W<br>~~es~~<br>~~ss~~<br>~~es~~|-||ACCEL_Z_OFFUSER[13:8]||||||
|7B<br>~~a~~|123|IPREG_SYS2_REG_123<br>~~es~~|R/W<br>~~es~~|-||||||ACCEL_SRC_CTRL||
|81<br>~~a~~<br>~~a~~<br>~~a~~|129<br>~~a~~<br>~~ss~~|IPREG_SYS2_REG_129<br>~~es~~<br>~~eG~~<br>~~ss es~~|R/W<br>~~es~~<br>~~eG~~<br>~~es~~|-<br>~~eG~~||||ACCEL_LP_AVG_SEL<br>~~eG~~||||
|83<br>~~a ~~<br>~~a~~|131<br> ~~a~~<br>~~ss~~|IPREG_SYS2_REG_131<br>~~eG~~<br>~~ss es~~|R/W<br>~~eG~~<br>~~es~~|-<br>~~eG~~|||||ACCEL_UI_LPFBW_SEL<br>~~eG~~|||



Detailed register descriptions are provided in the sections that follow. 

Register fields marked as Reserved must not be modified by the user. The Reset Value of the register can be used to determine the default value of reserved register fields, and unless otherwise noted this default value must be maintained even if the values of other register fields are modified by the user. 

In the sections that follow, some register fields are described as “can be changed on-the-fly.” These are the only register fields that can be changed on-the-fly even if sensor is on. Register fields not described as such must not be changed on-the-fly if sensor is on. 

Page 63 of 191 

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_**ICM-45605**_ 

## _**17 USER BANK 0 REGISTER MAP – DESCRIPTIONS**_ 

Please refer to the procedure in Section 14 for configuring device data endianness before using the register map. 

**17.1 ACCEL_DATA_X1_UI** Name: ACCEL_DATA_X1_UI Address: 00 (00h) Serial IF: SYNCR Reset value: 0x00 Clock Domain: SCLK **BIT NAME FUNCTION** ~~—————~~ 7:0 ACCEL_DATA_X_UI[15:8] Upper byte of Accel X-axis data for UI path **17.2 ACCEL_DATA_X0_UI** Name: ACCEL_DATA_X0_UI Address: 01 (01h) Serial IF: SYNCR Reset value: 0x00 Clock Domain: SCLK **BIT NAME FUNCTION** ~~——————~~ 7:0 ACCEL_DATA_X_UI[7:0] Lower byte of Accel X-axis data for UI path **17.3 ACCEL_DATA_Y1_UI** Name: ACCEL_DATA_Y1_UI Address: 02 (02h) Serial IF: SYNCR Reset value: 0x00 Clock Domain: SCLK **BIT NAME FUNCTION** ~~———~~ 7:0 ACCEL_DATA_Y_UI[15:8] Upper byte of Accel Y-axis data for UI path **17.4 ACCEL_DATA_Y0_UI** Name: ACCEL_DATA_Y0_UI Address: 03 (03h) Serial IF: SYNCR Reset value: 0x00 Clock Domain: SCLK **BIT NAME FUNCTION** ~~——————~~ 7:0 ACCEL_DATA_Y_UI[7:0] Lower byte of Accel Y-axis data for UI path 

**17.5 ACCEL_DATA_Z1_UI** 

Name: ACCEL_DATA_Z1_UI Address: 04 (04h) Serial IF: SYNCR Reset value: 0x00 Clock Domain: SCLK **BIT NAME FUNCTION** ~~———~~ 7:0 ACCEL_DATA_Z_UI[15:8] Upper byte of Accel Z-axis data for UI path Page 64 of 191 Document Number: DS-000576 Revision: 1.0 

_**ICM-45605**_ 

**17.6 ACCEL_DATA_Z0_UI** 

Name: ACCEL_DATA_Z0_UI Address: 05 (05h) Serial IF: SYNCR Reset value: 0x00 Clock Domain: SCLK **BIT NAME FUNCTION** ~~—————~~ 7:0 ACCEL_DATA_Z_UI[7:0] Lower byte of Accel Z-axis data for UI path **17.7 GYRO_DATA_X1_UI** Name: GYRO_DATA_X1_UI Address: 06 (06h) Serial IF: SYNCR Reset value: 0x00 Clock Domain: SCLK **BIT NAME FUNCTION** ~~—————~~ 7:0 GYRO_DATA_X_UI[15:8] Upper byte of Gyro X-axis data for UI path **17.8 GYRO_DATA_X0_UI** Name: GYRO_DATA_X0_UI Address: 07 (07h) Serial IF: SYNCR Reset value: 0x00 Clock Domain: SCLK **BIT NAME FUNCTION** ~~————~~ 7:0 GYRO_DATA_X_UI[7:0] Lower byte of Gyro X-axis data for UI path **17.9 GYRO_DATA_Y1_UI** Name: GYRO_DATA_Y1_UI Address: 08 (08h) Serial IF: SYNCR Reset value: 0x00 Clock Domain: SCLK **BIT NAME FUNCTION** ~~—————~~ 7:0 GYRO_DATA_Y_UI[15:8] Upper byte of Gyro Y-axis data for UI path 

**17.10 GYRO_DATA_Y0_UI** 

Name: GYRO_DATA_Y0_UI Address: 09 (09h) Serial IF: SYNCR Reset value: 0x00 Clock Domain: SCLK **BIT NAME FUNCTION** ~~———~~ 7:0 GYRO_DATA_Y_UI[7:0] Lower byte of Gyro Y-axis data for UI path 

Page 65 of 191 

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_**ICM-45605**_ 

## **17.11 GYRO_DATA_Z1_UI** 

Name: GYRO_DATA_Z1_UI Address: 10 (0Ah) Serial IF: SYNCR Reset value: 0x00 Clock Domain: SCLK **BIT NAME FUNCTION** 7:0 GYRO_DATA_Z_UI[15:8] Upper byte of Gyro Z-axis data for UI path 

## **17.12 GYRO_DATA_Z0_UI** 

Name: GYRO_DATA_Z0_UI Address: 11 (0Bh) Serial IF: SYNCR Reset value: 0x00 Clock Domain: SCLK **BIT NAME FUNCTION** 7:0 GYRO_DATA_Z_UI[7:0] Lower byte of Gyro Z-axis data for UI path 

## **17.13 TEMP_DATA1_UI** 

Name: TEMP_DATA1_UI Address: 12 (0Ch) Serial IF: SYNCR Reset value: 0x00 Clock Domain: SCLK **BIT NAME FUNCTION** 7:0 TEMP_DATA_UI[15:8] Upper byte of temperature data for UI path 

## **17.14 TEMP_DATA0_UI** 

Name: TEMP_DATA0_UI Address: 13 (0Dh) Serial IF: SYNCR Reset value: 0x00 Clock Domain: SCLK **BIT NAME FUNCTION** 7:0 TEMP_DATA_UI[7:0] Lower byte of temperature data for UI path 

Temperature data value from the sensor data registers can be converted to degrees centigrade by using the following formula: 

Temperature in Degrees Centigrade = (TEMP_DATA / 128) + 25 

Temperature data stored in FIFO is an 8-bit quantity, FIFO_TEMP_DATA.  It can be converted to degrees centigrade by using the following formula: 

Temperature in Degrees Centigrade = (FIFO_TEMP_DATA / 2) + 25 

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_**ICM-45605**_ 

## **17.15 TMST_FSYNCH** 

|**17.15 TMST_FSYNCH**|**17.15 TMST_FSYNCH**|**17.15 TMST_FSYNCH**|
|---|---|---|
|Name: TMST_FSYNCH<br>Address: 14 (0Eh)<br>Serial IF: SYNCR<br>Reset value: 0x00<br>Clock Domain: SCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7:0|TMST_FSYNC_DATA_UI[15:8]|Stores the upper byte of the time delta from the rising edge of FSYNC to<br>the latest ODR until the UI Interface reads the FSYNC tag in the status<br>register|



## **17.16 TMST_FSYNCL** 

|**17.16 TMST_FSYNCL**|**17.16 TMST_FSYNCL**|**17.16 TMST_FSYNCL**|
|---|---|---|
|Name: TMST_FSYNCL<br>Address: 15 (0Fh)<br>Serial IF: SYNCR<br>Reset value: 0x00<br>Clock Domain: SCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7:0|TMST_FSYNC_DATA_UI[7:0]|Stores the lower byte of the time delta from the rising edge of FSYNC to<br>the latest ODR until the UI Interface reads the FSYNC tag in the status<br>register|



## **17.17 PWR_MGMT0** 

Name: PWR_MGMT0 Address: 16 (10h) Serial IF: R/W Reset value: 0x00 Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|7:4|-|Reserved|
|||00: Turns gyroscope off|
|||01: Places gyroscope in Standby Mode|
|3:2|GYRO_MODE|10: Places gyroscope in Low Power (LP) Mode<br>11: Places gyroscope in Low Noise (LN) Mode|
|||Can be changed on-the-fly.|
|||00: Turns accelerometer off|
|||01: Turns accelerometer off|
|1:0|ACCEL_MODE|10: Places accelerometer in Low Power (LP) Mode<br>11: Places accelerometer in Low Noise (LN) Mode|
|||Can be changed on-the-fly.|



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## **17.18 FIFO_COUNT_0** 

Name: FIFO_COUNT_0 Address: 18 (12h) Serial IF: R Reset value: 0x00 Clock Domain: SCLK **BIT NAME FUNCTION** 7:0 FIFO_DATA_CNT[15:8] High Bits, count indicates the number of packets available in FIFO. 

## **17.19 FIFO_COUNT_1** 

Name: FIFO_COUNT_1 Address: 19 (13h) Serial IF: R Reset value: 0x00 Clock Domain: SCLK **BIT NAME FUNCTION** 7:0 FIFO_DATA_CNT[7:0] Low Bits, count indicates the number of packets available in FIFO. 

## **17.20 FIFO_DATA** 

Name: FIFO_DATA Address: 20 (14h) Serial IF: R Reset value: 0x7F Clock Domain: SCLK **BIT NAME FUNCTION** 7:0 FIFO_DATA FIFO data port 

Page 68 of 191 

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## **17.21 INT1_CONFIG0** 

|**17.21 INT1_CONFIG0**|**17.21 INT1_CONFIG0**|**17.21 INT1_CONFIG0**|
|---|---|---|
|Name: INT1_CONFIG0<br>Address: 22 (16h)<br>Serial IF: R/W<br>Reset value: 0x80<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7|INT1_STATUS_EN_RESET_<br>DONE|Enable interrupt status bit to flag the occurrence of Reset Done event on<br>INT1<br>0: Disable interrupt.<br>1: Enable interrupt.<br>Settingcan be changed byUI interface.|
|6|INT1_STATUS_EN_AUX1_A<br>GC_RDY|Enable interrupt status bit to flag the occurrence of AUX1 AGC Ready event<br>on INT1<br>0: Disable interrupt.<br>1: Enable interrupt.<br>Settingcan be changed byUI interface.|
|5|INT1_STATUS_EN_AP_AGC<br>_RDY|Enable interrupt status bit to flag the occurrence of UI AGC Ready event on<br>INT1<br>0: Disable interrupt.<br>1: Enable interrupt.<br>Settingcan be changed byUI interface.|
|4|INT1_STATUS_EN_AP_FSY<br>NC|Enable interrupt status bit to flag the occurrence of UI FSYNC event on INT1<br>0: Disable interrupt.<br>1: Enable interrupt.<br>Settingcan be changed byUI interface.|
|3|INT1_STATUS_EN_AUX1_D<br>RDY|Enable interrupt status bit to flag the occurrence of AUX1 Data Ready event<br>on INT1<br>0: Disable interrupt.<br>1: Enable interrupt.<br>Settingcan be changed byUI interface.|
|2|INT1_STATUS_EN_DRDY|Enable interrupt status bit to flag the occurrence of UI Data Ready event on<br>INT1<br>0: Disable interrupt.<br>1: Enable interrupt.<br>Settingcan be changed byUI interface.|
|1|INT1_STATUS_EN_FIFO_TH<br>S|Enable interrupt status bit to flag the occurrence of FIFO count ≥ FIFO<br>threshold event on INT1|



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|||<br>**_ICM-45605_**|
|---|---|---|
|||0: Disable interrupt.<br>1: Enable interrupt.<br>Settingcan be changed byUI interface.|
|0|INT1_STATUS_EN_FIFO_FU<br>LL|Enable interrupt status bit to flag the occurrence of FIFO full event on INT1<br>0: Disable interrupt.<br>1: Enable interrupt.<br>Settingcan be changed byUI interface.|



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## **17.22 INT1_CONFIG1** 

|**17.22 INT1_CONFIG1**|**17.22 INT1_CONFIG1**|**17.22 INT1_CONFIG1**|
|---|---|---|
|Name: INT1_CONFIG1<br>Address: 23 (17h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7|-|Reserved|
|6|INT1_STATUS_EN_APEX_E<br>VENT|Enable interrupt status bit to flag the occurrence of APEX event on INT1<br>0: Disable interrupt.<br>1: Enable interrupt.<br>Settingcan be changed byUI interface.|
|5|INT1_STATUS_EN_I2CM_D<br>ONE|Enable interrupt status bit to flag the completion of I2C master event on INT1<br>0: Disable interrupt.<br>1: Enable interrupt.<br>Settingcan be changed byUI interface.|
|4|INT1_STATUS_EN_I3C_PRO<br>TOCOL_ERR|Enable interrupt status bit to flag the occurrence of I3C Protocol Error event<br>on INT1<br>0: Disable interrupt.<br>1: Enable interrupt.<br>Settingcan be changed byUI interface.|
|3|INT1_STATUS_EN_WOM_Z|Enable interrupt status bit to flag the occurrence of WOM on Z-axis event on<br>INT1<br>0: Disable interrupt.<br>1: Enable interrupt.<br>Settingcan be changed byUI interface.|
|2|INT1_STATUS_EN_WOM_Y|Enable interrupt status bit to flag the occurrence of WOM on Y-axis event on<br>INT1<br>0: Disable interrupt.<br>1: Enable interrupt.<br>Settingcan be changed byUI interface.|
|1|INT1_STATUS_EN_WOM_X|Enable interrupt status bit to flag the occurrence of WOM on X-axis event on<br>INT1<br>0: Disable interrupt.<br>1: Enable interrupt.<br>Settingcan be changed byUI interface.|
|0|INT1_STATUS_EN_PLL_RDY|Enable interrupt status bit to flag the occurrence of PLL Ready event on INT1<br>0: Disable interrupt.|



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1: Enable interrupt. Setting can be changed by UI interface. 

## **17.23 INT1_CONFIG2** 

Name: INT1_CONFIG2 Address: 24 (18h) Serial IF: R/W Reset value: 0x04 Clock Domain: MCLK 

|**17.23 INT1_CONFIG2**|**17.23 INT1_CONFIG2**|**17.23 INT1_CONFIG2**|
|---|---|---|
|Name: INT1_CONFIG2<br>Address: 24 (18h)<br>Serial IF: R/W<br>Reset value: 0x04<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7:3|-|Reserved|
|2|INT1_DRIVE|Sets INT1 to open-drain or push-pull<br>0: Push-pull<br>1: Open-drain|
|1|INT1_MODE|INT1 interrupt mode<br>0: Pulse mode<br>1: Latch mode<br>Setting can be changed only when all interrupts of the corresponding serial<br>interface are disabled|
|0|INT1_POLARITY|INT1 interrupt polarity<br>0: Active low<br>1: Active high<br>Setting can be changed only when all interrupts of the corresponding serial<br>interface are disabled|



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## **17.24 INT1_STATUS0** 

|**17.24 INT1_STATUS0**|**17.24 INT1_STATUS0**|**17.24 INT1_STATUS0**|
|---|---|---|
|Name: INT1_STATUS0<br>Address: 25 (19h)<br>Serial IF: R/C<br>Reset value: 0x00<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7|INT1_STATUS_RESET_DON<br>E|Flags the occurrence of Reset Done event on INT1<br>0: Interrupt did not occur<br>1: Interrupt occurred|
|6|INT1_STATUS_AUX1_AGC_<br>RDY|Flags the occurrence of AUX1 AGC Ready event on INT1<br>0: Interrupt did not occur<br>1: Interrupt occurred|
|5|INT1_STATUS_AP_AGC_RD<br>Y|Flags the occurrence of UI AGC Ready event on INT1<br>0: Interrupt did not occur<br>1: Interrupt occurred|
|4|INT1_STATUS_AP_FSYNC|Flags the occurrence of UI FSYNC event on INT1<br>0: Interrupt did not occur<br>1: Interrupt occurred|
|3|INT1_STATUS_AUX1_DRDY|Flags the occurrence of AUX1 Data Ready event on INT1<br>0: Interrupt did not occur<br>1: Interrupt occurred|
|2|INT1_STATUS_DRDY|Flags the occurrence of UI Data Ready event on INT1<br>0: Interrupt did not occur<br>1: Interrupt occurred|
|1|INT1_STATUS_FIFO_THS|Flags the occurrence of FIFO count ≥ FIFO threshold event on INT1<br>0: Interrupt did not occur<br>1: Interrupt occurred|
|0|INT1_STATUS_FIFO_FULL|Flags the occurrence of FIFO full event on INT1<br>0: Interrupt did not occur<br>1: Interrupt occurred|



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## **17.25 INT1_STATUS1** 

|**17.25 INT1_STATUS1**|**17.25 INT1_STATUS1**|**17.25 INT1_STATUS1**|
|---|---|---|
|Name: INT1_STATUS1<br>Address: 26 (1Ah)<br>Serial IF: R/C<br>Reset value: 0x00<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7|-|Reserved|
|6|INT1_STATUS_APEX_EVEN<br>T|Flags the occurrence of APEX event on INT1<br>0: Interrupt did not occur<br>1: Interrupt occurred|
|5|INT1_STATUS_I2CM_DONE|Flags the occurrence of I2C Master Done event on INT1<br>0: Interrupt did not occur<br>1: Interrupt occurred|
|4|INT1_STATUS_I3C_PROTO<br>COL_ERR|Flags the occurrence of I3CSMProtocol Error event on INT1<br>0: Interrupt did not occur<br>1: Interrupt occurred|
|3|INT1_STATUS_WOM_Z|Flags the occurrence of Z-axis WOM event on INT1<br>0: Interrupt did not occur<br>1: Interrupt occurred|
|2|INT1_STATUS_WOM_Y|Flags the occurrence of Y-axis WOM event on INT1<br>0: Interrupt did not occur<br>1: Interrupt occurred|
|1|INT1_STATUS_WOM_X|Flags the occurrence of X-axis WOM event on INT1<br>0: Interrupt did not occur<br>1: Interrupt occurred|
|0|INT1_STATUS_PLL_RDY|Flags the occurrence of PLL Ready event on INT1<br>0: Interrupt did not occur<br>1: Interrupt occurred|



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## **17.26 ACCEL_CONFIG0** 

|**17.26 ACCEL_CONFIG0**|**17.26 ACCEL_CONFIG0**|**17.26 ACCEL_CONFIG0**|
|---|---|---|
|Name: ACCEL_CONFIG0<br>Address: 27 (1Bh)<br>Serial IF: R/W<br>Reset value: 0x06<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7|-|Reserved|
|6:4|ACCEL_UI_FS_SEL|Full scale select for accelerometer UI interface output<br>000: Reserved<br>001: ±16g<br>010: ±8g<br>011: ±4g<br>100: ±2g<br>101: Reserved<br>110: Reserved<br>111: Reserved<br>Can be changed on-the-fly.|
|3:0|ACCEL_ODR|Accelerometer ODR selection for UI interface output<br>0000: Reserved<br>0001: Reserved<br>0010: Reserved<br>0011: 6.4kHz (LN mode)<br>0100: 3.2kHz (LN mode)<br>0101: 1.6kHz (LN mode)<br>0110: 800Hz (LN mode)<br>0111: 400Hz (LP or LN mode)<br>1000: 200Hz (LP or LN mode)<br>1001: 100Hz (LP or LN mode)<br>1010: 50Hz (LP or LN mode)<br>1011: 25Hz (LP or LN mode)<br>1100: 12.5Hz (LP or LN mode)<br>1101: 6.25Hz (LP mode)<br>1110: 3.125Hz (LP mode)<br>1111: 1.5625Hz (LP mode)<br>Can be changed on-the-fly.|



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## **17.27 GYRO_CONFIG0** 

|**17.27 GYRO_CONFIG0**|**17.27 GYRO_CONFIG0**|**17.27 GYRO_CONFIG0**|
|---|---|---|
|Name: GYRO_CONFIG0<br>Address: 28 (1Ch)<br>Serial IF: R/W<br>Reset value: 0x06<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7:4|GYRO_UI_FS_SEL|Full scale select for gyroscope UI interface output<br>0000: Reserved<br>0001: ±2000dps<br>0010: ±1000dps<br>0011: ±500dps<br>0100: ±250dps<br>0101: ±125dps<br>0110: ±62.5dps<br>0111: ±31.25dps<br>1000: ±15.625dps<br>Rest of the settings are reserved<br>Can be changed on-the-fly.|
|3:0|GYRO_ODR|Gyroscope ODR selection for UI interface output<br>0000: Reserved<br>0001: Reserved<br>0010: Reserved<br>0011: 6.4kHz (LN mode)<br>0100: 3.2kHz (LN mode)<br>0101: 1.6kHz (LN mode)<br>0110: 800Hz (LN mode)<br>0111: 400Hz (LP or LN mode)<br>1000: 200Hz (LP or LN mode)<br>1001: 100Hz (LP or LN mode)<br>1010: 50Hz (LP or LN mode)<br>1011: 25Hz (LP or LN mode)<br>1100: 12.5Hz (LP or LN mode)<br>1101: 6.25Hz (LP mode)<br>1110: 3.125Hz (LP mode)<br>1111: 1.5625Hz (LP mode)<br>Can be changed on-the-fly.|



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## **17.28 FIFO_CONFIG0** 

|**17.28 FIFO_CONFIG0**|**17.28 FIFO_CONFIG0**|**17.28 FIFO_CONFIG0**|
|---|---|---|
|Name: FIFO_CONFIG0<br>Address: 29 (1Dh)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7:6|FIFO_MODE|Set the FIFO operation mode.<br>00: Bypass (disabled)<br>01: Stream mode - Frames are overwritten when the FIFO full condition is<br>reached. Supported only for 8, 16, 20 bytes frame size. When this mode is<br>selected for 32 or 64 bytes frame sizes, FIFO remains in Bypass mode.<br>10: Stop-on-full mode - Frames are not stored in FIFO once the FIFO full<br>condition is reached.<br>11: Reserved<br>Can be changed on-the-fly.|
|5:0|FIFO_DEPTH|Set the FIFO depth in bytes.<br>000111: Sets FIFO depth to 2K bytes (recommended setting)<br>011111: Sets FIFO depth to 8K bytes (valid when all APEX features are<br>disabled)<br>Others: Reserved<br>Can be changed when FIFO is disabled(Bypass mode).|



## **17.29 FIFO_CONFIG1_0** 

|**17.29 FIFO_CONFIG1_0**|**17.29 FIFO_CONFIG1_0**|**17.29 FIFO_CONFIG1_0**|
|---|---|---|
|Name: FIFO_CONFIG1_0<br>Address: 30 (1Eh)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7:0|FIFO_WM_TH[7:0]|Lower bits of FIFO watermark threshold. When set to 0, the watermark is<br>disabled. When writing new threshold value, user must first write<br>threshold LSByte (bits [7:0]), then MSByte (bits [15:8]). New threshold<br>register value will take effect only when MSByte is written.<br>Can be changed on-the-fly.|



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## **17.30 FIFO_CONFIG1_1** 

|**17.30 FIFO_CONFIG1_1**|**17.30 FIFO_CONFIG1_1**|**17.30 FIFO_CONFIG1_1**|
|---|---|---|
|Name: FIFO_CONFIG1_1<br>Address: 31 (1Fh)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7:0|FIFO_WM_TH[15:8]|Upper bits of FIFO watermark threshold. When set to 0, the watermark is<br>disabled. When writing new threshold value, user must first write<br>threshold LSByte (bits [7:0]), then MSByte (bits [15:8]). New threshold<br>register value will take effect only when MSByte is written.<br>Can be changed on-the-fly.|



## **17.31 FIFO_CONFIG2** 

Name: FIFO_CONFIG2 Address: 32 (20h) Serial IF: R/W Reset value: 0x20 Clock Domain: MCLK 

|**17.31 FIFO_CONFIG2**|**17.31 FIFO_CONFIG2**|**17.31 FIFO_CONFIG2**|
|---|---|---|
|Name: FIFO_CONFIG2<br>Address: 32 (20h)<br>Serial IF: R/W<br>Reset value: 0x20<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7|FIFO_FLUSH|FIFO flush command. When set high the FIFO is flushed, meaning the<br>pointers and control logic is reset. Configuration registers are not reset.<br>Can be changed on-the-fly.|
|6:4|-|Reserved|
|3|FIFO_WR_WM_GT_TH|Set write watermark interrupt generating condition:<br>0: Write watermark interrupt generated when FIFO data count is equal to<br>the FIFO watermark threshold<br>1: Write watermark interrupt generated when FIFO data count is greater<br>than or equal to FIFO watermark threshold<br>Can be changed when FIFO is disabled(Bypass mode).|
|2:0|-|Reserved|



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## **17.32 FIFO_CONFIG3** 

|**17.32 FIFO_CONFIG3**|**17.32 FIFO_CONFIG3**|**17.32 FIFO_CONFIG3**|
|---|---|---|
|Name: FIFO_CONFIG3<br>Address: 33 (21h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7:6|-|Reserved|
|5|FIFO_ES1_EN|Enable External Sensor 1 data insertion into FIFO frame|
|4|FIFO_ES0_EN|Enable External Sensor 0 data insertion into FIFO frame|
|3|FIFO_HIRES_EN|Enable high resolution accel andgyro data insertion into FIFO frame|
|2|FIFO_GYRO_EN|Enablegyro data insertion into FIFO frame|
|1|FIFO_ACCEL_EN|Enable accel data insertion into FIFO frame|
|0|FIFO_IF_EN|Enable Sensor Registers write interface to FIFO. This interface should be<br>enabled when the FIFO is also enabled (i.e., not in bypass mode). A<br>standard enable sequence is:<br>1) Enable FIFO.<br>2) Enable Sensor Registers to FIFO interface.<br>The opposite sequence should be used for the disable.<br>To prevent power drain, FIFO_IF_EN should be set to 0 if FIFO is in bypass<br>mode.<br>Can be changed on-the-fly.|



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## **17.33 FIFO_CONFIG4** 

Name: FIFO_CONFIG4 Address: 34 (22h) Serial IF: R/W Reset value: 0x00 Clock Domain: MCLK 

|**17.33 FIFO_CONFIG4**|**17.33 FIFO_CONFIG4**|**17.33 FIFO_CONFIG4**|
|---|---|---|
|Name: FIFO_CONFIG4<br>Address: 34 (22h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7:6|-|Reserved|
|5:3|FIFO_COMP_NC_FLOW_CFG|Configures the compression algorithm to write non-compressed packets<br>to FIFO at a certain rate<br>000: Non-compressed packet flow is disabled<br>001: Non-compressed packet every 8 frames<br>010: Non-compressed packet every 16 frames<br>011: Non-compressed packet every 32 frames<br>100: Non-compressed packet every 64 frames<br>101: Non-compressed packet every 128 frames<br>Others: Reserved|
|2|FIFO_COMP_EN|0: FIFO compression disabled<br>1: FIFO compression enabled|
|1|FIFO_TMST_FSYNC_EN|Enable the insertion of the Timestamp or FSYNC data into FIFO frame<br>0: No Timestamp/FSYNC data inserted into FIFO frame (timestamp fields<br>are 0x0000). FSYNC_TAG_EN bit in FIFO header is 0.<br>1: Timestamp/FSYNC data inserted into FIFO frame. FSYNC_TAG_EN bit in<br>FIFO header is set on an FSYNC trigger event.|
|0|FIFO_ES0_6B_9B|Select number of valid bytes provided by External Sensor 0<br>0: 6 bytes<br>1: 9 bytes|



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## **17.34 TMST_WOM_CONFIG** 

|**17.34 TMST_WOM_CONFIG**|**17.34 TMST_WOM_CONFIG**|**17.34 TMST_WOM_CONFIG**|
|---|---|---|
|Name: TMST_WOM_CONFIG<br>Address: 35 (23h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7|-|Reserved|
|6|TMST_DELTA_EN|Time Stamp Delta Enable<br>0: Time stamp field does not contain the measurement of time since the<br>last occurrence of trigger event<br>1: Time stamp field contains the measurement of time since the last<br>occurrence of trigger event|
|5|TMST_RESOL|Time Stamp Resolution<br>0: 1µs<br>1: 16µs|
|4|WOM_EN|Wake on Motion Enable<br>0: Wake on Motion not enabled<br>1: Wake on Motion enabled|
|3|WOM_MODE|Wake on Motion Mode<br>0: Initial sample is stored. Future samples are compared to initial sample<br>1: Compare current sample toprevious sample|
|2|WOM_INT_MODE|Wake on Motion Interrupt<br>0: Off<br>1: On|
|1:0|WOM_INT_DUR|Wake on Motion Interrupt Duration<br>00: Wake on Motion interrupt asserted at first over-threshold event<br>01: Wake on Motion interrupt asserted at second over-threshold event<br>10: Wake on Motion interrupt asserted at third over-threshold event<br>11: Wake on Motion interrupt asserted at fourth over-threshold event|



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## **17.35 FSYNC_CONFIG0** 

|**17.35 FSYNC_CONFIG0**|**17.35 FSYNC_CONFIG0**|**17.35 FSYNC_CONFIG0**|
|---|---|---|
|Name: FSYNC_CONFIG0<br>Address: 36 (24h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7:4|-|Reserved|
|3|AP_FSYNC_FLAG_CLEAR_SEL|Select the AP/UI FSYNC flag clear policy.<br>0: The FSYNC flag is cleared when UI/AP sensor register is updated.<br>1: The FSYNC flag is cleared when UI/AP serial interface reads the sensor<br>register LSB of FSYNC tagged axis.|
|2:0|AP_FSYNC_SEL|Select the AP/UI sensor that will carry the FSYNC tagging.<br>0: FSYNC tagging is disabled<br>1: Tag FSYNC flag to TEMP_DATA_UI LSB<br>2: Tag FSYNC flag to GYRO_DATA_X_UI LSB<br>3: Tag FSYNC flag to GYRO_DATA_Y_UI LSB<br>4: Tag FSYNC flag to GYRO_DATA_Z_UI LSB<br>5: Tag FSYNC flag to ACCEL_DATA_X_UI LSB<br>6: Tag FSYNC flag to ACCEL_DATA_Y_UI LSB<br>7: TagFSYNC flagto ACCEL_DATA_Z_UI LSB|



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## **17.36 DMP_EXT_SEN_ODR_CFG** 

|**17.36 DMP_EXT_SEN_ODR_CFG**|**17.36 DMP_EXT_SEN_ODR_CFG**|**17.36 DMP_EXT_SEN_ODR_CFG**|
|---|---|---|
|Name: DMP_EXT_SEN_ODR_CFG<br>Address: 39 (27h)<br>Serial IF: R/W<br>Reset value: 0x01<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7|-|Reserved|
|6|EXT_SENSOR_EN|0: Disables generation of ODR event for external sensor operation per the<br>setting of EXT_ODR.<br>1: Enables generation of ODR event for external sensor operation per the<br>settingof EXT_ODR.|
|5:3|EXT_ODR|I2C master external sensor ODR<br>000: 3.125Hz<br>001: 6.25Hz<br>010: 12.5Hz<br>011: 25Hz<br>100: 50Hz<br>101: 100Hz<br>110: 200Hz<br>111: 400Hz|
|2:0|APEX_ODR|DMP Output Data Rate. APEX_ODR should be smaller than or equal to<br>both ACCEL_ODR and GYRO_ODR. All rates shown below except 800Hz<br>can be set if Accel UI/AP in in LP mode. Accel UI/AP must be in LN mode to<br>set 800Hz.<br>000: 25Hz<br>001: 50Hz<br>010: 100Hz<br>011: 200Hz<br>100: 400Hz<br>101: 800Hz<br>110: Reserved<br>111: Reserved|



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## **17.37 ODR_DECIMATE_CONFIG** 

|**17.37 ODR_DECIMATE_CONFIG**|**17.37 ODR_DECIMATE_CONFIG**|**17.37 ODR_DECIMATE_CONFIG**|
|---|---|---|
|Name: ODR_DECIMATE_CONFIG<br>Address: 40 (28h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7:4|GYRO_FIFO_ODR_DEC|Decimation factor for Gyroscope FIFO data:<br>0000: 1 (same are input ODR)<br>0001: 2<br>0010: 4<br>0011: 8<br>0100: 16<br>0101: 32<br>0110: 64<br>0111: 128<br>1000: 256<br>1001: 512<br>1010: 1024<br>1011: 2048<br>1100: 4096<br>1101: Reserved<br>1110: Reserved<br>1111: Reserved|
|3:0|ACCEL_FIFO_ODR_DEC|Decimation factor for Accelerometer FIFO data:<br>0000: 1 (same are input ODR)<br>0001: 2<br>0010: 4<br>0011: 8<br>0100: 16<br>0101: 32<br>0110: 64<br>0111: 128<br>1000: 256<br>1001: 512<br>1010: 1024<br>1011: 2048<br>1100: 4096<br>1101: Reserved<br>1110: Reserved<br>1111: Reserved|



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## **17.38 EDMP_APEX_EN0** 

Name: EDMP_APEX_EN0 Address: 41 (29h) Serial IF: R/W Reset value: 0x00 Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|7|SMD_EN|Set 1 to enable SMD algorithm|
|6|R2W_EN|Set 1 to enable Raise to Wake algorithm|
|5|FF_EN|Set 1 to enable Freefall algorithm|
|4|PEDO_EN|Set 1 to enable Pedometer algorithm|
|3|TILT_EN|Set 1 to enable Tilt algorithm|
|2:1|-|Reserved|
|0|TAP_EN|Set 1 to enable Tapalgorithm|



## **17.39 EDMP_APEX_EN1** 

Name: EDMP_APEX_EN1 Address: 42 (2Ah) Serial IF: R/W Reset value: 0x00 Clock Domain: MCLK 

|**17.39 EDMP_APEX_EN1**|**17.39 EDMP_APEX_EN1**|**17.39 EDMP_APEX_EN1**|
|---|---|---|
|Name: EDMP_APEX_EN1<br>Address: 42 (2Ah)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7|-|Reserved|
|6|EDMP_ENABLE|Set 1 to enable eDMP|
|5|FEATURE3_EN|Set 1 to enable eDMP to run algorithms from RAM image|
|4:3|-|Reserved|
|2|POWER_SAVE_EN|Set 1 to enablepower save mode|
|1|INIT_EN|This bit is set by the host to indicate: eDMP executes only the segment of<br>code that initialize constants used byalgorithms.|
|0|SOFT_HARD_IRON_CORR_EN|Set 1 to enable soft iron hard iron correction|



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## **17.40 APEX_BUFFER_MGMT** 

|**17.40 APEX_BUFFER_MGMT**|**17.40 APEX_BUFFER_MGMT**|**17.40 APEX_BUFFER_MGMT**|
|---|---|---|
|Name: APEX_BUFFER_MGMT<br>Address: 43 (2Bh)<br>Serial IF: R/W (bits 5:4 are R only)<br>Reset value: 0x00<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7:6|FF_DURATION_HOST_RPTR|LSB indicates SRAM address for host to read; MSB indicates size 2 buffer<br>wrap around<br>00: Host reads buffer 0<br>01: Host reads buffer 1<br>10: Host reads buffer 0<br>11: Host reads buffer 1|
|5:4|FF_DURATION_EDMP_WPTR|Read only register field: LSB indicates SRAM address for eDMP to write;<br>MSB indicates size 2 buffer wrap around<br>00: eDMP writes to buffer 0<br>01: eDMP writes to buffer 1<br>10: eDMP writes to buffer 0<br>11: eDMP writes to buffer 1|
|3:2|STEP_COUNT_HOST_RPTR|LSB indicates SRAM address for host to read; MSB indicates size 2 buffer<br>wrap around<br>00: Host reads buffer 0<br>01: Host reads buffer 1<br>10: Host reads buffer 0<br>11: Host reads buffer 1|
|1:0|STEP_COUNT_EDMP_WPTR|Read only register field: LSB indicates SRAM address for eDMP to write;<br>MSB indicates size 2 buffer wrap around<br>00: eDMP writes to buffer 0<br>01: eDMP writes to buffer 1<br>10: eDMP writes to buffer 0<br>11: eDMP writes to buffer 1|



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## **17.41 INTF_CONFIG0** 

Name: INTF_CONFIG0 Address: 44 (2Ch) Serial IF: R/W (bits 1 and 0 are Read only) Reset value: 0x9A Clock Domain: MCLK 

|**17.41 INTF_CONFIG0**|**17.41 INTF_CONFIG0**|**17.41 INTF_CONFIG0**|
|---|---|---|
|Name: INTF_CONFIG0<br>Address: 44 (2Ch)<br>Serial IF: R/W (bits 1 and 0 are Read only)<br>Reset value: 0x9A<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7:2|-|Reserved|
|1|AP_SPI_34_MODE|Read only register field, shows OTP trim for UI interface SPI in 3-wire or 4-<br>wire mode<br>0: 3-wire mode<br>1: 4-wire mode|
|0|AP_SPI_MODE|Read only register field, shows OTP trim for UI interface SPI mode<br>selection<br>0: SPI mode 0 or 3<br>1: SPI mode 1 or 2|



## **17.42 INTF_CONFIG1_OVRD** 

Name: INTF_CONFIG1_OVRD Address: 45 (2Dh) Serial IF: R/W Reset value: 0x0C Clock Domain: SCLK 

|**17.42 INTF_CONFIG1_OVRD**|**17.42 INTF_CONFIG1_OVRD**|**17.42 INTF_CONFIG1_OVRD**|
|---|---|---|
|Name: INTF_CONFIG1_OVRD<br>Address: 45 (2Dh)<br>Serial IF: R/W<br>Reset value: 0x0C<br>Clock Domain: SCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7:4|-|Reserved|
|3|AP_SPI_34_MODE_OVRD|0: Override disable for AP interface SPI 4-wire/3-wire modes<br>1: Override enable for AP interface SPI 4-wire/3-wire modes|
|2|AP_SPI_34_MODE_OVRD_VA<br>L|Override value for AP interface SPI 4-wire/3-wire modes<br>0: SPI 3-wire mode<br>1: SPI 4-wire mode|
|1|AP_SPI_MODE_OVRD|0: Override disable for AP interface SPI_MODE value<br>1: Override enable for AP interface SPI_MODE value|
|0|AP_SPI_MODE_OVRD_VAL|Override value for AP interface SPI Mode<br>0: SPI mode 0 or 3<br>1: SPI mode 1 or 2|



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## **17.43 IOC_PAD_SCENARIO** 

|**17.43 IOC_PAD_SCENARIO**|**17.43 IOC_PAD_SCENARIO**|**17.43 IOC_PAD_SCENARIO**|
|---|---|---|
|Name: IOC_PAD_SCENARIO<br>Address: 47 (2Fh)<br>Serial IF: R<br>Reset value: 0x09<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7:3|-|Reserved|
|2:1|AUX1_MODE|Read only register field, effective only when AUX1_ENABLE is 1. Selects<br>AUX1 mode:<br>00: Reserved<br>01: AUX1 in I2C Master mode<br>10: AUX1 in I2C Master Bypass mode (Enable only when AP is not in SPI<br>mode)<br>11: Reserved|
|0|AUX1_ENABLE|Read only register field, enable or disable AUX1<br>0: AUX1 disabled<br>1: AUX1 enabled|



## **17.44 IOC_PAD_SCENARIO_AUX_OVRD** 

|Name: IOC_PAD_SCENARIO_AUX_OVRD<br>Address: 48 (30h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: IOC_PAD_SCENARIO_AUX_OVRD<br>Address: 48 (30h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: IOC_PAD_SCENARIO_AUX_OVRD<br>Address: 48 (30h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: MCLK|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:5|-|Reserved|
|4|AUX1_MODE_OVRD|Override enable for AUX1_MODE<br>0: Disable<br>1: Enable|
|3:2|AUX1_ENABLE_OVRD_VAL|Override value for AUX1_ENABLE. Effective only when AUX1_ENABLE is 1.<br>Selects modes of AUX1 use:<br>0: Reserved<br>1: AUX1 in I2C Master mode<br>2: AUX1 in I2C Master Bypass mode (enable only when AP is not in SPI<br>mode)<br>Note: When enabling the I2C Master Bypass mode, this register should be<br>programmed individually,not aspart of a burst transaction.|
|1|AUX1_ENABLE_OVRD|Override enable for AUX1_ENABLE<br>0: Disable<br>1: Enable|
|0|AUX1_ENABLE_OVRD_VAL|Override value for AUX1_ENABLE<br>0: AUX1 disabled<br>1: AUX1 enabled|



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## **17.45 DRIVE_CONFIG0** 

|**17.45 DRIVE_CONFIG0**|**17.45 DRIVE_CONFIG0**|**17.45 DRIVE_CONFIG0**|
|---|---|---|
|Name: DRIVE_CONFIG0<br>Address: 50 (32h)<br>Serial IF: R/W<br>Reset value: 0x6C<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7|-|Reserved|
|6:4|PADS_I2C_SLEW|Slew rate control for any pin in the I2C mode of operation, including pins<br>on the AP serial interface when device is a client device of an I2C bus,<br>including pins on the AUX1 serial interface when device is a master device<br>of an I2C bus. Setting of the slew rate takes effect 1.5µs after the register<br>is programmed.<br>000: MIN: 3 ns; TYP: 20 ns; MAX: 136 ns<br>010: MIN: 2 ns; TYP: 7 ns; MAX: 84 ns<br>Others: Reserved|
|3:1|PADS_SPI_SLEW|Slew rate control for any pin in the SPI mode of operation.<br>Setting of the slew rate takes effect 1.5µs after the register is<br>programmed.<br>000: MIN: 12 ns; TYP: 38 ns; MAX: 106 ns<br>001: MIN: 4 ns; TYP: 14 ns; MAX: 45 ns<br>010: MIN: 3 ns; TYP: 10 ns; MAX: 37 ns<br>011: MIN: 2 ns; TYP: 7 ns; MAX: 25 ns<br>100: MIN: 1 ns; TYP: 5 ns; MAX: 17 ns<br>101: MIN: 1 ns; TYP: 4 ns; MAX: 14 ns<br>11x: MIN: 0.1 ns;TYP: 0.5 ns;MAX: 6 ns|
|0|-|Reserved|



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## **17.46 DRIVE_CONFIG1** 

|**17.46 DRIVE_CONFIG1**|**17.46 DRIVE_CONFIG1**|**17.46 DRIVE_CONFIG1**|
|---|---|---|
|Name: DRIVE_CONFIG1<br>Address: 51 (33h)<br>Serial IF: R/W<br>Reset value: 0x36<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7:6|-|Reserved|
|5:3|PADS_I3C_DDR_SLEW|Slew rate control when device is in I3CSMDDR protocol. Setting of the slew<br>rate takes effect 1.5µs after the register is programmed.<br>000: MIN: 12 ns; TYP: 38 ns; MAX: 106 ns<br>001: MIN: 4 ns; TYP: 14 ns; MAX: 45 ns<br>010: MIN: 3 ns; TYP: 10 ns; MAX: 37 ns<br>011: MIN: 2 ns; TYP: 7 ns; MAX: 25 ns<br>100: MIN: 1 ns; TYP: 5 ns; MAX: 17 ns<br>101: MIN: 1 ns; TYP: 4 ns; MAX: 14 ns<br>11x: MIN: 0.1 ns;TYP: 0.5 ns;MAX: 6 ns|
|2:0|PADS_I3C_SDR_SLEW|Slew rate control when device is in I3CSMSDR protocol. Setting of the slew<br>rate takes effect 1.5µs after the register is programmed.<br>000: MIN: 12 ns; TYP: 38 ns; MAX: 106 ns<br>001: MIN: 4 ns; TYP: 14 ns; MAX: 45 ns<br>010: MIN: 3 ns; TYP: 10 ns; MAX: 37 ns<br>011: MIN: 2 ns; TYP: 7 ns; MAX: 25 ns<br>100: MIN: 1 ns; TYP: 5 ns; MAX: 17 ns<br>101: MIN: 1 ns; TYP: 4 ns; MAX: 14 ns<br>11x: MIN: 0.1 ns;TYP: 0.5 ns;MAX: 6 ns|



## **17.47 DRIVE_CONFIG2** 

|**17.47 DRIVE_CONFIG2**|**17.47 DRIVE_CONFIG2**|**17.47 DRIVE_CONFIG2**|
|---|---|---|
|Name: DRIVE_CONFIG2<br>Address: 52 (34h)<br>Serial IF: R/W<br>Reset value: 0x06<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7:3|-|Reserved|
|2:0|PADS_SLEW|Slew rate control for INT1 pin at all times. Slew rate control for all pins<br>before OTP copy operation is completed. Setting of the slew rate takes<br>effect 1.5µs after the register is programmed.<br>000: MIN: 12 ns; TYP: 38 ns; MAX: 106 ns<br>001: MIN: 4 ns; TYP: 14 ns; MAX: 45 ns<br>010: MIN: 3 ns; TYP: 10 ns; MAX: 37 ns<br>011: MIN: 2 ns; TYP: 7 ns; MAX: 25 ns<br>100: MIN: 1 ns; TYP: 5 ns; MAX: 17 ns<br>101: MIN: 1 ns; TYP: 4 ns; MAX: 14 ns<br>11x: MIN: 0.1 ns;TYP: 0.5 ns;MAX: 6 ns|



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## **17.48 REG_MISC1** 

|**17.48 REG_MISC1**|**17.48 REG_MISC1**|**17.48 REG_MISC1**|
|---|---|---|
|Name: REG_MISC1<br>Address: 53 (35h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7:4|-|Reserved|
|3:0|OSC_ID_OVRD|Selects MCLK source.<br>0000: MCLK source requested by internal logic (default)<br>0010: Requests internal relaxation oscillator<br>1000: Requests external clock<br>Rest: Reserved<br>The selected clock source is the highest index that's requested and that is<br>ready.|



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## **17.49 INT_APEX_CONFIG0** 

|**17.49 INT_APEX_CONFIG0**|**17.49 INT_APEX_CONFIG0**|**17.49 INT_APEX_CONFIG0**|
|---|---|---|
|Name: INT_APEX_CONFIG0<br>Address: 57 (39h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7|INT_STATUS_MASK_PIN_R2<br>W_WAKE_DET|Enable interrupt pin assertion when the INT_STATUS_R2W_WAKE_DET<br>status bit is 1.<br>0: Enable Interrupt pin assertion<br>1: No Interruptpin assertion|
|6|INT_STATUS_MASK_PIN_FF_<br>DET|Enable interrupt pin assertion when the INT_STATUS_FF_DET status bit is<br>1.<br>0: Enable Interrupt pin assertion<br>1: No Interruptpin assertion|
|5|INT_STATUS_MASK_PIN_STE<br>P_DET|Enable interrupt pin assertion when the INT_STATUS_STEP_DET status bit<br>is 1.<br>0: Enable Interrupt pin assertion<br>1: No Interruptpin assertion|
|4|INT_STATUS_MASK_PIN_STE<br>P_CNT_OVFL|Enable interrupt pin assertion when the INT_STATUS_STEP_CNT_OVFL<br>status bit is 1.<br>0: Enable Interrupt pin assertion<br>1: No Interruptpin assertion|
|3|INT_STATUS_MASK_PIN_TILT<br>_DET|Enable interrupt pin assertion when the INT_STATUS_TILT_DET status bit<br>is 1.<br>0: Enable Interrupt pin assertion<br>1: No Interruptpin assertion|
|2|INT_STATUS_MASK_PIN_LO<br>W_G_DET|Enable interrupt pin assertion when the INT_STATUS_LOW_G_DET status<br>bit is 1.<br>0: Enable Interrupt pin assertion<br>1: No Interruptpin assertion|
|1|INT_STATUS_MASK_PIN_HIG<br>H_G_DET|Enable interrupt pin assertion when the INT_STATUS_HIGH_G_DET status<br>bit is 1.<br>0: Enable Interrupt pin assertion<br>1: No Interruptpin assertion|
|0|INT_STATUS_MASK_PIN_TAP<br>_DET|Enable interrupt pin assertion when the INT_STATUS_TAP_DET status bit<br>is 1.<br>0: Enable Interrupt pin assertion<br>1: No Interruptpin assertion|



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## **17.50 INT_APEX_CONFIG1** 

|**17.50 INT_APEX_CONFIG1**|**17.50 INT_APEX_CONFIG1**|**17.50 INT_APEX_CONFIG1**|
|---|---|---|
|Name: INT_APEX_CONFIG1<br>Address: 58 (3Ah)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7:5|-|Reserved|
|4|INT_STATUS_MASK_PIN_SA_<br>DONE|0: Enable interrupt generation when Secure Authentication is done<br>1: Disable interruptgeneration for Secure Authentication|
|3|-|Reserved|
|2|INT_STATUS_MASK_PIN_SELF<br>TEST_DONE|0: Enable interrupt generation when self-test is done<br>1: Disable interruptgeneration for self-test|
|1|INT_STATUS_MASK_PIN_SM<br>D_DET|0: Enable interrupt generation for Significant Motion Detection (SMD)<br>1: Disable interruptgeneration for Significant Motion Detection(SMD)|
|0|INT_STATUS_MASK_PIN_R2<br>W_SLEEP_DET|0: Enable interrupt generation for Wake Sleep Detection<br>1: Disable interruptgeneration for Wake SleepDetection|



## **17.51 INT_APEX_STATUS0** 

Name: INT_APEX_STATUS0 Address: 59 (3Bh) Serial IF: R/C Reset value: 0x00 Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|7|INT_STATUS_R2W_WAKE_DE<br>T|0: Wake interrupt did not occur.<br>1: Wake interrupt occurred.|
|6|INT_STATUS_FF_DET|0: Freefall interrupt did not occur.<br>1: Freefall interrupt occurred.|
|5|INT_STATUS_STEP_DET|0: Step Detection interrupt did not occur.<br>1: StepDetection interrupt occurred.|
|4|INT_STATUS_STEP_CNT_OVF<br>L|0: Step-Count Overflow interrupt did not occur.<br>1: Step-Count Overflow interrupt occurred.|
|3|INT_STATUS_TILT_DET|0: Tilt Detection interrupt did not occur.<br>1: Tilt Detection interrupt occurred.|
|2|INT_STATUS_LOW_G_DET|0: LowG Detection interrupt did not occur.<br>1: LowG Detection interrupt occurred.|
|1|INT_STATUS_HIGH_G_DET|0: HighG Detection interrupt did not occur.<br>1: HighG Detection interrupt occurred.|
|0|INT_STATUS_TAP_DET|0: Tap Detection interrupt did not occur.<br>1: TapDetection interrupt occurred.|



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## **17.52 INT_APEX_STATUS1** 

|**17.52 INT_APEX_STATUS1**|**17.52 INT_APEX_STATUS1**|**17.52 INT_APEX_STATUS1**|
|---|---|---|
|Name: INT_APEX_STATUS1<br>Address: 60 (3Ch)<br>Serial IF: R/C<br>Reset value: 0x00<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7:5|-|Reserved|
|4|INT_STATUS_SA_DONE|For EDMP_OUT interface.<br>0: Secure Authentication interrupt did not occur.<br>1: Secure Authentication interrupt occurred.|
|3|-|Reserved|
|2|INT_STATUS_SELFTEST_DONE|0: Self-Test interrupt did not occur.<br>1: Self-Test interrupt occurred.|
|1|INT_STATUS_SMD_DET|This bit is set to 1 when Significant Motion Detection (SMD) interrupt is<br>generated<br>0: Significant Motion Detection (SMD) interrupt did not occur.<br>1: Significant Motion Detection(SMD)interrupt occurred.|
|0|INT_STATUS_R2W_SLEEP_DE<br>T|0: Sleep interrupt did not occur.<br>1: Sleepinterrupt occurred.|



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## **17.53 INT2_CONFIG0** 

|**17.53 INT2_CONFIG0**|**17.53 INT2_CONFIG0**|**17.53 INT2_CONFIG0**|
|---|---|---|
|Name: INT2_CONFIG0<br>Address: 86 (56h)<br>Serial IF: R/W<br>Reset value: 0x80<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7|INT2_STATUS_EN_RESET_<br>DONE|Enable interrupt status bit to flag the occurrence of Reset Done event on<br>INT2<br>0: Disable interrupt.<br>1: Enable interrupt.<br>Settingcan be changed byUI or AUX1 interface.|
|6|INT2_STATUS_EN_AUX1_A<br>GC_RDY|Enable interrupt status bit to flag the occurrence of AUX1 AGC Ready event<br>on INT2<br>0: Disable interrupt.<br>1: Enable interrupt.<br>Settingcan be changed byUI or AUX1 interface.|
|5|INT2_STATUS_EN_AP_AGC<br>_RDY|Enable interrupt status bit to flag the occurrence of UI AGC Ready event on<br>INT2<br>0: Disable interrupt.<br>1: Enable interrupt.<br>Settingcan be changed byUI or AUX1 interface.|
|4|INT2_STATUS_EN_AP_FSY<br>NC|Enable interrupt status bit to flag the occurrence of UI FSYNC event on INT2<br>0: Disable interrupt.<br>1: Enable interrupt.<br>Settingcan be changed byUI or AUX1 interface.|
|3|INT2_STATUS_EN_AUX1_D<br>RDY|Enable interrupt status bit to flag the occurrence of AUX1 Data Ready event<br>on INT2<br>0: Disable interrupt.<br>1: Enable interrupt.<br>Settingcan be changed byUI or AUX1 interface.|
|2|INT2_STATUS_EN_DRDY|Enable interrupt status bit to flag the occurrence of UI Data Ready event on<br>INT2<br>0: Disable interrupt.<br>1: Enable interrupt.<br>Settingcan be changed byUI or AUX1 interface.|
|1|INT2_STATUS_EN_FIFO_TH<br>S|Enable interrupt status bit to flag the occurrence of FIFO count ≥ FIFO<br>threshold event on INT2|



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|||<br>**_ICM-45605_**|
|---|---|---|
|||0: Disable interrupt.<br>1: Enable interrupt.<br>Settingcan be changed byUI or AUX1 interface.|
|0|INT2_STATUS_EN_FIFO_FU<br>LL|Enable interrupt status bit to flag the occurrence of FIFO full event on INT2<br>0: Disable interrupt.<br>1: Enable interrupt.<br>Settingcan be changed byUI or AUX1 interface.|



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## **17.54 INT2_CONFIG1** 

|**17.54 INT2_CONFIG1**|**17.54 INT2_CONFIG1**|**17.54 INT2_CONFIG1**|
|---|---|---|
|Name: INT2_CONFIG1<br>Address: 87 (57h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7|-|Reserved|
|6|INT2_STATUS_EN_APEX_E<br>VENT|Enable interrupt status bit to flag the occurrence of APEX event on INT2<br>0: Disable interrupt.<br>1: Enable interrupt.<br>Settingcan be changed byUI interface.|
|5|INT2_STATUS_EN_I2CM_D<br>ONE|Enable interrupt status bit to flag the completion of I2C master event on INT2<br>0: Disable interrupt.<br>1: Enable interrupt.<br>Settingcan be changed byUI interface.|
|4|INT2_STATUS_EN_I3C_PRO<br>TOCOL_ERR|Enable interrupt status bit to flag the occurrence of I3C Protocol Error event<br>on INT2<br>0: Disable interrupt.<br>1: Enable interrupt.<br>Settingcan be changed byUI interface.|
|3|INT2_STATUS_EN_WOM_Z|Enable interrupt status bit to flag the occurrence of WOM on Z-axis event on<br>INT2<br>0: Disable interrupt.<br>1: Enable interrupt.<br>Settingcan be changed byUI interface.|
|2|INT2_STATUS_EN_WOM_Y|Enable interrupt status bit to flag the occurrence of WOM on Y-axis event on<br>INT2<br>0: Disable interrupt.<br>1: Enable interrupt.<br>Settingcan be changed byUI interface.|
|1|INT2_STATUS_EN_WOM_X|Enable interrupt status bit to flag the occurrence of WOM on X-axis event on<br>INT2<br>0: Disable interrupt.<br>1: Enable interrupt.<br>Settingcan be changed byUI interface.|
|0|INT2_STATUS_EN_PLL_RDY|Enable interrupt status bit to flag the occurrence of PLL Ready event on INT2<br>0: Disable interrupt.|



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1: Enable interrupt. Setting can be changed by UI interface. 

## **17.55 INT2_CONFIG2** 

Name: INT2_CONFIG2 Address: 88 (58h) Serial IF: R/W Reset value: 0x04 Clock Domain: MCLK 

|**17.55 INT2_CONFIG2**|**17.55 INT2_CONFIG2**|**17.55 INT2_CONFIG2**|
|---|---|---|
|Name: INT2_CONFIG2<br>Address: 88 (58h)<br>Serial IF: R/W<br>Reset value: 0x04<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7:3|-|Reserved|
|2|INT2_DRIVE|Sets INT2 to open-drain or push-pull<br>0: Push-pull<br>1: Open-drain|
|1|INT2_MODE|INT2 interrupt mode<br>0: Pulse mode<br>1: Latch mode<br>Setting can be changed only when all interrupts of the corresponding serial<br>interface are disabled|
|0|INT2_POLARITY|INT2 interrupt polarity<br>0: Active low<br>1: Active high<br>Setting can be changed only when all interrupts of the corresponding serial<br>interface are disabled|



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## **17.56 INT2_STATUS0** 

|**17.56 INT2_STATUS0**|**17.56 INT2_STATUS0**|**17.56 INT2_STATUS0**|
|---|---|---|
|Name: INT2_STATUS0<br>Address: 89 (59h)<br>Serial IF: R/C<br>Reset value: 0x00<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7|INT2_STATUS_RESET_DON<br>E|Flags the occurrence of Reset Done event on INT2<br>0: Interrupt did not occur<br>1: Interrupt occurred|
|6|INT2_STATUS_AUX1_AGC_<br>RDY|Flags the occurrence of AUX1 AGC Ready event on INT2<br>0: Interrupt did not occur<br>1: Interrupt occurred|
|5|INT2_STATUS_AP_AGC_RD<br>Y|Flags the occurrence of UI AGC Ready event on INT2<br>0: Interrupt did not occur<br>1: Interrupt occurred|
|4|INT2_STATUS_AP_FSYNC|Flags the occurrence of UI FSYNC event on INT2<br>0: Interrupt did not occur<br>1: Interrupt occurred|
|3|INT2_STATUS_AUX1_DRDY|Flags the occurrence of AUX1 Data Ready event on INT2<br>0: Interrupt did not occur<br>1: Interrupt occurred|
|2|INT2_STATUS_DRDY|Flags the occurrence of UI Data Ready event on INT2<br>0: Interrupt did not occur<br>1: Interrupt occurred|
|1|INT2_STATUS_FIFO_THS|Flags the occurrence of FIFO count ≥ FIFO threshold event on INT2<br>0: Interrupt did not occur<br>1: Interrupt occurred|
|0|INT2_STATUS_FIFO_FULL|Flags the occurrence of FIFO full event on INT2<br>0: Interrupt did not occur<br>1: Interrupt occurred|



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## **17.57 INT2_STATUS1** 

|Name: INT2_STATUS1<br>Address: 90 (5Ah)<br>Serial IF: R/C<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: INT2_STATUS1<br>Address: 90 (5Ah)<br>Serial IF: R/C<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: INT2_STATUS1<br>Address: 90 (5Ah)<br>Serial IF: R/C<br>Reset value: 0x00<br>Clock Domain: MCLK|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7|-|Reserved|
|6|INT2_STATUS_APEX_EVEN<br>T|Flags the occurrence of APEX event on INT2<br>0: Interrupt did not occur<br>1: Interrupt occurred|
|5|INT2_STATUS_I2CM_DONE|Flags the occurrence of I2C Master Done event on INT2<br>0: Interrupt did not occur<br>1: Interrupt occurred|
|4|INT2_STATUS_I3C_PROTO<br>COL_ERR|Flags the occurrence of I3CSMProtocol Error event on INT2<br>0: Interrupt did not occur<br>1: Interrupt occurred|
|3|INT2_STATUS_WOM_Z|Flags the occurrence of Z-axis WOM event on INT2<br>0: Interrupt did not occur<br>1: Interrupt occurred|
|2|INT2_STATUS_WOM_Y|Flags the occurrence of Y-axis WOM event on INT2<br>0: Interrupt did not occur<br>1: Interrupt occurred|
|1|INT2_STATUS_WOM_X|Flags the occurrence of X-axis WOM event on INT2<br>0: Interrupt did not occur<br>1: Interrupt occurred|
|0|INT2_STATUS_PLL_RDY|Flags the occurrence of PLL Ready event on INT2<br>0: Interrupt did not occur<br>1: Interrupt occurred|



## **17.58 WHO_AM_I** 

|Name: WHO_AM_I<br>Address: 114 (72h)<br>Serial IF: R<br>Reset value: 0xE5<br>Clock Domain: ALL|Name: WHO_AM_I<br>Address: 114 (72h)<br>Serial IF: R<br>Reset value: 0xE5<br>Clock Domain: ALL|Name: WHO_AM_I<br>Address: 114 (72h)<br>Serial IF: R<br>Reset value: 0xE5<br>Clock Domain: ALL|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:0|WHOAMI|Register to indicate to user which device is beingaccessed|



## Description: 

This register is used to verify the identity of the device. The contents of WHOAMI is an 8-bit device ID. The default value of the register is 0xE5. This is different from the I[2] C address of the device as seen on the slave I[2] C controller by the applications processor. 

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## **17.59 REG_HOST_MSG** 

|Name: REG_HOST_MSG<br>Address: 115 (73h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: SCLK|Name: REG_HOST_MSG<br>Address: 115 (73h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: SCLK|Name: REG_HOST_MSG<br>Address: 115 (73h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: SCLK|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:6|-|Reserved|
|5|EDMP_ON_DEMAND_EN|When set, a trigger will be sent which will cause the eDMP to run once. It is<br>automaticallyreset to 0.|
|4:1|-|Reserved|
|0|TESTOPENABLE|1: Enable test operation|



## **17.60 IREG_ADDR_15_8** 

|Name: IREG_ADDR_15_8<br>Address: 124 (7Ch)<br>Serial IF: R/W<br>Reset value: 0xAF<br>Clock Domain: SCLK|Name: IREG_ADDR_15_8<br>Address: 124 (7Ch)<br>Serial IF: R/W<br>Reset value: 0xAF<br>Clock Domain: SCLK|Name: IREG_ADDR_15_8<br>Address: 124 (7Ch)<br>Serial IF: R/W<br>Reset value: 0xAF<br>Clock Domain: SCLK|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:0|IREG_ADDR_15_8|Address bit[15:8] of the 16-bit indirect address for assessing indirect access<br>registers (IREG)<br>Can be changed on-the-fly.|



## **17.61 IREG_ADDR_7_0** 

Name: IREG_ADDR_7_0 Address: 125 (7Dh) Serial IF: R/W Reset value: 0x06 Clock Domain: SCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Address bit[7:0] of the 16-bit indirect address for assessing indirect access|
|7:0|IREG_ADDR_7_0|registers (IREG)|
|||Can be changed on-the-fly.|



## **17.62 IREG_DATA** 

|Name: IREG_DATA<br>Address: 126 (7Eh)<br>Serial IF: R/W<br>Reset value: 0x02<br>Clock Domain: SCLK|Name: IREG_DATA<br>Address: 126 (7Eh)<br>Serial IF: R/W<br>Reset value: 0x02<br>Clock Domain: SCLK|Name: IREG_DATA<br>Address: 126 (7Eh)<br>Serial IF: R/W<br>Reset value: 0x02<br>Clock Domain: SCLK|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:0|IREG_DATA|Register for indirect access registers (IREG) data read/write operations.<br>Can be changed on-the-fly.|



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## **17.63 REG_MISC2** 

|**17.63 REG_MISC2**|**17.63 REG_MISC2**|**17.63 REG_MISC2**|
|---|---|---|
|Name: REG_MISC2<br>Address: 127 (7Fh)<br>Serial IF: R/W<br>Reset value: 0x01<br>Clock Domain: SCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7:2|-|Reserved|
|1|SOFT_RST|0: Soft reset not enabled.<br>1: Triggers soft reset operation. The programmed value of 1 is self-cleared to<br>0 upon completion of soft reset operation.<br>Can be changed on-the-fly.|
|0|IREG_DONE|0: Indicates that an indirect register access operation is in progress. No new<br>indirect register access should be triggered.<br>1: Indirect register access has completed. New indirect register access can be<br>triggered.|



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## _**18 USER BANK IMEM_SRAM REGISTER MAP – DESCRIPTIONS**_ 

This section describes the function and contents of each register within user bank IMEM_SRAM. The registers described in this section are indirect access registers. Section 13 describes the procedure for accessing indirect access registers. 

## **18.1 IMEM_SRAM_REG_0** 

|Name: IMEM_SRAM_REG_0<br>Address: 00 (00h)<br>Serial IF: R/W<br>Reset value: Random value after reset until host runs EDMP_INIT procedure<br>Clock Domain: MCLK|Name: IMEM_SRAM_REG_0<br>Address: 00 (00h)<br>Serial IF: R/W<br>Reset value: Random value after reset until host runs EDMP_INIT procedure<br>Clock Domain: MCLK|Name: IMEM_SRAM_REG_0<br>Address: 00 (00h)<br>Serial IF: R/W<br>Reset value: Random value after reset until host runs EDMP_INIT procedure<br>Clock Domain: MCLK|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:0|GYRO_X_STR_FT[7:0]|Self-test response for gyro X-axis. Units are in kdps. Full scale is 0.5kdps, LSB<br>is 30mdps.|



## **18.2 IMEM_SRAM_REG_1** 

|Name: IMEM_SRAM_REG_1<br>Address: 01 (01h)<br>Serial IF: R/W<br>Reset value: Random value after reset until host runs EDMP_INIT procedure<br>Clock Domain: MCLK|Name: IMEM_SRAM_REG_1<br>Address: 01 (01h)<br>Serial IF: R/W<br>Reset value: Random value after reset until host runs EDMP_INIT procedure<br>Clock Domain: MCLK|Name: IMEM_SRAM_REG_1<br>Address: 01 (01h)<br>Serial IF: R/W<br>Reset value: Random value after reset until host runs EDMP_INIT procedure<br>Clock Domain: MCLK|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:0|GYRO_X_STR_FT[15:8]|Self-test response for gyro X-axis. Units are in kdps. Full scale is 0.5kdps, LSB<br>is 30mdps.|



## **18.3 IMEM_SRAM_REG_2** 

|Name: IMEM_SRAM_REG_2<br>Address: 02 (02h)<br>Serial IF: R/W<br>Reset value: Random value after reset until host runs EDMP_INIT procedure<br>Clock Domain: MCLK|Name: IMEM_SRAM_REG_2<br>Address: 02 (02h)<br>Serial IF: R/W<br>Reset value: Random value after reset until host runs EDMP_INIT procedure<br>Clock Domain: MCLK|Name: IMEM_SRAM_REG_2<br>Address: 02 (02h)<br>Serial IF: R/W<br>Reset value: Random value after reset until host runs EDMP_INIT procedure<br>Clock Domain: MCLK|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:0|GYRO_Y_STR_FT[7:0]|Self-test response for gyro Y-axis. Units are in kdps. Full scale is 0.5kdps, LSB<br>is 30mdps.|



## **18.4 IMEM_SRAM_REG_3** 

Name: IMEM_SRAM_REG_3 Address: 03 (03h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK **BIT NAME FUNCTION** Self-test response for gyro Y-axis. Units are in kdps. Full scale is 0.5kdps, LSB 7:0 GYRO_Y_STR_FT[15:8] is 30mdps. 

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## **18.5 IMEM_SRAM_REG_4** 

|**18.5**<br>**IMEM_SRAM_REG_4**|**18.5**<br>**IMEM_SRAM_REG_4**|**18.5**<br>**IMEM_SRAM_REG_4**|
|---|---|---|
|Name: IMEM_SRAM_REG_4<br>Address: 04 (04h)<br>Serial IF: R/W<br>Reset value: Random value after reset until host runs EDMP_INIT procedure<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7:0|GYRO_Z_STR_FT[7:0]|Self-test response for gyro Z-axis. Units are in kdps. Full scale is 0.5kdps, LSB<br>is 30mdps.|



## **18.6 IMEM_SRAM_REG_5** 

|Name: IMEM_SRAM_REG_5<br>Address: 05 (05h)<br>Serial IF: R/W<br>Reset value: Random value after reset until host runs EDMP_INIT procedure<br>Clock Domain: MCLK|Name: IMEM_SRAM_REG_5<br>Address: 05 (05h)<br>Serial IF: R/W<br>Reset value: Random value after reset until host runs EDMP_INIT procedure<br>Clock Domain: MCLK|Name: IMEM_SRAM_REG_5<br>Address: 05 (05h)<br>Serial IF: R/W<br>Reset value: Random value after reset until host runs EDMP_INIT procedure<br>Clock Domain: MCLK|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:0|GYRO_Z_STR_FT[15:8]|Self-test response for gyro Z-axis. Units are in kdps. Full scale is 0.5kdps, LSB<br>is 30mdps.|



## **18.7 IMEM_SRAM_REG_6** 

|Name: IMEM_SRAM_REG_6<br>Address: 06 (06h)<br>Serial IF: R/W<br>Reset value: Random value after reset until host runs EDMP_INIT procedure<br>Clock Domain: MCLK|Name: IMEM_SRAM_REG_6<br>Address: 06 (06h)<br>Serial IF: R/W<br>Reset value: Random value after reset until host runs EDMP_INIT procedure<br>Clock Domain: MCLK|Name: IMEM_SRAM_REG_6<br>Address: 06 (06h)<br>Serial IF: R/W<br>Reset value: Random value after reset until host runs EDMP_INIT procedure<br>Clock Domain: MCLK|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:0|GYRO_X_CMOS_GAIN_FT[<br>7:0]|Gyro X-axis gain measurement result. Units are in kdps. FSR is 500 dps,<br>resolution is 122 mdps.|



## **18.8 IMEM_SRAM_REG_7** 

Name: IMEM_SRAM_REG_7 Address: 07 (07h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|7:4|-|Reserved|
|3:0|GYRO_X_CMOS_GAIN_FT[<br>11:8]|Gyro X-axis gain measurement result. Units are in kdps. FSR is 500 dps,<br>resolution is 122 mdps.|



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## **18.9 IMEM_SRAM_REG_8** 

Name: IMEM_SRAM_REG_8 Address: 08 (08h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|7:0|GYRO_Y_CMOS_GAIN_FT[<br>7:0]|Gyro Y-axis gain measurement result. Units are in kdps. FSR is 500 dps,<br>resolution is 122 mdps.|



## **18.10 IMEM_SRAM_REG_9** 

Name: IMEM_SRAM_REG_9 Address: 09 (09h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|7:4|-|Reserved|
|3:0|GYRO_Y_CMOS_GAIN_FT<br>[11:8]|Gyro Y-axis gain measurement result. Units are in kdps. FSR is 500 dps,<br>resolution is 122 mdps.|



## **18.11 IMEM_SRAM_REG_10** 

Name: IMEM_SRAM_REG_10 Address: 10 (0Ah) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|7:0|GYRO_Z_CMOS_GAIN_FT[<br>7:0]|Gyro Z-axis gain measurement result. Units are in kdps. FSR is 500 dps,<br>resolution is 122 mdps.|



## **18.12 IMEM_SRAM_REG_11** 

Name: IMEM_SRAM_REG_11 Address: 11 (0Bh) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|7:4|-|Reserved|
|3:0|GYRO_Z_CMOS_GAIN_FT<br>[11:8]|Gyro Z-axis gain measurement result. Units are in kdps. FSR is 500 dps,<br>resolution is 122 mdps.|



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## **18.13 IMEM_SRAM_REG_56** 

Name: IMEM_SRAM_REG_56 Address: 56 (38h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**18.13 IMEM_SRAM_REG_56**|**18.13 IMEM_SRAM_REG_56**|**18.13 IMEM_SRAM_REG_56**|
|---|---|---|
|Name: IMEM_SRAM_REG_56<br>Address: 56 (38h)<br>Serial IF: R/W<br>Reset value: Random value after reset until host runs EDMP_INIT procedure<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7|ST_AVG_TIME[0]|Averaging time used to perform self-test (ST_AVG_TIME[2:1] in<br>IMEM_SRAM_REG_57)<br>000: 10ms<br>001: 20ms<br>010: 40ms<br>011: 80ms<br>100: 160ms<br>101: 320ms<br>Rest: Reserved|
|6:3|-|Reserved|
|2|ST_GYRO_EN|1: Enablegyro self-test operation|
|1|ST_ACCEL_EN|1: Enable accel self-test operation|
|0|STC_INIT_EN|1: Initializes self-testparameters|



## **18.14 IMEM_SRAM_REG_57** 

Name: IMEM_SRAM_REG_57 Address: 57 (39h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|Name: IMEM_SRAM_REG_57<br>Address: 57 (39h)<br>Serial IF: R/W<br>Reset value: Random value after reset until host runs EDMP_INIT procedure<br>Clock Domain: MCLK|Name: IMEM_SRAM_REG_57<br>Address: 57 (39h)<br>Serial IF: R/W<br>Reset value: Random value after reset until host runs EDMP_INIT procedure<br>Clock Domain: MCLK|Name: IMEM_SRAM_REG_57<br>Address: 57 (39h)<br>Serial IF: R/W<br>Reset value: Random value after reset until host runs EDMP_INIT procedure<br>Clock Domain: MCLK|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:5|ST_GYRO_LIMIT|Tolerance between factory trim and gyro self-test response<br>000: 5%<br>001: 10%<br>010: 15%<br>011: 20%<br>100: 25%<br>101: 30%<br>110: 40%<br>111: 50%|
|4:2|ST_ACCEL_LIMIT|Tolerance between factory trim and accel self-test response<br>000: 5%<br>001: 10%<br>010: 15%<br>011: 20%<br>100: 25%<br>101: 30%<br>110: 40%<br>111: 50%|



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|1:0|ST_AVG_TIME[2:1]|Averaging time used to perform self-test (ST_AVG_TIME[0] in<br>IMEM_SRAM_REG_56)<br>000: 10ms<br>001: 20ms<br>010: 40ms<br>011: 80ms<br>100: 160ms<br>101: 320ms<br>Rest: Reserved|
|---|---|---|



## **18.15 IMEM_SRAM_REG_64** 

|**18.15 IMEM_SRAM_REG_64**|**18.15 IMEM_SRAM_REG_64**|**18.15 IMEM_SRAM_REG_64**|
|---|---|---|
|Name: IMEM_SRAM_REG_64<br>Address: 64 (40h)<br>Serial IF: R/W<br>Reset value: Random value after reset until host runs EDMP_INIT procedure<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7:0|ST_DEBUG_EN|Debug capability of self-test feature. Must be set to 0 whenever self-test is<br>requested.|



## **18.16 IMEM_SRAM_REG_68** 

Name: IMEM_SRAM_REG_68 Address: 68 (44h) Serial IF: R Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Self-test status (gyro or accel)|
|7:6|ST_STATUS|00: Done<br>01: In Progress|
|||10: Error|
|||11: Reserved|
|5|GZ_ST_PASS|1: Gyro Z-axis self-testpassed|
|4|GY_ST_PASS|1: Gyro Y-axis self-testpassed|
|3|GX_ST_PASS|1: Gyro X-axis self-testpassed|
|2|AZ_ST_PASS|1: Accel Z-axis self-testpassed|
|1|AY_ST_PASS|1: Accel Y-axis self-testpassed|
|0|AX_ST_PASS|1: Accel X-axis self-testpassed|



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## **18.17 IMEM_SRAM_REG_92** 

Name: IMEM_SRAM_REG_92 Address: 92 (5Ch) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Set 1 to force reset 3-axis quaternion when next tilt reset is done. This is|
|7:0|QUAT_RESET_EN|applicable only if TILT_RESET_EN is also set to 1.<br>Range: [0 – 1]|
|||Default: 0|



## **18.18 IMEM_SRAM_REG_96** 

Name: IMEM_SRAM_REG_96 Address: 96 (60h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK **BIT NAME FUNCTION** 7:0 STC_GAIN_GX[7:0] Gyro measurements for X-axis in s32.16 for gyro self-test 

## **18.19 IMEM_SRAM_REG_97** 

Name: IMEM_SRAM_REG_97 Address: 97 (61h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK **BIT NAME FUNCTION** 7:0 STC_GAIN_GX[15:8] Gyro measurements for X-axis in s32.16 for gyro self-test 

## **18.20 IMEM_SRAM_REG_98** 

Name: IMEM_SRAM_REG_98 Address: 98 (62h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK **BIT NAME FUNCTION** 7:0 STC_GAIN_GX[23:16] Gyro measurements for X-axis in s32.16 for gyro self-test 

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**FUNCTION** yro measurements for X-axis in s32.16 for gyro self-test ro measurements for X-axis in s32.16 for gyro self-test gyro self-test ro self-test 

**FUNCTION** yro measurements for Y-axis in s32.16 for gyro self-test ro measurements for Y-axis in s32.16 for gyro self-test gyro self-test ro self-test 

**18.21 IMEM_SRAM_REG_99** 

Name: IMEM_SRAM_REG_99 Address: 99 (63h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK **BIT NAME FUNCTION** ~~———~~ 7:0 STC_GAIN_GX[31:24] Gyro measurements for X-axis in s32.16 for gyro self-test ro measurements for X-axis in s32.16 for gyro self-test gyro self-test ro self-test 

**18.22 IMEM_SRAM_REG_100** 

Name: IMEM_SRAM_REG_100 Address: 100 (64h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK **BIT NAME FUNCTION** ~~———~~ 7:0 STC_GAIN_GY[7:0] Gyro measurements for Y-axis in s32.16 for gyro self-test 

**18.23 IMEM_SRAM_REG_101** 

Name: IMEM_SRAM_REG_101 Address: 101 (65h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK **BIT NAME FUNCTION** ~~———~~ 7:0 STC_GAIN_GY[15:8] Gyro measurements for Y-axis in s32.16 for gyro self-test ro measurements for Y-axis in s32.16 for gyro self-test gyro self-test ro self-test 

**18.24 IMEM_SRAM_REG_102** 

Name: IMEM_SRAM_REG_102 Address: 102 (66h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK **BIT NAME FUNCTION** ~~———~~ 7:0 STC_GAIN_GY[23:16] Gyro measurements for Y-axis in s32.16 for gyro self-test 

**18.25 IMEM_SRAM_REG_103** 

Name: IMEM_SRAM_REG_103 Address: 103 (67h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK **BIT NAME FUNCTION** ~~———~~ 7:0 STC_GAIN_GY[31:24] Gyro measurements for Y-axis in s32.16 for gyro self-test 

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## **18.26 IMEM_SRAM_REG_104** 

Name: IMEM_SRAM_REG_104 Address: 104 (68h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK **BIT NAME FUNCTION** 7:0 STC_GAIN_GZ[7:0] Gyro measurements for Z-axis in s32.16 for gyro self-test 

## **18.27 IMEM_SRAM_REG_105** 

Name: IMEM_SRAM_REG_105 Address: 105 (69h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK **BIT NAME FUNCTION** 7:0 STC_GAIN_GZ[15:8] Gyro measurements for Z-axis in s32.16 for gyro self-test 

## **18.28 IMEM_SRAM_REG_106** 

Name: IMEM_SRAM_REG_106 Address: 106 (6Ah) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK **BIT NAME FUNCTION** 7:0 STC_GAIN_GZ[23:16] Gyro measurements for Z-axis in s32.16 for gyro self-test 

## **18.29 IMEM_SRAM_REG_107** 

Name: IMEM_SRAM_REG_107 Address: 107 (6Bh) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK **BIT NAME FUNCTION** 7:0 STC_GAIN_GZ[31:24] Gyro measurements for Z-axis in s32.16 for gyro self-test 

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## **18.30 IMEM_SRAM_REG_136** 

Name: IMEM_SRAM_REG_136 Address: 136 (88h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Duration of the freefall in number of samples. Filled in alternatively with|
|7:0|FF_DURATION_BUF1[7:0]|FF_DURATION_BUF2.<br>Unit: Number of samples. Freefall duration in seconds is|
|||FF_DURATION_BUF1/ACCEL_ODR(in Hz)|



## **18.31 IMEM_SRAM_REG_137** 

Name: IMEM_SRAM_REG_137 Address: 137 (89h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Duration of the freefall in number of samples. Filled in alternatively with|
|7:0|FF_DURATION_BUF1[15:8]|FF_DURATION_BUF2.<br>Unit: Number of samples. Freefall duration in seconds is|
|||FF_DURATION_BUF1/ACCEL_ODR(in Hz)|



## **18.32 IMEM_SRAM_REG_138** 

Name: IMEM_SRAM_REG_138 Address: 138 (8Ah) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Duration of the freefall in number of samples. Filled in alternatively with|
|7:0|FF_DURATION_BUF2[7:0]|FF_DURATION_BUF1.<br>Unit: Number of samples. Freefall duration in seconds is|
|||FF_DURATION_BUF2/ACCEL_ODR(in Hz)|



## **18.33 IMEM_SRAM_REG_139** 

Name: IMEM_SRAM_REG_139 Address: 139 (8Bh) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Duration of the freefall in number of samples. Filled in alternatively with|
|7:0|FF_DURATION_BUF2[15:8]|FF_DURATION_BUF1.<br>Unit: Number of samples. Freefall duration in seconds is|
|||FF_DURATION_BUF2/ACCEL_ODR(in Hz)|



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## **18.34 IMEM_SRAM_REG_141** 

|**18.34 IMEM_SRAM_REG_141**|**18.34 IMEM_SRAM_REG_141**|**18.34 IMEM_SRAM_REG_141**|
|---|---|---|
|Name: IMEM_SRAM_REG_141<br>Address: 141 (8Dh)<br>Serial IF: R/W<br>Reset value: Random value after reset until host runs EDMP_INIT procedure<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7:0|TAP_NUM|Type of the last reported TAP event:<br>0: no tap,1: single tap,2: double tap|



## **18.35 IMEM_SRAM_REG_142** 

|Name: IMEM_SRAM_REG_142<br>Address: 142 (8Eh)<br>Serial IF: R/W<br>Reset value: Random value after reset until host runs EDMP_INIT procedure<br>Clock Domain: MCLK|Name: IMEM_SRAM_REG_142<br>Address: 142 (8Eh)<br>Serial IF: R/W<br>Reset value: Random value after reset until host runs EDMP_INIT procedure<br>Clock Domain: MCLK|Name: IMEM_SRAM_REG_142<br>Address: 142 (8Eh)<br>Serial IF: R/W<br>Reset value: Random value after reset until host runs EDMP_INIT procedure<br>Clock Domain: MCLK|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:0|TAP_AXIS|Indicates the axis of the tap in the device frame<br>0: AX,1: AY,2: AZ|



## **18.36 IMEM_SRAM_REG_143** 

Name: IMEM_SRAM_REG_143 Address: 143 (8Fh) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|7:0|TAP_DIR|Indicates the direction of the tap in the device frame<br>0: Positive,1: Negative|



## **18.37 IMEM_SRAM_REG_144** 

Name: IMEM_SRAM_REG_144 Address: 144 (90h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Indicate in case of double tap, the sample count between the 2 detected|
|||pulses|
|7:0|DOUBLE_TAP_TIMING|In case of double tap, indicates the sample count between the two detected|
|||pulses. Double tap timing in seconds is DOUBLE_TAP_TIMING / ACCEL_ODR|
|||(in Hz).|



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## **18.38 IMEM_SRAM_REG_146** 

Name: IMEM_SRAM_REG_146 Address: 146 (92h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Set 1 to reset tilt prior to any further tilt processing on next sensor data.|
|7:0|TILT_RESET_EN|Range: [0 - 1]|
|||Default: 0|



## **18.39 IMEM_SRAM_REG_154** 

|Name: IMEM_SRAM_REG_154<br>Address: 154 (9Ah)<br>Serial IF: R/W<br>Reset value: Random value after reset until host runs EDMP_INIT procedure<br>Clock Domain: MCLK|Name: IMEM_SRAM_REG_154<br>Address: 154 (9Ah)<br>Serial IF: R/W<br>Reset value: Random value after reset until host runs EDMP_INIT procedure<br>Clock Domain: MCLK|Name: IMEM_SRAM_REG_154<br>Address: 154 (9Ah)<br>Serial IF: R/W<br>Reset value: Random value after reset until host runs EDMP_INIT procedure<br>Clock Domain: MCLK|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:0|PED_STEP_CNT_BUF1[7:0]|Number of steps done since the last init of the pedometer feature. Filled in<br>alternativelywith PED_STEP_CNT_BUF2. Unit: number of steps|



## **18.40 IMEM_SRAM_REG_155** 

|Name: IMEM_SRAM_REG_155<br>Address: 155 (9Bh)<br>Serial IF: R/W<br>Reset value: Random value after reset until host runs EDMP_INIT procedure<br>Clock Domain: MCLK|Name: IMEM_SRAM_REG_155<br>Address: 155 (9Bh)<br>Serial IF: R/W<br>Reset value: Random value after reset until host runs EDMP_INIT procedure<br>Clock Domain: MCLK|Name: IMEM_SRAM_REG_155<br>Address: 155 (9Bh)<br>Serial IF: R/W<br>Reset value: Random value after reset until host runs EDMP_INIT procedure<br>Clock Domain: MCLK|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:0|PED_STEP_CNT_BUF1[15:8<br>]|Number of steps done since the last init of the pedometer feature. Filled in<br>alternativelywith PED_STEP_CNT_BUF2. Unit: number of steps|



## **18.41 IMEM_SRAM_REG_156** 

|Name: IMEM_SRAM_REG_156<br>Address: 156 (9Ch)<br>Serial IF: R/W<br>Reset value: Random value after reset until host runs EDMP_INIT procedure<br>Clock Domain: MCLK|Name: IMEM_SRAM_REG_156<br>Address: 156 (9Ch)<br>Serial IF: R/W<br>Reset value: Random value after reset until host runs EDMP_INIT procedure<br>Clock Domain: MCLK|Name: IMEM_SRAM_REG_156<br>Address: 156 (9Ch)<br>Serial IF: R/W<br>Reset value: Random value after reset until host runs EDMP_INIT procedure<br>Clock Domain: MCLK|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:0|PED_STEP_CNT_BUF2[7:0]|Number of steps done since the last init of the pedometer feature. Filled in<br>alternativelywith PED_STEP_CNT_BUF1. Unit: number of steps|



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## **18.42 IMEM_SRAM_REG_157** 

|Name: IMEM_SRAM_REG_157<br>Address: 157 (9Dh)<br>Serial IF: R/W<br>Reset value: Random value after reset until host runs EDMP_INIT procedure<br>Clock Domain: MCLK|Name: IMEM_SRAM_REG_157<br>Address: 157 (9Dh)<br>Serial IF: R/W<br>Reset value: Random value after reset until host runs EDMP_INIT procedure<br>Clock Domain: MCLK|Name: IMEM_SRAM_REG_157<br>Address: 157 (9Dh)<br>Serial IF: R/W<br>Reset value: Random value after reset until host runs EDMP_INIT procedure<br>Clock Domain: MCLK|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:0|PED_STEP_CNT_BUF2[15:8<br>]|Number of steps done since the last init of the pedometer feature. Filled in<br>alternativelywith PED_STEP_CNT_BUF1. Unit: number of steps|



## **18.43 IMEM_SRAM_REG_159** 

Name: IMEM_SRAM_REG_159 Address: 159 (9Fh) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Instant step cadence measured by the algorithm Unit: 4*number of samples|
|7:0|PED_STEP_CADENCE|between two consecutive steps. Cadency (step/s) = (ped_step_cadence / 4) /|
|||(pedometer_ODR).|



## **18.44 IMEM_SRAM_REG_160** 

Name: IMEM_SRAM_REG_160 Address: 160 (A0h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Activity classification of step detected|
|7:0|POWER_ACTIVITY_CLASS|00000000: Unknown<br>00000001: Walk|
|||00000010: Run|
|||Others: Reserved|



## **18.45 IMEM_SRAM_REG_182** 

Name: IMEM_SRAM_REG_182 Address: 182 (B6h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|7:0|ES_RAM_IMAGE_EN|Set 1 to load device specific RAM image for external sensor support,<br>otherwise set 0|



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## **18.46 IMEM_SRAM_REG_185** 

|**18.46 IMEM_SRAM_REG_185**|**18.46 IMEM_SRAM_REG_185**|**18.46 IMEM_SRAM_REG_185**|
|---|---|---|
|Name: IMEM_SRAM_REG_185<br>Address: 185 (B9h)<br>Serial IF: R/W<br>Reset value: Random value after reset until host runs EDMP_INIT procedure<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7:0|ES0_COMPASS_EN|Set 1 for compass support with es0, for other external sensors with es0, set<br>0|



## **18.47 IMEM_SRAM_REG_186** 

|Name: IMEM_SRAM_REG_186<br>Address: 186 (BAh)<br>Serial IF: R/W<br>Reset value: Random value after reset until host runs EDMP_INIT procedure<br>Clock Domain: MCLK|Name: IMEM_SRAM_REG_186<br>Address: 186 (BAh)<br>Serial IF: R/W<br>Reset value: Random value after reset until host runs EDMP_INIT procedure<br>Clock Domain: MCLK|Name: IMEM_SRAM_REG_186<br>Address: 186 (BAh)<br>Serial IF: R/W<br>Reset value: Random value after reset until host runs EDMP_INIT procedure<br>Clock Domain: MCLK|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:0|ES_POWER_MODE|Set 1 for possibility of power savings when APEX features utilization is<br>minimal. Set 0 when APEX features utilization is at maximum.|



## **18.48 IMEM_SRAM_REG_196** 

Name: IMEM_SRAM_REG_196 Address: 196 (C4h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Time of inactivity after which eDMP goes into power save mode.|
|7:0|POWER_SAVE_TIME[7:0]|Units: Time in sample number|
|||Range: [0 - 4294967295]|
|||Default: 6400 correspondingto 8s for ODR = 800Hz|



## **18.49 IMEM_SRAM_REG_197** 

Name: IMEM_SRAM_REG_197 Address: 197 (C5h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Time of inactivity after which eDMP goes into power save mode.|
|7:0|POWER_SAVE_TIME[15:8]|Units: Time in sample number|
|||Range: [0 - 4294967295]|
|||Default: 6400 correspondingto 8s for ODR = 800Hz|



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## **18.50 IMEM_SRAM_REG_198** 

Name: IMEM_SRAM_REG_198 Address: 198 (C6h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Time of inactivity after which eDMP goes into power save mode.|
|7:0|POWER_SAVE_TIME[23:16<br>]|Units: Time in sample number<br>Range: [0 - 4294967295]|
|||Default: 6400 correspondingto 8s for ODR = 800Hz|



## **18.51 IMEM_SRAM_REG_199** 

Name: IMEM_SRAM_REG_199 Address: 199 (C7h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Time of inactivity after which eDMP goes into power save mode.|
|7:0|POWER_SAVE_TIME[31:24<br>]|Units: Time in sample number<br>Range: [0 - 4294967295]|
|||Default: 6400 correspondingto 8s for ODR = 800Hz|



## **18.52 IMEM_SRAM_REG_288** 

Name: IMEM_SRAM_REG_288 Address: 288 (120h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Minimum freefall duration. Shorter freefalls are ignored.|
|7:0|FF_MIN_DURATION[7:0]|Unit: time in samples number<br>Range: [4 - 420]|
|||Default: 57(set for default ODR = 400 Hz,equivalent to 142 ms)|



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## **18.53 IMEM_SRAM_REG_289** 

Name: IMEM_SRAM_REG_289 Address: 289 (121h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Minimum freefall duration. Shorter freefalls are ignored.|
|7:0|FF_MIN_DURATION[15:8]|Unit: time in samples number<br>Range: [4 - 420]|
|||Default: 57(set for default ODR = 400 Hz,equivalent to 142 ms)|



## **18.54 IMEM_SRAM_REG_290** 

Name: IMEM_SRAM_REG_290 Address: 290 (122h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Minimum freefall duration. Shorter freefalls are ignored.|
|7:0|FF_MIN_DURATION[23:16]|Unit: time in samples number<br>Range: [4 - 420]|
|||Default: 57(set for default ODR = 400 Hz,equivalent to 142 ms)|



## **18.55 IMEM_SRAM_REG_291** 

Name: IMEM_SRAM_REG_291 Address: 291 (123h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK **BIT NAME FUNCTION** Minimum freefall duration. Shorter freefalls are ignored. Unit: time in samples number 7:0 FF_MIN_DURATION[31:24] Range: [4 - 420] Default: 57 (set for default ODR = 400 Hz, equivalent to 142 ms) 

## **18.56 IMEM_SRAM_REG_292** 

Name: IMEM_SRAM_REG_292 Address: 292 (124h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Maximum freefall duration. Longer freefalls are ignored.|
|7:0|FF_MAX_DURATION[7:0]|Unit: time in samples number<br>Range: [12 - 1040]|
|||Default: 285(set for default ODR = 400 Hz,equivalent to 712 ms)|



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## **18.57 IMEM_SRAM_REG_293** 

Name: IMEM_SRAM_REG_293 Address: 293 (125h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Maximum freefall duration. Longer freefalls are ignored.|
|7:0|FF_MAX_DURATION[15:8]|Unit: time in samples number<br>Range: [12 - 1040]|
|||Default: 285(set for default ODR = 400 Hz,equivalent to 712 ms)|



## **18.58 IMEM_SRAM_REG_294** 

Name: IMEM_SRAM_REG_294 Address: 294 (126h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Maximum freefall duration. Longer freefalls are ignored.|
|7:0|FF_MAX_DURATION[23:16<br>]|Unit: time in samples number<br>Range: [12 - 1040]|
|||Default: 285(set for default ODR = 400 Hz,equivalent to 712 ms)|



## **18.59 IMEM_SRAM_REG_295** 

Name: IMEM_SRAM_REG_295 Address: 295 (127h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK **BIT NAME FUNCTION** Maximum freefall duration. Longer freefalls are ignored. FF_MAX_DURATION[31:24 Unit: time in samples number 7:0 ] Range: [12 - 1040] Default: 285 (set for default ODR = 400 Hz, equivalent to 712 ms) 

## **18.60 IMEM_SRAM_REG_296** 

Name: IMEM_SRAM_REG_296 Address: 296 (128h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Period after a freefall is signaled during which a new freefall will not be|
|7:0|FF_DEBOUNCE_DURATION<br>[7:0]|detected. Prevents false detection due to bounces.<br>Unit: time in samples number<br>Range: [75 - 3000]|
|||Default: 800(set for default ODR = 800 Hz,equivalent to 1 s)|



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## **18.61 IMEM_SRAM_REG_297** 

Name: IMEM_SRAM_REG_297 Address: 297 (129h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Period after a freefall is signaled during which a new freefall will not be|
|7:0|FF_DEBOUNCE_DURATION<br>[15:8]|detected. Prevents false detection due to bounces.<br>Unit: time in samples number<br>Range: [75 - 3000]|
|||Default: 800(set for default ODR = 800 Hz,equivalent to 1 s)|



## **18.62 IMEM_SRAM_REG_298** 

Name: IMEM_SRAM_REG_298 Address: 298 (12Ah) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Period after a freefall is signaled during which a new freefall will not be|
|7:0|FF_DEBOUNCE_DURATION<br>[23:16]|detected. Prevents false detection due to bounces.<br>Unit: time in samples number<br>Range: [75 - 3000]|
|||Default: 800(set for default ODR = 800 Hz,equivalent to 1 s)|



## **18.63 IMEM_SRAM_REG_299** 

Name: IMEM_SRAM_REG_299 Address: 299 (12Bh) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Period after a freefall is signaled during which a new freefall will not be|
|7:0|FF_DEBOUNCE_DURATION<br>[31:24]|detected. Prevents false detection due to bounces.<br>Unit: time in samples number<br>Range: [75 - 3000]|
|||Default: 800(set for default ODR = 800 Hz,equivalent to 1 s)|



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## **18.64 IMEM_SRAM_REG_304** 

Name: IMEM_SRAM_REG_304 Address: 304 (130h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Threshold for accel values above which high-g state is detected.|
|7:0|HIGHG_PEAK_TH[7:0]|Unit: g in q12<br>Range: [1024 - 32768]|
|||Default: 29696|



## **18.65 IMEM_SRAM_REG_305** 

Name: IMEM_SRAM_REG_305 Address: 305 (131h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Threshold for accel values above which high-g state is detected.|
|7:0|HIGHG_PEAK_TH[15:8]|Unit: g in q12<br>Range: [1024 - 32768]|
|||Default: 29696|



## **18.66 IMEM_SRAM_REG_306** 

Name: IMEM_SRAM_REG_306 Address: 306 (132h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Hysteresis value subtracted from the high-g threshold after exceeding it.|
|7:0|HIGHG_PEAK_TH_HYST[7:0<br>]|Unit: g in q12<br>Range: [128 - 1024]|
|||Default: 640|



## **18.67 IMEM_SRAM_REG_307** 

Name: IMEM_SRAM_REG_307 Address: 307 (133h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Hysteresis value subtracted from the high-g threshold after exceeding it.|
|7:0|HIGHG_PEAK_TH_HYST[15:<br>8]|Unit: g in q12<br>Range: [128 - 1024]|
|||Default: 640|



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## **18.68 IMEM_SRAM_REG_308** 

Name: IMEM_SRAM_REG_308 Address: 308 (134h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Threshold for accel values above which high-g state is detected.|
|7:0|HIGHG_TIME_TH[7:0]|Unit: time in samples number<br>Range: [1-300]|
|||Default: 1(set for default ODR = 800 Hz,equivalent to 1.25 ms)|



## **18.69 IMEM_SRAM_REG_309** 

Name: IMEM_SRAM_REG_309 Address: 309 (135h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Threshold for accel values above which high-g state is detected.|
|7:0|HIGHG_TIME_TH[15:8]|Unit: time in samples number<br>Range: [1-300]|
|||Default: 1(set for default ODR = 800 Hz,equivalent to 1.25 ms)|



## **18.70 IMEM_SRAM_REG_316** 

Name: IMEM_SRAM_REG_316 Address: 316 (13Ch) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Threshold for accel values below which low-g state is detected.|
|7:0|LOWG_PEAK_TH[7:0]|Unit: g in q12<br>Range: [128 - 4096]|
|||Default: 2048|



## **18.71 IMEM_SRAM_REG_317** 

Name: IMEM_SRAM_REG_317 Address: 317 (13Dh) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Threshold for accel values below which low-g state is detected.|
|7:0|LOWG_PEAK_TH[15:8]|Unit: g in q12<br>Range: [128 - 4096]|
|||Default: 2048|



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## **18.72 IMEM_SRAM_REG_318** 

Name: IMEM_SRAM_REG_318 Address: 318 (13Eh) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Hysteresis value added to the low-g threshold after exceeding it.|
|7:0|LOWG_PEAK_TH_HYST[7:0<br>]|Unit: g in q12<br>Range: [128 - 1024]|
|||Default: 128|



## **18.73 IMEM_SRAM_REG_319** 

Name: IMEM_SRAM_REG_319 Address: 319 (13Fh) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Hysteresis value added to the low-g threshold after exceeding it.|
|7:0|LOWG_PEAK_TH_HYST[15:<br>8]|Unit: g in q12<br>Range: [128 - 1024]|
|||Default: 128|



## **18.74 IMEM_SRAM_REG_320** 

Name: IMEM_SRAM_REG_320 Address: 320 (140h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Number of samples required to enter low-g state.|
|7:0|LOWG_TIME_TH[7:0]|Unit: time in samples number<br>Range: [1 - 300]|
|||Default: 13(set for default ODR = 800 Hz,equivalent to 16 ms)|



## **18.75 IMEM_SRAM_REG_321** 

Name: IMEM_SRAM_REG_321 Address: 321 (141h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Number of samples required to enter low-g state.|
|7:0|LOWG_TIME_TH[15:8]|Unit: time in samples number<br>Range: [1 - 300]|
|||Default: 13(set for default ODR = 800 Hz,equivalent to 16 ms)|



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## **18.76 IMEM_SRAM_REG_392** 

Name: IMEM_SRAM_REG_392 Address: 392 (188h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Minimum duration for which the device should be tilted before signaling|
|||event.|
|7:0|TILT_WAIT_TIME[7:0]|Unit: time in sample number|
|||Range: [0 - 65536]|
|||Default: 200 for ODR = 50Hz,100 for ODR = 25Hz|



## **18.77 IMEM_SRAM_REG_393** 

Name: IMEM_SRAM_REG_393 Address: 393 (189h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Minimum duration for which the device should be tilted before signaling|
|||event.|
|7:0|TILT_WAIT_TIME[15:8]|Unit: time in sample number|
|||Range: [0 - 65536]|
|||Default: 200 for ODR = 50Hz,100 for ODR = 25Hz|



## **18.78 IMEM_SRAM_REG_400** 

Name: IMEM_SRAM_REG_400 Address: 400 (190h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Size of the analysis window to detect tap events (single-tap or double-tap)|
|7:0|TAP_TMAX[7:0]|unit: time in sample number<br>range: [49 – 496]|
|||default: 99(set for default ODR = 200Hz,equivalent to. 0.5s)|



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## **18.79 IMEM_SRAM_REG_401** 

Name: IMEM_SRAM_REG_401 Address: 401 (191h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Size of the analysis window to detect tap events (single-tap or double-tap)|
|7:0|TAP_TMAX[15:8]|unit: time in sample number<br>range: [49 – 496]|
|||default: 99(set for default ODR = 200Hz,equivalent to. 0.5s)|



## **18.80 IMEM_SRAM_REG_402** 

Name: IMEM_SRAM_REG_402 Address: 402 (192h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Single tap window, sub-windows within Tmax to detect single-tap event.|
|7:0|TAP_TMIN|Unit: time in sample number<br>Range: [24 – 184]|
|||Default: 33(set for default ODR = 200Hz,equivalent to. 0.165s)|



## **18.81 IMEM_SRAM_REG_403** 

Name: IMEM_SRAM_REG_403 Address: 403 (193h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||The minimal value of jerk to be considered as a tap candidate.|
|7:0|TAP_MIN_JERK|Unit: g in q6<br>Range: [0 - 64]|
|||Default: 17|



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## **18.82 IMEM_SRAM_REG_404** 

Name: IMEM_SRAM_REG_404 Address: 404 (194h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Max acceptable number of samples (jerk value) over TAP_MAX_PEAK_TOL|
|7:0|TAP_SMUDGE_REJECT_TH<br>R|during the Tmin window. Over this value, Tap event is rejected<br>unit: time in number of samples<br>range: [13 – 92]|
|||Default: 17(set for default ODR = 200Hz,equivalent to 0.085s)|



## **18.83 IMEM_SRAM_REG_405** 

Name: IMEM_SRAM_REG_405 Address: 405 (195h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Maximum peak tolerance is the percentage of pulse amplitude to get the|
|||smudge threshold for rejection.|
|7:0|TAP_MAX_PEAK_TOL|Range: [1 (12.5%) 2 (25.0%) 3 (37.5%) 4 (50.0 %)]|
|||Default: 2|
|||Default: 17|



## **18.84 IMEM_SRAM_REG_406** 

Name: IMEM_SRAM_REG_406 Address: 406 (196h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Energy measurement window size to determine the tap axis associated with|
|||the 1st tap.|
|7:0|TAP_TAVG|Unit: time in sample number|
|||Range: [1 ; 2 ; 4 ; 8]|
|||Default: 8|



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## **18.85 IMEM_SRAM_REG_540** 

Name: IMEM_SRAM_REG_540 Address: 540 (21Ch) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Defines the duration after wake event to report sleep event no matter if|
|7:0|R2W_SLEEP_TIME_OUT[7:<br>0]|position changes or not.<br>Unit: time in ms (millisecond)<br>Range: [100 - 10000]|
|||Default: 640(equivalent to 0.64s)|



## **18.86 IMEM_SRAM_REG_541** 

Name: IMEM_SRAM_REG_541 Address: 541 (21Dh) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Defines the duration after wake event to report sleep event no matter if|
|7:0|R2W_SLEEP_TIME_OUT[15<br>:8]|position changes or not.<br>Unit: time in ms (millisecond)<br>Range: [100 - 10000]|
|||Default: 640(equivalent to 0.64s)|



## **18.87 IMEM_SRAM_REG_542** 

Name: IMEM_SRAM_REG_542 Address: 542 (21Eh) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Defines the duration after wake event to report sleep event no matter if|
|7:0|R2W_SLEEP_TIME_OUT[23<br>:16]|position changes or not.<br>Unit: time in ms (millisecond)<br>Range: [100 - 10000]|
|||Default: 640(equivalent to 0.64s)|



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## **18.88 IMEM_SRAM_REG_543** 

Name: IMEM_SRAM_REG_543 Address: 543 (21Fh) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Defines the duration after wake event to report sleep event no matter if|
|7:0|R2W_SLEEP_TIME_OUT[31<br>:24]|position changes or not.<br>Unit: time in ms (millisecond)<br>Range: [100 - 10000]|
|||Default: 640(equivalent to 0.64s)|



## **18.89 IMEM_SRAM_REG_544** 

Name: IMEM_SRAM_REG_544 Address: 544 (220h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Defines the minimal duration of sleep position before trigger the sleep|
|7:0|R2W_SLEEP_GESTURE_DEL<br>AY[7:0]|event.<br>Unit: time in ms (millisecond)<br>Range: [0 - 256]|
|||Default: 96(equivalent to 0.096s)|



## **18.90 IMEM_SRAM_REG_545** 

Name: IMEM_SRAM_REG_545 Address: 545 (221h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Defines the minimal duration of sleep position before trigger the sleep|
|7:0|R2W_SLEEP_GESTURE_DEL<br>AY[15:8]|event.<br>Unit: time in ms (millisecond)<br>Range: [0 - 256]|
|||Default: 96(equivalent to 0.096s)|



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## **18.91 IMEM_SRAM_REG_546** 

Name: IMEM_SRAM_REG_546 Address: 546 (222h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Defines the minimal duration of sleep position before trigger the sleep|
|7:0|R2W_SLEEP_GESTURE_DEL<br>AY[23:16]|event.<br>Unit: time in ms (millisecond)<br>Range: [0 - 256]|
|||Default: 96(equivalent to 0.096s)|



## **18.92 IMEM_SRAM_REG_547** 

Name: IMEM_SRAM_REG_547 Address: 547 (223h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Defines the minimal duration of sleep position before trigger the sleep|
|7:0|R2W_SLEEP_GESTURE_DEL<br>AY[31:24]|event.<br>Unit: time in ms (millisecond)<br>Range: [0 - 256]|
|||Default: 96(equivalent to 0.096s)|



## **18.93 IMEM_SRAM_REG_548** 

Name: IMEM_SRAM_REG_548 Address: 548 (224h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Mounting matrix to rotate data from chip frame to device frame.|
|||Range: 3 lower bits only are used [b2 b1 b0]:|
|7:0|R2W_MOUNTING_MATRIX<br>[7:0]|-<br>b2 = 1 swap X and Y<br>-<br>b1 = 1 flip X sign|
|||-<br>b0 = 1 flip Y sign|
|||Default: 0(device frame aligned with android frame)|



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## **18.94 IMEM_SRAM_REG_549** 

Name: IMEM_SRAM_REG_549 Address: 549 (225h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Mounting matrix to rotate data from chip frame to device frame.|
|||Range: 3 lower bits only are used [b2 b1 b0]:|
|7:0|R2W_MOUNTING_MATRIX<br>[15:8]|-<br>b2 = 1 swap X and Y<br>-<br>b1 = 1 flip X sign|
|||-<br>b0 = 1 flip Y sign|
|||Default: 0(device frame aligned with android frame)|



## **18.95 IMEM_SRAM_REG_550** 

Name: IMEM_SRAM_REG_550 Address: 550 (226h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Mounting matrix to rotate data from chip frame to device frame.|
|||Range: 3 lower bits only are used [b2 b1 b0]:|
|7:0|R2W_MOUNTING_MATRIX<br>[23:16]|-<br>b2 = 1 swap X and Y<br>-<br>b1 = 1 flip X sign|
|||-<br>b0 = 1 flip Y sign|
|||Default: 0(device frame aligned with android frame)|



## **18.96 IMEM_SRAM_REG_551** 

Name: IMEM_SRAM_REG_551 Address: 551 (227h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Mounting matrix to rotate data from chip frame to device frame.|
|||Range: 3 lower bits only are used [b2 b1 b0]:|
|7:0|R2W_MOUNTING_MATRIX<br>[31:24]|-<br>b2 = 1 swap X and Y<br>-<br>b1 = 1 flip X sign|
|||-<br>b0 = 1 flip Y sign|
|||Default: 0(device frame aligned with android frame)|



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## **18.97 IMEM_SRAM_REG_556** 

Name: IMEM_SRAM_REG_556 Address: 556 (22Ch) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Gain used to filter the accelerometer to obtain an estimation of the gravity|
|7:0|R2W_GRAVITY_FILTER_GAI<br>N[7:0]|(low-pass filter), defined as: forgetting factor = Gain * SAMPLING_PERIOD /<br>(40 * 32), and 100Hz.<br>Range: [2-16]|
|||Default: 6 for ODR = 50Hz,8 for ODR = 25Hz|



## **18.98 IMEM_SRAM_REG_557** 

Name: IMEM_SRAM_REG_557 Address: 557 (22Dh) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Gain used to filter the accelerometer to obtain an estimation of the gravity|
|7:0|R2W_GRAVITY_FILTER_GAI<br>N[15:8]|(low-pass filter), defined as: forgetting factor = Gain * SAMPLING_PERIOD /<br>(40 * 32), and 100Hz.<br>Range: [2-16]|
|||Default: 6 for ODR = 50Hz,8 for ODR = 25Hz|



## **18.99 IMEM_SRAM_REG_558** 

Name: IMEM_SRAM_REG_558 Address: 558 (22Eh) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Gain used to filter the accelerometer to obtain an estimation of the gravity|
|7:0|R2W_GRAVITY_FILTER_GAI<br>N[23:16]|(low-pass filter), defined as: forgetting factor = Gain * SAMPLING_PERIOD /<br>(40 * 32), and 100Hz.<br>Range: [2-16]|
|||Default: 6 for ODR = 50Hz,8 for ODR = 25Hz|



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## **18.100 IMEM_SRAM_REG_559** 

Name: IMEM_SRAM_REG_559 Address: 559 (22Fh) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Gain used to filter the accelerometer to obtain an estimation of the gravity|
|7:0|R2W_GRAVITY_FILTER_GAI<br>N[31:24]|(low-pass filter), defined as: forgetting factor = Gain * SAMPLING_PERIOD /<br>(40 * 32), and 100Hz.<br>Range: [2-16]|
|||Default: 6 for ODR = 50Hz,8 for ODR = 25Hz|



## **18.101 IMEM_SRAM_REG_560** 

Name: IMEM_SRAM_REG_560 Address: 560 (230h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Set the minimal angle that needed to be applied to device to detect R2W|
|7:0|R2W_MOTION_THR_ANGL<br>E_COSINE[7:0]|Unit: fixed point value q30 of cosine of the angle<br>Range: [130856211 - 1069655912], corresponding to angle between 5 and<br>85 degrees|
|||Default: 1046221864,correspondingto an angle of 13 degrees|



## **18.102 IMEM_SRAM_REG_561** 

Name: IMEM_SRAM_REG_561 Address: 561 (231h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Set the minimal angle that needed to be applied to device to detect R2W|
|7:0|R2W_MOTION_THR_ANGL<br>E_COSINE[15:8]|Unit: fixed point value q30 of cosine of the angle<br>Range: [130856211 - 1069655912], corresponding to angle between 5 and<br>85 degrees|
|||Default: 1046221864,correspondingto an angle of 13 degrees|



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## **18.103 IMEM_SRAM_REG_562** 

Name: IMEM_SRAM_REG_562 Address: 562 (232h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Set the minimal angle that needed to be applied to device to detect R2W|
|7:0|R2W_MOTION_THR_ANGL<br>E_COSINE[23:16]|Unit: fixed point value q30 of cosine of the angle<br>Range: [130856211 - 1069655912], corresponding to angle between 5 and<br>85 degrees|
|||Default: 1046221864,correspondingto an angle of 13 degrees|



## **18.104 IMEM_SRAM_REG_563** 

Name: IMEM_SRAM_REG_563 Address: 563 (233h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Set the minimal angle that needed to be applied to device to detect R2W|
|7:0|R2W_MOTION_THR_ANGL<br>E_COSINE[31:24]|Unit: fixed point value q30 of cosine of the angle<br>Range: [130856211 - 1069655912], corresponding to angle between 5 and<br>85 degrees|
|||Default: 1046221864,correspondingto an angle of 13 degrees|



## **18.105 IMEM_SRAM_REG_564** 

Name: IMEM_SRAM_REG_564 Address: 564 (234h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Timer relative to the rapidity of the algorithm to trigger wake up when the|
|||orientation before motion is Y axis up (with less than 30 degrees of|
|7:0|R2W_MOTION_THR_TIME<br>R_FAST[7:0]|inclination).<br>Unit: ms (no dependency on ODR, it is managed internally by the algorithm)|
|||Range: [100 - 500]|
|||Default: 240|



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## **18.106 IMEM_SRAM_REG_565** 

Name: IMEM_SRAM_REG_565 Address: 565 (235h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Timer relative to the rapidity of the algorithm to trigger wake up when the|
|||orientation before motion is Y axis up (with less than 30 degrees of|
|7:0|R2W_MOTION_THR_TIME<br>R_FAST[15:8]|inclination).<br>Unit: ms (no dependency on ODR, it is managed internally by the algorithm)|
|||Range: [100 - 500]|
|||Default: 240|



## **18.107 IMEM_SRAM_REG_566** 

Name: IMEM_SRAM_REG_566 Address: 566 (236h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Timer relative to the rapidity of the algorithm to trigger wake up when the|
|||orientation before motion is Y axis up (with less than 30 degrees of|
|7:0|R2W_MOTION_THR_TIME<br>R_FAST[23:16]|inclination).<br>Unit: ms (no dependency on ODR, it is managed internally by the algorithm)|
|||Range: [100 - 500]|
|||Default: 240|



## **18.108 IMEM_SRAM_REG_567** 

Name: IMEM_SRAM_REG_567 Address: 567 (237h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Timer relative to the rapidity of the algorithm to trigger wake up when the|
|||orientation before motion is Y axis up (with less than 30 degrees of|
|7:0|R2W_MOTION_THR_TIME<br>R_FAST[31:24]|inclination).<br>Unit: ms (no dependency on ODR, it is managed internally by the algorithm)|
|||Range: [100 - 500]|
|||Default: 240|



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## **18.109 IMEM_SRAM_REG_568** 

Name: IMEM_SRAM_REG_568 Address: 568 (238h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Timer relative to the rapidity of the algorithm to trigger wake up when the|
|||orientation before motion is Y axis up (with less than 30 degrees of|
|7:0|R2W_MOTION_THR_TIME<br>R_SLOW[7:0]|inclination).<br>Unit: ms (no dependency on ODR, it is managed internally by the algorithm)|
|||Range: [100 - 500]|
|||Default: 240|



## **18.110 IMEM_SRAM_REG_569** 

Name: IMEM_SRAM_REG_569 Address: 569 (239h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Timer relative to the rapidity of the algorithm to trigger wake up when the|
|||orientation before motion is Y axis up (with less than 30 degrees of|
|7:0|R2W_MOTION_THR_TIME<br>R_SLOW[15:8]|inclination).<br>Unit: ms (no dependency on ODR, it is managed internally by the algorithm)|
|||Range: [100 - 500]|
|||Default: 240|



## **18.111 IMEM_SRAM_REG_570** 

Name: IMEM_SRAM_REG_570 Address: 570 (23Ah) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Timer relative to the rapidity of the algorithm to trigger wake up when the|
|||orientation before motion is Y axis up (with less than 30 degrees of|
|7:0|R2W_MOTION_THR_TIME<br>R_SLOW[23:16]|inclination).<br>Unit: ms (no dependency on ODR, it is managed internally by the algorithm)|
|||Range: [100 - 500]|
|||Default: 240|



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## **18.112 IMEM_SRAM_REG_571** 

Name: IMEM_SRAM_REG_571 Address: 571 (23Bh) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Timer relative to the rapidity of the algorithm to trigger wake up when the|
|||orientation before motion is Y axis up (with less than 30 degrees of|
|7:0|R2W_MOTION_THR_TIME<br>R_SLOW[31:24]|inclination).<br>Unit: ms (no dependency on ODR, it is managed internally by the algorithm)|
|||Range: [100 - 500]|
|||Default: 240|



## **18.113 IMEM_SRAM_REG_572** 

Name: IMEM_SRAM_REG_572 Address: 572 (23Ch) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Time delay to update internal value of previous gravity when no motion is|
|||detected.|
|7:0|R2W_MOTION_PREV_GRA<br>VITY_TIMEOUT[7:0]|Longer time enables detection motion during slower gesture.<br>Unit: ms (no dependency on ODR, it is managed internally by the algorithm)|
|||Range: [100 - 1000]|
|||Default: 300|



## **18.114 IMEM_SRAM_REG_573** 

Name: IMEM_SRAM_REG_573 Address: 573 (23Dh) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Time delay to update internal value of previous gravity when no motion is|
|||detected.|
|7:0|R2W_MOTION_PREV_GRA<br>VITY_TIMEOUT[15:8]|Longer time enables detection motion during slower gesture.<br>Unit: ms (no dependency on ODR, it is managed internally by the algorithm)|
|||Range: [100 - 1000]|
|||Default: 300|



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## **18.115 IMEM_SRAM_REG_574** 

Name: IMEM_SRAM_REG_574 Address: 574 (23Eh) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Time delay to update internal value of previous gravity when no motion is|
|||detected.|
|7:0|R2W_MOTION_PREV_GRA<br>VITY_TIMEOUT[23:16]|Longer time enables detection motion during slower gesture.<br>Unit: ms (no dependency on ODR, it is managed internally by the algorithm)|
|||Range: [100 - 1000]|
|||Default: 300|



## **18.116 IMEM_SRAM_REG_575** 

Name: IMEM_SRAM_REG_575 Address: 575 (23Fh) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Time delay to update internal value of previous gravity when no motion is|
|||detected.|
|7:0|R2W_MOTION_PREV_GRA<br>VITY_TIMEOUT[31:24]|Longer time enables detection motion during slower gesture.<br>Unit: ms (no dependency on ODR, it is managed internally by the algorithm)|
|||Range: [100 - 1000]|
|||Default: 300|



## **18.117 IMEM_SRAM_REG_576** 

Name: IMEM_SRAM_REG_576 Address: 576 (240h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Time delay to update the current gravity estimator when no motion is|
|7:0|R2W_LAST_GRAVITY_MOT<br>ION_TIMER[7:0]|detected.<br>Unit: ms (no dependency on ODR, it is managed internally by the algorithm)<br>Range: [100 - 1000]|
|||Default: 480|



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## **18.118 IMEM_SRAM_REG_577** 

Name: IMEM_SRAM_REG_577 Address: 577 (241h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Time delay to update the current gravity estimator when no motion is|
|7:0|R2W_LAST_GRAVITY_MOT<br>ION_TIMER[15:8]|detected.<br>Unit: ms (no dependency on ODR, it is managed internally by the algorithm)<br>Range: [100 - 1000]|
|||Default: 480|



## **18.119 IMEM_SRAM_REG_578** 

Name: IMEM_SRAM_REG_578 Address: 578 (242h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Time delay to update the current gravity estimator when no motion is|
|7:0|R2W_LAST_GRAVITY_MOT<br>ION_TIMER[23:16]|detected.<br>Unit: ms (no dependency on ODR, it is managed internally by the algorithm)<br>Range: [100 - 1000]|
|||Default: 480|



## **18.120 IMEM_SRAM_REG_579** 

Name: IMEM_SRAM_REG_579 Address: 579 (243h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Time delay to update the current gravity estimator when no motion is|
|7:0|R2W_LAST_GRAVITY_MOT<br>ION_TIMER[31:24]|detected.<br>Unit: ms (no dependency on ODR, it is managed internally by the algorithm)<br>Range: [100 - 1000]|
|||Default: 480|



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## **18.121 IMEM_SRAM_REG_580** 

Name: IMEM_SRAM_REG_580 Address: 580 (244h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Time delay to update gravity in case motion is detected all the time, force to|
|7:0|R2W_LAST_GRAVITY_TIME<br>OUT[7:0]|update gravity estimator even if the device is not stable.<br>Unit: ms (no dependency on ODR, it is managed internally by the algorithm)<br>Range: [1000 - 10000]|
|||Default: 2600|



## **18.122 IMEM_SRAM_REG_581** 

Name: IMEM_SRAM_REG_581 Address: 581 (245h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Time delay to update gravity in case motion is detected all the time, force to|
|7:0|R2W_LAST_GRAVITY_TIME<br>OUT[15:8]|update gravity estimator even if the device is not stable.<br>Unit: ms (no dependency on ODR, it is managed internally by the algorithm)<br>Range: [1000 - 10000]|
|||Default: 2600|



## **18.123 IMEM_SRAM_REG_582** 

Name: IMEM_SRAM_REG_582 Address: 582 (246h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Time delay to update gravity in case motion is detected all the time, force to|
|7:0|R2W_LAST_GRAVITY_TIME<br>OUT[23:16]|update gravity estimator even if the device is not stable.<br>Unit: ms (no dependency on ODR, it is managed internally by the algorithm)<br>Range: [1000 - 10000]|
|||Default: 2600|



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## **18.124 IMEM_SRAM_REG_583** 

Name: IMEM_SRAM_REG_583 Address: 583 (247h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Time delay to update gravity in case motion is detected all the time, force to|
|7:0|R2W_LAST_GRAVITY_TIME<br>OUT[31:24]|update gravity estimator even if the device is not stable.<br>Unit: ms (no dependency on ODR, it is managed internally by the algorithm)<br>Range: [1000 - 10000]|
|||Default: 2600|



## **18.125 IMEM_SRAM_REG_584** 

Name: IMEM_SRAM_REG_584 Address: 584 (248h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||If gesture is not completed in this timeout limit, gesture is invalid.|
|7:0|R2W_GESTURE_VALIDITY_<br>TIMEOUT[7:0]|Unit: ms (no dependency on ODR, it is managed internally by the algorithm)<br>Range: [100 - 1000]|
|||Default: 240|



## **18.126 IMEM_SRAM_REG_585** 

Name: IMEM_SRAM_REG_585 Address: 585 (249h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||If gesture is not completed in this timeout limit, gesture is invalid.|
|7:0|R2W_GESTURE_VALIDITY_<br>TIMEOUT[15:8]|Unit: ms (no dependency on ODR, it is managed internally by the algorithm)<br>Range: [100 - 1000]|
|||Default: 240|



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## **18.127 IMEM_SRAM_REG_586** 

Name: IMEM_SRAM_REG_586 Address: 586 (24Ah) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||If gesture is not completed in this timeout limit, gesture is invalid.|
|7:0|R2W_GESTURE_VALIDITY_<br>TIMEOUT[23:16]|Unit: ms (no dependency on ODR, it is managed internally by the algorithm)<br>Range: [100 - 1000]|
|||Default: 240|



## **18.128 IMEM_SRAM_REG_587** 

Name: IMEM_SRAM_REG_587 Address: 587 (24Bh) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||If gesture is not completed in this timeout limit, gesture is invalid.|
|7:0|R2W_GESTURE_VALIDITY_<br>TIMEOUT[31:24]|Unit: ms (no dependency on ODR, it is managed internally by the algorithm)<br>Range: [100 - 1000]|
|||Default: 240|



## **18.129 IMEM_SRAM_REG_988** 

Name: IMEM_SRAM_REG_988 Address: 988 (3DCh) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Minimum number of steps that must be detected before step count is|
|||incremented.|
|||Low values reduce latency but increase false positives.|
|7:0|PED_STEP_CNT_TH[7:0]|High values increase step count accuracy but increase latency|
|||Unit: Number of steps|
|||Range: [0-15]|
|||Default: 5|



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## **18.130 IMEM_SRAM_REG_989** 

Name: IMEM_SRAM_REG_989 Address: 989 (3DDh) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Minimum number of steps that must be detected before step count is|
|||incremented.|
|||Low values reduce latency but increase false positives.|
|7:0|PED_STEP_CNT_TH[15:8]|High values increase step count accuracy but increase latency|
|||Unit: Number of steps|
|||Range: [0-15]|
|||Default: 5|



## **18.131 IMEM_SRAM_REG_990** 

Name: IMEM_SRAM_REG_990 Address: 990 (3DEh) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Minimum number of steps that must be detected before step event is|
|||signaled.|
|||Low values reduce latency but increase false positives.|
|7:0|PED_STEP_DET_TH[7:0]|High values increase step event validity but increase latency.|
|||Unit: number of steps|
|||Range: [0-7]|
|||Default: 2|



## **18.132 IMEM_SRAM_REG_991** 

Name: IMEM_SRAM_REG_991 Address: 991 (3DFh) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Minimum number of steps that must be detected before step event is|
|||signaled.|
|||Low values reduce latency but increase false positives.|
|7:0|PED_STEP_DET_TH[15:8]|High values increase step event validity but increase latency.|
|||Unit: number of steps|
|||Range: [0-7]|
|||Default: 2|



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## **18.133 IMEM_SRAM_REG_994** 

Name: IMEM_SRAM_REG_994 Address: 994 (3E2h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||While in the step buffer state, the step buffer count resets to 0 if a new step|
|||isn't detected for this amount of time (user is considered to have "stopped|
|7:0|PED_SB_TIMER_TH[7:0]|walking").<br>Unit: time in samples number|
|||Range: [0 - 225]|
|||Default: 150 for ODR = 50Hz|



## **18.134 IMEM_SRAM_REG_995** 

Name: IMEM_SRAM_REG_995 Address: 995 (3E3h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||While in the step buffer state, the step buffer count resets to 0 if a new step|
|||isn't detected for this amount of time (user is considered to have "stopped|
|7:0|PED_SB_TIMER_TH[15:8]|walking").<br>Unit: time in samples number|
|||Range: [0 - 225]|
|||Default: 150 for ODR = 50Hz|



## **18.135 IMEM_SRAM_REG_1000** 

Name: IMEM_SRAM_REG_1000 Address: 1000 (3E8h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Threshold to select a valid step. Used to increase step detection for slow|
|7:0|PED_LOW_EN_AMP_TH[7:<br>0]|walk use case only.<br>Unit: g in q25.<br>Range: [1006632 - 3523215]|
|||Default: 2684354|



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## **18.136 IMEM_SRAM_REG_1001** 

Name: IMEM_SRAM_REG_1001 Address: 1001 (3E9h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Threshold to select a valid step. Used to increase step detection for slow|
|7:0|PED_LOW_EN_AMP_TH[15<br>:8]|walk use case only.<br>Unit: g in q25.<br>Range: [1006632 - 3523215]|
|||Default: 2684354|



## **18.137 IMEM_SRAM_REG_1002** 

Name: IMEM_SRAM_REG_1002 Address: 1002 (3EAh) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Threshold to select a valid step. Used to increase step detection for slow|
|7:0|PED_LOW_EN_AMP_TH[23<br>:16]|walk use case only.<br>Unit: g in q25.<br>Range: [1006632 - 3523215]|
|||Default: 2684354|



## **18.138 IMEM_SRAM_REG_1003** 

Name: IMEM_SRAM_REG_1003 Address: 1003 (3EBh) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Threshold to select a valid step. Used to increase step detection for slow|
|7:0|PED_LOW_EN_AMP_TH[31<br>:24]|walk use case only.<br>Unit: g in q25.<br>Range: [1006632 - 3523215]|
|||Default: 2684354|



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## **18.139 IMEM_SRAM_REG_1004** 

Name: IMEM_SRAM_REG_1004 Address: 1004 (3ECh) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Pedometer sensitivity mode.|
|||Slow walk mode improves slow walk detection (<1 Hz) but the number of|
|7:0|PED_SENSITIVITY_MODE|false positives may increase|
|||Range: 0: Normal 1: Slow walk|
|||Default: 0|



## **18.140 IMEM_SRAM_REG_1008** 

Name: IMEM_SRAM_REG_1008 Address: 1008 (3F0h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Threshold of step detection sensitivity.|
|||Low values increase detection sensitivity: reduce miss-detection.|
|7:0|PED_AMP_TH[7:0]|High values reduce detection sensitivity: reduce false-positive.<br>Unit: g in q25.|
|||Range: [1006632 - 3019898]|
|||Default: 2080374|



## **18.141 IMEM_SRAM_REG_1009** 

Name: IMEM_SRAM_REG_1009 Address: 1009 (3F1h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Threshold of step detection sensitivity.|
|||Low values increase detection sensitivity: reduce miss-detection.|
|7:0|PED_AMP_TH[15:8]|High values reduce detection sensitivity: reduce false-positive.<br>Unit: g in q25.|
|||Range: [1006632 - 3019898]|
|||Default: 2080374|



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## **18.142 IMEM_SRAM_REG_1010** 

Name: IMEM_SRAM_REG_1010 Address: 1010 (3F2h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Threshold of step detection sensitivity.|
|||Low values increase detection sensitivity: reduce miss-detection.|
|7:0|PED_AMP_TH[23:16]|High values reduce detection sensitivity: reduce false-positive.<br>Unit: g in q25.|
|||Range: [1006632 - 3019898]|
|||Default: 2080374|



## **18.143 IMEM_SRAM_REG_1011** 

Name: IMEM_SRAM_REG_1011 Address: 1011 (3F3h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Threshold of step detection sensitivity.|
|||Low values increase detection sensitivity: reduce miss-detection.|
|7:0|PED_AMP_TH[31:24]|High values reduce detection sensitivity: reduce false-positive.<br>Unit: g in q25.|
|||Range: [1006632 - 3019898]|
|||Default: 2080374|



## **18.144 IMEM_SRAM_REG_1016** 

Name: IMEM_SRAM_REG_1016 Address: 1016 (3F8h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Threshold to classify acceleration signal as motion not due to steps|
|||High values improve vibration rejection.|
|7:0|PED_HI_EN_TH[7:0]|Low values improve detection.<br>Unit: g in q25.|
|||Range: [2949120 - 5210112]|
|||Default: 3506176|



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## **18.145 IMEM_SRAM_REG_1017** 

Name: IMEM_SRAM_REG_1017 Address: 1017 (3F9h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Threshold to classify acceleration signal as motion not due to steps|
|||High values improve vibration rejection.|
|7:0|PED_HI_EN_TH[15:8]|Low values improve detection.<br>Unit: g in q25.|
|||Range: [2949120 - 5210112]|
|||Default: 3506176|



## **18.146 IMEM_SRAM_REG_1018** 

Name: IMEM_SRAM_REG_1018 Address: 1018 (3FAh) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Threshold to classify acceleration signal as motion not due to steps|
|||High values improve vibration rejection.|
|7:0|PED_HI_EN_TH[23:16]|Low values improve detection.<br>Unit: g in q25.|
|||Range: [2949120 - 5210112]|
|||Default: 3506176|



## **18.147 IMEM_SRAM_REG_1019** 

Name: IMEM_SRAM_REG_1019 Address: 1019 (3FBh) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Threshold to classify acceleration signal as motion not due to steps|
|||High values improve vibration rejection.|
|7:0|PED_HI_EN_TH[31:24]|Low values improve detection.<br>Unit: g in q25.|
|||Range: [2949120 - 5210112]|
|||Default: 3506176|



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## **18.148 IMEM_SRAM_REG_1042** 

Name: IMEM_SRAM_REG_1042 Address: 1042 (412h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Parameter to tune SMD algorithm robustness to rejection, ranging from 0 to|
|||4 (values higher than 4 are reserved).|
|||Low values increase detection rate but increase false positives.|
|7:0|SMD_SENSITIVITY|High values reduce false positives but reduce detection rate (especially for|
|||transport use cases).|
|||Range: [0 - 4]|
|||Default: 0|



## **18.149 IMEM_SRAM_REG_1168 TO IMEM_SRAM_REG_1203** 

Name: IMEM_SRAM_REG_1168 to IMEM_SRAM_REG_1203 Address: 1168 to 1203 (490h to 4B3h) Serial IF: R/W Reset value: Random value after reset until host runs EDMP_INIT procedure Clock Domain: MCLK **BIT NAME FUNCTION** SOFT_IRON_SENSITIVITY_ 7:0 Input 3x3 calibration matrix in q14 format applied to uncalibrated data. MATRIX[287:0] 

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## _**19 USER BANK IPREG_BAR REGISTER MAP – DESCRIPTIONS**_ 

This section describes the function and contents of each register within user bank IPREG_BAR. The registers described in this section are indirect access registers. Section 13 describes the procedure for accessing indirect access registers. 

## **19.1 IPREG_BAR_REG_57** 

Name: IPREG_BAR_REG_57 Address: 57 (39h) Serial IF: R/W Reset value: 0x33 Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|7|-|Reserved|
|||Set this register field to 1 for optimal speed of IOs.|
|6|IO_OPT0|IO_OPT1 must be also set to 1 if IO_OPT0 is set to 1.|
|||Can be changed on-the-fly.|
|||Set this register field to 1 for optimal speed of IOs.|
|5|IO_OPT1||
|||Can be changed on-the-fly.|
|4:0|-|Reserved|



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## **19.2 IPREG_BAR_REG_58** 

|**19.2**<br>**IPREG_BAR_REG_58**|**19.2**<br>**IPREG_BAR_REG_58**|**19.2**<br>**IPREG_BAR_REG_58**|
|---|---|---|
|Name: IPREG_BAR_REG_58<br>Address: 58 (3Ah)<br>Serial IF: R/W<br>Reset value: 0xD9<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7|PADS_AP_SCLK_PUD_TRIM<br>_D2A|Selects internal resistor pull direction for AP_SCLK pin (pin 13)<br>0: Down<br>1: Up<br>Can be changed on-the-fly.|
|6|PADS_AP_SCLK_PE_TRIM_<br>D2A|Enables internal pull resistor to pull up or down for AP_SCLK pin (pin 13),<br>depending on direction selected by bit 7.<br>0: Not enabled<br>1: Enabled<br>Can be changed on-the-fly.|
|5|-|Reserved|
|4|PADS_AP_CS_PUD_TRIM_<br>D2A|Selects internal resistor pull direction for AP_CS pin (pin 12)<br>0: Down<br>1: Up<br>Can be changed on-the-fly.|
|3|PADS_AP_CS_PE_TRIM_D2<br>A|Enables internal pull resistor to pull up or down for AP_CS pin (pin 12),<br>depending on direction selected by bit 4.<br>0: Not enabled<br>1: Enabled<br>Can be changed on-the-fly.|
|2:1|-|Reserved|
|0|IO_OPT2|Set this register field to 1 for optimal speed of IOs.<br>IO_OPT1 must be also set to 1 if IO_OPT2 is set to 1<br>Can be changed on-the-fly.|



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## **19.3 IPREG_BAR_REG_59** 

|**19.3**<br>**IPREG_BAR_REG_59**|**19.3**<br>**IPREG_BAR_REG_59**|**19.3**<br>**IPREG_BAR_REG_59**|
|---|---|---|
|Name: IPREG_BAR_REG_59<br>Address: 59 (3Bh)<br>Serial IF: R/W<br>Reset value: 0xB6<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7|PADS_PIN7_PE_TRIM_D2A|Enables internal pull resistor to pull up or down for pin 7, depending on<br>direction selected by bit 0 of register IPREG_BAR_REG_60<br>0: Not enabled<br>1: Enabled<br>Can be changed on-the-fly.|
|6|-|Reserved|
|5|PADS_AP_SDO_PUD_TRIM<br>_D2A|Selects internal resistor pull direction for AP_SDO pin (pin 1)<br>0: Down<br>1: Up<br>Can be changed on-the-fly.|
|4|PADS_AP_SDO_PE_TRIM_<br>D2A|Enables internal pull resistor to pull up or down for AP_SDO pin (pin 1),<br>depending on direction selected by bit 5.<br>0: Not enabled<br>1: Enabled<br>Can be changed on-the-fly.|
|3|-|Reserved|
|2|PADS_AP_SDI_PUD_TRIM_<br>D2A|Selects internal resistor pull direction for AP_SDI pin (pin 14)<br>0: Down<br>1: Up<br>Can be changed on-the-fly.|
|1|PADS_AP_SDI_PE_TRIM_D<br>2A|Enables internal pull resistor to pull up or down for AP_SDI pin (pin 14),<br>depending on direction selected by bit 2.<br>0: Not enabled<br>1: Enabled<br>Can be changed on-the-fly.|
|0|-|Reserved|



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## **19.4 IPREG_BAR_REG_60** 

|**19.4**<br>**IPREG_BAR_REG_60**|**19.4**<br>**IPREG_BAR_REG_60**|**19.4**<br>**IPREG_BAR_REG_60**|
|---|---|---|
|Name: IPREG_BAR_REG_60<br>Address: 60 (3Ch)<br>Serial IF: R/W<br>Reset value: 0x6D<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7|-|Reserved|
|6|PADS_AUX1_SCLK_PUD_TR<br>IM_D2A|Enables internal pull resistor to pull up or down for AUX1_SCLK pin (pin 3),<br>depending on direction selected by bit 5.<br>0: Not enabled<br>1: Enabled<br>Can be changed on-the-fly.|
|5|PADS_AUX1_SCLK_PE_TRI<br>M_D2A|Selects internal resistor pull direction for AUX1_SCLK pin (pin 3)<br>0: Down<br>1: Up<br>Can be changed on-the-fly.|
|4|PADS_AUX_SCLK_TP2_FRO<br>M_PAD_DISABLE_TRIM_D<br>2A|Set this bit to 1 if using I2C master mode. Set it to 0 otherwise.|
|3|PADS_AUX1_CS_PUD_TRI<br>M_D2A|Enables internal pull resistor to pull up or down for AUX1_CS pin (pin 10),<br>depending on direction selected by bit 2.<br>0: Not enabled<br>1: Enabled<br>Can be changed on-the-fly.|
|2|PADS_AUX1_CS_PE_TRIM_<br>D2A|Selects internal resistor pull direction for AUX1_CS pin (pin 10)<br>0: Down<br>1: Up<br>Can be changed on-the-fly.|
|1|-|Reserved|
|0|PADS_PIN7_CS_PUD_TRIM<br>_D2A|Selects internal resistor pull direction for pin 7<br>0: Down<br>1: Up<br>Can be changed on-the-fly.|



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## **19.5 IPREG_BAR_REG_61** 

|**19.5**<br>**IPREG_BAR_REG_61**|**19.5**<br>**IPREG_BAR_REG_61**|**19.5**<br>**IPREG_BAR_REG_61**|
|---|---|---|
|Name: IPREG_BAR_REG_61<br>Address: 61 (3Dh)<br>Serial IF: R/W<br>Reset value: 0xBB<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7|PADS_INT1_PUD_TRIM_D2<br>A|Enables internal pull resistor to pull up or down for INT1 pin (pin 4),<br>depending on direction selected by bit 6.<br>0: Not enabled<br>1: Enabled<br>Can be changed on-the-fly.|
|6|PADS_INT1_PE_TRIM_D2A|Selects internal resistor pull direction for INT1 pin (pin 4)<br>0: Down<br>1: Up<br>Can be changed on-the-fly.|
|5|-|Reserved|
|4|PADS_AUX1_SDO_PUD_TR<br>IM_D2A|Selects internal resistor pull direction for AUX1_SDO pin (pin 11)<br>0: Down<br>1: Up<br>Can be changed on-the-fly.|
|3|PADS_AUX1_SDO_PE_TRI<br>M_D2A|Enables internal pull resistor to pull up or down for AUX1_SDO pin (pin 11),<br>depending on direction selected by bit 4.<br>0: Not enabled<br>1: Enabled<br>Can be changed on-the-fly.|
|2|-|Reserved|
|1|PADS_AUX1_SDI_PUD_TRI<br>M_D2A|Enables internal pull resistor to pull up or down for AUX1_SDI pin (pin 2),<br>depending on direction selected by bit 0.<br>0: Not enabled<br>1: Enabled<br>Can be changed on-the-fly.|
|0|PADS_AUX1_SDI_PE_TRIM<br>_D2A|Selects internal resistor pull direction for AUX1_SDI pin (pin 2)<br>0: Down<br>1: Up<br>Can be changed on-the-fly.|



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## **19.6 IPREG_BAR_REG_62** 

|**19.6**<br>**IPREG_BAR_REG_62**|**19.6**<br>**IPREG_BAR_REG_62**|**19.6**<br>**IPREG_BAR_REG_62**|
|---|---|---|
|Name: IPREG_BAR_REG_62<br>Address: 62 (3Eh)<br>Serial IF: R/W<br>Reset value: 0x06<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7:3|-|Reserved|
|2|PADS_INT2_PUD_TRIM_D2<br>A|Selects internal resistor pull direction for INT2 pin (pin 9)<br>0: Down<br>1: Up<br>Can be changed on-the-fly.|
|1|PADS_INT2_PE_TRIM_D2A|Enables internal pull resistor to pull up or down for INT2 pin (pin 9),<br>depending on direction selected by bit 2.<br>0: Not enabled<br>1: Enabled<br>Can be changed on-the-fly.|
|0|-|Reserved|



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## _**20 USER BANK IPREG_TOP1 REGISTER MAP – DESCRIPTIONS**_ 

This section describes the function and contents of each register within user bank IPREG_TOP1. The registers described in this section are indirect access registers. Section 13 describes the procedure for accessing indirect access registers. 

## **20.1 I2CM_COMMAND_0** 

Name: I2CM_COMMAND_0 (I[2] C master command buffer 0) Address: 06 (06h) Serial IF: R/W Reset value: 0x00 Clock Domain: MCLK 

|**20.1**<br>**I2CM_COMMAND_0**|**20.1**<br>**I2CM_COMMAND_0**|**20.1**<br>**I2CM_COMMAND_0**|
|---|---|---|
|Name: I2CM_COMMAND_0 (I[2]C master command buffer 0)<br>Address: 06 (06h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7|ENDFLAG_0|Indicates if the current entry is the last I2C master communication with the<br>external slave device.|
|6|CH_SEL_0|Specifies the channel number for I2C master transaction.<br>Two external sensors are supported.<br>0: Specify one external sensor with device ID “ID1”<br>1: Specify the other external sensor with device ID “ID2”<br>“ID1” and “ID2” should be replaced by the actual device ID of the chosen<br>external devices.|
|5:4|R_W_0|I2C master read/write command.<br>00: Write operation<br>01: Read operation with register address specified<br>10: Read operation without register address specified<br>11: Reserved|
|3:0|BURSTLEN_0|Specifies the burst length of I2C master communication with the external<br>slave device.<br>0000: Reserved<br>0001: 1 byte<br>0010: 2 bytes<br>0011: 3 bytes<br>0100: 4 bytes<br>0101: 5 bytes<br>0110: 6 bytes<br>0111: 7 bytes<br>1000: 8 bytes<br>1001: 9 bytes<br>1010: 10 bytes<br>1011: 11 bytes<br>1100: 12 bytes<br>1101: 13 bytes<br>1110: 14 bytes<br>1111: 15 bytes<br>Note: For write operation the valid values are 0001 to 0110; For read<br>operation the valid values are 0001 to 1111.|



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## **20.2 I2CM_COMMAND_1** 

|**20.2**<br>**I2CM_COMMAND_1**|**20.2**<br>**I2CM_COMMAND_1**|**20.2**<br>**I2CM_COMMAND_1**|
|---|---|---|
|Name: I2CM_COMMAND_1 (I2C master command buffer 1)<br>Address: 07 (07h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7|ENDFLAG_1|Indicates if the current entry is the last I2C master communication with the<br>external slave device.|
|6|CH_SEL_1|Specifies the channel number for I2C master transaction.<br>Two external sensors are supported.<br>0: Specify one external sensor with device ID “ID1”<br>1: Specify the other external sensor with device ID “ID2”<br>“ID1” and “ID2” should be replaced by the actual device ID of the chosen<br>external devices.|
|5:4|R_W_1|I2C master read/write command.<br>00: Write operation<br>01: Read operation with register address specified<br>10: Read operation without register address specified<br>11: Reserved|
|3:0|BURSTLEN_1|Specifies the burst length of I2C master communication with the external<br>slave device.<br>0000: Reserved<br>0001: 1 byte<br>0010: 2 bytes<br>0011: 3 bytes<br>0100: 4 bytes<br>0101: 5 bytes<br>0110: 6 bytes<br>0111: 7 bytes<br>1000: 8 bytes<br>1001: 9 bytes<br>1010: 10 bytes<br>1011: 11 bytes<br>1100: 12 bytes<br>1101: 13 bytes<br>1110: 14 bytes<br>1111: 15 bytes<br>Note: For write operation the valid values are 0001 to 0110; For read<br>operation the valid values are 0001 to 1111.|



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## **20.3 I2CM_COMMAND_2** 

|**20.3**<br>**I2CM_COMMAND_2**|**20.3**<br>**I2CM_COMMAND_2**|**20.3**<br>**I2CM_COMMAND_2**|
|---|---|---|
|Name: I2CM_COMMAND_2 (I2C master command buffer 2)<br>Address: 08 (08h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7|ENDFLAG_2|Indicates if the current entry is the last I2C master communication with the<br>external slave device.|
|6|CH_SEL_2|Specifies the channel number for I2C master transaction.<br>Two external sensors are supported.<br>0: Specify one external sensor with device ID “ID1”<br>1: Specify the other external sensor with device ID “ID2”<br>“ID1” and “ID2” should be replaced by the actual device ID of the chosen<br>external devices.|
|5:4|R_W_2|I2C master read/write command.<br>00: Write operation<br>01: Read operation with register address specified<br>10: Read operation without register address specified<br>11: Reserved|
|3:0|BURSTLEN_2|Specifies the burst length of I2C master communication with the external<br>slave device.<br>0000: Reserved<br>0001: 1 byte<br>0010: 2 bytes<br>0011: 3 bytes<br>0100: 4 bytes<br>0101: 5 bytes<br>0110: 6 bytes<br>0111: 7 bytes<br>1000: 8 bytes<br>1001: 9 bytes<br>1010: 10 bytes<br>1011: 11 bytes<br>1100: 12 bytes<br>1101: 13 bytes<br>1110: 14 bytes<br>1111: 15 bytes<br>Note: For write operation the valid values are 0001 to 0110; For read<br>operation the valid values are 0001 to 1111.|



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## **20.4 I2CM_COMMAND_3** 

|**20.4**<br>**I2CM_COMMAND_3**|**20.4**<br>**I2CM_COMMAND_3**|**20.4**<br>**I2CM_COMMAND_3**|
|---|---|---|
|Name: I2CM_COMMAND_3 (I2C master command buffer 3)<br>Address: 09 (09h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7|ENDFLAG_3|Indicates if the current entry is the last I2C master communication with the<br>external slave device.|
|6|CH_SEL_3|Specifies the channel number for I2C master transaction.<br>Two external sensors are supported.<br>0: Specify one external sensor with device ID “ID1”<br>1: Specify the other external sensor with device ID “ID2”<br>“ID1” and “ID2” should be replaced by the actual device ID of the chosen<br>external devices.|
|5:4|R_W_3|I2C master read/write command.<br>00: Write operation<br>01: Read operation with register address specified<br>10: Read operation without register address specified<br>11: Reserved|
|3:0|BURSTLEN_3|Specifies the burst length of I2C master communication with the external<br>slave device.<br>0000: Reserved<br>0001: 1 byte<br>0010: 2 bytes<br>0011: 3 bytes<br>0100: 4 bytes<br>0101: 5 bytes<br>0110: 6 bytes<br>0111: 7 bytes<br>1000: 8 bytes<br>1001: 9 bytes<br>1010: 10 bytes<br>1011: 11 bytes<br>1100: 12 bytes<br>1101: 13 bytes<br>1110: 14 bytes<br>1111: 15 bytes<br>Note: For write operation the valid values are 0001 to 0110; For read<br>operation the valid values are 0001 to 1111.|



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## **20.5 I2CM_DEV_PROFILE0** 

Name: I2CM_DEV_PROFILE0 Address: 14 (0Eh) Serial IF: R/W Reset value: 0x00 Clock Domain: MCLK **BIT NAME FUNCTION** 7:0 RD_ADDRESS_0 Specifies the read address for channel 0 I[2] C master transaction 

## **20.6 I2CM_DEV_PROFILE1** 

Name: I2CM_DEV_PROFILE1 Address: 15 (0Fh) Serial IF: R/W Reset value: 0x00 Clock Domain: MCLK **BIT NAME FUNCTION** 7 - Reserved 6:0 DEV_ID_0 Specifies the slave ID for channel 0 I[2] C master transaction 

## **20.7 I2CM_DEV_PROFILE2** 

Name: I2CM_DEV_PROFILE2 Address: 16 (10h) Serial IF: R/W Reset value: 0x00 Clock Domain: MCLK **BIT NAME FUNCTION** 7:0 RD_ADDRESS_1 Specifies the read address for channel 1 I[2] C master transaction 

## **20.8 I2CM_DEV_PROFILE3** 

Name: I2CM_DEV_PROFILE3 Address: 17 (11h) Serial IF: R/W Reset value: 0x00 Clock Domain: MCLK **BIT NAME FUNCTION** 7 - Reserved 6:0 DEV_ID_1 Specifies the slave ID for channel 1 I[2] C master transaction 

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## **20.9 I2CM_CONTROL** 

|**20.9**<br>**I2CM_CONTROL**|**20.9**<br>**I2CM_CONTROL**|**20.9**<br>**I2CM_CONTROL**|
|---|---|---|
|Name: I2CM_CONTROL<br>Address: 22 (16h)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7|-|Reserved|
|6|I2CM_RESTART_EN|0: No Restart is used<br>1: In an I2C register read transaction, the Restart is used to bridge the<br>register-address write transaction and register-data read transaction. This bit<br>is notprogrammable byMCU when I2CM_BUSY = 1.|
|5:4|-|Reserved|
|3|I2CM_SPEED|0: I2C Fast Mode<br>1: I2C Standard Mode|
|2:1|-|Reserved|
|0|I2CM_GO|1: Kicks off I2C master operation. Clears to 0 after I2C master operation is<br>completed. This bit is notprogrammable when I2CM_BUSY = 1|



## **20.10 I2CM_STATUS** 

Name: I2CM_STATUS Address: 24 (18h) Serial IF: R Reset value: 0x00 Clock Domain: MCLK 

|Name: I2CM_STATUS<br>Address: 24 (18h)<br>Serial IF: R<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: I2CM_STATUS<br>Address: 24 (18h)<br>Serial IF: R<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: I2CM_STATUS<br>Address: 24 (18h)<br>Serial IF: R<br>Reset value: 0x00<br>Clock Domain: MCLK|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:6|-|Reserved|
|5|I2CM_SDA_ERR|I2C master SDA error indication|
|4|I2CM_SCL_ERR|I2C master SCL error indication|
|3|I2CM_SRST_ERR|I2C master SRST error indication|
|2|I2CM_TIMEOUT_ERR|I2C master timeout error indication|
|1|I2CM_DONE|1: Status bit, indicates I2C master operation has completed, with or without<br>errors. This bit is cleared due to (a) MCU read or (b) when I2CM_GO is<br>programmed to 1 or (c) ODR event for fetching sensor data from the<br>external sensor.|
|0|I2CM_BUSY|0: Indicates no I2C master operation is running<br>1: Indicates I2C master operation is running|



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## **20.11 I2CM_EXT_DEV_STATUS** 

|Name: I2CM_EXT_DEV_STATUS<br>Address: 26 (1Ah)<br>Serial IF: R/C<br>Reset value: 0x0F<br>Clock Domain: MCLK|Name: I2CM_EXT_DEV_STATUS<br>Address: 26 (1Ah)<br>Serial IF: R/C<br>Reset value: 0x0F<br>Clock Domain: MCLK|Name: I2CM_EXT_DEV_STATUS<br>Address: 26 (1Ah)<br>Serial IF: R/C<br>Reset value: 0x0F<br>Clock Domain: MCLK|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:4|-|Reserved|
|3:0|I2CM_EXT_DEV_STATUS|Indicates ACK/NACK feedback from the external device per each entry of the<br>command buffer. I2CM_EXT_DEV_STATUS is set to 0xF whenever I2C master<br>operation is kicked off.<br>Bit 0 of I2CM_EXT_DEV_STATUS: ACK/NACK feedback from the external<br>device to I2CM_COMMAND_0.<br>0: ACK<br>1: NACK<br>Bit 1 of I2CM_EXT_DEV_STATUS: ACK/NACK feedback from the external<br>device to I2CM_COMMAND_1.<br>0: ACK<br>1: NACK<br>Bit 2 of I2CM_EXT_DEV_STATUS: ACK/NACK feedback from the external<br>device to I2CM_COMMAND_2.<br>0: ACK<br>1: NACK<br>Bit 3 of I2CM_EXT_DEV_STATUS: ACK/NACK feedback from the external<br>device to I2CM_COMMAND_3.<br>0: ACK<br>1: NACK|



## **20.12 I2CM_RD_DATA0** 

|Name: I2CM_RD_DATA0<br>Address: 27 (1Bh)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: I2CM_RD_DATA0<br>Address: 27 (1Bh)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: I2CM_RD_DATA0<br>Address: 27 (1Bh)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:0|I2CM_RD_DATA0|The 1stbyte received from I2C slave.<br>Content of this register is automatically cleared to 0 when I2CM_GO = 1 or<br>upon ODR event for fetchingsensor data from the external sensor.|



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## **20.13 I2CM_RD_DATA1** 

|Name: I2CM_RD_DATA1<br>Address: 28 (1Ch)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: I2CM_RD_DATA1<br>Address: 28 (1Ch)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: I2CM_RD_DATA1<br>Address: 28 (1Ch)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:0|I2CM_RD_DATA1|The 2ndbyte received from I2C slave.<br>Content of this register is automatically cleared to 0 when I2CM_GO = 1 or<br>upon ODR event for fetchingsensor data from the external sensor.|



## **20.14 I2CM_RD_DATA2** 

|Name: I2CM_RD_DATA2<br>Address: 29 (1Dh)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: I2CM_RD_DATA2<br>Address: 29 (1Dh)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: I2CM_RD_DATA2<br>Address: 29 (1Dh)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:0|I2CM_RD_DATA2|The 3rdbyte received from I2C slave.<br>Content of this register is automatically cleared to 0 when I2CM_GO = 1 or<br>upon ODR event for fetchingsensor data from the external sensor.|



## **20.15 I2CM_RD_DATA3** 

|Name: I2CM_RD_DATA3<br>Address: 30 (1Eh)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: I2CM_RD_DATA3<br>Address: 30 (1Eh)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: I2CM_RD_DATA3<br>Address: 30 (1Eh)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:0|I2CM_RD_DATA3|The 4thbyte received from I2C slave.<br>Content of this register is automatically cleared to 0 when I2CM_GO = 1 or<br>upon ODR event for fetchingsensor data from the external sensor.|



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## **20.16 I2CM_RD_DATA4** 

|Name: I2CM_RD_DATA4<br>Address: 31 (1Fh)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: I2CM_RD_DATA4<br>Address: 31 (1Fh)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: I2CM_RD_DATA4<br>Address: 31 (1Fh)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:0|I2CM_RD_DATA4|The 5thbyte received from I2C slave.<br>Content of this register is automatically cleared to 0 when I2CM_GO = 1 or<br>upon ODR event for fetchingsensor data from the external sensor.|



## **20.17 I2CM_RD_DATA5** 

|Name: I2CM_RD_DATA5<br>Address: 32 (20h)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: I2CM_RD_DATA5<br>Address: 32 (20h)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: I2CM_RD_DATA5<br>Address: 32 (20h)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:0|I2CM_RD_DATA5|The 6thbyte received from I2C slave.<br>Content of this register is automatically cleared to 0 when I2CM_GO = 1 or<br>upon ODR event for fetchingsensor data from the external sensor.|



## **20.18 I2CM_RD_DATA6** 

|Name: I2CM_RD_DATA6<br>Address: 33 (21h)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: I2CM_RD_DATA6<br>Address: 33 (21h)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: I2CM_RD_DATA6<br>Address: 33 (21h)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:0|I2CM_RD_DATA6|The 7thbyte received from I2C slave.<br>Content of this register is automatically cleared to 0 when I2CM_GO = 1 or<br>upon ODR event for fetchingsensor data from the external sensor.|



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## **20.19 I2CM_RD_DATA7** 

|Name: I2CM_RD_DATA7<br>Address: 34 (22h)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: I2CM_RD_DATA7<br>Address: 34 (22h)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: I2CM_RD_DATA7<br>Address: 34 (22h)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:0|I2CM_RD_DATA7|The 8thbyte received from I2C slave.<br>Content of this register is automatically cleared to 0 when I2CM_GO = 1 or<br>upon ODR event for fetchingsensor data from the external sensor.|



## **20.20 I2CM_RD_DATA8** 

|Name: I2CM_RD_DATA8<br>Address: 35 (23h)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: I2CM_RD_DATA8<br>Address: 35 (23h)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: I2CM_RD_DATA8<br>Address: 35 (23h)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:0|I2CM_RD_DATA8|The 9thbyte received from I2C slave.<br>Content of this register is automatically cleared to 0 when I2CM_GO = 1 or<br>upon ODR event for fetchingsensor data from the external sensor.|



## **20.21 I2CM_RD_DATA9** 

|Name: I2CM_RD_DATA9<br>Address: 36 (24h)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: I2CM_RD_DATA9<br>Address: 36 (24h)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: I2CM_RD_DATA9<br>Address: 36 (24h)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:0|I2CM_RD_DATA9|The 10thbyte received from I2C slave.<br>Content of this register is automatically cleared to 0 when I2CM_GO = 1 or<br>upon ODR event for fetchingsensor data from the external sensor.|



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## **20.22 I2CM_RD_DATA10** 

|Name: I2CM_RD_DATA10<br>Address: 37 (25h)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: I2CM_RD_DATA10<br>Address: 37 (25h)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: I2CM_RD_DATA10<br>Address: 37 (25h)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:0|I2CM_RD_DATA10|The 11thbyte received from I2C slave.<br>Content of this register is automatically cleared to 0 when I2CM_GO = 1 or<br>upon ODR event for fetchingsensor data from the external sensor.|



## **20.23 I2CM_RD_DATA11** 

|Name: I2CM_RD_DATA11<br>Address: 38 (26h)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: I2CM_RD_DATA11<br>Address: 38 (26h)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: I2CM_RD_DATA11<br>Address: 38 (26h)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:0|I2CM_RD_DATA11|The 12thbyte received from I2C slave.<br>Content of this register is automatically cleared to 0 when I2CM_GO = 1 or<br>upon ODR event for fetchingsensor data from the external sensor.|



## **20.24 I2CM_RD_DATA12** 

|Name: I2CM_RD_DATA12<br>Address: 39 (27h)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: I2CM_RD_DATA12<br>Address: 39 (27h)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: I2CM_RD_DATA12<br>Address: 39 (27h)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:0|I2CM_RD_DATA12|The 13thbyte received from I2C slave.<br>Content of this register is automatically cleared to 0 when I2CM_GO = 1 or<br>upon ODR event for fetchingsensor data from the external sensor.|



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## **20.25 I2CM_RD_DATA13** 

|Name: I2CM_RD_DATA13<br>Address: 40 (28h)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: I2CM_RD_DATA13<br>Address: 40 (28h)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: I2CM_RD_DATA13<br>Address: 40 (28h)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:0|I2CM_RD_DATA13|The 14thbyte received from I2C slave.<br>Content of this register is automatically cleared to 0 when I2CM_GO = 1 or<br>upon ODR event for fetchingsensor data from the external sensor.|



## **20.26 I2CM_RD_DATA14** 

|Name: I2CM_RD_DATA14<br>Address: 41 (29h)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: I2CM_RD_DATA14<br>Address: 41 (29h)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: I2CM_RD_DATA14<br>Address: 41 (29h)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:0|I2CM_RD_DATA14|The 15thbyte received from I2C slave.<br>Content of this register is automatically cleared to 0 when I2CM_GO = 1 or<br>upon ODR event for fetchingsensor data from the external sensor.|



## **20.27 I2CM_RD_DATA15** 

|Name: I2CM_RD_DATA15<br>Address: 42 (2Ah)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: I2CM_RD_DATA15<br>Address: 42 (2Ah)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: I2CM_RD_DATA15<br>Address: 42 (2Ah)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:0|I2CM_RD_DATA15|The 16thbyte received from I2C slave.<br>Content of this register is automatically cleared to 0 when I2CM_GO = 1 or<br>upon ODR event for fetchingsensor data from the external sensor.|



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## **20.28 I2CM_RD_DATA16** 

|Name: I2CM_RD_DATA16<br>Address: 43 (2Bh)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: I2CM_RD_DATA16<br>Address: 43 (2Bh)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: I2CM_RD_DATA16<br>Address: 43 (2Bh)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:0|I2CM_RD_DATA16|The 17thbyte received from I2C slave.<br>Content of this register is automatically cleared to 0 when I2CM_GO = 1 or<br>upon ODR event for fetchingsensor data from the external sensor.|



## **20.29 I2CM_RD_DATA17** 

|Name: I2CM_RD_DATA17<br>Address: 44 (2Ch)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: I2CM_RD_DATA17<br>Address: 44 (2Ch)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: I2CM_RD_DATA17<br>Address: 44 (2Ch)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:0|I2CM_RD_DATA17|The 18thbyte received from I2C slave.<br>Content of this register is automatically cleared to 0 when I2CM_GO = 1 or<br>upon ODR event for fetchingsensor data from the external sensor.|



## **20.30 I2CM_RD_DATA18** 

|Name: I2CM_RD_DATA18<br>Address: 45 (2Dh)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: I2CM_RD_DATA18<br>Address: 45 (2Dh)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: I2CM_RD_DATA18<br>Address: 45 (2Dh)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:0|I2CM_RD_DATA18|The 19thbyte received from I2C slave.<br>Content of this register is automatically cleared to 0 when I2CM_GO = 1 or<br>upon ODR event for fetchingsensor data from the external sensor.|



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## **20.31 I2CM_RD_DATA19** 

|Name: I2CM_RD_DATA19<br>Address: 46 (2Eh)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: I2CM_RD_DATA19<br>Address: 46 (2Eh)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: I2CM_RD_DATA19<br>Address: 46 (2Eh)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:0|I2CM_RD_DATA19|The 20thbyte received from I2C slave.<br>Content of this register is automatically cleared to 0 when I2CM_GO = 1 or<br>upon ODR event for fetchingsensor data from the external sensor.|



## **20.32 I2CM_RD_STATUS20** 

|Name: I2CM_RD_DATA20<br>Address: 47 (2Fh)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: I2CM_RD_DATA20<br>Address: 47 (2Fh)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: I2CM_RD_DATA20<br>Address: 47 (2Fh)<br>Serial IF: RWS<br>Reset value: 0x00<br>Clock Domain: MCLK|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:0|I2CM_RD_DATA20|The 21stbyte received from I2C slave.<br>Content of this register is automatically cleared to 0 when I2CM_GO = 1 or<br>upon ODR event for fetchingsensor data from the external sensor.|



## **20.33 I2CM_WR_DATA0** 

|Name: I2CM_WR_DATA0<br>Address: 51 (33h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: I2CM_WR_DATA0<br>Address: 51 (33h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: I2CM_WR_DATA0<br>Address: 51 (33h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: MCLK|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:0|I2CM_WR_DATA0|The data/address byte for a Write transaction.|



## **20.34 I2CM_WR_DATA1** 

Name: I2CM_WR_DATA1 Address: 52 (34h) Serial IF: R/W Reset value: 0x00 Clock Domain: MCLK **BIT NAME FUNCTION** 7:0 I2CM_WR_DATA1 The data/address byte for a Write transaction. 

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## **20.35 I2CM_WR_DATA2** 

Name: I2CM_WR_DATA2 Address: 53 (35h) Serial IF: R/W Reset value: 0x00 Clock Domain: MCLK **BIT NAME FUNCTION** 7:0 I2CM_WR_DATA2 The data/address byte for a Write transaction. 

## **20.36 I2CM_WR_DATA3** 

Name: I2CM_WR_DATA3 Address: 54 (36h) Serial IF: R/W Reset value: 0x00 Clock Domain: MCLK **BIT NAME FUNCTION** 7:0 I2CM_WR_DATA3 The data/address byte for a Write transaction. 

## **20.37 I2CM_WR_DATA4** 

Name: I2CM_WR_DATA4 Address: 55 (37h) Serial IF: R/W Reset value: 0x00 Clock Domain: MCLK **BIT NAME FUNCTION** 7:0 I2CM_WR_DATA4 The data/address byte for a Write transaction. 

## **20.38 I2CM_WR_DATA5** 

Name: I2CM_WR_DATA5 Address: 56 (38h) Serial IF: R/W Reset value: 0x00 Clock Domain: MCLK **BIT NAME FUNCTION** 7:0 I2CM_WR_DATA5 The data/address byte for a Write transaction. 

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## **20.39 SIFS_IXC_ERROR_STATUS** 

|**20.39 SIFS_IXC_ERROR_STATUS**|**20.39 SIFS_IXC_ERROR_STATUS**|**20.39 SIFS_IXC_ERROR_STATUS**|
|---|---|---|
|Name: SIFS_IXC_ERROR_STATUS<br>Address: 75 (4Bh)<br>Serial IF: R/C<br>Reset value: 0x00<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7:2|-|Reserved|
|1|AUX1_SIFS_IXC_TIMEOUT_<br>ERR|0: No timeout error.<br>1: Indicates than an IxC timeout error occurred in AUX1 SIFS. No clock toggle<br>condition from host for 32ms while an IxC transaction was ongoing (after<br>START and before STOP).|
|0|SIFS_IXC_TIMEOUT_ERR|0: No timeout error or when SPI slave is selected for serial transfers.<br>1: Indicates than an IxC timeout error occurred in SIFS. No clock toggle<br>condition from host for 32ms while an IxC transaction was ongoing (after<br>START and before STOP).|



## **20.40 EDMP_PRGRM_IRQ0_0** 

|Name: EDMP_PRGRM_IRQ0_0||
|---|---|
|Address: 79 (4Fh)||
|Serial IF: R/W||
|Reset value: 0x00||
|Clock Domain: MCLK||
|**BIT**<br>**NAME**|**FUNCTION**|
|7:0<br>PRGRM_STRT_ADDR_IRQ_<br>0[7:0]|Start address of IRQ_0 vector.<br>Can be changed on-the-fly.|



## **20.41 EDMP_PRGRM_IRQ0_1** 

|Name: EDMP_PRGRM_IRQ0_1||
|---|---|
|Address: 80 (50h)||
|Serial IF: R/W||
|Reset value: 0x00||
|Clock Domain: MCLK||
|**BIT**<br>**NAME**|**FUNCTION**|
|7:0<br>PRGRM_STRT_ADDR_IRQ_<br>0[15:8]|Start address of IRQ_0 vector.<br>Can be changed on-the-fly.|



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## **20.42 EDMP_PRGRM_IRQ1_0** 

Name: EDMP_PRGRM_IRQ1_0 Address: 81 (51h) Serial IF: R/W Reset value: 0x00 Clock Domain: MCLK **BIT NAME FUNCTION** Start address of IRQ_1 vector. PRGRM_STRT_ADDR_IRQ_ 7:0 1[7:0] Can be changed on-the-fly. 

## **20.43 EDMP_PRGRM_IRQ1_1** 

Name: EDMP_PRGRM_IRQ1_1 Address: 82 (52h) Serial IF: R/W Reset value: 0x00 Clock Domain: MCLK **BIT NAME FUNCTION** Start address of IRQ_1 vector. PRGRM_STRT_ADDR_IRQ_ 7:0 1[15:8] Can be changed on-the-fly. 

## **20.44 EDMP_PRGRM_IRQ2_0** 

Name: EDMP_PRGRM_IRQ2_0 Address: 83 (53h) Serial IF: R/W Reset value: 0x00 Clock Domain: MCLK **BIT NAME FUNCTION** Start address of IRQ_2 vector. PRGRM_STRT_ADDR_IRQ_ 7:0 2[7:0] Can be changed on-the-fly. 

## **20.45 EDMP_PRGRM_IRQ2_1** 

Name: EDMP_PRGRM_IRQ2_1 Address: 84 (54h) Serial IF: R/W Reset value: 0x00 Clock Domain: MCLK **BIT NAME FUNCTION** Start address of IRQ_2 vector. PRGRM_STRT_ADDR_IRQ_ 7:0 2[15:8] Can be changed on-the-fly. 

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## **20.46 EDMP_SP_START_ADDR** 

|Name: EDMP_SP_START_ADDR||
|---|---|
|Address: 85 (55h)||
|Serial IF: R/W||
|Reset value: 0x00||
|Clock Domain: MCLK||
|**BIT**<br>**NAME**|**FUNCTION**|
||Sets eDMP stack address.|
|7:0<br>EDMP_SP_START_ADDR||
||Can be changed on-the-fly.|



## **20.47 SMC_CONTROL_0** 

Name: SMC_CONTROL_0 Address: 88 (58h) Serial IF: R/W Reset value: 0x60 Clock Domain: MCLK 

|Name: SMC_CONTROL_0<br>Address: 88 (58h)<br>Serial IF: R/W<br>Reset value: 0x60<br>Clock Domain: MCLK|Name: SMC_CONTROL_0<br>Address: 88 (58h)<br>Serial IF: R/W<br>Reset value: 0x60<br>Clock Domain: MCLK|Name: SMC_CONTROL_0<br>Address: 88 (58h)<br>Serial IF: R/W<br>Reset value: 0x60<br>Clock Domain: MCLK|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:5|-|Reserved|
|4|ACCEL_LP_CLK_SEL|This bit is applicable to host interface operation.<br>A. When RTC mode is not enabled (or RTC_MODE = 0 ):<br>This bit is effective when the host interface is in accel only operation with<br>ACCEL_MODE set to LP mode.<br>0: Host interface is in AULP mode.<br>1: Host interface is in ALP mode.<br>When I3CSMSynchronous Timing Control function is enabled on host<br>interface, if the host interface is in accel only operation with ACCEL_MODE<br>set to LP mode, ACCEL_LP_CLK_SEL must be set to 1. I3CSMSynchronous<br>Timing Control may not generate correct timing if ACCEL_LP_CLK_SEL is set<br>to 0.<br>B. When RTC mode is enabled (or RTC_MODE = 1):<br>Independent of enabling/disabling of I3CSMSynchronous timing control<br>function, ACCEL_LP_CLK_SEL must be set to 1.<br>Dynamic Change Supported.|
|3|TEMP_DIS|0: Temperature Sensor not disabled.<br>1: Temperature Sensor disabled.|
|2|TMST_FORCE_AUX_FINE_E<br>N|0: Time Stamp fine counting enabled only on UI interface.<br>1: Time Stamp fine counting enabled on AUX interfaces in addition to UI<br>interface.|
|1|TMST_FSYNC_EN|Time Stamp register FSYNC Enable.<br>0: Timestampfeature of FSYNC not enabled.|



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1: Timestamp feature of FSYNC enabled. 0: Timestamp not enabled. 0 TMST_EN 1: Timestamp enabled. 

## **20.48 SMC_CONTROL_1** 

Name: SMC_CONTROL_1 Address: 89 (59h) Serial IF: R/W Reset value: 0x04 Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|7:4|-|Reserved|
|||0: Sensor data register read from AUX1 interface is supported only if gyro|
|3|SREG_AUX_ACCEL_ONLY_E<br>N|sensor is enabled.<br>1: Sensor data register read from AUX1 interface is supported even if gyro|
|||sensor is not enabled.|
|2:0|-|Reserved|



## **20.49 STC_CONFIG** 

Name: STC_CONFIG Address: 99 (63h) Serial IF: R/W Reset value: 0x00 Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|7:4|-|Reserved|
|||Sensor that controls STC:|
|3:2|STC_SENSOR_SEL|0 or 1: Slowest ODR sensor<br>2: Accel|
|||3: Gyro|
|1:0|-|Reserved|



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## **20.50 SREG_CTRL** 

|**20.50 SREG_CTRL**|**20.50 SREG_CTRL**|**20.50 SREG_CTRL**|
|---|---|---|
|Name: SREG_CTRL<br>Address: 103 (67h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7:2|-|Reserved|
|1|SREG_DATA_ENDIAN_SEL|Selects Endianness of Sensor Data Registers and FIFO data<br>0: Sensor data, FIFO data, and FIFO count is in Little Endian format<br>1: Sensor data, FIFO data, and FIFO count is in Big Endian format<br>Note: User must set register field SREG_DATA_ENDIAN_SEL to 1, to enable<br>Big Endian data format for data in Sensor Data Registers and FIFO, and for<br>FIFO Count.|
|0|-|Reserved|



## **20.51 SIFS_I3C_STC_CFG** 

|Name: SIFS_I3C_STC_CFG<br>Address: 104 (68h)<br>Serial IF: R/W<br>Reset value: 0x23<br>Clock Domain: MCLK|Name: SIFS_I3C_STC_CFG<br>Address: 104 (68h)<br>Serial IF: R/W<br>Reset value: 0x23<br>Clock Domain: MCLK|Name: SIFS_I3C_STC_CFG<br>Address: 104 (68h)<br>Serial IF: R/W<br>Reset value: 0x23<br>Clock Domain: MCLK|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:3|-|Reserved|
|2|I3C_STC_MODE|Enable the STC controller<br>0: Disable I3C STC.<br>1: Enable I3C STC.<br>Toggling this bit restarts the ODR frequency and phase correction operation<br>as if the chip is out of reset.<br>The STC functionality can be enabled only if ACCEL_LP_CLK_SEL is set to 1;<br>otherwise device maynot behave as expected.|
|1:0|-|Reserved|



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## **20.52 INT_PULSE_MIN_ON_INTF0** 

|**20.52 INT_PULSE_MIN_ON_INTF0**|**20.52 INT_PULSE_MIN_ON_INTF0**|**20.52 INT_PULSE_MIN_ON_INTF0**|
|---|---|---|
|Name: INT_PULSE_MIN_ON_INTF0<br>Address: 105 (69h)<br>Serial IF: R/W<br>Reset value: 0x01<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7:3|-|Reserved|
|2:0|INT0_TPULSE_DURATION|INT0 interrupt pulse minimum “on” duration for host interface, when in<br>pulse mode.<br>0: 100µs (use only if ODR < 4kHz)<br>1: 8µs (required if ODR ≥ 4kHz, optional for ODR < 4kHz)<br>Other Settings: Reserved|



## **20.53 INT_PULSE_MIN_ON_INTF1** 

|Name: INT_PULSE_MIN_ON_INTF1<br>Address: 106 (6Ah)<br>Serial IF: R/W<br>Reset value: 0x01<br>Clock Domain: MCLK|Name: INT_PULSE_MIN_ON_INTF1<br>Address: 106 (6Ah)<br>Serial IF: R/W<br>Reset value: 0x01<br>Clock Domain: MCLK|Name: INT_PULSE_MIN_ON_INTF1<br>Address: 106 (6Ah)<br>Serial IF: R/W<br>Reset value: 0x01<br>Clock Domain: MCLK|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:3|-|Reserved|
|2:0|INT1_TPULSE_DURATION|INT1 interrupt pulse minimum “on” duration for host interface, when in<br>pulse mode.<br>0: 100µs (use only if ODR < 4kHz)<br>1: 8µs (required if ODR ≥ 4kHz, optional for ODR < 4kHz)<br>Other Settings: Reserved|



## **20.54 INT_PULSE_MIN_OFF_INTF0** 

|Name: INT_PULSE_MIN_OFF_INTF0<br>Address: 107 (6Bh)<br>Serial IF: R/W<br>Reset value: 0x01<br>Clock Domain: MCLK|Name: INT_PULSE_MIN_OFF_INTF0<br>Address: 107 (6Bh)<br>Serial IF: R/W<br>Reset value: 0x01<br>Clock Domain: MCLK|Name: INT_PULSE_MIN_OFF_INTF0<br>Address: 107 (6Bh)<br>Serial IF: R/W<br>Reset value: 0x01<br>Clock Domain: MCLK|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:3|-|Reserved|
|2:0|INT0_TDEASSERT_DISABLE|INT0 interrupt pulse minimum “off” duration for host interface, indicates<br>minimum interrupt de-assertion duration.<br>0: 100µs<br>1: 8µs<br>Other Settings: Reserved|



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## **20.55 INT_PULSE_MIN_OFF_INTF1** 

Name: INT_PULSE_MIN_OFF_INTF1 Address: 108 (6Ch) Serial IF: R/W Reset value: 0x01 Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|7:3|-|Reserved|
|||INT1 interrupt pulse minimum “off” duration for host interface, indicates|
|||minimum interrupt de-assertion duration.|
|2:0|INT1_TDEASSERT_DISABLE|0: 100µs|
|||1: 8µs|
|||Other Settings: Reserved|



## **20.56 ISR_0_7** 

Name: ISR_0_7 Address: 110 (6Eh) Serial IF: R/C Reset value: 0x00 Clock Domain: MCLK 

|**20.56 ISR_0_7**|**20.56 ISR_0_7**|**20.56 ISR_0_7**|
|---|---|---|
|Name: ISR_0_7<br>Address: 110 (6Eh)<br>Serial IF: R/C<br>Reset value: 0x00<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7:6|-|Reserved|
|5|INT_STATUS_ON_DEMAND<br>_PIN_0|For IRQ0 interface, if this interrupt status bit is enabled, this bit is to flag the<br>occurrence of on demand event.<br>0: Interrupt did not occur.<br>1: Interrupt occurred.|
|4|-|Reserved|
|3|INT_STATUS_EXT_ODR_DR<br>DY_PIN_0|For IRQ0 interface, if this interrupt status bit is enabled, this bit is to flag the<br>occurrence of EXT ODR DRDY event.<br>0: Interrupt did not occur.<br>1: Interrupt occurred.|
|2:1|-|Reserved|
|0|INT_STATUS_ACCEL_DRDY<br>_PIN_0|For IRQ0 interface, if this interrupt status bit is enabled, this bit is to flag the<br>occurrence of Accel DRDY event.<br>0: Interrupt did not occur.<br>1: Interrupt occurred.|



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## **20.57 ISR_8_15** 

|**20.57 ISR_8_15**|**20.57 ISR_8_15**|**20.57 ISR_8_15**|
|---|---|---|
|Name: ISR_8_15<br>Address: 111 (6Fh)<br>Serial IF: R/C<br>Reset value: 0x00<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7:6|-|Reserved|
|5|INT_STATUS_ON_DEMAND<br>_PIN_1|For IRQ1 interface, if this interrupt status bit is enabled, this bit is to flag the<br>occurrence of on demand event.<br>0: Interrupt did not occur.<br>1: Interrupt occurred.|
|4|-|Reserved|
|3|INT_STATUS_EXT_ODR_DR<br>DY_PIN_1|For IRQ1 interface, if this interrupt status bit is enabled, this bit is to flag the<br>occurrence of EXT ODR DRDY event.<br>0: Interrupt did not occur.<br>1: Interrupt occurred.|
|2:1|-|Reserved|
|0|INT_STATUS_ACCEL_DRDY<br>_PIN_1|For IRQ1 interface, if this interrupt status bit is enabled, this bit is to flag the<br>occurrence of Accel DRDY event.<br>0: Interrupt did not occur.<br>1: Interrupt occurred.|



## **20.58 ISR_16_23** 

|**20.58 ISR_16_23**|**20.58 ISR_16_23**|**20.58 ISR_16_23**|
|---|---|---|
|Name: ISR_16_23<br>Address: 112 (70h)<br>Serial IF: R/C<br>Reset value: 0x00<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7:6|-|Reserved|
|5|INT_STATUS_ON_DEMAND<br>_PIN_2|For IRQ2 interface, if this interrupt status bit is enabled, this bit is to flag the<br>occurrence of on demand event.<br>0: Interrupt did not occur.<br>1: Interrupt occurred.|
|4|-|Reserved|
|3|INT_STATUS_EXT_ODR_DR<br>DY_PIN_2|For IRQ2 interface, if this interrupt status bit is enabled, this bit is to flag the<br>occurrence of EXT ODR DRDY event.<br>0: Interrupt did not occur.<br>1: Interrupt occurred.|
|2:1|-|Reserved|
|0|INT_STATUS_ACCEL_DRDY<br>_PIN_2|For IRQ2 interface, if this interrupt status bit is enabled, this bit is to flag the<br>occurrence of Accel DRDY event.<br>0: Interrupt did not occur.|



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1: Interrupt occurred. 

## **20.59 STATUS_MASK_PIN_0_7** 

|**20.59 STATUS_MASK_PIN_0_7**|**20.59 STATUS_MASK_PIN_0_7**|**20.59 STATUS_MASK_PIN_0_7**|
|---|---|---|
|Name: STATUS_MASK_PIN_0_7<br>Address: 113 (71h)<br>Serial IF: R/W<br>Reset value: 0x3F<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7:6|-|Reserved|
|5|INT_ON_DEMAND_PIN_0_<br>DIS|For IRQ0, on-demand DRDY event, this is to enable the interrupt pin<br>assertion when the INT_STATUS_ON_DEMAND_PIN_0 status bit is 1.<br>0: Enable the Interrupt pin assertion.<br>1: No Interruptpin assertion.|
|4|-|Reserved|
|3|INT_EXT_ODR_DRDY_PIN_<br>0_DIS|For IRQ0, ODR DRDY event, this is to enable the interrupt pin assertion when<br>the INT_STATUS_EXT_ODR_DRDY_PIN_0 status bit is 1.<br>0: Enable the Interrupt pin assertion.<br>1: No Interruptpin assertion.|
|2:1|-|Reserved|
|0|INT_ACCEL_DRDY_PIN_0_<br>DIS|For IRQ0, accel DRDY event, this is to enable the interrupt pin assertion<br>when the INT_STATUS_ACCEL_DRDY_PIN_0 status bit is 1.<br>0: Enable the Interrupt pin assertion.<br>1: No Interruptpin assertion.|



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## **20.60 STATUS_MASK_PIN_8_15** 

Name: STATUS_MASK_PIN_8_15 Address: 114 (72h) Serial IF: R/W Reset value: 0x3F Clock Domain: MCLK 

|**20.60 STATUS_MASK_PIN_8_15**|**20.60 STATUS_MASK_PIN_8_15**|**20.60 STATUS_MASK_PIN_8_15**|
|---|---|---|
|Name: STATUS_MASK_PIN_8_15<br>Address: 114 (72h)<br>Serial IF: R/W<br>Reset value: 0x3F<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7:6|-|Reserved|
|5|INT_ON_DEMAND_PIN_1_<br>DIS|For IRQ1, on-demand DRDY event, this is to enable the interrupt pin<br>assertion when the INT_STATUS_ON_DEMAND_PIN_1 status bit is 1.<br>0: Enable the Interrupt pin assertion.<br>1: No Interruptpin assertion.|
|4|-|Reserved|
|3|INT_EXT_ODR_DRDY_PIN_<br>1_DIS|For IRQ1, ODR DRDY event, this is to enable the interrupt pin assertion when<br>the INT_STATUS_EXT_ODR_DRDY_PIN_1 status bit is 1.<br>0: Enable the Interrupt pin assertion.<br>1: No Interruptpin assertion.|
|2:1|-|Reserved|
|0|INT_ACCEL_DRDY_PIN_1_<br>DIS|For IRQ1, accel DRDY event, this is to enable the interrupt pin assertion<br>when the INT_STATUS_ACCEL_DRDY_PIN_1 status bit is 1.<br>0: Enable the Interrupt pin assertion.<br>1: No Interruptpin assertion.|



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## **20.61 STATUS_MASK_PIN_16_23** 

Name: STATUS_MASK_PIN_16_23 Address: 115 (73h) Serial IF: R/W Reset value: 0x3F Clock Domain: MCLK 

|**20.61 STATUS_MASK_PIN_16_23**|**20.61 STATUS_MASK_PIN_16_23**|**20.61 STATUS_MASK_PIN_16_23**|
|---|---|---|
|Name: STATUS_MASK_PIN_16_23<br>Address: 115 (73h)<br>Serial IF: R/W<br>Reset value: 0x3F<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7:6|-|Reserved|
|5|INT_ON_DEMAND_PIN_2_<br>DIS|Enables the eDMP to be run once when IRQ2 is triggered by setting the<br>EDMP_ON_DEMAND_EN bit.|
|4|-|Reserved|
|3|INT_EXT_ODR_DRDY_PIN_<br>2_DIS|For IRQ2, ODR DRDY event, this is to enable the interrupt pin assertion when<br>the INT_STATUS_EXT_ODR_DRDY_PIN_2 status bit is 1.<br>0: Enable the Interrupt pin assertion.<br>1: No Interruptpin assertion.|
|2:1|-|Reserved|
|0|INT_ACCEL_DRDY_PIN_2_<br>DIS|For IRQ2, accel DRDY event, this is to enable the interrupt pin assertion<br>when the INT_STATUS_ACCEL_DRDY_PIN_2 status bit is 1.<br>0: Enable the Interrupt pin assertion.<br>1: No Interruptpin assertion.|



## **20.62 INT_I2CM_SOURCE** 

Name: INT_I2CM_SOURCE Address: 116 (74h) Serial IF: R/W Reset value: 0x00 Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|7:2|-|Reserved|
|1|INT_STATUS_I2CM_SMC_E<br>XT_ODR_EN|0: Does not automatically trigger eDMP operation on target ODR<br>1: Automaticallytriggers eDMP operation on target ODR|
|0|-|Reserved|



## **20.63 ACCEL_WOM_X_THR** 

Name: ACCEL_WOM_X_THR Address: 126 (7Eh) Serial IF: R/W Reset value: 0x00 Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|||Set X-axis Wake on Motion threshold|
|7:0|WOM_X_TH|Wake on Motion thresholds are expressed in fixed “mg” independently of|
|||the selected full-scale (format <U,8,0>, range [0g : 1g], resolution|
|||1g/256=~4mg)|



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## **20.64 ACCEL_WOM_Y_THR** 

|**20.64 ACCEL_WOM_Y_THR**|**20.64 ACCEL_WOM_Y_THR**|**20.64 ACCEL_WOM_Y_THR**|
|---|---|---|
|Name: ACCEL_WOM_Y_THR<br>Address: 127 (7Fh)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7:0|WOM_Y_TH|Set Y-axis Wake on Motion threshold<br>Wake on Motion thresholds are expressed in fixed “mg” independently of<br>the selected full-scale (format <U,8,0>, range [0g : 1g], resolution<br>1g/256=~4mg)|



## **20.65 ACCEL_WOM_Z_THR** 

|**20.65 ACCEL_WOM_Z_THR**|**20.65 ACCEL_WOM_Z_THR**|**20.65 ACCEL_WOM_Z_THR**|
|---|---|---|
|Name: ACCEL_WOM_Z_THR<br>Address: 128 (80h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7:0|WOM_Z_TH|Set Z-axis Wake on Motion threshold<br>Wake on Motion thresholds are expressed in fixed “mg” independently of<br>the selected full-scale (format <U,8,0>, range [0g : 1g], resolution<br>1g/256=~4mg)|



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## **20.66 SELFTEST** 

|**20.66 SELFTEST**|**20.66 SELFTEST**|**20.66 SELFTEST**|
|---|---|---|
|Name: SELFTEST<br>Address: 144 (90h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7:6|-|Reserved|
|5|EN_GZ_ST|0: Z-axis gyroscope self-test is not enabled<br>1: Z-axis gyroscope self-test is enabled<br>Can be changed on-the-fly.|
|4|EN_GY_ST|0: Y-axis gyroscope self-test is not enabled<br>1: Y-axis gyroscope self-test is enabled<br>Can be changed on-the-fly.|
|3|EN_GX_ST|0: X-axis gyroscope self-test is not enabled<br>1: X-axis gyroscope self-test is enabled<br>Can be changed on-the-fly.|
|2|EN_AZ_ST|0: Z-axis accelerometer self-test is not enabled<br>1: Z-axis accelerometer self-test is enabled<br>Can be changed on-the-fly.|
|1|EN_AY_ST|0: Y-axis accelerometer self-test is not enabled<br>1: Y-axis accelerometer self-test is enabled<br>Can be changed on-the-fly.|
|0|EN_AX_ST|0: X-axis accelerometer self-test is not enabled<br>1: X-axis accelerometer self-test is enabled<br>Can be changed on-the-fly.|



## **20.67 IPREG_MISC** 

Name: IPREG_MISC Address: 151 (97h) Serial IF: R Reset value: 0x02 Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|7:2|-|Reserved|
|1|EDMP_IDLE|0: Indicates eDMP is busy.<br>1: Indicates eDMP is idle.|
|0|-|Reserved|



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## **20.68 SW_PLL1_TRIM** 

|**20.68 SW_PLL1_TRIM**|**20.68 SW_PLL1_TRIM**|**20.68 SW_PLL1_TRIM**|
|---|---|---|
|Name: SW_PLL1_TRIM<br>Address: 162 (A2h)<br>Serial IF: R<br>Reset value: 0x00<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7:0|SW_PLL1_TRIM|Stores variation of PLL frequency test measurement vs. target value, used for<br>SW applications. Value to trim =(PLL_measurement – 6144000Hz) /<br>6144000Hz * 2540. 6144000Hz is the target PLL freq. 2540 is the resolution<br>coefficient: max register range / max oscillator frequency error = (2^7 - 1) /<br>5%,with a sign bit.|



## **20.69 FIFO_SRAM_SLEEP** 

Name: FIFO_SRAM_SLEEP Address: 167 (A7h) Serial IF: R/W Reset value: 0x00 Clock Domain: MCLK 

|Name: FIFO_SRAM_SLEEP<br>Address: 167 (A7h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: FIFO_SRAM_SLEEP<br>Address: 167 (A7h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: FIFO_SRAM_SLEEP<br>Address: 167 (A7h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: MCLK|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:2|-|Reserved|
|1:0|FIFO_GSLEEP_SHARED_SR<br>AM|Set selected SRAM bank global sleep mode<br>**Bit 0:**<br>1. When set to 1:  SRAM bank-0  will remain enabled<br>2. When 0:  permits SRAM bank-0 to go to sleep mode<br>a. SRAM bank goes to sleep, if not allocated as FIFO memory<br>space<br>b. If allocated as FIFO memory space, remains active unless<br>FIFO is empty and sensors are off<br>**Bit 1:**<br>1. When set to 1:  SRAM bank-1  will remain enabled<br>2. When 0:  Permits SRAM bank-1 to go to sleep mode<br>a. SRAM bank goes to sleep, if not allocated as FIFO memory<br>space<br>b. If allocated as FIFO memory space, remains active unless<br>FIFO is emptyand sensors are off|



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## _**21 USER BANK IPREG_SYS1 REGISTER MAP – DESCRIPTIONS**_ 

This section describes the function and contents of each register within user bank IPREG_SYS1. The registers described in this section are indirect access registers. Section 13 describes the procedure for accessing indirect access registers. 

## **21.1 IPREG_SYS1_REG_42** 

Name: IPREG_SYS1_REG_42 Address: 42 (2Ah) Serial IF: R/W Reset value: 0x00 Clock Domain: MCLK **BIT NAME FUNCTION** Low bits for X-gyro offset programmed by user. Range is ±62.5dps, 7:0 GYRO_X_OFFUSER[7:0] resolution is 7.5mdps. 

## **21.2 IPREG_SYS1_REG_43** 

|Name: IPREG_SYS1_REG_43<br>Address: 43 (2Bh)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: IPREG_SYS1_REG_43<br>Address: 43 (2Bh)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: IPREG_SYS1_REG_43<br>Address: 43 (2Bh)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: MCLK|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:6|-|Reserved|
|5:0|GYRO_X_OFFUSER[13:8]|Upper bits for X-gyro offset programmed by user. Range is ±62.5dps,<br>resolution is 7.5mdps.|



## **21.3 IPREG_SYS1_REG_56** 

Name: IPREG_SYS1_REG_56 Address: 56 (38h) Serial IF: R/W Reset value: 0x00 Clock Domain: MCLK **BIT NAME FUNCTION** Low bits for Y-gyro offset programmed by user. Range is ±62.5dps, resolution 7:0 GYRO_Y_OFFUSER[7:0] is 7.5mdps. 

## **21.4 IPREG_SYS1_REG_57** 

Name: IPREG_SYS1_REG_57 Address: 57 (39h) Serial IF: R/W Reset value: 0x00 Clock Domain: MCLK **BIT NAME FUNCTION** 7:6 - Reserved Upper bits for Y-gyro offset programmed by user. Range is ±62.5dps, 5:0 GYRO_Y_OFFUSER[13:8] resolution is 7.5mdps. 

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## **21.5 IPREG_SYS1_REG_70** 

Name: IPREG_SYS1_REG_70 Address: 70 (46h) Serial IF: R/W Reset value: 0x00 Clock Domain: MCLK **BIT NAME FUNCTION** Low bits for Z-gyro offset programmed by user. Range is ±62.5dps, resolution 7:0 GYRO_Z_OFFUSER[7:0] is 7.5mdps. 

## **21.6 IPREG_SYS1_REG_71** 

|**21.6**<br>**IPREG_SYS1_REG_71**|**21.6**<br>**IPREG_SYS1_REG_71**|**21.6**<br>**IPREG_SYS1_REG_71**|
|---|---|---|
|Name: IPREG_SYS1_REG_71<br>Address: 71 (47h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7:6|-|Reserved|
|5:0|GYRO_Z_OFFUSER[13:8]|Upper bits for Z-gyro offset programmed by user. Range is ±62.5dps,<br>resolution is 7.5mdps.|



## **21.7 IPREG_SYS1_REG_166** 

Name: IPREG_SYS1_REG_166 Address: 166 (A6h) Serial IF: R/W Reset value: 0x1B Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|7|-|Reserved|
|||Gyro SRC CTRL:|
|||0: Interpolator and AAF FIR filter off|
|6:5|GYRO_SRC_CTRL|1: Interpolator off and AAF FIR filter on|
|||2: Interpolator on and AAF FIR filter on|
|||3: Reserved(debugmode)|
|4:0|-|Reserved|



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## **21.8 IPREG_SYS1_REG_170** 

Name: IPREG_SYS1_REG_170 Address: 170 (AAh) Serial IF: R/W Reset value: 0x0A Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|7:5|-|Reserved|
|||Gyro Low Power Mode Averaging Filter Selection|
|||0000: 1x|
|||0001: 2x|
|||0010: 4x|
|||0011: 5x|
|||0100: 7x|
|||0101: 8x|
|4:1|GYRO_LP_AVG_SEL|0110: 10x|
|||0111: 11x|
|||1000: 16x|
|||1001: 18x|
|||1010: 20x|
|||1011: 32x|
|||1100: 64x|
|||Others: Reserved|
|0|-|Reserved|



## **21.9 IPREG_SYS1_REG_172** 

Name: IPREG_SYS1_REG_172 Address: 172 (ACh) Serial IF: R/W Reset value: 0x80 Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|7:3|-|Reserved|
|||Selects cut-off bandwidth for Gyro UI path LPF|
|||000: Bypass|
|||001: ODR/4|
|||010: ODR/8|
|2:0|GYRO_UI_LPFBW_SEL|011: ODR/16|
|||100: ODR/32|
|||101: ODR/64|
|||110: ODR/128|
|||111: ODR/128|



Note: When the FIR AAF is enabled, the signal path BW is decided by the FIR AAF and UI LPF combination. Please refer to AN-000365 ICM-456xx User Guide for details. 

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## _**22 USER BANK IPREG_SYS2 REGISTER MAP – DESCRIPTIONS**_ 

This section describes the function and contents of each register within user bank IPREG_SYS2. The registers described in this section are indirect access registers. Section 13 describes the procedure for accessing indirect access registers. 

## **22.1 IPREG_SYS2_REG_24** 

Name: IPREG_SYS2_REG_24 Address: 24 (18h) Serial IF: R/W Reset value: 0x00 Clock Domain: MCLK **BIT NAME FUNCTION** Low bits for X-accel offset programmed by user. Range is ±1g, resolution is 7:0 ACCEL_X_OFFUSER[7:0] 0.125mg. 

## **22.2 IPREG_SYS2_REG_25** 

|Name: IPREG_SYS2_REG_25<br>Address: 25 (19h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: IPREG_SYS2_REG_25<br>Address: 25 (19h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: IPREG_SYS2_REG_25<br>Address: 25 (19h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: MCLK|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:6|-|Reserved|
|5:0|ACCEL_X_OFFUSER[13:8]|Upper bits for X-accel offset programmed by user. Range is ±1g, resolution is<br>0.125mg.|



## **22.3 IPREG_SYS2_REG_32** 

Name: IPREG_SYS2_REG_32 Address: 32 (20h) Serial IF: R/W Reset value: 0x00 Clock Domain: MCLK **BIT NAME FUNCTION** Low bits for Y-accel offset programmed by user. Range is ±1g, resolution is 7:0 ACCEL_Y_OFFUSER[7:0] 0.125mg. 

## **22.4 IPREG_SYS2_REG_33** 

|Name: IPREG_SYS2_REG_33<br>Address: 33 (21h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: IPREG_SYS2_REG_33<br>Address: 33 (21h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: MCLK|Name: IPREG_SYS2_REG_33<br>Address: 33 (21h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: MCLK|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:6|-|Reserved|
|5:0|ACCEL_Y_OFFUSER[13:8]|Upper bits for Y-accel offset programmed by user. Range is ±1g, resolution is<br>0.125mg.|



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## **22.5 IPREG_SYS2_REG_40** 

|**22.5**<br>**IPREG_SYS2_REG_40**|**22.5**<br>**IPREG_SYS2_REG_40**|**22.5**<br>**IPREG_SYS2_REG_40**|
|---|---|---|
|Name: IPREG_SYS2_REG_40<br>Address: 40 (28h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7:0|ACCEL_Z_OFFUSER[7:0]|Low bits for Z-accel offset programmed by user. Range is ±1g, resolution is<br>0.125mg.|



## **22.6 IPREG_SYS2_REG_41** 

|**22.6**<br>**IPREG_SYS2_REG_41**|**22.6**<br>**IPREG_SYS2_REG_41**|**22.6**<br>**IPREG_SYS2_REG_41**|
|---|---|---|
|Name: IPREG_SYS2_REG_41<br>Address: 41 (29h)<br>Serial IF: R/W<br>Reset value: 0x00<br>Clock Domain: MCLK|||
|**BIT**|**NAME**|**FUNCTION**|
|7:6|-|Reserved|
|5:0|ACCEL_Z_OFFUSER[13:8]|Upper bits for Z-accel offset programmed by user. Range is ±1g, resolution is<br>0.125mg.|



## **22.7 IPREG_SYS2_REG_123** 

Name: IPREG_SYS2_REG_123 Address: 123 (7Bh) Serial IF: R/W Reset value: 0x14 Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|7:2|-|Reserved|
|||Accel SRC CTRL:|
|||0: Interpolator and AAF FIR filter off|
|1:0|ACCEL_SRC_CTRL|1: Interpolator off and AAF FIR filter on|
|||2: Interpolator on and AAF FIR filter on|
|||3: Reserved(debugmode)|



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## **22.8 IPREG_SYS2_REG_129** 

Name: IPREG_SYS2_REG_129 Address: 129 (81h) Serial IF: R/W Reset value: 0x02 Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|7:4|-|Reserved|
|||Accel Low Power Mode Averaging Filter Selection|
|||0000: 1x|
|||0001: 2x|
|||0010: 4x|
|||0011: 5x|
|||0100: 7x|
|||0101: 8x|
|3:0|ACCEL_LP_AVG_SEL|0110: 10x|
|||0111: 11x|
|||1000: 16x|
|||1001: 18x|
|||1010: 20x|
|||1011: 32x|
|||1100: 64x|
|||Others: Reserved|



## **22.9 IPREG_SYS2_REG_131** 

Name: IPREG_SYS2_REG_131 Address: 131 (83h) Serial IF: R/W Reset value: 0x00 Clock Domain: MCLK 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|7:3|-|Reserved|
|||Selects cut-off bandwidth for Accel UI path LPF|
|||000: Bypass|
|||001: ODR/4|
|||010: ODR/8|
|2:0|ACCEL_UI_LPFBW_SEL|011: ODR/16|
|||100: ODR/32|
|||101: ODR/64|
|||110: ODR/128|
|||111: ODR/128|



Note: When the FIR AAF is enabled, the signal path BW is decided by the FIR AAF and UI LPF combination. Please refer to AN-000365 ICM-456xx User Guide for details. 

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## _**23 REFERENCE**_ 

Please refer to the following application notes for additional information. 

- IxM-4xxxx, IxM-2xxxx and MPU-6xxx Products PCB Design, Mounting, and Handling Guidelines (AN000393) 

- Understanding IMU Sensor Offset (AN-000257) 

- TDK InvenSense IMU Calibration Application Note (AN-000265) 

- ICM-456xx Errata Update (AN-000364) 

- ICM-45605 & ICM-45686 User Guide (AN-000478) 

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## _**24 REVISION HISTORY**_ 

|**Revision Date**|**Revision**|**Description**|
|---|---|---|
|07/25/2024|1.0|Initial Release|



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## ~~G8 TDIB tvenserse~~ 

This information furnished by InvenSense or its affiliates (“TDK InvenSense”) is believed to be accurate and reliable. However, no responsibility is assumed by TDK InvenSense for its use, or for any infringements of patents or other rights of third parties that may result from its use. Specifications are subject to change without notice. TDK InvenSense reserves the right to make changes to this product, including its circuits and software, in order to improve its design and/or performance, without prior notice. TDK InvenSense makes no warranties, neither expressed nor implied, regarding the information and specifications contained in this document. TDK InvenSense assumes no responsibility for any claims or damages arising from information contained in this document, or from the use of products and services detailed therein. This includes, but is not limited to, claims or damages based on the infringement of patents, copyrights, mask work and/or other intellectual property rights. 

Certain intellectual property owned by InvenSense and described in this document is patent protected. No license is granted by implication or otherwise under any patent or patent rights of InvenSense. This publication supersedes and replaces all information previously supplied. Trademarks that are registered trademarks are the property of their respective companies. TDK InvenSense sensors should not be used or sold in the development, storage, production or utilization of any conventional or mass-destructive weapons or for any other weapons or life threatening applications, as well as in any other life critical applications such as medical equipment, transportation, aerospace and nuclear instruments, undersea equipment, power plant equipment, disaster prevention and crime prevention equipment. 

©2024 InvenSense. All rights reserved. InvenSense, MotionTracking, MotionProcessing, MotionProcessor, MotionFusion, MotionApps, DMP, AAR, and the InvenSense logo are trademarks of InvenSense, Inc. The TDK logo is a trademark of TDK Corporation. Other company and product names may be trademarks of the respective companies with which they are associated. 

©2024 InvenSense. All rights reserved. 

Page 191 of 191 

Document Number: DS-000576 Revision: 1.0
Updated at April 17, 2026
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