ICL5102HVXUMA1

**ICL5102HV Data Sheet** 

**==> picture [103 x 46] intentionally omitted <==**

## **ICL5102HV PFC + Resonant Half-Bridge Controller for LED Drivers** 

## **2nd Generation** 

## **Datasheet** 

## **Rev1.2** 

## **Features** 

- Integrated two stage combination controller allows for reduced number of external components, optimizes Bill of Materials (BOM) and form factor. 

- PFC controller with Critical Conduction Mode (CrCM) + Discontinuous Conduction Mode (DCM) 

- Resonant Half-Bridge (HB) controller with fixed or variable switching frequency control 

- Maximum 500 KHz HB switching frequency and soft-start frequency up to 1.3 MHz 

- Resonant HB Burst Mode (BM) ensures power limitation and low standby power < 300mW. 

- Supports universal AC input voltage (90 to 480 Vrms) nominal 

- Excellent system efficiency up to 94% 

- THD optimization ensures Low harmonic distortion (Total Harmonic Distortion (THD) < 5%) down to 30% nominal load. 

- Integrated High Side MOSFET driver 

Comprehensive set of protection features with auto-restart reaction: 

- Input brown-out protection 

- PFC bus over-voltage protection 

- PFC over-current protection 

- Output over-voltage protection (OVP) 

- Output over-current/short circuit protection (OCP) 

- Output over-power/over-load protection (OPP) 

- Capacitive mode protection 

- External over-temperature protection (OTP) 

## **Potential applications** 

- Offline LED Drivers for commercial and industrial lighting up to 350 W 

- High density AC/DC power supply 

## **Product validation** 

|**Product validation**||
|---|---|
|**Product Type **|**Package **|
|ICL5102HV|PG-DSO-19|



Please read the Important Notice and Warnings at the end of this document page 1 of 34 

Datasheet **www.infineon.com** 

V 1.2 2019-04-01 

**ICL5102HV PFC + Resonant Half-Bridge Controller 2nd Generation** 

## **Description** 

The ICL5102HV is a highly integrated multi-mode ~~(C~~ r ~~CM and DCM) PFC and~~ resonant HB combination controller. The integration of PFC and HB into a single controller enables reduction of external compon ~~e~~ nts and optimizes performance by harmonized operation ~~o~~ f the two stages. 

The two ~~-stag~~ e a ~~p~~ p ~~r~~ oach divides the ~~PFC resp~~ onsibilities from t ~~h~~ e output current regulatio ~~n~~ s functions. This ensures low variation in the output voltage and current and allows for low THD, high power f ~~a~~ ctor and a greater ability to w ~~ithsta~~ nd AC line perturb ~~atio~~ ns. The multi-mod ~~e op~~ e ~~r~~ a ~~t~~ i ~~o~~ n of P ~~FC~~ converter provides excellent efficiency over the whole load range. 

Resonant HB converter supports b ~~ot~~ h ~~LLC and~~ LCC topologies with fixed or variabl ~~e s~~ witching frequency control for highest efficiency and the ~~BM enables the low standby power consumpt~~ ion. 

A comprehensive set of protection features with a ~~uto-restart ensures the highest~~ safe ~~ty and rel~~ iability of the components and overall system. 

The following ~~Figure shows a typical LED driver application using ICL510~~ 2HV with PFC+LCC topology: 

**Figure 1 ICL5102HV Typical Application with PFC+LCC Topology** 

## **Table of contents** 

|**Features ........................................................................................................................................ 1**|
|---|
|**Potential applications ..................................................................................................................... 1**|
|**Product validation .......................................................................................................................... 1**|
|**Description .................................................................................................................................... 2**|
|**Table of contents ............................................................................................................................ 2**|
|**1**<br>**Pin Configuration and Description ........................................................................................... 4**|
|**2**<br>**Functional Block Diagram ....................................................................................................... 6**|
|**3**<br>**Functional Description ............................................................................................................ 7**|
|3.1<br>IC Power Up ............................................................................................................................................. 7|
|3.2<br>Multi-Mode PFC Controller ...................................................................................................................... 7|



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|3.2.1|Control Scheme .................................................................................................................................. 7|
|---|---|
|3.2.1.1|PFC Soft-start ................................................................................................................................ 8|
|3.2.1.2|PFC Multi-Mode Control ................................................................................................................ 8|
|3.2.1.3|PFC THD Correction .................................................................................................................... 10|
|3.2.2|PFC Bus voltage Sensing .................................................................................................................. 10|
|3.2.3|Input voltage sensing ....................................................................................................................... 11|
|3.2.4|PFC Inductor Peak Current limitation ............................................................................................. 11|
|3.2.5|PFC Protection features ................................................................................................................... 11|
|3.2.5.1|PFC Bus Under-voltage Protection ............................................................................................. 12|
|3.2.5.2|PFC Bus Over-voltage Protection Level 1 ................................................................................... 12|
|3.2.5.3|PFC Bus Over-voltage Protection Level 2 ................................................................................... 12|
|3.2.5.4|PFC Open Control Loop Protection ............................................................................................ 12|
|3.2.5.5|PFC Inductor Over-current Protection ....................................................................................... 12|
|3.2.5.6|Input Brown-out Protection ....................................................................................................... 13|
|3.3|Resonant Half-Bridge Controller .......................................................................................................... 13|
|3.3.1|Control Scheme ................................................................................................................................ 13|
|3.3.1.1|HB Frequency Control via CCO ................................................................................................... 13|
|3.3.1.2|HB Controller Frequency Setting................................................................................................ 14|
|3.3.1.3|HB Soft-Start Control via TCO .................................................................................................... 15|
|3.3.1.4|HB Burst Mode operation ........................................................................................................... 16|
|3.3.2|HB Self-Adaptive Dead Time ............................................................................................................ 17|
|3.3.3|HB Protection Features .................................................................................................................... 18|
|3.3.3.1|HB Over-Current Protection Level 1 (OCP1) ............................................................................... 18|
|3.3.3.2|HB Over-Current Protection Level 2 (OCP2) ............................................................................... 18|
|3.3.3.3|HB Output Over-Voltage Protection ........................................................................................... 19|
|3.3.3.4|HB Capacitive Mode Protection .................................................................................................. 19|
|3.4|Other Protection Features .................................................................................................................... 20|
|3.4.1|External Over-Temperature Protection (OTP) ................................................................................ 20|
|**4**<br>**ICL5102HV Operation Flow Chart ............................................................................................ 22**||
|**5**<br>**Electrical Characteristics ....................................................................................................... 23**||
|5.1|Package Characteristics ........................................................................................................................ 23|
|5.2|Absolute Maximum Ratings .................................................................................................................. 23|
|5.3|Operating Conditions ............................................................................................................................ 24|
|5.4|DC Electrical Characteristics ................................................................................................................. 25|
|5.4.1|Power Supply Characteristics .......................................................................................................... 25|
|5.4.2|PFC Stage Characteristics ................................................................................................................ 26|
|5.4.3|HB Stage Characteristics .................................................................................................................. 28|
|**6**<br>**Package Dimensions .............................................................................................................. 32**||
|**Revision**|**history............................................................................................................................. 33**|



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**Pin Configuration and Description** 

**==> picture [103 x 46] intentionally omitted <==**

## **1 Pin Configuration and Description** 

ICL5102HV pin assignments and basic pin description are shown below in the **Figure 2** and **Table 1** . 

|LSGD|||1|||20|||N.C.|
|---|---|---|---|---|---|---|---|---|---|
|LSCS|||2|||19|||HSGD|
|PFCZCD<br>GND<br>PFCGD<br>PFCCS<br>VCC|||7<br>4<br>5<br>6<br>3|ICL5102HV||14<br>17<br>16<br>15<br>18|||HSVCC<br>HSGND<br>BO<br>OVP|
|PFCVS|||8|||13|||OTP|
|N.C.|||9|||12|||BM|
|RF|||10|||11|||N.C.|
|||||PG-DSO-19-1|(300mil)|||||



## **Figure 2 Pinning of ICL5102HV** 

## **Table 1 Pin Definitions and Functions** 

|**Name**|**Pin**|**Type **|**Function**|
|---|---|---|---|
|LSGD|1|O|**HB low side gate driver**<br>Output for directlydrivingthe HB low side MOSFET via a resistor|
|LSCS|2|I|**HB current sense**<br>Connected to an external shunt resistor and the source of the HB low side<br>MOSFET|
|VCC|3|I|**Positive power supply**<br>ICpower supply|
|GND|4|-|**Ground**<br>IC Ground|
|PFCGD|5|O|**PFC gate driver**<br>Output for directlydrivingthe PFC MOSFET via a resistor|
|PFCCS|6|I|**PFC current sense**<br>Connected to an external shunt resistor and the source of the PFC MOSFET|
|PFCZCD|7|I|**PFC zero-crossing detection**<br>Connected to the PFC auxiliary winding via a resistor for PFC inductor current<br>zero-crossingdetection|
|PFCVS|8|I|**PFC bus voltage sense**<br>Connected to a high impedance resistor divider from the PFC controller output<br>for bus voltage sensing|
|N.C.|9|-|**Not Connected**|
|RF|10|I|**HB minimum switching frequency setting**<br>Connected via an external resistor to GND for HB minimum switching<br>frequencysetting|



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**ICL5102HV PFC + Resonant Half-Bridge Controller 2nd Generation** 

## **Pin Configuration and Description** 

|**Name**|**Pin**|**Type **|**Function**|
|---|---|---|---|
|N.C.|11|-|**Not Connected**|
|BM|12|I|**Burst Mode (BM) enter/exit switching frequency setting**<br>Connected to an opto-coupler and to the RF pin with an external resistor for<br>BM enter/exit setting|
|OTP|13|I|**Over Temperature Protection (OTP)**<br>Connected to an external Negative Temperature Coefficient thermistor (NTC)<br>for external over temperatureprotection|
|BO|14|I|**Brown in/out detection**<br>Connected to the rectified input voltage via an external resistor for input<br>brown in/out detection|
|OVP|15|I|**Output Over Voltage Protection (OVP)**<br>Connected to the HB auxiliary winding via a resistor divider and diode for OVP<br>of the secondaryoutput voltage|
|-|16|-|**Creepage Distance**|
|HSGND|17|-|**High side ground**<br>Ground for floatinghigh side driver of HB|
|HSVCC|18|I|**High side VCC power supply**<br>Power supply of the high side floating driver of HB, supplied via bootstrap<br>circuit|
|HSGD|19|O|**High side floating gate driver**<br>Output for directlydrivingthe HB floatinghigh side MOSFET via a resistor.|
|N.C.|20|-|**Not Connected**|



The ICL5102HV pin connection schematic is shown in the following **Figure 3** : 

**Figure 3 ICL5102HV Pin Connection** 

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**ICL5102HV PFC + Resonant Half-Bridge Controller 2nd Generation** 

## **Functional Block Diagram** 

## **2 Functional Block Diagram** 

**Figure 4 ICL5102HV Functional Block Diagram** 

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**ICL5102HV PFC + Resonant Half-Bridge Controller 2nd Generation** 

**Functional Description** 

**==> picture [103 x 46] intentionally omitted <==**

## **3 Functional Description** 

Functional description section provides an overview of the integrated functions. It includes: 

- ICL5102HV power up 

- Multi-mode PFC controller 

- Resonant HB controller 

The parameters and equations are based on typical values at TA = 25 °C. The correlated minimum and maximum values are shown in the electrical characteristics in chapter **5** . 

## **3.1 IC Power Up** 

ICL5102HV has four power supply pins: VCC, GND, HSVCC and HSGND: 

- Normal start-up operation of ICL5102HV requires a positive voltage at pin VCC higher than the turn-on threshold VCC_on. After the ICL5102HV is active, the Vcc voltage should remain between the VCC_on and VCC_off Once the voltage drops below VCC_off, under-voltage lock out (UVLO) will occur and IC operation is disabled. 

- HSVCC and HSGND power pins are the power supply for the integrated floating high side driver, usually derived using an external boot strap circuit. The high side driver is active after the voltage between pin HSVCC and HSGND is higher than the turn-on threshold VHSVCC_on. Once this voltage drops below VHSVCC_off in the normal operation, the high side driver is disabled. 

## **3.2 Multi-Mode PFC Controller** 

The PFC controller ensures high power quality by maximizing the power factor (PF) and minimizing Total Harmonic Distortion (THD). It is designed in a boost topology to provide a constant high DC voltage for the HB controller. 

## **3.2.1 Control Scheme** 

During normal to heavy load conditions, PFC bus voltage regulation is achieved using CrCM with a constant ontime control. The PFC MOSFET on-time is proportional to the PFC output power and determined by the PFC choke inductance LPFC, the input voltage Vin_rms, the applied PFC load PO_PFC and the PFC converter efficiency ηPFC. This is given by: 

**==> picture [127 x 28] intentionally omitted <==**

ICL5102HV PFC controller has an integrated PI compensator which calculates the PFC on-time according to the error between the value at PFCVS pin and the reference value VPFC_ref = 2.5 V. A notch filter before the compensator filters out the double AC line frequency ripple in the bus voltage and stabilizes the controller loop. 

To support light load condition, DCM is implemented for efficient operation. 

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**ICL5102HV PFC + Resonant Half-Bridge Controller 2nd Generation Functional Description** 

## **3.2.1.1 PFC Soft-start** 

After the voltage at pin VCC is higher than the threshold VCC_on, PFC controller will initiate a soft-start to minimize the stress on the input filter, PFC MOSFET, PFC choke and diode when the following conditions are fulfilled: 

- Brown-in: the voltage at Brown-Out pin (BO) must be higher than VBO_in = 1.4 V 

- PFC open-loop not detected: the voltage at pin PFCVS must be higher than VPFCVSUV2 = 12.5%*VPFC_ref = 0.31 V 

- PFC output over-voltage not detected: the voltage at pin PFCVS must be lower than VPFCVSUV2 = 105%* VPFC_ref = 2.63 V 

- Other protections (e.g. OTP or OVP) not present 

ICL5102HV PFC soft-start is implemented by increasing PFC MOSFET on-time from tPFC_on_initial to tPFC_on_max = 22 us every 280 us. The initial PFC on-time tPFC_on_initial is dependent on the input voltage sensed at the BO pin. Once the voltage at pin PFCVS reaches the threshold VPFC_UV2 = 95%* VPFC_ref = 2.375V, soft-start is completed. At this time normal operation on-time control takes place via the integrated PI compensator. 

## **3.2.1.2 PFC Multi-Mode Control** 

During CrCM operation of the PFC, the PFC MOSFET is turned on with a constant on-time throughout the complete AC half cycle and the off-time is varying depending on the instantaneous value of the input AC voltage amplitude. Therefore, the switching frequency is changing within each AC half cycle with the lowest switching frequency at the peak of the AC input voltage and the highest switching frequency near the zero-crossings. As shown in the **Figure 5** , a new switching cycle starts with a tiny delay after the inductor current reaches zero. 

**Figure 5 Switching Cycle of ICL5102HV Critical Conduction Mode PFC** 

PFC CrCM is ideal for full and heavy load conditions, where the constant on-time is large.  As load decreases and/or the input AC input peak voltage increases towards the magnitude of the PFC output bus voltage, on-times reduces (switching frequency increases), and PFC switching losses increase.  This results in poor efficiency at light load and/or high AC line conditions. 

To help minimize switching losses during this condition and to optimize light load efficiency, the ICL5102HV PFC controller switches from CrCM to DCM mode.  This transition occurs once the PFC MOSFET on-time reduces below 1 us.  In DCM operation, the switching frequency can be further reduced by skipping switching cycles once the PFC inductor current reaches zero.  As shown in the **Figure 6** , the inserted delay is the switching time (from PFC gate on until the PFC inductor current decreases to zero) multiplied with an internal factor. Once the PFC on-time increases to 4 us in the DCM operation, ICL5102HV will switch back to CrCM. The transferred power is regulated 

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## **ICL5102HV PFC + Resonant Half-Bridge Controller 2nd Generation** 

## **Functional Description** 

both in CrCM and DCM operation. The on-time hysteresis between the two modes (overlapped area) ensures the smooth mode change as shown in the **Figure 7** . 

## **Figure 6 ICL5102HV PFC Mode Change from CrCM to DCM** 

**Figure 7 ICL5102HV Operating Frequency and On-Time in CrCM and DCM** 

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**ICL5102HV PFC + Resonant Half-Bridge Controller 2nd Generation** 

## **Functional Description** 

## **3.2.1.3 PFC THD Correction** 

The input AC current becomes most distorted in the area when zero-crossings of AC input voltage occurs. In order to ensure the sinusoidal current waveform in this area, the ICL5102HV extends the PFC on-time dynamically up to two times of PFC maximum on-time according to the instantaneous value of the input voltage amplitude. The detection of AC input voltage zero-crossings is realized through the PFC auxiliary winding. When the voltage across the PFC auxiliary winding after PFC MOSFET turns-off reaches the maximum value, AC zero-crossings is detected. The concept of THD correction is shown in the following **Figure 8** . 

**Figure 8 PFC THD Correction** 

## **3.2.2 PFC Bus voltage Sensing** 

The PFC output bus voltage is scaled down using a resistor divider and sensed at the pin PFCVS pin as shown in the **Figure 9** . A good quality ceramic filter capacitor should be placed as close as possible at the pin to filter any high frequency switching noise.  This filter capacitor ensures no false PFC bus voltage protections are triggered due to noise perturbations. 

**Figure 9 ICL5102HV PFC Bus Voltage Sensing** 

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**Functional Description** 

## **3.2.3 Input voltage sensing** 

As shown in the **Figure 10** , the AC input voltage is sensed at the BO pin with a resistor divider which scales down the full wave rectified AC line voltage. A smooth capacitor CBO with a high ohmic resistor RBO1 are strongly recommended direct after the full wave rectifier diodes so that the peak value of AC input voltage is sensed. As the peak value of AC input voltage is not distorted when the input current is near zero (e.g. in case of brown-out) compared to the RMS value. 

## **Figure 10 ICL5102HV Input Voltage Sensing** 

The voltage at the BO pin which represents the peak voltage of the AC input has feed-forward control on the PFC converter. 

- It decides the initial on-time of the initial PFC soft-start. 

- In the light load condition, the PFC on-time is dependent on the input voltage. 

The brown-in and brown-out are implemented by sensing the voltage at BO pin. The conditions are defined as following: 

- Brown-in: the voltage at pin BO is higher than VBO_in = 1.4 V. 

- Brown-out: the voltage at pin BO is lower than VBO_out = 1.2 V in the normal operation. 

## **3.2.4 PFC Inductor Peak Current limitation** 

The PFC inductor peak current through the PFC MOSFET is monitored via the PFC shunt resistor RPFCCS to limit the maximum power through the PFC inductor, MOSFET and the freewheeling diode. Once the voltage across the shunt resistor exceeds the over-current threshold VPFC_OCP1 = 1.0 V for longer than the blanking time (including propagation delay) tPFC_OCP1_blanking = 200 ns, the PFC MOSFET is turned off immediately. The next PFC switching cycle will be initialized on either PFC ZCD or maximum period time out. This peak current limitation is active in every switching cycle. 

## **3.2.5 PFC Protection features** 

Protections features are triggered if fault conditions are present longer than the blanking time. The controller may continue operation after exceeding protection threshold because of blanking time as shown in **Figure 11** . 

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## **Functional Description** 

**Figure 11 Excess of threshold due to Blanking Time** 

## **3.2.5.1 PFC Bus Under-voltage Protection** 

PFC bus under-voltage is monitored at the PFCVS pin. 

In the normal operation, the PFCVS pin voltage is sensed and compared to the under-voltage threshold VPFC_UV1 = 75%* VPFC_ref = 1.88 V. Once the pin voltage is below this threshold for longer than the blanking time, PFC stops switching and ICL5102HV will enter auto-restart. 

## **3.2.5.2 PFC Bus Over-voltage Protection Level 1** 

PFC bus over-voltage level 1 is monitored at the PFCVS pin. 

The PFCVS pin voltage is sensed and compared to the over-voltage threshold VPFC_OV1 = 109%* VPFC_ref = 2.73 V. Once the pin voltage is above this threshold, PFC will stop switching within 5 us. As long as the pin voltage drops below VPFC_OV = 105%* VPFC_ref = 2.63 V, PFC resumes operation. 

## **3.2.5.3 PFC Bus Over-voltage Protection Level 2** 

PFC bus over-voltage level 2 is monitored at the PFCVS pin. 

The PFCVS pin voltage is sensed and compared to the over-voltage threshold VPFC_OV2 = 115%* VPFC_ref = 2.88 V. Once the pin voltage is above this threshold for longer than the blanking time, both PFC and HB stop switching and ICL5102HV will enter auto-restart. 

## **3.2.5.4 PFC Open Control Loop Protection** 

PFC control loop open is monitored at the PFCVS pin. 

The PFCVS pin voltage is sensed and compared to the under-voltage threshold VPFC_UV2 = 12.5%* VPFC_ref = 0.31 V. 

- In the normal operation, once the pin voltage is below this threshold for longer than the blanking time, both PFC and HB stop switching and ICL5102HV will enter auto-restart. 

- In the IC power up phase, if the pin voltage is below this threshold, ICL5102HV will not start-up. 

## **3.2.5.5 PFC Inductor Over-current Protection** 

PFC inductor over-current is monitored at the PFCCS pin. 

The voltage across the PFC current sense shunt resistor is sensed at the PFCCS pin and compared to the overcurrent threshold VPFC_OCP1 = 1.0 V. Once the pin voltage is above this threshold for longer than the blanking time tPFC_OCP1_blanking = 200 ns, the PFC MOSFET is turned off in the current switching cycle. 

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**Functional Description** 

## **3.2.5.6 Input Brown-out Protection** 

Input brown-out is monitored at the BO pin. 

The BO pin voltage is sensed and compared to the brown-out threshold VBO_out = 1.2V. 

- In the normal operation, once the pin voltage is below this threshold for longer than the blanking time tblanking_BO = 50ms, both PFC and HB stop switching and ICL5102HV will enter auto-restart. Once the pin voltage is higher than VBO_in = 1.4V, normal operation starts (brown-in). 

- In the IC power up phase, if the pin voltage is below this threshold, ICL5102HV will not start-up. 

## **3.3 Resonant Half-Bridge Controller** 

Resonant Half-Bridge (HB) topologies reduce losses and switching noise in the converter compared to traditional “Hard Switching” topologies.  This is accomplished by soft commutation in a sinusoidal manner and zero voltage switching (ZVS) of HB MOSFETs. 

Soft commutation of the power devices allows for increased converter operating switching frequency and smaller sizes of the passive components such as transformers and filters. ICL5102HV provides the independent control of resonant HB (e.g. LLC or LCC) for constant voltage (CV) or constant current (CC) output. It supports both fixed and variable switching frequency control. 

## **3.3.1 Control Scheme** 

The ICL5102HV resonant HB control is realized through a TCO (Time Controlled Oscillator) in the soft-start phase and a current controlled oscillator (CCO) in the regulated normal operation.  During light load operation the ICL5102HV will enter Burst Mode (BM) to maximize light-load efficiency. This is described as following: 

- HB switching frequency control via the Current Controlled Oscillator (CCO) 

- HB controller frequency setting 

- Soft-start control via a Time Controlled Oscillator (TCO) 

- HB Burst Mode (BM) operation 

## **3.3.1.1 HB Frequency Control via CCO** 

During normal operation, ICL5102HV HB controller uses CCO to determine the switching frequency.  The switching frequency is determined by current IRF that flows out of the RF pin. The RF pin maintains a constant voltage of VRF = 2.5 V. This voltage together with the voltage at pin VBM, resistors RBM and RRF, and the opto-coupler define the current flowing out of the RF pin as shown in the following formula and **Figure 12** : 

**==> picture [149 x 26] intentionally omitted <==**

**----- Start of picture text -----**<br>
𝐼𝑅𝐹 = 𝐼1 + 𝐼2 = 𝐼𝐵𝑀 + 𝐼𝑂𝑃 + 𝑅 [𝑉][𝑅𝐹] 𝑅𝐹<br>**----- End of picture text -----**<br>


**Figure 12 ICL5102HV RF Pin Current Definition** 

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## **ICL5102HV PFC + Resonant Half-Bridge Controller 2nd Generation** 

## **Functional Description** 

The CCO of ICL5102HV HB controller is defined linearly with the constant slew rate CFC as shown in **Figure 13** : 

## 𝐶𝐹𝐶 = 400 𝐾𝐻𝑧/𝑚𝐴 

**Figure 13 CCO of ICL5102HV in Normal Operation** 

## **3.3.1.2 HB Controller Frequency Setting** 

Both TCO and CCO of ICL5102HVHV operate based on the defined minimum and maximum HB operating frequency. 

- Minimum HB operating frequency  fHB_min: 

It is defined in the HB resonant tank calculation to prevent HB operation in the capacitive region where reverse gain occurs and HB MOSFETs ZVS is lost. ICL5102HV HB controller operates with fHB_min if the minimum current IRF_min flows out of the RF pin according to the CCO: 

**==> picture [110 x 12] intentionally omitted <==**

This minimum current occurs when the opto-coupler is off IOP = 0 and the voltage of the pin is clamped at VBM_max = 2.25 V: 

**==> picture [147 x 27] intentionally omitted <==**

- Maximum HB operating frequency fHB_max: 

ICL5102HV HB controller increases the HB operating frequency as the output load reduces. However above the maximum operating frequency fHB_max the output power cannot be reduced furthermore and HB controller enters BM. According to the CCO, fHB_max is defined with the maximum current IFR_max: 

𝑓𝐻𝐵_𝑚𝑎𝑥 = 𝐶𝐹𝐶 ∗𝐼𝑅𝐹_𝑚𝑎𝑥 

ICL5102HV enters BM when the voltage at BM pin is VBM_entry = 0.75V: 

**==> picture [154 x 27] intentionally omitted <==**

- The minimum and maximum HB operating frequencies must fulfill the following condition: 

𝑓𝐻𝐵_𝑚𝑎𝑥 < 7 ∗𝑓𝐻𝐵_𝑚𝑖𝑛 

Both minimum and maximum HB operating frequencies are set together by the external resistors RBM and RRF as shown in the **Figure 12** . 

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**Functional Description** 

## **3.3.1.3 HB Soft-Start Control via TCO** 

ICL5102HV HB controller initializes a soft-start at power up after the bus voltage reaches 75% of nominal value (when the VSPFC pin reaches the VPFC_UV1 = 75%*VPFC_ref = 1.88 V). During soft-start, the HB switching frequency reduces with respect to the elapsed time (time controlled oscillator), which is shown in **Figure 14** : 

**Figure 14 TCO for Half-Bridge Soft-start** 

The complete HB soft-start takes maximum 7 ms and is divided into three time phases in which the frequency reduction has different slew rate: 

- Soft-start phase I 

   - The maximum duration of soft-start phase I is tHB_SS1 = 624 us. 

   - The HB soft-start phase I begins with the switching frequency fHB_ss0, which is defined as: 

      - 𝑓𝐻𝐵_𝑠𝑠0 = 4 ∗(𝑓𝑚𝑎𝑥 −𝑓𝑚𝑖𝑛) + 𝑓𝑚𝑖𝑛 

   - The maximum possible soft-start start frequency is fHB_ss_start_max = 1300 KHz. 

   - The HB soft-start phase I ends with the switching frequency fHB_ss1, which is defines as: 

      - 𝑓𝐻𝐵_𝑠𝑠1 = 2.6 ∗(𝑓𝑚𝑎𝑥 −𝑓𝑚𝑖𝑛) + 𝑓𝑚𝑖𝑛 

- Soft-start phase II 

   - The maximum duration of soft-start phase II is tHB_SS2 = 2.5 ms. 

   - The HB soft-start phase II begins with the switching frequency fHB_ss1. 

   - The HB soft-start phase II ends with the maximum switching frequency fHB_max. 

- Soft-start phase III 

   - The maximum duration of soft-start phase III is tHB_SS3 = 3.75 ms. 

   - The HB soft-start phase III begins with the switching frequency fHB_max. 

   - The HB soft-start phase III ends with the minimum switching frequency fHB_min. 

The voltage at the BM pin is clamped to 0.75 V during soft-start phase I and phase II. Therefore the current flowing out of the RF pin is constant and the HB switching frequency is only determined by the TCO. 

In the soft-start phase III, the voltage at BM pin is ramped up from 0.75 V to 2.25 V and the current flowing out of the RF pin reduces accordingly. In the meantime, as the secondary side output voltage approaches the target value, the current flowing through the opto-coupler primary side begins to increase. Once the current through 

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## **ICL5102HV PFC + Resonant Half-Bridge Controller 2nd Generation** 

## **Functional Description** 

opto-coupler IOP is equal to the current I1 through the resistor RBM so that the current IBM = 0 (see **Figure 12** ), the soft-start is terminated and the CCO will takes over the control from the TCO. 

During soft-start operation, if the voltage at the LSCS pin is greater than the threshold 0.8V, the HB controller will stop reducing the switching frequency. The switching frequency reduction resumes once the voltage drops below the threshold. 

## **3.3.1.4 HB Burst Mode operation** 

ICL5102HV HB controller will enter the BM as the transferred power to output is greater than the output load demands although the HB is operated at the maximum switching frequency fHB_max. It is recommended to put ICL5102 into BM in standby (dim-to-off) mode for lowest input standby power. 

**Figure 15 HB BM Control** 

As shown in the **Figure 15** , the BM control is implemented by the sensing the voltage VBM at pin BM: 

##  BM entry: 

During normal operation, once the BM pin voltage is lower than VHB_BM_Entry = 0.75V for longer than VHB_BM_Entry_blanking = 10ms, ICL5102HV will first initialize a soft-off by increasing the HB switching frequency from fHB_max to fHB_BM. After fHB_BM is reached, both PFC and HB switching are stopped and ICL5102HV is in sleep mode. 

**==> picture [161 x 24] intentionally omitted <==**

##  BM burst-on: 

During sleep mode, the BM pin voltage VBM increases as the output voltage drops. ICL5102HV will activate both PFC and HB stages once VBM = 2.25V is reached. 

The ICL5102HV HB controller turns on with a switching frequency of fHB_BM and steadily decreases it to fHB_max to initialize a soft-on. After soft-on, the switching frequency continues to decrease until the BM power limitation is active. 

##  BM power limitation: 

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## **Functional Description** 

The ICL5102HV activates power limitation in the BM burst-on phase once the switching frequency fHB_PL is reached. The transferred power in BM can be adjusted through the resistor RPL from LSCS pin to the HB low side MOSFET source as shown in the **Figure 16** . In the BM power limitation phase, the HB switching frequency is maintained around fHB_PL. 

## **Figure 16 ICL5102HV Burst Mode Power Limitation** 

- BM burst-off: 

Once current flowing through the opto-coupler (as output voltage increasing) is equal to the current I1 through the resistor RBM which means IBM = 0 (see **Figure 12** ), soft-off operation is initialized by increasing the HB switching frequency to fHB_BM. After fHB_BM is reached, both PFC and HB stages stop switching and ICL5102HV enter the sleep mode. 

- BM exit: 

ICL5102HV will exit the BM under 4 different conditions: 

- During BM burst-off: 

If a sudden output load-step increase occurs during the burst-off phase (sleep mode)   the voltage at BM pin will increase abruptly.  If VBM increases from 2.0 V to 2.25 V within 400 us, ICL5102HV will exit the BM. 

- During BM burst-on when power limitation is active: 

When the ICL5102HV is in the burst-on phase and power limitation is active, the voltage at BM pin is clamped, and cannot change quickly.  Once the voltage change (increasing) ∆VBM = + 100 mV within 8 HB switching cycles, an output load step is detected and ICL5102HV will exit BM. 

- During BM burst-on when power limitation is active: 

Once the BM burst-on duration is longer than 10 ms, which means that a static load at output consumes more power than the BM power limitation level, ICL5102HV will exit the BM. 

- During BM burst-on when power limitation is active: 

Once the BM burst-on duration is 2 times longer than the burst-off duration, which means a higher load at output and the BM is not efficient enough. ICL5102HV will exit the BM. 

To disable the HB BM operation, a resistor between the BM pin and the opto-coupler should be added to prevent the voltage at BM pin to reduce below 0.75 V. 

## **3.3.2 HB Self-Adaptive Dead Time** 

The dead time between ICL5102HV HB low side (LS) and high side (HS) gate driver turn-on signals is self-adaptive. The typical range of the dead time adjustment is between 250 and 750 ns. The dead time is measured after the HS gate driver is turned off until the voltage at pin LSCS drops below -50 mV. This time is then used for the dead time between LS and HS as shown in the **Figure 17** . 

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## **Functional Description** 

**Figure 17 HB Self-Adaptive Dead Time** 

## **3.3.3 HB Protection Features** 

## **3.3.3.1 HB Over-Current Protection Level 1 (OCP1)** 

HB over-current level 1 is monitored at the LSCS pin. 

The voltage across the HB LSCS shunt resistor is sensed at the LSCS pin during the HB low side gate driver turningon and compared to the over-current threshold VHB_OCP1 = 0.8 V. Once the voltage exceeds this threshold, the controller will increase the HB switching frequency cycle by cycle till the maximum switching frequency fHB_maxis reached. If a HB over-current event occurs (HB OCP1) beyond the blanking time tHB_OCP1_blanking = 50ms, ICL5102HV will enter auto-restart. 

**Figure 18 HB Over-current Protection Level 1** 

## **3.3.3.2 HB Over-Current Protection Level 2 (OCP2)** 

HB over-current level 2 is monitored at the LSCS pin. 

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## **ICL5102HV PFC + Resonant Half-Bridge Controller 2nd Generation** 

## **Functional Description** 

The voltage across the HB low side current sense shunt resistor is sensed at the LSCS pin during the HB low side gate driver turning-on and compared to the over-current threshold VHB_OCP2 = 1.6 V. Once the voltage exceeds this threshold for longer than the blanking time tHB_OCP2_blanking = 500ns, both PFC and HB stop switching and ICL5102HV will enter auto-restart. 

## **3.3.3.3 HB Output Over-Voltage Protection** 

HB output over-voltage is monitored at the OVP pin. 

ICL5102HV provides an independent OVP pin for the output-over voltage protection. This pin should be connected to the auxiliary winding of the HB transformer as shown in the **Figure 19** below: 

**Figure 19 HB Output OVP Detection Circuit** 

A resistor divider scales down the auxiliary winding voltage, allowing for auxiliary voltage sensing and OVP protection.  Once the voltage at OVP pin VOVP is higher than VOVP_ref = 2.5 V for longer than tHB_OVP_blank = 5 us, both PFC and HB stages stop switching and ICL5102HV enters auto-restart. 

## **3.3.3.4 HB Capacitive Mode Protection** 

The designed impedance of the resonant network is inductive when the minimum HB switching frequency is above the peak gain frequency. Once the HB switching frequency is below the peak gain frequency, the impedance of the resonant network becomes capacitive and the HB converter enters capacitive mode. Capacitive mode occurs most often due to low input voltage to the HB resonant converter, or during an overload condition on the HB output (shorted or overloaded). 

ICL5102HV detects the capacitive mode operation by monitoring the LSCS pin: 

**Figure 20 HB Capacitive Mode Detection** 

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## **Functional Description** 

As shown in the **Figure 20** , once the voltage at the LSCS pin is greater than 1.6 V during turn-on of the HS gate driver or drops below -50 mV in the second half of LSGD on-time or during the dead time between LS and HS, capacitive mode operation is detected. 

ICL5102HV is able to provide the cycle by cycle frequency control for capacitive mode regulation. This is activated if the LSCS pin voltage is higher than +50 mV within the first 7% of LSGD on-time. The HB controller will increase the frequency cycle by cycle till the +50 mV crossing of the LSCS pin voltage shifts behind the 7% threshold as shown in the **Figure 21** . 

**Figure 21 HB Capacitive Mode Regulation** 

If the capacitive mode operation is detected longer than 620 us despite the capacitive mode control, ICL5102HV will enter auto-restart. 

## **3.4 Other Protection Features** 

## **3.4.1 External Over-Temperature Protection (OTP)** 

External temperature is sensed at the OTP pin via an external NTC resistor from OTP pin to GND. 

The source current out of the OTP pin is IOTP = 100 uA. The current generates a voltage drop on the connected NTC. Once the voltage at the OTP pin decreases below VOTP_off = 625 mV longer than the blanking time tOTP_blanking = 620 us in the normal operation, both PFC and HB stages stop switching and ICL5102HV will enter auto-restart. PFC and HB operations recover after the voltage at the OTP pin is higher than VOTP_start = 703 mV for longer than tOTP_blanking. This is shown in the **Figure 22** . 

It is recommended to place good quality ceramic capacitor close to the OTP pin to prevent noise from falsely triggering OTP protection. 

To disable the External OTP, a resistor can be added at the OTP pin instead of the NTC to hold the voltage always higher than VOTP_start = 703 mV. 

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**Figure 22 External Over-Temperature Protection** 

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**ICL5102HV PFC + Resonant Half-Bridge Controller 2nd Generation ICL5102HV Operation Flow Chart** 

**==> picture [103 x 46] intentionally omitted <==**

## **4 ICL5102HV Operation Flow Chart** 

**==> picture [417 x 633] intentionally omitted <==**

**----- Start of picture text -----**<br>
Operating FLOW Chart ICL5102<br>VCC Clamp OFF<br>UVLO<br>VCC < 9.0V Vcc < 9.0V<br>Icc   < 90µA<br>VCC Clamp ON when VCC > 16.3V<br>Monitoring<br>VCC < 16.3V<br> 9.0V < Vcc < 16.3V<br>VBO < 1.4V<br>Icc  < 100µA<br>VBUS < 12,5% Power-up<br>VBUS > 105% Gate Drives off<br>OTP / OVP 9.0V < VCC < 16.3V<br>Icc  approx 4.0mA<br>VCC Clamp OFF VCC Clamp ON<br>Start-up<br>VBO < 1.2V<br>VBUS < 75% Inverter Gates OFFPFC Gate ON OVP / OTP<br>9.0V < Vcc < 16.3V<br>Fault t = 500ms<br>Exempt BO<br>Softstart<br>Inverter Gates ON Full Protection Full Protection:<br>9.0V < Vcc < 16.3V<br>t > 50ms:<br>fSoftStart = fSSx 16.3V> Vcc > 9.0V VBO < 1.2V<br>Gate Drives off VPFC > 115%<br>POWER Down VLSCS > 0.8V<br>AUTO RESTART t > 620µs:<br>Run<br>OTP / CapLoad<br>9.0 V < Vcc < 16.3V Full Protection t > 5.0µs:<br>f = fRUN OVP<br>VLSCS > 1.6V<br>t > 1.0µs<br>VCC < 9.0V<br>VBM < 0.75V<br>t > 620µs:<br>BM OTP / CapLoad<br>t = 10ms t > 5.0µs:<br>ENTRY OVP<br>VLSCS > 1.6V<br>t > 1.0µs<br>VCC < 9.0V<br>BM Sleep<br>BM EXIT 1 - 4 0.25 < VBM < 2.2V OVPVCC < 9.0V<br>All Gates OFF<br>IBM = xxx µA<br>VBM = 2.2V<br>IBM = 0µA<br>BM Pulse<br>VVBUSBUS < 12.5% > 109% VBM < 2.2V Full Protection<br>fBM = fRUN (stored)<br>EXIT 1 bis<br>EXIT 4<br>**----- End of picture text -----**<br>


**Figure 23 ICL5102HV Operation Flow Chart** 

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## **5 Electrical Characteristics** 

_Note: All voltages except the high-side signals are measured with respect to GND (pin 4). The high-side voltages are measured with respect to HSGND (pin 14). The voltage levels are valid if other ratings are not violated._ 

## **5.1 Package Characteristics** 

## **Table 2 Package Characteristics** 

|**Parameter**|**Symbol**|**Limit Values**|**Limit Values**|**Unit**|**Remarks**|
|---|---|---|---|---|---|
|||**Min.**|**Max.**|||
|Thermal resistance for PG-<br>DSO-19|RthJA|—|60|K/W|PG-DSO-19 @ TA= 85°C &<br>PCB Area > 30x20mm|
|Creepage distance HSGND<br>vs OVPpin|DCRHS|2.1|—|mm||



## **5.2 Absolute Maximum Ratings** 

_Note: Absolute maximum ratings (Table 3) are defined as ratings which when being exceeded may lead to destruction of the integrated circuit. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. These values are not tested during production test._ 

**Table 3 Absolute Maximum Ratings** 

|**Table 3**<br>**Absolute Maximum**|**Ratings**|||||
|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Limit Values**||**Unit**|**Remarks**|
|||**Min.**|**Max.**|||
|LSCSpin Voltage|VLSCS|- 5|6|V||
|LSCSpin Current|ILSCS|- 3|3|mA||
|LSGDpin Voltage|VLSGD|- 0.3|VCC+0.3|V|Internally clamped to 11V|
|LSGDpinpeak source current|ILSGD_O_max|- 75|5|mA|< 500 ns|
|LSGDpinpeak sink current|ILSGD_I_max|- 50|400|mA|< 100 ns|
|Voltage externally supplied to pin<br>VCC|VVcc|- 0.3|18.5|V||
|Vcc pin internal zener diode<br>clampcurrent|IVCC_clamp|- 5|5|mA||
|PFCGDpin voltage|VPFCGD|- 0.3|VCC+0.3|V|Internallyclamped to 11V|
|PFCGDpinpeak source current|IPFCGD_O_max|- 150|5|mA|< 500 ns|
|PFCGDpinpeak sink current|IPFCGD_I_max|- 100|700|mA|< 100 ns|
|PFCCSpin voltage|VPFCCS|- 5|6|V||
|PFCCSpin current|IPFCCS|- 3|3|mA||



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## **Electrical Characteristics** 

|**2nd Generation**<br>**Electrical Characteristics**||||||
|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Limit Values**||**Unit**|**Remarks**|
|||**Min.**|**Max.**|||
|PFCZCDpin voltage|VPFCZCD|- 3|6|V||
|PFCZCDpin current|IPFCZCD|- 5|5|mA||
|PFCVSpin voltage|VPFCVS|- 0.3|5.3|V||
|RFpin voltage|VRF|- 0.3|5.3|V||
|OTPpin voltage|VOTP|- 0.3|5.3|V||
|OVPpin voltage|VOVP|- 0.3|5.3|V||
|BMpin voltage|VBM|- 0.3|5.3|V||
|BOpin Voltage|VBO|- 0.3|5.3|V||
|HSGNDpin voltage|VHSGND|- 980|980|V|Referringto GND**1**|
|HSGNDpin voltage transient|dVHSGND/dt|- 40|40|V/ns||
|Voltage externally supplied to pin<br>HSVCC|VHSVcc|- 0.3|18.0|V|Referred to HSGND|
|HSGDpin voltage|VHSGD|- 0.3|VHSVCC+0.3|V|Internallyclamped to 11V|
|HSGDpinpeak source current|IHSGD_O_max|- 75|0|mA|< 500 ns|
|HSGDpinpeak sink current|IHSGD_I_max|0|400|mA|< 100 ns|
|Junction temperature|TJ|- 40|150|°C||
|Storage temperature|TS|- 55|150|°C||
|Total ICpower dissipation|PTOT|—|1|W|PG-DSO-19 / Tamb=25°C|
|Solderingtemperature|TSOLD|—|260|°C|Wave Soldering**2**|
|Latch-up capability|ILU|—|150|mA|Pin voltages acc. to abs.<br>maximum ratings**3**|
|ESD CapabilityHBM|VESD_HBM|—|2|kV|Human BodyModel**4**|
|ESD CapabilityCDM|VESD_CDM|—|500|V|Charged Device Model**5**|



## **5.3 Operating Conditions** 

The recommended operating conditions are shown for which the DC Electrical Characteristics are valid. 

## **Table 4 Operating Range** 

> 1 Limitation due to creepage distance between the high side and low side pins (CTT 900V inside) 

> 2 According to JESD22-A111 Rev A 

> 3 Latch-up capability according to JEDEC JESD78D, TA= 85°C 

> 4 ESD-HBM according to ANSI/ESDA/JEDEC JS-001-2012 

> 5 ESD-CDM according to JESD22-C101F 

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## **Electrical Characteristics** 

|**2nd Generation**<br>**Electrical Characteristics**||||||
|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Limit Values**||**Unit**|**Remarks**|
|||**Min.**|**Max.**|||
|Voltage externally supplied to pin<br>HSVCC|VHSVcc|7.9|17.5|V|Referring to HSGND|
|HSGNDpin voltage|VHSGND|- 900|900|V|Referringto GND**1**|
|External supplied VCC|VVcc|8.5|17.5|V|TJ= 25°C|
|External supplied VCC|VVcc|8.5|18.0|V|TJ= 125°C|
|LSCSpin voltage|VLSCS|- 4|5|V|In active mode|
|PFCVSpin voltage|VPFCVS|0|4|V||
|PFCCSpin voltage|VPFCCS|- 4|5|V|In active mode|
|PFCZCDpin voltage|IPFCZCD|- 3|3|mA|In active mode|
|OVPpin voltage|VOVP|0|2.5|V||
|Junction temperature|TJ|- 40|125|°C||
|Adjustable HB switching<br>frequency|fHB|20|500|kHz|@ Tj_max= 125°C / TA= - 40°C|
|HB Soft-start switchingfrequency|fHB_SS_max|-|1300|kHz|@ Soft Start|
|AC mains input frequency|fAC|45|65|Hz|For notch filter|



## **5.4 DC Electrical Characteristics** 

_Note: The electrical characteristics involve the spread of values given within the specified supply voltage and junction temperature range TJ from -40 °C to 125 °C. Typical values represent the median values, which are given in reference to 25 °C. If not otherwise stated, a supply voltage of 15 V and VHSVCC = 15 V is assumed and the IC operates in active mode. Furthermore, all voltages refer to GND if not otherwise mentioned._ 

## **5.4.1 Power Supply Characteristics** 

## **Table 5 Operating Range** 

|**Table 5**<br>**Operating Range**|||||||
|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Limit Values**|||**Unit**|**Remarks**|
|||**Min.**|**Typ. **|**Max.**|||
|Vcc Quiescent supplyCurrent 1|IVcc_QU1|—|70|120|µA|VVcc= 8.0V|
|Vcc Quiescent supplyCurrent 2|IVcc_QU2|—|4.0|5.8|mA|VPFCVS> 2.725V|
|Vcc supply current in sleep<br>mode|IVcc_sleep|—|100|160|µA||
|Vcc turn-on threshold|VVcc_On|15.4|16.0|16.6|V||
|Vcc turn-off threshold|VVcc_Off|8.5|9.0|9.5|V||
|Vcc on-off hysteresis|VVcc_Hys|6.7|7.0|7.4|V||
|Vcc internal clampingvoltage|VVcc_Clamp|15.4|16.3|16.6|V|IVcc= 2mA|
|Vcc internal clampingcurrent|IVcc_clamp|3|—|6|mA|VVcc= 18V|
|High side leakage current|IHSGND_leak|—|0.01|2.0|µA|VHSGND= 950V, VGND= 0V|



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## **ICL5102HV PFC + Resonant Half-Bridge Controller 2nd Generation** 

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## **Electrical Characteristics** 

|**2nd Generation**<br>**Electrical Characteristics**|||||||
|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Limit Values**|||**Unit**|**Remarks**|
|||**Min.**|**Typ. **|**Max.**|||
|HSVcc Quiescent supply<br>Current 1|IHSVcc_QU1|—|190|280|µA|VHSVcc= 8.0V|
|HSVcc Quiescent supply<br>Current 2|IHSVcc_QU2|—|0.65|1.2|mA|VHSVcc> VHSVcc_On|
|HSVcc turn-on threshold|VHSVcc_On|9.55|10.3|11|V|**1**|
|HSVcc turn-off threshold|VHSVcc_Off|7.9|8.6|9.3|V|**1**|
|HSVcc on-off hysteresis|VHSVcc_Hy|1.4|1.7|2.1|V|**1**|



## **5.4.2 PFC Stage Characteristics** 

## **Table 6 Electrical Characteristics of the PFCGD Pin** 

|**Parameter**|**Symbol**|**Limit Values**|**Limit Values**||**Unit**|**Remarks**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ. **|**Max.**|||
|PFCGD low voltage|VPFCGDL|0.40|0.70|0.92|V|IPFCGD= 5mA|
|||0.40|0.75|1.12|V|IPFCGD= 20mA|
|||- 0.20|0.30|0.62|V|IPFCGD= -20mA|
|PFCGD high voltage|VPFCGDH|10.0|11.0|11.6|V|IPFCGD= -20mA|
|||7.5|—|—|V|IPFCGD= -1mA/VVCC2|
|||7.0|—|—|V|IPFCGD= -5mA/VVCC1|
|PFCGD active shut down|VPFCGDLASD|0.40|0.75|1.12|V|IPFCGD= 20mA / VVCC=5V|
|PFCGD UVLO shut down|VPFCGDLUVLO|0.30|1.00|1.60|V|IPFCGD= 5mA / VVCC=2V|
|PFCGDpeak source current|IPFCGDSO|—|- 100|—|mA|3+4|
|PFCGDpeak sink current|IPFCGDSI|—|500|—|mA|2+3|
|PFCGD voltage during sink<br>current|VPFCGDHS|10.8|11.7|12.3|V|IPFCGD= 3mA|
|PFCGD rise time|tPFCGDR|125|275|580|ns|2V > VLSGD< 8V2|
|PFCGD fall time|tPFCGDF|20|45|72|ns|8V > VLSGD> 2V2|



## **Table 7 Electrical Characteristics of the PFCCS Pin** 

|**Parameter**|**Symbol**|**Limit Values**|**Limit Values**||**Unit**|**Remarks**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ. **|**Max.**|||
|PFC OCP1 comparator<br>reference voltage|VPFC_OCP1|0.95|1.0|1.05|V||



- 1 Referring to high-side ground (HSGND) 

- 2 VVcc = VVcc_off + 0.3V 

- 3 RLoad = 4Ω and CLoad = 3.3nF 

4 This parameter is no subject to production testing – verified by design / characterization Datasheet 26 of 34 

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**Electrical Characteristics** 

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|**2nd Generation**<br>**Electrical Characteristics**|||||||
|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Limit Values**|||**Unit**|**Remarks**|
|||**Min.**|**Typ. **|**Max.**|||
|PFC OCP1 blanking time (incl.<br>prorogation delay)|tPFC_OCP1_blanking|140|200|260|ns||
|Leading-edge blanking|tPFC_LEB|180|250|320|ns|Pulse width when VPFCCS<br>> 1.0V|
|PFCCSpin bias current|IPFCCSBIAS|- 0.5|—|0.5|µA|VPFCCS= 1.5V|



## **Table 8 Electrical Characteristics of the PFCZCD Pin** 

|**Parameter**|**Symbol**|**Limit Values**|**Limit Values**||**Unit**|**Remarks**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ. **|**Max.**|||
|ZCD reset threshold|VPFCZCDTHRH|1.4|1.5|1.6|V||
|ZCD threshold|VPFCZCDTHRL|0.4|0.5|0.6|V||
|ZCD hysteresis|VPFCZCDHY|—|1.0|—|V||
|Input voltage positive clamping<br>level|VPFCZCDCLAMPH|4.1|4.6|5.10|V|IPFCZCD= 2mA|
|Input voltage negative<br>clampinglevel|VPFCZCDCLAMPL|- 1.70|- 1.4|- 1.0|V|IPFCZCD=  - 2mA|
|PFCZCDpin bias current,high|IPFCZCDBIASH|- 0.5|—|5.0|µA|VPFCZCD= 1.5V|
|PFCZCDpin bias current,low|IPFCZCDBIASL|- 0.5|—|0.5|µA|VPFCZCD= 0.5V|
|Ringingsuppression-time|tPFCZCDRING|350|500|650|ns||
|Limit value for ON-time<br>extension|Δt x IZCD|400|600|670|pC||



## **Table 9 Electrical Characteristics of the PFCVS Pin** 

|**Parameter**|**Symbol**|**Limit Values**|**Limit Values**||**Unit**|**Remarks**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ. **|**Max.**|||
|PFCVSpin reference voltage|VPFCVS_ref|2.46|2.50|2.54|V||
|PFC OVP level 2 threshold (115%<br>VPFCVS_ref)|VPFCVSOV2|2.82|2.88|2.93|V|PFC and HB OFF|
|PFC OVP level 1 threshold<br>(109% VPFCVS_ref)|VPFCVSOV1|2.67|2.73|2.78|V|PFC OFF|
|PFC OVP recovery threshold<br>(105% VPFCVS_ref)|VPFCVSOVR|2.56|2.63|2.68|V||
|PFC OVP hysteresis|VPFCVSOVHY|70|100|130|mV|4 % rated bus voltage|
|PFC UVP threshold (75% VPFCVS_ref)|VPFCVSUV1|1.83|1.88|1.92|V||
|PFC open loop threshold(12.5%<br>VPFCVS_ref)|VPFCVSUV2|0.237|0.31|0.387|V||
|PFCVSpin bias current|IPFCVSBIAS|- 1.0|—|1.0|µA|VPFCVS= 2.5V|



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## **Electrical Characteristics** 

## **Table 10 PFC PWM Generation** 

|**Parameter**|**Symbol**|**Limit Values**|**Limit Values**||**Unit**|**Remarks**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ. **|**Max.**|||
|PFC initial on-time in soft-start|tPFC_on_initial|1.75|6.0|10.64|µs|VPFCZCD= 0V, VBO= 2.0V|
|PFC maximum on-time|tPFC_on_max|17|22|26|µs|VACIN= 90V|
|PFC minimum on-time in CrCM<br>operation|tPFC_on_min|100|220|370|ns||
|PFC repetition-time|tPFC_rep|47|52|60|µs|VPFCZCD= 0V|
|PFC maximum off-time|tPFC_off|42|47|52.5|µs||



## **5.4.3 HB Stage Characteristics** 

## **Table 11 Electrical Characteristics of the LSGD Pin** 

|**Parameter**|**Symbol**|**Limit Values**|**Limit Values**||**Unit**|**Remarks**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ. **|**Max.**|||
|LSGD low voltage|VLSGDL|0.40|0.70|1.00|V|ILSGD= 5 mA|
|||0.40|0.80|1.20|V|ILSGD= 20 mA|
|||- 0.30|0.20|0.53|V|ILSGD= - 20 mA|
|LSGD high voltage|VLSGDH|10.0|10.8|11.6|V|ILSGD= - 20 mA|
|||7.5|—|—|V|ILSGD= –1 mA1|
|||7.0|—|—|V|ILSGD= –5 mA2|
|LSGD active shut down|VLSGDLASD|0.4|0.75|1.12|V|ILSGD= 20 mA / VCC= 5V|
|LSGD UVLO shut down|VLSGDLUVLO|0.3|1.0|1.6|V|ILSGD= 5 mA / VCC= 2 V|
|LSGDpeak source current|ILSGDSO|—|- 50|—|mA|**2 +3**|
|LSGDpeak sink current|ILSGDSI|—|300|—|mA|**1 + 2**|
|LSGD voltage during sink<br>current|VLSGDHS|—|11.7|—|V|ILSGD= 3 mA|
|LSGD rise time|tLSGDR|125|275|580|ns|2 V < VLSGD< 8 V1|
|LSGD fall time|tLSGDF|20|35|60|ns|8 V > VLSGD> 2 V1|



## **Table 12 Electrical Characteristics of the LSCS Pin** 

|**Parameter**|**Symbol**|**Limit Values**|**Limit Values**||**Unit**|**Remarks**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ. **|**Max.**|||
|HB over-current protection<br>level 2|VHB_OCP2|1.54|1.6|1.66|V||



1 VCC = VCCOFF + 0.3 V 

2 Load: RLoad = 10 Ω and CLoad = 1 nF 

3 The parameter is not subject to production testing – verified by design/characterization Datasheet 28 of 34 

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**Electrical Characteristics** 

**==> picture [103 x 46] intentionally omitted <==**

|**2nd Generation**<br>**Electrical Characteristics**|||||||
|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Limit Values**|||**Unit**|**Remarks**|
|||**Min.**|**Typ. **|**Max.**|||
|Blanking time for HB over-<br>currentprotection level 2|tHB_OCP2_blanking|430|600|670|ns||
|HB over-current protection<br>level 1|VHB_OCP1|0.74|0.8|0.86|V||
|Blanking time for HB over-<br>currentprotection level 1|tHB_OCP1_blanking|—|50|—|ms|**1**|
|HB capacitive mode detection<br>level 1|VHB_Cap1|1.54|1.6|1.66|V|during turn-on of the<br>HSGD|
|Blanking time for HB capacitive<br>mode detection level 1|tHB_Cap1_blanking|30|50|90|ns||
|HB capacitive mode detection<br>level 2|VHB_Cap2|- 70|- 50|- 25|mV|before turn-on of the<br>HSGD|
|Blanking time for HB capacitive<br>mode detection level 2|tHB_Cap2_blanking|300|390|550|ns||
|HB capacitive mode regulation<br>voltage|VHB_cap_reg|25|50|70|mV||
|HB capacitive mode regulation<br>ratio|KHB_cap_reg|4.5|7.0|9.0|%||
|HB over-current control|VLSCSCC|0.74|0.8|0.86|V||
|LSCSpin bias current|ILSCSBA|-1.0|—|1.0|µA|VLSCS= 1.5 V|



|**Table 13**<br>**Electrical Characteristics of the HSGD Pin**|**Table 13**<br>**Electrical Characteristics of the HSGD Pin**|**Table 13**<br>**Electrical Characteristics of the HSGD Pin**|**Table 13**<br>**Electrical Characteristics of the HSGD Pin**||||
|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Limit Values**|||**Unit**|**Remarks**|
|||**Min.**|**Typ. **|**Max.**|||
|HSGD low voltage|VHSGDL|0.018|0.05|0.1|V|IHSGD= 5mA|
|||0.40|1.10|2.50|V|IHSGD= 100mA|
|||- 0.40|-0.20|- 0.04|V|IHSGD= - 20mA|
|HSGD high voltage|VHSGDH|9.7|10.5|11.3|V|VCC_HS=15V|
|||7.8|—|—|V|IHSGD= - 20mA|
|HSGD active shut down|VHSGDLASD|0.04|0.22|0.50|V|VCC_HS_OFF+ 0.3V|
|HSGDpeak source current|IHSGDSO|—|- 50|—|V|IHSGD= - 1mA**1**|
|HSGDpeak sink current|IHSGDSI|—|300|—|V|VCC_HS=5V1|
|HSGD rise time|tHSGDR|120|220|320|ns|IHSGD= 20mA|
|HSGD fall time|tHSGDF|17|35|70|ns|RLoad= 10Ω+CLoad= 1nF|



## **Table 14 Electrical Characteristics of the RF Pin** 

1 The parameter is not subject to Production Test – verified by Design / Characterization Datasheet 29 of 34 

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## **Electrical Characteristics** 

|**2nd Generation**<br>**Electrical Characteristics**|||||||
|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Limit Values**|||**Unit**|**Remarks**|
|||**Min.**|**Typ. **|**Max.**|||
|RF pin voltage in normal<br>operation|VRF|2.46|2.5|2.54|V|@ 100µA < IRFM< 800µA|
|HB nominal switching<br>frequency|fNOM|97.5|100|102.5|kHz|RRF= 10kΩ without the<br>resistor to BMpin|
|Adjustable HB switching<br>frequency via the CCO|f1|37|40|43|kHz|IRF= - 100µA|
||f2|76|80|84|kHz|IRF= - 200µA|
||f3|190|200|210|kHz|IRF= - 500µA|
||f4|220|240|260|kHz|IRF= - 600µA|
||f5|290|320|350|kHz|IRF= - 800µA|
||fmax-25°C|450|500|-|kHz|IRF= - 1.25 mA  / @ Tj= -<br>25°C**1**|
||fmax-40°C|400|500|-|kHz|IRF= - 1.25 mA  / @ Tj= -<br>40°C**1**|



## **Table 15 Electrical Characteristics of the BM Pin** 

|**Parameter**|**Symbol**|**Limit Values**|**Limit Values**||**Unit**|**Remarks**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ. **|**Max.**|||
|HB burst mode entry voltage<br>threshold|VHB_BM_entry|710|750|790|mV||
|Blanking time for HB burst<br>mode entry|tHB_BM_entry_blanking|8.5|10.0|11.5|ms||
|HB burst mode turn-on<br>threshold|VHB_BM_on|2.13|2.20|2.27|V||
|HB burst mode exit threshold|VHB_BM_exit|1.93|2.0|2.07|V||
|Maximum sink current into<br>the BMpin|IBM_max||800||µA||
|BM pin current in the sleep<br>mode|IBM_Stop|-3|—|14|µA||



## **Table 16 Electrical Characteristics of the BO Pin** 

|**Parameter**|**Symbol**|**Limit Values**|**Limit Values**||**Unit**|**Remarks**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ. **|**Max.**|||
|Brown-out threshold|VBO_out|1.14|1.2|1.26|V||
|Brown-in threshold|VBO_in|1.34|1.4|1.46|V||
|BOpin bias current|IBOBA|-0.5|—|0.5|µA|VBO= 5.0V|



## **Table 17 Electrical Characteristics of the OVP Pin** 

> 1 Make sure, that the expected ambient temperature does NOT cause a maximum junction temperature higher than 125°C 

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## **Electrical Characteristics** 

|**2nd Generation**<br>**Electrical Characteristics**|||||||
|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Limit Values**|||**Unit**|**Remarks**|
|||**Min.**|**Typ. **|**Max.**|||
|HB OVP pin reference voltage<br>for OVP detection|VHB_OVP_ref|2.45|2.5|2.55|V|t > 5µs|
|Blanking time for HB OVP<br>detection|tHB_OVP_blanking|—|5|—|µs||
|OVPpin bias current|IOVPBA|- 0.5|—|0.5|µA|VOVP= 3.0V|



## **Table 18 Electrical Characteristics of the OTP Pin** 

|**Parameter**|**Symbol**|**Limit Values**|**Limit Values**||**Unit**|**Remarks**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ. **|**Max.**|||
|OTP turn-on threshold|VOTP_start|670|703|735|mV||
|OTP turn-off threshold|VOTP_off|594|625|665|mV||
|Blanking time for OTP<br>detection|tOTP_blanking|—|620|—|µs||
|OTP pin source current in<br>normal operation|IOTP|- 106|- 100|- 94|µA||



## **Table 19 Time Section** 

|**Table 19**<br>**Time Section**|||||||
|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Limit Values**|||**Unit**|**Remarks**|
|||**Min.**|**Typ. **|**Max.**|||
|HB maximum dead time 1|tDead_max1|550|750|930|ns|LSCS > - 50mV / 100kHz|
|HB maximum dead time 2|tDead_max2|350|500|600|ns|LSCS > - 50mV / 500kHz|
|HB minimum dead time|tDead_min|150|250|300|ns|LSCS < - 50mV / 500kHz|



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## **Package Dimensions** 

## **6 Package Dimensions** 

The package dimensions of PG-DSO-19 are provided. 

## **Figure 24 Package Dimensions for PG-DSO-19** 

_Note: Dimensions in mm._ 

_Note: You can find all of our packages, packing types and other package information on our Infineon internet page “Products”: http://www.infineon.com/products._ 

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## **ICL5102HV PFC + Resonant Half-Bridge Controller 2nd Generation Revision history** 

**==> picture [103 x 46] intentionally omitted <==**

## **Revision history** 

|**Document**<br>**version**|**Date of release**|**Description of changes**|
|---|---|---|
|V1.2|01.04.2019|Errors correction and content modification|
|V1.1|09.11.2018|Errors correction and content modification|
|V1.0|01.06.2018|First release|



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## **Trademarks** 

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