HVLED101TR

**HVLED101** 

Datasheet 

## Advanced high power factor flyback controller with valley locking and maximum power control 

## **Features** 

- Quasi-Resonant (QR) topology 

- Primary side regulation of output voltage 

- Direct optocoupler connection for secondary side regulated loop 

- High power factor and low THD in universal and extended range (PF> 0.9 and THD < 5% @ full load and < 10% @ 1/3 load) 

- 800 V fast high-voltage startup 

- Extremely low input power at no-load and standby conditions 

- Integrated input voltage detection for high power factor capabilty, DC rail detection and protection triggering 

- Programmable frequency foldback with valley locking for noise free operation 

## **Product status link** 

HVLED101 

- Programmable maximum input power limitation for safety standard compliancy 

- Programmable brownout and input overvoltage protection 

- Latch-free device guarantee by smart Auto Restart Timer (ART) 

|**Product summary**|**Product summary**|**Product summary**|
|---|---|---|
|**Order code**|**Package**|**Packaging**|
|HVLED101|SOP14|Tube|
|HVLED101TR||Tape and reel|



- Input pin for remote protection with NTC management (threshold hysteresis and linearization) 

## **Application** 

- Single-stage LED drivers with high power factor up to 180 W 

- Two-stage LED drivers up to 200 W 

## **Description** 

The HVLED101 is an enhanced peak current mode controller able to control mainly high power factor (HPF) flyback or buck-boost topologies having an output power up to 180 W. Some other topologies, like buck, boost and SEPIC could also be implemented. Primary Side Regulation of output voltage and Optocoupler control can be applied independently on the chip both exploiting precise regulation and very low standby power during no-load conditions. The innovative ST high-voltage technology allows to directly connect the HVLED101 to the input voltage in order to both start up the device and monitor the input voltage without the need of external components. Integrated valley locking feature guarantees noise free operation during medium and low load operation and maximum power control allows limiting the input power to a level programmable by the user to increase converter safety. Abnormal conditions like open circuit, output short-circuit, input overvoltage or undervoltage, external protection circuitries and circuit failures like open loop and overcurrent of the main switch are effectively controlled. A smart Auto Restart Timer (ART) function is built in to guarantee an automatic application recover, without any loss of reliability. 

**DS14143** - **Rev 2** - **December 2022** For further information contact your local STMicroelectronics sales office. 

www.st.com 

**HVLED101 Block diagram** 

**1 Block diagram** 

**Figure 1. Block diagram** 

**==> picture [455 x 259] intentionally omitted <==**

**----- Start of picture text -----**<br>
HVSU NC VCC PGND CS<br>CFG [1…5] CFG DLY/CFG<br>Icharge KHVCFG<br>CS pin DC Det CFG<br>BO CFG<br>iOVP CFG LEB iOVPCFG Delay<br>UVLO UVLO Generator<br>Logic<br>iOVP iOVP Dly_on<br>BO CFG<br>HV-StUpBO BO OPTO_BMPSR_BMFAULTUVPBO Operational LogicMode SelectionProtections OCPRamp-up2 [nd] OC P VCS_TH PWM Comp& Latch SR Q MOSFET DRIVER GD<br>iOVP PSR_BM Limiter<br>Turn On Logic ZCD<br>Vpk<br>PkDet THD<br>(FB, OPTO)MIN  FBint MULT Optim FSW-RU Valley Lock + DCM<br>AC/DC  NDC MPC MPC MIN  FBint IVLBIAS VL<br>Detect Block (FBint, MPC)<br>KHV CFG ROPTO IOPTO CS pin VFF_TPD<br>UVP UVP<br>DC Det CFG<br>PSR E/A Demag Logic<br>OTA S&H<br>VBM VREF_PSR VBM<br>PSR_BM OPTO_BM FAULT Fault Bias & COMP FAULT<br>FB OPTO THD SGND<br>**----- End of picture text -----**<br>


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**HVLED101 Typical applications** 

**2 Typical applications** 

**Figure 2. HVLED101 typical PSR application** 

**==> picture [426 x 237] intentionally omitted <==**

**----- Start of picture text -----**<br>
DSec<br>Vin BR1 Cin Ccl Rcl Cout Rmin Out<br>Dcl<br>Dvcc<br>HVSU VCC RFB<br>ZCD<br>DLY/CFG<br>FAULT RGD<br>FB HVLED101 GD<br>CS DGD M1<br>VL<br>SGND THD OPTO PGND<br>RFF<br>RVL RCS<br>1k<br>ZCD<br>R<br>VCC<br>C<br>DLY<br>R PSR,s<br>R PSR,p<br>C<br>CFG<br>C NTC CPSR,s CVL CTHD COPTO<br>**----- End of picture text -----**<br>


**Figure 3. HVLED101 typical SSR application** 

**==> picture [454 x 246] intentionally omitted <==**

**----- Start of picture text -----**<br>
DSec<br>Vin BR1 Cin Ccl Rcl Out<br>Cout Rmin<br>Dcl<br>Rshunt<br>Dvcc<br>VccS<br>HVSU VCC RFB<br>ZCD<br>DLY/CFG R1_CC<br>FAULT RGD<br>FB HVLED101 GD Rbias<br>CS DGD<br>VL R2_CC C2_CC<br>SGND THD OPTO PGND CV-Rup<br>RFF M1<br>OC1<br>RVL RCS Vref_CC<br>Vref_CV<br>R2_CV C2_CV<br>CV-Rdw<br>1k<br>ZCD<br>R<br>VCC<br>C<br>DLY<br>R<br>FB<br>C<br>CFG<br>C NTC CVL CTHD CSSR<br>**----- End of picture text -----**<br>


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**HVLED101 Pin Settings** 

**3** 

## **Pin Settings** 

**Figure 4. Device pinout** 

**==> picture [290 x 219] intentionally omitted <==**

**----- Start of picture text -----**<br>
HVSU 1 14 VCC<br>N.C. 2 13 GD<br>FAULT 3 PGND<br>12<br>DLY/CFG 4 11 CS<br>VL 5 10 ZCD<br>FB 6 9 SGND<br>OPTO 7 8 THD<br>**----- End of picture text -----**<br>


**Table 1. Pin description** 

|**Symbol**|**Pin**|**Description**|
|---|---|---|
|HVSU|1|High-voltage startup and input voltage detection.<br>The pin, able to withstand 800 V, is to be connected to either the DC side of the input rectifier bridge, using a<br>low value resistor (1 kΩ typ), or the AC side of a rectifier bridge with two diodes.<br>It embeds the internal startup unit that quickly charges the capacitor connected between VCC pin and PGND<br>pin during startup and low consumption.<br>During operational mode, this pin measures the input voltage to obtain high power factor and to detect both<br>input overvoltage and undervoltage, according to protection configuration, selected on the DLY/CFG pin.|
|N.C.|2|Not connected pin for clearance.|
|FAULT|3|This pin is intended to stop the IC when either the voltage goes below an internal threshold or the pin is left<br>floating.<br>It is suitable to supply an NTC thermistor. The hysteresis of lower disable threshold results in a thermal<br>hysteresis when NTC is connected. When the functionality is unused, connect a 33 kΩ resistor between<br>FAULT pin and SGND.|
|DLY/CFG|4|The parallel of a resistor and a capacitor is connected between this pin and SGND pin: the value of the<br>resistance sets the delay time between ZCD detection and MOSFET turn-on, while the time constant of the<br>RC network selects the input detection configuration and protection. Recommended values ranges are 22 ÷<br>560 kΩ for R and 10 pF ÷ 100 nF for C.|
|VL|5|The voltage applied to this pin controls valley locking and frequency fold-back operation. It is internally biased<br>with a current that is proportional to the minimum between the voltages that are present at the FB pin and<br>at the OPTO pin (the internal FBintsignal). The level of the frequency fold-back depth is set by a resistor<br>connected to SGND. A capacitor between the VL pin and SGND can be used to filter the fluctuations of FBint<br>signal.|
|FB|6|Output of the primary side regulation error amplifier (OTA).<br>The pin must be connected to the compensation network for Primary Side Regulation.<br>The voltage present at this pin also controls adaptive burst-mode (deep low consumption mode) and is<br>internally connected to the multiplier, together with OPTO pin voltage and MCP voltage in an “OR-ed”<br>structure.|



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**HVLED101 Pin Settings** 

|**Symbol**|**Pin**|**Description**|
|---|---|---|
|OPTO|7|This pin is intended to be directly connected to the collector of the optocoupler or to the output of the error<br>amplifier of a non-isolated topology: a pull-up current together with gain resistance is embedded in this pin.<br>The OPTO pin voltage is internally connected to the multiplier, together with FB pin voltage and MCP voltage<br>in an “OR-ed” structure.<br>Deep low consumption mode is invoked pulling this pin lower than the VBMthreshold that features as<br>burst-mode level when OPTO is used.|
|THD|8|A ceramic capacitor is placed between this pin and SGND to set the time constant of the THD optimizer unit.<br>It is strongly recommended to use small package ceramic capacitors, placed as close to the above mentioned<br>pins as possible, to avoid any undesired noise injection.|
|SGND|9|Reference pin for signal’s ground potential.|
|ZCD|10|Multiple function pin able to detect the zero current instant, to sense the output voltage for primary side<br>regulation (PSR) and to compensate the peak current detection propagation delay (VFF).<br>The delay time between zero current instant detection and MOSFET turn-on is programmed by the resistance<br>between DLY/CFG pin and SGND.<br>An internal starter unit is active to generate the triggering signal when not externally available (for example, at<br>startup).<br>Valley skipping counter is fed by internal ZCD signal processor.<br>Adaptive minimum turn-off time (for example, the blanking after turn-on), larger during UVP condition, is<br>implemented.|
|CS|11|Input of the current sense comparator for the power regulation.<br>The current sense resistor (RCS, from primary MOSFET source to ground) must be connected to this pin<br>through a series resistance (RFF): this resistor is fed by an internal current, proportional to ZCD pin current<br>during MOSFET on time interval, that creates the offset to compensate for the PWM comparator propagation<br>delay.<br>A leading-edge blanking time avoids false triggering of the MOSFET’s turn-off due to the noise that may be<br>generated after gate driver turn-on.|
|PGND|12|Reference pin for VCC and gate driver.|
|GD|13|Gate driver output.<br>The output stage is suitable to directly drive power MOSFETs.<br>An internal pulldown resistor aims to keep the MOSFET off during low power operating modes.|
|VCC|14|Supply voltage of the IC.<br>Internal UVLO logic prevents the operation at voltages that are insufficient for an efficient gate driving or<br>internal signal processing.<br>Both a bulk capacitor (typically around 22 µF) and a high frequency filter capacitor (100 nF ceramic, mounted<br>as close to the device as possible) should be connected between this pin and PGND.|



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**HVLED101 Electrical data** 

**4 Electrical data** 

## **4.1 Absolute maximum ratings** 

**Table 2. Absolute maximum ratings** 

|**Symbol**|**Pin**|**Parameter**|**Test condition**|**Value**|**Unit**|
|---|---|---|---|---|---|
|VHVSU_MAX|HVSU|HVSU maximum voltage|IHVSU< 100 µA,<br>VCC= 15 V|800|V|
|VHVSU_neg|HVSU|HVSU negative voltage||-0.3|V|
|VCC_MAX|VCC|IC supply voltage||20|V|
|VGD|GD|Maximum swing voltage||VCC+ 0.3|V|
|VCS|CS|Current sense applied voltage||7|V|
|VZCD|ZCD|Max. ZCD voltage||Self-limited||
|IZCD_sink|ZCD|Max. ZCD pin entering current||1|mA|
|IZCD_source|ZCD|Max. ZCD pin exiting current||6|mA|
|VNEG|CS, FB, OPTO, FAULT, VL,<br>DLY/CFG, THD|Maximum negative voltage||-0.3|V|
|VPOS|FB, OPTO, FAULT, VL,<br>DLY/CFG, THD|Maximum positive voltage||3.6|V|
|VGND_D|SGND, PGND|Maximum voltage difference between PGND<br>and SGND||+/- 0.3|V|



Where not otherwise indicated the AMRs are intended applied when VCC > VCCon. When VCC < VCCon, the minimum between the indicated value and VCC+0.3 V must be considered. 

_Stressing the device above the rating listed in the above table may cause permanent damage to the device. Exposure to absolute maximum rated conditions may affect device reliability._ 

## **4.2 ESD immunity levels** 

**Table 3. ESD immunity levels** 

|**Mode**|**Pin**|**Reference Specification**|**Value**|**Unit**|
|---|---|---|---|---|
|HBM|All|According to JS001|±1.75|kV|
|CDM|All|According to JES002|±500|V|



## **4.3** 

## **Thermal data** 

**Table 4. Thermal data** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|Rth_JA|Thermal resistance junction to ambient|120|°C/W|
|TJ|Junction temperature operating range|-40 to 125|°C|
|Tstg|Storage temperature range|-55 to 150|°C|



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**HVLED101 Recommended operating conditions** 

## **4.4 Recommended operating conditions** 

**Table 5. Recommended operating conditions** 

|**Symbol**|**Parameter**|**Min.**|**Max. **|**Unit**|**Remarks**|
|---|---|---|---|---|---|
|VCC|VCCsupply voltage|VCC-OFF|19|V|After device turn-on|
|VHV_op_1|HVSU voltage range CFG1, CFG3, CFG5|0|480|V|Linearity not guaranteed above 480 V|
|VHV_op_2|HVSU voltage range CFG2, CFG4|0|760|V|Linearity not guaranteed if VPKis lower than<br>200 V|
|VFB|FB pin regulation voltage range|0.3|2.8|V||
|VOPTO|OPTO pin regulation voltage range|VBM|2.8|V||
|VCS_op|CS pin operative condition|0|1.2|V||
|VZCD|ZCD pin operative voltage|Self-limited|3.3|V|DC condition, Isource< 1 mA RZCD= 22 kΩ to<br>47 kΩ|
|IZCD_src|ZCD pin operative source current|0|3|mA|During on-time|
|IZCD_snk|ZCD pin operative sink current|0|1|mA|During off-time|
|VVL|VL pin operative voltage|0|3.0|V||
|VFAULT|FAULT pin operating range|0|3.3|V||



**DS14143** - **Rev 2** 

**page 7/36** 

**HVLED101 Electrical characteristics** 

## **5 Electrical characteristics** 

(TJ = -40 °C to 125 °C, 25 °C production tested, VCC = 16 V, SGND = PGND = 0 V, unless otherwise specified.) 

**Table 6. Electrical characteristics** 

|**Symbol**|**Pin/Block**|**Parameter**|**Test condition**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|---|
|**Supply voltage**||||||||
|VCC-ON|VCC|Turn-on threshold|VHVSU> VHV-START[TrackVCC]|13|14|15|V|
|VCC-OFF|VCC|Low consumption<br>mode activation|Active mode [TrackVCC]|7.4|7.8|8.2|V|
|VCC-LOW|VCC|VCCfor HVSU high<br>current activation||||1.5|V|
|VCC-SHD|VCC|VCCfor IC reset|Low consumption|6.5||7.4|V|
|**Supply current**||||||||
|ICC-START-UP|VCC|Startup current|Startup, VCC= 12 V|||270|μA|
|ICC|VCC|Operating supply<br>current|fSW= 25 kHz, CGD= 1 nF||5.4|6|mA|
|ICC-LC|VCC|Protection VCC<br>supply current|OCP, brownout, or iOVP|||510|μA|
|ICC-OPTO-BM|VCC|OPTO burst-mode<br>VCC current|OPTO = 0 V, FAULT active, DLY/CFG<br>active RDLY= 120 kΩ|||610|μA|
|ICC-PSR-BM|VCC|PSR burst-mode<br>VCC current|FB = 0 V, OPTO unbiased, FAULT<br>active, DLY/CFG active RDLY= 120<br>kΩ|||500|μA|
|**High-voltage startup generator**||||||||
|VHV-START|HVSU|Start voltage|IVcc< 100 μA|||20|V|
|ICHG-H|VCC|VCCcharging<br>current|VHVSU> VHV-START, startup, VCC= 13<br>V|5|||mA|
|ICHG-L|VCC|VCCcharging<br>current during iOVP<br>or at low VCC|VHVSU> VHV-START, iOVP on<br>OR VCC< VCC-LOW|1.2|||mA|
|IHV-ON|HVSU|HVSU on-state<br>current|VHVSU> VHV-START, startup, VCC= 13<br>V|5|||mA|
|IBLEED|HVSU|HVSU discharging<br>current during iOVP|VHVSU> VHV-START, iOVP on, CFG1,<br>CFG3, VCC< 18 V|1.55||||
|IHV-LKG|HVSU|HVSU off-state<br>leakage current|VHVSU= 400 V, active mode||17|25|μA|
|**Input voltage sensing**||||||||
|ViOVP|HVSU|Input overvoltage<br>protection threshold|CFG1, CFG3, or CFG5|530|555|580|V|
|VBO-L|HVSU|Brownout threshold<br>(instantaneous<br>voltage)|CFG1, CFG4, or CFG5|94|105|116|V|
|VBO-H|HVSU||CFG3|170|190|210|V|
|TBO|HVSU|Brownout activation<br>time|CFG1, CFG3, CFG4, or CFG5|500|835|1180|ms|
|TBO-LEB|HVSU|Blanking time after<br>brownout activation|CFG1, CFG3, CFG4, or CFG5|150|250|350|ms|
|TDBNC|HVSU|Brownout<br>debounce time|CFG1, CFG3, CFG4, or CFG5|0.78|1.25|1.72|ms|



**DS14143** - **Rev 2** 

**page 8/36** 

**HVLED101 Electrical characteristics** 

|**Symbol**|**Pin/Block**|**Parameter**|**Test condition**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|---|
|KHV-LV|HVSU|Internal voltage<br>divider ratio|VHVSU-pk< 480V, CFG1, CFG3 or<br>CFG5||4.65||mV/V|
|KHV-HV|HVSU||VHVSU-pk> 150V, CFG2, or CFG4||2.91||mV/V|
|VDC-DET-L|HVSU|DC voltage<br>detection level|CFG1, CFG2, CFG4, or CFG5|94|105|116|V|
|VDC-DET-H|HVSU||CFG3|170|190|210|V|
|TDC-DET|HVSU|DC voltage<br>detection time||30|50|70|ms|
|**Feedback input and multiplier**||||||||
|VOS|FB, OPTO|FB or OPTO offset<br>voltage|Active mode [TrackFB]|0.45|0.5|0.55|V|
|KM|FB, OPTO|Multiplier gain|Active mode||0.176||V/V|
|KMPC|FB, OPTO|Scaling factor<br>for MPC level<br>calculation|||270||V2|
|VBM|FB, OPTO|Burst-mode<br>threshold|Active mode, falling [TrackFB]||0.6||V|
|VBM_HYST|FB, OPTO|Burst-mode<br>hysteresis|Low consumption, rising||50||mV|
|TREP|FB|PSR burst-mode<br>repetition rate|VFB= 0.6 V||0.4||ms|
||||VFB= 0.3 V|2.6|4|5.4|ms|
|RTHD|THD|THD optimizer<br>internal resistance|On time running||22||kΩ|
|**PSR OTA**||||||||
|VREF-PSR|FB|PSR loop reference|TAMB= 25 °C|2.55|2.6|2.65|V|
||||Over all temperature range|2.5|2.6|2.7|V|
|gm|OTA|Transconductance|ΔIFB= ±10 μA, VFB= 1.65 V|1.3|2.3|3.2|mS|
|GV-dB|OTA|Voltage gain|Open loop||75||dB|
|GBWP|OTA|Gain-bandwidth<br>product|||360||kHz|
|IFB-SRC|FB – OTA|FB pin pull-up<br>current (OTA)|Active mode, VZCD, off = 2.0 V,<br>VFB= 1.65 V||2||mA|
|IFB-SNK|FB – OTA|FB pin pull-down<br>current (OTA)|Active mode, VZCD, off = 3.2 V,<br>VFB= 1.65 V||2||mA|
|VUVP|FB|Undervoltage<br>protection level|[TRACKZCD]|0.35|0.4|0.45|V|
|TUVP|FB|Maximum<br>undervoltage<br>protection time||60|100|140|ms|
|**OPTO input**||||||||
|VOPTO-BIAS|OPTO|OPTO biasing<br>voltage|Whole temperature range|2.8|||V|
|IOPTO-BIAS|OPTO|OPTO biasing<br>current|VOPTO= 0 V|120|150|180|µA|
|ROPTO|OPTO|Internal parallel<br>resistor||40|52|65|kΩ|



**DS14143** - **Rev 2** 

**page 9/36** 

**HVLED101 Electrical characteristics** 

|**Symbol**|**Pin/Block**|**Parameter**|**Test condition**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|---|
|TOPTO-TRIG|OPTO|Minimum pulse<br>duration to exit<br>from ramp-up<br>phase||||10.5|µs|
|**Current sense input**||||||||
|VCS-MIN|CS|Current sense<br>minimum level<br>during burst-mode|VFB< VBM|25|50|80|mV|
|VCS-RU|CS|Current sense level<br>during ramp-up|During fixed frequency ramp-up<br>phase|170|200|230|mV|
|TLEB|CS|Leading edge<br>blanking||230|300|390|ns|
|VOCP2|CS|Saturation<br>protection threshold<br>(2ndOCP)|During on-time [TrackCS]|1.2|1.3|1.4|V|
|VOCP1|CS|Cycle-by-cycle<br>current sense limit<br>(1stOCP)|During on-time [TrackCS]|0.837|0.9|0.963|V|
|TOCP|CS|Max. stop state<br>duration after 2nd<br>OCP|Tpulse = 1 µs, amplitude 2 V|0.72|1.04|1.41|ms|
|TPD|CS|Propagation to<br>output of current<br>sense detection|On time running, dV/dt = 0.141 V/us||80||ns|
|KFF|CS, ZCD|Current gain<br>between ZCD<br>source current and<br>CS pin source<br>current|On time running, IZCD= 0 to 3 mA||75||µA/mA|
|**ZCD input**||||||||
|VZCD-TRIG|ZCD|ZCD triggering<br>threshold|Negative going edge [TRACKZCD]|0.16|0.2|0.26|V|
|VZCD-ARM|ZCD|ZCD arming<br>threshold|Positive going edge [TRACKZCD]|0.24|0.3|0.39|V|
|TBLANK|ZCD|ZCD minimum<br>blanking time|From MOSFET turn-off,<br>with PSR S&H > VUVP|0.97|1.5|2.1|µs|
||||From MOSFET turn-off,<br>with PSR S&H < VUVP|3.3|5.5|7.7|µs|
|TDLY-MIN|DLY/CFG|ZCD trigger to GD<br>on min. delay|RDLY= 120 kΩ||355||ns|
|TDLY-MAX|DLY/CFG|ZCD trigger to GD<br>on max. delay|RDLY= 270 kΩ||675||ns|
|TWAIT-MIN|ZCD|ZCD waiting time<br>after TBLANKelapse|Starting from ZCD trigger, RDLY= 120<br>kΩ [track TDLY]||2.2||µs|
|TWAIT-MAX|ZCD||Starting from ZCD trigger, RDLY= 2.7<br>kΩ [track TDLY]||4.8||µs|
|VZCD-CLP-low|ZCD|ZCD negative<br>clamping voltage|IZCDsource = 3 mA|-250|||mV|
|IZCD-Bias|ZCD|ZCD pin biasing<br>current|VZCD= 2.7 V|||1|µA|
|VZCD-max|ZCD|ZCD pin max.<br>positive voltage|IZCDsink = 1mA|3|||V|



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**HVLED101 Electrical characteristics** 

|**Symbol**|**Pin/Block**|**Parameter**|**Test condition**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|---|
|**Timing**||||||||
|TART||Auto-restart time||1.5|2.5|3.5|s|
|FSW-RU||Ramp-up operating<br>frequency||15|25|35|kHz|
|δMAX-RU||Max. Duty cycle<br>during ramp-up||40|50|60|%|
|TCF||Maximum duration<br>of ramp-up phase||120|200|280|ms|
|**FAULT pin characteristics**||||||||
|VFLT-OFF|FAULT|FAULT pin disable<br>threshold|Falling edge [trackFLT]|740|800|860|mV|
|VFLT-ON|FAULT|FAULT pin enable<br>threshold|Rising edge [trackFLT]|790|850|910|mV|
|IFLT-BIAS|FAULT|FAULT pin biasing<br>current|FAULT = GND|45|50|55|µA|
|VFLT-OPEN|FAULT|FAULT pin open<br>detection voltage|Active mode|2.6|2.7|2.8|V|
|**Gate driver**||||||||
|VGDH|GD|Output high voltage|IGDsource = 5 mA|15.5|||V|
|VGDL|GD|Output low voltage|IGDsink = 5 mA|||0.1|V|
|ISRC|GD|Output source peak<br>current|Max. value [not tested in production]|0.48|0.6||A|
|ISNK|GD|Output sink peak<br>current|Max. value [not tested in production]|0.83|1.2||A|
|TF|GD|Fall time|CGD= 1 nF, from 14.5 V to 1.5 V||15||ns|
|TR|GD|Rise time|CGD= 1 nF, from 1.5 V to 14.5 V||30||ns|
|RP-DWN|GD|Gate driver pull-<br>down resistor|||80||kΩ|
|**VL pin characteristics**||||||||
|VVL-BIAS|VL|Saturation voltage|VL = open, VFB= 3V, VOPTO= 2.8V<br>[TrackVL]|2.8|||V|
|IVL-P-UP|VL|Pull-up current|VVL= 0 V, VFB= 3 V, VOPTO= 1 V<br>[TrackVL]||10||µA|
||||VVL= 0 V, VFB= 3 V, VOPTO= 2 V<br>[TrackVL]||20||µA|
|VL1H|VL|Hysteresis level for<br>VL1|||1.9||V|
|VL1|VL|QR to 2ndvalley<br>threshold|||1.7||V|
|VL2H|VL|Hysteresis level for<br>VL2|||1.5||V|
|VL2|VL|2ndto 3rdvalley<br>threshold|||1.3||V|
|VL3|VL|3rdto 4thvalley<br>threshold|||1.2||V|
|VL4|VL|4thto 5thvalley<br>threshold|||1.1||V|



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**HVLED101 Electrical characteristics** 

|**Symbol**|**Pin/Block**|**Parameter**|**Test condition**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|---|
|VL5|VL|5thto 6thvalley<br>threshold|||1||V|
|VDCM|VL|Unlocked operation<br>limit|||0.86||V|
|KDCM|VL|DCM characteristic<br>slope|||-130||µs / V|
|TDCM-MAX|VL|Max. DCM time<br>with linearity<br>guaranteed|VL = 0.3V||70||µs|
|**DLY/CFG pin characteristics**||||||||
|VDLY-BIAS|DLY/CFG|DLY pin Bias<br>voltage|Active mode [TrackCFG]||1.5||V|
|KDLY|DLY/CFG|ZCD to GD on gain|||2.13||ns/kΩ|
|VCFG-L|DLY/CFG|Decay hysteresis<br>for CFG selection|[TrackCFG]||0.5||V|
|TauCFG1|DLY/CFG|Time constant to<br>set CFG1||30||45|µs|
|TauCFG2|DLY/CFG|Time constant to<br>set CFG2||100||140|µs|
|TauCFG3|DLY/CFG|Time constant to<br>set CFG3||300||410|µs|
|TauCFG4|DLY/CFG|Time constant to<br>set CFG4||860||1200|µs|
|TauCFG5|DLY/CFG|Time constant to<br>set CFG5||2050||TBD|µs|



**DS14143** - **Rev 2** 

**page 12/36** 

**HVLED101 Application information** 

## **6 Application information** 

## **6.1 Typical application** 

The HVLED101 high power factor flyback controller is suitable to operate either as a single-stage high power factor (HPF) flyback controller or as a DC/DC flyback controller in a two-stage application with front-end PFC converter. The control can be primary side (PSR) or secondary side (SSR). Application schematics of the two control types are reported in Figure 2 and Figure 3. 

## **6.2** 

## **Operating modes** 

The IC presents various operating modes, described in the following sections. Figure 5 shows the operation during initial startup phase. 

**Figure 5. Initial startup phase** 

**==> picture [285 x 366] intentionally omitted <==**

**----- Start of picture text -----**<br>
VHVSU<br>VHV-START<br>ICHG<br>I CHG-H<br>ICHG-L<br>VCC<br>VCC-ON<br>PROG<br>VCC-LOW Reading<br>ICC<br>ICC<br>ICC-LC<br>I CC-START-UP<br>Start-up Low Cons. Ramp-up Active mode<br>FAULT<br>VFLT-ON<br>FB, VL<br>OPTO<br>VBM<br>switching<br>activity<br>VZCD S&H<br>VUVP<br>VCS-RU<br>**----- End of picture text -----**<br>


## **6.2.1 Startup phase** 

As soon as HVSU pin voltage reaches VHV-START, the high-voltage startup unit is turned on to charge the VCC capacitor. 

The charging current is limited to ICHG-L until VCC voltage reaches VCC-LOW threshold, and then it is toggled to a higher charging current (ICHG-H) to minimize the startup time. 

Once the VCC reaches VCC-ON threshold, the DLY/CFG pin is read to set the configuration of input voltage protections and input voltage range. 

**DS14143** - **Rev 2** 

**page 13/36** 

**HVLED101 Operating modes** 

Once the protection set-up is fetched, the following pins are pulled up: FB, VL, FAULT and OPTO. When the voltage on the FAULT pin is higher than VFLT-ON threshold, the HVSU recharges the VCC capacitor and the switching activity starts. The first switching cycles activate the next operating phase: the ramp-up phase. 

## **6.2.2** 

## **Ramp-up phase** 

This operating mode is intended to ensure a safe increase of the output voltage. This goal is achieved transferring an almost constant power to the output by fixing the minimum current sense threshold at VCS-RU and driving the external power MOSFET at constant operating frequency FSW-RU, with the maximum duty cycle fixed at 50%. 

The THD optimizer unit is forced to operate with a duty cycle equal to 1 (see relevant section for further details). 

**Figure 6. Ramp-up waveforms** 

**==> picture [342 x 136] intentionally omitted <==**

**----- Start of picture text -----**<br>
Max duty fixed by<br>CK falling edge<br>FSW-RU<br>VCS<br>VCS-RU<br>VGD<br>**----- End of picture text -----**<br>


When both output voltages (read by ZCD sample and hold block) are higher than VUVP threshold and OPTO pin is pulled up for at least TOPTO-TRIG, the IC enters active mode. 

If the ramp-up exit condition is not satisfied within TCF, the IC shuts down, and automatic restart is attempted after TART. 

During this phase the internal PSR error amplifier is always on as well as the FAULT pin pull-up current. 

## **6.2.3** 

## **Active mode** 

During active mode, the IC provides the GD signal to drive the external power switch according to application signals. 

All the parameters are set at their operating range performance and protections are ready to manage undesired events. 

The power consumption of the IC in this phase depends on the switching frequency and the characteristics of the adopted switch. 

The OPTO disable feature activates a deep low consumption mode, while the FAULT disable mean activates a standard low consumption mode. 

The input OVP is active (in CFG 1, 3 and 5) as well as the brownout and output undervoltage protections. 

## **6.2.4 Low consumption mode** 

In this state, the IC stops switching activity and turns off the major part of internal structures in order to reduce VCC consumption down to ICC-LC. 

In this operating mode, the high-voltage startup logic is active to maintain the VCC pin above VCC-OFF (low level) if necessary. 

This state is invoked when the following conditions are met: 

- overcurrent protection. 

- FAULT pin protection. 

- the inactive phase of brownout level protection is running. 

- input overvoltage protection senses an excessive input voltage at pin HVSU. 

**DS14143** - **Rev 2** 

**page 14/36** 

**HVLED101 Control loop** 

## **6.2.5 Deep low consumption mode** 

This state is intended to reduce the IC consumption to the minimum level in order to reduce the input power consumption during burst-mode condition (FB or OPTO driven). 

When the deep low consumption mode condition is removed, the system evolves to the relevant next state without turning on the high-voltage startup unit. 

## **6.2.6 Auto-restart time and check state** 

These are auxiliary states. Auto-restart time is intended to maintain the device supplied for a time equal to TART until a new restart procedure is automatically generated. 

If VCC drops below VCC-OFF, the timers are frozen, while if VCC drops below VCC-SHD the internal logic of the device is reset and all automatic procedures are also interrupted. 

The check state is a logic state that is invoked after VCC-ON trigger to check the status of all protections and take the proper actions according to protection logic. 

## **6.3** 

## **Control loop** 

The HVLED101 IC is optimized to operate as high power factor peak current mode quasi-resonant (QR) flyback (Figure 7). In order to realize this operating scheme, it embeds a multiplier that creates the threshold for the PWM comparator that turns off the main switch when the current measured across a shunt resistor, placed between the source of said switch and GND, reaches the above-mentioned threshold. 

During QR operation, the turn-on command is given by an internal logic that detects the falling edge subsequent to the transformer demagnetization and applies the delay time programmed by the resistance connected to DLY/CFG pin. 

A minimum off-time (TBLANK) is provided to ignore the falling edges that could be associated with spurious oscillations of leakage inductance. 

## **Figure 7. QR operating scheme** 

**==> picture [455 x 113] intentionally omitted <==**

**----- Start of picture text -----**<br>
GD TDLY GD TDLY<br>CS VCS CS VCSunarmed<br>already triggered<br>ZCD ZCD<br>V ARM VARM<br>VTRIG VTRIG<br>TBLANK TBLANK TWAIT<br>**----- End of picture text -----**<br>


The IC operates in quasi-resonant mode, but one or more resonance valley can be skipped to slow down the operating frequency and improve the system efficiency. The VL pin can be used to adjust the valley skipping levels as described in the relevant paragraph. 

During fixed frequency operation, the turn-on command is given by an internal logic. 

**DS14143** - **Rev 2** 

**page 15/36** 

**HVLED101 Control loop** 

## **6.3.1 Multiplier and THD optimization** 

The HVLED101 is primarily intended to deliver power to a load from an AC line. A multiplier is needed to shape the current sense threshold and obtain the desired power factor correction. 

The proprietary THD optimizer embedded into HVLED101 minimizes the distortion of the absorbed AC current (THD) and maximizes the Power Factor (PF), independently from the particular set-up of the transformer (turn ratio and primary inductance). 

The THD optimization unit is placed between the multiplier output and the current sense threshold limiter and is active during active mode only. 

The IC performance is optimized for the use of a transformer that has a reflected voltage (Vout times turn ratio) into a range between 100 V and 250 V. 

The current sense threshold is given by the following relationship: 

VCS = VHVSU_pkVHVSU[∙] δTHDKM θ ∙ VFBint −VOS 

**Figure 8. Multiplier and THD optimizer block diagram** 

**==> picture [26 x 7] intentionally omitted <==**

**----- Start of picture text -----**<br>
HVSU<br>**----- End of picture text -----**<br>


**==> picture [456 x 272] intentionally omitted <==**

**----- Start of picture text -----**<br>
VPK 1/ X<br>Fc = 10 kHz<br>VMULT Vmult, norm<br>K_ hv _ CFG KMPC-X MPC<br>VCS-TH<br>V to I<br>converter<br>OPTO<br>MIN VFBint + MIN<br>(FB, OPTO) (FBint, MPC) RTHD<br>FB -<br>V OS<br>THD<br>GD<br>CTHD<br>ACTIVE MODE<br>**----- End of picture text -----**<br>


Where KM is the DC gain of the THD optimizer and δTHD(θ) is the duty cycle of the internal optimizer MOSFET. An external Capacitor, CTHD, connected between THD pin and GND is used to filter the switching frequency from VCS threshold. The value of such capacitor must be selected in order to obtain: 

**==> picture [174 x 22] intentionally omitted <==**

The internal THD switch is normally switched together with GD: if valley skipping operation is running, the THD pin is put in high impedance on in correspondence with the 6[th] valid falling edge of ZCD signal. The THD MOSFET activity is described in Table 7. 

The minimum value of VCS is set to VCS-RU during startup or VCS-MIN when PSR burst-mode is activated, while it is zero during normal operation. 

The peak detector of the input voltage divider is intended to operate when the peak amplitude (or DC value) of the input voltage is between 105 V and 480 V (CFG1, CFG2 or CFG5) or between 175 V and 760 V (CFG3 or CFG4). 

**DS14143** - **Rev 2** 

**page 16/36** 

**HVLED101 Control loop** 

**Table 7. THD gate activity vs. operating modes** 

|**Operating mode**|**THD gate activity**|
|---|---|
|Active mode (QR up to 6thvalley)|GDTHDsame as GD activity|
|Active mode (from 6thvalley DCM mode)|GDTHDoff (THD pin = HiZ)|
|Ramp-up time|GDTHDalways on|
|Burst mode inactive phase (both PSR or OPTO)|GDTHDalways on|
|OCP protection period|GDTHDalways on|
|iOVP protection period|GDTHDalways off (THD pin = HiZ)|
|Brownout protection|GDTHDalways off (THD pin = HiZ)|
|Fault protection|GDTHDalways off (THD pin = HiZ)|
|Auto restart time (after UVP)|GDTHDalways off (THD pin = HiZ)|



## **6.3.2 Maximum power control** 

The THD optimizer block lets the average value of the OPTO or FB value to be proportional to input power and input voltage. 

An internal MPC block generates a value that is derived from input voltage and that is connected in OR logic with OPTO and FB. 

Such a method allows the topology to absorb from the input source a maximum power that is independent from input voltage and input shape. 

At overloading occurrence, the IC does not take any action, but simply limits the delivered power to MPC level. 

The value of current sense resistor RCS is defined by this MPC block. 

**==> picture [103 x 22] intentionally omitted <==**

MPC block automatically detects if input voltage is AC or DC: if the input voltage does not drop below VDC-DET for a time longer than TDC-DET, then it is assumed that a DC voltage is connected and MPC level is adjusted accordingly, putting NDC = ½. 

The AC mode is recovered (NDC = 1) at first crossing of said level. 

Note that the internal peak detector is always active and triggers the maximum of any fluctuation superimposed to HVSU voltage. If said voltage is a pure DC, the peak detector stores the input voltage itself. 

## **Figure 9. DC detection waveforms** 

**==> picture [454 x 201] intentionally omitted <==**

**----- Start of picture text -----**<br>
TDC-DET<br>VHVSU<br>VDC-DET<br>NDC 1/ 1  1 / 2<br>Switching activity<br>**----- End of picture text -----**<br>


**DS14143** - **Rev 2** 

**page 17/36** 

**HVLED101 Control loop** 

|**6.3.3**|**Current sense input**|
|---|---|
||The power switch current is read across a shunt resistor placed between the source of the switch and ground.|
||Said voltage is compared with the value generated by the THD optimizer.|
||The leading edge blanking (LEB) unit prevents the turn-on spikes from reaching the PWM comparator and avoids|
||false triggering.|
||When the primary side regulation (PSR) loop serves very light loads, the demagnetization time is very short, and|
||the PSR sampling unit could underestimate the output voltage and could react increasing the real voltage. In|
||order to guarantee a correct sampling of VOUT, a minimum current sense level is activated when PSR burst-mode|
||is active.|
||The propagation delay of the peak current detection to GD off (TPD+ external TPROP) results in a turn-off current|
||that is higher than expected. Said error is proportional to input voltage.|
||The HVLED101 embeds a propagation delay compensation logic that injects a portion of the current sourced by|
||ZCD pin during on-time into the CS pin. Said current multiplied by the resistance that is placed between CS pin|
||and the shunt resistor develops a voltage offset that compensates the above mentioned error.|
||Vcs . OS =<br>RFF<br>RZCD ∙KFF ∙<br>Naux<br>Npri ∙VIN =<br>RCS∙<br>TPD+ TPROP<br>LP<br>∙VIN|
||Since RZCDmust be fixed at first to have proper biasing of ZCD pin, then RFFcan be used to adjust the|
||propagation delay compensation.|
|**6.3.4**|**Feedback inputs**|
|**_6.3.4.1_**|**_OPTO_**|
||The OPTO pin is intended to bias and manage the signal coming from the phototransistor collector of a standard|
||optocoupler operating as pull-down current generator.|
||An internal degeneration resistor facilitates the loop compensation equalizing the ideal current source that bias|
||the pin.|
||When OPTO pin voltage is lower than burst-mode threshold, the IC stops switching and enters deep low|
||consumption mode: this mechanism can be used also as an alternate entry to disable the IC.|
|**_6.3.4.2_**|**_FB_**|
||The FB pin is internally connected to the output of the PSR error amplifier: the PSR loop compensation network|
||must be placed between this pin and GND|
||When FB pin voltage is lower than PSR burst-mode threshold, the IC starts to generate the PSR burst-mode|
||algorithm, described into the relevant paragraph.|
||The voltage of the FB pin is internally applied to a “MIN selection” structure together with OPTO pin voltage and|
||MCP internal signal (see “Maximum power control” section).|
||In order to improve PSR performance, FB is put in high impedance state when input voltage is near zero crossing.|
|**6.3.5**|**Zero Current Detection (ZCD)**|
||The ZCD pin is intended to realize the zero current detection mechanism according to the state diagram of|
||Figure 10.|
|**_6.3.5.1_**|**_ZCD state machine description_**|
||When the MOSFET turns off, the HVLED101 applies a minimum blanking time (TBLANK) in order to reject spurious|
||oscillations.|
||Said blanking time is longer when VOUTis lower than the undervoltage protection level: in fact, huge oscillations|
||are foreseen in case of output short-circuit.|
||After minimum blanking time, ZCD logic checks the level of ZCD voltage, if it is higher than arming threshold, then|
||it waits indefinitely for the first falling edge on the ZCD pin below the triggering threshold.|
||On the contrary, if ZCD level is lower than the arming threshold, a maximum waiting time (TWAIT) is started to|
||prevent latching conditions.|
||Said waiting time (TWAIT) is proportional to the programmed delay time (TDLY) configured by RDLYresistor on|
||DLY/CFG pin as per the following relationship:|
||TWAIT = 8 ∙<br>TDLY −100ns<br>+ 100ns|



**DS14143** - **Rev 2** 

**page 18/36** 

**HVLED101 Control loop** 

When the falling edge is detected, the IC can either turn on the MOSFET after the programmed delay time or start counting the number of falling edges (valley) defined by the voltage at VL pin as per valley locking algorithm (see relevant paragraph). 

**Figure 10. ZCD algorithm diagram** 

**==> picture [334 x 233] intentionally omitted <==**

**----- Start of picture text -----**<br>
VCS > VCS _ th<br>TLEB<br>GD = OFF<br>GD_THD = OFF<br>TBLANK , min<br>ZCD_arm = FALSE<br>Wait ZCD<br>Trigger<br>N = 1 N = 2 N = 3 N = 4 N = 5<br>ZCD_trig = TRUE<br>AND<br>Nvalley > 0 Twait Twait Twait Twait Twait<br>EndOfTwait OR ZCD_trig = TRUE<br>AND Fbint < VDCM<br>ZCD_trigAND = TRUE  T DCM<br>Nvalley = 0<br>GD = ON<br>Twait GD_THD = ON<br>Tdly OR ZCD_trig = TRUE<br>EndOfTwait GD = OFF OFF (FB = Hi Z)<br>GD_THD =<br>= TRUE<br>ZCD_arm<br>OR ZCD_trig = TRUE<br>EndOfTwait<br>AND Fbint > VDCM<br>(TDCM)<br>EndOfTimer<br>OR ZCD_trig = TRUE<br>EndOfTwaitAND N >= NValley<br>**----- End of picture text -----**<br>


## _**6.3.5.2 Bottom valley synchronization**_ 

The pin DLY/CFG is used to adjust the delay time that the HVLED101 applies between ZCD trigger signal (falling edge) and MOSFET turn-on. 

A delay time can be programmed selecting a proper value of the resistor mounted between DLY/CFG and GND. 

## _**6.3.5.3 Valley locking and frequency fold-back**_ 

The QR flyback efficiency as well as Power Factor and THD can be improved reducing the operating frequency at light load. 

In order to maintain low turn-on losses, the frequency fold-back technique is achieved turning on the MOSFET on the bottom of a resonance valley (valley skip). 

In order to avoid random jumping between adjacent valleys (especially at high power), the valley locking scheme is adopted and the number of jumping valleys remains constant until a significant modification of output power or input voltage presents. As a result, input THD is minimized at intermediate load, audible noise is avoided and output variable is smoothly regulated. 

**DS14143** - **Rev 2** 

**page 19/36** 

**HVLED101 Primary side regulation feature** 

**Figure 11. Valley skipping algorithm** 

**==> picture [342 x 231] intentionally omitted <==**

**----- Start of picture text -----**<br>
TDCM<br>TDCM-max<br>0 us<br>N=5  VVL =0.3V<br>N=4<br>N=3<br>N=2<br>N=1<br>N=0 (QR)<br>VDCM VL5 VL4 VL3 VL2 VL2H VL1 VL1H VL<br>DCM Mode Valley Locking Mode<br>**----- End of picture text -----**<br>


## **6.4 Primary side regulation feature** 

The HVLED101 can regulate the output voltage of a high power factor flyback stage without the need of an error amplifier and relevant optocoupler. 

## **6.4.1** 

## **PSR operation** 

An ST proprietary structure is able to measure the output voltage reading the signal present at the ZCD pin during demagnetization time. 

The output voltage measurement is performed in correspondence with the transformer demagnetization instant. 

**Figure 12. PSR related signal** 

**==> picture [342 x 227] intentionally omitted <==**

**----- Start of picture text -----**<br>
DEMAG<br>V drain<br>VIN + VR<br>VIN<br>V IN - VR<br>TBLANK<br>VZCD<br>VZCD-ARM<br>VZCD-TRiG VGD<br>TDLY<br>**----- End of picture text -----**<br>


The internal measurement peripheral is active when the switching activity is running and is not frozen by minimum blanking time or frequency fold-back. 

**DS14143** - **Rev 2** 

**page 20/36** 

**HVLED101 Primary side regulation feature** 

When ramp-up mode is running, the PSR unit is functional as well. 

The voltage divider connected between the transformer’s auxiliary winding and ground sets the output voltage according to the following equation: 

**==> picture [159 x 22] intentionally omitted <==**

Near mains zero crossing the converter manages a very low energy amount in each switching cycle. For this reason, ZCD signal amplitude is no longer good information of the output voltage. In order to improve converter performance (THD, PF), in such condition, the FB pin is put in high impedance and is not driven by internal OTA. External compensation network capacitors keep the pin voltage almost constant. The zero crossing condition is detected when the input voltage level goes below a threshold ( ≈ 70 V). 

## **6.4.2 PSR burst-mode operation** 

When the output power becomes very small and frequency fold-back is no longer able to reduce the delivered power, the flyback converter must enter burst-mode operation to maintain the output variable regulation. 

When the application is regulated by an optocoupler, the secondary side error amplifier sets the repetition rate between active and inactive phase of the burst-mode. 

The PSR operation needs to generate some switching activity to refresh the content of the measurement unit. The HVLED101 generates 4 switching cycles following a pure QR scheme (including TDLY) with a repetition time (TREP) that is inversely proportional to the voltage that is present at the FB pin at the end of the 4 switching cycles. 

**Figure 13. PSR burst-mode waveforms** 

**==> picture [455 x 289] intentionally omitted <==**

**----- Start of picture text -----**<br>
TREP<br>1 2 3 4<br>0.2ms<br>GD  Not in scale<br>VCS-MIN<br>V CS<br>I CC_DLC<br>I CC I CC<br>operating<br>VDRAIN<br>**----- End of picture text -----**<br>


The following graph represents the relation between FB voltage and TREP. 

**DS14143** - **Rev 2** 

**page 21/36** 

**HVLED101 Gate driver** 

**Figure 14. PSR burst-mode repetition rate** 

**==> picture [334 x 170] intentionally omitted <==**

**----- Start of picture text -----**<br>
TREP<br>8ms<br>4ms<br>0.4ms<br>300mV VBM VFB<br>**----- End of picture text -----**<br>


During the inactive phase of the burst-mode, the consumption of the HVLED101 is reduced to ICC_DLC. During the generation of the 4 GD cycles, the current sense threshold is bottom limited to generate a minimum demagnetization time and improve the VOUT measurement’s accuracy. 

This minimum current sense level represents, in turn, a small minimum power delivered from primary to secondary side: this minimum power delivery has to be dissipated by simple secondary side bleeder resistor (or equivalent structure). 

## **6.5** 

## **Gate driver** 

The gate driver of the HVLED101 is able to drive high and low the gate of an N-channel Silicon MOSFET, with a typical driving strength of 1.2 A/0.6 A (sink/source). 

The output of GD pin can reach VCC: care has to be taken to verify that VCC is lower than the absolute maximum rating of the adopted switch. 

## **6.6** 

## **IC supply management** 

The HVLED101 is supplied applying a DC voltage source between VCC pin and PGND. 

This voltage can be easily obtained, during normal operation, by auxiliary winding of flyback transformer, but also other voltage sources can be used. 

## **6.6.1** 

## **VCC supply management** 

The HVLED101 operational scheme is designed to minimize the VCC power consumption, especially during low consumption and deep low consumption modes. 

**Figure 15. UVLO and VCC regulation block diagram** 

**==> picture [340 x 145] intentionally omitted <==**

**----- Start of picture text -----**<br>
VCC PGND<br>VCC-ON<br>R       Q UVLO<br>VCC-OFF<br>S      \Q PWR_good<br>**----- End of picture text -----**<br>


**DS14143** - **Rev 2** 

**page 22/36** 

**HVLED101 Parameter selection** 

When VCC drops below VCC-OFF, the IC moves to low consumption mode and activates the high-voltage startup to recover a sufficient VCC level (VCC-ON). 

## **6.6.2** 

## **High-voltage startup** 

The high-voltage startup unit is intended to charge the VCC capacitor to a voltage that is at least equal to VCC-ON. This unit is invoked: 

- at startup 

- during low consumption to maintain the VCC level 

- during TART time to maintain the VCC level 

- in case of iOVP to discharge the input capacitor. 

Two different charging currents are provided depending on the operating condition as summarized in the table below. The charging current automatically shuts down when VCC reaches approximately 19 V. 

**Table 8. HVSU activation summary** 

|**Operating condition**|**VCC range**|**OFF**|**ICHG-H**|**ICHG-L**|
|---|---|---|---|---|
|All states if VHVSU< VHV-START|Any|X|||
|Startup (initial phase)|0 V ... VCC-LOW|||X|
|Startup (IC startup)|VCC-LOW... VCC-ON||X||
|Active mode|VCC-OFF... VCC-ON|X|||
|Input OVP|VCC-OFF... VCC-AMR|||X|
|Low consumption mode (LC)|VCC-ON... VCC-OFF(falling)|X|||
|VCC recover during LC mode|VCC-OFF... VCC-ON(rising)||X||
|Deep low consumption mode (DLC)|Any|X|||



## **6.7** 

## **Parameter selection** 

Some internal parameters of the device can be programmed selecting the value of the time constant (TauCFGn) associated with the RC network placed between DLY/CFG and GND. 

Once the VCC has risen for the first time above VCC-ON, the DLY/CFG pin is pre-charged up to the VDLY-BIAS and then released. 

The DLY/CFG capacitor CCFG is then discharged by RDLY to define a time constant that is internally detected to configure the internal parameters as per the following table. 

**Table 9. Programming configuration** 

|**TauCFGn (µs)**|**CFG**|**iOVP**|**BrOut**|**KHV**|**DC Det.**|**IBLEED @ iOVP**|
|---|---|---|---|---|---|---|
|30 µs ... 45 µs|CFG1|ON|Low|High|Low|ON|
|100 µs ... 140 µs|CFG2|OFF|OFF|Low|Low|N.A.|
|300 µs ... 410 µs|CFG3|ON|High|High|High|ON|
|860 µs ... 1.2 ms|CFG4|OFF|Low|Low|Low|N.A.|
|> 2.05 ms|CFG5|ON|Low|High|Low|OFF|



If the detected time is shorter than 20 µs the IC does not start, while if the time is not detected within an approximate time of 2.05 ms, the IC autonomously proceeds into ramp-up state and sets CFG5. In this phase, the HVSU unit is active to prevent program errors. 

The following table summarizes the suggested combination of RDLY and CCFG to obtain both delay time and configuration programming. 

**DS14143** - **Rev 2** 

**page 23/36** 

**HVLED101 Protections** 

Please note that CFG2 has the brownout detection disabled. This is intended to be used mainly for debug purposes because an input voltage lower than 80 V could lead to unpredictable Vout behavior (see PSR operation section). 

**Table 10. Suggested RDLY-CCFG programming values** 

|**T (ns)**|**R (kΩ) (1%)**|**CDLY (nF) (5% - >6.3V rated)**|**CDLY (nF) (5% - >6.3V rated)**|**CDLY (nF) (5% - >6.3V rated)**|**CDLY (nF) (5% - >6.3V rated)**|**CDLY (nF) (5% - >6.3V rated)**|
|---|---|---|---|---|---|---|
|**DLY **|**DLY  **|**CFG1**|**_CFG2_**|**_CFG3_**|**_CFG4_**|**_CFG5_**|
|163.9|30|1.2n|3.9n|12n|33n|82n|
|183.1|39|1n|2.7n|8.2n|27n|56n|
|219.3|56|680p|2.2n|6.2n|18n|39n|
|259.8|75|470p|1.5n|4.7n|12n|33n|
|355.6|120|270p|1n|2.7n|8.2n|18n|
|419.5|150|220p|680p|2.2n|6.8n|15n|
|483.4|180|180p|560p|1.8n|5.6n|12n|
|568.6|220|150p|470p|1.5n|4.7n|10n|
|675.1|270|120p|390p|1.2n|3.3n|8.2n|
|802.9|330|100p|330p|1n|2.7n|6.8n|
|1101.1|470|82p|220p|680p|2.2n|4.7n|
|1292.8|560|68p|180p|560p|1.8n|3.9n|



The above configurations are intended to be selected in order to fit different application requirements in terms of input voltage. The typical use of the different configurations is shown in the next table. 

**Table 11. Suggested configuration vs. application input voltage requirements** 

|**CFG**|**Mains voltage range**|**Typ. Vin range**|**Note**|
|---|---|---|---|
|CFG1|Universal|90 Vac ÷ 305 Vac||
|CFG2|Extended|> 80 V ÷ 400 Vac|Only for debug purpose|
|CFG3|European|180 Vac ÷ 305 Vac||
|CFG4|Extended|90 Vac ÷ 400 Vac||
|CFG5|Universal|90 Vac ÷ 305 Vac||



## **6.8** 

## **Protections** 

A comprehensive set of protections is embedded in the HVLED101 in order to facilitate the design of an application with a very high grade of robustness. 

## **6.8.1** 

## **Overcurrent protection (2[nd] OCP)** 

In case of transformer saturation or secondary side rectifier short-circuit, the primary side current rises quickly to a very high value. 

To avoid this current becoming dangerous, a second level OCP protection threshold is provided. It stops the switching activity for a longer duration (TOCP) before recovering the switching activity. 

During TOCP, the THD optimizer drives the internal switched resistor always ON (setting δc = 1 in Section  6.3.1  ). 

## **6.8.2 Input overvoltage protection (iOVP)** 

The level of this protection is programmed selecting the value of the time constant of the RC network placed between the DLY/CFG pin and GND according to Table 9. 

**DS14143** - **Rev 2** 

**page 24/36** 

**HVLED101 Protections** 

When input voltage surpasses the programmed value, the input overvoltage protection stops the switching activity and activates the discharge current IBLEED (where required). 

During iOVP, the internal THD optimizer drives the internal switched resistor always OFF (setting δc = 0 in Section  6.3.1  ) and the THD pin is set in high impedance. 

IBLEED current discharges the input capacitor to speed up the recover from surge occurrence. 

In case of steady input overvoltage, the VCC pin rises until the IBLEED generator automatically reduces the absorbed current. At this occurrence, the HVSU unit provides the whole current for HVLED101 and the input capacitor is discharged by a current that is almost equal to ICC plus the internal consumption of the HVSU unit. 

When HVSU voltage is lower than protection level, the HVSU charges VCC to reach VCC-ON (if required) and active mode is entered. 

**Figure 16. iOVP waveforms** 

**==> picture [455 x 365] intentionally omitted <==**

**----- Start of picture text -----**<br>
VHVSU<br>Temporary Overvoltage<br>( e.g. surge)<br>ViOVP<br>VCC<br>~19V<br>V CC-ON<br>VCC-OFF<br>Low consumption<br>Active Mode  (fault)  Active Mode<br>IHVSU<br>I HV-ON<br>IBLEED<br>I Vcc<br>~ ICC<br>I CC<br>ICC-L - I CHG-L<br>**----- End of picture text -----**<br>


## **6.8.3** 

## **Brownout protection (BO)** 

In order to avoid operation at insufficient input voltage, the IC moves to low consumption mode if the input voltage is lower than the programmed threshold (Table 9) for at least TBO (500 ms min.). During masking time (TBO-LEB), activated after brownout triggering time, the HVSU comparator is ignored to prevent false restart due to EMI filter resonance oscillations, while IBLEED is turned on to discharge any residual oscillation due to EMI filter operating condition at turn-off instant. 

After the end of TBO_LEB, the input voltage is checked to be higher than the threshold only during the charging period of VCC: a small time (TDBNC) is applied after HVSU activation to prevent false reading. To be noted that the value of the resistance that is in series with the HVSU pin, multiplied by ICHG-H, sets the hysteresis for brownout threshold voltage. 

**DS14143** - **Rev 2** 

**page 25/36** 

**HVLED101 Protections** 

During brownout, the internal THD optimizer drives the internal switched resistor always OFF (setting δc = 0 in Section  6.3.1  ) and the THD pin is set in high impedance. 

**Figure 17. Brownout protection** 

**==> picture [454 x 250] intentionally omitted <==**

**----- Start of picture text -----**<br>
Ignored<br>VHVSU<br>VBO<br>BO exit<br>IHVSU < TBO TBO TBO-LEB<br>I HV-ON TDBNC TDBNC<br>IBLEED<br>VCC<br>V CC-ON<br>VCC-OFF<br>V CC-SHD<br>Complete restart by ramp-up<br>Active Mode  Low Consumption Active Mode<br>**----- End of picture text -----**<br>


## **6.8.4** 

## **Undervoltage protection (UVP)** 

Primary side regulation sample and hold constantly monitors the output voltage. If it steadily falls below the VUVP threshold for at least TUVP, the IC is shut down and ART state is invoked to try a new operating attempt. Note that, during the VCC recycling, the ART timer is frozen during VCC recharging phase (from turn-off to turn-on thresholds); furthermore, as TART elapses, the HV current generator is activated immediately, without waiting that the VCC turn-off threshold is reached. At operation resuming attempt after ART state, the IC starts from the ramp-up phase. 

## **6.8.5 General fault pin and NTC connection** 

The HVLED101 embeds one general purpose pin intended to disable the switching activity and move the IC into low consumption if the voltage at this pin falls below a threshold level or is left floating. Also in this case (like for UVP), as the protection is triggered, the ART state is invoked: after TART elapses, the IC waits for the FAULT condition reset before resuming operation (starting from ramp-up phase). 

The FAULT pin is mainly used to manage an NTC thermistor: in fact, the lower threshold has a well-defined hysteresis, the pin sources a precise current to create the desired thermal hysteresis for final application. 

**DS14143** - **Rev 2** 

**page 26/36** 

**HVLED101 Protections** 

## **Figure 18. Fault pin block diagram** 

**==> picture [342 x 144] intentionally omitted <==**

**----- Start of picture text -----**<br>
IFLT-BIAS<br>VFLT-OFF<br>NTC VFLT-ON FLT<br>R A<br>RB<br>VFLT-Open<br>-<br>+<br>-<br>+<br>**----- End of picture text -----**<br>


The NTC can be linearized using a resistor network consisting of one resistor in series and one in parallel. The design approach must firstly guarantee that FAULT voltage is greater than VFLT-OPEN if either the temperature is lower than minimum operating value or the NTC is disconnected. Then the value of fault voltage is equal to VFLT-OFF at maximum operating temperature. 

The pin is also able to sense the absence of NTC, because the pin left open is internally pulled up above an upper threshold. If NTC is not used, a fixed resistor (22 kΩ to 47 kΩ) should be connected to GND. 

During FAULT pin protection, the internal THD optimizer drives the internal switched resistor always OFF (setting δc = 0 in Section  6.3.1  ) and the THD pin is set in high impedance. 

**DS14143** - **Rev 2** 

**page 27/36** 

**HVLED101 Package mechanical data** 

## **7 Package mechanical data** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. 

ECOPACK is an ST trademark. 

**Table 12. SOP14 mechanical data** 

|**Dii**|**mm**|**mm**|**mm**|
|---|---|---|---|
|**mensons**|**Min.**|**Typ.**|**Max.**|
|A|1.350||1.750|
|A1|0.100||0.250|
|A2|1.100||1.650|
|B|0.330||0.510|
|C|0.190||0.250|
|D|8.550||8.750|
|E|3.800||4.000|
|e||1.270||
|H|5.800||6.200|
|h|0.250||0.500|
|L|0.400||1.270|
|k|0d||8d|
|ddd|||0.100|



**DS14143** - **Rev 2** 

**page 28/36** 

**HVLED101 Package mechanical data** 

**Figure 19. Package dimensions** 

**==> picture [424 x 515] intentionally omitted <==**

0016019_E 

**DS14143** - **Rev 2** 

**page 29/36** 

**HVLED101 Ordering information** 

## **8 Ordering information** 

## **Table 13. Ordering information** 

|**Part number**|**Package**|**Packaging**|
|---|---|---|
|HVLED101|SOP14|Tube|
|HVLED101TR||Tape and reel|



**DS14143** - **Rev 2** 

**page 30/36** 

**HVLED101** 

## **Revision history** 

**Table 14. Document revision history** 

|**Date**|**Version**|**Changes**|
|---|---|---|
|19-Dec-2022|1|Initial release.|
|21-Dec-2022|2|UpdatedTable 5|



**DS14143** - **Rev 2** 

**page 31/36** 

**HVLED101 Contents** 

## **Contents** 

|**1**|**Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2**|**Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2**|
|---|---|---|
|**2**|**Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3**||
|**3**|**Pin Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4**||
|**4**|**Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6**||
||**4.1**|Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6|
||**4.2**|ESD immunity levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6|
||**4.3**|Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6|
||**4.4**|Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7|
|**5**|**Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8**||
|**6**|**Application information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13**||
||**6.1**|Typical application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13|
||**6.2**|Operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13|
|||**6.2.1**<br>Startup phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13|
|||**6.2.2**<br>Ramp-up phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14|
|||**6.2.3**<br>Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14|
|||**6.2.4**<br>Low consumption mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14|
|||**6.2.5**<br>Deep low consumption mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15|
|||**6.2.6**<br>Auto-restart time and check state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15|
||**6.3**|Control loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15|
|||**6.3.1**<br>Multiplier and THD optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16|
|||**6.3.2**<br>Maximum power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17|
|||**6.3.3**<br>Current sense input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18|
|||**6.3.4**<br>Feedback inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18|
|||**6.3.5**<br>Zero Current Detection (ZCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18|
||**6.4**|Primary side regulation feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20|
|||**6.4.1**<br>PSR operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20|
|||**6.4.2**<br>PSR burst-mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21|
||**6.5**|Gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22|
||**6.6**|IC supply management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22|
|||**6.6.1**<br>VCC supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22|
|||**6.6.2**<br>High-voltage startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23|
||**6.7**|Parameter selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23|
||**6.8**|Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24|
|||**6.8.1**<br>Overcurrent protection (2ndOCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24|
|||**6.8.2**<br>Input overvoltage protection (iOVP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24|



**DS14143** - **Rev 2** 

**page 32/36** 

**HVLED101 Contents** 

||**6.8.3**<br>Brownout protection (BO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25|
|---|---|
||**6.8.4**<br>Undervoltage protection (UVP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26|
||**6.8.5**<br>General fault pin and NTC connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26|
|**7**|**Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28**|
|**8**|**Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30**|
|**Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31**||
|**List**|**of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34**|
|**List**|**of figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35**|



**DS14143** - **Rev 2** 

**page 33/36** 

**HVLED101 List of tables** 

## **List of tables** 

|**Table**|**1.**|Pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4|
|---|---|---|
|**Table**|**2.**|Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6|
|**Table**|**3.**|ESD immunity levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6|
|**Table**|**4.**|Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6|
|**Table**|**5.**|Recommended operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7|
|**Table**|**6.**|Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8|
|**Table**|**7.**|THD gate activity vs. operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17|
|**Table**|**8.**|HVSU activation summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23|
|**Table**|**9.**|Programming configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23|
|**Table**|**10.**|Suggested RDLY-CCFG programming values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24|
|**Table**|**11.**|Suggested configuration vs. application input voltage requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24|
|**Table**|**12.**|SOP14 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28|
|**Table**|**13.**|Ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30|
|**Table**|**14.**|Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31|



**DS14143** - **Rev 2** 

**page 34/36** 

**HVLED101 List of figures** 

|**List**|**of**|**figures**|
|---|---|---|
|**Figure**|**1.**|Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2|
|**Figure**|**2.**|HVLED101 typical PSR application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3|
|**Figure**|**3.**|HVLED101 typical SSR application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3|
|**Figure**|**4.**|Device pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4|
|**Figure**|**5.**|Initial startup phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13|
|**Figure**|**6.**|Ramp-up waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14|
|**Figure**|**7.**|QR operating scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15|
|**Figure**|**8.**|Multiplier and THD optimizer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16|
|**Figure**|**9.**|DC detection waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17|
|**Figure**|**10.**|<br>ZCD algorithm diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19|
|**Figure**|**11.**|<br>Valley skipping algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20|
|**Figure**|**12.**|<br>PSR related signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20|
|**Figure**|**13.**|<br>PSR burst-mode waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21|
|**Figure**|**14.**|<br>PSR burst-mode repetition rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22|
|**Figure**|**15.**|<br>UVLO and VCC regulation block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22|
|**Figure**|**16.**|<br>iOVP waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25|
|**Figure**|**17.**|<br>Brownout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26|
|**Figure**|**18.**|<br>Fault pin block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27|
|**Figure**|**19.**|<br>Package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29|



**DS14143** - **Rev 2** 

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**HVLED101** 

## **IMPORTANT NOTICE – READ CAREFULLY** 

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**DS14143** - **Rev 2** 

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