FS1703-3300-AS

**FS1703 POL[™] µ** ~~ee~~ 

## **3A Rated µPOL[™]** Buck Regulator with Integrated Inductor 

## **DATASHEET** 

## **Features** 

## **Description** 

- µPOL™ package with output inductor included 

The FS1703 is an easy-to-use, fully integrated and highly efficient micro-point-of-load (µPOL™) voltage regulator. The on-chip pulse-width modulation (PWM) controller and integrated MOSFETs, plus incorporated inductor and capacitors, result in an extremely compact and accurate regulator. The low-profile package is suitable for automated assembly using standard surface-mount equipment. 

- Small size: 3.3mm x 3.3mm x 1.5mm 

- Continuous 3A load capability 

- Plug and play: no external compensation required 

- Input voltage range: 4.5V–5.5V 

- Factory trimmed 3.3V ±0.5% initial accuracy 

- Supports 3.3V output applications with 5V input 

- Enabled input, programmable under-voltage lock-out (UVLO) circuit 

Developed by a cross-functional engineering team, the design exemplifies best practice and uses class-leading technologies. From early in the integrated circuit design phase, designers worked with application and packaging engineers to select compatible technologies and implement them in ways that reduce compromise. Developing and optimizing all of these elements together has yielded the smallest, most efficient and fully featured 3A µPOL™ currently available. 

- Open-drain power-good indicator 

- Built-in protection features 

- Operating temperature from -40°C to +125°C 

- Lead-free and halogen-free 

- Compliant with EU REACH and RoHS 

## **Applications** 

- Storage applications 

- Telecom, wireless and 5G applications 

- Networking and datacenter applications 

The built-in protection features include pre-biased start-up, soft-start protection, over-voltage protection, thermally compensated over-current protection with hiccup mode, thermal shut-down with auto-recovery. 

- Industrial applications 

- Distributed point-of-load power architectures 

- Computing peripheral voltage regulation 

- General DC-DC conversion 

**==> picture [447 x 132] intentionally omitted <==**

**----- Start of picture text -----**<br>
3.5<br>3<br>V<br>OUT<br>PVIN PVVININ VVOSOUT 2.52<br>V<br>CC 1.5<br>1<br>LFM = 0<br>PG PGnd 0.5 PVIN = 5V, VOUT = 3.3V<br>* SI En AGnd OF+ 0 a [<br>0 20 40 60 80 100 120<br>Ambient Temperature (°C)<br>Maximum Load Current (A)<br>**----- End of picture text -----**<br>


**Page 1** 

**Rev 1.2, July 11, 2022** 

Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright © 2018–22 TDK Corporation. All rights reserved. All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice. 

**FS1703 POL[™] µ** ~~ee~~ 

## **Pin configuration** 

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1 15 14 13 13 14 15 1<br>2 17 12 12 17 2<br>16 16<br>a a<br>3 11 11 3<br>_ pbs 03 = =<br>4 10 10 4<br>- 5 _ oe 9 BE 9 5<br>P q ba ----4 07 = =<br>6 7 8 8 7 6<br>Be ne<br>**----- End of picture text -----**<br>


_**Figure 1 Pin layout (top view)**_ 

_**Figure 2 Pin layout (bottom view)**_ 

## **Pin functions** 

|**Pin**<br>**Number**|**Name**|**Description**|
|---|---|---|
|1|NC|**Connect to AGnd.**|
|2|PG|**Power Good status.**Open drain of an internal MOSFET.<br>Pull upto VCC–pin 10 or an external bias voltage – with a 49.9kΩ resistor.|
|3|En|**Enable.**Switches the FS1703 on and off. Can be used with two external resistors to set an external UVLO|
|4|NC|**Connect to AGnd.**|
|5|VOS|**V**OUT**sense pin.**Connect to VOUTon the application board using an external resistor divider to set<br>desired output voltage(subject to minimum off time and maximum dutylimitations)|
|6|NC|**Connect to AGnd.**|
|7|VOUT|**Regulator output voltage.**Place output capacitors between thispin and PGnd(pin 8).|
|8, 16|PGnd|**Power ground.**Serves as a separate ground for the MOSFETs. Connect to the power ground plane in the<br>application.|
|9|AGnd|**Signalground.**Serves as theground for the internal reference and control circuitry.|
|10|VCC|**Supply voltage.**Maybe an input bias for an external VCCvoltage. Tie to the VINpin externally.|
|11|VIN|**Input voltage.**Tie to PVINthrough a 2.7Ω resistor.|
|12,13,14,<br>17|PVIN|**Power input voltage.**Input for the MOSFETs.|
|15|VSW|**Testpoint for internal V**SW**.**Connect to an isolatedpad on the PCB.|



**Page 2** 

**Rev 1.2, July 11, 2022** 

Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright© 2018–22 TDK Corporation. All rights reserved. All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice. 

**FS1703 POL[™] µ** ~~ee~~ 

## **Block diagram** 

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VIN VCC<br>AGnd<br>Low Drop-Out<br>fault (LDO)<br>Internal Reference VOUT PVIN En Regulator<br>(Digital-to-Analog VCC<br>Converter (DAC))<br>Pulse Generator<br>for Pulse Width PWM PVIN<br>signal<br>HDrv<br>ue Start SS Gate Drive<br>signal<br>OTP fault Logic and L<br>shut-downthermal VCC HDrv Control LDrv VCC VOUT<br>fault<br>VOS = Control te PGnd<br>En<br>and Fault<br>PG Logic<br>mo<br>power-on reset<br>S|<br>**----- End of picture text -----**<br>


_**Figure 3 FS1703 µPOL™**_ 

## **Typical applications** 

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3.3V<br>4.5V to 5.5V PVIN VOUT<br>V<br>V OS<br>IN<br>V<br>CC<br>PGnd<br>PG<br>En AGnd<br>**----- End of picture text -----**<br>


_**Figure 4 Single supply applications circuit**_ 

**Page 3** 

**Rev 1.2, July 11, 2022** 

Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright© 2018–22 TDK Corporation. All rights reserved. All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice. 

**FS1703 POL[™] µ** ~~ee~~ 

## **Absolute maximum ratings** 

**Warning:** Stresses beyond those shown may cause permanent damage to the FS1703. 

**Note:** Functional operation of the FS1703 is not implied under these or any other conditions beyond those stated in the FS1703 specification. 

|**Reference**|**Range **|
|---|---|
|PVIN,VIN,En to PGnd|-0.3V to 18V(Note 1, page 6)|
|VCCto PGnd|-0.3V to 6V(Note 2, page 6)|
|VOSto AGnd|-0.3V to VCC (Note 2, page 6)|
|PG to AGnd|-0.3V to VCC(Note 2, page 6)|
|PGnd to AGnd|-0.3V to +0.3V|
|ESD Classification|2kV(HBM JESD22-A114)|
|Moisture SensitivityLevel|MSL 3(JEDEC J-STD-020D)|



|**Thermal Information**|**Range **|
|---|---|
|Junction-to-Ambient Thermal Resistance ƟJA|22.6°C/W|
|Junction to PCB Thermal Resistance ƟJ-PCB|2.36°C/W|
|Storage Temperature Range|-55°C to 150°C|
|Junction Temperature Range|-40°C to 150°C|
|Note:<br>ƟJA: FS1703 evaluation board and JEDEC specifications JESD 51-2A||
|ƟJ-c (bottom): JEDEC specification JESD 51-8||



## **Order information** 

## **Package details** 

The FS1703 uses a µPOL™ 3.3 mm x 3.3 mm package delivered in tape-and-reel format, with either 250 or 4000 devices on a reel. 

## **Standard part numbers** 

||**Part numbers**|**Part numbers**|
|---|---|---|
|**VOUT**|**250 devices on a reel**|**4000 devices on a reel**|
|3.3|FS1703-3300-AS|FS1703-3300-AL|



**Page 4** 

**Rev 1.2, July 11, 2022** 

Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright© 2018–22 TDK Corporation. All rights reserved. All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice. 

**FS1703 POL[™] µ** ~~ee~~ 

## **Recommended operating conditions for various output voltages** 

## **Output voltage= 3.3V** 

|**Definition**|**Symbol**|**Min**|**Max**|**Units**|
|---|---|---|---|---|
|Input Voltage Range with external VCC (Note 3, Note 5)|PVIN|4.5|5.5|V|
|SupplyVoltage Range (Note 2)|VCC,VIN|4.5|5.5||
|Continuous Output Current Range|IO|0|3|A|
|OperatingJunction Temperature|TJ|-40|125|°C|



## **Electrical characteristics** 

|**ELECTRICAL CHARACTERISTICS**<br>~~a~~|**ELECTRICAL CHARACTERISTICS**<br>~~a~~|**ELECTRICAL CHARACTERISTICS**<br>~~a~~|**ELECTRICAL CHARACTERISTICS**<br>~~a~~|**ELECTRICAL CHARACTERISTICS**<br>~~a~~|**ELECTRICAL CHARACTERISTICS**<br>~~a~~|**ELECTRICAL CHARACTERISTICS**<br>~~a~~|
|---|---|---|---|---|---|---|
|**Unless otherwise stated, these specifications apply over: 4.5V < PVIN < 5.5V, 4.5V < VIN < 5.5V, 0°C < T < 125°C**<br>**Typical values are specified at TA = 25°C**<br>~~aii~~<br>~~a~~|||||||
|**Parameter**|**Symbol**|**Conditions**|**Min**|**Typ**<br>~~a~~|**Max**<br>~~a~~|**Unit**<br>~~a~~|
|**Supply Current**<br>~~ee ee~~|||||||
|VINSupplyCurrent(Standby)<br>~~ee ee~~|IIN(STANDBY)<br>~~ee~~|Enable low<br>~~ee~~|~~ee~~|1<br>~~ee~~|~~ee~~|mA<br>~~ee~~|
|VINSupplyCurrent(Static)<br>~~ee ee~~|IIN(STATIC)<br>~~ee~~|No switching,En = 2V<br>~~ee~~|~~ee~~|2<br>~~ee~~|~~ee~~||
|VINSupply Current (Dynamic)<br>~~ee ee~~|IIN (DYN)<br>~~ee~~|En high, VIN= 5V, VOUT= 3.3V,<br>FSW = 570kHz<br>~~ee~~|~~ee~~|6.3<br>~~ee~~|9<br>~~ee~~||
|**Soft-Start**<br>~~ee ee~~|||||||
|Soft-Start Rate|SSRATE (default)|(Note 6)||1||V/ms|
|**Output Voltage **<br>~~Oe~~|||||||
|Accuracy<br>~~Oe~~|~~Oe~~|TJ= 25°C,PVIN= 5V,VOUT= 3.3V(Note 5) <br>~~Oe~~|<br>~~Oe~~|±0.5 <br>~~Oe~~|<br>~~Oe~~|%<br>~~Oe~~|
|||-40°C < TJ< 125°C, PVIN= 5V,<br>(Note 5),VOUT= 3.3V<br>~~Oe~~|-1.4 <br>~~Oe~~|<br>~~Oe~~|+1.4<br>~~Oe~~||
|**On-Time Timer Control**<br>~~ee~~|||||||
|On Time<br>~~oe~~|TON<br>~~oe~~<br>~~ee~~|PVIN= 5V,VOUT= 3.3V,FSW= 570kHz<br>~~oe~~|~~oe~~|1190 <br>~~oe~~|<br>~~oe~~|ns<br>~~oe~~|
|Minimum On-Time<br>~~oe~~|TON(MIN)<br>~~oe~~<br>~~ee~~|(Note 6)<br>~~oe~~|~~oe~~|50<br>~~oe~~|~~oe~~||
|**Thermal Shut-Down**<br>~~ee~~<br>~~re~~|||||||
|Thermal Shut-Down<br>~~re~~|TSD(default)<br>~~re~~|~~re~~|~~re~~|145<br>~~re~~|145<br>~~re~~|°C<br>~~re~~|
|Hysteresis<br>~~re~~|~~re~~|~~re~~|~~re~~|25<br>~~re~~|~~re~~||
|**Under-Voltage Lock-Out**|||||||
|VCCStart Threshold<br>~~——~~|VCC_UVLO(START)<br>~~——~~|VCCRisingTripLevel<br>~~ae~~|3.7 4.0<br>~~ae~~|3.7 4.0<br>~~ae~~|4.2<br>~~ae~~|V<br>~~ae~~|
|VCC StopThreshold<br>~~——~~|VCC_UVLO(STOP)<br>~~——~~|VCC FallingTripLevel<br>~~ae~~|3.6<br>~~ae~~|3.8<br>~~ae~~|3.95<br>~~ae~~||
|Enable Threshold<br>~~——~~|En(HIGH)<br>~~——~~|RampingUp<br>~~ae~~|1.1 1.2<br>~~ae~~|1.1 1.2<br>~~ae~~|1.3<br>~~ae~~||
||En(LOW)<br>~~——~~|RampingDown<br>~~ae~~|0.9 1<br>~~ae~~|0.9 1<br>~~ae~~|1.06<br>~~ae~~||
|Input Impedance<br>~~——~~|REN<br>~~——~~|~~ae~~|500 <br>~~ae~~|1000 <br>~~ae~~|1500<br>~~ae~~|kΩ<br>~~ae~~|
|**Current Limit**<br>~~——~~<br>~~ae~~|||||||
|Current Limit Threshold|IOC (default)|TJ= 25°C|3.6 4|3.6 4|4.3|A|



**Page 5** 

**Rev 1.2, July 11, 2022** 

Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright© 2018–22 TDK Corporation. All rights reserved. All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice. 

**FS1703 POL[™] µ** ~~ee~~ 

|**ELECTRICAL CHARACTERISTICS**<br>~~|~~|**ELECTRICAL CHARACTERISTICS**<br>~~|~~|**ELECTRICAL CHARACTERISTICS**<br>~~|~~|**ELECTRICAL CHARACTERISTICS**<br>~~|~~|**ELECTRICAL CHARACTERISTICS**<br>~~|~~|**ELECTRICAL CHARACTERISTICS**<br>~~|~~|**ELECTRICAL CHARACTERISTICS**<br>~~|~~|
|---|---|---|---|---|---|---|
|**Unless otherwise stated, these specifications apply over: 4.5V < PVIN < 5.5V, 4.5V < VIN < 5.5V, 0°C < T < 125°C**<br>**Typical values are specified at TA = 25°C**<br>~~|~~|||||||
|**Parameter**|**Symbol**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|HiccupBlankingTime<br>~~a~~|TBLK(HICCUP)<br>~~a~~<br>~~GC~~|~~a~~<br>~~GC~~|~~a~~<br>~~GC~~|20<br>~~a~~<br>~~GC~~|~~a~~<br>~~GC~~|ms<br>~~a~~<br>~~GC~~|
|**Over-Voltage Protection**<br>~~Rn~~|||||||
|Output Over-Voltage Protection<br>Threshold<br>~~Rn~~<br>~~a~~|VOVP(default)<br>~~Rn~~<br>~~Ge~~|OVP Detect (Note 6), VOUT= 3.3V<br>~~Rn~~<br>~~FO~~|115 <br>~~Rn~~<br>~~FO~~|120 125 V<br>~~Rn~~<br>~~FO~~|120 125 V<br>~~Rn~~<br>~~FO~~|120 125 VOS%<br>~~Rn~~<br>~~FO~~|
|Output Over-voltage Protection Delay <br>~~a~~|TOVPDEL<br>~~Ge~~|~~FO~~|~~FO~~|5<br>~~FO~~|~~FO~~|µs<br>~~FO~~|
|**Power Good(PG)**<br>~~Ge FO~~<br>~~es~~~~**G**e ee~~|||||||
|Power Good Upper Threshold<br>~~es~~|VPG(UPPER) (default) <br>~~**G**e ee~~|VOUTRisingto 3.3V<br>~~ee~~|85<br>~~ee~~|90<br>~~ee~~|95<br>~~ee~~|VOS%<br>~~ee~~|
|Power Good Hysteresis<br>~~es~~<br>~~a~~|VPG(LOWER)<br>~~**G**e ee~~|VOUTFallingfrom 3.3V<br>~~ee~~<br>~~G~~|~~ee~~<br>~~G~~|5<br>~~ee~~<br>~~G~~|~~ee~~<br>~~G~~<br>~~GO~~||
|Power Good Sink Current<br>~~es ~~<br>~~GF~~|IPG<br> ~~**G**e ee~~<br>~~GF~~|PG = 0.5V,En = 2V<br>~~ee~~<br>~~GF~~|~~ee~~<br>~~GF~~|9<br>~~ee~~<br>~~GF~~|~~ee~~<br>~~GF~~<br>~~GO~~|mA<br>~~ee~~<br>~~GF~~|



## **Notes** 

- 1 PGnd pin and AGnd pin are connected together 

- 2  Must not exceed 6V 

- 3 VIN is connected to VCC to bypass the internal Low Drop-Out (LDO) regulator and also to PVIN 

- 4 Maximum switch node voltage should not exceed 22V 

- 5 Hot and cold temperature performance is assured by correlation using statistical quality control, but not tested in production; performance at 25°C is tested and guaranteed in production environment 

- 6 Guaranteed by design but not tested in production 

**Rev 1.2, July 11, 2022** 

**Page 6** 

Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright© 2018–22 TDK Corporation. All rights reserved. All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice. 

## **FS1703 POL[™] µ** 

## **Temperature characteristics** 

## **Output Voltage** 

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**----- Start of picture text -----**<br>
3.35<br>3.34<br>3.33<br>3.32<br>3.31<br>3.30 ee<br>3.29<br>pf | | | | | oP<br>3.28<br>3.27<br>3.26<br>3.25<br>-40 -20 0 20 40 60 80 100 120 140<br>Temperature (°C)<br> (V)<br>VOUT<br>**----- End of picture text -----**<br>


## **Enable Start Threshold** 

## **VIN Supply Current (Dynamic)** 

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**----- Start of picture text -----**<br>
8.0<br>7.5<br>7.0<br>6.5<br>6.0 | | | | | |HF<br>5.5<br>Pt tT ET TE TT |<br>5.0<br>4.5<br>4.0<br>-40 -20 0 20 40 60 80 100 120 140<br>Temperature (°C)<br> (mA)<br>IIN_DYN<br>**----- End of picture text -----**<br>


## **Enable Stop Threshold** 

## **VCC Start Threshold** 

## **VCC Stop Threshold** 

**Page 7** 

**Rev 1.2, July 11, 2022** 

Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright© 2018–22 TDK Corporation. All rights reserved. All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice. 

## **FS1703 POL[™] µ** 

## **On Time** 

## **Soft-Start Rate** 

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**----- Start of picture text -----**<br>
1.30<br>1.28<br>1.26<br>1.24<br>1.221.20 er|__|<br>1.18<br>1.16<br>1.14<br>1.12<br>1.10<br>-40 -20 0 20 40 60 80 100 120 140<br>Temperature (°C)<br> (µs)<br>TON<br>**----- End of picture text -----**<br>


## **Current Limit Threshold** 

**Rev 1.2, July 11, 2022** 

**Page 8** 

Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright© 2018–22 TDK Corporation. All rights reserved. All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice. 

**FS1703 POL[™] µ** ~~ee~~ 

## **Efficiency characteristics** 

## **Typical efficiency and power loss** 

PVIN =4.5V–5.5V, IO = 0A–3A, room temperature, no air flow, all losses included 

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**----- Start of picture text -----**<br>
100<br>95<br>90<br>85<br>80<br>75<br>70<br>PVIN =  VIN = VCC = 5V<br>65 PVIN =  VIN = VCC = 4.5V<br>PVIN =  VIN = VCC = 5.5V<br>60<br>0 500 1000 1500 2000 2500 3000<br>Load Current (mA)<br>1200<br>PVIN =  VIN = VCC = 4.5V<br>1000 PVIN =  VIN = VCC = 5V<br>PVIN =  VIN = VCC = 5.5V<br>800<br>600<br>400<br>200<br>0<br>0 500 1000 1500 2000 2500 3000<br>IOUT (mA)<br>Efficiency ( %)<br>Ploss (mW)<br>**----- End of picture text -----**<br>


**Page 9** 

**Rev 1.2, July 11, 2022** 

Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright© 2018–22 TDK Corporation. All rights reserved. All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice. 

## **FS1703 POL[™] µ** 

## **Typical load regulation** 

PVIN = 4.5V–5.5V, IO = 0A–3A, room temperature, no air flow 

**==> picture [392 x 241] intentionally omitted <==**

**----- Start of picture text -----**<br>
Load Current (mA)<br>0 500 1000 1500 2000 2500 3000<br>0.0<br>-0.1<br>-0.2<br>cS<br>3°<br>S<br>s<br>3 -0.3<br>QO<br>i)<br>a<br>no)<br>©<br>aie}<br>x -0.4 oo<br>-e PVIN =  VIN = VCC = 5V<br>-0.5 - PVIN =  VIN = VCC = 5.5V<br>~~ PVIN =  VIN = VCC = 4.5V<br>-0.6<br>**----- End of picture text -----**<br>


**Page 10** 

**Rev 1.2, July 11, 2022** 

Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright© 2018–22 TDK Corporation. All rights reserved. All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice. 

**FS1703 POL[™] µ** 

## **Applications information** 

## **Overview** 

The FS1703 is an easy-to-use, fully integrated and highly efficient DC/DC regulator. It uses a proprietary modulator to deliver fast transient responses. The modulator has internal stability compensation so that it can be used in a wide range of applications, with various types of output capacitors, without loop stability issues. 

## **Bias voltage** 

For single-rail operation, the VIN pin of the FS1703 should be connected to the PVIN pin and VCC pin (Figure 5). 

## **Soft-start and target output voltage** 

The FS1703 has an internal digital soft-start circuit to control output voltage rise-time and limit current surge at start-up. When VCC exceeds its start threshold (VCC_UVLO(START)), the FS1703 exits reset mode and initialization begins. 

Once initialization is complete and the Enable (En) pin has been asserted (Figure 6), the internal reference soft-starts to the target output voltage at 1mV/µs. 

During initial start-up, the FS1703 operates with a minimum of high-drive (HDrv) pulses until the output voltage increases (see Switching frequency and minimum values for on-time on page 12). Ontime is increased until VOUT reaches the target value. 

**Note: Until initialization is complete, a small leakage current (≈3.4µA) will flow from the device into the output. This may significantly pre-bias the output voltage in applications with long V** IN **/V** CC **rise times. To prevent this, a small load capable of sinking 3.4µA should be connected in such applications.** 

**==> picture [441 x 218] intentionally omitted <==**

**----- Start of picture text -----**<br>
PV<br>IN<br>PV V V<br>IN CC IN Figure 6 Theoretical operational waveforms<br>REN1 during soft-start<br>En<br>FS1703<br>REN2<br>ra av— Peseaind lage allogic love<br>Figure 5 Single supply configuration: internal LDO<br>regulator, adjustable PVIN_UVLO<br>**----- End of picture text -----**<br>


**Page 11** 

**Rev 1.2, July 11, 2022** 

Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright© 2018–22 TDK Corporation. All rights reserved. All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice. 

## **FS1703 POL[™] µ** 

## **Pre-biased start-up** 

The FS1703 can start up into a pre-charged output smoothly, without causing oscillations and disturbances of the output voltage. When it starts up in this way, the Control and Synchronous MOSFETs are forced off until the internal Soft-Start (SS) signal exceeds the sensed output voltage at the VOS pin. Only then is the first gate signal of the Control MOSFET generated, followed by complementary turn on of the Synchronous MOSFET. The Power Good (PG) function is not active until this point. 

## **Shut-down mechanism** 

The FS1703 shuts down by de-asserting the En pin. Both drivers switch off and the digital-to-analog converter (DAC) and soft-start are pulled down instantaneously. 

## **Switching frequency and minimum values for on-time** 

## **Enable (En) pin** 

The Enable (En) pin has several functions: 

- It is used to switch the FS1703 on and off. It has a precise threshold, which is internally monitored by the UVLO circuit. If it is left floating, an internal 1MΩ resistor pulls it down to prevent the FS1703 being switched on unintentionally. 

- It can be used to implement a precise input voltage UVLO. The input of the En pin is derived from the PVIN voltage by a set of resistive dividers, REN1 and REN2 (Figure 5). Users can program the UVLO threshold voltage by selecting different ratios. This is a useful feature that stops the FS1703 regulating when PVIN is lower than the desired voltage. 

- It can be directly connected to PVIN without external resistive dividers for some spaceconstrained designs. This is a useful feature for standalone start-up, when no logic signal is available to enable the FS1703. 

The switching frequency of the FS1703 is set at the factory to 570kHz. 

As a result, system designers need not concern themselves with selecting the switching frequency and have one fewer design task to manage. 

When input voltage is high relative to target output voltage, the Control MOSFET is switched on for shorter periods. The shortest period for which it can reliably be switched on is defined by minimum on-time (TON(MIN)). During start-up, when the output voltage is very small, the FS1703 operates with minimum on-time. 

**Page 12** 

_**Figure 7 Start-up: PVIN, VIN, VCC and En pins tied together, PG pin pulled up to an external supply**_ 

**Rev 1.2, July 11, 2022** 

Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright© 2018–22 TDK Corporation. All rights reserved. All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice. 

## **FS1703 POL[™] µ** 

When the current exceeds the OCP threshold, the PG and SS signals are pulled low. The Synchronous MOSFET remains on until the current falls to 0, then the FS1703 enters hiccup mode (Figure 9). Both the Control MOSFET and the Synchronous MOSFET remain off for the hiccup-blanking time. After this time, the FS1703 tries to restart. If an over-current fault is still detected, the preceding actions are repeated. The FS1703 remains in hiccup mode until the over-current fault is remedied. 

_**Figure 8 Start-up: En pin asserted after PVIN and VIN, PG pin pulled up to an external supply**_ For VOUT to start up as defined by the soft-start rate requires correct sequencing: 

- PVIN must start up before VCC and/or Enable. 

- PVIN must ramp down only after VCC has ramped down below its UVLO threshold and/or Enable has been de-asserted. 

## **Over-current protection (OCP)** 

Over-current protection (OCP) is provided by sensing the current through the RDS(on) of the Synchronous MOSFET. When this current exceeds the OCP threshold, a fault condition is generated. This method provides several benefits: 

- Provides accurate overcurrent protection without reducing converter efficiency (the current sensing is lossless) 

- Reduces cost by eliminating a current-sense resistor 

- Reduces any layout-related noise issues. 

The OCP threshold is set to 4A. 

The threshold is internally compensated so that it remains almost constant at different ambient temperatures. 

_**Figure 9 Illustration of OCP in hiccup mode**_ 

## **Over-voltage protection (OVP)** 

Over-voltage protection (OVP) is provided by sensing the voltage at the VOS pin. When VOS exceeds the output OVP threshold for longer than the output OVP delay (typically 5μs), a fault condition is generated. 

The OVP threshold is set internally to 120% of VOUT 

When an OVP condition is detected, the Control MOSFET is switched off immediately and the PG pin is pulled low. The Synchronous MOSFET is switched on to discharge the output capacitor. 

The Control MOSFET remains latched off until reset by cycling either VCC or En. The voltage at the VOS pin falling below the output OVP threshold (with 5% hysteresis) does not switch on the Control 

**Page 13** 

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Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright© 2018–22 TDK Corporation. All rights reserved. All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice. 

## **FS1703 POL[™] µ** 

MOSFET but it does switch off the Synchronous MOSFET to prevent build-up of negative current. 

## **Power Good (PG)** 

Figure 11 shows PG behavior. 

Figure 10 shows a timing diagram for over-voltage protection. 

The PG signal is asserted when: 

- En and VCC are both above their thresholds 

- No fault has occurred (including over-current, over-voltage and over-temperature) 

- VOUT is within the target range (determined by continuously monitoring whether VOS is above the PG threshold) 

_**Figure 10 Illustration of latched OVP**_ 

## **Over-temperature protection (OTP)** 

Temperature sensing is provided inside the FS1703. The OTP threshold is internally set to 145°C. 

When the threshold is exceeded, thermal shutdown switches off both MOSFETs and resets the internal soft-start, but the internal LDO regulator is still in operation. 

Automatic restart is initiated when the sensed temperature drops within the operating range. There is a 20°C hysteresis in the OTP threshold. 

## _**Figure 11 PG signal behavior**_ 

As can be seen, when VOS rises above the power good rising threshold (90% of setpoint), the PG signal is pulled high. When VOS drops below the power good falling threshold (85% of setpoint), the PG signal is pulled low. 

For pre-biased start-up, the PG signal is not active until the first gate signal of the Control MOSFET is generated. 

FS1703 also integrates an additional PMOS in parallel to the NMOS internally connected to the PG pin (Figure 3). This PMOS allows the PG signal to stay at logic low, even if VCC is low and the PG pin is pulled up to an external voltage not VCC (Figure 7 and Figure 8). 

**Rev 1.2, July 11, 2022** 

**Page 14** 

Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright© 2018–22 TDK Corporation. All rights reserved. All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice. 

## **FS1703 POL[™] µ** 

## **Design example** 

Let us now consider a simple design example, using the FS1703 for the following design parameters: 

- PVIN = VIN = 5V 

- VOUT = 3.3V 

- FSW = 570kHz 

- COUT = 3 x 22μF 

- CIN = 2 x 22μF 

noise on PVIN. The VIN pin should be shorted to the VCC pin, bypassing the internal LDO. 

## **Output voltage and output capacitor** 

The FS1703 is supplied pre-programmed and factory-trimmed in a closed loop to the target voltage specified for the part number. As a result, no external resistor divider is required and resistor tolerances are eliminated from the error budget. 

- Ripple Voltage = ± 1% * VOUT 

- ΔVOUT(MAX) = ±3% * VOUT (for 100% load transient) 

## **Input capacitor** 

The input capacitor selected for this design must: 

- Handle the peak and root mean square (RMS) input currents required by the FS1703 

- Have low equivalent series resistance and inductance (ESR and ESL) to reduce input voltage ripple 

MLCCs (multi-layer ceramic capacitors) are ideal. Typically, in 0805 case size, they can handle 2A RMS current with less than 5°C temperature rise. 

For a buck converter operating at duty cycle D and output current IO, the RMS value of the input current is: 

In this application, IO = 3A and 

Therefore, _I_ RMS = 1.4A and we can select two 22μF 16V ceramic capacitors for the input capacitors (C3216X5R1C226M160AB from TDK). 

If the FS1703 is not located close to the 12V power supply, a bulk capacitor (68–330μF) may be used in addition to the ceramic capacitors. 

For VIN, it is recommended to use a 1μF capacitor very close to the pin. The VIN pin should be connected to PVIN through a 2.7Ω resistor. Together, the 2.7Ω resistor and 1μF capacitor filter 

The design requires minimal output capacitance to meet the target output voltage ripple and target maximum output voltage deviation under load transient conditions. 

For the FS1703, the minimum number of output capacitors required to achieve target peak-to-peak VOUT ripple is: 

**==> picture [213 x 64] intentionally omitted <==**

- _D_ = duty cycle 

- _C_ = equivalent capacitance of each output capacitor 

- _F_ SW = switching frequency 

- _ESR_ = equivalent series resistance of each output capacitor 

- _ESL_ = equivalent series inductance of each output capacitor 

- ∆ i 

   - = target peak-to-peak VOUT ripple 

This design uses C2012X5R0J226K125AB from TDK; this is a 22μF MLCC, 0805 case size, rated at 6.3V. At 3.3V, accounting for DC bias and AC ripple derating, it has an equivalent capacitance of 7μF ( _C_ ). Equivalent series resistance is 3mΩ (ESR) and equivalent series inductance is 0.44nH (ESL). 

Putting these parameters into the equation gives: 

_N_ MIN = 1.02 

**Rev 1.2, July 11, 2022** 

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Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright© 2018–22 TDK Corporation. All rights reserved. All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice. 

## **FS1703 POL[™] µ** ~~ee~~ 

To meet the maximum voltage deviation _ΔVo_ max under a load transient, the minimum required number of output capacitors is: 

48 ) 9 ∆+,-.:;< -. 

where: 

- = load step 

- ∆+,-.:;< = target maximum voltage deviation 

- +,-. = output voltage 

- _C_ = equivalent capacitance of each output capacitor 

Again, using _C_ = 7μF, it can be seen that the minimum number of output capacitors required is 1.96. 

In our design intended for space-constrained applications, therefore, we use three C2012X5R0J226K125AB capacitors. 

It should be noted here that the calculation for the minimum number of output capacitors under a load transient makes some assumptions: 

- a) No ESR or ESL 

- b) Converter can saturate its duty cycle instantly 

- c) No latency 

- d) Step load (infinite slew rate) 

Assumptions (a), (b) and (c) are liberal, whereas (d) is conservative. Therefore, in a real application, additional capacitance may be required to meet transient requirements and should be carefully considered by the system designer. 

The typical application waveforms in Figure 19 and Figure 20 show the steady state VOUT ripple as well as the voltage deviation in response to a 50% load transient. 

It should be noted that even in the absence of a target VOUT ripple or target maximum voltage deviation under load transient, at least one 22μF capacitor is still required in order to ensure stable operation without excessive jitter. 

Up to six 22μF capacitors may be used in the design. If more capacitance is required, it is recommended to use a capacitor with relatively high ESR (>3mΩ) such as POSCAP or specialty polymer capacitors. 

## **VCC capacitor selection** 

FS1703 uses an on-package VCC capacitor to ensure effective high-frequency bypassing. The 1μF capacitor on the VIN pin provides additional bypassing when the LDO is bypassed by shorting the VIN pin to the VCC pin. 

**Page 16** 

**Rev 1.2, July 11, 2022** 

Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright© 2018–22 TDK Corporation. All rights reserved. All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice. 

**FS1703 POL[™] µ** ~~ee~~ 

**==> picture [458 x 220] intentionally omitted <==**

**----- Start of picture text -----**<br>
C<br>PVIN (5V) IN PVIN VOUT VOUT (3.3V)<br>2.7Ω  VOS<br>Iz<br>V<br>IN<br>VCC COUT<br>C<br>Vcc<br>Lt 49.9kΩ<br>PGnd<br>PG<br>I En AGnd<br>L<br>CIN<br>+ 2 X 22uF/0805/X5R/16V<br>CVcc 1µF/0603/X5R/10V<br>pffo COUT 3 X 22µF/0805/X5R/6.3V 5 i<br>**----- End of picture text -----**<br>


_**Figure 12 Application circuit for a single supply, PVIN=5V, VOUT=3.3V, 3A**_ 

**Page 17** 

**Rev 1.2, July 11, 2022** 

Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright© 2018–22 TDK Corporation. All rights reserved. All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice. 

**FS1703 POL[™] µ** 

## **Typical operating waveforms** 

PVIN=5V, VOUT=3.3V, IO=0–3A, room temperature, no airflow 

_**Figure 13 Startup with no load (Ch1:PVIN, Ch2: VOUT, Ch3: PG, Ch5: Enable, Ch8:IOUT)**_ 

_**Figure 14 Startup with 3A load (Ch1:PVIN, Ch2: VOUT, Ch3: PG, Ch5: Enable, Ch8: IOUT)**_ 

**Page 18** 

**Rev 1.2, July 11, 2022** 

Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright© 2018–22 TDK Corporation. All rights reserved. All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice. 

## **FS1703 POL[™] µ** 

_**Figure 15 Shutdown with VCC UVLO at 3A load (Ch1: PVIN, Ch2: VOUT, Ch3: PG, Ch5: Enable, Ch8: IOUT**_ 

_**Figure 16 Soft turn off at 3A load (Ch1:PVIN, Ch2: VOUT, Ch3: PG, Ch5: Enable, Ch8: IOUT)**_ 

**Page 19** 

**Rev 1.2, July 11, 2022** 

Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright© 2018–22 TDK Corporation. All rights reserved. All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice. 

## **FS1703 POL[™] µ** 

_**Figure 17 Startup into pre-bias (Ch1: PVIN, Ch2: VOUT, Ch3: PG, Ch5: Enable, Ch8: IOUT)**_ 

**==> picture [21 x 10] intentionally omitted <==**

**----- Start of picture text -----**<br>
Bey<br>**----- End of picture text -----**<br>


_**Figure 18 Over-current protection and auto-recover to 3A**_ 

- _**(Ch1: PVIN, Ch2: VOUT, Ch3: PG, Ch5: Enable, Ch8: IOUT)**_ 

## **Rev 1.2, July 11, 2022** 

**Page 20** 

Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright© 2018–22 TDK Corporation. All rights reserved. All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice. 

## **FS1703 POL[™] µ** 

_**Figure 19 Sw and VOUT ripple at 0A (Ch2: VOUT Ripple, Ch4: Sw)**_ 

_**Figure 20 Sw and VOUT ripple at 3A (Ch2: VOUT Ripple, Ch4: Sw)**_ 

> Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright© 2018–22 TDK Corporation. All rights reserved. All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice. 

**Rev 1.2, July 11, 2022** 

**Page 21** 

## **FS1703 POL[™] µ** 

_**Figure 21 Transient response 0A to 1.5A (Ch2: VOUT  rIpple, Ch3: IOUT ), peak-peak deviation = 89mV**_ 

_**Figure 22 Thermal image (PVIN=5V, IOUT =3A) – maximum temperature rise = 30°C**_ 

> Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright© 2018–22 TDK Corporation. All rights reserved. All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice. 

**Rev 1.2, July 11, 2022** 

**Page 22** 

**FS1703 POL[™] µ** ~~ee~~ 

## **Thermal considerations** 

## **Layout recommendations** 

FS1703 is a highly integrated device with very few external components, which simplifies PCB layout. However, to achieve the best performance, these general PCB design guidelines should be followed: 

The FS1703 has been thermally tested and modelled in accordance with JEDEC specifications JESD 51-2A and JESD 51-8. It has been tested using a 4-layer application PCB, with thermal vias under the device to assist cooling (for details of the PCB, refer to the application notes). 

- Bypass capacitors, including input/output capacitors and the VCC bypass capacitor (if used), should be placed as close as possible to the FS1703 pins. 

The FS1703 has two significant sources of heat: 

   - The power MOSFET section of the IC 

- Output voltage should be sensed with a separated trace directly from the output capacitor. 

- The inductor 

The IC is well coupled to the PCB, which provides its primary cooling path. Although the inductor is also connected to the PCB, its primary cooling path is through convection. The cooling process for both heat sources is ultimately through convection. The PCB can be seen as a heat-spreader or, to some degree, a heat-sink. 

- Analog ground and power ground are connected through a single-point connection. 

- To aid thermal dissipation, the PGnd pad should be connected to the power ground plane using vias. Copper-filled vias are preferred but plated-through-hole vias are acceptable, provided that they are not filled with resin or covered with solder mask. 

Inductor Thermal Output 

**==> picture [433 x 168] intentionally omitted <==**

**----- Start of picture text -----**<br>
with resin or covered with solder mask.<br> Adequate numbers of vias should be used to<br>make connections between layers, especially<br>for the power traces.  Inductor<br> To minimize power losses and thermal<br>dissipation, wide copper polygons should be<br>used for input and output power connections.<br>IC<br>a<br>*<br>IC Thermal Output<br>Figure 23 Heat sources in the FS1703<br>**----- End of picture text -----**<br>


**Rev 1.2, July 11, 2022** 

**Page 23** 

Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright© 2018–22 TDK Corporation. All rights reserved. All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice. 

## **FS1703 POL[™] µ** 

Figure 24 shows the thermal resistances in the FS1703, where: 

- **ϴ** JA is the measure of natural convection from the assembled test sample within a confined enclosure of approximately 30x30x30cm. The air is passive within this environment and the only air movement is due to convection from the device on test. 

- **ϴ** JCbottom is the heat flow from the IC to the bottom of the package, to which it is well coupled. The testing method adopts the method outlined in JESD 51-8, where the test PCB is clamped between cold plates at defined distances from the device. 

- **ϴ** JCtop is theoretically the heat flow from the IC to the top of the package. This is not representative for the FS1703 for two reasons: firstly, it is not the primary conduction path of the IC and, more importantly, the inductor is positioned directly over the IC. As the inductor is a heat source, generating a similar amount of heat to the IC, a meaningful value for junction-to-case (top) cannot be derived. 

The values of the thermal resistances are: 

- **ϴ** JA = 22.6°C/W 

- **ϴ** JCbottom = 2.36°C/W 

Although these values indicate how the FS1703 compares with similar point-of-load products tested using the same conditions and specifications, they cannot be used to predict overall thermal performance. For accurate modeling of the µPOL™’s interaction with its environment, computational fluid dynamics (CFD) simulation software is needed to calculate combined routes of conduction and convection simultaneously. 

Note: In all tests, airflow has been considered as passive or static; applications using forced air may achieve a greater cooling effect. 

**==> picture [192 x 123] intentionally omitted <==**

**----- Start of picture text -----**<br>
Ambient<br>(top) Top-to-ambient<br>ϴ ϴ<br>JCtop topA<br>contribution] [low contribution]<br>PCB-<br>Junction- Bottom- |<br>to-case to-PCB to-ambient<br>(solder) (PCB)<br>ϴ<br>(bottom) |<br>FS1703 µPOL™ External<br>**----- End of picture text -----**<br>


_**Figure 24 Thermal resistances of the FS1703**_ 

**Page 24** 

**Rev 1.2, July 11, 2022** 

Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright© 2018–22 TDK Corporation. All rights reserved. All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice. 

## **FS1703 POL[™] µ** ~~Fo~~ 

## **Package description** 

The FS1703 is designed for use with standard surface-mount technology (SMT) population techniques. It has a positive (raised) footprint, with the pads being higher than the surrounding substrate. The finish on the pads is ENiG (Electroless Nickel Immersion Gold). 

As a result of these properties, the FS1703 works extremely well in lead-free environments. The surface wets easily and the positive footprint accommodates processing variations. 

Note: Refer to the Design Guidelines for more information about TDK’s µPOL™ package series, including importance guidance on checking the compatibility of manufacturing processes such as cleanable flux systems. 

**==> picture [379 x 387] intentionally omitted <==**

**----- Start of picture text -----**<br>
3.300<br>1.140<br>B= 0.360 =y<br>> 0.175 > 0.175<br>1.350 1.350<br>0.850 0.850 1 x (1.70 x 0.40)<br>All dimensions subject to +/- 0.100mm tolerance<br>1 x (0.30 x 0.70)<br>i Sa<br>1 x (1.10 x 0.30) 1.100 12 x (0.40 x 0.30)<br>0.700<br>LUy |<br>0.300<br>1 x (0.30 x 0.30)<br>> 0.250 > 0.250<br>0.750<br>3.300<br>0.750<br>> 0.250 > 0.250<br>yp.<br>0.550 T<br>1.325<br>0.825 1.375 0.750<br>1.750 1.470 +/- 0.150<br>0.575<br>0.925<br>**----- End of picture text -----**<br>


_**Figure 25 Dimensioned drawings**_ 

**Page 25** 

**Rev 1.2, July 11, 2022** 

Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright© 2018–22 TDK Corporation. All rights reserved. All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice. 

## **FS1703 POL[™] µ** 

**==> picture [357 x 506] intentionally omitted <==**

**----- Start of picture text -----**<br>
4.00±0.10 8.00±0.10 2.00±0.05<br>Ø1.50-1.60<br>p |<br>| Go 8 O/ S O| O | 4<br>3.60<br>Ø1.50min<br>Pin 1 oo Oo<br>0.30±0.05 3.60 1.80<br>—_— :<br>A<br>Reel capacity Reel diameter<br>(number of devices) (dimension A)<br>4000 330 ± 2.0<br>250 178 ± 1.0<br>qa ) t=<br>ey<br>2.0±0.2 8.5±0.03<br>i .<br>102±1.0<br>1.75±0.10<br>5.50±0.05<br>12.00±0.30<br>**----- End of picture text -----**<br>


## _**Figure 26 Tape and reel pack**_ 

**Page 26** 

## **Rev 1.2, July 11, 2022** 

Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright© 2018–22 TDK Corporation. All rights reserved. All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice. 

## **FS1703 POL[™] µ** ~~Fo~~ 

## **REMINDERS FOR USING THESE PRODUCTS** 

Before using these products, be sure to request the delivery specifications. 

## SAFETY REMINDERS 

Please pay sufficient attention to the warnings for safe designing when using these products. 

## **REMINDER** Po 

The products listed on this specification sheet are intended for use in general electric equipment (AV equipment, telecommunication equipment, home appliances, amusement equipment, computer equipment, personal equipment, office equipment, measurement equipment, industrial robots) under a normal condition and use condition. 

The products are not designed or warranted to meet the requirements of the applications listed below, whose performance and/or quality require a more stringent level of safety or reliability, or whose failure, malfunction or trouble could cause serious damage to sociality, person or property. Please understand that we are not responsible for any damage or liability caused by use of the products in any of the applications below or for any other use exceeding the range or conditions set forth in this specification sheet. 

1. Aerospace/Aviation equipment 

2. Transportation equipment (cars, electric trains, ships, etc.) 

3. Medical equipment 4. Power-generation control equipment 5. Atomic energy related equipment 6. Seabed equipment 7. Transportation control equipment 8. Public Information-processing equipment 9. Military equipment 10. Electric heating apparatus, burning equipment 11. Disaster prevention/crime prevention equipment 12. Safety equipment 13. Other applications that are not considered general-purpose applications 

When using this product in general-purpose application, you are kindly requested to take into consideration securing protection circuit/ equipment or providing backup circuits, etc., to ensure higher safety. 

**Page 27** 

**Rev 1.2, July 11, 2022** 

Patent Protected: US 9,729,059 B1; US 10,193,442 B2 Copyright© 2018–22 TDK Corporation. All rights reserved. All registered trademarks and trademarks are the property of their respective owners. Data and specifications subject to change without notice.