FDMS9620S

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May 2014<br>**----- End of picture text -----**<br>


## **FDMS9620S** 

# **Dual N-Channel PowerTrench[®] MOSFET Q1: 30V, 16A, 21.5m Q2: 30V, 18A, 13m** 

## **Features** 

Q1: N-Channel 

Max rDS(on) = 21.5m at VGS = 10V, ID = 7.5A Max rDS(on) = 29.5m at VGS = 4.5V, ID = 6.5A 

Q2: N-Channel 

Max rDS(on) = 13m at VGS = 10V, ID = 10A Max rDS(on) = 17m at VGS = 4.5V, ID = 8.5A Low Qg high side MOSFET 

Low r low side MOSFET DS(on) Thermally efficient dual Power 56 package Pinout optimized for simple PCB design RoHS Compliant 

## **General Description** 

This device includes two specialized MOSFETs in a unique dual Power 56 package.  It is designed to provide an optimal Synchronous Buck power stage in terms of efficiency and PCB utilization.  The low switching loss "High Side" MOSFET is complemented by a Low Conduction Loss  "Low Side"  SyncFET. 

## **Applications** 

Synchronous Buck Converter for: 

Notebook System Power 

General Purpose Point of Load 

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G1<br>D1<br>D1<br>D1 D1<br>S1/D2<br>G2<br>S2<br>S2<br>> S2<br>Power 56<br>**----- End of picture text -----**<br>


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S2 5 4 D1<br>S2 6 3 D1<br>S2 7 2 D1<br>G2 8 1 G1<br>**----- End of picture text -----**<br>


## **MOSFET Maximum Ratings** TA 

|**MOSFET Maximum Ratings**|**MOSFET Maximum Ratings**||||||||
|---|---|---|---|---|---|---|---|---|
|**MOSFET Maximum Ratings** TAA= 25°C unless otherwise noted|||||||||
|**Symbol**<br>**Parameter**||||**Q1**|||**Q2**|**Units**|
|VDS<br>Drain to Source Voltage||||30|||30|V|
|VGS<br>Gate to Source Voltage||||±20||±20||V|
|C = 25°C<br>Drain Current      -Continuous<br>T||||16|||18||
|ID<br>-Continuous                               TA = 25°C||= 25°C(Note 1a)||7.5|||10|A|
|-Pulsed||||60|||60||
|PD<br>Power Dissipation  for Single Operation                TA = 25°C<br>TA = 25°C||= 25°C(Note 1a)<br>= 25°C(Note 1b)|||2.5<br>1|||W|
|TJ, TSTG<br>Operatingand Storage Junction Temperature Range||||-55 to +150|-55 to +150|-55 to +150||°C|
|**Thermal Characteristics**|||||||||
|R JC<br>Thermal Resistance, Junction to Case|Thermal Resistance, Junction to Case|Thermal Resistance, Junction to Case||8.2|||3.1||
|R JA<br>Thermal Resistance, Junction to Ambient|Thermal Resistance, Junction to Ambient|Thermal Resistance, Junction to Ambient(Note 1a)|||50|||°C/W|
|R JA<br>Thermal Resistance, Junction to Ambient                                                 (Note 1b)|Thermal Resistance, Junction to Ambient                                                 (Note 1b)|Thermal Resistance, Junction to Ambient                                                 (Note 1b)|||120||||
|**Package Marking and Ordering Information**|||||||||
|**Device Marking**<br>**Device**<br>**Package**<br>FDMS9620S<br>FDMS9620S<br>Power 56<br>~~[[_i~~|~~i~~|**Reel Size**<br>13”<br>~~i~~|~~i~~|**Tape Width**<br>12mm<br>~~i~~|||**Quantity**<br>3000 units<br>~~i~~||



**1** 

©2007 Fairchild Semiconductor Corporation FDMS9620S Rev.D3 

www.fairchildsemi.com 

## **Electrical Characteristics** TJ = 25°C unless otherwise noted 

|**Electrica**|**l Characteristics**TJ= 25°C un|less otherwise noted||||||
|---|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test Conditions**|**Type**|**Min**|**Typ**|**Max**|**Units**|
|**Off Characteristics**||||||||
|BVDSS|Drain to Source Breakdown Voltage|ID= 250�A, VGS= 0V<br>ID= 1mA, VGS= 0V|Q1<br>Q2|30<br>30|||V|
|�BVDSS<br>�TJ|Breakdown Voltage Temperature<br>Coefficient|ID= 250�A, referenced to 25°C<br>ID= 1mA, referenced to 25°C|Q1<br>Q2||23<br>23||mV/°C|
|IDSS|Zero Gate Voltage Drain Current|VDS= 24V,   VGS= 0V|Q1<br>Q2|||1<br>500|�A|
|IGSS|Gate to Source Leakage Current|VGS= ±20V, VDS= 0V|Q1<br>Q2|||±100<br>±100|nA|
|**On Characteristics**||||||||
|VGS(th)|Gate to Source Threshold Voltage|VGS= VDS,  ID= 250�A<br>VGS= VDS,  ID= 1mA|Q1<br>Q2|1<br>1|1.6<br>1.6|3<br>3|V|
|�VGS(th)<br>�TJ|Gate to Source Threshold Voltage<br>Temperature Coefficient|ID= 250�A, referenced to 25°C<br>ID= 1mA, referenced to 25°C|Q1<br>Q2||-4<br>-4||mV/°C|
|rDS(on)|Drain to Source On Resistance|VGS= 10V,  ID= 7.5A<br>VGS= 4.5V,  ID= 6.5A<br>VGS= 10V,  ID= 7.5A , TJ= 125°C|<br>Q1||18<br>23<br>25|21.5<br>29.5<br>32|m�|
|||VGS= 10V,  ID= 10A<br>VGS= 4.5V,  ID= 8.5A<br>VGS= 10V,  ID= 10A , TJ= 125°C|Q2||9<br>13<br>14|13<br>17<br>22||
|gFS|Forward Transconductance|VDD= 10V,  ID= 7.5A<br>VDD= 10V,  ID= 10A|Q1<br>Q2||25<br>27||S|
|**Dynamic Characteristics**||||||||
|Ciss|Input Capacitance|VDS= 15V, VGS= 0V, f = 1MHZ|Q1<br>Q2||500<br>700|665<br>935|pF|
|Coss|Output Capacitance||Q1<br>Q2||100<br>500|135<br>665|pF|
|Crss|Reverse Transfer Capacitance||Q1<br>Q2||65<br>100|100<br>150|pF|
|Rg|Gate Resistance|f = 1MHz|Q1<br>Q2||0.9<br>1.8||�|
|**Switching Characteristics**||||||||
|td(on)|Turn-On Delay Time|VDD= 15V, ID= 1A,<br>VGS= 10V, RGEN= 6�|Q1<br>Q2||11<br>15|20<br>27|ns|
|tr|Rise Time||Q1<br>Q2||7<br>13|14<br>24|ns|
|td(off)|Turn-Off Delay Time||Q1<br>Q2||23<br>27|37<br>44|ns|
|tf|Fall Time||Q1<br>Q2||2.3<br>7|10<br>14|ns|
|Qg|Total Gate Charge|Q1<br>VDD= 15V, VGS= 10V ,ID= 7.5A<br>Q2<br>VDD= 15V, VGS= 10V ,ID= 10A|Q1<br>Q2||10<br>18|14<br>25|nC|
|Qgs|Gate to Source Gate Charge||Q1<br>Q2||1.7<br>2.8||nC|
|Qgd|Gate to Drain “Miller” Charge||Q1<br>Q2||2.0<br>3.6||nC|



©2007 Fairchild Semiconductor Corporation FDMS9620S Rev.D3 

www.fairchildsemi.com 

**2** 

**Electrical Characteristics** TJ = 25°C unless otherwise noted 

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a Symbol Parameter Test Conditions Type Min Typ Max Units<br>Drain-Source Diode Characteristics<br>Q1 2.1<br>IS Maximum Continuous Drain-Source Diode Forward Current Q2 3.5 A<br>Pt<br>Q1 0.7 1.2<br>ee VSD Source to Drain Diode  Forward Voltage V [V][GS] GS [ = 0V, I] = 0V, I [S] S [ = 2.1A           (Note 2)] = 3.5A           (Note 2) Q2 0.5 1.0 V<br>Q1 Q1 13<br>a trr Reverse Recovery Time IF = 7.5A, di/dt = 100A/ » s Et Q2 14 ns<br>Q2 Q1 4<br>a Qrr Reverse Recovery Charge IF = 10A, di/dt = 300A/ s Q2 | 9 tT ty nC<br>ee eeee<br>**----- End of picture text -----**<br>


## **Notes:** 

- **1:** R JA is determined with the device mounted on a 1in[2] pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R JC is guaranteed by design while R CA is determined by the user's board design. 

a.50°C/W when mounted  on b. 120°C/W when mounted on  a a 1 in[2] pad of  2 oz  copper minimum pad of 2 oz copper 

- **2:** Pulse Test: Pulse Width < 300 s, Duty cycle < 2.0%. 

©2007 Fairchild Semiconductor Corporation FDMS9620S Rev.D3 

www.fairchildsemi.com 

**3** 

## **Typical Characteristics (Q1 N-Channel)** TJ = 25°C unless otherwise noted 

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60 2.8<br>50 VGS = 10V VGS = 6V 2.6 PULSE DURATION = 300DUTY CYCLE = 2.0%MAX � s<br>2.4<br>40 VGS = 4.5V 2.2 V GS  =3.5V<br>VGS = 4V 2.0 VGS = 4V V GS  = 4.5V<br>30 1.8<br>1.6 VGS = 6V<br>20 VGS = 3.5V 1.4<br>10 PULSE DURATION = 300 � s 1.2<br>DUTY CYCLE = 2.0%MAX<br>1.0 V GS = 10V<br>0 0.8<br>0 1 2 3 4 0 10 20 30 40 50 60<br>VDS, DRAIN TO SOURCE VOLTAGE (V) ID, DRAIN CURRENT(A)<br>Figure 1.  On Region Characteristics Figure 2.  Normalized On-Resistance<br>vs Drain Current and Gate Voltage<br>1.6<br>70<br>1.5 V IDGS = 7.5A =10V ID = 3.8A PULSE DURATION = 300DUTY CYCLE = 2.0%MAX � s<br>1.4 60<br>1.3<br>50<br>1.2<br>1.1 40<br>TJ = 125 [o] C<br>1.0<br>30<br>0.9<br>0.8 20<br>TJ = 25 [o] C<br>0.7<br>-50 -25 0 25 50 75 100 125 150 10<br>2 4 6 8 10<br>TJ, JUNCTION TEMPERATURE ( [o] C)<br>VGS, GATE TO SOURCE VOLTAGE (V)<br>Figure 3.  Normalized  On  Resistance                                         Figure 4.   On-Resistance vs  Gate to<br>vs Junction Temperature Source Voltage<br>40 60<br>PULSE DURATION = 300 � s V GS = 0V<br>DUTY CYCLE = 2.0%MAX 10<br>30 VDD = 5V<br>1 TJ = 125 [o] C<br>20<br>0.1 TJ = 25 [o] C<br>TJ =125 [o] C<br>10<br>TJ = 25 [o] C 0.01<br>TJ = -55 [o] C<br>TJ = -55 [o] C<br>0 0.001<br>1 2 3 4 5 0.2 0.4 0.6 0.8 1.0 1.2 1.4<br>VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V)<br>Figure 5.  Transfer Characteristics Figure 6.    Source to Drain  Diode<br>Forward Voltage vs Source Current<br>NORMALIZED<br>DRAIN CURRENT (A)<br>ID,<br>DRAIN TO SOURCE ON-RESISTANCE<br>)<br>�<br>m<br>(<br>DRAIN TO<br>NORMALIZED<br>rDS(on),<br>SOURCE ON-RESISTANCE<br> DRAIN TO SOURCE ON-RESISTANCE<br> DRAIN CURRENT (A)I,D<br>REVERSE DRAIN CURRENT (A)<br>IS,<br>**----- End of picture text -----**<br>


©2007 Fairchild Semiconductor Corporation FDMS9620S Rev.D3 

www.fairchildsemi.com 

**4** 

## **Typical Characteristics (Q1 N-Channel)** TJ = 25°C unless otherwise noted 

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10 1000<br>ID = 7.5A<br>VDD =10V<br>8<br>Ciss<br>VDD = 15V<br>6<br>Coss<br>4 VDD = 20V<br>100<br>2 f = 1MHz<br>VGS = 0V C rss<br>0 30<br>0 2 4 6 8 10 12 0.1 1 10 30<br>Qg, GATE CHARGE(nC) VDS, DRAIN TO SOURCE VOLTAGE (V)<br>Figure 7.  Gate Charge Characteristics Figure 8.  Capacitance vs Drain<br>to Source Voltage<br>100 100<br>VGS = 10V<br>10<br>1ms 10<br>1 SINGLE PULSE<br>TJ = MAX RATE 10ms<br>R � JA  = 120oC 100ms<br>o SINGLE PULSE<br>0.1 TA = 25 C 1s<br>THIS AREA IS LIMITED 10s 1 R � JA = 120 [o] C/W<br> BY r DS(ON)  DC TA= 25 [o] C<br>0.010.1 1 10 100 0.510-3 10-2 10-1 1 10 100 1000<br>VDS, DRAIN to SOURCE VOLTAGE (V) t, PULSE WIDTH (sec)<br>Figure 9.  Forward Bias Safe                                                               Figure 10.     Single  Pulse Maximum<br>Operating Area  Power  Dissipation<br>2<br>1<br>DUTY CYCLE-DESCENDING ORDER<br>D = 0.5<br>      0.2<br>      0.1<br>      0.05<br>      0.02 PDM<br>0.1       0.01<br>t1<br>t 2<br>SINGLE PULSE NOTES:<br>DUTY FACTOR: D = t1/t2<br>R � JA = 120 [o] C/W PEAK TJ = PDM x Z �JA  x R �JA  + TA<br>0.01<br>10-3 10-2 10-1 1 10 100 1000<br>t, RECTANGULAR PULSE DURATION (sec)<br>Figure 11.  Transient Thermal Response Curve<br>CAPACITANCE (pF)<br>GATE TO SOURCE VOLTAGE(V)<br>GS,<br>V<br>DRAIN CURRENT (A)<br>ID, PEAK TRANSIENT POWER (W)<br>P)(PK,<br>IMPEDANCE, ZJA �<br>NORMALIZED THERMAL<br>**----- End of picture text -----**<br>


www.fairchildsemi.com 

©2007 Fairchild Semiconductor Corporation FDMS9620S Rev.D3 

**5** 

## **Typical Characteristics (Q2 SyncFET)** 

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60 2.8<br>50 VGS = 10V VGS = 4.5V VGS = 4V 2.6 VGS =3.5V PULSE DURATION = 300DUTY CYCLE = 2.0%MAX � s<br>2.4<br>40 V GS = 6V 2.2<br>2.0 VGS = 4V<br>30 VGS = 3.5V 1.8 VGS = 4.5V<br>1.6<br>20<br>1.4 V GS  = 6V<br>1.2<br>10<br>PULSE DURATION = 300DUTY CYCLE = 2.0%MAX � s 1.0 VGS = 10V<br>0 0.8<br>0.0 0.5 1.0 1.5 2.0 2.5 0 10 20 30 40 50 60<br>VDS, DRAIN TO SOURCE VOLTAGE (V) ID, DRAIN CURRENT(A)<br>Figure 12. On-Region Characteristics Figure 13. Normalized on-Resistance vs Drain<br>Current and Gate  Voltage<br>1.8 60<br> ID = 10A PULSE DURATION = 300 � s<br>1.6 V GS =10V 50 ID = 5A DUTY CYCLE = 2.0%MAX<br>1.4 40<br>1.2 30<br>TJ = 125 [o] C<br>1.0 20<br>0.8 10<br>TJ = 25 [o] C<br>0.6 0<br>-50 -25 0 25 50 75 100 125 150 2 4 6 8 10<br>TJ, JUNCTION TEMPERATURE ( [o] C) VGS, GATE TO SOURCE VOLTAGE (V)<br>Figure 14. Normalized On-Resistance  Figure 15. On-Resistance vs Gate to<br>vs Junction Temperature Source Voltage<br>60 10<br>PULSE DURATION = 300 � s VGS = 0V<br>50 DUTY CYCLE = 2.0%MAX<br>VDD = 5V 1<br>40 TJ = 125 [o] C<br>30 0.1<br>TJ = 25 [o] C<br>20 TJ =125 [o] C<br>0.01<br>10 T J = 25 [o] C<br>T J  = -55 [o] C<br>TJ = -55 [o] C<br>0 0.001<br>1 2 3 4 5 0.0 0.2 0.4 0.6 0.8<br>VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V)<br>NORMALIZED<br>DRAIN CURRENT (A)<br>ID,<br>DRAIN TO SOURCE ON-RESISTANCE<br>)<br>�<br>m<br>(<br>DRAIN TO<br>,<br>NORMALIZED rDS(on)<br>SOURCE ON-RESISTANCE<br> DRAIN TO SOURCE ON-RESISTANCE<br>, DRAIN CURRENT (A)<br>ID<br>REVERSE DRAIN CURRENT (A)<br>IS,<br>**----- End of picture text -----**<br>


**Figure 16. Transfer Characteristics** 

**Figure 17. Source to Drain Diode Forward Voltage vs Source Current** 

©2007 Fairchild Semiconductor Corporation FDMS9620S Rev.D3 

www.fairchildsemi.com 

**6** 

## **Typical Characteristics** 

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10<br>ID = 10A<br>VDD =10V<br>8<br>6 V DD  = 15V<br>4 V DD  = 20V<br>2<br>0<br>0 4 8 12 16 20<br>Qg, GATE CHARGE(nC)<br>, GATE TO SOURCE VOLTAGE(V)<br>GS<br>V<br>**----- End of picture text -----**<br>


**Figure 18. Gate Charge Characteristics** 

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2000<br>1000 Ciss<br>Coss<br>100 f = 1MHz<br>VGS = 0V C rss<br>50<br>0.1 1 10 30<br>VDS, DRAIN TO SOURCE VOLTAGE (V)<br>CAPACITANCE (pF)<br>**----- End of picture text -----**<br>


**Figure 19. Capacitance vs Drain to Source Voltage** 

©2007 Fairchild Semiconductor Corporation FDMS9620S Rev.D3 

www.fairchildsemi.com 

**7** 

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## ~~—~~ 

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## **PRODUCT STATUS DEFINITIONS** 

**Definition of Terms** 

|**Datasheet Identification**|**Product Status**|**Definition**|
|---|---|---|
|Advance Information|Formative / In Design|Datasheet contains the design specifications for product development. Specifications may change<br>in anymanner without notice.|
|Preliminary|First Production|Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild<br>Semiconductor reserves the right to make changes at anytime without notice to improve design.|
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Rev. I77 

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