FDMC8200

## **Is Now Part of** 

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## **FDMC8200** 

## **Dual N-Channel PowerTrench[®] MOSFET 30 V, 9.5 m** Ω and **20 m** Ω 

## **Features General Description** 

Q1: N-Channel 

Max rDS(on) = 20 mΩ at VGS = 10 V, ID = 6 A Max rDS(on) = 32 mΩ at VGS = 4.5 V, ID = 5 A 

- Q2: N-Channel 

Max rDS(on) = 9.5 mΩ at VGS = 10 V, ID = 9 A Max rDS(on) = 13.5 mΩ at VGS = 4.5 V, ID = 7 A RoHS Compliant 

This device includes two specialized N-Channel MOSFETs in a dual Power33 (3mm x 3mm MLP) package.  The switch node has been internally connected to enable easy placement and routing of synchronous buck converters.   The control MOSFET (Q1) and synchronous MOSFET (Q2) have been designed to provide optimal power efficiency. 

## **Applications** 

Mobile Computing 

Mobile Internet Devices 

General Purpose Point of Load 

|**G2**<br>**D1**<br>**S2**<br>**S2**<br>**S2**<br>**D1**<br>**G1 D1**<br>**D1**<br>**D2/S1**<br>**Pin 1**<br>**VIN**<br>**SWITCH NODE**<br>**GLS**<br>**VIN**<br>**GND GND GND**<br>**GHS VIN**<br>**VIN**||**G2**<br>**S2**<br>**S2**<br>**S2**|**5**<br>**6**<br>**7**<br>**8**<br>**Q1**<br>**Q2**|**5**<br>**6**<br>**7**<br>**8**<br>**Q1**<br>**Q2**|**5**<br>**6**<br>**7**<br>**8**<br>**Q1**<br>**Q2**|**4**<br>**3**<br>**2**<br>**1**|**G1**<br>**D1**<br>**D1**<br>**D1**|**G1**<br>**D1**<br>**D1**<br>**D1**|
|---|---|---|---|---|---|---|---|---|
|**BOTTOM**<br>**BOTTOM**|||||||||
|**Power 33**|||||||||
|**MOSFET Maximum Ratings  **TC= 25 °C unless otherwise noted|||||||||
|**Symbol**<br>**Parameter**|||**Q1**||**Q2**|**Units**|||
|VDS<br>Drain to Source Voltage|||30||30|V|||
|VGS<br>Gate to Source Voltage   (Note 3)|||±20||±20|V|||
|Drain Current - Continuous(Package limited)TC = 25 °C|||18||18||||
|ID<br>- Continuous(Silicon limited)TC = 25 °C<br>- Continuous                                                                       TA= 25 °C|||23<br>81a||45<br>121b|A|||
|- Pulsed|||40||40||||
|PD<br>Power Dissipation                                                                                       TA= 25 °C<br>Power Dissipation                                                                                       TA= 25 °C|||1.91a<br>0.71c||2.21b<br>0.91d|W|||
|TJ, TSTG<br>Operatingand Storage Junction Temperature Range|||-55 to +150||-55 to +150|°C|||
|**Thermal Characteristics**|||||||||
|RθJA<br>Thermal Resistance, Junction to Ambient<br>651a<br>551b<br>°C/W<br>RθJA<br>Thermal Resistance, Junction to Ambient<br>1801c<br>1451d<br>RθJC<br>Thermal Resistance, Junction to Case<br>7.5<br>4<br>~~————~~|||||||||
|**Package Marking and Ordering Information**|||||||||
|**Device Marking**<br>**Device**<br>**Package**<br>**Reel Size**<br>**Tape Width**<br>**Quantity**<br>FDMC8200<br>FDMC8200<br>Power 33<br>13 ”<br>12 mm<br>3000 units<br>~~ee~~|||||||||



©2009 Fairchild Semiconductor Corporation **1** www.fairchildsemi.com 

FDMC8200  Rev.A2 

## **Electrical Characteristics** TJ = 25 °C unless otherwise noted 

|**Electrica**|**l Characteristics **TJ= 25 °C u|nless otherwise noted||||||
|---|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test Conditions**|**Type**|**Min**|**Typ**|**Max**|**Units**|
|**Off Characteristics**||||||||
|BVDSS|Drain to Source Breakdown Voltage|ID= 250μA, VGS= 0 V<br>ID= 250μA, VGS= 0 V|Q1<br>Q2|30<br>30|||V|
|ΔBVDSS<br>ΔTJ|Breakdown Voltage Temperature<br>Coefficient|ID= 250μA, referenced to 25 °C<br>ID= 250μA, referenced to 25 °C|Q1<br>Q2||14<br>14||mV/°C|
|IDSS|Zero Gate Voltage Drain Current|VDS= 24 V,  VGS= 0 V<br>VDS= 24 V,  VGS = 0 V|Q1<br>Q2|||1<br>1|μA|
|IGSS|Gate to Source Leakage Current|VDS= 20 V,  VGS= 0 V|Q1<br>Q2|||100<br>100|nA<br>nA|
|**On Characteristics**||||||||
|VGS(th)|Gate to Source Threshold Voltage|VGS= VDS,  ID= 250μA<br>VGS= VDS,  ID= 250μA|Q1<br>Q2|1.0<br>1.0|2.3<br>2.3|3.0<br>3.0|V|
|ΔVGS(th)<br>ΔTJ|Gate to Source Threshold Voltage<br>Temperature Coefficient|ID= 250μA, referenced to 25 °C<br>ID= 250μA, referenced to 25 °C|Q1<br>Q2||-5<br>-6||mV/°C|
|rDS(on)|Static Drain to Source On Resistance|VGS= 10 V,  ID= 6 A<br>VGS= 4.5 V,  ID= 5 A<br>VGS= 10 V,  ID= 6 A, TJ = 125 °C|Q1||16<br>24<br>22|20<br>32<br>28|mΩ|
|||VGS= 10 V,  ID= 9 A<br>VGS= 4.5 V,  ID= 7 A<br>VGS= 10 V,  ID= 9 A, TJ = 125 °C|Q2||7.3<br>9.5<br>10|9.5<br>13.5<br>13||
|gFS|Forward Transconductance|VDD= 5 V,  ID= 6 A<br>VDD= 5 V,  ID= 9 A|Q1<br>Q2||29<br>56||S|
|**Dynamic Characteristics**||||||||
|Ciss|Input Capacitance|VDS= 15 V, VGS= 0 V, f = 1 MHZ|Q1<br>Q2||495<br>1180|660<br>1570|pF|
|Coss|Output Capacitance||Q1<br>Q2||145<br>330|195<br>440|pF|
|Crss|Reverse Transfer Capacitance||Q1<br>Q2||20<br>30|30<br>45|pF|
|Rg|Gate Resistance||Q1<br>Q2||1.4<br>1.4||Ω|
|**Switching Characteristics**||||||||
|td(on)|Turn-On Delay Time|Q1<br>VDD= 15 V, ID= 1 A,<br>VGS= 10 V, RGEN= 6Ω<br>Q2<br>VDD= 15 V, ID= 1 A,<br>VGS= 10 V, RGEN= 6Ω|Q1<br>Q2||11<br>13|20<br>23|ns|
|tr|Rise Time||Q1<br>Q2||3.1<br>4|10<br>10|ns|
|td(off)|Turn-Off Delay Time||Q1<br>Q2||35<br>38|56<br>60|ns|
|tf|Fall Time||Q1<br>Q2||1.3<br>6|10<br>12|ns|
|Qg(TOT)|Total Gate Charge|VGS= 0 V  to 10 V|Q1<br>Q2||7.3<br>16|10<br>22|nC|
|Qg(TOT)|Total Gate Charge|VGS= 0 V  to 4.5 V|Q1<br>Q2||3.1<br>7|4.3<br>10|nC|
|Qgs|Gate to Source  Charge||Q1<br>Q2||1.8<br>4.1||nC|
|Qgd|Gate to Drain “Miller” Charge||Q1<br>Q2||1<br>1.5||nC|



©2009 Fairchild Semiconductor Corporation **2** www.fairchildsemi.com FDMC8200  Rev.A2 

## **Electrical Characteristics** TJ = 25 °C unless otherwise noted ~~aGG~~ **Symbol Parameter Test Conditions Type Min Typ Max Units Drain-Source Diode Characteristics** 

|VSD|Source to Drain Diode  Forward Volt-<br>age|VGS= 0 V, IS= 6 A (Note 2)<br>VGS = 0 V, IS = 9 A  (Note 2)|Q1<br>Q2||0.8<br>0.8|1.2<br>1.2|V|
|---|---|---|---|---|---|---|---|
|trr|Reverse Recovery Time|Q1<br>IF= 6 A, di/dt = 100 A/s<br>Q2<br>IF= 9 A, di/dt = 100 A/s|Q1<br>Q2||13<br>21|24<br>34|ns|
|Qrr|Reverse Recovery Charge||Q1<br>Q2||2.3<br>5.6|10<br>12|nC|



Notes: 

1. Rθ **JA** is determined with the device mounted on a 1in[2] pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. Rθ **JC** is guaranteed by design while Rθ **CA** is determined by  the user's board design. 

a.65 °C/W when mounted on b.55 °C/W when mounted on a 1 in[2  ] pad of  2 oz  copper a 1 in[2  ] pad of  2 oz  copper 

c. 180 °C/W when mounted on  a minimum pad of 2 oz copper 

d. 145 °C/W when mounted on  a minimum pad of 2 oz copper 

2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%. 

3. As an N-ch device, the negative Vgs rating is for  low duty cycle pulse ocurrence only. No continuous rating is implied. 

©2009 Fairchild Semiconductor Corporation **3** www.fairchildsemi.com FDMC8200  Rev.A2 

## **Typical Characteristics (Q1 N-Channel)** TJ = 25 °C unless otherwise noted 

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40 4<br>VGS = 10 V PULSE DURATION = 80  μ s<br>VGS =  6 V DUTY CYCLE = 0.5% MAX<br>30 V GS  = 4.5 V 3<br>VGS = 3.5 V<br>VGS = 4 V<br>20 2<br>VGS =  4 V VGS = 4.5 V<br>10 1<br>VGS = 3.5 V PULSE DURATION = 80  μ s VGS = 6 V VGS = 10 V<br>DUTY CYCLE = 0.5% MAX<br>0 0<br>0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 10 20 30 40<br>VDS, DRAIN TO SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)<br>Figure 1.  On Region Characteristics Figure 2.  Normalized On-Resistance<br>vs Drain Current and Gate Voltage<br>1.6 100<br>ID = 6 A PULSE DURATION = 80  μ s<br>VGS = 10 V DUTY CYCLE = 0.5% MAX<br>80<br>1.4<br>ID = 6 A<br>60<br>1.2<br>TJ = 125  [o] C<br>40<br>1.0<br>20<br>TJ = 25 [ o] C<br>0.8 0<br>-75 -50 -25 0 25 50 75 100 125 150 2 4 6 8 10<br>TJ, JUNCTION TEMPERATURE ( [o] C) VGS, GATE TO SOURCE VOLTAGE (V)<br>Figure 3.  Normalized  On  Resistance                                         Figure 4.   On-Resistance vs  Gate to<br>vs Junction Temperature Source Voltage<br>40 40<br>PULSE DURATION = 80  μ s VGS = 0 V<br>DUTY CYCLE = 0.5% MAX 10<br>30<br>VDS = 5 V 1<br>TJ = 150  [o] C<br>20<br>TJ = 150 [ o] C 0.1 TJ = 25 [ o] C<br>TJ = 25 [ o] C<br>10<br>0.01<br>TJ = -55 [o] C<br>TJ = -55  [o] C<br>0 0.001<br>2.0 2.5 3.0 3.5 4.0 4.5 0.2 0.4 0.6 0.8 1.0 1.2<br>VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V)<br>NORMALIZED<br>DRAIN CURRENT (A)<br>,<br>ID<br>DRAIN TO SOURCE ON-RESISTANCE<br>)<br>Ω<br>m<br>(<br>DRAIN TO<br>NORMALIZED rDS(on),<br>SOURCE ON-RESISTANCE<br> DRAIN TO SOURCE ON-RESISTANCE<br>, DRAIN CURRENT (A)<br>ID<br>, REVERSE DRAIN CURRENT (A)<br>IS<br>**----- End of picture text -----**<br>


**Figure 5.  Transfer Characteristics** 

**Figure 6. Forward Voltage vs Source Current** 

©2009 Fairchild Semiconductor Corporation **4** www.fairchildsemi.com FDMC8200  Rev.A2 

## **Typical Characteristics (Q1 N-Channel)** TJ = 25 °C unless otherwise noted 

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10 1000<br>ID = 6 A Ciss<br>8<br>VDD = 15 V VDD = 20 V Coss<br>6<br>VDD = 10 V 100<br>4<br>2 Crss<br>f = 1 MHz<br>VGS = 0 V<br>0 10<br>0 2 4 6 8 0.1 1 10 30<br>Qg, GATE CHARGE (nC) VDS, DRAIN TO SOURCE VOLTAGE (V)<br>Figure 7.  Gate Charge Characteristics Figure 8.  Capacitance vs Drain<br>to Source Voltage<br>100<br>25<br>R θ JC = 7.5 oC/W<br>10 100 us 20<br>1 ms VGS = 10 V<br>1 15<br>10 ms<br>THIS AREA IS  Limited by Package<br>100 ms<br>0.1 LIMITED BY r DS(on) 1 s 10<br>SINGLE PULSE 10 s VGS = 4.5 V<br>T J = MAX RATED DC<br>0.01 R θ JA = 180  [o] C/W 5<br>TA = 25  [o] C<br>0.001 0<br>0.01 0.1 1 10 100200 25 50 75 100 125 150<br>VDS, DRAIN to SOURCE VOLTAGE (V) Tc, CASE TEMPERATURE (oC)<br>Figure 9.  Forward Bias Safe                                      Figure 10.  Maximum Continuous Drain Current<br>Operating Area vs Case Temperature<br>300<br>SINGLE PULSE<br>VGS = 10 V<br>100 R θ JA  = 180  [o] C/W<br>TA = 25  [o] C<br>10<br>1<br>0.5<br>10-4 10-3 10-2 10-1 1 10 100 1000<br>t, PULSE WIDTH (s)<br>CAPACITANCE (pF)<br>, GATE TO SOURCE VOLTAGE (V)<br>GS<br>V<br>DRAIN CURRENT (A)<br>, DRAIN CURRENT (A)ID I, D<br>, PEAK TRANSIENT POWER (W)<br>(PK)<br>P<br>**----- End of picture text -----**<br>


**Figure 11.  Single Pulse Maximum Power Dissipation** 

©2009 Fairchild Semiconductor Corporation **5** www.fairchildsemi.com FDMC8200  Rev.A2 

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Typical Characteristics (Q1 N-Channel)  TJ = 25 °C unless otherwise noted<br>2<br>DUTY CYCLE-DESCENDING ORDER<br>1<br>D = 0.5<br>      0.2<br>      0.1<br>      0.05<br>0.1       0.02 PDM<br>      0.01<br>t1<br>t 2<br>0.01 SINGLE PULSE R θ JA = 180  [o] C/W NOTES: DUTY FACTOR: D = tPEAK TJ = PDM x Z θJA 1 x R/t2 θJA  + TA<br>0.003<br>10-4 10-3 10-2 10-1 1 10 100 1000<br>t, RECTANGULAR PULSE DURATION (sec)<br>Z JA θ<br>IMPEDANCE,<br>NORMALIZED THERMAL<br>**----- End of picture text -----**<br>


**Figure 12.  Junction-to-Ambient Transient Thermal Response Curve** 

©2009 Fairchild Semiconductor Corporation **6** www.fairchildsemi.com FDMC8200  Rev.A2 

## **Typical Characteristics (Q2 N-Channel)** TJ = 25 °C unless otherwise noted 

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40 6<br>VGS =  10 V PULSE DURATION = 80  μ s<br>DUTY CYCLE = 0.5% MAX<br>5<br>30 VGS = 3 V<br>VGS = 4.5 V 4<br>VGS =  4 V VGS =  3.5 V<br>20 3<br>VGS = 3.5 V 2 VGS = 4 V VGS = 4.5 V<br>10<br>1<br>PULSE DURATION = 80  μ s<br>VGS = 3 V DUTY CYCLE = 0.5% MAX VGS =  10 V<br>0 0<br>0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 10 20 30 40<br>VDS, DRAIN TO SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)<br>Figure 13. On-Region Characteristics Figure 14. Normalized on-Resistance vs Drain<br>Current and Gate  Voltage<br>1.6 60<br>ID = 9 A PULSE DURATION = 80  μ s<br>VGS = 10 V 50 DUTY CYCLE = 0.5% MAX<br>1.4<br>ID = 9 A<br>40<br>1.2<br>30<br>1.0<br>20<br>TJ = 125  [o] C<br>0.8<br>10<br>TJ = 25 [ o] C<br>0.6 0<br>-75 -50 -25 0 25 50 75 100 125 150 2 4 6 8 10<br>TJ, JUNCTION TEMPERATURE ( [o] C) VGS, GATE TO SOURCE VOLTAGE (V)<br>Figure 15. Normalized On-Resistance  Figure 16. On-Resistance vs Gate to<br> vs Junction Temperature Source Voltage<br>40 40<br>PULSE DURATION = 80  μ s 10 VGS = 0 V<br>DUTY CYCLE = 0.5% MAX<br>30<br>VDS = 5 V 1 TJ = 150  [o] C<br>20<br>0.1 TJ = 25 [ o] C<br>TJ = 150 [ o] C<br>TJ = 25 [ o] C<br>10<br>0.01 TJ = -55 [ o] C<br>TJ = -55  [o] C<br>0 0.001<br>1.5 2.0 2.5 3.0 3.5 4.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2<br>VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V)<br>NORMALIZED<br>DRAIN CURRENT (A)<br>,<br>ID<br>DRAIN TO SOURCE ON-RESISTANCE<br>)<br>Ω<br>m<br>(<br>DRAIN TO<br>NORMALIZED rDS(on),<br>SOURCE ON-RESISTANCE<br> DRAIN TO SOURCE ON-RESISTANCE<br>, DRAIN CURRENT (A)<br>ID<br>, REVERSE DRAIN CURRENT (A)<br>IS<br>**----- End of picture text -----**<br>


**Figure 17. Transfer Characteristics** 

**Figure 18. Source to Drain Diode Forward Voltage vs Source Current** 

©2009 Fairchild Semiconductor Corporation **7** www.fairchildsemi.com FDMC8200  Rev.A2 

**Typical Characteristics (Q2 N-Channel)** TJ = 25 °C unless otherwise noted 

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10 2000<br>ID = 9 A Ciss<br>1000<br>8<br>VDD = 15 V Coss<br>6<br>VDD = 10 V VDD = 20 V<br>100<br>4<br>Crss<br>2<br>f = 1 MHz<br>VGS = 0 V<br>0 10<br>0 3 6 9 12 15 18 0.1 1 10 30<br>Qg, GATE CHARGE (nC) VDS, DRAIN TO SOURCE VOLTAGE (V)<br>Figure 19. Gate Charge Characteristics Figure  20.   Capacitance vs Drain<br>to Source Voltage<br>100 50<br>VGS = 10 V R θ JC = 4 oC/W<br>100 us 40<br>10<br>1 ms 30<br>1 THIS AREA IS  10 ms VGS = 4.5 V<br>LIMITED BY rDS(on) 20<br>100 ms<br>SINGLE PULSE<br>0.1 TJ = MAX RATED 1 s 10 Limited by Package<br>R θ JA = 145  [o] C/W 10 s<br>TA = 25  [o] C DC<br>0.01 0<br>0.01 0.1 1 10 100200 25 50 75 100 125 150<br>VDS, DRAIN to SOURCE VOLTAGE (V) Tc, CASE TEMPERATURE (oC)<br>Figure  21.    Forward Bias Safe                                            Figure 22.  Maximum Continuous Drain<br>Operating Area                     Current vs Case Temperature<br>1000<br>SINGLE PULSE<br>V GS  = 10 V R θ JA  = 145  [o] C/W<br>100 TA = 25  [o] C<br>10<br>1<br>0.5<br>10-4 10-3 10-2 10-1 1 10 100 1000<br>t, PULSE WIDTH (s)<br>Figure 22.  Single Pulse Maximum Power Dissipation<br>CAPACITANCE (pF)<br>, GATE TO SOURCE VOLTAGE (V)<br>GS<br>V<br>DRAIN CURRENT (A)<br>, DRAIN CURRENT (A)ID I, D<br>, PEAK TRANSIENT POWER (W)<br>(PK)<br>P<br>**----- End of picture text -----**<br>


©2009 Fairchild Semiconductor Corporation **8** www.fairchildsemi.com FDMC8200  Rev.A2 

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Typical Characteristics (Q2 N-Channel)  TJ = 25 °C unless otherwise noted<br>2<br>DUTY CYCLE-DESCENDING ORDER<br>1<br>D = 0.5<br>      0.2<br>      0.1<br>0.1       0.05<br>      0.02 PDM<br>      0.01<br>t 1<br>0.01 t 2<br>NOTES:<br>SINGLE PULSE DUTY FACTOR: D = t1/t2<br>R θ JA  = 145  [o] C/W PEAK T J  = P DM  x Z θ JA  x R θ JA  + T A<br>0.001<br>10-4 10-3 10-2 10-1 1 10 100 1000<br>t, RECTANGULAR PULSE DURATION (sec)<br>Z JA θ<br>IMPEDANCE,<br>NORMALIZED THERMAL<br>**----- End of picture text -----**<br>


**Figure 23. Junction-to-Ambient Transient Thermal Response Curve** 

©2009 Fairchild Semiconductor Corporation **9** www.fairchildsemi.com FDMC8200  Rev.A2 

## **Dimensional Outline and Pad Layout** 

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**----- Start of picture text -----**<br>
FDMC8200 Dual N-Channel PowerTrench<br>®<br> MOSFET<br>**----- End of picture text -----**<br>


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_Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/package/packageDetails.html?id=PN_MLDED-CX8_ 

©2009 Fairchild Semiconductor Corporation **10** www.fairchildsemi.com FDMC8200  Rev.A2 

## **TRADEMARKS** 

The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. 

|AccuPower™<br>AX-CAP®*<br>BitSiC™<br>Build it Now™<br>CorePLUS™<br>CorePOWER™<br>_CROSSVOLT_™<br>CTL™<br>Current Transfer Logic™<br>DEUXPEED®<br>Dual Cool™<br>EcoSPARK®<br>EfficentMax™<br>ESBC™<br>Fairchild®<br>Fairchild Semiconductor®<br>FACT Quiet Series™<br>FACT®<br>FAST®<br>FastvCore™<br>FETBench™<br>FPS™<br>®|F-PFS™<br>FRFET®<br>Global Power ResourceSM<br>GreenBridge™<br>Green FPS™<br>Green FPS™ e-Series™<br>G_max_™<br>GTO™<br>IntelliMAX™<br>ISOPLANAR™<br>Marking Small Speakers Sound Louder<br>and Better™<br>MegaBuck™<br>MICROCOUPLER™<br>MicroFET™<br>MicroPak™<br>MicroPak2™<br>MillerDrive™<br>MotionMax™<br>mWSaver®<br>OptoHiT™<br>OPTOLOGIC®<br>OPTOPLANAR®|PowerTrench®<br>PowerXS™<br>Programmable Active Droop™<br>QFET®<br>QS™<br>Quiet Series™<br>RapidConfigure™<br>Saving our world, 1mW/W/kW at a time™<br>SignalWise™<br>SmartMax™<br>SMART START™<br>Solutions for Your Success™<br>SPM®<br>STEALTH™<br>SuperFET®<br>SuperSOT™-3<br>SuperSOT™-6<br>SuperSOT™-8<br>SupreMOS®<br>SyncFET™<br>™<br>tm®<br>#8,|®*<br>TinyBoost®<br>TinyBuck®<br>TinyCalc™<br>TinyLogic®<br>TINYOPTO™<br>TinyPower™<br>TinyPWM™<br>TinyWire™<br>TranSiC™<br>TriFault Detect™<br>TRUECURRENT®*<br>μSerDes™<br>UHC®<br>Ultra FRFET™<br>UniFET™<br>VCX™<br>VisualMax™<br>VoltagePlus™<br>XS™<br>[ceva|
|---|---|---|---|
|||Sync-Lock™|仙童™|



*Trademarks of System General Corporation, used under license by Fairchild Semiconductor. 

## **DISCLAIMER** 

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. 

## **LIFE SUPPORT POLICY** 

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. 

As used here in: 

1. Life support devices or systems are devices or systems which, (a) are 2. intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 

A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 

## **ANTI-COUNTERFEITING POLICY** 

Fairchild Semiconductor Corporation’s Anti-Counterfeiting Policy. Fairchild’s Anti-Counterfeiting Policy is also stated on our external website, www.Fairchildsemi.com, under Sales Support. 

Counterfeiting of semiconductor parts is a growing problem in the industry. All manufactures of semiconductor products are experiencing counterfeiting of their parts. Customers who inadvertently purchase counterfeit parts experience many problems such as loss of brand reputation, substandard performance, failed application, and increased cost of production and manufacturing delays. Fairchild is taking strong measures to protect ourselves and our customers from the proliferation of counterfeit parts. Fairchild strongly encourages customers to purchase Fairchild parts either directly from Fairchild or from Authorized Fairchild Distributors who are listed by country on our web page cited above. Products customers buy either from Fairchild directly or from Authorized Fairchild Distributors are genuine parts, have full traceability, meet Fairchild’s quality standards for handing and storage and provide access to Fairchild’s full range of up-to-date technical and product information. Fairchild and our Authorized Distributors will stand behind all warranties and will appropriately address and warranty issues that may arise. Fairchild will not provide any warranty coverage or other assistance for parts bought from Unauthorized Sources. Fairchild is committed to combat this global problem and encourage our customers to do their part in stopping this practice by buying direct or from authorized distributors. 

## **PRODUCT STATUS DEFINITIONS Definition of Terms** 

|**Definition of Terms**|||
|---|---|---|
|**Datasheet Identification**|**Product Status**|**Definition**|
|Advance Information|Formative / In Design|Datasheet contains the design specifications for product development. Specifications<br>may change in any manner without notice.|
|Preliminary|First Production|Datasheet contains preliminary data; supplementary data will be published at a later<br>date. Fairchild Semiconductor reserves the right to make changes at any time without<br>notice to improve design.|
|No Identification Needed|Full Production|Datasheet contains final specifications. Fairchild Semiconductor reserves the right to<br>make changes at any time without notice to improve the design.|
|Obsolete|Not In Production|Datasheet contains specifications on a product that is discontinued by Fairchild<br>Semiconductor. The datasheet is for reference information only.|



Rev. I68 

©2009 Fairchild Semiconductor Corporation **11** www.fairchildsemi.com 

FDMC8200  Rev.A2 

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