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CYBT-483039-02
Bluetooth 5.0 + EDR, Class 2 Module, 1.76V to 3.63V Supply, 3Mbps, -88dBm Sensitivity
⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
- Manufacturer: Cypress
- Product type: Bluetooth Modules & Adaptors
- Data Rate: 3Mbps
- Product Range: EZ-BT XR WICED Series
- Bluetooth Class: Class 2
- Bluetooth Version: Bluetooth 5.0 + EDR
- Supply Voltage Max: 3.63V
- Supply Voltage Min: 1.76V
- Receive Sensitivity: -88dBm
- Operating Temperature Max: 85°C
- Operating Temperature Min: -30°C
| Delivery and price | |
|---|---|
| Units per pack | 1 |
| Price | 9.36 € |
| Current stock | 10+ |
| Lead time | 30 days |
Datasheet
**CYBT-483039-02**
EZ-BT™ XR WICED[®] Module
## **General Description**
The CYBT-483039-02 is a dual-mode Bluetooth[] BR/EDR and Low Energy (BLE) wireless module solution. The CYBT-483039-02 includes onboard crystal oscillators, passive components, PA/LNA, and the Cypress CYW20719 silicon device.
The CYBT-483039-02 supports a number of peripheral functions (ADC, PWM), as well as multiple serial communication protocols (UART, SPI, I[2] C, I[2] S/PCM). The CYBT-483039-02 includes a royalty-free stack compatible with Bluetooth 5.0 in a 12.75 × 18.59 × 1.80 mm module form-factor.
The CYBT-483039-02 includes an integrated chip antenna, onboard external power/low noise amplifier, qualified by Bluetooth SIG, and includes regulatory certification approval for FCC, ISED, MIC, and CE.
## **Module Description**
- Module size: 12.75 mm × 18.59 mm × 1.80 mm
- Complies with Bluetooth Core Specification version 5.0 supporting BR, EDR 2/3 Mbps, eSCO, BLE, and LE 2 Mbps. ❐ QDID: D040143
- ❐ Declaration ID: 113067
- True Extended Range with up to +20 dBm output power:
- ❐ Up to 1 kilometer bidirectional communication[[1, 2]]
- Certified up to +20 dBm for FCC and ISED
- Certified up to +10 dBm for MIC and CE standards
- Up to 15 GPIOs
- 1024-KB flash memory, 512-KB SRAM memory
- Industrial temperature range: –30 °C to +85 °C
- Integrated Arm[®] Cortex[®] -M4 microprocessor core with floating point unit (FPU)
## **Functional Capabilities**
- 1x ADC with (12-bit ENoB for DC measurement and 13-bit ENoB for Audio measurement) with 10 channels.
- 1x HCI UART for programming and HCI
- 1x peripheral UART (PUART)
- 2x SPI (master or slave) blocks (SPI, Quad SPI, MIPI DBI-C)
- 1x I[2] C master/slave and 1x I[2] C master only
- I[2] S/PCM audio interfaces
- Up to 6 16-bit PWMs
- Watchdog Timer (WDT)
- Bluetooth Basic Rate (BR) and Enhanced Data Rate (EDR) Support
- BLE protocol stack supporting generic access profile (GAP) Central, Peripheral, or Broadcaster roles
- Hardware Security Engine
## **RF Characteristics**
- Maximum TX output power: +20.0 dBm
- BLE RX Receive Sensitivity: –95.0 dbm
- Received signal strength indicator (RSSI) with 1-dB resolution
## **Power Consumption**
- TX current consumption
- ❐ BLE silicon: 5.6 mA (MCU + radio only, 0 dbm)
- ❐ RFX2401C: 100 mA peak (PA/LNA only, +20 dBm Pout)
- ❐ RFX2401C: 27 mA peak (PA/LNA only, +7.5 dBm Pout)
## ■ RX current consumption
- ❐ Bluetooth silicon: 5.9 mA (MCU + radio only)
- ❐ RFX2401C: 8.0 mA (PA/LNA only)
- Cypress CYW20719 silicon low power mode support
- ❐ PDS: 6.1 µA with 512 KB SRAM retention
- ❐ SDS: 1.6 µA
## **Benefits**
CYBT-483039-02 is fully integrated and certified solution that provides all necessary components required to operate Bluetooth communication standards.
- Proven hardware design ready to use
- Ultra-flexible supermux I/O design allows maximum flexibility for GPIO function assignment
- Large nonvolatile memory for complex application development
- Over-the-Air (OTA) update capable for development or field updates
- Bluetooth SIG qualified with QDID and Declaration ID
- WICED™ Studio provides an easy-to-use integrated design environment (IDE) to configure, develop, program, and test your Bluetooth application
- ❐ HIDOFF (External Interrupt): 400 nA
## **Notes**
1. Connection range tested module-to-module in full line-of-sight environment, free of obstacles or interference sources with output power of +19 dBm POUT.
2. Specified as EZ-BT XT module to module range. Mobile phone connection will decrease based on the PA/LNA performance of the mobile phone used.
**Cypress Semiconductor Corporation** • 198 Champion Court Document Number: 002-23993 Rev. *A
San Jose, CA 95134-1709 • 408-943-2600 Revised January 4, 2019
•
**CYBT-483039-02**
## **More Information**
Cypress provides a wealth of data at www.cypress.com to help you to select the right module for your design, and to help you to quickly and effectively integrate the module into your design.
## **References**
■ Overview: EZ-BLE/EZ-BT Module Portfolio, Module Roadmap
- Development Kits:
- ❐ CYBT-483039-EVAL, CYBT-483039-02 Evaluation Board
- ❐ CYW920719Q40EVB-01, Evaluation Kit for CYW20719 silicon device
- Test and Debug Tools:
- ❐ CYSmart, Bluetooth[®] LE Test and Debug Tool (Windows)
- ❐ CYSmart Mobile, Bluetooth[®] LE Test and Debug Tool (Android/iOS Mobile App)
## ■ Knowledge Base Article
- ❐ KBA97095 - EZ-BLE™ Module Placement
- ❐ KBA224516 - RF Regulatory Certifications for CYBT-483039-02 EZ-BT™ WICED Modules
- ❐ KBA213976 - FAQ for BLE and Regulatory Certifications with EZ-BLE modules
- ❐ KBA210802 - Queries on BLE Qualification and Declaration Processes
- ❐ KBA218122 - 3D Model Files for EZ-BLE/EZ-BT Modules
- ❐ KBA223428 - Programming an EZ-BT WICED Module
- ❐ KBA225450 - Putting 2073x, 2070x, and 20719 Based Devices or Modules in HCI Mode
## **Development Environments**
## _Wireless Connectivity for Embedded Devices (WICED) Studio Software Development Kit (SDK)_
Cypress' WICED[®] (Wireless Connectivity for Embedded Devices) is a full-featured platform with proven Software Development Kits (SDKs) and turnkey hardware solutions from partners to readily enable Wi-Fi and Bluetooth[®] connectivity in system design.
WICED Studio is the only SDK for the Internet of Things (IoT) that combines Wi-Fi and Bluetooth into a single integrated development environment. In addition to providing WICED APIs and an application framework designed to abstract complexity, WICED Studio also leverages many common industry standards.
## **Technical Support**
- Cypress Community: Whether you’re a customer, partner or a developer interested in the latest Cypress innovations, the Cypress Developer Community offers you a place to learn, share and engage with both Cypress experts and other embedded engineers around the world.
- Frequently Asked Questions (FAQs): Learn more about our Bluetooth ECO System.
- Visit our support page and create a technical support case or contact a local sales representatives. If you are in the United States, you can talk to our technical support team by calling our toll-free number: +1-800-541-4736. Select option 2 at the prompt.
Document Number: 002-23993 Rev. *A
Page 2 of 50
**CYBT-483039-02**
## **Contents**
**Overview ............................................................................4** Functional Block Diagram ...........................................4 Module Description ......................................................4 **Pad Connection Interface ................................................6 Recommended Host PCB Layout ...................................8 Module Connections ......................................................10** Connections and Optional External Components .....12 Power Connections (VDD and VDDPA) ....................12 External Reset (XRES) ..............................................13 HCI UART Connections ............................................13 External Component Recommendation ....................13 Critical Components List ...........................................15 Antenna Design .........................................................15 Power Amplifier (PA) and Low Noise Amplifier (LNA) 15 **Bluetooth Baseband Core .............................................16** BQB and Regulatory Testing Support .......................16 **Power Management Unit ................................................17 Integrated Radio Transceiver ........................................18** Transmitter Path ........................................................18 Receiver Path ............................................................18 Local Oscillator ..........................................................18 **Microcontroller Unit .......................................................19** External Reset ...........................................................19 **Peripheral and Communication Interfaces ..................20** I2C .............................................................................20 HCI UART Interface ..................................................20 Peripheral UART Interface ........................................20 Serial Peripheral Interface .........................................20 32 kHz Crystal Oscillator ...........................................21 ADC Port ...................................................................22 GPIO Ports ................................................................22 PWM ..........................................................................23 PDM Microphone .......................................................24 I2S Interface ..............................................................24 PCM Interface ...........................................................24 Security Engine .........................................................25
**Power Modes ..................................................................26 Firmware ..........................................................................26 Electrical Characteristics ...............................................27** Core Buck Regulator .................................................29 Digital LDO ................................................................30 Digital I/O Characteristics ..........................................30 ADC Electrical Characteristics ..................................31 **Chipset RF Specifications .............................................32 Timing and AC Characteristics .....................................35** UART Timing .............................................................35 SPI Timing .................................................................36 I2C Compatible Interface Timing ...............................38 I2S Interface Timing ..................................................39 **Environmental Specifications .......................................41** Environmental Compliance .......................................41 RF Certification ..........................................................41 Safety Certification ....................................................41 Environmental Conditions .........................................41 ESD and EMI Protection ...........................................41 **Regulatory Information ..................................................42** FCC ...........................................................................42 ISED ..........................................................................43 European Declaration of Conformity .........................44 MIC Japan .................................................................44 **Packaging ........................................................................45 Ordering Information ......................................................47 Acronyms ........................................................................48 Document Conventions .................................................48** Units of Measure .......................................................48 **Document History Page .................................................49 Sales, Solutions, and Legal Information ......................50** Worldwide Sales and Design Support .......................50 Products ....................................................................50 PSoC® Solutions ......................................................50 Cypress Developer Community .................................50 Technical Support .....................................................50
Document Number: 002-23993 Rev. *A
Page 3 of 50
**CYBT-483039-02**
## **Overview**
## **Functional Block Diagram**
Figure 1 illustrates the CYBT-483039-02 functional block diagram.
## **Figure 1. Functional Block Diagram**
**Note** General Purpose Input/Output pins shown in Figure 1 are configuratble to any specified input or output function in the SuperMux table detailed in Table 5 in the Module Connections section.
**Note** Connections shown in the above block diagram are maximum number of connections per function. The total number of GPIOs available on the CYBT-483039-02 is 15.
## **Module Description**
The CYBT-483039-02 module is a complete module designed to be soldered to the applications main board.
## _Module Dimensions and Drawing_
Cypress reserves the right to select components from various vendors to achieve the Bluetooth module functionality. Such selections will still guarantee that all mechanical specifications and module certifications are maintained. Any changes to the current BOM for the CYBT-483039-02 will not be made until approval is provided by the end customer for this product. The CYBT-483039-02 will be held within the physical dimensions shown in the mechanical drawings in Figure 2. All dimensions are in millimeters (mm).
## **Table 1. Module Design Dimensions**
|**Dimension Item**|**Dimension Item**|**Specification**|
|---|---|---|
|Module dimensions|Length (X)|12.75 ± 0.15 mm|
||Width (Y)|18.59 ± 0.15 mm|
|Antenna location dimensions|Length (X)|12.75 mm|
||Width (Y)|4.82 mm|
|PCB thickness|Height (H)|0.50 ± 0.10 mm|
|Shield height|Height (H)|1.20 mm|
|Maximum component height|Height (H)|1.30 mm typical (Chip Antenna)|
|Total module thickness (bottom of module to top of shield)|Height (H)|1.80 mm typical|
See Figure 2 for the mechanical reference drawing for CYBT-483039-02.
Document Number: 002-23993 Rev. *A
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**CYBT-483039-02**
**Figure 2. Module Mechanical Drawing**
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Side View<br>**----- End of picture text -----**<br>
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Bottom View (Seen from Bottom)<br>**----- End of picture text -----**<br>
## **Note**
3. No metal should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area. For more information on recommended host PCB layout, see “Recommended Host PCB Layout” on page 8.
Document Number: 002-23993 Rev. *A
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**CYBT-483039-02**
## **Pad Connection Interface**
As shown in the bottom view of Figure 2 on page 5, the CYBT-483039-02 has 34 connections to a host board via solder pads (SP). Table 2 and Figure 3 detail the solder pad length, width, and pitch dimensions of the CYBT-483039-02 module.
## **Table 2. Connection Description**
|**Name**|**Connections**|**Connection Type**|**Pad Length**<br>**Dimension**|**Pad Width**<br>**Dimension**|**Pad Pitch**|
|---|---|---|---|---|---|
|SP|34|Solder Pad|1.02 mm|0.71 mm|1.02 mm|
**Figure 3. Solder Pad Dimensions (Seen from Bottom)**
**==> picture [119 x 23] intentionally omitted <==**
**----- Start of picture text -----**<br>
Solder Pad Connections<br>(Seen from Bottom)<br>**----- End of picture text -----**<br>
To maximize RF performance, the host layout should follow these recommendations:
1. Antenna Area Keepout: The host board directly below the antenna area of the Cypress module (see Figure 2 on page 5) must contain no ground or signal traces. This keep out area requirement applies to all layers of the host board.
2. Module Placement: The ideal placement of the Cypress Bluetooth module is in a corner of the host board with the chip antenna located at the far corner. This placement minimizes the additional recommended keep out area stated in item 3 below. Refer to AN96841 for module placement best practices.
3. Optional Keepout: To maximize RF performance, the area immediately around the Cypress Bluetooth module chip antenna may contain an additional keep out area, where there are no grounding or signal traces. The keep out area applies to all layers of the host board. The recommended dimensions of the host PCB keep out area are shown in Figure 4 (dimensions are in mm).
Document Number: 002-23993 Rev. *A
Page 6 of 50
**CYBT-483039-02**
**Figure 4. Optional Additional Host PCB Keep Out Area Around the CYBT-483039-02 Chip Antenna**
Document Number: 002-23993 Rev. *A
Page 7 of 50
**CYBT-483039-02**
## **Recommended Host PCB Layout**
Figure 5, Figure 6, Figure 7, and Table 3 on page 9 provide details that can be used for the recommended host PCB layout pattern for the CYBT-483039-02. Dimensions are in millimeters unless otherwise noted. Pad length of 1.27 mm (0.635 mm from center of the pad on either side) shown in Figure 7 is the minimum recommended host pad length. The host PCB layout pattern can be completed using either Figure 5, Figure 6, or Figure 7. It is not necessary to use all figures to complete the host PCB layout pattern.
**Figure 5. CYBT-483039-02 Host Layout (Dimensioned)**
**Figure 6. CYBT-483039-02 Host Layout (Relative to Origin)**
**Top View (Seen on Host PCB)**
**==> picture [142 x 10] intentionally omitted <==**
**----- Start of picture text -----**<br>
Top View (Seen on Host PCB)<br>**----- End of picture text -----**<br>
Document Number: 002-23993 Rev. *A
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**CYBT-483039-02**
Table 3 provides the center location for each solder pad on the CYBT-483039-02. All dimensions are referenced to the center of the solder pad. Refer to Figure 7 for the location of each module solder pad.
**Table 3. Module Solder Pad Location**
|**Solder Pad**<br>**(Center of Pad)**<br>~~ee~~|**Location (X,Y)**<br>**from Orign (mm)**|**Dimension from**<br>**Orign (mils)**|
|---|---|---|
|1<br>~~ee~~<br>~~ee ee~~|(0.38, 5.92)<br>~~ee~~|(14.96, 233.07)|
|2<br>~~ee~~<br>~~ee ee~~|(0.38, 6.93)<br>~~ee~~|(14.96, 272.83)|
|3<br>~~ee ee~~<br>~~ee~~|(0.38, 7.95)<br>~~ee~~<br>~~ee~~|(14.96, 312.99)<br>~~ee~~|
|4<br>~~ee~~<br>~~ee~~<br>~~ee ee~~|(0.38, 8.97)<br>~~ee~~<br>~~ee~~<br>~~ee~~|(14.96, 353.15)<br>~~ee~~<br>~~ee~~|
|5<br>~~ee ee~~<br>~~ee~~|(0.38, 9.98)<br>~~ee~~|(14.96, 392.91)|
|6<br>~~ee ee~~<br>~~ee~~<br>~~ee~~|(0.38, 11.00)<br>~~ee~~|(14.96, 433.07)|
|7<br>~~ee~~<br>~~ee~~<br>~~ee ee~~|(0.38, 12.01)<br>~~ee~~|(14.96, 472.83)|
|8<br>~~ee~~<br>~~ee ee~~<br>~~ee~~|(0.38, 13.03)<br>~~ee~~|(14.96, 512.99)|
|9<br>~~ee ee~~<br>~~ee~~<br>~~ee~~|(0.38, 14.05)<br>~~ee~~|(14.96, 553.15)|
|10<br>~~ee~~<br>~~ee~~<br>~~ee ee~~|(0.38, 15.06)<br>~~ee~~|(14.96, 592.91)|
|11<br>~~ee~~<br>~~ee ee~~<br>~~ee~~|(0.38, 16.08)<br>~~ee~~|(14.96, 633.07)|
|12<br>~~ee ee~~<br>~~ee~~<br>~~ee~~|(0.38, 17.09)<br>~~ee~~|(14.96, 672.83)|
|13<br>~~ee~~<br>~~ee~~<br>~~ee ee~~|(1.80, 18.21)<br>~~ee~~|(70.87, 716.93)|
|14<br>~~ee~~<br>~~ee ee~~<br>~~ee~~|(2.82, 18.21)<br>~~ee~~|(111.02, 716.93)|
|15<br>~~ee ee~~<br>~~ee~~<br>~~ee~~|(3.84, 18.21)<br>~~ee~~|(151.18, 716.93)|
|16<br>~~ee~~<br>~~ee~~<br>~~ee ee~~|(4.85, 18.21)<br>~~ee~~|(190.94, 716.93)|
|17<br>~~ee~~<br>~~ee ee~~|(5.87, 18.21)<br>~~ee~~|(231.10, 716.93)|
|18<br>~~ee ee~~<br>~~ee~~|(6.88, 18.21)<br>~~ee~~<br>~~ee~~|(270.87, 716.93)<br>~~ee~~|
|19<br>~~ee~~<br>~~ee~~<br>~~ee ee~~|(7.90, 18.21)<br>~~ee~~<br>~~ee~~<br>~~ee~~|(311.02, 716.93)<br>~~ee~~<br>~~ee~~|
|20<br>~~ee ee~~<br>~~ee~~|(8.92, 18.21)<br>~~ee~~|(351.18, 716.93)|
|21<br>~~ee ee~~<br>~~ee~~<br>~~ee~~|(9.93, 18.21)<br>~~ee~~|(390.94, 716.93)|
|22<br>~~ee~~<br>~~ee~~<br>~~ee ee~~|(10.95, 18.21)<br>~~ee~~|(431.10, 716.93)|
|23<br>~~ee~~<br>~~ee ee~~<br>~~ee~~|(12.37, 17.09)<br>~~ee~~|(487.01, 672.83)|
|24<br>~~ee ee~~<br>~~ee~~<br>~~ee~~|(12.37, 16.08)<br>~~ee~~|(487.01, 633.07)|
|25<br>~~ee~~<br>~~ee~~<br>~~ee ee~~|(12.37, 15.06)<br>~~ee~~|(487.01, 592.91)|
|26<br>~~ee~~<br>~~ee ee~~<br>~~ee ee~~|(12.37, 14.05)<br>~~ee~~<br>~~ee~~|(487.01, 553.15)|
|27<br>~~ee ee~~<br>~~ee ee~~|(12.37, 13.03)<br>~~ee~~<br>~~ee~~|(487.01, 512.99)|
|28<br>~~ee ee~~<br>~~ee~~<br>~~ee ee~~|(12.37, 12.01)<br>~~ee~~<br>~~ee~~<br>~~ee~~|(487.01, 472.83)<br>~~ee~~|
|29<br>~~ee ee~~<br>~~_——~~|(12.37, 11.00)<br>~~ee~~|(487.01, 433.07)|
|30<br>~~ee ee~~<br>~~_——~~|(12.37, 9.98)<br>~~ee~~|(487.01, 392.91)|
|31<br>~~_——~~<br>~~ee ee~~|(12.37, 8.97)<br>~~ee~~|(487.01, 353.15)|
|32<br>~~_——~~<br>~~ee ee~~|(12.37, 7.95)<br>~~ee~~|(487.01, 312.99)|
|33<br>~~ee ee~~<br>~~ee~~|(12.37, 6.93)<br>~~ee~~<br>~~ee~~|(487.01, 272.83)<br>~~ee~~|
|34<br>~~ee~~<br>~~es~~|(12.37, 5.92)<br>~~ee~~<br>~~es~~|(487.01, 233.07)<br>~~ee~~<br>~~es~~|
**Figure 7. Solder Pad Reference Location**
## **Top View (Seen on Host PCB)**
Document Number: 002-23993 Rev. *A
Page 9 of 50
**CYBT-483039-02**
## **Module Connections**
Table 4 details the solder pad connection definitions and available functions for each connection pad. The GPIO connections available on the CYBT-483039-02 can be configured to any of the input or output functions listed in Table 5. Table 4 specifies any function that is required to be used on a specific solder pad, and also identifies GPIOs that can be configured using the SuperMux.
**Table 4. CYBT-483039-02 Solder Pad Connection Definitions**
|**Pad**<br>~~a~~<br>~~ee~~|**Pad Name**<br>~~a~~|**Silicon Pin Name**<br>~~a~~|**XTAL I/O**|**ADC**|**GPIO**|**SuperMux Capable**[4]|
|---|---|---|---|---|---|---|
|1<br>~~a~~<br>~~ee~~|VDD<br>~~a~~|VDDIO<br>~~a~~|Silicon Power Supply Input (1.76V ~ 3.63V)||||
|2<br>~~ee~~<br>~~a~~|GND|GND|Ground||||
|3<br>~~a~~|XRES|RST_N|External Reset (Active Low)||||
|4<br>~~a~~<br>~~a~~|P33<br>~~a~~|P33<br>~~a~~||IN6|✓|✓seeTable 5|
|5<br>~~aeS~~|P25<br>~~eS~~|P25|||✓|✓seeTable 5|
|6<br>~~eS~~|P26<br>~~eS~~|P26|||✓|✓seeTable 5|
|7<br>~~eS~~<br>~~a~~<br>~~a~~|P38<br>~~eS~~<br>~~a~~<br>~~a~~<br>|P38<br>~~a~~<br>~~ee~~|<br>~~ee~~|IN1<br>~~ee~~|✓<br>~~ee~~|✓seeTable 5<br>~~ee~~|
|8<br>~~a~~<br>~~a~~|P34/P35/P36<br>~~a~~<br>|P34<br>P35<br>P36<br>~~ee~~|<br>~~ee~~|IN5 (P34)<br>IN4 (P35)<br>IN3 (P36)<br>~~ee~~|✓(P34/P35/P36)<br>~~ee~~|✓seeTable 5<br>~~ee~~|
|9<br>~~aeS~~|P1<br>~~eS~~|P1<br>~~ee~~|<br>~~ee~~|IN28<br>~~ee ~~|✓<br> ~~ee~~|✓seeTable 5<br>~~ee~~|
|10<br>~~eS~~|P0<br>~~eS~~|P0||IN29|✓|✓seeTable 5|
|11<br>~~eS~~<br>~~a~~<br>~~a~~|P29<br>~~eS~~<br>~~a~~<br>~~a~~<br>~~a~~|P29<br>~~a~~<br>~~ee~~|<br>~~ee~~|IN10<br>~~ee~~|✓<br>~~ee~~|✓seeTable 5<br>~~ee~~|
|12<br>~~a~~<br>~~a~~|P13/P23/P28<br>~~a~~<br>~~a~~|P13<br>P23<br>P28<br>~~ee~~|<br>~~ee~~|IN22 (P13)<br>IN12 (P23)<br>IN11 (P28)<br>~~ee~~|✓(P13/P23/P28)<br>~~ee~~|✓seeTable 5<br>~~ee~~|
|13<br>~~a~~|GND<br>~~a~~|GND<br>~~ee~~|Ground<br>~~ee~~<br>~~ee~~||||
|14<br>~~a~~|P10/P11|P10<br>P11||IN25 (P10)<br>IN24 (P11)|✓(P10/P11)|✓seeTable 5|
|15<br>~~aeS~~|P17<br>~~eS~~|P17||IN18|✓|✓seeTable 5|
|16<br>~~eS~~|P7<br>~~eS~~|P7|||✓||
|17<br>~~eS~~<br>~~aa~~|P6<br>~~eS~~<br>~~aa~~|P6<br>~~aa~~|||✓|✓seeTable 5|
|18<br>~~a~~|P4<br>~~a~~|P4|||✓||
|19<br>~~a~~<br>~~Re~~|XTALO_32K<br>~~a~~<br>~~a~~<br>~~Re~~|XTALO_32K<br>~~ee~~<br>~~es~~|External Oscillator<br>Output (32kHz)<br>~~ee~~||||
|20<br>~~Re~~|XTALI_32K/<br>P15[5]<br>~~Re~~|XTALI_32K<br>P15<br>~~es~~|External Oscillator<br>Input (32kHz)|IN20 (P15)|✓(P15)|✓(P15), seeTable 5|
|21<br>~~Re~~<br>~~a~~|UART_CTS_N<br>~~Re~~<br>~~a~~<br>~~a~~|BT_UART_CTS_N<br>~~es~~<br>~~a~~<br>~~a~~|UART (HCI UART) Clear To Send Input Only<br>~~a~~||||
|22<br>~~a~~|UART_RTS_N<br>~~a~~|BT_UART_RTS_N<br>~~a~~|UART (HCI UART) Request To Send Output Only||||
|23<br>~~a~~|UART_TXD<br>~~a~~|BT_UART_TXD<br>~~a~~|UART (HCI UART) Transmit Data Only||||
|24<br>~~a~~<br>~~a~~<br><br>~~a~~|UART_RXD<br>~~a~~<br>~~a~~<br>|BT_UART_RXD<br>~~a~~<br>~~a~~<br>~~ee~~|UART (HCI UART) Receive Data Only<br>~~ee~~||||
|25<br>~~a~~<br>~~a~~|HOST_WAKE<br>~~a~~|BT_HOST_WAKE<br>~~aee~~|A signal from the CYBT-483039-02 module to the host indicating that the Bluetooth device<br>requires attention.<br>~~ee~~||||
|26<br><br>~~a~~|GND<br>|GND<br>~~ee~~|Ground<br>~~ee~~||||
|27<br>~~a~~|GND|GND|Ground||||
|28<br>~~a~~<br>~~i~~|GND|GND|Ground||||
|29<br>~~i~~<br>~~a~~|GND|GND|Ground||||
|30<br>~~a~~|GND|GND|Ground||||
|31<br>~~a~~<br>~~i~~|GND|GND|Ground||||
**Notes**
4. The CYBT-483039-02 can configure GPIO connections to any Input/Output function described in Table 5.
5. P15 should not be driven high externally while the part is held in reset (it can be floating or driven low). Failure to do so may cause some current to flow through P15 until the device comes out of reset.
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**CYBT-483039-02**
**Table 4. CYBT-483039-02 Solder Pad Connection Definitions** (continued)
|**Function**<br>~~ee~~|**Input/Output**<br>~~es~~|**Function Type**<br>~~I~~|**GPIOs Required**<br>~~(Tn~~|**Function Connection Description**|
|---|---|---|---|---|
|SPI 1<br>~~ee~~|Input/Output<br>~~es~~<br>-|Serial Communication<br>(Master or Slave)<br>~~I ~~|4 ~ 8<br> ~~(Tn~~<br>~~PO~~|SPI 1 Clock<br>~~PO~~|
|||||SPI 1 Chip Select<br>~~PO~~|
|||||SPI 1 MOSI<br>~~PO~~|
|||||SPI 1 MISO<br>~~PO~~<br>~~Pe~~|
|||||SPI 1 I/O 2 (Quad SPI)<br>~~PO~~<br>~~PO~~|
|||||SPI 1 I/O 3 (Quad SPI)<br>~~PO~~<br>~~PO~~<br>~~Ps~~|
|||||SPI 1 Interrupt<br>~~PO~~|
||Output|||SPI 1 DCX (DBI-C DCX 8-bit mode)|
|SPI 2|Input/Output|Serial Communication<br>(Master or Slave)|4 ~ 8|SPI 2 Clock|
|||||SPI 2 Chip Select<br>~~PO~~|
|||||SPI 2 MOSI<br>~~PO~~<br>~~Ps~~|
|||||SPI 2 MISO<br>~~Ps~~<br>~~Ps~~|
|||||SPI 2 I/O 2 (Quad SPI)<br>~~PO~~|
|||||SPI 2 I/O 3 (Quad SPI)<br>~~PO~~|
|||||SPI 2 Interrupt|
||Output|||SPI 2 DCX (DBI-C DCX 8-bit mode)|
|PUART<br>~~———~~|Input<br>~~———~~|Serial Communication Input<br>~~———~~|4<br>~~———~~|Peripheral UART RX<br>~~———~~|
|||||Peripheral UART CTS<br>~~———~~|
||Output<br>~~———~~<br>~~rr~~|Serial Communication Output<br>~~———~~<br>~~rr~~||Peripheral UART TX<br>~~———~~|
|||||Peripheral UART RTS<br>~~———~~|
|I2C<br>~~r~~<br>~~|~~|Input/Output<br>~~r~~<br>~~|~~|Serial Communication<br>(Master or Slave)<br>~~r~~<br>~~|~~|2<br>~~rr~~<br>~~CO~~|I2C Clock<br>~~r~~|
|||||I2C Data<br>~~r~~<br>~~CO~~|
|PCM In<br>~~r~~<br>~~|~~<br>~~|~~|Input<br>~~r~~<br>~~|~~<br>~~|~~|Audio Input Communication<br>~~r~~<br>~~|~~<br>~~|~~|3<br>~~rr~~<br>~~CO~~<br>~~CO~~|PCM Input<br>~~r~~<br>~~CO~~|
|||||PCM Clock<br>~~CO~~|
|||||PCM Sync<br>~~CO~~<br>~~CO~~|
|PCM Out<br>~~| ~~<br>~~|~~|Output<br> ~~|~~<br>~~|~~|Audio Output Communication<br>~~|~~<br>~~|~~|3<br>~~CO~~<br>~~CO~~|PCM Output<br>~~CO~~<br>~~CO~~|
|||||PCM Clock<br>~~CO~~|
|||||PCM Sync<br>~~CO~~|
|I2S In<br>~~| ~~<br>~~|~~<br>~~|~~<br>~~|~~|Input<br> ~~|~~<br>~~|~~<br>~~|~~|Audio Input Communication<br>~~|~~<br>~~|~~<br>~~|~~|3<br>~~CO~~|I2S DI, Data Input<br>~~CO~~|
|||||I2S WS, Word Select|
|||||I2S Clock|
|I2S Out<br>~~|~~<br>~~|~~<br>~~|~~|Output<br>~~|~~<br>~~|~~|Audio Output Communication<br>~~|~~<br>~~|~~|3|I2S DO, Data Output|
|||||I2S WS, Word Select|
|||||I2S Clock|
Table 5 details the available Input and Output functions configurable to any solder pad in Table 4 that are marked as SuperMux capable.
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**CYBT-483039-02**
**Table 5. GPIO SuperMux Input and Output Functions** (continued)
|**Function**|**Input/Output**|**Function Type**|**GPIOs Required**|**Function Connection Description**|
|---|---|---|---|---|
|PDM|Input|Microphone|1 ~ 2|PDM Input Channel 1|
|||||PDM Input Channel 2|
|PWM|Output|Pulse Width Modulator|1 ~ 6|PWM Channel 0|
|||||PWM Channel 1|
|||||PWM Channel 2|
|||||PWM Channel 3|
|||||PWM Channel 4|
|||||PWM Channel 5|
## **Connections and Optional External Components**
## **Power Connections (VDD and VDDPA)**
The CYBT-483039-02 contains two power supply connections, VDD and VDDPA.
VDD is the power supply connection for the Cypress CYW20719 silicon device. VDD accepts a supply input of 1.76 V to 3.63 V. Table 14 on page 27 provides this specification. The maximum power supply ripple for this power connection is 100 mV, as shown in Table 14.
VDDPA is the power supply connection for the on-module power amplifier/low-noise amplifier. VDDPA accepts a supply input of 2.00 V to 3.60 V, as shown in Table 14. The maximum power supply ripple for this power connection is 100 mV, as shown in Table 14.
## _Considerations and Optional Components for Brownout (BO) Conditions_
Power supply design must be completed to ensure that the CYBT-483039-02 module does not encounter a Brownout condition, which can lead to unexpected functionality, or module lock up. A Brownout condition may be met if power supply provided to the module during power up or reset is in the range shown below: VILVDD VIH.
Refer to Table 20 on page 30 for the VIL and VIH specifications.
System design should ensure that the condition above is not encountered when power is removed from the system. In the event that this cannot be guaranteed (i.e. battery installation, high value power capacitors with slow discharge), it is recommended that an external voltage detection device be used to prevent the Brownout voltage range from occuring during power removal.
Figure 8 shows the recommended circuit design when using an external voltage detection IC.
**Figure 8. Reference Circuit Block Diagram for External Voltage Detection IC**
In the event that the module does encounter a Brownout condition, and is operating erratically or not responsive, power cycling the module will correct this issue and once reset, the module should operate correctly. Brownout conditions can potentially cause issues that cannot be corrected, but in general, a power-on-reset operation will correct a Brownout condition.
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**CYBT-483039-02**
## **External Reset (XRES)**
The CYBT-483039-02 has an integrated power-on reset circuit which completely resets all circuits to a known power on state. This action can also be envoked by an external reset signal, forcing it into a power-on reset state. The XRES signal is an active-low signal, which is an input to the CYBT-483039-02 module (solder pad 3). The CYBT-483039-02 module does not require an external pull-up resistor on the XRES input.
During power on operation, the XRES connection to the CYBT-483039-02 is required to be held low 50 ms after the VDD power supply input to the module is stable. This can be accomplished in the following ways:
- The host device can connect a GPIO to the XRES of Cypress CYBT-483039-02 module and pull XRES low until VDD is stable. XRES is recommended to be released 50 ms after VDD is stable.
- If the XRES connection of the CYBT-483039-02 module is not used in the application, a 0.33 µF capacitor may be connected to the XRES solder pad of the CYBT-483039-02 in order to delay the XRES release. The capacitor value for this recommended implementation is approximate, and the exact value may differ depending on the VDD power supply ramp time of the system. The capacitor value should result in an XRES release timing of at least 50 ms after VDD stability.
■ The XRES release timing may be controlled by a external voltage detection IC. XRES should be released 50 ms after VDD is stable. Refer to Figure 11 on page 19 for XRES operating and timing requirements during power on events.
## **HCI UART Connections**
The recommendations in this section apply to the HCI UART (Solder Pads 21, 22, 23, and 24). For full UART functionality, all UART signals must be connected to the Host device. If full UART functionality is not being used, and only UART RXD and TXD are desired or capable, then the following connection considerations should be followed for UART RTS and CTS:
- UART RTS: Can be left floating, pulled low, or pulled high. RTS is not critical for initial firmware uploading at power on.
- UART CTS: Must be pulled low to bypass flow control and to ensure that continuous data transfers are made from the host to the module.
## **External Component Recommendation**
_Power Supply Input Options and Circuitry_
Two connection options are available for the VDD and VDDPA power supplies:
1. Single supply: Connect VDD and VDDPA to the same supply.
2. Independent supply: Power VDD and VDDPA separately.
In either connection scenario, it is recommended to place an external ferrite bead between the supply and the module connection. The ferrite bead should be positioned as close as possible to the module pad connection.
The recommended ferrite bead value is 330, 100 MHz. (Murata BLM21PG331SN1D).
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**CYBT-483039-02**
Figure 9 illustrates the CYBT-483039-02 schematic.
**Figure 9. CYBT-483039-02 Schematic Diagram**
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**CYBT-483039-02**
## **Critical Components List**
Table 6 details the critical components used in the CYBT-483039-02 module.
**Table 6. Critical Component List**
|**Component**|**Reference Designator**|**Description**|
|---|---|---|
|Silicon|U2|40-pin QFN Bluetooth Silicon Device - CYW20719|
|Chip Antenna|A1|Antenna, 2.4 GHz, ALA321C3-C|
|PA/LNA|U2|PA/LNA, +25 dBm maximum boost, RFX2401C|
|Crystal|Y1|24 MHz, 12 pF|
## **Antenna Design**
Table 7 details the chip antenna used in the CYBT-483039-02 module.
**Table 7. Chip Antenna Specifications**
|**Item**|**Description**|
|---|---|
|Frequency Range|2400 – 2500 MHz|
|Peak Gain|2.5 dBi typical|
|Return Loss|10.0 dB typical|
## **Power Amplifier (PA) and Low Noise Amplifier (LNA)**
Table 8 details the PA/LNA that is used on the CYBT-483039-02 module.
**Table 8. Power Amplifier/Low Noise Amplifier Details**
|**Item**|**Description**|
|---|---|
|PA/LNA Manufacturer|Skyworks Inc.|
|PA/LNA Part Number|RFX2401C|
|Power Supply Range|2.0V to 3.6V|
Table 9 details the power consumption of the integrated PA/LNA used on the More Part Numbers module. Table 9 only details the current consumption of the RFX2401C PA/LNA. VDD = 3.3 V, TA = +25 °C, measured on the RFX2401C evaluation board, unless otherwise noted.
## **Table 9. Power Amplifier/Low Noise Amplifier Current Consumption Specifications**
|**Parameter**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|
|TX High Power Current|Pout = +20dBm||100||mA|
|TX Quiescent Current|No RF applied||17||mA|
|RX Quiescent Current|No RF applied||8||mA|
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**CYBT-483039-02**
## **Bluetooth Baseband Core**
The Bluetooth Baseband Core (BBC) implements all time-critical functions required for high-performance Bluetooth operation. The BBC manages the buffering, segmentation, and routing of data for all connections. It prioritizes and schedules all RX/TX activities including adv, paging, scanning, and servicing of connections. In addition to these functions, it independently handles the host controller interface (HCI) including all commands, events, and data flowing over HCI. The core also handles symbol timing, forward error correction (FEC), header error control (HEC), cyclic redundancy check (CRC), authentication, data encryption/decryption, and data whitening/dewhitening.
## **Table 10. Bluetooth Features**
|**Bluetooth 1.0**|**Bluetooth 1.2**|**Bluetooth 2.0**|
|---|---|---|
|Basic Rate|Interlaced Scans|EDR 2 Mbps and 3 Mbps|
|SCO|Adaptive Frequency Hopping|–|
|Paging and Inquiry|eSCO|–|
|Page and Inquiry Scan|–|–|
|Sniff|–|–|
|**Bluetooth 2.1**|**Bluetooth 3.0**|**Bluetooth 4.0**|
|Secure Simple Pairing|Unicast Connectionless Data|Bluetooth Low Energy|
|Enhanced Inquiry Response|Enhanced Power Control|–|
|Sniff Subrating|eSCO|–|
|**Bluetooth 4.1**|**Bluetooth 4.2**|**Bluetooth 5.0**|
|Low Duty Cycle Advertising|Data Packet Length Extension|LE 2 Mbps|
|Dual Mode|LE Secure Connection|Slot Availability Mask|
|LE Link Layer Topology|Link Layer Privacy|High Duty Cycle Advertising|
## **BQB and Regulatory Testing Support**
The CYBT-483039-02 fully supports Bluetooth Test mode as described in Part I:1 of the Specification of the Bluetooth System Version 3.0. This includes the transmitter tests, normal and delayed loop back tests, and reduced hopping sequence.
In addition to the standard Bluetooth Test Mode, the CYBT-483039-02 also supports enhanced testing features to simplify RF debugging and qualification and type-approval testing. These features include:
- Fixed frequency carrier wave (unmodulated) transmission
- ❐ Simplifies some type-approval measurements (Japan)
- ❐ Aids in transmitter performance analysis
- Fixed frequency constant receiver mode
- ❐ Receiver output directed to I/O pin
- ❐ Allows for direct BER measurements using standard RF test equipment
- ❐ Facilitates spurious emissions testing for receive mode
- Fixed frequency constant transmission
- ❐ 8-bit fixed pattern or PRBS-9
- ❐ Enables modulated signal measurements with standard RF test equipment
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**CYBT-483039-02**
## **Power Management Unit**
Figure 10 shows the CYW20719 power management unit (PMU) block diagram. The CYW20719 includes an integrated buck regulator, a bypass LDO, a capless LDO for digital circuits and a separate LDO for RF. The bypass LDO automatically takes over from the buck once VBAT supply falls below 2.1V.
The voltage levels shown in this figure are the default settings; the firmware may change voltage levels based on operating conditions.
**Figure 10. Default Usage Mode**
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**CYBT-483039-02**
## **Integrated Radio Transceiver**
The CYBT-483039-02 has an integrated radio transceiver that has been designed to provide low power operation in the globally available 2.4 GHz unlicensed ISM band. It is fully compliant with Bluetooth Radio Specification 3.0 and meets or exceeds the requirements to provide the highest communication link quality of service.
## **Transmitter Path**
CYBT-483039-02 features a fully integrated transmitter. The baseband transmit data is GFSK modulated in the 2.4 GHz ISM band.
## _Digital Modulator_
The digital modulator performs the data modulation and filtering required for the GFSK signal. The fully digital modulator minimizes any frequency drift or anomalies in the modulation characteristics of the transmitted signal.
## _Power Amplifier_
The CYBT-483039-02 includes an external power amplifier (ePA) that can transmit up to +20 dBm for class 1 operation.
## **Receiver Path**
The receiver path uses a low IF scheme to downconvert the received signal for demodulation in the digital demodulator and bit synchronizer. The receiver path provides a high degree of linearity, and an extended dynamic range to ensure reliable operation in the noisy 2.4 GHz ISM band. The front-end topology, which has built-in out-of-band attenuation, enables the CYBT-483039-02 to be used in most applications without off-chip filtering.
## _Digital Demodulator and Bit Synchronizer_
The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit synchronization algorithm.
## _Receiver Signal Strength Indicator_
The radio portion of the CYBT-483039-02 provides a receiver signal strength indicator (RSSI) to the baseband. This enables the controller to take part in a Bluetooth power-controlled link by providing a metric of its own receiver signal strength to determine whether the transmitter should increase or decrease its output power.
## **Local Oscillator**
The local oscillator (LO) provides fast frequency hopping (1600 hops/second) across the 79 maximum available channels. The CYBT-483039-02 uses an internal loop filter.
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**CYBT-483039-02**
## **Microcontroller Unit**
The CYBT-483039-02 includes a Arm Cortex-M4 processor with 2 MB of ROM, 448 KB of data RAM, 64 KB of patch RAM, and 1 MB of on-chip flash. The CM4 has a maximum speed of 96 MHz. CYBT-483039-02 supports execution from on-chip flash (OCF).
The CM4 also includes a single precision IEEE 754 compliant floating point unit (FPU).
The CM4 runs all the BT layers as well as application code. The ROM includes LM, HCI, L2CAP, GATT, as well as other stack layers freeing up the flash for application usage. A standard serial wire debug (SWD) interface provides debugging support.
## **External Reset**
An external active-low reset signal, XRES, can be used to put the CYBT-483039-02 in the reset state. An external voltage detector reset IC with 50 ms delay is recommended on the XRES connection. The XRES must only be released after the VDDO supply voltage level has been stabilized for 50 ms.
## **Figure 11. Reset Timing**
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**CYBT-483039-02**
## **Peripheral and Communication Interfaces**
## **I[2] C**
The CYBT-483039-02 provides a 2-pin I[2] C compatible master interface to communicate with I[2] C compatible peripherals. The following transfer clock rates are supported are:
- 100 kHz
- 400 kHz
- 800 kHz (Not a standard I[2] C-compatible speed)
■ 1 MHz (Compatibility with high-speed I[2] C-compatible devices is not guaranteed)
SCL and SDA lines can be routed to any of the P0-P39 GPIOs allowing for flexible system configuration. When used as SCL/SDA the GPIOs go into open drain mode and require an external pull-up for proper operation. I[2] C block does not support multi master capability by either master or slave devices.
I[2] C is Master Only.
## **HCI UART Interface**
The CYBT-483039-02 includes a UART interface for factory programming as well as when operating as a BT HCI device in a system with an external host. The UART physical interface is a standard, 4-wire interface (RX, TX, RTS, and CTS) with adjustable baud rates from 115200 bps to 1.5 Mbps. Typical rates are 115200, 921600, 1500000 bps although intermediate speeds are also available. Support for changing the baud rate during normal HCI UART operation is included through a vendor-specific command. The CYBT-483039-02 UART operates correctly with the host UART as long as the combined baud rate error of the two devices is within ±5%. The UART interface has a 1040-byte receive FIFO and a 1040-byte transmit FIFO to support enhanced data rates. The interface supports the Bluetooth UART HCI (H4) specification. The default baud rate for H4 is 115.2 kbaud.
The CYBT-483039-02 can wake up the host as needed or allow the host to sleep via the HOST_WAKE signal (solder pad 2). signal allows the CYBT-483039-02 to optimize system power consumption by allowing a host device to remain in low power modes as long as possible. The HOST_WAKE signal can be enabled via a vendor specific command.
## **Peripheral UART Interface**
The CYBT-483039-02 has a second UART that may be used to interface to peripherals. This peripheral UART is accessed through the optional I/O ports, which can be configured individually and separately for each functional pin. The CYBT-483039-02 can map the peripheral UART to any GPIO. The Peripheral UART functionality is the same as the HCI UART, but with a 256-byte transmit and receive FIFO.
## **Serial Peripheral Interface**
The CYBT-483039-02 has two independent SPI interfaces. Both interfaces support Single, Dual, and Quad mode SPI operations as well as MIPI DBI-C Interface.Either of the interface can be a master or a slave. SPI2 can support only 1 slave. SPI1 has a 1024 byte transmit and receive buffers which is shared with the host UART interface. SPI2 has a dedicated 256-byte transmit and receive buffers. To support more flexibility for user applications, the CYBT-483039-02 has optional I/O ports that can be configured individually and separately for each functional pin. SPI IO voltage depends on VDDO.
## _MIPI Interface_
There are three options in DBI type-C corresponding to 9-bit, 16-bit, and 8-bit modes. The CYBT-483039-02 plays the role of host, and only the 9-bit and 8-bit modes (option 1 and option 3 in DBI-C spec) are supported. In the 9-bit mode, the SCL, CS, MOSI, and MISO pins are used. In the 8-bit mode, an additional pin (DCX) is required. The DCX pin indicates if the current outgoing bit stream is a command or data byte.
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**CYBT-483039-02**
## **32 kHz Crystal Oscillator**
The CYBT-483039-02 utilizes the built-in Local Oscillator (LO) on the CYW20719 silicon device for 32 kHz timing. The accuracy of the LO is +/- 500 ppm. The use of an external XTAL oscillator is optional. CYBT-483039-02 includes external XTAL oscillator connections for applications requiring higher timing accuracy. Figure 12 shows an external 32 kHz XTAL oscillator with external components and Table 11 lists the recommended external oscillator’s characteristics. This oscillator input can be operated with a 32 kHz or 32.768 kHz crystal oscillator or be driven with a clock input at similar frequency. The default component values are: R1 = 10 M and C1 = C2 = ~6 pF. The values of C1 and C2 are used to fine-tune the oscillator.
**Figure 12. 32 kHz Oscillator Block Diagram**
**Table 11. XTAL Oscillator Characteristics**
|**Parameter**<br>~~es~~|**Symbol**<br>~~Ge~~|**Conditions**<br>~~QQ~~|**Min**<br>~~QQ~~|**Typ**<br>~~QQ~~<br>~~(~~|**Max**<br>~~(~~|**Unit**|
|---|---|---|---|---|---|---|
|Output Frequency<br>~~es~~<br>~~eG~~<br>~~ee~~|Foscout<br>~~Ge~~<br>~~eG~~<br>~~Ge~~|–<br>~~QQ~~<br>~~GG~~<br>~~GQ~~|–<br>~~QQ~~<br>~~GG~~<br>~~GQ~~|32.768<br>~~QQ~~<br>~~(~~<br>~~GG~~<br>~~GQ~~|–<br>~~(~~<br>~~GQ~~|kHz<br>~~GQ~~|
|FrequencyTolerance<br>~~eG~~<br>~~ee~~|–<br>~~eG ~~<br>~~Ge~~|Crystal-dependent<br> ~~GG~~<br>~~GQ~~|–<br>~~GG~~<br>~~GQ~~|100<br>~~GG~~<br>~~GQ~~|–<br>~~GQ~~|ppm<br>~~GQ~~|
|Start-upTime<br>~~ee~~<br>~~Ge~~<br>~~ee~~|Tstartup<br>~~Ge ~~<br>~~Ge~~<br>|–<br> ~~GQ~~<br>~~GG~~<br>~~Qe~~<br>|–<br>~~GQ~~<br>~~GG~~<br>~~Gs~~<br>|500<br>~~GQ~~<br>~~GG~~<br>~~Gs~~<br>|–<br>~~GQ~~<br>~~Gs~~<br>|ms<br>~~GQ~~<br>|
|XTAL Drive Level<br>~~Ge~~<br>~~eG~~<br>~~ee~~|Pdrv<br>~~Ge~~<br>~~eG~~<br>~~Ge~~|For crystal selection<br>~~GG~~<br>~~eG~~<br>~~Qe~~<br>~~GQ~~|–<br>~~GG~~<br>~~eG~~<br>~~Gs~~<br>~~GQ~~|–<br>~~GG~~<br>~~eG~~<br>~~Gs~~<br>~~GQ~~|0.5<br>~~eG~~<br>~~Gs~~<br>~~GQ~~|µW<br>~~eG~~<br>~~GQ~~|
|XTAL Series Resistance<br>~~eG~~<br>~~ee~~|Rseries<br>~~eG~~<br>~~Ge~~|For crystal selection<br>~~eG~~<br>~~Qe~~<br>~~GQ~~|–<br>~~eG~~<br>~~Gs~~<br>~~GQ~~|–<br>~~eG~~<br>~~Gs~~<br>~~GQ~~|70<br>~~eG~~<br>~~Gs~~<br>~~GQ~~|k<br>~~eG~~<br>~~GQ~~|
|XTAL Shunt Capacitance<br>~~ee~~<br>~~ee ee~~|Cshunt<br>~~Ge ~~<br>~~ee~~|For crystal selection<br>~~Qe~~<br> ~~GQ~~|–<br>~~Gs~~<br>~~GQ~~|–<br>~~Gs~~<br>~~GQ~~|2.2<br>~~Gs~~<br>~~GQ~~|pF<br>~~GQ~~|
|External AC Input Amplitude<br>~~ee ee~~|VIN(AC)<br>~~ee~~|Ccouple= 100 pF; Rbias= 10 M|400|–|–|mVpp|
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**CYBT-483039-02**
## **ADC Port**
The ADC is a - ADC core designed for audio (13 bits) and DC (12 bits) measurement. It operates at 12 MHz and has 10 solder pad connections that can act as input channels. The internal bandgap reference has ±5% accuracy without calibration. Calibration and digital correction schemes can be applied to reduce ADC absolute error and improve measurement accuracy in DC mode.
The following CYBT-483039-02 module solder pads can be used as ADC inputs:
- Pad 4: P33, ADC Input Channel 6
- Pad 7: P38, ADC Input Channel 1
- Pad 8: P34/P35/P36, ADC Input Channels 5/4/3 respectively. **Note** Only one ADC input on this solder pad can be active at a given time.
- Pad 9: P1, ADC Input Channel 28
- Pad 10: P0, ADC Input Channel 29
- Pad 11: P29, ADC Input Channel 10
- Pad 12: P13/P23/28, ADC Input Channels 22/12/11 respectively. **Note** Only one ADC input on this solder pad can be active at a given time.
- Pad 14: P10/P11, ADC Input Channels 25/24 respectively.
- **Note** Only one ADC input on this solder pad can be active at a given time.
- Pad 15: P17, ADC Input Channel 18
- Pad 20: P15, ADC Input Channel 20. P15 should not be driven high externally while the part is held in reset (it can be floating or driven low). Failure to do so may cause some current to flow through P15 until the device comes out of reset.
## **GPIO Ports**
The CYBT-483039-02 has a maximum of 15 general-purpose I/Os (GPIOs). All GPIOs support the following:
- Programmable pull-up/down of approximately 45 k.
- Input disable, allowing pins to be left floating or analog signals connected without risk of leakage.
- Source/sink 8 mA at 3.3V and 4 mA at 1.8V.
- P15 is Bonded to the same pin as XTALI_32K (Pad 20). If an External 32.768 kHz crystal is not used, then this pin can be used as GPIO P15.
- P26/P28/P29 can sink/source 16 mA at 3.3V and 8 mA at 1.8V.
Most peripheral functions can be assigned to any GPIO. For details, refer to Table 5 on page 11. For more details on Supermux configuration and control, refer to “Supermux Wizard for CYW20719” user guide.
The list below details the GPIOs that are available on the CYBT-483039-02 module:
- ❐ P0-P1, P4, P6, P7, P17, P25, P26, P29, P33, and P38
- ❐ P10/P11 (Double bonded connection on the CYBT-483039-02 module, only one of two is available)
- ❐ P13/P23/P28 (Triple bonded connection on the CYBT-483039-02 module, only one of three is available)
- ❐ P15/XTALI_32K (Double bonded pin on the CYBT-483039-02 module, only one of two is available)
- ❐ P34/P35/P36 (Triple bonded pin on the CYBT-483039-02 module, only one of three is available)
- ❐ P19, P20 and P39 are reserved for system use. Do not use these three GPIOs.
For GPIOs highlighted as double or triple bonded connections, only one of the connections can be used at a given time. When a certain GPIO is selected, the other GPIOs bonded to the same connection must be configured to input with output disable.
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**CYBT-483039-02**
## **PWM**
The CYBT-483039-02 has six internal PWMs, labeled PWM0-5. The PWM module consists of the following:
- Each of the six PWM channels contains the following registers:
- ❐ 16-bit initial value register (read/write)
- ❐ 16-bit toggle register (read/write)
- ❐ 16-bit PWM counter value register (read)
- PWM configuration register shared among PWM0–5 (read/write). This 18-bit register is used:
- ❐ To configure each PWM channel
- ❐ To select the clock of each PWM channel
- ❐ To change the phase of each PWM channel
The application can access the PWM module through the FW driver.
Figure 13 shows the structure of one PWM channel.
**Figure 13. PWM Block Diagram**
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**CYBT-483039-02**
## **PDM Microphone**
The CYBT-483039-02 accepts a -based one-bit pulse density modulation (PDM) input stream and outputs filtered samples at either 8 kHz or 16 kHz sampling rates. The PDM signal derives from an external kit that can process analog microphone signals and generate digital signals. The PDM input shares the filter path with the auxADC. Two types of data rates can be supported:
## ■ 8 kHz
## ■ 16 kHz
The external digital microphone takes in a 2.4 MHz clock generated by the CYBT-483039-02 and outputs a PDM signal which is registered by the PDM interface with either the rising or falling edge of the 2.4 MHz clock selectable through a programmable control bit. The design can accommodate two simultaneous PDM input channels, so stereo voice is possible.
**Note** Subject to the driver support in WICED Studio.
## **I[2] S Interface**
The CYBT-483039-02 supports a single I[2] S digital audio port with both master and slave modes. The I[2] S signals are:
- I[2] S Clock: I[2] S SCK
- I[2] S Word Select: I[2] S WS
- I[2] S Data Out: I[2] S DO
## ■ I[2] S Data In: I[2] S DI
I[2] S SCK and I[2] S WS become outputs in master mode and inputs in slave mode, while I[2] S DO always stays as an output. The channel word length is 16 bits and the data is justified so that the MSN of the left-channel data is aligned with the MSB of the I[2] S bus, per I[2] S Specifications. The MSB of each data word is transmitted one bit clock cycle after the I[2] S WS transition, synchronous with the falling edge of bit clock. Left Channel data is transmitted when I[2] S WS is low, and right-channel data is transmitted when I[2] S WS is high. Data bits sent by the CYBT-483039-02 are synchronized with the falling edge of I[2] S SCK and should be sampled by the receiver on the rising edge of the I[2] S SCK.
**Note** The PCM interface shares HW with the I[2] S interface and only one can be used at a given time.
## **PCM Interface**
The CYBT-483039-02 includes a PCM interface that can connect to linear PCM codec devices in master or slave mode. In master mode, the CYBT-483039-02 generates the PCM_CLK and PCM_SYNC signals. In slave mode, these signals are provided by another master on the PCM interface and are inputs to the CYBT-483039-02.The configuration of the PCM interface may be adjusted by the host through the use of vendor-specific HCI commands.
**Note** The PCM interface shares HW with the I[2] S interface and only one can be used at a given time.
## _Slot Mapping_
The CYBT-483039-02 supports up to three simultaneous full-duplex SCO or eSCO channels through the PCM Interface. These three channels are time-multiplexed onto the single PCM interface by using a time-slotting scheme where the 8 kHz or 16 kHz audio sample interval is divided into as many as 16 slots. The number of slots is dependent on the selected interface rate (128 kHz, 512 kHz, or 1024 kHz). The corresponding number of slots for these interface rate is 1, 2, 4, 8, and 16, respectively. Transmit and receive PCM data from an SCO channel is always mapped to the same slot. The PCM data output driver tristates its output on unused slots to allow other devices to share the same PCM interface signals. The data output driver tristates its output after the falling edge of the PCM clock during the last bit of the slot.
## _Frame Synchronization_
The CYBT-483039-02 supports both short- and long-frame synchronization in both master and slave modes. In short frame synchronization mode, the frame synchronization signal is an active-high pulse at the audio frame rate that is a single-bit period in width and is synchronized to the rising edge of the bit clock. The PCGM slave looks for a high on the falling edge of the bit clock and expects the first bit of the first slot to start at the next rising edge of the clock. In long-frame synchronization mode, the frame synchronization signal is again an active-high pulse at the audio frame rate; however, the duration is three bit periods and the pulse starts coincident with the first bit of the first slot.
## _Data Formatting_
The CYBT-483039-02 may be configured to generate and accept several different data formats. For conventional narrow band speech mode, the CYBT-483039-02 uses 13 of the 16 bits in each PCM frame. The location and order of these 13 bits can be configured to support various data formats on the PCM interface. The remaining three bits are ignored on the input and may be filled with 0s, 1s, a sign bit, or a programmed value on the output. The default format is 13-bit 2’s complement data, left justified, and clocked MSB first.
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**CYBT-483039-02**
## _Burst PCM Mode_
In this mode of operation, the PCM bus runs at a significantly higher rate of operation to allow the host to duty cycle its operation and save current. In this mode of operation, the PCM bus can operate at a rate of up to 24 MHz. This mode of operation is initiated with an HCI command from the host.
## **Security Engine**
The CYBT-483039-02 includes a hardware security accelerator which greatly decreases the time required to perform typical security operations. Access to the hardware block is provided via a firmware interface.
This security engine includes:
- Public key acceleration (PKA) cryptography
- AES-CTR/CBC-MAC/CCM acceleration
- SHA2 message hash and HMAC acceleration
- RSA encryption and decryption of modulus sizes up to 2048 bits
- Elliptic curve Diffie-Hellman in prime field GF(p)
**Note** Security Engine is used only by the Bluetooth stack to reduce CPU overhead. It is not available for application use.
## _Random Number Generator_
This hardware block is used for key generation for Bluetooth.
**Note** Availability for use by the application is subject to the support in WICED Studio.
**Note** The Random Number Generator block must be warmed up prior to use. A delay of 500 ms from cold boot is necessary prior to using the Random Number Generator.
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**CYBT-483039-02**
## **Power Modes**
The CYBT-483039-02 support the following HW power modes are supported:
- **Active mode** - Normal operating mode in which all peripherals are available and the CPU is active.
- **Idle mode** - In this mode, the CPU is in “Wait for Interrupt” (WFI) and the HCLK, which is the high frequency clock derived from the main crystal oscillator is running at a lower clock speed. Other clocks are active and the state of the entire chip is retained.
- **Sleep mode** - In this mode, CPU is in WFI and the HCLK is not running. The PMU determines if the other clocks can be turned off and does accordingly. State of the entire chip is retained, the internal LDOs run at a lower voltage (voltage is managed by the PMU), and SRAM is retained.
- **PDS mode** - This mode is an extension of the PMU Sleep wherein most of the peripherals such as UART and SPI are turned off. The entire memory is retained, and on wakeup the execution resumes from where it paused.
- **Shut Down Sleep (SDS)** - Everything is turned off except the IO Power Domain, RTC, and LPO. The device can come out of this mode either due to BT activity or by an external interrupt. Before going into this mode, the application can store some bytes of data into “Always On RAM” (AON). When the device comes out of this mode, the data from AON is restored. After waking from SDS, the application will start from the beginning (warmboot) and has to restore its state based on information stored in AON. In the SDS mode, a single BT task with no data activity, such as an ACL connection, BLE connection, or BLE advertisement can be performed.
- **HIDOFF (Timed-Wake) mode** - The device can enter this mode asynchronously, that is, the application can force the device into this mode at any time. IO Power Domain, RTC, and LPO are the only active blocks. A timer that runs off the LPO is used to wake the device up after a predetermined fixed time.
- **HIDOFF (External Interrupt-Waked) mode** - This mode is similar to Timed-Wake, but in HID-off mode even the LPO and RTC are turned off. So, the only wakeup source is an external interrupt.
Transition between power modes is handled by the on-chip firmware with host/application involvement. Refer to the Firmware Section for details.
## **Firmware**
The CYBT-483039-02 ROM firmware runs on a real time operating system and handles the programming and configuration of all on-chip hardware functions as well as the BT/LE baseband, LM, HCI, GATT, ATT, L2CAP and SDP layers. The ROM also includes drivers for on-chip peripherals as well as handling on-chip power management functions including transitions between different power modes.
The CYBT-483039-02 is fully supported by the Cypress WICED Studio platform. WICED releases provide latest ROM patches, drivers, and sample applications allowing customized applications using the CYBT-483039-02 to be built quickly and efficiently.
Refer to WICED Technical Brief and CYBT-483039-02 Product Guide for details on the firmware architecture, driver documentation, power modes and how to write applications/profiles using the .
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**CYBT-483039-02**
## **Electrical Characteristics**
The absolute maximum ratings in the following table indicate levels where permanent damage to the device can occur, even if these limits are exceeded for only a brief duration. Functional operation is not guaranteed under these conditions. Operation at absolute maximum conditions for extended periods can adversely affect long-term reliability of the device.
**Table 12. Silicon Absolute Maximum Ratings**
|**Requirement Parameter**<br>~~pt~~<br>~~ee~~<br>~~a~~|**Specification**<br>~~pt~~<br>~~ee~~<br>~~es eeeee~~|**Specification**<br>~~pt~~<br>~~ee~~<br>~~es eeeee~~|**Specification**<br>~~pt~~<br>~~ee~~<br>~~es eeeee~~|**Unit**<br>~~ee~~|
|---|---|---|---|---|
||**Min**<br>~~ee~~<br>~~es ee~~|**Nom**<br>~~ee~~<br>~~ee~~|**Max**<br>~~ee~~<br>~~eee~~||
|Maximum Junction Temperature<br>~~ee~~<br>~~a~~|–<br>~~ee~~<br>~~es ee~~|–<br>~~ee~~<br>~~ee ~~|125<br>~~ee~~<br> ~~eee~~|°C<br>~~ee~~|
|VDD IO<br>~~a~~|–0.5|–|3.795|V|
|VDD RF<br>~~a~~<br>~~a~~|–0.5|–|1.38<br>~~G~~|V|
|VDDBAT3V<br>~~a~~|–0.5|–|3.795|V|
|DIGLDO_VDDIN1P5<br>~~a~~|–0.5|–|1.65|V|
|RFLDO_VDDIN1P5<br>~~a~~|–0.5|–|1.65|V|
|PALDO_VDDIN_5V<br>~~a~~|–0.5|–|3.795|V|
|MIC_AVDD<br>~~a~~|–0.5|–|3.795|V|
**Table 13. ESD/Latchup**
|**Requirement Parameter**|**Specification**|**Specification**|**Specification**|**Unit**|
|---|---|---|---|---|
||**Min**|**Nom**|**Max**||
|ESD Tolerance HBM (Silicon)|–2000|–|2000|V|
|ESD Tolerance CDM (Silicon)|–500|–|500|V|
|Latch-up|–|200|–|mA|
**Table 14. Power Supply Specifications**
|**Parameter**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|
|VDDInput|Module Chipset Input|1.76|3.0|3.63|V|
|VDDPAInput|Module PA/LNA Input|2.0|3.0|3.60|V|
|VDDRipple|Module Input Ripple (VDDPA, VDD)|–|–|100|mV|
|VBATInput|Internal to Module (not accessible)|1.90|3.0|3.6|V|
|PMU turn-on time|VBATis ready|–|–|300|µs|
The CYBT-483039-02 uses an onboard low voltage detector to shut down the part when supply voltage (VDD) drops below operating range.
**Table 15. Power Supply Shut Down Specifications**
|**Parameter**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|
|VSHUT|1.625|1.7|1.76|V|
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**CYBT-483039-02**
**Table 16. Bluetooth, BLE, BR and EDR Current Consumption**
|**Parameter**<br>~~a~~<br>~~ee~~|**Description**<br>~~a~~|**Silicon or Module**<br>**Parameter**<br>~~ee~~|**Typ**|**Unit**|
|---|---|---|---|---|
|HCI<br>~~a ~~<br>~~ee~~<br>~~eS~~|48 MHz with Pause<br> ~~a~~|Silicon<br>~~ee~~|1.1|mA|
|HCI<br>~~ee~~<br>~~eS~~<br>~~eS~~|48 MHz without Pause|Silicon|2.2|mA|
|RX<br>~~eS~~<br>~~eS~~<br>~~eS~~|Continuous RX|Silicon|5.9|mA|
|TX<br>~~eS~~<br>~~eS~~<br>~~eS~~|Continuous TX - 0 dBm|Silicon|5.6|mA|
|PDS<br>~~eS~~<br>~~eS~~<br>~~eS~~|–|Silicon|6.1|µA|
|HID-Off (SDS)<br>~~eS~~<br>~~eS~~<br>~~eS~~|32 kHz XTAL and 16 KB Retention RAM on|Silicon|1.6|µA|
|Advertising<br>~~eS~~<br>~~eS~~<br>~~eS~~|Unconnectable - 1 second|Silicon|14|µA|
|Advertising<br>~~eS~~<br>~~eS~~<br>~~eS~~|Connectable Undirected - 1 second|Silicon|17|µA|
|Page Scan - PDS<br>~~eS~~<br>~~eS~~<br>~~eS~~|Interlaced - R1|Silicon|122|µA|
|Sniff - PDS<br>~~eS~~<br>~~eS~~<br>~~eS~~|500 ms Sniff, 1 attempt, 0 timeout - Master|Silicon|132|µA|
|Sniff - PDS<br>~~eS~~<br>~~eS~~<br>~~**a**~~|500 ms Sniff, 1 attempt, 0 timeout - Slave<br>~~es~~|Silicon|138|µA|
|Bidirectional Data<br>Exchange<br>~~eS~~<br>~~**a**~~|Continuous DM5 or DH5 packets - Master or Slave<br>~~es~~|Silicon|6.9|mA|
|**Bluetooth Low Energy (BLE, 20 dBm)**<br>~~**a**~~<br>~~es~~<br>~~eS~~|||||
|RX Peak<br>~~eS~~<br>~~eS~~|Peak RX current|Module|8.8|mA|
|TX Peak<br>~~eS~~<br>~~eS~~<br>~~eS~~|Peak TX Current|Module|90|mA|
|PDS<br>~~eS~~<br>~~eS~~<br>~~eS~~|–|Module|13.9|µA|
|HID-Off (SDS)<br>~~eS~~<br>~~eS~~<br>~~eS~~|–|Module|14.9|µA|
|Advertising - SDS<br>~~eS~~<br>~~eS~~<br>~~eS~~|Connectable Undirected - 1 second<br>~~a~~|Module<br>~~a~~|48<br>~~a~~|µA<br>~~a~~|
|LE Connection - SDS<br>~~eS~~<br>~~eS~~|Slave - 1 second<br>~~a~~|Module<br>~~a~~|35<br>~~a~~|µA<br>~~a~~|
|**Bluetooth Classic (BR, EDR, 20 dBm)**<br>~~eSa~~<br>~~a~~<br>~~ee ee~~<br>~~eS~~|||||
|IDLE<br>~~a~~<br>~~eS~~|Module is idle, non-discoverable and<br>non-connectable<br>~~a~~<br>~~ee ee~~|Module<br>~~a~~<br>~~ee~~|8.3<br>~~a~~|µA<br>~~a~~|
|Iscan<br>~~eS~~<br>~~eS~~|Inquiry scan (1.28 seconds)<br>~~ee ee~~|Module<br>~~ee~~|160|µA|
|Pscan<br>~~eS~~<br>~~eS~~<br>~~eS~~|Page scan (1.28 seconds)<br>~~ee ee~~|Module<br>~~ee~~|160|µA|
|IScan + Pscan<br>~~eS~~<br>~~eS~~<br>~~eS~~|Inquiry scan + Page Scan (1.28 seconds)|Module|10.4|µA|
|Connected<br>~~eS~~<br>~~eS~~<br>~~a~~|Connected with no data transfer<br>|Module<br>~~ee~~<br>|12.7<br>~~ee~~<br>|mA<br>|
|Connected + Pscan<br>~~eS~~<br>~~a~~<br>~~a~~<br>~~eS~~|Connected with no data transfer + Page Scan (1.28<br>seconds)<br>~~ee~~<br>|Module<br>~~ee~~<br>~~ee~~<br><br>~~ee~~|12.75<br>~~ee~~<br>~~ee~~<br><br>~~ee~~|mA<br>~~ee~~<br>|
|Connected + IScan +<br>Pscan<br>~~a~~<br>~~eS~~|Connected with no data transfer + Inquiry Scan (1.28<br>seconds) + Page Scan (1.28 seconds)<br>~~ee~~|Module<br>~~ee~~<br>~~ee~~<br>~~ee~~|12.9<br>~~ee~~<br>~~ee~~<br>~~ee~~|mA<br>~~ee~~|
|Connected + SNIFF<br>~~eS~~<br>~~a~~|Connected with no data transfer + SNIFF (500 ms)<br>~~ee ee~~|Module<br>~~ee~~<br>~~ee~~|10<br>~~ee~~<br>~~ee~~|mA|
|Connected + SNIFF +<br>IScan + Pscan<br>~~eS~~<br>~~a~~<br>~~eS~~|Connected with no data transfer + SNIFF (500 ms) +<br>Inquiry Scan and Page Scan 1.28 seconds<br>~~ee ee~~|Module<br>~~ee~~<br>~~ee~~|10.5<br>~~ee~~<br>~~ee~~|mA|
|TX_BR<br>~~a~~<br>~~eS~~<br>~~eS~~|Data transfer @115200 baud rate<br>~~ee ee~~|Module<br>~~ee~~|21.5<br>~~ee~~|mA|
|TX + SNIFF_BR<br>~~eS~~<br>~~eS~~|Data transfer @115200 baud rate + Sniff (500 ms)|Module|14.5|mA|
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**CYBT-483039-02**
**Table 17. Power Amplifier/Low Noise Amplifier Current Consumption Specifications**
|**Parameter**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|
|TX High Power Current|Pout = +20dBm|–|100|–|mA|
|TX Quiescent Current|No RF applied|–|17|–|mA|
|RX Quiescent Current|No RF applied|–|8|–|mA|
## **Core Buck Regulator**
## **Table 18. Silicon Core Buck Regulator**
|**Parameter**<br>~~ee~~<br>~~**e**e~~|**Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|
|Input supply voltage DC, VBAT<br>~~ee~~<br>~~**e**e~~|DC voltage range inclusive of disturbances|1.90|3.0|3.63|V|
|CBUCK output current<br>~~**e**e~~<br>~~ee~~|LPOM only<br>~~e~~<br>~~ee~~|–<br>~~e~~<br>~~ee~~|–<br>~~e~~|65<br>~~e~~|mA<br>~~e~~|
|Output voltage range<br>~~ee~~<br>~~**e**e~~|Programmable, 30 mV/step<br>default = 1.2V (bits = 0000)<br>~~e~~<br>~~ee~~|1.2<br>~~e~~<br>~~ee~~|1.26<br>~~e~~|1.5<br>~~e~~|V<br>~~e~~|
|Output voltage DC accuracy<br>~~ee ~~<br>~~**e**e~~|Includes load and line regulation<br> ~~ee~~|–4<br>~~ee~~|–|+4|%|
|LPOM efficiency (high load)<br>~~**e**e~~<br>~~ee~~|–<br>~~e~~|–<br>~~e~~|85<br>~~e~~|–<br>~~e~~|%<br>~~e~~|
|LPOM efficiency (low load)<br>~~ee~~<br>~~ee~~|–<br>~~e~~|–<br>~~e~~|80<br>~~e~~|–<br>~~e~~|%<br>~~e~~|
|Input supply voltage ramp-up time<br>~~ee~~<br>~~ee~~|0 to 3.3V|40|–|–|µs|
- Minimum capacitor value refers to residual capacitor value after taking into account part-to-part tolerance, DC-bias, temperature, and aging.
- Maximum capacitor value refers to the total capacitance seen at a node where the capacitor is connected. This also includes any decoupling capacitors connected at the load side, if any.
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**CYBT-483039-02**
## **Digital LDO**
## **Table 19. Digital LDO**
|**Parameter**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|
|Input supply voltage, Vin|Minimum Vin = Vo + 0.12V requirement must be<br>met under maximum load.|1.2|1.2|1.6|V|
|Nominal output voltage, Vo|Internal default setting|–|1.1|–|V|
|Dropout voltage|At maximum load|–|–|120|mV|
## **Digital I/O Characteristics**
**Table 20. Digital I/O Characteristics**
|**Characteristics**<br>~~pf~~|**Symbol**<br>~~pf~~|**Min**<br>~~pf~~|**Typ**<br>~~pf~~|**Max**<br>~~pf~~|**Unit**<br>~~pf~~|
|---|---|---|---|---|---|
|Input low voltage (VDD= 3V)<br>~~pf~~<br>~~CGO~~|VIL<br>~~pf~~<br>~~CGO~~|–<br>~~pf~~<br>~~CGO~~|–<br>~~pf~~<br>~~CGO~~|0.8<br>~~pf~~<br>~~CGO~~|V<br>~~pf~~<br>~~CGO~~|
|Input high voltage (VDD= 3V)<br>~~CGO~~<br>~~GG~~|VIH<br>~~CGO~~<br>~~GG~~|2.4<br>~~CGO~~<br>~~GG~~|–<br>~~CGO~~<br>~~GG~~|–<br>~~CGO~~<br>~~GG~~|V<br>~~CGO~~<br>~~GG~~|
|Input low voltage (VDD= 1.8V)<br>~~GG~~<br>~~CGO~~|VIL<br>~~GG~~<br>~~CGO~~|–<br>~~GG~~<br>~~CGO~~|–<br>~~GG~~<br>~~CGO~~|0.4<br>~~GG~~<br>~~CGO~~|V<br>~~GG~~<br>~~CGO~~|
|Input high voltage (VDD= 1.8V)<br>~~CGO~~<br>~~GG~~|VIH<br>~~CGO~~<br>~~GG~~|1.4<br>~~CGO~~<br>~~GG~~|–<br>~~CGO~~<br>~~GG~~|–<br>~~CGO~~<br>~~GG~~|V<br>~~CGO~~<br>~~GG~~|
|Output low voltage<br>~~GG~~<br>~~CGO~~|VOL<br>~~GG~~<br>~~CGO~~|–<br>~~GG~~<br>~~CGO~~|–<br>~~GG~~<br>~~CGO~~|0.45<br>~~GG~~<br>~~CGO~~|V<br>~~GG~~<br>~~CGO~~|
|Output high voltage<br>~~CGO~~<br>~~GG~~|VOH<br>~~CGO~~<br>~~GG~~|VDDO– 0.45V<br>~~CGO~~<br>~~GG~~|–<br>~~CGO~~<br>~~GG~~|–<br>~~CGO~~<br>~~GG~~|V<br>~~CGO~~<br>~~GG~~|
|Input low current<br>~~GG~~<br>~~CGO~~|IIL<br>~~GG~~<br>~~CGO~~|–<br>~~GG~~<br>~~CGO~~|–<br>~~GG~~<br>~~CGO~~|1.0<br>~~GG~~<br>~~CGO~~|µA<br>~~GG~~<br>~~CGO~~|
|Input high current<br>~~CGO~~<br>~~GG~~|IIH<br>~~CGO~~<br>~~GG~~|–<br>~~CGO~~<br>~~GG~~|–<br>~~CGO~~<br>~~GG~~|1.0<br>~~CGO~~<br>~~GG~~|µA<br>~~CGO~~<br>~~GG~~|
|Output low current (VDD= 3V, VOL= 0.5V)<br>~~GG~~<br>~~CGO~~|IOL<br>~~GG~~<br>~~CGO~~|–<br>~~GG~~<br>~~CGO~~|–<br>~~GG~~<br>~~CGO~~|8.0<br>~~GG~~<br>~~CGO~~|mA<br>~~GG~~<br>~~CGO~~|
|Output low current (VDD= 1.8V, VOL= 0.5V)<br>~~CGO~~<br>~~GG~~|IOL<br>~~CGO~~<br>~~GG~~|–<br>~~CGO~~<br>~~GG~~|–<br>~~CGO~~<br>~~GG~~|4.0<br>~~CGO~~<br>~~GG~~|mA<br>~~CGO~~<br>~~GG~~|
|Output high current (VDD= 3V, VOH= 2.55V)<br>~~GG~~<br>~~CGO~~|IOH<br>~~GG~~<br>~~CGO~~|–<br>~~GG~~<br>~~CGO~~|–<br>~~GG~~<br>~~CGO~~|8.0<br>~~GG~~<br>~~CGO~~|mA<br>~~GG~~<br>~~CGO~~|
|Output high current (VDD= 1.8V, VOH= 1.35V)<br>~~CGO~~<br>~~GG~~|IOH<br>~~CGO~~<br>~~GG~~|–<br>~~CGO~~<br>~~GG~~|–<br>~~CGO~~<br>~~GG~~|4.0<br>~~CGO~~<br>~~GG~~|mA<br>~~CGO~~<br>~~GG~~|
|Input capacitance<br>~~GG~~<br>~~DG~~|CIN<br>~~GG~~<br>~~DG~~|–<br>~~GG~~<br>~~DG~~|–<br>~~GG~~<br>~~DG~~|0.4<br>~~GG~~<br>~~DG~~|pF<br>~~GG~~<br>~~DG~~|
Document Number: 002-23993 Rev. *A
Page 30 of 50
**CYBT-483039-02**
## **ADC Electrical Characteristics**
## **Table 21. Electrical Characteristics**
|**Parameter**<br>~~Po~~<br>~~es~~|**Symbol**<br>~~Po~~<br>~~ne er~~|**Conditions/Comments**<br>~~Po~~<br>~~er~~|**Min**<br>~~Po~~<br>~~ns~~|**Typ**<br>~~Po~~<br>~~ns~~|**Max**<br>~~Po~~<br>~~I~~|**Unit**<br>~~Po~~|
|---|---|---|---|---|---|---|
|Current consumption<br>~~Po~~<br>~~es~~<br>~~ns~~|ITOT<br>~~Po~~<br>~~ne er~~<br>~~Py~~|–<br>~~Po~~<br>~~er~~<br>~~nn~~|–<br>~~Po~~<br>~~ns~~<br>~~Un~~|2<br>~~Po~~<br>~~ns~~<br>~~I~~|3<br>~~Po~~<br>~~I~~|mA<br>~~Po~~|
|Power down current<br>~~es~~<br>~~ns~~|–<br>~~ne er~~<br>~~Py~~|At room temperature<br>~~er~~<br>~~nn~~|–<br>~~ns~~<br>~~Un~~|1<br>~~ns ~~<br>~~I~~|–<br> ~~I~~|µA|
|**ADC Core Specification**<br>~~nsPy nn~~<br>~~Un I~~<br>~~ns~~<br>~~nynn~~<br>~~(I~~<br>~~nn~~|||||||
|ADC reference voltage<br>~~ns~~<br>~~nn~~|VREF<br>~~ny~~|From BG with ±3% accuracy<br>~~nn~~|–<br>~~nn~~<br>~~(I~~|0.85<br>~~nn~~|–<br>~~nn~~|V<br>~~nn~~|
|ADC sampling clock<br>~~ns~~<br>~~nn~~<br>~~i~~|–<br>~~ny~~|–<br>~~nn~~<br>~~eee~~|–<br>~~nn~~<br>~~(I~~<br>~~eee~~|12<br>~~nn~~<br>~~eee~~|–<br>~~nn~~<br>~~eee~~|MHz<br>~~nn~~<br>~~eee~~|
|Absolute error<br>~~nn~~<br>~~i~~|–|Includes gain error, offset and<br>distortion. Without factory<br>calibration.<br>~~eee~~|–<br>~~(I~~<br>~~eee~~|–<br>~~eee~~|5<br>~~eee~~|%<br>~~eee~~|
|||Includes gain error, offset and<br>distortion. After factory calibration.<br>~~eee~~|–<br>~~(I~~<br>~~eee~~|–<br>~~eee~~|2<br>~~eee~~|%<br>~~eee~~|
|ENOB<br>~~i~~|–|For audio application<br>~~eee~~|12<br>~~eee~~|13<br>~~eee~~|–<br>~~eee~~|Bit<br>~~eee~~|
|||For static measurement|10|–|–||
|ADC input full scale<br>~~Yh~~|FS<br>~~Yh~~|For audio application<br>~~Yh~~|–<br>~~Yh~~|1.6<br>~~Yh~~|–||
|||For static measurement<br>~~Yh~~|1.8<br>~~Yh~~|–<br>~~Yh~~|3.6||
|Conversion rate<br>~~Yh~~|–<br>~~Yh~~|For audio application<br>~~Yh~~|8<br>~~Yh~~|16<br>~~Yh~~|–|kHz|
|||For static measurement|50|100|–||
|Signal bandwidth|–|For audio application|20|–|8K|Hz|
|||For static measurement|–|DC|–||
|Input impedance<br>~~ee~~|RIN|For audio application|10|–|–|KW<br>~~eee~~|
|||For static measurement<br>~~es~~|500<br>~~ee~~|–<br>~~eee~~|–<br>~~eee~~||
|Startup time<br>~~ee~~|–|For audio application<br>~~es~~|–<br>~~ee~~|10<br>~~eee~~|–<br>~~eee~~|ms<br>~~eee~~|
|||For static measurement<br>~~es~~|–<br>~~ee~~|20<br>~~eee~~|–<br>~~eee~~|µs<br>~~eee~~|
|**MIC PGA Specifications**<br>~~ee~~<br>~~es ee eee~~<br>~~ns~~<br>~~nynn~~<br>~~(I~~<br>~~es~~|||||||
|MIC PGA gain range<br>~~ns~~<br>~~es~~<br>~~ns~~|–<br>~~ny~~<br>~~**n**s~~|–<br>~~nn~~<br>~~nr~~|0<br>~~nn~~<br>~~(I~~<br>~~I~~|–<br>~~nn~~<br>~~I~~|42<br>~~nn~~<br>~~I~~|dB<br>~~nn~~|
|MIC PGA gain step<br>~~ns~~<br>~~es~~<br>~~ns~~<br>~~es~~|–<br>~~ny~~<br>~~**n**s~~<br>~~n~~<br>|–<br>~~nn~~<br>~~nr~~<br>~~nnn)~~<br>|–<br>~~nn~~<br>~~(I~~<br>~~I~~<br>~~nnn)~~<br>~~ns I~~|1<br>~~nn~~<br>~~I~~<br>~~nnn)~~<br>~~I~~|–<br>~~nn~~<br>~~I~~<br>~~nnn)~~|dB<br>~~nn~~<br>~~nnn)~~|
|MIC PGA gain error<br>~~es ~~<br>~~ns~~<br>~~es~~<br>~~ns~~|–<br> ~~**n**s~~<br>~~n~~<br>~~ns~~<br>|Includes part-to-part gain variation<br>~~nr~~<br>~~nnn)~~<br>~~**n**r~~|–1<br>~~(I~~<br>~~I~~<br>~~nnn)~~<br>~~ns I~~<br>~~I~~|–<br>~~I~~<br>~~nnn)~~<br>~~I~~<br>~~**I**~~|1<br>~~I~~<br>~~nnn)~~<br>~~**I**~~|dB<br>~~nnn)~~|
|PGA input referred noise<br> <br>~~ns~~<br>~~es~~<br>~~ns~~|–<br> ~~**n**s ~~<br>~~n~~<br>~~ns~~<br>~~Gs~~|At 42 dB PGA gain A-weighted<br> ~~nr~~<br>~~nnn)~~<br>~~**n**r~~<br>~~n~~|–<br>~~I ~~<br>~~nnn)~~<br>~~ns I~~<br>~~I~~<br>~~(Os~~|–<br> ~~I ~~<br>~~nnn)~~<br>~~I~~<br>~~**I**~~|4<br> ~~I~~<br>~~nnn)~~<br>~~**I**~~|µV<br>~~nnn)~~|
|Passband gain flatness<br>~~es ~~<br>~~ns~~|–<br> ~~ns~~<br>~~Gs~~|PGA and ADC, 100 Hz–4 kHz<br>~~**n**r~~<br>~~n~~|–0.5<br>~~ns I~~<br>~~I~~<br>~~(Os~~|–<br>~~I~~<br>~~**I**~~|0.5<br>~~**I**~~|dB|
|**MIC Bias Specifications**<br> ~~ns ~~~~**n**r~~<br>~~I ~~~~**I** ~~~~**I**~~<br>~~nsGs~~<br>~~n~~<br>~~(Os~~<br>~~ns~~<br>~~nynn~~<br>~~(I~~<br>~~es~~|||||||
|MIC bias output voltage<br>~~ns~~<br>~~es~~<br>~~ee~~|–<br>~~ny~~<br>~~ns nr~~<br>|At 2.5V supply<br>~~nn~~<br>~~nr~~|–<br>~~nn~~<br>~~(I~~<br>~~I~~|2.1<br>~~nn~~<br>~~I~~|–<br>~~nn~~<br>~~I~~|V<br>~~nn~~|
|MIC bias loading current<br>~~ns~~<br>~~es~~<br>~~ee~~<br>~~ns~~|–<br>~~ny~~<br>~~ns nr~~<br>~~es~~|–<br>~~nn~~<br>~~nr~~<br>~~es~~|–<br>~~nn~~<br>~~(I~~<br>~~I~~<br>~~es~~|–<br>~~nn~~<br>~~I~~<br>~~ee~~|3<br>~~nn~~<br>~~I~~|mA<br>~~nn~~|
|MIC bias noise<br>~~es ~~<br>~~ee~~<br>~~ns~~<br>~~es~~|–<br> ~~ns nr~~<br>~~es~~<br>~~nn~~<br>|Refers to PGA input 20 Hz to<br>8 kHz, A-weighted<br>~~nr~~<br>~~es~~<br>~~nnn)~~<br>|–<br>~~(I~~<br>~~I~~<br>~~es~~<br>~~nnn)~~<br>~~ns I~~|–<br>~~I~~<br>~~ee~~<br>~~nnn)~~<br>~~I~~|3<br>~~I~~<br>~~nnn)~~|µV<br>~~nnn)~~|
|MIC bias PSRR<br> <br>~~ee ~~<br>~~ns~~<br>~~es~~<br>~~es~~|–<br> ~~ns nr~~<br> ~~es~~<br>~~nn~~<br>~~ns~~<br>|at 1 kHz<br>~~nr~~<br>~~es~~<br>~~nnn)~~<br>~~nr~~<br>|40<br>~~I ~~<br>~~es~~<br>~~nnn)~~<br>~~ns I~~<br>~~I~~|–<br> ~~I ~~<br>~~ee~~<br>~~nnn)~~<br>~~I~~<br>~~I~~|–<br> ~~I~~<br>~~nnn)~~<br>~~I~~|dB<br>~~nnn)~~|
|ADC SNR<br> <br>~~ns~~<br>~~es~~<br>~~es~~|–<br> ~~es~~<br>~~nn~~<br>~~ns~~<br>~~Rs~~|A-weighted 0 dB PGA gain<br>~~es~~<br>~~nnn)~~<br>~~nr~~<br>~~nn~~|78<br>~~es ~~<br>~~nnn)~~<br>~~ns I~~<br>~~I~~<br>~~ns~~|–<br> ~~ee~~<br>~~nnn)~~<br>~~I~~<br>~~I~~<br>~~I~~|–<br>~~nnn)~~<br>~~I~~|dB<br>~~nnn)~~|
|ADC THD + N<br>~~es ~~<br>~~es~~<br>~~ee~~|–<br> ~~ns~~<br>~~Rs~~<br>~~ee~~|–3 dB FS input 0 dB PGA gain<br>~~nr~~<br>~~nn~~<br>~~ee~~|74<br>~~ns I~~<br>~~I~~<br>~~ns~~<br>~~ee~~|–<br>~~I~~<br>~~I~~<br>~~I~~<br>~~ee~~|–<br>~~I~~<br>~~ee~~|dB<br>~~ee~~|
|GPIO input voltage<br> <br>~~es~~<br>~~ee~~|~~ns ~~<br>~~Rs ~~<br>~~ee~~|Always lower than VDDBAT<br> ~~nr~~<br> ~~nn~~<br>~~ee~~|–<br>~~I ~~<br>~~ns ~~<br>~~ee~~|–<br> ~~I ~~<br> ~~I~~<br>~~ee~~|3.6<br> ~~I~~<br>~~ee~~|V<br>~~ee~~|
|GPIO source impedance[6]<br>~~ee~~<br>~~eee~~|–<br>~~ee~~<br>~~eee~~|Resistance<br>~~ee~~<br>~~eee~~|–<br>~~ee~~<br>~~eee~~|–<br>~~ee~~<br>~~eee~~|1<br>~~ee~~<br>~~eee~~|k<br>~~ee~~<br>~~eee~~|
|||Capacitance<br>~~ee~~<br>~~eee~~|–<br>~~ee~~<br>~~eee~~|–<br>~~ee~~<br>~~eee~~|10<br>~~ee~~<br>~~eee~~|pF<br>~~ee~~<br>~~eee~~|
Document Number: 002-23993 Rev. *A
Page 31 of 50
**CYBT-483039-02**
## **Chipset RF Specifications**
Table 22 and Table 23 apply to single-ended industrial temperatures. Unused inputs are left open.
**Table 22. Chipset Receiver RF Specifications**
|**Parameter**<br>~~Ge~~|**Mode and Conditions**<br>~~Ge~~|**Min**<br>~~Ge~~<br>~~OO~~|**Typ**<br>~~Ge~~<br>~~OO~~|**Max**<br>~~Ge~~|**Unit**<br>~~Ge~~|
|---|---|---|---|---|---|
|Frequency range<br>~~Ge~~<br>~~Ge~~|–<br>~~Ge~~<br>~~Ge~~|2402<br>~~Ge~~<br>~~OO~~<br>~~Ge~~|–<br>~~Ge~~<br>~~OO~~<br>~~Ge~~|2480<br>~~Ge~~<br>~~Ge~~|MHz<br>~~Ge~~<br>~~Ge~~|
|RX sensitivity[7]<br>~~Ge~~|GFSK, 0.1% BER, 1 Mbps<br>~~Ge~~<br>~~po~~|–<br>~~Ge~~<br>~~po~~|–92.0[7]<br>~~Ge~~<br>~~po~~|–<br>~~Ge~~<br>~~po~~|dBm<br>~~Ge~~<br>~~po~~|
||/4-DQPSK, 0.01% BER, 2 Mbps<br>~~po~~<br>~~po~~|–<br>~~po~~<br>~~po~~|–94.0[8]<br>~~po~~<br>~~po~~|–<br>~~po~~<br>~~po~~|dBm<br>~~po~~<br>~~po~~|
||8-DPSK, 0.01% BER, 3 Mbps<br>~~po~~<br>~~a~~|–<br>~~po~~<br>~~a~~|–88.0[8]<br>~~po~~<br>~~a~~|–<br>~~po~~<br>~~a~~|dBm<br>~~po~~<br>~~a~~|
|Maximum input<br>~~Ce~~|All data rates<br>~~a~~<br>~~Ce~~|–<br>~~a~~<br>~~Ce~~|–<br>~~a~~<br>~~Ce~~|–20<br>~~a~~<br>~~Ce~~|dBm<br>~~a~~<br>~~Ce~~|
|**GFSK Modulation**<br>~~Ce~~<br>~~RC~~||||||
|C/I cochannel<br>~~RC~~<br>~~Ce~~|GFSK, 0.1% BER[7]<br>~~RC~~<br>~~Ce~~|–<br>~~RC~~<br>~~Ce~~<br>~~OO~~|–<br>~~RC~~<br>~~Ce~~<br>~~OO~~|11.0<br>~~RC~~<br>~~Ce~~|dB<br>~~RC~~<br>~~Ce~~|
|C/I 1 MHz adjacent channel<br>~~Ce~~<br>~~Ge~~|GFSK, 0.1% BER[8]<br>~~Ce~~<br>~~Ge~~|–<br>~~Ce~~<br>~~Ge~~<br>~~OO~~|–<br>~~Ce~~<br>~~Ge~~<br>~~OO~~|0<br>~~Ce~~<br>~~Ge~~|dB<br>~~Ce~~<br>~~Ge~~|
|C/I 2 MHz adjacent channel<br>~~Ge~~<br>~~Ge~~|GFSK, 0.1% BER[9]<br>~~Ge~~<br>~~Ge~~|–<br>~~Ge~~<br>~~OO~~<br>~~Ge~~<br>~~OO~~|–<br>~~Ge~~<br>~~OO~~<br>~~Ge~~<br>~~OO~~|–30.0<br>~~Ge~~<br>~~Ge~~|dB<br>~~Ge~~<br>~~Ge~~|
|C/I3 MHz adjacent channel<br>~~Ge~~<br>~~Ge~~|GFSK, 0.1% BER[7]<br>~~Ge~~<br>~~Ge~~|–<br>~~Ge~~<br>~~Ge~~<br>~~OO~~|–<br>~~Ge~~<br>~~Ge~~<br>~~OO~~|–40.0<br>~~Ge~~<br>~~Ge~~|dB<br>~~Ge~~<br>~~Ge~~|
|C/I image channel<br>~~Ge~~<br>~~Ge~~|GFSK, 0.1% BER[9]<br>~~Ge~~<br>~~Ge~~|–<br>~~Ge~~<br>~~OO~~<br>~~Ge~~<br>~~CO~~|–<br>~~Ge~~<br>~~OO~~<br>~~Ge~~<br>~~CO~~|–9.0<br>~~Ge~~<br>~~Ge~~<br>~~CO~~|dB<br>~~Ge~~<br>~~Ge~~|
|C/I 1 MHz adjacent to image channel <br>~~Ge~~<br>~~Fe~~|GFSK, 0.1% BER[9]<br>~~Ge~~<br>~~Fe~~|–<br>~~Ge~~<br>~~Fe~~<br>~~CO~~|–<br>~~Ge~~<br>~~Fe~~<br>~~CO~~|–20.0<br>~~Ge~~<br>~~Fe~~<br>~~CO~~|dB<br>~~Ge~~<br>~~Fe~~|
|**QPSK Modulation**<br>~~Fe~~<br>~~CO~~<br>~~Re~~<br>~~GO~~||||||
|C/I cochannel<br>~~Re~~<br>~~Ge~~|/4-DQPSK, 0.1% BER[9]<br>~~Re~~<br>~~Ge~~|–<br>~~Re~~<br>~~Ge~~<br>~~GO~~|–<br>~~Re~~<br>~~Ge~~<br>~~GO~~|13.0<br>~~Re~~<br>~~Ge~~|dB<br>~~Re~~<br>~~Ge~~|
|C/I 1 MHz adjacent channel<br>~~Ge~~<br>~~Ge~~|/4-DQPSK, 0.1% BER4<br>~~Ge~~<br>~~Ge~~|–<br>~~Ge~~<br>~~GO~~<br>~~Ge~~<br>~~OO~~|–<br>~~Ge~~<br>~~GO~~<br>~~Ge~~<br>~~OO~~|0<br>~~Ge~~<br>~~Ge~~|dB<br>~~Ge~~<br>~~Ge~~|
|C/I 2 MHz adjacent channel<br>~~Ge~~<br>~~Ge~~|/4-DQPSK, 0.1% BER[9]<br>~~Ge~~<br>~~Ge~~|–<br>~~Ge~~<br>~~Ge~~<br>~~OO~~|–<br>~~Ge~~<br>~~Ge~~<br>~~OO~~|–30.0<br>~~Ge~~<br>~~Ge~~|dB<br>~~Ge~~<br>~~Ge~~|
|C/I3 MHz adjacent channel<br>~~Ge~~<br>~~Ge~~|/4-DQPSK, 0.1% BER5<br>~~Ge~~<br>~~Ge~~|–<br>~~Ge~~<br>~~OO~~<br>~~Ge~~<br>~~OO~~|–<br>~~Ge~~<br>~~OO~~<br>~~Ge~~<br>~~OO~~|–40.0<br>~~Ge~~<br>~~Ge~~|dB<br>~~Ge~~<br>~~Ge~~|
|C/I image channel<br>~~Ge~~<br>~~Ge~~|/4-DQPSK, 0.1% BER[9]<br>~~Ge~~<br>~~Ge~~|–<br>~~Ge~~<br>~~Ge~~<br>~~OO~~|–<br>~~Ge~~<br>~~Ge~~<br>~~OO~~|–9.0<br>~~Ge~~<br>~~Ge~~|dB<br>~~Ge~~<br>~~Ge~~|
|C/I 1 MHz adjacent to image channel <br>~~Ge~~<br>~~Ge~~|/4-DQPSK, 0.1% BER[9]<br>~~Ge~~<br>~~Ge~~|–<br>~~Ge~~<br>~~OO~~<br>~~Ge~~|–<br>~~Ge~~<br>~~OO~~<br>~~Ge~~|–20.0<br>~~Ge~~<br>~~Ge~~|dB<br>~~Ge~~<br>~~Ge~~|
|**8PSK Modulation**<br>~~Ge~~<br>~~Ce~~||||||
|C/I cochannel<br>~~Ce~~<br>~~Ce~~|8-DPSK, 0.1% BER[9]<br>~~Ce~~<br>~~Ce~~|–<br>~~Ce~~<br>~~Ce~~<br>~~OO~~|–<br>~~Ce~~<br>~~Ce~~<br>~~OO~~|21.0<br>~~Ce~~<br>~~Ce~~|dB<br>~~Ce~~<br>~~Ce~~|
|C/I 1 MHz adjacent channel<br>~~Ce~~<br>~~Ge~~|8-DPSK, 0.1% BER[9]<br>~~Ce~~<br>~~Ge~~|–<br>~~Ce~~<br>~~Ge~~<br>~~OO~~|–<br>~~Ce~~<br>~~Ge~~<br>~~OO~~|5.0<br>~~Ce~~<br>~~Ge~~|dB<br>~~Ce~~<br>~~Ge~~|
|C/I 2 MHz adjacent channel<br>~~Ge~~<br>~~Ge~~|8-DPSK, 0.1% BER[9]<br>~~Ge~~<br>~~Ge~~|–<br>~~Ge~~<br>~~OO~~<br>~~Ge~~<br>~~OO~~|–<br>~~Ge~~<br>~~OO~~<br>~~Ge~~<br>~~OO~~|–25.0<br>~~Ge~~<br>~~Ge~~|dB<br>~~Ge~~<br>~~Ge~~|
|C/I3 MHz adjacent channel<br>~~Ge~~<br>~~Ge~~|8-DPSK, 0.1% BER5<br>~~Ge~~<br>~~Ge~~|–<br>~~Ge~~<br>~~Ge~~<br>~~OO~~|–<br>~~Ge~~<br>~~Ge~~<br>~~OO~~|–33.0<br>~~Ge~~<br>~~Ge~~|dB<br>~~Ge~~<br>~~Ge~~|
|C/I image channel<br>~~Ge~~<br>~~Ge~~|8-DPSK, 0.1% BER[9]<br>~~Ge~~<br>~~Ge~~|–<br>~~Ge~~<br>~~OO~~<br>~~Ge~~<br>~~CO~~|–<br>~~Ge~~<br>~~OO~~<br>~~Ge~~<br>~~CO~~|0<br>~~Ge~~<br>~~Ge~~<br>~~CO~~|dB<br>~~Ge~~<br>~~Ge~~|
|C/I 1 MHz adjacent to image channel <br>~~Ge~~<br>~~Fe~~|8-DPSK, 0.1% BER[9]<br>~~Ge~~<br>~~Fe~~|–<br>~~Ge~~<br>~~Fe~~<br>~~CO~~|–<br>~~Ge~~<br>~~Fe~~<br>~~CO~~|13<br>~~Ge~~<br>~~Fe~~<br>~~CO~~|dB<br>~~Ge~~<br>~~Fe~~|
|**Out-of-Band Blocking Performance (CW)**[10]<br>~~Fe~~<br>~~CO~~<br>~~Re~~<br>~~GO~~||||||
|30 MHz to 2000 MHz<br>~~Re~~<br>~~Ge~~|BDR GFSK 0.1% BER<br>~~Re~~<br>~~Ge~~|–<br>~~Re~~<br>~~Ge~~<br>~~GO~~|–10.0<br>~~Re~~<br>~~Ge~~<br>~~GO~~|–<br>~~Re~~<br>~~Ge~~|dBm<br>~~Re~~<br>~~Ge~~|
|2000 MHz to 2399 MHz<br>~~Ge~~<br>~~Ge~~|BDR GFSK 0.1% BER<br>~~Ge~~<br>~~Ge~~|–<br>~~Ge~~<br>~~GO~~<br>~~Ge~~<br>~~OO~~|–27.0<br>~~Ge~~<br>~~GO~~<br>~~Ge~~<br>~~OO~~|–<br>~~Ge~~<br>~~Ge~~|dBm<br>~~Ge~~<br>~~Ge~~|
|2498 MHz to 3000 MHz<br>~~Ge~~<br>~~Ge~~|BDR GFSK 0.1% BER<br>~~Ge~~<br>~~Ge~~|–<br>~~Ge~~<br>~~Ge~~<br>~~OO~~|–27.0<br>~~Ge~~<br>~~Ge~~<br>~~OO~~|–<br>~~Ge~~<br>~~Ge~~|dBm<br>~~Ge~~<br>~~Ge~~|
|3000 MHz to 12.75 GHz<br>~~Ge~~<br>~~Ge~~|BDR GFSK 0.1% BER<br>~~Ge~~<br>~~Ge~~|–<br>~~Ge~~<br>~~OO~~<br>~~Ge~~|–10.0<br>~~Ge~~<br>~~OO~~<br>~~Ge~~|–<br>~~Ge~~<br>~~Ge~~|dBm<br>~~Ge~~<br>~~Ge~~|
|**Inter-modulation Performance**[7]<br>~~Ge~~<br>~~Ce~~||||||
|BT, interferer signal level<br>~~Ce~~<br>~~a~~|BDR GFSK 0.1% BER<br>~~Ce~~|–<br>~~Ce~~|–<br>~~Ce~~|–39.0<br>~~Ce~~|dBm<br>~~Ce~~|
**Notes**
7. Dirty TX is Off.
8. Up to 1 dB of variation may potentially be seen from typical sensitivity specs due to the chip, board and associated variations.
9. The receiver sensitivity is measured at BER of 0.1% on the device interface.
10. Desired signal is 10 dB above the reference sensitivity level (defined as –70 dBm).
11. Desired signal is 3 dB above the reference sensitivity level (defined as –70 dBm).
12. Desired signal is -64 dBm Bluetooth-modulated signal, interferer 1 is –39 dBm sine wave at frequency f1, interferer 2 is –39 dBm Bluetooth modulated signal at frequency f2, f0 = 2 * f1 – f2, and |f2 – f1| = n * 1 MHz, where n is 3, 4, or 5. For the typical case, n = 4.
Document Number: 002-23993 Rev. *A
Page 32 of 50
**CYBT-483039-02**
**Table 22. Chipset Receiver RF Specifications** (continued)
|**Parameter**|**Mode and Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|
|**Spurious Emissions**||||||
|30 MHz to 1 GHz|–|–|–|–57.0|dBm|
|1 GHz to 12.75 GHz|–|–|–|–55.0|dBm|
## **Notes**
7. Dirty TX is Off.
8. Up to 1 dB of variation may potentially be seen from typical sensitivity specs due to the chip, board and associated variations.
9. The receiver sensitivity is measured at BER of 0.1% on the device interface.
10. Desired signal is 10 dB above the reference sensitivity level (defined as –70 dBm).
11. Desired signal is 3 dB above the reference sensitivity level (defined as –70 dBm).
12. Desired signal is -64 dBm Bluetooth-modulated signal, interferer 1 is –39 dBm sine wave at frequency f1, interferer 2 is –39 dBm Bluetooth modulated signal at frequency f2, f0 = 2 * f1 – f2, and |f2 – f1| = n * 1 MHz, where n is 3, 4, or 5. For the typical case, n = 4.
**Table 23. Chipset Transmitter RF Specifications**
|**Parameter**<br>~~a~~|**Min**<br>~~a~~|**Typ**<br>~~a~~|**Max**<br>~~a~~|**Unit**<br>~~a~~|
|---|---|---|---|---|
|**Transmitter Section**|||||
|Frequencyrange<br>~~a~~<br>~~a~~|2402<br>~~a~~|–<br>~~a~~|2480<br>~~a~~|MHz<br>~~a~~|
|Class 2: GFSK TXpower<br>~~a~~<br>~~a~~|–<br>~~a~~|4.0<br>~~a~~|–<br>~~a~~|dBm<br>~~a~~|
|Class 2: EDR TX Power<br>~~a~~<br>~~es~~|–<br>~~es~~|0<br>~~es~~|–<br>~~es~~|dBm<br>~~es~~|
|20 dB bandwidth<br>~~es~~|–<br>~~es~~|930<br>~~es~~|1000<br>~~es~~|kHz<br>~~es~~|
|**Adjacent Channel Power**<br>~~|~~|||||
||M – N|= 2<br>~~|~~<br>~~es~~|–<br>~~|~~<br>~~es~~|–<br>~~|~~<br>~~es~~|–20<br>~~|~~<br>~~es~~|dBm<br>~~|~~<br>~~es~~|
||M – N| 3<br>~~es~~|–<br>~~es~~|–<br>~~es~~|–40<br>~~es~~|dBm<br>~~es~~|
|**Out-of-Band Spurious Emission**<br>~~En~~|||||
|30 MHz to 1 GHz<br>~~a~~|–<br>~~a~~|–<br>~~a~~|–36.0<br>~~a~~|dBm<br>~~a~~|
|1 GHz to 12.75 GHz<br>~~a~~<br>~~ee~~<br>~~a~~|–<br>~~a~~<br>~~ee~~|–<br>~~a~~<br>~~ee~~|–30.0<br>~~a~~<br>~~ee~~|dBm<br>~~a~~<br>~~ee~~|
|1.8 GHz to 1.9 GHz<br>~~ee~~<br>~~a~~|–<br>~~ee~~|–<br>~~ee~~|–47.0<br>~~ee~~|dBm<br>~~ee~~|
|5.15 GHz to 5.3 GHz<br>~~a~~<br>~~GC~~|–<br>~~GC~~|–<br>~~GC~~|–47.0<br>~~GC~~|dBm<br>~~GC~~|
|**LO Performance**|||||
|Initial carrier frequencytolerance|–75|–|+75|kHz|
|**Frequency Drift**<br>~~En~~|||||
|DH1packet<br>~~a~~<br>~~a~~|–25<br>~~a~~|–<br>~~a~~|+25<br>~~a~~|kHz<br>~~a~~|
|DH3packet<br>~~a~~<br>~~a~~|–40<br>~~a~~|–<br>~~a~~|+40<br>~~a~~|kHz<br>~~a~~|
|DH5packet<br>~~a~~<br>~~es~~|–40<br>~~es~~|–<br>~~es~~|+40<br>~~es~~|kHz<br>~~es~~|
|Drift rate<br>~~es~~<br>~~ee~~|–20<br>~~es~~<br>~~ee~~|~~es~~<br>~~ee~~|20<br>~~es~~<br>~~ee~~|kHz/50µs<br>~~es~~<br>~~ee~~|
|**Frequency Deviation**<br>~~ee~~|||||
|Average deviation inpayload(sequence used is 00001111)<br>~~a~~|140<br>~~a~~|–<br>~~a~~|175<br>~~a~~|kHz<br>~~a~~|
|Maximum deviation inpayload(sequence used is 10101010)<br>~~a~~<br>~~ee~~|115<br>~~a~~<br>~~ee~~|–<br>~~a~~<br>~~ee~~|–<br>~~a~~<br>~~ee~~|kHz<br>~~a~~<br>~~ee~~|
|Channel spacing<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~|1<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~|MHz<br>~~ee~~<br>~~ee~~|
|**Modulation Accuracy**|||||
|/4-DQPSK FrequencyStability<br>~~a~~<br>~~a~~|–10<br>~~a~~|–<br>~~a~~|10<br>~~a~~|kHz<br>~~a~~|
|/4-DQPSK RMS DEVM<br>~~a~~<br>~~a~~|–<br>~~a~~|–<br>~~a~~|20<br>~~a~~|%<br>~~a~~|
|/4-QPSK Peak DEVM<br>~~a~~<br>~~es~~|–<br>~~es~~|–<br>~~es~~|35<br>~~es~~|%<br>~~es~~|
|/4-DQPSK 99% DEVM<br>~~es~~<br>~~ee~~<br>~~a~~|–<br>~~es~~<br>~~ee~~<br>|–<br>~~es~~<br>~~ee~~<br>|30<br>~~es~~<br>~~ee~~<br>|%<br>~~es~~<br>~~ee~~<br>|
|8-DPSK frequencystability<br>~~ee~~<br>~~a~~|–10<br>~~ee~~<br>|–<br>~~ee~~<br>|10<br>~~ee~~<br>|kHz<br>~~ee~~<br>|
|8-DPSK RMS DEVM<br>~~aes~~|–<br>~~es~~|–<br>~~es~~|13<br>~~es~~|%<br>~~es~~|
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**CYBT-483039-02**
**Table 23. Chipset Transmitter RF Specifications** (continued)
|**Parameter**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|
|8-DPSK Peak DEVM|–|–|25|%|
|8-DPSK 99% DEVM|–|–|20|%|
|**In-Band Spurious Emissions**|||||
|1.0 MHz <|M – N|< 1.5 MHz|–|–|–26|dBm|
|1.5 MHz <|M – N|< 2.5 MHz|–|–|–20|dBm|
||M – N|> 2.5 MHz|–|–|–40|dBm|
**Table 24. BLE RF Specifications**
|**Parameter**<br>~~Ge~~<br>~~**e**e~~|**Conditions**<br>~~Ge~~<br>|**Min**<br>~~Ge~~<br>~~(GO~~<br>|**Typ**<br>~~Ge~~<br>~~(GO~~<br>~~OO~~<br>|**Max**<br>~~Ge~~<br>~~I~~<br>~~OO~~<br>|**Unit**<br>~~Ge~~<br>|
|---|---|---|---|---|---|
|Frequencyrange<br>~~Ge~~<br>~~GG~~<br>~~**e**e~~|N/A<br>~~Ge~~<br>~~GG~~<br>|2402<br>~~Ge~~<br>~~(GO~~<br>~~GG~~<br>|–<br>~~Ge~~<br>~~(GO~~<br>~~GG~~<br>~~OO~~<br>|2480<br>~~Ge~~<br>~~I~~<br>~~GG~~<br>~~OO~~<br>|MHz<br>~~Ge~~<br>~~GG~~<br>|
|RX sensitivity (QFN)[13]<br>~~GG~~<br>~~**e**e~~|LE GFSK, 0.1% BER, 1 Mbps<br>~~GG~~<br>~~GG~~|–<br>~~GG~~<br>~~GG~~|–95.0[14]<br>~~GG~~<br>~~OO~~<br>~~GG~~|–<br>~~GG~~<br>~~OO~~<br>~~GG~~|dBm<br>~~GG~~<br>~~GG~~|
|TXpower<br>~~**e**e~~|BLE Silicon Device CYW20719 Only<br>~~GG~~<br>~~e~~|–<br>~~GG~~<br>~~e~~<br>~~GO~~|4.0<br>~~OO~~<br>~~GG~~<br>~~e~~<br>~~GO~~|–<br>~~OO~~<br>~~GG~~<br>~~e~~|dBm<br>~~GG~~<br>~~e~~|
|TXpower<br>~~eG~~|Module total outputpower<br>~~e~~<br>~~eG~~|–<br>~~e~~<br>~~eG~~<br>~~GO~~|–<br>~~e~~<br>~~eG~~<br>~~GO~~|20<br>~~e~~<br>~~eG~~|dBm<br>~~e~~<br>~~eG~~|
|Mod Char: Delta F1 average <br>~~eG~~<br>~~GC~~|N/A<br>~~eG~~<br>~~GC~~|225<br>~~eG~~<br>~~GO~~<br>~~GC~~|255<br>~~eG~~<br>~~GO~~<br>~~GC~~|275<br>~~eG~~<br>~~GC~~|kHz<br>~~eG~~<br>~~GC~~|
|Mod Char: Delta F2 max[15]<br>~~GC~~<br>~~ee~~|N/A<br>~~GC~~<br>~~ee~~|99.9<br>~~GC~~<br>~~ee~~|–<br>~~GC~~<br>~~ee~~<br>~~DO~~|–<br>~~GC~~<br>~~ee~~<br>~~DO~~|%<br>~~GC~~<br>~~ee~~|
|Mod Char: Ratio<br>~~ee~~<br>~~GG~~|N/A<br>~~ee~~<br>~~GG~~|0.8<br>~~ee~~<br>~~GG~~|0.95<br>~~ee~~<br>~~GG~~<br>~~DO~~|–<br>~~ee~~<br>~~GG~~<br>~~DO~~|%<br>~~ee~~<br>~~GG~~|
**Table 25. CYBT-483039-02 GPS and GLONASS Band Spurious Emission**
|**Parameter**|**Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|
|1570-1580 MHz|GPS|–|–160|–|dBm/Hz|
|1592-1610 MHz|GLONASS|–|–159|–|dBm/Hz|
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**CYBT-483039-02**
## **Timing and AC Characteristics**
In this section, use the numbers listed in the **Reference** column of each table to interpret the following timing diagrams.
## **UART Timing**
**Table 26. UART Timing Specifications**
|**Reference**|**Characteristics**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|
|1|Delay time, UART_CTS_N low to UART_TXD valid.|–|–|1.50|Bit periods|
|2|Setup time, UART_CTS_N high before midpoint of stop bit.|–|–|0.67|Bit periods|
|3|Delay time, midpoint of stop bit to UART_RTS_N high.|–|–|1.33|Bit periods|
## **Figure 14. UART Timing**
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**CYBT-483039-02**
## **SPI Timing**
The SPI interface can be clocked up to 24 MHz.
Table 27 and Figure 15 show the timing requirements when operating in SPI Mode 0 and 2.
## **Table 27. SPI Mode 0 and 2**
|**Reference**|**Characteristics**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|
|1|Time from master assert SPI_CSN to first clock edge|45|–|ns|
|2|Hold time for MOSI data lines|12|½ SCK|ns|
|3|Time from last sample on MOSI/MISO to slave deassert SPI_INT|0|100|ns|
|4|Time from slave deassert SPI_INT to master deassert SPI_CSN|0|–|ns|
|5|Idle time between subsequent SPI transactions|1 SCK|–|ns|
## **Figure 15. SPI Timing, Mode 0 and 2**
Document Number: 002-23993 Rev. *A
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**CYBT-483039-02**
Table 28 and Figure 16 show the timing requirements when operating in SPI Mode 1 and 3.
## **Table 28. SPI Mode 1 and 3**
|**Reference**|**Characteristics**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|
|1|Time from master assert SPI_CSN to first clock edge|45|–|ns|
|2|Hold time for MOSI data lines|12|½ SCK|ns|
|3|Time from last sample on MOSI/MISO to slave deassert SPI_INT|0|100|ns|
|4|Time from slave deassert SPI_INT to master deassert SPI_CSN|0|–|ns|
|5|Idle time between subsequent SPI transactions|1 SCK|–|ns|
**Figure 16. SPI Timing, Mode 1 and 3**
Document Number: 002-23993 Rev. *A
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**CYBT-483039-02**
## **I[2] C Compatible Interface Timing**
The specifications in Table 29 references Figure 17.
**Table 29. I[2] C Compatible Interface Timing Specifications (up to 1 MHz)**
|**Reference**|**Characteristics**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|
|1|Clock frequency|–|100|kHz|
||||400||
||||800||
||||1000||
|2|START condition setup time|650|–|ns|
|3|START condition hold time|280|–|ns|
|4|Clock low time|650|–|ns|
|5|Clock high time|280|–|ns|
|6|Data input hold time[16]|0|–|ns|
|7|Data input setup time|100|–|ns|
|8|STOP condition setup time|280|–|ns|
|9|Output valid from clock|–|400|ns|
|10|Bus free time[17]|650|–|ns|
## **Notes**
16. As a transmitter, 125 ns of delay is provided to bridge the undefined region of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 17. Time that the CBUS must be free before a new transaction can start.
## **Figure 17. I[2] C Interface Timing Diagram**
Document Number: 002-23993 Rev. *A
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**CYBT-483039-02**
## **I[2] S Interface Timing**
I[2] S timing is shown below in Table 30, Figure 18, and Figure 19.
**Table 30. Timing for I[2] S Transmitters and Receivers**
|**Parameter**<br>~~ee~~<br>~~pe~~<br>~~ee~~<br>~~po~~|**Transmitter**<br>~~ee~~<br>~~pe~~|**Transmitter**<br>~~ee~~<br>~~pe~~|**Transmitter**<br>~~ee~~<br>~~pe~~|**Transmitter**<br>~~ee~~<br>~~pe~~|**Receiver**<br>~~ee~~<br>~~pe~~|**Receiver**<br>~~ee~~<br>~~pe~~|**Receiver**<br>~~ee~~<br>~~pe~~|**Receiver**<br>~~ee~~<br>~~pe~~|**Notes**<br>~~pe~~|
|---|---|---|---|---|---|---|---|---|---|
||**Lower Limit**<br>~~ee~~<br>~~pe~~||**Upper Limit**<br>~~ee~~<br>~~pe~~||**Lower Limit**<br>~~ee~~<br>~~pe~~||**Upper Limit**<br>~~ee~~<br>~~pe~~|||
||**Min**<br>~~pe~~<br>~~ee~~|**Max**<br>~~pe~~<br>~~ee~~|**Min**<br>~~pe~~<br>~~ee~~|**Max**<br>~~pe~~<br>~~ee~~|**Min**<br>~~pe~~<br>~~ee~~|**Max**<br>~~pe~~<br>~~ee~~|**Min**<br>~~pe~~<br>~~ee~~|**Max**<br>~~pe~~<br>~~ee~~||
|Clock Period T<br>~~pe~~<br>~~ee~~<br>~~po~~|Ttr<br>~~pe~~<br>~~ee~~|–<br>~~pe~~<br>~~ee~~|–<br>~~pe~~<br>~~ee~~|–<br>~~pe~~<br>~~ee~~|Tr<br>~~pe~~<br>~~ee~~|–<br>~~pe~~<br>~~ee~~|–<br>~~pe~~<br>~~ee~~|–<br>~~pe~~<br>~~ee~~|Note 18<br>~~pe~~|
|**Master Mode: Clockgenerated by transmitter or receiver**<br>~~ee~~<br>~~po~~||||||||||
|HIGH tHC<br>~~po~~<br>~~pO~~|0.35Ttr<br>~~po~~|–<br>~~po~~|–<br>~~po~~|–<br>~~po~~|0.35Ttr<br>~~po~~|–<br>~~po~~|–<br>~~po~~|–<br>~~po~~|Note 19<br>~~po~~|
|LOWtLC<br>~~pO~~|0.35Ttr|–|–|–|0.35Ttr|–|–|–|Note 19|
|**Slave Mode: Clock accepted by transmitter or receiver**<br>~~pO~~||||||||||
|HIGH tHC<br>~~po~~<br>~~po~~|–<br>~~po~~|0.35Ttr<br>~~po~~|–<br>~~po~~|–<br>~~po~~|–<br>~~po~~|0.35Ttr<br>~~po~~|–<br>~~po~~|–<br>~~po~~|Note 20<br>~~po~~|
|LOW tLC<br>~~po~~<br>~~po~~|–|0.35Ttr|–|–|–|0.35Ttr|–|–|Note 20|
|Rise time tRC<br>~~po~~<br>~~po~~|–|–|0.15Ttr|–|–|–||–|Note 21|
|**Transmitter**<br>~~po~~||||||||||
|Delaytdtr<br>~~po~~<br>~~po~~|–<br>~~po~~|–<br>~~po~~|–<br>~~po~~|0.8T<br>~~po~~|–<br>~~po~~|–<br>~~po~~|–<br>~~po~~|–<br>~~po~~|Note 22<br>~~po~~|
|Hold time thtr<br>~~po~~<br>~~po~~|0<br>~~po~~|–<br>~~po~~|–<br>~~po~~|–<br>~~po~~|–<br>~~po~~|–<br>~~po~~|–<br>~~po~~|–<br>~~po~~|Note 21<br>~~po~~|
|**Receiver**<br>~~po~~||||||||||
|Setup time tsr<br>~~po~~<br>~~po~~|–<br>~~po~~|–<br>~~po~~|–<br>~~po~~|–<br>~~po~~|0.2Ttr<br>~~po~~|–<br>~~po~~|–<br>~~po~~|–<br>~~po~~|Note 23<br>~~po~~|
|Hold time thr<br>~~po~~|–|–|–|–|0.2Ttr|–|–|–|Note 23|
18. The system clock period T must be greater than Ttr and Tr because both the transmitter and receiver have to be able to handle the data transfer rate.
19. At all data rates in master mode, the transmitter or receiver generates a clock signal with a fixed mark/space ratio. For this reason, tHC and tLC are specified with respect to T.
20. In slave mode, the transmitter and receiver need a clock signal with minimum HIGH and LOW periods so that they can detect the signal. So long as the minimum periods are greater than 0.35Tr, any clock that meets the requirements can be used.
21. Because the delay (tdtr) and the maximum transmitter speed (defined by Ttr) are related, a fast transmitter driven by a slow clock edge can result in tdtr not exceeding tRC which means thtr becomes zero or negative. Therefore, the transmitter has to guarantee that thtr is greater than or equal to zero, so long as the clock rise-time tRC is not more than tRCmax, where tRCmax is not less than 0.15Ttr.
22. To allow data to be clocked out on a falling edge, the delay is specified with respect to the rising edge of the clock signal and T, always giving the receiver sufficient setup time.
23. The data setup and hold time must not be less than the specified receiver setup and hold time.
Document Number: 002-23993 Rev. *A
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**CYBT-483039-02**
## **Figure 18. I[2] S Transmitter Timing**
## **Figure 19. I[2] S Receiver Timing**
Document Number: 002-23993 Rev. *A
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**CYBT-483039-02**
## **Environmental Specifications**
## **Environmental Compliance**
This Cypress BLE module is produced in compliance with the Restriction of Hazardous Substances (RoHS) and Halogen-Free (HF) directives. The Cypress module and components used to produce this module are RoHS and HF compliant.
## **RF Certification**
The CYBT-483039-02 module is certified under the following RF certification standards:
■ FCC: WAP3039
■ IC: 7922A-3039
- MIC: 203-JN0875
- CE
## **Safety Certification**
The CYBT-483039-02 module complies with the following safety regulations:
■ Underwriters Laboratories, Inc. (UL): Filing E331901
■ CSA
- TUV
## **Environmental Conditions**
Table 31 describes the operating and storage conditions for the Cypress BLE module.
## **Table 31. Environmental Conditions for CYBT-483039-02**
|**Description**|**Minimum Specification**|**Maximum Specification**|
|---|---|---|
|Operating temperature|30 °C|85 °C|
|Operating humidity (relative, non-condensation)|5%|85%|
|Thermal ramp rate|–|10 °C/minute|
|Storage temperature|–40 °C|85 °C|
|Storage temperature and humidity|–|85 °C at 85%|
|ESD: Module integrated into system Components[24]|–|15 kV Air<br>2.0 kV Contact|
## **ESD and EMI Protection**
Exposed components require special attention to ESD and electromagnetic interference (EMI).
A grounded conductive layer inside the device enclosure is suggested for EMI and ESD performance. Any openings in the enclosure near the module should be surrounded by a grounded conductive layer to provide ESD protection and a low-impedance path to ground. **Device Handling** : Proper ESD protocol must be followed in manufacturing to ensure component reliability.
> 24. This does not apply to the RF pins (ANT).
**Note**
Document Number: 002-23993 Rev. *A
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**CYBT-483039-02**
## **Regulatory Information**
## **FCC**
## FCC NOTICE:
The device CYBT-483039-02 complies with Part 15 of the FCC Rules. The device meets the requirements for modular transmitter approval as detailed in FCC public Notice DA00-1407.transmitter Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation.
## CAUTION:
The FCC requires the user to be notified that any changes or modifications made to this device that are not expressly approved by Cypress Semiconductor may void the user's authority to operate the equipment.
This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions,ê may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures:
■ Reorient or relocate the receiving antenna.
■ Increase the separation between the equipment and receiver.
■ Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
■ Consult the dealer or an experienced radio/TV technician for help
## LABELING REQUIREMENTS:
The Original Equipment Manufacturer (OEM) must ensure that FCC labelling requirements are met. This includes a clearly visible label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor FCC identifier for this product as well as the FCC Notice above. The FCC identifier is FCC ID: WAP3039.
In any case the end product must be labeled exterior with “Contains FCC ID: WAP3039”.
## ANTENNA WARNING:
This device is tested with a standard SMA connector and with the antenna listed in Table 7 on page 15. When integrated in the OEMs product, this fixed antenna requires installation preventing end-users from replacing them with non-approved antennas. Any antenna not in Table 7 must be tested to comply with FCC Section 15.203 for unique antenna connectors and Section 15.247 for emissions.
## RF EXPOSURE:
To comply with FCC RF Exposure requirements, the Original Equipment Manufacturer (OEM) must ensure to install the approved antenna in the previous.
The preceding statement must be included as a CAUTION statement in manuals, for products operating with the approved antennas in Table 7, to alert users on FCC RF Exposure compliance. Any notification to the end user of installation or removal instructions about the integrated radio module is not allowed.
The radiated output power of CYBT-483039-02 with the integrated chip antenna (FCC ID: WAP3039) is far below the FCC radio frequency exposure limits. Nevertheless, use CYBT-483039-02 in such a manner that minimizes the potential for human contact during normal operation.
End users may not be provided with the module installation instructions. OEM integrators and end users must be provided with transmitter operating conditions for satisfying RF exposure compliance.
Document Number: 002-23993 Rev. *A
Page 42 of 50
**CYBT-483039-02**
## **ISED**
## **Innovation, Science and Economic Development (ISED) Canada Certification**
CYBT-483039-02 is licensed to meet the regulatory requirements of Innovation, Science and Economic Development (ISED) Canada. License: IC: 7922A-3039
Manufacturers of mobile, fixed or portable devices incorporating this module are advised to clarify any regulatory questions and ensure compliance for SAR and/or RF exposure limits. Users can obtain Canadian information on RF exposure and compliance from www.ic.gc.ca.
This device has been designed to operate with the antennas listed in Table 7 on page 15, having a maximum gain of -0.5 dBi. Antennas not included in Table 7 or having a gain greater than -0.5 dBi are strictly prohibited for use with this device. The required antenna impedance is 50 . The antenna used for this transmitter must not be co-located or operating in conjunction with any other antenna or transmitter.
## ISED NOTICE:
The device CYBT-483039-02 including the built-in trace antenna complies with Canada RSS-GEN Rules. The device meets the requirements for modular transmitter approval as detailed in RSS-GEN. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation.
L'appareil CYBT-483039-02, y compris l'antenne intégrée, est conforme aux Règles RSS-GEN de Canada. L'appareil répond aux exigences d'approbation de l'émetteur modulaire tel que décrit dans RSS-GEN. L'opération est soumise aux deux conditions suivantes: (1) Cet appareil ne doit pas causer d'interférences nuisibles, et (2) Cet appareil doit accepter toute interférence reçue, y compris les interférences pouvant entraîner un fonctionnement indésirable.
## ISED INTERFERENCE STATEMENT FOR CANADA
This device complies with Innovation, Science and Economic Development (ISED) Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device.
Cet appareil est conforme à la norme sur l'innovation, la science et le développement économique (ISED) norme RSS exempte de licence. L'exploitation est autorisée aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
## ISED RADIATION EXPOSURE STATEMENT FOR CANADA
This equipment complies with ISED radiation exposure limits set forth for an uncontrolled environment.
Cet équipement est conforme aux limites d'exposition aux radiations ISED prévues pour un environnement incontrôlé.
## LABELING REQUIREMENTS:
The Original Equipment Manufacturer (OEM) must ensure that ISED labelling requirements are met. This includes a clearly visible label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor IC identifier for this product as well as the ISED Notices above. The IC identifier is 7922A-3039. In any case, the end product must be labeled in its exterior with “Contains IC: 7922A-3039”.
Le fabricant d'équipement d'origine (OEM) doit s'assurer que les exigences d'étiquetage ISED sont respectées. Cela comprend une étiquette clairement visible à l'extérieur de l'enceinte OEM spécifiant l'identifiant Cypress Semiconductor IC approprié pour ce produit ainsi que l'avis ISED ci-dessus. L'identificateur IC est 7922A-3039. En tout cas, le produit final doit être étiqueté dans son extérieur avec “Contient IC: 7922A-3039”.
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**CYBT-483039-02**
## **European Declaration of Conformity**
Hereby, Cypress Semiconductor declares that the Bluetooth module CYBT-483039-02 complies with the essential requirements and other relevant provisions of Directive 2014. As a result of the conformity assessment procedure described in Annex III of the Directive 2014, the end-customer equipment should be labeled as follows:
All versions of the CYBT-483039-02 in the specified reference design can be used in the following countries: Austria, Belgium, Cyprus, Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, Poland, Portugal, Slovakia, Slovenia, Spain, Sweden, The Netherlands, the United Kingdom, Switzerland, and Norway.
## **MIC Japan**
More Part Numbers is certified as a module with certification number 203-JN0875. End products that integrate More Part Numbers do not need additional MIC Japan certification for the end product.
End product can display the certification label of the embedded module.
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**CYBT-483039-02**
## **Packaging**
**Table 32. Solder Reflow Peak Temperature**
|**Module Part Number**|**Package**|**Maximum Peak Temperature**|**Maximum Time at Peak Temperature**|**No. of Cycles**|
|---|---|---|---|---|
|CYBT-483039-02|34-pad SMT|260 °C|30 seconds|2|
**Table 33. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2**
|**Module Part Number**|**Package**|**MSL**|
|---|---|---|
|CYBT-483039-02|34-pad SMT|MSL 3|
The CYBT-483039-02 is offered in tape and reel packaging. Figure 20 details the tape dimensions used for the CYBT-483039-02.
**Figure 20. CYBT-483039-02 Tape Dimensions**
Figure 21 details the orientation of the CYBT-483039-02 in the tape as well as the direction for unreeling.
**Figure 21. Component Orientation in Tape and Unreeling Direction (TBD)**
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**CYBT-483039-02**
Figure 22 details reel dimensions used for the CYBT-483039-02.
**Figure 22. Reel Dimensions**
The CYBT-483039-02 is designed to be used with pick-and-place equipment in an SMT manufacturing environment. The center-of-mass for the CYBT-483039-02 is detailed in Figure 23.
**Figure 23. CYBT-483039-02 Center of Mass**
**Top View (Seen from Top)**
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**CYBT-483039-02**
## **Ordering Information**
Table 34 lists the CYBT-483039-02 part number and features. Table 34 also lists the target program for the respective module ordering codes. Table 35 lists the reel shipment quantities for the CYBT-483039-02.
## **Table 34. Ordering Information**
|**Ordering Part**<br>**Number**|**Max CPU**<br>**Speed**<br>**(MHz)**|**Flash**<br>**Size**<br>**(KB)**|**RAM**<br>**Size**<br>**(KB)**|**UART**|**I2C**|**SPI**|**I2S**|**PCM**|**PWM**|**ADC**<br>**Inputs**|**GPIOs**|**Package**|**Packaging**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|CYBT-483039-02|96|1024|512|Yes|Yes|Yes|Yes|Yes|6|10|15|34-SMT|Tape and Reel|
**Table 35. Tape and Reel Package Quantity and Minimum Order Amount**
|**Description**|**Minimum Reel Quantity**|**Maximum Reel Quantity**|**Comments**|
|---|---|---|---|
|Reel Quantity|500|500|Ships in 500 unit reel quantities.|
|Minimum Order Quantity (MOQ)|500|–|–|
|Order Increment (OI)|500|–|–|
The CYBT-483039-02 is offered in tape and reel packaging. The CYBT-483039-02 ships in a reel size of 500 units.
For additional information and a complete list of Cypress Semiconductor Bluetooth products, contact your local Cypress sales representative. To locate the nearest Cypress office, visit our website.
|U.S. Cypress Headquarters Address|198 Champion Court, San Jose, CA 95134|
|---|---|
|U.S. Cypress Headquarter Contact Info|(408) 943-2600|
|Cypress website address|http://www.cypress.com|
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**CYBT-483039-02**
## **Acronyms**
## **Table 36. Acronyms Used in this Document**
|**Acronym**|**Description**|
|---|---|
|BLE|Bluetooth Low Energy|
|Bluetooth<br>SIG|Bluetooth Special Interest Group|
|CE|European Conformity|
|CSA|Canadian Standards Association|
|EMI|electromagnetic interference|
|ESD|electrostatic discharge|
|FCC|Federal Communications Commission|
|GPIO|general-purpose input/output|
|ISED|Innovation, Science and Economic Development<br>(Canada)|
|IDE|integrated design environment|
|KC|Korea Certification|
|MIC|Ministry of Internal Affairs and Communications<br>(Japan)|
|OTA|Over-the-Air|
|PCB|printed circuit board|
|RX|receive|
|QDID|qualification design ID|
|SMT|surface-mount technology; a method for<br>producing electronic circuitry in which the compo-<br>nents are placed directly onto the surface of<br>PCBs|
|TCPWM|timer, counter, pulse width modulator (PWM)|
|TUV|Germany: Technischer Überwachungs-Verein<br>(Technical Inspection Association)|
|TX|transmit|
## **Document Conventions**
## **Units of Measure**
## **Table 37. Units of Measure**
|**Symbol**|**Unit of Measure**|
|---|---|
|°C|degree Celsius|
|kV|kilovolt|
|mA|milliamperes|
|mm|millimeters|
|mV|millivolt|
|µA|microamperes|
|µm|micrometers|
|MHz|megahertz|
|GHz|gigahertz|
|V|volt|
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**CYBT-483039-02**
## **Document History Page**
**Document Title: CYBT-483039-02, EZ-BT™ XR WICED[®] Module Document Number: 002-23993**
|**Document Title: CYBT-483039-02, EZ-BT™ XR WICED[®] Module**<br>**Document Number: 002-23993**|**Document Title: CYBT-483039-02, EZ-BT™ XR WICED[®] Module**<br>**Document Number: 002-23993**|**Document Title: CYBT-483039-02, EZ-BT™ XR WICED[®] Module**<br>**Document Number: 002-23993**|**Document Title: CYBT-483039-02, EZ-BT™ XR WICED[®] Module**<br>**Document Number: 002-23993**|**Document Title: CYBT-483039-02, EZ-BT™ XR WICED[®] Module**<br>**Document Number: 002-23993**|
|---|---|---|---|---|
|**Revision**|**ECN**|**Orig. of**<br>**Change**|**Submission**<br>**Date**|**Description of Change**|
|**|6195905|DSO|06/01/2018|Preliminary datasheet for CYBT-483039-02 module.|
|*A|6413419|DSO|01/04/2019|Final datasheet for CYBT-483039-02 module.<br>UpdatedModule Descriptionto update Bluetooth QDID and Declaration ID.<br>UpdatedReferencesto add additional items.<br>UpdatedTable 5to outline final functions available with SuperMux Configurator.<br>UpdatedTable 14detailing module and silicon current consumption.<br>UpdatedRF CertificationandMIC Japanto state final MIC certification identification number.<br>Added drawings forFigure 21andFigure 23.<br>Updated Acronyms: Added Over-the-Air (OTA).|
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**CYBT-483039-02**
## **Sales, Solutions, and Legal Information**
## **Worldwide Sales and Design Support**
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.
## **Products**
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## **PSoC[®] Solutions**
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## **Cypress Developer Community**
Forums | WICED IOT Forums | Projects | Video | Blogs | Training | Components
## **Technical Support**
cypress.com/support
© Cypress Semiconductor Corporation, 2018-2019. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress does not assume any liability arising out of any security breach, such as unauthorized access to or use of a Cypress product. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-23993 Rev. *A
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Revised January 4, 2019
Updated at February 9, 2023
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