CYBT-343026-01

Bluetooth 5.0 + EDR, 2.3V to 3.6V Supply, EZ-BT WICED Series Range, 3Mbps, -89.5dBm Sensitivity

⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
Manufacturer: INFINEON
Product type: Bluetooth Modules & Adaptors
Bluetooth Version:Bluetooth 5.0 + EDR; Supply Voltage Min:2.3V; Supply Voltage Max:3.6V; Signal Range Max:-; Data Rate:3Mbps; Bluetooth Class:-; Receive Sensitivity:-89.5dBm; Operatin
SVHC: No SVHC (25-Jun-2025)
Interfaces: I2C, SPI, UART
Product Range: EZ-BT WICED Series
Certifications: CE, FCC, ISED, MIC
Bluetooth Class: -
Bluetooth Version: Bluetooth 5.0 + EDR
Supply Voltage Range: 2.3 V to 3.6 V
Receiver Sensitivity Rx: -89.5 dBm
Operating Temperature Range: -30 °C to 85 °C
Delivery and price
Units per pack	250
Price	5.72 €
Current stock	200+
Lead time	30 days
Datasheet
**CYBT-343026-01** 

EZ-BT[™ ] WICED[®] Module 

## **General Description** 

The CYBT-343026-01 is a fully integrated Bluetooth[] Smart Ready wireless module. The CYBT-343026-01 includes an onboard crystal oscillator, passive components, flash memory, and the Cypress CYW20706 silicon device. Refer to the CYW20706 datasheet for additional details on the capabilities of the silicon device used in this module. 

The CYBT-343026-01 supports peripheral functions (ADC and PWM), UART, I[2] C, and SPI communication, and a PCM/I2S audio interface. The CYBT-343026-01 includes a royalty-free Bluetooth stack compatible with Bluetooth 5.0 in a 12.0 × 15.5 × 1.95 mm package. 

The CYBT-343026-01 includes 512 KB of onboard serial flash memory and is designed for standalone operation. The CYBT-343026-01 uses an integrated power amplifier to achieve Class I or Class II output power capability. 

The CYBT-343026-01 is fully qualified by Bluetooth SIG and is targeted at applications requiring cost optimized Bluetooth wireless connectivity. 

## **Module Description** 

- Module size: 12.00 mm × 15.50 mm × 1.95 mm 

- Bluetooth 5.0 Qualified Smart Ready module 

- ❐ QDID: 99198 

- ❐ Declaration ID: D035378 

- Certified to FCC, ISED, MIC, and CE regulations 

- Castelated solder pad connections for ease-of-use 

- 512-KB on-module serial flash memory 

## **Power Consumption** 

- Enhanced Data Rate (EDR) at 8 dBm 

- ❐ Peak TX current: 52.5 mA 

- ❐ Peak RX current consumption: 26.4 mA 

- Bluetooth Low Energy (BLE) at 0 dBm 

- ❐ 1-second interval BLE ADV average current consumption: 315 uA 

- Low power mode support 

- ❐ Deep Sleep: 2.69 uA 

## **Functional Capabilities** 

- - ADC for audio (12 bits) and DC measurement (10 bits) 

- Serial Communications interface compatible with I[2] C slaves 

- Serial Peripheral Interface (SPI) support for both master and slave modes 

- HCI interface through UART 

- PCM/I2S Audio interface 

- Two-wire Global Coexistence Interface (GCI) 

- Integrated peripherals such as PWM, ADC 

- Programmable output power control 

- Supports extended synchronous connections (eSCO), for enhanced voice quality by allowing for retransmission of dropped packets 

- Bluetooth wideband speech support 

## **Benefits** 

- Up to 11 GPIOs 

- Temperature range: –30 °C to +85 °C 

- Cortex-M3 32-bit processor 

- Maximum TX output power 

- ❐ +12 dbm for Bluetooth Classic 

- ❐ +9 dBm for Bluetooth Low Energy 

- BLE connection range of up to 250 meters at 9 dBm[[1]] 

- RX Receive Sensitivity: 

- ❐ Bluetooth Classic: 

- –93.5 dBm at 1 Mbps, GFSK 

- –95.5 dBm at 2 Mbps, /4-DQPSK 

- –89.5 dBm at 3 Mbps, 8-DPSK 

- ❐ –96.5 dBm for Bluetooth Low Energy 

CYBT-343026-01 provides all necessary components required to operate BLE and/or BR/EDR communication standards. 

- Proven hardware design ready to use 

- Dual-mode operation eliminates the need for multiple modules 

- Cost optimized for applications without space constraints 

- Nonvolatile memory for self-sufficient operation and Over-the-air updates 

- Bluetooth SIG Listed with QDID and Declaration ID 

- Fully certified module eliminates the time needed for design, development and certification processes 

- WICED[®] Studio provides an easy-to-use integrated design environment (IDE) to configure, develop, and program a Bluetooth application 

## **Note** 

1. Connection range tested module-to-module in full line-of-sight environment, free of obstacles or interference sources with output power of +9.0 dBm. Actual range will vary based on end product design, environment, receive sensitivity and transmit output power of the central device. 

**Cypress Semiconductor Corporation** • 198 Champion Court Document Number: 002-19525 Rev. *B 

San Jose, CA 95134-1709 • 408-943-2600 Revised April 26, 2018 

• 

**CYBT-343026-01** 

## **More Information** 

Cypress provides a wealth of data at www.cypress.com to help you to select the right module for your design, and to help you to quickly and effectively integrate the module into your design. 

## **References** 

■ Overview: EZ-BLE/BT Module Portfolio, Module Roadmap 

■ CYW20706 BT Silicon Datasheet 

- Development Kits: 

- ❐ CYBT-343026-EVAL, CYBT-343026-01 Evaluation Board 

- Test and Debug Tools: 

- ❐ CYSmart, Bluetooth[®] LE Test and Debug Tool (Windows) 

- ❐ CYSmart Mobile, Bluetooth[®] LE Test and Debug Tool (Android/iOS Mobile App) 

## ■ Knowledge Base Article 

- ❐ KBA97095 - EZ-BLE™ Module Placement 

- ❐ KBA213260- RF Regulatory Certifications for CYBT-343026-01 EZ-BT™ WICED Modules 

- ❐ KBA213976 - FAQ for BLE and Regulatory Certifications with EZ-BLE modules 

- ❐ KBA210802 - Queries on BLE Qualification and Declaration Processes 

- ❐ KBA218122 - 3D Model Files for EZ-BLE/EZ-BT Modules 

- ❐ KBA221025 - Platform Files for CYBT-343026-EVAL 

- ❐ KBA223428 - Programming an EZ-BT WICED Module 

## **Development Environments** 

## _Wireless Connectivity for Embedded Devices (WICED) Studio Software Development Kit (SDK)_ 

Cypress' WICED[®] (Wireless Connectivity for Embedded Devices) is a full-featured platform with proven Software Development Kits (SDKs) and turnkey hardware solutions from partners to readily enable Wi-Fi and Bluetooth® connectivity in system design. 

WICED Studio is the only SDK for the Internet of Things (IoT) that combines Wi-Fi and Bluetooth into a single integrated development environment. In addition to providing WICED APIs and an application framework designed to abstract complexity, WICED Studio also leverages many common industry standards. 

## **Technical Support** 

- Cypress Community: Whether you’re a customer, partner or a developer interested in the latest Cypress innovations, the Cypress Developer Community offers you a place to learn, share and engage with both Cypress experts and other embedded engineers around the world. 

- Frequently Asked Questions (FAQs): Learn more about our Bluetooth ECO System. 

- Visit our support page and create a technical support case or contact a local sales representatives. If you are in the United States, you can talk to our technical support team by calling our toll-free number: +1-800-541-4736. Select option 2 at the prompt. 

Page 2 of 52 

Document Number: 002-19525 Rev. *B 

**CYBT-343026-01** 

## **Contents** 

**Overview............................................................................ 4** Functional Block Diagram ........................................... 4 Module Description...................................................... 4 **Pad Connection Interface ................................................ 6 Recommended Host PCB Layout ................................... 7 Module Connections ........................................................ 9 Connections and Optional External Components....... 10** Power Connections (VDDIN)..................................... 10 External Reset (XRES).............................................. 10 Multiple-Bonded GPIO Connections ......................... 11 Critical Components List ........................................... 13 Antenna Design......................................................... 13 **Functional Description................................................... 14** Bluetooth Baseband Core ......................................... 14 Microcontroller Unit ................................................... 16 External Reset (XRES).............................................. 17 **Integrated Radio Transceiver........................................ 18** Transmitter Path........................................................ 18 Receiver Path............................................................ 18 Local Oscillator Generation....................................... 18 Calibration ................................................................. 18 Internal LDO.............................................................. 19 **Collaborative Coexistence............................................. 19 Global Coexistence Interface ........................................ 19** SECI I/O .................................................................... 19 **Peripheral and Communication Interfaces .................. 20** I2C Communication Interface.................................... 20 HCI UART Interface .................................................. 20 Peripheral UART Interface ........................................ 21 Serial Peripheral Interface......................................... 21 PCM Interface ........................................................... 21 **Clock Frequencies.......................................................... 21 GPIO Port ........................................................................ 22 PWM................................................................................. 22 Power Management Unit................................................ 24** RF Power Management ............................................ 24 Host Controller Power Management ......................... 24 BBC Power Management.......................................... 24 

**Electrical Characteristics............................................... 25 Chipset RF Specifications ............................................. 27 Timing and AC Characteristics ..................................... 30** UART Timing............................................................. 30 SPI Timing................................................................. 31 I2C Interface Timing.................................................. 33 PCM Interface Timing................................................ 34 I2S Interface Timing .................................................. 38 **Environmental Specifications ....................................... 41** Environmental Compliance ....................................... 41 RF Certification.......................................................... 41 Safety Certification .................................................... 41 Environmental Conditions ......................................... 41 ESD and EMI Protection ........................................... 41 **Regulatory Information.................................................. 42** FCC........................................................................... 42 ISED.......................................................................... 43 European Declaration of Conformity ......................... 44 MIC Japan................................................................. 44 **Packaging........................................................................ 45 Ordering Information...................................................... 47 Acronyms........................................................................ 48 Document Conventions ................................................. 50** Units of Measure ....................................................... 50 **Document History Page................................................. 51 Sales, Solutions, and Legal Information ...................... 52** Worldwide Sales and Design Support....................... 52 Products .................................................................... 52 PSoC® Solutions ...................................................... 52 Cypress Developer Community................................. 52 Technical Support ..................................................... 52 

Page 3 of 52 

Document Number: 002-19525 Rev. *B 

**CYBT-343026-01** 

## **Overview** 

## **Functional Block Diagram** 

Figure 1 illustrates the CYBT-343026-01 functional block diagram. 

**Figure 1.  Functional Block Diagram (GPIOs)** 

## **Module Description** 

The CYBT-343026-01 module is a complete module designed to be soldered to the application’s main board. 

## _Module Dimensions and Drawing_ 

Cypress reserves the right to select components from various vendors to achieve the Bluetooth module functionality. Such selections will still guarantee that all mechanical specifications and module certifications are maintained. Designs should be held within the physical dimensions shown in the mechanical drawings in Figure 2 on page 5. All dimensions are in millimeters (mm). 

## **Table 1.  Module Design Dimensions** 

|**Dimension Item**|**Dimension Item**|**Specification**|
|---|---|---|
|Module dimensions|Length (X)|12.00 ± 0.15 mm|
||Width (Y)|15.50 ± 0.15 mm|
|Antenna connection location dimensions|Length (X)|12.0 mm|
||Width (Y)|4.62 mm|
|PCB thickness|Height (H)|0.50 ± 0.05 mm|
|Shield height|Height (H)|1.45 mm typical|
|Maximum component height|Height (H)|1.45 mm typical|
|Total module thickness (bottom of module to highest component)|Height (H)|1.95 mm typical|



See Figure 2 for the mechanical reference drawing for CYBT-343026-01. 

Page 4 of 52 

Document Number: 002-19525 Rev. *B 

**CYBT-343026-01** 

**Figure 2.  Module Mechanical Drawing**[[2, 3]] 

**==> picture [48 x 8] intentionally omitted <==**

**----- Start of picture text -----**<br>
Side View<br>**----- End of picture text -----**<br>


## **Top View (Seen from Top)** 

**==> picture [65 x 9] intentionally omitted <==**

**----- Start of picture text -----**<br>
Bottom View<br>**----- End of picture text -----**<br>


## **Notes** 

2. No metal should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area. For more information on recommended host PCB layout, see “Recommended Host PCB Layout” on page 7. 

3. The CYBT-343026-01 includes castellated pad connections, denoted as the circular openings at the pad location above. 

Page 5 of 52 

Document Number: 002-19525 Rev. *B 

**CYBT-343026-01** 

## **Pad Connection Interface** 

As shown in the bottom view of Figure 2 on page 5, the CYBT-343026-01 connects to the host board via solder pads on the backside of the module. Table 2 and Figure 3 detail the solder pad length, width, and pitch dimensions of the CYBT-343026-01 module. 

**Table 2.  Connection Description** 

|**Name**|**Connections**|**Connection Type**|**Pad Length Dimension**|**Pad Width Dimension**|**Pad Pitch**|
|---|---|---|---|---|---|
|SP|24|Solder Pads|1.02 mm|0.71 mm|1.22 mm|
|||**Figure 3.  Solder Pad Dimensions (Seen from Bottom**||||



To maximize RF performance, the host layout should follow these recommendations: 

1. Antenna Area Keepout: The host board directly below the antenna area of the Cypress module (see Figure 2 on page 5) must contain no ground or signal traces. This keep out area requirement applies to all layers of the host board. 

2. Module Placement: The ideal placement of the Cypress Bluetooth module is in a corner of the host board with the PCB trace antenna located at the far corner. This placement minimizes the additional recommended keep out area stated in item 2. Refer to AN96841 for module placement best practices. 

**Figure 4.  Recommended Host PCB Keep Out Area Around the CYBT-343026-01 Antenna** 

Page 6 of 52 

Document Number: 002-19525 Rev. *B 

**CYBT-343026-01** 

## **Recommended Host PCB Layout** 

Figure 5, Figure 6, Figure 7, and Table 3 provide details that can be used for the recommended host PCB layout pattern for the CYBT-343026-01. Dimensions are in millimeters unless otherwise noted. Pad length of 1.27 mm (0.635 mm from center of the pad on either side) shown in Figure 7 is the minimum recommended host pad length. The host PCB layout pattern can be completed using either Figure 5, Figure 6, or Figure 7. It is not necessary to use all figures to complete the host PCB layout pattern. 

**Figure 5.  CYBT-343026-01 Host Layout (Dimensioned)** 

**Figure 6.  CYBT-343026-01 Host Layout (Relative to Origin)** 

**Top View (Seen on Host PCB)** 

**Top View (Seen on Host PCB)** 

Page 7 of 52 

Document Number: 002-19525 Rev. *B 

**CYBT-343026-01** 

Table 3 provides the center location for each solder pad on the CYBT-343026-01. All dimensions are referenced to the center of the solder pad. Refer to Figure 7 for the location of each module solder pad. 

**Table 3.  Module Solder Pad Location** 

|**Solder Pad**<br>**(Center of Pad)**|**Location (X,Y) from**<br>**Orign (mm)**|**Dimension from**<br>**Orign (mils)**|
|---|---|---|
|1|(0.38, 5.04)|(14.96, 198.42)|
|2<br>~~ee ee~~|(0.38, 6.26)<br>~~ee~~|(14.96, 246.46)|
|3<br>~~ee ee~~|(0.38, 7.48)<br>~~ee~~|(14.96, 294.49)|
|4<br>~~ee ee~~<br>~~i~~|(0.38, 8.70)<br>~~ee~~|(14.96, 342.52)|
|5<br>~~i~~<br>~~ee ee~~|(0.38, 9.92)<br>~~ee~~|(14.96, 390.55)|
|6<br>~~ee ee~~<br>~~ee~~|(0.38, 11.14)<br>~~ee~~|(14.96, 438.58)|
|7<br>~~ee ee~~<br>~~ee~~<br>~~es ee~~|(0.38, 12.35)<br>~~ee~~<br>~~ee~~|(14.96, 486.22)|
|8<br>~~ee~~<br>~~es ee~~|(0.38, 13.57)<br>~~ee~~|(14.96, 534.25)|
|9<br>~~es ee~~|(1.73, 15.11)<br>~~ee~~|(68.11, 594.88)|
|10<br>~~pats~~|(2.95, 15.11)<br>~~pats~~|(116.14, 594.88)<br>~~pats~~|
|11<br>~~pats~~|(4.17, 15.11)<br>~~pats~~|(164.17, 594.88)<br>~~pats~~|
|12|(5.39, 15.11)|(212.20, 594.88)|
|13|(6.61, 15.11)|(260.24, 594.88)|
|14|(7.83, 15.11)|(308.27, 594.88)|
|15|(9.05, 15.11)|(356.30, 594.88)|
|16|(10.27, 15.11)|(404.33, 594.88)|
|17<br>~~ee ee~~|(11.62, 13.57)<br>~~ee~~|(457.48, 534.25)|
|18<br>~~ee ee~~|(11.62, 12.35)<br>~~ee~~|(457.48, 486.22)|
|19<br>~~ee ee~~<br>~~es ee~~|(11.62, 11.14)<br>~~ee~~<br>~~ee~~|(457.48, 438.58)|
|20<br>~~es ee~~|(11.62, 9.92)<br>~~ee~~|(457.48, 390.55)|
|21<br>~~es ee~~|(11.62, 8.70)<br>~~ee~~|(457.48, 342.52)|
|22|(11.62, 7.48)|(457.48, 294.49)|
|23|(11.62, 6.26)|(457.48, 246.46)|
|24|(11.62, 5.04)|(457.48, 198.42)|



**Figure 7.  Solder Pad Reference Location** 

## **Top View (Seen on Host PCB)** 

Page 8 of 52 

Document Number: 002-19525 Rev. *B 

**CYBT-343026-01** 

## **Module Connections** 

Table 4 details the solder pad connection definitions and available functions for the pad connections for the CYBT-343026-01 module. Table 4 lists the solder pads on the CYBT-343026-01 module, the silicon device pin, and denotes what functions are available for each solder pad. 

**Table 4.  CYBT-343026-01 Solder Pad Connection Definitions** 

|**Pad**<br>~~TLL~~<br>~~ae~~|**Pad**<br>**Pad Name**<br>~~TLL~~<br>~~ae~~|**Silicon**<br>**Pin**<br>**Name**<br>~~TLL~~<br>~~es~~|**Silicon**<br>**Port-Pin Name**<br>~~TLL~~<br>~~es~~|**UART**<br>~~TLL~~<br>~~ee~~|**SPI**[4,5]<br>~~TLL~~<br>~~ITLL~~<br>~~ee~~|**I2C**<br>~~TLL~~<br>~~ITLL~~<br>~~ee~~|**ADC**<br>~~TLL~~<br>~~ITLL~~<br>~~ss~~|**COEX**<br>~~TLL~~<br>~~ITLLILL~~<br>~~ss~~|**CLK/**<br>**XTAL**<br>~~TLL~~<br>~~ILL~~|**GPIO**<br>~~TLL~~<br>~~ILL~~|**Other**<br>~~TLL~~<br>~~ILL~~|
|---|---|---|---|---|---|---|---|---|---|---|---|
|1<br>~~ae~~|P0/P34<br>~~ae~~|C8<br>~~es~~|PCM_Sync/<br>I2S_WS/P0/P34<br>~~es~~|PUART_TX/P0<br>PUART_RX/P34<br>~~ee~~|SPI1_MOSI/P0<br>(master/slave)<br>~~ITLL~~<br>~~ee~~|~~ITLL~~<br>~~ee~~|IN29/P0<br>IN5/P34<br>~~ITLL~~<br>~~ss~~|~~ITLLILL~~<br>~~ss~~|~~ILL~~|✓<br>~~ILL~~|PCM_Sync<br>I2S_WS<br>~~ILL~~|
|2<br>~~ae~~<br>~~a~~|I2C_SCL<br>~~ae ~~<br>~~a~~|A8<br> ~~es~~<br>~~a~~|I2S_DO/<br>PCM_Out/P3/<br>P29/P35<br>~~es~~<br>~~a~~|PUART_CTS/<br>P3 or P35<br>~~ee~~<br>~~a~~|SPI1_CLK/P3<br>(master/slave)<br>~~ITLL~~<br>~~ee~~<br>~~a~~|SCL<br>SDA/<br>P35<br>~~ITLL~~<br>~~ee ~~<br>~~a~~|IN4/P35<br>IN10/29<br>~~ITLL~~<br> ~~ss~~<br>~~a~~|~~ITLLILL~~<br>~~ss~~<br>~~a~~|~~ILL~~<br>~~a~~|✓<br>(P3/P29<br>/P35)<br>~~ILL~~<br>~~a~~|I2S_DO<br>PCM_Out<br>PWM3 (P29)<br>~~ILL~~<br>~~a~~|
|3<br>~~a~~<br>~~Oe~~|XRES<br>~~a~~|RESET<br>_N<br>~~a~~|RESET_N<br>~~a~~|External Reset (Active Low)<br>~~a~~<br>~~Pe~~||||||||
|4<br>~~Oe~~<br>~~{of~~|I2C_SDA<br>~~{of~~|C7<br>~~{of ff~~|PCM_IN/<br>I2S_DI/P12<br>~~ff~~|~~Pe~~<br>~~ff~~|~~Pe~~<br>|SDA<br>~~Pe~~<br>|IN23/P12<br>~~Pe~~<br>|~~Pe~~<br>|~~Pe~~<br>|✓<br>(P12)<br>~~Pe~~<br>|PCM_IN<br>I2S_DI<br>~~Pe~~<br>|
|5<br>~~Oe~~<br>~~{of~~|P2/P37/P28<br>~~{of~~|B7<br>~~{of ff~~|PCM_CLK/<br>I2S_CLK/P2/<br>P28/P37<br>~~ff~~|PUART_RX/P2<br>~~Pe~~<br>~~ffEE~~|SPI1_CS(slave)/P2<br>SPI1_MOSI(master)/P2<br>SPI1_MISO(slave)/P37<br>~~Pe~~<br>~~EE~~|SCL/<br>P37<br>~~Pe~~<br>~~EE~~|IN11/P28<br>IN2/P37<br>~~Pe~~<br>~~EE~~|~~Pe~~<br>~~EE~~|ACLK1<br>/P37<br>~~Pe~~<br>~~EE~~|✓<br>~~Pe~~<br>~~EE~~|PWM2 (P28)<br>I2S_CLK<br>PCM_CLK<br>~~Pe~~<br>~~EE~~|
|6<br>~~{of~~|SPI2_CS_N<br>~~{of~~|D7<br>~~{of ff~~|N/A<br>~~ff~~|No Connect (Used for on-module memory SPI interface for CYBT-343026-01)<br>~~ffEE~~||||||||
|7<br>~~{of~~<br>~~————————————————~~|GND<br>~~{of~~<br>~~————————————————~~|GND<br>~~{of ff~~<br>~~————————————————~~|GND<br>~~ff~~<br>~~————————————————~~|Ground<br>~~ffEE~~<br>~~————————————————~~||||||||
|8<br>~~————————————————~~|SPI2_MISO<br>~~————————————————~~|D8<br>~~————————————————~~|N/A<br>~~————————————————~~|No Connect (Used for on-module memory SPI interface for CYBT-343026-01)<br>~~————————————————~~||||||||
|9<br>~~—————————~~|SPI2_MOSI<br>~~—————————~~|E8<br>~~—————————~~|N/A<br>~~—————————~~|No Connect (Used for on-module memory SPI interface for CYBT-343026-01)<br>~~—————————~~||||||||
|10<br>~~—————————~~|SPI2_CLK<br>~~—————————~~|E7<br>~~—————————~~|N/A<br>~~—————————~~|No Connect (Used for on-module memory SPI interface for CYBT-343026-01)<br>~~—————————~~||||||||
|11<br>~~TE~~|GPIO_0<br>~~TE~~|F8<br>~~TE~~|BT_GPIO_0/<br>P36/P38<br>~~TE~~||SPI1_CLK/P36<br>SPI1_MOSI/P38<br>(master/slave)<br>~~TLL.~~|~~TLL.~~|IN3/P36<br>IN1/P38<br>~~TLL.~~|~~TLL.~~|ACLK0<br>/P36<br>~~TLL.~~|✓<br>(DevWa<br>ke)<br>~~TLL.~~|~~TLL.~~|
|12<br>~~ee~~|GPIO_1<br>~~ee~~|F7<br>~~ee~~|BT_GPIO_1/<br>P25/P32<br>~~ee~~|PUART_RX/P25<br>PUART_TX/P32<br>~~ee~~|SPI1_MISO/P25<br>(master/slave)<br>SPI1_CS/P32<br>(slave)<br>~~eee~~|~~eee~~|IN7/P32<br>~~eee~~|~~eee~~|ACLK0<br>/P32<br>~~eee~~|✓<br>(HostWa<br>ke)<br>~~eee~~|~~eee~~|
|13<br>~~ee~~<br>~~Pf~~|GND<br>~~ee~~<br>~~Pfof~~|GND<br>~~ee~~<br>~~offo~~|GND<br>~~ee~~<br>~~fo~~|Ground<br>~~ee eee~~<br>~~fe~~||||||||
|14<br>~~Pf~~<br>~~fot}~~|GPIO_4<br>~~Pfof~~<br>~~fot}~~|D6<br>~~offo~~<br>~~fot}~~|BT_GPIO_4/P6/<br>P31/LPO_IN<br>~~fo~~<br>~~fot}~~<br>~~|~~|PUART_RTS/P6<br>PUART_TX/P31<br>~~fe~~<br>~~fy~~|SPI1_CS/P6<br>(slave)<br>~~fe~~<br>~~fy~~<br>~~te~~|~~fe~~<br>~~te~~|IN8/P31<br>~~fe~~<br>~~te~~|~~fe~~|~~fe~~|✓<br>~~fe~~|Ext LPO In<br>~~fe~~|
|15<br>~~Pf~~<br>~~fot}~~|P4/P24<br>~~Pf of~~<br>~~fot}~~|G8<br>~~of fo~~<br>~~fot}~~|BT_CLK_REQ/<br>P4/P24<br>~~fo ~~<br>~~fot}~~<br>~~|~~|PUART_RX/P4<br>PUART_TX/P24<br> ~~fe~~<br>~~fy~~|SPI1_MOSI/P4<br>(master/slave)<br>SPI1_CLK/P24<br>(master/slave)<br>~~fe~~<br>~~fy~~<br>~~te~~|~~fe~~<br>~~te~~|~~fe~~<br>~~te~~|~~fe~~|~~fe~~|✓<br>(CLK_R<br>EQ)<br>~~fe~~|~~fe~~|
|16<br>~~fot}~~<br>~~—_—_~~|UART_TXD<br>~~fot}~~<br>~~—_—_~~|F4<br>~~fot}~~<br>~~—_—_~~|BT_UART_TXD<br>~~fot}~~<br>~~|~~<br>~~—_—_~~|HCI UART Transmit Data<br>~~fy~~<br>~~te~~<br>~~—_—_~~||||||||
|17<br>~~fot}~~<br>~~—_—_~~|UART_CTS<br>~~fot}~~<br>~~—_—_~~|G4<br>~~fot}~~<br>~~—_—_~~|BT_UART_CTS<br>~~fot}~~<br>~~|~~<br>~~—_—_~~|HCI UART Clear To Send Input<br>~~fy~~<br>~~te~~<br>~~—_—_~~||||||||
|18<br>~~—_—_~~<br>~~a~~|UART_RTS<br>~~—_—_~~<br>|F3<br>~~—_—_~~|BT_UART_RTS<br>~~—_—_~~|HCI UART Request To Send Output<br>~~—_—_~~<br>~~TTTTTT~~||||||||
|19<br>~~—_—_~~<br>~~oy~~<br>~~a~~|GPIO_7<br>~~—_—_~~<br>~~oy~~<br>|C6<br>~~—_—_~~<br>~~oy~~|BT_GPIO_7/<br>P30<br>~~—_—_~~<br>~~oy~~|PUART_RTS/<br>P30<br>~~—_—_~~<br>~~oy~~|~~—_—_~~<br>~~oy~~<br>~~TT~~|~~—_—_~~<br>~~oy~~<br>~~TT~~|IN9/P30<br>~~—_—_~~<br>~~oy~~<br>~~TTTT~~|✓<br>(GCI_SE<br>CI_OUT)<br>~~—_—_~~<br>~~oy~~<br>~~TT~~|~~—_—_~~<br>~~oy~~<br>~~TTTT~~|✓<br>~~—_—_~~<br>~~oy~~<br>~~TT~~|~~—_—_~~<br>~~oy~~<br>~~TT~~|
|20<br>~~oy~~<br>~~a~~|UART_RXD<br>~~oy~~<br>~~a~~|F5<br>~~oy~~<br>~~i~~|BT_UART_RXD<br>~~oy~~<br>~~es~~|HCI UART Receive Data<br>~~oy~~<br>~~TTTTTT~~||||||||
|21<br>~~oy~~<br>~~a~~|VDDIN<br>~~oy~~<br>~~a~~|G1<br>~~oy~~<br>~~i~~|VDDIN<br>~~oy~~<br>~~es~~|VDDIN (2.3V ~ 3.6V)<br>~~oy~~<br>~~TTTTTT~~||||||||
|22<br>~~a ~~<br>~~ee~~|GPIO_3<br> ~~a~~<br>~~ee~~|C5<br>~~i ~~<br>~~ee~~|BT_GPIO_3/<br>P27/P33<br> ~~es~~<br>~~ee~~|PUART_RX/P33<br>~~ee~~|SPI1_MOSI/P27<br>(master/slave)<br>SPI1_MOSI/P33<br>(slave)<br>~~TT~~|~~TT~~|IN6/P33<br>~~TT TT~~|~~TT~~|ACLK1<br>/P33<br>~~TT TT~~|✓<br>~~TT~~|PWM1 (P27)<br>~~TT~~|
|23<br>~~LO~~|GPIO_6<br>~~LO~~|B6<br>~~LO~~|BT_GPIO_6/<br>P11/P26<br>~~LO~~|~~LO~~|SPI1_CS/P26<br>(slave)<br>~~LO~~|~~LO~~|IN24/P11<br>~~LO~~|✓<br>(GCI_SE<br>CI_IN)<br>~~LO~~|~~LO~~|✓<br>~~LO~~|PWM0 (P26)<br>~~LO~~|
|24<br>~~LO~~|GND<br>~~LO~~|GND<br>~~LO~~|GND<br>~~LO~~|Ground<br>~~LO~~||||||||



Page 9 of 52 

Document Number: 002-19525 Rev. *B 

**CYBT-343026-01** 

## **Connections and Optional External Components** 

## **Power Connections (VDDIN)** 

The CYBT-343026-01 contains one power supply connection, VDDIN, that accepts a supply input range of 2.3 V to 3.6 V for CYBT-343026-01. Table 11 provides this specification. The maximum power supply ripple for this power connection is 100 mV, as shown in Table 11. 

It is not required to place any power supply decoupling or noise reduction circuitry on the host PCB. If desired, an external ferrite bead between the supply and the module connection can be included, but is not necessary. If used, the ferrite bead should be positioned as close as possible to the module pin connection and the recommended ferrite bead value is 330 , 100 MHz. 

## _Considerations and Optional Components for Brown Out (BO) Conditions_ 

Power supply design must be completed to ensure that the CYBT-343026-01 module does not encounter a Brown Out condition, which can lead to unexpected functionality, or module lock-up. A Brown Out condition may be met if power supply provided to the module during power up or reset is in the following range: 

**==> picture [79 x 11] intentionally omitted <==**

## Refer to Table 12 for the VIL and VIH specifications. 

System design should ensure that the condition above is not encountered when power is removed from the system. In the event that this cannot be guaranteed (that is, battery installation, high-value power capacitors with slow discharge), it is recommended that an external voltage detection device be used to prevent the Brown Out voltage range from occurring during power removal. Refer to Figure 8 for the recommended circuit design when using an external voltage detection IC. 

**Figure 8.  Reference Circuit Block Diagram for External Voltage Detection IC** 

In the event that the module does encounter a Brown Out condition, and is operating erratically or not responsive, power cycling the module will correct this issue and once reset, the module should operate correctly. Brown Out conditions can potentially cause issues that cannot be corrected, but in general, a power-on-reset operation will correct a Brown Out condition. 

## **External Reset (XRES)** 

The CYBT-343026-01 has an integrated power-on reset circuit, which completely resets all circuits to a known power-on state. This action can also be evoked by an external reset signal, forcing it into a power-on reset state. The XRES signal is an active-low signal, which is an input to the CYBT-343026-01 module (solder pad 3). The CYBT-343026-01 module does not require an external pull-up resistor on the XRES input 

During power-on operation, the XRES connection to the CYBT-343026-01 is required to be held low 50 ms after the VDD power supply input to the module is stable. This can be accomplished in the following ways: 

- The host device should connect a GPIO to the XRES of the Cypress CYBT-343026-01 module and pull XRES low until VDD is stable. XRES is recommended to be released 50 ms after VDDIN is stable. 

- If the XRES connection of the CYBT-343026-01 module is not used in the application, a 10-µF capacitor may be connected to the XRES solder pad of the CYBT-343026-01 to delay the XRES release. The capacitor value for this recommended implementation is approximate, and the exact value may differ depending on the VDDIN power supply ramp time of the system. The capacitor value should result in an XRES release timing of 50 ms after VDDIN stability. 

- The XRES release timing may be controlled by a external voltage detection IC. XRES should be released 50 ms after VDD is stable. 

- Refer to Figure 11 on page 17 for XRES operating and timing requirements during power-on events. 

Page 10 of 52 

Document Number: 002-19525 Rev. *B 

**CYBT-343026-01** 

## **Multiple-Bonded GPIO Connections** 

The CYBT-343026-01 contains GPIOs, which are multiple-bonded at the silicon level. If any of these dual-bonded GPIOs are used, only the functionality and features for one of these port pins may be used. The desired port pin should be configured in the WICED Studio SDK. For details on the features and functions that each of these multiple-bonded GPIOs provide, refer to Table 4. 

The following list details the multiple-bonded GPIOs available on the CYBT-343026-01 module: 

- PAD 1 P0/34: I2S_WS_PCM_SYNC/P0/P34 (triple bonded; only one of four is available) 

- PAD 2 I2C_SCL: I2S_PCM_OUT/P3/P29/P35 (quadruple bonded; only one of four is available) 

- PAD 4 I2C_SDA: I2S_PCM_IN/P12 (dual bonded; only one of two is available) 

- PAD 5 P2/P37/P28: I2S_PCM_CLK/P2/P28/P37 (quadruple bonded; only one of four is available) 

- PAD 11 GPIO_0: GPIO_0/P36/P38 (triple bonded; only one of three is available) 

- PAD 12 GPIO_1: GPIO_1/P25/P32 (triple bonded; only one of three is available) 

- PAD 14 GPIO_4: GPIO_4/LPO_IN/P6/P31 (quadruple bonded; only of four is available) 

- PAD 15 P4/P24: BT_CLK_REQ/P4/P24 (triple bonded; only one of three is available) 

- PAD 19 GPIO_7: GPIO_7/P30 (Dual bonded; only one of two is available) 

- PAD 22 GPIO_3: GPIO_3/P27/P33 (triple bonded; only one of three is available) 

- PAD 23 GPIO_6: GPIO_6/P11/P26 (triple bonded; only one of three is available) 

Page 11 of 52 

Document Number: 002-19525 Rev. *B 

**CYBT-343026-01** 

Figure 9 illustrates the CYBT-343026-01 schematic. 

**Figure 9.  CYBT-343026-01 Schematic Diagram** 

Page 12 of 52 

Document Number: 002-19525 Rev. *B 

**CYBT-343026-01** 

## **Critical Components List** 

Table 5 details the critical components used in the CYBT-343026-01 module. 

## **Table 5.  Critical Component List** 

|**Component**|**Reference Designator**|**Description**|
|---|---|---|
|Silicon|U1|49-pin FBGA BT/BLE Silicon Device - CYW20706|
|Silicon|U2|8-pin TDF8N, 512K Serial Flash|
|Crystal|Y1|24.000 MHz, 12PF|



## **Antenna Design** 

Table 6 details the trace antenna used in the CYBT-343026-01 module. 

## **Table 6.  Trace Antenna Specifications** 

|**Item**||**Description**|
|---|---|---|
|Frequency Range|2400–2500 MHz||
|Peak Gain|–0.5 dBi typical||
|Return Loss|10 dB minimum||



Page 13 of 52 

Document Number: 002-19525 Rev. *B 

**CYBT-343026-01** 

## **Functional Description** 

## **Bluetooth Baseband Core** 

The Bluetooth Baseband Core (BBC) implements all of the time-critical functions required for high-performance Bluetooth operation. The BBC manages the buffering, segmentation, and routing of data for all connections. It also buffers data that passes through it, handles data flow control, schedules SCO/ACL and TX/RX transactions, monitors Bluetooth slot usage, optimally segments and packages data into baseband packets, manages connection status indicators, and composes and decodes HCI packets. In addition to these functions, it independently handles HCI event types, and HCI command types. The following transmit and receive functions are also implemented in the BBC hardware to increase reliability and security of the TX/RX data before sending over the air: 

- Symbol timing recovery, data deframing, forward error correction (FEC), header error control (HEC), cyclic redundancy check (CRC), data decryption, and data dewhitening in the receiver. 

- Data framing, FEC generation, HEC generation, CRC generation, key generation, data encryption, and data whitening in the transmitter. 

## **Table 7. Bluetooth Features** 

|**Bluetooth 1.0**|**Bluetooth 1.2**|**Bluetooth 2.0**|
|---|---|---|
|Basic Rate|Interlaced Scans|EDR 2 Mbps and 3 Mbps|
|SCO|Adaptive Frequency Hopping|–|
|Paging and Inquiry|eSCO|–|
|Page and Inquiry Scan|–|–|
|Sniff|–|–|
|**Bluetooth 2.1**|**Bluetooth 3.0**|**Bluetooth 4.0**|
|Secure Simple Pairing|Unicast Connectionless Data|Bluetooth Low Energy|
|Enhanced Inquiry Response|Enhanced Power Control|–|
|Sniff Subrating|eSCO|–|
|**Bluetooth 4.1**|**Bluetooth 4.2**||
|Low Duty Cycle Advertising|Data Packet Length Extension||
|Dual Mode|LE Secure Connection||
|LE Link Layer Topology|Link Layer Privacy||



## _Link Control Layer_ 

The link control layer is part of the Bluetooth link control functions that are implemented in dedicated logic in the link control unit (LCU). This layer consists of the command controller that takes commands from the software, and other controllers that are activated or configured by the command controller, to perform the link control tasks. Each task is performed in a different state in the Bluetooth Link Controller. 

## ■ States: 

- ❐ Standby 

- ❐ Connection 

- ❐ Page 

- ❐ Page Scan 

- ❐ Inquiry 

- ❐ Inquiry Scan 

- ❐ Sniff 

- ❐ Advertising 

- ❐ Scanning 

Page 14 of 52 

Document Number: 002-19525 Rev. *B 

**CYBT-343026-01** 

## _Test Mode Support_ 

The CYBT-343026-01 fully supports Bluetooth Test mode as described in Part I:1 of the Specification of the Bluetooth System Version 3.0. This includes the transmitter tests, normal and delayed loopback te ~~st~~ s, and reduced hopping sequence. 

In addition to the standard Bluetooth Test Mode, the CYBT-343026-01 also supports enhanced testing features to simplify RF debugging and qualification and type-approval testing. These features include: 

- Fixed frequency carrier wave (unmodulated) transmission 

- ❐ Simplifies some type-approval measurements (Japan) 

- ❐ Aids in transmitter performance analysis 

- Fixed frequency constant receiver mode 

- ❐ Receiver output directed to I/O pin 

- ❐ Allows for direct BER measurements using standard RF test equipment 

- ❐ Facilitates spurious emissions testing for receive mode 

- Fixed frequency constant transmission 

- ❐ 8-bit fixed pattern or PRBS-9 

- ❐ Enables modulated signal measurements with standard RF test equipment. 

## _Frequency Hopping Generator_ 

The frequency hopping sequence generator selects the correct hopping channel number based on the link controller state, Bluetooth clock, and device address. 

Page 15 of 52 

Document Number: 002-19525 Rev. *B 

**CYBT-343026-01** 

## **Microcontroller Unit** 

The microprocessor unit in CYBT-343026-01 runs software from the link control (LC) layer up to the host controller interface (HCI). The microprocessor is based on the Cortex-M3 32-bit RISC processor with embedded ICE-RT debug and JTAG interface units. The microprocessor also includes 848 KB of ROM memory for program storage and boot ROM, 352 KB of RAM for data scratch-pad, and patch RAM code. 

The internal boot ROM provides flexibility during power-on reset to enable the same device to be used in various configurations. At power-up, the lower layer protocol stack is executed from the internal ROM. 

External patches can be applied to the ROM-based firmware to provide flexibility for bug fixes and features additions. These patches can be downloaded using external NVRAM. The device can also support the integration of user applications and profiles using an external serial flash memory. 

## _NVRAM Configuration Data and Storage_ 

NVRAM contains configuration information about the customer application, including the following: 

■ Fractional-N information 

- BD_ADDR 

- UART baud rate 

- SDP service record 

■ File system information used for code, code patches, or data. The CYBT-343026-01 uses SPI Serial Flash for NVRAM storage. 

## _One-Time Programmable Memory_ 

The microprocessor unit in CYBT-343026-01 includes 2 KB of one-time programmable (OTP) memory allow manufacturing customization and to avoid the need for an on-board NVRAM. If customization is not required, then the OTP does not need to be programmed. Whether the OTP is programmed or not, to save power it is disabled when the boot process is complete. The OTP is designed to store a minimal amount of information. Aside from OTP data, most user configuration information will be downloaded to RAM after the CYBT-343026-01 boots and is ready for host transport communication. 

The OTP contents are limited to: 

■ Parameters required prior to downloading the user configuration to RAM. 

■ Parameters unique to each part and each customer (for example, the Bluetooth device address and/or the software license key). 

■ VDDIN for the module must be kept to 3.0 V to 3.6 V power supply range if OTP is used in the application. 

Page 16 of 52 

Document Number: 002-19525 Rev. *B 

**CYBT-343026-01** 

## **External Reset (XRES)** 

The CYBT-343026-01 has an integrated power-on reset circuit that completely resets all circuits to a known power-on state. An external active low reset signal, XRES, can be used to put the CYBT-343026-01 in the reset state. The XRES pin has an internal pull-up resistor and, in most applications, it does not require anything to be connected to it. 

## **Figure 10.  External Reset Internal Timing** 

## _External Reset (XRES) Recommended External Components and Proper Operation_ 

During a power-on event, the XRES line of the CYBT-343026-01 is required to be held low 50 ms after the VDD power supply input to the module is stable. Refer to Figure 11 for the Power-On XRES timing operation. This power-on operation can be accomplished in the following ways: 

- A host device should connect a GPIO to the XRES of the Cypress CYBT-343026-01 module and pull XRES low until VDD is stable. XRES can be released after VDD is stable. 

- If the XRES connection of the CYBT-343026-01 module is not used in the application, a 10-µF capacitor may be connected to the XRES solder pad of the CYBT-343026-01. 

- The XRES release timing can also be controlled via an external voltage detection circuit. 

**Figure 11.  Power-On External Reset (XRES) Operation** 

Page 17 of 52 

Document Number: 002-19525 Rev. *B 

**CYBT-343026-01** 

## **Integrated Radio Transceiver** 

The CYBT-343026-01 has an integrated radio transceiver that has been optimized for use in 2.4-GHz Bluetooth wireless systems. It has been designed to provide low-power, low-cost, robust communications for applications operating in the globally available 2.4-GHz unlicensed ISM band. The CYBT-343026-01 is fully compliant with the Bluetooth Radio Specification and enhanced data rate (EDR) specification and meets or exceeds the requirements to provide the highest communication link quality of service. 

## **Transmitter Path** 

The CYBT-343026-01 a fully integrated zero-IF transmitter. The baseband transmit data is GFSK-modulated in the modem block and upconverted to the 2.4-GHz ISM band in the transmitter path. The transmitter path consists of signal filtering, I/Q upconversion, output power amplifier, and RF filtering. The transmitter path also incorporates /4-DQPSK for 2 Mbps and 8-DPSK for 3 Mbps to support EDR. The transmitter section is compatible with the BLE specification. The transmitter PA bias can also be adjusted to provide Bluetooth class 1 or class 2 operation. 

## _Digital Modulator_ 

The digital modulator performs the data modulation and filtering required for the GFSK, 4-DQPSK, and 8-DPSK signal. The fully digital modulator minimizes any frequency drift or anomalies in the modulation characteristics of the transmitted signal and is much more stable than direct VCO modulation schemes. 

## _Digital Demodulator and Bit Synchronizer_ 

The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit synchronization algorithm. 

## _Power Amplifier_ 

The fully integrated PA supports Class 1 or Class 2 output using a highly linearized, temperature-compensated design. This provides greater flexibility in front-end matching and filtering. Due to the linear nature of the PA combined with some integrated filtering, external filtering is required to meet the Bluetooth and regulatory harmonic and spurious requirements. For integrated mobile handset applications in which Bluetooth is integrated next to the cellular radio, external filtering can be applied to achieve near thermal noise levels for spurious and radiated noise emissions. The transmitter features a sophisticated on-chip transmit signal strength indicator (TSSI) block to keep the absolute output power variation within a tight range across process, voltage, and temperature. 

## **Receiver Path** 

The receiver path uses a low-IF scheme to downconvert the received signal for demodulation in the digital demodulator and bit synchronizer. The receiver path provides a high degree of linearity, an extended dynamic range, and high-order on-chip channel filtering to ensure reliable operation in the noisy 2.4 GHz ISM band. The front-end topology, with built-in out-of-band attenuation, enables the CYBT-343026-01 to be used in most applications with minimal off-chip filtering. For integrated handset operation, in which the Bluetooth function is integrated close to the cellular transmitter, external filtering is required to eliminate the desensitization of the receiver by the cellular transmit signal. 

## _Digital Demodulator and Bit Synchronizer_ 

The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit synchronization algorithm. 

## _Receiver Signal Strength Indicator_ 

The radio portion of the CYBT-343026-01 provides a receiver signal strength indicator (RSSI) to the baseband. This enables the controller to take part in a Bluetooth power-controlled link by providing a metric of its own receiver signal strength to determine whether the transmitter should increase or decrease its output power. 

## **Local Oscillator Generation** 

The local oscillator (LO) provides fast frequency hopping (1600 hops/second) across the 79 maximum available channels. The LO generation sub-block employs an architecture for high immunity to LO pulling during PA operation. The CYBT-343026-01 uses an internal loop filter. 

## **Calibration** 

The CYBT-343026-01 radio transceiver features an automated calibration scheme that is fully self-contained in the radio. No user interaction is required during normal operation or during manufacturing to provide optimal performance. Calibration tunes the performance of all the major blocks within the radio to within 2% of optimal conditions, including gain and phase characteristics of filters, matching between key components, and key gain blocks. This takes into account process variation and temperature variation. Calibration occurs transparently during normal operation during the settling time of the hops, and calibrates for temperature variations as the device cools and heats during normal operation in its environment. 

Page 18 of 52 

Document Number: 002-19525 Rev. *B 

**CYBT-343026-01** 

## **Internal LDO** 

The microprocessor in CYBT-343026-01 uses two LDOs – one for 1.2 V and the other for 2.5 V. The 1.2-V LDO provides power to the baseband and radio and the 2.5-V LDO powers the PA. 

## **Collaborative Coexistence** 

The CYBT-343026-01 provides extensions and collaborative coexistence to the standard Bluetooth AFH for direct communication with WLAN devices. Collaborative coexistence enables WLAN and Bluetooth to operate simultaneously in a single device. The device supports industry-standard coexistence signaling, including 802.15.2, and supports Cypress and third-party WLAN solutions. 

## **Global Coexistence Interface** 

The CYBT-343026-01 supports the proprietary Cypress Global Coexistence Interface (GCI) which is a 2-wire interface. The following key features are associated with the interface: 

- Enhanced coexistence data can be exchanged over GCI_SECI_IN and GCI_SECI_OUT a two-wire interface, one serial input (GCI_SECI_IN), and one serial output (GCI_SECI_OUT). The pad configuration registers must be programmed to choose the digital I/O pins that serve the GCI_SECI_IN and GCI_SECI_OUT function. 

- It supports generic UART communication between WLAN and Bluetooth devices. 

- To conserve power, it is disabled when inactive. 

- It supports automatic resynchronization upon waking from sleep mode. 

- It supports a baud rate of up to 4 Mbps. 

## **SECI I/O** 

The microprocessor in CYBT-343026-01 has dedicated GCI_SECI_IN (PAD 23/GPIO_6) and GCI_SECI_OUT (PAD19/GPIO_7) pins. Refer to Table 4, which detail the module solder pad number used for SECI I/O. 

Page 19 of 52 

Document Number: 002-19525 Rev. *B 

**CYBT-343026-01** 

## **Peripheral and Communication Interfaces** 

## **I[2] C Communication Interface** 

The CYBT-343026-01 provides a 2-pin master I[2] C interface, which can be used to retrieve configuration information from an external EEPROM or to communicate with peripherals such as track-ball or touch-pad modules, and motion tracking ICs used in mouse devices. This interface is compatible with I[2] C slave devices. I[2] C does not support multimaster capability or flexible wait-state insertion by either master or slave devices. 

The following transfer clock rates are supported by the I[2] C: 

- 100 kHz 

- 400 kHz 

- 800 kHz (not a standard I[2] C-compatible speed.) 

- 1 MHz (Compatibility with high-speed I[2] C-compatible devices is not guaranteed.) 

The following transfer types are supported by the I[2] C: 

- Read (Up to 127 bytes can be read) 

- Write (Up to 127 bytes can be written) 

- Read-then-Write (Up to 127 bytes can be read and up to 127 bytes can be written) 

- Write-then-Read (Up to127 bytes can be written and up to 127 bytes can be read) 

Hardware controls the transfers, requiring minimal firmware setup and supervision. 

The clock pad (I2C_SCL) and data pad 2 (I2C_SDA) are both open-drain I/O pins. Pull-up resistors, external to the CYBT-343026-01, are required on both the SCL and SDA pad for proper operation. 

## **HCI UART Interface** 

The UART physical interface is a standard, 4-wire interface (RX, TX, RTS, and CTS) with adjustable baud rates from 38400 bps to 4 Mbps. During initial boot, UART speeds may be limited to 750 kbps. The baud rate may be selected via a vendor-specific UART HCI command. The CYBT-343026-01 has a 1040-byte receive FIFO and a 1040-byte transmit FIFO to support enhanced data rates. The interface supports the Bluetooth UART HCI (H4) specification. The default baud rate for H4 is 115.2 kbaud. 

The UART clock default setting is 24 MHz, and can be configured to run as high as 48 MHz to support up to 4 Mbps. The baud rate of the CYBT-343026-01UART is controlled by two values. The first is a UART clock divisor (set in the DLBR register) that divides the UART clock by an integer multiple of 16. The second is a baud rate adjustment (set in the DHBR register) that is used to specify a number of UART clock cycles to stuff in the first or second half of each bit time. Up to eight UART cycles can be inserted into the first half of each bit time, and up to eight UART clock cycles can be inserted into the end of each bit time. 

Table 8 contains example values to generate common baud rates with a 24-MHz UART clock. 

**Table 8.  Common Baud Rate Examples, 24 MHz Clock** 

|**Baud Rate (bps)**<br>~~a~~|**Baud Rate Adjustment**<br>~~**e**e~~<br>~~e~~|**Baud Rate Adjustment**<br>~~**e**e~~<br>~~e~~|**Mode**<br>~~e~~<br>~~Ge~~|**Error (%)**<br>~~e~~|
|---|---|---|---|---|
||**High Nibble**<br>~~**e**e~~|**Low Nibble**<br>~~e~~<br>~~e~~<br>~~Ge~~|||
|4M<br>~~Ce~~|0xFF<br>~~Ce~~|0xF4<br>~~Ce~~<br>~~Ge~~<br>~~GO~~|High rate<br>~~Ce~~<br>~~Ge~~<br>~~GO~~|0.00<br>~~Ce~~|
|3M<br>~~Ge~~|0xFF<br>~~Ge~~|0xF8<br>~~Ge~~<br>~~Ge~~<br>~~GO~~<br>~~Ge~~|High rate<br>~~Ge~~<br>~~Ge~~<br>~~GO~~<br>~~Ge~~|0.00<br>~~Ge~~|
|2M<br>~~Ce~~|0XFF<br>~~Ce~~|0XF4<br>~~GO~~<br>~~Ce~~<br>~~Ge~~<br>~~GO~~|High rate<br>~~GO~~<br>~~Ce~~<br>~~Ge~~<br>~~GO~~|0.00<br>~~Ce~~|
|1M<br>~~Ge~~|0X44<br>~~Ge~~|0XFF<br>~~Ge~~<br>~~Ge~~<br>~~GO~~<br>~~Ge~~|Normal<br>~~Ge~~<br>~~Ge~~<br>~~GO~~<br>~~Ge~~|0.00<br>~~Ge~~|
|921600<br>~~Ce~~|0x05<br>~~Ce~~|0x05<br>~~GO~~<br>~~Ce~~<br>~~Ge~~<br>~~GO~~|Normal<br>~~GO~~<br>~~Ce~~<br>~~Ge~~<br>~~GO~~|0.16<br>~~Ce~~|
|460800<br>~~Ge~~|0x02<br>~~Ge~~|0x02<br>~~Ge~~<br>~~Ge~~<br>~~GO~~<br>~~Ge~~|Normal<br>~~Ge~~<br>~~Ge~~<br>~~GO~~<br>~~Ge~~|0.16<br>~~Ge~~|
|230400<br>~~Ce~~|0x04<br>~~Ce~~|0x04<br>~~GO~~<br>~~Ce~~<br>~~Ge~~<br>~~GO~~|Normal<br>~~GO~~<br>~~Ce~~<br>~~Ge~~<br>~~GO~~|0.16<br>~~Ce~~|
|115200<br>~~eC~~|0x00<br>~~eC~~|0x00<br>~~Ge~~<br>~~eC~~<br>~~GO~~<br>~~Ge~~|Normal<br>~~Ge~~<br>~~eC~~<br>~~GO~~<br>~~Ge~~|0.16<br>~~eC~~|
|57600<br>~~Ce~~|0x00<br>~~Ce~~|0x00<br>~~GO~~<br>~~Ce~~<br>~~Ge~~<br>~~GO~~|Normal<br>~~GO~~<br>~~Ce~~<br>~~Ge~~<br>~~GO~~|0.16<br>~~Ce~~|
|38400<br>~~Ce~~|0x01<br>~~Ce~~|0x00<br>~~Ge~~<br>~~Ce~~<br>~~GO~~|Normal<br>~~Ge~~<br>~~Ce~~<br>~~GO~~|0.00<br>~~Ce~~|



Page 20 of 52 

Document Number: 002-19525 Rev. *B 

**CYBT-343026-01** 

Normally, the UART baud rate is set by a configuration record downloaded after reset. Support for changing the baud rate during normal HCI UART operation is included through a vendor-specific command that allows the host to adjust the contents of the baud rate registers. 

The CYBT-343026-01 UART operates correctly with the host UART as long as the combined baud rate error of the two devices is within ±2%. 

## **Peripheral UART Interface** 

The CYBT-343026-01 has a second UART that may be used to interface to other peripherals. This peripheral UART is accessed through the optional I/O ports, which can be configured individually and separately for each signal as shown in Table 9 

**Table 9.  CYBT-343026-01 Peripheral UART** 

|**Signal Name**|**PUART_TX**|**PUART_RX**|**PUART_CTS_N**|**PUART_RTS_N**|
|---|---|---|---|---|
|PUART Port Configuration #1|P0|P2|P3|P6|
|PUART Port Configuration #2|P31|P33|P35|P30|



## **Serial Peripheral Interface** 

The CYBT-343026-01 has two independent SPI interfaces. One is a master-only interface (SPI2) and the other (SPI1) can be either a master or a slave. Each interface has a 64-byte transmit buffer and a 64-byte receive buffer. To support more flexibility for user applications, the CYBT-343026-01 has optional I/O ports that can be configured individually and separately for each functional pin. The CYBT-343026-01 acts as an SPI master device that supports 3.3 V SPI slaves. In master mode, refer to Table 4 to identify the solder pads available for SPI1_MISO, SPI1_MOSI, and SPI1_CLK connections. NOTE: In master mode, any available GPIO can be assigned as SPI1_CS. 

The CYBT-343026-01 can also act as an SPI slave device that supports a 3.3 V SPI master. For SPI1 slave mode, refer to Table 4 to identify the solder pads available for SPI1 slave mode connections. 

SPI voltage depends on VDDIN; therefore, VDDIN should be set to 3.3 V for SPI communication. 

## **PCM Interface** 

The CYBT-343026-01 includes a PCM interface that shares pins with the I[2] S interface. The PCM Interface on the CYBT-343026-01 can connect to linear PCM codec devices in master or slave mode. In master mode, the CYBT-343026-01 generates the PCM_CLK and PCM_SYNC signals. In slave mode, these signals are provided by another master on the PCM interface and are inputs to the CYBT-343026-01. 

## _Slot Mapping_ 

The CYBT-343026-01 supports up to three simultaneous full-duplex SCO or eSCO channels through the PCM interface. These three channels are time-multiplexed onto the single PCM interface by using a time-slotting scheme where the 8 kHz or 16 kHz audio sample interval is divided into as many as 16 slots. The number of slots is dependent on the selected interface rate (128 kHz, 512 kHz, or 1024 kHz). The corresponding number of slots for these interface rate is 1, 2, 4, 8, and 16, respectively. Transmit and receive PCM data from an SCO channel is always mapped to the same slot. The PCM data output driver tristates its output on unused slots to allow other devices to share the same PCM interface signals. The data output driver tristates its output after the falling edge of the PCM clock during the last bit of the slot. 

## _Frame Synchronization_ 

The CYBT-343026-01 supports both short- and long-frame synchronization in both master and slave modes. In short-frame synchronization mode, the frame synchronization signal is an active-high pulse at the audio frame rate that is a single-bit period in width and is synchronized to the rising edge of the bit clock. The PCM slave looks for a high on the falling edge of the bit clock and expects the first bit of the first slot to start at the next rising edge of the clock. In long-frame synchronization mode, the frame synchronization signal is again an active-high pulse at the audio frame rate; however, the duration is three bit periods and the pulse starts coincident with the first bit of the first slot. 

## _Data Formatting_ 

The CYBT-343026-01 may be configured to generate and accept several different data formats. For conventional narrowband speech mode, the CYBT-343026-01 uses 13 of the 16 bits in each PCM frame. The location and order of these 13 bits can be configured to support various data formats on the PCM interface. The remaining three bits are ignored on the input and may be filled with 0s, 1s, a sign bit, or a programmed value on the output. The default format is 13-bit 2’s complement data, left justified, and clocked MSB first. 

Page 21 of 52 

Document Number: 002-19525 Rev. *B 

**CYBT-343026-01** 

## **Clock Frequencies** 

The CYBT-343026-01 has an integrated 24-MHz crystal on the module. There is no need to add an additional crystal oscillator. 

## **GPIO Port** 

The CYBT-343026-01 has nine GPIOs besides two I[2] C pads. All GPIOs support programmable pull-ups and are capable of driving up to 8 mA at 3.3 V or 4 mA at 1.8 V, except chips P26, P27, P28, and P29, which are capable of driving up to 16 mA at 3.3 V. The following GPIOs are available on the module pads: 

- PAD 1 P0/34: I2S_WS_PCM_SYNC/P0/P34 (triple bonded; only one of four is available) 

- PAD 2 I2C_SCL: I2S_PCM_OUT/P3/P29/P35 (quadruple bonded; only one of four is available) 

- PAD 4 I2C_SDA: I2S_PCM_IN/P12 (dual bonded; only one of two is available) 

- PAD 5 P2/P37/P28: I2S_PCM_CLK/P2/P28/P37 (quadruple bonded; only one of four is available) 

- PAD 11 GPIO_0: GPIO_0/P36/P38 (triple bonded; only one of three is available) 

- PAD 12 GPIO_1: GPIO_1/P25/P32 (triple bonded; only one of three is available) 

- PAD 14 GPIO_4: GPIO_4/LPO_IN/P6/P31 (quadruple bonded; only of four is available) 

- PAD 15 P4/P24: BT_CLK_REQ/P4/P24 (triple bonded; only one of three is available) 

- PAD 19 GPIO_7: GPIO_7/P30 (Dual bonded; only one of two is available) 

- PAD 22 GPIO_3: GPIO_3/P27/P33 (triple bonded; only one of three is available) 

- PAD 23 GPIO_6: GPIO_6/P11/P26 (triple bonded; only one of three is available) 

Refer to Table 4 to determine what GPIOs can be configured as ADC Inputs. 

NOTE: Any available GPIO can be used for SPI1_CS when in master mode. 

## **Port 26–Port 29 in PAD 23/PAD 22/PAD 5/PAD 2** 

P[26:29] in PAD 23/PAD 22/PAD 5/PAD 2 consists of four pins. All pins are capable of sinking up to 16 mA for LEDs. These pins also have PWM functionality, which can be used for LED dimming. 

For a description of the capabilities of all GPIOs, see Table 4. 

## **PWM** 

The CYBT-343026-01 has four PWMs. The PWM module consists of the following: 

■ PWM0-3 

- The following GPIOs can be mapped as PWMs (the module pad is shown in [ ]): 

- ❐ PWM0: P26 on P11/P26 [Pad 23] 

- ❐ PWM1: P27 on P33/P27 [Pad 22] 

- ❐ PWM2: P28 on P2/P37/P28 [Pad 5] 

- ❐ PWM3: P29 on P3/P35/P29/I2C_SCL [Pad 2] 

- PWM1-4: Each of the four PWM channels contains the following registers: 

- ❐ 10-bit initial value register (read/write) 

- ❐ 10-bit toggle register (read/write) 

- ❐ 10-bit PWM counter value register (read) 

- PWM configuration register shared among PWM1-4 (read/write). This 12-bit register is used: 

- ❐ To configure each PWM channel 

- ❐ To select the clock of each PWM channel 

- ❐ To change the phase of each PWM channel 

Figure 12 shows the structure of one PWM. 

Page 22 of 52 

Document Number: 002-19525 Rev. *B 

**CYBT-343026-01** 

**Figure 12.  PWM Block Diagram** 

Page 23 of 52 

Document Number: 002-19525 Rev. *B 

**CYBT-343026-01** 

## **Power Management Unit** 

The Power Management Unit (PMU) provides power management features that can be invoked by software through power management registers or packet-handling in the baseband core. 

## **RF Power Management** 

The BBC generates power-down control signals for the transmit path, receive path, PLL, and power amplifier to the 2.4-GHz transceiver, which then processes the power-down functions accordingly. 

## **Host Controller Power Management** 

Power is automatically managed by the firmware based on input device activity. As a power-saving task, the firmware controls the disabling of the on-chip regulator when in deep sleep (HIDOFF) mode. 

## **BBC Power Management** 

There are several low-power operations for the BBC: 

- Physical layer packet handling turns RF on and off dynamically within packet TX and RX. 

- Bluetooth-specified low-power connection mode. While in these low-power connection modes, the CYBT-343026-01 runs on the Low Power Oscillator and wakes up after a predefined time period. 

The CYBT-343026-01 automatically adjusts its power dissipation based on user activity. The following power modes are supported: 

- Active mode 

- Idle mode 

## ■ Sleep mode 

## ■ HIDOFF (Deep Sleep) mode 

The CYBT-343026-01 transitions to the next lower state after a programmable period of user inactivity. Busy mode is immediately entered when user activity resumes. 

In HIDOFF (Deep Sleep) mode, the CYBT-343026-01 baseband and core are powered off by disabling power to LDOOUT. The VDDO domain remains powered up and will turn the remainder of the chip on when it detects user events. This mode minimizes chip power consumption and is intended for long periods of inactivity. 

Page 24 of 52 

Document Number: 002-19525 Rev. *B 

**CYBT-343026-01** 

## **Electrical Characteristics** 

Table 10 shows the maximum electrical rating for voltages referenced to VDDIN pad. 

## **Table 10.  Maximum Electrical Rating** 

|**Rating**|||**Symbol**|**Symbol**|||**Value**||**Unit**|
|---|---|---|---|---|---|---|---|---|---|
|VDDIN|||–||||3.795||V|
|Voltage on input or outputpin|||–|||VSS– 0.3 to V|– 0.3 to VDD+ 0.3||V|
|Operatingambient temperature range|||Topr||||–30 to +85||°C|
|Storage temperature range|||Tstg||||–40 to +85||°C|
|Table 11shows the power supply characteristics for the range TJ= 0 to 125 °C.|= 0 to 125 °C.|||||||||
|**Table 11.  Power Supply**||||||||||
|**Parameter**<br>**Description**||**Minimum**[6]|||**Typical**||**Maximum**[6]||**Unit**|
|VDDIN<br>Power SupplyInput(CYBT-343026-01)||2.3||||–|3.6||V|
|VDDIN_RIPPLE<br>Maximum Power SupplyRipple for VDDINinput voltage|||–|||–|100||mV|



Table 11 shows the power supply characteristics for the range TJ = 0 to 125 °C. 

## **Table 11.  Power Supply** 

Table 12 shows the specifications for the digital voltage levels. 

**Table 12.  Digital Voltage Levels** 

|**Characteristics**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|
|Input low voltage|VIL|–|–|0.8|V|
|Input high voltage|VIH|2.0|–|–|V|
|Output low voltage|VOL|–|–|0.4|V|
|Output high voltage|VOH|VDDIN– 0.4|–|–|V|
|Input capacitance(VDDMEMdomain)|CIN|–|–|0.4|pF|



Table 13 shows the current consumption measurements 

**Table 13.  Bluetooth, BLE, BR and EDR Current Consumption** 

|**Parameter**<br>~~RC~~|**Description**<br>|**Silicon or**<br>**Module**<br>**Parameter**<br>|**Output**<br>**Power**<br>**Level/Class**<br>|**Typ**<br>|**Unit**<br>|
|---|---|---|---|---|---|
|**Bluetooth Classic (BR, EDR)**<br>~~RC~~<br>~~I~~<br>~~es~~||||||
|3DM5/3DH5<br>~~RCenn~~<br>~~es~~|HCI control mode<br>~~enn~~<br>~~nD~~|Silicon<br>~~enn~~<br>~~I~~<br>~~I~~|Class 1<br>~~enn~~<br>~~I~~<br>~~I~~|37.1<br>~~enn~~|mA<br>~~enn~~|
|DM1/DH1<br>~~es~~|HCI control mode<br>~~nD~~|Silicon<br>~~I~~<br>~~I~~|Class 1<br>~~I~~<br>~~I~~|32.2|mA|
|DM3/DH3<br>~~es~~<br>~~I~~<br>~~es~~|HCI control mode<br>~~nD ~~<br>~~I~~<br>~~nn~~|Silicon<br>~~I~~<br> ~~I~~<br>~~I~~<br>~~I~~|Class 1<br>~~I~~<br>~~I~~<br>~~I~~|38.2<br>~~I~~|mA<br>~~I~~|
|DM5/DH5<br>~~es~~|HCI control mode<br>~~nn~~|Silicon<br>~~I~~|Class 1|38.5|mA|
|RX1M_BR<br>~~es~~<br>~~a ~~|Peak receive (1 Mbps) current level when receiving<br>a basic rate packet (radio only)<br>~~nn ~~<br> ~~GO~~|Silicon<br> ~~I~~<br>~~GO~~|Class 1<br>~~GO~~|26.4<br>~~GO~~|mA<br>~~GO~~|
|TX1M_BR<br>~~oe~~|Peak transmit (1 Mbps) current level when trans-<br>mitting a basic rate packet (radio only)<br>~~oe~~|Silicon<br>~~oe~~|10 dBm<br>~~oe~~|60.3<br>~~oe~~|mA<br>~~oe~~|
|RX23M_EDR<br>~~oe~~<br>~~oe~~|Peak receive (EDR) current level when receiving a<br>2 or 3 Mbps rate packet (radio only)<br>~~oe~~<br>~~oe~~|Silicon<br>~~oe~~<br>~~oe~~|Class 1<br>~~oe~~<br>~~oe~~|26.4<br>~~oe~~<br>~~oe~~|mA<br>~~oe~~<br>~~oe~~|
|TX23M_EDR<br>~~oe~~<br>~~a ~~|Peak transmit (EDR) current level when trans-<br>mitting a 2 or 3 Mbps rate packet (radio only)<br>~~oe~~<br> ~~GO~~|Silicon<br>~~oe~~<br>~~GO~~|8 dBm<br>~~oe~~<br>~~GO~~|52.5<br>~~oe~~<br>~~GO~~|mA<br>~~oe~~<br>~~GO~~|



6. Overall performance degrades beyond minimum and maximum supply voltages.The voltage range specified is determined by the minimum and maximum operating voltage of the SPI Serial Flash included on the module. 

**Note** 

Page 25 of 52 

Document Number: 002-19525 Rev. *B 

**CYBT-343026-01** 

**Table 13.  Bluetooth, BLE, BR and EDR Current Consumption** (continued) 

|**Parameter**<br>~~ee~~|**Description**<br>~~ee~~|**Silicon or**<br>**Module**<br>**Parameter**<br>~~ee~~|**Output**<br>**Power**<br>**Level/Class**<br>~~ee~~|**Typ**<br>~~ee~~|**Unit**<br>~~ee~~|
|---|---|---|---|---|---|
|**Bluetooth Classic (BR, EDR)**<br>~~eeee~~<br>~~eee~~||||||
|Deep Sleep<br>~~eee~~|Deep Sleep (HIDOFF) current<br>~~eee~~|Module<br>~~eee~~|All<br>~~eee~~|2.69<br>~~eee~~|uA<br>~~eee~~|
|IDLE<br>~~a~~|Module is idle, non-discoverable and<br>non-connectable<br>~~a~~|Module<br>~~a~~|Class 1<br>~~a~~|0.11<br>~~a~~|mA<br>~~a~~|
|IScan<br>~~ee~~|Inquiry Scan (1.28 seconds)<br>~~ee~~|Module<br>~~ee~~|Class 1<br>~~ee~~|0.65<br>~~ee~~|mA<br>~~ee~~|
|PScan<br>~~ee~~|Page scan (1.28 seconds)<br>~~ee~~|Module<br>~~ee~~|Class 1<br>~~ee~~|0.65<br>~~ee~~|mA<br>~~ee~~|
|IScan+PScan<br>~~ee~~|Inquiry scan + Page Scan (1.28 seconds)<br>~~ee~~|Module<br>~~ee~~|Class 1<br>~~ee~~|1.2<br>~~ee~~|mA<br>~~ee~~|
|Connected<br>~~ee~~|Connected with no data transfer<br>~~ee~~|Module<br>~~ee~~|Class 1<br>~~ee~~|2.6<br>~~ee~~|mA<br>~~ee~~|
|Connected + PScan<br>~~ee~~<br>~~I~~|Connected with no data transfer + Page Scan (1.28<br>seconds)<br>~~ee~~<br>~~I~~|Module<br>~~ee~~<br>~~I~~|Class 1<br>~~ee~~<br>~~I~~|3.3<br>~~ee~~<br>~~I~~|mA<br>~~ee~~<br>~~I~~|
|Connected + IScan+ PScan<br>~~a~~|Connected with no data transfer + Inquiry<br>Scan(1.28 seconds) + Page Scan (1.28 seconds)<br>~~a~~<br>~~TD~~|Module<br>~~a~~<br>~~I~~|Class 1<br>~~a~~|3.6<br>~~a~~|mA<br>~~a~~|
|Connected + SNIFF<br>~~a~~<br>~~a~~|Connected with no data transfer + SNIFF (500 ms)<br>~~a~~<br>~~a~~<br>~~TD~~|Module<br>~~a~~<br>~~a~~<br>~~I~~|Class 1<br>~~a~~<br>~~a~~|0.95<br>~~a~~<br>~~a~~|mA<br>~~a~~<br>~~a~~|
|Connected + SNIFF+ IScan<br>+ PScan<br>~~a~~|Connected with no data transfer + SNIFF (500 ms)<br>+ Inquiry Scan and Page Scan 1.28 seconds<br>~~TD ~~<br>~~a~~|Module<br> ~~I~~<br>~~a~~|Class 1<br>~~a~~|1.9<br>~~a~~|mA<br>~~a~~|
|TX_BR<br>~~pr~~|Data transfer @ 115200 baud rate<br>~~pr~~|Module<br>~~pr~~|Class 1<br>~~pr~~|22<br>~~pr~~|mA<br>~~pr~~|
|TX+SNIFF_BR<br>~~pr~~<br>~~RS~~|Data transfer @ 115200 baud rate + Sniff (500 ms)<br>~~pr~~<br>|Module<br>~~pr~~<br>|Class 1<br>~~pr~~<br>|5.5<br>~~pr~~<br>|mA<br>~~pr~~<br>|
|**Bluetooth Low Energy (BLE)**<br>~~RS~~||||||
|RXPeak<br>~~RSa~~<br>~~pp~~|Peak RX current<br>~~eee~~<br>~~pp~~|Module<br>~~eee~~|–2.5 dBm<br>+6.5 dBm<br>+9.0 dBm<br>~~eee~~|42<br>54<br>56<br>~~eee~~|mA<br>~~eee~~|
|TXPeak<br>~~a ~~<br>~~pp~~|Peak TX Current<br> ~~eee~~<br>~~pp~~|Module<br>~~eee~~|–2.5 dBm<br>+6.5 dBm<br>+9.0 dBm<br>~~eee~~|28<br>28<br>28<br>~~eee~~|mA<br>~~eee~~|
|Deep Sleep<br>~~pp~~<br>~~ae~~|Deep Sleep (HIDOFF) current<br>~~pp~~<br>~~ee~~|Module<br>~~ee~~|All<br>~~ee~~|2.69<br>~~ee~~|uA<br>~~ee~~|
|Connection_1s<br>~~pp~~<br>~~ae~~<br>~~ae~~|Connection - 1-second interval<br>~~pp~~<br>~~ee~~<br>~~ee~~|Module<br>~~ee~~<br>~~ee~~|–2.5 dBm<br>+6.5 dBm<br>+9.0 dBm<br>~~ee~~<br>~~ee~~|970<br>980<br>1000<br>~~ee~~<br>~~ee~~|uA<br>~~ee~~<br>~~ee~~|
|Connection_4s<br>~~ae~~<br>~~ae~~<br>~~ee~~|Connection - 4-second interval<br>~~ee~~<br>~~ee~~<br>~~ee~~|Module<br>~~ee~~<br>~~ee~~<br>~~ee~~|–2.5dBm<br>+6.5 dBm<br>+9.0 dBm<br>~~ee~~<br>~~ee~~<br>~~ee~~|900<br>945<br>950<br>~~ee~~<br>~~ee~~<br>~~ee~~|uA<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|Adv_640<br>~~ae~~<br>~~ee~~<br>~~ee~~|Advertisement (low duty cycle) - 640 ms<br>~~ee~~<br>~~ee~~<br>~~ee~~|Module<br>~~ee~~<br>~~ee~~<br>~~ee~~|–2.5 dBm<br>+6.5 dBm<br>+9.0 dBm<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.4<br>0.5<br>0.5<br>~~ee~~<br>~~ee~~<br>~~ee~~|mA<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|Adv_30<br>~~ee~~<br>~~ee~~|Advertisement (high duty cycle) - 30 ms<br>~~ee~~<br>~~ee~~|Module<br>~~ee~~<br>~~ee~~|–2.5 dBm<br>+6.5 dBm<br>+9.0 dBm<br>~~ee~~<br>~~ee~~<br>~~ee~~|3.8<br>4.2<br>4.3<br>~~ee~~<br>~~ee~~<br>~~ee~~|mA<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|Adv_1s<br>~~ee~~<br>~~a ~~|1-second non-connectable advertisement<br>(Beacon)<br>~~ee~~<br> ~~ee~~|Module<br>~~ee~~<br>~~ee~~|–2.5 dBm<br>+6.5 dBm<br>+9.0 dBm<br>~~ee~~<br>~~ee~~<br>~~ee~~|315<br>350<br>350<br>~~ee~~<br>~~ee~~<br>~~ee~~|uA<br>~~ee~~<br>~~ee~~<br>~~ee~~|



Page 26 of 52 

Document Number: 002-19525 Rev. *B 

**CYBT-343026-01** 

## **Chipset RF Specifications** 

All specifications in Table 14 are for industrial temperatures and are single-ended. Unused inputs are left open. 

## **Table 14.  Chipset Receiver RF Specifications** 

|**Parameter**<br>~~PO~~|**Conditions**<br>~~ee~~|**Minimum**<br>~~ee~~|**Typical**[7]|**Maximum**|**Unit**|
|---|---|---|---|---|---|
|**General**<br>~~PO~~<br>~~ee~~<br>~~Pe~~<br>~~POes~~||||||
|Frequency range<br>~~Pe~~<br>~~PO~~<br>~~es ee~~|–<br>~~Pe~~<br>~~es~~<br>~~ee~~|2402<br>~~Pe~~<br>~~es~~<br>~~ee Gs~~<br>~~re~~~~**s**~~<br>~~er~~|–<br>~~Pe~~<br>~~es~~<br>~~Gs~~<br>~~**Ge**n~~~~**s**~~<br>~~er~~|2480<br>~~Pe~~<br>~~es~~<br>~~**GR**~~<br>~~ee~~|MHz<br>~~Pe~~<br>~~es~~<br>~~ee~~|
|RX sensitivity[8]<br>~~PO ~~<br>~~es ee~~<br>~~PO~~|GFSK, 0.1% BER, 1 Mbps<br>~~es~~<br>~~ee~~|–<br>~~es~~<br>~~ee Gs~~<br>~~re~~~~**s**~~<br>~~er~~|–93.5<br>~~es~~<br>~~Gs~~<br>~~**Ge**n~~~~**s**~~<br>~~er~~|–<br>~~es~~<br>~~**GR**~~<br>~~ee~~|dBm<br>~~es~~<br>~~ee~~|
||LE GFSK, 0.1% BER, 1 Mbps<br> ~~es~~<br>~~es~~<br>~~ee~~|–<br>~~es~~<br>~~ee Gs~~<br>~~es~~<br>~~re~~~~**s**~~<br>~~er~~|–96.5<br>~~es~~<br>~~Gs~~<br>~~es~~<br>~~**Ge**n~~~~**s**~~<br>~~er~~|–<br>~~es~~<br>~~es~~<br>~~**GR**~~<br>~~ee~~|dBm<br>~~es~~<br>~~es~~<br>~~ee~~|
||/4-DQPSK, 0.01% BER, 2 Mbps<br>~~ee~~<br>|–<br>~~re~~~~**s**~~<br>~~er~~<br>~~es~~|–95.5<br>~~**Ge**n~~~~**s**~~<br>~~er~~<br>~~e~~|–<br>~~**GR**~~<br>~~ee~~|dBm<br>~~ee~~|
||8-DPSK, 0.01% BER, 3 Mbps<br>~~ee~~<br>~~e~~<br>~~tts~~|–<br>~~re~~~~**s**~~<br>~~er~~<br>~~ees~~<br>~~terns~~|–89.5<br>~~**Ge**n~~~~**s**~~<br>~~er~~<br>~~e~~<br>~~RU~~|–<br>~~**GR**~~<br>~~ee~~<br>~~I~~|dBm<br>~~ee~~|
|Maximum input<br>~~es ee~~<br>~~ee~~<br>~~PO~~|GFSK, 1 Mbps<br>~~ee ~~<br><br>~~ee~~<br>~~tts~~|–<br>~~re~~~~**s**~~<br> ~~er~~<br>~~es~~<br>~~ee~~<br>~~terns~~|–<br>~~**Ge**n~~~~**s**~~<br>~~er ~~<br>~~e~~<br>~~ee~~<br>~~RU~~|–20<br>~~**GR**~~<br> ~~ee~~<br>~~ee~~<br>~~I~~|dBm<br>~~ee~~<br>~~ee~~|
|Maximum input<br>~~ee~~<br>~~PO~~|/4-DQPSK, 8-DPSK, 2/3 Mbps<br>~~ee~~<br>~~tts~~|–<br>~~ee~~<br>~~terns~~|–<br>~~ee~~<br>~~RU~~|–20<br>~~ee~~<br>~~I~~|dBm<br>~~ee~~|
|**Interference Performance**<br>~~tts terns RU~~<br>~~I~~<br>~~PO~~<br>~~Pee~~<br>~~PO~~||||||
|C/I cochannel<br>~~Pee~~<br>~~PO~~<br>~~PO~~|GFSK, 0.1% BER<br>~~Pee~~<br>~~tts~~|–<br>~~Pee~~<br>~~terns~~|9.5<br>~~Pee~~<br>~~RU~~|11<br>~~Pee~~<br>~~I~~|dB<br>~~Pee~~|
|C/I 1 MHz adjacent channel<br>~~PO~~<br>~~ee~~<br>~~PO~~|GFSK, 0.1% BER<br>~~ee~~<br>~~tts~~|–<br>~~ee~~<br>~~terns~~|–5<br>~~ee~~<br>~~RU~~|0<br>~~ee~~<br>~~I~~|dB<br>~~ee~~|
|C/I 2 MHz adjacent channel<br>~~ee~~<br>~~PO~~<br>~~PO~~|GFSK, 0.1% BER<br>~~ee~~<br>~~tts~~<br>~~tts~~<br>|–<br>~~ee~~<br>~~terns~~<br>~~tts~~<br>|–40<br>~~ee~~<br>~~RU~~<br>|–30.0<br>~~ee~~<br>~~I~~<br>|dB<br>~~ee~~<br>|
|C/I><br> 3 MHz adjacent channel<br>~~PO~~<br>~~ee~~<br>~~PO~~|GFSK, 0.1% BER<br>~~tts ~~<br>~~ee~~<br>~~tts~~<br>|–<br> ~~terns ~~<br>~~ee~~<br>~~tts~~<br>|–49<br> ~~RU~~<br>~~ee~~<br>|–40.0<br>~~I~~<br>~~ee~~<br>|dB<br>~~ee~~<br>|
|C/I image channel<br>~~ee~~<br>~~PO~~|GFSK, 0.1% BER<br>~~ee~~<br>~~tts~~<br>|–<br>~~ee~~<br>~~tts~~<br>|–27<br>~~ee~~<br>|–9.0<br>~~ee~~<br>|dB<br>~~ee~~<br>|
|C/I 1 MHz adjacent to image<br>channel<br>~~POPo~~<br>~~PO~~|GFSK, 0.1% BER<br>~~tts~~<br>~~Po~~<br>~~tts~~|–<br>~~tts~~<br>~~Po~~<br>~~terns~~|–37<br>~~Po~~<br>~~RU~~|–20.0<br>~~Po~~<br>~~I~~|dB<br>~~Po~~|
|C/I cochannel<br>~~ee~~<br>~~PO~~|/4-DQPSK, 0.1% BER<br>~~ee~~<br>~~tts~~|–<br>~~ee~~<br>~~terns~~|11<br>~~ee~~<br>~~RU~~|13<br>~~ee~~<br>~~I~~|dB<br>~~ee~~|
|C/I 1 MHz adjacent channel<br>~~ee~~<br>~~PO~~|/4-DQPSK, 0.1% BER<br>~~ee~~<br>~~tts~~<br>~~tts~~|–<br>~~ee~~<br>~~terns~~<br>~~terns RU~~|–8<br>~~ee~~<br>~~RU~~<br>~~RU~~|0<br>~~ee~~<br>~~I~~<br>~~I~~|dB<br>~~ee~~|
|C/I 2 MHz adjacent channel<br>~~PO~~<br>~~ee~~|/4-DQPSK, 0.1% BER<br>~~tts ~~<br>~~ee~~<br>~~tts~~<br>~~rns~~|–<br> ~~terns ~~<br>~~ee~~<br>~~terns RU~~<br>~~rr~~|–40<br> ~~RU~~<br>~~ee~~<br>~~RU~~|–30.0<br>~~I~~<br>~~ee~~<br>~~I~~<br>~~GO~~|dB<br>~~ee~~|
|C/I><br> 3 MHz adjacent channel<br>~~ee~~<br>~~ee~~|8-DPSK, 0.1% BER<br>~~ee~~<br>~~tts ~~<br>~~ee~~<br>~~rns~~<br>~~tts~~|–<br>~~ee~~<br> ~~terns RU~~<br>~~ee~~<br>~~rr~~<br>~~terns RU~~|–50<br>~~ee~~<br>~~RU~~<br>~~ee~~<br>~~RU~~|–40.0<br>~~ee~~<br>~~I~~<br>~~ee~~<br>~~GO~~<br>~~I~~|dB<br>~~ee~~<br>~~ee~~|
|C/I image channel<br>~~ee~~|/4-DQPSK, 0.1% BER<br>~~rns ~~<br>~~ee~~<br>~~tts~~|–<br> ~~rr~~<br>~~ee~~<br>~~terns RU~~|–27<br>~~ee~~<br>~~RU~~|–7.0<br>~~GO~~<br>~~ee~~<br>~~I~~|dB<br>~~ee~~|
|C/I 1 MHz adjacent to image<br>channel<br>~~ee~~<br>~~po~~<br>~~es~~|/4-DQPSK, 0.1% BER<br>~~ee~~<br>~~tts ~~<br>~~po~~<br>~~Gerry rn~~|–<br>~~ee~~<br> ~~terns RU~~<br>~~po~~<br>~~rn~~|–40<br>~~ee~~<br>~~RU~~<br>~~po~~|–20.0<br>~~ee~~<br>~~I~~<br>~~po~~|dB<br>~~ee~~<br>~~po~~|
|C/I cochannel<br>~~es~~<br>~~PO~~|8-DPSK, 0.1% BER<br>~~Gerry rn~~|–<br>~~rn~~|17|21|dB|
|C/I 1 MHz adjacent channel<br>~~es~~<br>~~PO~~<br>~~re Genres~~|8-DPSK, 0.1% BER<br>~~Gerry rn~~<br>~~Genres tr~~|–<br>~~rn~~<br>~~tr~~|–5<br>~~rs~~|5|dB|
|C/I 2 MHz adjacent channel<br>~~PO~~<br>~~re Genres~~<br>~~es~~|8-DPSK, 0.1% BER<br>~~Genres tr~~<br>~~tty~~<br>|–<br>~~tr~~<br>~~nny ts~~<br>|–40<br>~~rs~~<br>~~ts~~|–25.0<br>~~Gs~~|dB|
|C/I><br>3 MHz adjacent channel<br>~~re Genres~~<br>~~ee~~<br>~~es Greenery~~|8-DPSK, 0.1% BER<br>~~Genres tr~~<br>~~ee~~<br>~~tty~~<br>~~Greenery rt~~|–<br>~~tr~~<br>~~ee~~<br>~~nny ts~~<br>~~rt~~|–47<br>~~rs~~<br>~~ee~~<br>~~ts~~|–33.0<br>~~ee~~<br>~~Gs~~|dB<br>~~ee~~|
|C/I Image channel<br>~~ee~~<br>~~es Greenery~~|8-DPSK, 0.1% BER<br>~~ee~~<br>~~tty~~<br>~~Greenery rt~~|–<br>~~ee~~<br>~~nny ts~~<br>~~rt~~|–20<br>~~ee~~<br>~~ts~~|0<br>~~ee~~<br>~~Gs~~|dB<br>~~ee~~|
|C/I 1 MHz adjacent to image<br>channel<br>~~es Greenery~~<br>~~A~~|8-DPSK, 0.1% BER<br>~~tty~~<br>~~Greenery rt~~<br>~~A~~|–<br>~~nny ts~~<br>~~rt~~<br>~~A~~|–35<br>~~ts~~<br>~~A~~|–13.0<br>~~Gs~~<br>~~A~~|dB<br>~~A~~|
|**Out-of-Band Blocking Performance (CW)**[9]<br>~~A~~<br>~~nn~~<br>~~rttrentRR~~<br>~~I~~<br>~~PO~~||||||
|30 MHz–2000 MHz<br>~~te~~<br>~~PO~~|0.1% BER<br>~~te~~<br>~~rt~~|–<br>~~te~~<br>~~trent~~|–10.0<br>~~te~~<br>~~RR~~|–<br>~~te~~<br>~~I~~|dBm<br>~~te~~|
|2000–2399 MHz<br>~~te~~<br>~~PO~~|0.1% BER<br>~~te~~<br>~~rt~~|–<br>~~te~~<br>~~trent~~|–27<br>~~te~~<br>~~RR~~|–<br>~~te~~<br>~~I~~|dBm<br>~~te~~|



> 7. Typical operating conditions are 1.22-V operating voltage and 25°C ambient temperature. 

> 8. The receiver sensitivity is measured at BER of 0.1% on the device interface. 

> 9. Meets this specification using front-end band pass filter. 

**Notes** 

Page 27 of 52 

Document Number: 002-19525 Rev. *B 

**CYBT-343026-01** 

**Table 14.  Chipset Receiver RF Specifications** (continued) 

|**Parameter**<br>~~DG~~|**Conditions**<br>~~DG~~|**Minimum**<br>~~DG~~|**Typical**[7]<br>~~DG~~|**Maximum**<br>~~DG~~|**Unit**<br>~~DG~~|
|---|---|---|---|---|---|
|2498–3000 MHz<br>~~a~~|0.1% BER|–|–27|–|dBm|
|3000 MHz–12.75 GHz<br>~~a~~|0.1% BER<br>~~DG~~|–<br>~~DG~~|–10.0<br>~~DG~~|–<br>~~DG~~|dBm<br>~~DG~~|
|**Out-of-Band Blocking Performance, Modulated Interferer**<br>~~Re~~||||||
|776–764 MHz<br>~~Re~~<br>~~DG~~|CDMA<br>~~Re~~<br>~~DG~~|–<br>~~Re~~<br>~~DG~~|–10[10]<br>~~Re~~<br>~~DG~~<br>~~I~~|–<br>~~Re~~<br>~~DG~~|dBm<br>~~Re~~<br>~~DG~~|
|824–849 MHz<br>~~a~~|CDMA<br>~~Gs~~|–<br>~~Gs~~|–10[10]<br>~~Gs~~<br>~~I~~|–<br>~~Gs~~|dBm<br>~~Gs~~|
|1850–1910 MHz<br>~~a~~<br>~~nD~~|CDMA<br>~~Gs~~<br>~~nD~~|–<br>~~Gs~~<br>~~nD~~|–23[10]<br>~~Gs~~<br>~~I~~<br>~~nD~~<br>~~I~~|–<br>~~Gs~~<br>~~nD~~|dBm<br>~~Gs~~<br>~~nD~~|
|824–849 MHz<br>~~a~~|EDGE/GSM<br>~~Gs~~|–<br>~~Gs~~|–10[10]<br>~~Gs~~<br>~~I~~|–<br>~~Gs~~|dBm<br>~~Gs~~|
|880–915 MHz<br>~~a~~<br>~~nD~~|EDGE/GSM<br>~~Gs~~<br>~~nD~~|–<br>~~Gs~~<br>~~nD~~|–10[10]<br>~~Gs~~<br>~~I~~<br>~~nD~~<br>~~I~~|–<br>~~Gs~~<br>~~nD~~|dBm<br>~~Gs~~<br>~~nD~~|
|1710–1785 MHz<br>~~a~~|EDGE/GSM<br>~~Gs~~|–<br>~~Gs~~|–23[10]<br>~~Gs~~<br>~~I~~|–<br>~~Gs~~|dBm<br>~~Gs~~|
|1850–1910 MHz<br>~~a~~<br>~~nD~~|EDGE/GSM<br>~~Gs~~<br>~~nD~~|–<br>~~Gs~~<br>~~nD~~|–23[10]<br>~~Gs~~<br>~~I~~<br>~~nD~~<br>~~I~~|–<br>~~Gs~~<br>~~nD~~|dBm<br>~~Gs~~<br>~~nD~~|
|1850–1910 MHz<br>~~a~~|WCDMA<br>~~Gs~~|–<br>~~Gs~~|–23[10]<br>~~Gs~~<br>~~I~~|–<br>~~Gs~~|dBm<br>~~Gs~~|
|1920–1980 MHz<br>~~a~~<br>~~DG~~|WCDMA<br>~~Gs~~<br>~~DG~~|–<br>~~Gs~~<br>~~DG~~|–23[10]<br>~~Gs~~<br>~~I~~<br>~~DG~~|–<br>~~Gs~~<br>~~DG~~|dBm<br>~~Gs~~<br>~~DG~~|
|**Intermodulation Performance**[11]<br>~~Re~~<br>~~nDGO~~||||||
|BT, Df = 5 MHz<br>~~Re~~<br>~~nD~~|–<br>~~Re~~<br>~~nD~~|–39.0<br>~~Re~~<br>~~GO~~|–<br>~~Re~~<br>~~GO~~|–<br>~~Re~~<br>~~GO~~|dBm<br>~~Re~~|
|**Spurious Emissions**[12]<br>~~nDGO~~<br>~~Re~~||||||
|30 MHz to 1 GHz<br>~~Re~~<br>~~DG~~|–<br>~~Re~~<br>~~DG~~|–<br>~~Re~~<br>~~DG~~|–<br>~~Re~~<br>~~DG~~<br>~~I~~|–62<br>~~Re~~<br>~~DG~~|dBm<br>~~Re~~<br>~~DG~~|
|1 GHz to 12.75 GHz<br>~~a~~|–<br>~~Gs~~|–<br>~~Gs~~|–<br>~~Gs~~<br>~~I~~|–47<br>~~Gs~~|dBm<br>~~Gs~~|
|65 MHz to 108 MHz<br>~~a~~<br>~~nD~~|FM Rx<br>~~Gs~~<br>~~nD~~|–<br>~~Gs~~<br>~~nD~~|–147<br>~~Gs~~<br>~~I~~<br>~~nD~~<br>~~I~~|–<br>~~Gs~~<br>~~nD~~|dBm/Hz<br>~~Gs~~<br>~~nD~~|
|746 MHz to 764 MHz<br>~~a~~|CDMA<br>~~Gs~~|–<br>~~Gs~~|–147<br>~~Gs~~<br>~~I~~|–<br>~~Gs~~|dBm/Hz<br>~~Gs~~|
|851–894 MHz<br>~~a~~<br>~~nD~~|CDMA<br>~~Gs~~<br>~~nD~~|–<br>~~Gs~~<br>~~nD~~|–147<br>~~Gs~~<br>~~I~~<br>~~nD~~<br>~~I~~|–<br>~~Gs~~<br>~~nD~~|dBm/Hz<br>~~Gs~~<br>~~nD~~|
|925–960 MHz<br>~~a~~|EDGE/GSM<br>~~Gs~~|–<br>~~Gs~~|–147<br>~~Gs~~<br>~~I~~|–<br>~~Gs~~|dBm/Hz<br>~~Gs~~|
|1805–1880 MHz<br>~~a~~<br>~~nD~~|EDGE/GSM<br>~~Gs~~<br>~~nD~~|–<br>~~Gs~~<br>~~nD~~|–147<br>~~Gs~~<br>~~I~~<br>~~nD~~<br>~~I~~|–<br>~~Gs~~<br>~~nD~~|dBm/Hz<br>~~Gs~~<br>~~nD~~|
|1930–1990 MHz<br>~~a~~|PCS<br>~~Gs~~|–<br>~~Gs~~|–147<br>~~Gs~~<br>~~I~~|–<br>~~Gs~~|dBm/Hz<br>~~Gs~~|
|2110–2170 MHz<br>~~a~~<br>~~DG~~|WCDMA<br>~~Gs~~<br>~~DG~~|–<br>~~Gs~~<br>~~DG~~|–147<br>~~Gs~~<br>~~I~~<br>~~DG~~|–<br>~~Gs~~<br>~~DG~~|dBm/Hz<br>~~Gs~~<br>~~DG~~|



## **Notes** 

> 10. Numbers are referred to the pin output with an external BPF filter. 

> 11. f0 = -64 dBm Bluetooth-modulated signal, f1 = –39 dBm sine wave, f2 = –39 dBm Bluetooth-modulated signal, f0 = 2f1 – f2, and |f2 – f1| = n*1 MHz, where n is 3, 4, or 5. For the typical case, n = 4. 

> 12. Includes baseband radiated emissions. 

Page 28 of 52 

Document Number: 002-19525 Rev. *B 

**CYBT-343026-01** 

## **Table 15.  Chipset Transmitter RF Specifications** 

|**Parameter**<br>~~a~~|**Conditions**|**Minimum**|**Typical**|**Maximum**|**Unit**|
|---|---|---|---|---|---|
|**General**<br>~~pn~~||||||
|Frequency range<br>~~a~~|–|2402|–|2480|MHz|
|Class1: GFSK Tx power[13]<br>~~a~~|–|–|12|–|dBm|
|Class1: EDR Tx power[14]<br>~~a~~<br>~~a~~|–|–|9|–|dBm|
|Class 2: GFSK Tx power<br>~~a~~|–|–|2|–|dBm|
|Power control step<br>~~a~~<br>~~a~~|–|2|4|8|dB|
|**Modulation Accuracy**<br>~~pt~~||||||
|/4-DQPSK Frequency Stability<br>~~pt~~<br>~~a~~|–<br>~~pt~~|–10<br>~~pt~~|–<br>~~pt~~|10<br>~~pt~~|kHz<br>~~pt~~|
|/4-DQPSK RMS DEVM<br>~~a~~|–|–|–|20|%|
|/4-QPSK Peak DEVM<br>~~a~~|–|–|–|35|%|
|/4-DQPSK 99% DEVM<br>~~a~~|–|–|–|30|%|
|8-DPSK frequency stability<br>~~a~~|–|–10|–|10|kHz|
|8-DPSK RMS DEVM<br>~~a~~|–|–|–|13|%|
|8-DPSK Peak DEVM<br>~~a~~|–|–|–|25|%|
|8-DPSK 99% DEVM<br>~~a~~|–|–|–|20|%|
|**In-Band Spurious Emissions**||||||
|1.0 MHz < |M – N| < 1.5 MHz<br>~~a~~|–|–|–|–26|dBc|
|1.5 MHz < |M – N| < 2.5 MHz<br>~~a~~|–|–|–|–20|dBm|
||M – N|><br>2.5 MHz<br>~~a~~|–|–|–|–40|dBm|
|**Out-of-Band Spurious Emissions**||||||
|30 MHz to 1 GHz<br>~~a~~|–|–|–|–36.0[15]|dBm|
|1 GHz to 12.75 GHz<br>~~a~~|–|–|–|–30.0[15, 16]|dBm|
|1.8 GHz to 1.9 GHz<br>~~a~~|–|–|–|–47.0|dBm|
|5.15 GHz to 5.3 GHz<br>~~a~~|–|–|–|–47.0|dBm|



**Table 16.  Chipset BLE RF Specifications** 

|**Parameter**|**Conditions**|**Minimum**|**Typical**|**Maximum**|**Unit**|
|---|---|---|---|---|---|
|Frequency range|N/A|2402|–|2480|MHz|
|Rx sense[17]|GFSK, 0.1% BER, 1 Mbps|–|–96.5|–|dBm|
|Tx power[18]|N/A|–|–|9|dBm|
|Mod Char: Delta F1 average|N/A|225|255|275|kHz|
|Mod Char: Delta F2 max[19]|N/A|99.9|–|–|%|
|Mod Char: Ratio|N/A|0.8|0.95|–|%|



13. TBD dBm output for GFSK measured with PAVDD = 2.5 V. 

> 14. TBD dBm output for EDR measured with PAVDD = 2.5 V. 

15. Maximum value is the value required for Bluetooth qualification. 

16. Meets this spec using a front-end band-pass filter. 

17. Dirty Tx is Off. 

18. The BLE Tx power can be increased to compensate for front-end losses such as BPF, diplexer, switch, etc. The output is capped at 12 dBm out. The BLE Tx power at the antenna port cannot exceed the 10 dBm EIRP specification limit. 

19. At least 99.9% of all delta F2 max frequency values recorded over 10 packets must be greater than 185 kHz. 

Page 29 of 52 

Document Number: 002-19525 Rev. *B 

**CYBT-343026-01** 

## **Timing and AC Characteristics** 

In this section, use the numbers listed in the **Reference** column of each table to interpret the following timing diagrams. 

## **UART Timing** 

**Table 17.  UART Timing Specifications** 

|**Reference**|**Characteristics**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|
|1|Delaytime, UART_CTS_N low to UART_TXD valid|–|24|Baud out cycles|
|2|Setuptime, UART_CTS_N high before midpoint of stopbit|–|10|ns|
|3|Delaytime, midpoint of stopbit to UART_RTS_N high|–|2|Baud out cycles|



**Figure 13.  UART Timing** 

Page 30 of 52 

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**CYBT-343026-01** 

## **SPI Timing** 

The SPI interface supports clock speeds up to 12 MHz 

Table 18 and Figure 14 show the timing requirements when operating in SPI Mode 0 and 2, and SPI Mode 1 and 3, respectively. 

## **Table 18.  SPI Mode 0 and 2** 

|**Reference**|**Characteristics**|**Minimum**|**Maximum**|**Unit**|
|---|---|---|---|---|
|1|Time from slave assert SPI_INT to master assert SPI_CSN (Direc-<br>tRead)|0||ns|
|2|Time from master assert SPI_CSN to slave assert SPI_INT (Direct-<br>Write)|0||ns|
|3|Time from master assert SPI_CSN to first clock edge|20||ns|
|4|Setup time for MOSI data lines|8|½SCK|ns|
|5|Hold time for MOSI data lines|8|½SCK|ns|
|6|Time from last sample on MOSI/MISO to slave deassert SPI_INT|0|100|ns|
|7|Time from slave deassert SPI_INT to master deassert SPI_CSN|0||ns|
|8|Idle time between subsequent SPI transactions|1 SCK||ns|



## **Figure 14.  SPI Timing – Mode 0 and 2** 

Table 19 and Figure 15 show the timing requirements when operating in SPI Mode 1 and 3. 

Page 31 of 52 

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**CYBT-343026-01** 

## **Table 19.  SPI Mode 1 and 3** 

|**Reference**|**Characteristics**|**Minimum**|**Maximum**|**Unit**|
|---|---|---|---|---|
|1|Time from slave assert SPI_INT to master assert<br>SPI_CSN (DirectRead)|0||ns|
|2|Time from master assert SPI_CSN to slave assert<br>SPI_INT (DirectWrite)|0||ns|
|3|Time from master assert SPI_CSN to first clock edge|20||ns|
|4|Setup time for MOSI data lines|8|½SCK|ns|
|5|Hold time for MOSI data lines|8|½SCK|ns|
|6|Time from last sample on MOSI/MISO to slave<br>deassert SPI_INT|0|100|ns|
|7|Time from slave deassert SPI_INT to master<br>deassert SPI_CSN|0||ns|
|8|Idle time between subsequent SPI transactions|1 SCK||ns|



**Figure 15.  SPI Timing – Mode 1 and 3** 

Page 32 of 52 

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**CYBT-343026-01** 

## **I[2] C Interface Timing** 

**Table 20.  I[2] C Interface Timing Specifications** 

|**Reference**<br>~~se~~|**Characteristics**<br>~~se~~|**Min**<br>~~se~~|**Max**<br>~~se~~|**Unit**<br>~~se~~|
|---|---|---|---|---|
|1<br>~~a~~|Clock frequency<br>|–<br>|100<br>~~Po~~|kHz<br>|
||||400<br>~~|~~||
||||800<br>~~|~~<br>~~po~~||
||||1000<br>~~po~~<br>~~Po~~<br>||
|2<br>~~a~~|START condition setuptime<br>|650<br>|–<br>~~Po~~<br>|ns<br>|
|3<br>~~aCe~~|START condition hold time<br>~~Ce~~|280<br>~~Ce~~|–<br>~~Po~~<br>~~Ce~~|ns<br>~~Ce~~|
|4<br>~~Ce~~<br>~~Ge~~<br>~~a~~|Clock low time<br>~~Ce~~<br>~~Ge~~<br>|650<br>~~Ce~~<br>~~Ge~~<br>|–<br>~~Ce~~<br>~~Ge~~<br>|ns<br>~~Ce~~<br>~~Ge~~<br>|
|5<br>~~a~~|Clock high time<br>|280<br>|–<br>|ns<br>|
|6<br>~~ase~~|Data input hold time[20]<br>~~se~~|0<br>~~se~~|–<br>~~se~~|ns<br>~~se~~|
|7<br>~~eC~~<br>~~a~~|Data input setuptime<br>~~eC~~<br>|100<br>~~eC~~<br>|–<br>~~eC~~<br>|ns<br>~~eC~~<br>|
|8<br>~~a~~|STOP condition setuptime<br>|280<br>|–<br>|ns<br>|
|9<br>~~ase~~|Output valid from clock<br>~~se~~|–<br>~~se~~|400<br>~~se~~|ns<br>~~se~~|
|10<br>~~ee~~|Bus free time[21]<br>~~ee~~|650<br>~~ee~~|–<br>~~ee~~|ns<br>~~ee~~|



## **Figure 16.  I[2] C Interface Timing Diagram** 

## **Notes** 

20. As a transmitter, 125 ns of delay is provided to bridge the undefined region of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 21. Time that the cbus must be free before a new transaction can start. 

Page 33 of 52 

Document Number: 002-19525 Rev. *B 

**CYBT-343026-01** 

## **PCM Interface Timing** 

_Short Frame Sync, Master Mode_ 

**Figure 17.  PCM Timing Diagram (Short Frame Sync, Master Mode)** 

**Table 21.  PCM Interface Timing Specifications (Short Frame Sync, Master Mode)** 

|**Reference**<br>~~a~~|**Characteristics**<br>~~G~~|**Minimum**<br>~~G~~|**Typical**<br>~~G~~|**Maximum**<br>~~G~~|**Unit**<br>~~G~~|
|---|---|---|---|---|---|
|1<br>~~a~~|PCM bit clock frequency<br>~~a~~|–<br>~~a~~|–<br>~~a~~|12<br>~~a~~|MHz<br>~~a~~|
|2<br>~~a~~|PCM bit clock LOW<br>~~a~~|41.0<br>~~a~~|–<br>~~a~~|–<br>~~a~~|ns<br>~~a~~|
|3<br>~~a~~|PCM bit clock HIGH<br>~~a~~|41.0<br>~~a~~|–<br>~~a~~|–<br>~~a~~|ns<br>~~a~~|
|4<br>~~a~~|PCM_SYNC delay<br>~~a~~|0<br>~~a~~|–<br>~~a~~|25.0<br>~~a~~|ns<br>~~a~~|
|5<br>~~a~~|PCM_OUT delay<br>~~a~~|0<br>~~a~~|–<br>~~a~~|25.0<br>~~a~~|ns<br>~~a~~|
|6<br>~~a~~|PCM_IN setup<br>~~a~~|8.0<br>~~a~~|–<br>~~a~~|–<br>~~a~~|ns<br>~~a~~|
|7<br>~~a~~|PCM_IN hold<br>~~a~~<br>~~G~~|8.0<br>~~a~~<br>~~G~~|–<br>~~a~~<br>~~G~~|–<br>~~a~~<br>~~G~~|ns<br>~~a~~<br>~~G~~|
|8|Delay from rising edge of PCM_BCLK during last bit period<br>to PCM_OUT becoming high impedance|0|–|25.0|ns|



Page 34 of 52 

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**CYBT-343026-01** 

_Short Frame Sync, Slave Mode_ 

**Figure 18.  PCM Timing Diagram (Short Frame Sync, Slave Mode)** 

**Table 22.  PCM Interface Timing Specifications (Short Frame Sync, Slave Mode)** 

|**Reference**<br>~~a GG~~<br>~~es~~|**Characteristics**<br>~~GG~~<br>~~OC~~|**Minimum**<br>~~GG~~<br>~~OC~~|**Typical**<br>~~GG~~<br>~~OC~~|**Maximum**<br>~~GG~~<br>~~OC~~|**Unit**<br>~~GG~~<br>~~OC~~|
|---|---|---|---|---|---|
|1<br>~~a GG~~<br>~~es~~|PCM bit clock frequency<br>~~GG~~<br>~~OC~~|–<br>~~GG~~<br>~~OC~~|–<br>~~GG~~<br>~~OC~~|12.0<br>~~GG~~<br>~~OC~~|MHz<br>~~GG~~<br>~~OC~~|
|2<br>~~es~~<br>~~a~~|PCM bit clock LOW<br>~~OC~~<br>~~GG~~|41.0<br>~~OC~~<br>~~GG~~|–<br>~~OC~~<br>~~GG~~|–<br>~~OC~~<br>~~GG~~|ns<br>~~OC~~<br>~~GG~~|
|3<br>~~a~~<br>~~a GC~~|PCM bit clock HIGH<br>~~GG~~<br>~~GC~~|41.0<br>~~GG~~<br>~~GC~~|–<br>~~GG~~<br>~~GC~~|–<br>~~GG~~<br>~~GC~~|ns<br>~~GG~~<br>~~GC~~|
|4<br>~~a~~|PCM_SYNC setup<br>~~GG~~|8.0<br>~~GG~~|–<br>~~GG~~|–<br>~~GG~~|ns<br>~~GG~~|
|5<br>~~a~~<br>~~a GC~~|PCM_SYNC hold<br>~~GG~~<br>~~GC~~|8.0<br>~~GG~~<br>~~GC~~|–<br>~~GG~~<br>~~GC~~|–<br>~~GG~~<br>~~GC~~|ns<br>~~GG~~<br>~~GC~~|
|6<br>~~a~~|PCM_OUT delay<br>~~GG~~|0<br>~~GG~~|–<br>~~GG~~|25.0<br>~~GG~~|ns<br>~~GG~~|
|7<br>~~a GC~~|PCM_IN setup<br>~~GC~~|8.0<br>~~GC~~|–<br>~~GC~~|–<br>~~GC~~|ns<br>~~GC~~|
|8<br>~~a~~|PCM_IN hold<br>~~GG~~|8.0<br>~~GG~~|–<br>~~GG~~|–<br>~~GG~~|ns<br>~~GG~~|
|9<br>~~a~~|Delay from rising edge of PCM_BCLK during last bit<br>period to PCM_OUT becoming high impedance<br>~~GG~~|0<br>~~GG~~|–<br>~~GG~~|25.0<br>~~GG~~|ns<br>~~GG~~|



Page 35 of 52 

Document Number: 002-19525 Rev. *B 

**CYBT-343026-01** 

_Long Frame Sync, Master Mode_ 

## **Figure 19.  PCM Timing Diagram (Long Frame Sync, Master Mode)** 

**Table 23.  PCM Interface Timing Specifications (Long Frame Sync, Master Mode)** 

|**Reference**|**Characteristics**|**Minimum**|**Typical**|**Maximum**|**Unit**|
|---|---|---|---|---|---|
|1|PCM bit clock frequency|–|–|12|MHz|
|2|PCM bit clock LOW|41.0|–|–|ns|
|3|PCM bit clock HIGH|41.0|–|–|ns|
|4|PCM_SYNC delay|0|–|25.0|ns|
|5|PCM_OUT delay|0|–|25.0|ns|
|6|PCM_IN setup|8.0|–|–|ns|
|7|PCM_IN hold|8.0|–|–|ns|
|8|Delay from rising edge of PCM_BCLK during last bit period<br>to PCM_OUT becoming high impedance|0|–|25.0|ns|



Page 36 of 52 

Document Number: 002-19525 Rev. *B 

**CYBT-343026-01** 

_Long Frame Sync, Slave Mode_ 

## **Figure 20.  PCM Timing Diagram (Long Frame Sync, Slave Mode)** 

**Table 24.  PCM Interface Timing Specifications (Long Frame Sync, Slave Mode)** 

|**Reference**|**Characteristics**|**Minimum**|**Typical**|**Maximum**|**Unit**|
|---|---|---|---|---|---|
|1|PCM bit clock frequency|–|–|12|MHz|
|2|PCM bit clock LOW|41.0|–|–|ns|
|3|PCM bit clock HIGH|41.0|–|–|ns|
|4|PCM_SYNC setup|8.0|–|–|ns|
|5|PCM_SYNC hold|8.0|–|–|ns|
|6|PCM_OUT delay|0|–|25.0|ns|
|7|PCM_IN setup|8.0|–|–|ns|
|8|PCM_IN hold|8.0|–|–|ns|
|9|Delay from rising edge of PCM_BCLK during last bit period<br>to PCM_OUT becoming high impedance|0|–|25.0|ns|



Page 37 of 52 

Document Number: 002-19525 Rev. *B 

**CYBT-343026-01** 

## **I[2] S Interface Timing** 

The I[2] S interface supports both master and slave modes. The I[2] S signals are: 

- I[2] S clock: I[2] S SCK 

- I[2] S Word Select: I[2] S WS 

- I[2] S Data Out: I[2] S SDO 

- I[2] S Data In: I[2] S SDI 

I[2] S SCK and I[2] S WS become outputs in master mode and inputs in slave mode, while I[2] S SDO always stays as an output. The channel word length is 16 bits and the data is justified so that the MSB of the left-channel data is aligned with the MSB of the I[2] S bus, per the I[2] S specification. The MSB of each data word is transmitted one bit clock cycle after the I[2] S WS transition, synchronous with the falling edge of bit clock. Left-channel data is transmitted when I[2] S WS is low, and right-channel data is transmitted when I[2] S WS is high. Data bits sent by the CYBT-343026-01 are synchronized with the falling edge of I2S_SCK and should be sampled by the receiver on the rising edge of I2S_SSCK. 

The clock rate in master mode is either of the following: 

- 48 kHz x 32 bits per frame = 1.536 MHz 

- 48 kHz x 50 bits per frame = 2.400 MHz 

Page 38 of 52 

Document Number: 002-19525 Rev. *B 

**CYBT-343026-01** 

The master clock is generated from the input reference clock using a N/M clock divider. In the slave mode, any clock rate is supported to a maximum of 3.072 MHz. Timing values specified in Table 25 are relative to high and low threshold levels. 

**Table 25.  Timing for I[2] S Transmitters and Receivers** 

|~~Be~~|**Transmitter**<br>~~a~~<br>~~Be~~|**Transmitter**<br>~~a~~<br>~~Be~~|**Transmitter**<br>~~a~~<br>~~Be~~|**Transmitter**<br>~~a~~<br>~~Be~~|**Receiver**<br>~~a~~<br>~~Be~~|**Receiver**<br>~~a~~<br>~~Be~~|**Receiver**<br>~~a~~<br>~~Be~~|**Receiver**<br>~~a~~<br>~~Be~~|**Notes**<br>~~Be~~|
|---|---|---|---|---|---|---|---|---|---|
||**Lower LImit**<br>~~Be~~<br>~~pf~~||**Upper Limit**<br>~~Be~~||**Lower Limit**<br>~~Be~~||**Upper Limit**<br>~~Be~~|||
||**Min**<br>~~Be~~<br>~~pf~~|**Max**<br>~~Be~~<br>~~pf~~|**Min**<br>~~Be~~|**Max**<br>~~Be~~|**Min**<br>~~Be~~|**Max**<br>~~Be~~|**Min**<br>~~Be~~|**Max**<br>~~Be~~||
|Clock Period T<br>~~se~~|Ttr<br>~~pf~~<br>~~se~~|–<br>~~pf~~<br>~~se~~|–<br>~~se~~|–<br>~~se~~|Tr<br>~~se~~|–<br>~~se~~|–<br>~~se~~|–<br>~~se~~|Note 22<br>~~se~~|
|**Master Mode: Clock generated by transmitter or receiver**<br>~~se~~<br>~~TT~~<br>~~po~~||||||||||
|HIGH tHC<br>~~po~~<br>~~po~~|0.35Ttr|–|–|–|0.35Ttr|–|–|–|Note 23|
|LOWtLC<br>~~po~~<br>~~po~~|0.35Ttr|–|–|–|0.35Ttr|–|–|–|Note 23|
|**Slave Mode: Clock accepted by transmitter or receiver**<br>~~po~~<br>~~TT~~<br>~~**e**s~~<br>~~es ese~~~~**s**~~||||||||||
|HIGH tHC<br>~~**e**s~~|–<br>~~es es~~|0.35Ttr<br>~~es~~|–<br>~~e~~|–<br>~~e~~~~**s**~~|–|0.35Ttr|–|–|Note 24|
|LOW tLC<br>~~**e**s~~<br>~~po~~|–<br>~~es es~~|0.35Ttr<br>~~es ~~|–<br> ~~e~~|–<br>~~e~~~~**s**~~|–|0.35Ttr|–|–|Note 24|
|Rise time tRC<br>~~po~~|–|–|0.15Ttr|–|–|–||–|Note 25|
|**Transmitter**<br>~~po~~<br>~~TT~~||||||||||
|Delay tdtr<br>~~OO~~|–<br>~~OO~~|–<br>~~OO~~|–<br>~~OO~~|0.8T<br>~~OO~~|–<br>~~OO~~|–<br>~~OO~~|–<br>~~OO~~|–<br>~~OO~~|Note 26<br>~~OO~~|
|Hold time thtr<br>~~a~~|0|–|–|–|–|–|–|–|Note 26|
|**Receiver**<br>~~TT~~<br>~~esseee~~||||||||||
|Setup time tsr<br>~~es~~|–<br>~~se~~|–<br>~~se~~|–<br>~~ee~~|–<br>~~ee~~|–|0.2Tr|–|–|Note 27|
|Hold time thr<br>~~es ~~<br>~~a~~|–<br> ~~se~~<br>~~OO~~|–<br>~~se ~~<br>~~OO~~|–<br> ~~ee~~<br>~~OO~~|–<br>~~ee~~|–|0|–|–|Note 27|



Note: The time periods specified in Figure 21 and Figure 22 are defined by the transmitter speed. The receiver specifications must match transmitter performance. 

## **Notes** 

> 22. The system clock period T must be greater than Ttr and Tr because both the transmitter and receiver have to be able to handle the data transfer rate. 

> 23. At all data rates in master mode, the transmitter or receiver generates a clock signal with a fixed mark/space ratio. For this reason, tHC and tLC are specified with respect to T. 

> 24. In slave mode, the transmitter and receiver need a clock signal with minimum HIGH and LOW periods so that they can detect the signal. So long as the minimum periods are greater than 0.35Tr, any clock that meets the requirements can be used. 

> 25. Because the delay (tdtr) and the maximum transmitter speed (defined by Ttr) are related, a fast transmitter driven by a slow clock edge can result in tdtr not exceeding tRC which means thtr becomes zero or negative. Therefore, the transmitter has to guarantee that thtr is greater than or equal to zero, so long as the clock rise-time tRC is not more than tRCmax, where tRCmax is not less than 0.15Ttr. 

> 26. To allow data to be clocked out on a falling edge, the delay is specified with respect to the rising edge of the clock signal and T, always giving the receiver sufficient setup time. 

> 27. The data setup and hold time must not be less than the specified receiver setup and hold time. 

Page 39 of 52 

Document Number: 002-19525 Rev. *B 

**CYBT-343026-01** 

**Figure 21.  I[2] S Transmitter Timing** 

**Figure 22.  I[2] S Receiver Timing** 

Page 40 of 52 

Document Number: 002-19525 Rev. *B 

**CYBT-343026-01** 

## **Environmental Specifications** 

## **Environmental Compliance** 

This CYBT-343026-01 BLE module is produced in compliance with the Restriction of Hazardous Substances (RoHS) and Halogen-Free (HF) directives. The Cypress module and components used to produce this module are RoHS and HF compliant. 

## **RF Certification** 

The CYBT-343026-01 module will be certified under the following RF certification standards at production release. 

■ FCC: WAP3026 

■ CE 

■ IC: 7922A-3026 

■ MIC: 203-JN0721 

## **Safety Certification** 

The CYBT-343026-01 module complies with the following safety regulations: 

■ Underwriters Laboratories, Inc. (UL): Filing E331901 

■ CSA 

- TUV 

## **Environmental Conditions** 

Table 26 describes the operating and storage conditions for the Cypress BLE module. 

## **Table 26.  Environmental Conditions for CYBT-343026-01** 

|**Description**|**Minimum Specification**|**Maximum Specification**|
|---|---|---|
|Operating temperature|–30 °C|85 °C|
|Operating humidity (relative, non-condensation)|5%|85%|
|Thermal ramp rate|–|3 °C/minute|
|Storage temperature|–40 °C|85 °C|
|Storage temperature and humidity|–|85 °C at 85%|
|ESD: Module integrated into end system<br>Components[28]|–|15 kV Air<br>2.0 kV Contact|



## **ESD and EMI Protection** 

Exposed components require special attention to ESD and electromagnetic interference (EMI). 

A grounded conductive layer inside the device enclosure is suggested for EMI and ESD performance. Any openings in the enclosure near the module should be surrounded by a grounded conductive layer to provide ESD protection and a low-impedance path to ground. **Device Handling** : Proper ESD protocol must be followed in manufacturing to ensure component reliability. 

> 28. This does not apply to the RF pins (ANT). 

**Note** 

Page 41 of 52 

Document Number: 002-19525 Rev. *B 

**CYBT-343026-01** 

## **Regulatory Information** 

## **FCC** 

## FCC NOTICE: 

The device CYBT-343026-01 complies with Part 15 of the FCC Rules. The device meets the requirements for modular transmitter approval as detailed in FCC public Notice DA00-1407.transmitter Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation. 

## CAUTION: 

The FCC requires the user to be notified that any changes or modifications made to this device that are not expressly approved by Cypress Semiconductor may void the user's authority to operate the equipment. 

This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures: 

■ Reorient or relocate the receiving antenna. 

■ Increase the separation between the equipment and receiver. 

■ Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. 

- Consult the dealer or an experienced radio/TV technician for help 

## LABELING REQUIREMENTS: 

The Original Equipment Manufacturer (OEM) must ensure that FCC labelling requirements are met. This includes a clearly visible label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor FCC identifier for this product as well as the FCC Notice above. The FCC identifier is FCC ID: WAP3026. 

In any case the end product must be labeled exterior with "Contains FCC ID: WAP3026" 

## ANTENNA WARNING: 

This device is tested with a standard SMA connector and with the antenna listed in Table 6 on page 13. When integrated in the OEMs product, these fixed antennas require installation preventing end-users from replacing them with non-approved antennas. Any antenna not in the following table must be tested to comply with FCC Section 15.203 for unique antenna connectors and Section 15.247 for emissions. 

## RF EXPOSURE: 

To comply with FCC RF Exposure requirements, the Original Equipment Manufacturer (OEM) must ensure to install the approved antenna in the previous. 

The preceding statement must be included as a CAUTION statement in manuals, for products operating with the approved antenna in Table 6 on page 13, to alert users on FCC RF Exposure compliance. Any notification to the end user of installation or removal instructions about the integrated radio module is not allowed. 

The radiated output power of CYBT-343026-01 with the trace antenna is far below the FCC radio frequency exposure limits. Nevertheless, use CYBT-343026-01 in such a manner that minimizes the potential for human contact during normal operation. 

End users may not be provided with the module installation instructions. OEM integrators and end users must be provided with transmitter operating conditions for satisfying RF exposure compliance. 

Page 42 of 52 

Document Number: 002-19525 Rev. *B 

**CYBT-343026-01** 

## **ISED** 

## **Innovation, Science, and Economic Development Canada (ISED) Certification** 

CYBT-343026-01 is licensed to meet the regulatory requirements of Innovation, Science, and Economic Development Canada (ISED), License: IC: 7922A-3026 

Manufacturers of mobile, fixed, or portable devices incorporating this module are advised to clarify any regulatory questions and ensure compliance for SAR and/or RF exposure limits. Users can obtain Canadian information on RF exposure and compliance from www.ic.gc.ca. 

This device has been designed to operate with the antennas listed in Table 6 on page 13, having a maximum gain of –0.5 dBi. Antennas not included in this list or having a gain greater than –0.5 dBi are strictly prohibited for use with this device. The required antenna impedance is 50 ohms. The antenna used for this transmitter must not be co-located or operating in conjunction with any other antenna or transmitter. 

## ISED NOTICE: 

The device CYBT-343026-01 including the built-in trace antenna complies with Canada RSS-GEN Rules. The device meets the requirements for modular transmitter approval as detailed in RSS-GEN. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation. 

L'appareil CYBT-343026-01, y compris l'antenne intégrée, est conforme aux Règles RSS-GEN de Canada. L'appareil répond aux exigences d'approbation de l'émetteur modulaire tel que décrit dans RSS-GEN. L'opération est soumise aux deux conditions suivantes: (1) Cet appareil ne doit pas causer d'interférences nuisibles, et (2) Cet appareil doit accepter toute interférence reçue, y compris les interférences pouvant entraîner un fonctionnement indésirable. 

## ISED INTERFERENCE STATEMENT FOR CANADA 

This device complies with Innovation, Science and Economic Development (ISED) Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device. 

Cet appareil est conforme à la norme sur l'innovation, la science et le développement économique (ISED) norme RSS exempte de licence. L'exploitation est autorisée aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement. 

## ISED RADIATION EXPOSURE STATEMENT FOR CANADA 

This equipment complies with ISED radiation exposure limits set forth for an uncontrolled environment. This equipment should be 

installed and operated with a minimum distance of 10 mm between the radiator and your body. 

Cet équipement est conforme aux limites d'exposition aux radiations ISED prévues pour un environnement incontrôlé. Cet équipement doit être installé et utilisé avec un minimum de 10 mm de distance entre la source de rayonnement et votre corps. 

## LABELING REQUIREMENTS: 

The Original Equipment Manufacturer (OEM) must ensure that ISED labelling requirements are met. This includes a clearly visible label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor IC identifier for this product as well as the ISED Notices above. The IC identifier is 7922A-3026. In any case, the end product must be labeled in its exterior with "Contains IC: 7922A-3026" 

Page 43 of 52 

Document Number: 002-19525 Rev. *B 

**CYBT-343026-01** 

## **European Declaration of Conformity** 

Hereby, Cypress Semiconductor declares that the Bluetooth module CYBT-343026-01 complies with the essential requirements and other relevant provisions of Directive 2014. As a result of the conformity assessment procedure described in Annex III of the Directive 2014, the end-customer equipment should be labeled as follows: 

All versions of the CYBT-343026-01 in the specified reference design can be used in the following countries: Austria, Belgium, Cyprus, Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, Poland, Portugal, Slovakia, Slovenia, Spain, Sweden, The Netherlands, the United Kingdom, Switzerland, and Norway. 

## **MIC Japan** 

CYBT-343026-01 is certified as a module with certification number 203-JN0721. End products that integrate CYBT-343026-01 do not need additional MIC Japan certification for the end product. 

End product can display the certification label of the embedded module. 

**Figure 23.  MIC Label** 

Page 44 of 52 

Document Number: 002-19525 Rev. *B 

**CYBT-343026-01** 

## **Packaging** 

**Table 27.  Solder Reflow Peak Temperature** 

|**Module Part Number**|**Package**|**Maximum Peak Temperature**|**Maximum Peak Temperature**|**Maximum Time at Peak Temperature**|**Maximum Time at Peak Temperature**|**No. of Cycles**|
|---|---|---|---|---|---|---|
|CYBT-343026-01|24-pad SMT||260 °C||30 seconds|2|
|**Table 28.  Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2**||**Table 28.  Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2**|||||
|**Module Part Number**|||**Package**||**MSL**||
|CYBT-343026-01|||24-pad SMT||MSL 3||



**Table 28.  Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2** 

The CYBT-343026-01 is offered in tape and reel packaging. Figure 24 details the tape dimensions used for the CYBT-343026-01. 

**Figure 24.  CYBT-343026-01 Tape Dimensions** 

Figure 25 details the orientation of the CYBT-343026-01 in the tape as well as the direction for unreeling. 

**Figure 25.  Component Orientation in Tape and Unreeling Direction** 

Page 45 of 52 

Document Number: 002-19525 Rev. *B 

**CYBT-343026-01** 

Figure 26 details reel dimensions used for the CYBT-343026-01. 

**Figure 26.  Reel Dimensions** 

The CYBT-343026-01 is designed to be used with pick-and-place equipment in an SMT manufacturing environment. The center-of-mass for the CYBT-343026-01 is detailed in Figure 27. 

**Figure 27.  CYBT-343026-01 Center of Mass** 

Page 46 of 52 

Document Number: 002-19525 Rev. *B 

**CYBT-343026-01** 

## **Ordering Information** 

Table 29 lists the CYBT-343026-01 part number and features. Table 30 lists the reel shipment quantities for the CYBT-343026-01. 

## **Table 29.  Ordering Information** 

|**Part Number**|**CPU**<br>**Speed**<br>**(MHz)**|**Flash**<br>**Size (KB)**|**RAM**<br>**Size (KB)**|**UART**|**I2C**<br>**(BSC)**|**PWM**|**Package**|**Packaging**|
|---|---|---|---|---|---|---|---|---|
|CYBT-343026-01|24|512|352|Yes|Yes|4|24-SMT|Tape and Reel|



**Table 30.  Tape and Reel Package Quantity and Minimum Order Amount** 

|**Description**|**Minimum Reel Quantity**|**Maximum Reel Quantity**|**Comments**|
|---|---|---|---|
|Reel Quantity|500|500|Ships in 500 unit reel quantities.|
|Minimum Order Quantity (MOQ)|500|–|–|
|Order Increment (OI)|500|–|–|



The CYBT-343026-01 is offered in tape and reel packaging. The CYBT-343026-01 ships in a reel size of 500. 

For additional information and a complete list of Cypress Semiconductor Wireless products, contact your local Cypress sales representative. To locate the nearest Cypress office, visit our website. 

|U.S. Cypress Headquarters Address|198 Champion Court, San Jose, CA 95134|
|---|---|
|U.S. Cypress Headquarter Contact Info|(408) 943-2600|
|Cypress website address|http://www.cypress.com|



Page 47 of 52 

Document Number: 002-19525 Rev. *B 

**CYBT-343026-01** 

## **Acronyms** 

**Table 31.  Acronyms Used in this Document** 

|**Acronym**<br>~~a~~|**Description**<br>~~a~~|**Acronym**<br>~~a~~|**Description**<br>~~a~~|
|---|---|---|---|
|ADC<br>~~a~~|analog-to-digital converter<br>~~a~~|IDE<br>~~a~~|integrated development environment<br>~~a~~|
|ALU<br>~~a~~|arithmetic logic unit<br>~~a~~|I2C, or IIC<br>~~a~~|Inter-Integrated Circuit, a communications<br>protocol<br>~~a~~|
|AMUXBUS<br>~~a~~<br>~~a~~|analog multiplexer bus<br>~~a~~<br>~~a~~|IC<br>~~a~~<br>~~a~~|Industry Canada<br>~~a~~<br>~~a~~|
|API<br>~~a~~|application programming interface<br>~~a~~|IIR<br>~~a~~|infinite impulse response, see also FIR<br>~~a~~|
|ARM®<br>~~a~~<br>~~a~~|advanced RISC machine, a CPU architecture<br>~~a~~<br>~~a~~|ILO<br>~~a~~<br>~~a~~|internal low-speed oscillator, see also IMO<br>~~a~~<br>~~a~~|
|BLE<br>~~a~~|Bluetooth Low Energy<br>~~a~~<br>~~es~~|IMO<br>~~a~~|internal main oscillator, see also ILO<br>~~a~~|
|Bluetooth<br>SIG<br>~~a~~<br>~~a~~|Bluetooth Special Interest Group<br>~~a~~<br>~~a~~<br>~~es~~|INL<br>~~a~~<br>~~a~~|integral nonlinearity, see also DNL<br>~~a~~<br>~~a~~|
|BW<br>~~a~~<br>~~a~~|bandwidth<br>~~a~~<br>~~es~~<br>~~a~~|I/O<br>~~a~~<br>~~a~~|input/output, see also GPIO, DIO, SIO, USBIO<br>~~a~~<br>~~a~~|
|CAN<br>~~a~~|Controller Area Network, a communications<br>protocol<br>~~a~~|IPOR<br>~~a~~|initial power-on reset<br>~~a~~|
|CE<br>~~a~~|European Conformity<br>~~a~~|IPSR<br>~~a~~|interrupt program status register<br>~~a~~|
|CSA<br>~~a~~|Canadian Standards Association<br>~~a~~|IRQ<br>~~a~~|interrupt request<br>~~a~~|
|CMRR<br>~~a~~|common-mode rejection ratio<br>~~a~~|ITM<br>~~a~~|instrumentation trace macrocell<br>~~a~~|
|CPU<br>~~a~~|central processing unit<br>~~a~~|KC<br>~~a~~|Korea Certification<br>~~a~~|
|CRC<br>~~a~~|cyclic redundancy check, an error-checking<br>protocol<br>~~a~~<br>~~es~~|LCD<br>~~a~~|liquid crystal display<br>~~a~~|
|ECC<br>~~a~~<br>~~a~~|error correcting code<br>~~a~~<br>~~a~~<br>~~es~~|LIN<br>~~a~~<br>~~a~~|Local Interconnect Network, a communica-<br>tions protocol.<br>~~a~~<br>~~a~~|
|ECO<br>~~a~~<br>~~a~~|external crystal oscillator<br>~~a~~<br>~~es~~<br>~~a~~|LNA<br>~~a~~<br>~~a~~|low noise amplifier<br>~~a~~<br>~~a~~|
|EEPROM<br>~~a~~|electrically erasable programmable read-only<br>memory<br>~~a~~|LR<br>~~a~~|link register<br>~~a~~|
|EMI<br>~~a~~|electromagnetic interference<br>~~a~~|LUT<br>~~a~~|lookup table<br>~~a~~|
|EMIF<br>~~a~~|external memory interface<br>~~a~~|LVD<br>~~a~~|low-voltage detect, see also LVI<br>~~a~~|
|EOC<br>~~a~~|end of conversion<br>~~a~~|LVI<br>~~a~~|low-voltage interrupt, see also HVI<br>~~a~~|
|EOF<br>~~a~~|end of frame<br>~~a~~|LVTTL<br>~~a~~|low-voltage transistor-transistor logic<br>~~a~~|
|ESD<br>~~a~~|electrostatic discharge<br>~~a~~|MAC<br>~~a~~|multiply-accumulate<br>~~a~~|
|FCC<br>~~a~~<br>~~a~~|Federal Communications Commission<br>~~a~~<br>~~a~~|MCU<br>~~a~~<br>~~a~~|microcontroller unit<br>~~a~~<br>~~a~~|
|FET<br>~~a~~|field-effect transistor<br>~~a~~|MIC<br>~~a~~|Ministry of Internal Affairs and Communica-<br>tions (Japan)<br>~~a~~|
|FIR<br>~~a~~<br>~~a~~|finite impulse response, see also IIR<br>~~a~~<br>~~a~~|MISO<br>~~a~~<br>~~a~~|master-in slave-out<br>~~a~~<br>~~a~~|
|FPB<br>~~a~~|flash patch and breakpoint<br>~~a~~|NC<br>~~a~~|no connect<br>~~a~~|
|FS<br>~~a~~<br>~~a~~|full-speed<br>~~a~~<br>~~a~~|NMI<br>~~a~~<br>~~a~~|nonmaskable interrupt<br>~~a~~<br>~~a~~|
|GPIO<br>~~a~~|general-purpose input/output, applies to a PSoC<br>pin<br>~~a~~|NRZ<br>~~a~~|non-return-to-zero<br>~~a~~|
|HCI<br>~~a~~|host controller interface<br>~~a~~|NVIC<br>~~a~~|nested vectored interrupt controller<br>~~a~~|
|HVI<br>~~a~~|high-voltage interrupt, see also LVI, LVD<br>~~a~~|NVL<br>~~a~~|nonvolatile latch, see also WOL<br>~~a~~|
|IC<br>~~a~~|integrated circuit<br>~~a~~|Opamp<br>~~a~~|operational amplifier<br>~~a~~|
|IDAC<br>~~a~~|current DAC, see also DAC, VDAC<br>~~a~~|PA<br>~~a~~|power amplifier<br>~~a~~|



Page 48 of 52 

Document Number: 002-19525 Rev. *B 

**CYBT-343026-01** 

**Table 31.  Acronyms Used in this Document** (continued) 

|**Acronym**<br>~~a~~|**Description**|**Acronym**<br>~~a~~|**Description**<br>~~a~~|
|---|---|---|---|
|PAL<br>~~ee~~|programmable array logic, see also PLD<br>~~ee~~|SOF<br>~~ee~~|start of frame<br>~~ee~~|
|PC<br>~~ee~~|program counter<br>~~ee~~|S/H<br>~~ee~~|sample and hold<br>~~ee~~|
|PCB|printed circuit board|SINAD|signal to noise and distortion ratio|
|PGA|programmable gain amplifier<br>~~ee~~|SIO<br>~~a~~|special input/output, GPIO with advanced<br>features. See GPIO.|
|PHUB<br>~~ee~~|peripheral hub<br>~~ee~~<br>~~ee~~|SMT<br>~~a~~<br>~~ee~~|surface-mount technology; a method for<br>producing electronic circuitry in which the<br>components are placed directly onto the<br>surface of PCBs<br>~~ee~~|
|PHY<br>~~ee~~<br>~~es~~|physical layer<br>~~ee~~<br>|SPI<br>~~a~~<br>|Serial Peripheral Interface, a communications<br>protocol<br>|
|PICU<br>~~es~~|port interrupt control unit<br>|SR<br>|slew rate<br>|
|PLA<br>~~es~~|programmable logic array<br>|SRAM<br>|static random access memory<br>|
|PLD<br>~~esa~~|programmable logic device, see also PAL<br>~~a~~|SRES<br>~~a~~<br>~~a~~|software reset<br>~~a~~<br>~~a~~|
|PLL<br>~~a~~|phase-locked loop<br>~~a~~|STN<br>~~a~~|super twisted nematic<br>~~a~~|
|PMDD<br>~~a~~|package material declaration data sheet<br>~~a~~|SWD<br>~~a~~|serial wire debug, a test protocol<br>~~a~~|
|POR<br>~~a~~|power-on reset<br>~~a~~|SWV<br>~~a~~|single-wire viewer<br>~~a~~|
|PRES<br>~~a~~|precise power-on reset<br>~~a~~|TD<br>~~a~~<br>~~a~~|transaction descriptor, see also DMA<br>~~a~~<br>~~a~~|
|PRS<br>~~ee~~|pseudo random sequence<br>~~ee~~|THD<br>~~ee~~|total harmonic distortion<br>~~ee~~|
|PS<br>~~ee~~|port read data register<br>~~ee~~|TIA<br>~~ee~~|transimpedance amplifier<br>~~ee~~|
|PSoC®<br>~~a~~|Programmable System-on-Chip™|TN|twisted nematic|
|PSRR<br>~~a~~|power supply rejection ratio|TRM<br>~~a~~|technical reference manual<br>~~a~~|
|PWM<br>~~a~~|pulse-width modulator<br>|TTL<br>|transistor-transistor logic<br>|
|QDID<br>~~SE~~|qualification design ID<br>~~SE~~|TUV<br>~~SE~~|Germany: Technischer Überwachungs-Verein<br>(Technical Inspection Association)<br>~~SE~~|
|RAM<br>~~SE~~|random-access memory<br>~~SE~~|TX<br>~~SE~~<br>~~ee~~|transmit<br>~~SE~~<br>~~—~~<br>~~eee~~|
|RISC<br>~~Se~~|reduced-instruction-set computing<br>~~Se~~|UART<br>~~Se~~<br>~~ee~~|Universal Asynchronous Transmitter<br>Receiver, a communications protocol<br>~~Se~~<br>~~eee~~|
|RMS<br>~~Se~~|root-mean-square<br>~~Se~~|UDB<br>~~Se~~<br>~~ee~~<br>~~a~~|universal digital block<br>~~Se~~<br>~~eee~~<br>~~a~~|
|RTC<br>~~Se~~<br>~~a~~|real-time clock<br>~~Se~~<br>~~a~~|USB<br>~~Se~~<br>~~ee ~~<br>~~a~~<br>~~a~~|Universal Serial Bus<br>~~Se~~<br> ~~eee~~<br>~~a~~<br>~~a~~|
|RTL<br>~~EE~~|register transfer language<br>~~EE~~|USBIO<br>~~EE~~|USB input/output, PSoC pins used to connect<br>to a USB port<br>~~EE~~|
|RTR<br>~~EE~~|remote transmission request<br>~~EE~~|VDAC<br>~~EE~~|voltage DAC, see also DAC, IDAC<br>~~EE~~|
|RX<br>~~EE~~<br>~~a~~|receive<br>~~EE~~|WDT<br>~~EE~~|watchdog timer<br>~~EE~~|
|SAR<br>~~a~~|successive approximation register|WOL<br>~~a~~|write once latch, see also NVL<br>~~a~~|
|SC/CT<br>~~a~~<br>~~a~~|switched capacitor/continuous time<br>~~a~~|WRES<br>~~a~~<br>~~a~~|watchdog timer reset<br>~~a~~<br>~~a~~|
|SCL<br>~~a~~|I2C serial clock<br>~~a~~|XRES<br>~~a~~|external reset I/O pin<br>~~a~~|
|SDA<br>~~a~~|I2C serial data<br>~~a~~|XTAL<br>~~a~~|crystal<br>~~a~~|
|SOC<br>~~a~~|start of conversion<br>~~a~~|~~a~~||



Page 49 of 52 

Document Number: 002-19525 Rev. *B 

**CYBT-343026-01** 

## **Document Conventions** 

## **Units of Measure** 

## **Table 32.  Units of Measure** 

|**Symbol**<br>~~ee~~|**Unit of Measure**|
|---|---|
|°C<br>~~ee~~<br>~~a~~|degrees Celsius|
|dB<br>~~a~~<br>~~a~~|decibel|
|dBm<br>~~a~~|decibel-milliwatts|
|fF<br>~~a~~<br>~~a~~|femtofarads|
|Hz<br>~~a~~|hertz|
|KB<br>~~a~~<br>~~a~~|1024 bytes|
|kbps<br>~~a~~|kilobits per second|
|Khr<br>~~a~~<br>~~a~~|kilohour|
|kHz<br>~~a~~|kilohertz|
|k<br>~~a~~<br>~~a~~|kilo ohm|
|ksps<br>~~a~~|kilosamples per second|
|LSB<br>~~a~~<br>~~a~~|least significant bit|
|Mbps<br>~~a~~|megabits per second|
|MHz<br>~~a~~<br>~~a~~|megahertz|
|M<br>~~a~~|mega-ohm|
|Msps<br>~~a~~<br>~~a~~|megasamples per second|
|µA<br>~~a~~|microampere|
|µF<br>~~a~~<br>~~a~~|microfarad|
|µH<br>~~a~~|microhenry|
|µs<br>~~a~~<br>~~a~~|microsecond|
|µV<br>~~a~~|microvolt|
|µW<br>~~a~~<br>~~a~~|microwatt|
|mA<br>~~a~~|milliampere|
|ms<br>~~a~~<br>~~a~~|millisecond|
|mV<br>~~a~~|millivolt|
|nA<br>~~a~~<br>~~a~~|nanoampere|
|ns<br>~~a~~|nanosecond|
|nV<br>~~a~~<br>~~a~~|nanovolt|
|<br>~~a~~|ohm|
|pF<br>~~a~~<br>~~a~~|picofarad|
|ppm<br>~~a~~|parts per million|
|ps<br>~~a~~<br>~~a~~|picosecond|
|s<br>~~a~~|second|
|sps<br>~~a~~<br>~~a~~<br>~~ee~~|samples per second|
|sqrtHz<br>~~ee~~|square root of hertz|
|V<br>~~ee~~<br>~~a~~|volt|



Page 50 of 52 

Document Number: 002-19525 Rev. *B 

**CYBT-343026-01** 

## **Document History Page** 

## **Document Title: CYBT-343026-01 EZ-BT™ WICED[®] Module Document Number: 002-19525** 

|**Document Title: CYBT-343026-01 EZ-BT™ WICED[®] Module**<br>**Document Number: 002-19525**|**Document Title: CYBT-343026-01 EZ-BT™ WICED[®] Module**<br>**Document Number: 002-19525**|**Document Title: CYBT-343026-01 EZ-BT™ WICED[®] Module**<br>**Document Number: 002-19525**|**Document Title: CYBT-343026-01 EZ-BT™ WICED[®] Module**<br>**Document Number: 002-19525**|**Document Title: CYBT-343026-01 EZ-BT™ WICED[®] Module**<br>**Document Number: 002-19525**|
|---|---|---|---|---|
|**Revision**|**ECN**|**Orig. of**<br>**Change**|**Submission**<br>**Date**|**Description of Change**|
|**|5796061|MINS|07/03/2017|Preliminary datasheet for CYBT-343026-01 module.|
|*A|5866701|DSO|09/08/2017|Remove references to CYBT-143038-01 and associated specifications related to<br>this part number.<br>UpdatedMIC Japanlabel to indicate final certification number.|
|*B|6155763|DSO|04/26/2018|Changed status from "Preliminary" to "Final".<br>UpdatedModule Descriptionto specify Bluetooth QDID and Declaration ID.<br>UpdatedReferencesto add additional document references.<br>UpdatedDevelopment Environmentsto remove EZ-Serial reference.<br>UpdatedTable 4to display silicon Port-Pin name instead of only Pin identifier.<br>Added Footnote 5 toTable 4to state that any GPIO can be used for SPI1_CS in<br>master mode.<br>UpdatedFigure 9to improve image quality.<br>UpdatedBluetooth Baseband Coreto improve readability.<br>Renamed Peripheral Transport Unit toPeripheral and Communication Interfaces<br>UpdatedTable 9.<br>UpdatedTable 13to specify current consumption of silicon and module solutions.<br>UpdatedChipset RF Specificationsto specify as Chipset.<br>UpdatedTable 21,Table 22,Table 23, andTable 24to specify PCM interface<br>timing.<br>AddedFigure 21andFigure 22.<br>UpdatedFigure 23to improve image quality.<br>UpdatedFigure 24to add tape drawing.<br>UpdatedFigure 25to add Component Orientation reference drawing.<br>UpdatedFigure 26to add Reel Dimension drawing.<br>UpdatedFigure 27to add Center of Mass drawing.<br>UpdatedTable 30to specify Reel Quantity, MOQ, and OI|



Page 51 of 52 

Document Number: 002-19525 Rev. *B 

**CYBT-343026-01** 

## **Sales, Solutions, and Legal Information** 

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© Cypress Semiconductor Corporation, 2017-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress").  This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide.  Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights.  If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products.  Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. 

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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. 

Page 52 of 52 

Document Number: 002-19525 Rev. *B 

Revised April 26, 2018
Updated at April 28, 2026
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