Image not available
Illustrative purposes only
CYBLE-416045-02
Bluetooth 5.0 Module, 1.71V to 3.6V Supply, 2Mbps, -89dBm Sensitivity
⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
- Manufacturer: INFINEON
- Product type: Bluetooth Modules & Adaptors
- Bluetooth Version:Bluetooth 5.0; Supply Voltage Min:1.71V; Supply Voltage Max:3.6V; Signal Range Max:-; Data Rate:2Mbps; Bluetooth Class:-; Receive Sensitivity:-89dBm; Operating Temper
- SVHC: No SVHC (25-Jun-2025)
- Interfaces: I2C, SPI, UART
- Product Range: EZ-BLE Series
- Certifications: CE, FCC, ISED, MIC
- Bluetooth Class: -
- Bluetooth Version: Bluetooth 5.0
- Supply Voltage Range: 1.71 V to 3.6 V
- Receiver Sensitivity Rx: -89 dBm
- Operating Temperature Range: -40 °C to 85 °C
| Delivery and price | |
|---|---|
| Units per pack | 250 |
| Price | 8.6 € |
| Current stock | 500+ |
| Lead time | 30 days |
Datasheet
**CYBLE-416045-02**
EZ-BLE™ Creator Module
## **General Description**
The Cypress CYBLE-416045-02 is a fully certified and qualified module supporting Bluetooth[] Low Energy (BLE) wireless communication. The CYBLE-416045-02 is a turnkey solution and includes onboard crystal oscillators, trace antenna, passive components, and the Cypress PSoC[®] 63 BLE silicon device. Refer to the PSoC 63 BLE datasheet for additional details on the capabilities of the PSoC 63 BLE device used on this module.
The EZ-BLE™ Creator module is a scalable and reconfigurable platform architecture. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. The CYBLE-416045-02 also includes digital programmable logic, high-performance analog-to-digital conversion (ADC), low-power comparators, and standard communication and timing peripherals.
The CYBLE-416045-02 includes a royalty-free BLE stack compatible with Bluetooth 5.0 and provides up to 36 GPIOs in a 14 × 18.5 × 2.00 mm package.
The CYBLE-416045-02 is a complete solution and an ideal fit for applications seeking a high-performance BLE wireless solution.
## **Module Description**
- Module size: 14.0 mm × 18.5 mm × 2.00 mm (with shield)
- 1 MB Application Flash with 32-KB EEPROM area and 32-KB Secure Flash
- 288-KB SRAM with Selectable Retention Granularity
- Up to 36 GPIOs with programmable drive modes, strengths, and slew rates
- Bluetooth 5.0 qualified single-mode module
- ❐ QDID: D040144
- ❐ Declaration ID:112778
- Certified to FCC, CE, MIC, and ISED regulations
- Industrial temperature range: –40 °C to +85 °C
- 150-MHz Arm[®] Cortex[®] -M4F CPU with single-cycle multiply (Floating Point Unit (FPU) and Memory Protection Unit (MPU))
- 100-MHz Cortex-M0+ CPU with single-cycle multiply and MPU
- OTP eFuse memory for validation and security
## **Power Consumption**
- TX output power: –20 dbm to +4 dbm
- Received signal strength indication (RSSI) with 4-dB resolution
- TX current consumption of 5.7 mA (radio only, 0 dbm)
- RX current consumption of 6.7 mA (radio only)
## **Low-Power 1.71 V to 3.6 V Operation**
- Active, Low-power Active, Sleep, Low-power Sleep, Deep Sleep, and Hibernate modes for fine-grained power management
- Deep Sleep mode current with 64K SRAM retention is 7 µA with 3.3-V external supply and internal buck
- On-chip Single-In Multiple Out (SIMO) DC-DC Buck converter, less than 1 µA quiescent current
- Backup domain with 64 bytes of memory and Real-Time-Clock (RTC) programmable analog
## **Serial Communication**
- Five independent runtime reconfigurable serial communication blocks (SCBs), each is software configurable as I[2] C, SPI, or UART
## **Timing and Pulse-Width Modulation (TCPWM)**
- Thirty-two TCPWM blocks
- Center-aligned, Edge, and Pseudo-random modes
- Comparator-based triggering of Kill signals
## **Up to 36 Programmable GPIOs**
- Any GPIO pin can be CapSense[®] , analog/digital
## **Audio Subsystem**
- I[2] S interface; up to 192 kilosamples (ksps) word clock
- Two pulse-density modulation (PDM) channels for stereo digital microphones
## **Programmable Analog**
- 12-bit 1 Msps SAR ADC with differential and single-ended modes and Sequencer with signal averaging
- One 12-bit voltage mode DAC with less than 5 µs settling time
- Two opamps with low-power operation modes
- Two low-power comparators that operate in Deep Sleep and Hibernate modes
- Built-in temperature sensor connected to ADC
## **Programmable Digital**
- 12 programmable logic blocks, each with eight macrocells and an 8-bit data path (called universal digital blocks or UDBs)
- Usable as drag-and-drop Boolean primitives (gates, registers), or as Verilog programmable blocks
- Cypress-provided peripheral component library using UDBs to implement functions such as communication peripherals (for example, LIN, UART, SPI, I[2] C, S/PDIF and other protocols), waveform generators, pseudo-random sequence (PRS) generation, and other functions.
- Smart I/O (Programmable I/O) blocks enable Boolean operations on signals coming from, and going to, GPIO pins
**Cypress Semiconductor Corporation** • 198 Champion Court Document Number: 002-24085 Rev. *A
• San Jose, CA 95134-1709 • 408-943-2600 Revised February 21, 2019
**CYBLE-416045-02**
- Two ports with Smart I/O block capability are provided and are available during Deep Sleep
## **Capacitive Sensing**
- Cypress Capacitive Sigma-Delta (CSD) provides best-in-class SNR, liquid tolerance, and proximity sensing
- Mutual capacitance sensing (Cypress CSX) with dynamic usage of both self and mutual sensing
- Wake-on-Touch (WOT) with very low current
- Cypress-supplied software component makes capacitive sensing design fast and easy
- Automatic hardware tuning (SmartSense)
## **Energy Profiler**
- Authentication during boot using hardware hashing
- Step-wise authentication of execution images
- Secure execution of code in execute only mode for protected routines
- All debug and test ingress paths can be disabled
## **Cryptography Accelerators**
- Hardware acceleration for Symmetric and Asymmetric Cryptographic methods (AES, 3DES, RSA, and ECC) and Hash functions (SHA-512, SHA-256)
- True Random Number Generator (TRNG) function
- Block that provides history of time spent in different power modes
- Software energy profiling to observe and optimize energy consumption
## **Security Built into Platform Architecture**
- Multi-faceted secure architecture based on ROM-based root of trust
- Secure boot uninterruptible until system protection attributes are established
Document Number: 002-24085 Rev. *A
Page 2 of 59
**CYBLE-416045-02**
## **More Information**
Cypress provides a wealth of data at www.cypress.com to help you to select the right module for your design, and to help you to quickly and effectively integrate the module into your design.
- Overview: Module Roadmap
- PSoC 63 BLE Silicon Datasheet
- Application Notes:
- ❐ AN96841 - Getting Started with EZ-BLE Module
- ❐ AN210781 - Getting Started with PSoC 6 MCU BLE
- ❐ AN215656 - PSoC 6 MCU Dual-CPU System Design
- ❐ AN91162 - Creating a BLE Custom Profile
- ❐ AN217666 - PSoC 6 MCU Interrupts
- ❐ AN91445 - Antenna Design and RF Layout Guidelines
- ❐ AN213924 - PSoC 6 MCU Bootloader Guide
- ❐ AN219528 - PSoC 6 MCU Power Reduction Techniques
- Technical Reference Manual (TRM):
- ❐ PSoC 63 with BLE Architecture Technical Reference Manual
- Knowledge Base Articles
- ❐ KBA97095 - EZ-BLE™ Module Placement
- ❐ KBA213976 - FAQ for BLE and Regulatory Certifications with EZ-BLE modules
- ❐ KBA210802 - Queries on BLE Qualification and Declaration Processes
- Development Kits:
- ❐ CYBLE-416045-EVAL, CYBLE-416045-02 Evaluation Board
- ❐ CY8CKIT-062-BLE, PSoC 63 BLE Pioneer Kit
- Test and Debug Tools:
- ❐ CYSmart, Bluetooth LE Test and Debug Tool (Windows)
- ❐ CYSmart Mobile, Bluetooth LE Test and Debug Tool (Android/iOS Mobile App)
- ❐ PSoC 63 with BLE Registers Technical Reference Manual
## **PSoC Creator™ Integrated Design Environment (IDE)**
PSoC Creator is a free Windows-based Integrated Design Environment (IDE). It enables you to design hardware and firmware systems concurrently, based on PSoC 6 MCU. As shown below, with PSoC Creator, you can:
1. Explore the library of 200+ Components in PSoC Creator
2. Drag and drop Component icons to complete your hardware system design in the main design workspace
3. Configure Components using the Component Configuration Tools and the Component Datasheets
4. Co-design your application firmware and hardware in the PSoC Creator IDE or build project for 3rd party IDE
5. Prototype your solution with the CYBLE-416045-02 Evaluation Kit. If a design change is needed, PSoC Creator and Components enable you to make changes on the fly without the need for hardware revisions
**Figure 1. PSoC Creator Schematic Entry and Components**
Document Number: 002-24085 Rev. *A
Page 3 of 59
**CYBLE-416045-02**
## **Contents**
**Functional Definition ........................................................5** CPU and Memory Subsystem .....................................5 System Resources ......................................................5 BLE Radio and Subsystem .........................................6 Analog Blocks ..............................................................6 Programmable Digital ..................................................7 Fixed-Function Digital ..................................................7 GPIO ...........................................................................8 Special-Function Peripherals ......................................8 **Module Overview ..............................................................9** Module Description ......................................................9 **Pad Connection Interface ..............................................11 Recommended Host PCB Layout .................................12 Digital and Analog Capabilities and Connections .......14 Power ...............................................................................18** 32-kHz Crystal Oscillator ...........................................19 Critical Components List ...........................................21 Antenna Design .........................................................21 **Electrical Specification ..................................................22** Device-Level Specifications ......................................22 Analog Peripherals ....................................................28 Digital Peripherals .....................................................37 Memory .....................................................................39 System Resources ....................................................40
**Environmental Specifications .......................................48** Environmental Compliance .......................................48 RF Certification ..........................................................48 Environmental Conditions .........................................48 ESD and EMI Protection ...........................................48 **Regulatory Information ..................................................49** FCC ...........................................................................49 ISED ..........................................................................50 European Declaration of Conformity .........................51 MIC Japan .................................................................51 **Packaging ........................................................................52 Ordering Information ......................................................54** Part Numbering Convention ......................................54 **Acronyms ........................................................................55 Document Conventions .................................................57** Unit of Measure .........................................................57 **Document History Page .................................................58 Sales, Solutions, and Legal Information ......................59** Worldwide Sales and Design Support .......................59 Products ....................................................................59 PSoC® Solutions ......................................................59 Cypress Developer Community .................................59 Technical Support .....................................................59
Document Number: 002-24085 Rev. *A
Page 4 of 59
**CYBLE-416045-02**
## **Functional Definition**
## **CPU and Memory Subsystem**
## _CPU_
The CPU subsystem in the CYBLE-416045-02 consists of two Arm Cortex cores and their associated buses and memories: M4 with FPU and MPU, and M0+ with an MPU. The M4 and M0+ cores have 8-KB instruction caches (I-Cache) with a four-way set associativity. This subsystem also includes independent DMA controllers with 32 channels each, a cryptographic accelerator block, 1 MB of on-chip Flash, 288 KB of SRAM, and 128 KB of ROM.
The Cortex-M0+ provides a secure, uninterruptible boot function. This guarantees that post-boot, system integrity is checked and privileges enforced. Shared resources can be accessed through the normal Arm multilayer bus arbitration and exclusive accesses are supported by an Inter-Processor Communication (IPC) scheme, which implements hardware semaphores and protection. Active power consumption for the Cortex-M4 is 22 µA/MHz and 15 µA/MHz for the Cortex-M0+, both at 3.3-V supply voltage with the internal buck enabled and at 0.9 V internal supply. Note that at Cortex-M4 speeds above 100 MHz, the M0+ and Peripheral subsystem are limited to half the M4 speed. If the M4 is running at 150 MHz, the M0+ and peripheral subsystem is limited to 75 MHz.
## _DMA Controllers_
There are two DMA controllers with 16 channels each. They support independent accesses to peripherals using the AHB multilayer bus.
## _Flash_
CYBLE-416045-02 has 1 MB of flash with additional 32K of flash that can be used for EEPROM emulation for longer retention and a separate 32 KB block of flash that can be securely locked and is only accessible via a key lock that cannot be changed (OTP).
## _SRAM with 32-KB Retention Granularity_
There is 288 KB of SRAM memory, which can be fully retained or retained in increments of user-designated 32-KB blocks.
## **System Resources**
## _Power System_
The power system provides assurance that voltage levels are as required for each respective mode and will either delay mode entry (for example, on power-on reset (POR)) until voltage levels are as required for proper function or generate resets (brownout detect (BOD)) when the power supply drops below specified levels. The design will guarantee safe chip operation between power supply voltage dropping below specified levels (for example, below 1.71 V) and the reset occurring. There are no voltage sequencing requirements. The VDD core logic supply (1.71 to 3.6 V) will feed an on-chip buck, which will produce the core logic supply of either 1.1 V or 0.9 V selectable. Depending on the frequency of operation, the buck converter will have a quiescent current of <1 µA. A separate power domain called Backup is provided; note this is not a power mode. This domain is powered from the VBACKUP domain and includes the 32-kHz watch crystal oscillator (WCO), RTC, and backup registers. It is connected to VDD when not used as a backup domain. Port 0 is powered from this supply. Pin 5 of Port 0 (P0.5) can be assigned as a PMIC wakeup output (timed by the RTC); P0.5 is driven to the resistive pull-up mode by default.
## _Clock System_
The CYBLE-416045-02 clock system is responsible for providing clocks to all subsystems that require clocks and for switching between different clock sources without glitching. In addition, the clock system ensures that no metastable conditions occur.
The clock system for the CYBLE-416045-02 consists of the internal main oscillator (IMO) and internal low-speed oscillator (ILO), crystal oscillators: external crystal oscillator (ECO) and WCO, PLL, frequency-locked loop (FLL), and provision for an external clock. An FLL will provide fast wake-up at high clock speeds without waiting for a PLL lock event (which can take up to 50 µs). Clocks may be buffered and brought out to a pin on a Smart I/O port.
The 32-kHz oscillator is trimmable to within 2 ppm using a higher accuracy clock. The ECO will deliver ±20 ppm accuracy and will use an external crystal.
## _IMO Clock Source_
## _SROM_
There is a supervisory 128 KB ROM that contains boot and configuration routines. This ROM will guarantee Secure Boot if authentication of user flash is required.
## _OTP eFuse_
The 1024-bit OTP memory can provide a unique and unalterable Identifier on a per chip basis. This unalterable key can be used to access secured flash.
The IMO is the primary source of internal clocking in CYBLE-416045-02. It is trimmed during testing to achieve the specified accuracy. The IMO default frequency is 8 MHz. IMO tolerance is ±2% and its current consumption is less than 10 µA.
## _ILO Clock Source_
The ILO is a very low-power oscillator, nominally 32 kHz, which may be used to generate clocks for peripheral operation in Deep Sleep mode. ILO-driven counters can be calibrated to the IMO to improve accuracy. Cypress provides a software component, which does the calibration.
Document Number: 002-24085 Rev. *A
Page 5 of 59
**CYBLE-416045-02**
## _Watchdog Timer (WDT)_
A WDT is implemented in the clock block running from the ILO or from the WCO; this allows watchdog operation during Deep Sleep and Hibernate modes, and generates a watchdog reset if not serviced before the timeout occurs. The watchdog reset is recorded in the Reset Cause register.
## _Clock Dividers_
Integer and Fractional clock dividers are provided for peripheral use and timing purposes. There are eight 8-bit integer and sixteen 16-bit integer clock dividers. There is also one 24.5-bit fractional and four 16.5-bit fractional clock dividers.
## _Reset_
The CYBLE-416045-02 can be reset from a variety of sources including software reset. Reset events are asynchronous and guarantee reversion to a known state. The reset cause is recorded in a register, which is present through reset and allows software to determine the cause of the reset. An XRES pin is reserved for external reset to avoid complications with configuration and multiple pin functions during power-on or reconfiguration.
## **BLE Radio and Subsystem**
CYBLE-416045-02 incorporates a Bluetooth Smart subsystem that contains the PHY and Link Layer (LL) engines with an embedded security engine. The physical layer consists of the digital PHY and the RF transceiver that transmits and receives GFSK packets at 2 Mbps over a 2.4-GHz ISM band, which is compliant with Bluetooth Smart Bluetooth Specification 5.0. The baseband controller is a composite hardware and firmware implementation that supports both master and slave modes. Key protocol elements, such as Host controller Interface (HCI) and link control, are implemented in firmware. Time-critical functional blocks, such as encryption, CRC, data whitening, and access code correlation, are implemented in hardware (in the LL engine).
The RF transceiver contains an integrated balun, which provides a single-ended RF port pin to drive a 50 antenna via a matching/filtering network. In the receive direction, this block converts the RF signal from the antenna to a digital bit stream after performing GFSK demodulation. In the transmit direction, this block performs GFSK modulation and then converts a digital baseband signal to a radio frequency before transmitting it to air through the antenna.
Key features of BLESS are as follows:
- Master and Slave single-mode protocol stack with logical link control and adaptation protocol (L2CAP), attribute (ATT), and security manager (SM) protocols
- API access to generic attribute profile (GATT), generic access profile (GAP), and L2CAP
- L2CAP connection-oriented channel (Bluetooth 4.1 feature)
## ■ GAP features
- ❐ Broadcaster, Observer, Peripheral, and Central roles
- ❐ Security mode 1: Level 1, 2, and 3
- ❐ User-defined advertising data
- ❐ Multiple bond support
## ■ GATT features
- ❐ GATT client and server
- ❐ Supports GATT sub-procedures
- ❐ 32-bit universally unique identifier (UUID) (Bluetooth 4.1 feature)
## ■ Security Manager (SM)
- ❐ Pairing methods: Just works, Passkey Entry, and Out of Band
- ❐ LE Secure Connection Pairing model
- ❐ Authenticated man-in-the-middle (MITM) protection and data signing
## ■ LL
- ❐ Master and slave roles
- ❐ 128-bit AES engine
- ❐ Low-duty cycle advertising
- ❐ LE Ping
- Supports all SIG-adopted BLE profiles
- Power levels for advertisement (1.28s, 32 bytes, 0 dBm) and Connection (300 ms, 0 byte, 0 dBm) are 42 µW and 70 µW respectively
## **Analog Blocks**
## _12-bit SAR ADC_
The 12-bit, 1-Msps SAR ADC can operate at a maximum clock rate of 18 MHz and requires a minimum of 18 clocks at that frequency to do a 12-bit conversion.
The block functionality is augmented for the user by adding a reference buffer to it (trimmable to ±1%) and by providing the choice of three internal voltage references, VDD, VDD/2, and VREF (nominally 1.024 V), as well as an external reference through a GPIO pin. The sample and hold (S/H) aperture is programmable; it allows the gain bandwidth requirements of the amplifier driving the SAR inputs, which determine its settling time, to be relaxed if required. System performance will be 65 dB for true 12-bit precision provided appropriate references are used and system noise levels permit it. To improve the performance in noisy conditions, it is possible to provide an external bypass (through a fixed pin location) for the internal reference amplifier.
The SAR is connected to a fixed set of pins through an eight-input sequencer. The sequencer cycles through the selected channels autonomously (sequencer scan) and does so with zero switching overhead (that is, the aggregate sampling bandwidth is equal to 1 Msps whether it is for a single channel or distributed over several channels). The sequencer switching is effected through a state machine or through firmware-driven switching. A feature provided by the sequencer is the buffering of each channel to reduce CPU interrupt-service requirements. To accommodate signals with varying source impedances and frequencies, it is possible to have different sample times programmable for each channel. Also, the signal range specification through a pair of range registers (low- and high-range values) is implemented with a corresponding out-of-range interrupt if the digitized value exceeds the programmed range; this allows fast detection of out-of-range values without having to wait for a sequencer scan to be completed and the CPU to read the values and check for out-of-range values in software. There are sixteen channels of which any thirteen can be sampled in a single scan.
Document Number: 002-24085 Rev. *A
Page 6 of 59
**CYBLE-416045-02**
The SAR is able to digitize the output of the on-chip temperature sensor for calibration and other temperature-dependent functions. The SAR is not available in Deep Sleep and Hibernate modes as it requires a high-speed clock (up to 18 MHz). The SAR operating range is 1.71 V to 3.6 V.
## _Temperature Sensor_
Part Number has an on-chip temperature sensor. This consists of a diode, which is biased by a current source that can be disabled to save power. The temperature sensor is connected to the ADC, which digitizes the reading and produces a temperature value by using a Cypress-supplied software that includes calibration and linearization.
## _12-bit DAC_
There is a 12-bit voltage mode DAC on the chip, which can settle in less than 5 µs. The DAC may be driven by the DMA controllers to generate user-defined waveforms. The DAC output from the chip can either be the resistive ladder output (highly linear near ground) or a buffered output.
## _Continuous Time Block (CTB) with two Opamps_
This block consists of two opamps, which have their inputs and outputs connected to fixed pins and have three power modes and a comparator mode. The outputs of these opamps can be used as buffers for the SAR Inputs. The non-inverting inputs of these opamps can be connected to either of two pins, thus allowing independent sensors to be used at different times. The pin selection can be made via firmware. The opamps can be set to one of the four power levels; the lowest level allowing operation in Deep Sleep mode in order to preserve lower performance Continuous-Time functionality in Deep Sleep mode. The DAC output can be buffered through an opamp.
## _Low-Power Comparators_
CYBLE-416045-02 has a pair of low-power comparators, which can also operate in Deep Sleep and Hibernate modes. This allows the analog system blocks to be disabled while retaining the ability to monitor external voltage levels during Deep Sleep and Hibernate modes. The comparator outputs are normally synchronized to avoid metastability unless operating in an asynchronous power mode (Hibernate) where the system wakeup circuit is activated by a comparator-switch event.
One of the low-power comparators (lpcomp1) has dedicated connections to minimize the signal path. Lpcomp1 can also be routed to other I/Os via the analog mux bus, if needed.
The second low-power comparator (lpcomp0) has one dedicated connection exposed on the module (P5.6 – positive input); however, the negative input must be routed via the analog mux bus to an I/O.
## **Programmable Digital**
## _Smart I/O_
There are two Smart I/O blocks, which allow Boolean operations on signals going to the GPIO pins from the subsystems of the chip or on signals coming into the chip. Operation can be synchronous or asynchronous and the blocks operate in low-power modes, such as Deep Sleep and Hibernate.This allows, for example, detection of logic conditions that can indicate that the CPU should wakeup instead of waking up on
general I/O interrupts, which consume more power and can generate spurious wakeups.
## _Universal Digital Blocks (UDBs) and Port Interfaces_
The CYBLE-416045-02 has twelve UDBs; the UDB array also provides a switched Digital System Interconnect (DSI) fabric that allows signals from peripherals and ports to be routed to and through the UDBs for communication and control.
## **Fixed-Function Digital**
## _Timer/Counter/PWM Block_
The timer/counter/PWM block consists of thirty-two counters with user-programmable period length. There is a capture register to record the count value at the time of an event (which may be an I/O event), a period register which is used to either stop or auto-reload the counter when its count is equal to the period register, and compare registers to generate compare value signals which are used as PWM duty cycle outputs. The block also provides true and complementary outputs with programmable offset between them to allow the use as deadband programmable complementary PWM outputs. It also has a kill input to force outputs to a predetermined state; for example, this is used in motor-drive systems when an overcurrent state is indicated and the PWMs driving the FETs need to be shut off immediately with no time for software intervention. There are eight 32-bit counters and twenty-four 16-bit counters.
## _Serial Communication Blocks (SCB)_
CYBLE-416045-02 has five SCBs, which can each implement an I[2] C, UART, or SPI Interface. Two SCBs (SCB_6 and SCB_8) share the same pin connections and cannot be used at the same time. One of these SCBs (SCB_8) will operate in Deep Sleep with an external clock, this SCB will only operate in Slave mode (requires external clock).
**I[2] C Mode** : The hardware I[2] C block implements a full multimaster and Slave Interface (it is capable of multimaster arbitration). This block is capable of operating at speeds of up to 1 Mbps (Fast Mode plus) and has flexible buffering options to reduce the interrupt overhead and latency for the CPU. It also supports EZI[2] C that creates a mailbox address range in the memory of CYBLE-416045-02 and effectively reduces the I[2] C communication to reading from and writing to an array in the memory. In addition, the block supports a 256 byte-deep FIFO for receive and transmit, which, by increasing the time given for the CPU to read the data, greatly reduces the need for clock stretching caused by the CPU not having read the data on time. The FIFO mode is available in all channels and is very useful in the absence of DMA.
The I[2] C peripheral is compatible with I[2] C Standard-mode, Fast-mode, and Fast-Mode Plus devices as defined in the NXP I[2] C-bus specification and user manual (UM10204). The I[2] C bus I/O is implemented with GPIO in open-drain modes.
**UART Mode** : This is a full-feature UART operating at up to 8 Mbps. It supports automotive single-wire interface (LIN), infrared interface (IrDA), and SmartCard (ISO7816) protocols, all of which are minor variants of the basic UART protocol. In addition, it supports the 9-bit multiprocessor mode that allows the addressing of peripherals connected over common RX and TX lines. Common UART functions such as parity error, break
Document Number: 002-24085 Rev. *A
Page 7 of 59
**CYBLE-416045-02**
detect, and frame error are supported. A 256 byte-deep FIFO allows much greater CPU service latencies to be tolerated.
**SPI Mode** : The SPI mode supports full Motorola SPI, TI Secure Simple Pairing (SSP) (essentially adds a start pulse that is used to synchronize SPI codecs), and National Microwire (half-duplex form of SPI). The SPI block can use the FIFO and supports an EZSPI mode in which the data interchange is reduced to reading and writing an array in memory. The SPI Interface will operate with a 25-MHz SPI Clock.
## **GPIO**
CYBLE-416045-02 has up to thirty-six GPIOs. The GPIO block implements the following:
- Eight drive strength modes:
- ❐ Analog input mode (input and output buffers disabled)
- ❐ Input only
- ❐ Weak pull-up with strong pull-down
- ❐ Strong pull-up with weak pull-down
- ❐ Open drain with strong pull-down
- ❐ Open drain with strong pull-up
- ❐ Strong pull-up with strong pull-down
- ❐ Weak pull-up with weak pull-down
- Input threshold select (CMOS or LVTTL)
- Hold mode for latching previous state (used for retaining the I/O state in Deep Sleep and Hibernate modes)
- Selectable slew rates for dV-/dt-related noise control to improve EMI
The pins are organized in logical entities called ports, which are 8-bit in width. During power-on and reset, the blocks are forced to the disable state so as not to crowbar any inputs and/or cause excess turn-on current. A multiplexing network known as a high-speed I/O matrix (HSIOM) is used to multiplex between various signals that may connect to an I/O pin. Data output and pin state registers store, respectively, the values to be driven on the pins and the states of the pins themselves.
Every I/O pin can generate an interrupt if so enabled and each I/O port has an IRQ and ISR vector associated with it. Six GPIO pins are capable of over-voltage tolerant (OVT) operation where the input voltage may be higher than VDD (these may be used for I[2] C functionality to allow powering the chip off while maintaining physical connection to an operating I[2] C bus without affecting its functionality).
## **Special-Function Peripherals**
## _CapSense_
CapSense is supported on all pins in the CYBLE-416045-02 through a CapSense Sigma-Delta (CSD) block that can be connected to an analog multiplexed bus. Any GPIO pin can be connected to this AMUX bus through an analog switch. CapSense function can thus be provided on any pin or a group of pins in a system under software control. Cypress provides a software component for the CapSense block for ease-of-use.
Shield Voltage can be driven on another mux bus to provide water tolerance capability. Water tolerance is provided by driving the shield electrode in phase with the sense electrode to keep the shield capacitance from attenuating the sensed input. Proximity sensing can also be implemented.
The CapSense block is an advanced, low-noise, programmable block with programmable voltage references and current source ranges for improved sensitivity and flexibility. It can also use an external reference voltage. It has a full-wave CSD mode that alternates sensing to VDDA and ground to null out power-supply related noise.
The CapSense block has two 7-bit IDACs, which can be used for general purposes if CapSense is not being used (both IDACs are available in that case) or if CapSense is used without water tolerance (one IDAC is available). A (slow) 10-bit Slope ADC may be realized by using one of the IDACs.
The block can implement Swipe, Tap, Wake-on-Touch (< 3 µA at 1.8 V), mutual capacitance, and other types of sensing functions.
## _Audio Subsystem_
This subsystem consists of an I[2] S block and two PDM channels. The PDM channels interface to a PDM microphone's bit-stream output. The PDM processing channel provides drop correction and can operate with clock speeds ranging from 384 kHz to 3.072 MHz and produce word lengths of 16 to 24 bits at audio sample rates of up to 48 ksps.
The I[2] S Interface supports both master and slave modes with Word Clock rates of up to 192 ksps (8-bit to 32-bit words).
GPIO pins can be ganged to sink 16 mA or higher values of sink current. GPIO pins, including OVT pins, may not be pulled-up higher than 3.6 V.
Document Number: 002-24085 Rev. *A
Page 8 of 59
**CYBLE-416045-02**
## **Module Overview**
## **Module Description**
The CYBLE-416045-02 module is a complete module designed to be soldered to the main host board.
## _Module Dimensions and Drawing_
Cypress reserves the right to select components (including the appropriate BLE device) from various vendors to achieve the BLE module functionality. Such selections will guarantee that all height restrictions of the component area are maintained. Designs should be completed with the physical dimensions shown in the mechanical drawings in Figure 2. All dimensions are in millimeters (mm).
## **Table 1. Module Design Dimensions**
|**Dimension Item**|**Dimension Item**|**Specification**|
|---|---|---|
|Module dimensions|Length (X)|14.00 ± 0.15 mm|
||Width (Y)|18.50 ± 0.15 mm|
|Antenna location dimensions|Length (X)|14.00 ± 0.15 mm|
||Width (Y)|4.62 ± 0.15 mm|
|PCB thickness|Height (H)|0.80 ± 0.10 mm|
|Shield height|Height (H)|1.20 ± 0.10 mm|
|Maximum component height|Height (H)|1.20 mm typical (shield)|
|Total module thickness (bottom of module to highest component)|Height (H)|2.00 mm typical|
See Figure 2 on page 10 for the mechanical reference drawing for CYBLE-416045-02.
Document Number: 002-24085 Rev. *A
Page 9 of 59
**CYBLE-416045-02**
**Figure 2. Module Mechanical Drawing**[[1]]
**==> picture [48 x 9] intentionally omitted <==**
**----- Start of picture text -----**<br>
Side View<br>**----- End of picture text -----**<br>
**==> picture [64 x 274] intentionally omitted <==**
**----- Start of picture text -----**<br>
Top View<br>|<br>oT<br>e<br>vm<br>=<br>=<br>=<br>a<br>iS<br>&<br>de<br>+46<br>LIEB<br>0.69<br>15<br>Bottom View<br>**----- End of picture text -----**<br>
## **Note**
1. No metal should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area. For more information on recommended host PCB layout, see Figure 4 on page 11, Figure 5 and Figure 6 on page 12, and Figure 7 and Table 3 on page 13.
Document Number: 002-24085 Rev. *A
Page 10 of 59
**CYBLE-416045-02**
## **Pad Connection Interface**
As shown in the bottom view of Figure 2 on page 10, the CYBLE-416045-02 connects to the host board via solder pads on the back of the module. Table 2 and Figure 3 detail the solder pad length, width, and pitch dimensions of the CYBLE-416045-02 module.
**Table 2. Solder Pad Connection Description**
|**Name**|**Connections**|**Connection Type**|**Pad Length Dimension**|**Pad Width Dimension**|**Pad Pitch**|
|---|---|---|---|---|---|
|SP|43|Solder Pads|1.02 mm|0.61 mm|0.90 mm|
**Figure 3. Solder Pad Dimensions**
To maximize RF performance, the host layout should follow these recommendations:
1. The ideal placement of the Cypress BLE Module is in a corner of the host board with the antenna located on the edge of the host board. This placement minimizes the additional recommended keep-out area stated in item 2. Refer to AN96841 for module placement best practices.
2. To maximize RF performance, the area immediately around the Cypress BLE Module trace antenna should contain an additional keep-out area, where no grounding or signal traces are contained. The keep-out area applies to all layers of the host board. The recommended dimensions of the host PCB keep-out area are shown in Figure 4 (dimensions are in mm).
**Figure 4. Recommended Host PCB Keep-Out Area Around the CYBLE-416045-02 Trace Antenna**
**Host PCB Keep-out area Around Trace Antenna**
Document Number: 002-24085 Rev. *A
Page 11 of 59
**CYBLE-416045-02**
## **Recommended Host PCB Layout**
Figure 5 through Figure 7 and Table 3 provide details that can be used for the recommended host PCB layout pattern for the CYBLE-416045-02. Dimensions are in millimeters unless otherwise noted. Pad length of 0.99 mm (0.494 mm from center of the pad on either side) shown in Figure 7 is the minimum recommended host pad length. The host PCB layout pattern can be completed using either Figure 5, Figure 6, or Figure 7. It is not necessary to use all figures to complete the host PCB layout pattern.
**Figure 5. Host Layout Pattern for CYBLE-416045-02**
**Figure 6. Module Pad Location from Origin**
**Top View**
**Top View**
Document Number: 002-24085 Rev. *A
Page 12 of 59
**CYBLE-416045-02**
Table 3 provides the center location for each solder pad on the CYBLE-416045-02. All dimensions reference the to the center of the solder pad. Refer to Figure 7 for the location of each module solder pad.
**Table 3. Module Solder Pad Location**
**Table 3. Module Solder Pad Location** (continued)
|**Solder Pad**<br>**(Center of Pad)**|**Location (X,Y) from**<br>**Origin (mm)**|**Dimension from Origin**<br>**(mils)**||**Solder Pad**<br>**(Center of Pad)**|**Solder Pad**<br>**(Center of Pad)**|**Location (X,Y) from**<br>**Origin (mm)**|**Dimension from Origin**<br>**(mils)**|**Dimension from Origin**<br>**(mils)**|**Dimension from Origin**<br>**(mils)**|
|---|---|---|---|---|---|---|---|---|---|
|1<br>2<br>3<br>4<br>5<br>6<br>7<br>~~ne~~<br>~~a~~|(0.38, 4.93)<br>(0.38, 5.83)<br>(0.38, 6.73)<br>(0.38, 7.63)<br>(0.38, 8.54)<br>(0.38, 9.44)<br>(0.38, 10.34)|(14.96, 194.09)<br>(14.96, 229.53)<br>(14.96, 264.96)<br>(14.96, 300.39)<br>(14.96, 336.22)<br>(14.96, 371.65)<br>(14.96, 407.09)||**Figure 7. Solder Pad Reference Location**<br>41<br>42<br>43|**Figure 7. Solder Pad Reference Location**<br>(13.62, 6.73)<br>(536.22, 264.96)<br>(13.62, 5.83)<br>(536.22, 229.53)<br>(13.62, 4.93)<br>(536.22, 194.09)<br>;<br>||||||
|8|(0.38, 11.24)|(14.96, 442.52)||||||||
|9|(0.38, 12.14)|(14.96, 477.95)||||||||
|10<br>(0.38, 13.04)<br>(14.96, 513.38)<br>11<br>(0.38, 13.95)<br>(14.96, 549.21)<br>12<br>(0.38, 14.85)<br>(14.96, 584.64)<br>13<br>(0.38, 15.75)<br>(14.96, 620.08)<br>14<br>(0.38, 16.65)<br>(14.96, 655.51)<br>15<br>(0.69, 18.12)<br>(27.17, 713.38)<br>16<br>(1.59, 18.12)<br>(62.60, 713.38)<br>17<br>(2.49, 18.12)<br>(98.03, 713.38)<br>18<br>(3.39, 18.12)<br>(133.46, 713.38)<br>19<br>(4.29, 18.12)<br>(168.90, 713.38)<br>~~Fr~~<br>~~OtC«dtSC<“Ctst‘C;‘;é*r.C~CSCSCSOS~~<br>~~a~~<br>~~ne~~<br>~~Fr~~<br>~~OtC«dtSC<“Ctst‘C;‘;é*r.C~CSCSCSOS~~<br>~~a~~<br>~~ne~~<br>~~Fr~~<br>~~OtC«dtSC<“Ctst‘C;‘;é*r.C~CSCSCSOS~~<br>~~a~~<br>~~ne~~||||[|]<br>al<br>Z<br>=<br>]<br>LT<br>i=<br>-<br>i=<br>=<br>—<br>feeqyDETAIL &<br>**=**<br>i=<br>[|]<br>al<br>==<br>]<br>Li<br>**=**<br>**=**<br>FaDpso— (J<br>[<br>PATI4<br>OCggoooo0oo0o0d<br>i<br>||||||==|
|20<br>21<br>22<br>~~a~~<br>~~ne~~|(5.20, 18.12)<br>(6.10, 18.12)<br>(7.00, 18.12)|(204.72, 713.38)<br>(240.16, 713.38)<br>(275.59, 713.38)|||ao<br>“Lt<br>:<br>ao<br>a<br>:||i<br>=L<br>zt|||
|23|(7.90, 18.12)|(311.02, 713.38)||||**Top View**||||
|24|(8.80, 18.12)|(346.46, 713.38)||||||||
|25|(9.70, 18.12)|(381.89, 713.38)||||||||
|26|(10.61, 18.12)|(417.72, 713.38)||||||||
|27|(11.51, 18.12)|(453.15, 713.38)||||||||
|28|(12.41, 18.12)|(488.58, 713.38)||||~ 635||||
|29|(13.31, 18.12)|(524.01, 713.38)||||||||
|30|(13.62, 16.65)|(536.22, 655.51)||||||||
|31|(13.62, 15.75)|(536.22, 620.08)||||||||
|32|(13.62, 14.85)|(536.22, 584.64)||||||||
|33|(13.62, 13.95)|(536.22, 549.21)||||||||
|34|(13.62, 13.04)|(536.22, 513.38)||||||||
|35|(13.62, 12.14)|(536.22, 477.95)||||||||
|36|(13.62, 11.24)|(536.22, 442.52)||||||||
|37|(13.62, 10.34)|(536.22, 407.09)||||||||
|38|(13.62, 9.44)|(536.22, 371.65)||||||||
|39|(13.62, 8.54)|(536.22, 336.22)||||||||
|40|(13.62, 7.63)|(536.22, 300.39)||||||||
Document Number: 002-24085 Rev. *A
Page 13 of 59
**CYBLE-416045-02**
## **Digital and Analog Capabilities and Connections**
Table 4 and Table 5 detail the solder pad connection definitions and available functions for each connection pad. Table 4 lists the solder pads on CYBLE-416045-02, the BLE device port-pin, and denotes whether the digital function shown is available for each solder pad. Table 5 denotes whether the analog function shown is available for each solder pad. Each connection is configurable for a single option shown with a ✓ .
**Table 4. Digital Peripheral Capabilities**
|**Pad Number**<br>~~pf~~|**Device Port Pin**<br>~~pf—_f~~|**UART**<br>~~—_fFP~~|**SPI**<br>~~FP~~|**I2C**<br>~~FP~~|**TCPWM [2, 3]**<br>~~FP~~|**EXT_-**<br>**CLK_IN**<br>~~FP~~|**Audio**<br>~~FP~~|**SWD/JTAG**<br>~~FP~~|**GPIO**<br>~~FP~~|
|---|---|---|---|---|---|---|---|---|---|
|1<br>~~pf~~<br>~~a~~|GND[4]<br>~~pf—_f~~<br>~~ee~~|Ground Connection<br>~~—_fFP~~<br>~~Rsrs nr~~||||||||
|2<br>~~pf~~<br>~~a~~<br>~~a~~|P0.5<br>~~pf —_f~~<br>~~ee~~<br>~~er~~|–<br>~~—_fFP~~<br>~~Rs~~|–<br>~~FP~~<br>~~Rs~~|–<br>~~FP~~<br>~~rs nr~~|tcpwm[0].line_compl[2]<br>tcpwm[1].line_compl[2]<br>~~FP~~<br>~~nr~~|✓<br>~~FP~~|–<br>~~FP~~|–<br>~~FP~~|✓<br>~~FP~~|
|3<br>~~a~~<br>~~a~~<br>~~a~~|VBACKUP<br>~~ee~~<br>~~er~~<br>~~ee~~|Battery Backup Domain Input Voltage (1.71 V to 3.6 V)<br>~~Rs rs nr~~||||||||
|4<br>~~a~~<br>~~a~~<br>~~ee~~|VDD<br>~~er~~<br>~~ee~~<br>~~es~~|Power Supply Input Voltage (1.71 V to 3.6 V)<br>~~rs ns rs~~||||||||
|5<br>~~a~~<br>~~ee~~<br>~~ee~~|P0.0<br>~~ee~~<br>~~es~~|–<br>~~rs ns~~|–<br>~~ns rs~~|–<br>~~rs~~|tcpwm[0].line[0]<br>tcpwm[1].line[0]<br>~~Gn~~|✓|–|–|✓|
|6<br>~~ee~~<br>~~ss~~<br>~~ee~~<br>~~a~~|P0.1<br>~~es ~~<br>~~ss~~<br>~~es~~|–<br> ~~rs ns~~<br>~~ss~~<br>~~es rs~~|–<br>~~ns rs~~<br>~~ss~~<br>~~rs~~|–<br>~~rs~~<br>~~ss~~<br>~~ees~~|tcpwm[0].line_compl[0]<br>tcpwm[1].line_compl[0]<br>~~ss~~<br>~~Gn~~<br>~~rs~~|–<br>~~ss~~|–<br>~~ss~~|✓(JTAG RST)<br>~~ss~~|✓<br>~~ss~~|
|7<br>~~ss~~<br>~~ee~~<br>~~a~~<br>~~a~~|P10.3<br>~~ss~~<br>~~es~~<br>~~ee~~<br>|✓(scb1_CTS)<br>~~ss~~<br>~~es rs~~<br>~~ee Rs~~<br>|✓(scb1_SS0)<br>~~ss~~<br>~~rs~~<br>~~Rs~~<br>|–<br>~~ss~~<br>~~ees~~<br>~~rs nr~~<br>|tcpwm[0].line_compl[7]<br>tcpwm[1].line_compl[23]<br>~~ss~~<br>~~Gn~~<br>~~rs~~<br>~~nr~~|–<br>~~ss~~|–<br>~~ss~~|–<br>~~ss~~|✓<br>~~ss~~|
|8<br>~~ee~~<br>~~a~~<br>~~a~~<br>~~ee~~|P10.4<br>~~es ~~<br>~~ee~~<br>~~ee~~<br>|–<br> ~~es rs~~<br>~~ee Rs~~<br>~~ee~~<br>|✓(scb1_SS1)<br>~~rs ~~<br>~~Rs~~<br>~~ee~~<br>|–<br> ~~ees ~~<br>~~rs nr~~<br>~~es~~<br>|tcpwm[0].line[0]<br>tcpwm[1].line[0]<br>~~Gn~~<br> ~~rs~~<br>~~nr~~<br>~~rr~~|–|✓PDM_CLK|–|✓|
|9<br>~~a ~~<br>~~ee~~<br>~~ee~~|P9.3<br>~~ee ~~<br> ~~ee~~<br>~~es~~|✓(scb2_CTS)<br> ~~ee Rs~~<br>~~ee~~<br>~~**rs**~~|✓(scb2_SS0)<br>~~Rs ~~<br>~~ee~~<br>~~n~~~~**s**~~|–<br> ~~rs nr~~<br>~~es~~<br>~~**rs**~~|tcpwm[0].line_compl[5]<br>tcpwm[1].line_compl[21]<br>~~nr~~<br>~~rr~~|–|–|–|✓|
|10<br> <br>~~ee~~<br>~~ee~~|P10.6<br> ~~ee~~<br>~~es~~<br>~~es~~|–<br>~~ee~~<br>~~**rs**~~|✓(scb1_SS3)<br>~~ee~~<br>~~n~~~~**s**~~<br>~~e~~|–<br>~~es~~<br>~~**rs**~~|tcpwm[0].line[1]<br>tcpwm[1].line[2]<br>~~rr~~|–|–|–|✓|
|11<br> <br>~~ee ~~<br>~~ee~~<br>~~ee~~|P10.5<br> ~~ee ~~<br> ~~es~~<br>~~es~~|–<br> ~~ee ~~<br>~~**rs**~~|✓(scb1_SS2)<br> ~~ee ~~<br>~~n~~~~**s**~~<br>~~e~~<br>~~ss~~|–<br> ~~es~~<br>~~**rs**~~<br>~~ss~~|tcpwm[0].line_compl[0]<br>tcpwm[1].line_compl[0]<br>~~rr~~<br>~~(~~|–|✓PDM_DATA|–|✓|
|12<br> <br>~~ee~~<br>~~ss~~<br>~~ee~~<br>~~a~~|P10.1<br> ~~es ~~<br>~~es~~<br>~~ss~~<br>~~es~~|✓(scb1_TX)<br> ~~**rs** ~~<br>~~ss~~<br>~~es rs~~|✓(scb1_MISO)<br> ~~n~~~~**s** ~~<br>~~e~~<br>~~ss~~<br>~~ss~~<br>~~rs~~|✓(scb1_SDA)<br> ~~**rs**~~<br>~~ss~~<br>~~ss~~<br>~~ees~~|tcpwm[0].line_compl[6]<br>tcpwm[1].line_compl[22]<br>~~ss~~<br>~~(~~<br>~~rs~~|–<br>~~ss~~|–<br>~~ss~~|–<br>~~ss~~|✓<br>~~ss~~|
|13<br>~~ss~~<br>~~ee~~<br>~~a~~<br>~~a~~|P10.0<br>~~ss~~<br>~~es~~<br>~~ee~~|✓(scb1_RX)<br>~~ss~~<br>~~es rs~~<br>~~es es~~|✓(scb1_MOSI)<br>~~ss~~<br>~~ss~~<br>~~rs~~<br>~~es~~|✓(scb1_SCL)<br>~~ss~~<br>~~ss~~<br>~~ees~~<br>~~rn nr~~|tcpwm[0].line[6]<br>tcpwm[1].line[22]<br>~~ss~~<br>~~(~~<br>~~rs~~<br>~~nr~~|–<br>~~ss~~|–<br>~~ss~~|–<br>~~ss~~|✓<br>~~ss~~|
|14<br>~~ee~~<br>~~a~~<br>~~a~~<br>~~a~~|P9.4<br>~~es ~~<br>~~ee~~<br>~~er~~<br>|–<br> ~~es rs~~<br>~~es es~~|✓(scb2_SS1)<br>~~ss~~<br>~~rs ~~<br>~~es~~|–<br>~~ss~~<br> ~~ees ~~<br>~~rn nr~~|tcpwm[0].line[7]<br>tcpwm[1].line[0]<br>~~(~~<br> ~~rs~~<br>~~nr~~|–|–|–|✓|
|15<br>~~a~~<br>~~a~~<br>~~ee~~|GND<br>~~ee~~<br>~~er~~<br>~~ee~~|Ground Connection<br>~~es esrn nr~~||||||||
|16<br>~~a~~<br>~~a ~~<br>~~ee~~<br>~~a~~|VREF<br>~~ee~~<br>~~er~~<br> ~~ee~~<br>~~es~~<br>|Voltage Reference Input (Optional)<br>~~es es rn nr~~<br>~~rsests~~<br>||||||||
|17<br> <br>~~ee~~<br>~~a~~|P9.0<br> ~~ee~~<br>~~es~~<br>|✓(scb2_RX)<br>~~rs~~<br>|✓(scb2_MOSI)<br>~~es~~<br>|✓(scb2_SCL)<br>~~ts~~<br>|tcpwm[0].line[4]<br>tcpwm[1].line[20]<br><br>~~(ne~~|–<br><br>~~(ne~~|–<br>|–<br>|✓<br>|
|18<br> <br>~~ee~~<br>~~a ss~~|P9.1<br> ~~ee~~<br>~~es ~~<br>~~ss~~|✓(scb2_TX)<br> ~~rs ~~<br>~~ss~~|✓(scb2_MISO)<br> ~~es ~~<br>~~ss~~|✓(scb2_SDA)<br> ~~ts~~<br>~~ss~~|tcpwm[0].line_compl[4]<br>tcpwm[1].line_compl[20]<br>~~ss~~<br>~~(ne~~|–<br>~~ss~~<br>~~(ne~~|–<br>~~ss~~|–<br>~~ss~~|✓<br>~~ss~~|
Document Number: 002-24085 Rev. *A
Page 14 of 59
**CYBLE-416045-02**
**Table 4. Digital Peripheral Capabilities** (continued)
|**Pad Number**<br>~~ee~~<br>~~ee~~|**Device Port Pin**<br>~~ee ee~~<br>~~ee~~|**UART**<br>~~ee~~<br>~~ee~~|**SPI**<br>~~es~~<br>~~ee~~|**I2C**<br>~~es~~<br>~~es~~|**TCPWM [2, 3]**<br>~~rs~~<br>~~Gs~~|**EXT_-**<br>**CLK_IN**<br>~~nn~~<br>~~tr~~|**Audio**<br>~~es~~|**SWD/JTAG**|**GPIO**|
|---|---|---|---|---|---|---|---|---|---|
|19<br>~~ee ~~<br>~~ee~~<br>~~ee~~|P9.5<br> ~~ee ee~~<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~<br>~~ee~~|✓(scb2_SS2)<br>~~es~~<br>~~ee~~|–<br>~~es~~<br>~~es~~<br>~~Gs~~|tcpwm[0].line_compl[7]<br>tcpwm[1].line_compl[0]<br>~~rs~~<br>~~Gs~~<br>~~Gs Gs~~|–<br>~~nn~~<br>~~tr~~<br>~~Gs es~~|–<br>~~es~~<br>~~es~~|–|✓|
|20<br>~~ee ~~<br>~~ee~~<br>~~ee~~|P9.6<br> ~~ee~~<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~<br>~~i~~|✓(scb2_SS3)<br>~~ee~~<br>~~rs~~|–<br>~~es~~<br>~~Gs~~<br>~~rs~~|tcpwm[0].line[0]<br>tcpwm[1].line[1]<br>~~Gs ~~<br>~~Gs Gs~~<br>~~rs~~|–<br> ~~tr ~~<br>~~Gs es~~|–<br> ~~es~~<br>~~es~~|–|✓|
|21<br>~~ee~~<br>~~ee~~<br>~~ee~~|P9.2<br>~~ee~~<br>~~ee~~<br>~~ee~~|✓(scb2_RTS)<br>~~ee~~<br>~~i~~<br>~~ss~~|✓(scb2_SCLK)<br>~~rs~~<br>~~ss~~|–<br>~~Gs~~<br>~~rs~~<br>~~rs ts~~|tcpwm[0].line[5]<br>tcpwm[1].line[21]<br>~~Gs Gs~~<br>~~rs~~<br>~~ts~~|–<br>~~Gs es~~|–<br>~~es~~|–|✓|
|22<br>~~ee ~~<br>~~ee~~|P7.2<br> ~~ee ~~<br>~~ee~~|–<br> ~~i~~<br>~~ss~~|–<br>~~rs~~<br>~~ss~~|–<br>~~rs~~<br>~~rs ts~~|tcpwm[0].line[5]<br>tcpwm[1].line[13]<br>~~rs~~<br>~~ts~~|–|–|–|✓|
|23<br>~~ee~~<br>~~a~~<br>~~ee~~|P7.1<br>~~ee ~~<br>~~es~~|–<br> ~~ss~~<br>~~es~~|–<br>~~ss ~~<br>~~es~~|–<br> ~~rs ts~~<br>~~rn~~|tcpwm[0].line_compl[4]<br>tcpwm[1].line_compl[12]<br>~~ts~~<br>~~rn~~|–|–|–|✓|
|24<br>~~a~~<br>~~a~~<br>~~ee~~<br>~~ee~~|P6.4<br>~~es~~<br>~~ee~~|✓(scb6_RX)<br>~~es~~<br>~~rs~~<br>|✓(scb6_MOSI)<br>(scb8_MOSI)<br>~~es~~<br>~~rs~~|✓(scb8_SCL)<br>(scb6_SCL)<br>~~rn~~<br>~~rs ts~~|tcpwm[0].line[2]<br>tcpwm[1].line[10]<br>~~rn~~<br>~~ts~~|–<br>~~I~~|–|✓(JTAG TDO)|✓|
|25<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|P5.4<br>~~es~~<br>~~ee~~<br>|–<br>~~es~~<br>~~rs~~<br>~~ee~~<br>|✓(scb5_SS1)<br>~~es~~<br>~~rs~~|–<br>~~rn~~<br>~~rs ts~~<br>~~Gs~~|tcpwm[0].line[6]<br>tcpwm[1].line[6]<br>~~rn~~<br>~~ts~~<br>~~Gs~~|–<br>~~I~~<br>~~Gs~~|✓I2S_SCK_RX<br>~~es~~|–|✓|
|26<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|P6.7<br>~~es ~~<br>~~ee~~<br>~~ee~~<br>|✓(scb6_CTS)<br> ~~es~~<br>~~rs~~<br>~~ee~~<br>~~i~~<br>|✓(scb6_SS0)<br>(scb8_SS0)<br>~~es ~~<br>~~rs~~<br>~~rs~~<br>|–<br> ~~rn~~<br>~~rs ts~~<br>~~Gs~~<br>~~rs~~<br>|tcpwm[0].line_compl[3]<br>tcpwm[1].line_compl[11<br>~~rn~~<br>~~ts~~<br>~~Gs~~<br>~~rs~~|–<br>~~I~~<br>~~Gs~~|–<br>~~es~~|✓(SWDCLK)<br>(JTAG TCLK)|✓|
|27<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|P6.6<br>~~ee ~~<br>~~ee~~<br>~~ee~~|✓(scb6_RTS)<br>~~rs~~<br> ~~ee~~<br>~~i~~<br>~~re~~|✓(scb6_SCLK)<br>(scb8_SCLK)<br>~~rs ~~<br>~~rs~~<br>~~rs~~|–<br> ~~rs ts~~<br>~~Gs~~<br>~~rs~~<br>~~rs~~|tcpwm[0].line[3]<br>tcpwm[1].line[11]<br>~~ts ~~<br>~~Gs~~<br>~~rs~~<br>~~rs~~|–<br> ~~I~~<br>~~Gs~~|–<br>~~es~~|✓(SWDIO)<br>(JTAG TMS)|✓|
|28<br><br>~~ee ~~<br>~~ee~~<br>~~ee~~|P6.2<br> <br> ~~ee~~<br>~~ee~~|~~ee~~<br>~~i~~<br>~~re~~|✓(scb8_SCLK)<br>~~rs~~<br>~~rs~~|–<br>~~Gs~~<br>~~rs~~<br>~~rs~~|tcpwm[0].line[1]<br>tcpwm[1].line[9]<br>~~Gs~~<br>~~rs~~<br>~~rs~~|–<br>~~Gs ~~|–<br> ~~es~~|–|✓|
|29<br> <br>~~ee ~~<br>~~ee~~<br>~~a~~|P6.5<br> ~~ee ~~<br> ~~ee~~<br>~~es~~|✓(scb6_TX)<br> ~~i~~<br>~~re~~<br>~~es~~|✓(scb6_MISO)<br>(scb8_MISO)<br>~~rs~~<br>~~rs~~<br>~~es~~|✓(scb8_SDA)<br>✓(scb6_SDA)<br>~~rs~~<br>~~rs~~<br>~~rn~~|tcpwm[0].line_compl[2]<br>tcpwm[1].line_compl[10]<br>~~rs~~<br>~~rs~~<br>~~rn~~|–|–|✓(JTAG TDI)|✓|
|30<br> <br>~~ee~~<br>~~a~~<br>~~ee~~|P6.3<br> ~~ee ~~<br>~~es~~|–<br> ~~re ~~<br>~~es~~<br>~~rs~~|✓(scb8_SS0)<br> ~~rs~~<br>~~es~~<br>~~rs~~|–<br>~~rs~~<br>~~rn~~<br>~~rs ts~~|tcpwm[0].line_compl[1]<br>tcpwm[1].line_compl[9]<br>~~rs~~<br>~~rn~~<br>~~ts~~|–<br>~~I~~|–|–|✓|
|31<br>~~a~~<br>~~ee~~<br>~~ee~~|P7.7<br>~~es ~~<br>~~ee~~|–<br> ~~es~~<br>~~rs~~<br>~~ee~~|–<br>~~es ~~<br>~~rs~~|–<br> ~~rn~~<br>~~rs ts~~<br>~~Gs~~|tcpwm[0].line_compl[7]<br>tcpwm[1].line_compl[15]<br>~~rn~~<br>~~ts~~<br>~~Gs Gs~~|–<br>~~I~~<br>~~Gs es~~|–<br>~~es~~|–|✓|
|32<br>~~ee~~<br>~~ee~~<br>~~ee~~|P5.6<br>~~ee~~<br>~~ee~~|–<br>~~rs~~<br>~~ee~~<br>~~i~~|✓(scb5_SS3)<br>~~rs~~<br>~~rs~~|–<br>~~rs ts~~<br>~~Gs~~<br>~~rs~~|tcpwm[0].line[7]<br>tcpwm[1].line[7]<br>~~ts ~~<br>~~Gs Gs~~<br>~~rs~~|–<br> ~~I~~<br>~~Gs es~~|✓I2S_SDI_RX<br>~~es~~|–|✓|
|33<br>~~ee~~<br>~~ee~~<br>~~ee~~|P10.2<br>~~ee~~<br>~~ee~~<br>~~es~~|✓(scb1_RTS)<br>~~ee~~<br>~~i~~<br>~~ee~~|✓(scb1_SCLK)<br>~~rs~~<br>~~rs~~|–<br>~~Gs~~<br>~~rs~~<br>~~rs~~|tcpwm[0].line[7]<br>tcpwm[1].line[23]<br>~~Gs Gs~~<br>~~rs~~<br>~~rs~~|–<br>~~Gs es~~|–<br>~~es~~|–|✓|
|34<br>~~ee ~~<br>~~ee~~<br>~~ee~~|P12.6<br> ~~ee ~~<br>~~es~~<br>~~rs~~|–<br> ~~i~~<br>~~ee~~<br>~~rs~~|✓(scb6_SS3)<br>~~rs~~<br>~~rs~~<br>~~rs~~|–<br>~~rs~~<br>~~rs~~<br>~~ns~~|tcpwm[0].line[7]<br>tcpwm[1].line[7]<br>~~rs~~<br>~~rs~~|–|–|–|✓|
|35<br>~~ee~~<br>~~ee~~<br>~~a~~|P12.7<br>~~es~~<br>~~rs~~<br>~~es~~|–<br>~~ee ~~<br>~~rs~~<br>~~es~~|–<br> ~~rs~~<br>~~rs~~<br>~~es~~|–<br>~~rs~~<br>~~ns~~<br>~~rn~~|tcpwm[0].line_compl[7]<br>tcpwm[1].line_compl[7]<br>~~rs~~<br>~~rn~~|–|–|–|✓|
|36<br>~~ee~~<br>~~a~~<br>~~ee~~|P5.5<br>~~rs~~<br>~~es~~|–<br>~~rs~~<br>~~es~~<br>~~es~~|✓(scb5_SS2)<br>~~rs~~<br>~~es~~<br>~~es~~|–<br>~~ns~~<br>~~rn~~<br>~~rs~~|tcpwm[0].line_compl[6]<br>tcpwm[1].line_compl[6]<br>~~rn~~<br>~~es~~|–<br>~~ts~~|✓I2S_WS_RX|–|✓|
|37<br>~~a~~<br>~~ee~~|P5.3<br>~~es ~~|✓(scb5_CTS)<br> ~~es~~<br>~~es~~|✓(scb5_SS0)<br>~~es ~~<br>~~es~~|–<br> ~~rn~~<br>~~rs~~|cpwm[0].line_compl[5]<br>tcpwm[1].line_compl[5]<br>~~rn~~<br>~~es~~|–<br>~~ts~~|✓I2S_SDO_TX|–|✓|
Document Number: 002-24085 Rev. *A
Page 15 of 59
**CYBLE-416045-02**
**Table 4. Digital Peripheral Capabilities** (continued)
|**Pad Number**<br>~~a~~|**Device Port Pin**<br>~~a~~|**UART**<br>~~a~~|**SPI**<br>~~a~~|**I2C**<br>~~ee~~|**TCPWM [2, 3]**<br>~~ee~~|**EXT_-**<br>**CLK_IN**<br>~~ee~~|**Audio**<br>~~ee~~|**SWD/JTAG**<br>~~ee~~|**GPIO**<br>~~ee~~|
|---|---|---|---|---|---|---|---|---|---|
|38<br>~~a~~<br>~~aa~~|P5.2<br>~~a~~<br>~~aa~~|✓(scb5_RTS)<br>~~a~~<br>~~aa~~|✓(scb5_SCLK)<br>~~a~~<br>~~aa~~|–<br>~~ee~~|tcpwm[0].line[5]<br>tcpwm[1].line[5]<br>~~ee~~|–<br>~~ee~~|✓I2S_WS_TX<br>~~ee~~|–<br>~~ee~~|✓<br>~~ee~~|
|39<br>~~a~~|P5.0<br>~~a~~<br>~~a~~|✓(scb5_RX)<br>~~ee~~|✓(scb5_MOSI)<br>~~ee~~|✓(scb5_SCL)<br>~~ee~~|tcpwm[0].line[4]<br>tcpwm[1].line[4]<br>~~ee~~|–<br>~~ee~~|✓I2S_EX-<br>T_CLK<br>~~ee~~|–<br>~~ee~~|✓<br>~~ee~~|
|40<br>~~aa~~|P5.1<br>~~aa~~|✓(scb5_TX)<br>~~aa~~|✓(scb5_MISO)<br>~~aa~~|✓(scb5_SDA)|tcpwm[0].line_compl[4]<br>tcpwm[1].line_compl[4]|–|✓I2S_CLK_TX|–|✓|
|41<br>~~a~~<br>~~a~~|P0.4<br>~~aa~~|–|–|–|tcpwm[0].line[2]<br>tcpwm[1].line[2]|–|–|–|✓|
|42<br><br>~~a~~|XRES<br>~~a~~|External Reset (Active Low)||||||||
|43<br><br>~~a~~<br>~~i~~|GND[4]<br>~~a~~|Ground Connection||||||||
## **Notes**
> 2. TCPWM stands for timer, counter, and PWM. If supported, the pad can be configured to any of these peripheral functions.
> 3. TCPWM connections on ports 0, 1, 2, and 3 can be routed through the Digital Signal Interconnect (DSI) to any of the TCPWM blocks and can be either positive or negative polarity. 4. The main board needs to connect both GND connections (Pad 1 and Pad 32) on the module to the common ground of the system.
Document Number: 002-24085 Rev. *A
Page 16 of 59
**CYBLE-416045-02**
**Table 5. Additional Analog and Digital Capabilities**
|**Pad Number**<br>~~a~~<br>~~ee~~|**Device Port Pin**<br>~~a~~|**Analog Functionality**|**Universal Digital Block**<br>**(UDB)**|**CapSense**|**Smart IO**|
|---|---|---|---|---|---|
|1<br>~~ee~~<br>~~ee~~|GND<br>~~eG~~|Ground Connection<br>~~eG~~||||
|2<br>~~ee~~<br>~~ee~~|P0.5<br>~~eG~~|–<br>~~eG~~|✓<br>~~eG~~|✓<br>~~eG~~|–<br>~~eG~~|
|3<br>~~ee~~<br>~~a~~<br>~~Re~~|VBACKUP<br>~~eG~~|Battery Backup Domain Input Voltage (1.71 V to 3.6 V)<br>~~eG~~||||
|4<br>~~a~~<br>~~Re~~|VDD|Power Supply Input Voltage (1.71 V to 3.6 V)||||
|5<br>~~Re~~<br>~~eG~~|P0.0<br>~~eG~~|wco_in<br>~~eG~~|✓<br>~~eG~~|✓<br>~~eG~~|–<br>~~eG~~|
|6<br>~~eG~~<br>~~ee~~|P0.1<br>~~eG~~<br>~~Gn~~|wco_out<br>~~eG~~<br>~~Gn~~|✓<br>~~eG~~|✓<br>~~eG~~|–<br>~~eG~~|
|7<br>~~ee~~<br>~~ee~~|P10.3<br>~~Gn~~<br>~~eG~~|sarmux[3]<br>~~Gn~~<br>~~eG~~|✓<br>~~eG~~|✓<br>~~eG~~|–<br>~~eG~~|
|8<br>~~ee~~<br>~~ee~~|P10.4<br>~~Gn~~<br>~~eG~~|sarmux[4]<br>~~Gn~~<br>~~eG~~|✓<br>~~eG~~|✓<br>~~eG~~|–<br>~~eG~~|
|9<br>~~ee~~<br>~~a~~|P9.3<br>~~eG~~<br>~~eG~~|ctb_oa1_out<br>~~eG~~<br>~~eG~~|✓<br>~~eG~~<br>~~eG~~|✓<br>~~eG~~<br>~~eG~~|SMARTIO10[3]<br>~~eG~~<br>~~eG~~|
|10<br>~~eG~~|P10.6<br>~~eG~~|sarmux[6]<br>~~eG~~|✓<br>~~eG~~|✓<br>~~eG~~|–<br>~~eG~~|
|11<br>~~a ~~|P10.5<br> ~~eG~~|sarmux[5]<br>~~eG~~|✓<br>~~eG~~|✓<br>~~eG~~|–<br>~~eG~~|
|12<br>~~eG~~<br>~~ee~~|P10.1<br>~~eG~~<br>~~Gn~~|sarmux[1]<br>~~eG~~<br>~~Gn~~|✓<br>~~eG~~|✓<br>~~eG~~|–<br>~~eG~~|
|13<br>~~ee~~<br>~~ee~~|P10.0<br>~~Gn~~<br>~~eG~~|sarmux[0]<br>~~Gn~~<br>~~eG~~|✓<br>~~eG~~|✓<br>~~eG~~|–<br>~~eG~~|
|14<br>~~ee~~<br>~~ee~~|P9.4<br>~~Gn~~<br>~~eG~~|ctb_oa1-<br>~~Gn~~<br>~~eG~~|✓<br>~~eG~~|✓<br>~~eG~~|SMARTIO9[4]<br>~~eG~~|
|15<br>~~ee~~<br>~~a ~~<br>~~**e**e~~|GND<br>~~eG~~<br> ~~eG~~|Ground Connection<br>~~eG~~<br>~~eG~~||||
|16<br>~~**e**e~~|VREF|Reference Voltage Input (Optional)||||
|17<br>~~**e**e~~|P9.0|ctb_oa0+<br>~~G~~|✓<br>~~G~~|✓<br>~~G~~|SMARTIO9[0]<br>~~G~~|
|18<br>~~eG~~<br>~~ee~~|P9.1<br>~~eG~~<br>~~Gn~~|ctb_oa0-<br>~~eG~~<br>~~Gn~~|✓<br>~~eG~~|✓<br>~~eG~~|SMARTIO9[1]<br>~~eG~~|
|19<br>~~ee~~<br>~~ee~~|P9.5<br>~~Gn~~<br>~~eG~~|ctb_oa1+<br>~~Gn~~<br>~~eG~~|✓<br>~~eG~~|✓<br>~~eG~~|SMARTIO9[5]<br>~~eG~~|
|20<br>~~ee~~<br>~~ee~~<br>~~ee en~~|P9.6<br>~~Gn~~<br>~~eG~~<br>~~en~~|ctb_oa0+<br>~~Gn~~<br>~~eG~~<br>~~Ga~~|✓<br>~~eG~~|✓<br>~~eG~~|SMARTIO9[6]<br>~~eG~~|
|21<br>~~ee~~<br>~~ee en~~|P9.2<br>~~eG~~<br>~~en~~|ctb_oa0_out<br>~~eG~~<br>~~Ga~~|✓<br>~~eG~~|✓<br>~~eG~~|SMARTIO9[2]<br>~~eG~~|
|22<br>~~ee en~~<br>~~a~~|P7.2<br>~~en~~|csd.csh_tankpadd<br>csd.csh_tankpads<br>~~Ga~~|✓|✓|–|
|23<br>~~a~~|P7.1|csd.cmodpadd<br>csd.cmodpads|✓|✓|–|
|24<br>~~eG~~|P6.4<br>~~eG~~|–<br>~~eG~~|✓<br>~~eG~~|✓<br>~~eG~~|–<br>~~eG~~|
|25<br>~~a ~~|P5.4<br> ~~eG~~|–<br>~~eG~~|✓<br>~~eG~~|✓<br>~~eG~~|–<br>~~eG~~|
|26<br>~~eG~~<br>~~ee~~|P6.7<br>~~eG~~<br>~~Gn~~|–<br>~~eG~~<br>~~Gn~~|✓<br>~~eG~~|✓<br>~~eG~~|–<br>~~eG~~|
|27<br>~~ee~~<br>~~ee~~|P6.6<br>~~Gn~~<br>~~eG~~|–<br>~~Gn~~<br>~~eG~~|✓<br>~~eG~~|✓<br>~~eG~~|–<br>~~eG~~|
|28<br>~~ee~~<br>~~ee~~<br>~~**e**e en~~|P6.2<br>~~Gn~~<br>~~eG~~<br>~~en~~|lpcomp.inp_comp1<br>~~Gn~~<br>~~eG~~<br>~~Ga~~|✓<br>~~eG~~<br>|✓<br>~~eG~~<br>|–<br>~~eG~~<br>|
|29<br>~~ee~~<br>~~**e**e en~~|P6.5<br>~~eG~~<br>~~en~~|~~eG~~<br>~~Ga~~|✓<br>~~eG~~<br>|✓<br>~~eG~~<br>|–<br>~~eG~~<br>|
|30<br>~~**e**e en~~|P6.3<br>~~en~~|lpcomp.inn_comp1<br>~~Ga G~~|✓<br>~~G~~|✓<br>~~G~~|–<br>~~G~~|
|31<br>~~a ~~|P7.7<br> ~~eG~~|csd.cshieldpads<br>~~eG~~|✓<br>~~eG~~|✓<br>~~eG~~|–<br>~~eG~~|
|32<br>~~eG~~<br>~~ee~~|P5.6<br>~~eG~~<br>~~Gn~~|lpcomp.inp_comp0<br>~~eG~~<br>~~Gn~~|✓<br>~~eG~~|✓<br>~~eG~~|–<br>~~eG~~|
|33<br>~~ee~~<br>~~ee~~|P10.2<br>~~Gn~~<br>~~eG~~|sarmux[2]<br>~~Gn~~<br>~~eG~~|✓<br>~~eG~~|✓<br>~~eG~~|–<br>~~eG~~|
|34<br>~~ee~~<br>~~ee~~<br>~~**e**e en~~|P12.6<br>~~Gn~~<br>~~eG~~<br>~~en~~|–<br>~~Gn~~<br>~~eG~~<br>~~Ga~~|✓<br>~~eG~~<br>|✓<br>~~eG~~<br>|–<br>~~eG~~<br>|
|35<br>~~ee~~<br>~~**e**e en~~|P12.7<br>~~eG~~<br>~~en~~|–<br>~~eG~~<br>~~Ga~~|✓<br>~~eG~~<br>|✓<br>~~eG~~<br>|–<br>~~eG~~<br>|
|36<br>~~**e**e en~~|P5.5<br>~~en~~|–<br>~~Ga G~~|✓<br>~~G~~|✓<br>~~G~~|–<br>~~G~~|
|37<br>~~a ~~|P5.3<br> ~~eG~~|–<br>~~eG~~|✓<br>~~eG~~|✓<br>~~eG~~|–<br>~~eG~~|
|38<br>~~eG~~<br>~~ee~~|P5.2<br>~~eG~~<br>~~Gn~~|–<br>~~eG~~<br>~~Gn~~|✓<br>~~eG~~|✓<br>~~eG~~|–<br>~~eG~~|
|39<br>~~ee~~<br>~~ee~~|P5.0<br>~~Gn~~<br>~~eG~~|–<br>~~Gn~~<br>~~eG~~|✓<br>~~eG~~|✓<br>~~eG~~|–<br>~~eG~~|
|40<br>~~ee~~<br>~~ee~~|P5.1<br>~~Gn~~<br>~~eG~~|–<br>~~Gn~~<br>~~eG~~|✓<br>~~eG~~|✓<br>~~eG~~|–<br>~~eG~~|
|41<br>~~ee~~<br>~~a~~<br>~~**e**e~~|P0.4<br>~~eG~~<br>~~eG~~<br>~~G~~|–<br>~~eG~~<br>~~eG~~<br>~~G~~|✓<br>~~eG~~<br>~~eG~~<br>~~G~~|✓<br>~~eG~~<br>~~eG~~<br>~~G~~|–<br>~~eG~~<br>~~eG~~<br>~~G~~|
|42<br>~~a ~~<br>~~**e**e~~|XRES<br> ~~eG~~<br>~~G~~|External Reset (Active Low)<br>~~eG~~<br>~~G~~||||
|43<br>~~**e**e~~|GND<br>~~G~~|Ground Connection<br>~~G~~<br>~~G~~||||
Document Number: 002-24085 Rev. *A
Page 17 of 59
**CYBLE-416045-02**
## **Power**
The power connection diagram (see Figure 8) shows the general requirements for power pins on the CYBLE-416045-02. The CYBLE-416045-02 contains a single power supply connection (VDD) and a backup voltage input (VBACKUP).
Description of the power pins is as follows:
- VBACKUP is the supply to the backup domain. The backup domain includes the 32-kHz WCO, real-time clock (RTC), and backup registers. It can generate a wakeup interrupt to the chip via the RTC timers or an external input. It can also generate an output to wakeup external circuitry. It is connected to VDD when not used as a separate battery backup domain. VBACKUP provides the supply for Port 0.
- VDD is the main power supply input (1.71 V to 3.6 V). It provides the power input to the digital, analog, and radio domains. Isolation required for these domains is integrated on-module; therefore, no additional isolation is required for the CYBLE-416045-02.
The supply voltage range is 1.71 to 3.6 V with all functions and circuits operating over that range. All ground connections specified must be connected to system ground.
VDD and VBACKUP may be shorted together externally. They are not required to be separate input voltages.
**Figure 8. CYBLE-416045-02 Power Connections**
Document Number: 002-24085 Rev. *A
Page 18 of 59
**CYBLE-416045-02**
## **32-kHz Crystal Oscillator**
The CYBLE-416045-02 includes connections for a 32-kHz oscillator to provide accurate timing during low-power operations. Figure 9 shows the 32-kHz XTAL oscillator with external components and Table 6 lists the oscillators characteristics. This oscillator can be operated with a 32-kHz or 32.768-kHz crystal oscillator, or be driven with a clock input at similar frequency. The XTAL must have an accuracy of ±250 ppm or better according to the BLE specification over temperature and including aging. The values for C1 and C2 are used to fine-tune the oscillator. The external 32-kHz XTAL is optional, and the precision internal low-speed oscillator (PILO) can be used if precise timing is not required. Precise timing will improve overall system power consumption, as shown in Table 11.
## **Figure 9. 32-kHz Oscillator Block Diagram**
**Table 6. XTAL Oscillator Characteristics**
|**Parameter**<br>~~dG~~<br>~~ee~~|**Description**<br>~~dG~~<br>~~GG~~|**Minimum**<br>~~dG~~<br>~~GG~~|**Typical**<br>~~dG~~<br>~~GG~~|**Maximum**<br>~~dG~~<br>~~GG~~|**Unit**<br>~~dG~~<br>~~GG~~|**Details/Conditions**<br>~~dG~~<br>~~GG~~|
|---|---|---|---|---|---|---|
|FWCO<br>~~dG~~<br>~~ee~~|Crystal frequency<br>~~dG~~<br>~~GG~~|–<br>~~dG~~<br>~~GG~~|32.768<br>~~dG~~<br>~~GG~~|–<br>~~dG~~<br>~~GG~~|kHz<br>~~dG~~<br>~~GG~~|~~dG~~<br>~~GG~~|
|FTOL<br>~~ee~~<br>~~GG~~<br>~~Re~~|Frequencytolerance<br>~~GG~~<br>~~GG~~|–<br>~~GG~~<br>~~GG~~|50<br>~~GG~~<br>~~GG~~|–<br>~~GG~~<br>~~GG~~|ppm<br>~~GG~~<br>~~CO~~|~~GG~~<br>~~CO~~|
|ESR<br>~~Re~~|Equivalent series resistance|–|70|–|k||
|PD<br>~~Re~~<br>~~GG~~|Drive level<br>~~GG~~|–<br>~~GG~~|–<br>~~GG~~|1<br>~~GG~~|W<br>~~GG~~|~~GG~~|
|TSTART<br>~~GG~~<br>~~GG~~<br>~~Re~~|Startuptime<br>~~GG~~<br>~~GG~~|–<br>~~GG~~<br>~~GG~~|–<br>~~GG~~<br>~~GG~~|500<br>~~GG~~<br>~~GG~~|ms<br>~~GG~~<br>~~CO~~|~~GG~~<br>~~CO~~|
|CL<br>~~Re~~|Crystal load capacitance|6<br>~~DG~~|–<br>~~DG~~|12.5<br>~~DG~~|pF<br>~~DO~~|~~DO~~|
|C0<br>~~Re~~<br>~~ee~~|Crystal shunt capacitance<br>~~ee~~|–<br>~~ee~~<br>~~DG~~|1.35<br>~~ee~~<br>~~DG~~|–<br>~~ee~~<br>~~DG~~|pF<br>~~ee~~<br>~~DO~~|~~ee~~<br>~~DO~~|
Document Number: 002-24085 Rev. *A
Page 19 of 59
**CYBLE-416045-02**
The CYBLE-416045-02 schematic is shown in Figure 10.
**Figure 10. CYBLE-416045-02 Schematic Diagram**
Document Number: 002-24085 Rev. *A
Page 20 of 59
**CYBLE-416045-02**
## **Critical Components List**
Table 7 details the critical components used in the CYBLE-416045-02 module.
## **Table 7. Critical Component List**
|**Component**|**Reference Designator**|**Description**|
|---|---|---|
|Silicon|U1|116-pin BGA Programmable System-on-Chip (PSoC 6) with BLE|
|Crystal|Y1|32.000 MHz, 10 PF|
## **Antenna Design**
Table 8 details the PCB trace antenna used on the CYBLE-416045-02 module.
**Table 8. Trace Antenna Specifications**
|**Item**|**Description**|
|---|---|
|Frequency Range|2400 – 2500 MHz|
|Peak Gain|–0.5 dBi typical|
|Return Loss|10 dB minimum|
Document Number: 002-24085 Rev. *A
Page 21 of 59
**CYBLE-416045-02**
## **Electrical Specification**
Table 9 details the absolute maximum electrical characteristics for the Cypress BLE Module. **Table 9. CYBLE-416045-02 Absolute Maximum Ratings**[[5]]
|**Parameter**<br>~~es~~<br>~~es~~|**Description**<br>~~sO~~<br>|**Min**<br>~~sO~~<br>|**Typ**<br>~~sO~~<br>|**Max**<br>~~sO~~<br>|**Unit**<br>~~sO~~<br>|**Details/Conditions**<br>~~sO~~<br>|
|---|---|---|---|---|---|---|
|VDDD_ABS<br>~~es~~<br>~~es~~|VDD, VDDA, and VDDRsupply relative to VSS(VSSD= VSSA)<br>~~sO~~<br>|)<br>–0.5<br>~~sO~~<br>|–<br>~~sO~~<br>|4<br>~~sO~~<br>|V<br>~~sO~~<br>|Absolute maximum<br>~~sO~~<br>|
|VCCD_ABS<br>~~es~~|Direct digital core voltage input relative to VSSD<br>|–0.5<br>|–<br>|1.2<br>|V<br>|Absolute maximum<br>|
|VDDD_RIPPLE<br>~~ee~~<br>~~es~~|Maximum power supply ripple for VDD, VDDA, and VDDR<br>input voltage<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~|–<br><br>~~ee~~|100<br>~~ee~~<br>~~ee~~|mV<br>~~ee~~<br>~~ee~~|3.0 V supply<br>Ripple frequency of<br>100 kHz to 750 kHz<br>~~ee~~<br>~~ee~~|
|VGPIO_ABS<br>~~ee~~<br>~~es~~<br>~~es~~|GPIO voltage<br>~~ee~~<br>~~ee~~|–0.5<br>~~ee ~~<br>~~ee~~|–<br> <br>~~ee~~|VDD +0.5<br> ~~ee~~<br>~~ee~~|V<br>~~ee~~<br>~~ee~~|Absolute maximum<br>~~ee~~<br>~~ee~~|
|IGPIO_ABS<br>~~es~~<br>~~es~~|Maximum current per GPIO<br>~~ee~~|–25<br>~~ee~~|–<br>~~ee~~|25<br>~~ee~~|mA<br>~~ee~~|Absolute maximum<br>~~ee~~|
|IGPIO_injection <br>~~es~~<br>~~es~~|GPIO injection current per pin<br>|–0.5<br>|–<br>|0.5<br>|mA<br>|Absolute maximum<br>current injected per pin<br>|
|LU<br>~~es~~|Pin current for latch up<br>|–100<br>||100<br>|mA<br>|Absolute maximum<br>|
|**Parameter**<br>~~PP~~<br>~~CR~~|**Description**<br>~~PP~~|**Min**<br>~~PP~~|**Typ**<br>~~PP~~|**Max**<br>~~PP~~|**Unit**<br>~~PP~~|**Details/Conditions**<br>~~PP~~|
|---|---|---|---|---|---|---|
|**DC Specifications**<br>~~PP~~<br>~~CR~~<br>~~esDGD~~<br>~~GO (O~~|||||||
|VDDD<br>~~CR~~<br>~~es~~|Internal regulator and Port 1 GPIO supply<br>~~DGD~~|1.71<br>~~DGD~~|–<br>~~DGD~~|3.6<br>~~DGD~~<br>~~GO~~|V<br>~~DGD~~<br>~~GO (O~~|–<br>~~DGD~~<br>~~(O~~|
|VDDA<br>~~es~~<br>~~ee~~<br>~~es~~|Analog power supply voltage. Shorted to VDDIOA<br>on PCB<br>~~DGD~~<br>~~ee~~<br>~~DQG~~|1.71<br>~~DGD~~<br>~~ee~~<br>~~DQG~~|–<br>~~DGD~~<br>~~ee~~<br>~~DQG~~|3.6<br>~~DGD~~<br>~~GO~~<br>~~ee~~<br>~~DQG~~|V<br>~~DGD~~<br>~~GO (O~~<br>~~ee~~<br>~~(~~|Internally unregulated supply<br>~~DGD~~<br>~~(O~~<br>~~ee~~<br>~~(~~|
|VDDIO1<br>~~es~~<br>~~es~~<br>~~es~~|GPIO supplyfor Ports 5 to 8 whenpresent<br>~~DQG~~<br>~~DD~~<br>|1.71<br>~~DQG~~<br>~~DD~~<br>|–<br>~~DQG~~<br>~~DD~~<br>~~GO~~<br>|3.6<br>~~DQG~~<br>~~DD~~<br>~~GO~~<br>|V<br>~~(~~<br>~~DD~~<br>~~(~~<br>|VDDIO_1must beto VDDA.<br>~~(~~<br>~~DD~~<br>~~(~~<br>|
|VDDIO0<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~|GPIO supplyfor Ports 11 to 13 whenpresent<br>~~DQG~~<br>~~DD~~<br>|1.71<br>~~DQG~~<br>~~DD~~<br>|–<br>~~DQG~~<br>~~DD~~<br>~~GO~~<br><br>~~GO~~|3.6<br>~~DQG ~~<br>~~DD~~<br>~~GO~~<br><br>~~GO~~|V<br> ~~(~~<br>~~DD~~<br>~~(~~<br><br>~~G~~|~~(~~<br>~~DD~~<br>~~(~~<br><br>~~G~~~~**O**~~|
|VDDIO0<br>~~es~~<br>~~es~~<br>~~es~~|Supplyfor eFuseprogramming<br>~~DD~~<br>~~DD~~|2.38<br>~~DD~~<br>~~DD~~|2.5<br>~~DD~~<br>~~GO~~<br>~~DD~~<br>~~GO~~|2.62<br>~~DD~~<br>~~GO~~<br>~~DD~~<br>~~GO~~|V<br>~~DD~~<br>~~(~~<br>~~DD~~<br>~~G~~|eFuseprogrammingvoltage<br>~~DD~~<br>~~(~~<br>~~DD~~<br>~~G~~~~**O**~~|
|VDDIOR<br>~~es~~<br>~~es~~<br>~~a~~|GPIO supplyfor Ports 2 to 4 on BGA 124 only<br><br>~~GG~~<br>|1.71<br><br>~~GG~~<br>~~e~~<br>|–<br>~~GO~~<br><br>~~GO~~<br>~~GG~~<br>~~e~~~~**e**~~<br>|3.6<br>~~GO ~~<br><br>~~GO~~<br>~~GG~~|V<br> ~~(~~<br><br>~~G~~<br>~~Q~~|–<br>~~(~~<br><br>~~G~~~~**O**~~<br>~~Q~~|
|VDDIOA<br>~~es~~<br>~~a ee~~<br>~~a~~<br>~~es~~|GPIO supply for Ports 9 to 10. Shorted to VDDAon<br>PCB<br>~~GG~~<br>~~ee~~<br><br>|1.71<br>~~GG~~<br>~~ee~~<br>~~e~~<br>~~ee~~<br>|–<br>~~GO ~~<br>~~GG~~<br>~~ee~~<br>~~e~~~~**e**~~<br>~~ee~~<br>|3.6<br> ~~GO ~~<br>~~GG ~~<br>~~ee~~<br>|V<br> ~~G~~<br> ~~Q~~<br>~~ee~~<br>|–<br>~~G~~~~**O**~~<br>~~Q~~<br>~~ee~~<br>|
|VBACKUP<br>~~a e~~<br>~~es~~<br>~~es~~|Backup power and GPIO Port 0 supply when<br>present<br>~~e~~<br>|1.71<br>~~e~~<br>~~eee~~<br>|–<br>~~e~~~~**e**~~<br>~~eee~~<br><br>~~GO~~|3.6<br><br>~~GO~~|V<br><br>~~GO~~|Minimum is 1.4 V in Backup mode<br><br>~~GO~~|
|VCCD1<br><br>~~es~~<br>~~es~~|Output voltage(for core logic bypass)<br><br>~~DD~~|–<br>~~ee~~<br>~~DD~~|1.1<br>~~ee~~<br>~~DD~~<br>~~GO~~|–<br>~~DD~~<br>~~GO~~|V<br>~~DD~~<br>~~GO~~|High-speed mode<br>~~DD~~<br>~~GO~~|
|VCCD2<br><br>~~es~~<br>~~es~~<br>~~es~~|Output voltage(for core logic bypass)<br><br><br>~~GG~~|–<br>~~ee~~<br><br>~~GG~~|0.9<br>~~ee~~<br><br>~~GO~~<br>~~GG~~|–<br><br>~~GO~~<br>~~GG~~|~~GO~~<br>~~QO~~|ULP mode. Valid for –20 to 85 °C<br><br>~~GO~~<br>~~QO~~|
|CEFC<br>~~es~~<br>~~es~~<br>~~es~~<br>~~Ce~~|External regulator voltage(VCCD)bypass<br>~~GG~~<br>~~QO~~<br><br>~~Ce~~|3.8<br>~~GG~~<br>~~QO~~<br>|4.7<br>~~GO ~~<br>~~GG~~<br>~~QO~~<br><br>~~GO~~|5.6<br> ~~GO ~~<br>~~GG~~<br>~~QO GQ~~<br><br>~~GO~~|µF<br> ~~GO~~<br>~~QO~~<br>~~GQ~~<br><br>~~GO~~|X5R ceramic or better<br>~~GO~~<br>~~QO~~<br>~~GQ~~<br><br>~~GO~~|
|CEXC<br>~~es~~<br>~~es~~<br>~~Ce~~|Power supplydecouplingcapacitor<br>~~GG~~<br>~~QO~~<br>~~DD~~<br>~~Ce~~|–<br>~~GG~~<br>~~QO~~<br>~~DD~~|10<br>~~GG~~<br>~~QO~~<br>~~DD~~<br>~~GO~~|–<br>~~GG ~~<br>~~QO GQ~~<br>~~DD~~<br>~~GO~~|µF<br> ~~QO~~<br>~~GQ~~<br>~~DD~~<br>~~GO~~|X5R ceramic or better<br>~~QO~~<br>~~GQ~~<br>~~DD~~<br>~~GO~~|
|**LP Range Power Specifications(for VCCD = 1.1 V with Buck and LDO)**<br>~~QO GQ~~<br>~~esDD~~<br>~~GOGO~~<br>~~Ce~~<br>~~RC~~|||||||
|**Cortex-M4 - Active Mode**<br>~~GO GO~~<br>~~Ce~~<br>~~RC~~|||||||
|**Execute with Cache Disabled(Flash)**<br>~~RCCs~~<br>~~a~~<br>~~eeee~~|||||||
|IDD1<br>~~TA~~|Execute from Flash; CM4 Active 50 MHz, CM0+<br>Sleep 25 MHz. With IMO and FLL. While(1)<br>~~TA~~|–<br>~~a~~<br>~~TA~~|2.3<br>~~ee~~<br>~~TA~~|3.2<br>~~ee~~<br>~~TA~~|mA<br>~~TA~~<br>~~es~~|VDDD= 3.3 V, Buck ON, max at 60 °C<br>~~TA~~|
|||–<br>~~a~~<br>~~TA~~<br>~~a~~|3.1<br>~~ee ~~<br>~~TA~~<br>~~ee~~|3.6<br> ~~ee~~<br>~~TA~~<br>~~ee~~||VDDD= 1.8 V, Buck ON, max at 60 °C<br>~~TA~~|
|||–<br>~~TA~~<br>~~a~~|4.2<br>~~TA~~<br>~~ee~~|5.1<br>~~TA~~<br>~~ee~~||VDDD= 1.8 to 3.3 V, LDO, max at 60 °C<br>~~TA~~|
|IDD2<br>~~===~~|Execute from Flash; CM4 Active 8 MHz, CM0+<br>Sleep 8 MHz.With IMO. While(1)<br>~~===~~|–<br>~~a ~~<br>~~a~~<br>~~===~~|0.9<br> ~~ee~~<br>~~ee~~<br>~~===~~|1.5<br>~~ee ~~<br>~~ee~~<br>~~===~~|mA<br> ~~es~~<br>~~===~~<br>~~es~~|VDDD= 3.3 V, Buck ON, max at 60 °C<br>~~===~~|
|||–<br>~~===~~<br>~~ee~~|1.2<br>~~===~~<br>~~ee~~|1.6<br>~~===~~<br>~~ee~~||VDDD= 1.8 V, Buck ON, max at 60 °C<br>~~===~~|
|||–<br>~~===~~<br>~~ee~~|1.6<br>~~===~~<br>~~ee~~|2.4<br>~~===~~<br>~~ee~~||VDDD= 1.8 to 3.3 V, LDO, max at 60 °C<br>~~===~~|
Document Number: 002-24085 Rev. *A
Page 22 of 59
**CYBLE-416045-02**
**Table 10. Power Supply Range, CPU Current, and Transition Time Specifications** (continued)
|**Parameter**<br>~~GG~~|**Description**<br>~~GG~~|**Min**<br>~~GG~~|**Typ**<br>~~GG~~|**Max**<br>~~GG~~|**Unit**<br>~~(ODO~~|**Details/Conditions**<br>~~(ODO~~|
|---|---|---|---|---|---|---|
|**Execute with Cache Enabled**<br>~~GG (ODO~~<br>~~Ee~~|||||||
|IDD3|Execute from Cache; CM4 Active150 MHz, CM0+<br>Sleep 75 MHz. IMO and FLL. Dhrystone|–<br>~~a~~|6.3<br>~~a~~|7<br>~~a~~|mA|VDDD= 3.3 V, Buck ON, max at 60 °C|
|||–<br>~~a~~|9.7<br>~~a~~|11.2<br>~~a~~||VDDD= 1.8 V, Buck ON, max at 60 °C|
|||–<br>~~a~~|13.2<br>~~a~~|13.7<br>~~a~~||VDDD= 1.8 to 3.3 V, LDO, max at 60 °C|
|IDD4|Execute from Cache; CM4 Active100 MHz, CM0+<br>Sleep 100 MHz. IMO and FLL. Dhrystone|–<br>~~a~~|4.8<br>~~a~~|5.8<br>~~a~~|mA<br>~~ce~~|VDDD= 3.3 V, Buck ON, max at 60 °C|
|||–<br>~~a~~<br>~~a~~|7.4<br>~~a~~<br>~~a~~|8.4<br>~~a~~<br>~~a~~<br>~~ce~~||VDDD= 1.8 V, Buck ON, max at 60 °C|
|||–<br>~~a~~<br>~~a~~|10.1<br>~~a~~<br>~~a~~|10.7<br>~~a~~<br>~~a~~<br>~~ce~~||VDDD= 1.8 to 3.3 V, LDO, max at 60 °C|
|IDD5|Execute from Cache; CM4 Active 50 MHz, CM0+<br>Sleep 25 MHz. IMO and FLL. Dhrystone|–<br>~~a~~<br>~~a~~|2.4<br>~~a~~<br>~~a~~|3.4<br>~~a~~<br>~~ce~~<br>~~a~~|mA<br>~~ce~~|VDDD= 3.3 V, Buck ON, max at 60 °C|
|||–<br>~~a~~|3.7<br>~~a~~|4.1<br>~~a~~||VDDD= 1.8 V, Buck ON, max at 60 °C|
|||–<br>~~a~~|5.1<br>~~a~~|5.8<br>~~a~~||VDDD= 1.8 to 3.3 V, LDO, max at 60 °C|
|IDD6|Execute from Cache; CM4 Active 8 MHz, CM0+<br>Sleep 8 MHz. IMO. Dhrystone|–<br>~~a~~|0.90<br>~~a~~|1.5<br>~~a~~|mA|VDDD= 3.3 V, Buck ON, max at 60 °C|
|||–<br>~~a~~<br>~~a~~|1.27<br>~~a~~<br>~~a~~|1.75<br>~~a~~<br>~~a~~||VDDD= 1.8 V, Buck ON, max at 60 °C|
|||–<br>~~a~~<br>~~a~~|1.8<br>~~a~~<br>~~a~~|2.6<br>~~a~~<br>~~a~~||VDDD= 1.8 to 3.3 V, LDO, max at 60 °C|
|**Cortex-M0+. Active Mode**<br>~~ER~~|||||||
|**Execute with Cache Disabled(Flash)**|||||||
|IDD7|Execute from Flash;CM4 OFF, CM0+ Active 50<br>MHz. With IMO and FLL. While (1).|–<br>~~a~~|2.4<br>~~a~~|3.3<br>~~a~~|mA|VDDD= 3.3 V, Buck ON, max at 60 °C|
|||–<br>~~a~~|3.2<br>~~a~~|3.7<br>~~a~~||VDDD= 1.8 V, Buck ON, max at 60 °C|
|||–<br>~~a~~<br>~~a~~|4.1<br>~~a~~<br>~~a~~|4.8<br>~~a~~<br>~~a~~||VDDD= 1.8 to 3.3 V, LDO, max at 60 °C|
|IDD8|Execute from Flash;CM4 OFF, CM0+ Active 8<br>MHz. With IMO. While (1)|–<br>~~a~~<br>~~a~~|0.8<br>~~a~~<br>~~a~~|1.5<br>~~a~~<br>~~a~~|mA|VDDD= 3.3 V, Buck ON, max at 60 °C|
|||–<br>~~a~~|1.1<br>~~a~~|1.6<br>~~a~~||VDDD= 1.8 V, Buck ON, max at 60 °C|
|||–<br>~~a~~|1.45<br>~~a~~|1.9<br>~~a~~||VDDD= 1.8 to 3.3 V, LDO, max at 60 °C|
|**Execute with Cache Enabled**|||||||
|IDD9|Execute from Cache;CM4 OFF, CM0+ Active 100<br>MHz. With IMO and FLL. Dhrystone|–<br>~~a~~|3.8<br>~~aee~~|4.5<br>~~aee~~|mA<br>~~ee~~<br>~~ce~~|VDDD= 3.3 V, Buck ON, max at 60 °C<br>~~ee~~|
|||–<br>~~a~~<br>~~a~~|5.9<br>~~aee~~<br>~~a~~|6.5<br>~~aee~~<br>~~a~~<br>~~ce~~||VDDD= 1.8 V, Buck ON, max at 60 °C<br>~~ee~~|
|||–<br>~~a~~<br>~~a~~|7.7<br>~~a~~<br>~~a~~|8.2<br>~~a~~<br>~~a~~<br>~~ce~~||VDDD= 1.8 to 3.3 V, LDO, max at 60 °C|
|IDD10|Execute from Cache;CM4 OFF, CM0+ Active 8<br>MHz. With IMO. Dhrystone|–<br>~~a~~|0.80<br>~~a~~|1.3<br>~~ce~~<br>~~a~~|mA<br>~~ce~~|VDDD= 3.3 V, Buck ON, max at 60 °C|
|||–<br>~~a~~|1.2<br>~~a~~|1.7<br>~~a~~||VDDD= 1.8 V, Buck ON, max at 60 °C|
|||–<br>~~a~~|1.41<br>~~a~~|2<br>~~a~~||VDDD= 1.8 to 3.3 V, LDO, max at 60 °C|
|**Cortex-M4. Sleep Mode**|||||||
|IDD11|CM4 Sleep 100 MHz, CM0+ Sleep 25 MHz. With<br>IMO and FLL|–<br>~~a~~|1.5<br>~~a~~|2.2<br>~~a~~|mA<br>~~ce~~<br>~~ee~~|VDDD= 3.3 V, Buck ON, max at 60 °C|
|||–<br>~~a~~<br>~~a~~<br><br>~~a~~|2.2<br>~~a~~<br>~~a~~<br>|2.7<br>~~a~~<br>~~a~~<br>~~ce~~||VDDD= 1.8 V, Buck ON, max at 60 °C|
|||–<br>~~a~~<br>~~a~~|2.9<br>~~a~~<br>~~ee~~|3.5<br>~~ace~~<br>~~ee~~||VDDD= 1.8 to 3.3 V, LDO, max at 60 °C|
|IDD12|CM4 Sleep 50 MHz, CM0+ Sleep 25 MHz. With<br>IMO and FLL|–<br><br>~~a~~|1.20<br><br>~~ee~~|1.9<br>~~ce~~<br>~~ee~~|mA<br>~~ce~~<br>~~ee~~|VDDD= 3.3 V, Buck ON, max at 60 °C|
|||–<br>~~a~~|1.70<br>~~ee~~<br>~~a~~|2.2<br>~~ee~~<br>~~a~~||VDDD= 1.8 V, Buck ON, max at 60 °C|
|||–<br>~~a~~|2.20<br>~~a~~|2.8<br>~~a~~||VDDD= 1.8 to 3.3 V, LDO, max at 60 °C|
|IDD13|CM4 Sleep 8 MHz, CM0+ Sleep 8 MHz. With IMO|–<br>~~a~~<br>~~a~~|0.7<br>~~a~~<br>~~a~~|1.3<br>~~a~~<br>~~a~~|mA|VDDD= 3.3 V, Buck ON, max at 60 °C|
|||–<br>~~a~~<br>~~a~~|0.96<br>~~a~~<br>~~a~~|1.5<br>~~a~~<br>~~a~~||VDDD= 1.8 V, Buck ON, max at 60 °C|
|||–<br>~~a~~<br>~~a~~|1.22<br>~~a~~<br>~~a~~|2<br>~~a~~<br>~~a~~||VDDD= 1.8 to 3.3 V, LDO, max at 60 °C|
|**Cortex**-**M0+. Sleep Mode**|||||||
|IDD14|CM4 Off, CM0+ Sleep 50 MHz. With IMO and FLL|–<br>~~a~~|1.3<br>~~a~~|2<br>~~a~~|mA<br>~~ce~~|VDDD= 3.3 V, Buck ON, max at 60 °C|
|||–<br>~~a~~|1.94<br>~~a~~|2.4<br>~~a~~<br>~~ce~~||VDDD= 1.8 V, Buck ON, max at 60 °C|
|||–<br>~~a~~<br>~~a~~|2.57<br>~~a~~<br>~~a~~|3.2<br>~~a~~<br>~~a~~<br>~~ce~~||VDDD= 1.8 to 3.3 V, LDO, max at 60 °C|
|IDD15|CM4 Off, CM0+ Sleep 8 MHz. With IMO|–<br>~~a~~|0.7<br>~~a~~|1.3<br>~~ce~~<br>~~a~~|mA<br>~~ce~~|VDDD= 3.3 V, Buck ON, max at 60 °C|
|||–<br>~~a~~<br>~~a~~|0.95<br>~~a~~<br>~~a~~|1.5<br>~~a~~<br>~~a~~||VDDD= 1.8 V, Buck ON, max at 60 °C|
|||–<br>~~a~~|1.25<br>~~a~~|2<br>~~a~~||VDDD= 1.8 to 3.3 V, LDO, max at 60 °C|
Document Number: 002-24085 Rev. *A
Page 23 of 59
**CYBLE-416045-02**
**Table 10. Power Supply Range, CPU Current, and Transition Time Specifications** (continued)
|**Parameter**<br>~~PO~~|**Description**<br>~~PO~~|**Min**<br>~~PO~~|**Typ**<br>~~PO~~|**Max**<br>~~PO~~|**Unit**<br>~~PO~~|**Details/Conditions**<br>~~PO~~|
|---|---|---|---|---|---|---|
|**Cortex-M4. Low-Power Active(LPA) Mode**<br>~~PO~~<br>~~esee~~|||||||
|IDD16<br>~~===~~|Execute from Flash; CM4 LPA 8 MHz, CM0+ Sleep<br>8 MHz. With IMO. While (1)<br>~~===~~|–<br>~~es~~<br>~~===~~|0.85<br>~~ee~~<br>~~===~~|1.5<br>~~ee~~<br>~~===~~|mA<br>~~===~~<br>~~es~~|VDDD= 3.3 V, Buck ON, max at 60 °C<br>~~===~~|
|||–<br>~~es ~~<br>~~===~~<br>|1.18<br> ~~ee~~<br>~~===~~<br>|1.65<br>~~ee~~<br>~~===~~<br>~~es~~||VDDD= 1.8 V, Buck ON, max at 60 °C<br>~~===~~|
|||–<br>~~===~~<br>~~i~~|1.63<br>~~===~~<br>~~i~~<br>~~ee~~|2.4<br>~~===~~<br>~~ies~~<br>~~ee~~||VDDD= 1.8 to 3.3 V, LDO, max at 60 °C<br>~~===~~|
|IDD17<br>~~EE~~|Execute from Cache; CM4 LPA 8 MHz, CM0+<br>Sleep 8 MHz. With IMO. Dhrystone<br>~~EE~~|–<br><br>~~a~~<br>~~EE~~|0.90<br><br>~~a~~<br>~~ee~~<br>~~EE~~|1.5<br>~~es~~<br>~~a~~<br>~~ee~~<br>~~EE~~|mA<br>~~es~~<br>~~EE~~<br>~~es~~|VDDD= 3.3 V, Buck ON, max at 60 °C<br>~~EE~~|
|||–<br>~~a~~<br>~~EE~~<br>~~es~~|1.27<br>~~a~~<br>~~ee ~~<br>~~EE~~<br>~~es~~|1.75<br>~~a~~<br> ~~ee~~<br>~~EE~~<br>~~es~~||VDDD= 1.8 V, Buck ON, max at 60 °C<br>~~EE~~|
|||–<br>~~EE~~<br>~~es~~|1.77<br>~~EE~~<br>~~es~~|2.5<br>~~EE~~<br>~~es~~||VDDD= 1.8 to 3.3 V, LDO, max at 60 °C<br>~~EE~~|
|**Cortex-M0+. Low-Power Active(LPA) Mode**<br>~~EE~~<br>~~es es~~|||||||
|IDD18<br>~~=~~|Execute from Flash; CM4 Off, CM0+ LPA 8 MHz.<br>With IMO. While (1)<br>~~===~~|–<br>~~a~~<br>~~==~~|0.8<br>~~ee~~<br>~~==~~|1.4<br>~~ee~~<br>~~==~~|mA<br>~~==~~<br>~~ee~~|VDDD= 3.3 V, Buck ON, max at 60 °C<br>~~==~~|
|||–<br>~~==~~<br>~~a~~|1.14<br>~~==~~<br>~~ee~~|1.6<br>~~==~~<br>~~e~~||VDDD= 1.8 V, Buck ON, max at 60 °C<br>~~==~~|
|||–<br>~~==~~<br>~~a~~<br>~~a~~|1.6<br>~~==~~<br>~~a~~<br>~~ee~~|2.4<br>~~==~~<br>~~a~~<br>~~e~~||VDDD= 1.8 to 3.3 V, LDO, max at 60 °C<br>~~==~~|
|IDD19<br>~~=~~<br>~~EE~~<br>~~RC~~|Execute from Cache; CM4 Off, CM0+ LPA 8 MHz.<br>With IMO. Dhrystone<br>~~===~~<br>~~EE~~|–<br>~~==~~<br>~~a~~<br>~~a~~<br>~~EE~~|0.8<br>~~==~~<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~EE~~|1.4<br>~~==~~<br>~~a~~<br>~~e~~<br>~~ee~~<br>~~EE~~|mA<br>~~==~~<br>~~ee~~<br>~~EE~~|VDDD= 3.3 V, Buck ON, max at 60 °C<br>~~==~~<br>~~EE~~|
|||–<br>~~a~~<br>~~EE~~|1.15<br>~~ee ~~<br>~~ee~~<br>~~EE~~|1.65<br> ~~e~~<br>~~ee~~<br>~~EE~~||VDDD= 1.8 V, Buck ON, max at 60 °C<br>~~EE~~|
|||–<br>~~EE~~<br>~~es~~|1.62<br>~~EE~~<br>~~es~~|2.4<br>~~EE~~<br>~~es~~||VDDD= 1.8 to 3.3 V, LDO, max at 60 °C<br>~~EE~~|
|**Cortex-M4. Low-Power Sleep (LPS) Mode**<br>~~RC~~<br>~~es~~<br>~~ee~~|||||||
|IDD20<br>~~RC~~<br>~~PT~~|CM4 LPS 8 MHz, CM0+ LPS 8 MHz. With IMO<br>~~PT~~|–<br>~~es~~<br>~~PT~~|0.65<br>~~es~~<br>~~ee~~<br>~~PT~~|1.1<br>~~es~~<br>~~PT~~|mA<br>~~PT~~|VDDD= 3.3 V, Buck ON, max at 60 °C<br>~~PT~~|
|||–<br>~~PT~~|0.95<br>~~ee~~<br>~~PT~~|1.5<br>~~PT~~||VDDD= 1.8 V, Buck ON, max at 60 °C<br>~~PT~~|
|||–<br>~~PT~~|1.31<br>~~PT~~|2.1<br>~~PT~~||VDDD= 1.8 to 3.3 V, LDO, max at 60 °C<br>~~PT~~|
|**Cortex-M0+. Low-Power Sleep (LPS) Mode**<br>~~PT~~<br>~~Re~~<br>~~esee~~|||||||
|IDD22<br>~~TO~~<br>~~RC~~|CM4 OFF, CM0+ LPS 8 MHz. With IMO<br>~~TO~~<br>|–<br>~~es~~<br>~~TO~~|0.64<br>~~ee~~<br>~~TO~~|1.1<br>~~ee~~<br>~~TO~~|mA<br>~~TO~~<br>|VDDD= 3.3 V, Buck ON, max at 60 °C<br>~~TO~~|
|||–<br>~~es ~~<br>~~TO~~|0.93<br> ~~ee~~<br>~~TO~~|1.45<br>~~ee~~<br>~~TO~~||VDDD= 1.8 V, Buck ON, max at 60 °C<br>~~TO~~|
|||–<br>~~TO~~<br>|1.29<br>~~TO~~<br>|2<br>~~TO~~<br>||VDDD= 1.8 to 3.3 V, LDO, max at 60 °C<br>~~TO~~<br>|
|**ULP Range Power Specifications(for VCCD = 0.9 V using the Buck). ULP Mode is valid from -20 to +85 °C.**<br>~~RC~~|||||||
|**Cortex-M4. Active Mode**<br>~~RCCe~~<br>~~RC~~|||||||
|**Execute with Cache Disabled(Flash)**<br>~~Ce~~<br>~~RCPf~~<br>~~ht~~<br>~~Po~~|||||||
|IDD3<br>~~RCPf~~|Execute from Flash; CM4 Active 50 MHz, CM0+<br>Sleep 25 MHz. With IMO and FLL. While(1)<br>~~Pf~~|–<br>~~ht~~|1.7<br>~~ht~~|2.2|mA<br>~~Po~~|VDDD= 3.3 V, Buck ON, max at 60 °C<br>~~Po~~|
|||–<br>~~ht~~|2.1<br>~~ht~~|2.4||VDDD= 1.8 V, Buck ON, max at 60 °C<br>~~Po~~|
|IDD4<br>~~—~~|Execute from Flash; CM4 Active 8 MHz, CM0+<br>Sleep 8 MHz. With IMO. While (1)<br>|–<br>|0.56<br>|0.8<br>|mA<br>|VDDD= 3.3 V, Buck ON, max at 60 °C<br>|
|||–<br>|0.75<br>|1<br>||VDDD= 1.8 V, Buck ON, max at 60 °C<br>|
|**Execute with Cache Enabled**<br>~~—Ce~~|||||||
|IDD10<br>~~Ce~~<br>~~a~~<br>~~a~~|Execute from Cache; CM4 Active 50 MHz, CM0+<br>Sleep 25 MHz. With IMO and FLL. Dhrystone<br>~~Ce~~<br>~~ee~~<br>|–<br>~~Ce~~<br>~~ee~~|1.6<br>~~Ce~~<br>~~ee~~|2.2<br>~~Ce~~<br>~~ee~~|mA<br>~~Ce~~<br>|VDDD= 3.3 V, Buck ON, max at 60 °C<br>~~Ce~~<br>~~ee~~|
|||–<br>~~ee~~<br>~~es~~<br>|2.4<br>~~ee~~<br>~~**e**~~<br>|2.7<br>~~ee ~~<br>~~**e**e~~||VDDD= 1.8 V, Buck ON, max at 60 °C<br> ~~ee~~|
|IDD11<br>~~a~~|Execute from Cache; CM4 Active 8 MHz, CM0+<br>Sleep 8 MHz. With IMO. Dhrystone<br>~~e~~|–<br>~~es~~<br>~~e~~|0.65<br>~~**e**~~<br>~~e~~|0.8<br>~~**e**e~~|mA|VDDD= 3.3 V, Buck ON, max at 60 °C|
|||–<br>~~es ~~<br>~~e~~|0.8<br> ~~**e**~~<br>~~e~~|1.1<br>~~**e**e~~||VDDD= 1.8 V, Buck ON, max at 60 °C|
|**Cortex-M0+. Active Mode**|||||||
|**Execute with Cache Disabled(Flash)**<br>~~Re~~|||||||
|IDD16<br>~~Re~~<br>~~a~~<br>~~a~~|Execute from Flash; CM4 Off, CM0+ Active 25<br>MHz. With IMO and FLL. Write(1)<br>~~Re~~<br>~~ee~~<br>|–<br>~~Re~~<br>~~ee~~|1.00<br>~~Re~~<br>~~ee~~|1.4<br>~~Re~~<br>~~ee~~|mA<br>~~Re~~<br>~~ee~~|VDDD= 3.3 V, Buck ON, max at 60 °C<br>~~Re~~<br>~~ee~~|
|||–<br>~~ee~~<br>~~es~~<br>|1.34<br>~~ee~~<br>~~**e**~~<br>|1.6<br>~~ee~~<br>~~**e**e~~||VDDD= 1.8 V, Buck ON, max at 60 °C<br>~~ee~~|
|IDD17<br>~~a~~|Execute from Flash; CM4 Off, CM0+ Active 8 MHz.<br>With IMO. While(1)<br>~~e~~|–<br>~~es~~<br>~~e~~|0.54<br>~~**e**~~<br>~~e~~|0.75<br>~~**e**e~~|mA|VDDD= 3.3 V, Buck ON, max at 60 °C|
|||–<br>~~es ~~<br>~~e~~|0.73<br> ~~**e**~~<br>~~e~~|1<br>~~**e**e~~||VDDD= 1.8 V, Buck ON, max at 60 °C|
|**Execute with Cache Enabled**<br>~~a~~<br>~~eeeee~~|||||||
|IDD18<br>~~a~~|Execute from Cache; CM4 Off, CM0+ Active 25<br>MHz. With IMO and FLL. Dhrystone<br>~~ee~~|–<br>~~ee~~|0.91<br>~~ee~~|1.25<br>~~ee~~|mA<br>|VDDD= 3.3 V, Buck ON, max at 60 °C<br>~~eee~~|
|||–<br>~~ee~~|1.34<br>~~ee~~|1.6<br>~~ee~~||VDDD= 1.8 V, Buck ON, max at 60 °C<br>~~eee~~|
|IDD19<br>~~a~~<br>~~a~~|Execute from Cache; CM4 Off, CM0+ Active 8<br>MHz. With IMO. Dhrystone<br>~~ee~~<br>~~e~~|–<br>~~ee~~<br>~~a~~<br>~~e~~|0.51<br>~~ee~~<br>~~**e**~~<br>~~e~~|0.72<br>~~ee ~~<br>~~**e**e~~|mA<br>|VDDD= 3.3 V, Buck ON, max at 60 °C<br> ~~eee~~|
|||–<br>~~a ~~<br>~~e~~|0.73<br> ~~**e**~~<br>~~e~~|0.95<br>~~**e**e~~||VDDD= 1.8 V, Buck ON, max at 60 °C|
Document Number: 002-24085 Rev. *A
Page 24 of 59
**CYBLE-416045-02**
**Table 10. Power Supply Range, CPU Current, and Transition Time Specifications** (continued)
|**Parameter**<br>~~es~~|**Description**<br>~~en~~|**Min**<br>~~en~~<br>~~rs~~|**Typ**<br>~~en~~<br>~~rs~~|**Max**<br>~~en~~|**Unit**<br>~~en~~|**Details/Conditions**<br>~~en~~|
|---|---|---|---|---|---|---|
|**Cortex-M4. Sleep Mode**<br>~~esen~~<br>~~rs~~|||||||
|IDD21<br>~~a a~~|CM4 Sleep 50 MHz, CM0+ Sleep 25 MHz. With<br>IMO and FLL<br>~~a~~|–|0.76|1.1|mA<br>~~EE~~|VDDD= 3.3 V, Buck ON, max at 60 °C<br>~~Po~~|
|||–|1.1<br>~~EE~~|1.4<br>~~EE~~||VDDD= 1.8 V, Buck ON, max at 60 °C<br>~~Po~~<br>~~EE~~|
|IDD22<br>~~ep~~|CM4 Sleep 8 MHz, CM0+ Sleep 8 MHz. With IMO<br>~~ep~~|–<br>~~ep~~|0.42<br>~~ep~~<br>~~EE~~|0.65<br>~~ep~~<br>~~EE~~|mA<br>~~ep~~<br>~~EE~~|VDDD= 3.3 V, Buck ON, max at 60 °C<br>~~ep~~<br>~~EE~~|
|||–<br>~~ep~~|0.59<br>~~ep~~<br>~~EE~~|0.8<br>~~ep~~<br>~~EE~~||VDDD= 1.8 V, Buck ON, max at 60 °C<br>~~ep~~<br>~~EE~~|
|**Cortex-M0+. Sleep Mode**<br>~~ep~~<br>~~EE~~|||||||
|IDD23<br>~~a~~|CM4 Off, CM0+ Sleep 25 MHz. With IMO and FLL<br>~~ee~~|–<br>~~ee~~|0.62<br><br>~~ee~~|0.9<br><br>~~ee~~|mA<br>|VDDD= 3.3 V, Buck ON, max at 60 °C<br>~~PO~~|
|||–<br>~~ee~~|0.88<br><br>~~ee~~|1.1<br><br>~~ee~~||VDDD= 1.8 V, Buck ON, max at 60 °C<br>~~PO~~|
|IDD24<br>~~ee~~|CM4 Off, CM0+ Sleep 8 MHz. With IMO<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~|0.41<br>~~ee~~<br>~~ee~~|0.6<br>~~ee~~<br>~~ee~~|mA<br>~~ee~~|VDDD= 3.3 V, Buck ON, max at 60 °C<br>~~ee~~|
|||–<br>~~ee~~|0.58<br>~~ee~~|0.8<br>~~ee~~||VDDD= 1.8 V, Buck ON, max at 60 °C<br>~~ee~~|
|**Cortex-M4. Ultra Low-Power Active(ULPA) Mode**|||||||
|IDD25<br>~~a~~<br>~~ee~~|Execute from Flash. CM4 ULPA 8 MHz, CM0+<br>ULPS 8 MHz. With IMO. While(1)<br>~~ee~~|–<br>~~ee~~|0.52<br>~~ee~~|0.75<br>~~ee~~|mA<br>~~ee~~|VDDD= 3.3 V, Buck ON, max at 60 °C<br>~~Po~~<br>~~ee~~|
|||–<br>~~ee~~|0.76<br>~~ee~~|1<br>~~ee~~||VDDD= 1.8 V, Buck ON, max at 60 °C<br>~~Po~~<br>~~ee~~|
|IDD26<br>~~ee~~|Execute from Cache. CM4 ULPA 8 MHz, CM0+<br>ULPS 8 MHz. With IMO. Dhrystone<br>~~ee~~|–<br>~~ee~~|0.54<br>~~ee~~|0.76<br>~~ee~~|mA<br>~~ee~~|VDDD= 3.3 V, Buck ON, max at 60 °C<br>~~ee~~|
|||–<br>~~ee~~|0.78<br>~~ee~~|1<br>~~ee~~||VDDD= 1.8 V, Buck ON, max at 60 °C<br>~~ee~~|
|**Cortex-M0+. Ultra Low-Power Active(ULPA) Mode**<br>~~ee~~<br>~~ee~~<br>~~PO~~<br>~~ee~~|||||||
|IDD27<br>~~ee~~<br>~~ef~~|Execute from Flash. CM4 OFF, CM0+ ULPA 8<br>MHz. With IMO. While (1)<br>~~ee~~<br>~~ef~~|–<br>~~ee~~|0.51<br>~~ee~~|0.75<br>~~ee~~|mA<br>~~ee~~|VDDD= 3.3 V, Buck ON, max at 60 °C<br>~~PO~~<br>~~ee~~|
|||–<br>~~ee~~|0.75<br>~~ee~~|1<br>~~ee~~||VDDD= 1.8 V, Buck ON, max at 60 °C<br>~~PO~~<br>~~ee~~|
|IDD28<br>~~ee~~<br>~~ef~~|Execute from Cache. CM4 OFF, CM0+ ULPA 8<br>MHz. With IMO. Dhrystone<br>~~ee~~<br>~~ef~~|–<br>~~ee~~<br>~~EE~~|0.48<br>~~ee~~<br>~~EE~~|0.7<br>~~ee~~<br>~~EE~~|mA<br> ~~ee~~<br>~~EE~~|VDDD= 3.3 V, Buck ON, max at 60 °C<br>~~PO~~<br>~~ee~~<br>|
|||–<br>~~ee~~<br>~~EE~~|0.7<br>~~ee~~<br>~~EE~~|0.95<br>~~ee ~~<br>~~EE~~||VDDD= 1.8 V, Buck ON, max at 60 °C<br>~~PO~~<br>~~ee~~<br>|
|**Cortex-M4. Ultra Low-Power Sleep (ULPS) Mode**<br>~~Po~~<br>~~ae~~<br>~~ereeece~~|||||||
|IDD29<br>~~ae~~|CM4 ULPS 8 MHz, CM0 ULPS 8 MHz. With IMO<br>~~er~~|–<br><br>~~er~~|0.4<br><br>~~eee~~|0.6<br><br>~~eee~~|mA<br><br>~~ce~~|VDDD= 3.3 V, Buck ON, max at 60 °C<br>~~Po~~<br>~~ce~~|
|||–<br><br>~~er~~|0.57<br><br>~~eee~~|0.8<br><br>~~eee~~||VDDD= 1.8 V, Buck ON, max at 60 °C<br>~~Po~~<br>~~ce~~|
|**Cortex-M0+. Ultra Low-Power Sleep (ULPS) Mode**<br>~~Po~~<br>~~ae~~<br>~~er eeece~~<br>~~PO~~<br>~~—~~<br>~~=~~<br>~~a~~|||||||
|IDD31<br>~~—=~~<br>~~a~~|CM4 Off, CM0+ ULPS 8 MHz. With IMO.<br>~~=~~|–<br>~~=~~|0.39<br>~~=~~|0.6<br>~~=~~<br>~~=~~|mA<br>~~=~~|VDDD= 3.3 V, Buck ON, max at 60 °C<br>~~PO~~<br>~~=~~|
|||–<br>~~=~~|0.56<br>~~=~~|0.8<br>~~=~~<br>~~=~~||VDDD= 1.8 V, Buck ON, max at 60 °C<br>~~PO~~<br>~~=~~|
|**Deep Sleep Mode**<br>~~PO~~<br>~~—=~~<br>~~=~~<br>~~a~~<br>~~te~~<br>~~ee~~<br>~~a~~|||||||
|IDD33A<br>~~—~~<br>~~a~~<br>~~a~~|With internal Buck enabled and 64K SRAM<br>retention<br><br>~~te~~<br>|–<br><br>~~te~~<br>|7<br><br>|–<br><br>~~=~~<br>~~ee~~<br>|µA<br><br>~~ee~~<br>|Max value is at 85 °C<br>~~PO~~<br><br>|
|IDD33A_B<br>~~a~~<br>~~ee~~|With internal Buck enabled and 64K SRAM<br>retention<br>~~te~~<br>~~ee~~|–<br>~~te~~<br>~~ee~~|7<br>~~ee~~|–<br>~~ee~~<br>~~ee~~|µA<br>~~ee~~<br>~~ee~~|Max value is at 60 °C<br>~~ee~~|
|IDD33B<br><br>~~ee~~|With internal Buck enabled and 256K SRAM<br>retention<br>~~ee~~|–<br>~~ee~~<br>~~ee~~|9<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~|µA<br>~~ee~~<br>~~ee~~|Max value is at 85 °C<br>~~ee~~|
|IDD33B_B<br><br>~~ee~~<br>~~a ee~~|With internal Buck enabled and 256K SRAM<br>retention<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~<br>~~ee~~|9<br>~~ee~~<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~<br>~~ee~~|µA<br>~~ee~~<br>~~ee~~<br>~~ee~~|Max value is at 60 °C<br>~~ee~~<br>~~ee~~|
|**Hibernate Mode**<br>~~a ee~~<br>~~ee ee~~<br>~~eea~~<br>~~rsrdSs~~|||||||
|IDD34<br>~~ee~~|VDDD= 1.8 V<br>~~a~~|–<br>~~rs~~|300<br>~~rd~~|–<br>~~Ss~~|nA<br>~~Ss~~|No clocks running|
|IDD34A<br>~~ee~~<br>~~ee~~|VDDD= 3.3 V<br>~~a~~<br>~~ee~~|–<br>~~rs ~~<br>~~ee~~|800<br> ~~rd ~~<br>~~ee~~|–<br> ~~Ss~~<br>~~ee~~|nA<br>~~Ss~~<br>~~ee~~|No clocks running<br>~~ee~~|
|**Power Mode Transition Times**<br>~~ee~~<br>~~a~~<br>~~rs~~<br>~~rs~~<br>~~rs~~|||||||
|TLPACT_ACT<br>~~ee~~<br>~~a~~<br>~~a~~|Low-Power Active to Active transition time<br>~~ee~~<br>~~rs~~<br>~~rs rs~~|–<br>~~ee~~<br>~~rs~~<br>~~rs~~|–<br>~~ee~~<br>~~rs~~<br>~~rs~~|35<br>~~ee~~|µs<br>~~ee~~|IncludingPLL lock time<br>~~ee~~|
|TDS_LPACT<br>~~a~~<br>~~a~~<br>~~es~~<br>~~a~~|DeepSleepto LP Active transition time<br>~~rs~~<br>~~rs rs~~<br>~~DD~~<br>|–<br>~~rs~~<br>~~rs~~<br>~~DD~~<br>|–<br>~~rs~~<br>~~rs~~<br>~~DD~~<br>~~rs~~<br>|25<br>~~DD~~<br>|µs<br>~~DD~~<br>|Guaranteed bydesign<br>~~DD~~<br>|
|TDS_ACT<br>~~a~~<br>~~es~~<br>~~a~~|DeepSleepto Active transition time<br>~~rs rs~~<br>~~DD~~<br>|–<br>~~rs ~~<br>~~DD~~<br><br>~~rr~~|–<br> ~~rs~~<br>~~DD~~<br>~~rs~~<br><br>~~rn~~|25<br>~~DD~~<br>|µs<br>~~DD~~<br>|Guaranteed bydesign<br>~~DD~~<br>|
|THIB_ACT<br>~~es~~<br>~~a es~~|Hibernate to Active transition time<br>~~DD~~<br>~~es~~|–<br>~~DD~~<br>~~es~~<br>~~rr~~|500<br>~~DD~~<br>~~rs~~<br>~~es~~<br>~~rn~~|–<br>~~DD~~<br>~~es~~|µs<br>~~DD~~<br>~~es~~|IncludingPLL lock time<br>~~DD~~<br>~~es~~|
Document Number: 002-24085 Rev. *A
Page 25 of 59
**CYBLE-416045-02**
## _Module Level Power Consumption_
Test Condition: VDDD = 3.3 V, Execute from Cache, WCO Enable
**Table 11. Module Level Power Consumption**
|**Test Items**<br>~~qe~~|**Specification (1.1 V LDO)**<br>~~es~~<br>~~qe~~|**Specification (1.1 V LDO)**<br>~~es~~<br>~~qe~~|**Specification (1.1 V Buck)**<br>~~es~~<br>~~qe~~|**Specification (1.1 V Buck)**<br>~~es~~<br>~~qe~~|**Condition**<br>~~qe~~|
|---|---|---|---|---|---|
||**Typ**<br>~~qe~~|**Max**<br>~~qe~~|**Typ**<br>~~qe~~|**Max**<br>~~qe~~||
|**CM0 Power Mode Transition**<br>~~pe~~<br>~~eG~~<br>~~GeOG~~||||||
|Active<br>~~pe~~<br>~~eG~~|7.7 mA<br>~~pe~~<br>~~eG~~|8.2 mA<br>~~pe~~<br>~~Ge~~|3.8 mA<br>~~pe~~<br>~~OG~~|4.5 mA<br>~~pe~~<br>~~OG~~|CM4 Off, CM0+ Active 100 MHz<br>~~pe~~<br>~~OG~~|
|Sleep<br>~~eG~~<br>~~GG~~<br>~~eG~~|2.57 mA<br>~~eG~~<br>~~GG~~<br>~~eG~~|3.2 mA<br>~~Ge ~~<br>~~GG ~~<br>~~Ge~~|1.3 mA<br> ~~OG~~<br> ~~OO~~<br>~~OC~~|2 mA<br>~~OG~~<br>~~OO~~<br>~~OC~~|CM4 Off, CM0+ Sleep 50 MHz<br>~~OG~~<br>~~OO~~<br>~~OC~~|
|Low-Power Active<br>~~eG~~<br>~~eG~~|1.62 mA<br>~~eG~~<br>~~eG~~|2.4 mA<br>~~Ge~~<br>~~Ge~~|0.8 mA<br>~~OC~~<br>~~GF~~|1.4 mA<br>~~OC~~<br>~~GF~~|CM4 Off, CM0+ LPA 8 MHz<br>~~OC~~<br>~~GF~~|
|Low-Power Sleep<br>~~eG~~<br>~~eG~~|1.29 mA<br>~~eG~~<br>~~eG~~|2 mA<br>~~Ge ~~<br>~~Ge~~|0.64 mA<br> ~~OC~~<br>~~GF~~|1.1 mA<br>~~OC~~<br>~~GF~~|CM4 Off, CM0+ LPS 8 MHz<br>~~OC~~<br>~~GF~~|
|**CM4 Power Mode Transition**<br>~~eG~~<br>~~Ge GF~~||||||
|Active<br>~~a~~<br>~~eG~~|10.1 mA<br>~~a~~<br>~~eG~~|10.7 mA<br>~~ee~~<br>~~Ge~~|4.8 mA<br>~~ee~~<br>~~OC~~|5.8 mA<br>~~OC~~|CM4 Active 100 MHz, CM0+ Sleep 100<br>MHz<br>~~OC~~|
|Sleep<br>~~eG~~<br>~~eG~~|2.9 mA<br>~~eG~~<br>~~eG~~|3.5 mA<br>~~Ge~~<br>~~Ge~~|1.5 mA<br>~~OC~~<br>~~GC~~|2.2 mA<br>~~OC~~<br>~~GC~~|CM4 Sleep 100 MHz, CM0+ Sleep 25 MHz<br>~~OC~~<br>~~GC~~|
|Low-Power Active<br>~~eG~~<br>~~eG~~<br>~~eG~~|1.77 mA<br>~~eG~~<br>~~eG~~<br>~~eG~~|2.5 mA<br>~~Ge ~~<br>~~Ge~~<br>~~Ge~~|0.9 mA<br> ~~OC~~<br>~~GC~~<br>~~GF~~|1.5 mA<br>~~OC~~<br>~~GC~~<br>~~GF~~|CM4 LPA 8 MHz, CM0+ Sleep 8 MHz<br>~~OC~~<br>~~GC~~<br>~~GF~~|
|Low-Power Sleep<br>~~eG~~<br>~~eG~~|1.31 mA<br>~~eG~~<br>~~eG~~|2.1 mA<br>~~Ge ~~<br>~~Ge~~|0.65 mA<br> ~~GC~~<br>~~GF~~|1.1 mA<br>~~GC~~<br>~~GF~~|CM4 LPS 8 MHz, CM0+ LPS 8 MHz<br>~~GC~~<br>~~GF~~|
|**BLE RF Current (DIRECT_TEST_MODE)**<br>~~eG~~<br>~~Ge GF~~<br>~~pe~~<br>~~eG~~<br>~~GeOG~~||||||
|TX (0dBm, 1 Mbps)<br>~~pe~~<br>~~eG~~|10 mA<br>~~pe~~<br>~~eG~~|~~pe~~<br>~~Ge~~|5.7 mA<br>~~pe~~<br>~~OG~~|~~pe~~<br>~~OG~~|HCI Command<br>~~pe~~<br>~~OG~~|
|TX (0dBm, 2 Mbps)<br>~~eG~~<br>~~GG~~<br>~~eG~~|10 mA<br>~~eG~~<br>~~GG~~<br>~~eG~~|~~Ge ~~<br>~~GG ~~<br>~~Ge~~|5.7 mA<br> ~~OG~~<br> ~~OO~~<br>~~OC~~|~~OG~~<br>~~OO~~<br>~~OC~~|~~OG~~<br>~~OO~~<br>~~OC~~|
|RX (1 Mbps)<br>~~eG~~<br>~~eG~~|11 mA<br>~~eG~~<br>~~eG~~|~~Ge~~<br>~~Ge~~|6.7 mA<br>~~OC~~<br>~~GF~~|~~OC~~<br>~~GF~~|HCI Command<br>~~OC~~<br>~~GF~~|
|RX (2 Mbps)<br>~~eG~~<br>~~eG~~|11.3 mA<br>~~eG~~<br>~~eG~~|~~Ge ~~<br>~~Ge~~|7 mA<br> ~~OC~~<br>~~GF~~|~~OC~~<br>~~GF~~|~~OC~~<br>~~GF~~|
|**System Level BLE (System_Level)**<br>~~eG~~<br>~~Ge GF~~<br>~~PR~~||||||
|**Test Items**<br>~~yee~~<br>~~eG~~|**PILO (1.1 V Buck)**<br>~~es~~<br>~~yee~~||**WCO (1.1 V Buck)**<br>~~es~~<br>~~yee~~||**Condition**<br>~~yee~~<br>~~GC~~|
||**Typ**<br>~~yee~~<br>~~eG~~|**Max**<br>~~yee~~<br>~~Ge~~|**Typ**<br>~~yee~~<br>~~GC~~|**Max**<br>~~yee~~<br>~~GC~~||
|Deep Sleep<br>~~eG~~<br>~~eG~~|90 µA<br>~~eG~~<br>~~eG~~|120 µA<br>~~Ge~~<br>~~Ge~~|7 µA<br>~~GC~~<br>~~OC~~|14 µA<br>~~GC~~<br>~~OC~~|~~GC~~<br>~~OC~~|
|Adv 1.28s interval<br>~~eG~~<br>~~eG~~|80 µA<br>~~eG~~<br>~~eG~~|121 µA<br>~~Ge ~~<br>~~Ge~~|21 µA<br> ~~GC~~<br>~~OC~~|28 µA<br>~~GC~~<br>~~OC~~|32 bytes,0 dBm, 3.3 V, Buck<br>~~GC~~<br>~~OC~~|
|300 ms connection<br>interval<br>~~eG~~<br>~~a~~<br>~~eG~~|170 µA<br>~~eG~~<br>~~eG~~|305 µA<br>~~Ge ~~<br>~~Ge~~|28 µA<br> ~~OC~~<br>~~GC~~|34 µA<br>~~OC~~<br>~~GC~~|0 byte,0 dBm, 3.3 V, Buck<br>~~OC~~<br>~~GC~~|
|1s connection interval<br>~~a~~<br>~~eG~~|75 µA<br>~~eG~~|106 µA<br>~~Ge~~|18 µA<br>~~GC~~|23 µA<br>~~GC~~|~~GC~~|
|4s connection interval<br>~~eG~~<br>~~GG~~<br>~~eG~~|75 µA<br>~~eG~~<br>~~GG~~<br>~~eG~~|106 µA<br>~~Ge ~~<br>~~GG ~~<br>~~Ge~~|14 µA<br> ~~GC~~<br> ~~OO~~<br>~~GG~~|19 µA<br>~~GC~~<br>~~OO~~<br>~~GG~~|~~GC~~<br>~~OO~~<br>~~GG~~|
|Hibernate<br>~~eG~~|1.2 µA<br>~~eG~~|1.8 µA<br>~~Ge~~|2.0 µA<br>~~GG~~|2.3 µA<br>~~GG~~|~~GG~~|
## _XRES_
## **Table 12. XRES**
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|**XRES (Active Low) Specifications**|||||||
|**XRES AC Specifications**|||||||
|TXRES_ACT|POR or XRES release to active transition time|–|750|–|µs|Normal mode, 50 MHz M0+|
|TXRES_PW|XRES Pulse width|5|–|–|µs|–|
## **Notes**
6. Cypress-supplied software wakeup routines take approximately 100 CPU clock cycles after hardware wakeup (the 25 µs) before transition to Application code. With an 8-MHz CPU clock (LP Active), the time before user code executes is 25 + 12.5 = 37.5 µs.
7. Cypress-supplied software wakeup routines take approximately 100 CPU clock cycles after hardware wakeup (the 25 µs) before transition to Application code. With a 25-MHz CPU clock (FLL), the time before user code executes is 25 + 4 = 29 µs. With a 100-MHz CPU clock, the time is 25 + 1 = 26 µs.
Document Number: 002-24085 Rev. *A
Page 26 of 59
**CYBLE-416045-02**
## **Table 12. XRES** (continued)
|**Parameter**<br>|**Description**<br>|**Min**<br>|**Typ**<br>|**Max**<br>|**Unit**<br>|**Details/Conditions**<br>~~]~~|
|---|---|---|---|---|---|---|
|**XRES DC Specifications**<br>~~a]~~|||||||
|TXRES_IDD<br><br>~~a~~|IDDwhen XRES asserted<br><br>~~a~~|–<br><br>~~a~~|300<br><br>~~a~~|–<br><br>~~a~~|nA<br><br>~~a~~|VDDD= 1.8 V<br>~~]~~<br>~~a~~|
|TXRES_IDD_1<br>~~a~~<br>~~a~~|IDDwhen XRES asserted<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|800<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|nA<br>~~a~~<br>~~a~~|VDDD= 3.3 V<br>~~a~~<br>~~a~~|
|VIH<br>~~a~~|Input voltage high threshold<br>~~a~~|0.7 * VDD<br>~~a~~|–<br>~~a~~|–<br>~~a~~|V<br>~~a~~|CMOS Input<br>~~a~~|
|VIL<br>~~a~~|Input voltage low threshold<br>~~a~~<br>~~a~~|–<br>~~a~~|–<br>~~a~~|0.3* VDD<br>~~a~~|V<br>~~a~~|CMOS Input<br>~~a~~|
|CIN<br>~~a~~<br>~~a~~|Input capacitance<br>~~a~~<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|3<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|pF<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|
|VHYSXRES<br>~~a~~|Input voltage hysteresis<br>~~a~~|–<br>~~a~~|100<br>~~a~~|–<br>~~a~~|mV<br>~~a~~|–<br>~~a~~|
|IDIODE<br>~~a~~|Current through protection diode to VDD/VSS<br>~~a~~|–<br>~~a~~|–<br>~~a~~|100<br>~~a~~|µA<br>~~a~~|–<br>~~a~~|
## **Table 13. GPIO Specifications**
|**Parameter**<br>~~a~~|**Description**<br>~~a~~|**Min**<br>~~a~~|**Typ**<br>~~a~~|**Max**<br>~~a~~|**Unit**<br>~~a~~|**Details/Conditions**<br>~~a~~|
|---|---|---|---|---|---|---|
|**GPIO DC Specifications**<br>~~a~~<br>~~]~~|||||||
|VIH<br>~~a~~<br>~~a~~<br>~~a~~|Input voltage high threshold<br>~~a~~<br>|0.7 * VDD<br>~~a~~<br>|–<br>~~a~~<br>|–<br>~~a~~<br>~~ee~~<br>|V<br>~~a~~<br>~~ee~~<br>|CMOS Input<br>~~a~~<br>|
|IIHS<br>~~a~~<br>~~a~~<br>~~a~~|Input current when Pad > VDDIO for OVT<br>inputs<br>~~ee~~<br>|–<br>~~ee~~<br>|–<br>~~ee~~<br>|10<br>~~ee~~<br>~~ee~~<br>|µA<br>~~ee~~<br>~~ee~~<br>|Per I2C Spec<br>~~ee~~<br>|
|VIL<br>~~a~~<br>~~a~~|Input voltage low threshold<br>~~ee~~<br>|–<br>~~ee~~<br>|–<br>~~ee~~<br>|0.3*VDD<br>~~ee~~<br>~~ee~~<br>|V<br>~~ee~~<br>~~ee~~<br>|CMOS Input<br>~~ee~~<br>|
|VIH<br>~~aa~~|LVTTL input, VDD< 2.7 V<br>~~a~~|0.7 * VDD<br>~~a~~|–<br>~~a~~|–<br>~~ee~~<br>~~a~~|V<br>~~ee~~<br>~~a~~|–<br>~~a~~|
|VIL<br>~~a~~|LVTTL input, VDD< 2.7 V<br>~~a~~|–<br>~~a~~|–<br>~~a~~|0.3*VDD<br>~~a~~|V<br>~~a~~|–<br>~~a~~|
|VIH<br>~~a~~<br>~~a~~|LVTTL input, VDD 2.7 V<br>~~a~~<br>~~a~~|2.0<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|V<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|
|VIL<br>~~a~~<br>~~a~~|LVTTL input, VDD 2.7 V<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|0.8<br>~~a~~<br>~~a~~|V<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|
|VOH<br>~~a~~|Output voltage high level<br>~~a~~|VDD- 0.5<br>~~a~~|–<br>~~a~~|–<br>~~a~~|V<br>~~a~~|IOH= 8 mA<br>~~a~~|
|VOL<br>~~a~~<br>~~a~~|Output voltage low level<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|0.4<br>~~a~~<br>~~a~~|V<br>~~a~~<br>~~a~~|IOL= 8 mA<br>~~a~~<br>~~a~~|
|RPULLUP<br>~~a~~<br>~~a~~|Pull-up resistor<br>~~a~~<br>~~a~~|3.5<br>~~a~~<br>~~a~~|5.6<br>~~a~~<br>~~a~~|8.5<br>~~a~~<br>~~a~~|k<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|
|RPULLDOWN<br>~~a~~|Pull-down resistor<br>~~a~~|3.5<br>~~a~~|5.6<br>~~a~~|8.5<br>~~a~~|k<br>~~a~~|–<br>~~a~~|
|IIL<br>~~a~~<br>~~a~~|Input leakage current (absolute value)<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|2<br>~~a~~<br>~~a~~|nA<br>~~a~~<br>~~a~~|25 °C, VDD= 3.0 V<br>~~a~~<br>~~a~~|
|IIL_CTBM<br>~~a~~|Input leakage on CTBm input pins<br>~~a~~|–<br>~~a~~|–<br>~~a~~|4<br>~~a~~|nA<br>~~a~~|–<br>~~a~~|
|CIN<br>~~a~~|Input Capacitance<br>~~a~~|–<br>~~a~~|–<br>~~a~~|5<br>~~a~~|pF<br>~~a~~|–<br>~~a~~|
|VHYSTTL<br>~~a~~<br>~~a~~|Input hysteresis LVTTL VDD> 2.7 V<br>~~a~~<br>~~a~~|100<br>~~a~~<br>~~a~~|0<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|mV<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|
|VHYSCMOS<br>~~a~~|Input hysteresis CMOS<br>~~a~~|0.05 * VDD<br>~~a~~|–<br>~~a~~|–<br>~~a~~|mV<br>~~a~~|–<br>~~a~~|
|IDIODE<br>~~a~~|Current through protection diode to VDD/VSS<br>~~a~~|–<br>~~a~~|–<br>~~a~~|100<br>~~a~~|µA<br>~~a~~|–<br>~~a~~|
|ITOT_GPIO<br>~~a~~<br>~~a~~|Maximum Total Source or Sink Chip Current<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|200<br>~~a~~<br>~~a~~|mA<br>~~a~~<br>~~a~~|~~a~~<br>~~a~~|
|**GPIO AC Specifications**<br>~~a~~<br>~~a]~~|||||||
|TRISEF<br>~~a~~<br>~~a~~|Rise time in Fast Strong mode. 10% to 90%<br>of VDD<br>~~ee~~<br>~~es~~|–<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~|2.5<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~|Cload= 15 pF, 8 mA drive<br>strength<br>~~ee~~|
|TFALLF<br>~~a~~|Fall time in Fast Strong mode. 10% to 90% of<br>VDD<br>~~es~~|–<br>~~ee~~|–<br>~~ee~~|2.5<br>~~ee~~|ns|Cload= 15 pF, 8 mA drive<br>strength|
|TRISES_1<br>~~a~~|Rise time in Slow Strong mode. 10% to 90%<br>of VDD<br>~~es~~|52<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~|142<br>~~ee~~<br>~~eee~~|ns<br>~~eee~~|Cload= 15 pF, 8 mA drive<br>strength, VDD 2.7 V<br>~~eee~~|
|TRISES_2<br>~~ee~~|Rise time in Slow Strong mode. 10% to 90%<br>of VDD<br>~~ee~~|48<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~|102<br>~~ee~~<br>~~eee~~|ns<br>~~ee~~<br>~~eee~~|Cload= 15 pF, 8 mA drive<br>strength, 2.7 V < VDD <br>3.6 V<br>~~ee~~<br>~~eee~~|
Document Number: 002-24085 Rev. *A
Page 27 of 59
**CYBLE-416045-02**
**Table 13. GPIO Specifications** (continued)
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|TFALLS_1<br>~~a~~|Fall time in Slow Strong mode. 10% to 90%<br>of VDD<br>|44<br>|–<br>~~ee~~<br>|211<br>~~ee~~<br>|ns<br>|Cload= 15 pF, 8 mA drive<br>strength, VDD 2.7 V<br>|
|TFALLS_2<br>~~ee~~<br>~~a~~<br>~~a~~|Fall time in Slow Strong mode. 10% to 90%<br>of VDD<br>~~ee~~<br><br>|42<br>~~ee~~<br><br>|–<br>~~ee~~<br>~~ee~~<br><br>|93<br>~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|ns<br>~~ee~~<br><br>~~ee~~<br>|Cload= 15 pF, 8 mA drive<br>strength, 2.7 V < VDD <br>3.6 V<br>~~ee~~<br><br>|
|TFALL_I2C<br>~~ee~~<br>~~a~~<br>~~a~~<br>~~a~~|Fall time (30% to 70% of VDD) in Slow Strong<br>mode<br>~~ee~~<br>~~ee~~<br><br>|20*VDDIO/5.5<br>~~ee~~<br>~~ee~~<br><br>|–<br>~~ee~~<br>~~ee~~<br>~~ee~~<br><br>|250<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|ns<br>~~ee~~<br>~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|Clload= 10 pF to 400 pF,<br>8-mA drive strength<br>~~ee~~<br>~~ee~~<br><br>|
|FGPIOUT1<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~|GPIO Fout. Fast Strong mode<br>~~ee~~<br>~~ee~~<br><br>|–<br>~~ee~~<br>~~ee~~<br><br>|–<br>~~ee~~<br>~~ee~~<br>~~ee~~<br><br>|100<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|MHz<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|90/10%, 15-pF load,<br>60/40 duty cycle<br>~~ee~~<br>~~ee~~<br><br>|
|FGPIOUT2<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~|GPIO Fout; Slow Strong mode<br>~~ee~~<br>~~ee~~<br><br>|–<br>~~ee~~<br>~~ee~~<br><br>|–<br>~~ee~~<br>~~ee~~<br><br>|16.7<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|MHz<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|90/10%, 15-pF load,<br>60/40 duty cycle<br>~~ee~~<br>~~ee~~<br><br>|
|FGPIOUT3<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~|GPIO Fout; Fast Strong mode<br>~~ee~~<br>~~ee~~<br><br>|–<br>~~ee~~<br>~~ee~~<br><br>|–<br>~~ee~~<br>~~ee~~<br><br>|7<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|MHz<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|90/10%, 25-pF load,<br>60/40 duty cycle<br>~~ee~~<br>~~ee~~<br><br>|
|FGPIOUT4<br>~~a~~<br>~~a~~<br>~~a~~|GPIO Fout; Slow Strong mode<br>~~ee~~<br>~~ee~~<br>|–<br>~~ee~~<br>~~ee~~<br>|–<br>~~ee~~<br>~~ee~~<br>|3.5<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br><br>~~ee~~|MHz<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br><br>~~ee~~|90/10%, 25-pF load,<br>60/40 duty cycle<br>~~ee~~<br>~~ee~~<br>|
|FGPIOIN<br>~~a~~<br>~~a~~|GPIO input operating frequency;1.71 VVDD<br>3.6 V<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~|100<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|MHz<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|90/10% VIO<br>~~ee~~<br>~~ee~~|
## **Analog Peripherals**
_Opamp_
|**Parameter**<br>~~eS~~|**Description**<br>~~a~~|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|IDD<br>~~eS ~~<br>~~a~~<br>~~ee~~|Opamp block current. No load.<br> ~~a~~|–|–|–|–|–|
|IDD_HI<br>~~a~~<br>~~ee~~|Power = HI|–|1300|1500|µA|–|
|IDD_MED<br>~~ee~~<br>~~a~~|Power = MED|–|450|600|µA|–|
|IDD_LOW<br>~~aa~~<br>~~a~~|Power = LO<br>~~a~~<br>~~ee~~|–<br>~~a~~<br>~~ee~~|250<br>~~a~~<br>~~ee~~|350<br>~~a~~<br>~~ee~~|µA<br>~~a~~<br>~~ee~~|–<br>~~a~~|
|GBW<br>~~aa~~<br>~~a~~<br>~~ee~~|Load = 20 pF, 0.1 mA<br>VDDA= 2.7 V<br>~~a~~<br>~~ee~~|–<br>~~a~~<br>~~ee~~|–<br>~~a~~<br>~~ee~~|–<br>~~a~~<br>~~ee~~|–<br>~~a~~<br>~~ee~~|–<br>~~a~~|
|GBW_HI<br>~~a~~<br>~~ee~~|Power = HI<br>~~ee ~~|6<br> ~~ee~~|–<br>~~ee~~|–<br>~~ee ~~|MHz<br> ~~ee~~|–|
|GBW_MED<br>~~ee~~<br>~~a~~|Power = MED|4|–|–|MHz|–|
|GBW_LO<br>~~aa~~<br>~~ee~~|Power = LO<br>~~a~~|–<br>~~a~~|1<br>~~a~~|–<br>~~a~~|MHz<br>~~a~~|–<br>~~a~~|
|IOUT_MAX<br>~~aa~~<br>~~ee~~|VDDA 2.7 V, 500 mV from rail<br>~~a~~|–<br>~~a~~|–<br>~~a~~|–<br>~~a~~|–<br>~~a~~|–<br>~~a~~|
|IOUT_MAX_HI<br>~~a~~<br>~~ee~~<br>~~a~~|Power = HI<br>~~a~~|–<br>~~a~~|–<br>~~a~~|–<br>~~a~~|mA<br>~~a~~|–<br>~~a~~|
|IOUT_MAX_MID<br>~~aa~~<br>~~ee~~|Power = MID<br>~~a~~|10<br>~~a~~|–<br>~~a~~|–<br>~~a~~|mA<br>~~a~~|–<br>~~a~~|
|IOUT_MAX_LO<br>~~aa~~<br>~~ee~~|Power = LO<br>~~a~~|–<br>~~a~~|5<br>~~a~~|–<br>~~a~~|mA<br>~~a~~|–<br>~~a~~|
|IOUT<br>~~a~~<br>~~ee~~<br>~~a~~|VDDA= 1.71 V, 500 mV from rail<br>~~a~~|–<br>~~a~~|–<br>~~a~~|–<br>~~a~~|~~a~~|–<br>~~a~~|
|IOUT_MAX_HI<br>~~aa~~<br>~~ee~~|Power = HI<br>~~a~~|4<br>~~a~~|–<br>~~a~~|–<br>~~a~~|mA<br>~~a~~|–<br>~~a~~|
|IOUT_MAX_MID<br>~~aa~~<br>~~ee~~|Power = MID<br>~~a~~|4<br>~~a~~|–<br>~~a~~|–<br>~~a~~|mA<br>~~a~~|–<br>~~a~~|
|IOUT_MAX_LO<br>~~a~~<br>~~ee~~<br>~~a~~|Power = LO<br>~~a~~|–<br>~~a~~|2<br>~~a~~|–<br>~~a~~|mA<br>~~a~~|–<br>~~a~~|
|VIN<br>~~aa~~<br>~~ee~~|Input voltage range<br>~~a~~|0<br>~~a~~|–<br>~~a~~|VDDA-0.2<br>~~a~~|V<br>~~a~~|–<br>~~a~~|
|VCM<br>~~a~~<br>~~ee~~|Input common mode voltage<br>~~a~~|0<br>~~a~~|–<br>~~a~~|VDDA-0.2<br>~~a~~|V<br>~~a~~|–<br>~~a~~|
|VOUT<br>~~a~~<br>~~ee~~<br>~~a~~|VDDA 2.7 V<br>~~a~~|–<br>~~a~~|–<br>~~a~~|–<br>~~a~~|~~a~~|–<br>~~a~~|
|VOUT_1<br>~~aa~~|Power = HI, Iload= 10 mA<br>~~a~~|0.5<br>~~a~~|–<br>~~a~~|VDDA-0.5<br>~~a~~|V<br>~~a~~|–<br>~~a~~|
|VOUT_2<br>~~a~~|Power = HI, Iload= 1 mA<br>~~a~~|0.2<br>~~a~~|–<br>~~a~~|VDDA-0.2<br>~~a~~|V<br>~~a~~|–<br>~~a~~|
Document Number: 002-24085 Rev. *A
Page 28 of 59
**CYBLE-416045-02**
**Table 14. Opamp Specifications** (continued)
|**Parameter**<br>~~eS~~<br>~~eS~~|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|VOUT_3<br>~~eS~~<br>~~eS~~|Power = MED, Iload= 1 mA|0.2|–|VDDA-0.2|V|–|
|VOUT_4<br>~~eS~~<br>~~a~~|Power = LO, Iload= 0.1 mA|0.2|–|VDDA-0.2|V|–|
|VOS_UNTR<br>~~a~~<br>~~a~~<br>~~ee~~|Offset voltage, untrimmed|–|–|–|mV|–|
|VOS_TR<br>~~ee~~|Offset voltage, trimmed|–|±0.5|–|mV|High mode, 0.2 to VDDA- 0.2|
|VOS_TR<br>~~ee~~<br>~~a~~|Offset voltage, trimmed|–|±1|–|mV|Medium mode|
|VOS_TR<br>~~a~~<br>~~a~~<br>~~es~~|Offset voltage, trimmed|–|±2|–|mV|Low mode|
|VOS_DR_UNTR<br>~~a~~<br>~~es~~|Offset voltage drift, untrimmed|–|–|–|µV/°C|–|
|VOS_DR_TR<br>~~es~~<br>~~a~~|Offset voltage drift, trimmed|–10|±3|10|µV/°C|High mode, 0.2 to VDDA- 0.2|
|VOS_DR_TR<br>~~a~~<br>~~a~~<br>~~ee~~|Offset voltage drift, trimmed<br>|–<br>|±10<br>|–<br>|µV/°C<br>|Medium mode<br>|
|VOS_DR_TR<br>~~ee~~|Offset voltage drift, trimmed<br>|–<br>|±10<br>|–<br>|µV/°C<br>|Low mode<br>|
|common-mode<br>rejection ratio (CMRR) <br>~~eea~~|DC common mode rejection ratio<br>~~a~~|67<br>~~a~~|80<br>~~a~~|–<br>~~a~~|dB<br>~~a~~|VDDD= 3.3 V<br>~~a~~|
|power supply rejection<br>ratio (PSRR)<br>~~a~~|Power supply rejection ratio at 1 kHz,<br>10-mV ripple<br>~~a~~|70<br>~~a~~|85<br>~~a~~|–<br>~~a~~|dB<br>~~a~~|VDDD= 3.3 V<br>~~a~~|
|Noise<br>~~a~~|–<br>~~a~~|–<br>~~a~~|–<br>~~a~~|–<br>~~a~~|–<br>~~a~~|–<br>~~a~~|
|VN1<br>~~a~~<br>~~a~~|Input-referred, 1 Hz - 1 GHz, power = HI<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|100<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|µVrms<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|
|VN2<br>~~a~~<br>~~ee~~<br>~~a~~|Input-referred, 1 kHz, power = HI<br>~~a~~<br>~~ee~~<br>~~ee ee~~|–<br>~~a~~<br>~~ee~~<br>~~ee~~|180<br>~~a~~<br>~~ee~~<br>~~ee~~|–<br>~~a~~<br>~~ee~~<br>~~ee~~|nV/root<br>Hz<br>~~a~~<br>~~ee~~<br>~~ee~~|–<br>~~a~~<br>~~ee~~|
|VN3<br>~~a~~<br>~~a~~|Input-referred, 10 kHz, power = HI<br>~~ee ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~|70<br>~~ee~~<br>~~ee~~|–<br>~~ee~~|nV/root<br>Hz<br>~~ee~~<br>~~ee~~|–|
|VN4<br>~~a~~<br>~~a~~<br>~~a~~|Input-referred, 100 kHz, power = HI<br>~~ee ee~~<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~<br>~~ee~~|38<br>~~ee~~<br>~~ee~~<br>~~ee~~|–<br>~~ee~~|nV/root<br>Hz<br>~~ee~~<br>~~ee~~<br>~~ee~~|–|
|CLOAD<br>~~a~~<br>~~a~~<br>~~a~~|Stable up to maximum load<br>Performance specs at 50 pF<br>~~ee ~~<br>~~ee~~<br>~~ee~~|–<br> ~~ee~~<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~<br>~~ee~~|125|pF<br>~~ee~~<br>~~ee~~<br>~~ee~~|–|
|SLEW_RATE<br>~~a~~<br>~~a~~<br>~~a~~|Output slew rate<br>~~ee ~~<br>~~ee~~<br>~~ee~~|6<br> ~~ee~~<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~<br>~~ee~~|–|V/µs<br>~~ee~~<br>~~ee~~<br>~~ee~~|Cload= 50 pF, Power = High,<br>VDDA 2.7 V|
|T_OP_WAKE<br>~~a~~<br>~~a~~<br>~~a~~|From disable to enable, no external RC<br>dominating<br>~~ee ~~<br>~~ee~~<br>~~ee~~|–<br> ~~ee~~<br>~~ee~~<br>~~ee~~|25<br>~~ee~~<br>~~ee~~<br>~~ee~~|–|µs<br>~~ee~~<br>~~ee~~<br>~~ee~~|–|
|COMP_MODE<br>~~a~~<br>~~a~~<br>~~es~~|Comparator mode; 50-mV overdrive,<br>Trise= Tfall(approx.)<br>~~ee ~~<br>~~ee~~|–<br> ~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~|–|–<br>~~ee~~<br>~~ee~~|–|
|TPD1<br>~~a~~<br>~~es~~|Response time; power = HI<br>~~ee ~~|–<br> ~~ee~~|150<br>~~ee~~|–|ns<br>~~ee~~|–|
|TPD2<br>~~es~~<br>~~a~~|Response time; power = MED|–|400|–|ns|–|
|TPD3<br>~~a~~<br>~~a~~|Response time; power = LO|–|2000|–|ns|–|
|VHYST_OP<br>~~a~~|Hysteresis|–|10|–|mV|–|
|Deep Sleep mode<br>~~ee~~|Mode 2 is lowest current range<br>Mode 1 has higher GBW<br>~~ee~~|–<br>~~ee~~|–<br>~~ee~~|–|–<br>~~ee~~|Deep Sleep mode operation:<br>VDDA 2.7 V<br>VINis 0.2 to VDDA-1.5|
|IDD_HI_M1<br>~~a~~<br>~~ee~~|Mode 1, High current<br>~~ee~~|–<br>~~ee~~|130<br>0<br>~~ee~~|1500|µA<br>~~ee~~|Typ at 25 °C|
|IDD_MED_M1<br>~~ee~~|Mode 1, Medium current<br>~~ee~~|–<br>~~ee~~|460<br>~~ee~~|600|µA<br>~~ee~~|Typ at 25 °C|
|IDD_LOW_M1<br>~~ee~~<br>~~a~~|Mode 1, Low current<br>~~ee ~~|–<br> ~~ee~~|230<br>~~ee~~|350|µA<br>~~ee~~|Typ at 25 °C|
|IDD_HI_M2<br>~~a~~<br>~~a~~|Mode 2, High current|–|120|–|µA|25 °C|
|IDD_MED_M2<br>~~a~~<br>~~a~~|Mode 2, Medium current|–|60|–|µA|25 °C|
|IDD_LOW_M2<br>~~a a~~|Mode 2, Low current<br>~~a~~|–<br>~~a~~|15<br>~~a~~|–<br>~~a~~|µA<br>~~a~~|25 °C<br>~~a~~|
|GBW_HI_M1<br>~~a a~~<br>~~a~~<br>~~ee~~|Mode 1, High current<br>~~a~~|–<br>~~a~~|4<br>~~a~~|–<br>~~a~~|MHz<br>~~a~~|25 °C<br>~~a~~|
|GBW_MED_M1<br>~~a~~<br>~~ee~~|Mode 1, Medium current|–|2|–|MHz|25 °C|
Document Number: 002-24085 Rev. *A
Page 29 of 59
**CYBLE-416045-02**
**Table 14. Opamp Specifications** (continued)
|**Parameter**<br>~~Po~~<br>~~ee~~|**Description**<br>~~Po~~|**Min**<br>~~Po~~<br>~~ts~~|**Typ**<br>~~Po~~<br>~~SD~~|**Max**<br>~~Po~~<br>~~ID~~|**Unit**<br>~~Po~~|**Details/Conditions**<br>~~Po~~|
|---|---|---|---|---|---|---|
|GBW_LOW_M1<br>~~a ey~~<br>~~ee~~<br>~~ee~~|Mode 1, Low current<br>~~ey~~<br>~~es~~|–<br>~~ey~~<br>~~ts~~<br>~~ee~~|0.5<br>~~ey~~<br>~~SD~~<br>~~ee~~|–<br>~~ey~~<br>~~ID~~<br>~~ee~~|MHz<br>~~ey~~<br>~~es~~|25 °C<br>~~ey~~|
|GBW_HI_M2<br>~~ee~~<br>~~ee~~<br>~~ee~~|Mode 2, High current<br>~~es~~<br>~~es~~|–<br>~~ts~~<br>~~ee~~<br>~~ee~~|0.5<br>~~SD~~<br>~~ee~~<br>~~ee~~|–<br>~~ID~~<br>~~ee~~<br>~~ee~~|MHz<br>~~es~~<br>~~es~~|20-pF load, no DC load 0.2 V<br>to VDDA-1.5 V|
|GBW_MED_M2<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|Mode 2, Medium current<br>~~es~~<br>~~es~~<br>~~es~~|–<br>~~ts~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.2<br>~~SD ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|–<br> ~~ID~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|MHz<br>~~es~~<br>~~es~~<br>~~es~~|20-pF load, no DC load 0.2 V<br>to VDDA-1.5 V|
|GBW_LOW_M2<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|Mode 2, Low current<br>~~es ~~<br>~~es~~<br>~~es~~<br>~~es~~|–<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.1<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|–<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|MHz<br> ~~es~~<br>~~es~~<br>~~es~~<br>~~es~~|20-pF load, no DC load 0.2 V<br>to VDDA-1.5 V|
|VOS_HI_M1<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|Mode 1, High current<br>~~es ~~<br>~~es~~<br>~~es~~<br>~~es~~|–<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|5<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|–<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|mV<br> ~~es~~<br>~~es~~<br>~~es~~<br>~~es~~|With trim 25 °C, 0.2 V to<br>VDDA-1.5 V|
|VOS_MED_M1<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|Mode 1, Medium current<br>~~es ~~<br>~~es~~<br>~~es~~<br>~~es~~|–<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|5<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|–<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|mV<br> ~~es~~<br>~~es~~<br>~~es~~<br>~~es~~|With trim 25 °C, 0.2 V to<br>VDDA-1.5 V|
|VOS_LOW_M1<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|Mode 1, Low current<br>~~es ~~<br>~~es~~<br>~~es~~<br>~~es~~|–<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|5<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|–<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|mV<br> ~~es~~<br>~~es~~<br>~~es~~<br>~~es~~|With trim 25 °C, 0.2 V to<br>VDDA-1.5 V|
|VOS_HI_M2<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|Mode 2, High current<br>~~es ~~<br>~~es~~<br>~~es~~<br>~~es~~|–<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|5<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|–<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|mV<br> ~~es~~<br>~~es~~<br>~~es~~<br>~~es~~|With trim 25 °C, 0.2 V to<br>VDDA-1.5 V|
|VOS_MED_M2<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|Mode 2, Medium current<br>~~es ~~<br>~~es~~<br>~~es~~<br>~~es~~|–<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|5<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|–<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|mV<br> ~~es~~<br>~~es~~<br>~~es~~<br>~~es~~|With trim 25 °C, 0.2 V to<br>VDDA-1.5 V|
|VOS_LOW_M2<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|Mode 2, Low current<br>~~es ~~<br>~~es~~<br>~~es~~<br>~~tn~~|–<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~tn~~|5<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~rs~~|–<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ss~~|mV<br> ~~es~~<br>~~es~~<br>~~es~~<br>~~ss~~|With trim 25 °C, 0.2 V to<br>VDDA-1.5 V|
|IOUT_HI_M1<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~a~~|Mode 1, High current<br>~~es ~~<br>~~es~~<br>~~tn~~<br>~~ry ts~~|–<br> ~~ee ~~<br>~~ee~~<br>~~tn~~<br>~~ts~~|10<br> ~~ee ~~<br>~~ee~~<br>~~rs~~<br>~~Ss~~|–<br> ~~ee ~~<br>~~ee~~<br>~~ss~~<br>~~ts~~|mA<br> ~~es~~<br>~~es~~<br>~~ss~~|Output is 0.5 V to VDDA-0.5 V|
|IOUT_MED_M1<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~ee~~|Mode 1, Medium current<br>~~es ~~<br>~~tn~~<br>~~ry ts~~<br>~~nD~~|–<br> ~~ee ~~<br>~~tn~~<br>~~ts~~<br>~~I~~|10<br> ~~ee ~~<br>~~rs~~<br>~~Ss~~<br>~~ts~~|–<br> ~~ee ~~<br>~~ss~~<br>~~ts~~<br>~~I~~|mA<br> ~~es~~<br>~~ss~~|Output is 0.5 V to VDDA-0.5 V|
|IOUT_LOW_M1<br>~~ee~~<br>~~a~~<br>~~ee~~<br>~~ee~~|Mode 1, Low current<br>~~tn~~<br>~~ry ts~~<br>~~nD~~<br>~~tn~~|–<br>~~tn ~~<br>~~ts~~<br>~~I~~<br>~~tn~~|4<br> ~~rs ~~<br>~~Ss~~<br>~~ts~~<br>~~rs~~|–<br> ~~ss~~<br>~~ts~~<br>~~I~~<br>~~ss~~|mA<br>~~ss~~<br>~~ss~~|Output is 0.5 V to VDDA-0.5 V|
|IOUT_HI_M2<br>~~ee~~<br>~~ee~~<br>~~ee~~|Mode 2, High current<br>~~nD~~<br>~~tn~~<br>~~ry~~|–<br>~~I~~<br>~~tn~~<br>~~ts~~|1<br>~~ts~~<br>~~rs~~<br>~~Ss~~|–<br>~~I~~<br>~~ss~~<br>~~**t**s~~|mA<br>~~ss~~|Output is 0.5 V to VDDA-0.5 V|
|IOUT_MED_M2<br>~~ee~~<br>~~ee~~<br>~~ee~~|Mode 2, Medium current<br>~~nD ~~<br>~~tn~~<br>~~ry~~<br>~~nD~~|–<br> ~~I ~~<br>~~tn~~<br>~~ts~~<br>~~I~~|1<br> ~~ts ~~<br>~~rs~~<br>~~Ss~~<br>~~Is~~|–<br> ~~I~~<br>~~ss~~<br>~~**t**s~~<br>~~n~~|mA<br>~~ss~~|Output is 0.5 V to VDDA-0.5 V|
|IOUT_LOW_M2<br>~~ee~~<br>~~ee~~|Mode 2, Low current<br>~~tn~~<br>~~ry~~<br>~~nD~~|–<br>~~tn ~~<br>~~ts~~<br>~~I~~|0.5<br> ~~rs ~~<br>~~Ss~~<br>~~Is~~|–<br> ~~ss~~<br>~~**t**s~~<br>~~n~~|mA<br>~~ss~~|Output is 0.5 V to VDDA-0.5 V|
Document Number: 002-24085 Rev. *A
Page 30 of 59
**CYBLE-416045-02**
**Table 15. Low-Power (LP) Comparator Specifications**
|**Parameter**<br>~~es~~|**Description**<br>~~rs~~|**Min**<br>~~(tI~~|**Typ**<br>~~tts~~|**Max**<br>~~(OU~~|**Unit**<br>~~(OU~~|**Details/Conditions**|
|---|---|---|---|---|---|---|
|**LP Comparator DC Specifications**<br>~~es~~<br>~~rs (tI~~<br>~~tts~~<br>~~(OU~~<br>~~eee~~<br>~~a~~<br>~~ee~~|||||||
|VOFFSET1<br>~~a~~<br>~~es~~|Input offset voltage for COMP1. Normal power<br>mode<br>~~ee~~<br>~~nr~~|–10<br>~~ee~~<br>~~tnt~~|–<br>~~tt es~~|10<br>~~es~~|mV<br>~~es~~|COMP0 offset is ±25 mV|
|VOFFSET2<br>~~a~~<br>~~es~~<br>~~es~~|Input offset voltage. Low-power mode<br>~~ee~~<br>~~nr~~<br>~~rr~~|–25<br>~~ee~~<br>~~tnt~~<br>~~ID~~|±12<br>~~tt es~~<br>~~I~~|25<br>~~es~~<br>~~I~~|mV<br>~~es~~<br>~~(OO~~|–|
|VOFFSET3<br>~~es~~<br>~~es~~<br>~~es~~|Input offset voltage. Ultra low-power mode<br>~~nr~~<br>~~rr~~<br>~~nr~~|–25<br>~~tnt ~~<br>~~ID~~<br>~~tnt~~|±12<br> ~~tt es~~<br>~~I~~<br>~~tt es~~|25<br>~~es~~<br>~~I~~<br>~~es~~|mV<br>~~es~~<br>~~(OO~~<br>~~es~~|–|
|VHYST1<br>~~es~~<br>~~es~~<br>~~es~~|Hysteresis when enabled in Normal mode<br>~~rr~~<br>~~nr~~<br>~~rr~~|–<br>~~ID ~~<br>~~tnt~~<br>~~ID~~|–<br> ~~I~~<br>~~tt es~~<br>~~I~~|60<br>~~I ~~<br>~~es~~<br>~~I~~|mV<br> ~~(OO~~<br>~~es~~<br>~~(OO~~|–|
|VHYST2<br>~~es~~<br>~~es~~<br>~~es~~|Hysteresis when enabled in Low-power mode<br>~~nr~~<br>~~rr~~<br>~~nr~~|–<br>~~tnt ~~<br>~~ID~~<br>~~tnt~~|–<br> ~~tt es~~<br>~~I~~<br>~~tt es~~|80<br>~~es~~<br>~~I~~<br>~~es~~|mV<br>~~es~~<br>~~(OO~~<br>~~es~~|–|
|VICM1<br>~~es~~<br>~~es~~<br>~~es~~|Input common mode voltage in Normal mode<br>~~rr~~<br>~~nr~~<br>~~ee~~|0<br>~~ID ~~<br>~~tnt~~<br>~~ee~~|–<br> ~~I~~<br>~~tt es~~|VDDIO1-0.1<br>~~I ~~<br>~~es~~|V<br> ~~(OO~~<br>~~es~~|–|
|VICM2<br>~~es~~<br>~~es~~<br>~~es~~|Input common mode voltage in Low-power<br>mode<br>~~nr~~<br>~~ee~~<br>~~se~~|0<br>~~tnt ~~<br>~~ee~~<br>~~se~~|–<br> ~~tt es~~|VDDIO1-0.1<br>~~es~~|V<br>~~es~~|–|
|VICM3<br>~~es~~<br>~~es~~<br>~~es~~|Input common mode voltage in Ultra<br>low-power mode<br>~~ee~~<br>~~se~~<br>~~se~~|0<br>~~ee~~<br>~~se~~<br>~~se~~|–|VDDIO1-0.1|V|–|
|CMRR<br>~~es~~<br>~~es~~<br>~~es~~|Common mode rejection ratio in Normal<br>power mode<br>~~se~~<br>~~se~~<br>~~nr~~|50<br>~~se~~<br>~~se~~<br>~~tnt~~|–<br>~~tt es~~|–<br>~~es~~|dB<br>~~es~~|–|
|ICMP1<br>~~es~~<br>~~es~~<br>~~es~~|Block current, Normal mode<br>~~se~~<br>~~nr~~<br>~~rr~~|–<br>~~se~~<br>~~tnt~~<br>~~ID~~|–<br>~~tt es~~<br>~~I~~|150<br>~~es~~<br>~~I~~|µA<br>~~es~~<br>~~(OO~~|–|
|ICMP2<br>~~es~~<br>~~es~~<br>~~es~~|Block current, Low-power mode<br>~~nr~~<br>~~rr~~<br>~~nr~~|–<br>~~tnt ~~<br>~~ID~~<br>~~tnt~~|–<br> ~~tt es~~<br>~~I~~<br>~~tt es~~|10<br>~~es~~<br>~~I~~<br>~~es~~|µA<br>~~es~~<br>~~(OO~~<br>~~es~~|–|
|ICMP3<br>~~es~~<br>~~es~~<br>~~es~~|Block current in Ultra low-power mode<br>~~rr~~<br>~~nr~~<br>~~rts~~|–<br>~~ID ~~<br>~~tnt~~<br>~~Itty~~|0.3<br> ~~I~~<br>~~tt es~~<br>~~tn~~|0.85<br>~~I ~~<br>~~es~~|µA<br> ~~(OO~~<br>~~es~~|–|
|ZCMP<br>~~es~~<br>~~es~~|DC input impedance of comparator<br>~~nr~~<br>~~rts~~|35<br>~~tnt ~~<br>~~Itty~~|–<br> ~~tt es~~<br>~~tn~~|–<br>~~es~~|M<br>~~es~~|–|
|**LP Comparator AC Specifications**<br>~~es~~<br>~~rts Itty tn~~<br>~~Ce~~<br>~~a~~<br>~~esee~~|||||||
|TRESP1<br>~~Ce~~<br>~~a~~<br>~~es~~|Response time, Normal mode, 100 mV<br>overdrive<br>~~Ce~~<br>~~es~~<br>~~se~~|–<br>~~Ce~~<br>~~ee~~<br>~~se~~|–<br>~~Ce~~<br>~~ee~~|100<br>~~Ce~~|ns<br>~~Ce~~|–<br>~~Ce~~|
|TRESP2<br>~~a~~<br>~~es~~<br>~~es~~|Response time, Low-power mode, 100 mV<br>overdrive<br>~~es ~~<br>~~se~~<br>~~es~~|–<br> ~~ee~~<br>~~se~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~|1000|ns|–|
|TRESP3<br>~~es~~<br>~~es~~<br>~~es~~|Response time, Ultra low-power mode, 100<br>mV overdrive<br>~~se~~<br>~~es~~<br>~~rr~~|–<br>~~se~~<br>~~ee~~<br>~~ID~~|–<br>~~ee~~<br>~~I~~|20<br>~~I~~|µs<br>~~(OO~~|–|
|T_CMP_EN1<br>~~es~~<br>~~es~~<br>~~es~~|Time from enabling to operation<br>~~es ~~<br>~~rr~~<br>~~nr~~|–<br> ~~ee~~<br>~~ID~~<br>~~Int~~|–<br>~~ee~~<br>~~I~~<br>~~tt~~|10<br>~~I~~<br>~~en~~|µs<br>~~(OO~~<br>~~ID~~|Normal and Low-power modes|
|T_CMP_EN2<br>~~es~~<br>~~es~~|Time from enabling to operation<br>~~rr~~<br>~~nr~~|–<br>~~ID ~~<br>~~Int~~|–<br> ~~I~~<br>~~tt~~|50<br>~~I ~~<br>~~en~~|µs<br> ~~(OO~~<br>~~ID~~|Ultra low-power mode|
Document Number: 002-24085 Rev. *A
Page 31 of 59
**CYBLE-416045-02**
## _SAR ADC_
**Table 18. 12-bit SAR ADC DC Specifications**
|**Parameter**<br>~~a~~<br>~~ee~~|**Description**<br>~~I~~<br>~~I~~|**Min**<br>~~fs~~<br>~~IID~~|**Typ**<br>~~I~~<br>~~I~~|**Max**<br>~~DO~~|**Unit**<br>~~DO~~|**Details/Conditions**|
|---|---|---|---|---|---|---|
|A_RES<br>~~a~~<br>~~ee~~<br>~~a~~|SAR ADC resolution<br>~~I ~~<br>~~I~~<br>~~I~~|–<br> ~~fs ~~<br>~~IID~~<br>~~I~~|–<br> ~~I~~<br>~~I~~<br>~~I~~|12<br>~~DO~~<br>~~ID~~|bits<br>~~DO~~<br>~~I~~|–|
|A_CHNLS_S<br>~~ee~~<br>~~a~~<br>~~ee~~|Number of channels - single ended<br>~~I~~<br>~~I~~<br>~~es~~|–<br>~~IID ~~<br>~~I~~<br>~~ee~~|–<br> ~~I~~<br>~~I~~|16<br>~~ID~~|–<br>~~I~~|8 full speed|
|A-CHNKS_D<br>~~a~~<br>~~ee~~<br>~~a~~|Number of channels - differential<br>~~I~~<br>~~es~~<br>~~rE~~|–<br>~~I ~~<br>~~ee~~<br>~~rESD~~|–<br> ~~I~~<br>~~SD~~|8<br>~~ID ~~<br>~~SD~~|–<br> ~~I~~|Differential inputs use neighboring<br>I/O|
|A-MONO<br>~~ee~~<br>~~a~~<br>~~a~~|Monotonicity<br>~~es ~~<br>~~rE~~<br>~~I~~|–<br> ~~ee~~<br>~~rESD~~<br>~~I~~|–<br>~~SD~~<br>~~I~~|–<br>~~SD~~<br>~~ID~~|–<br>~~I~~|Yes|
|A_GAINERR<br>~~a~~<br>~~a~~<br>~~a~~|Gain error<br>~~rE~~<br>~~I~~<br>~~rE~~|–<br>~~rE SD~~<br>~~I~~<br>~~rESD~~|–<br>~~SD~~<br>~~I~~<br>~~SD~~|±0.2<br>~~SD~~<br>~~ID~~<br>~~SD~~|%<br>~~I~~|With external reference|
|A_OFFSET<br>~~a~~<br>~~a~~<br>~~ee~~|Input offset voltage<br>~~I~~<br>~~rE~~<br>~~sd~~|–<br>~~I ~~<br>~~rESD~~<br>~~sd~~|–<br> ~~I~~<br>~~SD~~|2<br>~~ID ~~<br>~~SD~~|mV<br> ~~I~~|Measured with 1-V reference|
|A_ISAR_1<br>~~a~~<br>~~ee~~<br>~~ee~~|Current consumption at 1 Msps<br>~~rE~~<br>~~sd~~<br>~~es~~|–<br>~~rE SD~~<br>~~sd~~<br>~~ee~~|–<br>~~SD~~|1<br>~~SD~~|mA|At 1 Msps. External bypass<br>capacitor|
|A_ISAR_2<br>~~ee~~<br>~~ee~~<br>~~a~~|Current consumption at 1 Msps.<br>Reference = VDD<br>~~sd~~<br>~~es~~<br>~~rE~~|–<br>~~sd~~<br>~~ee~~<br>~~rESD~~|–<br>~~SD~~|1.25<br>~~SD~~|mA|At 1 Msps. External bypass<br>capacitor|
|A_VINS<br>~~ee~~<br>~~a~~<br>~~a~~|Input voltage range - single-ended<br>~~es ~~<br>~~rE~~<br>~~I~~|Vss<br> ~~ee~~<br>~~rESD~~<br>~~I~~|–<br>~~SD~~<br>~~I~~|VDDA<br>~~SD~~<br>~~ID~~|V<br>~~I~~|–|
|A_VIND<br>~~a~~<br>~~a~~<br>~~a~~|Input voltage range - differential<br>~~rE~~<br>~~I~~<br>~~rE~~|Vss<br>~~rE SD~~<br>~~I~~<br>~~rESD~~|–<br>~~SD~~<br>~~I~~<br>~~SD~~|VDDA<br>~~SD~~<br>~~ID~~<br>~~SD~~|V<br>~~I~~|–|
|A_INRES<br>~~a~~<br>~~a~~<br>~~es~~|Input resistance<br>~~I~~<br>~~rE~~<br>~~I~~|–<br>~~I ~~<br>~~rESD~~<br>~~I~~|–<br> ~~I~~<br>~~SD~~<br>~~ss~~|2.2<br>~~ID ~~<br>~~SD~~<br>~~ss~~|K<br> ~~I~~<br>~~I~~|–|
|A_INCAP<br>~~a~~<br>~~es~~|Input capacitance<br>~~rE~~<br>~~I~~|–<br>~~rE SD~~<br>~~I~~|–<br>~~SD~~<br>~~ss~~|10<br>~~SD~~<br>~~ss~~|pF<br>~~I~~|–|
**Table 19. 12-bit SAR ADC AC Specifications**
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|**12-bit SAR ADC AC Specifications**<br>~~Re~~<br>~~ee~~<br>~~rsttt~~<br>~~treRUSs~~|||||||
|A_PSRR<br>~~Re~~<br>~~ee~~<br>~~ee~~|Power supply rejection ratio<br>~~Re~~<br>~~rs~~<br>~~rs~~|70<br>~~Re~~<br>~~ttt~~<br>~~tt~~|–<br>~~Re~~<br>~~tre~~<br>~~rs~~|–<br>~~Re~~<br>~~RU~~<br>~~I~~|dB<br>~~Re~~<br>~~Ss~~<br>~~ns~~|–<br>~~Re~~|
|A_CMRR<br>~~ee~~<br>~~ee~~|Common mode rejection ratio<br>~~rs ~~<br>~~rs~~|66<br> ~~ttt~~<br>~~tt~~|–<br>~~tre ~~<br>~~rs~~|–<br> ~~RU ~~<br>~~I~~|dB<br> ~~Ss~~<br>~~ns~~|Measured at 1 V|
|**One Msp per second mode:**<br>~~ee~~<br>~~rs tt~~<br>~~rs I~~<br>~~ns~~<br>~~Re~~<br>~~aeeeeeeee~~|||||||
|A_SAMP_1<br>~~Re~~<br>~~a~~<br>~~ee~~|Sample rate with external reference<br>bypass capacitor<br>~~Re~~<br>~~ee~~<br>~~ee~~|–<br>~~Re~~<br>~~ee~~<br>~~ee~~|–<br>~~Re~~<br>~~ee~~<br>~~ee~~|1<br>~~Re~~<br>~~ee~~<br>~~ee~~|Msps<br>~~Re~~<br>~~ee~~|–<br>~~Re~~|
|A_SAMP_2<br>~~a ~~<br>~~ee~~|Sample rate with no bypass<br>capacitor; Reference = VDD<br> ~~ee ~~<br>~~ee~~|–<br> ~~ee ~~<br>~~ee~~|–<br> ~~ee ~~<br>~~ee~~|250<br> ~~ee~~<br>~~ee~~|Ksps<br>~~ee~~|–|
|A_SAMP_3<br>~~ee~~|Sample rate with no bypass<br>capacitor; Internal reference<br>~~ee ~~|–<br> ~~ee ~~|–<br> ~~ee ~~|100<br> ~~ee ~~|Ksps<br> ~~ee~~|–|
|A_SINAD<br>~~ee~~|Signal-to-noise and Distortion ratio<br>(SINAD). VDDA= 2.7 to 3.6 V,<br>1 Msps<br>~~ee~~|64<br>~~ee~~|–<br>~~ee~~|–<br>~~ee~~|dB<br>~~ee~~|Fin= 10 kHz|
|A_INL<br>~~ee~~<br>~~ee~~|Integral Non Linearity. VDDA= 2.7 to<br>3.6 V, 1 Msps<br>~~ee~~<br>~~ee~~|–2<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~|2<br>~~ee~~<br>~~ee~~|LSB<br>~~ee~~<br>~~ee~~|Measured with internal VREF=1.2 V and<br>bypass capacitor|
|A_INL<br>~~ee~~<br>~~ee~~<br>~~ee~~|Integral Non Linearity. VDDA= 2.7 to<br>3.6 V, 1 Msps<br>~~ee ~~<br>~~ee~~<br>~~ee~~|–4<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|–<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|4<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|LSB<br> ~~ee~~<br>~~ee~~<br>~~ee~~|Measured with external VREF 1 V and VIN<br>common mode < 2 * VREF|
|A_DNL<br>~~ee~~<br>~~ee~~<br>~~ee~~|Differential Non Linearity. VDDA=<br>2.7 to 3.6 V, 1 Msps<br>~~ee ~~<br>~~ee~~<br>~~es~~|–1<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|–<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|1.4<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|LSB<br> ~~ee~~<br>~~ee~~<br>~~ee~~|Measured with internal VREF= 1.2 V and<br>bypass capacitor|
|A_DNL<br>~~ee~~<br>~~ee~~<br>~~a~~|Differential Non Linearity. VDDA=<br>2.7 to 3.6 V, 1 Msps<br>~~ee ~~<br>~~es~~<br>~~ee~~|–1<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|–<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|1.7<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|LSB<br> ~~ee~~<br>~~ee~~<br>~~ee~~|Measured with external VREF1 V and VIN<br>common mode < 2 * VREF|
|A_THD<br>~~ee~~<br>~~a~~|Total harmonic distortion. VDDA=<br>2.7 to 3.6 V, 1 Msps<br>~~es ~~<br>~~ee~~|–<br> ~~ee ~~<br>~~ee~~|–<br> ~~ee ~~<br>~~ee~~|–65<br> ~~ee ~~<br>~~ee~~|dB<br> ~~ee~~<br>~~ee~~|Fin= 10 kHz|
Document Number: 002-24085 Rev. *A
Page 32 of 59
**CYBLE-416045-02**
**Table 20. 12-bit DAC Specifications**
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|**12-bit DAC DC Specifications**<br>~~Srna~~|||||||
|DAC_RES<br>~~a~~<br>~~ee~~|DAC resolution|–|–|12|bits|–|
|DAC_INL<br>~~a~~<br>~~ee~~|Integral nonlinearity|–4|–|4|LSB|–|
|DAC_DNL<br>~~ee~~<br>~~a~~|Differential nonlinearity|–2|–|2|LSB|Monotonic to 11 bits.|
|DAC_OFFSET<br>~~a~~<br>~~ee~~|Output Voltage zero offset error<br>|–10<br>|–<br>|10<br>|mV<br>|For 000 (hex)<br>|
|DAC_OUT_RES <br>~~a~~<br>~~ee~~|DAC Output resistance<br>|–<br>|15<br>|–<br>|k<br>|–<br>|
|DAC_IDD<br>~~eea~~|DAC Current<br>~~a~~|–<br>~~a~~|–<br>~~a~~|125<br>~~a~~|µA<br>~~a~~|–<br>~~a~~|
|DAC_QIDD<br>~~a~~|DAC Current when DAC stopped<br>~~a~~|–<br>~~a~~|–<br>~~a~~|1<br>~~a~~|µA<br>~~a~~|–<br>~~a~~|
|**12-bit DAC AC Specifications**<br>~~a~~<br>~~|~~|||||||
|DAC_CONV<br>~~a~~|DAC Settling time<br>~~a~~|–<br>~~a~~|–<br>~~a~~|2<br>~~a~~|µs<br>~~a~~|Driving through CTBm buffer; 25 pF load<br>~~a~~|
|DAC_WAKEUP<br>~~a~~|Time from Enabling to ready for<br>conversion<br>~~a~~<br>~~ee~~|–<br>~~a~~<br>~~ee~~|–<br>~~a~~<br>~~ee~~|10<br>~~a~~<br>~~ee~~|µs<br>~~a~~<br>~~ee~~|–<br>~~a~~<br>~~ee~~|
Document Number: 002-24085 Rev. *A
Page 33 of 59
**CYBLE-416045-02**
## _CSD_
**Table 21. CapSense Sigma-Delta (CSD) Specifications**
|**Parameter**<br>~~ee~~|**Description**<br>~~ee eee~~|**Min**<br>~~eee~~|**Typ**<br>~~eee~~|**Max**<br>~~eee~~|**Unit**<br>~~eee~~|**Details/Conditions**<br>~~eee~~|
|---|---|---|---|---|---|---|
|**CSD V2 Specifications**<br>~~ee eee~~<br>~~Ce~~|||||||
|VDD_RIPPLE|Max allowed ripple on power supply,<br>DC to 10 MHz|–|–|±50|mV|VDDA> 2 V (with ripple), 25 °C TA,<br>Sensitivity = 0.1 pF|
|VDD_RIPPLE_1.8<br>~~a~~|Max allowed ripple on power supply,<br>DC to 10 MHz<br>~~rs~~|–<br>~~rrr~~|–<br>~~rr~~|±25<br>~~rr~~|mV<br>~~rs~~|VDDA> 1.75 V (with ripple), 25 °C<br>TA, Parasitic Capacitance (CP) <<br>20 pF, Sensitivity0.4 pF|
|ICSD<br>~~a~~|Maximum block current<br>~~rs~~|~~rrr~~|~~rr~~|4500<br>~~rr~~|µA<br>~~rs~~||
|VREF<br>~~a~~<br>~~a~~|Voltage reference for CSD and<br>comparator<br>~~rs ~~<br>~~ee~~|0.6<br> ~~rrr~~<br>~~ee~~|1.2<br>~~rr~~<br>~~ee~~|VDDA- 0.6<br>~~rr ~~<br>~~ee~~|V<br> ~~rs~~<br>~~ee~~|VDDA– VREF 0.6 V|
|VREF_EXT<br>~~a~~<br>~~a~~<br>~~es~~|External voltage reference for CSD<br>and comparator<br>~~ee~~<br>~~ee~~<br>~~rs~~|0.6<br>~~ee~~<br>~~ee~~<br>~~rs~~|~~ee ~~<br>~~ee ~~<br>~~rr~~|VDDA- 0.6<br> ~~ee~~<br> ~~ee~~<br>~~rs~~|V<br>~~ee~~<br>~~ee~~<br>~~(rs~~|VDDA– VREF 0.6 V|
|IDAC1IDD<br>~~es~~<br>~~a~~|IDAC1 (7-bits) block current<br>~~rs~~|–<br>~~rs~~<br>~~rs~~|–<br>~~rr~~<br>~~rs~~|1900<br>~~rs~~|µA<br>~~(rs~~||
|IDAC2IDD<br>~~es~~<br>~~rs~~<br>~~a~~<br>~~es~~|IDAC2 (7-bits) block current<br>~~rs ~~<br>~~rs~~<br>~~rs~~|–<br> ~~rs ~~<br>~~rs~~<br>~~rs~~<br>~~rrr~~|–<br> ~~rr ~~<br>~~rs~~<br>~~rs~~<br>~~rr~~|1900<br> ~~rs~~<br>~~rs~~<br>~~rr~~|µA<br>~~(rs~~<br>~~rs~~<br>~~rs~~|~~rs~~|
|VCSD<br>~~rs~~<br>~~a~~<br>~~es~~|Voltage range of operation<br>~~rs~~<br>~~rs~~<br>~~rs~~|1.71<br>~~rs~~<br>~~rs ~~<br>~~rrr~~<br>~~rs~~|–<br>~~rs~~<br> ~~rs~~<br>~~rr~~<br>~~rr~~|3.6<br>~~rs~~<br>~~rr~~<br>~~rs~~|V<br>~~rs~~<br>~~rs~~<br>~~(rs~~|1.71 to 3.6 V<br>~~rs~~|
|VCOMPIDAC<br>~~es~~<br>~~a~~|Voltage compliance range of IDAC<br>~~rs~~<br>~~rs~~|0.6<br>~~rrr~~<br>~~rs~~<br>~~rs~~|–<br>~~rr~~<br>~~rr~~<br>~~rs~~|VDDA–0.6<br>~~rr~~<br>~~rs~~|V<br>~~rs~~<br>~~(rs~~|VDDA– VREF 0.6 V|
|IDAC1DNL<br>~~es~~<br>~~rs~~<br>~~a~~|DNL<br>~~rs ~~<br>~~rs ~~<br>~~rs~~|–1<br> ~~rrr~~<br> ~~rs ~~<br>~~rs~~<br>~~rs~~|–<br>~~rr~~<br> ~~rr ~~<br>~~rs~~<br>~~rs~~|1<br>~~rr ~~<br> ~~rs~~<br>~~rs~~|LSB<br> ~~rs~~<br>~~(rs~~<br>~~rs~~|~~rs~~|
|IDAC1INL<br>~~rs~~<br>~~a~~<br>~~a~~|INL<br>~~rs~~<br>~~ee~~<br>~~rs~~|–3<br>~~rs~~<br>~~rs~~<br>~~ee~~<br>~~rrr~~|–<br>~~rs~~<br>~~rs~~<br>~~rr~~|3<br>~~rs~~<br>~~rr~~|LSB<br>~~rs~~<br>~~rs~~|If VDDA< 2 V then for LSB of 2.4 µA<br>or less<br>~~rs~~|
|IDAC2DNL<br>~~a~~<br>~~a~~<br>~~pf~~|DNL<br>~~ee~~<br>~~rs~~<br>~~pf~~|–1<br>~~rs ~~<br>~~ee~~<br>~~rrr~~<br>|–<br> ~~rs~~<br>~~rr~~<br>|1<br>~~rr~~<br><br>~~|}~~|LSB<br>~~rs~~<br><br>~~|}~~|~~|}~~|
|IDAC2INL<br>~~a~~<br>~~pf|_|~~|INL<br>~~rs ~~<br>~~pf|_|~~|–3<br> ~~rrr~~<br>~~|_|~~|–<br>~~rr~~<br>~~|_|~~|3<br>~~rr ~~<br>~~|_|~~<br>~~|}~~|LSB<br> ~~rs~~<br>~~|_|~~<br>~~|}~~|If VDDA< 2 V then for LSB of 2.4 µA<br>or less<br>~~|_|~~<br>~~|}~~|
|**SNRC of the following is Ratio of counts of finger to noise. Guaranteed by characterization**<br>~~pf|_|~~<br>~~|}~~|||||||
|SNRC_1<br>~~pf~~<br>~~ee~~|SRSS Reference. IMO + FLL Clock<br>Source. 0.1-pF sensitivity<br>~~pf~~<br>~~ee~~|5<br><br>~~ee~~|–<br><br>~~ee~~|–<br><br>~~|}~~<br>~~ee~~|Ratio<br><br>~~|}~~<br>~~ee~~|9.5-pF maximum capacitance<br><br>~~|}~~<br>~~ee~~|
|SNRC_2<br>~~a~~|SRSS Reference. IMO + FLL Clock<br>Source. 0.3-pF sensitivity|5|–|–|Ratio|31-pF maximum capacitance|
|SNRC_3<br>~~a~~|SRSS Reference. IMO + FLL Clock<br>Source. 0.6-pF sensitivity|5|–|–|Ratio|61-pF maximum capacitance|
|SNRC_4<br>~~a~~|PASS Reference. IMO + FLL Clock<br>Source. 0.1-pF sensitivity|5|–|–|Ratio|12-pF maximum capacitance|
|SNRC_5<br>~~a~~|PASS Reference. IMO + FLL Clock<br>Source. 0.3-pF sensitivity|5|–|–|Ratio|47-pF maximum capacitance|
|SNRC_6<br>~~a~~|PASS Reference. IMO + FLL Clock<br>Source. 0.6-pF sensitivity|5|–|–|Ratio|86-pF maximum capacitance|
|SNRC_7<br>~~a~~|PASS Reference. IMO + PLL Clock<br>Source. 0.1-pF sensitivity|5|–|–|Ratio|27-pF maximum capacitance|
|SNRC_8<br>~~a~~<br>~~a~~|PASS Reference. IMO + PLL Clock<br>Source. 0.3-pF sensitivity<br>|5<br>|–<br><br>~~ee~~|–<br>|Ratio<br>|86-pF maximum capacitance<br>|
|SNRC_9<br>~~se~~<br>~~a~~<br>~~a~~|PASS Reference. IMO + PLL Clock<br>Source. 0.6-pF sensitivity<br>~~se~~<br>~~ee~~|5<br>~~se~~<br>~~ee~~|–<br>~~se~~<br>~~ee~~<br>~~ee~~|–<br>~~se~~<br>~~ee~~|Ratio<br>~~se~~|168-pF maximum capacitance<br>~~se~~|
|IDAC1CRT1<br>~~a~~<br>~~a~~<br>~~ee~~|Output current of IDAC1 (7 bits) in<br>low range<br>~~ee~~<br>~~ee~~<br>|4.2<br>~~ee~~<br>~~**ee**~~|~~ee~~<br>~~ee~~<br>~~**ee**~~|5.7<br>~~ee~~<br>~~**ee**~~|µA|LSB = 37.5 nA typical|
|IDAC1CRT2<br>~~a~~<br>~~ee~~|Output current of IDAC1(7 bits) in<br>medium range<br>~~ee ~~<br>~~ee~~<br>~~ee~~|33.7<br> ~~ee ~~<br>~~**ee**~~|~~ee ~~<br>~~**ee**~~|45.6<br> ~~ee~~<br>~~**ee**~~|µA|LSB = 300 nA typical|
|IDAC1CRT3<br>~~ee~~|Output current of IDAC1(7 bits) in<br>high range<br>~~ee~~<br>~~ee~~|270<br>~~**ee**~~|~~**ee**~~|365<br>~~**ee**~~|µA|LSB = 2.4 µA typical|
Document Number: 002-24085 Rev. *A
Page 34 of 59
**CYBLE-416045-02**
**Table 21. CapSense Sigma-Delta (CSD) Specifications** (continued)
|**Parameter**<br>~~ee~~|**Description**<br>~~ee~~|**Min**<br>~~ee~~|**Typ**<br>~~eee~~|**Max**<br>~~eee~~|**Unit**<br>~~ee~~|**Details/Conditions**<br>~~eee~~|
|---|---|---|---|---|---|---|
|IDAC1CRT12<br>~~ee~~<br>~~ee~~|Output current of IDAC1 (7 bits) in<br>low range, 2X mode<br>~~ee~~<br>~~ee~~|8<br>~~ee ~~<br>~~ee~~|~~eee~~<br>~~ee~~|11.4<br>~~eee ~~<br>~~ee~~|µA<br> ~~ee ~~<br>~~ee~~|LSB = 37.5 nA typical 2X output<br>stage<br> ~~eee~~<br>~~ee~~|
|IDAC1CRT22<br>~~a~~|Output current of IDAC1(7 bits) in<br>medium range, 2X mode|67||91|µA|LSB = 300 nA typical 2X output<br>stage|
|IDAC1CRT32<br>~~a~~|Output current of IDAC1(7 bits) in<br>high range, 2X mode. VDDA> 2 V|540||730|µA|LSB = 2.4 µA typical 2X output<br>stage|
|IDAC2CRT1<br>~~a~~|Output current of IDAC2 (7 bits) in<br>low range|4.2||5.7|µA|LSB = 37.5 nA typical|
|IDAC2CRT2<br>~~a~~|Output current of IDAC2 (7 bits) in<br>medium range|33.7||45.6|µA|LSB = 300 nA typical|
|IDAC2CRT3<br>~~a~~|Output current of IDAC2 (7 bits) in<br>high range|270||365|µA|LSB = 2.4 µA typical|
|IDAC2CRT12<br>~~a~~|Output current of IDAC2 (7 bits) in<br>low range, 2X mode|8||11.4|µA|LSB = 37.5 nA typical 2X output<br>stage|
|IDAC2CRT22<br>~~a~~|Output current of IDAC2(7 bits) in<br>medium range, 2X mode|67||91|µA|LSB = 300 nA typical 2X output<br>stage|
|IDAC2CRT32<br>~~a~~|Output current of IDAC2(7 bits) in<br>high range, 2X mode. VDDA> 2 V|540||730|µA|LSB = 2.4 µA typical 2X output<br>stage|
|IDAC3CRT13<br>~~a~~|Output current of IDAC in 8-bit mode<br>in low range|8||11.4|µA|LSB = 37.5 nA typical|
|IDAC3CRT23<br>~~a~~|Output current of IDAC in 8-bit mode<br>in medium range|67||91|µA|LSB = 300 nA typical|
|IDAC3CRT33<br>~~a~~<br>~~a~~|Output current of IDAC in 8-bit mode<br>in high range. VDDA> 2 V<br>~~rs~~|540<br>~~rs~~|~~rr~~|730<br>~~rs~~|µA<br>~~rs~~|LSB = 2.4 µA typical|
|IDACOFFSET<br>~~a~~<br>~~a~~<br>~~a~~|All zeros input<br>~~rs~~<br>~~rs~~|–<br>~~rs~~<br>~~errs~~|–<br>~~rr~~<br>~~rr~~|1<br>~~rs~~<br>~~Ss~~|LSB<br>~~rs~~<br>~~rs~~|Polarity set by Source or Sink|
|IDACGAIN<br>~~a~~<br>~~a~~|Full-scale error less offset<br>~~rs~~<br>~~rs~~|–<br>~~rs~~<br>~~errs~~|–<br>~~rr~~<br>~~rr~~|±15<br>~~rs~~<br>~~Ss~~|%<br>~~rs~~<br>~~rs~~|LSB = 2.4 µA typical|
|IDACMISMATCH1<br>~~a~~<br>~~a~~|Mismatch between IDAC1 and<br>IDAC2 in Low mode<br>~~rs ~~<br>~~rs~~<br>~~ee~~|–<br> ~~rs ~~<br>~~errs~~<br>~~ee~~|–<br> ~~rr~~<br>~~rr~~|9.2<br>~~rs ~~<br>~~Ss~~|LSB<br> ~~rs~~<br>~~rs~~|LSB = 37.5 nA typical|
|IDACMISMATCH2<br>~~a~~<br>~~a~~|Mismatch between IDAC1 and<br>IDAC2 in Medium mode<br>~~rs ~~<br>~~ee~~<br>~~ee~~|–<br> ~~errs ~~<br>~~ee~~<br>~~ee~~|–<br> ~~rr~~|6<br>~~Ss ~~|LSB<br> ~~rs~~|LSB = 300 nA typical|
|IDACMISMATCH3<br>~~a~~<br>~~a~~|Mismatch between IDAC1 and<br>IDAC2 in High mode<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~|–|5.8|LSB|LSB = 2.4 µA typical|
|IDACSET8<br>~~a~~<br>~~a~~|Settling time to 0.5 LSB for 8-bit<br>IDAC<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~|–|10|µs|Full-scale transition. No external<br>load|
|IDACSET7<br>~~a~~<br>~~a~~<br>~~a~~|Settling time to 0.5 LSB for 7-bit<br>IDAC<br>~~ee~~<br>~~ee~~<br>~~rs~~|–<br>~~ee~~<br>~~ee~~<br>~~erred~~|–<br>~~rr~~|10<br>~~rr~~|µs<br>~~rs~~|Full-scale transition. No external<br>load|
|CMOD<br>~~a~~<br>~~a~~|External modulator capacitor<br>~~ee~~<br>~~rs~~|–<br>~~ee~~<br>~~erred~~|2.2<br>~~rr~~|–<br>~~rr~~|nF<br>~~rs~~|5-V rating, X7R or NP0 capacitor|
Document Number: 002-24085 Rev. *A
Page 35 of 59
**CYBLE-416045-02**
**Table 22. CSD ADC Specifications**
|**Parameter**<br>~~—~~|**Description**<br>~~—~~|**Min**<br>~~—~~|**Typ**<br>~~—~~|**Max**<br>~~—~~|**Unit**<br>~~—~~|**Details/Conditions**<br>~~—~~|
|---|---|---|---|---|---|---|
|**CSDv2 ADC Specifications**<br>~~—~~<br>~~eersirsrs~~<br>~~es~~|||||||
|A_RES<br>~~a~~<br>~~es ee~~<br>~~ee~~|Resolution<br>~~a~~<br>~~ee~~<br>~~ee~~|–<br>~~a~~<br>~~rs~~|–<br>~~a~~<br>~~i~~|10<br>~~a~~<br>~~rs~~|bits<br>~~a~~<br>~~rs~~|Auto-zeroing is required every millisecond<br>~~a~~|
|A_CHNLS_S<br>~~es ee~~<br>~~ee~~|Number of channels - single<br>ended<br>~~ee~~<br>~~ee~~|–<br>~~rs~~|–<br>~~i~~|–<br>~~rs~~|16<br>~~rs~~||
|A-MONO<br>~~es ee~~<br>~~ee~~|Monotonicity<br>~~ee ~~<br>~~ee~~|–<br> ~~rs ~~|–<br> ~~i ~~|Yes<br> ~~rs ~~|–<br> ~~rs~~|VREFmode|
|A_GAINERR_VREF<br>~~ee~~<br>~~ee~~|Gain error<br>~~ee~~|–|0.6|–|%|Reference Source: SRSS<br>(VREF= 1.20 V, VDDA< 2.2 V),<br>(VREF= 1.6 V, 2.2 V < VDDA< 2.7 V), (VREF= 2.13 V,<br>VDDA> 2.7 V)|
|A_GAINERR_VDDA<br>~~ee~~<br>~~ee~~<br>~~a~~|Gain error<br>~~ee~~<br>~~eee~~|–<br>~~eee~~|0.2<br>~~eee~~|–<br>~~eee~~|%<br>~~eee~~|Reference Source: SRSS<br>(VREF= 1.20 V, VDDA< 2.2 V),<br>(VREF= 1.6 V, 2.2 V < VDDA< 2.7 V),<br>(VREF= 2.13 V, VDDA> 2.7 V)<br>~~eee~~|
|A_OFFSET_VREF<br>~~a~~<br>~~ee~~|Input offset voltage<br>~~eee~~<br>~~ee~~|–<br>~~eee~~<br>~~ee~~|0.5<br>~~eee~~<br>~~ee~~|–<br>~~eee~~<br>~~ee~~|LSB<br>~~eee~~<br>~~ee~~|After ADC calibration, Ref. SRC = SRSS, (VREF=<br>1.20 V, VDDA< 2.2 V), (VREF=1.6 V, 2.2 V < VDDA<br>< 2.7 V), (VREF= 2.13 V, VDDA> 2.7 V)<br>~~eee~~<br>~~ee~~|
|A_OFFSET_VDDA<br>~~a~~<br>~~ee~~<br>~~Ce~~|Input offset voltage<br>~~eee~~<br>~~ee~~|–<br>~~eee~~<br>~~ee~~|0.5<br>~~eee~~<br>~~ee~~|–<br>~~eee~~<br>~~ee~~|LSB<br>~~eee~~<br>~~ee~~|After ADC calibration, Ref. SRC = SRSS, (VREF=<br>1.20 V, VDDA< 2.2 V), (VREF= 1.6 V, 2.2 V< VDDA<br>< 2.7 V), (VREF= 2.13 V, VDDA> 2.7 V)<br>~~eee~~<br>~~ee~~|
|A_ISAR_VREF<br>~~ee~~<br>~~Ce~~|Current consumption<br>~~ee~~|–<br>~~ee~~|0.3<br>~~ee~~|–<br>~~ee~~|mA<br>~~ee~~|CSD ADC Block current<br>~~ee~~|
|A_ISAR_VDDA<br>~~Ce~~<br>~~es~~|Current consumption<br>~~ee~~|–|0.3|–|mA|CSD ADC Block current|
|A_VINS_VREF<br>~~Ce~~<br>~~es~~<br>~~es~~|Input voltage range - single<br>ended<br>~~ee~~<br>~~ee~~|VSSA|–|VREF|V|(VREF= 1.20 V, VDDA< 2.2 V), (VREF= 1.6 V, 2.2 V<br><VDDA< 2.7 V), (VREF= 2.13 V, VDDA> 2.7 V)|
|A_VINS_VDDA<br>~~es ~~<br>~~es~~|Input voltage range - single<br>ended<br> ~~ee~~<br>~~ee~~|VSSA|–|VDDA|V|(VREF= 1.20 V, VDDA< 2.2 V), (VREF= 1.6 V,<br>2.2 V< VDDA< 2.7 V), (VREF= 2.13 V, VDDA> 2.7 V)|
|A_INRES<br>~~es ~~<br>~~a~~|Input charging resistance<br> ~~ee~~<br>~~a~~|–<br>~~a~~|15<br>~~a~~|–<br>~~a~~|k<br>~~a~~|–<br>~~a~~|
|A_INCAP<br>~~a~~<br>~~ee~~|Input capacitance<br>~~a~~<br>~~ee~~|–<br>~~a~~<br>~~ee~~|41<br>~~a~~<br>~~ee~~|–<br>~~a~~<br>~~ee~~|pF<br>~~a~~<br>~~ee~~|–<br>~~a~~|
|A_PSRR<br>~~ee~~|Power supply rejection ratio<br>(DC)<br>~~ee~~|–<br>~~ee~~|60<br>~~ee~~|–<br>~~ee~~|dB<br>~~ee~~|–|
|A_TACQ<br>~~ee~~<br>~~tt~~|Sample acquisition time<br>~~ee ~~<br>~~tt~~|–<br> ~~ee~~<br>~~tt~~|10<br>~~ee~~<br>~~tt~~|–<br>~~ee~~<br>~~tt~~|µs<br>~~ee~~<br>~~tt~~|Measured with 50 Œ© source impedance. 10 ?s is<br>default software driver acquisition time setting.<br>Settling to within 0.05%.<br>~~—~~|
|A_CONV8<br>~~tt~~|Conversion time for 8-bit<br>resolution at conversion rate<br>= Fhclk/(2 × (N+ 2)). Clock<br>frequency = 50 MHz.<br>~~tt~~|–<br>~~tt~~|25<br>~~tt~~|–<br>~~tt~~|µs<br>~~tt~~|Does not include acquisition time<br>~~—~~|
|A_CONV10<br>~~ee~~|Conversion time for 10-bit<br>resolution at conversion rate<br>= Fhclk/(2 × (N + 2)). Clock<br>frequency = 50 MHz.<br>~~ee~~|–<br>~~ee~~|60<br>~~ee~~|–|µs|Does not include acquisition time|
|A_SND_VRE<br>~~ee~~<br>~~ee~~|Signal-to-noise and<br>Distortion ratio (SINAD)<br>~~ee~~|–<br>~~ee~~<br>~~rs~~|57<br>~~ee~~<br>~~Gr~~|–<br>~~rs~~|dB<br>~~GOs~~|Measured with 50source impedance|
|A_SND_VDDA<br>~~ee~~<br>~~re~~<br>~~ee~~<br>~~ee~~|SINAD<br>~~ee~~<br>~~re~~<br>~~**ee**~~|–<br>~~ee~~<br>~~re~~<br>~~rs~~<br>~~**e**~~|52<br>~~ee~~<br>~~re~~<br>~~Gr~~<br>~~**e**e~~|–<br>~~re~~<br>~~rs~~<br>~~e~~|dB<br>~~re~~<br>~~GOs~~<br>~~**ee**~~|Measured with 50source impedance<br>~~re~~|
|A_INL_VREF<br>~~re~~<br>~~ee~~<br>~~ee~~|Integral nonlinearity –<br>11.6 ksps<br>~~re~~<br>~~**ee**~~|–<br>~~re~~<br>~~rs~~<br>~~**e**~~|–<br>~~re~~<br>~~Gr~~<br>~~**e**e~~<br>~~e~~|2<br>~~re~~<br>~~rs~~<br>~~e~~|LSB<br>~~re~~<br>~~GOs~~<br>~~**ee**~~|Measured with 50source impedance<br>~~re~~|
|A_INL_VDDA<br>~~ee~~<br>~~ee~~|Integral nonlinearity –<br>11.6 ksps<br>~~**ee**~~|–<br>~~rs~~<br>~~**e**~~|–<br>~~Gr ~~<br>~~**e**e~~<br>~~e~~|2<br> ~~rs~~<br>~~e~~|LSB<br>~~GOs~~<br>~~**ee**~~|Measured with 50source impedance|
Document Number: 002-24085 Rev. *A
Page 36 of 59
**CYBLE-416045-02**
**Table 22. CSD ADC Specifications** (continued)
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|A_DNL_VREF|Differential nonlinearity –<br>11.6 ksps|–|–|1|LSB|Measured with 50source impedance|
|A_DNL_VDDA|Differential nonlinearity –<br>11.6 ksps|–|–|1|LSB|Measured with 50source impedance|
## **Digital Peripherals**
**Table 23. Timer/Counter/PWM (TCPWM) Specifications**
|**Parameter**<br>~~EEE~~|**Description**<br>~~EEE~~|**Min**<br>~~EEE~~|**Typ**<br>~~EEE~~|**Max**<br>~~EEE~~|**Unit**<br>~~EEE~~|**Details/Conditions**<br>~~EEE~~|
|---|---|---|---|---|---|---|
|ITCPWM1<br>~~EEE~~<br>~~es~~<br>~~es~~|Block current consumption at 8 MHz<br>~~EEE~~<br>~~ey~~<br>|–<br>~~EEE~~<br>~~ey~~<br>~~**tn**~~<br>|–<br>~~EEE~~<br>~~ey~~<br>~~**ID**~~<br>|70<br>~~EEE~~<br>~~ey~~<br>~~**Is**~~<br>|µA<br>~~EEE~~<br>~~ey~~<br>~~**I**~~<br>|All modes (TCPWM)<br>~~EEE~~<br>~~ey~~<br>|
|ITCPWM2<br>~~es~~<br>~~es~~|Block current consumption at 24 MHz<br>~~ey~~<br>|–<br>~~ey~~<br>~~**tn**~~<br>|–<br>~~ey~~<br>~~**ID**~~<br>|180<br>~~ey~~<br>~~**Is**~~<br>|µA<br>~~ey~~<br>~~**I**~~<br>|All modes (TCPWM)<br>~~ey~~<br>|
|ITCPWM3<br>~~es~~<br>~~es~~|Block current consumption at 50 MHz<br>~~ey~~<br>~~ey~~|–<br>~~ey~~<br>~~**tn**~~<br>~~ey~~|–<br>~~ey~~<br>~~**ID**~~<br>~~ey~~|270<br>~~ey~~<br>~~**Is**~~<br>~~ey~~|µA<br>~~ey~~<br>~~**I**~~<br>~~ey~~<br>~~ee~~|All modes (TCPWM)<br>~~ey~~<br>~~ey~~|
|ITCPWM4<br>~~es~~<br>~~ee~~<br>~~a~~|Block current consumption at<br>100 MHz<br><br>~~ee~~<br>|–<br>~~**tn** ~~<br><br>~~ee~~<br>|–<br> ~~**ID** ~~<br><br>~~ee~~<br>|540<br> ~~**Is** ~~<br><br>~~ee~~<br>|µA<br> ~~**I**~~<br><br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|All modes (TCPWM)<br><br>~~ee~~<br>|
|TCPWMFREQ <br>~~ee~~<br>~~a~~|Operating frequency<br>~~ee~~<br>|–<br>~~ee~~<br>|–<br>~~ee~~<br>|100<br>~~ee~~<br>|MHz<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|Fcmax= Fcpu<br>Maximum = 100 MHz<br>~~ee~~<br>|
|TPWMENEXT<br>~~a~~|Input trigger pulse width for all trigger<br>events<br>~~ee~~|2/Fc<br>~~ee~~|–<br>~~ee~~|–<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|Trigger Events can be Stop, Start, Reload, Count,<br>Capture, or Kill depending on which mode of<br>operation is selected<br>~~ee~~|
|TPWMEXT<br>~~a~~<br>~~fr~~<br>~~ee~~|Output trigger pulse widths<br>~~ee~~<br>~~fr~~<br>~~ee~~|1.5/Fc<br>~~ee~~<br>~~fr~~<br>~~ee~~|–<br>~~ee~~<br>~~fr~~|–<br>~~ee~~<br>~~fr~~|ns<br>~~ee~~<br>~~ee~~<br>~~fr~~|Minimum possible width of Overflow, Underflow,<br>and CC (Counter equals Compare value) trigger<br>outputs<br>~~ee~~<br>~~fr~~|
|TCRES<br>~~ee~~<br>~~ee~~|Resolution of counter<br>~~ee~~<br>~~ee~~|1/Fc<br>~~ee~~<br>~~ee~~|–|–|ns|Minimum time between successive counts|
|PWMRES<br>~~ee~~<br>~~ee~~<br>~~ee~~|PWM resolution<br>~~ee~~<br>~~ee~~|1/Fc<br>~~ee~~<br>~~ee~~|–|–|ns|Minimum pulse width of PWM output|
|QRES<br>~~ee~~<br>~~ee~~|Quadrature inputs resolution<br>~~ee~~|2/Fc<br>~~ee~~|–|–|ns|Minimum pulse width between Quadrature phase<br>inputs. Delays from pins should be similar|
Document Number: 002-24085 Rev. *A
Page 37 of 59
**CYBLE-416045-02**
**Table 24. Serial Communication Block (SCB) Specifications**
|**Parameter**<br>~~a~~<br>|**Description**<br>~~a~~<br>~~a~~<br>|**Min**<br>~~a~~<br>~~a~~<br>|**Typ**<br>~~a~~<br>~~a~~<br>|**Max**<br>~~a~~<br>~~a~~<br>|**Unit**<br>~~a~~<br>~~a~~<br>|**Details/Conditions**<br>~~a~~<br>~~a~~<br>~~]~~|
|---|---|---|---|---|---|---|
|**Fixed I2C DC Specifications**<br>~~a]~~|||||||
|II2C1<br><br>~~a~~|Block current consumption at 100 kHz<br><br>~~a~~|–<br><br>~~a~~|–<br><br>~~a~~|30<br><br>~~a~~|µA<br><br>~~a~~|–<br>~~]~~<br>~~a~~|
|II2C2<br>~~a~~|Block current consumption at 400 kHz<br>~~a~~|–<br>~~a~~|–<br>~~a~~|80<br>~~a~~|µA<br>~~a~~|–<br>~~a~~|
|II2C3<br>~~a~~<br>~~a~~|Block current consumption at 1 Mbps<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|180<br>~~a~~<br>~~a~~|µA<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|
|II2C4<br>~~a~~|I2C enabled in Deep Sleep mode<br>~~a~~|–<br>~~a~~|–<br>~~a~~|1.7<br>~~a~~|µA<br>~~a~~|At 60 °C<br>~~a~~|
|**Fixed I2C AC Specifications**<br>~~a~~<br>~~a~~|||||||
|FI2C1<br>~~a~~<br>~~a~~|Bit Rate<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|1<br>~~a~~<br>~~a~~|Mbps<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|
|**Fixed UART DC Specifications**<br>~~a~~|||||||
|IUART1<br>~~a~~<br>~~a~~|Block current consumption at 100 Kbps<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|30<br>~~a~~<br>~~a~~|µA<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|
|IUART2<br>~~a~~|Block current consumption at 1000 Kbps<br>~~a~~|–<br>~~a~~|–<br>~~a~~|180<br>~~a~~|µA<br>~~a~~|–<br>~~a~~|
|**Fixed UART AC Specifications**<br>~~a~~|||||||
|FUART1<br>~~a~~<br>~~a~~|Bit Rate<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~<br>~~a~~|3<br>~~a~~<br>~~a~~<br>~~a~~|Mbps<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~<br>~~i~~<br>~~a~~|ULP mode<br>~~a~~<br>~~a~~<br>~~a~~|
|FUART2<br>~~a~~<br>~~a~~||–<br>~~a~~<br>~~a~~<br>~~a~~<br>~~i~~|–<br>~~a~~<br>~~a~~<br>~~a~~<br>~~i~~<br>~~a~~|8<br>~~a~~<br>~~a~~<br>~~a~~<br>~~i~~<br>~~a~~||LP mode<br>~~a~~<br>~~a~~<br>~~a~~<br>~~i~~<br>~~a~~|
|**Fixed SPI DC Specifications**<br>~~a~~|||||||
|ISPI1<br>~~a~~<br>~~a~~|Block current consumption at 1 Mbps<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|220<br>~~a~~<br>~~a~~|µA<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|
|ISPI2<br>~~a~~|Block current consumption at 4 Mbps<br>~~a~~|–<br>~~a~~|–<br>~~a~~|340<br>~~a~~|µA<br>~~a~~|–<br>~~a~~|
|ISPI3<br>~~a~~|Block current consumption at 8 Mbps<br>~~a~~|–<br>~~a~~|–<br>~~a~~|360<br>~~a~~|µA<br>~~a~~|–<br>~~a~~|
|ISP14<br>~~a~~<br>~~a~~|Block current consumption at 25 Mbps<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|800<br>~~a~~<br>~~a~~|µA<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|
|**Fixed SPI AC Specifications for LP Mode (1.1 V) unless noted otherwise**<br>~~a~~|||||||
|FSPI<br>~~a~~|SPI operating frequency Master and externally<br>clocked slave<br>~~a~~|–<br>~~a~~|–<br>~~a~~|25<br>~~a~~|MHz<br>~~a~~|14-MHz maximum for<br>ULP (0.9 V) mode<br>~~a~~|
|FSPI_IC<br>~~a~~|SPI Slave internally clocked<br>~~a~~<br>~~ee~~|–<br>~~a~~<br>~~ee~~|–<br>~~a~~<br>~~ee~~|15<br>~~a~~<br>~~ee~~|MHz<br>~~a~~<br>~~ee~~|5 MHz maximum for ULP<br>(0.9 V) mode<br>~~a~~<br>~~ee~~|
|**Fixed SPI Master mode AC Specifications for LP Mode (1.1 V) unless noted otherwise**<br>~~a~~|||||||
|TDMO<br>~~a~~|master out, slave in (MOSI) valid after SClock<br>driving edge<br>~~a~~|–<br>~~a~~|–<br>~~a~~|12<br>~~a~~|ns<br>~~a~~|20 ns maximum for ULP<br>(0.9 V) mode<br>~~a~~|
|TDSI|MISO valid before SClock capturing edge|5|–|–|ns|Full clock, late master in,<br>slave out (MISO)<br>sampling|
|THMO<br>~~a~~|MOSI data hold time<br>~~a~~<br>~~ee~~|0<br>~~a~~<br>~~ee~~|–<br>~~a~~<br>~~ee~~|–<br>~~a~~<br>~~ee~~|ns<br>~~a~~<br>~~ee~~|Referred to slave<br>capturing edge<br>~~a~~<br>~~ee~~|
|**Fixed SPI Slave mode AC Specifications for LP Mode (1.1 V) unless noted otherwise**<br>~~a~~|||||||
|TDMI<br>~~a~~<br>~~a~~|MOSI valid before Sclock capturing edge<br>~~a~~<br>~~a~~|5<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|ns<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|
|TDSO_EXT<br>~~a~~|MISO valid after Sclock driving edge in external<br>clock mode<br>~~a~~<br>~~ee~~|–<br>~~a~~<br>~~ee~~|–<br>~~a~~<br>~~ee~~|20<br>~~a~~<br>~~ee~~|ns<br>~~a~~<br>~~ee~~|35 ns maximum for ULP<br>(0.9 V) mode<br>~~a~~<br>~~ee~~|
|TDSO<br>~~a~~<br>~~**a**~~|MISO valid after Sclock driving edge in internal<br>clock mode<br>~~ee~~<br>~~ee~~|–<br>~~ee ee~~<br>~~ee ee~~|–<br>~~ee~~<br>~~ee~~|TDSO_EXT+ 3<br>* Tscb<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~|Tscbis SCB clock period|
|TDSO<br>~~**a**~~|MISO valid after Sclock driving edge in internal<br>clock mode with median filter enabled<br>~~ee~~|–<br>~~ee ee~~|–<br>~~ee~~|TDSO_EXT+ 4<br>* Tscb<br>~~ee~~|ns<br>~~ee~~|Tscbis SCB clock period|
|THSO<br>~~**a**~~|Previous MISO data hold time<br>~~ee~~<br>~~a~~|5<br>~~ee ee~~<br>~~a~~|–<br>~~ee~~<br>~~a~~|–<br>~~ee ~~<br>~~a~~|ns<br> ~~ee~~<br>~~a~~|–<br>~~a~~|
|TSSELSCK1<br>~~a~~|SSEL valid to first SCK valid edge<br>~~a~~|65<br>~~a~~|–<br>~~a~~|–<br>~~a~~|ns<br>~~a~~|–<br>~~a~~|
|TSSELSCK2<br>~~a~~|SSEL hold after Last SCK valid edge<br>~~a~~|65<br>~~a~~|–<br>~~a~~|–<br>~~a~~|ns<br>~~a~~|–<br>~~a~~|
Document Number: 002-24085 Rev. *A
Page 38 of 59
**CYBLE-416045-02** or CYPRESS ~~aaa~~
## _LCD Specifications_
**Table 25. LCD Direct Drive DC Specifications**
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|ILCDLOW|Operating current in low-power mode|–|5|–|µA|16 x 4 small segment display at<br>50 Hz|
|CLCDCAP|LCD capacitance per segment/common<br>driver|–|500|5000|pF|–|
|LCDOFFSET|Long-term segment offset|–|20|–|mV|–|
|ILCDOP1|PWM mode current.<br>3.3-V bias. 8-MHz IMO. 25 °C.|–|0.6|–|mA|32 x 4 segments 50 Hz|
|ILCDOP2|PWM mode current.<br>3.3-V bias. 8-MHz IMO. 25 °C.|–|0.5|–|mA|32 x 4 segments 50 Hz|
## **Table 26. LCD Direct Drive AC Specifications**
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|FLCD|LCD frame rate|10|50|150|Hz|–|
## **Memory**
**Table 27. Flash Specifications**
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|**Flash DC Specifications**<br>~~pT~~|||||||
|VPE<br>~~po~~|Erase and program voltage<br>~~po~~|1.71<br>~~po~~|–<br>~~po~~|3.6<br>~~po~~|V<br>~~po~~|–<br>~~po~~|
|**Flash AC Specifications**<br>~~po~~<br>~~pT~~<br>~~**p**o~~|||||||
|TROWWRITE<br>~~**p**o~~|Row (Block) write time (erase & program)|–|–|16|ms|Row (Block) = 512 bytes|
|TROWERASE<br>~~**p**o~~|Row erase time<br>~~o~~|–<br>~~o~~|–<br>~~o~~|11<br>~~o~~|ms<br>~~o~~|–<br>~~o~~|
|TROWPROGRAM <br>~~po~~|Row program time after erase<br>~~o~~<br>~~po~~|–<br>~~o~~<br>~~po~~|–<br>~~o~~<br>~~po~~|5<br>~~o~~<br>~~po~~|ms<br>~~o~~<br>~~po~~|–<br>~~o~~<br>~~po~~|
|TBULKERASE<br>~~po~~|Bulk erase time (1024 KB)<br>~~po~~|–<br>~~po~~|–<br>~~po~~|11<br>~~po~~|ms<br>~~po~~|–<br>~~po~~|
|TSECTORERASE <br>~~po~~|Sector erase time (256 KB)<br>~~po~~|–<br>~~po~~|–<br>~~po~~|11<br>~~po~~|ms<br>~~po~~|512 rows per sector<br>~~po~~|
|TSSERIAE<br>~~po~~<br>~~a~~|Sub-sector erase time<br>~~po~~<br>~~ee~~|–<br>~~po~~<br>~~ee ee~~|–<br>~~po~~<br>~~ee~~|11<br>~~po~~<br>~~ee~~|ms<br>~~po~~|8 rows per sub-sector<br>~~po~~|
|TSSWRITE<br>~~a~~|Sub-sector write time; 1 erase plus 8 program<br>times<br>~~ee~~|–<br>~~ee ee~~|–<br>~~ee~~|51<br>~~ee~~|ms|–|
|TSWRITE<br>~~a~~<br>~~po~~|Sector write time; 1 erase plus 512 program times<br>~~ee ~~<br>~~po~~|–<br> ~~ee ee~~<br>~~po~~|–<br>~~ee~~<br>~~po~~|2.6<br>~~ee~~<br>~~po~~|seconds<br>~~po~~|–<br>~~po~~|
|TDEVPROG<br>~~po~~|Total device program time<br>~~po~~|–<br>~~po~~|–<br>~~po~~|15<br>~~po~~|seconds<br>~~po~~|–<br>~~po~~|
|FEND<br>~~po~~|Flash Endurance<br>~~po~~|100 K<br>~~po~~|–<br>~~po~~|–<br>~~po~~|cycles<br>~~po~~|–<br>~~po~~|
|FRET1<br>~~po~~|Flash Retention. Ta25 °C, 100 K P/E cycles<br>~~po~~|10<br>~~po~~|–<br>~~po~~|–<br>~~po~~|years<br>~~po~~|–<br>~~po~~|
|FRET2<br>~~po~~|Flash Retention. Ta85 °C, 10 K P/E cycles<br>~~po~~|10<br>~~po~~|–<br>~~po~~|–<br>~~po~~|years<br>~~po~~|–<br>~~po~~|
|FRET3<br>~~po~~|Flash Retention. Ta55 °C, 20 K P/E cycles<br>~~po~~|20<br>~~po~~|–<br>~~po~~|–<br>~~po~~|years<br>~~po~~|–<br>~~po~~|
|TWS100<br>~~po~~|Number of Wait states at 100 MHz<br>~~po~~|3<br>~~po~~|–<br>~~po~~|–<br>~~po~~|–<br>~~po~~|–<br>~~po~~|
|TWS50<br>~~a ss~~|Number of Wait states at 50 MHz<br>~~ss~~|2<br>~~ss~~|–<br>~~ss~~|–<br>~~ss~~|–<br>~~ss~~|–<br>~~ss~~|
## **Note**
> 8. It can take as much as 16 ms to write to flash. During this time, the device should not be reset, or flash operations will be interrupted and cannot be relied on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdog. Make certain that these are not inadvertently activated.
Document Number: 002-24085 Rev. *A
Page 39 of 59
**CYBLE-416045-02**
## **System Resources**
**Table 28. CYBLE-416045-02 System Resources**
|**Parameter**<br>~~ee~~|**Description**<br>~~ts~~|**Min**<br>~~ts~~|**Typ**<br>~~ts~~|**Max**<br>~~ts~~|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|**POR with Brownout DC Specifications**<br>~~ee~~<br>~~ts ts ts~~<br>~~eee~~|||||||
|**Precise POR (PPOR)**<br>~~eee~~<br>~~a~~<br>~~ee ee~~|||||||
|VFALLPPOR<br>~~eee~~<br>~~a~~<br>~~ee~~|BOD trip voltage in Active and Sleep<br>modes, VDDD<br>~~eee~~<br>~~ee~~<br>~~rs~~|1.54<br>~~eee~~<br>~~ee~~<br>~~ts~~|–<br>~~eee~~<br>~~ee~~<br>~~ts~~|–<br>~~eee~~<br>~~ee ee~~<br>~~rs~~|V<br>~~eee~~<br>~~ee~~<br>~~ts~~|BOD Reset guaranteed for levels<br>below 1.54 V<br>~~eee~~<br>~~ee~~|
|VFALLDPSLP<br>~~a~~<br>~~ee~~|BOD trip voltage in Deep Sleep, VDDD<br>~~ee~~<br>~~rs~~|1.54<br>~~ee~~<br>~~ts~~|–<br>~~ee~~<br>~~ts~~|–<br>~~ee ee~~<br>~~rs~~|V<br>~~ee~~<br>~~ts~~<br>~~ee~~|–<br>~~ee~~|
|VDDRAMP<br>~~ee~~<br>~~a ee~~|Maximum power supply ramp rate (any<br>supply)<br>~~rs ~~<br>~~ee~~|–<br> ~~ts~~<br>~~ee~~|–<br>~~ts ~~<br>~~ee~~|100<br> ~~rs ~~<br>~~ee~~|mV/µs <br> ~~ts~~<br>~~ee~~<br>~~ee~~|Active mode<br>~~ee~~|
|**POR with Brownout AC Specification**<br>~~a ee~~<br>~~ee~~<br>~~eee~~<br>~~ee~~|||||||
|VDDRAMP_DS<br>~~ee~~|Maximum power supply ramp rate (any<br>supply) in Deep Sleep|–|–|10|mV/µs|BOD operation guaranteed|
|**Voltage Monitors DC Specifications**<br>~~ee~~<br>~~eee~~<br>~~a~~<br>~~rs(ns(ts ns~~<br>~~ns~~|||||||
|VHVD0<br>~~eee~~<br>~~a~~<br>~~ee~~|–<br>~~eee~~<br>~~rs~~<br>~~rs~~|1.18<br>~~eee~~<br>~~(ns~~<br>~~ts~~|1.23<br>~~eee~~<br>~~(ts ns~~<br>~~rs~~|1.27<br>~~eee~~<br>~~ns~~<br>~~ts~~|V<br>~~eee~~<br>~~ns~~<br>~~I~~|–<br>~~eee~~|
|VHVDI1<br>~~a~~<br>~~ee~~<br>~~ee~~|–<br>~~rs ~~<br>~~rs~~<br>~~rs~~|1.38<br> ~~(ns ~~<br>~~ts~~<br>~~tts~~|1.43<br> ~~(ts ns~~<br>~~rs~~<br>~~ss~~|1.47<br>~~ns~~<br>~~ts~~<br>~~ss~~|V<br>~~ns~~<br>~~I~~<br>~~Is~~|–|
|VHVDI2<br>~~ee~~<br>~~ee~~<br>~~ee~~|–<br>~~rs ~~<br>~~rs~~<br>~~rs~~|1.57<br> ~~ts~~<br>~~tts~~<br>~~ts~~|1.63<br>~~rs ~~<br>~~ss~~<br>~~rs~~|1.68<br> ~~ts ~~<br>~~ss~~<br>~~ts~~|V<br> ~~I~~<br>~~Is~~<br>~~I~~|–|
|VHVDI3<br>~~ee~~<br>~~ee~~<br>~~ee~~|–<br>~~rs ~~<br>~~rs~~<br>~~rs~~|1.76<br> ~~tts ~~<br>~~ts~~<br>~~tts~~|1.83<br> ~~ss~~<br>~~rs~~<br>~~ss~~|1.89<br>~~ss ~~<br>~~ts~~<br>~~ss~~|V<br> ~~Is~~<br>~~I~~<br>~~Is~~|–|
|VHVDI4<br>~~ee~~<br>~~ee~~<br>~~ee~~|–<br>~~rs ~~<br>~~rs~~<br>~~rs~~|1.95<br> ~~ts~~<br>~~tts~~<br>~~ts~~|2.03<br>~~rs ~~<br>~~ss~~<br>~~rs~~|2.1<br> ~~ts ~~<br>~~ss~~<br>~~ts~~|V<br> ~~I~~<br>~~Is~~<br>~~I~~|–|
|VHVDI5<br>~~ee~~<br>~~ee~~<br>~~ee~~|–<br>~~rs ~~<br>~~rs~~<br>~~rs~~|2.05<br> ~~tts ~~<br>~~ts~~<br>~~tts~~|2.13<br> ~~ss~~<br>~~rs~~<br>~~ss~~|2.2<br>~~ss ~~<br>~~ts~~<br>~~ss~~|V<br> ~~Is~~<br>~~I~~<br>~~Is~~|–|
|VHVDI6<br>~~ee~~<br>~~ee~~<br>~~ee~~|–<br>~~rs ~~<br>~~rs~~<br>~~rs~~|2.15<br> ~~ts~~<br>~~tts~~<br>~~ts~~|2.23<br>~~rs ~~<br>~~ss~~<br>~~rs~~|2.3<br> ~~ts ~~<br>~~ss~~<br>~~ts~~|V<br> ~~I~~<br>~~Is~~<br>~~I~~|–|
|VHVDI7<br>~~ee~~<br>~~ee~~<br>~~ee~~|–<br>~~rs ~~<br>~~rs~~<br>~~rs~~|2.24<br> ~~tts ~~<br>~~ts~~<br>~~tts~~|2.33<br> ~~ss~~<br>~~rs~~<br>~~ss~~|2.41<br>~~ss ~~<br>~~ts~~<br>~~ss~~|V<br> ~~Is~~<br>~~I~~<br>~~Is~~|–|
|VHVDI8<br>~~ee~~<br>~~ee~~<br>~~ee~~|–<br>~~rs ~~<br>~~rs~~<br>~~rs~~|2.34<br> ~~ts~~<br>~~tts~~<br>~~ts~~|2.43<br>~~rs ~~<br>~~ss~~<br>~~rs~~|2.51<br> ~~ts ~~<br>~~ss~~<br>~~ts~~|V<br> ~~I~~<br>~~Is~~<br>~~I~~|–|
|VHVDI9<br>~~ee~~<br>~~ee~~<br>~~ee~~|–<br>~~rs ~~<br>~~rs~~<br>~~rs~~|2.44<br> ~~tts ~~<br>~~ts~~<br>~~tts~~|2.53<br> ~~ss~~<br>~~rs~~<br>~~ss~~|2.61<br>~~ss ~~<br>~~ts~~<br>~~ss~~|V<br> ~~Is~~<br>~~I~~<br>~~Is~~|–|
|VHVDI10<br>~~ee~~<br>~~ee~~<br>~~ee~~|–<br>~~rs ~~<br>~~rs~~<br>~~rs~~|2.53<br> ~~ts~~<br>~~tts~~<br>~~ts~~|2.63<br>~~rs ~~<br>~~ss~~<br>~~rs~~|2.72<br> ~~ts ~~<br>~~ss~~<br>~~ts~~|V<br> ~~I~~<br>~~Is~~<br>~~I~~|–|
|VHVDI11<br>~~ee~~<br>~~ee~~<br>~~ee~~|–<br>~~rs ~~<br>~~rs~~<br>~~rs~~|2.63<br> ~~tts ~~<br>~~ts~~<br>~~tts~~|2.73<br> ~~ss~~<br>~~rs~~<br>~~ss~~|2.82<br>~~ss ~~<br>~~ts~~<br>~~ss~~|V<br> ~~Is~~<br>~~I~~<br>~~Is~~|–|
|VHVDI12<br>~~ee~~<br>~~ee~~<br>~~ee~~|–<br>~~rs ~~<br>~~rs~~<br>~~rs~~|2.73<br> ~~ts~~<br>~~tts~~<br>~~ts~~|2.83<br>~~rs ~~<br>~~ss~~<br>~~rs~~|2.92<br> ~~ts ~~<br>~~ss~~<br>~~ts~~|V<br> ~~I~~<br>~~Is~~<br>~~I~~|–|
|VHVDI13<br>~~ee~~<br>~~ee~~<br>~~ee~~|–<br>~~rs ~~<br>~~rs~~<br>~~rs~~|2.82<br> ~~tts ~~<br>~~ts~~<br>~~tts~~|2.93<br> ~~ss~~<br>~~rs~~<br>~~ss~~|3.03<br>~~ss ~~<br>~~ts~~<br>~~ss~~|V<br> ~~Is~~<br>~~I~~<br>~~Is~~|–|
|VHVDI14<br>~~ee~~<br>~~ee~~<br>~~ee~~|–<br>~~rs ~~<br>~~rs~~<br>~~rs~~|2.92<br> ~~ts~~<br>~~tts~~<br>~~ts~~|3.03<br>~~rs ~~<br>~~ss~~<br>~~rs~~|3.13<br> ~~ts ~~<br>~~ss~~<br>~~ts~~|V<br> ~~I~~<br>~~Is~~<br>~~I~~|–|
|VHVDI15<br>~~ee~~<br>~~ee~~<br>~~ee~~|–<br>~~rs ~~<br>~~rs~~<br>~~rs~~|3.02<br> ~~tts ~~<br>~~ts~~<br>~~PRRs~~|3.13<br> ~~ss~~<br>~~rs~~<br>~~ss~~|3.23<br>~~ss ~~<br>~~ts~~<br>~~ss~~|V<br> ~~Is~~<br>~~I~~<br>~~ts~~|–|
|LVI_IDD<br>~~ee~~<br>~~ee~~|Block current<br>~~rs ~~<br>~~rs~~|–<br> ~~ts~~<br>~~PRRs~~|5<br>~~rs ~~<br>~~ss~~|15<br> ~~ts ~~<br>~~ss~~|µA<br> ~~I~~<br>~~ts~~|–|
|**Voltage Monitors AC Specification**<br>~~ee~~<br>~~rs PRRs ss~~<br>~~ts~~<br>~~eee~~<br>~~a~~<br>~~ns(Isns~~<br>~~ts~~|||||||
|TMONTRIP<br>~~eee~~<br>~~a~~|Voltage monitor trip time<br>~~eee~~<br>~~ns~~|–<br>~~eee~~<br>~~(Is~~|–<br>~~eee~~<br>~~ns~~|170<br>~~eee~~<br>~~ns~~|ns<br>~~eee~~<br>~~ts~~|–<br>~~eee~~|
Document Number: 002-24085 Rev. *A
Page 40 of 59
**CYBLE-416045-02**
## _SWD Interface_
## **Table 29. SWD and Trace Specifications**
**Parameter Description Min Typ Max Unit Details/Conditions** ~~a~~ **SWD and Trace Interface** ~~a~~ F_SWDCLK2 1.71 V VDDD 3.6 V – – 25 MHz LP mode. VCCD = 1.1 V ~~a~~ F_SWDCLK2L 1.71 V VDDD 3.6 V – – 12 MHz ULP mode. VCCD = 0.9 V. ~~a~~ T_SWDI_SETUP T = 1/f SWDCLK 0.25 * T – – ns – ~~a~~ T_SWDI_HOLD T = 1/f SWDCLK 0.25 * T – – ns – ~~a~~ T_SWDO_VALID T = 1/f SWDCLK – – 0.5 * T ns – ~~a~~ T_SWDO_HOLD T = 1/f SWDCLK 1 – – ns – F_TRCLK_LP1 With Trace Data setup/hold times of 2/1 ns respectively – – 75 MHz LP mode. VDD = 1.1 V ~~aee~~ F_TRCLK_LP2 With Trace Data setup/hold times of 3/2 ns respectively – – 70 MHz LP mode. VDD = 1.1 V ~~aee~~ F_TRCLK_ULP With Trace Data setup/hold times of 3/2 ns respectively – – 25 MHz ULP mode. VDD = 0.9 V ~~a~~
_Internal Main Oscillator_
## **Table 30. IMO DC Specifications**
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|IIMO1|IMO operating current at 8 MHz|–|9|15|µA|–|
**Table 31. IMO AC Specifications**
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|FIMOTOL1|Frequency variation centered on 8 MHz|–|–|±2|%|–|
|TJITR|Cycle-to-Cycle and Period jitter|–|250|–|ps|–|
_Internal Low-Speed Oscillator_
## **Table 32. ILO DC Specification**
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|IILO2|ILO operating current at 32 kHz|–|0.3|0.7|µA|–|
**Table 33. ILO AC Specifications**
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|TSTARTILO1|ILO startup time|–|–|7|µs|Startup time to 95% of final<br>frequency|
|TLIODUTY|ILO duty cycle|45|50|55|%|–|
|FILOTRIM1|32-kHz trimmed frequency|28.8|32|35.2|kHz|10% variation|
Document Number: 002-24085 Rev. *A
Page 41 of 59
**CYBLE-416045-02**
**Table 34. UDB AC Specifications**
|**Parameter**<br>**Description**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**<br>**Details/Conditions**<br>~~a~~|
|---|
|**Data Path Performance**<br>~~Ce~~|
|FMAX-TIMER<br>Maximum frequency of 16-bit timer in a UDB pair<br>–<br>–<br>100<br>MHz<br>–<br>~~a ee~~|
|FMAX-ADDER<br>Maximum frequency of 16-bit adder in a UDB pair<br>–<br>–<br>100<br>MHz<br>–<br>FMAX_CRC<br>Maximum frequency of 16-bit CRC/PRS in a UDB<br>pair<br>–<br>–<br>100<br>MHz<br>–<br>**PLD Performance in UDB**<br>FMAX_PLD<br>Maximum frequency of 2-pass PLD function in a<br>UDB pair<br>–<br>–<br>100<br>MHz<br>–<br>**Clock to Output Performance**<br>TCLK_OUT_UDB1<br>Propagation delay for clock in to data out<br>–<br>5<br>–<br>ns<br>–<br>**UDB Port Adapter Specifications**<br>_Conditions: 10-pF load, 3-V VDDIO and VDDD_<br>TLCLKDO<br>LCLKto output delay<br>–<br>–<br>11<br>ns<br>–<br>~~a ee~~<br>~~a~~<br>~~ee ee~~<br>~~Ce~~<br>~~a~~<br>~~ee ee~~<br>~~Ce~~<br>~~**a**~~<br>~~ee ee~~<br>~~]~~<br>~~oO~~<br>~~a~~|
|TDINLCLK<br>Input setup time to LCLCKrising edge<br>–<br>–<br>7<br>ns<br>–<br>~~a~~|
|TDINLCLKHLD<br>Input hold time from LCLKrising edge<br>5<br>–<br>–<br>ns<br>–<br>~~a~~|
|TLCLKHIZ<br>LCLKto output tristate<br>–<br>–<br>28<br>ns<br>–<br>~~a~~|
|TFLCLK<br>LCLKfrequency<br>–<br>–<br>33<br>MHz<br>–<br>~~a~~|
|TLCLKDUTY<br>LCLKduty cycle (percentage high)<br>40%<br>–<br>60%<br>%<br>–<br>~~a~~|
|**Table 35. Audio Subsystem Specifications**|
|**Parameter**<br>**Description**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**<br>**Details/Conditions**|
|**Audio Subsystem specifications**<br>**PDM Specifications**<br>~~(a~~<br>~~a~~|
|PDM_IDD1<br>PDM active current, Stereo operation,<br>1-MHz clock<br>–<br>175<br>–<br>µA<br>16-bit audio at 16 ksps<br>~~a~~|
|PDM_IDD2<br>PDM active current, Stereo operation,<br>3-MHz clock<br>–<br>600<br>–<br>µA<br>24-bit audio at 48 ksps<br>~~a~~|
|PDM_JITTER<br>RMS jitter in PDM clock<br>–200<br>–<br>200<br>ps<br>~~a~~|
|PDM_CLK<br>PDM clock speed<br>0.384<br>–<br>3.072<br>MHz<br>PDM_BLK_CLK<br>PDM block input clock<br>1.024<br>–<br>49.152<br>MHz<br>~~a~~<br>~~a~~|
|PDM_SETUP<br>Data input setup time to PDM_CLK edge<br>10<br>–<br>–<br>ns<br>~~a~~|
|PDM_HOLD<br>Data input hold time to PDM_CLK edge<br>10<br>–<br>–<br>ns<br>~~a~~|
|PDM_OUT<br>Audio sample rate<br>8<br>–<br>48<br>ksps<br>~~a~~|
|PDM_WL<br>Word length<br>16<br>–<br>24<br>bits<br>~~a~~|
|PDM_SNR<br>Signal-to-noise ratio (A-weighted)<br>–<br>100<br>–<br>dB<br>PDM input, 20 Hz to 20 kHz BW<br>~~a~~|
|PDM_DR<br>Dynamic range (A-weighted)<br>–<br>100<br>–<br>dB<br>20 Hz to 20 kHz BW, -60 dB FS<br>~~a~~|
|PDM_FR<br>Frequency response<br>–0.2<br>–<br>0.2<br>dB<br>DC to 0.45. DC Blocking filter<br>OFF<br>~~a~~|
|PDM_SB<br>Stop band<br>–<br>0.566<br>–<br>f<br>–<br>PDM_SBA<br>Stop band attenuation<br>–<br>60<br>–<br>dB<br>–<br>~~a~~<br>~~a~~|
Document Number: 002-24085 Rev. *A
Page 42 of 59
**CYBLE-416045-02**
**Table 35. Audio Subsystem Specifications** (continued)
|**Parameter**<br>~~ee~~<br>~~ee~~|**Description**<br>~~ee~~<br>~~rs~~|**Min**<br>~~ee~~<br>~~rrr~~|**Typ**<br>~~eee~~<br>~~ts~~|**Max**<br>~~eee~~<br>~~Ss~~|**Unit**<br>~~eee~~<br>~~Ss~~|**Details/Conditions**<br>~~ee~~|
|---|---|---|---|---|---|---|
|PDM_GAIN<br>~~ee~~<br>~~ee~~<br>~~ee~~|Adjustable gain<br>~~ee~~<br>~~rs~~<br>~~ers~~|–12<br>~~ee ~~<br>~~rrr~~<br>~~ers~~<br>~~rer~~|–<br> ~~eee~~<br>~~ts~~<br>~~ers~~<br>~~rs~~|10.5<br>~~eee~~<br>~~Ss~~<br>~~ers~~<br>~~re~~|dB<br>~~eee~~<br>~~Ss~~<br>~~ers~~<br>~~es~~|PDM to PCM, 1.5 dB/step<br>~~ee~~<br>~~ers~~|
|PDM_ST<br>~~ee~~<br>~~ee~~|Startup time<br>~~rs ~~<br>~~ers~~|–<br> ~~rrr ~~<br>~~ers~~<br>~~rer~~|48<br> ~~ts ~~<br>~~ers~~<br>~~rs~~|–<br> ~~Ss~~<br>~~ers~~<br>~~re~~|–<br>~~Ss~~<br>~~ers~~<br>~~es~~|Word Select (WS) cycles<br>~~ers~~|
|**I2S Specifications (same for LP and ULP modes unless stated otherwise)**<br>~~eeers~~<br>~~rer~~<br>~~rs re es~~<br>~~ee~~<br>~~rsrsss~~|||||||
|I2S_WORD<br>~~ee~~<br>~~a~~|Length of I2S word<br>~~rs~~<br>|8<br>~~rs~~<br>~~ee~~<br>|–<br>~~ss~~<br>**e**e<br>|32<br>~~ss~~<br>~~ee~~|bits<br>~~ss~~|–|
|I2S_WS<br>~~ee~~<br>~~a ee~~<br>~~a~~<br>~~a~~|Word clock frequency in LP mode<br>~~rs ~~<br>~~ee~~<br><br>|–<br> ~~rs ~~<br>~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|–<br> ~~ss~~<br>~~ee~~<br>**e**e<br><br>**e**e<br>|192<br>~~ss~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|kHz<br>~~ss~~<br>~~ee~~|12.288 MHz bit clock with 32-bit<br>word<br>~~ee~~|
|I2S_WS_U<br>~~a e~~<br>~~a~~|Word clock frequency in ULP mode<br>~~e~~<br>|–<br>~~ee~~ <br>~~e~~<br>~~ee~~<br><br>~~ee~~|–<br> **e**e <br>~~e~~<br>**e**e<br><br>~~ee~~|48<br> ~~ee~~<br>~~ee~~<br>~~ee~~|kHz|3.072 MHz bit clock with 32-bit<br>word|
|I2S_WS_TDM<br>~~a e~~<br>~~a~~|Word clock frequency in TDM mode for<br>LP<br>~~e~~<br>|–<br>~~ee~~ <br>~~e~~<br>~~ee~~<br>~~e~~<br>|–<br> **e**e <br>~~e~~<br>~~ee~~<br>~~e~~~~**e**~~<br>|48<br> ~~ee~~<br>~~ee~~<br>~~**e**~~|kHz<br>~~eee~~|8 32-bit channels<br>~~eee~~|
|I2S_WS_TDM_U<br>~~ee~~<br>~~a~~|Word clock frequency in TDM mode for<br>ULP<br>~~ee~~<br>|–<br>~~ee ~~<br>~~ee~~<br>~~e~~<br>|–<br> ~~ee ~~<br>~~ee~~<br>~~e~~~~**e**~~<br>|12<br> ~~ee~~<br>~~ee~~<br>~~**e**~~|kHz<br>~~ee~~<br>~~eee~~|8 32-bit channels<br>~~ee~~<br>~~eee~~|
|**I2S Slave Mode**<br>~~ee~~<br>~~e~~~~**e**eee~~<br>~~a~~<br>~~ee~~<br>~~eee~~|||||||
|TS_WS<br>~~ee~~<br>~~a e~~|WS setup time to the following rising edge<br>of SCK for LP mode<br>~~ee~~<br>~~e~~|5<br>~~ee~~<br>~~e~~<br>~~e~~<br>~~ee~~|–<br>~~ee~~<br>~~e~~~~**e**~~<br>~~e~~|–<br>~~ee~~<br>~~**e** ~~<br>~~e~~|ns<br>~~ee~~<br> ~~eee~~<br>~~ee~~|–<br>~~ee~~<br>~~eee~~|
|TS_WS|WS setup time to the following rising edge<br>of SCK for ULP mode|11<br>~~ee~~|–|–<br>~~e ~~|ns<br> ~~ee~~|–|
|TH_WS|WS hold time to the following edge of SCK|TMCLK_<br>SOC + 5|–|–|ns|–|
|TD_SDO|Delay time of TX_SDO transition from<br>edge of TX_SCK for LP mode|-(TMCLK_<br>SOC + 25)|–|TMCLK_<br>SOC+25|ns|Associated clock edge depends<br>on selected polarity|
|TD_SDO<br>~~es~~|Delay time of TX_SDO transition from<br>edge of TX_SCK for ULP mode<br>~~es~~|-(TMCLK_<br>SOC + 70)<br>~~es~~|–|TMCLK_<br>SOC+70|ns|Associated clock edge depends<br>on selected polarity|
|TS_SDI<br>~~es~~|RX_SDI setup time to the following edge<br>of RX_SCK in LP mode<br>~~es~~|5<br>~~es~~|–|–|ns|–|
|TS_SDI<br>~~es~~|RX_SDI setup time to the following edge<br>of RX_SCK in ULP mode<br>~~es ~~|11<br> ~~es~~|–|–|ns|–|
|TH_SDI|RX_SDI hold time to the rising edge of<br>RX_SCK|TMCLK_<br>SOC + 5<br>~~rr~~|–<br>~~rs~~|–<br>~~rs~~|ns<br>~~rs~~|–|
|TSCKCY<br>~~a~~|TX/RX_SCK bit clock duty cycle<br>~~errs~~|45<br>~~errs~~<br>~~rr~~|–<br>~~errs~~<br>~~rs~~|55<br>~~errs~~<br>~~rs~~|%<br>~~errs~~<br>~~rs~~|–<br>~~errs~~|
|**I2S Master Mode**<br>~~a errs~~<br>~~rr~~<br>~~rs rs~~<br>**e**e<br>~~a~~|||||||
|TD_WS<br>~~a ~~<br>~~a~~<br>~~a~~|WS transition delay from falling edge of<br>SCK in LP mode<br> ~~es~~<br>|–10<br>~~es~~<br><br>~~ee ee~~|–<br>~~es~~<br>**e**e<br><br>~~ee~~|20<br>~~es~~<br>~~ee~~|ns<br>~~es~~<br>~~ee~~|–<br>~~es~~|
|TD_WS_U<br>~~a e~~<br>~~a~~<br>~~a~~|WS transition delay from falling edge of<br>SCK in ULP mode<br>~~e~~<br>~~es~~<br>|–10<br>~~e~~<br>~~ee ee~~<br>~~es~~<br>|–<br>**e**e<br>~~e~~<br>~~ee~~<br>**e**e<br>|40<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|–|
|TD_SDO<br>~~a~~<br>~~a~~<br>~~a~~|SDO transition delay from falling edge of<br>SCK in LP mode<br>~~es~~<br>|–10<br>~~ee ee~~<br>~~es~~<br><br>~~ee~~|–<br>~~ee~~<br>**e**e<br><br>~~**ee**~~|20<br>~~ee ~~<br>~~ee~~<br>~~**ee**~~|ns<br> ~~ee~~<br>~~ee~~<br>~~ee~~|–|
|TD_SDO<br>~~a e~~<br>~~a~~|SDO transition delay from falling edge of<br>SCK in ULP mode<br>~~es~~<br>~~e~~<br>~~es~~|–10<br>~~es~~<br>~~e~~<br>~~ee~~<br>~~ee~~|–<br>**e**e<br>~~e~~<br>~~**ee**~~|40<br>~~ee~~<br>~~**ee**~~|ns<br>~~ee~~<br>~~ee~~<br>~~ee~~|–|
|TS_SDI<br>~~a~~|SDI setup time to the associated edge of<br>SCK<br>~~es~~|5<br>~~ee ~~<br>~~ee~~|–<br> ~~**ee**~~|–<br>~~**ee** ~~|ns<br> ~~ee~~<br>~~ee~~|Associated clock edge depends<br>on selected polarity|
Document Number: 002-24085 Rev. *A
Page 43 of 59
**CYBLE-416045-02**
**Table 35. Audio Subsystem Specifications** (continued)
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|TH_SDI<br>~~a~~<br>~~pO~~|SDI hold time to the associated edge of<br>SCK<br>~~a~~<br>|TMCLK_<br>SOC + 5<br>|–<br>|–<br>|ns<br>|T is TX/RX_SCK bit clock<br>period. Associated clock edge<br>depends on selected polarity<br>|
|TSCKCY<br>~~pO~~|SCK bit clock duty cycle<br>|45<br>|–<br>|55<br>|%<br>|–<br>|
|FMCLK_SOC<br>~~pOeG~~<br>~~pO~~|MCLK_SOC frequency in LP mode<br>~~eG~~|1.024<br>~~eG~~|–<br>~~eG~~|98.304<br>~~eG~~|MHz<br>~~eG~~|FMCLK_SOC = 8 * Bit-clock<br>~~eG~~|
|FMCLK_SOC_U<br>~~eG~~<br>~~pO~~<br>~~pO~~|MCLK_SOC frequency in ULP mode<br>~~eG~~<br>|1.024<br>~~eG~~<br>|–<br>~~eG~~<br>|24.576<br>~~eG~~<br>|MHz<br>~~eG~~<br>|FMCLK_SOC_U = 8 * Bit-clock<br>~~eG~~<br>|
|TMCLKCY<br>~~pO~~<br>~~pO~~|MCLK_SOC duty cycle<br>|45<br>|–<br>|55<br>|%<br>|–<br>|
|TJITTER<br>~~pOpe~~|MCLK_SOC input jitter<br>~~pe~~|–100<br>~~pe~~|–<br>~~pe~~|100<br>~~pe~~|ps<br>~~pe~~|–<br>~~pe~~|
Document Number: 002-24085 Rev. *A
Page 44 of 59
**CYBLE-416045-02**
**Table 37. BLE Subsystem Specifications**
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|**BLE Subsystem specifications**<br>~~Rs~~<br>~~CR~~|||||||
|**RF Receiver Specifications(1 Mbps)**<br>~~Rs~~<br>~~CReeee~~<br>~~eeeeesee~~<br>~~ee~~|||||||
|RXS, IDLE<br>~~CRee~~<br>~~ee~~<br>~~ee~~|RX Sensitivity with Ideal Transmitter<br>~~ee~~<br>~~**e**s~~|–<br>~~ee~~<br>~~ee~~|–95<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~es~~|dBm<br>~~ee~~<br>~~ee~~|Across RF operating<br>frequencyrange<br>~~ee~~|
|RXS, IDLE<br>~~ee~~<br>~~ee~~<br>~~ee~~|RX Sensitivity with Ideal Transmitter<br>~~ee~~<br>~~**e**s~~<br>~~e~~|–<br>~~ee~~<br>~~ee~~<br>~~ee~~|–93<br>~~ee~~<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~es~~<br>~~ee~~|dBm<br>~~ee~~<br>~~ee~~<br>~~ee~~|255-byte packet length,<br>across frequencyrange<br>~~ee~~|
|RXS, DIRTY<br>~~ee~~<br>~~ee~~|RX Sensitivity with Dirty Transmitter<br>~~**e**s~~<br>~~e~~|–<br>~~ee ~~<br>~~ee~~|–92<br> ~~ee ~~<br>~~ee~~|–<br> ~~es ~~<br>~~ee~~|dBm<br> ~~ee~~<br>~~ee~~|RF-PHY Specification<br>(RCV-LE/CA/01/C)|
|PRXMAX<br>~~ee~~|Maximum received signal strength at < 0.1%<br>PER<br>~~**e**s~~<br>~~e ~~|–<br> ~~ee ~~|0<br> ~~ee ~~|–<br> ~~ee ~~|dBm<br> ~~ee~~|RF-PHY Specification<br>(RCV-LE/CA/06/C)|
|CI1|Co-channel interference,<br>Wanted Signal at –67 dBm and Interferer at<br>FRX|–|9|21|dB|RF-PHY Specification<br>(RCV-LE/CA/03/C)|
|CI2|Adjacent channel interference<br>Wanted Signal at –67 dBm and Interferer at<br>FRX ± 1 MHz|–|3|15|dB|RF-PHY Specification<br>(RCV-LE/CA/03/C)|
|CI3|Adjacent channel interference<br>Wanted Signal at –67 dBm and Interferer at<br>FRX ± 2 MHz|–|–26|–17|dB|RF-PHY Specification<br>(RCV-LE/CA/03/C)|
|CI4|Adjacent channel interference<br>Wanted Signal at –67 dBm and Interferer at<br>FRX ± 3 MHz|–|–33|–27|dB|RF-PHY Specification<br>(RCV-LE/CA/03/C)|
|CI5|Adjacent channel interference<br>Wanted Signal at –67 dBm and Interferer at<br>Image frequency (FIMAGE)|–|–20|–9|dB|RF-PHY Specification<br>(RCV-LE/CA/03/C)|
|CI6<br>~~Cn~~|Adjacent channel interference<br>Wanted Signal at –67 dBm and |Interferer at<br>Image frequency (FIMAGE ± 1 MHz )|–|–28|–15|dB|RF-PHY Specification<br>(RCV-LE/CA/03/C)|
|**RF Receiver Specifications(2 Mbps)**<br>~~Cn~~<br>~~ee~~<br>~~eeeeeeee~~|||||||
|RXS, IDLE<br>~~Cn~~<br>~~ee~~<br>~~ee~~|RX Sensitivity with Ideal Transmitter<br>~~ee~~<br>~~es~~|–<br>~~ee~~<br>~~ee~~|–92<br>~~ee~~<br>~~et~~|–<br>~~ee~~<br>~~es~~|dBm<br>~~ee~~|Across RF operating<br>frequencyrange|
|RXS, IDLE<br>~~ee~~<br>~~ee~~<br>~~ee~~|RX Sensitivity with Ideal Transmitter<br>~~ee ~~<br>~~es~~<br>~~rs~~|–<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|–90<br> ~~ee ~~<br>~~et~~|–<br> ~~ee~~<br>~~es~~|dBm<br>~~ee~~|255-byte packet length,<br>across frequencyrange|
|RXS, DIRTY<br>~~ee~~<br>~~ee~~|RX Sensitivity with Dirty Transmitter<br>~~es ~~<br>~~rs~~|–<br> ~~ee ~~<br>~~ee~~|–89<br> ~~et~~|–<br>~~es ~~|dBm<br> ~~ee~~|RF-PHY Specification<br>(RCV-LE/CA/01/C)|
|PRXMAX<br>~~ee~~|Maximum received signal strength at < 0.1%<br>PER<br>~~rs ~~|–<br> ~~ee~~|0|–|dBm|RF-PHY Specification<br>(RCV-LE/CA/06/C)|
|CI1|Co-channel interference,<br>Wanted Signal at –67 dBm and Interferer at<br>FRX|–|9|21|dB|RF-PHY Specification<br>(RCV-LE/CA/03/C)|
|CI2|Adjacent channel interference<br>Wanted Signal at –67 dBm and Interferer at<br>FRX ± 2 MHz|–|3|15|dB|RF-PHY Specification<br>(RCV-LE/CA/03/C)|
|CI3|Adjacent channel interference<br>Wanted Signal at –67 dBm and Interferer at<br>FRX ± 4 MHz|–|-26|–17|dB|RF-PHY Specification<br>(RCV-LE/CA/03/C)|
|CI4|Adjacent channel interference<br>Wanted Signal at –67 dBm and Interferer at<br>‚â• FRX ± 6 MHz|–|–33|–27|dB|RF-PHY Specification<br>(RCV-LE/CA/03/C)|
Document Number: 002-24085 Rev. *A
Page 45 of 59
**CYBLE-416045-02**
**Table 37. BLE Subsystem Specifications** (continued)
|**Parameter**<br>~~Pf~~<br>~~p~~|**Description**<br>~~Pf~~<br>|**Min**<br>~~Pf~~<br>~~ee~~<br>|**Typ**<br>~~Pf~~<br>~~ee~~<br>|**Max**<br>~~Pf~~<br>~~ee~~<br>|**Unit**<br>~~Pf~~<br>~~ee~~<br>|**Details/Conditions**<br>~~Pf~~<br>~~eee~~<br>|
|---|---|---|---|---|---|---|
|CI5<br>~~ee~~<br>~~p~~|Adjacent channel interference<br>Wanted Signal at –67 dBm and Interferer at<br>Image frequency (FIMAGE)<br>~~ee~~<br>|–<br>~~ee~~<br>~~ee~~<br>|–20<br>~~ee~~<br>~~ee~~<br>|–9<br>~~ee~~<br>~~ee~~<br>|dB<br>~~ee~~<br>~~ee~~<br>|RF-PHY Specification<br>(RCV-LE/CA/03/C)<br>~~ee~~<br>~~eee~~<br>|
|CI6<br>~~ee~~<br>~~p|]~~|Adjacent channel interference<br>Wanted Signal at –67 dBm and Interferer at<br>Image frequency (FIMAGE ± 2 MHz)<br>~~ee~~<br>~~|]~~|–<br>~~ee~~<br>~~ee~~<br>~~|]~~|–28<br>~~ee~~<br>~~ee~~<br>~~|]~~|–15<br>~~ee~~<br>~~ee~~<br>~~|]~~|dB<br>~~ee~~<br>~~ee~~<br>~~|]~~|RF-PHY Specification<br>(RCV-LE/CA/03/C)<br>~~ee~~<br>~~eee~~<br>~~|]~~|
|**RF Receiver Specification(1 and 2 Mbps)**<br>~~eeeee~~<br>~~p|]~~|||||||
|OBB1<br>~~p~~<br>~~|~~|Out of Band blocking<br>Wanted Signal at –67 dBm and Interferer at<br>F = 30 -2000 MHz<br><br>~~|~~|–30<br>~~ee~~<br><br>~~|~~|–27<br>~~ee~~<br><br>~~|~~|–<br>~~ee~~<br><br>~~|~~|dBm<br>~~ee ~~<br><br>~~|~~|RF-PHY Specification<br>(RCV-LE/CA/04/C)<br> ~~eee~~<br><br>~~|~~|
|OBB2<br>~~fo~~|Out of Band blocking<br>Wanted Signal at –67 dBm and Interferer at<br>F = 2003 -2399 MHz<br>~~fo~~|–35<br>~~fo~~|–27<br>~~fo~~|–<br>~~fo~~|dBm<br>~~fo~~|RF-PHY Specification<br>(RCV-LE/CA/04/C)<br>~~fo~~|
|OBB3<br>~~|~~|Out of Band blocking<br>Wanted Signal at –67 dBm and Interferer at<br>F= 2484-2997 MHz<br>~~|~~|–35<br>~~|~~|–27<br>~~|~~|–<br>~~|~~|dBm<br>~~|~~|RF-PHY Specification<br>(RCV-LE/CA/04/C)<br>~~|~~|
|OBB4<br>~~|~~<br>~~|~~|Out of Band blocking<br>Wanted Signal at –67 dBm and Interferer at<br>F= 3000-12750 MHz<br>~~|~~<br>~~|~~|–30<br>~~|~~<br>~~|~~|–27<br>~~|~~<br>~~|~~|–<br>~~|~~<br>~~|~~|dBm<br>~~|~~<br>~~|~~|RF-PHY Specification<br>(RCV-LE/CA/04/C)<br>~~|~~<br>~~|~~|
|IMD<br>~~|~~|Intermodulation performance<br>Wanted Signal at –64 dBm and 1 Mbps BLE,<br>3rd, 4th and 5th offset channel<br>~~|~~|–50<br>~~|~~|–<br>~~|~~|–<br>~~|~~|dBm<br>~~|~~<br>~~ee~~|RF-PHY Specification<br>(RCV-LE/CA/05/C)<br>~~|~~<br>~~ee~~|
|RXSE1<br>~~|~~<br>~~ee~~|Receiver Spurious emission<br>30 MHz to 1.0 GHz<br>~~|~~<br>~~ee~~|–<br>~~|~~<br>~~ee~~|–<br>~~|~~<br>~~ee~~|–57<br>~~|~~<br>~~ee~~|dBm<br>~~|~~<br>~~ee~~<br>~~ee~~|100 kHz measurement<br>bandwidth<br>ETSI EN300 328 V2.1.1<br>~~|~~<br>~~ee~~<br>~~ee~~|
|RXSE2<br>~~ee~~<br>~~Ff~~|Receiver Spurious emission<br>1.0 GHz to 12.75 GHz<br>~~ee~~<br>~~Ff~~|–<br>~~ee~~<br>~~Ff~~|–<br>~~ee~~<br>~~Ff~~|–53<br>~~ee~~<br>~~Ff~~|dBm<br>~~ee~~<br>~~ee~~<br>~~Ff~~|1 MHz measurement<br>bandwidth<br>ETSI EN300 328 V2.1.1<br>~~ee~~<br>~~ee~~<br>~~Ff~~|
|**RF Transmitter Specifications**<br>~~rs~~<br>~~rsre~~<br>~~re~~|||||||
|TXP, ACC<br>~~rs~~<br>~~rs~~|RF Power Accuracy<br>~~rs~~<br>|–<br>~~re~~<br>|–<br>~~re~~<br>|1<br>~~re~~<br>|dB<br>|–|
|TXP, RANGE<br>~~rs~~<br>~~rs~~|FrequencyAccuracy<br>~~rs ~~<br>|–<br> ~~re~~<br>|24<br>~~re~~<br>|–<br>~~re~~<br>|dB<br>|–20 dBm to +4 dBm|
|TXP, 0 dBm<br>~~rsee~~|Output Power, 0 dB Gain Setting<br>~~ee~~|–<br>~~ee~~|0<br>~~ee~~|–<br>~~ee~~|dBm<br>~~ee~~|–|
|TXP, MAX<br>~~ee~~|Output Power, Maximum Power Setting<br>~~ee~~|–<br>~~ee~~|4<br>~~ee~~|–<br>~~ee~~|dBm<br>~~ee~~|–|
|TXP, MIN<br>~~ee~~<br>~~es~~<br>~~ee~~|Output Power, Minimum Power Setting<br>~~ee~~<br>~~es~~|–<br>~~ee~~<br>~~es~~<br>~~Oe~~|–20<br>~~ee~~<br>~~es~~<br>~~se~~|–<br>~~ee~~<br>~~es~~<br>~~se~~|dBm<br>~~ee~~<br>~~es~~<br>~~ee~~|–<br>~~es~~|
|F2AVG<br>~~es~~<br>~~ee~~<br>~~a~~|Average Frequency Deviation for 10101010<br>pattern<br>~~es~~<br>~~es~~|185<br>~~es~~<br>~~Oe~~|–<br>~~es~~<br>~~se~~|–<br>~~es~~<br>~~se~~|kHz<br>~~es~~<br>~~ee~~|RF-PHY Specification<br>(TRM-LE/CA/05/C)<br>~~es~~|
|F2AVG_2M<br>~~es~~<br>~~ee~~<br>~~a~~<br>~~a~~|Average Frequency Deviation for 10101010<br>pattern for 2 Mbps<br>~~es~~<br>~~es~~<br>~~ee ee~~<br>|370<br>~~es~~<br>~~Oe~~<br>~~ee~~<br>|–<br>~~es~~<br>~~se~~<br>~~**e**e~~<br>|–<br>~~es~~<br>~~se~~<br>~~ee~~|kHz<br>~~es~~<br>~~ee~~|RF-PHY Specification<br>(TRM-LE/CA/05/C)<br>~~es~~|
|F1AVG<br>~~ee~~<br>~~a~~<br>~~a~~<br>~~a~~|Average Frequency Deviation for 11110000<br>pattern<br>~~es~~<br>~~ee ee~~<br>|225<br>~~Oe ~~<br>~~ee~~<br><br>~~ee~~|250<br> ~~se~~<br>~~**e**e~~<br><br>~~es~~|275<br>~~se ~~<br>~~ee~~<br>~~ee~~|kHz<br> ~~ee~~|RF-PHY Specification<br>(TRM-LE/CA/05/C)|
|F1AVG_2M<br>~~a~~<br>~~a ~~<br>~~a~~<br>~~es~~|Average Frequency Deviation for 11110000<br>pattern for 2 Mbps<br>~~es~~<br>~~ee ee~~<br> ~~e~~<br>~~ee~~<br>|450<br>~~ee ~~<br>~~e~~<br>~~ee~~<br>~~ee~~<br>|500<br> ~~**e**e ~~<br>~~e~~<br>~~es~~<br>~~ee~~<br>|550<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>|kHz<br>|RF-PHY Specification<br>(TRM-LE/CA/05/C)<br>|
|EO<br>~~a~~<br>~~es~~<br>~~es~~|Eye opening =F2AVG/F1AVG<br>~~ee~~<br><br>|0.8<br>~~ee ~~<br>~~ee~~<br><br>~~ee~~<br>|–<br> ~~es ~~<br>~~ee~~<br><br>~~(ee~~<br>|–<br> ~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|–<br><br>|RF-PHY Specification<br>(TRM-LE/CA/05/C)<br><br>|
|FTX, ACC<br>~~es~~<br>~~es~~<br>~~es~~|Frequency Accuracy<br>~~ee~~<br>~~es~~<br>|–150<br>~~ee~~<br>~~es~~<br>~~ee~~<br><br>~~Oe~~|–<br>~~ee~~<br>~~es~~<br>~~(ee~~<br><br>~~se~~|150<br>~~ee~~<br>~~es~~<br>~~ee~~<br><br>~~se~~|kHz<br>~~es~~<br><br>~~**ee**~~|RF-PHY Specification<br>(TRM-LE/CA/06/C)<br>~~es~~<br>|
|FTX, MAXDR<br>~~es~~<br>~~es~~<br>~~es~~|Maximum Frequency Drift<br>~~ee ~~<br><br>~~es~~<br>~~es~~|–50<br> ~~ee ~~<br><br>~~ee~~<br>~~es~~<br>~~Oe~~<br>~~ee~~|–<br> ~~ee ~~<br><br>~~(ee~~<br>~~es~~<br>~~se~~<br>~~ee~~|50<br> ~~ee~~<br><br>~~ee~~<br>~~es~~<br>~~se~~<br>~~ee~~|kHz<br><br>~~es~~<br>~~**ee**~~|RF-PHY Specification<br>(TRM-LE/CA/06/C)<br><br>~~es~~|
|FTX, INITDR<br>~~es~~<br>~~es~~|Initial Frequency Drift<br>~~es~~<br>~~es~~|–20<br>~~ee ~~<br>~~es~~<br>~~Oe~~<br>~~ee~~|–<br> ~~(ee ~~<br>~~es~~<br>~~se~~<br>~~ee~~|20<br> ~~ee~~<br>~~es~~<br>~~se~~<br>~~ee~~|kHz<br>~~es~~<br>~~**ee**~~|RF-PHY Specification<br>(TRM-LE/CA/06/C)<br>~~es~~|
Document Number: 002-24085 Rev. *A
Page 46 of 59
**CYBLE-416045-02**
**Table 37. BLE Subsystem Specifications** (continued)
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|FTX, DR|Maximum Drift Rate|–20|–|20|kHz/<br>50µs|RF-PHY Specification<br>(TRM-LE/CA/06/C)|
|IBSE1|In Band Spurious Emission at 2 MHz offset<br>(1 Mbps)<br>In Band Spurious Emission at 4 MHz offset<br>(2 Mbps)|–|–|–20|dBm|RF-PHY Specification<br>(TRM-LE/CA/03/C)|
|IBSE2|In Band Spurious Emission at 3 MHz offset<br>(1 Mbps)<br>In Band Spurious Emission at 6 MHz offset<br>(2 Mbps)|–|–|–30|dBm|RF-PHY Specification<br>(TRM-LE/CA/03/C)|
|TXSE1<br>~~a~~|Transmitter Spurious Emissions (Averaging),<br>< 1.0 GHz|–|–|–55.5|dBm|FCC-15.247|
|TXSE2<br>~~a~~|Transmitter Spurious Emissions (Averaging),<br>> 1.0 GHz|||–41.5|dBm|FCC-15.247|
|**General RF Specification**<br>~~ET~~<br>~~Ce~~<br>~~GOO~~|||||||
|FREQ<br>~~Ce~~<br>~~Ce~~|RF OperatingFrequency<br>~~Ce~~<br>~~Ce~~|2400|–<br>~~GOO~~|2482<br>~~GOO~~<br>~~GOO~~|MHz<br>~~GOO~~<br>~~GOO~~|–<br>~~GOO~~<br>~~GOO~~|
|CHBW<br>~~Ce~~<br>~~Ce~~|Channel Spacing<br>~~Ce~~<br>~~Ce~~|–|2<br>~~GOO~~|–<br>~~GOO~~<br>~~GOO~~|MHz<br>~~GOO~~<br>~~GOO~~|–<br>~~GOO~~<br>~~GOO~~|
|DR1<br>~~Ce~~<br>~~ee~~<br>~~ee~~<br>~~es~~|On-air Data Rate(1 Mbps)<br>~~Ce~~<br>~~ee~~<br>~~I~~<br>|–<br>~~I~~<br>|1000<br>~~I~~<br>|–<br>~~GOO~~<br>~~GO~~<br>~~I~~<br>|Kbps<br>~~GOO~~<br>~~GO~~<br>~~I~~<br>|–<br>~~GOO~~<br>~~GO~~<br>~~I~~<br>~~(~~<br>|
|DR2<br>~~ee~~<br>~~ee~~<br>~~es~~<br>~~ee~~|On-air Data Rate(2 Mbps)<br>~~ee~~<br>~~I~~<br><br>~~ee~~|–<br>~~I~~<br>|2000<br>~~I~~<br>|–<br>~~GO~~<br>~~I~~<br>|Kbps<br>~~GO~~<br>~~I~~<br>|–<br>~~GO~~<br>~~I~~<br>~~(~~<br><br>~~OO~~|
|TXSUP<br>~~ee~~<br>~~es~~<br>~~ee~~|Transmitter Startuptime<br>~~I~~<br>~~eG~~<br>~~ee~~|–<br>~~I~~<br>~~eG~~|80<br>~~I~~<br>~~eG~~<br>~~DCO~~|82<br>~~I~~<br>~~eG~~<br>~~DCO~~|µs<br>~~I~~<br>~~eG~~<br>~~DCO~~|–<br>~~I~~<br>~~(~~<br>~~eG~~<br>~~OO~~<br>~~DCO~~|
|RXSUP<br>~~es~~<br>~~ee~~|Receiver Startuptime<br><br>~~ee~~|–<br>|80<br><br>~~DCO~~|82<br><br>~~DCO~~|µs<br><br>~~DCO~~|–<br>~~(~~<br><br>~~OO~~<br>~~DCO~~|
|**RSSI Specification**<br>~~DCO~~<br>~~En~~|||||||
|RSSI, ACC<br>~~a~~|RSSI Accuracy|–4|–|4|dB|–95 dBm to –20 dBm<br>measurement range|
|RSSI, RES<br>~~a~~|RSSI Resolution|–|1|–|dB|–|
|RSSI, PER<br>~~a~~|RSSI Sample Period|–|6|–|µs|–|
**Table 38. Precision ILO (PILO) Specifications**
Document Number: 002-24085 Rev. *A
Page 47 of 59
**CYBLE-416045-02**
## **Environmental Specifications**
## **Environmental Compliance**
This Cypress BLE module is built in compliance with RoHS and Halogen Free (HF) directives. The Cypress module and components used to produce this module are RoHS and HF compliant.
## **RF Certification**
The CYBLE-416045-02 module is certified under the following RF certification standards:
■ FCC ID: WAP6045
- CE
- ISED: 7922A-6045
■ MIC: 201-180370
## **Environmental Conditions**
Table 39 describes the operating and storage conditions for the Cypress BLE module.
## **Table 39. Environmental Conditions for CYBLE-416045-02**
|**Description**|**Minimum Specification**|**Maximum Specification**|
|---|---|---|
|Operating temperature|–40 °C|85 °C|
|Operating humidity (relative, non-condensation)|5%|85%|
|Thermal ramp rate|–|3 °C/minute|
|Storage temperature|–40 °C|85 °C|
|Storage temperature and humidity|–|85 ° C at 85%|
|ESD: Module integrated into system components[9]|–|15 kV Air<br>2.2 KV Contact|
## **ESD and EMI Protection**
Exposed components require special attention to ESD and EMI.
A grounded conductive layer inside the device enclosure is suggested for EMI and ESD performance. Any openings in the enclosure near the module should be surrounded by a grounded conductive layer to provide ESD protection and a low-impedance path to ground. **Device Handling** : Proper ESD protocol must be followed in manufacturing to ensure component reliability.
> 9. This does not apply to the RF pins (ANT, XTALI, and XTALO). RF pins (ANT, XTALI, and XTALO) are tested for 500 V HBM.
**Note**
Document Number: 002-24085 Rev. *A
Page 48 of 59
**CYBLE-416045-02**
## **Regulatory Information**
## **FCC**
## FCC NOTICE:
The device CYBLE-416045-02 complies with Part 15 of the FCC Rules. The device meets the requirements for modular transmitter approval as detailed in FCC public Notice DA00-1407. Transmitter Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation.
## CAUTION:
The FCC requires the user to be notified that any changes or modifications made to this device that are not expressly approved by Cypress Semiconductor may void the user's authority to operate the equipment.
This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates and can radiate radio frequency energy and, if not installed and used in accordance with the instruction may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures:
■ Reorient or relocate the receiving antenna.
- Increase the separation between the equipment and receiver.
■ Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
- Consult the dealer or an experienced radio/TV technician for help
## LABELING REQUIREMENTS:
The Original Equipment Manufacturer (OEM) must ensure that FCC labeling requirements are met. This includes a clearly visible label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor FCC identifier for this product as well as the FCC Notice above. The FCC identifier is FCC ID: WAP6045.
In any case the end product must be labeled exterior with “Contains FCC ID: WAP6045”.
## ANTENNA WARNING:
This device is tested with a standard SMA connector and with the antennas listed in Table 8 on page 21. When integrated in the OEMs product, these fixed antennas require installation preventing end-users from replacing them with non-approved antennas. Any antenna not in the following table must be tested to comply with FCC Section 15.203 for unique antenna connectors and Section 15.247 for emissions.
## RF EXPOSURE:
To comply with FCC RF Exposure requirements, the OEM must ensure to install the approved antenna in the previous.
The preceding statement must be included as a CAUTION statement in manuals, for products operating with the approved antennas in Table 8 on page 21, to alert users on FCC RF Exposure compliance. Any notification to the end user of installation or removal instructions about the integrated radio module is not allowed.
The radiated output power of CYBLE-416045-02 is far below the FCC radio frequency exposure limits. Nevertheless, use CYBLE-416045-02 in such a manner that minimizes the potential for human contact during normal operation.
End users may not be provided with the module installation instructions. OEM integrators and end users must be provided with transmitter operating conditions for satisfying RF exposure compliance.
Document Number: 002-24085 Rev. *A
Page 49 of 59
**CYBLE-416045-02**
## **ISED**
## **Innovation, Science and Economic Development (ISED) Canada Certification**
CYBLE-416045-02 is licensed to meet the regulatory requirements of Innovation, Science and Economic Development (ISED) Canada.
## License: IC: 7922A-6045
Manufacturers of mobile, fixed or portable devices incorporating this module are advised to clarify any regulatory questions and ensure compliance for SAR and/or RF exposure limits. Users can obtain Canadian information on RF exposure and compliance from www.ic.gc.ca.
This device has been designed to operate with the antennas listed in Table 8 on page 21, having a maximum gain of -0.5 dBi. Antennas not included in Table 8 on page 21 or having a gain greater than -0.5 dBi are strictly prohibited for use with this device. The required antenna impedance is 50 ohms. The antenna used for this transmitter must not be co-located or operating in conjunction with any other antenna or transmitter.
## ISED NOTICE:
The device CYBLE-416045-02 including the built-in trace antenna complies with Canada RSS-GEN Rules. The device meets the requirements for modular transmitter approval as detailed in RSS-GEN. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation.
L'appareil CYBLE-416045-02, y compris l'antenne intégrée, est conforme aux Règles RSS-GEN de Canada. L'appareil répond aux exigences d'approbation de l'émetteur modulaire tel que décrit dans RSS-GEN. L'opération est soumise aux deux conditions suivantes: (1) Cet appareil ne doit pas causer d'interférences nuisibles, et (2) Cet appareil doit accepter toute interférence reçue, y compris les interférences pouvant entraîner un fonctionnement indésirable.
## ISED INTERFERENCE STATEMENT FOR CANADA
This device complies with Innovation, Science and Economic Development (ISED) Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device.
Cet appareil est conforme à la norme sur l'innovation, la science et le développement économique (ISED) norme RSS exempte de licence. L'exploitation est autorisée aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
## ISED RADIATION EXPOSURE STATEMENT FOR CANADA
This equipment complies with ISED radiation exposure limits set forth for an uncontrolled environment.
Cet équipement est conforme aux limites d'exposition aux radiations ISED prévues pour un environnement incontrôlé.
## LABELING REQUIREMENTS:
The Original Equipment Manufacturer (OEM) must ensure that ISED labelling requirements are met. This includes a clearly visible label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor IC identifier for this product as well as the ISED Notices above. The IC identifier is 7922A-6045. In any case, the end product must be labeled in its exterior with “Contains IC: 7922A-6045”.
Le fabricant d'équipement d'origine (OEM) doit s'assurer que les exigences d'étiquetage ISED sont respectées. Cela comprend une étiquette clairement visible à l'extérieur de l'enceinte OEM spécifiant l'identifiant Cypress Semiconductor IC approprié pour ce produit ainsi que l'avis ISED ci-dessus. L'identificateur IC est 7922A-6045. En tout cas, le produit final doit être étiqueté dans son extérieur avec “Contient IC: 7922A-6045”.
Document Number: 002-24085 Rev. *A
Page 50 of 59
**CYBLE-416045-02**
## **European Declaration of Conformity**
Hereby, Cypress Semiconductor declares that the Bluetooth module CYBLE-416045-02 complies with the essential requirements and other relevant provisions of Directive 2014. As a result of the conformity assessment procedure described in Annex III of the Directive 2014, the end-customer equipment should be labeled as follows:
All versions of the CYBLE-416045-02 in the specified reference design can be used in the following countries: Austria, Belgium, Cyprus, Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, Poland, Portugal, Slovakia, Slovenia, Spain, Sweden, The Netherlands, the United Kingdom, Switzerland, and Norway.
## **MIC Japan**
CYBLE-416045-02 is certified as a module with type certification number 201-180370. End products that integrate CYBLE-416045-02 do not need additional MIC Japan certification for the end product.
End product can display the certification label of the embedded module.
Document Number: 002-24085 Rev. *A
Page 51 of 59
**CYBLE-416045-02**
## **Packaging**
**Table 40. Solder Reflow Peak Temperature**
|**Module Part Number**|**Package**|**Maximum Peak Temperature**|**Maximum Time at Peak**<br>**Temperature**|**No. of Cycles**|
|---|---|---|---|---|
|CYBLE-416045-02|43-pad SMT|260 °C|30 seconds|2|
**Table 41. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2**
|**Module Part Number**|**Package**|**MSL**|
|---|---|---|
|CYBLE-416045-02|43-pad SMT|MSL 3|
The CYBLE-416045-02 is offered in tape and reel packaging. Figure 11 details the tape dimensions used for the CYBLE-416045-02.
**Figure 11. CYBLE-416045-02 Tape Dimensions**
Figure 12 details the orientation of the CYBLE-416045-02 in the tape as well as the direction for unreeling.
**Figure 12. Component Orientation in Tape and Unreeling Direction**
Document Number: 002-24085 Rev. *A
Page 52 of 59
**CYBLE-416045-02**
Figure 13 details reel dimensions used for the CYBLE-416045-02.
**Figure 13. Reel Dimensions**
The CYBLE-416045-02 is designed to be used with pick-and-place equipment in an SMT manufacturing environment. The center-of-mass for the CYBLE-416045-02 is detailed in Figure 14.
**Figure 14. CYBLE-416045-02 Center of Mass**
Document Number: 002-24085 Rev. *A
Page 53 of 59
**CYBLE-416045-02**
## **Ordering Information**
Table 42 lists the CYBLE-416045-02 part number and features. Table 43 lists the reel shipment quantities for the CYBLE-416045-02.
## **Table 42. Ordering Information**
**==> picture [501 x 106] intentionally omitted <==**
**----- Start of picture text -----**<br>
Features<br>MPN<br>CYBLE-416045-02 150/50 100/25 1024 288 12 ✓ ✓ 1 Msps 2 5 ✓ 36 43-SMT<br>UDB GPIO Package<br>I2S/PDM<br>Flash (KB) SRAM (KB) CapSense SCB Blocks<br>CPU Speed (M4) CPU Speed (M0+) Direct LCD Drive 12-bit SAR ADC LP Comparators<br>**----- End of picture text -----**<br>
**Table 43. Tape and Reel Package Quantity and Minimum Order Amount**
|**Description**|**Minimum Reel Quantity**|**Maximum Reel Quantity**|**Comments**|
|---|---|---|---|
|Reel Quantity|500|500|Ships in 500 unit reel quantities.|
|Minimum Order Quantity (MOQ)|500|–||
|Order Increment (OI)|500|–||
The CYBLE-416045-02 is offered in tape and reel packaging. The CYBLE-416045-02 ships with a maximum of 500 Unit/reel.
## **Part Numbering Convention**
The part numbers are of the form CYBLE-ABCDEF-GH where the fields are defined as follows.
For additional information and a complete list of Cypress Semiconductor BLE products, contact your local Cypress sales representative. To locate the nearest Cypress office, visit our website.
|U.S. Cypress Headquarters Address|198 Champion Court, San Jose, CA 95134|
|---|---|
|U.S. Cypress Headquarter Contact Information|(408) 943-2600|
|Cypress Website Address|www.cypress.com|
Document Number: 002-24085 Rev. *A
Page 54 of 59
**CYBLE-416045-02**
## **Acronyms**
**Table 44. Acronyms Used in this Document**
**Table 44. Acronyms Used in this Document** (continued)
|**Table 44. Acronyms Used in this Document**|**Table 44. Acronyms Used in this Document**|**Table 44. Acronyms Used in this Document**|**Table 44. Acronyms Used in this Document**(continued)|
|---|---|---|---|
|**Acronym**<br>**Description**<br>3DES<br>Triple Data Encryption Standard<br>abus<br>analog local bus<br>ADC<br>analog-to-digital converter<br>AES<br>Advanced Encryption Standard<br>AG<br>analog global<br>AHB<br>AMBA (advanced microcontroller bus<br>architecture) high-performance bus, an Arm data<br>transfer bus<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~<br>~~ee~~||EOC<br>EOF<br>EPSR<br>ESD<br>ETM<br>FIR<br>FPB<br>FS<br>**Acronym**<br>~~a~~|end of conversion<br>end of frame<br>execution program status register<br>electrostatic discharge<br>embedded trace macrocell<br>finite impulse response, see also IIR<br>flash patch and breakpoint<br>full-speed<br>**Description**|
|ALU<br>arithmetic logic unit<br>AMUXBUS<br>analog multiplexer bus<br>API<br>application programming interface<br>~~asp ~~<br>~~a~~||GPIO<br>HVI<br> ~~Oe~~|general-purpose input/output, applies to a PSoC<br>pin<br>high-voltage interrupt, see also LVI, LVD|
|APSR<br>application program status register<br>~~a~~||IC|integrated circuit|
|Arm<br>advanced RISC machine, a CPU architecture<br>~~a~~||IDAC|current DAC, see also DAC, VDAC|
|ATM<br>automatic thump mode<br>BW<br>bandwidth<br>CAN<br>Controller Area Network, a communications<br>protocol<br>CMRR<br>common-mode rejection ratio<br>CPU<br>central processing unit<br>IDE<br>integrated development environment<br>I2C, or IIC<br>Inter-Integrated Circuit, a communications<br>protocol<br>IIR<br>infinite impulse response, see also FIR<br>ILO<br>internal low-speed oscillator, see also IMO<br>IMO<br>internal main oscillator, see also ILO<br>~~a~~<br>~~eees ee~~<br>~~|~~<br>~~pOoT~~||||
|CTBm<br>Continuous Time Block mini<br>CRC<br>cyclic redundancy check, an error-checking<br>protocol<br>DAC<br>digital-to-analog converter, see also IDAC, VDAC<br>~~aee ~~<br>~~a~~||INL<br>I/O<br>IPOR<br>IPSR<br> ~~ES~~|integral nonlinearity, see also DNL<br>input/output, see also GPIO, DIO, SIO, USBIO<br>initial power-on reset<br>interrupt program status register<br>~~OO~~|
|DFB<br>digital filter block<br>DIO<br>digital input/output, GPIO with only digital<br>capabilities, no analog. See GPIO.<br>DMIPS<br>Dhrystone million instructions per second<br>DMA<br>direct memory access, see also TD<br>DNL<br>differential nonlinearity, see also INL<br>~~a~~<br>~~—— a~~<br>~~a~~<br>~~a~~<br>~~a a~~|~~a~~|IRQ<br>ITM<br>LCD<br>LIN<br>LR<br>~~a~~|interrupt request<br>instrumentation trace macrocell<br>liquid crystal display<br>Local Interconnect Network, a communications<br>protocol.<br>link register|
|DNU<br>do not use<br>DR<br>port write data registers<br>~~a~~<br>~~a a~~||LUT<br>LVD|lookup table<br>low-voltage detect, see also LVI|
|DSI<br>digital system interconnect<br>DWT<br>data watchpoint and trace<br>ECC<br>error correcting code or Elliptic Curve<br>Cryptography<br>ECO<br>external crystal oscillator<br>EEPROM<br>electrically erasable programmable read-only<br>memory<br>LVI<br>low-voltage interrupt, see also HVI<br>LVTTL<br>low-voltage transistor-transistor logic<br>MAC<br>multiply-accumulate<br>MCU<br>microcontroller unit<br>MISO<br>master-in slave-out<br>NC<br>no connect<br>~~aa~~<br>~~OO~~<br>~~FE~~<br>~~a~~<br>~~aee eeOO~~||||
|EMI<br>electromagnetic interference<br>~~a~~||NMI|nonmaskable interrupt|
|EMIF<br>external memory interface||NRZ|non-return-to-zero|
|||NVIC<br>~~a~~|nested vectored interrupt controller|
Document Number: 002-24085 Rev. *A
Page 55 of 59
**CYBLE-416045-02**
**Table 44. Acronyms Used in this Document** (continued)
**Table 44. Acronyms Used in this Document** (continued)
|NVL<br>nonvolatile latch, see also WOL<br>opamp<br>operational amplifier<br>PAL<br>programmable array logic, see also PLD<br>PC<br>program counter<br>PCB<br>printed circuit board<br>PDM<br>Pulse-Density Modulation<br>P/E<br>Program/Erase<br>PGA<br>programmable gain amplifier<br>PHUB<br>peripheral hub<br>PHY<br>physical layer<br>PICU<br>port interrupt control unit<br>PLA<br>programmable logic array<br>PLD<br>programmable logic device, see also PAL<br>PLL<br>phase-locked loop<br>PMDD<br>package material declaration data sheet<br>POR<br>power-on reset<br>PRES<br>precise power-on reset<br>PRS<br>pseudo random sequence<br>PS<br>port read data register<br>PSoC<br>Programmable System-on-Chip<br>PSRR<br>power supply rejection ratio<br>PWM<br>pulse-width modulator<br>RAM<br>random-access memory<br>RMS<br>root-mean-square<br>RISC<br>reduced-instruction-set computing<br>RSA<br>Rivest–Shamir–Adleman<br>RTC<br>real-time clock<br>RTL<br>register transfer language<br>**Acronym**<br>**Description**<br>SOF<br>start of frame<br>S/PDIF<br>Sony/Philips Digital Interface<br>SPI<br>Serial Peripheral Interface, a communications<br>protocol<br>SR<br>slew rate<br>SRAM<br>static random access memory<br>SRES<br>software reset<br>SRSS<br>System Resources Subsystem<br>SWD<br>serial wire debug, a test protocol<br>SWV<br>single-wire viewer<br>TD<br>transaction descriptor, see also DMA<br>THD<br>total harmonic distortion<br>TIA<br>transimpedance amplifier<br>TRM<br>technical reference manual<br>TRNG<br>True Random Number Generator<br>TTL<br>transistor-transistor logic<br>TX<br>transmit<br>UART<br>Universal Asynchronous Transmitter Receiver, a<br>communications protocol<br>UDB<br>universal digital block<br>ULP<br>Ultra-low power<br>USB<br>Universal Serial Bus<br>USBIO<br>USB input/output, PSoC pins used to connect to<br>a USB port<br>VDAC<br>voltage DAC, see also DAC, IDAC<br>WDT<br>watchdog timer<br>WOL<br>write once latch, see also NVL<br>WRES<br>watchdog timer reset<br>XRES<br>external reset I/O pin<br>**Acronym**<br>**Description**<br>~~a ree es~~<br>~~eeDrs~~<br>~~eees~~fr<br>~~rs~~<br>~~ee||~~<br>~~ng a (~~<br>~~neOd~~<br>~~ng a (~~<br>~~neOd~~<br>~~ng a (~~<br>~~neOd~~<br>~~ng a (~~<br>~~neOd~~<br>~~ng a (~~<br>~~neOd~~<br>~~ng a (~~<br>~~neOd~~<br>~~| Oe~~<br>~~aee~~<br>~~0~~<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~Sa a~~<br>~~eefrre~~<br>~~i frre~~<br>~~eefrre~~<br>~~ee~~<br>~~ee~~<br>~~eefrre~~|
|---|
|RTR<br>remote transmission request<br>XTAL<br>crystal|
|RX<br>receive<br>SAR<br>successive approximation register<br>SC/CT<br>switched capacitor/continuous time<br>SCL<br>I2C serial clock<br>SDA<br>I2C serial data<br>S/H<br>sample and hold<br>SIG<br>Special Interest Group<br>SINAD<br>signal to noise and distortion ratio<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|SIO<br>special input/output, GPIO with advanced<br>features. See GPIO.|
|SOC<br>start of conversion<br>~~ee~~|
Document Number: 002-24085 Rev. *A
Page 56 of 59
**CYBLE-416045-02**
## **Document Conventions**
## **Unit of Measure**
## **Table 45. Unit of Measure**
|**Symbol**<br>~~ee~~|**Unit of Measure**|
|---|---|
|°C<br>~~ee~~<br>~~a~~|degrees Celsius|
|dB<br>~~a~~<br>~~a~~|decibel|
|dBm<br>~~a~~|decibel-milliwatts|
|fF<br>~~a~~<br>~~a~~|femtofarads|
|Hz<br>~~a~~|hertz|
|KB<br>~~a~~<br>~~a~~|1024 bytes|
|kbps<br>~~a~~|kilobits per second|
|Khr<br>~~a~~<br>~~a~~|kilohour|
|kHz<br>~~a~~|kilohertz|
|k<br>~~a~~<br>~~a~~|kilo ohm|
|ksps<br>~~a~~|kilosamples per second|
|LSB<br>~~a~~<br>~~a~~|least significant bit|
|Mbps<br>~~a~~|megabits per second|
|MHz<br>~~a~~<br>~~a~~|megahertz|
|M<br>~~a~~|mega-ohm|
|Msps<br>~~a~~<br>~~a~~|megasamples per second|
|µA<br>~~a~~|microampere|
|µF<br>~~a~~<br>~~a~~|microfarad|
|µH<br>~~a~~|microhenry|
|µs<br>~~a~~<br>~~a~~|microsecond|
|µV<br>~~a~~|microvolt|
|µW<br>~~a~~<br>~~a~~|microwatt|
|mA<br>~~a~~|milliampere|
|ms<br>~~a~~<br>~~a~~|millisecond|
|mV<br>~~a~~|millivolt|
|nA<br>~~a~~<br>~~a~~|nanoampere|
|ns<br>~~a~~|nanosecond|
|nV<br>~~a~~<br>~~a~~|nanovolt|
|<br>~~a~~|ohm|
|pF<br>~~a~~<br>~~a~~|picofarad|
|ppm<br>~~a~~|parts per million|
|ps<br>~~a~~<br>~~a~~|picosecond|
|s<br>~~a~~|second|
|sps<br>~~a~~<br>~~a~~<br>~~ee~~|samples per second|
|sqrtHz<br>~~ee~~|square root of hertz|
|V<br>~~ee~~<br>~~a~~|volt|
Document Number: 002-24085 Rev. *A
Page 57 of 59
**CYBLE-416045-02**
## **Document History Page**
## **Document Title: CYBLE-416045-02 EZ-BLE™ Creator Module Document Number: 002-24085**
|**Document Title: CYBLE-416045-02 EZ-BLE™ Creator Module**<br>**Document Number: 002-24085**|**Document Title: CYBLE-416045-02 EZ-BLE™ Creator Module**<br>**Document Number: 002-24085**|**Document Title: CYBLE-416045-02 EZ-BLE™ Creator Module**<br>**Document Number: 002-24085**|**Document Title: CYBLE-416045-02 EZ-BLE™ Creator Module**<br>**Document Number: 002-24085**|**Document Title: CYBLE-416045-02 EZ-BLE™ Creator Module**<br>**Document Number: 002-24085**|
|---|---|---|---|---|
|**Revision**|**ECN**|**Orig. of**<br>**Change**|**Submission**<br>**Date**|**Description of Change**|
|**|6179687|DSO|06/05/2018|Preliminary Datasheet for CYBLE-416045-02 Module.|
|*A|6486349|SHNG|02/21/2019|Updated theLow-Power ComparatorsandSerial Communication Blocks (SCB)<br>sections.<br>Added the32-kHz Crystal Oscillatorsection.<br>AddedTable 11and UpdatedTable 37.<br>Updated certification.<br>Updated Tape, unreeling direction, and Center of Mass drawings.|
Document Number: 002-24085 Rev. *A
Page 58 of 59
**CYBLE-416045-02**
## **Sales, Solutions, and Legal Information**
## **Worldwide Sales and Design Support**
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.
## **Products**
Arm[®] Cortex[®] Microcontrollers cypress.com/arm Automotive cypress.com/automotive Clocks & Buffers cypress.com/clocks Interface cypress.com/interface Internet of Things cypress.com/iot Memory cypress.com/memory Microcontrollers cypress.com/mcu PSoC cypress.com/psoc Power Management ICs cypress.com/pmic Touch Sensing cypress.com/touch USB Controllers cypress.com/usb Wireless Connectivity cypress.com/wireless
## **PSoC[®] Solutions**
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
## **Cypress Developer Community**
Forums | WICED IOT Forums | Projects | Video | Blogs | Training | Components
## **Technical Support**
cypress.com/support
Notice regarding compliance with Universal Serial Bus specification. Cypress offers firmware and hardware solutions that are certified to comply with the Universal Serial Bus specification, USB Type-C™ Cable and Connector Specification, and other specifications of USB Implementers Forum, Inc (USB-IF). You may use Cypress or third party software tools, including sample code, to modify the firmware for Cypress USB products. Modification of such firmware could cause the firmware/hardware combination to no longer comply with the relevant USB-IF specification. You are solely responsible ensuring the compliance of any modifications you make, and you must follow the compliance requirements of USB-IF before using any USB-IF trademarks or logos in connection with any modifications you make. In addition, if Cypress modifies firmware based on your specifications, then you are responsible for ensuring compliance with any desired standard or specifications as if you had made the modification. CYPRESS IS NOT RESPONSIBLE IN THE EVENT THAT YOU MODIFY OR HAVE MODIFIED A CERTIFIED CYPRESS PRODUCT AND SUCH MODIFIED PRODUCT NO LONGER COMPLIES WITH THE RELEVANT USB-IF SPECIFICATIONS.
© Cypress Semiconductor Corporation, 2018-2019. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress does not assume any liability arising out of any security breach, such as unauthorized access to or use of a Cypress product. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-24085 Rev. *A
Page 59 of 59
Revised February 21, 2019
Updated at April 28, 2026
Infineon Technologies is a globally recognized leader in semiconductor solutions, renowned for driving innovation in power management, energy efficiency, and modern mobility. With a strong legacy of engineering excellence, the company provides highly reliable components designed to meet the rigorous demands of industrial, automotive, and advanced commercial applications. The core of our Infineon portfolio is centered on their industry-leading discrete semiconductors. We offer an extensive selection of single and dual MOSFETs, alongside a robust range of single IGBTs and advanced IGBT modules. These flagship power transistors are essential for high-efficiency power conversion and motor control, providing engineers with superior thermal performance and minimized switching losses. Beyond advanced field-effect transistors, the selection includes a comprehensive array of diodes and rectifiers, heavily featuring Schottky diodes, as well as fast-recovery and RF/PIN diodes. This power foundation is further supported by bipolar transistors, intelligent power modules, and thyristor SCR modules, delivering the critical building blocks required for complex power system designs. To support broader system integration, the portfolio also encompasses specialized solutions such as solid-state relays, AC/DC LED driver ICs, and Bluetooth communications modules. From high-power industrial rectifiers to wireless connectivity adapters, Infineon equips designers with the precision components needed to build efficient, scalable, and fully connected electronic systems.
About Novapart
Novapart is a B2B electronic component broker specialising in stock shortages and cost reduction. We source hard-to-find parts and identify compliant alternatives across a catalogue of 410,000+ components from 500+ manufacturers.
Learn more →Stock Shortage Specialist
When a component is unavailable, discontinued or has an unacceptable lead time, we tap into our network of vetted European and Asian distributors to source what you need — without compromising on quality or traceability.
Request a quote →Compliant Alternatives
We identify pin-to-pin, electrically equivalent substitutes that meet the same certifications (RoHS, AEC-Q100, REACH) as your original specification — validated against datasheets, not just part numbers. Often at a lower cost.
BOM Analysis service →