CYBLE-202007-01

**CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11** 

## EZ-BLE™ PRoC™  XR Module 

## **General Description** 

The CYBLE-2X20XX-X1 is a Bluetooth[] Low Energy (BLE) wireless module solution. The CYBLE-2X20XX-X1 is a turnkey solution and includes onboard crystal oscillators, passive components, and the Cypress PRoC™ BLE. Refer to the CYBL1XX7X datasheet for additional details on the capabilities of the PRoC BLE device used on this module. 

The CYBLE-2X20XX-X1 supports a number of peripheral functions (ADC, timers, counters, PWM) and serial communication protocols (I[2] C, UART, SPI) through its programmable architecture. The CYBLE-2X20XX-X1 includes a royalty-free BLE stack compatible with Bluetooth 4.2 and provides up to 19 GPIOs in a 15.0 × 23.0 × 2.0 mm package. 

The CYBLE-2X20XX-X1 is offered in two certified versions (CYBLE-212006-01 and CYBLE-202007-01), as well as an uncertified version (CYBLE-202013-11). The CYBLE-212006-01 includes an integrated trace antenna. The CYBLE-202007-01 supports an external antenna via a u-FL connector. The CYBLE-202013-11 supports an external antenna through a RF solder pad output. The CYBLE-202013-11 does not include a RF shield and is not regulatory certified. 

## **Module Description** 

■ Module size: 15.00 mm × 23.00 mm × 2.00 mm 

- Extended Range: 

- ❐ Up to 400 meters bidirectional communication[[1,2]] 

- ❐ Up to 450 meters in beacon only mode[[1]] 

- Bluetooth 4.2 qualified single-mode module 

- ❐ QDID: 88957 

- ❐ Declaration ID: D032786 

- Footprint compatible options for integrated antenna or antenna-less design options 

- Certified to FCC, IC, MIC, KC, and CE regulations (CYBLE-212006-01 and CYBLE-202007-01 only) 

- Castelated solder pad connections for ease-of-use 

- 256-KB flash memory, 32-KB SRAM memory 

- Up to 19 GPIOs 

- Industrial temperature range: –40 °C to +85 °C 

- 32-bit processor (0.9 DMIPS/MHz) operating up to 48 MHz 

- Watchdog timer with dedicated internal low-speed oscillator 

## **Power Consumption** 

- Maximum TX output power: +7.5 dbm 

- RX Receive Sensitivity: –93 dbm 

- Received signal strength indicator (RSSI) with 1-dB resolution 

- TX current consumption 

- ❐ BLE silicon: 15.6 mA (radio only, 0 dbm) 

- ❐ RFX2401C: 27 mA (PA/LNA only, +7.5 dBm) 

- RX current consumption 

- ❐ BLE silicon: 16.4 mA (radio only, 0 dbm) 

- ❐ RFX2401C: 8.0 mA (PA/LNA only) 

- Cypress CYBL1XX7X silicon low power mode support 

- ❐ Deep Sleep: 1.3 A with watch crystal oscillator (WCO) on ❐ Hibernate: 150 nA with SRAM retention 

- ❐ Stop: 60 nA with XRES wakeup 

## **Functional Capabilities** 

- Up to 18 capacitive sensors for buttons or sliders 

- 12-bit, 1-Msps SAR ADC with internal reference, sample-and-hold (S/H), and channel sequencer 

- Two serial communication blocks (SCBs) supporting I[2] C (master/slave), SPI (master/slave), or UART 

- Four dedicated 16-bit timer, counter, or PWM blocks (TCPWMs) 

- LCD drive supported on all GPIOs (common or segment) 

- Programmable low voltage detect (LVD) from 1.8 V to 4.5 V 

- I[2] S master interface 

- BLE protocol stack supporting generic access profile (GAP) Central, Peripheral, Observer, or Broadcaster roles 

- Switches between Central and Peripheral roles on-the-go 

- Standard BLE profiles and services for interoperability 

- Custom profile and service for specific use cases 

## **Benefits** 

CYBLE-2X20XX-X1 is provided as a turnkey solution, including all necessary hardware required to use BLE communication standards. 

- Proven hardware design ready to use 

- Cost optimized for applications without space constraint 

- Reprogrammable architecture 

- Fully certified module eliminates the time needed for design, development and certification 

- Bluetooth SIG qualified with QDID and Declaration ID 

- Flexible communication protocol support 

- PSoC Creator™ provides an easy-to-use integrated design environment (IDE) to configure, develop, program, and test a BLE application 

## **Notes** 

1. Connection range tested module-to-module in full line-of-sight environment, free of obstacles or interferance sources with output power of +7.5 dBm. 

2. Specified as EZ-BLE XR module to module range. Mobile phone connection range will decrease based on the PA/LNA performance of the mobile phone used. 

**Cypress Semiconductor Corporation** • 198 Champion Court Document Number: 002-15631 Rev.*D 

San Jose, CA 95134-1709 • 408-943-2600 Revised April 21, 2017 

• 

**CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11** 

## **More Information** 

Cypress provides a wealth of data at www.cypress.com to help you to select the right module for your design, and to help you to quickly and effectively integrate the module into your design. 

- Overview: EZ-BLE Module Portfolio, Module Roadmap 

- EZ-BLE PRoC Product Overview 

- PRoC BLE Silicon Datasheet 

- Application notes: Cypress offers a number of BLE application notes covering a broad range of topics, from basic to advanced level. Recommended application notes for getting started with EZ-BLE modules are: 

- ❐ AN96841 - Getting Started with EZ-BLE Module 

- ❐ AN94020 - Getting Started with PRoC BLE 

- ❐ AN97060 - PSoC[®] 4 BLE and PRoC™ BLE - Over-The-Air (OTA) Device Firmware Upgrade (DFU) Guide 

- ❐ AN91162 - Creating a BLE Custom Profile 

- ❐ AN91184 - PSoC 4 BLE - Designing BLE Applications 

- ❐ AN92584 - Designing for Low Power and Estimating Battery Life for BLE Applications 

- ❐ AN85951 - PSoC[®] 4 CapSense[®] Design Guide 

- ❐ AN95089 - PSoC[®] 4/PRoC™ BLE Crystal Oscillator Selection and Tuning Techniques 

- ❐ AN91445 - Antenna Design and RF Layout Guidelines 

- Technical Reference Manual (TRM): 

- ❐ PRoC[®] BLE Technical Reference Manual 

## ■ Knowledge Base Articles 

- ❐ KBA212334 - Pin Mapping Differences Between the EZ-BLE PRoC® Evaluation Boards (CYBLE-212006-EVAL/CYBLE-202007-EVAL/CYBLE-202013-EVAL) and the BLE Pioneer Kit (CY8CKIT-042-BLE) 

- ❐ KBA97095 - EZ-BLE™ Module Placement 

- ❐ KBA216380 - RF Regulatory Certifications for CYBLE-212006-01 and CYBLE-202007-01 EZ-BLE™ PRoC® XR Modules 

- ❐ KBA213976 - FAQ for BLE and Regulatory Certifications with EZ-BLE modules 

- ❐ KBA210802 - Queries on BLE Qualification and Declaration Processes 

## ■ Development Kits: 

- ❐ CYBLE-212006-EVAL, CYBLE-212006-01 Eval Board ❐ CYBLE-202007-EVAL, CYBLE-202007-01 Eval Board 

- ❐ CYBLE-202013-EVAL, CYBLE-202013-11 Eval Board 

- ❐ CY8CKIT-042-BLE, Bluetooth[®] Low Energy Pioneer Kit 

- ❐ CY8CKIT-002, PSoC[®] MiniProg3 Program and Debug Kit 

- Test and Debug Tools: 

- ❐ CYSmart, Bluetooth[®] LE Test and Debug Tool (Windows) 

- ❐ CYSmart Mobile, Bluetooth[®] LE Test and Debug Tool (Android/iOS Mobile App) 

## **Two Easy-To-Use Design Environments to Get You Started Quickly** 

## **PSoC[®] Creator™ Integrated Design Environment (IDE)** 

PSoC Creator is an Integrated Design Environment (IDE) that enables concurrent hardware and firmware editing, compiling and debugging of PSoC 3, PSoC 4, PSoC 5LP, PSoC 4 BLE, PRoC BLE and EZ-BLE module systems with no code size limitations. PSoC peripherals are designed using schematic capture and simple graphical user interface (GUI) with over 120 pre-verified, production-ready PSoC Components™. 

PSoC Components are analog and digital “virtual chips,” represented by an icon that users can drag-and-drop into a design and configure to suit a broad array of application requirements. 

## _Bluetooth Low Energy Component_ 

The Bluetooth Low Energy Component inside PSoC Creator provides a comprehensive GUI-based configuration window that lets you quickly design BLE applications. The Component incorporates a Bluetooth Core Specification v4.2 compliant BLE protocol stack and provides API functions to enable user applications to interface with the underlying Bluetooth Low Energy Sub-System (BLESS) hardware via the stack. 

## **EZ-Serial™ BLE Firmware Platform** 

The EZ-Serial Firmware Platform provides a simple way to access the most common hardware and communication features needed in BLE applications. EZ-Serial implements an intuitive API protocol over the UART interface and exposes various status and control signals through the module’s GPIOs, making it easy to add BLE functionality quickly to existing designs. 

Use a simple serial terminal and evaluation kit to begin development without requiring an IDE. Refer to the EZ-Serial webpage for User Manuals and instructions for getting started as well as detailed reference materials. 

EZ-BLE modules are pre-flashed with the EZ-Serial Firmware Platform. If you do not have EZ-Serial pre-loaded on your module, you can download each EZ-BLE module’s firmware images on the EZ-Serial webpage. 

## **Technical Support** 

■ Frequently Asked Questions (FAQs): Learn more about our BLE ECO System. 

- Forum: See if your question is already answered by fellow developers on the PSoC 4 BLE and PRoC BLE forums. 

- Visit our support page and create a technical support case or contact a local sales representatives. If you are in the United States, you can talk to our technical support team by calling our toll-free number: +1-800-541-4736. Select option 2 at the prompt. 

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## **Contents** 

**Overview............................................................................ 4** Module Description...................................................... 4 **Pad Connection Interface ................................................ 6 Recommended Host PCB Layout ................................... 7 Digital and Analog Capabilities and Connections......... 9 Power Supply Connections and Recommended External Components.................................................................... 10** Connection Options................................................... 10 External Component Recommendation .................... 10 Antenna Matching Network Requirements for CYBLE-202013-11 ................................................................ 12 Critical Components List ........................................... 14 Antenna Design......................................................... 14 Qualified Antenna for CYBLE-202007-01 and CYBLE-202013-11 ................................................................ 14 Power Amplifier (PA) and Low Noise Amplifier (LNA) 14 Enabling Extended Range Feature ........................... 15 Low Power Operation................................................ 15 **Electrical Specification .................................................. 16** GPIO ......................................................................... 18 XRES......................................................................... 19 Digital Peripherals ..................................................... 22 Serial Communication ............................................... 24 Memory ..................................................................... 25 System Resources .................................................... 25 

**Environmental Specifications ....................................... 31** Environmental Compliance ....................................... 31 RF Certification.......................................................... 31 Safety Certification .................................................... 31 Environmental Conditions ......................................... 31 ESD and EMI Protection ........................................... 31 **Regulatory Information.................................................. 32** FCC........................................................................... 32 Industry Canada (IC) Certification............................. 33 European R&TTE Declaration of Conformity ............ 33 MIC Japan................................................................. 34 KC Korea................................................................... 34 **Packaging........................................................................ 35 Ordering Information...................................................... 37** Part Numbering Convention...................................... 37 **Acronyms........................................................................ 38 Document Conventions ................................................. 38** Units of Measure ....................................................... 38 **Document History Page................................................. 39 Sales, Solutions, and Legal Information ...................... 40** Worldwide Sales and Design Support....................... 40 Products .................................................................... 40 PSoC® Solutions ...................................................... 40 Cypress Developer Community................................. 40 Technical Support ..................................................... 40 

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**CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11** 

## **Overview** 

## **Module Description** 

The CYBLE-2X20XX-X1 module is a complete module designed to be soldered to the applications main board. 

## _Module Dimensions and Drawing_ 

Cypress reserves the right to select components (including the appropriate BLE device) from various vendors to achieve the BLE module functionality. Such selections will still guarantee that all height restrictions of the component area are maintained. Designs should be held within the physical dimensions shown in the mechanical drawings in Figure 1. All dimensions are in millimeters (mm). 

## **Table 1.  Module Design Dimensions** 

|**Dimension Item**|**Dimension Item**|**Specification**|
|---|---|---|
|Module dimensions|Length (X)|15.00 ± 0.15 mm|
||Width (Y)|23.00 ± 0.15 mm|
|Antenna location dimensions|Length (X)|15.00 ± 0.15 mm|
||Width (Y)|4.65 ± 0.15 mm|
|PCB thickness|Height (H)|0.80 ± 0.10 mm|
|Shield height|Height (H)|1.20 ± 0.10 mm|
|Maximum component height|Height (H)|1.20 mm typical (shield) - CYBLE-212006-01<br>1.25 mm typical (connector) - CYBLE-202007-01<br>0.75mm typical (crystal) - CYBLE-202013-11|
|Total module thickness (bottom of module to highest component)|Height (H)|2.00 mm typical - CYBLE-212006-01<br>2.05 mm typical - CYBLE-202007-01<br>1.55 mm typical - CYBLE-202013-11|



See Figure 1 on page 5 for the mechanical reference drawing for CYBLE-2X20XX-X1. 

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**Figure 1.  Module Mechanical Drawing** 

## **Top View** 

## **Side View** 

## **Bottom View** 

## **Note** 

3. No metal or traces should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area. For more information on recommended host PCB layout, see Figure 3, Figure 4, Figure 5, and Figure 6 and Table 3. 

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**CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11** 

## **Pad Connection Interface** 

As shown in the bottom view of Figure 1 on page 5, the CYBLE-2X20XX-X1 connects to the host board via solder pads on the backside of the module. Table 2 and Figure 2 detail the solder pad length, width, and pitch dimensions of the CYBLE-2X20XX-X1 module. 

**Table 2. Solder Pad Connection Description** 

|**Name**|**Connections**|**Connection Type**|**Pad Length Dimension**|**Pad Width Dimension**|**Pad Pitch**|
|---|---|---|---|---|---|
|SP|30|Solder Pads|1.02 mm|0.71 mm|1.27 mm|



**Figure 2.  Solder Pad Dimensions (Seen from Bottom)** 

To maximize RF performance, the host layout should follow these recommendations: 

1. The ideal placement of the Cypress BLE module is in a corner of the host board with the trace antenna located at the far corner. This placement minimizes the additional recommended keep out area stated in item 2. Refer to AN96841 for module placement best practices. 

2. To maximize RF performance, the area immediately around the Cypress BLE module trace antenna should contain an additional keep out area, where no grounding or signal trace are contained. The keep out area applies to all layers of the host board. The recommended dimensions of the host PCB keep out area are shown in Figure 3 (dimensions are in mm). 

**Figure 3.  Recommended Host PCB Keep Out Area Around the CYBLE-2X20XX-X1 Antenna** 

**Host PCB Keep Out Area Around Trace Antenna** 

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**CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11** 

## **Recommended Host PCB Layout** 

Figure 4, Figure 5, Figure 6, and Table 3 provide details that can be used for the recommended host PCB layout pattern for the CYBLE-212006-01. Dimensions are in millimeters unless otherwise noted. Pad length of 1.27 mm (0.635 mm from center of the pad on either side) shown in Figure 6 is the minimum recommended host pad length. The host PCB layout pattern can be completed using either Figure 4, Figure 5, or Figure 6. It is not necessary to use all figures to complete the host PCB layout pattern. 

**Figure 4.  Host Layout Pattern for CYBLE-2X20XX-X1** 

**Figure 5.  Module Pad Location from Origin** 

**Top View (Seen on Host PCB)** 

**Top View (Seen on Host PCB)** 

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**CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11** 

Table 3 provides the center location for each solder pad on the CYBLE-2X20XX-X1. All dimensions are referenced to the center of the solder pad. Refer to Figure 6 for the location of each module solder pad. 

**Table 3.  Module Solder Pad Location** 

|**Solder Pad**<br>**(Center of Pad)**|**Location (X,Y) from**<br>**Orign (mm)**|**Dimension from**<br>**Orign (mils)**|
|---|---|---|
|1|(0.38, 10.54)|(14.96, 414.96)|
|2<br>~~es~~|(0.38, 11.81)|(14.96, 464.96)|
|3<br>~~es~~<br>~~es~~|(0.38, 13.08)<br>~~ee~~|(14.96, 514.96)|
|4<br>~~es~~<br>~~es~~|(0.38, 14.35)<br>~~ee~~|(14.96, 564.96)|
|5<br>~~es~~<br>~~es~~|(0.38, 15.62)<br>~~ee~~|(14.96, 614.96)|
|6<br>~~es~~|(0.38, 16.89)|(14.96, 664.96)|
|7<br>~~es~~|(0.38, 18.16)|(14.96, 714.96)|
|8|(0.38, 19.43)|(14.96, 764.96)|
|9|(0.38, 20.70)|(14.96, 814.96)|
|10|(0.38, 21.97)|(14.96, 864.96)|
|11<br>~~es~~|(2.32, 22.62)|(91.34, 890.55)|
|12<br>~~es~~<br>~~es~~<br>~~es~~|(3.59, 22.62)<br>~~ee~~|(141.34, 890.55)|
|13<br>~~es~~<br>~~es~~<br>~~es~~|(4.86, 22.62)<br>~~ee~~|(191.34, 890.55)|
|14<br>~~es~~<br>~~es~~|(6.13, 22.62)<br>~~ee~~|(241.34, 890.55)|
|15<br>~~es~~|(7.40, 22.62)<br>~~ee~~|(291.34, 890.55)|
|16|(8.67, 22.62)|(341.34, 890.55)|
|17<br>~~es~~|(9.94, 22.62)<br>~~ee~~|(391.34,8 90.55)|
|18<br>~~es~~|(11.21, 22.62)<br>~~ee~~|(441.34, 890.55)|
|19<br>~~es~~|(12.48, 22.62)<br>~~ee~~|(491.34, 890.55)|
|20|(13.75, 22.62)|(541.34, 890.55|
|21|(14.62, 20.70)|(575.59, 814.96)|
|22|(14.62, 19.43)|(575.59, 764.96)|
|23|(14.62, 18.16)|(575.59, 714.96)|
|24|(14.62, 16.89)|(575.59, 664.96)|
|25|(14.62, 15.62)|(575.59, 614.96)|
|26|(14.62, 14.35)|(575.59, 564.96)|
|27|(14.62, 13.08)|(575.59, 514.96)|
|28|(14.62, 11.81)|(575.59, 464.96)|
|29|SeeFigure 2|SeeFigure 2|
|30|SeeFigure 2|SeeFigure 2|



**Figure 6.  Solder Pad Reference Location** 

## **Top View (Seen on Host PCB)** 

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## **Digital and Analog Capabilities and Connections** 

Table 4 details the solder pad connection definitions and available functions for each connection pad. Table 4 lists the solder pads on CYBLE-2X20XX-X1, the BLE device port-pin, and denotes whether the function shown is available for each solder pad. Each connection is configurable for a single option shown with a ✓ . 

## **Table 4. Solder Pad Connection Definitions** 

|**Solder Pad**<br>**Number**<br>~~a~~|**Device**<br>**Port Pin**<br>~~ee~~|**UART**|**SPI**|**I2C**|**TCPWM**[4,5]|**Cap-**<br>**Sense**|**WCO**<br>**Out**|**WCO**<br>**ECO**<br>**Out**|**LCD**|**SWD**|**GPIO**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|1<br>~~a~~|GND<br>~~ee~~|Ground Connection||||||||||
|2<br>~~a~~<br>~~ai~~|XRES<br><br>~~ee~~<br>~~ai~~|External Reset Hardware Connection Input<br>✓✓<br>✓✓<br>~~ai~~||||||||||
|3<br>~~ai~~<br>~~a~~<br>~~ee~~|P4.0[6] <br>~~ai~~<br>~~aee~~<br>~~ee~~|✓(SCB1_RTS) <br>✓<br>~~ai~~<br>~~ee~~|✓(SCB1_MOSI)<br>~~GG~~<br>~~GG~~|~~GG~~<br>~~GG~~|✓(TCPWM0_P) <br>✓<br>~~GG~~|✓(CMOD)<br>✓<br>~~OO~~<br>~~OG~~|~~OO~~<br>~~OG~~|~~OO~~<br>~~OG~~|✓<br>~~OO~~<br>~~OG~~||✓|
|4<br>~~ee~~<br>~~ee~~|P3.7<br>~~ee~~<br>~~ee~~|✓(SCB1_CTS)<br>✓<br>~~ee~~|~~ee~~<br>~~GG~~<br>~~eG~~|~~ee~~<br>~~GG~~<br>~~eG~~|✓(TCPWM)<br>✓<br>~~ee~~<br>~~GG~~<br>~~OG~~|✓(Sensor)<br>✓<br>~~ee~~<br>~~OG~~<br>~~OG~~|✓<br>~~ee~~<br>~~OG~~<br>~~OG~~|~~ee~~<br>~~OG~~<br>~~OG~~|✓<br>~~ee~~<br>~~OG~~<br>~~OG~~|~~ee~~|✓<br>~~ee~~|
|5<br>~~ee~~|P3.6<br>~~ee~~|✓(SCB1_RTS)<br>✓|~~GG~~<br>~~eG~~<br>~~GG~~|✓<br>~~GG~~<br>~~eG~~<br>~~GG~~|✓(TCPWM)<br>✓<br>~~GG~~<br>~~OG~~<br>~~GG~~|✓(Sensor)<br>✓<br>~~OG~~<br>~~OG~~<br>~~OG~~|~~OG~~<br>~~OG~~<br>~~OG~~|~~OG~~<br>~~OG~~<br>~~OG~~|✓<br>~~OG~~<br>~~OG~~<br>~~OG~~|~~OG~~|✓|
|6<br>~~ee~~<br>~~ee~~|P3.5<br>~~ee~~<br>~~ee~~|✓(SCB1_TX)<br>✓<br>~~ee~~|~~GG~~<br>~~eG~~<br>~~ee~~<br>~~GG~~|✓(SCB1_SCL)<br>✓<br>~~GG~~<br>~~eG~~<br>~~ee~~<br>~~GG~~|✓(TCPWM)<br>✓<br>~~GG~~<br>~~OG~~<br>~~ee~~<br>~~GG~~|✓(Sensor)<br>✓<br>~~OG~~<br>~~OG~~<br>~~ee~~<br>~~OG~~|~~OG~~<br>~~OG~~<br>~~ee~~<br>~~OG~~|~~OG~~<br>~~OG~~<br>~~ee~~<br>~~OG~~|✓<br>~~OG~~<br>~~OG~~<br>~~ee~~<br>~~OG~~|~~ee~~<br>~~OG~~|✓<br>~~ee~~|
|7<br>~~Se~~|P3.4<br>~~Se~~|✓(SCB1_RX)<br>~~Se~~|~~GG~~<br>~~Se~~|✓(SCB1_SDA)<br>~~GG~~<br>~~Se~~|✓(TCPWM)<br>~~GG~~<br>~~Se~~|✓(Sensor)<br>~~OG~~<br>~~Se~~|~~OG~~<br>~~Se~~|~~OG~~<br>~~Se~~|✓<br>~~OG~~<br>~~Se~~|~~OG~~<br>~~Se~~|✓<br>~~Se~~|
|8<br>~~Se~~<br>~~a~~|VREF<br>~~Se~~<br>~~ee~~|Reference Voltage Input (Optional)<br>✓<br>✓<br>~~Se~~<br>~~|~~<br>~~eeGG~~<br>~~OG~~||||||||||
|9<br>~~Se~~<br>~~a~~<br>~~a~~|P2.6<br>~~Se~~<br>~~ee~~<br>~~ee~~|~~Se~~<br>~~|~~<br>~~ee~~<br>~~ee~~|~~Se~~<br>~~|~~<br>~~GG~~<br>~~GG~~|~~Se~~<br>~~|~~<br>~~GG~~<br>~~GG~~|✓(TCPWM)<br>✓<br>~~Se~~<br>~~|~~<br>~~OG~~<br>~~OO~~|✓(Sensor)<br>✓<br>~~Se~~<br>~~|~~<br>~~OG~~<br>~~OO~~|~~Se~~<br>~~|~~<br>~~OG~~<br>~~OO~~|~~Se~~<br>~~|~~<br>~~OG~~<br>~~OO~~|✓<br>~~Se~~<br>~~|~~<br>~~OG~~<br>~~OO~~|~~Se~~<br>~~|~~|✓<br>~~Se~~<br>~~|~~|
|10<br>~~a~~<br>~~a~~<br>~~a~~|P2.4<br>~~ee~~<br>~~ee~~<br>~~es~~|~~ee~~<br>~~ee~~|~~GG~~<br>~~GG~~<br>~~Qe~~|~~GG~~<br>~~GG~~<br>~~Qe~~|✓(TCPWM)<br>✓<br>~~OG~~<br>~~OO~~<br>~~QR~~|✓(Sensor)<br>✓<br>~~OG~~<br>~~OO~~<br>~~OO~~|~~OG~~<br>~~OO~~<br>~~OO~~|~~OG~~<br>~~OO~~<br>~~OO~~|✓<br>~~OG~~<br>~~OO~~<br>~~OO~~||✓|
|11<br>~~a~~<br>~~a~~|P2.3<br>~~ee~~<br>~~es~~|~~ee~~|✓<br>~~GG~~<br>~~Qe~~|~~GG~~<br>~~Qe~~|✓(TCPWM)<br>✓<br>~~OO~~<br>~~QR~~|✓(Sensor)<br>✓<br>~~OO~~<br>~~OO~~|✓<br>~~OO~~<br>~~OO~~|~~OO~~<br>~~OO~~|✓<br>~~OO~~<br>~~OO~~||✓|
|12<br>~~a~~<br>~~a~~<br>~~a~~|P2.2<br>~~es~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|✓(SCB0_SS3)<br>✓<br>~~Qe~~<br>~~GG~~<br>~~GG~~|~~Qe~~<br>~~GG~~<br>~~GG~~|✓(TCPWM)<br>✓<br>~~QR~~<br>~~OO~~|✓(Sensor)<br>✓<br>~~OO~~<br>~~GG~~<br>~~OO~~|~~OO~~<br>~~GG~~<br>~~OO~~|~~OO~~<br>~~GG~~<br>~~OO~~|✓<br>~~OO~~<br>~~GG~~<br>~~OO~~||✓|
|13<br>~~a~~<br>~~a~~|P2.0<br>~~ee~~<br>~~es~~|✓<br>~~ee~~|✓(SCB0_SS1)<br>✓<br>~~GG~~<br>~~Qe~~|~~GG~~<br>~~Qe~~|✓(TCPWM)<br>✓<br>~~OO~~<br>~~QR~~|✓(Sensor)<br>✓<br>~~OO~~<br>~~OO~~|~~OO~~<br>~~OO~~|~~OO~~<br>~~OO~~|✓<br>~~OO~~<br>~~OO~~||✓|
|14<br>~~a~~<br>~~a~~<br>~~ee~~|P1.7<br>~~ee~~<br>~~es~~<br>~~ee~~|✓(SCB0_CTS) <br>✓<br>~~ee~~<br>~~GG~~|✓(SCB0_SCLK<br>✓<br>~~GG~~<br>~~Qe~~<br>~~GG~~|~~GG~~<br>~~Qe~~<br>~~GG~~|✓(TCPWM)<br>✓<br>~~OO~~<br>~~QR~~<br>~~GG~~|✓(Sensor)<br>✓<br>~~OO~~<br>~~OO~~<br>~~GG~~|~~OO~~<br>~~OO~~<br>~~GG~~|~~OO~~<br>~~OO~~<br>~~GG~~|✓<br>~~OO~~<br>~~OO~~<br>~~GG~~||✓|
|15<br>~~a~~<br>~~ee~~|P1.6<br>~~es~~<br>~~ee~~|✓(SCB0_RTS) <br>✓<br>~~GG~~|✓(SCB0_SS0)<br>✓<br>~~Qe~~<br>~~GG~~|✓<br>~~Qe~~<br>~~GG~~|✓(TCPWM)<br>✓<br>~~QR~~<br>~~GG~~|✓(Sensor)<br>✓<br>~~OO~~<br>~~GG~~|~~OO~~<br>~~GG~~|~~OO~~<br>~~GG~~|✓<br>~~OO~~<br>~~GG~~||✓|
|16<br>~~ee~~<br>~~a~~<br>~~a~~|P1.5<br>~~ee ~~<br>~~ee~~<br>~~es~~|✓(SCB0_TX) <br>✓<br> ~~GG~~<br>~~ee~~|✓(SCB0_MISO) <br>✓<br>~~GG~~<br>~~GG~~<br>~~Qe~~|✓(SCB0_SCL)<br>✓<br>~~GG~~<br>~~GG~~<br>~~Qe~~|✓(TCPWM)<br>✓<br>~~GG~~<br>~~QR~~|✓(Sensor)<br>✓<br>~~GG~~<br>~~GO~~<br>~~OO~~|~~GG~~<br>~~GO~~<br>~~OO~~|~~GG~~<br>~~GO~~<br>~~OO~~|✓<br>~~GG~~<br>~~GO~~<br>~~OO~~||✓|
|17<br>~~a~~<br>~~ee~~|P1.4<br>~~es~~<br>~~ee~~|✓(SCB0_RX) <br>✓<br>~~GG~~|✓(SCB0_MOSI) <br>✓<br>~~Qe~~<br>~~GG~~|✓(SCB0_SDA)<br>~~Qe~~<br>~~GG~~|✓(TCPWM)<br>✓<br>~~QR~~<br>~~GG~~|✓(Sensor)<br>✓<br>~~OO~~<br>~~GG~~|~~OO~~<br>~~GG~~|~~OO~~<br>~~GG~~|✓<br><br>~~OO~~<br>~~GG~~|✓|✓|
|18<br>~~a~~<br>~~ee~~|P0.7<br>~~es~~<br>~~ee~~|✓(SCB0_CTS) <br>~~GG~~|✓(SCB0_SCLK<br>~~Qe~~<br>~~GG~~|~~Qe~~<br>~~GG~~|✓(TCPWM)<br>✓<br>~~QR~~<br>~~GG~~|✓(Sensor)<br>✓<br>~~OO~~<br>~~GG~~|~~OO~~<br>~~GG~~|~~OO~~<br>~~GG~~|✓<br>~~OO~~<br>~~GG~~|✓(SWDCLK)|✓|
|19<br>~~ee~~<br>~~a~~<br>~~a~~|P1.0<br>~~ee ~~<br>~~ee~~<br>~~es~~|✓<br> ~~GG~~<br>~~ee~~|✓<br>~~GG~~<br>~~GG~~<br>~~Qe~~|✓<br>~~GG~~<br>~~GG~~<br>~~Qe~~|✓(TCPWM)<br>✓<br>~~GG~~<br>~~QR~~|✓(Sensor)<br>✓<br>~~GG~~<br>~~GO~~<br>~~OO~~|~~GG~~<br>~~GO~~<br>~~OO~~|~~GG~~<br>~~GO~~<br>~~OO~~|✓<br>~~GG~~<br>~~GO~~<br>~~OO~~||✓|
|20<br>~~a~~|P0.4<br>~~es~~|✓(SCB0_RX) <br>✓|✓(SCB0_MOSI) <br>✓<br>~~Qe~~|✓(SCB0_SDA)<br>✓<br>~~Qe~~|✓(TCPWM)<br>✓<br>~~QR~~|✓(Sensor)<br>✓<br>~~OO~~|~~OO~~|✓<br>~~OO~~|✓<br>~~OO~~||✓|
|21<br>~~a~~<br>~~a~~|P0.5<br>~~es~~<br>~~ee~~|✓(SCB0_TX) <br>~~ee~~|✓(SCB0_MISO) <br>~~Qe~~<br>~~GG~~|✓(SCB0_SCL)<br>~~Qe~~<br>~~GG~~|✓(TCPWM)<br>~~QR~~|✓(Sensor)<br>~~OO~~<br>~~GO~~|~~OO~~<br>~~GO~~|~~OO~~<br>~~GO~~|✓<br>~~OO~~<br>~~GO~~||✓|
|22<br>~~a~~<br>~~Po~~|VDD<br>~~i~~<br>~~FT~~|Digital Power Supply Input (1.8 to 5.5V)<br>✓✓<br>✓<br>✓<br>✓<br>~~FT~~||||||||||
|23<br>~~Po~~|P0.6<br>~~FT~~|✓(SCB0_RTS) <br>~~FT~~|✓(SCB0_SS0)||✓(TCPWM)|✓(Sensor)|||✓|✓(SWDIO)|✓|
|24<br>~~Po ~~<br>~~ai~~|GND[7]<br> ~~FT~~<br>~~ai~~|Ground Connection<br>~~FT~~<br>~~ai~~||||||||||
|25<br>~~ai~~<br>~~a~~|GND<br>~~ai~~<br>~~a~~<br>~~i~~|Ground Connection<br>~~ai~~||||||||||
|26<br>~~a~~<br>~~aa~~|GND<br>~~a~~<br>~~i~~<br>~~aa~~|Ground Connection<br>~~aa~~||||||||||
|27<br>~~aa~~<br>~~a~~|GND<br>~~aa~~<br>~~aa~~|Ground Connection<br>~~aa~~||||||||||
|28<br>~~ee~~<br>~~es~~|VDDR<br>~~ee~~<br>~~ee~~|Radio Power Supply (2V to 3.6V)||||||||||
|29<br>~~es~~<br>~~a~~|GND<br>~~ee~~<br>~~ee~~|RF Ground Connection for use with CYBLE-202013-11 only; No Connect for CYBLE-212006-01 and CYBLE-202007-01||||||||||
|30<br>~~es ~~<br>~~a~~|ANT<br> ~~ee~~<br>~~ee~~|RF Pin to External Antenna for use with CYBLE-202013-11 only; No Connect for CYBLE-212006-01 and CYBLE-202007-01||||||||||



## **Notes** 

> 4. TCPWM: Timer, Counter, and Pulse Width Modulator. If supported, the pad can be configured to any of these peripheral functions. 

> 5. TCPWM connections on ports 0, 1, 2, and 3 can be routed through the Digital Signal Interconnect (DSI) to any of the TCPWM blocks and can be either positive or negative polarity. TCPWM connections on port 4 are direct and can only be used with the specified TCPWM block and polarity specified above. 6. When using the capacitive sensing functionality, Pad 3 (P4.0) must be connected to a CMOD capacitor (located off of Cypress BLE Module). The value of this capacitor is 2.2 nF and should be placed as close to the module as possible. 

7. The main board needs to connect all GND connections (Pad 24/25/26/27) on the module to the common ground of the system. 

8. If the I[2] S feature is used in the design, the I[2] S pins shall be dynamically routed to the appropriate available GPIO by PSoC Creator. 

Document Number: 002-15631 Rev.*D 

Page 9 of 40 

**CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11** 

## **Power Supply Connections and Recommended External Components** 

## **Power Connections** 

The CYBLE-2X20XX-X1 contains two power supply connections, VDD and VDDR. The VDD connection supplies power for both digital and analog device operation. The VDDR connection supplies power for the device radio. 

VDD accepts a supply range of 1.71 V to 5.5 V. VDDR accepts a supply range of 2.0 V to 3.6 V. These specifications can be found in Table 12. The maximum power supply ripple for both power connections on the module is 100 mV, as shown in Table 10. 

The power supply ramp rate of VDD must be equal to or greater than that of VDDR. 

## **Connection Options** 

## **External Component Recommendation** 

In either connection scenario, it is recommended to place an external ferrite bead between the supply and the module connection. The ferrite bead should be positioned as close as possible to the module pin connection. 

Figure 7 details the recommended host schematic options for a single supply scenario. The use of one or two ferrite beads will depend on the specific application and configuration of the CYBLE-2X20XX-X1. 

Figure 8 details the recommended host schematic for an independent supply scenario. 

The recommended ferrite bead value is 330 , 100 MHz. (Murata BLM21PG331SN1D). 

Two connection options are available for any application: 

1. Single supply: Connect VDD and VDDR to the same supply. 

2. Independent supply: Power VDD and VDDR separately. 

**Figure 7.  Recommended Host Schematic Options for a Single Supply Option** 

**Single Ferrite Bead Option (Seen from Bottom)** 

**Two Ferrite Bead Option (Seen from Bottom)** 

Document Number: 002-15631 Rev.*D 

Page 10 of 40 

**CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11** 

**Figure 8.  Recommended Host Schematic for an Independent Supply Option** 

**Independent Power Supply Option (Seen from Bottom)** 

Document Number: 002-15631 Rev.*D 

Page 11 of 40 

**CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11** 

## **Antenna Matching Network Requirements for CYBLE-202013-11** 

The CYBLE-202013-11 module requires ANT and GND connections to an external antenna via the RF pad connections on the module (Pads 29 and 30). To optimize RF performance, an Antenna Matching Network (AMN) is required to be placed between the ANT connection (Pad 29) and the antenna used in the final design. Figure 9 details the recommended Pi topology circuit footprint to use for the Antenna Matching Network. 

**Figure 9.  Recommended Antenna Matching Network for CYBLE-202013-11 Module** 

**Module Pad Assignments Seen from Bottom View** 

The design guidelines that should be followed when completing the Antenna Matching Network are as follows: 

- The AMN should be placed close to the antenna on the main board. 

- Routing to the AMN from the ANT pad on the module must be controlled to an impedance of 50 . 

- The final AMN circuit may contain only a single component, or all three components shown above. The final number and type of components will be determined based on the actual design of the system, and the final values for each component can be determined through tuning the AMN. For details on how to properly tune an AMN, refer to the application note, AN91445. 

Document Number: 002-15631 Rev.*D 

Page 12 of 40 

**CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11** 

The CYBLE-2X20XX-X1 schematic is shown in Figure 10. 

**Figure 10.  CYBLE-2X20XX-X1 Schematic Diagram** 

Document Number: 002-15631 Rev.*D 

Page 13 of 40 

**CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11** 

## **Critical Components List** 

Table 5 details the critical components used in the CYBLE-2X20XX-X1 module. 

## **Table 5.  Critical Component List** 

|**Component**|**Reference Designator**|**Description**|
|---|---|---|
|Silicon|U1|56-pin QFN Programmable Radio-on-Chip (PRoC) with BLE|
|Crystal|Y1|24.000 MHz, 12PF|
|Crystal|Y2|32.768 kHz, 12.5PF|



## **Antenna Design** 

Table 6 details trace antenna used in the CYBLE-212006-01 module. For more information, see Table 11. 

## **Table 6.  Trace Antenna Specifications** 

|**Item**|**Description**|
|---|---|
|Frequency Range|2402 – 2480 MHz|
|Peak Gain|-0.5 dBi typical|
|Return Loss|10 dB minimum|



## **Qualified Antenna for CYBLE-202007-01 and CYBLE-202013-11** 

The CYBLE-202007-01 module has been designed to work with a standard 2.2 dBi dipole antenna. Any antenna of equivalent or less gain can be used without additional application and testing for FCC regulations. Table 7 details the approved antennas for the CYBLE-202007-01 module for BLE operation. These antennas may also be used for the CYBLE-202013-11 module, however all FCC and other regulatory testing will be required. 

## **Table 7.  Qualified Antenna** 

|**Manufacturer**|**Part Number**|**Gain**|
|---|---|---|
|Antenova|B4844-01|2.2 dBi|
|RFlink|RF21C01228A|2.0 dBi|
|Pulse|W1030|2.0 dBi|



## **Power Amplifier (PA) and Low Noise Amplifier (LNA)** 

Table 8 details the PA/LNA that is used on the CYBLE-2X20XX-X1 module. For more information, see Table 11. 

## **Table 8.  Power Amplifier/Low Noise Amplifier Details** 

|**Item**|**Description**|
|---|---|
|PA/LNA Manufacturer|Skyworks Inc.|
|PA/LNA Part Number|RFX2401C|
|Power Supply Range|2.0 V to 3.6 V|



Table 9 details the power consumption of the integrated PA/LNA used on the CYBLE-2X20XX-X1 module. Table 9 only details the current consumption of the RFX2401C PA/LNA. VDD= 3.3 V, TA = +25 °C, measured on the RFX2401C evaluation board, unless otherwise noted. 

**Table 9.  Power Amplifier/Low Noise Amplifier Current Consumption Specifications** 

|**Parameter**|**Test Condition**|**Min**|**Typical**|**Max**|**Unit**|
|---|---|---|---|---|---|
|Tx High Power Current|Pout = +20 dBm|–|90|–|mA|
|Tx Quiescent Current|No RF applied|–|17|–|mA|
|Rx Quiescent Current|No RF applied|–|8|–|mA|



Document Number: 002-15631 Rev.*D 

Page 14 of 40 

**CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11** 

## **Enabling Extended Range Feature** 

The CYBLE-2X20XX-X1 modules come with an integrated Power Amplifier/Low Noise Amplifier to allow for extended communication range of up to 400 meters full line-of-sight. This section describes the firmware steps required to enable extended range operation of the CYBLE-2X20XX-X1 modules. 

The Skyworks RFX2401C PA/LNA is controlled by PRoC BLE and uses two GPIOs: 

1.One GPIO to control the PA enable (P3[2]). The PA enable GPIO is controlled directly by the BLE Link Layer. 

2.One GPIO to control the LNA enable (P3[3]). The LNA enable GPIO is controlled directly by the BLE Link Layer. 

Ensure that the PRoC BLE silicon device “Adv/Scan TX Power Level (dBm)” and “Connection TX Power Level (dBm)” in the BLE Component are both set to -12 dBm[[9]] 

To enable the extended range functionality, follow the steps outlined below. 

1.Open your project's _main.c_ file and write the following code to define the register at the top of the code. 

/* define the test register to switch the PA/LNA hardware control pins */ #define     CYREG_SRSS_TST_DDFT_CTRL    0x40030008 

2.Locate/add the event “CYBLE_EVT_STACK_ON" in the application code and insert the following two lines of code to enable the Skyworks RFX2401C. 

/* Mandatory events to be handled by BLE application code */ case CYBLE_EVT_STACK_ON: 

/* Configure the Link Layer to automatically switch PA control pin P3[2] and LNA control pin P3[3] */ CY_SET_XTND_REG32((void CYFAR *)(CYREG_BLE_BLESS_RF_CONFIG), 0x0331); CY_SET_XTND_REG32((void CYFAR *)(CYREG_SRSS_TST_DDFT_CTRL), 0x80000302); 

## **Low Power Operation** 

The CYBLE-2X20XX-X1 module is already optimized for low power operation when in high output power, high gain mode. The Cypress BLE Link Layer will automatically enable TX high power operation, as well as RX high gain operation. When the radio TX or RX operation is not in use (that is, Sleep), the PA/LNA will be set to shutdown mode by the BLE Link Layer. This occurs during sleep modes of the Cypress PRoC BLE silicon device. 

To learn more about optimizing the Cypress PRoC BLE power consumption, refer to AN92584: Designing for Low Power and Estimating Battery Life for BLE Applications. 

## **Note** 

> 9. The CYBLE-212006-01 module is certified for FCC, IC, CE, MIC and KC regulations at an output power of +7.5 dBm. To achieve this output power, RFO2 (PRoC BLE silicon PA level) must be set to the -12 dBm setting in firmware. Settings higher than this will result in higher output power than specified in the CYBLE-212006-01 certifications. 

Document Number: 002-15631 Rev.*D 

Page 15 of 40 

**CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11** 

## **Electrical Specification** 

Table 10 details the absolute maximum electrical characteristics for the Cypress BLE module. 

## **Table 10.  CYBLE-2X20XX-X1 Absolute Maximum Ratings** 

|**Parameter**<br>~~ee~~|**Description**<br>~~rs~~|**Min**<br>~~rsss~~|**Typ**<br>~~ss~~<br>~~es~~|**Max**<br>~~nD~~|**Units**<br>~~I~~|**Details/Conditions**|
|---|---|---|---|---|---|---|
|VDDD_ABS<br>~~ee~~<br>~~a se~~|Analog, digital, or radio supply relative to VSS<br>(VSSD= VSSA)<br>~~rs~~<br>~~se~~|–0.5<br>~~rs ss~~<br>~~se~~|–<br>~~ss~~<br>~~se~~<br>~~es~~|6<br>~~nD ~~<br>~~se~~|V<br> ~~I~~<br>~~se~~|Absolute maximum<br>~~se~~|
|VCCD_ABS<br>~~PF~~|Direct digital core voltage input relative to VSSD<br>|–0.5<br>|–<br>~~es~~<br>|1.95<br>|V<br>|Absolute maximum<br>|
|VDD_RIPPLE<br>~~PFof~~<br>~~ee~~|Maximum power supply ripple for VDDand VDDR<br>input voltage<br>~~of~~<br>~~ts~~|–<br>~~of~~<br>~~ts~~|–<br>~~of~~<br>~~ts~~|100<br>~~of~~<br>~~nD~~|mV<br>~~of~~<br>~~I~~|3.0V supply<br>Ripple frequency of 100 kHz<br>to 750 kHz<br>~~of~~|
|VGPIO_ABS<br>~~PFof~~<br>~~ee~~<br>~~es~~|GPIO voltage<br>~~of~~<br>~~ts~~<br>~~nn~~|–0.5<br>~~of~~<br>~~ts~~<br>~~Is~~|–<br>~~of~~<br>~~ts~~<br>~~(I~~|VDD+0.5<br>~~of~~<br>~~nD~~|V<br>~~of~~<br>~~I~~|Absolute maximum<br>~~of~~|
|IGPIO_ABS<br>~~ee~~<br>~~es~~|Maximum current per GPIO<br>~~ts~~<br>~~nn~~|–25<br>~~ts ~~<br>~~Is~~|–<br> ~~ts~~<br>~~(I~~|25<br>~~nD ~~|mA<br> ~~I~~|Absolute maximum|
|IGPIO_injection<br>~~es~~<br>~~de~~<br>~~ee~~|GPIO injection current: Maximum for VIH> VDD<br>and minimum for VIL< VSS<br>~~nn~~<br>~~de~~<br>~~rs~~|–0.5<br>~~Is~~<br>~~de~~<br>~~rsRs~~|–<br>~~(I~~<br>~~de~~<br>~~rs~~|0.5<br>~~de~~<br>~~nD~~|mA<br>~~de~~<br>~~ns~~|Absolute maximum current<br>injected per pin<br>~~de~~|
|LU<br>~~ee~~|Pin current for latch up<br>~~rs~~|–200<br>~~rsRs~~|~~rs~~|200<br>~~nD~~|mA<br>~~ns~~|–|



Table 11 details the RF characteristics for the Cypress BLE module. 

**Table 11.  CYBLE-2X20XX-X1 RF Performance Characteristics** 

|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Units**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|RFO|RF output power on ANT|1||7.5|dBm|Configurable via silicon<br>register settings|
|RXS|RF receive sensitivity on ANT|–|–93|–|dBm|Measured value<br>(CYBLE-212006-01)|
|FR|Module frequency range|2402|–|2480|MHz|–|
|GP|Peak gain|–|–0.5|–|dBi|–|
|RL|Return loss|–|–10|–|dB|–|



Table 12 through Table 51 list the module level electrical characteristics for the CYBLE-2X20XX-X1. All specifications are valid for – 40 °C  TA  85 °C and TJ  100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted. 

**Table 12.  CYBLE-2X20XX-X1 DC Specifications** 

|**Parameter**<br>~~eeDD~~<br>~~es~~|**Description**<br>~~DD~~<br>|**Min**<br>~~DD~~<br><br>~~Us~~|**Typ**<br>~~DD~~<br>~~tn~~<br><br>~~Us~~|**Max**<br>~~DD~~<br>~~I~~<br><br>~~(QO~~|**Units**<br>~~DD~~<br>~~(~~<br><br>~~(QO~~|**Details/Conditions**<br>~~DD~~<br><br>~~(O~~|
|---|---|---|---|---|---|---|
|VDD1<br>~~eeDD~~<br>~~esnD~~|Power supply input voltage<br>~~DD~~<br>~~nD~~|1.8<br>~~DD~~<br>~~nD~~<br>~~Us~~|–<br>~~DD~~<br>~~tn~~<br>~~nD~~<br>~~Us~~|5.5<br>~~DD~~<br>~~I~~<br>~~nD~~<br>~~(QO~~|V<br>~~DD~~<br>~~(~~<br>~~nD~~<br>~~(QO~~|With regulator enabled<br>~~DD~~<br>~~nD~~<br>~~(O~~|
|VDD2<br>~~esnD~~<br>~~Fir~~<br>~~es~~|Power supply input voltage unregulated<br>~~nD~~<br>~~Fir~~<br>~~rs~~|1.71<br>~~nD~~<br>~~Us~~<br>~~Fir~~<br>~~I~~|1.8<br>~~tn ~~<br>~~nD~~<br>~~Us~~<br>~~Fir~~<br>~~Ss~~|1.89<br> ~~I ~~<br>~~nD~~<br>~~(QO~~<br>~~Fir~~<br>~~QO~~|V<br> ~~(~~<br>~~nD~~<br>~~(QO ~~<br>~~Fir~~<br>~~QO~~|Internally unregulated<br>supply<br>~~nD~~<br> ~~(O~~<br>~~Fir~~|
|VDDR1<br>~~Fir~~<br>~~es~~<br>~~eeey~~|Radio supply voltage (radio on)<br>~~Fir~~<br>~~rs~~<br>~~ey~~|2.0<br>~~Fir~~<br>~~I~~<br>~~ey~~<br>~~Dn~~|–<br>~~Fir~~<br>~~Ss~~<br>~~ey~~<br>~~Dn~~|3.6<br>~~Fir~~<br>~~QO~~<br>~~ey~~|V<br>~~Fir~~<br>~~QO~~<br>~~ey~~|Restricted by RFX2401C<br>~~Fir~~<br>~~ey~~|
|VDDR2<br>~~es~~<br>~~eeey~~|Radio supply voltage (radio off)<br>~~rs ~~<br>~~ey~~|2.0<br> ~~I ~~<br>~~ey~~<br>~~Dn~~|–<br> ~~Ss~~<br>~~ey~~<br>~~Dn~~|3.6<br>~~QO~~<br>~~ey~~|V<br>~~QO~~<br>~~ey~~|–<br>~~ey~~|
|**Active Mode, VDD = 1.71 V to 5.5 V**<br>~~eeey~~<br>~~Dn~~<br>~~Ce~~|||||||
|IDD3<br>~~Ce~~<br>~~fir~~<br>~~es~~|Execute from flash; CPU at 3 MHz<br>~~Ce~~<br>~~fir~~<br>~~nD~~|–<br>~~Ce~~<br>~~fir~~<br>~~I~~|1.7<br>~~Ce~~<br>~~fir~~<br>~~ts~~|–<br>~~Ce~~<br>~~fir~~<br>~~(QO~~|mA<br>~~Ce~~<br>~~fir~~<br>~~(QO~~|T = 25 °C,<br>VDD= 3.3 V<br>~~Ce~~<br>~~fir~~|
|IDD4<br>~~es~~<br>~~es~~|Execute from flash; CPU at 3 MHz<br>~~nD~~<br>|–<br>~~I~~<br>~~ee~~<br>|–<br>~~ts~~<br>~~ee~~<br>|–<br>~~(QO~~<br>~~ee~~<br>|mA<br>~~(QO~~<br>~~ee ee~~<br>|T = –40 °C to 85 °C<br>~~ee~~<br>|
|IDD5<br>~~es~~<br>~~a ee~~<br>~~es~~<br>~~—~~|Execute from flash; CPU at 6 MHz<br>~~nD ~~<br>~~ee~~<br><br>|–<br> ~~I~~<br>~~ee~~<br>~~ee~~<br><br>~~I~~<br>|2.5<br>~~ts~~<br>~~ee~~<br>~~ee~~<br><br>~~rs~~<br>|–<br>~~(QO~~<br>~~ee~~<br>~~ee~~<br><br>~~I~~<br>|mA<br>~~(QO~~<br>~~ee~~<br>~~ee ee~~<br><br>~~( (~~<br>|T = 25 °C,<br>VDD= 3.3 V<br>~~ee~~<br>~~ee~~<br><br>~~(~~<br>|
|IDD6<br>~~esnD~~<br>~~—~~|Execute from flash; CPU at 6 MHz<br>~~nD~~<br>|–<br>~~ee~~<br>~~nD~~<br>~~I~~<br>|–<br>~~ee~~<br>~~nD~~<br>~~rs~~<br>|–<br>~~ee~~<br>~~nD~~<br>~~I~~<br>|mA<br>~~ee ee~~<br>~~nD~~<br>~~( (~~<br>|T = –40 °C to 85 °C<br>~~ee~~<br>~~nD~~<br>~~(~~<br>|
|IDD7<br>~~esnD~~<br>~~—F—“‘i—‘i~~<br>~~es~~|Execute from flash; CPU at 12 MHz<br>~~nD~~<br>~~F—“‘i—‘i~~<br>~~nDs(n~~|–<br>~~ee ~~<br>~~nD~~<br>~~I~~<br>~~F—“‘i—‘i~~<br>~~s(n~~|4<br> ~~ee ~~<br>~~nD~~<br>~~rs~~<br>~~F—“‘i—‘i~~<br>~~s(n~~|–<br> ~~ee~~<br>~~nD~~<br>~~I~~<br>~~F—“‘i—‘i~~<br>~~s(n~~|mA<br>~~ee ee~~<br>~~nD~~<br>~~( (~~<br>~~F—“‘i—‘i~~<br>~~s(n~~|T = 25 °C,<br>VDD= 3.3 V<br>~~ee~~<br>~~nD~~<br>~~(~~<br>~~F—“‘i—‘i~~<br>~~s(n~~|
|IDD8<br>~~— F—“‘i—‘i~~<br>~~es~~|Execute from flash; CPU at 12 MHz<br>~~F—“‘i—‘i~~<br>~~nDs(n~~|–<br>~~I~~<br>~~F—“‘i—‘i~~<br>~~s(n~~|–<br>~~rs ~~<br>~~F—“‘i—‘i~~<br>~~s(n~~|–<br> ~~I ~~<br>~~F—“‘i—‘i~~<br>~~s(n~~|mA<br> ~~( (~~<br>~~F—“‘i—‘i~~<br>~~s(n~~|T = –40 °C to 85 °C<br>~~(~~<br>~~F—“‘i—‘i~~<br>~~s(n~~|



Document Number: 002-15631 Rev.*D 

Page 16 of 40 

**CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11** 

**Table 12.  CYBLE-2X20XX-X1 DC Specifications** (continued) 

|**Parameter**<br>~~es~~|**Description**<br>~~aD~~|**Min**<br>~~aD~~<br>~~Ut SD~~|**Typ**<br>~~aD~~<br>~~SD~~|**Max**<br>~~aD~~<br>~~I~~|**Units**<br>~~aD~~<br>~~(RO (~~|**Details/Conditions**<br>~~aD~~<br>~~(~~|
|---|---|---|---|---|---|---|
|IDD9<br>~~es~~<br>~~Fir~~<br>~~es~~|Execute from flash; CPU at 24 MHz<br>~~aD~~<br>~~Fir~~<br>~~nD~~|–<br>~~aD~~<br>~~Ut SD~~<br>~~Fir~~<br>~~ts~~|7.1<br>~~aD~~<br>~~SD ~~<br>~~Fir~~<br>~~ts~~|–<br>~~aD~~<br> ~~I ~~<br>~~Fir~~<br>~~QO~~|mA<br>~~aD~~<br> ~~(RO (~~<br>~~Fir~~<br>~~QO~~|T = 25 °C,<br>VDD= 3.3 V<br>~~aD~~<br>~~(~~<br>~~Fir~~|
|IDD10<br>~~es~~<br>~~ee~~|Execute from flash; CPU at 24 MHz<br>~~nD~~<br>|–<br>~~ts~~<br>~~ee~~<br>|–<br>~~ts~~<br>|–<br>~~QO~~<br>|mA<br>~~QO~~<br>|T = –40 °C to 85 °C<br>|
|IDD11<br>~~es~~<br>~~ee~~<br>~~ee~~|Execute from flash; CPU at 48 MHz<br>~~nD~~<br>~~ee~~<br>|–<br>~~ts~~<br>~~ee~~<br>~~ee~~<br><br>~~Dn~~|13.4<br>~~ts~~<br>~~ee~~<br><br>~~Dn~~|–<br>~~QO~~<br>~~ee~~<br>|mA<br>~~QO~~<br>~~ee~~<br>|T = 25 °C,<br>VDD= 3.3 V<br>~~ee~~<br>|
|IDD12<br>~~ee~~|Execute from flash; CPU at 48 MHz<br>~~ey~~|–<br>~~ee~~<br>~~ey~~<br>~~Dn~~|–<br>~~ey~~<br>~~Dn~~|–<br>~~ey~~|mA<br>~~ey~~|T = –40 °C to 85 °C<br>~~ey~~|
|**Sleep Mode, VDD = 1.8 to 5.5 V**<br>~~ee~~<br>~~eeey~~<br>~~Dn~~<br>~~Ce~~|||||||
|IDD13<br>~~Ce~~<br>~~fit~~|IMO on<br>~~Ce~~<br>~~fit~~|–<br>~~Ce~~<br>~~fit~~|–<br>~~Ce~~<br>~~fit~~|–<br>~~Ce~~<br>~~fit~~|mA<br>~~Ce~~<br>~~fit~~|T = 25 °C, VDD= 3.3 V,<br>SYSCLK = 3 MHz<br>~~Ce~~<br>~~fit~~|
|**Sleep Mode, VDD and VDDR = 1.9 to 5.5 V**<br>~~fit~~<br>~~eee~~<br>~~Gsee~~|||||||
|IDD14<br>~~ee~~|ECO on<br>~~ee~~|–<br>~~ee~~<br>~~Gs~~|–<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~|mA<br>~~ee~~|T = 25 °C, VDD= 3.3 V,<br>SYSCLK = 3 MHz<br>~~ee~~|
|**Deep-Sleep Mode, VDD = 1.8 to 3.6 V**<br>~~Gs ee~~<br>~~Ce~~<br>~~—F—“—‘—i~~|||||||
|IDD15<br>~~Ce~~<br>~~—F—“—‘—i~~<br>~~es~~<br>~~—~~|WDT with WCO on<br>~~Ce~~<br>~~F—“—‘—i~~<br>~~nD~~<br>|–<br>~~Ce~~<br>~~F—“—‘—i~~<br>~~nD~~<br>~~rs~~<br>|1.5<br>~~Ce~~<br>~~F—“—‘—i~~<br>~~nD~~<br>~~rs~~<br>|–<br>~~Ce~~<br>~~F—“—‘—i~~<br>~~nD~~<br>~~QO~~<br>|A<br>~~Ce~~<br>~~F—“—‘—i~~<br>~~nD~~<br>~~QO~~<br>|T = 25 °C,<br>VDD= 3.3 V<br>~~Ce~~<br>~~F—“—‘—i~~<br>~~nD~~<br>|
|IDD16<br>~~— F—“—‘—i~~<br>~~es~~<br>~~—~~|WDT with WCO on<br>~~F—“—‘—i~~<br>~~nD~~<br>|–<br>~~F—“—‘—i~~<br>~~nD~~<br>~~rs~~<br>|–<br>~~F—“—‘—i~~<br>~~nD~~<br>~~rs~~<br>|–<br>~~F—“—‘—i~~<br>~~nD~~<br>~~QO~~<br>|A<br>~~F—“—‘—i~~<br>~~nD~~<br>~~QO~~<br>|T = –40 °C to 85 °C<br>~~F—“—‘—i~~<br>~~nD~~<br>|
|IDD17<br>~~es~~<br>~~— f—i—ir~~<br>~~es~~|WDT with WCO on<br>~~nD~~<br>~~f—i—ir~~<br>~~Ds~~|–<br>~~nD~~<br>~~rs~~<br>~~f—i—ir~~<br>~~Ds~~|–<br>~~nD~~<br>~~rs~~<br>~~f—i—ir~~<br>~~Ds~~|–<br>~~nD~~<br>~~QO~~<br>~~f—i—ir~~<br>~~Ds~~<br>~~(Os~~|A<br>~~nD~~<br>~~QO~~<br>~~f—i—ir~~<br>~~Ds~~<br>~~( (~~|T = 25 °C,<br>VDD= 5 V<br>~~nD~~<br>~~f—i—ir~~<br>~~Ds~~<br>~~(~~|
|IDD18<br>~~— ~~<br>~~es~~|WDT with WCO on<br><br>~~Ds~~|–<br>~~rs~~<br><br>~~Ds~~|–<br>~~rs ~~<br><br>~~Ds~~|–<br> ~~QO~~<br><br>~~Ds~~<br>~~(Os~~|A<br>~~QO~~<br><br>~~Ds~~<br>~~( (~~|T = –40 °C to 85 °C<br><br>~~Ds~~<br>~~(~~|
|**Deep-Sleep Mode, VDD = 1.71 to 1.89 V (Regulator Bypassed)**<br>~~esDs~~<br>~~(Os( (~~<br>~~Ce~~<br>~~es~~<br>~~nD~~<br>~~rs~~<br>~~( (~~|||||||
|IDD19<br>~~Ce~~<br>~~es~~<br>~~es~~|WDT with WCO on<br>~~Ce~~<br>~~nD~~<br>~~nD~~|–<br>~~Ce~~<br>~~rs~~<br>~~rs~~|–<br>~~Ce~~<br>~~rs~~<br>~~rs~~|–<br>~~Ce~~<br>~~(~~<br>~~I~~|A<br>~~Ce~~<br>~~( (~~<br>~~(~~|T = 25 °C<br>~~Ce~~<br>~~(~~|
|IDD20<br>~~es~~<br>~~es~~|WDT with WCO on<br>~~nD~~<br>~~nD~~|–<br>~~rs~~<br>~~rs~~|–<br>~~rs~~<br>~~rs~~|–<br>~~(~~<br>~~I~~|A<br>~~( (~~<br>~~(~~|T = –40 °C to 85 °C<br>~~(~~|
|**Hibernate Mode, VDD = 1.8 to 3.6 V**<br>~~es~~<br>~~nD rs I (~~<br>~~Ce~~<br>~~—F——“‘—i—i~~|||||||
|IDD27<br>~~Ce~~<br>~~—F——“‘—i—i~~<br>~~es~~|GPIO and reset active<br>~~Ce~~<br>~~F——“‘—i—i~~<br>~~nD~~|–<br>~~Ce~~<br>~~F——“‘—i—i~~<br>~~rs~~|150<br>~~Ce~~<br>~~F——“‘—i—i~~<br>~~rs~~|–<br>~~Ce~~<br>~~F——“‘—i—i~~<br>~~I (~~|nA<br>~~Ce~~<br>~~F——“‘—i—i~~<br>~~( (~~|T = 25 °C,<br>VDD= 3.3 V<br>~~Ce~~<br>~~F——“‘—i—i~~<br>~~(~~|
|IDD28<br>~~— F——“‘—i—i~~<br>~~es~~|GPIO and reset active<br>~~F——“‘—i—i~~<br>~~nD~~|–<br>~~F——“‘—i—i~~<br>~~rs~~|–<br>~~F——“‘—i—i~~<br>~~rs~~|–<br>~~F——“‘—i—i~~<br>~~I (~~|nA<br>~~F——“‘—i—i~~<br>~~( (~~|T = –40 °C to 85 °C<br>~~F——“‘—i—i~~<br>~~(~~|
|**Hibernate Mode, VDD = 3.6 to 5.5 V**<br>~~es~~<br>~~nD~~<br>~~rs~~<br>~~I ( (~~<br>~~eee~~<br>~~Ge~~<br>~~ee~~|||||||
|IDD29<br>~~ee~~<br>~~ee~~|GPIO and reset active<br>~~ee~~<br>|–<br>~~ee~~<br>~~Ge~~<br><br>~~Dn~~|–<br>~~ee~~<br><br>~~Dn~~|–<br>~~ee~~<br>|nA<br>~~ee~~<br>|T = 25 °C,<br>VDD= 5 V<br>~~ee~~<br>|
|IDD30<br>~~ee~~|GPIO and reset active<br>~~ey~~|–<br>~~Ge~~<br>~~ey~~<br>~~Dn~~|–<br>~~ey~~<br>~~Dn~~|–<br>~~ey~~|nA<br>~~ey~~|T = –40 °C to 85 °C<br>~~ey~~|
|**Stop Mode, VDD = 1.8 to 3.6 V**<br>~~Ge~~<br>~~eeey~~<br>~~Dn~~<br>~~Ce~~<br>~~—F——i—‘ir~~|||||||
|IDD33<br>~~—F——i—‘ir~~|Stop-mode current (VDD)<br>~~F——i—‘ir~~|–<br>~~F——i—‘ir~~|20<br>~~F——i—‘ir~~|–<br>~~F——i—‘ir~~|nA<br>~~F——i—‘ir~~|T = 25 °C,<br>VDD= 3.3 V<br>~~F——i—‘ir~~|
|IDD34<br>~~— F——i—‘ir~~<br>~~Fir~~<br>~~es~~|Stop-mode current (VDDR)<br>~~F——i—‘ir~~<br>~~Fir~~<br>~~rs~~|–<br>~~F——i—‘ir~~<br>~~Fir~~<br>~~I~~|40<br>~~F——i—‘ir~~<br>~~Fir~~<br>~~Ss~~|–-<br>~~F——i—‘ir~~<br>~~Fir~~<br>~~QO~~|nA<br>~~F——i—‘ir~~<br>~~Fir~~<br>~~QO~~|T = 25 °C,<br>VDDR= 3.3 V<br>~~F——i—‘ir~~<br>~~Fir~~|
|IDD35<br>~~Fir~~<br>~~es~~|Stop-mode current (VDD)<br>~~Fir~~<br>~~rs~~|–<br>~~Fir~~<br>~~I~~<br>~~ee~~|–<br>~~Fir~~<br>~~Ss~~<br>~~ee~~|–<br>~~Fir~~<br>~~QO~~|nA<br>~~Fir~~<br>~~QO~~|T = –40 °C to 85 °C<br>~~Fir~~|
|IDD36<br>~~es~~<br>~~ee~~|Stop-mode current (VDDR)<br>~~rs ~~<br>~~ee~~|–<br> ~~I ~~<br>~~ee~~<br>~~ee~~|–<br> ~~Ss~~<br>~~ee~~<br>~~ee~~|–<br>~~QO~~<br>~~ee~~|nA<br>~~QO~~<br>~~ee~~|T = –40 °C to 85 °C,<br>VDDR= 1.9 V to 3.6 V<br>~~ee~~|
|**Stop Mode, VDD = 3.6 to 5.5 V**<br>~~ee ee~~<br>~~Ce~~<br>~~—F——“‘—i—i~~|||||||
|IDD37<br>~~Ce~~<br>~~—F——“‘—i—i~~<br>~~—F—“‘i—‘i~~|Stop-mode current (VDD)<br>~~Ce~~<br>~~F——“‘—i—i~~<br>~~F—“‘i—‘i~~|–<br>~~Ce~~<br>~~F——“‘—i—i~~<br>~~F—“‘i—‘i~~|–<br>~~Ce~~<br>~~F——“‘—i—i~~<br>~~F—“‘i—‘i~~|–<br>~~Ce~~<br>~~F——“‘—i—i~~<br>~~F—“‘i—‘i~~|nA<br>~~Ce~~<br>~~F——“‘—i—i~~<br>~~F—“‘i—‘i~~|T = 25 °C,<br>VDD= 5 V<br>~~Ce~~<br>~~F——“‘—i—i~~<br>~~F—“‘i—‘i~~|
|IDD38<br>~~— F——“‘—i—i~~<br>~~—F—“‘i—‘i~~<br>~~es~~|Stop-mode current (VDDR)<br>~~F——“‘—i—i~~<br>~~F—“‘i—‘i~~<br>~~nD~~|–<br>~~F——“‘—i—i~~<br>~~F—“‘i—‘i~~<br>~~ns~~|–<br>~~F——“‘—i—i~~<br>~~F—“‘i—‘i~~<br>~~ns~~|–<br>~~F——“‘—i—i~~<br>~~F—“‘i—‘i~~<br>~~QO~~|nA<br>~~F——“‘—i—i~~<br>~~F—“‘i—‘i~~<br>~~QO~~|T = 25 °C,<br>VDDR= 5 V<br>~~F——“‘—i—i~~<br>~~F—“‘i—‘i~~|
|IDD39<br>~~— F—“‘i—‘i~~<br>~~es~~<br>~~es~~|Stop-mode current (VDD)<br>~~F—“‘i—‘i~~<br>~~nD~~<br>~~nD~~|–<br>~~F—“‘i—‘i~~<br>~~ns~~<br>~~I~~|–<br>~~F—“‘i—‘i~~<br>~~ns~~<br>~~s(n~~|–<br>~~F—“‘i—‘i~~<br>~~QO~~<br>~~s(n~~|nA<br>~~F—“‘i—‘i~~<br>~~QO~~<br>~~s(n~~|T = –40 °C to 85 °C<br>~~F—“‘i—‘i~~|
|IDD40<br>~~es~~<br>~~es~~|Stop-mode current (VDDR)<br>~~nD ~~<br>~~nD~~|–<br> ~~ns~~<br>~~I~~|–<br>~~ns~~<br>~~s(n~~|–<br>~~QO~~<br>~~s(n~~|nA<br>~~QO~~<br>~~s(n~~|T = –40 °C to 85 °C|



Document Number: 002-15631 Rev.*D 

Page 17 of 40 

**CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11** 

## **Table 13.  AC Specifications** 

|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Units**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|FCPU|CPU frequency|DC|–|48|MHz|1.71 VVDD 5.5 V|
|TSLEEP|Wakeup from Sleep mode|–|0|–|s|Guaranteed by characterization|
|TDEEPSLEEP|Wakeup from Deep-Sleep mode|–|–|25|s|24-MHz IMO. Guaranteed by<br>characterization|
|THIBERNATE|Wakeup from Hibernate mode|–|–|2|ms|Guaranteed by characterization|
|TSTOP|Wakeup from Stop mode|–|–|2|ms|XRES wakeup|



|**Parameter**<br>~~PT~~|**Description**<br>~~PTeee~~|**Min**<br>~~eee~~|**Typ**<br>~~eee~~<br>~~ts~~|**Max**<br>~~eee~~<br>~~ts~~|**Units**<br>~~eee~~|**Details/Conditions**<br>~~eee~~|
|---|---|---|---|---|---|---|
|VIH<br>[10]<br>~~PT~~|Input voltage HIGH threshold<br>~~PT~~<br>~~Pn~~|0.7 × VDD<br><br>~~Pn~~|–<br><br>~~Pn~~<br>~~ts~~|–<br><br>~~Pn~~<br>~~ts~~<br>~~Gn~~|V<br><br>~~Pn~~<br>~~ns~~|CMOS input<br><br>~~Pn~~|
||LVTTL input, VDD< 2.7 V<br>~~Pn~~<br>~~RG~~|0.7 × VDD<br>~~Pn~~<br>~~RG~~|–<br>~~Pn~~<br>~~ts~~<br>~~RG~~<br>~~rts~~|–<br>~~Pn~~<br>~~ts~~<br>~~RG~~<br>~~Gn~~<br>~~rts~~|V<br>~~Pn~~<br>~~RG~~<br>~~ns~~<br>~~ns~~|–<br>~~Pn~~<br>~~RG~~|
||LVTTL input, VDD 2.7 V<br>~~RG~~<br>~~et~~|2.0<br>~~RG~~<br>~~et~~|–<br>~~RG~~<br>~~et~~<br>~~rts~~|–<br>~~RG~~<br>~~Gn~~<br>~~et~~<br>~~rts~~|V<br>~~RG~~<br>~~ns~~<br>~~et~~<br>~~ns~~|–<br>~~RG~~<br>~~et~~|
|VIL<br>~~——————————~~|Input voltage LOW threshold<br>~~Gn~~|–<br>~~Gn~~|–<br>~~rts~~<br>~~Gn~~|0.3 × VDD<br>~~rts~~<br>~~Gn~~<br>~~Gn~~|V<br>~~ns~~<br>~~Gn~~<br>~~ns~~|CMOS input<br>~~Gn~~|
||LVTTL input, VDD< 2.7 V<br>~~Gn~~<br>~~RG~~|–<br>~~Gn~~<br>~~RG~~|–<br>~~Gn~~<br>~~RG~~<br>~~rts~~|0.3 × VDD<br>~~Gn~~<br>~~RG~~<br>~~Gn~~<br>~~rts~~|V<br>~~Gn~~<br>~~RG~~<br>~~ns~~<br>~~ns~~|–<br>~~Gn~~<br>~~RG~~|
||LVTTL input, VDD 2.7 V<br>~~RG~~<br>~~et~~<br>~~—————————~~|–<br>~~RG~~<br>~~et~~<br>~~—————————~~|–<br>~~RG~~<br>~~et~~<br>~~rts~~<br>~~—————————~~|0.8<br>~~RG~~<br>~~Gn~~<br>~~et~~<br>~~rts~~<br>~~—————————~~|V<br>~~RG~~<br>~~ns~~<br>~~et~~<br>~~ns~~<br>~~—————————~~|–<br>~~RG~~<br>~~et~~<br>~~—————————~~|
|VOH<br>~~——————————~~|Output voltage HIGH level<br>~~—————————~~<br>~~a~~|VDD–0.6<br>~~—————————~~<br>~~rr~~|–<br>~~rts~~<br>~~—————————~~<br>|–<br>~~rts~~<br>~~—————————~~<br>~~(~~|V<br>~~ns~~<br>~~—————————~~<br>~~(~~|IOH= 4 mA at 3.3-V VDD<br>~~—————————~~<br>~~(~~|
||Output voltage HIGH level<br>~~—————————~~<br>~~a~~<br>~~a~~|VDD–0.5<br>~~—————————~~<br>~~rr~~<br>~~rs~~|–<br>~~—————————~~<br><br>~~rs~~|–<br>~~—————————~~<br>~~(~~<br>~~nr~~|V<br>~~—————————~~<br>~~(~~|IOH= 1 mA at 1.8-V VDD<br>~~—————————~~<br>~~(~~|
|VOL<br>~~——————————~~<br>~~es~~|Output voltage LOW level<br>~~—————————~~<br>~~a~~<br>~~a~~|–<br>~~—————————~~<br>~~rr ~~<br>~~rs~~|–<br>~~—————————~~<br> <br>~~rs~~|0.6<br>~~—————————~~<br> ~~(~~<br>~~nr~~|V<br>~~—————————~~<br>~~(~~|IOL= 8 mA at 3.3-V VDD<br>~~—————————~~<br>~~(~~|
||Output voltage LOW level<br>~~a~~<br>~~Gn~~<br>~~a~~|–<br>~~rs~~<br>~~Gn~~<br>~~rr~~|–<br>~~rs ~~<br>~~Gn~~<br>|0.6<br> ~~nr~~<br>~~Gn~~<br>~~(~~|V<br>~~Gn~~<br>~~(~~|IOL= 4 mA at 1.8-V VDD<br>~~Gn~~<br>~~(~~|
||Output voltage LOW level<br>~~Gn~~<br>~~a~~|–<br>~~Gn~~<br>~~rr~~|–<br>~~Gn~~<br>|0.4<br>~~Gn~~<br>~~(~~|V<br>~~Gn~~<br>~~(~~|IOL= 3 mA at 3.3-V VDD<br>~~Gn~~<br>~~(~~|
|RPULLUP<br>~~es~~<br>~~es~~|Pull-up resistor<br>~~a~~<br>~~tt tr~~|3.5<br>~~rr~~<br>~~tr~~|5.6<br><br>~~tr~~|8.5<br>~~(~~<br>~~I~~|k<br>~~(~~|–<br>~~(~~|
|RPULLDOWN<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~|Pull-down resistor<br>~~a~~<br>~~tt tr~~<br>~~te~~|3.5<br>~~rr ~~<br>~~tr~~<br>~~te~~|5.6<br> <br>~~tr~~<br>~~te~~|8.5<br> ~~(~~<br>~~I~~<br>~~te~~<br>~~QO~~|k<br>~~(~~<br>~~te~~<br>~~QO~~|–<br>~~(~~<br>~~te~~|
|IIL<br>~~es~~<br>~~es~~<br>~~es~~|Input leakage current (absolute value)<br>~~tt tr~~<br>~~te~~|–<br>~~tr~~<br>~~te~~|–<br>~~tr~~<br>~~te~~|2<br>~~I~~<br>~~te~~<br>~~QO~~|nA<br>~~te~~<br>~~QO~~|25 °C, VDD= 3.3 V<br>~~te~~|
|IIL_CTBM<br>~~es~~<br>~~es~~<br>~~es~~|Input leakage on CTBm input pins<br>~~te~~<br>~~tt tr~~|–<br>~~te~~<br>~~tr~~|–<br>~~te~~<br>~~tr~~|4<br>~~te~~<br>~~QO~~<br>~~I~~|nA<br>~~te~~<br>~~QO~~|–<br>~~te~~|
|CIN<br>~~es~~<br>~~es~~<br>~~es~~|Input capacitance<br>~~tt tr~~<br>~~rs~~|–<br>~~tr~~<br>~~rs(~~|–<br>~~tr~~|7<br>~~QO~~<br>~~I~~|pF<br>~~QO~~|–|
|VHYSTTL<br>~~es~~<br>~~es~~<br>~~es~~|Input hysteresis LVTTL<br>~~tt tr~~<br>~~rs~~<br>~~rs~~|25<br>~~tr~~<br>~~rs(~~<br>~~rs~~|40<br>~~tr~~|–<br>~~I~~|mV|VDD> 2.7 V|
|VHYSCMOS<br>~~es~~<br>~~es~~|Input hysteresis CMOS<br>~~rs~~<br>~~rs~~|0.05 × VDD<br>~~rs(~~<br>~~rs~~<br>~~ee~~|–<br>~~ee~~|–<br>~~ee~~|1<br>~~ee~~|–<br>~~ee~~|
|IDIODE<br>~~es~~<br>~~a ee~~|Current through protection diode to<br>VDD/VSS<br>~~rs~~<br>~~ee~~|–<br>~~rs~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~<br>~~ee~~|100<br>~~ee~~<br>~~ee~~<br>~~ee~~|A<br>~~ee~~<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|ITOT_GPIO<br>~~ee~~|Maximum total source or sink chip<br>current<br>~~ee~~|–<br>~~ee ~~<br>~~ee~~<br>~~ee~~|–<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|200<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|mA<br> ~~ee~~<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~<br>~~ee~~|



**Note** 10. VIH must not exceed VDD + 0.2 V. 

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**Table 15.  GPIO AC Specifications** 

|**Parameter**<br>~~ae~~<br>~~ee~~|**Description**<br>~~rn~~<br>~~OI~~|**Min**<br>~~nts~~<br>~~OI~~|**Typ**<br>~~ttt~~<br>~~II~~|**Max**<br>~~(tre~~<br>~~I~~|**Units**<br>~~I~~<br>~~I~~|**Details/Conditions**|
|---|---|---|---|---|---|---|
|TRISEF<br>~~ae~~<br>~~ee~~<br>~~ee~~|Rise time in Fast-Strong mode<br>~~rn ~~<br>~~OI~~<br>~~Pr~~|2<br> ~~nts ~~<br>~~OI~~<br>~~Pr~~|–<br> ~~ttt ~~<br>~~II~~<br>~~ttt~~|12<br> ~~(tre~~<br>~~I~~<br>~~UD~~|ns<br>~~I~~<br>~~I~~|3.3-V VDDD, CLOAD= 25 pF|
|TFALLF<br>~~ee~~<br>~~ee~~<br>~~ee~~|Fall time in Fast-Strong mode<br>~~OI~~<br>~~Pr~~<br>~~ts~~|2<br>~~OI~~<br>~~Pr~~<br>~~ts~~|–<br>~~II ~~<br>~~ttt~~<br>~~It~~|12<br> ~~I~~<br>~~UD~~|ns<br>~~I~~|3.3-V VDDD, CLOAD= 25 pF|
|TRISES<br>~~ee~~<br>~~ee~~<br>~~es~~|Rise time in Slow-Strong mode<br>~~Pr~~<br>~~ts~~<br>~~rs~~|10<br>~~Pr ~~<br>~~ts~~<br>~~rs~~|–<br> ~~ttt ~~<br>~~It~~<br>~~rs~~|60<br> ~~UD~~<br>~~rs~~|ns|3.3-V VDDD, CLOAD= 25 pF|
|TFALLS<br>~~ee~~<br>~~es~~<br>~~ee~~|Fall time in Slow-Strong mode<br>~~ts~~<br>~~rs~~<br>~~ee~~|10<br>~~ts ~~<br>~~rs~~<br>~~ee~~|–<br> ~~It~~<br>~~rs~~<br>~~ee~~|60<br>~~rs~~<br>~~ee~~|ns<br>~~ee~~|3.3-V VDDD, CLOAD= 25 pF|
|FGPIOUT1<br>~~es~~<br>~~ee~~<br>~~ee~~|GPIO Fout; 3.3 VVDD5.5 V<br>Fast-Strong mode<br>~~rs ~~<br>~~ee~~<br>~~ee~~|–<br> ~~rs~~<br>~~ee~~<br>~~ee~~|–<br>~~rs~~<br>~~ee~~<br>~~ee~~|33<br>~~rs~~<br>~~ee~~<br>~~ee~~|MHz<br>~~ee~~<br>~~ee~~|90/10%, 25 pF load, 60/40 duty<br>cycle|
|FGPIOUT2<br>~~ee~~<br>~~ee~~<br>~~ee~~|GPIO Fout; 1.7 VVDD3.3 V<br>Fast-Strong mode<br>~~ee ~~<br>~~ee~~<br>~~ee~~|–<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|–<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|16.7<br> ~~ee~~<br>~~ee~~<br>~~ee~~|MHz<br>~~ee~~<br>~~ee~~<br>~~ee~~|90/10%, 25 pF load, 60/40 duty<br>cycle|
|FGPIOUT3<br>~~ee~~<br>~~ee~~<br>~~ee~~|GPIO Fout; 3.3 VVDD5.5 V<br>Slow-Strong mode<br>~~ee ~~<br>~~ee~~<br>~~ee~~|–<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|–<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|7<br> ~~ee~~<br>~~ee~~<br>~~ee~~|MHz<br>~~ee~~<br>~~ee~~<br>~~ee~~|90/10%, 25 pF load, 60/40 duty<br>cycle|
|FGPIOUT4<br>~~ee~~<br>~~ee~~<br>~~a~~|GPIO Fout; 1.7 VVDD3.3 V<br>Slow-Strong mode<br>~~ee ~~<br>~~ee~~<br>~~es~~|–<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|–<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|3.5<br> ~~ee~~<br>~~ee~~<br>~~ee~~|MHz<br>~~ee~~<br>~~ee~~<br>~~ee~~|90/10%, 25 pF load, 60/40 duty<br>cycle|
|FGPIOIN<br>~~ee~~<br>~~a~~|GPIO input operating frequency<br>1.71 VVDD5.5 V<br>~~ee ~~<br>~~es~~|–<br> ~~ee ~~<br>~~ee~~|–<br> ~~ee ~~<br>~~ee~~|48<br> ~~ee~~<br>~~ee~~|MHz<br>~~ee~~<br>~~ee~~|90/10% VIO|



**Table 16.  OVT GPIO DC Specifications (P5_0 and P5_1 Only)** 

**Table 17.  OVT GPIO AC Specifications (P5_0 and P5_1 Only)** 

|**Parameter**<br>**Description**<br>**Min**<br>**Typ**<br>**Max**<br>**Units**<br>TRISE_OVFS<br>Output rise time in Fast-Strong mode<br>1.5<br>–<br>12<br>ns<br>TFALL_OVFS<br>Output fall time in Fast-Strong mode<br>1.5<br>–<br>12<br>ns<br>TRISESS<br>Output rise time in Slow-Strong mode<br>10<br>–<br>60<br>ns<br>TFALLSS<br>Output fall time in Slow-Strong mode<br>10<br>–<br>60<br>ns<br>FGPIOUT1<br>GPIO FOUT; 3.3 VVDD5.5 V<br>Fast-Strong mode<br>–<br>–<br>24<br>MHz<br>FGPIOUT2<br>GPIO FOUT; 1.71 VVDD3.3 V<br>Fast-Strong mode<br>–<br>–<br>16<br>MHz<br>~~POE~~<br>~~es~~<br>~~Rs I rs~~<br>~~Ts~~<br>~~ee~~<br>~~rs rs ss~~<br>~~a~~<br>~~ee ee~~<br>~~ee~~<br>~~a~~<br>~~ee ee~~<br>~~ee~~<br>~~a~~<br>~~ee ee~~<br>~~ee~~<br>~~ee~~<br>~~ee ee~~<br>~~ee~~|**Parameter**<br>**Description**<br>**Min**<br>**Typ**<br>**Max**<br>**Units**<br>TRISE_OVFS<br>Output rise time in Fast-Strong mode<br>1.5<br>–<br>12<br>ns<br>TFALL_OVFS<br>Output fall time in Fast-Strong mode<br>1.5<br>–<br>12<br>ns<br>TRISESS<br>Output rise time in Slow-Strong mode<br>10<br>–<br>60<br>ns<br>TFALLSS<br>Output fall time in Slow-Strong mode<br>10<br>–<br>60<br>ns<br>FGPIOUT1<br>GPIO FOUT; 3.3 VVDD5.5 V<br>Fast-Strong mode<br>–<br>–<br>24<br>MHz<br>FGPIOUT2<br>GPIO FOUT; 1.71 VVDD3.3 V<br>Fast-Strong mode<br>–<br>–<br>16<br>MHz<br>~~POE~~<br>~~es~~<br>~~Rs I rs~~<br>~~Ts~~<br>~~ee~~<br>~~rs rs ss~~<br>~~a~~<br>~~ee ee~~<br>~~ee~~<br>~~a~~<br>~~ee ee~~<br>~~ee~~<br>~~a~~<br>~~ee ee~~<br>~~ee~~<br>~~ee~~<br>~~ee ee~~<br>~~ee~~|**Details/Conditions**<br>25-pF load, 10%–90%, VDD= 3.3 V<br>25-pF load, 10%–90%, VDD= 3.3 V<br>25 pF load, 10%-90%,<br>VDD= 3.3 V<br>25 pF load, 10%-90%,<br>VDD= 3.3 V<br>90/10%, 25 pF load, 60/40 duty<br>cycle<br>90/10%, 25 pF load, 60/40 duty<br>cycle|
|---|---|---|
|**XRES**|||
|**Table 18.  XRES DC Specifications**|||
|**Parameter**<br>**Description**<br>**Min**<br>**Typ**<br>**Max**<br>**Units**<br>**Details/Conditions**<br>VIH<br>Input voltage HIGH threshold<br>0.7 × VDDD<br>–<br>–<br>V<br>CMOS input<br>VIL<br>Input voltage LOW threshold<br>–<br>–<br>0.3 × VDDD<br>V<br>CMOS input<br>RPULLUP<br>Pull-up resistor<br>3.5<br>5.6<br>8.5<br>k<br>–<br>CIN<br>Input capacitance<br>–<br>3<br>–<br>pF<br>–<br>~~a~~<br>~~es en~~<br>~~rs te~~<br>~~es~~<br>~~nD Rt~~<br>~~I~~<br>~~es~~<br>~~ITD I~~<br>~~(I~~<br>~~a ey~~<br>~~ns ts~~<br>~~es~~<br>~~nD RU~~<br>~~I I~~|||
|VHYSXRES<br>Input voltage hysteresis<br>–<br>100<br>–|mV|–|
|IDIODE<br>Current through protection diode to<br>VDD/VSS<br>–<br>–<br>100<br>A<br>–<br>~~a ee~~<br>~~eeee~~|||



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## **Table 19.  XRES AC Specifications** 

|**Parameter**|**Description**||**Min**||**Typ**||**Max**||**Units**||**Details/Conditions**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|TRESETWIDTH|Reset pulse width||1||–||–||s||–|
|_Temperature Sensor_||||||||||||
|**Table 20.  Temperature Sensor Specifications**||||||||||||
|**Parameter**|**Description**||**Min**||**Typ**||**Max**||**Units**||**Details/Conditions**|
|TSENSACC|Temperature-sensor accuracy||–5||±1||5||°C||–40 °C to +85 °C|



_Temperature Sensor_ 

## **Table 20.  Temperature Sensor Specifications** 

_SAR ADC_ 

## **Table 21.  SAR ADC DC Specifications** 

|**Parameter**<br>~~ee~~<br>~~es~~|**Description**<br>~~rt~~<br>~~nD~~|**Min**<br>~~rt~~<br>~~ID~~|**Typ**<br>~~tt~~<br>~~ID~~|**Max**<br>~~nD~~<br>~~(OD~~|**Units**<br>~~(OD~~|**Details/Conditions**|
|---|---|---|---|---|---|---|
|A_RES<br>~~ee~~<br>~~es~~<br>~~es~~|Resolution<br>~~rt~~<br>~~nD~~<br>~~nD~~|–<br>~~rt~~<br>~~ID~~<br>~~I)~~|–<br>~~tt~~<br>~~ID~~<br>~~I)~~|12<br>~~nD~~<br>~~(OD~~<br>~~(OO~~|bits<br>~~(OD~~<br>~~(OO~~||
|A_CHNIS_S<br>~~es~~<br>~~es~~<br>~~a~~|Number of channels - single-ended<br>~~nD ~~<br>~~nD~~|–<br> ~~ID~~<br>~~I)~~|–<br>~~ID~~<br>~~I)~~<br>~~ee~~|6<br>~~(OD~~<br>~~(OO~~<br>~~ee~~|~~(OD~~<br>~~(OO~~<br>~~ee~~|6 full-speed[11]<br>~~ee~~|
|A-CHNKS_D<br>~~es~~<br>~~a ee~~<br>~~a~~<br>~~es~~|Number of channels - differential<br>~~nD~~<br>~~ee~~<br>~~nD~~|–<br>~~I)~~<br>~~ee~~<br>~~nD~~|–<br>~~I)~~<br>~~ee~~<br>~~ee~~<br>~~nD~~|3<br>~~(OO~~<br>~~ee~~<br>~~ee~~<br>~~(OO~~|~~(OO~~<br>~~ee~~<br>~~ee~~<br>~~(OO~~|Diff inputs use<br>neighboring I/O[11]<br>~~ee~~<br>~~ee~~|
|A-MONO<br>~~a~~<br>~~es~~<br>~~es~~|Monotonicity<br>~~nD~~<br>~~ry~~|–<br>~~nD~~<br>~~SD~~|–<br>~~ee~~<br>~~nD~~<br>~~SD~~|–<br>~~ee~~<br>~~(OO~~<br>~~(Os~~|~~ee~~<br>~~(OO~~<br>~~(Os~~|Yes<br>~~ee~~|
|A_GAINERR<br>~~a~~<br>~~es~~<br>~~es~~<br>~~ee~~|Gain error<br>~~nD~~<br>~~ry~~<br>~~nD~~|–<br>~~nD~~<br>~~SD~~<br>~~I)~~|–<br>~~ee~~<br>~~nD~~<br>~~SD~~<br>~~I)~~|±0.1<br>~~ee~~<br>~~(OO~~<br>~~(Os~~<br>~~(OO~~|%<br>~~ee~~<br>~~(OO~~<br>~~(Os~~<br>~~(OO~~|With external reference<br>~~ee~~|
|A_OFFSET<br>~~es~~<br>~~es~~<br>~~ee~~<br>~~es~~|Input offset voltage<br>~~nD~~<br>~~ry~~<br>~~nD~~<br>~~nts~~<br>|–<br>~~nD~~<br>~~SD~~<br>~~I)~~<br>~~rs~~<br>|–<br>~~nD~~<br>~~SD~~<br>~~I)~~<br>~~t~~~~**s**~~<br>|2<br>~~(OO~~<br>~~(Os~~<br>~~(OO~~<br>~~Us~~|mV<br>~~(OO~~<br>~~(Os~~<br>~~(OO~~|Measured with 1-V VREF|
|A_ISAR<br>~~es~~<br>~~ee~~<br>~~es~~<br>~~es~~|Current consumption<br>~~ry ~~<br>~~nD~~<br>~~nts~~<br>|–<br> ~~SD~~<br>~~I)~~<br>~~rs~~<br><br>~~tt)~~|–<br>~~SD~~<br>~~I)~~<br>~~t~~~~**s**~~<br><br>~~tt)~~|1<br>~~(Os~~<br>~~(OO~~<br>~~Us~~<br>~~nD~~|mA<br>~~(Os~~<br>~~(OO~~<br>~~OU~~||
|A_VINS<br>~~ee~~<br>~~es~~<br>~~es~~<br>~~a~~|Input voltage range - single-ended<br>~~nD ~~<br>~~nts~~<br>~~e~~<br>~~rs~~|VSS<br> ~~I)~~<br>~~rs~~<br>~~e~~<br>~~tt)~~<br>~~Dn~~|–<br>~~I)~~<br>~~t~~~~**s**~~<br>~~e~~<br>~~tt)~~<br>~~Dn~~|VDDA<br>~~(OO~~<br>~~Us~~<br>~~nD~~<br>~~Dn~~|V<br>~~(OO~~<br>~~OU~~<br>~~(OO~~||
|A_VIND<br>~~es~~<br>~~es~~<br>~~a~~<br>~~es~~|Input voltage range - differential<br>~~nts ~~<br><br>~~rs~~<br>~~nD~~<br>|VSS<br> ~~rs ~~<br><br>~~tt)~~<br>~~Dn~~<br>~~nD~~<br>|–<br> ~~t~~~~**s** ~~<br><br>~~tt)~~<br>~~Dn~~<br>~~nD~~<br>|VDDA<br> ~~Us~~<br>~~nD~~<br>~~Dn~~<br>~~(OO~~<br>|V<br>~~OU~~<br>~~(OO~~<br>~~(OO~~<br>||
|A_INRES<br>~~es~~<br>~~a~~<br>~~es~~<br>~~es~~|Input resistance<br>~~rs~~<br>~~nD~~<br>|–<br>~~tt)~~<br>~~Dn~~<br>~~nD~~<br><br>~~tt)~~|–<br>~~tt)~~<br>~~Dn~~<br>~~nD~~<br><br>~~tt)~~|2.2<br>~~nD~~<br>~~Dn~~<br>~~(OO~~<br><br>~~nD~~|k<br>~~OU~~<br>~~(OO~~<br>~~(OO~~<br><br>~~OU~~||
|A_INCAP<br>~~a~~<br>~~es~~<br>~~es~~|Input capacitance<br>~~rs ~~<br>~~nD~~<br>~~es~~<br>~~Dn~~|–<br> ~~Dn~~<br>~~nD~~<br>~~es~~<br>~~tt)~~<br>~~Dn~~|–<br>~~Dn~~<br>~~nD~~<br>~~es~~<br>~~tt)~~<br>~~nD~~|10<br>~~Dn ~~<br>~~(OO~~<br>~~es~~<br>~~nD~~<br>~~(Os~~|pF<br> ~~(OO~~<br>~~(OO~~<br>~~es~~<br>~~OU~~<br>~~(Os~~|~~es~~|
|VREFSAR<br>~~es~~<br>~~es~~|Trimmed internal reference to SAR<br>~~nD~~<br><br>~~Dn~~|–1<br>~~nD~~<br><br>~~tt)~~<br>~~Dn~~|–<br>~~nD~~<br><br>~~tt)~~<br>~~nD~~|1<br>~~(OO~~<br><br>~~nD~~<br>~~(Os~~|%<br>~~(OO~~<br><br>~~OU~~<br>~~(Os~~|Percentage of Vbg (1.024 V)<br>|



## **Note** 

> 11. A maximum of six single-ended ADC Channels can be accomplished only if the AMUX Buses are not being used for other funcitonality (e.g. CapSense). If the AMUX Buses are being used for other functions, then the maximum number of single-ended ADC channels is four. Similarly, if the AMUX Buses are being used for other functionality, then the maximum number of differential ADC channels is two. 

Document Number: 002-15631 Rev.*D 

Page 20 of 40 

**CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11** 

**Table 22.  SAR ADC AC Specifications** 

|**Parameter**<br>~~ee~~<br>~~a~~|**Description**<br>~~tt~~|**Min**<br>~~tt~~<br>~~ee~~|**Typ**<br>~~ts~~<br>~~ee~~|**Max**<br>~~I~~<br>~~ee~~|**Units**<br>~~ee~~|**Details/Conditions**<br>~~ee~~|
|---|---|---|---|---|---|---|
|A_PSRR<br>~~ee~~<br>~~a ee~~<br>~~a~~<br>~~a~~|Power-supply rejection ratio<br>~~tt~~<br>~~ee~~<br>~~rs~~|70<br>~~tt~~<br>~~ee~~<br>~~ee~~<br>~~rr~~|–<br>~~ts ~~<br>~~ee~~<br>~~ee~~<br>~~rs~~|–<br> ~~I~~<br>~~ee~~<br>~~ee~~<br>~~ts~~|dB<br>~~ee~~<br>~~ee~~|Measured at 1-V<br>reference<br>~~ee~~<br>~~ee~~|
|A_CMRR<br>~~a~~<br>~~a~~<br>~~ee~~|Common-mode rejection ratio<br>~~rs~~<br>~~I~~<br>|66<br>~~ee~~<br>~~rr~~<br>~~I~~<br>|–<br>~~ee~~<br>~~rs~~<br>~~Ss~~<br>|–<br>~~ee~~<br>~~ts~~|dB<br>~~ee~~|~~ee~~|
|A_SAMP<br>~~a~~<br>~~a~~<br>~~ee~~<br>~~a~~|Sample rate<br>~~rs ~~<br>~~I~~<br>~~ee~~|–<br>~~ee ~~<br> ~~rr ~~<br>~~I~~<br>~~ee~~|–<br> ~~ee~~<br> ~~rs ~~<br>~~Ss~~<br>~~ee~~|1<br>~~ee~~<br> ~~ts~~|Msps<br>~~ee~~|~~ee~~|
|Fsarintref<br>~~ee~~<br>~~a~~<br>~~a~~|SAR operating speed without external ref.<br>bypass<br>~~I~~<br>~~ee~~<br>~~nn~~|–<br>~~I~~<br>~~ee~~<br>~~I~~|–<br>~~Ss~~<br>~~ee~~<br>~~ts~~|100|Ksps|12-bit resolution|
|A_SNR<br>~~ee ~~<br>~~a~~<br>~~a~~<br>~~ee~~|Signal-to-noise ratio (SNR)<br>~~I~~<br> ~~ee ~~<br>~~nn~~<br>~~rs~~<br>|65<br>~~I ~~<br> ~~ee~~<br>~~I~~<br>~~rr~~|–<br> ~~Ss~~<br>~~ee~~<br>~~ts~~<br>~~rs~~|–<br>~~ts~~|dB|FIN= 10 kHz|
|A_BW<br>~~a~~<br>~~ee~~<br>~~ee~~|Input bandwidth without aliasing<br>~~nn~~<br>~~rs~~<br>~~ee~~<br>|–<br>~~I~~<br>~~rr~~|–<br>~~ts~~<br>~~rs~~|A_SAMP/2<br>~~ts~~|kHz||
|A_INL<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|Integral nonlinearity. VDD= 1.71 V to 5.5 V,<br>1 Msps<br>~~nn ~~<br>~~rs~~<br>~~ee~~<br>~~ee~~<br>|–1.7<br> ~~I ~~<br>~~rr~~|–<br> ~~ts~~<br>~~rs~~|2<br>~~ts~~|LSB|VREF= 1 V to VDD|
|A_INL<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|Integral nonlinearity. VDDD= 1.71 V to 3.6 V,<br>1 Msps<br>~~rs ~~<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>|–1.5<br> ~~rr ~~|–<br> ~~rs ~~|1.7<br> ~~ts~~|LSB|VREF= 1.71 V to VDD|
|A_INL<br> <br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|Integral nonlinearity. VDD= 1.71 V to 5.5 V,<br>500 Ksps<br> ~~ee~~<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>|–1.5|–|1.7|LSB|VREF= 1 V to VDD|
|A_dnl<br> <br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|Differential nonlinearity. VDD= 1.71 V to<br>5.5 V, 1 Msps<br> ~~ee~~<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>|–1|–|2.2|LSB|VREF= 1 V to VDD|
|A_DNL<br> <br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|Differential nonlinearity. VDD= 1.71 V to<br>3.6 V, 1 Msps<br> ~~ee~~<br> ~~ee~~<br>~~ee~~<br>~~ee~~|–1|–|2|LSB|VREF= 1.71 V to VDD|
|A_DNL<br> <br>~~ee ~~<br>~~ee~~<br>~~ee~~|Differential nonlinearity. VDD= 1.71 V to<br>5.5 V, 500 Ksps<br> ~~ee~~<br> ~~ee~~<br>~~ee~~<br>~~I~~|–1<br>~~I~~|–<br>~~ts~~|2.2|LSB|VREF= 1 V to VDD|
|A_THD<br> <br>~~ee ~~<br>~~ee~~|Total harmonic distortion<br> ~~ee~~<br> ~~ee~~<br>~~I~~|–<br>~~I~~|–<br>~~ts~~|–65|dB|FIN= 10 kHz|



|**Parameter**<br>~~ee~~<br>~~ee~~|**Description**<br>~~re~~<br>~~nD~~|**Min**<br>~~ts~~<br>~~rs~~|**Typ**<br>~~rts~~<br>~~rs~~|**Max**<br>~~rns~~<br>~~I~~|**Units**<br>~~I~~|**Details/Conditions**|
|---|---|---|---|---|---|---|
|VCSD<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~es~~|Voltage range of operation<br>~~re~~<br>~~nD~~<br>~~RD~~|1.71<br>~~ts~~<br>~~rs~~<br>~~RD~~<br>~~I~~|–<br>~~rts~~<br>~~rs~~<br>~~RD~~<br>~~I~~|5.5<br>~~rns ~~<br>~~I~~<br>~~RD~~|V<br> ~~I~~<br>~~RD~~|–<br>~~RD~~|
|IDAC1<br>~~ee~~<br>~~ee~~<br>~~es~~<br>~~ee~~|DNL for 8-bit resolution<br>~~nD~~<br>~~RD~~<br>~~Irn~~|–1<br>~~rs~~<br>~~RD~~<br>~~I~~<br>~~I~~|–<br>~~rs ~~<br>~~RD~~<br>~~I~~<br>~~ts~~|1<br> ~~I~~<br>~~RD~~|LSB<br>~~RD~~|–<br>~~RD~~|
|IDAC1<br>~~ee~~<br>~~es~~<br>~~ee~~<br>~~ft~~|INL for 8-bit resolution<br>~~RD~~<br>~~Irn~~<br>~~ID~~<br>~~ft~~|–3<br>~~RD~~<br>~~I~~<br>~~I~~<br>~~IS~~|–<br>~~RD~~<br>~~I~~<br>~~ts~~<br>~~rs~~|3<br>~~RD~~|LSB<br>~~RD~~|–<br>~~RD~~|
|IDAC2<br>~~es~~<br>~~ee~~<br>~~ft~~|DNL for 7-bit resolution<br>~~Irn~~<br>~~ID~~<br>~~ft~~|–1<br>~~I ~~<br>~~I~~<br>~~IS~~|–<br> ~~I~~<br>~~ts~~<br>~~rs~~|1|LSB|–|
|IDAC2<br>~~ee~~<br>~~ft~~|INL for 7-bit resolution<br>~~Irn ~~<br>~~ID~~<br>~~ft~~<br>~~Tiere~~|–3<br> ~~I ~~<br>~~IS~~<br>~~Tiere~~|–<br> ~~ts~~<br>~~rs~~<br>~~Tiere~~|3<br>~~Tiere~~|LSB<br>~~Tiere~~|–<br>~~Tiere~~|
|SNR<br>~~ft~~|Ratio of counts of finger to noise<br>~~ID~~<br>~~ft~~<br>~~Tiere~~|5<br>~~IS~~<br>~~Tiere~~|–<br>~~rs~~<br>~~Tiere~~|–<br>~~Tiere~~|Ratio<br>~~Tiere~~|Capacitance range of<br>9 pF to 35 pF, 0.1-pF<br>sensitivity. Radio is not<br>operating during the<br>scan<br>~~Tiere~~|
|IDAC1_CRT1<br>~~ft~~|Output current of IDAC1 (8 bits) in High<br>range<br>~~ID ~~<br>~~ft~~<br>~~Tiere~~|–<br> ~~IS ~~<br>~~Tiere~~|612<br> ~~rs~~<br>~~Tiere~~|–<br>~~Tiere~~|A<br>~~Tiere~~|–<br>~~Tiere~~|
|IDAC1_CRT2|Output current of IDAC1 (8 bits) in Low<br>range|–|306|–|A|–|
|IDAC2_CRT1|Output current of IDAC2 (7 bits) in High<br>range|–|305|–|A|–|
|IDAC2_CRT2|Output current of IDAC2 (7 bits) in Low<br>range|–|153|–|A|–|



Document Number: 002-15631 Rev.*D 

Page 21 of 40 

**CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11** 

## **Digital Peripherals** 

_Timer_ 

## **Table 23.  Timer DC Specifications** 

**==> picture [523 x 441] intentionally omitted <==**

**----- Start of picture text -----**<br>
|||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Parameter|Description|Min|Typ|Max|Units|Details/Conditions|
|ITIM1|Block current consumption at 3 MHz|–|–|42|A|16-bit timer|
|ITIM2|Block current consumption at 12 MHz|–|–|130|A|16-bit timer|
|ITIM3|Block current consumption at 48 MHz|–|–|535|A|16-bit timer|
|Table 24.  Timer AC Specifications|
|Pf|Parameter|Description|Min|Typ|Max|Units|Details/Conditions|
|TTIMFREQ|Operating frequency|FCLK|–|48|MHz|
|esrs|
|TCAPWINT|Capture pulse width (internal)|2 × TCLK|–|–|ns|
|esns|
|TCAPWEXT|Capture pulse width (external)|2 × TCLK|–|–|ns|
|essD|
|TTIMRES|Timer resolution|TCLK|–|–|ns|
|es|I|
|TTENWIDINT|Enable pulse width (internal)|2 × TCLK|–|–|ns|
|essDns|
|TTENWIDEXT|Enable pulse width (external)|2 × TCLK|–|–|ns|
|es|I|
|TTIMRESWINT|Reset pulse width (internal)|2 × TCLK|–|–|ns|
|essDns|
|TTIMRESEXT|Reset pulse width (external)|2 × TCLK|–|–|ns|
|esrsOU|II|
|Counter|
|Table 25.  Counter DC Specifications|
|Parameter|Description|Min|Typ|Max|Units|Details/Conditions|
|ICTR1|Block current consumption at 3 MHz|–|–|42|A|16-bit counter|
|ICTR2|Block current consumption at 12 MHz|–|–|130|A|16-bit counter|
|ICTR3|Block current consumption at 48 MHz|–|–|535|A|16-bit counter|
|Table 26.  Counter AC Specifications|
|TD|Parameter|Description|Min|Typ|Max|Units|Details/Conditions|
|TCTRFREQ|Operating frequency|FCLK|–|48|MHz|–|
|es|(ON|(OD|(OO|(OO|
|TCTRPWINT|Capture pulse width (internal)|2 × TCLK|–|–|ns|–|
|ee|nD|(Os|
|TCTRPWEXT|Capture pulse width (external)|2 × TCLK|–|–|ns|–|
|es|rr|I|DD|I|
|TCTRES|Counter Resolution|TCLK|–|–|ns|–|
|ee|nD|
|TCENWIDINT|Enable pulse width (internal)|2 × TCLK|–|–|ns|–|
|es|rr|I|DD|I|
|TCENWIDEXT|Enable pulse width (external)|2 × TCLK|–|–|ns|–|
|ee|nD|
|TCTRRESWINT|Reset pulse width (internal)|2 × TCLK|–|–|ns|–|
|es|rr|I|DD|I|
|a|TCTRRESWEXT|ns|Reset pulse width (external)|nD|2 × T|ts|CLK|(rs|–|ID|–|ns|–|

**----- End of picture text -----**<br>


**Table 24.  Timer AC Specifications** 

Document Number: 002-15631 Rev.*D 

Page 22 of 40 

**CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11** 

## _Pulse Width Modulation (PWM)_ 

## **Table 27.  PWM DC Specifications** 

|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Units**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|IPWM1|Block current consumption at 3 MHz|–|–|42|A|16-bit PWM|
|IPWM2|Block current consumption at 12 MHz|–|–|130|A|16-bit PWM|
|IPWM3|Block current consumption at 48 MHz|–|–|535|A|16-bit PWM|



## **Table 28.  PWM AC Specifications** 

|**Parameter**<br>~~a~~|**Description**<br>~~rr~~|**Min**<br>~~rs~~|**Typ**<br>~~rs~~|**Max**|**Units**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|TPWMFREQ<br>~~a~~<br>~~Pee~~|Operating frequency<br>~~rr~~<br>~~Pee~~|FCLK<br>~~rs~~<br>~~Pee~~|–<br>~~rs~~<br>~~Pee~~|48<br>~~Pee~~|MHz<br>~~Pee~~|–<br>~~Pee~~|
|TPWMPWINT<br>~~Pee~~<br>~~es~~|Pulse width (internal)<br>~~Pee~~<br>~~rs~~|2 × TCLK<br>~~Pee~~<br>~~nD~~|–<br>~~Pee~~<br>~~OD~~|–<br>~~Pee~~<br>~~OD~~|ns<br>~~Pee~~<br>~~I~~|–<br>~~Pee~~|
|TPWMEXT<br>~~es~~<br>~~es~~|Pulse width (external)<br>~~rs~~<br>~~rs~~|2 × TCLK<br>~~nD~~<br>~~DD~~|–<br>~~OD~~<br>~~DD~~|–<br>~~OD~~<br>~~OO~~|ns<br>~~I~~|–|
|TPWMKILLINT<br>~~es~~<br>~~es~~|Kill pulse width (internal)<br>~~rs~~<br>~~rs~~|2 × TCLK<br>~~nD ~~<br>~~DD~~|–<br> ~~OD~~<br>~~DD~~|–<br>~~OD ~~<br>~~OO~~|ns<br> ~~I~~|–|
|TPWMKILLEXT<br>~~es~~<br>~~Pee~~<br>~~es~~|Kill pulse width (external)<br>~~rs ~~<br>~~Pee~~<br>~~rs~~|2 × TCLK<br> ~~DD~~<br>~~Pee~~<br>~~nD~~|–<br>~~DD~~<br>~~Pee~~<br>~~OD~~|–<br>~~OO~~<br>~~Pee~~<br>~~OD~~|ns<br>~~Pee~~<br>~~I~~|–<br>~~Pee~~|
|TPWMEINT<br>~~es~~<br>~~es~~|Enable pulse width (internal)<br>~~rs~~<br>~~rs~~|2 × TCLK<br>~~nD~~<br>~~DD~~|–<br>~~OD~~<br>~~DD~~|–<br>~~OD~~<br>~~OO~~|ns<br>~~I~~|–|
|TPWMENEXT<br>~~es~~<br>~~es~~|Enable pulse width (external)<br>~~rs~~<br>~~rs~~|2 × TCLK<br>~~nD ~~<br>~~DD~~|–<br> ~~OD~~<br>~~DD~~|–<br>~~OD ~~<br>~~OO~~|ns<br> ~~I~~|–|
|TPWMRESWINT<br>~~es~~<br>~~Pee~~<br>~~es~~|Reset pulse width (internal)<br>~~rs ~~<br>~~Pee~~<br>~~rs~~|2 × TCLK<br> ~~DD~~<br>~~Pee~~<br>~~nD~~|–<br>~~DD~~<br>~~Pee~~<br>~~(RD~~|–<br>~~OO~~<br>~~Pee~~<br>~~(OOD~~|ns<br>~~Pee~~<br>~~I~~|–<br>~~Pee~~|
|TPWMRESWEXT<br>~~es~~|Reset pulse width (external)<br>~~rs~~|2 × TCLK<br>~~nD~~|–<br>~~(RD~~|–<br>~~(OOD~~|ns<br>~~I~~|–|



## _LCD Direct Drive_ 

## **Table 29.  LCD Direct Drive DC Specifications** 

|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Units**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|ILCDLOW|Operating current in low-power mode|–|17.5|–|A|16 × 4 small segment<br>displayat 50 Hz|
|CLCDCAP|LCD capacitance per segment/common<br>driver|–|500|5000|pF|–|
|LCDOFFSET|Long-term segment offset|–|20|–|mV|–|
|ILCDOP1|LCD system operating current, VBIAS= 5 V|–|2|–|mA|32 × 4 segments. 50 Hz at<br>25 °C|
|ILCDOP2|LCD system operating current, VBIAS= 3.3 V|–|2|–|mA|32 × 4 segments<br>50 Hz at 25 °C|



**Table 30.  LCD Direct Drive AC Specifications** 

|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Units**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|FLCD|LCD frame rate|10|50|150|Hz|–|



Document Number: 002-15631 Rev.*D 

Page 23 of 40 

**CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11** 

## **Serial Communication** 

## **Table 31.  Fixed I[2] C DC Specifications** 

|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Units**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|II2C1|Block current consumption at 100 kHz|–|–|50|A|–|
|II2C2|Block current consumption at 400 kHz|–|–|155|A|–|
|II2C3|Block current consumption at 1 Mbps|–|–|390|A|–|
|II2C4|I2C enabled in Deep-Sleep mode|–|–|1.4|A|–|
|**Table 32.  Fixed I2C AC Specifications**|||||||
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Units**|**Details/Conditions**|
|FI2C1|Bit rate|–|–|400|kHz||
|**Table 33.  Fixed UART DC Specifications**|||||||
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Units**|**Details/Conditions**|
|IUART1|Block current consumption at 100 kbps|–|–|55|A|–|
|IUART2|Block current consumption at 1000 kbps|–|–|312|A|–|



## **Table 32.  Fixed I[2] C AC Specifications** 

## **Table 33.  Fixed UART DC Specifications** 

## **Table 34.  Fixed UART AC Specifications** 

|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Units**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|FUART|Bit rate|–|–|1|Mbps|–|
|**Table 35.  Fixed SPI DC Specifications**|||||||
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Units**|**Details/Conditions**|
|ISPI1|Block current consumption at 1 Mbps|–|–|360|A|–|
|ISPI2|Block current consumption at 4 Mbps|–|–|560|A|–|
|ISPI3|Block current consumption at 8 Mbps|–|–|600|A|–|



## **Table 35.  Fixed SPI DC Specifications** 

## **Table 36.  Fixed SPI AC Specifications** 

|**Parameter**|**Description**|**Min**|**Typ**||**Max**|**Units**|**Details/Conditions**|
|---|---|---|---|---|---|---|---|
|FSPI|SPI operating frequency (master; 6x over<br>sampling)|–|–||8|MHz|–|
|**Table 37.  Fixed SPI Master Mode AC Specifications**||||||||
|**Parameter**|**Description**|**Min**|**Typ**||**Max**|**Units**|**Details/Conditions**|
|TDMO|MOSI valid after SCLK driving edge|–|–||18|ns|–|
|TDSI|MISO valid before SCLK capturing edge<br>Full clock, late MISO samplingused|20|–||–|ns|Full clock, late MISO sampling|
|THMO|Previous MOSI data hold time|0|–||–|ns|Referred to Slave capturing edge|



## **Table 37.  Fixed SPI Master Mode AC Specifications** 

## **Table 38.  Fixed SPI Slave Mode AC Specifications** 

|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Units**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|TDMI|MOSI valid before SCLK capturing edge|40|–|–|ns||
|TDSO|MISO valid after SCLK driving edge|–|–|42 + 3 × TCPU|ns||
|TDSO_ext|MISO Valid after SCLK driving edge in<br>external clock mode. VDD< 3.0 V|–|–|50|ns||
|THSO|Previous MISO data hold time|0|–|–|ns||
|TSSELSCK|SSEL valid to first SCK valid edge|100|–|–|ns||



Document Number: 002-15631 Rev.*D 

Page 24 of 40 

**CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11** 

## **Memory** 

## **Table 39.  Flash DC Specifications** 

|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Units**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|VPE|Erase and program voltage|1.71|–|5.5|V|–|
|TWS48|Number of Wait states at 32–48 MHz|2|–|–||CPU execution from flash|
|TWS32|Number of Wait states at 16–32 MHz|1|–|–||CPU execution from flash|
|TWS16|Number of Wait states for 0–16 MHz|0|–|–||CPU execution from flash|



## **Table 40.  Flash AC Specifications** 

|**Parameter**<br>~~ee~~<br>~~ee~~|**Description**<br>~~rs~~<br>~~(RR~~|**Min**<br>~~rs~~<br>~~(RR~~|**Typ**<br>~~rs~~<br>~~(OU~~|**Max**<br>~~I~~<br>~~(OU~~|**Units**<br>~~(OU~~|**Details/Conditions**|
|---|---|---|---|---|---|---|
|TROWWRITE<br>[12]<br>~~ee~~<br>~~ee~~<br>~~ee~~|Row (block) write time (erase and program)<br>~~rs~~<br>~~(RR~~<br>~~I~~|–<br>~~rs~~<br>~~(RR~~<br>~~I~~|–<br>~~rs ~~<br>~~(OU~~<br>~~ns~~|20<br> ~~I~~<br>~~(OU~~|ms<br>~~(OU~~|Row (block) = 256 bytes|
|TROWERASE<br>[12]<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|Row erase time<br>~~(RR~~<br>~~I~~<br>~~Rs~~<br>|–<br>~~(RR~~<br>~~I~~<br>~~Rs~~<br>~~(ID~~<br>|–<br>~~(OU~~<br>~~ns~~<br>~~Rs~~<br>~~(OUD~~<br>|13<br>~~(OU~~<br>~~Rs~~<br>~~(OUD~~<br>|ms<br>~~(OU~~<br>~~Rs~~<br>|–<br>~~Rs~~<br>|
|TROWPROGRAM<br>[12]Row program time after erase<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|Row program time after erase<br>~~I~~<br>~~Rs~~<br>|–<br>~~I~~<br>~~Rs~~<br>~~(ID~~<br><br>~~GD~~|–<br>~~ns~~<br>~~Rs~~<br>~~(OUD~~<br><br>~~OR~~|7<br>~~Rs~~<br>~~(OUD~~<br><br>~~I~~|ms<br>~~Rs~~<br><br>~~(OO~~|–<br>~~Rs~~<br>|
|TBULKERASE<br>[12]<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|Bulk erase time (256 KB)<br>~~Rs~~<br>~~es~~<br>~~I~~<br>|–<br>~~Rs~~<br>~~(ID~~<br>~~es~~<br>~~GD~~<br>~~I~~<br>|–<br>~~Rs~~<br>~~(OUD~~<br>~~es~~<br>~~OR~~<br>~~ns~~<br>|35<br>~~Rs~~<br>~~(OUD~~<br>~~es~~<br>~~I~~<br>|ms<br>~~Rs~~<br>~~es~~<br>~~(OO~~<br>|–<br>~~Rs~~<br>~~es~~<br>|
|TDEVPROG<br>[12]<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|Total device program time<br><br>~~I~~<br><br>|–<br>~~(ID~~<br><br>~~GD~~<br>~~I~~<br><br>~~(ID~~<br>|–<br>~~(OUD~~<br><br>~~OR~~<br>~~ns~~<br><br>~~(OUD~~<br>|25<br>~~(OUD~~<br><br>~~I~~<br><br>~~(OUD~~<br>|seconds<br><br>~~(OO~~<br><br>|–<br><br><br>|
|FEND<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~a~~|Flash endurance<br>~~I~~<br>~~Rs~~<br>|100 K<br>~~GD ~~<br>~~I~~<br>~~Rs~~<br>~~(ID~~<br><br>~~GD~~|–<br> ~~OR ~~<br>~~ns~~<br>~~Rs~~<br>~~(OUD~~<br><br>~~OR~~|–<br> ~~I ~~<br>~~Rs~~<br>~~(OUD~~<br><br>~~I~~|cycles<br> ~~(OO~~<br>~~Rs~~<br><br>~~(OO~~|–<br>~~Rs~~<br>|
|FRET<br>~~ee~~<br>~~ee~~<br>~~a~~|Flash retention. TA 55 °C, 100 K P/E cycles<br>~~I~~<br><br>~~es~~<br>~~rn~~|20<br>~~I~~<br><br>~~(ID~~<br>~~es~~<br>~~GD~~<br>~~ID ts~~|–<br>~~ns~~<br><br>~~(OUD~~<br>~~es~~<br>~~OR~~<br>~~ts UI~~|–<br><br>~~(OUD~~<br>~~es~~<br>~~I~~<br>~~UI~~|years<br><br>~~es~~<br>~~(OO~~|–<br><br>~~es~~|
|FRET2<br>~~ee~~<br>~~a~~|Flash retention. TA 85 °C, 10 K P/E cycles<br><br>~~rn~~|10<br>~~(ID~~<br><br>~~GD ~~<br>~~ID ts~~|–<br>~~(OUD~~<br><br> ~~OR ~~<br>~~ts UI~~|–<br>~~(OUD~~<br><br> ~~I ~~<br>~~UI~~|years<br><br> ~~(OO~~|–<br>|



## **System Resources** 

_Power-on-Reset (POR)_ 

## **Table 41.  POR DC Specifications** 

|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Units**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|VRISEIPOR|Rising trip voltage|0.80|–|1.45|V|–|
|VFALLIPOR|Falling trip voltage|0.75|–|1.40|V|–|
|VIPORHYST|Hysteresis|15|–|200|mV|–|



## **Table 42.  POR AC Specifications** 

|**Parameter**|**Description**||||**Min**|**Min**||**Typ**|**Typ**||**Max**||**Units**||**Details/Conditions**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|TPPOR_TR|Precision power-on reset (PPOR) response<br>time in Active and Sleep modes||||–|||–|||1||s||–|
|**Table 43.  Brown-Out Detect**||||||||||||||||
|**Parameter**|**Description**||||**Min**|||**Typ**|||**Max**||**Units**||**Details/Conditions**|
|VFALLPPOR|BOD trip voltage in Active and Sleep modes||||1.64|||–|–||–||V||–|
|VFALLDPSLP|BOD trip voltage in Deep Sleep||||1.4|||–|–||–||V||–|
|**Table 44.  Hibernate Reset**||||||||||||||||
|**Parameter**|**Description**|**Min**||**Typ**|||**Max**|||**Units**||||**Details/Conditions**||
|VHBRTRIP|BOD trip voltage in Hibernate|1.1|||–|||–|||V||||–|



## **Table 43.  Brown-Out Detect** 

## **Table 44.  Hibernate Reset** 

## **Note** 

12. It can take as much as 20 ms to write to flash. During this time, the device should not be reset, or flash operations will be interrupted and cannot be relied on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs. Make certain that these are not inadvertently activated. 

Document Number: 002-15631 Rev.*D 

Page 25 of 40 

**CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11** 

_Voltage Monitors (LVD)_ 

**Table 45.  Voltage Monitor DC Specifications** 

|**Parameter**<br>~~es~~<br>~~ee~~|**Description**<br>~~nD~~<br>|**Min**<br>~~(I~~|**Typ**<br>~~(I~~<br>~~I~~|**Max**<br>~~(I~~<br>~~(RR~~|**Units**<br>~~(OO~~<br>~~(OU~~|**Details/Conditions**<br>~~(OU~~|
|---|---|---|---|---|---|---|
|VLVI1<br>~~es~~<br>~~es~~<br>~~ee~~|LVI_A/D_SEL[3:0] = 0000b<br>~~nD~~<br>~~es~~<br>~~es~~|1.71<br>~~(I~~<br>~~es~~<br>~~rs~~|1.75<br>~~(I~~<br>~~es~~<br>~~I~~<br>~~rs RD~~|1.79<br>~~(I ~~<br>~~es~~<br>~~(RR~~<br>~~RD~~|V<br> ~~(OO~~<br>~~es~~<br>~~(OU~~|–<br>~~es~~<br>~~(OU~~|
|VLVI2<br>~~es~~<br>~~ee~~<br>~~ee~~|LVI_A/D_SEL[3:0] = 0001b<br>~~es~~<br>~~es~~<br>|1.76<br>~~es~~<br>~~rs~~<br>~~I~~|1.80<br>~~es~~<br>~~I~~<br>~~rs RD~~<br>~~Is~~|1.85<br>~~es~~<br>~~(RR~~<br>~~RD~~<br>~~(I~~|V<br>~~es~~<br>~~(OU~~<br>~~I (~~|–<br>~~es~~<br>~~(OU~~<br>~~(~~|
|VLVI3<br>~~ee~~<br>~~er~~<br>~~ee~~|LVI_A/D_SEL[3:0] = 0010b<br>~~es~~<br>~~er~~<br>~~es~~|1.85<br>~~rs~~<br>~~er~~<br>~~I~~<br>~~rs~~|1.90<br>~~I ~~<br>~~rs RD~~<br>~~er~~<br>~~Is~~<br>~~rs RD~~|1.95<br> ~~(RR ~~<br>~~RD~~<br>~~er~~<br>~~(I~~<br>~~RD~~|V<br> ~~(OU~~<br>~~er~~<br>~~I (~~|–<br>~~(OU~~<br>~~er~~<br>~~(~~|
|VLVI4<br>~~er~~<br>~~ee~~<br>~~ee~~|LVI_A/D_SEL[3:0] = 0011b<br>~~er~~<br>~~es~~<br>|1.95<br>~~er~~<br>~~I~~<br>~~rs~~<br>~~I~~|2.00<br>~~er~~<br>~~Is~~<br>~~rs RD~~<br>~~Is~~|2.05<br>~~er~~<br>~~(I~~<br>~~RD~~<br>~~(I~~|V<br>~~er~~<br>~~I (~~<br>~~I (~~|–<br>~~er~~<br>~~(~~<br>~~(~~|
|VLVI5<br>~~ee~~<br>~~er~~<br>~~ee~~|LVI_A/D_SEL[3:0] = 0100b<br>~~es~~<br>~~er~~<br>~~es~~|2.05<br>~~I ~~<br>~~rs~~<br>~~er~~<br>~~I~~<br>~~rs~~|2.10<br> ~~Is~~<br>~~rs RD~~<br>~~er~~<br>~~Is~~<br>~~rs RD~~|2.15<br>~~(I ~~<br>~~RD~~<br>~~er~~<br>~~(I~~<br>~~RD~~|V<br> ~~I (~~<br>~~er~~<br>~~I (~~|–<br>~~(~~<br>~~er~~<br>~~(~~|
|VLVI6<br>~~er~~<br>~~ee~~<br>~~ee~~|LVI_A/D_SEL[3:0] = 0101b<br>~~er~~<br>~~es~~<br>|2.15<br>~~er~~<br>~~I~~<br>~~rs~~<br>~~I~~|2.20<br>~~er~~<br>~~Is~~<br>~~rs RD~~<br>~~Is~~|2.26<br>~~er~~<br>~~(I~~<br>~~RD~~<br>~~(I~~|V<br>~~er~~<br>~~I (~~<br>~~I (~~|–<br>~~er~~<br>~~(~~<br>~~(~~|
|VLVI7<br>~~ee~~<br>~~er~~<br>~~ee~~|LVI_A/D_SEL[3:0] = 0110b<br>~~es~~<br>~~er~~<br>~~es~~|2.24<br>~~I ~~<br>~~rs~~<br>~~er~~<br>~~I~~<br>~~rs~~|2.30<br> ~~Is~~<br>~~rs RD~~<br>~~er~~<br>~~Is~~<br>~~rs RD~~|2.36<br>~~(I ~~<br>~~RD~~<br>~~er~~<br>~~(I~~<br>~~RD~~|V<br> ~~I (~~<br>~~er~~<br>~~I (~~|–<br>~~(~~<br>~~er~~<br>~~(~~|
|VLVI8<br>~~er~~<br>~~ee~~<br>~~ee~~|LVI_A/D_SEL[3:0] = 0111b<br>~~er~~<br>~~es~~<br>|2.34<br>~~er~~<br>~~I~~<br>~~rs~~<br>~~I~~|2.40<br>~~er~~<br>~~Is~~<br>~~rs RD~~<br>~~Is~~|2.46<br>~~er~~<br>~~(I~~<br>~~RD~~<br>~~(I~~|V<br>~~er~~<br>~~I (~~<br>~~I (~~|–<br>~~er~~<br>~~(~~<br>~~(~~|
|VLVI9<br>~~ee~~<br>~~er~~<br>~~ee~~|LVI_A/D_SEL[3:0] = 1000b<br>~~es~~<br>~~er~~<br>~~es~~|2.44<br>~~I ~~<br>~~rs~~<br>~~er~~<br>~~I~~<br>~~rs~~|2.50<br> ~~Is~~<br>~~rs RD~~<br>~~er~~<br>~~Is~~<br>~~rs RD~~|2.56<br>~~(I ~~<br>~~RD~~<br>~~er~~<br>~~(I~~<br>~~RD~~|V<br> ~~I (~~<br>~~er~~<br>~~I (~~|–<br>~~(~~<br>~~er~~<br>~~(~~|
|VLVI10<br>~~er~~<br>~~ee~~<br>~~ee~~|LVI_A/D_SEL[3:0] = 1001b<br>~~er~~<br>~~es~~<br>|2.54<br>~~er~~<br>~~I~~<br>~~rs~~<br>~~I~~|2.60<br>~~er~~<br>~~Is~~<br>~~rs RD~~<br>~~Is~~|2.67<br>~~er~~<br>~~(I~~<br>~~RD~~<br>~~(I~~|V<br>~~er~~<br>~~I (~~<br>~~I (~~|–<br>~~er~~<br>~~(~~<br>~~(~~|
|VLVI11<br>~~ee~~<br>~~er~~<br>~~ee~~|LVI_A/D_SEL[3:0] = 1010b<br>~~es~~<br>~~er~~<br>~~es~~|2.63<br>~~I ~~<br>~~rs~~<br>~~er~~<br>~~I~~<br>~~rs~~|2.70<br> ~~Is~~<br>~~rs RD~~<br>~~er~~<br>~~Is~~<br>~~rs RD~~|2.77<br>~~(I ~~<br>~~RD~~<br>~~er~~<br>~~(I~~<br>~~RD~~|V<br> ~~I (~~<br>~~er~~<br>~~I (~~|–<br>~~(~~<br>~~er~~<br>~~(~~|
|VLVI12<br>~~er~~<br>~~ee~~<br>~~ee~~|LVI_A/D_SEL[3:0] = 1011b<br>~~er~~<br>~~es~~<br>|2.73<br>~~er~~<br>~~I~~<br>~~rs~~<br>~~I~~|2.80<br>~~er~~<br>~~Is~~<br>~~rs RD~~<br>~~Is~~|2.87<br>~~er~~<br>~~(I~~<br>~~RD~~<br>~~(I~~|V<br>~~er~~<br>~~I (~~<br>~~I (~~|–<br>~~er~~<br>~~(~~<br>~~(~~|
|VLVI13<br>~~ee~~<br>~~er~~<br>~~ee~~|LVI_A/D_SEL[3:0] = 1100b<br>~~es~~<br>~~er~~<br>~~es~~|2.83<br>~~I ~~<br>~~rs~~<br>~~er~~<br>~~I~~<br>~~rs~~|2.90<br> ~~Is~~<br>~~rs RD~~<br>~~er~~<br>~~Is~~<br>~~rs RD~~|2.97<br>~~(I ~~<br>~~RD~~<br>~~er~~<br>~~(I~~<br>~~RD~~|V<br> ~~I (~~<br>~~er~~<br>~~I (~~|–<br>~~(~~<br>~~er~~<br>~~(~~|
|VLVI14<br>~~er~~<br>~~ee~~<br>~~ee~~|LVI_A/D_SEL[3:0] = 1101b<br>~~er~~<br>~~es~~<br>|2.93<br>~~er~~<br>~~I~~<br>~~rs~~<br>~~I~~|3.00<br>~~er~~<br>~~Is~~<br>~~rs RD~~<br>~~Is~~|3.08<br>~~er~~<br>~~(I~~<br>~~RD~~<br>~~(I~~|V<br>~~er~~<br>~~I (~~<br>~~I (~~|–<br>~~er~~<br>~~(~~<br>~~(~~|
|VLVI15<br>~~ee~~<br>~~er~~<br>~~ee~~|LVI_A/D_SEL[3:0] = 1110b<br>~~es~~<br>~~er~~<br>~~es~~|3.12<br>~~I ~~<br>~~rs~~<br>~~er~~<br>~~I~~<br>~~rs~~|3.20<br> ~~Is~~<br>~~rs RD~~<br>~~er~~<br>~~Is~~<br>~~rs RD~~|3.28<br>~~(I ~~<br>~~RD~~<br>~~er~~<br>~~(I~~<br>~~RD~~|V<br> ~~I (~~<br>~~er~~<br>~~I (~~|–<br>~~(~~<br>~~er~~<br>~~(~~|
|VLVI16<br>~~er~~<br>~~ee~~|LVI_A/D_SEL[3:0] = 1111b<br>~~er~~<br>~~es~~|4.39<br>~~er~~<br>~~I~~<br>~~rs~~|4.50<br>~~er~~<br>~~Is~~<br>~~rs RD~~<br>~~Is Rs~~|4.61<br>~~er~~<br>~~(I~~<br>~~RD~~<br>~~Rs ID~~|V<br>~~er~~<br>~~I (~~<br>~~ID~~|–<br>~~er~~<br>~~(~~<br>~~(~~|
|LVI_IDD<br>~~ee~~<br>~~rs~~|Block current<br>~~es~~<br>~~rs~~|–<br>~~I ~~<br>~~rs~~<br>~~rs~~|–<br> ~~Is~~<br>~~rs RD~~<br>~~rs~~<br>~~Is Rs~~|100<br>~~(I ~~<br>~~RD~~<br>~~rs~~<br>~~Rs ID~~|A<br> ~~I (~~<br>~~rs~~<br>~~ID~~|–<br>~~(~~<br>~~rs~~<br>~~(~~|



_SWD Interface_ 

**Table 47.  SWD Interface Specifications** 

|**Parameter**<br>~~ee~~|**Description**<br>~~rn~~|**Min**<br>~~rs~~|**Typ**<br>~~ttt~~|**Max**<br>~~nt~~|**Units**<br>~~nt (~~|**Details/Conditions**<br>~~(~~|
|---|---|---|---|---|---|---|
|F_SWDCLK1<br>~~ee~~<br>~~a~~<br>~~ee~~|3.3 VVDD 5.5 V<br>~~rn ~~<br>~~a~~<br>~~I~~<br>~~es~~|–<br> ~~rs ~~<br>~~a~~<br>~~I~~<br>~~ID~~|–<br> ~~ttt~~<br>~~a~~<br>~~I~~<br>~~I~~|14<br>~~nt~~<br>~~I~~|MHz<br>~~nt (~~<br>~~I~~|SWDCLK1/3 CPU clock frequency<br>~~(~~<br>~~I~~|
|F_SWDCLK2<br>~~a~~<br>~~ee~~|1.71 VVDD 3.3 V<br>~~a~~<br>~~es~~<br>~~rs~~|–<br>~~a~~<br>~~ID~~<br>~~I~~|–<br>~~a~~<br>~~I~~<br>~~I~~|7<br>~~I~~|MHz|SWDCLK1/3 CPU clock frequency|
|T_SWDI_SETUP<br>~~ee~~<br>~~a~~|T = 1/f SWDCLK<br>~~es~~<br>~~rs~~<br>|0.25 × T<br>~~ID~~<br>~~I~~<br>~~OD~~<br>|–<br>~~I~~<br>~~I~~<br>|–<br>~~I~~|ns|–|
|T_SWDI_HOLD<br>~~ee~~<br>~~es~~<br>~~a~~<br>~~a~~|T = 1/f SWDCLK<br>~~es ~~<br>~~rs ~~<br>~~es~~<br>~~es~~|0.25 × T<br> ~~ID ~~<br> ~~I~~<br>~~es~~<br>~~OD~~<br>~~ID~~|–<br> ~~I~~<br>~~I ~~<br>~~es~~<br>~~**I**~~|–<br> ~~I~~<br>~~es~~|ns<br>~~es~~|–<br>~~es~~|
|T_SWDO_VALID<br>~~a ~~<br>~~a~~|T = 1/f SWDCLK<br> ~~es~~|–<br>~~OD~~<br>~~ID~~|–<br>~~**I**~~|0.5 × T|ns|–|
|T_SWDO_HOLD<br> <br>~~a~~|T = 1/f SWDCLK<br> ~~es ~~<br>~~I~~|1<br> ~~ID ~~<br>~~I~~|–<br> ~~**I**~~|–|ns|–|



Document Number: 002-15631 Rev.*D 

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**CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11** 

## _Internal Main Oscillator_ 

## **Table 48.  IMO DC Specifications** 

|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Units**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|IIMO1<br>IMO operating current at 48 MHz|IMO operating current at 48 MHz|–|–|1000|A|–|
|IIMO2<br>IMO operating current at 24 MHz|IMO operating current at 24 MHz|–|–|325|A|–|
|IIMO3<br>IMO operating current at 12 MHz|IMO operating current at 12 MHz|–|–|225|A|–|
|IIMO4<br>IMO operating current at 6 MHz|IMO operating current at 6 MHz|–|–|180|A|–|
|IIMO5<br>IMO operating current at 3 MHz|IMO operating current at 3 MHz|–|–|150|A|–|



## **Table 49.  IMO AC Specifications** 

|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Units**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|FIMOTOL3|Frequency variation from 3 to 48 MHz|–|–|±2|%|With API-called calibration|
|FIMOTOL3|IMO startup time|–|12|–|s|–|



_Internal Low-Speed Oscillator_ 

## **Table 50.  ILO DC Specifications** 

|**Parameter**<br>**Description**|**Min**|**Typ**||**Max**||**Units**||**Details/Conditions**|
|---|---|---|---|---|---|---|---|---|
|IILO2<br>ILO operating current at 32 kHz|–|0.3||1.05||A||–|
|**Table 51.  ILO AC Specifications**|||||||||
|**Parameter**<br>**Description**|**Min**|**Typ**||**Max**||**Units**||**Details/Conditions**|
|TSTARTILO1<br>ILO startup time|–|–||2||ms||–|
|FILOTRIM1<br>32-kHz trimmed frequency|15|32||50||kHz||–|



## **Table 51.  ILO AC Specifications** 

## **Table 52.  ECO Trim Value Specification** 

|**Parameter**|**Description**|**Value**|**Details/Conditions**|
|---|---|---|---|
|ECOTRIM|24-MHz trim value<br>(firmware configuration)|0x0000D0D0|Optimum trim value that needs to be loaded to register<br>CY_SYS_XTAL_BLERD_BB_XO_CAPTRIM_REG|



_BLE Subsystem_ 

## **Table 53.  BLE Subsystem** 

|**Parameter**<br>~~es~~|**Description**<br>~~rs~~|**Min**<br>~~tt~~|**Typ**<br>~~ttt~~|**Max**<br>~~rs~~|**Units**<br>~~I~~|**Details/Conditions**|
|---|---|---|---|---|---|---|
|**RF Receiver Specification**<br>~~es~~<br>~~rs tt ttt~~<br>~~rs I~~<br>~~Pee~~<br>~~aee~~|||||||
|RXS, IDLE<br>~~a~~|RX sensitivity with idle transmitter<br>~~ee~~|–|–89|–|dBm|Silicon only|
||RX sensitivity with idle transmitter<br>excluding Balun loss<br>~~ee~~|–|–91|–|dBm|Silicon only<br>Guaranteed by design<br>simulation|
|RXS, DIRTY<br>~~a ~~<br>~~a~~|RX sensitivity with dirty transmitter<br> ~~ee~~|–|–87|–70|dBm<br>~~ee~~|Silicon only<br>RF-PHY Specification<br>(RCV-LE/CA/01/C)<br>~~ee~~|
|RXS, HIGHGAIN<br>~~a~~<br>~~a~~<br>~~ee~~|RX sensitivity in high-gain mode with idle<br>transmitter<br>~~ee~~<br>~~**e**e~~|–<br>~~ee~~<br>~~ee~~|–91<br>~~ee~~<br>~~e~~~~**e**~~|–<br>~~ee~~<br>~~**e**e~~|dBm<br>~~ee~~<br>~~ee~~<br>~~**e**s~~|Silicon only<br>~~ee~~<br>~~ee~~|
|RXS, IDLE, MOD<br>~~a~~<br>~~a~~<br>~~ee~~|RX sensitivity for full module with idle<br>transmitter<br>~~ee~~<br>~~**e**e~~<br>~~e~~|–<br>~~ee~~<br>~~ee~~<br>~~ee~~|–93<br>~~ee~~<br>~~e~~~~**e**~~<br>~~e~~|–<br>~~ee~~<br>~~**e**e~~<br>~~s~~|dBm<br>~~ee~~<br>~~ee~~<br>~~**e**s~~<br>~~e~~|Full module, LNA active<br>~~ee~~<br>~~ee~~|
|PRXMAX<br>~~ee~~|Maximum input power<br>~~**e**e~~<br>~~e~~|–10<br>~~ee~~<br>~~ee~~|–1<br>~~e~~~~**e**~~<br>~~e~~|–<br>~~**e**e~~<br>~~s~~|dBm<br>~~**e**s~~<br>~~e~~|RF-PHY Specification<br>(RCV-LE/CA/06/C)|



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**CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11** 

**Table 53.  BLE Subsystem** (continued) 

|**Parameter**<br>~~es~~|**Description**|**Min**|**Typ**|**Max**|**Units**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|CI1<br>~~es~~|Cochannel interference,<br>Wanted signal at –67 dBm and Interferer<br>at FRX|–|9|21|dB|RF-PHY Specification<br>(RCV-LE/CA/03/C)|
|CI2<br>~~es~~|Adjacent channel interference<br>Wanted signal at –67 dBm and Interferer<br>at FRX ±1 MHz|–|3|15|dB|RF-PHY Specification<br>(RCV-LE/CA/03/C)|
|CI3|Adjacent channel interference<br>Wanted signal at –67 dBm and Interferer<br>at FRX ±2 MHz|–|–29|–|dB|RF-PHY Specification<br>(RCV-LE/CA/03/C)|
|CI4|Adjacent channel interference<br>Wanted signal at –67 dBm and Interferer<br>atFRX ±3 MHz|–|–39|–|dB|RF-PHY Specification<br>(RCV-LE/CA/03/C)|
|CI5|Adjacent channel interference<br>Wanted Signal at –67 dBm and Interferer<br>at Image frequency (FIMAGE)|–|–29|–|dB|RF-PHY Specification<br>(RCV-LE/CA/03/C)|
|CI6|Adjacent channel interference<br>Wanted signal at –67 dBm and Interferer<br>at Image frequency (FIMAGE± 1 MHz)|–|–30|–|dB|RF-PHY Specification<br>(RCV-LE/CA/03/C)|
|OBB1|Out-of-band blocking,<br>Wanted signal at –67 dBm and Interferer<br>at F = 30–2000 MHz|–30|–27|–|dBm|RF-PHY Specification<br>(RCV-LE/CA/04/C)|
|OBB2|Out-of-band blocking,<br>Wanted signal at –67 dBm and Interferer<br>at F = 2003–2399 MHz|–35|–27|–|dBm|RF-PHY Specification<br>(RCV-LE/CA/04/C)|
|OBB3|Out-of-band blocking,<br>Wanted signal at –67 dBm and Interferer<br>at F = 2484–2997 MHz|–35|–27|–|dBm|RF-PHY Specification<br>(RCV-LE/CA/04/C)|
|OBB4|Out-of-band blocking,<br>Wanted signal a –67 dBm and Interferer<br>at F = 3000–12750 MHz|–30|–27|–|dBm|RF-PHY Specification<br>(RCV-LE/CA/04/C)|
|IMD|Inter modulation performance<br>Wanted signal at –64 dBm and 1-Mbps<br>BLE, third, fourth, and fifth offset channel|–50|–|–|dBm|RF-PHY Specification<br>(RCV-LE/CA/05/C)|
|RXSE1|Receiver spurious emission<br>30 MHz to 1.0 GHz|–|–|–57|dBm|100-kHz measurement<br>bandwidth<br>ETSI EN300 328 V1.8.1|
|RXSE2<br>~~Co~~|Receiver spurious emission<br>1.0 GHz to 12.75 GHz|–|–|–47|dBm|1-MHz measurement<br>bandwidth<br>ETSI EN300 328 V1.8.1|
|**RF Transmitter Specifications**<br>~~Coa~~<br>~~nsttI~~|||||||
|TXP, ACC<br>~~Coa~~|RF power accuracy<br>~~ns~~|–<br>~~tt~~|±1<br>~~I~~|–|dB|–|
|TXP, RANGE<br>~~a~~|RF power control range<br>~~ns ~~|–<br> ~~tt ~~|6<br> ~~I~~|21|dB|Usable range to comply to<br>certifications.|
|TXP, TYP|Output power, –12-dB (PA2) Gain setting<br>for silicon|–|7.5|–|dBm|This is the required power<br>level to comply to certifica-<br>tions and qualifications for<br>this module|



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**CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11** 

**Table 53.  BLE Subsystem** (continued) 

|**Parameter**<br>~~F ]U~~|**Description**<br>~~]U~~|**Min**<br>~~]U~~|**Typ**<br>~~LLL~~|**Max**<br>~~LLL~~|**Units**<br>~~LLL~~|**Details/Conditions**<br>~~LLL~~|
|---|---|---|---|---|---|---|
|TXP, MAX<br>~~F ]U~~<br>~~ee~~|Output power, maximum power setting<br>~~]U~~<br>~~rs~~|–<br>~~]U~~<br>~~tts~~|22.5<br>~~LLL~~<br>~~ttt~~|–<br>~~LLL~~<br>~~ts~~|dBm<br>~~LLL~~|Output power above +7.5<br>dBm will void certifications<br>and qualifications of this<br>module.<br>~~LLL~~|
|TXP, MIN<br>~~F ]U~~<br>~~ee~~<br>~~a~~|Output power, minimum power setting<br>~~]U~~<br>~~rs~~<br>|–<br>~~]U ~~<br>~~tts~~<br>~~ee~~<br>|1.5<br> ~~LLL~~<br>~~ttt~~<br>|–<br>~~LLL~~<br>~~ts~~<br>|dBm<br>~~LLL~~<br>~~ee~~<br>|–<br>~~LLL~~<br>~~ee~~<br>|
|F2AVG<br>~~ee~~<br>~~a~~<br>~~a~~<br>~~a~~|Average frequency deviation for<br>10101010 pattern<br>~~rs ~~<br>~~ee~~<br>|185<br> ~~tts ~~<br>~~ee~~<br>~~ee~~<br><br>~~ee~~|–<br> ~~ttt ~~<br>~~ee~~<br><br>~~ee~~|–<br> ~~ts~~<br>~~ee~~<br><br>~~ee~~|kHz<br>~~ee~~<br>~~ee~~<br><br>~~ee~~|RF-PHY Specification<br>(TRM-LE/CA/05/C)<br>~~ee~~<br>~~ee~~<br><br>~~ee~~|
|F1AVG<br>~~a ~~<br>~~a~~<br>~~a~~<br>~~ae~~|Average frequency deviation for<br>11110000 pattern<br> ~~ee~~<br>~~ae~~<br>~~ee~~|225<br>~~ee~~<br>~~ee~~<br>~~ae~~<br>~~ee~~<br>~~ee~~|250<br>~~ee~~<br>~~ae~~<br>~~ee~~<br>~~ee~~|275<br>~~ee~~<br>~~ae~~<br>~~ee~~<br>~~ee~~|kHz<br>~~ee~~<br>~~ee~~<br>~~ae~~<br>~~ee~~<br>~~es~~|RF-PHY Specification<br>(TRM-LE/CA/05/C)<br>~~ee~~<br>~~ee~~<br>~~ae~~<br>~~ee~~|
|EO<br>~~a ~~<br>~~a~~<br>~~ae~~<br>~~ae~~|Eye opening =F2AVG/F1AVG<br> ~~ae~~<br>~~ee~~<br>~~ee~~|0.8<br>~~ee~~<br>~~ae~~<br>~~ee ~~<br>~~ee~~<br>~~ee~~|–<br>~~ae~~<br> ~~ee~~<br>~~ee~~<br>~~ee~~|–<br>~~ae~~<br>~~ee ~~<br>~~ee~~<br>~~es~~|~~ee~~<br>~~ae~~<br> ~~ee~~<br>~~es~~<br>~~es~~|RF-PHY Specification<br>(TRM-LE/CA/05/C)<br>~~ee~~<br>~~ae~~<br>~~ee~~|
|FTX, ACC<br>~~ae~~<br>~~ae~~<br>~~a~~|Frequency accuracy<br>~~ee~~<br>~~ee~~<br>~~es~~<br>|–150<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|–<br>~~ee~~<br>~~ee~~<br>~~**e**e~~<br>|150<br>~~ee~~<br>~~es~~<br>~~es~~|kHz<br>~~es~~<br>~~es~~<br>~~es~~|RF-PHY Specification<br>(TRM-LE/CA/06/C)|
|FTX, MAXDR<br>~~ae~~<br>~~ae~~<br>~~a~~<br>~~a~~|Maximum frequency drift<br>~~ee ~~<br>~~ee~~<br>~~es~~<br><br>|–50<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br><br>~~ee~~<br>|–<br> ~~ee ~~<br>~~ee~~<br>~~**e**e~~<br><br>~~ee~~<br>|50<br> ~~ee ~~<br>~~es~~<br>~~es~~<br>~~ee~~<br>|kHz<br> ~~es~~<br>~~es~~<br>~~es~~<br>~~ee~~<br>|RF-PHY Specification<br>(TRM-LE/CA/06/C)<br>~~ee~~<br>|
|FTX, INITDR<br>~~ae~~<br>~~a e~~<br>~~a~~<br>~~a~~|Initial frequency drift<br>~~ee ~~<br>~~es~~<br>~~e~~<br><br>|–20<br> ~~ee ~~<br>~~ee~~<br>~~e~~<br>~~ee~~<br><br>~~ee~~<br>|–<br> ~~ee ~~<br>~~**e**e~~<br>~~e~~<br>~~ee~~<br><br>|20<br> ~~es ~~<br>~~es~~<br>~~ee~~<br><br>|kHz<br> ~~es~~<br>~~es~~<br>~~ee~~<br><br>~~ee~~<br>|RF-PHY Specification<br>(TRM-LE/CA/06/C)<br>~~ee~~<br><br>~~ee~~<br>|
|FTX, DR<br>~~a e~~<br>~~a~~<br>~~a~~<br>~~a~~|Maximum drift rate<br>~~es ~~<br>~~e~~<br>~~ee~~<br>|–20<br> ~~ee ~~<br>~~e~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br><br>~~ee~~|–<br> ~~**e**e ~~<br>~~e~~<br>~~ee~~<br>~~ee~~<br><br>~~ee~~|20<br> ~~es ~~<br>~~ee~~<br>~~ee~~<br><br>~~ee~~|kHz/<br>50 s<br> ~~es~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br><br>~~ee~~|RF-PHY Specification<br>(TRM-LE/CA/06/C)<br>~~ee~~<br>~~ee~~<br>~~ee~~<br><br>~~ee~~|
|IBSE1<br>~~a ~~<br>~~a~~<br>~~a~~<br>~~ae~~|In-band spurious emission at 2-MHz<br>offset<br> ~~ee~~<br>~~ae~~<br>~~ee~~|–<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ae~~<br>~~ee~~<br>~~ee~~|–<br> ~~ee~~<br>~~ee~~<br>~~ae~~<br>~~ee~~<br>~~ee~~|–20<br>~~ee ~~<br>~~ee~~<br>~~ae~~<br>~~ee~~<br>~~ee~~|dBm<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ae~~<br>~~ee~~<br>~~es~~|RF-PHY Specification<br>(TRM-LE/CA/03/C)<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ae~~<br>~~ee~~|
|IBSE2<br>~~a~~<br>~~ae~~<br>~~a~~|In-band spurious emission at3-MHz<br>offset<br>~~ee~~<br>~~es~~|–<br>~~ee ~~<br>~~ee~~<br>~~ee~~|–<br> ~~ee~~<br>~~ee~~<br>~~ee~~|-30<br>~~ee ~~<br>~~ee~~<br>~~es~~|dBm<br> ~~ee~~<br>~~es~~<br>~~es~~|RF-PHY Specification<br>(TRM-LE/CA/03/C)<br>~~ee~~|
|TXSE1<br>~~ae~~<br>~~a~~|Transmitter spurious emissions<br>(average), <1.0 GHz<br>~~ee~~<br>~~es~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~<br>~~eee~~|-55.5<br>~~ee~~<br>~~es~~<br>~~eee~~|dBm<br>~~es~~<br>~~es~~<br>~~eee~~|FCC-15.247<br>~~eee~~|
|TXSE2<br>~~ae~~<br>~~a~~|Transmitter spurious emissions<br>(average), >1.0 GHz<br>~~ee ~~<br>~~es~~ <br>~~ee~~|–<br> ~~ee ~~<br> ~~ee~~ <br>~~ee~~|–<br> ~~ee ~~<br> ~~ee ~~<br>~~eee~~|-41.5<br> ~~ee ~~<br> ~~es ~~<br>~~eee~~|dBm<br> ~~es~~<br> ~~es~~<br>~~eee~~|FCC-15.247<br>~~eee~~|
|**RF Current Specifications**<br>~~ee eeeee~~<br>~~Be~~<br>~~ee~~<br>~~rsttstrts en~~|||||||
|IRX<br>~~ee~~<br>~~ee~~|Receive current in normal mode<br>~~rs~~|–<br>~~tts~~<br>~~ee~~|18.7<br>~~tr~~|–<br>~~ts en~~|mA<br>~~en~~<br>~~ee~~|Silicon only<br>~~ee~~|
|IRX_RF<br>~~ee~~<br>~~a~~<br>~~ee~~<br>~~ee~~|Radio receive current in normal mode<br>~~rs ~~<br>~~ee~~<br>~~rs~~|–<br> ~~tts ~~<br>~~ee~~<br>~~ee~~<br>~~tts~~|16.4<br> ~~tr ~~<br>~~ee~~<br>~~ttt~~|–<br> ~~ts en~~<br>~~ee~~<br>~~ts~~|mA<br>~~en~~<br>~~ee~~<br>~~ee~~|Silicon only<br>Measured at VDDR<br>~~ee~~<br>~~ee~~|
|IRX, HIGHGAIN<br>~~a ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|Receive current in high-gain mode<br> ~~ee~~<br>~~rs~~<br>~~rs~~|–<br>~~ee~~<br>~~ee~~<br>~~tts~~<br>~~tts~~|21.5<br>~~ee~~<br>~~ttt~~<br>~~ttre~~|–<br>~~ee~~<br>~~ts~~<br>~~ee~~|mA<br>~~ee~~<br>~~ee~~<br>~~I~~|Silicon only<br>~~ee~~<br>~~ee~~|
|IRX, LNA<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|Receive current, LNA<br>~~rs~~<br>~~rs~~<br>~~**rns**~~<br>|–<br>~~ee~~<br>~~tts~~<br>~~tts~~<br>~~**titres**~~<br>|8.0<br>~~ttt~~<br>~~ttre~~<br>~~**ttt**~~<br>|–<br>~~ts~~<br>~~ee~~<br>~~**ts**~~<br>|mA<br>~~ee~~<br>~~I~~<br>|LNA only<br>~~ee~~<br>|
|ITX, 3dBm<br>~~ee~~<br>~~ee~~<br>~~ee~~|TX current at 3-dBm setting (PA10)<br>~~rs ~~<br>~~rs~~<br>~~**rns**~~<br>|–<br> ~~tts ~~<br>~~tts~~<br>~~**titres**~~<br>|20<br> ~~ttt ~~<br>~~ttre~~<br>~~**ttt**~~<br>|–<br> ~~ts~~<br>~~ee~~<br>~~**ts**~~<br>|mA<br>~~I~~<br>|Silicon only<br>|
|ITX, 0dBm<br>~~ee~~<br>~~ee~~|TX current at 0-dBm setting (PA7)<br>~~rs ~~<br>~~**rns**~~<br>|–<br> ~~tts ~~<br>~~**titres**~~<br>|16.5<br> ~~ttre ~~<br>~~**ttt**~~<br>|–<br> ~~ee ~~<br>~~**ts**~~<br>|mA<br> ~~I~~<br>|Silicon only<br>|
|ITX_RF, 0dBm<br>~~eeooo~~|Radio TX current at 0 dBm setting (PA7)<br>~~**rns** ~~<br>~~ooo~~|–<br> ~~**titres** ~~<br>~~ooo~~|15.6<br> ~~**ttt** ~~<br>~~ooo~~|–<br> ~~**ts**~~<br>~~ooo~~|mA<br>~~ooo~~|Silicon only.<br>Measured at VDDR<br>~~ooo~~|
|ITX_RF, 0dBm<br>~~ooo~~<br>~~ee~~|Radio TX current at 0 dBm excluding<br>Balun loss<br>~~ooo~~<br>~~rs~~|–<br>~~ooo~~<br>~~tris~~|14.2<br>~~ooo~~<br>~~tts~~|–<br>~~ooo~~<br>~~tt~~|mA<br>~~ooo~~|Silicon only.<br>Guaranteed by design<br>simulation<br>~~ooo~~|
|ITX,-3dBm<br>~~ee~~<br>~~ee~~|TX current at –3-dBm setting (PA4)<br>~~rs~~<br>~~rns~~|–<br>~~tris~~<br>~~titres~~|15.5<br>~~tts~~<br>~~ttt~~|–<br>~~tt~~<br>~~ts~~|mA|Silicon only|
|ITX,-6dBm<br>~~ee~~<br>~~ee~~<br>~~ee~~|TX current at –6-dBm setting (PA3)<br>~~rs ~~<br>~~rns~~<br>~~errs~~|–<br> ~~tris ~~<br>~~titres~~<br>~~Getty~~|14.5<br> ~~tts ~~<br>~~ttt~~<br>~~etter~~|–<br> ~~tt~~<br>~~ts~~<br>~~ttt~~|mA|Silicon only|
|ITX,-12dBm<br>~~ee~~<br>~~ee~~|TX current at –12-dBm setting (PA2)<br>~~rns ~~<br>~~errs~~|–<br> ~~titres ~~<br>~~Getty~~|13.2<br> ~~ttt ~~<br>~~etter~~|–<br> ~~ts~~<br>~~ttt~~|mA|Silicon only|
|ITX,-18dBm<br>~~ee~~<br>~~Po~~|TX current at –18-dBm setting (PA1)<br>~~errs ~~<br>~~Po~~|–<br> ~~Getty ~~<br>~~Po~~|12.5<br> ~~etter ~~<br>~~Po~~|–<br> ~~ttt~~<br>~~Po~~|mA<br>~~Po~~|Silicon only<br>~~Po~~|



Document Number: 002-15631 Rev.*D 

Page 29 of 40 

**CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11** 

**Table 53.  BLE Subsystem** (continued) 

|**Parameter**<br>~~GO~~|**Description**<br>~~GO~~|**Min**<br>~~GO~~|**Typ**<br>~~GO~~|**Max**<br>~~GO~~<br>~~GO~~|**Units**<br>~~GO~~<br>~~(OO~~|**Details/Conditions**<br>~~GO~~<br>~~(OO~~|
|---|---|---|---|---|---|---|
|ITX, +7.5dBm|PA TX Current at +7.5 dBm module TXP<br>Silicon TXP set to –12-dBm setting (PA2)|–|8.0|–<br>~~GO~~|mA<br>~~(OO~~|PA only average current<br>Packet length of 0x01<br>Continuous Transmit<br>~~(OO~~|
|||–|27.0|–|mA|PA only average current<br>Packet length of 0xFF<br>Continuous Transmit|
|ITXRX, PA/LNA|PA/LNA set to shutdown mode|–|1.0|–|A|PA/LNA only current|
|Iavg_1sec, 7.5dBm|Average current at 1-second BLE<br>connection interval|–|30|–|A|Module TXP: +7.5 dBm;<br>±20-ppm master and<br>slave clock accuracy.<br>For empty PDU exchange|
|Iavg_4sec, 7.5dBm|Average current at 4-second BLE<br>connection interval|–|13|–|A|Module TXP: +7.5 dBm;<br>±20-ppm master and<br>slave clock accuracy.<br>For empty PDU exchange|
|**General RF Specifications**<br>~~po~~|||||||
|FREQ<br>~~po~~<br>~~po~~|RF operating frequency|2400|–|2482|MHz|–|
|CHBW<br>~~po~~<br>~~po~~<br>~~po~~|Channel spacing|–|2|–|MHz|–|
|DR<br>~~po~~<br>~~po~~<br>~~po~~|On-air data rate|–|1000|–|kbps|–|
|IDLE2TX<br>~~po~~<br>~~po~~<br>~~po~~|BLE.IDLE to BLE. TX transition time|–|120|140|s|–|
|IDLE2RX<br>~~po~~<br>~~po~~|BLE.IDLE to BLE. RX transition time|–|75|120|s|–|
|**RSSI Specifications**<br>~~po~~<br>~~po~~|||||||
|RSSI, ACC<br>~~po~~<br>~~po~~|RSSI accuracy|–|±5|–|dB|–|
|RSSI, RES<br>~~po~~<br>~~po~~<br>~~po~~|RSSI resolution|–|1|–|dB|–|
|RSSI, PER<br>~~po~~<br>~~po~~|RSSI sample period|–|6|–|s|–|



Document Number: 002-15631 Rev.*D 

Page 30 of 40 

**CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11** 

## **Environmental Specifications** 

## **Environmental Compliance** 

This Cypress BLE module is built in compliance with the Restriction of Hazardous Substances (RoHS) and Halogen Free (HF) directives. The Cypress module and components used to produce this module are RoHS and HF compliant. 

## **RF Certification** 

The CYBLE-212006-01 and CYBLE-202007-01 modules will be certified under the following RF certification standards at production release. 

■ FCC: WAP2006 

■ CE 

■ IC: 7922A-2006 

- MIC: 203-JN0599 

■ KC: MSIP-CRM-Cyp-2006 

## **Safety Certification** 

The CYBLE-212006-01 and CYBLE-202007-01 modules comply with the following regulations: 

■ Underwriters Laboratories, Inc. (UL) - Filing E331901 

■ CSA 

## ■ TUV 

## **Environmental Conditions** 

Table 54 describes the operating and storage conditions for the Cypress BLE module. 

## **Table 54.  Environmental Conditions for CYBLE-2X20XX-X1** 

|**Description**|**Minimum Specification**|**Maximum Specification**|
|---|---|---|
|Operating temperature|–40 °C|85 °C|
|Operating humidity (relative, non-condensation)|5%|85%|
|Thermal ramp rate|–|3 °C/minute|
|Storage temperature|–40 °C|85 °C|
|Storage temperature and humidity|–|85 ° C at 85%|
|ESD: Module integrated into system Components[13]|–|15 kV Air<br>2.2 kV Contact|



## **ESD and EMI Protection** 

Exposed components require special attention to ESD and electromagnetic interference (EMI). 

A grounded conductive layer inside the device enclosure is suggested for EMI and ESD performance. Any openings in the enclosure near the module should be surrounded by a grounded conductive layer to provide ESD protection and a low-impedance path to ground. 

**Device Handling** : Proper ESD protocol must be followed in manufacturing to ensure component reliability. 

**Note** 

13. This does not apply to the RF pins (ANT, XTALI, and XTALO). RF pins (ANT, XTALI, and XTALO) are tested for 500-V HBM. 

Document Number: 002-15631 Rev.*D 

Page 31 of 40 

**CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11** 

## **Regulatory Information** 

## **FCC** 

## FCC NOTICE: 

The devices CYBLE-212006-01 and CYBLE-202007-01 comply with Part 15 of the FCC Rules. The device meet the requirements for modular transmitter approval as detailed in FCC public Notice DA00-1407.transmitter Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation. 

## CAUTION: 

The FCC requires the user to be notified that any changes or modifications made to this device that are not expressly approved by Cypress Semiconductor may void the user's authority to operate the equipment. 

This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, ê may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures: 

■ Reorient or relocate the receiving antenna. 

■ Increase the separation between the equipment and receiver. 

■ Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. 

■ Consult the dealer or an experienced radio/TV technician for help 

## LABELING REQUIREMENTS: 

The Original Equipment Manufacturer (OEM) must ensure that FCC labelling requirements are met. This includes a clearly visible label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor FCC identifier for this product as well as the FCC Notice above. The FCC identifier is FCC ID: WAP2006. 

In any case the end product must be labeled exterior with “Contains FCC ID: WAP2006”. 

## ANTENNA WARNING: 

This device is tested with a standard SMA connector and with antennas meeting the characteristics shown in Table 7 on page 14. When integrated in the OEMs product, these fixed antennas require installation preventing end-users from replacing them with non-approved antennas. Any antenna not in the following table must be tested to comply with FCC Section 15.203 for unique antenna connectors and Section 15.247 for emissions. 

## RF EXPOSURE: 

To comply with FCC RF Exposure requirements, the Original Equipment Manufacturer (OEM) must ensure to install the approved antenna in the previous. 

The preceding statement must be included as a CAUTION statement in manuals, for products operating with the approved antennas in Table 6 and Table 7 on page 14, to alert users on FCC RF Exposure compliance. Any notification to the end user of installation or removal instructions about the integrated radio module is not allowed. 

The radiated output power of CYBLE-212006-01 with the trace antenna is far below the FCC radio frequency exposure limits. Nevertheless, use CYBLE-212006-01 in such a manner that minimizes the potential for human contact during normal operation. 

End users may not be provided with the module installation instructions. OEM integrators and end users must be provided with transmitter operating conditions for satisfying RF exposure compliance. 

Document Number: 002-15631 Rev.*D 

Page 32 of 40 

**CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11** 

## **Industry Canada (IC) Certification** 

CYBLE-212006-01 and CYBLE-202007-01 are licensed to meet the regulatory requirements of Industry Canada (IC), 

## License: IC: 7922A-2006 

Manufacturers of mobile, fixed or portable devices incorporating this module are advised to clarify any regulatory questions and ensure compliance for SAR and/or RF exposure limits. Users can obtain Canadian information on RF exposure and compliance from www.ic.gc.ca. 

This device has been designed to operate with the antennas listed in Table 6 and Table 7 on page 14, having a maximum gain of 2.2 dBi. Antennas not included in this list or having a gain greater than 2.2 dBi are strictly prohibited for use with this device. The required antenna impedance is 50 ohms. The antenna used for this transmitter must not be co-located or operating in conjunction with any other antenna or transmitter. 

## IC NOTICE: 

The device CYBLE-212006-01 including the built-in trace antenna complies with Canada RSS-GEN Rules. The device meets the requirements for modular transmitter approval as detailed in RSS-GEN. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation. 

## IC RADIATION EXPOSURE STATEMENT FOR CANADA 

This device complies with Industry Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device. For the CYBLE-202007-01, the SAR exemption distance is 15 mm. 

Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est autorisée aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement. Pour le CYBLE-202007-01, la SAR distance l'exemption est 15 mm. 

## LABELING REQUIREMENTS: 

The Original Equipment Manufacturer (OEM) must ensure that IC labelling requirements are met. This includes a clearly visible label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor IC identifier for this product as well as the IC Notice above. The IC identifier is 7922A-2006. In any case, the end product must be labeled in its exterior with "Contains IC: 7922A-2006" 

## **European R&TTE Declaration of Conformity** 

Hereby, Cypress Semiconductor declares that the Bluetooth module CYBLE-212006-01 and CYBLE-202007-01 comply with the essential requirements and other relevant provisions of Directive 1999/5/EC. As a result of the conformity assessment procedure described in Annex III of the Directive 1999/5/EC, the end-customer equipment should be labeled as follows: 

All versions of the CYBLE-212006-01 and CYBLE-202007-01 in the specified reference design can be used in the following countries: Austria, Belgium, Cyprus, Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, Poland, Portugal, Slovakia, Slovenia, Spain, Sweden, The Netherlands, the United Kingdom, Switzerland, and Norway. 

Document Number: 002-15631 Rev.*D 

Page 33 of 40 

**CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11** 

## **MIC Japan** 

CYBLE-212006-01 and CYBLE-202007-01 are certified as a module with type certification number 203-JN0599. End products that integrate CYBLE-212006-01 and CYBLE-202007-01 do not need additional MIC Japan certification for the end product. End product can display the certification label of the embedded module. 

## **KC Korea** 

CYBLE-212006-01 and CYBLE-202007-01 are certified for use in Korea with certificate number MSIP-CRM-Cyp-2006. 

Document Number: 002-15631 Rev.*D 

Page 34 of 40 

**CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11** 

## **Packaging** 

**Table 55.  Solder Reflow Peak Temperature** 

|**Module Part Number**|**Package**|**Maximum Peak Temperature**|**Maximum Time at Peak**<br>**Temperature**|**No. of Cycles**|
|---|---|---|---|---|
|CYBLE-2X20XX-X1|30-pad SMT|260 °C|30 seconds|2|



**Table 56.  Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2** 

|**Module Part Number**|**Package**|**MSL**|
|---|---|---|
|CYBLE-2X20XX-X1|30-pad SMT|MSL 3|



The CYBLE-2X20XX-X1 is offered in tape and reel packaging. Figure 11 details the tape dimensions used for the CYBLE-2X20XX-X1. 

**Figure 11.  CYBLE-2X20XX-X1 Tape Dimensions** 

Figure 12 details the orientation of the CYBLE-2X20XX-X1 in the tape as well as the direction for unreeling. 

**Figure 12.  Component Orientation in Tape and Unreeling Direction (Illustration Only)** 

Document Number: 002-15631 Rev.*D 

Page 35 of 40 

**CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11** 

Figure 13 details reel dimensions used for the CYBLE-2X20XX-X1. 

**Figure 13.  Reel Dimensions** 

The CYBLE-2X20XX-X1 is designed to be used with pick-and-place equipment in an SMT manufacturing environment. The center-of-mass for the CYBLE-2X20XX-X1 is detailed in Figure 14. 

**Figure 14.  CYBLE-2X20XX-X1 Center of Mass (Seen from Top)** 

**CYBLE-212006-01 Center of Mass CYBLE-202007-01 Center of Mass CYBLE-202013-11 Center of Mass** 

Document Number: 002-15631 Rev.*D 

Page 36 of 40 

**CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11** 

## **Ordering Information** 

Table 57 lists the CYBLE-2X20XX-X1 part numbers and features. 

## **Table 57.  Ordering Information** 

|**Part Number**<br>~~po~~|**CPU**<br>**Speed**<br>**(MHz)**|**Flash**<br>**Size**<br>**(KB)**|**CapSense**|**SCB**|**TCPWM**|**12-Bit**<br>**SAR**<br>**ADC**|**I2S**|**LCD**|**Package**|**Packing**|**Certified**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|CYBLE-212006-01<br>~~po~~<br>~~po~~|48|256|Yes|2|4|1 Msps Yes|1 Msps Yes|Yes|30-SMT|Tape and Reel|Yes|
|CYBLE-202007-01<br>~~po~~<br>~~po~~<br>~~Po~~|48|256|Yes|2|4|1 Msps Yes|1 Msps Yes|Yes|30-SMT|Tape and Reel|Yes|
|CYBLE-202013-11<br>~~po~~<br>~~Po~~|48|256|Yes|2|4|1 Msps Yes|1 Msps Yes|Yes|30-SMT|Tape and Reel|No|



**Table 58.  Tape and Reel Package Quantity and Minimum Order Amount** 

|**Description**|**Minimum Reel Quantity**|**Maximum Reel Quantity**|**Comments**|
|---|---|---|---|
|Reel Quantity|500|500|Ships in 500 unit reel quantities.|
|Minimum Order Quantity (MOQ)|500|–||
|Order Increment (OI)|500|–||



The CYBLE-2X20XX-X1 is offered in tape and reel packaging. The CYBLE-2X20XX-X1 ships with a maximum of 500 units/reel. 

## **Part Numbering Convention** 

The part numbers are of the form CYBLE-ABCDEF-GH where the fields are defined as follows. 

For additional information and a complete list of Cypress Semiconductor BLE products, contact your local Cypress sales representative. To locate the nearest Cypress office, visit our website. 

|U.S. Cypress Headquarters Address|198 Champion Court, San Jose, CA 95134|
|---|---|
|U.S. Cypress Headquarter Contact Info|(408) 943-2600|
|Cypress website address|http://www.cypress.com|



Document Number: 002-15631 Rev.*D 

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**CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11** 

## **Acronyms** 

## **Table 59.  Acronyms Used in this Document** 

|**Acronym**|**Description**|
|---|---|
|BLE|Bluetooth Low Energy|
|Bluetooth<br>SIG|Bluetooth Special Interest Group|
|CE|European Conformity|
|CSA|Canadian Standards Association|
|EMI|electromagnetic interference|
|ESD|electrostatic discharge|
|FCC|Federal Communications Commission|
|GPIO|general-purpose input/output|
|IC|Industry Canada|
|IDE|integrated design environment|
|KC|Korea Certification|
|MIC|Ministry of Internal Affairs and Communications<br>(Japan)|
|PCB|printed circuit board|
|RX|receive|
|QDID|qualification design ID|
|SMT|surface-mount technology; a method for producing<br>electronic circuitry in which the components are<br>placed directly onto the surface of PCBs|
|TCPWM|timer, counter, pulse width modulator (PWM)|
|TUV|Germany: Technischer Überwachungs-Verein<br>(Technical Inspection Association)|
|TX|transmit|



## **Document Conventions** 

## **Units of Measure** 

## **Table 60.  Units of Measure** 

|**Symbol**|**Unit of Measure**|
|---|---|
|°C|degree Celsius|
|kV|kilovolt|
|mA|milliamperes|
|mm|millimeters|
|mV|millivolt|
|A|microamperes|
|m|micrometers|
|MHz|megahertz|
|GHz|gigahertz|
|V|volt|



Document Number: 002-15631 Rev.*D 

Page 38 of 40 

**CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11** 

## **Document History Page** 

**Document Title: CYBLE-212006-01, CYBLE-202007-01, CYBLE-202013-11 EZ-BLE™ PRoC™  XR Module Document Number: 002-15631** 

|**Document Title: CYBLE-212006-01, CYBLE-202007-01, CYBLE-202013-11 EZ-BLE™ PRoC™  XR Module**<br>**Document Number: 002-15631**|**Document Title: CYBLE-212006-01, CYBLE-202007-01, CYBLE-202013-11 EZ-BLE™ PRoC™  XR Module**<br>**Document Number: 002-15631**|**Document Title: CYBLE-212006-01, CYBLE-202007-01, CYBLE-202013-11 EZ-BLE™ PRoC™  XR Module**<br>**Document Number: 002-15631**|**Document Title: CYBLE-212006-01, CYBLE-202007-01, CYBLE-202013-11 EZ-BLE™ PRoC™  XR Module**<br>**Document Number: 002-15631**|**Document Title: CYBLE-212006-01, CYBLE-202007-01, CYBLE-202013-11 EZ-BLE™ PRoC™  XR Module**<br>**Document Number: 002-15631**|
|---|---|---|---|---|
|**Revision**|**ECN**|**Orig. of**<br>**Change**|**Submission**<br>**Date**|**Description of Change**|
|**|5446955|DSO|10/07/2016|Preliminary datasheet for CYBLE-2X20XX-X1 modules.|
|*A|5536076|DSO|11/29/2016|UpdatedMore Information:<br>AddedEZ-Serial™ BLE Firmware Platformsection.<br>UpdatedOverview:<br>Added Bluetooth Declaration ID and QDID under “Bluetooth 4.2 qualified<br>single-mode module”<br>UpdatedRecommended Host PCB Layout:<br>UpdatedFigure 4,Figure 5, andFigure 6captions to specify that these as<br>“Seen on Host PCB”.<br>UpdatedPower Supply Connections and Recommended External Compo-<br>nents:<br>UpdatedFigure 7andFigure 8to specify that these are “Seen from Bottom”.<br>UpdatedDigital and Analog Capabilities and Connections:<br>UpdatedTable 4:<br>Updated TCPWM column to add TCPWM capability on Port 2 pins.<br>Added Footnote 5.|
|*B|5554670|DSO|12/15/2016|UpdatedMore Information:<br>Added hyperlinks for Evaluation Board listed under Development Kits<br>UpdatedEnabling Extended Range Feature:<br>UpdatedSAR ADC:<br>UpdatedTable 21to add Note 10 to specify under what conditions the<br>maximum number of ADC channels can be achieved.|
|*C|5667227|DSO|03/21/2017|Changed status from “Preliminary” to “Final”.<br>AddedAntenna Matching Network Requirements for CYBLE-202013-11<br>section.<br>UpdatedTable 53to update specifications for RX, TX, and module power<br>consumption.<br>UpdatedFigure 14to add Center of Mass for CYBLE-212006-01.|
|*D|5705684|AESATMP7|04/21/2017|Updated Cypress Logo and Copyright.|



Document Number: 002-15631 Rev.*D 

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**CYBLE-212006-01 CYBLE-202007-01 CYBLE-202013-11** 

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Document Number: 002-15631 Rev.*D 

Page 40 of 40 

Revised April 21, 2017