CSD25201W15

**CSD25201W15** 

SLPS269A – JUNE 2010 – REVISED JULY 2011 

**www.ti.com** 

## **P-Channel NexFET** ™ **Power MOSFET** 

**Check for Samples: CSD25201W15** 

## **1FEATURES** 

- **Low Resistance** 

- **Small Footprint 1.5-mm** × **1.5-mm** 

- **Gate ESD Protection** – **3kV** 

- **Pb Free** 

- **RoHS Compliant** 

- **Halogen Free** 

## **PRODUCT SUMMARY** 

|VDS|Drain to Drain Voltage|–20|–20|V|
|---|---|---|---|---|
|Qg|Gate Charge Total (–4.5V)|4.3||nC|
|Qgd|Gate Charge Gate to Drain|0.7||nC|
|RDS(on)|Drain to Source On Resistance|VGS =–1.8V|52|mΩ|
|||VGS=–2.5V|42|mΩ|
|||VGS=–4.5V|33|mΩ|
|VGS(th)|Threshold Voltage|–0.7||V|



- **Gate-Source Voltage Clamp** 

## **APPLICATIONS** 

- **Battery Management** 

- **Battery Protection** 

|**Device**|**Package**|**Media**|**Qty**|**Ship**|
|---|---|---|---|---|
|CSD25201W15|1.5-mm× 1.5-mm<br>Wafer Level Package|7-Inch<br>Reel|3000|Tape and<br>Reel|



## **DESCRIPTION** 

The device has been designed to deliver the lowest on resistance and gate charge in the smallest outline possible with excellent thermal characteristics in an ultra low profile. Low on resistance coupled with the small footprint and low profile make the device ideal for battery operated space constrained applications. 

**==> picture [150 x 97] intentionally omitted <==**

**----- Start of picture text -----**<br>
Top View Symbol<br>Pin A1 Indicator<br>Source<br>G D S<br>Gate<br>D D S<br>Crene<br>D S S Drain<br>COO ©)<br>P0117-01<br>**----- End of picture text -----**<br>


## **ABSOLUTE MAXIMUM RATINGS** 

|TA= 25°C unless otherwise stated|TA= 25°C unless otherwise stated|**VALUE**|**UNIT**|
|---|---|---|---|
|VDS|Drain to Source Voltage|–20|V|
|VGS|Gate to Source Voltage|–6|V|
|ID|Continuous Drain Current(1)(2)|4|A|
||Pulsed Drain Current(1)(2)|4|A|
|IG|Continuous Gate Current(1)(2)|0.5|A|
||Pulsed Gate Current(1)(2)|7|A|
|PD|Power Dissipation(1)|1.5|W|
|TJ,<br>TSTG|Operating Junction and Storage<br>Temperature Range|–55 to 150|°C|



(1) Based on Min Cu footprint 

(2) Ball limited 

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RDS(on) vs VGS<br>**----- End of picture text -----**<br>


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100<br>90 I D  = -2A<br>80<br>70 T J  = 125°C<br>60<br>50<br>40<br>30 T J = 25°C<br>20<br>10<br>0<br>0 1 2 3 4 5 6<br>-VGS - Gate-to-Source Voltage - V G006<br>Ω<br> - On-State Resistance - m<br>DS(on)<br>R<br>**----- End of picture text -----**<br>


## **GATE CHARGE** 

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4.5<br>4 ID = -2A<br>VDS = -10V<br>3.5<br>3<br>2.5<br>2<br>1.5<br>1<br>0.5<br>0<br>0 0.5 1 1.5 2 2.5 3 3.5 4 4.5<br>Qg - Gate Charge - nC G003<br> - Gate-to-Source Voltage - V<br>GS<br>-V<br>**----- End of picture text -----**<br>


Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. 

Copyright © 2010 – 2011, Texas Instruments Incorporated 

**CSD25201W15** 

SLPS269A – JUNE 2010 – REVISED JULY 2011 

**www.ti.com** 

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 

## **ELECTRICAL CHARACTERISTICS** 

|**ELECTRICAL CHARACTERISTICS**<br>(TA = 25°C unless otherwise stated)||||
|---|---|---|---|
|**PARAMETER**<br>~~a~~|**TEST CONDITIONS**|**MIN**<br>**TYP**<br>**MAX**|**UNIT**|
|**Static Characteristics**<br>~~a~~<br>~~Ce~~||||
|BVDSS<br>Drain to Source Voltage<br>~~Ce~~<br>~~a~~|VGS = 0V, IDS =–250μA<br>~~Ce~~<br>~~a~~|–20<br>~~Ce~~<br>~~a~~|V<br>~~Ce~~<br>~~a~~|
|BVGSS<br>Gate to Source Voltage<br>~~a~~<br>~~a~~|VDS = 0V, IG =–250μA<br>~~a~~<br>~~a~~|–6.1<br>–7.2<br>~~a~~<br>~~a~~|V<br>~~a~~<br>~~a~~|
|IDDS<br>Drain to Source Leakage Current<br>~~a~~<br>~~a~~|VGS = 0V, VDS =–16V<br>~~a~~<br>~~a~~|–1<br>~~a~~<br>~~a~~|μA<br>~~a~~<br>~~a~~|
|IGSS<br>Gate to Source Leakage Current<br>~~a~~<br>~~a~~|VDS = 0V, VGS =–6V<br>~~a~~<br>~~a~~|–100<br>~~a~~<br>~~a~~|nA<br>~~a~~<br>~~a~~|
|VGS(th)<br>Gate to Source Threshold Voltage<br>~~a~~<br>~~a~~|VDS = VGS, IDS =–250μA<br>~~a~~<br>~~a~~|–0.4<br>–0.7<br>–1.1<br>~~a~~<br>~~a~~|V<br>~~a~~<br>~~a~~|
|RDS(on)<br>Drain to Source On Resistance<br>~~a~~<br>~~a~~|VGS =–1.8V, IDS =–2A<br>~~a~~<br>~~a~~<br>~~a~~|52<br>70<br>~~a~~<br>~~a~~<br>|mΩ<br>~~a~~<br>~~a~~<br>|
||VGS =–2.5V, IDS =–2A<br>~~a~~<br>~~a~~|42<br>50<br>~~a~~<br>|mΩ<br>~~a~~<br>|
||VGS =–4.5V, IDS =–2A<br>~~aa~~|33<br>40<br>~~a~~|mΩ<br>~~a~~|
|gfs<br>Transconductance<br><br>~~a~~|VDS =–10V, IDS =–2A<br>~~a~~|12<br>~~a~~|S<br>~~a~~|
|**Dynamic Characteristics**<br>~~a~~<br>~~Ce~~<br>~~PO~~<br>~~ee~~<br>~~ee~~<br>~~PO~~||||
|CISS<br>Input Capacitance<br>~~Ce~~<br>~~PO~~<br>~~PO~~|VGS= 0V, VDS=–10V,<br>f = 1MHz<br>~~Ce~~|490<br>640<br>~~Ce~~<br>~~ee~~|pF<br>~~Ce~~<br>~~ee~~<br>~~ee~~|
|COSS<br>Output Capacitance<br>~~PO~~<br>~~PO~~<br>~~PO~~||215<br>280<br>~~ee~~<br>~~PT~~|pF<br>~~ee~~<br>~~ee~~<br>~~PT~~<br>~~ee~~|
|CRSS<br>Reverse Transfer Capacitance<br>~~PO~~<br>~~PO~~||70<br>91<br>~~PT~~<br>~~ee~~|pF<br>~~ee~~<br>~~PT~~<br>~~ee~~<br>~~ee~~|
|RG<br>Series Gate Resistance(1)<br>~~PO~~<br>~~a~~<br>~~PO~~|~~a~~|26<br>35<br>~~PT~~<br>~~ee~~<br>~~a~~<br>~~ee~~|Ω<br>~~PT~~<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~ee~~|
|Qg<br>Gate Charge Total(–4.5V)<br>~~a~~<br>~~PO~~<br>~~PO~~|VDS=–10V,<br>IO=–2A<br>~~a~~|4.3<br>5.6<br>~~a~~<br>~~ee~~<br>~~PT~~|nC<br>~~a~~<br>~~ee~~<br>~~PT~~|
|Qgd<br>Gate Charge - Gate to Drain<br>~~PO~~<br>~~PO~~<br>~~PO~~||0.7<br>~~ee~~<br>~~PT~~<br>~~PT~~|nC<br>~~ee~~<br>~~PT~~<br>~~PT~~|
|Qgs<br>Gate Charge - Gate to Source<br>~~PO~~<br>~~PO~~<br>~~PO~~||1<br>~~PT~~<br>~~PT~~<br>~~ee~~|nC<br>~~PT~~<br>~~PT~~<br>~~ee~~<br>~~ee~~|
|Qg(th)<br>Gate Charge at Vth<br>~~PO~~<br>~~PO~~||0.3<br>~~PT~~<br>~~ee~~|nC<br>~~PT~~<br>~~ee~~<br>~~ee~~|
|QOSS<br>Output Charge<br>~~PO~~<br>~~a~~<br>~~PO~~|VDS =–9.5V, VGS = 0V<br>~~a~~|3.1<br>~~ee~~<br>~~a~~<br>~~ee~~|nC<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~ee~~|
|td(on)<br>Turn On Delay Time(2)<br>~~a~~<br>~~PO~~<br>~~PO~~|VDS=–10V, VGS=–4.5V,<br>IDS=–2A, RG= 2Ω<br>~~a~~|9.5<br>~~a~~<br>~~ee~~<br>~~PT~~|ns<br>~~a~~<br>~~ee~~<br>~~PT~~|
|tr<br>Rise Time(2)<br>~~PO~~<br>~~PO~~<br>~~PO~~||11<br>~~ee~~<br>~~PT~~<br>~~PT~~|ns<br>~~ee~~<br>~~PT~~<br>~~PT~~|
|td(off)<br>Turn Off Delay Time(2)<br>~~PO~~<br>~~PO~~<br>~~PO~~||51<br>~~PT~~<br>~~PT~~<br>~~pr~~|ns<br>~~PT~~<br>~~PT~~<br>~~pr~~|
|tf<br>Fall Time(2)<br>~~PO~~<br>~~PO~~||38<br>~~PT~~<br>~~pr~~|ns<br>~~PT~~<br>~~pr~~|
|**Diode Characteristics**<br>~~PO~~<br>~~pr~~<br>~~Ce~~||||
|VSD<br>Diode Forward Voltage<br>~~Ce~~<br>~~a~~|IDS =–2A, VGS = 0V<br>~~Ce~~|0.7<br>1<br>~~Ce~~|V<br>~~Ce~~|
|Qrr<br>Reverse RecoveryCharge<br>~~a~~<br>~~J~~<br>~~PO~~|VDD=–9.5V, IF=–2A,<br>di/dt = 200A/μs|5.7<br>~~Po~~|nC<br>~~Po~~|
|trr<br>Reverse RecoveryTime<br>~~J~~<br>~~PO~~||10<br>~~Po~~|ns<br>~~Po~~|



(1) Includes gate clamp resistor (2) External RG is in addition to the internal gate clamp resistor 

## **THERMAL CHARACTERISTICS** 

° (TA = 25 C unless otherwise stated) 

|**THERMAL CHARACTERISTICS**<br>(TATAA = 25°C unless otherwise stated))|**THERMAL CHARACTERISTICS**<br>(TATAA = 25°C unless otherwise stated))|||
|---|---|---|---|
|**PARAMETER**||**MIN**<br>**TYP**<br>**MAX**|**UNIT**|
|RθJA|Junction to Ambient Thermal Resistance(1)|283|°C/W|
||Junction to Ambient Thermal Resistance(2)|185|°C/W|



(1) Device mounted on FR4 material with minimum Cu mounting area. 

(2) Device mounted on FR4 material with 1-inch[2] (6.45-cm[2] ), 2-oz. (0.071-mm thick) Cu. 

2 

Copyright © 2010 – 2011, Texas Instruments Incorporated 

**CSD25201W15** 

SLPS269A – JUNE 2010 – REVISED JULY 2011 

**www.ti.com** 

**==> picture [129 x 132] intentionally omitted <==**

Max R θ JA = 185 ° C/W when mounted on 1 inch[2] (6.45 cm[2] ) of 2-oz. (0.071-mm thick) Cu. M0149-01 M0150-01 

Max R θ JA = 283 ° C/W when mounted on a minimum pad area of 2-oz. (0.071-mm thick) Cu. 

## **TYPICAL MOSFET CHARACTERISTICS** 

TA = 25 ° C, unless stated otherwise. 

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10<br>1<br> 0.5<br> 0.3<br>0.1  0.1<br> 0.05<br>Duty Cycle = t1/t2<br> 0.02<br>0.01  0.01  P<br> Single Pulse   t 1 t2<br>0.001<br>Typical R�JA = 227�C/W (min Cu)<br>T J  = P � Z �JA � R �JA<br>0.0001<br>0.0001 0.001 0.01 0.1 1 10 100 1k<br>t  - Pulse Duration - s<br>p<br>G012<br> - Normalized Thermal Impedance<br>JA<br>�<br>Z<br>**----- End of picture text -----**<br>


**Figure 1. Transient Thermal Impedance** 

3 

Copyright © 2010 – 2011, Texas Instruments Incorporated 

**CSD25201W15** 

SLPS269A – JUNE 2010 – REVISED JULY 2011 

**www.ti.com** 

## **TYPICAL MOSFET CHARACTERISTICS (continued)** 

TA = 25 ° C, unless stated otherwise. 

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10<br>9<br>8<br>VGS = -4.5V<br>7<br>6<br>VGS = -4.0V<br>5<br>4 VGS = -3.0V<br>3 VGS = -2.5V<br>2<br>1 VGS = -1.5V<br>0<br>0 0.25 0.5 0.75 1<br>-VDS - Drain-to-Source Voltage - V G001<br>Figure 2. Saturation Characteristics<br>4.5<br>4 ID = -2A<br>VDS = -10V<br>3.5<br>3<br>2.5<br>2<br>1.5<br>1<br>0.5<br>0<br>0 0.5 1 1.5 2 2.5 3 3.5 4 4.5<br>Qg - Gate Charge - nC G003<br>Figure 4. Gate Charge<br>1<br>0.9 I D  = -250µA<br>0.8<br>0.7<br>0.6<br>0.5<br>0.4<br>0.3<br>0.2<br>0.1<br>0<br>-75 -25 25 75 125 175<br>TJ - Junction Temperature -  °C G005<br> - Drain-to-Source Current - A<br>DS<br>-I<br> - Gate-to-Source Voltage - V<br>GS<br>-V<br> - Threshold Voltage - V<br>GS(th)<br>-V<br>**----- End of picture text -----**<br>


**Figure 6. Threshold Voltage vs. Temperature** 

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10<br>9 V DS  = -5V<br>8<br>7<br>6<br>5<br>4 TJ = 125°C<br>3<br>2 TJ = 25°C<br>1 TJ = -55°C<br>0<br>0.5 0.75 1 1.25 1.5 1.75<br>-VGS - Gate-to-Source Voltage - V G002<br> - Drain-to-Source Current - A<br>DS<br>-I<br>**----- End of picture text -----**<br>


**Figure 3. Transfer Characteristics** 

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1k<br>C iss = C gd + C gs<br>100 Coss = Cds + Cgd<br>Crss = Cgd<br>f = 1MHz<br>VGS = 0V<br>10<br>0 5 10 15 20<br>-VDS - Drain-to-Source Voltage - V G004<br>Figure 5. Capacitance<br>100<br>90 I D  = -2A<br>80<br>70 T J  = 125°C<br>60<br>50<br>40<br>30 T J = 25°C<br>20<br>10<br>0<br>0 1 2 3 4 5 6<br>-VGS - Gate-to-Source Voltage - V G006<br>C - Capacitance - pF C - Capacitance - nF<br>Ω<br> - On-State Resistance - m<br>DS(on)<br>R<br>**----- End of picture text -----**<br>


**Figure 7. On-State Resistance vs. Gate-to-Source Voltage** 

4 

Copyright © 2010 – 2011, Texas Instruments Incorporated 

**CSD25201W15** 

SLPS269A – JUNE 2010 – REVISED JULY 2011 

**www.ti.com** 

## **TYPICAL MOSFET CHARACTERISTICS (continued)** 

TA = 25 ° C, unless stated otherwise. 

**==> picture [486 x 354] intentionally omitted <==**

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1.6 10<br>ID = -2A<br>1.4 VGS = -4.5V<br>1.2 1<br>1 T C  = 125°C<br>0.8 0.1 TC = 25°C<br>0.6<br>0.4 0.01<br>0.2<br>0 0.001<br>-75 -25 25 75 125 175 0 0.2 0.4 0.6 0.8 1<br>TJ - Junction Temperature -  °C G007 -VSD - Source-to-Drain Voltage - V G008<br>Figure 8. Normalized On-State Resistance vs. Temperature Figure 9. Typical Diode Forward Voltage<br>10 4.5<br>4<br>1ms<br>3.5<br>1<br>3<br>10ms<br>2.5<br>0.1<br>2<br>1 111000ms<br>Area Limited 1s 1.5<br>0.01 by RDS(on) DC 1<br>Single Pulse<br>Typical R θJA  = 227°C/W (min Cu) 0.5<br>0.001 0<br>0.01 0.1 1 10 100 -50 -25 0 25 50 75 100 125 150 175<br>-VDS - Drain-to-Source Voltage - V G009 TJ - Junction Temperature -  °C G011<br> - Source-to-Drain Current - A<br>SD<br>Normalized On-State Resistance -I<br> - Drain-to-Source Current - A  - Drain-to-Source Current - A<br>-IDS -IDS<br>**----- End of picture text -----**<br>


**Figure 10. Maximum Safe Operating Area** 

**Figure 11. Maximum Drain Current vs. Temperature** 

5 

Copyright © 2010 – 2011, Texas Instruments Incorporated 

**CSD25201W15** 

SLPS269A – JUNE 2010 – REVISED JULY 2011 

**www.ti.com** 

## **MECHANICAL DATA** 

## **CSD25201W15 Package Dimensions** 

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Pin�1 Solder�Ball<br>Mark Ø�0.31 ±0.075<br>1 2 3 3 2 1<br>A A<br>B B<br>C C<br>1.50 [+0.00] –0.08 0.62�Max 0.50<br>Top�View Side�View Bottom�View<br>Seating�Plate<br>0.50<br>+0.00 –0.08<br>1.00<br>1.50<br>0.35 ±0.10<br>0.04<br>0.62�Max<br>**----- End of picture text -----**<br>


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Front�View<br>**----- End of picture text -----**<br>


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M0171-01<br>**----- End of picture text -----**<br>


NOTE: All dimensions are in mm (unless otherwise specified) 

|**Pinout**|**Pinout**|
|---|---|
|**POSITION**|**DESIGNATION**|
|A1|Gate|
|A2, B1, B2, C1|Drain|
|A3, B3, C2, C3|Source|



6 

Copyright © 2010 – 2011, Texas Instruments Incorporated 

**CSD25201W15** 

SLPS269A – JUNE 2010 – REVISED JULY 2011 

**www.ti.com** 

## **Recommended Land Pattern** 

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**----- Start of picture text -----**<br>
�0.25<br>1 2 3<br>A<br>B<br>C<br>0.50<br>M0172-01<br>0.50<br>1.00<br>**----- End of picture text -----**<br>


NOTE: All dimensions are in mm (unless otherwise specified) 

## **Tape and Reel Information** 

**==> picture [494 x 267] intentionally omitted <==**

**----- Start of picture text -----**<br>
4.00�±0.10 2.00�±0.05 Ø�1.50�±0.10<br>5°�Max<br>4.00�±0.10 Ø�0.50�±0.05<br>0.86�±0.05 0.254�±0.02<br>5°�Max<br>1.60�±0.05<br>M0173-01<br>+0.30 –0.10<br>8.00 1.75�±0.10<br>3.50�±0.05<br>1.60�±0.05<br>**----- End of picture text -----**<br>


NOTES: 1. 10-sprocket hole-pitch cumulative tolerance ± 0.2 

2. Camber not to exceed 1mm in 100mm, noncumulative over 250mm 

3. Material: black static-dissipative polystyrene 

4. All dimensions are in mm (unless otherwise specified) 

5. Thickness: 0.30 ± 0.05mm 

6. MSL1 260 ° C (IR and convection) PbF reflow compatible 

7 

Copyright © 2010 – 2011, Texas Instruments Incorporated 

**CSD25201W15** 

SLPS269A – JUNE 2010 – REVISED JULY 2011 

**www.ti.com** 

## **REVISION HISTORY** 

|**Changes from Original (June 2010) to Revision A**<br>**Page**|
|---|
|•<br>Changed the CISSInput Capacitance Typ and Max Values From: 390 and 510 pF To: 490 and 640 pF ............................ 2|



8 

Copyright © 2010 – 2011, Texas Instruments Incorporated 

## **PACKAGE OPTION ADDENDUM** 

www.ti.com 

7-Jan-2016 

## **PACKAGING INFORMATION** 

|**Orderable Device**|**Status**|**Package Type**|**Package**|**Pins**|**Package**|**Eco Plan**|**Lead/Ball Finish**|**MSL Peak Temp**|**Op Temp (°C)**|**Device Marking**|**Samples**|
|---|---|---|---|---|---|---|---|---|---|---|---|
||(1)||**Drawing**||**Qty**|(2)|(6)|(3)||(4/5)||
|CSD25201W15|OBSOLETE<br>DSBGA||YZF|9||TBD|Call TI|Call TI|-55 to 150|||



> **(1)** The marketing status values are defined as follows: 

**ACTIVE:** Product device recommended for new designs. 

**LIFEBUY:** TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. 

**NRND:** Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. **PREVIEW:** Device has been announced but is not in production. Samples may or may not be available. 

**OBSOLETE:** TI has discontinued the production of the device. 

> **(2)** Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. 

**TBD:** The Pb-Free/Green conversion plan has not been defined. 

**Pb-Free (RoHS):** TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. **Pb-Free (RoHS Exempt):** This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based  die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. 

**Green (RoHS & no Sb/Br):** TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br)  and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) 

> **(3)** MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. 

> **(4)** There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. 

> **(5)** Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. 

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**Important Information and Disclaimer:** The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. 

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Addendum-Page 1 

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TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and services. 

Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. 

Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will thoroughly test such applications and the functionality of such TI products as used in such applications. 

TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information, including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource solely for this purpose and subject to the terms of this Notice. 

TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections, enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically described in the published documentation for a particular TI Resource. Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. 

TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM, INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL, DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. 

Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949 and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements. 

Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use. Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S. 

TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product). Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory requirements in connection with such selection. 

Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s noncompliance with the terms and provisions of this Notice. 

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