AS7343L-DLGM

## **Datasheet** 

DS001038 

## **AS7343L** 

## **13-Channel Multi-Spectral Sensor** 

v2-00 • 2022-Aug-12 

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AS7343L Content Guide 

## **Content Guide** 

|**1**|**General Description ...................... 3**|
|---|---|
|1.1|Key Benefits & Features ............................... 3|
|1.2|Applications .................................................. 4|
|1.3|Block Diagram .............................................. 4|
|**2**|**Ordering Information .................... 5**|
|**3**|**Pin Assignment ............................. 6**|
|3.1|Pin Diagram .................................................. 6|
|3.2|Pin Description ............................................. 6|
|**4**|**Absolute Maximum Ratings ......... 8**|
|**5**|**Electrical Characteristics.............. 9**|
|**6**|**Optical Characteristics ............... 10**|
|**7**|**Typical Operating**|
||**Characteristics ............................ 14**|
|**8**|**Functional Description................ 15**|
|8.1<br>8.2|Device Architecture .................................... 16<br>Sensor Array ............................................... 17|
|8.3<br>8.4|GPIO ........................................................... 17<br>Interrupt (INT) ............................................. 17|
|8.5|LED Driver (LDR) ....................................... 17|
|**9**|**I²C Interface .................................. 18**|



|9.1|I²C Address ................................................. 18|
|---|---|
|9.2|I²C Write Transaction .................................. 18|
|9.3|I²C Read Transaction ................................. 19|
|9.4|Timing Characteristics ................................ 19|
|9.5|Timing Diagrams ........................................ 20|
|**10**|**Register Description .................... 21**|
|10.1|Register Overview ...................................... 21|
|10.2|Detailed Register Description ..................... 24|
|**11**|**Application Information ............... 44**|
|11.1|Schematic ................................................... 44|
|11.2|PCB Pad Layout ......................................... 44|
|11.3|Application Optical Requirements .............. 45|
|**12**|**Package Drawings & Markings ... 46**|
|**13**|**Tape & Reel Information .............. 47**|
|**14**|**Soldering & Storage Information 49**|
|14.1|Storage Information .................................... 50|
|**15**|**Revision Information ................... 51**|
|**16**|**Legal Information ......................... 52**|



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AS7343L General Description 

## **1 General Description** 

The ams OSRAM AS7343L[1] is a 13-channel spectrometer designed for spectral identification of lateral flow particle markers. It is highly versatile sensor targeted to enable new laboratory applications. It is optimized for reflective, transmissive and emissive measurements including lateral flow test applications, fluid or reagent analysis, color matching, and spectral identification in the visible range. 

13 individual channels cover the spectral range from approximately 380 nm to 1000 nm. 11 channels are centered in the visible spectrum (VIS), plus one near-infrared (NIR) and a clear channel. Allowing a full spectral re-construction of the incoming light. 

AS7343L integrates high-precision optical filters onto standard CMOS silicon via deposited interference filter technology. A built-in aperture controls the light entering the sensor array to increase accuracy. A programmable digital GPIO and LED driver enable light source and trigger/sync control. Device control and spectral data access is implemented through a serial I²C interface. The device is available in an ultra-low profile package with dimensions of 3.1 mm x 2 mm x 1 mm. 

## 1.1 Key Benefits & Features 

The benefits and features of AS7343L, 13-Channel Multi-Spectral Sensor, are listed below: 

## **Figure 1:** 

## **Added Value of Using AS7343L** 

|**Benefits**|**Features**|
|---|---|
||●13 channels between 380 nm and 1000 nm|
|Highly versatile spectral sensor|●Reflective, transmissive and emissive applications<br>●Fluorescence and luminescence measurements|
||●Spectral re-construction|
||●Enables ultra-low light operation|
|Highest sensitivity|(e.g. chemiluminescence applications)<br>●Enables operation behind additional external|
||filters|
|Low power consumption and minimum I²C<br>traffic|●1.8 V VDD operation<br>●Configurable sleep mode|
||●Interrupt-driven device|
||●On chip interference filter technology|
|Ultra-high integration|●Integrated LED driver and 6 integrated ADCs|
||●3.1 mm x 2 mm x 1 mm package outline|



> 1 L = Lateral flow 

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AS7343L General Description 

|**Benefits**|**Features**|
|---|---|
|Electronic shutter/external trigger|GPIO can be configured to function as external|
|functionality|trigger input to enable fluorescence measurements|



## 1.2 Applications 

- Multi-analyte detection 

- Fluorescent-based measurement applications 

- Luminescence-based measurement applications 

- Reflection- or transmissivity-based color detection (e.g. lateral flow strips) 

## 1.3 Block Diagram 

The functional blocks of this device are shown below: 

## **Figure 2:** 

## **Functional Blocks of AS7343L** 

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**----- Start of picture text -----**<br>
1.8V VLED<br>VDD<br>LED<br>PGND (opt.)<br>AS7343L<br>GND LDR<br>1.8V<br>13CH<br>Spectral<br>Sensor<br>SCL<br>380-1000nm<br>MCU<br>SDA<br>INT GPIO<br>Trig/Sync<br>**----- End of picture text -----**<br>


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AS7343L Ordering Information 

## **2 Ordering Information** 

|**Ordering Code**|**Package**|**Delivery Form**|**Delivery Quantity**|
|---|---|---|---|
|AS7343L-DLGT|OLGA-8|Tape & Reel 13-inch|5000 pcs/reel|
|AS7343L-DLGM|OLGA-8|Tape & Reel 7-inch|500 pcs/reel|



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AS7343L Pin Assignment 

## **3 Pin Assignment** 

## 3.1 Pin Diagram 

**Figure 3: Pin Assignment of AS7343L (TOP VIEW)** 

**==> picture [191 x 218] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDD 1 8 SDA<br>SCL 2 7 INT<br>TOP VIEW<br>GND 3 6 GPIO<br>LDR 4 5 PGND<br>**----- End of picture text -----**<br>


## 3.2 Pin Description 

## **Figure 4:** 

**Pin Description of AS7343L** 

|**Pin Number**|**Pin Name**|**Pin Type(1)**|**Description**|
|---|---|---|---|
|1|VDD|P|Positive supply voltage terminal|
|2|SCL|DI|Serial interface clock signal line for I²C interface.<br>Connect pull up resistor to 1.8 V.|
|3|GND|P|Ground. All voltages referenced to GND|
|4|LDR|A_I/O|LED current sink input. If not used leave pin unconnected.|
|5|PGND|P|Ground. All voltages referenced to GND|
|6|GPIO|D_I/O|General purpose input/output. Default output open drain. If not<br>used leave pin unconnected.|
|7|INT|DO_OD|Interrupt. Open drain output active low. Connect pull up resistor<br>to 1.8 V. If not used leave pin unconnected.|



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AS7343L Pin Assignment 

|**Pin**|**Number**|**Pin Name**|**Pin Type(1)**|**Description**|
|---|---|---|---|---|
|8||SDA|D_I/O|Serial interface data signal line for I²C interface.<br>Connect pull up resistor to 1.8 V.|
|(1)|Explanation|of abbreviations:|||
||DI|Digital Input|||
||D_I/O|Digital Input/Output|||
||DO_OD|Digital Output, open drain|||
||P|Power pin|||
||A_I/O|Analog pin|||



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AS7343L Absolute Maximum Ratings 

## **4 Absolute Maximum Ratings** 

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under “Operating Conditions” is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All voltages with respect to GND/PGND. Device parameters are guaranteed at VDD=1.8 V and TA=25 °C unless otherwise noted. 

## **Figure 5:** 

## **Absolute Maximum Ratings of AS7343L** 

|**Symbol**|<br>**Parameter**|**Min**|||**Max**|**Unit**|**Comments**|
|---|---|---|---|---|---|---|---|
|**Electrical**|**Parameters**|||||||
|VDD/ VGND|Supply Voltage to Ground|-0.3|||1.98|V|Applicable for pin VDD|
|VANA_MAX|Analog Pins|-0.3|||3.6|V|Applicable for pin LDR|
|VDIG_MAX|Digital Pins|-0.3|||3.6|V|Applicable for pins<br>SCL,SDA,GPIO and INT|
|ISCR|Input Current (latch-up<br>immunity)||±|100||mA|AEC-Q100-004E|
|IO|Output Terminal Current|-1|||20|mA||
|**Electrostatic Discharge**||||||||
|ESDHBM|Electrostatic Discharge HBM||± 2000|||V|JS-001-2017|
|ESDCDM|Electrostatic Discharge CDM||±|500||V|JS-002-2018|
|**Temperature Ranges and Storage Conditions**||||||||
|TA|Operating Ambient Temperature|<br>-30|||85|°C||
|TSTRG|Storage Temperature Range|-40|||85|°C||
|TBODY|Package Body Temperature||||260|°C|IPC/JEDEC J-STD-020(1)|
|RHNC|Relative Humidity (non-<br>condensing)|5|||85|%||
|MSL|Moisture Sensitivity Level|||3|||Maximum floor life time of 168h|



(1) The reflow peak soldering temperature (body temperature) is specified according to IPC/JEDEC J-STD-020 “Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.” The lead finish for Pbfree leaded packages is “Matte Tin” (100% Sn) 

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AS7343L Electrical Characteristics 

## **5** 

## **Electrical Characteristics** 

All limits are guaranteed. The parameters with Min and Max values are guaranteed with production tests or SQC (Statistical Quality Control) methods. All voltages with respect to GND/PGND. Device parameters are guaranteed at VDD=1.8 V and TA=25 °C unless otherwise noted. 

## **Figure 6:** 

## **Electrical Characteristics of AS7343L** 

|**Symbol**<br>**Parameter**|**Conditions**<br>**Min**<br>**Typ**|**Max**<br>**Unit**|
|---|---|---|
|VDD<br>Supply Voltage|1.7<br>1.8|1.98<br>V|
|TA<br>Operating free-air<br>temperature(1)|-30<br>25|85<br>°C|
|**Power Consumption**|||
|IDD<br>Supply Current(2)|VDD=1.8 V; TA=25 °C<br>Active mode(3)<br>210|280<br>µA|
||VDD=1.8 V; TA=25 °C<br>Idle mode(4)<br>40|60<br>µA|
||VDD=1.8 V; TA=25 °C<br>Sleep mode(5)<br>0.7|5<br>µA|
|**Digital Pins**|||
|VIH<br>SCL,SDA input high<br>voltage|1.26|V|
|VIL<br>SCL,SDA input low<br>voltage||0.54<br>V|
|VOL<br>INT, SDA output low<br>voltage|6 mA sink current|0.4<br>V|
|CI<br>Input pin capacitance||10<br>pF|
|Ileak<br>Leakage current into<br>SCL,SDA,INT pins|-5|5<br>µA|
|**GPIO**|||
|CLOAD<br>Maximum capacitive<br>load GPIO||20<br>pF|
|**LED Driver**|||
|V_LDR<br>LDR compliance voltage|I_LDR= 4 mA ; LED_HALF = “0”<br>I_LDR= 4 mA ; LED_HALF = “1”|240<br>mV<br>130|
||I LDR 134 mA ; LED_HALF = “0”<br>I LDR 134 mA ; LED_HALF = “1”|280<br>mV<br>180|



(1) While the device is operational across the temperature range, functionality will vary with temperature. 

(2) Supply current values are shown at the VDD pin and do not include current through pin LDR. 

(3) Active state occurs during active integration. (PON = “1” ; SP_EN = “1”) If wait is enabled (WEN = “1”), supply current is lower during the wait period 

(4) Idle state occurs when PON = “1” and all functions are disabled 

(5) Sleep state occurs when PON = “0” and I[2] C bus is idle. If I[2] C traffic is active device automatically enters idle mode. 

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AS7343L Optical Characteristics 

## **6 Optical Characteristics** 

All limits are guaranteed. The parameters with Min and Max values are guaranteed with production tests or SQC (Statistical Quality Control) methods. All voltages with respect to GND/PGND. Device parameters are guaranteed at VDD=1.8 V and TA=25 °C unless otherwise noted. 

## **Figure 7:** 

## **AS7343L Optical Channel Summary** 

|**Channel**|**Peak Wavelength [nm](1)(2)**<br>**Full Width Half Maximum [nm]**|
|---|---|
||**(min)**<br>**λp (typ)**<br>**(max)**<br>**(typ)**|
|F1|395<br>405<br>415<br>30|
|F2|415<br>425<br>435<br>22|
|FZ|440<br>450<br>460<br>55|
|F3|465<br>475<br>485<br>30|
|F4|505<br>515<br>525<br>40|
|FY|545<br>555<br>565<br>100|
|F5|540<br>550<br>560<br>35|
|FXL|590<br>600<br>610<br>80|
|F6|630<br>640<br>650<br>50|
|F7|680<br>690<br>700<br>55|
|F8|735<br>745<br>755<br>60|
|NIR|845<br>855<br>865<br>54|



(1) Parameter measured on a production ongoing sample bases on glass using diffused light. The table above is valid for full sensor response including diffuser, package and photodiode response. 

(2) Peak Wavelength is validated by smoothed/averaged monochromator measurement data 

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AS7343L Optical Characteristics 

## **Figure 8:** 

**Optical Characteristics of Spectral Channels, AGAIN: 1024x, Integration Time: 27.8 ms** 

|**Symbol**|<br>**Parameter**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|Re_F1|Irradiance<br>responsivity<br>channel F1|LED_396nm ; Ee= 155 mW/m²<br>LED_408nm ; Ee= 155 mW/m²|4311|<br>5749|7186|counts|
|Re_F2|Irradiance<br>responsivity<br>channel F2|LED_408nm ; Ee= 155 mW/m²<br>LED_448nm ; Ee= 155 mW/m²|1317|<br>1756|2196|counts|
|Re_FZ|Irradiance<br>responsivity<br>channel FZ|LED_428nm ; Ee= 155 mW/m²<br>LED_480nm ; Ee= 155 mW/m²|1627|<br>2169|2711|counts|
|Re_F3|Irradiance<br>responsivity<br>channel F3|LED_448nm ; Ee= 155 mW/m²<br>LED_500nm ; Ee= 155 mW/m²|577|770|962|counts|
|Re_F4|Irradiance<br>responsivity<br>channel F4|LED_500nm ; Ee= 155 mW/m²<br>LED_534nm ; Ee= 155 mW/m²|2356|<br>3141|3926|counts|
|Re_FY|Irradiance<br>responsivity<br>channel FY|LED_534nm ; Ee= 155 mW/m²<br>LED_593nm ; Ee= 155 mW/m²|2810|<br>3747|4684|counts|
|Re_F5|Irradiance<br>responsivity<br>channel F5|LED_531nm ; Ee= 155 mW/m²<br>LED_594nm ; Ee= 155 mW/m²|1180|<br>1574|1967|counts|
|Re_FXL|Irradiance<br>responsivity<br>channel FXL|LED_593nm ; Ee= 155 mW/m²<br>LED_628nm ; Ee= 155 mW/m²|3582|<br>4776|5970|counts|
|Re_F6|Irradiance<br>responsivity<br>channel F6|LED_618nm ; Ee= 155 mW/m²<br>LED_665nm ; Ee= 155 mW/m²|2502|<br>3336|4170|counts|
|Re_F7|Irradiance<br>responsivity<br>channel F7|LED_685nm ; Ee= 155 mW/m²<br>LED_715nm ; Ee= 155 mW/m²|4095|<br>5435|6774|counts|
|Re_F8|Irradiance<br>responsivity<br>channel F8|LED_715nm ; Ee= 155 mW/m²<br>LED_766nm ; Ee= 155 mW/m²|648|864|1080|counts|
|Re_NIR|Irradiance<br>responsivity<br>channel NIR|LED_849nm ; Ee= 155 mW/m²<br>LED_903nm ; Ee= 155 mW/m²|7936|<br>10581|13226|counts|



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AS7343L Optical Characteristics 

## **Figure 9:** 

**Optical Characteristics of Broadband Channels, AGAIN: 1024x, FD_GAIN: 64x, Integration Time: 27.8 ms** 

|**Symbol**|<br>**Parameter**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
||Irradiance|LED_593nm ; Ee= 155 mW/m²|||||
|Re_FD|responsivity|LED_766nm ; Ee= 155 mW/m²|3233|<br>4311|<br>5389|counts|
||channel Flicker|FD_GAIN=64x|||||
||Irradiance|LED_396nm ; Ee= 155 mW/m²|||||
|Re_VIS|responsivity|LED_766nm ; Ee= 155 mW/m²|749|999|1248|counts|
||channel VIS|2 VIS PDs read-out|||||



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AS7343L Optical Characteristics 

## **Figure 10:** 

**Optical Characteristics of AS7343L, AGAIN: 128x, Integration Time: 11 ms (unless otherwise noted)** 

|**Symbol**<br>**Parameter**|**Conditions**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**|**Conditions**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**|
|---|---|---|
|Dark_1(1)<br>Dark ADC count<br>value|Ee = 0 μW/cm2<br>AGAIN: 512x<br>Integration time:<br>98 ms<br>0<br>5<br>counts||
||AGAIN: 0.5x<br>7.49|7.9<br>8.28|
|Gain(2)<br>ratio<br>Optical gain ratios,<br>relative to 64x gain<br>setting|See<br>note(3)<br>AGAIN: 1x<br>15<br>15.8<br>16.5<br>AGAIN: 2x<br>30<br>31.6<br>33.2<br>AGAIN: 4x<br>61<br>64<br>67<br>AGAIN: 8x<br>117<br>124<br>130<br>AGAIN: 16x<br>235<br>247<br>259||
||AGAIN: 32x<br>0.475|0.5<br>0.525|
||AGAIN: 64x<br>1<br>AGAIN: 128x<br>1.9<br>2<br>2.1<br>AGAIN: 256x<br>3.9<br>4.1<br>4.3<br>AGAIN: 512x<br>8.1<br>8.6<br>9.1<br>AGAIN: 1024x<br>15.2<br>16.9<br>18.6<br>AGAIN: 2048x<br>28.2<br>34.75<br>41.3||
|ADC<br>noise(4)|White LED, 2700 K<br>Integration time:<br>100 ms<br>0.05<br>% full<br>scale||
|tint<br>Typical integration<br>time(5)|ASTEP = 599<br>ATIME = 29<br>50<br>ms||
|tASTEP<br>Integration time step<br>size|ASTEP = 999<br>2.78<br>ms||
|hca<br>Half cone angle|On the sensor<br>40<br>deg||



(1) The typical 3-sigma distribution is between 0 and 1 counts for AGAIN setting of 16x. 

(2) The gain ratios are relative to 64x gain setting and are calculated relative to the response with integration time: 11 ms and AGAIN: 128x. 

(3) ADC noise is calculated as the standard deviation of relative to full scale. 

(4) Integration time, in milliseconds, is equal to: (ATIME + 1) x (ASTEP + 1) x 2.78 µs 

(5) AGAIN ratio 0.5x to 16x is multiplied by 1000 for easier readability 

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AS7343L Typical Operating Characteristics 

## **7 Typical Operating Characteristics** 

## **Figure 11:** 

**Typical Spectral Responsivity** 

**==> picture [450 x 273] intentionally omitted <==**

**----- Start of picture text -----**<br>
F1 F2 FZ F3 F4 FY F5<br>FXL F6 F7 F8 VIS NIR<br>0.9<br>0.8<br>0.7<br>0.6<br>0.5<br>0.4<br>0.3<br>0.2<br>0.1<br>0<br>350 400 450 500 550 600 650 700 750 800 850 900 950 1000<br>wavelength / λ [nm]<br>spectral responsivity scaled to Si response<br>**----- End of picture text -----**<br>


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AS7343L Functional Description 

## **8 Functional Description** 

Upon power-up (POR), the device initializes. During initialization (typically 200 μs), the device will deterministically send NAK on I²C and cannot accept I²C transactions. All communication with the device must be delayed and all outputs from the device must be ignored including interrupts. After initialization, the device enters the SLEEP state. In this operational state, the internal oscillator and other circuitry are not active, resulting in ultra-low power consumption. If an I²C transaction occurs during this state, the I²C core wakes up temporarily to service the communication. Once the Power ON bit, “PON”, is enabled, the device enters the IDLE state in which the internal oscillator and attendant circuitry are active, but power consumption remains low. Whenever the spectral measurement is enabled (SP_EN = “1”) the device enters the ACTIVE state. If the spectral measurement is disabled (SP_EN = “0”) the device returns to the IDLE state. The figure below describes a simplified state diagram and the typical supply currents in each state. 

If Sleep after Interrupt is enabled (SAI = “1” in register 0xAC), the state machine will enter SLEEP when an interrupt occurs. Entering SLEEP does not automatically change any of the register settings (e.g. PON bit is still high, but the normal operational state is over-ridden by SLEEP state). SLEEP state is terminated when the SAI_ACTIVE bit is cleared (the status bit is in register 0xA7 and the clear status bit is in register 0xFA). 

**Figure 12: Simplified State Diagram** 

**==> picture [133 x 240] intentionally omitted <==**

**----- Start of picture text -----**<br>
Power On<br>VDD > VDD_POR<br>SLEEP<br>IDD = 0.7µA (typ)<br>PON =  1"<br>IDLE<br>IDD = 40µA (typ)<br>SP_EN =  1"<br>ACTIVE<br>Spectral<br>IDD = 210µA (typ)<br>PON =  0"<br>SP_EN =  0"<br>**----- End of picture text -----**<br>


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AS7343L Functional Description 

## 8.1 Device Architecture 

The device features six independent 16-bit ADCs. Gain and integration time of the six ADCs can be adjusted with the I[2] C interface. A wait time can be programed to automatically set a delay between two consecutive spectral measurements and to reduce overall power consumption. Once a measurement is started, the device is automatically processing the channels and storing the measurement data on chip in the corresponding data registers. 

## **Figure 13: Simplified Block Diagram** 

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**----- Start of picture text -----**<br>
VDD LDR<br>Xx] DX<br>GND SYNC input automatic  LED<br>GPIO measurement engine Driver PGND<br>CH0 ADC Data 1<br>SCL<br>+ CH1 ADC Data 2 I2C<br>i CH2 ADC ] Data 3 Interface —a SDA<br>e CH3 ADC g . i<br>interrupt  INT<br>CH4 ADC .<br>handling<br>CH5 ADC Data 18<br>18 x 16bit<br>6 x 16bit<br>DATA<br>ADC<br>Register<br>freee) ’  LI]<br>256 byte RC-<br>5x5 PD array  FIFO OTP osc<br>NIR PD<br>on chip IF Filter<br>SMUX<br>**----- End of picture text -----**<br>


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AS7343L Functional Description 

## 8.2 Sensor Array 

The device features a 5x5-photodiode array and two near- infrared response (“NIR”) sense fields and two large clear photodiodes (“C”). 

## **Figure 14: Sensor Array** 

**==> picture [176 x 206] intentionally omitted <==**

**----- Start of picture text -----**<br>
520µm<br>NIR C<br>C F F6 C<br>F3 5<br>X F2 F7<br>F4 L<br>F1<br>FY F8<br>F8 FY FZ<br>F1<br>X F4<br>F7 F2 L<br>F F3<br>C F6 5 C<br>C NIR<br>520µm 780µm<br>**----- End of picture text -----**<br>


## 8.3 GPIO 

The GPIO can be used synchronization input to start/stop the spectral measurement. It also allows synchronizing the LED driver (LDR) with an external start/stop signal. Default state of the GPIO is “output”. 

## 8.4 Interrupt (INT) 

The interrupt (INT) can be used to define thresholds and read-out the device only when the channel threshold has been reached. The pin is active low. 

## 8.5 LED Driver (LDR) 

The LED driver is programmable and can be used to drive external LEDs. It is also possible to synchronize the LED driver with an external start/stop signal via pin GPIO. 

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AS7343L I²C Interface 

## **9 I²C Interface** 

The device uses I²C serial communication protocol for communication. The device supports 7-bit chip addressing and both standard and full-speed clock frequency modes. Read and Write transactions comply with the standard set by Philips (now NXP). Internal to the device, an 8-bit buffer stores the register address location of the desired byte to read or write. This buffer auto-increments upon each byte transfer and is retained between transaction events (i.e. valid even after the master issues a STOP command and the I²C bus is released). During consecutive Read transactions, the future/repeated I²C Read transaction may omit the memory address byte normally following the chip address byte; the buffer retains the last register address +1. All 16-bit fields have a latching scheme for reading and writing. In general, it is recommended to use I²C bursts whenever possible, especially in this case when accessing two bytes of one logical entity. When reading these fields, the low byte must be read first, and it triggers a 16-bit latch that stores the 16-bit field. The high byte must be read immediately afterwards. When writing to these fields, the low byte must be written first, immediately followed by the high byte. Reading or writing to these registers without following these requirements will cause errors. 

## 9.1 I²C Address 

**Figure 15: AS7343L I[2] C Slave Address** 

|**Device**|**I2C Address**|
|---|---|
|AS7343L|0x39|



## 9.2 I²C Write Transaction 

A Write transaction consists of a START, CHIP-ADDRESSWRITE, REGISTER-ADDRESS WRITE, DATA BYTE(S), and STOP (P). Following each byte (9TH clock pulse) the slave places an ACKNOWLEDGE/NOT- ACKNOWLEDGE (A/N) on the bus. If the slave transmits N, the master may issue a STOP. 

## **Figure 16: I[2] C Byte Write** 

**==> picture [224 x 49] intentionally omitted <==**

**----- Start of picture text -----**<br>
S DW A WA A reg_data A P<br>WA++<br>**----- End of picture text -----**<br>


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AS7343L I²C Interface 

## 9.3 I²C Read Transaction 

A Read transaction consists of a START, CHIP-ADDRESSWRITE, REGISTER-ADDRESS, RESTART, CHIP-ADDRESSREAD, DATA BYTE(S), and STOP. Following all but the final byte the master places an ACK on the bus (9TH clock pulse). Termination of the Read transaction is indicated by a NACK being placed on the bus by the master, followed by STOP. 

## **Figure 17: I[2] C Read** 

**==> picture [266 x 44] intentionally omitted <==**

**----- Start of picture text -----**<br>
S DW A WA A Sr DR A data N P<br>RA++<br>**----- End of picture text -----**<br>


## 9.4 Timing Characteristics 

## **Figure 18:** 

## **I²C Timing Characteristics** 

|**Symbol**|**Parameter**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|
|fSCL|I²C clock frequency|||1|MHz|
|tBUF|Bus free time between start and stop<br>condition|1.3||||
|tHS;STA|Hold time after (repeated) start condition.<br>After this period, the first clock is generated.|<br>0.6||||
|tSU;STA|Repeated start condition setup time|0.6|||µs|
|tSU;STO|Stop condition setup time|0.6||||
|tLOW|SCL clock low period|1.3||||
|tHIGH|SCL clock high period|0.6||||
|tHD;DAT|Data hold time|0||||
|tSU;DAT|Data setup time|100||||
||||||ns|
|tF|Clock/data fall time|||300||
|tR|Clock/data rise time|||300||



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AS7343L I²C Interface 

## 9.5 Timing Diagrams 

## **Figure 19:** 

**I²C Slave Timing Diagram** 

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AS7343L Register Description 

## **10 Register Description** 

The device is controlled and monitored by registers accessed through the I²C serial interface. These registers provide device control functions and can be read to determine device status and acquire device data. 

The register set is summarized below. The values of all registers and fields that are listed as reserved or are not listed must not be changed at any time. Two-byte fields are always latched with the low byte followed by the high byte. The “Name” column illustrates the purpose of each register by highlighting the function associated to each bit. The bits are shown from MSB (D7) to LSB (D0). GRAY fields are reserved and their values must not be changed at any time. 

In order to access registers from 0x60 to 0x74 bit REG_BANK in register CFG0 (0xA9) needs to be set to “1”. 

## 10.1 Register Overview 

## **Figure 20: Register Overview** 

|**Addr**<br>**Name**|**<D7>**<br>**<D6>**<br>**<D5>**<br>**<D4>**<br>**<D3>**<br>**<D2>**<br>**<D1>**<br>**<D0>**|
|---|---|
|0x58<br>AUXID|AUXID [3:0]|
|0x59<br>REVID|REVID [2:0]|
|0x5A<br>ID|ID [7:0]|
|0x66<br>CFG12|SP_TH_CH [2:0]|
|0x80<br>ENABLE|SMUXEN<br>WEN<br>SP_EN<br>PON|
|0x81<br>ATIME|ATIME [7:0]|
|0x83<br>WTIME|WTIME [7:0]|
|0x84<br>SP_TH_L<br>0x85|SP_TH_L_LSB [7:0]|
||SP_TH_L_MSB [7:0]|
|0x86<br>SP_TH_H<br>0x87|SP_TH_H_LSB [7:0]|
||SP_TH_H_MSB [7:0]|
|0x93<br>STATUS|ASAT<br>AINT<br>FINT<br>SINT|
|0x94<br>ASTATUS|ASAT_<br>STATUS<br>AGAIN_STATUS [3:0]|
|0x95<br>DATA_0<br>0x96|DATA_0_L [7:0]|
||DATA_0_H [7:0]|
|0x97<br>DATA_1<br>0x98|DATA_1_L [7:0]|
||DATA_1_H [7:0]|
|0x99<br>DATA_2<br>0x9A|DATA_2_L [7:0]|
||DATA_2_H [7:0]|



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AS7343L Register Description 

|**Addr**<br>**Name**|**<D7>**<br>**<D6>**<br>**<D5>**<br>**<D4>**<br>**<D3>**<br>**<D2>**<br>**<D1>**<br>**<D0>**|
|---|---|
|0x9B<br>DATA_3<br>0x9C|DATA_3_L [7:0]|
||DATA_3_H [7:0]|
|0x9D<br>DATA_4<br>0x9E|DATA_4_L [7:0]|
||DATA_4_H [7:0]|
|0x9F<br>DATA_5<br>0xA0|DATA_5_L [7:0]|
||DATA_5_H [7:0]|
|0xA1<br>DATA_6<br>0xA2|DATA_6_L [7:0]|
||DATA_6_H [7:0]|
|0xA3<br>DATA_7<br>0xA4|DATA_7_L [7:0]|
||DATA_7_H [7:0]|
|0xA5<br>DATA_8<br>0xA6|DATA_8_L [7:0]|
||DATA_8_H [7:0]|
|0xA7<br>DATA_9<br>0xA8|DATA_9_L [7:0]|
||DATA_9_H [7:0]|
|0xA9<br>DATA_10<br>0xAA|DATA_10_L [7:0]|
||DATA_10_H [7:0]|
|0xAB<br>DATA_11<br>0xAC|DATA_11_L [7:0]|
||DATA_11_H [7:0]|
|0xAD<br>DATA_12<br>0xAE|DATA_12_L [7:0]|
||DATA_12_H [7:0]|
|0xAF<br>DATA_13<br>0xB0|DATA_13_L [7:0]|
||DATA_13_H [7:0]|
|0xB1<br>DATA_14<br>0xB2|DATA_14_L [7:0]|
||DATA_14_H [7:0]|
|0xB3<br>DATA_15<br>0xB4|DATA_15_L [7:0]|
||DATA_15_H [7:0]|
|0xB5<br>DATA_16<br>0xB6|DATA_16_L [7:0]|
||DATA_16_H [7:0]|
|0xB7<br>DATA_17<br>0xB8|DATA_17_L [7:0]|
||DATA_17_H [7:0]|
|0x90<br>STATUS 2|AVALID<br>ASAT_<br>DIG<br>ASAT_<br>ANA|
|0x91<br>STATUS 3|INT_SP_H<br>INT_SP_L|
|0xBB<br>STATUS 5|SINT<br>_SMUX|
|0xBC<br>STATUS 4|FIFO_<br>OV<br>OVTEMP<br>SP_TRIG<br>SAI_<br>ACT<br>INT_BUS<br>Y|
|0xBF<br>CFG 0|LOW_<br>POWER<br>REG_<br>BANK<br>WLONG|
|0xC6<br>CFG1|AGAIN[4:0]|
|0xC7<br>CFG3|SAI|



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AS7343L Register Description 

|**Addr**<br>**Name**|**<D7>**<br>**<D6>**<br>**<D5>**<br>**<D4>**<br>**<D3>**<br>**<D2>**<br>**<D1>**<br>**<D0>**|
|---|---|
|0xF5<br>CFG6|SMUX_<br>CMD[4:3]|
|0xC9<br>CFG8|FIFO_TH [7:6]|
|0xCA<br>CFG9|SIEN<br>_SMUX|
|0x65<br>CFG10||
|0xCF<br>PERS|APERS [3:0]|
|0x6B<br>GPIO|GPIO_<br>INV<br>GPIO_<br>IN_EN<br>GPIO_<br>OUT<br>GPIO_<br>IN|
|0xD4<br>ASTEP<br>0xD5|ASTEP [7:0]|
||ASTEP [15:8]|
|0xD6<br>CFG20|auto_SMUX|
|0xCD<br>LED|LED_AC<br>T<br>LED_DRIVE [6:0]|
|0xD7<br>AGC_GAIN_<br>MAX|AGC_FD_GAIN_MAX [7:4]|
|0xDE<br>AZ_CONFIG|AT_NTH_ITERATION [7:0]|
|0xF9<br>INTENAB|ASIEN<br>SP_IEN<br>FIEN<br>SIEN|
|0xFA<br>CONTROL|SW_<br>RESET<br>SP_MAN<br>_AZ<br>FIFO_<br>CLR<br>CLEAR_<br>SAI_ACT|
|0xFC<br>FIFO_MAP|FIFO_WRITE_CH5_DATA – FIFO_WRITE_CH0_DATA [6:1]<br>ASTATU<br>S|
|0xFD<br>FIFO_LVL|FIFO_LVL [7:0]|
|0xFE<br>FDATA<br>0xFF|FDATA _L[7:0]|
||FDATA_H [15:8]|



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AS7343L Register Description 

## 10.2 Detailed Register Description 

For easier readability, the detailed register description is done in groups of registers related to dedicated device functions. This is not necessarily related to its register address. 

Explanation of register access abbreviations: RW = read or write 

R = read only W = write only SC = self-clearing after access 

## **10.2.1 Enable and Configuration Registers** 

The following registers are needed to power up and configure the device. To operate the device set bit PON = “1” first (register 0x80) after that configure the device and enable interrupts before setting SP_EN = “1”. Changing configuration while SP_EN = “1” may result in invalid results. 

## **ENABLE Register (Address 0x80)** 

## **Figure 21: ENABLE Register** 

|**Addr: 0x80**|**Addr: 0x80**|**ENABLE**|||
|---|---|---|---|---|
|**Bit**|**Bit Name**|**Default**|**Access**|**Bit Description**|
|7:5|Reserved|0|RW|Reserved|
|||||**SMUX Enable.**|
|4|SMUXEN|0|RW|1: Starts SMUX command|
|||||Note: This bit gets cleared automatically as soon as|
|||||SMUX operation is finished|
|||||**Wait Enable.**|
|||||0: Wait time between two consecutive spectral|
|3|WEN|0|RW|measurements disabled|
|||||1: Wait time between two consecutive spectral|
|||||measurements enabled|
|2|Reserved|0|RW|Reserved|
|||||**Spectral Measurement Enable.**|
|1|SP_EN|0|RW|0: Spectral Measurement Disabled|
|||||1: Spectral Measurement Enabled|
|||||**Power ON.**|
|||||0: AS7343L disabled|
|0|PON|0|RW|1: AS7343L enabled|
|||||Note: When bit is set, internal oscillator is activated,|
|||||allowing timers and ADC channels to operate.|



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AS7343L Register Description 

## **GPIO Register (Address 0x6B)** 

## **Figure 22: GPIO Register** 

|**Addr: 0x6B**|**Addr: 0x6B**|**GPIO**|||
|---|---|---|---|---|
|**Bit**|**Bit Name**|**Default**|**Access**|**Bit Description**|
|7:4|Reserved|0||Reserved|
|3|GPIO_INV|0|RW|**GPIO Invert.**<br>If set, the GPIO output is inverted.|
|2|GPIO_IN_EN|0|RW|**GPIO Input Enable.**<br>If set, the GPIO pin accepts a non-floating input.|
|1|GPIO_OUT|1|RW|**GPIO Output.**<br>If set, the output state of the GPIO is active directly.|
|||||**GPIO Input.**|
|0|GPIO_IN|0|R|Indicates the status of the GPIO input if|
|||||GPIO_IN_EN is set.|



## **LED Register (Address 0xCD)** 

## **Figure 23: LED Register** 

|**Addr: 0xCD**|**Addr: 0xCD**|**LED**|||
|---|---|---|---|---|
|**Bit**|**Bit Name**|**Default**|**Access**|**Bit Description**|
|||||**LED Control.**|
|7|LED_ACT|0|RW|0: External LED connected to pin LDR off|
|||||1: External LED connected to pin LDR on|
|||||**LED Driving Strength.**|
|||||000 0000: 4 mA|
|||||000 0001: 6 mA|
|||||000 0010: 8 mA|
|6:0|LED_DRIVE|000 0100|RW|000 0011: 10 mA|
|||||**000 0100:**12 mA|
|||||……|
|||||111 1110: 256 mA|
|||||111 1111: 258 mA|



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AS7343L Register Description 

## **INTENAB Register (Address 0xF9)** 

## **Figure 24: INTENAB Register** 

|**Addr: 0xF9**|**Addr: 0xF9**|**INTENAB**|||
|---|---|---|---|---|
|**Bit**|**Bit Name**|**Default**|**Access**|**Bit Description**|
|||||**Spectral and Flicker Detect Saturation Interrupt**|
|||||**Enable.**|
|7|ASIEN|0|RW||
|||||When asserted permits saturation interrupts to be|
|||||generated.|
|6:4|Reserved|||Reserved|
|||||**Spectral Interrupt Enable.**|
|3|SP_IEN|0|RW|When asserted permits interrupts to be generated,<br>subject to the spectral thresholds and persistence|
|||||filter. Bit is mirrored in the ENABLE register.|
|||||**FIFO Buffer Interrupt Enable.**|
|2|F_IEN|0|RW|When asserted permits interrupt to be generated<br>when FIFO_LVL exceeds the FIFO threshold|
|||||condition.|
|1|Reserved|0||Reserved|
|||||**System Interrupt Enable.**|
|0|SIEN||RW|When asserted permits system interrupts to be|
|||||generated. Indicates that flicker detection status has|
|||||changed or SMUX operation has finished.|



## **CONTROL Register (Address 0xFA)** 

## **Figure 25: CONTROL Register** 

|**Addr: 0xFA**|**Addr: 0xFA**|**CONTROL**|||
|---|---|---|---|---|
|**Bit**|**Bit Name**|**Default**|**Access**|**Bit Description**|
|7:4|Reserved|0||Reserved|
|||||**Software Reset.**|
|3|SW_RESET|0|RW|When set the device will force a power on reset.|
|||||**Spectral Engine Manual Autozero.**|
|2|SP_MAN_AZ|0|RW|Starts a manual autozero of the spectral engines.<br>Set SP_EN = 0 before starting a manual autozero for|
|||||it to work.|
|||||**FIFO Buffer Clear.**|
|1|FIFO_CLR|0|RW|Clears all FIFO data, FINT, FIFO_OV, and|
|||||FIFO_LVL.|
|||||**Clear Sleep-After-Interrupt Active.**|
|0|CLEAR_SAI_ACT|0|RW|Clears SAI_ACTIVE, ends sleep, and restarts device|
|||||operation.|



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AS7343L Register Description 

## **10.2.2 ADC Timing Configuration / Integration Time** 

The integration time is set using the ATIME (0x81) and ASTEP (0xD4, 0xD5) registers. The integration time, in milliseconds, is equal to: 

## **Equation 1: Setting the integration time** 

𝑡𝑖𝑛𝑡 = (𝐴𝑇𝐼𝑀𝐸+ 1) × (𝐴𝑆𝑇𝐸𝑃+ 1) × 2.78µ𝑠 

It is not allowed that both settings –ATIME and ASTEP – are set to “0”. 

The integration time also defines the full-scale ADC value, which is equal to: 

## **Equation 2: ADC full scale value[2]** 

𝐴𝐷𝐶𝑓𝑢𝑙𝑙𝑠𝑐𝑎𝑙𝑒 = (𝐴𝑇𝐼𝑀𝐸+ 1) × (𝐴𝑆𝑇𝐸𝑃+ 1) 

## **ATIME Register (Address 0x81)** 

## **Figure 26: ATIME Register** 

|**Addr: 0x81**<br>**ATIME**||
|---|---|
|**Bit**<br>**Bit Name**<br>**Default**<br>**Access**|**Bit Description**|
|7:0<br>ATIME<br>0x00<br>RW|**Integration Time.**<br>Sets the number of integration steps from 1 to 255.|
||**Value**<br>**Integration Time**|
||0<br>ASTEP|
||n<br>ASTEP x (n+1)|
||255<br>ASTEP x 256|



> 2 The maximum ADC count is 65535. Any ATIME/ASTEP field setting resulting in higher ADC full-scale values would result in a full-scale of 65535. 

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AS7343L Register Description 

## **ASTEP Register (Address 0xD4, 0xD5)** 

## **Figure 27: ASTEP Register** 

|**Addr: 0xD4, 0xD5**<br>**ASTEP**||
|---|---|
|**Bit**<br>**Bit Name**<br>**Default**<br>**Access**|**Bit Description**|
|7:0<br>ASTEP 0xCA<br>999<br>RW<br>15:8<br>ASTEP 0xCB|**Integration Time Step Size.**<br>Sets the integration time per step in increments of<br>2.78 µs. The default value is 999.|
||**VALUE**<br>**STEP SIZE**|
||0<br>2.78 µs|
||n<br>2.78 µs x (n+1)|
||599<br>1.67 ms|
||999<br>2.78 ms|
||17999<br>50 ms|
||65534<br>182 ms|
||65535<br>Reserved, do not use|



## **WTIME Register (Address 0x83)** 

If wait is enabled (WEN = “1” register 0x80), each new measurement is started based on WTIME. It is necessary for WTIME to be sufficiently long for spectral integration and any other functions to be completed within the period. The device will warn the user if the timing is configured incorrectly. If WTIME is too short, then SP_TRIG in register STATUS6 (ADDR: 0xA7) will be set to “1”. 

## **Figure 28: WTIME Register** 

|**Addr: 0x83**<br>**WTIME**||
|---|---|
|**Bit**<br>**Bit Name**<br>**Default**<br>**Access**|**Bit Description**|
|7:0<br>WTIME<br>0x00<br>RW|**Spectral Measurement Wait Time.**<br>8-bit value to specify the delay between two<br>consecutive spectral measurements.|
||**Value**<br>**Wait Cycles**<br>**Wait Time**|
||0x00<br>1<br>2.78 ms|
||0x01<br>2<br>5.56 ms|
||n<br>n<br>2.78 ms x (n+1)|
||0xff<br>256<br>711 ms|



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AS7343L Register Description 

## **10.2.3 ADC Configuration** 

The following registers provide configuration for the 6 integrated ADCs (CH0 to CH5). It is possible to adjust the gain and setup the auto zero compensation for the ADCs. 

## **CFG1 Register (Address 0xC6)** 

**Figure 29: CFG1 Register** 

|**Addr: 0xC6**<br>**CFG1**||
|---|---|
|**Bit**<br>**Bit Name**<br>**Default**<br>**Access**|**Bit Description**|
|7:5<br>Reserved<br>0|Reserved|
|4:0<br>AGAIN<br>9<br>RW|**Spectral Engines Gain Setting.**<br>Sets the spectral sensitivity.|
||**VALUE**<br>**GAIN**|
||0<br>0.5x|
||1<br>1x|
||2<br>2x|
||3<br>4x|
||4<br>8x|
||5<br>16x|
||6<br>32x|
||7<br>64x|
||8<br>128x|
||9<br>256x|
||10<br>512x|
||11<br>1024x|
||12<br>2048x|



## **AZ_CONFIG Register (Address 0xDE)** 

The following register configures how often the spectral engine offsets are reset (auto zero) to compensate for changes of the device temperature. The typical time auto zero needs to be completed is 15 ms. 

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AS7343L Register Description 

## **Figure 30: AZ_CONFIG Register** 

|**Addr: 0xDE**<br>**AZ_CONFIG**||
|---|---|
|**Bit**<br>**Bit Name**<br>**Default**<br>**Access**|**Bit Description**|
|7:0<br>AZ_NTH_ITERATION<br>255<br>RW|**AUTOZERO FREQUENCY.**<br>Sets the frequency at which the device performs auto<br>zero of the spectral engines.|
||**VALUE**<br>**AUTOZERO FREQUENCY**|
||0<br>Never (not recommended)|
||1<br>Every integration cycle|
||2<br>Every 2 cycles|
||…<br>Every “AZ_NTH_ITERATION” cycle|
||254<br>Every 254 cycles|
||255<br>Only before first measurement cycle|



## **CFG8 Register (Address 0xC9)** 

**Figure 31: CFG8 Register** 

|**Addr: 0xC9**<br>**CFG8**||
|---|---|
|**Bit**<br>**Bit Name**<br>**Default**<br>**Access**|**Bit Description**|
|7:6<br>FIFO_TH<br>2<br>RW|**FIFO Threshold.**<br>Sets a threshold on the FIFO level that triggers the<br>first FIFO buffer interrupt (FINT).|
||**VALUE**<br>**FIFO_LVL**|
||0<br>1|
||1<br>4|
||2<br>8|
||3<br>16|
|5:0<br>Reserved<br>0|Reserved|



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AS7343L Register Description 

## **10.2.4 Device Identification** 

The following registers provided device identification. Device ID, revision ID and auxiliary ID are read only. 

## **AUXID Register (Address 0x58)** 

**Figure 32: AUXID Register** 

|**Addr: 0x58**|**Addr: 0x58**|**AUXID**|||
|---|---|---|---|---|
|**Bit**|**Bit Name**|**Default**|**Access**|**Bit Description**|
|7:4|Reserved|||Reserved|
|3:0|AUXID|0000|R|**Auxiliary Identification.**|



## **REVID Register (Address 0x59)** 

**Figure 33: REVID Register** 

|**Addr: 0x59**|**Addr: 0x59**|**REVID**|||
|---|---|---|---|---|
|**Bit**|**Bit Name**|**Default**|**Access**|**Bit Description**|
|7:3|Reserved|||Reserved|
|2:0|REV_ID|000|R|**Revision Number Identification.**|



## **ID Register (Address 0x5A)** 

**Figure 34: ID Register** 

|**Addr: 0x5A**|**Addr: 0x5A**|**ID**|||
|---|---|---|---|---|
|**Bit**|**Bit Name**|**Default**|**Access**|**Bit Description**|
|||||**Part Number Identification.**|
|7:0|ID|10000001|R||
|||||Value 10000001|



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AS7343L Register Description 

## **10.2.5 Spectral Interrupt Configuration** 

The spectral interrupt threshold registers provide 16-bit values to be used as the high and low thresholds for comparison to the 16-bit CH0_DATA values (ADC CH0). If SP_IEN (register 0xF9) is enabled and CH0_DATA is not between the two thresholds for the number of consecutive measurements specified in APERS (register 0xBD) an interrupt is set. 

## **SP_TH_L_LSB Register (Address 0x84)** 

## **Figure 35:** 

**SP_TH_L_LSB Register** 

|**Addr: 0x84**|**Addr: 0x84**|**SP_TH_L_LSB**|**SP_TH_L_LSB**||
|---|---|---|---|---|
|**Bit**|**Bit Name**|**Default**|**Access**|**Bit Description**|
|||||**Spectral Low Threshold LSB.**|
|7:0|SP_TH_L_LSB|0x00|RW|This register provides the low byte of the low|
|||||interrupt threshold (CH0).|



## **SP_TH_L_MSB Register (Address 0x85)** 

**Figure 36: SP_TH_L_MSB Register** 

|**Addr: 0x85**|**Addr: 0x85**|**SP_TH_L_MSB**|**SP_TH_L_MSB**||
|---|---|---|---|---|
|**Bit**|**Bit Name**|**Default**|**Access**|**Bit Description**|
|||||**Spectral Low Threshold MSB.**|
|||||This register provides the high byte of the low|
|||||interrupt threshold (CH0).|
|||||Both SP_TH_L registers are combined to a 16-bit|
|||||threshold. If the value captured by channel 0 is|
|||||below the low threshold and the APERS value is|
|||||reached the bit SP_IEN is set and an interrupt is|
|7:0|SP_TH_L_MSB|0x00|RW|generated.|
|||||There is an 8-bit data latch implemented that stores|
|||||the written low byte until the high byte is written.|
|||||Both bytes will be applied at the same time to avoid|
|||||an invalid threshold.|
|||||Note: The LSB register cannot be changed without|
|||||writing to the MSB register. It is recommended to|
|||||write to SP_TH_L_LSB and SP_TH_L_MSB within|
|||||one I2C command.|



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AS7343L Register Description 

## **SP_TH_H_LSB Register (Address 0x86)** 

## **Figure 37:** 

## **SP_TH_H_LSB Register** 

|**Addr: 0x86**|**Addr: 0x86**|**SP_TH_H_LSB**|**SP_TH_H_LSB**||
|---|---|---|---|---|
|**Bit**|**Bit Name**|**Default**|**Access**|**Bit Description**|
|||||**Spectral High Threshold LSB.**|
|7:0|SP_TH_H_LSB|0x00|RW|This register provides the low byte of the high|
|||||interrupt threshold (CH0).|



## **SP _TH_H_MSB Register (Address 0x87)** 

## **Figure 38:** 

**SP_TH_H_MSB Register** 

|**Addr: 0x87**|**Addr: 0x87**|**SP_TH_H_MSB**|**SP_TH_H_MSB**||
|---|---|---|---|---|
|**Bit**|**Bit Name**|**Default**|**Access**|**Bit Description**|
|||||**Spectral High Threshold MSB.**|
|||||This register provides the high byte of the high|
|||||interrupt threshold (CH0).|
|7:0|SP_TH_H_MSB|0x00|RW|Both SP_TH_H registers are combined to a 16-bit|
|||||threshold. If the value captured by channel 0 is|
|||||above the high threshold and the APERS value is|
|||||reached the bit SP_IEN is set and an interrupt is|
|||||generated.|



## **CFG12 Register (Address 0x66)** 

**Figure 39: CFG12 Register** 

|**Addr: 0x66**<br>**CFG12**||
|---|---|
|**Bit**<br>**Bit Name**<br>**Default**<br>**Access**|**Bit Description**|
|7:3<br>Reserved<br>0|Reserved|
|2:0<br>SP_TH_CH<br>0<br>RW|**Spectral Threshold Channel.**<br>Sets the channel used for interrupts and persistence,<br>if enabled, to determine device status and gain<br>settings.|
||**VALUE**<br>**CHANNEL**|
||0<br>CH0|
||1<br>CH1|
||2<br>CH2|



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AS7343L Register Description 

|**Addr: 0x66**<br>**CFG12**||
|---|---|
|**Bit**<br>**Bit Name**<br>**Default**<br>**Access**|**Bit Description**|
||3<br>CH3|
||4<br>CH4|
||5<br>CH5|



## **10.2.6 Device Status Registers** 

The following registers provide status of the device and indicate details about saturation, interrupts, over temperature, device execution and ambient light flicker detection. 

## **STATUS Register (Address 0x93)** 

The primary status register for AS7343L indicates if there are saturation or interrupt events that need to be handled by the user. This register is self-clearing, meaning that writing a “1” to any bit in the register clears that status bit. In this way, the user should read the STATUS register, handle all indicated event(s) and then write the register value back to STATUS to clear the handled events. Writing “0” will not clear those bits if they have a value of “1”, which means that new events that occurred since the last read of the STATUS register will not be accidentally cleared. In case channel saturation has happened (ASAT) it is recommended to discard the measurement results and reconfigure device configuration such as AGAIN and Integration Time to avoid saturation. 

## **Figure 40: STATUS Register** 

|**Addr: 0x93**|**Addr: 0x93**|**STATUS**|||
|---|---|---|---|---|
|**Bit**|**Bit Name**|**Default**|**Access**|**Bit Description**|
|||||**Spectral and Flicker Detect Saturation.**|
|7|ASAT|0|R, SC|If ASIEN is set, indicates Spectral saturation. Check<br>STATUS2 register to distinguish between analog or|
|||||digital saturation.|
|6:4|Reserved|0|R|Reserved|
|||||**Spectral Channel Interrupt.**|
|3|AINT|0|R, SC|If SP_IEN is set, indicates that a spectral event that<br>met the programmed thresholds and persistence|
|||||(APERS) occurred.|
|||||**FIFO Buffer Interrupt.**|
|||||If FIEN is set, indicates that the FIFO_LVL fulfills the|
|2|FINT|0|R, SC|threshold condition. If cleared by writing 1, the<br>interrupt will be asserted again as more data is|
|||||collected. To fully clear this interrupt, all data must|
|||||be read from the FIFO buffer.|
|1|Reserved|0|R|Reserved|
|0|SINT|0|R, SC|**System Interrupt.**|



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AS7343L Register Description 

|**Addr: 0x93**|**Addr: 0x93**|**STATUS**|||
|---|---|---|---|---|
|**Bit**|**Bit Name**|**Default**|**Access**|**Bit Description**|
|||||If SIEN is set, indicates that system interrupt is set.|
|||||Refer to Status5 register**.**|



## **STATUS 2 Register (Address 0x90)** 

## **Figure 41: STATUS 2 Register** 

|**Addr: 0x90**|**Addr: 0x90**|**STATUS 2**|||
|---|---|---|---|---|
|**Bit**|**Bit Name**|**Default**|**Access**|**Bit Description**|
|7|Reserved|0||Reserved|
|||||**Spectral Valid**.|
|6|AVALID|0|R|Indicates that the spectral measurement has been|
|||||completed|
|5|Reserved|0||Reserved|
|||||**Digital Saturation**.|
|4|ASAT_DIGITAL|0|R|Indicates that the maximum counter value has been<br>reached. Maximum counter value depends on|
|||||integration time set in the ATIME register.|
|||||**Analog Saturation**.|
|3|ASAT_ANALOG|0|R|Indicates that the intensity of ambient light has<br>exceeded the maximum integration level for the|
|||||spectral analog circuit.|
|2:0|Reserved|0|R|Reserved|



## **STATUS 3 Register (Address 0x91)** 

**Figure 42: STATUS 3 Register** 

|**Addr: 0x91**|**Addr: 0x91**|**STATUS 3**|||
|---|---|---|---|---|
|**Bit**|**Bit Name**|**Default**|**Access**|**Bit Description**|
|7:6|Reserved|0||Reserved|
|||||**Spectral Interrupt High.**|
|5|INT_SP_H|0|R|Indicates that a spectral interrupt occurred because|
|||||the data exceeded the high threshold.|
|||||**Spectral Interrupt Low**.|
|4|INT_SP_L|0|R|Indicates that a spectral interrupt occurred because|
|||||the data is below the low threshold.|
|3:0|Reserved|0||Reserved|



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AS7343L Register Description 

## **STATUS 5 Register (Address 0xBB)** 

## **Figure 43:** 

## **STATUS 5 Register** 

|**Addr: 0xBB**|**Addr: 0xBB**|**STATUS 5**|||
|---|---|---|---|---|
|**Bit**|**Bit Name**|**Default**|**Access**|**Bit Description**|
|7:3|Reserved|0||Reserved|
|||||**SMUX Operation Interrupt.**|
|2|SINT_SMUX|0|R|Indicates that SMUX command execution has|
|||||finished.|
|1:0|Reserved|0||Reserved|



## **STATUS 4 Register (Address 0xBC)** 

## **Figure 44: STATUS 4 Register** 

|**Addr: 0xBC**|**Addr: 0xBC**|**STATUS 4**|||
|---|---|---|---|---|
|**Bit**|**Bit Name**|**Default**|**Access**|**Bit Description**|
|||||**FIFO Buffer Overflow.**|
|7|FIFO_OV|0|R|Indicates that the FIFO buffer overflowed and<br>information has been lost. Bit is automatically|
|||||cleared when the FIFO buffer is read|
|6|Reserved|0|R|Reserved|
|||||**Over Temperature Detected.**|
|5|OVTEMP|0|R|Indicates the device temperature is too high. Write 1|
|||||to clear this bit.|
|4:3|Reserved|0||Reserved|
|||||**Spectral Trigger Error.**|
|2|SP_TRIG|0|R|Indicates that there is a timing error. The WTIME is|
|||||too short for the selected ATIME.|
|||||**Sleep after Interrupt Active.**|
|1|SAI_ACTIVE|0|R|Indicates that the device is in SLEEP due to an|
|||||interrupt. To exit SLEEP mode, clear this bit.|
|||||**Initialization Busy.**|
|0|INT_BUSY|0|R|Indicates that the device is initializing. This bit will<br>remain 1 for about 300 μs after power on. Do not|
|||||interact with the device until initialization is complete.|



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AS7343L Register Description 

## **10.2.7 Spectral Data and Status** 

The ASTATUS register provides saturation and gain status associated to each set of spectral data. Reading the ASTATUS register (0x94) latches all 36 spectral data bytes to that status read. Reading these bytes consecutively (0x94 to 0xB8) ensures that the data is concurrent. All spectral data are stored as 16-bit values. The ASTATUS and spectral data registers are read only. 

## **ASTATUS Register (Address 0x94)** 

**Figure 45: ASTATUS Register** 

|**Addr: 0x94**|**Addr: 0x94**|**ASTATUS**|||
|---|---|---|---|---|
|**Bit**|**Bit Name**|**Default**|**Access**|**Bit Description**|
|||||**Saturation Status.**|
|7|ASAT_STATUS|0|R, SC|Indicates if the latched data is affected by analog or|
|||||digital saturation.|
|6:4|Reserved|0|R|Reserved|
|||||**Gain Status.**|
|3:0|AGAIN_STATUS|0|R, SC|Indicates the gain applied for the spectral data|
|||||latched to this ASTATUS read.|



## **DATA Register (Address 0x95/0xB8)** 

**Figure 46: DATA_L Register** 

|**Addr: 0x95/97/99..B7**|**Addr: 0x95/97/99..B7**|**DATA_N_L**|||
|---|---|---|---|---|
|**Bit**|**Bit Name**|**Default**|**Access**|**Bit Description**|
|7:0|DATA_L|0|R|Spectral Data – low byte|



**Figure 47: DATA_H Register** 

|**Addr: 0x96/98/9A..B8**|**Addr: 0x96/98/9A..B8**|**DATA_N_H**|||
|---|---|---|---|---|
|**Bit**|**Bit Name**|**Default**|**Access**|**Bit Description**|
|7:0|DATA_H|0|R|Spectral Data – high byte|



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AS7343L Register Description 

## **10.2.8 Miscellaneous Configuration** 

## **CFG0 Register (Address 0xBF)** 

## **Figure 48: CFG 0 Register** 

|**Addr: 0xBF**|**Addr: 0xBF**|**CFG0**|||
|---|---|---|---|---|
|**Bit**|**Bit Name**|**Default**|**Access**|**Bit Description**|
|7:6|Reserved|0||Reserved|
|||||**Low Power Idle.**|
|5|LOW_POWER|0|RW|When asserted, the device will automatically run in a<br>low power mode whenever all functions are in wait|
|||||states or disabled.|
|||||**Register Bank Access.**|
|||||0: Register access to register 0x80 and above|
|4|REG_BANK|0|RW|1: Register access to register 0x20 to 0x7F|
|||||Note: Bit needs to be set to access registers 0x20 to|
|||||0x7F. If registers 0x80 and above needs to be|
|||||accessed bit needs to be set to “0”.|
|3|Reserved|0||Reserved|
|2|WLONG|0|RW|**Trigger Long.**|
|||||Increases the WTIME setting by a factor of 16.|
|1:0|Reserved|0||Reserved|



## **CFG3 Register (Address 0xC7)** 

## **Figure 49: CFG 3 Register** 

|**Addr: 0xC7**|**Addr: 0xC7**|**CFG3**|||
|---|---|---|---|---|
|**Bit**|**Bit Name**|**Default**|**Access**|**Bit Description**|
|7:5|Reserved|0||Reserved|
|||||**Sleep After Interrupt.**|
|||||If set, the oscillator is turned off whenever an|
|4|SAI|0|RW|interrupt is active. SAI_ACTIVE is set in this event.|
|||||To activate the oscillator again, clear all interrupts|
|||||and clear the SAI_ACTIVE bit.|
|3:0|Reserved|0xC||Reserved|



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AS7343L Register Description 

## **CFG6 Register (Address 0xF5)** 

## **Figure 50: CFG6 Register** 

|**Addr: 0xF5**<br>**CFG6**||
|---|---|
|**Bit**<br>**Bit Name**<br>**Default**<br>**Access**|**Bit Description**|
|4:3<br>SMUX_CMD<br>2<br>RW|**SMUX Command.**<br>Selects the SMUX command to execute when<br>setting SMUXEN gets set. Do not change during<br>ongoing SMUX operation.|
||**VALUE**<br>**SMUX_CMD**|
||0<br>ROM code initialization of SMUX|
||1<br>Read SMUX configuration to RAM<br>from SMUX chain|
||2<br>Write SMUX configuration from<br>RAM to SMUX chain|
||3<br>Reserved, do not use|



## **CFG9 Register (Address 0xCA)** 

**Figure 51: CFG9 Register** 

|**Addr: 0xCA**|**Addr: 0xCA**|**CFG9**|||
|---|---|---|---|---|
|**Bit**|**Bit Name**|**Default**|**Access**|**Bit Description**|
|7:5|Reserved|0||Reserved|
|||||**System Interrupt SMUX Operation.**|
|4|SIEN_SMUX|0|RW|Enables system interrupt when SMUX command has|
|||||finished|
|3:0|Reserved|||Reserved|



## **CFG20 Register (Address 0xD6)** 

**Figure 52: CFG20 Register** 

|**Addr: 0xD6**|**Addr: 0xD6**|**CFG20**|||
|---|---|---|---|---|
|**Bit**|**Bit Name**|**Default**|**Access**|**Bit Description**|
|7|Reserved|||Reserved|



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AS7343L Register Description 

|**Addr: 0xD6**<br>**CFG20**||
|---|---|
|**Bit**<br>**Bit Name**<br>**Default**<br>**Access**|**Bit Description**|
|6:5<br>auto_smux<br>0<br>RW|**Automatic Channel Read-Out.**<br>**0:**6 Channel<br>FZ, FY, FXL, NIR, 2xVIS, Clear<br>**1:**Reserved<br>**2:**Automatic 12 channel<br>Cycle 1: FZ, FY, FXL, NIR, 2xVIS, Clear<br>Cycle 2: F2, F3, F4, F6, 2xVIS, Clear<br>**3:**Automatic 18 channel<br>Cycle 1: FZ, FY, FXL, NIR, 2xVIS, Clear<br>Cycle 2: F2, F3, F4, F6, 2xVIS, Clear<br>Cycle 3: F1, F5, F7, F8, 2xVIS, Clear<br>Note: The bit “auto_smux” should only be changed<br>before a measurement is started.<br>Once a measurement is started the device is<br>automatically processing the channels as per<br>definition above and storing the measurement<br>results in the eighteen data registers.<br>2xVIS: Per default the “Top Left” and “Bot Right”<br>VIS/CLEAR PD is read-out|
|4:0<br>Reserved|Reserved|
|**PERS Register (Address 0xCF)**<br>**Figure 53:**<br>**PERS Register**||
|**Addr: 0xCF**<br>**PERS**||
|**Bit**<br>**Bit Name**<br>**Default**<br>**Access**|**Bit Description**|
|7:4<br>Reserved<br>0|Reserved|
|3:0<br>APERS<br>0<br>RW|**Spectral Interrupt Persistence.**<br>Defines a filter for the number of consecutive<br>occurrences that spectral data must remain outside<br>the threshold range between SP_TH_L and<br>SP_TH_H before an interrupt is generated. The<br>spectral data channel used for the persistence filter<br>is set by SP_TH_CHANNEL. Any sample that is<br>inside the threshold range resets the counter to 0.|
||**VALUE**<br>**CHANNEL**|
||0<br>Every spectral cycle generates an<br>interrupt|
||1<br>1|
||2<br>2|
||3<br>3|
||4<br>5|
||5<br>10|



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AS7343L Register Description 

|**Addr: 0xCF**<br>**PERS**||
|---|---|
|**Bit**<br>**Bit Name**<br>**Default**<br>**Access**|**Bit Description**|
||…<br>5 x (APERS – 3)|
||14<br>55|
||15<br>60|



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AS7343L Register Description 

## **10.2.9 FIFO Buffer Data and Status** 

The FIFO buffer is used to poll spectral data with fewer I²C read and write transactions. The FIFO buffer is 256 bytes of RAM containing 128 two-byte datasets. If the FIFO overflows (i.e. 129 datasets before host reads data from the FIFO buffer), an overflow flag will be set and new data will be lost. The Host acquires data by reading addresses: 0xFE – 0xFF. The register address pointer automatically wraps from 0xFF to 0xFE as data are read. Data can be read one byte at a time or in blocks, (there is no block-read length limit). When reading single bytes, the internal FIFO read pointer and the FIFO Buffer Level, FIFO_LVL, are updated each time register 0xFF is read. For block-reads, the internal FIFO read pointer and the FIFO Buffer Level, FIFO_LVL update for each two-byte entry. If the FIFO continues to be accessed after FIFO_LVL = 0, the device will return 0 for all data. The FINT interrupt indicates when there is valid data in the FIFO buffer. The amount of unread data is indicated by the FIFO_LVL. 

## **FIFO_MAP Register (Address 0xFC)** 

## **Figure 54: FIFO_MAP Register** 

|**Addr: 0xFC**|**Addr: 0xFC**|**FIFO_MAP**|||
|---|---|---|---|---|
|**Bit**|**Bit Name**|**Default**|**Access**|**Bit Description**|
|7|Reserved|0||Reserved|
|||||**FIFO Write CH5 Data.**|
|6|FIFO_WRITE_CH5_DATA|<br>0|RW|If set, CH5 data is written to the FIFO Buffer. (two|
|||||bytes per sample)|
|||||**FIFO Write CH4 Data.**|
|5|FIFO_WRITE_CH4_DATA|<br>0|RW|If set, CH4 data is written to the FIFO Buffer. (two|
|||||bytes per sample)|
|||||**FIFO Write CH3 Data.**|
|4|FIFO_WRITE_CH3_DATA|<br>0|RW|If set, CH3 data is written to the FIFO Buffer. (two|
|||||bytes per sample)|
|||||**FIFO Write CH2 Data.**|
|3|FIFO_WRITE_CH2_DATA|<br>0|RW|If set, CH2 data is written to the FIFO Buffer. (two|
|||||bytes per sample)|
|||||**FIFO Write CH1 Data.**|
|2|FIFO_WRITE_CH1_DATA|<br>0|RW|If set, CH1 data is written to the FIFO Buffer. (two|
|||||bytes per sample)|
|||||**FIFO Write CH0 Data.**|
|1|FIFO_WRITE_CH0_DATA|<br>0|RW|If set, CH0 data is written to the FIFO Buffer. (two|
|||||bytes per sample)|
|||||**FIFO Write Status.**|
|0|FIFO_WRITE_ASTATUS|0|RW|If set, ASTATUS (one byte per sample) is written|
|||||to the FIFO Buffer.|



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AS7343L Register Description 

## **FIFO_LVL Register (Address 0xFD)** 

## **Figure 55:** 

## **FIFO_LVL Register** 

|**Addr: 0xFD**|**Addr: 0xFD**|**FIFO_LVL**|||
|---|---|---|---|---|
|**Bit**|**Bit Name**|**Default**|**Access**|**Bit Description**|
|||||**FIFO Buffer Level.**|
|||||Indicates the number of entries (each are 2 bytes)|
|7:0|FIFO_LVL|0|R|available in the FIFO buffer waiting for readout. The|
|||||FIFO RAM is 256byte, the FIFO_LVL range is from 0|
|||||entries to 128 entries.|



## **FDATA Register (Address 0xFE and 0xFF)** 

## **Figure 56: FDATA_L Register** 

|**Addr: 0xFE**|**Addr: 0xFE**|**FDATA_L**|||
|---|---|---|---|---|
|**Bit**|**Bit Name**|**Default**|**Access**|**Bit Description**|
|7:0|FDATA|0|R|FIFO Buffer Data|



## **Figure 57:** 

## **FDATA_H Register** 

|**Addr: 0xFF**|**Addr: 0xFF**|**FDATA_H**|||
|---|---|---|---|---|
|**Bit**|**Bit Name**|**Default**|**Access**|**Bit Description**|
|15:8|FDATA|0|R|FIFO Buffer Data|



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AS7343L Application Information 

## **11 Application Information** 

## 11.1 Schematic 

**Figure 58: Application Example** 

**==> picture [223 x 146] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDD<br>1.8V R1<br>22R<br>VDD<br>C1 =H C2 ©<br>4.7uF 1uF<br>V7 PGND GPIO<br>AS7343L<br>GND<br>Vbus<br>1.8V<br>13CH<br>SCL 2k2R2 R32k2 R410k SCL Spectral Sensor LDR<br>SDA x SDA 380-1000nm a<br>INT a INT SJ<br>**----- End of picture text -----**<br>


## 11.2 PCB Pad Layout 

**Figure 59: Recommended PCB Pad Layout** 

- (1) All dimensions are in millimeters. (2) Dimension tolerances are 0.05 mm unless otherwise noted. (3) This drawing is subject to change without notice. 

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AS7343L Application Information 

## 11.3 Application Optical Requirements 

For optimal performance, an achromatic diffuser shall be placed above the device aperture. The recommended solution is a bulk diffuser that meets the minimum recommended scattering characteristic shown below. For more details refer to the optical design guide or contact ams OSRAM. 

## **Figure 60:** 

**Diffuser Characteristics** 

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AS7343L Package Drawings & Markings 

## **12 Package Drawings & Markings** 

## **Figure 61: OLGA8 Package Outline Drawing** 

**==> picture [149 x 17] intentionally omitted <==**

**----- Start of picture text -----**<br>
RoHS Green<br>**----- End of picture text -----**<br>


- (1) All dimensions are in millimeters. Angles in degrees. 

- (2) Dimensioning and tolerance conform to ASME Y14.5M-1994. 

- (3) This package contains no lead (Pb). (4) This drawing is subject to change without notice. 

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AS7343L Tape & Reel Information 

## **13 Tape & Reel Information** 

## **Figure 62:** 

## **AS7343L OLGA8 Tape Dimensions** 

- (1) All dimensions are in millimeters. Angles in degrees. 

- (2) This drawing is subject to change without notice. 

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AS7343L Tape & Reel Information 

## **Figure 63: AS7343L OLGA8 Reel Dimensions** 

- (1) All dimensions are in millimeters. Angles in degrees. 

- (2) This drawing is subject to change without notice. 

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AS7343L Soldering & Storage Information 

## **14 Soldering & Storage Information** 

The module has been tested and has demonstrated an ability to be reflow soldered to a PCB substrate. The solder reflow profile describes the expected maximum heat exposure of components during the solder reflow process of product on a PCB. Temperature is measured on top of component. The components should be limited to a maximum of three passes through this solder reflow profile. 

## **Figure 64:** 

## **Solder Reflow Profile Graph** 

**Figure 65: Solder Reflow Profile** 

|**Parameter**|**Reference**|**Device**|
|---|---|---|
|Average temperature gradient in preheating||2.5 °C/s|
|Soak time|tsoak|2 to 3 minutes|
|Time above 217 °C (T1)|t1|Max 60 s|
|Time above 230 °C (T2)|t2|Max 50 s|
|Time above Tpeak– 10 °C (T3)|t3|Max 10 s|
|Peak temperature in reflow|Tpeak|260 °C|
|Temperature gradient in cooling||Max −5 °C/s|



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AS7343L Soldering & Storage Information 

## 14.1 Storage Information 

## **14.1.1 Moisture Sensitivity** 

Optical characteristics of the device can be adversely affected during the soldering process by the release and vaporization of moisture that has been previously absorbed into the package. 

To ensure the package contains the smallest amount of absorbed moisture possible, each device is baked prior to being dry packed for shipping. Devices are dry packed in a sealed aluminized envelope called a moisture-barrier bag with silica gel to protect them from ambient moisture during shipping, handling, and storage before use. 

## **14.1.2 Shelf Life** 

The calculated shelf life of the device in an unopened moisture barrier bag is 12 months from the date code on the bag when stored under the following conditions: 

- Shelf Life: 12 months 

- Ambient Temperature: <40 °C 

- Relative Humidity: <90% 

Rebaking of the devices will be required if the devices exceed the 12 month shelf life or the Humidity Indicator Card shows that the devices were exposed to conditions beyond the allowable moisture region. 

## **14.1.3 Floor Life** 

The module has been assigned a moisture sensitivity level of MSL 3. As a result, the floor life of devices removed from the moisture barrier bag is 168 hours from the time the bag was opened, provided that the devices are stored under the following conditions: 

- Floor Life: 168 hours 

- Ambient Temperature: <30°C 

- Relative Humidity: <60% 

If the floor life or the temperature/humidity conditions have been exceeded, the devices must be rebaked prior to solder reflow or dry packing. 

## **14.1.4 Rebaking Instructions** 

When the shelf life or floor life limits have been exceeded, rebake at 50 °C for 12 hours. 

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AS7343L Revision Information 

## **15 Revision Information** 

|**Document Status**|**Product Status**|**Definition**|
|---|---|---|
|Product Preview|Pre-Development|<br>Information in this datasheet is based on product ideas in the planning phase|
|||of development. All specifications are design goals without any warranty and|
|||are subject to change without notice|
|Preliminary Datasheet|Pre-Production|Information in this datasheet is based on products in the design, validation or|
|||qualification phase of development. The performance and parameters shown|
|||in this document are preliminary without any warranty and are subject to|
|||change without notice|
|Datasheet|Production|Information in this datasheet is based on products in ramp-up to full production|
|||or full production which conform to specifications in accordance with the terms|
|||of ams-OSRAM AG standard warranty as given in the General Terms of Trade|
|Datasheet|Discontinued|Information in this datasheet is based on products which conform to|
|(discontinued)||specifications in accordance with the terms of ams-OSRAM AG standard|
|||warranty as given in the General Terms of Trade, but these products have|
|||been superseded and should not be used for new designs|
|**Changes from previous version to current revision v2-00**<br>**Page**|||
|Document security|class is updated|to “Public” in the footer|



- Page and figure numbers for the previous version may differ from page and figure numbers in the current revision. 

- ● Correction of typographical errors is not explicitly mentioned. 

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AS7343L Legal Information 

## **16 Legal Information** 

## **Copyrights & Disclaimer** 

Copyright ams-OSRAM AG, Tobelbader Strasse 30, 8141 Premstaetten, Austria-Europe. Trademarks Registered. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. 

Devices sold by ams-OSRAM AG are covered by the warranty and patent indemnification provisions appearing in its General Terms of Trade. ams-OSRAM AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein. ams-OSRAM AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ams-OSRAM AG for current information. This product is intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams-OSRAM AG for each application. This product is provided by ams-OSRAM AG “AS IS” and any express or implied warranties, including, but not limited to the implied warranties of merchantability and fitness for a particular purpose are disclaimed. 

ams-OSRAM AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of ams-OSRAM AG rendering of technical or other services. 

## **RoHS Compliant & ams Green Statement** 

**RoHS Compliant:** The term RoHS compliant means that ams-OSRAM AG products fully comply with current RoHS directives. Our semiconductor products do not contain any chemicals for all 6 substance categories plus additional 4 substance categories (per amendment EU 2015/863), including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, RoHS compliant products are suitable for use in specified lead-free processes. 

**ams Green (RoHS compliant and no Sb/Br/Cl):** ams Green defines that in addition to RoHS compliance, our products are free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) and do not contain Chlorine (Cl not exceed 0.1% by weight in homogeneous material). 

**Important Information:** The information provided in this statement represents ams-OSRAM AG knowledge and belief as of the date that it is provided. ams-OSRAM AG bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. ams-OSRAM AG has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ams-OSRAM AG and ams-OSRAM AG suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. 

**Headquarters** Please visit our website at www.ams.com ams-OSRAM AG Buy our products or get free samples online at www.ams.com/Products Tobelbader Strasse 30 Technical Support is available at www.ams.com/Technical-Support 8141 Premstaetten Provide feedback about this document at www.ams.com/Document-Feedback Austria, Europe For sales offices, distributors and representatives go to www.ams.com/Contact Tel: +43 (0) 3136 500 0 For further information and requests, e-mail us at ams_sales@ams.com 

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