AIS25BATR

**AIS25BA** 

Datasheet 

Ultralow noise, wide bandwidth, 3-axis accelerometer with TDM interface for automotive applications 

## **Features** 

- AEC-Q100 qualified 

- 3-axis accelerometer with user-selectable full-scale: ±3.85/±7.7 _g_ 

- Wide and flat frequency response: from dc up to 2.4 kHz (typ) 

- Low latency (entire reading chain): 266 µs @ 2 kHz (typ) 

- Ultralow noise density (typ: 30 µ _g_ /√Hz for X and Y axes; 50 µ _g_ /√Hz for Z-axis) 

- TDM (8/16/24 kHz) slave interface for sensor data and I²C interface for configuration 

- Supply voltage: 1.71 V to 2.1 V 

- Extended temperature range from -40 °C to +125 °C 

- Embedded self-test 

- Compact package: LGA 2.5 x 2.5 x 0.86 mm 14-lead 

## **Product status link** 

AIS25BA 

- 10000 _g_ high shock survivability 

- Lead-free, ECOPACK and RoHS compliant 

|**Product summary**|**Product summary**|
|---|---|
|**Order code**|AIS25BATR|
|**Temp. range [°C]**|-40 to +125|
|**Package**|LGA-14L<br>2.5 x 2.5 x 0.86 mm3|
|**Packaging**|Tape and reel|



**Product resources** TN0018 (Design and soldering) 

## **Product label** 

## **Applications** 

- Wideband active noise control (ANC) 

- Vibration monitoring 

## **Description** 

The AIS25BA is an ultralow noise, low latency, wide bandwidth, 3-axis digital accelerometer with a dedicated TDM interface designed to address automotive nonsafety applications, in particular, wideband active noise control (ANC) and vibration monitoring. 

The AIS25BA has a user-selectable full-scale range of ±3.85/±7.7 _g_ , a time-division multiplexing (TDM) interface for the sensor data, and an I²C interface for device configuration. 

The AIS25BA is available in a small thin plastic land grid array package (LGA) and is guaranteed to operate over an extended temperature range from -40 °C to +125 °C. 

**DS14019** - **Rev 1** - **July 2022** For further information contact your local STMicroelectronics sales office. 

www.st.com 

**AIS25BA Pin description** 

**1 Pin description** 

**Figure 1. Pin connections** 

**==> picture [417 x 247] intentionally omitted <==**

**----- Start of picture text -----**<br>
Zz<br>12 13 14<br>; LL<br>I2C_A0  11 LGA 14L  1 I2C_SCL<br>“> - _<br>xX (TOP VIEW) Y RES (VDD) | 10 2.5x2.5x0.86mm  | 2 I2C_SDA<br>GND  9 BOTTOM  3 TDM_BCLK<br>DETECTABLE | |<br>ACCELERATIONS VIEW<br>VDD  | 8 | 4 TDM_WCLK<br>7 6  5<br>Decoupling ceramic capacitor of 10 µF<br>has to be placed between VDD and GND<br>pins.<br>RES (GND) RES (GND) RES (GND)<br>TDM_MCLK RES (GND) TDM_SDOUT<br>**----- End of picture text -----**<br>


**Table 1. Pin description** 

|**Pin#**|**Name**|**IN/OUT**|**Function**|
|---|---|---|---|
|1|I2C_SCL|IN|I²C serial clock - SCL|
|2|I2C_SDA|IN/OUT|I²C serial data - SDA|
|3|TDM_BCLK|IN|TDM bit clock|
|4|TDM_WCLK|IN|TDM word clock|
|5|TDM_SDOUT|OUT|TDM serial data output|
|6|RES (GND)|-|Reserved pin (connect to GND)|
|7|TDM_MCLK|IN|TDM master clock|
|8|VDD||Power supply|
|9|GND||0 V supply|
|10|RES (VDD)|-|Reserved pin (connect to VDD)|
|11|I2C_A0|IN|I²C slave address selection|
|12|RES (GND)|-|Reserved pin (connect to GND)|
|13|RES (GND)|-|Reserved pin (connect to GND)|
|14|RES (GND)|-|Reserved pin (connect to GND)|



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**AIS25BA Mechanical and electrical specifications** 

## **2 Mechanical and electrical specifications** 

## **2.1 Mechanical characteristics** 

@ Vdd = 1.8 V, temperature from -40 °C to +125 °C unless otherwise noted. 

The product is factory calibrated at 1.8 V. The operational power supply range is from 1.71 V to 2.1 V. 

**Table 2. Mechanical characteristics** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.(1)**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|FS|Measurement range|||3.85||_g_|
|||||7.7|||
|So|Nominal sensitivity(2)|@ FS ±3.85_g_@ 25 °C||0.122||m_g_/LSB|
|||@ FS ±3.85_g_@ 25 °C||-11.71||dBFS/_g_|
|||@ FS ±7.7_g_@ 25 °C||0.244||m_g_/LSB|
|||@ FS ±7.7_g_@ 25 °C||-17.73||dBFS/_g_|
|So %|Sensitivity tolerance(2)|@ T = 25 °C|-9||+9|%|
||Sensitivity tolerance - long term|Long term includes post solder, drift in temperature in the<br>range [-40°C to +125 °C] and over life|-15||+15||
|TCSo|Sensitivity change vs.<br>temperature(3)|From -40 to +125 °C, delta from 25 °C||±0.015||%/°C|
|TyOff|Zero-_g_level offset accuracy(2)|@ T = 25 °C|-180||+180|m_g_|
|Off|Zero-_g_level offset accuracy - long<br>term|Long term includes post solder, drift in temperature in the<br>range [-40°C to +125 °C] and over life|-800||+800|m_g_|
|TCOff|Zero-_g_level change vs.<br>temperature(3)|From -40 to +125 °C, delta from 25 °C||4||m_g_/°C|
|An|Acceleration electrical noise|BW = 2.4 kHz @ T = 25 °C<br>X, Y-axis|||1.6|m_g_rms|
|||BW = 2.4 kHz @ T = 25 °C<br>Z-axis|||2.4||
|An_tot|Acceleration noise density(4)|@ T = 25 °C<br>X, Y-axis||30||μ_g_/√Hz|
|||@ T = 25 °C<br>Z-axis||50||μ_g_/√Hz|
|BW|Signal bandwidth|@ T = 25 °C|2200|2400||Hz|
|LAT|Latency(5)|Including the full chain @ 2 kHz; TDM @ 16 kHz<br>@ T = 25 °C||266||μs|
|NL|Non-linearity(6)|@FS ±7.7_g_; -7.4_g_< input acceleration [_g_] < +7.4_g_<br>@ T = 25 °C|-0.5||+0.5|%FS|
|Cx|Cross-axis sensitivity(6)|@ FS ±3.85_g_, @ 25 °C||±1||%|
|RFm|Mechanical resonant frequency of<br>the MEMS element(5)|X-axis, @ T = 25 °C||5150||Hz|
|||Y-axis, @ T = 25 °C||5150||Hz|
|||Z-axis, @ T = 25 °C||4950||Hz|
|ST|Self-test deviation(7)|X-axis, from -40 to +125 °C|300||1000|m_g_|
|||Y-axis, from -40 to +125 °C|300||1000|m_g_|
|||Z-axis, from -40 to +125 °C|500||2700|mg|



_1. Typical specifications are not guaranteed._ 

**DS14019** - **Rev 1** 

**page 3/31** 

**AIS25BA Electrical characteristics** 

_2. Values after factory calibration test and trimming at T = 25 °C._ 

_3. Based on characterization results on a limited number of samples, not tested in production and not guaranteed._ 

_4. Includes Brownian noise. Based on characterization results at 3σ on a limited number of samples, not tested in production and not guaranteed._ 

_5. Specified by design, not tested in production and not guaranteed._ 

_6. Based on characterization results at 3σ on a limited number of samples, not tested in production and not guaranteed._ 

_7. This is the difference between the output in self-test mode and the output in normal mode._ 

## **2.2 Electrical characteristics** 

@ Vdd = 1.8 V, temperature from -40 °C to +125 °C unless otherwise noted. 

The product is factory calibrated at 1.8 V. The operational power supply range is from 1.71 V to 2.1 V. 

**Table 3. Electrical characteristics** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.(1)**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Vdd|Supply voltage||1.71|1.8|2.1|V|
|Idd|Current consumption in normal mode|Three axes enabled|||5.0|mA|
|Idd_PD|Current consumption in power-down mode|@ T = 25 °C|||1|µA|
|ODR|Output data rate|TDM @ 8 kHz||8||kHz|
|||TDM @ 16 kHz||16||kHz|
|||TDM @ 24 kHz||24||kHz|
|VIH|Digital high-level input voltage||0.7*Vdd|||V|
|VIL|Digital low-level input voltage||||0.3*Vdd|V|
|VOH|High-level output voltage|IOH = 2 mA(2)|Vdd - 0.2|||V|
|VOL|Low-level output voltage|IOL = 2 mA(2)|||0.2|V|
|Top|Operating temperature range||-40||+125|°C|



_1. Typical specifications are not guaranteed._ 

_2. 2 mA is the maximum driving capability, that is, the maximum DC current that can be sourced/sunk by the digital pad in order to guarantee the correct digital output voltage levels VOH and VOL._ 

**DS14019** - **Rev 1** 

**page 4/31** 

**AIS25BA Absolute maximum ratings** 

## **2.3 Absolute maximum ratings** 

Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 

**Table 4. Absolute maximum ratings** 

|**Symbol**<br>~~a~~|**Ratings**<br>~~ae~~|**Maximum value**<br>~~ae~~<br>~~ee~~|**Unit**<br>~~ae~~|
|---|---|---|---|
|Vdd|Supply voltage|-0.3 to 4.8<br>~~ee~~|V|
|STR|Storage temperature range|-40 to +150|°C|
|AUNP|Acceleration (any axis, unpowered)|10,000_g_for 0.2 ms|_g_|
|||3000_g_for 0.3 ms||
|EDP|Electrostatic discharge protection (HBM)|2|kV|
|VMAX|Maximum input voltage on all input pins|4.8|V|
|VMIN|Minimum input voltage on all input pins|-0.3|V|
|IIN|Input current on all I/O pins<br>(does not cause SCR latch-up)|±10|mA|



_Note:_ 

_Supply voltage on any pin should never exceed 4.8 V._ 

This device is sensitive to mechanical shock, improper handling can cause permanent damage to the part. 

This device is sensitive to electrostatic discharge (ESD), improper handling can cause permanent damage to the part. 

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**AIS25BA TDM interface characteristics** 

## **3 TDM interface characteristics** 

All setup times and hold times in Table 5 and in Figure 2 are valid for BCLK polarity set to “clock on rising”. If BCLK polarity is set to “clock on falling”, then all setup and hold times will refer to the falling edge of BCLK instead. Please refer to Section 4  TDM interface specifications for additional details. 

**Table 5. TDM interface characteristics** 

|**Symbol**<br>~~a ~~|**Parameter**<br> ~~ae~~|**Test conditions**<br>~~ae~~<br>~~ee~~|**Min.**<br>~~ae~~<br>ee|**Typ.**<br>~~ae~~|**Max.**<br>~~ae~~|**Unit**<br>~~ae~~|
|---|---|---|---|---|---|---|
|MCLK|MCLK frequency nominal|~~ee ~~|ee|12.288||MHz|
|MCLKA|MCLK frequency accuracy||-0.1||0.1|%|
|MCLKJ|MCLK jitter||||1|ns (peak to peak)|
|BCLK|BCLK frequency (1/tp)|in disabled mode|||MCLK|MHz|
|||WCLK = 8 kHz||1.024||MHz|
|||WCLK = 16 kHz||2.048||MHz|
|||WCLK = 24 kHz||3.072||MHz|
|WCLK8|8 kHz WCLK mode|||8||kHz|
|WCLK16|16 kHz WCLK mode|||16|||
|WCLK24|24 kHz WCLK mode|||24|||
|PDC|All clock pin duty cycle<br>(except WCLK)||45||55|%|
|WT|WCLK setup time before BCLK rising/falling edge (tss1)||20|||ns|
|SDOST|SDOUT setup time before BCLK rising/falling edge (tss2)||15|||ns|
|SDOHTR|SDOUT hold time after BCLK rising/falling edge (ths1)||15|||ns|
|SDOHTZ|SDOUT hold time of LSB after BCLK rising/falling edge (ths2)||15||50|ns|
|CMCLK|MCLK pin capacitance||||10|pF|
|CBCLK|BCLK pin capacitance||||10||
|CWCLK|VCLK pin capacitance||||10||
|CSDOUT|SDOUT load capacitance||||60||
|FRREL|Relative frequency response(1)|(2)|-0.5||0.4|dB|



_1. Data by simulation_ 

_2. All the DUT measurement points are normalized to the 294 Hz measurement. The deviation between each point and 294 Hz is calculated. The maximum deviation for points measured at frequencies below 2.0 kHz is given as FRREL._ 

**Figure 2. TDM interface characteristics** 

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**AIS25BA I²C interface characteristics** 

## **3.1** 

## **I²C interface characteristics** 

Refer to Section 5  I²C- inter-IC control interface for additional details. 

The data in the following table are based on standard I²C protocol requirements. Values are not tested in production and are not guaranteed. The I²C interface can be used only to access the registers of the device for configuration purposes, but not for reading accelerometer data. 

**Table 6. Digital input/output voltage for I²C pins** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.(1)**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|VIH|Digital high-level input voltage||0.7*Vdd|||V|
|VIL|Digital low-level input voltage||||0.3*Vdd|V|
|VOL|Low-level output voltage|IOL = 2 mA(2)|0.2|||V|



_1. Typical specifications are not guaranteed._ 

_2. 2 mA is the maximum driving capability, that is, the maximum DC current that can be sourced/sunk by the digital pad in order to guarantee the correct digital output voltage levels VOH and VOL._ 

**Table 7. I²C interface characteristics** 

|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.(1)**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|f(SCL)|SCL||96||400|kHz|
|CSDA-N|SDA/SCL bus capacitance normal mode|RSDA= 2.5 kOhm|||150|pF|
|CSDA-HS|SDA/SCL bus capacitance high-speed mode|RSDA= 2.5 kOhm|||50|pF|
|RSDA|SDA/SCL pull-up resistance||2500|||Ohm|
|tw(SCLL)|SCL clock low time||1.3|||µs|
|tw(SCLH)|SCL clock high time||0.6||||
|tsu(SDA)|SDA setup time||100|||ns|
|th(SDA)|SDA data hold time||0||0.9|µs|
|th(ST)|Start condition hold time||0.6||||
|tsu(SR)|Repeated start condition setup time||0.6||||
|tsu(SP)|Stop condition setup time||0.6||||
|tw(SP:SR)|Bus free time between stop and start condition||1.3||||
|I2C_HYST|SDA/SCL minimum pulse width hysteresis||||50|ns|



_1. Typical specifications are not guaranteed._ 

**DS14019** - **Rev 1** 

**page 7/31** 

**AIS25BA I²C interface characteristics** 

**Figure 3. I²C slave timing diagram** 

**==> picture [431 x 167] intentionally omitted <==**

**----- Start of picture text -----**<br>
REPEATED<br>START<br>START<br>tsu(SR)<br>SDA  tw(SP:SR) START<br>tsu(SDA) th(SDA)<br>tsu(SP) STOP<br>SCL<br>th(ST) tw(SCLL) tw(SCLH)<br>**----- End of picture text -----**<br>


_Note: Measurement points are done at 0.3·Vdd and 0.7·Vdd for both ports._ 

**Table 8. I²C high-speed mode specifications at 1 MHz** 

||**Symbol**|**Parameter**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|---|
|Fast mode plus(1)|fSCL|SCL clock frequency|0|1|MHz|
||tHD;STA|Hold time (repeated) START condition|260|-|ns|
||tLOW|Low period of the SCL clock|500|-||
||tHIGH|High period of the SCL clock|260|-||
||tSU;STA|Setup time for a repeated start condition|260|-||
||tHD;DAT|Data hold time|0|-||
||tSU;DAT|Data setup time|50|-||
||trDA|Rise time of SDA signal|-|120||
||tfDA|Fall time of SDA signal|-|120||
||trCL|Rise time of SCL signal|20*Vdd/5.5|120||
||tfCL|Fall time of SCL signal|20*Vdd/5.5|120||
||tSU;STO|Setup time for stop condition|260|-||
||Cb|Capacitive load for each bus line|-|550|pF|
||tVD;DAT|Data valid time|-|450|ns|
||tVD;ACK|Data valid acknowledge time|-|450||
||VnL|Noise margin at low level|0.1Vdd|-|V|
||VnH|Noise margin at high level|0.2Vdd|-||
||tSP|Pulse width of spikes that must be suppressed by the input filter|0|50|ns|



_1. Data based on characterization, not tested in production_ 

**DS14019** - **Rev 1** 

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**AIS25BA TDM interface specifications** 

## **4 TDM interface specifications** 

Time-division multiplexing (TDM) is a method of putting multiple data streams in one data signal by separating the signal into many frames. There are many ways to accomplish this. 

## **4.1 TDM interface overview** 

The block diagram of the TDM interface implemented in the AIS25BA device is illustrated in the following figure. 

**Figure 4. TDM block diagram** 

As depicted in the figure above, the TDM interface is comprised of two control clocks, a frame synchronization (WCLK) a serial clock (BCLK), and the serial data out (SDOUT). 

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**AIS25BA Frame synchronization (WCLK)** 

## **4.2 Frame synchronization (WCLK)** 

The function of the WCLK is simply to identify the beginning of a frame. In particular the frame start at the rising edge of WCLK, and the WCLK widths supported are: 

- 50% duty cycle 

- One slot width (16 BCLK) 

- One BCLK width 

In TDM mode, AIS25BA shall output accelerometer data on the SDOUT pin at the following sampling rates: 

- WCLK = 8 kHz 

- WCLK = 16 kHz 

- WCLK = 24 kHz 

As depicted in Figure 4. TDM block diagram, the TDM input sampling rate (ODR_8kHz, ODR_16kHz and ODR_24kHz), and the associated data inputs (dataX_8kHz, dataX_16kHz, dataX_24kHz, dataY_8kHz, dataY_16kHz, dataY_24kHz, dataZ_8kHz, dataZ_16kHz and dataZ_24kHz ) can be selected in two different ways: 

1. Using the I²C register wclk_fq (TDM_CTRL_REG (2Eh), bits 2 and 1). In this case the I²C register ODR_AUTO_EN (CTRL_REG_2 (2Fh), bit 0) is equal to zero, that means that the ODR_auto functionality is disabled. 

2. Using the output of the ODR_auto block (ODR_AUTO_EN (CTRL_REG_2 (2Fh), bit 0) equal to one). This latter simply receives as inputs both the MCLK and the WCLK and it computes the current sampling frequency as a ratio between the MCLK and WCLK. 

The possible outputs of the ODR_auto block are: 

- 00: sampling rate equal to 8 kHz (MCLK/WCLK = 1536) 

- 01: sampling rate equal to 16 kHz (MCLK/WCLK = 768) 

- 10: sampling rate equal to 24 kHz (MCLK/WCLK = 512) 

Observing Figure 4, it is possible to see, that if a ratio between MCLK and WCLK differ from 1536, 768 and 512, the sampling rate equal to 8 kHz is selected. 

## **4.3** 

## **Serial clock (BCLK)** 

The sole purpose of the serial clock BCLK is to shift the data out of the serial SDOUT port. To this purpose, the TDM interface uses an internal counter that is set to one when the rising edge of the WCLK is detected, and it is reset to zero when the maximum number of BCLK in a WCLK period is reached. 

The maximum number of BCLK contained in a WCLK period (cmax input of the TDM in Figure 4. TDM block diagram) can be expressed as a function of both the BCLK and WCLK frequencies, and can be computed using the following equation: 

## cmax = WCLKBCLK[−1] 

In order to support a serial clock BCLK variable in the range [1024 MHz, 12.288 MHz], and consequently to compute the correct maximum value of the internal TDM counter, two possible solutions can be selected: 

- The cmax value at the input of the TDM interface can be computed on the fly employing the BCLK_AUTO block (see Figure 4), which is able to compute the cmax value using the above equation. This functionality by default is enabled, and can be disabled employing the I²C register ODR_AUTO_EN (CTRL_REG_2 (2Fh) bit 0). 

- The TDM cmax can be programmed through the I²C registers TDM_cmax (24h-25h). 

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**AIS25BA Mapping the TDM axes** 

## **4.4 Mapping the TDM axes** 

Within one frame, the data signal (DOUT) is divided into multiple segments. We call each segment a slot hereafter in this document. 

The data slot width is fixed and equal to 16 bits. 

In each slot, data should be left-justified (MSB first). 

The number of slots in a WCLK frame can be variable, and it depends on the ratio between BCLK and WCLK. However, as depicted in Table 9 and Table 10, only the slots 0, 1, 2 and 4, 5, 6 can be used to send accelerometer data, all the others slots are always set in high-impedance. 

The mapping of the input data and the TDM output slots is flexible and can be configured through the I²C register mapping (TDM_CTRL_REG (2Eh) bit 4) in Figure 4. 

In particular two possible configurations can be selected: 

- Axes data (X,Y,Z) mapped on TDM slots (0,1,2) (mapping = 0) 

- Axes data (X,Y,Z) mapped on TDM slots (4,5,6) (mapping = 1) 

## **Table 9. X, Y, Z axes mapped to SLOT0, SLOT1, SLOT2** 

|SLOT0|SLOT1|SLOT2|SLOT3|SLOT4|SLOT5|SLOT6|SLOT7|...|SLOTN|
|---|---|---|---|---|---|---|---|---|---|
|X-axis|Y-axis|Z-axis|HiZ|HiZ|HiZ|HiZ|HiZ||HiZ|



## **Table 10. X, Y, Z axes mapped to SLOT4, SLOT5, SLOT6** 

|SLOT0|SLOT1|SLOT2|SLOT3|SLOT4|SLOT5|SLOT6|SLOT7|...|SLOTN|
|---|---|---|---|---|---|---|---|---|---|
|HiZ|HiZ|HiZ|HiZ|X-axis|Y-axis|Z-axis|HiZ||HiZ|



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**AIS25BA TDM configurations** 

## **4.5** 

## **TDM configurations** 

All the AIS25BA TDM configurations programmable over the I²C interface are explained in detail in the following subsections. 

## **4.5.1 Configuration 1** 

- No delay: SLOT0 data MSB is sampled on the first rising edge of BCLK after rising edge of WCLK (delayed I²C register TDM_CTRL_REG (2Eh) bit 6 equal to zero) 

- Data valid: data valid on the rising edge of BCLK (data_valid I²C register TDM_CTRL_REG (2Eh) bit 5 equal to zero) 

## **Figure 5. WCLK, SDOUT change on the falling edge of BCLK and are valid on the rising edge of BCLK, no delay** 

_Note: Setup and hold times are defined in Table 5. TDM interface characteristics._ 

## **4.5.2** 

## **Configuration 2** 

- No delay: SLOT0 data MSB is sampled on the first falling edge of BCLK after rising edge of WCLK (delayed I²C register TDM_CTRL_REG (2Eh) bit 6 equal to zero) 

- Data valid: data valid on the falling edge of BCLK (data_valid I²C register TDM_CTRL_REG (2Eh) bit 5 equal to one) 

**Figure 6. WCLK, SDOUT change on the rising edge of BCLK and are valid on the falling edge of BCLK, no delay** 

_Note: Setup and hold times are defined in Table 5. TDM interface characteristics._ 

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**AIS25BA TDM clocks and MCLK requirements** 

## **4.5.3 Configuration 3** 

- Delayed: SLOT0 data MSB is sampled on the second rising edge of BCLK after rising edge of WCLK (delayed I²C register TDM_CTRL_REG (2Eh) bit 6 equal to one) 

- Data valid: data valid on the rising edge of BCLK (data_valid I²C register TDM_CTRL_REG (2Eh) bit 5 equal to zero) 

- **Figure 7. WCLK, SDOUT change on the falling edge of BCLK and are valid on the rising edge of BCLK, delayed** 

_Note: Setup and hold times are defined in Table 5. TDM interface characteristics._ 

## **4.5.4 Configuration 4** 

- Delayed: SLOT0 data MSB is sampled on the second falling edge of BCLK after rising edge of WCLK (delayed I²C register TDM_CTRL_REG (2Eh) bit 6 equal to one) 

- Data valid: data valid on the falling edge of BCLK (data_valid I²C register TDM_CTRL_REG (2Eh) bit 5 equal to one) 

## **Figure 8. WCLK, SDOUT change on the rising edge of BCLK and are valid on the falling edge of BCLK, delayed** 

_Note:_ 

_Setup and hold times are defined in Table 5. TDM interface characteristics._ 

## **4.6 TDM clocks and MCLK requirements** 

The relationship between TDM clocks and MCLK should be: 

- Both BCLK and WCLK must be obtained from MCLK by integer division. This requirement is mandatory since ADC is clocked by MCLK, so the TDM data rate must be perfectly synchronous in frequency and phase with the decimated ADC data rate. 

- The BCLK/WCLK ratio must be an integer value. 

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**AIS25BA I²C- inter-IC control interface** 

**5 I²C- inter-IC control interface** 

## **5.1 I²C interface** 

The registers embedded inside the AIS25BA may be accessed also through the I²C serial interfaces. 

**Table 11. I²C serial interface pin description** 

|**Pin name**|**Pin description**|
|---|---|
|I2C_SCL|I²C serial clock (SCL)|
|I2C_SDA|I²C serial data (SDA)|



The AIS25BA I²C is a bus slave. The I²C is employed to write data into registers whose content can also be read back. 

The relevant I²C terminology is given in the table below. 

**Table 12. I²C terminology** 

|**Term**|**Description**|
|---|---|
|Transmitter|The device that sends data to the bus|
|Receiver|The device that receives data from the bus|
|Master|The device that initiates a transfer, generates clock signals, and terminates a transfer|
|Slave|The device addressed by the master|



There are two signals associated with the I²C bus: the serial clock line (SCL) and the serial data line (SDA). The latter is a bidirectional line used for sending and receiving the data to/from the interface. Both lines must be connected to Vdd through an external pull-up resistor. When the bus is free, both lines are high. 

The I²C interface is compliant with fast mode (400 kHz) I²C standards as well as with the normal mode. 

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**AIS25BA I²C interface details** 

## **5.2** 

## **I²C interface details** 

The transaction on the bus is started through a start signal. A start condition is defined as a high to low transition on the data line while the SCL line is held high (refer to the ST condition in the following paragraph). After this signal has been transmitted by the master, the bus is considered busy. The next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave (SAD subsequences). When an address is sent, each device in the system compares the first seven bits after a start condition with its address. If they match, the device considers itself addressed by the master. The address can be made up of a programmable part and a fixed part, thus allowing more than one device of the same type to be connected to the I²C bus. 

Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line low so that it remains stable low during the high period of the acknowledge clock pulse (SAK subsequence). A receiver that has been addressed must generate an acknowledge after each byte of data has been received. The I²C embedded inside the AIS25BA behaves like a slave device and the following protocol must be adhered to. After the start condition (ST) a slave address is sent, once a slave acknowledge has been returned (SAK), an 8-bit subaddress is transmitted (SUB): the 7 LSB represent the actual register address while the MSB enables address auto-increment. If the MSB of the SUB field is 1, the SUB (register address) is automatically incremented to allow multiple data read/write at increasing addresses. Otherwise, if the MSB of the SUB field is 0, the SUB remains unchanged and multiple read/write on the same address can be performed. If the LSB of the slave address is 1 (read), a repeated start (SR) condition must be issued after the subaddress byte; if the LSB is 0 (write) the master transmits to the slave with direction unchanged. 

## **5.3 I²C slave address** 

The slave address is equal to 001100yx (TDM mode, where y = not(I2C_A0 pin)) or in case of writing or reading respectively. 

## **5.4 I²C read and write sequences** 

Previous subsequences are used for the actual write and read sequences described in the tables below. 

**Table 13. Transfer when master is writing one byte to slave** 

|Master|Master|ST|ST|SAD + W|SAD + W|||SUB|SUB|||DATA|DATA|||SP|SP|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Slave||||||SAK||||SAK||||SAK||||
|**Table 14.Transfer when master is writing multiple bytes to slave**||||||||||||||||||
|Master|ST||SAD + W||||SUB||DATA||||DATA||||SP|
|Slave|||||SAK|||SAK|||SAK||||SAK|||



## **Table 15. Transfer when master is receiving (reading) one byte of data from slave** 

|Master|ST|SAD + W||SUB||SR|SAD + R|||NMAK|SP|
|---|---|---|---|---|---|---|---|---|---|---|---|
|Slave|||SAK||SAK|||SAK|DATA|||



**Table 16. Transfer when master is receiving (reading) multiple bytes of data from slave** 

|Master|ST|SAD+W||SUB||SR|SAD+R|||MAK||MAK||NMAK|SP|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Slave|||SAK||SAK|||SAK|DATA||DATA||DATA|||



Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred per transfer is unlimited. Data is transferred with the most significant bit (MSB) first. If a slave receiver doesn’t acknowledge the slave address (that is, it is not able to receive because it is performing some real-time function) the data line must be left high by the slave. The master can then abort the transfer. A low to high transition on the SDA line while the SCL line is high is defined as a stop condition (SP). Each data transfer must be terminated by the generation of a stop condition. 

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**AIS25BA Features** 

**6 Features** 

## **6.1** 

## **Self-test mode** 

In self-test mode the mechanical element is stimulated by electrostatic force to obtain an equivalent input force applied to the sensor. This equivalent input force applied has to be comparable with the full-scale range in order to have an effective self-test mode. 

The self-test mode can be enabled using the I²C interface, setting the ST bit in register TEST_REG (0Bh) to 1. 

For the self-test values of each axis please refer to Table 2. Mechanical characteristics. 

## **6.2 Power cycle/reset information** 

## **6.2.1 TDM interface power-on sequence** 

In TDM, the AIS25BA starts in disabled mode with the following sequence. 

**Figure 9. Power-on sequence (TDM interface)** 

In the figure above, T0 represents the time when Vdd reaches 90% of the final value. 

After TDIS = 5.5 ms the AIS25BA reaches the disabled mode condition. 

The TDM interface must be activated explicitly with I²C configuration. The first 3 samples after the enabling of the TDM may be invalid samples due to the fact that the interface should sync on the external WCLK. The samples will be invalid also after any subsequent disable-enable transition that may happen. TDM protocol can be changed on the fly, but also in this case the first 3 samples after the TDM configuration change will be invalid. 

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**AIS25BA** 

**Power cycle/reset information** 

## **6.2.2 Disabled mode** 

The AIS25BA can be put in disabled mode using the I²C interface. The power-down command will be executed immediately (no wait state). 

The AIS25BA can be resumed from disabled mode using the I²C as well. In this case the MCLK/BCLK/WCLK clocks must be set to the correct values before writing to the I²C. 

Please refer to the following figure for the disabled mode sequence. 

**Figure 10. Disabled mode sequence** 

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**AIS25BA Register map** 

## **7** 

## **Register map** 

The table below provides a list of the 8-bit registers embedded in the device and their respective addresses. 

## **Table 17. Registers address map** 

|**Nm**|**T(1)**|**Register address**|**Register address**|**Dflt**|
|---|---|---|---|---|
|**ae**|**ype**|**Hex**|**Binary**|**eau**|
|TEST_REG|R/W|0B|0000 1011|0000 0000|
|WHO_AM_I|R|0F|0000 1111|0010 0000|
|TDM_cmax[11:8]|R/W|24|0010 0100|0000 0000|
|TDM_cmax[7:0]|R/W|25|0010 0101|0111 1111|
|CTRL_REG_1|R/W|26|0010 0110|0010 0000|
|TDM_CTRL_REG|R/W|2E|0010 1110|1111 0000|
|CTRL_REG_2|R/W|2F|0010 1111|1110 0001|
|CTRL_REG_FS|R/W|30|0011 1111|0000 0000|



_1. Read only (R) - read/write (R/W)_ 

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**AIS25BA Register description** 

## **8 Register description** 

## **8.1 TEST_REG (0Bh)** 

Self-test register (R/W) 

## **Table 18. TEST_REG register** 

0[(1)] 0[(1)] 0[(1)] 0[(1)] ST 0[(1)] 0[(1)] 0[(1)] 

_1. This bit must be set to 0 for the correct operation of the device._ 

## **Table 19. TEST_REG register description** 

Enables self-test mode. Default value: 0 ST (0: disabled; 1: enabled) 

## **8.2 WHO_AM_I (0Fh)** 

Device identification register (R) 

## **Table 20. WHO_AM_I register** 

0 0 1 0 0 0 0 0 

## **8.3 TDM_cmax (24h-25h)** 

TDM counter max value when the BCLK autoconfiguration feature is disabled (R/W) 

## **Table 21. TDM_cmax register** 

|-|-|-|-|TDM_cmax[11:8] MSB|
|---|---|---|---|---|
||||||
|TDM_cmax[7:0] LSB|||||



## **8.4 CTRL_REG_1 (26h)** 

Control register (R/W) 

## **Table 22. CTRL_REG_1 register** 

0[(1)] 0[(1)] PD 0[(1)] 0[(1)] 0[(1)] 0[(1)] 0[(1)] 

_1. This bit must be set to 0 for the correct operation of the device._ 

## **Table 23. CTRL_REG_1 register description** 

Device in disabled mode. Default value: 1 PD (0: normal mode; 1: disabled mode: minimum power consumption, I²C still active) 

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**AIS25BA TDM_CTRL_REG (2Eh)** 

## **8.5 TDM_CTRL_REG (2Eh)** 

(R/W) 

## **Table 24. TDM_CTRL_REG register** 

TDM_pd Delayed data_valid mapping 0[(1)] WCLK_fq1 WCLK_fq0 0[(1)] 

_1. This bit must be set to 0 for the correct operation of the device._ 

## **Table 25. TDM_CTRL_REG register description** 

||**Table 25.TDM_CTRL_REG register description**|
|---|---|
|TDM_pd|Enables TDM. Default value: 1<br>(0: TDM on; 1: TDM off)|
|Delayed|TDM delayed configuration. Default value: 1<br>(0: TDM no delayed configuration; 1: TDM delayed configuration)|
|data_valid|TDM data valid. Default value: 1<br>(0: data valid on the rise edge of BCLK; 1: data valid on the falling edge of BCLK)|
|mapping|TDM mapping. Default value: 1<br>(0: AXEX → SLOT0; AXEY → SLOT1; AXEZ → SLOT2;<br>1: AXEX → SLOT4; AXEY → SLOT5; AXEZ → SLOT6)|
|WCLK_fq [1:0]|TDM clock frequencies. Default value: 00<br>(00: WCLK = 8 kHz;<br>01: WCLK = 16 kHz;<br>10: WCLK = 24 kHz)|



## **8.6** 

## **CTRL_REG_2 (2Fh)** 

(R/W) 

## **Table 26. CTRL_REG_2 register** 

|1(1)|1(1)|1(1)|0(2)|0(2)|0(2)|0(2)|ODR_AUTO_<br>EN|
|---|---|---|---|---|---|---|---|



_1. This bit must be set to 1 for the correct operation of the device._ 

_2. This bit must be set to 0 for the correct operation of the device._ 

## **Table 27. CTRL_REG_2 register description** 

Enables auto ODR. Default value: 1 

ODR_AUTO_EN 

(0: auto ODR and BCLK disabled[(1)] ; 1: auto ODR and BCLK enabled[(2)] ) 

_1. In this case it is mandatory to set TDM_CTRL_REG (2Eh) bits 2 and 1 to match the WCLK sampling rate and TDM_cmax (24h-25h) to match the BCLK/WCLK ratio_ 

_2. AIS25BA automatically measures the ratio r = MCLK/WCLK. The WCLK frequency is internally determined as FW=12.288 MHz/r. FW is used to configure automatically the decimation ratio between the ADC and TDM input data rate (same as TDM output data rate) bypassing TDM_CTRL_REG (2Eh) bits 2 and 1 configuration. When ODR_AUTO is 1 also the BCLK/WCLK ratio is automatically computed for proper TDM configuration as described in TDM_cmax (24h-25h)._ 

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**AIS25BA CTRL_REG_FS (30h)** 

## **8.7 CTRL_REG_FS (30h)** 

Accelerometer full-scale selection (R/W) 

## **Table 28. CTRL_REG_FS register** 

0[(1)] 0[(1)] 0[(1)] 0[(1)] 0[(1)] 0[(1)] 0[(1)] FS 

_1. This bit must be set to 0 for the correct operation of the device._ 

## **Table 29. CTRL_REG_FS register description** 

Full-scale range selection. Default value: 0 FS (0: FS ±3.85 _g_ ; 1: ±7.7 _g_ ) 

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**AIS25BA Soldering information** 

**9 Soldering information** 

The LGA package is compliant with the ECOPACK and RoHS standard. 

It is qualified for soldering heat resistance according to JEDEC J-STD-020. 

For land pattern and soldering recommendations, consult technical note TN0018 available on www.st.com. 

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**AIS25BA Package information** 

## **10 Package information** 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 

## **10.1 LGA-14 package information** 

The LGA-14 package is classified MSL 3. 

**Figure 11. LGA-14 2.5 x 2.5 x 0.86 mm package outline and mechanical data** 

**==> picture [449 x 184] intentionally omitted <==**

**----- Start of picture text -----**<br>
0.01 C<br>Pin 1 ref#  W   H   0.25  Pin 1 ref#<br>A B  0.30   0.60 ±0.05   0.10 ±0.05<br>C (x4)<br> 0.50<br>0.05 C<br> 1.00<br>Top View Side view Bottom View<br> L   1.50<br> 0.75   0.60 ±0.05<br>**----- End of picture text -----**<br>


Dimensions are in millimeters unless otherwise specified General tolerance is +/-0.1mm unless otherwise specified 

## OUTER DIMENSIONS 

||OUTER DIMENSIONS|||
|---|---|---|---|
|ITEM|DIMENSION (mm)|TOLERANCE (mm)||
|Lenght (L)|2.5||0.1|
|Width (W)|2.5||0.1|
|Height (H)|0.86 Max||/|



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**AIS25BA LGA-14 packing information** 

## **10.2 LGA-14 packing information** 

**Figure 12. Carrier tape information for LGA-14 package** 

**Figure 13. LGA-14 package orientation in carrier tape** 

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**AIS25BA LGA-14 packing information** 

**Figure 14. Reel information for carrier tape of LGA-14 package** 

**==> picture [363 x 213] intentionally omitted <==**

**----- Start of picture text -----**<br>
T<br>40mm min.<br>Access hole at<br>slot location<br>B<br>C<br>D N<br>A<br>G measured at hub<br>Full radius<br>Tape slot<br>in core for<br>tape start<br>2.5mm min. width<br>**----- End of picture text -----**<br>


**Table 30. Reel dimensions for carrier tape of LGA-14 package** 

|**Reel dimensions (mm)**|**Reel dimensions (mm)**|
|---|---|
|A (max)|330|
|B (min)|1.5|
|C|13 ±0.25|
|D (min)|20.2|
|N (min)|60|
|G|12.4 +2/-0|
|T (max)|18.4|



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**AIS25BA** 

## **Revision history** 

## **Table 31. Document revision history** 

|**Date**|**Version**|**Changes**|
|---|---|---|
|18-Jul-2022|1|Initial release|



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**AIS25BA Contents** 

|**Contents**|**Contents**||
|---|---|---|
|**1**|**Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2**||
|**2**|**Mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3**||
||**2.1**|Mechanical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3|
||**2.2**|Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4|
||**2.3**|Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5|
|**3**|**TDM interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6**||
||**3.1**|I²C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7|
|**4**|**TDM interface specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9**||
||**4.1**|TDM interface overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9|
||**4.2**|Frame synchronization (WCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10|
||**4.3**|Serial clock (BCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10|
||**4.4**|Mapping the TDM axes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11|
||**4.5**|TDM configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12|
|||**4.5.1**<br>Configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12|
|||**4.5.2**<br>Configuration 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12|
|||**4.5.3**<br>Configuration 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13|
|||**4.5.4**<br>Configuration 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13|
||**4.6**|TDM clocks and MCLK requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13|
|**5**|**I²C- inter-IC control interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14**||
||**5.1**|I²C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14|
||**5.2**|I²C interface details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15|
||**5.3**|I²C slave address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15|
||**5.4**|I²C read and write sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15|
|**6**|**Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16**||
||**6.1**|Self-test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16|
||**6.2**|Power cycle/reset information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16|
|||**6.2.1**<br>TDM interface power-on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16|
|||**6.2.2**<br>Disabled mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17|
|**7**|**Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18**||
|**8**|**Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19**||
||**8.1**|TEST_REG (0Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19|
||**8.2**|WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19|
||**8.3**|TDM_cmax (24h-25h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19|
||**8.4**|CTRL_REG_1 (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19|



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**AIS25BA Contents** 

||**8.5**<br>TDM_CTRL_REG (2Eh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20|
|---|---|
||**8.6**<br>CTRL_REG_2 (2Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20|
||**8.7**<br>CTRL_REG_FS (30h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21|
|**9**|**Soldering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22**|
|**10**|**Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23**|
||**10.1**<br>LGA-14 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23|
||**10.2**<br>LGA-14 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24|
|**Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26**||
|**List**|**of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29**|
|**List**|**of figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30**|



**DS14019** - **Rev 1** 

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**AIS25BA List of tables** 

## **List of tables** 

|**Table**|**1.**|Pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2|
|---|---|---|
|**Table**|**2.**|Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3|
|**Table**|**3.**|Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4|
|**Table**|**4.**|Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5|
|**Table**|**5.**|TDM interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6|
|**Table**|**6.**|Digital input/output voltage for I²C pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7|
|**Table**|**7.**|I²C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7|
|**Table**|**8.**|I²C high-speed mode specifications at 1 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8|
|**Table**|**9.**|X, Y, Z axes mapped to SLOT0, SLOT1, SLOT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11|
|**Table**|**10.**|X, Y, Z axes mapped to SLOT4, SLOT5, SLOT6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11|
|**Table**|**11.**|I²C serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14|
|**Table**|**12.**|I²C terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14|
|**Table**|**13.**|Transfer when master is writing one byte to slave. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15|
|**Table**|**14.**|Transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15|
|**Table**|**15.**|Transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15|
|**Table**|**16.**|Transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . . . . . . . . . . . . . . . . . 15|
|**Table**|**17.**|Registers address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18|
|**Table**|**18.**|TEST_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19|
|**Table**|**19.**|TEST_REG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19|
|**Table**|**20.**|WHO_AM_I register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19|
|**Table**|**21.**|TDM_cmax register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19|
|**Table**|**22.**|CTRL_REG_1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19|
|**Table**|**23.**|CTRL_REG_1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19|
|**Table**|**24.**|TDM_CTRL_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20|
|**Table**|**25.**|TDM_CTRL_REG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20|
|**Table**|**26.**|CTRL_REG_2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20|
|**Table**|**27.**|CTRL_REG_2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20|
|**Table**|**28.**|CTRL_REG_FS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21|
|**Table**|**29.**|CTRL_REG_FS register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21|
|**Table**|**30.**|Reel dimensions for carrier tape of LGA-14 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25|
|**Table**|**31.**|Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26|



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**AIS25BA List of figures** 

## **List of figures** 

|**Figure**|**1.**|Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2|
|---|---|---|
|**Figure**|**2.**|TDM interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6|
|**Figure**|**3.**|I²C slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8|
|**Figure**|**4.**|TDM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9|
|**Figure**|**5.**|WCLK, SDOUT change on the falling edge of BCLK and are valid on the rising edge of BCLK, no delay . . . . . 12|
|**Figure**|**6.**|WCLK, SDOUT change on the rising edge of BCLK and are valid on the falling edge of BCLK, no delay . . . . . 12|
|**Figure**|**7.**|WCLK, SDOUT change on the falling edge of BCLK and are valid on the rising edge of BCLK, delayed. . . . . . 13|
|**Figure**|**8.**|WCLK, SDOUT change on the rising edge of BCLK and are valid on the falling edge of BCLK, delayed. . . . . . 13|
|**Figure**|**9.**|Power-on sequence (TDM interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16|
|**Figure**|**10.**|Disabled mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17|
|**Figure**|**11.**|LGA-14 2.5 x 2.5 x 0.86 mm package outline and mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23|
|**Figure**|**12.**|Carrier tape information for LGA-14 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24|
|**Figure**|**13.**|LGA-14 package orientation in carrier tape. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24|
|**Figure**|**14.**|Reel information for carrier tape of LGA-14 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25|



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**AIS25BA** 

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**DS14019** - **Rev 1** 

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