ADXL354CEZ

MEMS Accelerometer, ± 2g, ± 8g, X, Y, Z, LCC, 14 Pins, 100mV/g

⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
Manufacturer: ANALOG DEVICES
Product type: MEMS Accelerometers
SVHC: No SVHC (04-Feb-2026)
No. of Pins: 14Pins
Sensing Axis: X, Y, Z
Product Range: -
Qualification: -
Sensitivity Max: 108mV/g
Sensitivity Min: 92mV/g
Sensitivity Typ: 100mV/g
Output Interface: -
Sensor Case Style: LCC
MEMS Sensor Output: Analogue
Supply Voltage Max: 3.6V
Supply Voltage Min: 2.25V
Sensor Case / Package: LCC
Operating Temperature Max: 125°C
Operating Temperature Min: -40°C
Sensing Range - Accelerometer: ± 2g, ± 8g
Delivery and price
Units per pack	100
Price	38.61 €
Current stock	200+
Lead time	30 days
Datasheet
**==> picture [160 x 45] intentionally omitted <==**

## **Low Noise, Low Drift, Low Power, 3-Axis MEMS Accelerometers** 

## **Data Sheet** 

## **ADXL354/ADXL355** 

## **FEATURES** 

## **Hermetic package offers excellent long-term stability** 

- **0** _**g**_ **offset vs. temperature (all axes): 0.15 m** _**g**_ **/°C maximum Ultralow noise density (all axes): 20 μ** _**g**_ **/√Hz (ADXL354) Low power, VSUPPLY (LDO enabled)** 

- **ADXL354 in measurement mode: 150 μA ADXL355 in measurement mode: 200 μA ADXL354/ADXL355 in standby mode: 21 μA** 

- **ADXL354 has user adjustable analog output bandwidth ADXL355 digital output features** 

- **Digital serial peripheral interface (SPI)/I[2] C interfaces 20-bit analog-to-digital converter (ADC) Data interpolation routine for synchronous sampling Programmable high- and low-pass digital filters** 

**Electromechanical self test Integrated temperature sensor Voltage range options** 

- **VSUPPLY with internal regulators: 2.25 V to 3.6 V** 

- **V1P8ANA, V1P8DIG with internal low dropout regulator (LDO) bypassed: 1.8 V typical ± 10%** 

**Operating temperature range: −40°C to +125°C** 

- **14-terminal, 6 mm × 6 mm × 2.1 mm, LCC package,** 

## **FUNCTIONAL BLOCK DIAGRAMS** 

**==> picture [231 x 253] intentionally omitted <==**

**----- Start of picture text -----**<br>
V1P8ANA V1P8DIG RANGE<br>VSUPPLY LDO LDO MANAGEMENTPOWER<br>XOUT<br>YOUT ANALOGFILTER ST1<br>3-AXIS<br>OUT SENSOR CONTROL ST2<br>LOGIC STBY<br>TEMP SENSORTEMP ADXL354 VDDIO<br>VSSIO VSS<br>Figure 1. ADXL354 Functional Block Diagram<br>V1P8ANA V1P8DIG VDDIO<br>POWER<br>VSUPPLY LDO LDO ADXL355 MANAGEMENT<br>ADC INT1<br>ANALOG ADC DIGITAL CONTROLLOGIC INT2<br>FILTER FILTER DRDY<br>3-AXIS ADC CS/SCL<br>SENSOR<br>SCLK/VSSIO<br>SENSORTEMP ADC FIFO SERIALI/O MOSI/SDAMISO/ASEL<br>VSSIO VSS<br>Figure 2. ADXL355 Functional Block Diagram<br>14205-002<br>14205-001<br>**----- End of picture text -----**<br>


- **0.26 grams** 

## **APPLICATIONS** 

**Inertial measurement units (IMUs)/altitude and heading reference systems (AHRSs)** 

## **Platform stabilization systems Structural health monitoring** 

## **Seismic imaging** 

## **Tilt sensing** 

## **Robotics Condition monitoring** 

## **GENERAL DESCRIPTION** 

The analog output ADXL354 and the digital output ADXL355 are low noise density, low 0 _g_ offset drift, low power, 3-axis accelerometers with selectable measurement ranges. The ADXL354B supports the ±2 _g_ and ±4 _g_ ranges, the ADXL354C supports the ±2 _g_ and ±8 _g_ ranges, and the ADXL355 supports the ±2.048 _g_ , ±4.096 _g_ , and ±8.192 _g_ ranges. The ADXL354/ ADXL355 offer industry leading noise, minimal offset drift over temperature, and long term stability enabling precision applications with minimal calibration. 

Highly integrated in a compact form factor, the low power ADXL355 is ideal in an Internet of Things (IoT) sensor node and other wireless product designs. 

The ADXL355 multifunction pin names may be referenced by their relevant function only for either the SPI or I[2] C interfaces. 

1 Protected by U.S. Patents 8,472,270; 9,041,462; 8,665,627; 8,917,099; 6,892,576; 9,297,825; and 7,956,621. 

**Document Feedback** 

**Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.** 

**One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2016–2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com** 

**ADXL354/ADXL355** 

**Data Sheet** 

## **TABLE OF CONTENTS** 

Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagrams ............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Analog Output for the ADXL354 ............................................... 3 Digital Output for the ADXL355 ............................................... 4 SPI Digital Interface Characteristics for the ADXL355 .......... 5 I[2] C Digital Interface Characteristics for the ADXL355 ........... 6 Absolute Maximum Ratings ............................................................ 8 Thermal Resistance ...................................................................... 8 ESD Caution .................................................................................. 8 Pin Configurations and Function Descriptions ........................... 9 Typical Performance Characteristics ........................................... 11 Root Allan Variance (RAV) ADXL355 Characteristics ......... 19 Theory of Operation ...................................................................... 20 Analog Output ............................................................................ 20 Digital Output ............................................................................. 21 Axes of Acceleration Sensitivity ............................................... 21 Power Sequencing ...................................................................... 22 Power Supply Description ......................................................... 22 Overrange Protection ................................................................. 22 Self Test ........................................................................................ 22 Filter ............................................................................................. 23 Serial Communications ................................................................. 25 SPI Protocol ................................................................................. 25 I[2] C Protocol ................................................................................. 26 Reading Acceleration or Temperature Data from the Interface ....................................................................................................... 26 FIFO ................................................................................................. 27 Interrupts ......................................................................................... 28 DATA_RDY ................................................................................. 28 DRDY Pin .................................................................................... 28 FIFO_FULL ................................................................................. 28 FIFO_OVR .................................................................................. 28 Activity ......................................................................................... 28 

NVM_BUSY ............................................................................... 28 External Synchronization and Interpolation .......................... 29 ADXL355 Register Map ................................................................. 31 Register Definitions........................................................................ 32 Analog Devices ID Register ...................................................... 32 Analog Devices MEMS ID Register ......................................... 32 Device ID Register ..................................................................... 32 Product Revision ID Register ................................................... 32 Status Register ............................................................................. 32 FIFO Entries Register ................................................................ 33 Temperature Data Registers ...................................................... 33 X-Axis Data Registers ................................................................ 33 Y-Axis Data Registers ................................................................ 34 Z-Axis Data Registers ................................................................ 34 FIFO Access Register ................................................................. 35 X-Axis Offset Trim Registers .................................................... 35 Y-Axis Offset Trim Registers .................................................... 35 Z-Axis Offset Trim Registers .................................................... 36 Activity Enable Register ............................................................ 36 Activity Threshold Registers ..................................................... 36 Activity Count Register ............................................................. 36 Filter Settings Register ............................................................... 37 FIFO Samples Register .............................................................. 37 Interrupt Pin (INTx) Function Map Register......................... 37 Data Synchronization ................................................................ 38 I[2] C Speed, Interrupt Polarity, and Range Register ................. 38 Power Control Register ............................................................. 38 Self Test Register ......................................................................... 39 Reset Register .............................................................................. 39 Recommended Soldering Profile ................................................. 40 PCB Footprint Pattern ............................................................... 41 Packaging and Ordering Information ......................................... 42 Outline Dimensions ................................................................... 42 Branding Information ................................................................ 42 Ordering Guide .......................................................................... 42 

## **REVISION HISTORY** 

## **4/2018—Rev. 0 to Rev.** 

## **8/2016—Revision 0: Initial Version** 

Added Vibration Parameter, Table 5 .............................................. 8 Changes to Overrange Protection Section .................................. 22 

Rev. A | Page 2 of 42 

**Data Sheet** 

**ADXL354/ADXL355** 

## **SPECIFICATIONS** 

## **ANALOG OUTPUT FOR THE ADXL354** 

TA = 25°C, VSUPPLY = 3.3 V, x-axis acceleration and y-axis acceleration = 0 _g_ , and z-axis acceleration = 1 _g_ , unless otherwise noted. 

**Table 1.** 

|**Table 1.**||||
|---|---|---|---|
|**Parameter**|**Test Conditions/Comments**|**Min**<br>**Typ**<br>**Max**|**Unit**|
|SENSOR INPUT<br>Output Full-Scale Range (FSR)<br>Resonant Frequency1<br>Nonlinearity<br>Cross Axis Sensitivity|Each axis<br>ADXL354B, supports two ranges<br>ADXL354C, supports two ranges<br>±2_g_|±2/±4<br>±2/±8<br>2.4<br>0.1<br>1|_g_<br>_g_<br>kHz<br>%<br>%|
|SENSITIVITY<br>Sensitivity at XOUT, YOUT, ZOUT<br>SensitivityChange due to Temperature|Ratiometric to V1P8ANA<br>±2_g_<br>±4_g_<br>±8_g_<br>−40°C to +125°C|368<br>400<br>432<br>184<br>200<br>216<br>92<br>100<br>108<br>±0.01|mV/_g_<br>mV/_g_<br>mV/_g_<br>%/°C|
|0_g_OFFSET<br>0_g_Output for XOUT, YOUT, ZOUT<br>0_g_Offset vs. Temperature (X-Axis, Y-Axis, and Z-Axis)2<br>Repeatability3<br>Vibration Rectification Error (VRE)4|Each axis, ±2_g_<br>Referred to V1P8ANA/2<br>−40°C to +125°C<br>X-axis and y-axis<br>Z-axis<br>±2_g_range, in a 1_g_orientation,<br>offset due to 2.5_g_rms vibration|−75<br>±25<br>+75<br>−0.15<br>±0.1<br>+0.15<br>±3.5<br>±9<br><0.4|m_g_<br>m_g_/°C<br>m_g_<br>m_g_<br>_g_|
|NOISE DENSITY<br>X-Axis, Y-Axis, and Z-Axis<br>Velocity Random Walk|±2_g_<br>X-axis and y-axis<br>Z-axis|20<br>9<br>13|μ_g_/√Hz<br>μm/sec/Hr<br>μm/sec/Hr|
|BANDWIDTH<br>Internal Low-Pass Filter Frequency|Fixed frequency, 50% response<br>attenuation|1500|Hz|
|SELF TEST<br>Output Change<br>X-Axis<br>Y-Axis<br>Z-Axis||0.3<br>0.3<br>1.5|_g_<br>_g_<br>_g_|
|POWER SUPPLY<br>Voltage Range<br>VSUPPLY5<br>VDDIO<br>V1P8ANA, V1P8DIGwith Internal Low Dropout<br>Regulator (LDO) Bypassed<br>Current<br>Measurement Mode<br>VSUPPLY(LDO Enabled)<br>V1P8ANA(LDO Disabled)<br>V1P8DIG(LDO Disabled)<br>Standby Mode<br>VSUPPLY(LDO Enabled)<br>V1P8ANA(LDO Disabled)<br>V1P8DIG(LDO Disabled)<br>Turn On Time6|VSUPPLY= 0 V<br>2_g_range<br>Power-off to standby|2.25<br>2.5<br>3.6<br>V1P8DIG<br>2.5<br>3.6<br>1.62<br>1.8<br>1.98<br>150<br>138<br>12<br>21<br>7<br>10<br><10<br><10|V<br>V<br>V<br>μA<br>μA<br>μA<br>μA<br>μA<br>μA<br>ms<br>ms|



Rev. A | Page 3 of 42 

**Data Sheet** 

## **ADXL354/ADXL355** 

|**Parameter**|**Test Conditions/Comments**|**Min**<br>**Typ**<br>**Max**|**Unit**|
|---|---|---|---|
|OUTPUT AMPLIFIER<br>Swing<br>Output Series Resistance|No load|0.03<br>V1P8ANA− 0.03<br>32|V<br>kΩ|
|TEMPERATURE SENSOR<br>Output at 25°C<br>Scale Factor||892.2<br>3.0|mV<br>mV/°C|
|TEMPERATURE<br>OperatingTemperature Range||−40<br>+125|°C|



1 The resonant frequency is a sensor characteristic. An integrated analog 1.5 kHz (−6 dB) sinc low-pass filter that cannot be bypassed limits the actual output response. 2 The temperature change is −40°C to +25°C or +25°C to +125°C. 

3 Repeatability is predicted for a 10 year life and includes shifts due to the high temperature operating life test (HTOL) (TA = 150°C, VSUPPLY = 3.6 V, and 1000 hours), temperature cycling (−55°C to +125°C and 1000 cycles), velocity random walk, broadband noise, and temperature hysteresis. 

> 4 The VRE measurement is the shift in dc offset while the device is subject to 2.5 _g_ rms of random vibration from 50 Hz to 2 kHz. The device under test (DUT) is configured for the ±2 _g_ range and an output data rate of 4 kHz. The VRE scales with the range setting. 

5 When V1P8ANA and V1P8DIG are generated internally, VSUPPLY is valid. To disable the LDO and drive V1P8ANA and V1P8DIG externally, connect VSUPPLY to VSS. 

> 6 Standby to measurement mode; valid when the output is within 1 m _g_ of the final value. 

## **DIGITAL OUTPUT FOR THE ADXL355** 

TA = 25°C, VSUPPLY = 3.3 V, x-axis acceleration and y-axis acceleration = 0 _g_ , and z-axis acceleration = 1 _g_ , and output data rate (ODR) = 500 Hz, unless otherwise noted. Note that multifunction pin names may be referenced by their relevant function only. 

**Table 2.** 

|**Table 2.**||||
|---|---|---|---|
|**Parameter**|**Test Conditions/Comments**|**Min**<br>**Typ**<br>**Max**|**Unit**|
|SENSOR INPUT<br>Output Full Scale Range (FSR)<br>Nonlinearity<br>Cross Axis Sensitivity|Each axis<br>User selectable<br>±2_g_|±2.048<br>±4.096<br>±8.192<br>0.1<br>1|_g_<br>_g_<br>_g_<br>% FS<br>%|
|SENSITIVITY<br>X-Axis, Y-Axis, and Z-Axis Sensitivity<br>X-Axis, Y-Axis, and Z-Axis Scale Factor<br>SensitivityChange due to Temperature|Each axis<br>±2_g_<br>±4_g_<br>±8_g_<br>±2_g_<br>±4_g_<br>±8_g_<br>−40°C to +125°C|235,520<br>256,000<br>276,480<br>117,760<br>128,000<br>138,240<br>58,880<br>64,000<br>69,120<br>3.9<br>7.8<br>15.6<br>±0.01|LSB/_g_<br>LSB/_g_<br>LSB/_g_<br>μ_g/_LSB<br>μ_g/_LSB<br>μ_g/_LSB<br>%/°C|
|0_g_OFFSET<br>X-Axis, Y-Axis, and Z-Axis 0_g_Output<br>0_g_Offset vs. Temperature (X-Axis, Y-Axis, and Z-Axis)1<br>Repeatability2<br>Vibration Rectification3|Each axis, ±2_g_<br>−40°C to +125°C<br>X-axis and y-axis<br>Z-axis<br>±2_g_range, in a 1_g_orientation,<br>offset due to 2.5_g_rms vibration|−75<br>±25<br>+75<br>−0.15<br>±0.02<br>+0.15<br>±3.5<br>±9<br><0.4|m_g_<br>m_g_/°C<br>m_g_<br>m_g_<br>_g_|
|NOISE DENSITY<br>X-Axis, Y-Axis, and Z-Axis<br>Velocity Random Walk|±2_g_<br>X-axis and y-axis<br>Z-axis|25<br>9<br>13|μ_g_/√Hz<br>μm/sec/Hr<br>μm/sec/Hr|
|OUTPUT DATA RATE AND BANDWIDTH<br>Low-Pass Filter Passband Frequency<br>High-Pass Filter Passband Frequency When Enabled<br>(Disabled byDefault)|User programmable, Register 0x28<br>User programmable, Register 0x28<br>for 4 kHz ODR|1<br>1000<br>0.0095<br>10|Hz<br>Hz|



Rev. A | Page 4 of 42 

## **Data Sheet** 

## **ADXL354/ADXL355** 

|**Parameter**|**Test Conditions/Comments**|**Min**<br>**Typ**<br>**Max**|**Unit**|
|---|---|---|---|
|SELF TEST<br>Output Change<br>X-Axis<br>Y-Axis<br>Z-Axis||0.3<br>0.3<br>1.5|_g_<br>_g_<br>_g_|
|POWER SUPPLY<br>Voltage Range<br>VSUPPLYOperating4<br>VDDIO<br>V1P8ANAand V1P8DIGwith Internal LDO Bypassed<br>Current<br>Measurement Mode<br>VSUPPLY(LDO Enabled)<br>V1P8ANA(LDO Disabled)<br>V1P8DIG(LDO Disabled)<br>Standby Mode<br>VSUPPLY(LDO Enabled)<br>V1P8ANA(LDO Disabled)<br>V1P8DIG(LDO Disabled)<br>Turn On Time5|VSUPPLY= 0 V<br>2_g_range<br>Power-off to standby|2.25<br>2.5<br>3.6<br>V1P8DIG<br>2.5<br>3.6<br>1.62<br>1.8<br>1.98<br>200<br>160<br>35.5<br>21<br>7<br>10<br><10<br><10|V<br>V<br>V<br>μA<br>μA<br>μA<br>μA<br>μA<br>μA<br>ms<br>ms|
|TEMPERATURE SENSOR<br>Output at 25°C<br>Scale Factor||1852<br>−9.05|LSB<br>LSB/°C|
|TEMPERATURE<br>OperatingTemperature Range||−40<br>+125|°C|



1 The temperature change is −40°C to +25°C or +25°C to +125°C. 

2 Repeatability is predicted for a 10 year life and includes shifts due to the HTOL (TA = 150°C, VSUPPLY = 3.6 V, and 1000 hours), temperature cycling (−55°C to +125°C and 1000 cycles), velocity random walk, broadband noise, and temperature hysteresis. 

> 3 The VRE measurement is the shift in dc offset while the device is subject to 2.5 _g_ rms random vibration from 50 Hz to 2 kHz. The DUT is configured for the ±2 _g_ range and an output data rate of 4 kHz. The VRE scales with the range setting. 

4 When V1P8ANA and V1P8DIG are generated internally, VSUPPLY is valid. To disable the LDO and drive V1P8ANA and V1P8DIG externally, connect VSUPPLY to VSS. 

> 5 Standby to measurement mode; valid when the output is within 1 m _g_ of final value. 

## **SPI DIGITAL INTERFACE CHARACTERISTICS FOR THE ADXL355** 

Note that multifunction pin names may be referenced by their relevant function only. 

**Table 3.** 

|**Table 3.**||||||
|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Test Conditions/Comments**|**Min**|**Typ**<br>**Max**|**Unit**|
|DC INPUT LEVELS<br>Input Voltage<br>Low Level<br>High Level<br>Input Current<br>Low Level<br>High Level|VIL<br>VIH<br>IIL<br>IIH|VIN= 0 V<br>VIN= VDDIO|0.7 × VDDIO<br>−0.1|0.3 × VDDIO<br>0.1|V<br>V<br>μA<br>μA|
|DC OUTPUT LEVELS<br>Output Voltage<br>Low Level<br>High Level<br>Output Current<br>Low Level<br>High Level|VOL<br>VOH<br>IOL<br>IOH|IOL= IOL, MIN<br>IOH= IOH, MAX<br>VOL= VOL, MAX<br>VOH= VOH, MIN|0.8 × VDDIO<br>−10|0.2 × VDDIO<br>4|V<br>V<br>mA<br>mA|



Rev. A | Page 5 of 42 

**ADXL354/ADXL355 Data Sheet** 

|**Parameter**|**Symbol**|**Test Conditions/Comments**|**Min**|**Typ**<br>**Max**|**Unit**|
|---|---|---|---|---|---|
|AC INPUT LEVELS<br>SCLK Frequency<br>SCLK High Time<br>SCLK Low Time<br>CS<br>Setup Time<br>CS<br>Hold Time<br>CS<br>Disable Time<br>Rising SCLK Setup Time<br>MOSI Setup Time<br>MOSI Hold Time|tHIGH<br>tLOW<br>tCSS<br>tCSH<br>tCSD<br>tSCLKS<br>tSU<br>tHD||0.1<br>40<br>40<br>20<br>20<br>40<br>20<br>20<br>20|10|MHz<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns|
|AC OUTPUT LEVELS<br>Propagation Delay<br>Enable MISO Time<br>Disable MISO Time|tP<br>tEN<br>tDIS|CLOAD= 30 pF|30|30<br>20|ns<br>ns<br>ns|



**==> picture [403 x 122] intentionally omitted <==**

**----- Start of picture text -----**<br>
tCSD<br>CS tCSS tHIGH tLOW tCSH tSCLKS<br>SCLK<br>tSU tHD<br>MOSI<br>tEN tP tDIS<br>MISO<br>14205-003<br>**----- End of picture text -----**<br>


_Figure 3. SPI Interface Timing Diagram_ 

## **I[2] C DIGITAL INTERFACE CHARACTERISTICS FOR THE ADXL355** 

Note that multifunction pin names may be referenced by their relevant function only. 

**Table 4.** 

|**Parameter**|**Symbol**|**Test Conditions/**<br>**Comments**|**I2C_HS = 0 (Fast Mode)**<br>**Min**<br>**Typ**<br>**Max**|**I2C_HS = 1 (High Speed Mode)**<br>**Min**<br>**Typ**<br>**Max**|**Unit**|
|---|---|---|---|---|---|
|DC INPUT LEVELS<br>Input Voltage<br>Low Level<br>High Level<br>Hysteresis of Schmitt<br>Trigger Inputs<br>Input Current|VIL<br>VIH<br>VHYS<br>IIL|0.1 × VDDIO< VIN<<br>0.9 × VDDIO|0.3 × VDDIO<br>0.7 × VDDIO<br>0.05 × VDDIO<br>−10<br>+10|0.3 × VDDIO<br>0.7 × VDDIO<br>0.1 × VDDIO|V<br>V<br>μA<br>μA|
|DC OUTPUT LEVELS<br>Output Voltage<br>Low Level<br>Output Current<br>Low Level|VOL1<br>VOL2<br>IOL|IOL= 3 mA<br>VDD> 2 V<br>VDD≤ 2 V<br>VOL= 0.4 V<br>VOL= 0.6 V|0.4<br>0.2 × VDDIO<br>20<br>6||V<br>V<br>mA<br>mA|



Rev. A | Page 6 of 42 

## **Data Sheet** 

## **ADXL354/ADXL355** 

|**Parameter**|**Symbol**|**Test Conditions/**<br>**Comments**|**I2C_HS = 0 (Fast Mode)**<br>**Min**<br>**Typ**<br>**Max**|**I2C_HS = 1 (High Speed Mode)**<br>**Min**<br>**Typ**<br>**Max**|**Unit**|
|---|---|---|---|---|---|
|AC INPUT LEVELS<br>SCLK Frequency<br>SCL High Time<br>SCL Low Time<br>Start Setup Time<br>Start Hold Time<br>SDA Setup Time<br>SDA Hold Time<br>Stop Setup Time<br>Bus Free Time<br>SCL Input Rise Time<br>SCL Input Fall Time<br>SDA Input Rise Time<br>SDA Input Fall Time<br>Width of Spikes to<br>Suppress|tHIGH<br>tLOW<br>tSUSTA<br>tHDSTA<br>tSUDAT<br>tHDDAT<br>tSUSTO<br>tBUF<br>tRCL<br>tFCL<br>tRDA<br>tFDA<br>tSP|Not shown in Figure 4|0<br>1<br>260<br>500<br>260<br>260<br>50<br>0<br>260<br>500<br>120<br>120<br>120<br>120<br>50|0<br>3.4<br>60<br>160<br>160<br>160<br>10<br>0<br>160<br>80<br>80<br>160<br>160<br>10|MHz<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns|
|AC OUTPUT LEVELS<br>Propagation Delay<br>Data<br>Acknowledge<br>Output Fall Time|tVDDAT<br>tVDACK<br>tF|CLOAD= 500 pF<br>Not shown in Figure 4|97<br>450<br>450<br>20 × (VDD/5.5)<br>120|27<br>135|ns<br>ns<br>ns|



**==> picture [468 x 71] intentionally omitted <==**

**----- Start of picture text -----**<br>
tFDA tRDA tBUF<br>SDA<br>tSUSTA tHDSTA tVDDAT tVDACK tSUSTO tSUSTA<br>tSUDAT tHDDAT tLOW tHIGH tFCL<br>tVDDAT tRCL<br>SCL<br>14205-004<br>**----- End of picture text -----**<br>


_Figure 4. I[2] C Interface Timing Diagram_ 

Rev. A | Page 7 of 42 

**ADXL354/ADXL355** 

**Data Sheet** 

## **ABSOLUTE MAXIMUM RATINGS** 

## **Table 5.** 

**Rating** 

|||
|---|---|
|**Parameter**|**Rating**|
|Acceleration (Any Axis, 0.1 ms)<br>Unpowered<br>Vibration|5,000_g_<br>Per MIL-STD-883|



Unpowered 5,000 _g_ Vibration Per MIL-STD-883 Method 2007, Test Condition A VSUPPLY, VDDIO 5.4 V V1P8ANA, V1P8DIG Configured as Inputs 1.98 V ADXL354 Digital Inputs (RANGE, ST1, ST2, STBY) −0.3 V to VDDIO + 0.3 V Analog Outputs (XOUT, YOUT, ZOUT, TEMP) −0.3 V to V1P8ANA + 0.3 V ADXL355 Digital Pins ([CS] , SCLK, MOSI, MISO, −0.3 V to VDDIO + 0.3 V INT1, INT2, DRDY) Operating Temperature Range −40°C to +125°C Storage Temperature Range −55°C to +150°C 

Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond 

the maximum operating conditions for extended periods may affect product reliability. 

## **THERMAL RESISTANCE** 

Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. 

## **Table 6. Thermal Resistance** 

|**Table 6. Thermal Resistance**|||
|---|---|---|
|**Package Type **|**θJA**|**Unit**|
|E-14-11|42|°C/W|



1 Thermal impedance simulated values are based on a JEDEC 2S2P thermal test board with four thermal vias. See JEDEC JESD51. 

## **ESD CAUTION** 

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Rev. A | Page 8 of 42 

**Data Sheet** 

**ADXL354/ADXL355** 

## **PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS** 

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RANGE 1 11 VSUPPLY Y<br>ST1 2 ADXL354 10 V1P8ANA<br>TOP VIEW<br>ST2 3 (Not to Scale) 9 VSS X<br>TEMP 4 8 V1P8DIG Z<br>Figure 5. ADXL354 Pin Configuration<br>OUT OUT OUT<br>Z Y X<br>14 13 12<br>5 6 7<br>DDIO SSIO<br>V V STBY 14205-007<br>**----- End of picture text -----**<br>


**Table 7. ADXL354 Pin Function Descriptions** 

|**Pin No.**|**Mnemonic**|**Description**|
|---|---|---|
|1<br>2<br>3<br>4<br>5<br>6<br>7<br>8<br>9<br>10<br>11<br>12<br>13<br>14|RANGE<br>ST1<br>ST2<br>TEMP<br>VDDIO<br>VSSIO<br>STBY<br>V1P8DIG<br>VSS<br>V1P8ANA<br>VSUPPLY<br>XOUT<br>YOUT<br>ZOUT|Range Selection Pin. Set this pin to ground to select the ±2_g_range, or set this pin to VDDIOto select the ±4_g_<br>or ±8_g_range. This pin is model dependent (see the Ordering Guide section).<br>Self Test Pin 1. This pin enables self test mode.<br>Self Test Pin 2. This pin activates the electromechanical self test actuation.<br>Temperature Sensor Output.<br>Digital Interface Supply Voltage.<br>Digital Ground.<br>Standby or Measurement Mode Selection Pin. Set this pin to ground to enter standby mode, or set this pin<br>to VDDIOto enter measurement mode.<br>Digital Supply. This pin requires a decoupling capacitor. If VSUPPLYconnects to VSS, supply the voltage to this<br>pin externally.<br>Analog Ground.<br>Analog Supply. This pin requires a decoupling capacitor. If VSUPPLYconnects to VSS, supply the voltage to this<br>pin externally.<br>Supply Voltage. When VSUPPLYequals 2.25 V to 3.6 V, VSUPPLYenables the internal LDOs to generate V1P8DIGand<br>V1P8ANA. For VSUPPLY= VSS, V1P8DIGand V1P8ANAare externally supplied.<br>X-Axis Output.<br>Y-Axis Output.<br>Z-Axis Output.|



Rev. A | Page 9 of 42 

**ADXL354/ADXL355** 

**Data Sheet** 

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CS/SCL 1 11 VSUPPLY Y<br>SCLK/VSSIO 2 ADXL355 10 V1P8ANA<br>TOP VIEW<br>MOSI/SDA 3 (Not to Scale) 9 VSS X<br>MISO/ASEL 4 8 V1P8DIG<br>Z<br>DRDY INT2 INT1<br>14 13 12<br>5 6 7<br>DDIO SSIO<br>V V<br>RESERVED 14205-006<br>**----- End of picture text -----**<br>


_Figure 6. ADXL355 Pin Configuration_ 

**Table 8. ADXL355 Pin Function Descriptions** 

|**Pin No.**|**Mnemonic**|**Description**|
|---|---|---|
|1<br>2<br>3<br>4<br>5<br>6<br>7<br>8<br>9<br>10<br>11<br>12<br>13<br>14|CS<br>/SCL<br>SCLK/VSSIO<br>MOSI/SDA<br>MISO/ASEL<br>VDDIO<br>VSSIO<br>RESERVED<br>V1P8DIG<br>VSS<br>V1P8ANA<br>VSUPPLY<br>INT1<br>INT2<br>DRDY|Chip Select for SPI (CS<br>).<br>Serial Communications Clock for I2C (SCL).<br>Serial Communications Clock for SPI (SCLK).<br>Connect to VSSIOfor I2C (VSSIO).<br>Master Output, Slave Input for SPI (MOSI).<br>Serial Data for I2C (SDA).<br>Master Input, Slave Output for SPI (MISO).<br>Alternate I2C Address Select for I2C (ASEL).<br>Digital Interface Supply Voltage.<br>Digital Ground.<br>Reserved. This pin can be connected to ground or left open.<br>Digital Supply. This pin requires a decoupling capacitor. If VSUPPLYconnects to VSS, supply the voltage to this<br>pin externally.<br>Analog Ground.<br>Analog Supply. This pin requires a decoupling capacitor. If VSUPPLYconnects to VSS, supply the voltage to this<br>pin externally.<br>Supply Voltage. When VSUPPLYequals 2.25 V to 3.6 V, VSUPPLYenables the internal LDOs to generate V1P8DIGand<br>V1P8ANA. For VSUPPLY= VSS, V1P8DIGand V1P8ANAare externally supplied.<br>Interrupt Pin 1.<br>Interrupt Pin 2.<br>Data ReadyPin.|



Rev. A | Page 10 of 42 

**Data Sheet** 

**ADXL354/ADXL355** 

## **TYPICAL PERFORMANCE CHARACTERISTICS** 

All figures include data for multiple devices and multiple lots, and they were taken in the ±2 _g_ range, unless otherwise noted. 

**==> picture [215 x 164] intentionally omitted <==**

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10<br>1<br>0.1<br>0.01<br>10 100 1000<br>FREQUENCY (Hz)<br>) g<br> (<br>OUT<br>X<br>14205-207<br>**----- End of picture text -----**<br>


_Figure 7. ADXL354 Frequency Response for X-Axis_ 

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1<br>0.1<br>0.01<br>10 100 1000<br>FREQUENCY (Hz) 14205-210<br>**----- End of picture text -----**<br>


_Figure 10. ADXL355 Normalized Frequency Response for X-Axis at 4 kHz ODR_ 

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**----- Start of picture text -----**<br>
10<br>1<br>0.1<br>0.01<br>10 100 1000<br>FREQUENCY (Hz)<br>) g<br> (<br>OUT<br>Y<br>14205-208<br>**----- End of picture text -----**<br>


_Figure 8. ADXL354 Frequency Response for Y-Axis_ 

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1<br>0.1<br>0.01<br>10 100 1000<br>FREQUENCY (Hz)<br>) g<br>Y-AXIS (<br>14205-211<br>**----- End of picture text -----**<br>


_Figure 11. ADXL355 Normalized Frequency Response for Y-Axis at 4 kHz ODR_ 

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**----- Start of picture text -----**<br>
10<br>1<br>0.1<br>10 100 1000<br>FREQUENCY (Hz)<br>) g<br> (<br>OUT<br>Z<br>14205-209<br>**----- End of picture text -----**<br>


_Figure 9. ADXL354 Frequency Response for Z-Axis_ 

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**----- Start of picture text -----**<br>
1<br>0.1<br>0.01<br>10 100 1000<br>FREQUENCY (Hz)<br>) g<br>Z-AXIS (<br>14205-212<br>**----- End of picture text -----**<br>


_Figure 12. ADXL355 Normalized Frequency Response for Z-Axis at 4 kHz ODR_ 

Rev. A | Page 11 of 42 

**ADXL354/ADXL355** 

**Data Sheet** 

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**----- Start of picture text -----**<br>
15.00<br>MAXIMUM CHANGE = 1.69m g<br>AVERAGE CHANGE = 1.18m g<br>10.00<br>5.00<br>0<br>–5.00<br>–9.75<br>–45 5 55 105<br>TEMPERATURE (°C)<br>ADXL354 X-Axis Zero  X-Axis Zero  g  Offset Relative to 25°C vs. Temperature<br>15.00<br>MAXIMUM CHANGE = 3.12m g<br>AVERAGE CHANGE = 1.85m g<br>10.00<br>5.00<br>0<br>–5.00<br>–9.75<br>–45 5 55 105<br>TEMPERATURE (°C)<br>ADXL354 Y-Axis Zero  Y-Axis Zero  g  Offset Relative to 25°C vs. Temperature<br>15.00<br>MAXIMUM CHANGE = 3.12m g<br>AVERAGE CHANGE = 1.85m g<br>10.00<br>5.00<br>0<br>–5.00<br>–9.75<br>–45 5 55 105<br>TEMPERATURE (°C)<br>) g<br>RELATIVE OFFSET (m<br>14205-213<br>) g<br>RELATIVE OFFSET (m<br>14205-214<br>) g<br>RELATIVE OFFSET (m<br>14205-215<br>**----- End of picture text -----**<br>


_Figure 13. ADXL354 X-Axis Zero  X-Axis Zero_ g _Offset Relative to 25°C vs. Temperature_ 

_Figure 14. ADXL354 Y-Axis Zero  Y-Axis Zero_ g _Offset Relative to 25°C vs. Temperature_ 

_Figure 15. ADXL354 Z-Axis Zero_ g _Offset Relative to 25°C vs. Temperature_ 

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1.00<br>MAXIMUM CHANGE = 0.60%<br>AVERAGE CHANGE = 0.34%<br>0.50<br>0<br>–0.50<br>–0.65<br>–45 5 55 105<br>TEMPERATURE (°C)<br>Figure 16. ADXL354 X-Axis Sensitivity Relative to 25°C vs. Temperature ADXL354 X-Axis Sensitivity Relative to 25°C vs. Temperature  X-Axis Sensitivity Relative to 25°C vs. Temperature<br>1.00<br>MAXIMUM CHANGE = 0.54%<br>AVERAGE CHANGE = 0.28%<br>0.50<br>0<br>–0.50<br>–0.65<br>–45 5 55 105<br>TEMPERATURE (°C)<br>Figure 17. ADXL354 Y-Axis Sensitivity Relative to 25°C vs. Temperature ADXL354 Y-Axis Sensitivity Relative to 25°C vs. Temperature  Y-Axis Sensitivity Relative to 25°C vs. Temperature<br>1.00<br>MAXIMUM CHANGE = 0.99%<br>AVERAGE CHANGE = 0.51%<br>0.50<br>0<br>–0.50<br>–0.65<br>–40 10 60 110<br>TEMPERATURE (°C)<br>RELATIVE SENSITIVITY (%)<br>14205-216<br>RELATIVE SENSITIVITY (%)<br>14205-217<br>RELATIVE SENSITIVITY (%)<br>14205-218<br>**----- End of picture text -----**<br>


_Figure 16. ADXL354 X-Axis Sensitivity Relative to 25°C vs. Temperature ADXL354 X-Axis Sensitivity Relative to 25°C vs. Temperature  X-Axis Sensitivity Relative to 25°C vs. Temperature_ 

_Figure 17. ADXL354 Y-Axis Sensitivity Relative to 25°C vs. Temperature ADXL354 Y-Axis Sensitivity Relative to 25°C vs. Temperature  Y-Axis Sensitivity Relative to 25°C vs. Temperature_ 

_Figure 18. ADXL354 Z-Axis Sensitivity Relative to 25°C vs. Temperature_ 

Rev. A | Page 12 of 42 

**ADXL354/ADXL355** 

## **Data Sheet** 

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**----- Start of picture text -----**<br>
70<br>60<br>50<br>40<br>30<br>20<br>10<br>0<br>ADXL354 2 g  OFFSET X-AXIS ( g )<br>Figure 19. ADXL354 Zero  g  Offset Histogram at 25°C, X-Axis<br>HITS PER BIN (Count)<br>0.075 0.070 0.065 0.060 0.055 0.050 0.045 –0.040 –0.035 –0.030 –0.025 –0.020 –0.015 –0.010 –0.005 0 0.005 0.010 0.015 0.020 0.025 0.030 0.035 0.040 0.045 0.050 0.055 0.060 0.065 0.070 0.075<br>14205-219<br>**----- End of picture text -----**<br>


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80<br>70<br>60<br>50<br>40<br>30<br>20<br>10<br>0<br>ADXL354 2 g  OFFSET Y-AXIS ( g )<br>Figure 20. ADXL354 Zero  g  Offset Histogram at 25°C, Y-Axis<br>HITS PER BIN (Count)<br>0.075 0.070 0.065 0.060 0.055 0.050 0.045 –0.040 –0.035 –0.030 –0.025 –0.020 –0.015 –0.010 –0.005 0 0.005 0.010 0.015 0.020 0.025 0.030 0.035 0.040 0.045 0.050 0.055 0.060 0.065 0.070 0.075<br>14205-220<br>**----- End of picture text -----**<br>


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45<br>40<br>35<br>30<br>25<br>20<br>15<br>10<br>5<br>0<br>ADXL354 2 g  OFFSET Z-AXIS ( g )<br>Figure 21. ADXL354 Zero  g  Offset Histogram at 25°C, Z-Axis<br>HITS PER BIN (Count)<br>14205-221<br>**----- End of picture text -----**<br>


**==> picture [210 x 189] intentionally omitted <==**

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80<br>70<br>60<br>50<br>40<br>30<br>20<br>10<br>0<br>ADXL354 2 g  SENSITIVITY X-AXIS (V/ g )<br>Figure 22. ADXL354 Sensitivity Histogram at 25°C, X-Axis<br>HITS PER BIN (Count)<br>0.368 0.370 0.372 0.374 0.376 0.378 0.380 0.382 0.384 0.386 0.388 0.390 0.392 0.394 0.396 0.398 0.400 0.402 0.404 0.406 0.408 0.410 0.412 0.414 0.416 0.418 0.420 0.422 0.424 0.426 0.428 0.430 0.432<br>14205-222<br>**----- End of picture text -----**<br>


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80<br>70<br>60<br>50<br>40<br>30<br>20<br>10<br>0<br>ADXL354 2 g  SENSITIVITY Y-AXIS (V/ g )<br>Figure 23. ADXL354 Sensitivity Histogram at 25°C, Y-Axis<br>70<br>60<br>50<br>40<br>30<br>20<br>10<br>0<br>ADXL354 2 g  SENSITIVITY Z-AXIS (V/ g )<br>HITS PER BIN (Count)<br>0.368 0.370 0.372 0.374 0.376 0.378 0.380 0.382 0.384 0.386 0.388 0.390 0.392 0.394 0.396 0.398 0.400 0.402 0.404 0.406 0.408 0.410 0.412 0.414 0.416 0.418 0.420 0.422 0.424 0.426 0.428 0.430 0.432<br>14205-223<br>HITS PER BIN (Count)<br>0.368 0.370 0.372 0.374 0.376 0.378 0.375 0.377 0.379 0.381 0.383 0.385 0.387 0.389 0.391 0.393 0.395 0.397 0.399 0.401 0.403 0.405 0.407 0.409 0.416 0.418 0.420 0.422 0.424 0.426 0.428 0.430 0.432<br>14205-224<br>**----- End of picture text -----**<br>


_Figure 24. ADXL354 Sensitivity Histogram at 25°C, Z-Axis_ 

Rev. A | Page 13 of 42 

**ADXL354/ADXL355** 

**Data Sheet** 

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**----- Start of picture text -----**<br>
0.7<br>0.6<br>0.5<br>0.4<br>0.3<br>0.2<br>0.1<br>0<br>0 1 2 3 4<br>INPUT VIBRATION ( g  rms)<br>Figure 25. ADXL354 Vibration Rectification Error (VRE),<br>X-Axis Offset from +1  g , ±2  g  Range, X-Axis Orientation = −1  g<br>0<br>–0.1<br>–0.2<br>–0.3<br>–0.4<br>–0.5<br>–0.6<br>–0.7<br>0 1 2 3 4<br>INPUT VIBRATION ( g  rms)<br>) g<br>OFFSET SHIFT (<br>14205-225<br>) g<br>OFFSET SHIFT (<br>14205-226<br>**----- End of picture text -----**<br>


_Figure 26. ADXL354 Vibration Rectification Error (VRE), Y-Axis Offset from +1_ g _, ±2_ g _Range, Y-Axis Orientation = +1_ g 

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0<br>–0.1<br>–0.2<br>–0.3<br>–0.4<br>–0.5<br>–0.6<br>–0.7<br>0 1 2 3 4<br>INPUT VIBRATION ( g  rms)<br>OFFSET SHIFT () g<br>14205-227<br>**----- End of picture text -----**<br>


_Figure 27. ADXL354 Vibration Rectification Error (VRE), Z-Axis Offset from +1_ g _, ±2_ g _Range, Z-Axis Orientation = +1_ g 

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**----- Start of picture text -----**<br>
0.68<br>0.58<br>0.48<br>0.38<br>0.28<br>0.18<br>0.08<br>–0.02<br>0 2 4 6 8 10<br>INPUT VIBRATION ( g  rms)<br>Figure 28. ADXL354 Vibration Rectification Error (VRE),<br>X-Axis Offset from +1  g , ±8  g  Range, X-Axis Orientation = −1  g<br>0<br>–0.1<br>–0.2<br>–0.3<br>–0.4<br>–0.5<br>–0.6<br>–0.7<br>0 2 4 6 8 10<br>INPUT VIBRATION ( g  rms)<br>Figure 29. ADXL354 Vibration Rectification Error (VRE),<br>Y-Axis Offset from +1  g , ±8  g  Range, Y-Axis Orientation = +1  g<br>0<br>–0.1<br>–0.2<br>–0.3<br>–0.4<br>–0.5<br>–0.6<br>–0.7<br>0 2 4 6 8 10<br>INPUT VIBRATION ( g  rms)<br>OFFSET SHIFT () g<br>14205-228<br>) g<br>OFFSET SHIFT (<br>14205-229<br>OFFSET SHIFT () g<br>14205-230<br>**----- End of picture text -----**<br>


_Figure 30. ADXL354 Vibration Rectification Error (VRE), Z-Axis Offset from +1_ g _, ±8_ g _Range, Z-Axis Orientation = +1_ g 

Rev. A | Page 14 of 42 

**ADXL354/ADXL355** 

## **Data Sheet** 

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**----- Start of picture text -----**<br>
15.00<br>MAXIMUM DELTA = 6.5m g<br>AVERAGE DELTA = 1.7m g<br>10.00<br>5.00<br>0<br>–5.00<br>–9.75<br>–45 5 55 105<br>TEMPERATURE (°C)<br>) g<br>RELATIVE OFFSET (m<br>14205-231<br>**----- End of picture text -----**<br>


_Figure 31. ADXL355 X-Axis Zero_ g _Offset Relative to 25°C vs. Temperature_ 

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**----- Start of picture text -----**<br>
15.00<br>MAXIMUM DELTA = 3.2m g<br>AVERAGE DELTA = 1.4m g<br>10.00<br>5.00<br>0<br>–5.00<br>–9.75<br>–45 5 55 105<br>TEMPERATURE (°C)<br>) g<br>RELATIVE OFFSET (m<br>14205-232<br>**----- End of picture text -----**<br>


_Figure 32. ADXL355 Y-Axis Zero_ g _Offset Relative to 25°C vs. Temperature_ 

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**----- Start of picture text -----**<br>
15.00<br>MAXIMUM DELTA = 10.6m g<br>AVERAGE DELTA = 5.3m g<br>10.00<br>5.00<br>0<br>–5.00<br>–9.75<br>–45 5 55 105<br>TEMPERATURE (°C)<br>) g<br>RELATIVE OFFSET (m<br>14205-233<br>**----- End of picture text -----**<br>


_Figure 33. ADXL355 Z-Axis Zero_ g _Offset Relative to 25°C vs. Temperature_ 

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**----- Start of picture text -----**<br>
1.00<br>MAXIMUM CHANGE = 0.78%<br>AVERAGE CHANGE = 0.72%<br>0.50<br>0<br>–0.50<br>–0.65<br>–45 5 55 105<br>TEMPERATURE (°C)<br>Figure 34. ADXL355 X-Axis Sensitivity Relative to 25°C vs. Temperature ADXL355 X-Axis Sensitivity Relative to 25°C vs. Temperature  X-Axis Sensitivity Relative to 25°C vs. Temperature<br>1.00<br>MAXIMUM CHANGE = 0.78%<br>AVERAGE CHANGE = 0.72%<br>0.50<br>0<br>–0.50<br>–0.65<br>–45 5 55 105<br>TEMPERATURE (°C)<br>RELATIVE SENSITIVITY (%)<br>14205-234<br>RELATIVE SENSTIVITY (%)<br>14205-235<br>**----- End of picture text -----**<br>


_Figure 34. ADXL355 X-Axis Sensitivity Relative to 25°C vs. Temperature ADXL355 X-Axis Sensitivity Relative to 25°C vs. Temperature  X-Axis Sensitivity Relative to 25°C vs. Temperature_ 

_Figure 35. ADXL355 Y-Axis Sensitivity Relative to 25°C vs. Temperature_ 

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1.00<br>MAXIMUM CHANGE = 0.47%<br>AVERAGE CHANGE = 0.3%<br>0.50<br>0<br>–0.50<br>–0.65<br>–45 5 55 105<br>TEMPERATURE (°C)<br>RELATIVE SENSTIVITY (%)<br>14205-236<br>**----- End of picture text -----**<br>


_Figure 36. ADXL355 Z-Axis Sensitivity Relative to 25°C vs. Temperature_ 

Rev. A | Page 15 of 42 

**ADXL354/ADXL355** 

**Data Sheet** 

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**----- Start of picture text -----**<br>
80<br>70<br>60<br>50<br>40<br>30<br>20<br>10<br>0<br>OFFSET (m g )<br>HITS PER BIN (Count)<br>–75 –69 –63 –57 –51 –45 –39 –33 –27 –21 –15 –9 –3 3 9 15 21 27 33 39 45 51 57 63 69 75 14205-237<br>**----- End of picture text -----**<br>


_Figure 37. ADXL355 Zero_ g _Offset Histogram at 25°C, X-Axis_ 

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80<br>70<br>60<br>50<br>40<br>30<br>20<br>10<br>0<br>OFFSET (m g )<br>Figure 38. ADXL355 Zero  g  Offset Histogram at 25°C, Y-Axis<br>45<br>40<br>35<br>30<br>25<br>20<br>15<br>10<br>5<br>0<br>OFFSET (m g )<br>HITS PER BIN (Count)<br>–75 –69 –63 –57 –51 –45 –39 –33 –27 –21 –15 –9 –3 3 9 15 21 27 33 39 45 51 57 63 69 75 14205-238<br>HITS PER BIN (Count)<br>–75 –69 –63 –57 –51 –45 –39 –33 –27 –21 –15 –9 –3 3 9 15 21 27 33 39 45 51 57 63 69 75 14205-239<br>**----- End of picture text -----**<br>


_Figure 39. ADXL355 Zero_ g _Offset Histogram at 25°C, Z-Axis_ 

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60<br>50<br>40<br>30<br>20<br>10<br>0<br>SENSITIVITY (lsb/g)<br>Figure 40. ADXL355 Sensitivity Histogram at 25°C, X-Axis<br>60<br>50<br>40<br>30<br>20<br>10<br>0<br>SENSITIVITY (LSB/ g )<br>Figure 41. ADXL355 Sensitivity Histogram at 25°C, Y-Axis<br>60<br>50<br>40<br>30<br>20<br>10<br>0<br>SENSITIVITY (LSB/ g )<br>HITS PER BIN (Count)<br>235520 237158 238797 240435 242074 243712 245350 246989 248627 250266 251904 253542 255181 256819 258458 260096 261734 263373 265011 266650 268288 269926 271565 273203 274842 276480<br>14205-240<br>HITS PER BIN (Count)<br>235520 237158 238797 240435 242074 243712 245350 246989 248627 250266 251904 253542 255181 256819 258458 260096 261734 263373 265011 266650 268288 269926 271565 273203 274842 276480<br>14205-241<br>HITS PER BIN (Count)<br>235520 237158 238797 240435 242074 243712 245350 246989 248627 250266 251904 253542 255181 256819 258458 260096 261734 263373 265011 266650 268288 269926 271565 273203 274842 276480<br>14205-242<br>**----- End of picture text -----**<br>


_Figure 42. ADXL355 Sensitivity Histogram at 25°C, Z-Axis_ 

Rev. A | Page 16 of 42 

**Data Sheet** 

**ADXL354/ADXL355** 

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**----- Start of picture text -----**<br>
0.7<br>0.6<br>0.5<br>0.4<br>0.3<br>0.2<br>0.1<br>0<br>0 1 2 3 4<br>INPUT VIBRATION ( g  rms)<br>Figure 43. ADXL355 Vibration Rectification Error (VRE),<br>X-Axis Offset from +1  g , ±2  g  Range, X-Axis Orientation = −1  g<br>0<br>–0.1<br>–0.2<br>–0.3<br>–0.4<br>–0.5<br>–0.6<br>–0.7<br>0 1 2 3 4<br>INPUT VIBRATION ( g  rms)<br>Figure 44. ADXL355 Vibration Rectification Error (VRE),<br>Y-Axis Offset from +1  g , ±2  g  Range, Y-Axis Orientation = +1  g<br>0<br>–0.1<br>–0.2<br>–0.3<br>–0.4<br>–0.5<br>–0.6<br>–0.7<br>0 1 2 3 4<br>INPUT VIBRATION ( g  rms)<br>) g<br>OFFSET CHANGE (<br>14205-243<br>) g<br>OFFSET CHANGE (<br>14205-244<br>) g<br>OFFSET CHANGE (<br>14205-245<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
Figure 45. ADXL355 Vibration Rectification Error (VRE),<br>Z-Axis Offset from +1  g , ±2  g  Range, Z-Axis Orientation = +1  g<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
0.68<br>0.58<br>0.48<br>0.38<br>0.28<br>0.18<br>0.08<br>–0.02<br>0 2 4 6 8 10<br>INPUT VIBRATION ( g  rms)<br>Figure 46. ADXL355 Vibration Rectification Error (VRE),<br>X-Axis Offset from +1  g , ±8  g  Range, X-Axis Orientation = −1  g<br>0<br>–0.1<br>–0.2<br>–0.3<br>–0.4<br>–0.5<br>–0.6<br>–0.7<br>0 2 4 6 8 10<br>INPUT VIBRATION ( g  rms)<br>Figure 47. ADXL355 Vibration Rectification Error (VRE),<br>Y-Axis Offset from +1  g , ±8  g  Range, Y-Axis Orientation = +1  g<br>0<br>–0.1<br>–0.2<br>–0.3<br>–0.4<br>–0.5<br>–0.6<br>–0.7<br>0 2 4 6 8 10<br>INPUT VIBRATION ( g  rms)<br>OFFSET SHIFT () g<br>14205-246<br>OFFSET SHIFT () g<br>14205-247<br>OFFSET SHIFT () g<br>14205-248<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
Figure 48. ADXL355 Vibration Rectification Error (VRE),<br>Z-Axis Offset from +1  g , ±8  g  Range, Z-Axis Orientation = +1  g<br>**----- End of picture text -----**<br>


Rev. A | Page 17 of 42 

**ADXL354/ADXL355** 

**Data Sheet** 

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**----- Start of picture text -----**<br>
1.35 0.006<br>TEMPERATURE SENSOR OUTPUT<br>LINEARITY<br>1.25 0.004<br>1.15 0.002<br>1.05 0<br>0.95 –0.002<br>0.85 –0.004<br>0.75 –0.006<br>–40 10 60 110<br>TEMPERATURE (°C)<br> LINEAR OFFSET (V)<br>ADXL354 TEMPERATURE SENSOR<br>ADXL354 TEMPERATURE SENSOR OUTPUT (V)<br>14205-249<br>**----- End of picture text -----**<br>


_Figure 49. ADXL354 Temperature Sensor Output and Linearity Offset vs. Temperature_ 

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**----- Start of picture text -----**<br>
80<br>70<br>60<br>50<br>40<br>30<br>20<br>10<br>0 125 129 133 137 141 145 149 153 157 161 165 169 173<br>TOTAL SUPPLY CURRENT (µA)<br>HITS PER BIN (Count)<br>14205-251<br>**----- End of picture text -----**<br>


_Figure 50. ADXL354 Total Supply Current, 3.3 V_ 

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**----- Start of picture text -----**<br>
2300 6<br>2100 4<br>1900<br>2<br>1700<br>0<br>1500<br>–2<br>1300<br>–4<br>1100<br>900 –6<br>TEMPERATURE SENSOR OUTPUT<br>LINEARITY<br>700 –8<br>–40 10 60 110<br>TEMPERATURE (°C)<br>Figure 52. ADXL355 Temperature Sensor Output and Linearity Offset vs.<br>Temperature<br>100<br>90<br>80<br>70<br>60<br>50<br>40<br>30<br>20<br>10<br>0<br>180 184 188 192 196 200 204 208 212 216 220 224 228<br>TOTAL SUPPLY CURRENT (µA)<br>Figure 53. ADXL355 Total Supply Current, 3.3 V<br> LINEAR OFFSET (LSB)<br>ADXL355 TEMPERATURE SENSOR<br>ADXL355 TEMPERATURE SENSOR OUTPUT (LSB)<br>14205-250<br>HITS PER BIN (Count)<br>14205-253<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
35<br>30<br>25<br>20<br>15<br>10<br>5<br>0<br>3800 3840 3880 3920 3960 4000 4040 4080 4120 4160 4200<br>ADXL355 CLOCK FREQUENCY (Hz)<br>Figure 51. ADXL355 Internal Clock Frequency Histogram<br>HITS PER BIN (Count)<br>14205-252<br>**----- End of picture text -----**<br>


Rev. A | Page 18 of 42 

**Data Sheet** 

**ADXL354/ADXL355** 

## **ROOT ALLAN VARIANCE (RAV) ADXL355 CHARACTERISTICS** 

All figures include data for multiple devices and multiple lots, and they were taken in the ±2 _g_ range, unless otherwise noted. 

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1000<br>100<br>10<br>1<br>0.01 0.1 1 10 100 1000<br>INTEGRATION TIME (Seconds)<br>) g<br>RAV (µ<br>14205-254<br>**----- End of picture text -----**<br>


_Figure 54. ADXL355 Root Allan Variance (RAV), X-Axis_ 

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**----- Start of picture text -----**<br>
1000<br>100<br>10<br>1<br>0.01 0.1 1 10 100 1000<br>INTEGRATION TIME (Seconds)<br>Figure 56. ADXL355 Root Allan Variance (RAV), Z-Axis<br>) g<br>RAV (µ<br>14205-256<br>**----- End of picture text -----**<br>


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1000<br>100<br>10<br>1<br>0.01 0.1 1 10 100 1000<br>INTEGRATION TIME (Seconds)<br>) g<br>RAV (µ<br>14205-255<br>**----- End of picture text -----**<br>


_Figure 55. ADXL355 Root Allan Variance (RAV), Y-Axis_ 

Rev. A | Page 19 of 42 

**ADXL354/ADXL355** 

**Data Sheet** 

## **THEORY OF OPERATION** 

The ADXL354 is a complete 3-axis, ultralow noise and ultrastable offset MEMS accelerometer with outputs ratiometric to the analog 1.8 V supply, V1P8ANA. The ADXL355 adds three high resolution ADCs that use the analog 1.8 V supply as a reference to provide digital outputs insensitive to the supply voltage. The ADXL354B is pin selectable for ±2 _g_ or ±4 _g_ full scale, the ADXL354C is pin selectable for ±2 _g_ or ±8 _g_ full scale, and the ADXL355 is programmable for ±2.048 _g_ , ±4.096 _g_ , and ±8.192 _g_ full scale. The ADXL355 offers both SPI and I[2] C communications ports. 

The micromachined, sensing elements are fully differential, comprising the lateral x-axis and y-axis sensors and the vertical, teeter totter z-axis sensors. The x-axis and y-axis sensors and the z-axis sensors go through separate signal paths that minimize offset drift and noise. The signal path is fully differential, except for a differential to single-ended conversion at the analog outputs of the ADXL354. 

The analog accelerometer outputs of the ADXL354 are ratiometric to V1P8ANA; therefore, carefully digitize them correctly. The temperature sensor output is not ratiometric. The XOUT, YOUT, and ZOUT analog outputs are filtered internally with an antialiasing filter. These analog outputs also have an internal 32 kΩ series resistor that can be used with an external capacitor to set the bandwidth of the output. 

The ADXL355 includes antialias filters before and after the high resolution Σ-Δ ADC. User-selectable output data rates and filter corners are provided. The temperature sensor is digitized with a 12-bit successive approximation register (SAR) ADC. 

## **ANALOG OUTPUT** 

Figure 57 shows the ADXL354 application circuit. The analog outputs (XOUT, YOUT, and ZOUT) are ratiometric to the 1.8 V analog voltage from the V1P8ANA pin. V1P8ANA can be powered with an on-chip LDO that is powered from VSUPPLY. V1P8ANA can also be supplied externally by forcing VSUPPLY to VSS, which disables the LDO. Due to the ratiometric response, the analog output requires referencing to the V1P8ANA supply when digitizing to achieve the inherent noise and offset performance of the ADXL354. The 0 _g_ bias output is nominally equal to V1P8ANA/2. The recommended option is to use the ADXL354 with a ratiometric ADC (for example, the Analog Devices, Inc., AD7682) with V1P8ANA providing the voltage reference. This configuration results in self cancellation of errors due to minor supply variations. 

The ADXL354 outputs two forms of filtering: internal antialiasing filtering with a cutoff frequency of approximately 1.5 kHz, and external filtering. The external filter uses a fixed, on-chip, 32 kΩ resistance in series with each output in conjunction with the external capacitors to implement the low-pass filter antialiasing and noise reduction prior to the external ADC. The antialias filter cutoff frequency must be significantly higher than the desired signal bandwidth. If the antialias filter corner is too low, ratiometricity can be degraded where the signal attenuation is different than the reference attenuation. 

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2.25V TO 3.6V<br>VDDIO (±4 g , ±8 g )<br>GND ( ± 2 g )<br>RANGE 1 11 VSUPPLY 0.1µF 1µF<br>ST1 2 10 V1P8ANA 0.1µF 1µF ADC VREF<br>ST2 3 ADXL354 9 VSS<br>TEMP 4 8 V1P8DIG<br>VDDIO (MEASUREMENT)<br>GND (STANDBY)<br>1µF 1µF<br>2.25V TO 3.6V<br>0.1µF 0.1µF<br>Figure 57. ADXL354 Application Circuit<br>OUT OUT OUT<br>Z Y X<br>14 13 12<br>5 6 7<br>VDDIO VSSIO STBY<br>14205-022<br>**----- End of picture text -----**<br>


Rev. A | Page 20 of 42 

**Data Sheet** 

**ADXL354/ADXL355** 

## **DIGITAL OUTPUT** 

Figure 59 shows the ADXL355 application circuit with the recommended bypass capacitors. The communications interface is either SPI or I[2] C (see the Serial Communications section for additional information). 

The ADXL355 includes an internal configurable digital bandpass filter. Both the high-pass and low-pass poles of the filter are adjustable, as detailed in the Filter Settings Register section and Table 43. At power-up, the default conditions for the filters are as follows: 

- High-pass filter (HPF) = dc (off) 

- Low-pass filter (LPF) = 1000 Hz 

- Output data rate = 4000 Hz 

## **AXES OF ACCELERATION SENSITIVITY** 

Figure 58 shows the axes of acceleration sensitivity. Note that the output voltage increases when accelerated along the sensitive axis. 

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Z<br>Y<br>X 14205-005<br>**----- End of picture text -----**<br>


_Figure 58. Axes of Acceleration Sensitivity_ 

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**----- Start of picture text -----**<br>
2.25V TO 3.6V<br>CS/SCL 1 11 VSUPPLY 0.1µF 1µF<br>SCLK/VSSIO 2 10 V1P8ANA<br>ADXL355 0.1µF 1µF<br>MOSI/SDA 3 TOP VIEW 9 VSS<br>(Not to Scale)<br>MISO/ASEL 4 8 V1P8DIG<br>1µF 1µF<br>2.25V TO 3.6V<br>0.1µF 0.1µF<br>Figure 59. ADXL355 Application Circuit<br>DRDY INT2 INT1<br>14 13 12<br>2CSPI/I<br>INTERFACE<br>5 6 7<br>DDIO SSIO<br>V V<br>RESERVED<br>14205-021<br>**----- End of picture text -----**<br>


Rev. A | Page 21 of 42 

**ADXL354/ADXL355** 

**Data Sheet** 

## **POWER SEQUENCING** 

There are two methods for applying power to the device. Typically, internal LDO regulators generate the 1.8 V power for the analog and digital supplies, V1P8ANA and V1P8DIG, respectively. Optionally, connecting VSUPPLY to VSS and driving V1P8ANA and V1P8DIG with an external supply can supply V1P8ANA and V1P8DIG. 

When using the internal LDO regulators, connect VSUPPLY to a voltage source between 2.25 V to 3.6 V. In this case, VDDIO and VSUPPLY can be powered in parallel. VSUPPLY must not exceed the VDDIO voltage by greater than 0.5 V. If necessary, VDDIO can be powered before VSUPPLY. 

When disabling the internal LDO regulators and using an external 1.8 V supply to power V1P8ANA and V1P8DIG, tie VSUPPLY to ground, and set V1P8ANA and V1P8DIG to the same final voltage level. In the case of bypassing the LDOs, the recommended power sequence is to apply power to VDDIO, followed by applying power to V1P8DIG approximately 10 μs later, and then applying power to V1P8ANA approximately 10 μs later. If necessary, V1P8DIG and VDDIO can be powered from the same 1.8 V supply, which can also be tied to V1P8ANA with proper isolation. In this case, proper decoupling and low frequency isolation is important to maintain the noise performance of the sensor. 

## **POWER SUPPLY DESCRIPTION** 

The ADXL354/ADXL355 have four different power supply domains: VSUPPLY, V1P8ANA, V1P8DIG, and VDDIO. The internal analog and digital circuitry operates at 1.8 V nominal. 

## _**VSUPPLY**_ 

VSUPPLY is 2.25 V to 3.6 V, which is the input range to the two LDO regulators that generate the nominal 1.8 V outputs for V1P8ANA and V1P8DIG. Connect VSUPPLY to VSS to disable the LDO regulators, which allows driving V1P8ANA and V1P8DIG from an external source. 

## _**V1P8ANA**_ 

All sensor and analog signal processing circuitry operates in this domain. Offset and sensitivity of the analog output ADXL354 are ratiometric to this supply voltage. When using external ADCs, use V1P8ANA as the reference voltage. The digital output ADXL355 includes ADCs that are ratiometric to V1P8ANA, thereby rendering offset and sensitivity insensitive to the value of V1P8ANA. V1P8ANA can be an input or an output as defined by the state of the VSUPPLY voltage. 

## _**V1P8DIG**_ 

V1P8DIG is the supply voltage for the internal logic circuitry. A separate LDO regulator decouples the digital supply noise from the analog signal path. V1P8ANA can be an input or an output as defined by the state of the VSUPPLY voltage. If driven externally, V1P8DIG must be the same voltage as the V1P8ANA voltage. 

## _**VDDIO**_ 

The VDDIO value determines the logic high levels. On the analog output ADXL354, VDDIO sets the logic high level for the self test pins, ST1 and ST2, as well as the STBY pin. On the digital output ADXL355, VDDIO sets the logic high level for communications interface ports, as well as the interrupt and DRDY outputs. 

The LDO regulators are operational when VSUPPLY is between 2.25 V and 3.6 V. V1P8ANA and V1P8DIG are the regulator outputs in this mode. Alternatively, when tying VSUPPLY to VSS, V1P8ANA and V1P8DIG are supply voltage inputs with a 1.62 V to 1.98 V range. 

## **OVERRANGE PROTECTION** 

The maximum nominal measurement range for the ADXL354/ ADXL355 is ±8 _g_ . Do not subject the device to (or use the device in) applications or assembly processes that reasonably expect to exceed this level of acceleration, particularly for long durations or on an ongoing basis. In such applications, the ADXL356/ ADXL357 offer higher _g_ ranges that may be better suited for such applications. 

If an overrange event does occur, all sensor drive clocks turn off for 0.5 ms to avoid electrostatic capture of the proof mass when the accelerometer is subject to input acceleration beyond the full-scale range. In the ±2 _g/_ ±2.048 _g_ range setting, the overrange protection activates for input signals beyond approximately ±8 _g/_ ±8.192 _g_ (±25%), and for the ±4 _g/_ ±4.096 _g_ and ±8 _g/_ ±8.192 _g_ range settings, the threshold corresponds to about ±16 _g_ (±25%). 

When overrange protection occurs, the XOUT, YOUT, and ZOUT pins on the ADXL354 begin to drive to midscale. The ADXL355 floats toward zero, and the first in, first out (FIFO) begins filling with this data. 

## **SELF TEST** 

The ADXL354 and ADXL355 incorporate a self test feature that effectively tests their mechanical and electronic systems simultaneously. In ADXL354, drive the ST1 pin to VDDIO to invoke self test mode. Then, by driving the ST2 pin to VDDIO, the ADXL354 applies an electrostatic force to the mechanical sensor and induces a change in output in response to the force. The self test delta (or response) is the difference in output voltages between when ST2 is high and ST2 is low, both when ST1 is asserted. After the self test measurement is complete, bring both pins low to resume normal operation. 

The self test operation is similar in the ADXL355, except ST1 and ST2 can be accessed through the SELF_TEST register (Register 0x2E). 

The self test feature rejects externally applied acceleration and only responds to the self test force, which allows an accurate measurement of the self test, even in the presence of external mechanical noise. 

Rev. A | Page 22 of 42 

**Data Sheet** 

**ADXL354/ADXL355** 

## **FILTER** 

The ADXL354/ADXL355 use an analog, low-pass, antialiasing filter to reduce out of band noise and to limit bandwidth. The ADXL355 provides further digital filtering options to maintain excellent noise performance at various ODRs. 

The analog, low-pass antialiasing filter in the ADXL354/ ADXL355 provides a fixed bandwidth of approximately 1.5 kHz, which is where the output response is attenuated by approximately 50%. The shape of the filter response in the frequency domain is that of a sinc3 filter. 

The ADXL354 x-axis, y-axis, and z-axis analog outputs include an amplifier followed by a series 32 kΩ resistor and output to the XOUT, the YOUT, and the ZOUT pins, respectively. 

The ADXL355 provides an internal 20-bit, Σ-Δ ADC to digitize the filtered analog signal. Additional digital filtering (beyond the analog, low-pass, antialiasing filter) consists of a low-pass digital decimation filter and a bypassable high-pass filter that supports output data rates between 4 kHz and 3.9 Hz. The decimation filter consists of two stages. The first stage is fixed decimation with a 4 kHz ODR with a low-pass filter cutoff (50% reduction in output response) at about 1 kHz. A variable second stage decimation filter is used for the 2 kHz output data rate and below (it is bypassed for 4 kHz ODR). Figure 60 shows the low-pass filter response with a 1 kHz corner (4 kHz ODR) for the ADXL355. Note that Figure 60 does not include the fixed frequency analog, low-pass, antialiasing filter with a fixed bandwidth of approximately 1.5 kHz. 

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0<br>–10<br>–20<br>–30<br>–40<br>–50<br>–60<br>–70<br>1 10 100 1k 10k<br>INPUT FREQUENCY (Hz)<br>DIGITAL LPF RESPONSE (dB)<br>14205-023<br>**----- End of picture text -----**<br>


_Figure 60. ADXL355 Digital Low-Pass Filter (LPF) Response for 4 kHz ODR_ 

The ADXL355 pass band of the signal path relates to the combined filter responses, including the analog filter previously discussed, and the digital decimation filter/ODR setting. Table 9 shows the delay associated with the decimation filter for each setting and provides the attenuation at the ODR/4 corner. 

**Table 9. Digital Filter Group Delay and Profile** 

|**Programmed ODR (Hz)**|**Delay**|**Delay**|**Attenuation**|**Attenuation**|
|---|---|---|---|---|
||**ODR (Cycles)**|**Time (ms)**|**Decimator at ODR/4 (dB)**|**Full Path at ODR/4 (dB)**|
|4000<br>4000/2 = 2000<br>4000/4 = 1000<br>4000/8 = 500<br>4000/16 = 250<br>4000/32 = 125<br>4000/64 = 62.5<br>4000/128 ~ 31<br>4000/256 ~ 16<br>4000/512 ~ 8<br>4000/1024 ~ 4|2.52<br>2.00<br>1.78<br>1.63<br>1.57<br>1.54<br>1.51<br>1.49<br>1.50<br>1.50<br>1.50|0.63<br>1.00<br>1.78<br>3.26<br>6.27<br>12.34<br>24.18<br>47.59<br>96.25<br>189.58<br>384.31|−3.44<br>−2.21<br>−1.92<br>−1.83<br>−1.83<br>−1.83<br>−1.83<br>−1.83<br>−1.83<br>−1.83<br>−1.83|−3.63<br>−2.26<br>−1.93<br>−1.83<br>−1.83<br>−1.83<br>−1.83<br>−1.83<br>−1.83<br>−1.83<br>−1.83|



Rev. A | Page 23 of 42 

**Data Sheet** 

## **ADXL354/ADXL355** 

The ADXL355 also includes an optional digital high-pass filter with a programmable corner frequency. By default, the highpass filter is disabled. The high pass corner frequency, where the output is attenuated by 50%, is related to the ODR, and the HPF_CORNER setting in the filter register (Register 0x28, Bits[6:4]). Table 10 shows the HPF_CORNER response. Figure 61 and Figure 62 show the simulated high-pass filter response and delay for a 10 Hz cutoff. 

The ADXL355 also includes an interpolation filter after the decimation filters to produce oversampled/upconverted data that provides an external synchronization option. See the Data Synchronization section for more details. Table 11 shows the delay and attenuation relative to the programmed ODR. 

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0<br>–3<br>–10<br>–20<br>–30<br>–40<br>–50<br>0 9.8801 100<br>FREQUENCY (kHz)<br>AMPLITUDE RELATIVE TO FULL SCALE (dB)<br>14205-024<br>**----- End of picture text -----**<br>


Group delay is the digital filter delay from the input to the ADC until data is available at the interface (see the Filter section). This delay is the largest component of the total delay from sensor to serial interface. 

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40<br>32.2122<br>30<br>20<br>10<br>1<br>0<br>0 9.8801<br>FREQUENCY (kHz)<br>DELAY (ODR CYCLES)<br>14205-025<br>**----- End of picture text -----**<br>


_Figure 62. High-Pass Filter Delay Response for a 4 kHz ODR and an HPF_CORNER Setting of 001 (Register 0x28, Bits[6:4])_ 

_Figure 61. High-Pass Filter Pass-Band Response for a 4 kHz ODR and an HPF_CORNER Setting of 001 (Register 0x28, Bits[6:4])_ 

**Table 10. Digital High-Pass Filter Response** 

|**HPF_CORNER Register Setting**<br>**(Register 0x28, Bits[6:4])**|**HPF_CORNER Frequency, −3 dB Point Relative to ODR Setting**|**−3 dB at 4 kHz ODR (Hz)**|
|---|---|---|
|000<br>001<br>010<br>011<br>100<br>101<br>110|Not applicable, no high-pass filter enabled<br>24.7 × 10−4× ODR<br>6.2084 × 10−4× ODR<br>1.5545 × 10−4× ODR<br>0.3862 × 10−4× ODR<br>0.0954 × 10−4× ODR<br>0.0238 × 10−4× ODR|Off<br>9.88<br>2.48<br>0.62<br>0.1545<br>0.03816<br>0.00952|



**Table 11. Combined Digital Interpolation Filter and Decimation Filter Response** 

|**Interpolator Data Rate Resolution**<br>**Relative to 64 × ODR (Hz)**|**Combined Interpolator/**<br>**Decimator Delay (ODR Cycles)**|**Combined Interpolator/**<br>**Decimator Delay (ms)**|**Combined Interpolator/Decimator**<br>**Output Attenuation at ODR/4 (dB)**|
|---|---|---|---|
|64 × 4000 = 256000<br>64 × 2000 = 128000<br>64 × 1000 = 64000<br>64 × 500 = 32000<br>64 × 250 = 16000<br>64 × 125 = 8000<br>64 × 62.5 = 4000<br>64 × 31.25 = 2000<br>64 × 15.625 = 1000<br>64 × 7.8125 = 500<br>64 × 3.90625 = 250|3.51661<br>3.0126<br>2.752<br>2.6346<br>2.5773<br>2.5473<br>2.53257<br>2.52452<br>2.52045<br>2.5194<br>2.51714|0.88<br>1.51<br>2.75<br>5.27<br>10.31<br>20.38<br>40.52<br>80.78<br>161.31<br>322.48<br>644.39|−6.18<br>−4.93<br>−4.66<br>−4.58<br>−4.55<br>−4.55<br>−4.55<br>−4.55<br>−4.55<br>−4.55<br>−4.55|



Rev. A | Page 24 of 42 

**Data Sheet** 

**ADXL354/ADXL355** 

## **SERIAL COMMUNICATIONS** 

The 4-wire serial interface communicates in either the SPI or I[2] C protocol. It affectively autodetects the format being used, requiring no configuration control to select the format. 

## **SPI PROTOCOL** 

Wire the ADXL355 for SPI communication as shown in the connection diagram in Figure 63. The SPI protocol timing is shown in Figure 64 to Figure 67. The timing scheme follows the clock polarity (CPOL) = 0 and clock phase (CPHA) = 0. The SPI clock speed ranges from 100 kHz to 10 MHz. 

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ADXL355 PROCESSOR<br>CS DOUT<br>MOSI DOUT<br>MISO DIN<br>SCLK DOUT<br>14205-026<br>**----- End of picture text -----**<br>


_Figure 63. 4-Wire SPI Connection_ 

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**----- Start of picture text -----**<br>
CS<br>1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16<br>SCLK<br>MOSI A6 A5 A4 A3 A2 A1 A0 RW<br>MISO D7 D6 D5 D4 D3 D2 D1 D0<br>Figure 64. SPI Timing Diagram—Single-Byte Read<br>CS<br>1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16<br>SCLK<br>MOSI A6 A5 A4 A3 A2 A1 A0 RW D7 D6 D5 D4 D3 D2 D1 D0<br>MISO<br>Figure 65. SPI Timing Diagram—Single-Byte Write<br>CS<br>1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17<br>SCLK<br>MOSI A6 A5 A4 A3 A2 A1 A0 RW<br>BYTE 1 BYTE n<br>MISO D7 D6 D5 D4 D3 D2 D1 D0 D7 D0 D7 D6 D5 D4 D3 D2 D1 D0<br>Figure 66. SPI Timing Diagram—Multibyte Read<br>CS<br>1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17<br>SCLK<br>BYTE 1 BYTE n<br>MOSI A6 A5 A4 A3 A2 A1 A0 RW D7 D6 D5 D4 D3 D2 D1 D0 D7 D0 D7 D6 D5 D4 D3 D2 D1 D0<br>MISO<br>14205-027<br>14205-028<br>14205-029<br>14205-030<br>**----- End of picture text -----**<br>


_Figure 67. SPI Timing Diagram—Multibyte Write_ 

Rev. A | Page 25 of 42 

**Data Sheet** 

## **ADXL354/ADXL355** 

## **I[2] C PROTOCOL** 

Figure 68 to Figure 70 detail the I[2] C protocol timing. The I[2] C interface can be used on most buses operating in I[2] C standard mode (100 kHz), fast mode (400 kHz), fast mode plus (1 MHz), and high speed mode (3.4 MHz). The ADXL355 I[2] C device ID is as follows: 

- ASEL (pin) = 0, device address = 0x1D 

- ASEL (pin) = 1, device address = 0x53 

## **READING ACCELERATION OR TEMPERATURE DATA FROM THE INTERFACE** 

Acceleration data is left justified and has a register address order of most significant data to least significant data, which allows the user to use multibyte transfers and to take only as much data as required—either 8 bits, 16 bits, or 20 bits plus the marker. Temperature data is 12 bits unsigned, right justified. The data in XDATA, YDATA, and ZDATA is always the most 

recent available. It is not guaranteed that XDATA, YDATA, and ZDATA form a set corresponding to one sample point in time. The routine used to retrieve the data from the device controls this data set continuity. If data transfers are initiated when the DATA_RDY bit goes high and completes in a time approximately equal to 1/ODR, XDATA, YDATA, and ZDATA apply to the same data set. 

For multibyte read or write transactions through either serial interface, the internal register address autoincrements. When the top of the register address range, 0x3FF, is reached the autoincrement stops and does not wrap back to Hex Address 0x00. 

The address autoincrement function disables when the FIFO address is used, so that data can be read continuously from the FIFO as a multibyte transaction. In cases where the starting address of a multibyte transaction is less than the FIFO address, the address autoincrements until reaching the FIFO address, and then stops at the FIFO address. 

**==> picture [496 x 209] intentionally omitted <==**

**----- Start of picture text -----**<br>
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37<br>SCL<br>REPEAT<br>START DEVICE ADDRESS REGISTER ADDRESS START DEVICE ADDRESS DATA BYTE STOP<br>SDA A6 A5 A4 A3 A2 A1 A0 RW AK 0 A6 A5 A4 A3 A2 A1 A0 AK A6 A5 A4 A3 A2 A1 A0 RW AK 0 D6 D5 D4 D3 D2 D1 D0 AK<br>SINGLE BYTE READ INDICATE SDA IS<br>CONTROLLED BY ADXL355<br>Figure 68. I [2] C Timing Diagram—Single-Byte Read<br>1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27<br>SCL<br>START DEVICE ADDRESS REGISTER ADDRESS DATA BYTE STOP<br>SDA A6 A5 A4 A3 A2 A1 A0 RW AK 0 A6 A5 A4 A3 A2 A1 A0 AK D7 D6 D5 D4 D3 D2 D1 D0 AK<br>Figure 69. I [2] C Timing Diagram—Single-Byte Write<br>1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 19<br>SCL<br>START DEVICE ADDRESS REGISTER ADDRESS DATA BYTE 1 DATA BYTE n<br>SDA A6 A5 A4 A3 A2 A1 A0 RW AK 0 A6 A5 A4 A3 A2 A1 A0 AK D7 D6 D5 D4 D3 D2 D1 D0 AK D7 D0 AK D7 D6 D5 D4 D3 D2 D1 D0 AK<br>14205-031<br>14205-032<br>14205-033<br>**----- End of picture text -----**<br>


_Figure 70. I[2] C Timing Diagram—Multibyte Write_ 

Rev. A | Page 26 of 42 

**Data Sheet** 

**ADXL354/ADXL355** 

## **FIFO** 

FIFO operates in a stream mode, that is, when the FIFO overruns new data overwrites the oldest data in the FIFO. A read from the FIFO address guarantees that the three bytes associated with the acceleration measurement on an axis all pertain to the same measurement. The FIFO never overruns, and data is always taken out in sets (multiples of three data points). 

There are 96 21-bit locations in the FIFO. Each location contains 20 bits of data and a marker bit for the x-axis data. A single-byte read from the FIFO address pops one location from the FIFO. A multibyte read to the FIFO location pops the FIFO on the read of the first byte and every third byte read thereafter. 

Figure 71 shows the organization of the data in the FIFO. The acceleration data is twos complement, 20-bit data. The FIFO control logic inserts the two LSB reads on the interface. Bit 1 indicates that an attempt was made to read an empty FIFO, and that the data is not valid acceleration data. Bit 0 is a marker bit to identify the x-axis, which allows a user to verify that the FIFO data was correctly read. An acceleration data point for a given axis occupies one FIFO location. The read pointer, RD_PTR, points to the oldest stored data that was not read already from the interface (see Figure 71). There are no physical x-acceleration, y-acceleration, or z-acceleration data registers. This data also comes directly from the most recent data set in the FIFO, which points to by the z pointer, Z_PTR, (see Figure 71). 

**==> picture [477 x 210] intentionally omitted <==**

**----- Start of picture text -----**<br>
Z_PTR + 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1<br>t Le Le Le<br>Z_PTR Z19 Z18 Z17 Z16 Z15 Z14 Z13 Z12 Z11 Z10 Z9 Z8 Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 0 0<br>t Le Le Le<br>Z_PTR – 1 Y19 Y18 Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 0 0<br>T L Le Le<br>Z_PTR – 2 | } X19 X18 X17 X16 X15 X14 X13. X12 X11 X10 X9 X8 X7 X6 X5 X4 X3_ X2 X1— = X0 0 1<br>Z19 Z18 Z17 Z16 Z15 Z14 Z13 212 Z11 Z10 Z9 Z8 27 26 Z5 Z4 Z3 22 21 20 an)<br>Y19 Y18 Y17 Y16 Y15 Y14 Y13 Y12 Yi1 Y10 Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 YO 0 0<br>RD_PTR | } X19 X18 X17 X16 X15 X14 X13. X12 X11. X10 X9 X8 X7 XG X5_ X4<br>VIRTUAL BITS<br>ACCELERATION DATA (NOT ALLOCATED IN THE FIFO)<br>EMPTY INDICATOR<br>X-AXIS MARKER<br>—eS<br>ASCENDING SPI ADDRESSES<br>ASCENDING<br>SPI ADDRESSES<br>ASCENDING FIFO ADDRESSES<br>DATA SET. SAMPLE POINT  IS THE SAME ACROSS A SINGLE X-AXIS, Y-AXIS,AND Z-AXIS DATA SET.<br>14205-035<br>**----- End of picture text -----**<br>


_Figure 71. FIFO Data Organization_ 

Rev. A | Page 27 of 42 

**ADXL354/ADXL355** 

**Data Sheet** 

## **INTERRUPTS** 

The status register (Register 0x04) contains five individual bits, four of which can be mapped to either the INT1 pin, the INT2 pin, or both. The polarity of the interrupt, active high or active low, is also selectable via the INT_POL bit in the range (Register 0x2C) register. In general, the status register clears when read, but this is not the case if the condition that caused the interrupt persists after the read of the register. The definition of persist varies slightly in each case, but it is described in the following sections. The DRDY pin is similar to an interrupt pins (INTx) but clears very differently. This case is also described. 

## **DATA_RDY** 

The DATA_RDY bit is set when new acceleration data is available to the interface. It clears on a read of the status register. It is not set again until acceleration data that is newer than the status register read is available. 

Special logic on the clear of the DATA_RDY bit covers the corner case where new data arrives during the read of the status register. In this case, the data ready condition may be missed completely. This logic results in a delay of the clearing of DATA_RDY of up to four 512 kHz cycles. 

## **DRDY PIN** 

DATA is not a status register bit; it instead behaves similar to an unmaskable interrupt. DRDY is set when new acceleration data is available to the interface. It clears on a read of the FIFO, on a read of XDATA, YDATA, or ZDATA, or by an autoclear function that occurs approximately halfway between output acceleration data sets. 

DRDY is always active high. The INT_POL bit does not affect DRDY. In EXT_SYNC modes, the first few DRDY pulses after initial synchronization can be lost or corrupted. The length of this potential corruption is less than the group delay. 

## **FIFO_FULL** 

The FIFO_FULL bit is set when the entries in the FIFO are equal to the setting of the FIFO_SAMPLES bits. It clears as follows: 

- If the entries in the FIFO fall below the FIFO_SAMPLES, which is only the case if sufficient data is read from the FIFO. 

- On a read of the status register, but only if the entries in the FIFO are less than the FIFO_SAMPLES bits. 

## **FIFO_OVR** 

The FIFO_OVR bit is set when the FIFO is so far overrange that data is lost. The specified size of the FIFO is 96 locations. There is an additional three location buffer to compensate for delays in the synchronization of the clock domains. It is only when there is an attempt to write past this 99 location limit that FIFO_OVR is set. 

A read of the status register clears FIFO_OVR. It is not set again until data is lost subsequent to this data register read. 

## **ACTIVITY** 

The activity bit (Register 0x04, Bit 3) is set when the measured acceleration on any axis is above the ACT_THRESH bits for ACT_COUNT consecutive measurements. An over threshold condition can shift from one axis to another on successive measurements and is still counted toward the consecutive ACT_COUNT count. 

A read of the status register clears the activity bit (Register 0x04, Bit 3), but it sets again at the end of the next measurement if the activity bit (Register 0x04, Bit 3) conditions are still satisfied. 

## **NVM_BUSY** 

The NVM_BUSY bit indicates that the nonvolatile memory (NVM) controller is busy, and it cannot be accessed to read, write, or generate an interrupt. 

A status register read that occurs after the NVM controller is no longer busy clears NVM_BUSY. 

Rev. A | Page 28 of 42 

**Data Sheet** 

**ADXL354/ADXL355** 

## **EXTERNAL SYNCHRONIZATION AND INTERPOLATION** 

There are three possible synchronization options for the ADXL355, shown in Figure 72 to Figure 74. For clarity, the clock frequencies and delays are drawn to scale. The labels in Figure 72 to Figure 74 are defined as follows: 

- Internal ODR is the alignment of the decimated output data based on the internal clock. 

- ADC clock shows the internal master clock rate 

- DRDY is an output indicator signaling a sample is ready. 

The three modes are include as follows: 

- No external synchronization (internal clocks used) 

- Synchronization with interpolation filter enabled 

- Sync with an external sync and clock signals, no interpolation filter 

## _**EXT_SYNC = 00—No External Sync or Interpolation**_ 

For this case, an internal clock that serves as the synchronization master generates the data. No external signals are required, and this is used commonly when the external processor retrieves data from the device asynchronously and absolute synchronization to an external source is not required. Use Register 0x28 to program the ODR. 

The device outputs a DRDY (active high) to signal that a new sample is available, and data is retrieved from the real-time registers or the FIFO. The group delay is based on the decimation setting as shown in Table 9. 

## _**EXT_SYNC = 10—External Sync with Interpolation**_ 

In this case, the internal clock generates data; however, an interpolation filter provides additional time resolution of 64 times the programmed ODR. Synchronization using interpolation filters and an external ODR clock is commonly used when the external processor can provide a synchronization signal (which is asynchronous to the internal clock) at the desired ODR. Synchronization with the interpolation filter enabled (EXT_SYNC = 10) allows the nonsynchronous external clock to output data most closely associated with the external clock rising edge. The interpolation filter provides a frequency resolution related to ODR (see Table 11). 

The advantage of this mode is that data is available at a user defined sample rate and is asynchronous to the internal oscillator. The disadvantage of this mode is that the group delay is increased, and there is increased attenuation at the band edge. Additionally, because there is a limit to the time resolution, there is some distortion related to the mismatch of the external sync relative to the internal oscillator. This mismatch degrades spectral performance. The group delay is based on the decimation setting and interpolation setting (see Table 11). Table 13 shows the delay between the SYNC signal (input) to DRDY (output). 

## _**EXT_SYNC = 01—External Sync and External Clock**_ 

In this case, an external source provides an external clock at a frequency of 4 × 64 × ODR. The external clock becomes the master clock source for the device. In addition, an external synchronization signal is needed to align the decimation filter output to a specific clock edge, which provides full external synchronization and is commonly used when a fixed external clock captures and processes data, and asynchronous clock(s) are not allowed. When using multiple sensors, synchronization with an external master clock is beneficial and requires time alignment. 

When configured for EXT_SYNC = 01 with an ODR of 4 kHz, the user must supply an external clock at 1.024 MHz (64 × 4 × 4 kHz) on the INT2 pin (Pin 13), and an external synchronization on DRDY pin (Pin 14), as shown in Table 12. 

Special restrictions when using this mode include the following: 

- An external clock (EXT_CLK) must be provided as well as an external sync. 

- The frequency of EXT_CLK must be exactly 4 × 64 × ODR. 

- The width of sync must be a minimum of four EXT_CLK periods. 

- The phase of sync must meet an approximate 25 ns setup time to the EXT_CLK rising edge. 

When using the EXT_SYNC mode and without providing sync, the device runs on its own synchronization. Similarly, after synchronization, the device continues to run synchronized to the last sync pulse it received, which means that EXT_SYNC = 01 mode can be used with only a single synchronization pulse. 

The interpolation filter provides a frequency resolution related to the ODR (see Table 11). In this case, the data provided corresponds to the external signal, which can be greater than the set ODR, but the output pass band remains the same it was prior to the interpolation filter. 

**Table 12. Multiplexing of INT2 and DRDY** 

||**Register or Bit Fields**|**Register or Bit Fields**|**Pins**|**Pins**||
|---|---|---|---|---|---|
|**EXT_CLK**|**EXT_SYNC[1:0]**|**INT_MAP[7:4]**|**INT2 (Pin 13)**|**DRDY (Pin 14)**|**Comments**|
|0<br>0<br>1<br>1|00<br>00<br>00<br>00|0000<br>Not 0000<br>0000<br>Not 00002|Low<br>INT2<br>EXT_CLK<br>EXT_CLK|DRDY<br>DRDY<br>DRDY<br>DRDY|Synchronization is to the internal clocks, and there is<br>no external clock synchronization.|
|0<br>0|01<br>011|0000<br>Not 0000|DRDY<br>INT2|SYNC<br>SYNC|These options reset the digital filters on every<br>synchronization pulse and are not recommended.|



Rev. A | Page 29 of 42 

**ADXL354/ADXL355** 

**Data Sheet** 

||**Register or Bit Fields**<br>**Pins**||
|---|---|---|
|**EXT_CLK**|**EXT_SYNC[1:0]**<br>**INT_MAP[7:4]**<br>**INT2 (Pin 13)**<br>**DRDY (**|**Pin 14)**<br>**Comments**|
|1<br>1|011<br>0000<br>EXT_CLK<br>SYNC<br>011<br>Not 00002<br>EXT_CLK<br>SYNC|External synchronization, no interpolation filter, and<br>DRDY (active high) signals that data is ready. Data<br>represents a samplepointgroupdelayearlier in time.|
|0<br>0<br>1<br>1|10<br>0000<br>DRDY<br>SYNC<br>101<br>Not 0000<br>INT2<br>SYNC<br>101<br>0000<br>EXT_CLK<br>SYNC<br>101<br>Not 0000<br>EXT_CLK<br>SYNC|External synchronization, interpolation filter, and<br>DRDY (active high) signals that data is ready. Data<br>sample group delay earlier in time.|



1 No DRDY. 

2 No INT2, even though it is enabled. 

|**INTERNAL ODR**<br>**SAMPLE POINT**<br>**ADC MOD. CLK.**<br>**64× ODR**<br>**DRDY**<br>_Figure 72. External Synchronization Option_<br>**INTERNAL ODR**<br>**INTERPOLATOR**<br>**64× ODR**<br>**DRDY**<br>**GROUP DELAY**<br>**(FIXED RELATIVE TO SYNC)**<br>**SAMPLE POINT**<br>**SYNC**<br>**110% ODR**<br>_Figure 73. External Synchronization Option—EXT_SYNC = 10_<br>**INTERNAL ODR**<br>**DRDY**<br>**GR**<br>**(FIXED R**<br>**SAMPLE POINT**<br>**LOST SAMPLE**<br>**SYNCHRONIZE**<br>**EXT_CLK**<br>**(4 × 64) × SYNC**<br>**SYNC**<br>_Figure 74. External Synchronization Option—EXT_SYN_<br>**Table 13. EXT_SYNC = 10, DRDY Delay**|**GROUP DELAY**<br>**(FIXED RELATIVE TO DRDY)**<br>14205-036<br>_—EXT_SYNC = 00, Internal Sync_<br>**INTERFACE SYNCHRONIZATION DELAY**<br>14205-037<br>_, External Sync, External Clock, Interpolation Filter_<br>**OUP DELAY**<br>**ELATIVE TO SYNC)**<br>14205-038<br>_C = 01, External Sync, No Interpolation Filter_|
|---|---|
|**ODR_LPF**<br>**Del**|**ay (OSC Cycles)**|
|0x0<br>8<br>0x1<br>10<br>0x2<br>14<br>0x3<br>22<br>0x4<br>38<br>0x5<br>70<br>0x6<br>134<br>0x7<br>262<br>0x8<br>103<br>0x9<br>205<br>0x10<br>410|<br> <br>1<br>4<br>2|



Rev. A | Page 30 of 42 

**Data Sheet** 

**ADXL354/ADXL355** 

## **ADXL355 REGISTER MAP** 

Note that while configuring the ADXL355 in an application, all configuration registers must be programmed before enabling measurement mode in the POWER_CTL register. When the ADXL355 is in measurement mode, only the following configurations can change: the HPF_CORNER bits in the filter register, the INT_MAP register, the ST1 and ST2 bits in the SELF_TEST register, and the reset register. 

**Table 14. ADXL355 Register Map** 

|**Hex. Addr.**|**Register Name**|**Bit 7**|**Bit 6**|**Bit 5**|**Bit 4**|**Bit 3**|**Bit 2**|**Bit 1**|**Bit 0**|**Reset **|**R/W**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|0x00|DEVID_AD|DEVID_AD||||||||0xAD|R|
|0x01|DEVID_MST|DEVID_MST||||||||0x1D|R|
|0x02|PARTID|PARTID||||||||0xED|R|
|0x03|REVID|REVID||||||||0x01|R|
|0x04|Status|Reserved|||NVM_BUSY|Activity|FIFO_OVR|FIFO_FULL|DATA_RDY|0x00|R|
|0x05|FIFO_ENTRIES|Reserved|FIFO_ENTRIES|||||||0x00|R|
|0x06|TEMP2|Reserved||||Temperature, Bits[11:8]||||0x00|R|
|0x07|TEMP1|Temperature, Bits[7:0]||||||||0x00|R|
|0x08|XDATA3|XDATA, Bits[19:12]||||||||0x00|R|
|0x09|XDATA2|XDATA, Bits[11:4]||||||||0x00|R|
|0x0A|XDATA1|XDATA, Bits[3:0]||||Reserved||||0x00|R|
|0x0B|YDATA3|YDATA, Bits[19:12]||||||||0x00|R|
|0x0C|YDATA2|YDATA, Bits[11:4]||||||||0x00|R|
|0x0D|YDATA1|YDATA, Bits[3:0]||||Reserved||||0x00|R|
|0x0E|ZDATA3|ZDATA, Bits[19:12]||||||||0x00|R|
|0x0F|ZDATA2|ZDATA, Bits[11:4]||||||||0x00|R|
|0x10|ZDATA1|ZDATA, Bits[3:0]||||Reserved||||0x00|R|
|0x11|FIFO_DATA|FIFO_DATA||||||||0x00|R|
|0x1E|OFFSET_X_H|OFFSET_X, Bits[15:8]||||||||0x00|R/W|
|0x1F|OFFSET_X_L|OFFSET_X, Bits[7:0]||||||||0x00|R/W|
|0x20|OFFSET_Y_H|OFFSET_Y, Bits[15:8]||||||||0x00|R/W|
|0x21|OFFSET_Y_L|OFFSET_Y, Bits[7:0]||||||||0x00|R/W|
|0x22|OFFSET_Z_H|OFFSET_Z, Bits[15:8]||||||||0x00|R/W|
|0x23|OFFSET_Z_L|OFFSET_Z, Bits[7:0]||||||||0x00|R/W|
|0x24|ACT_EN|Reserved|||||ACT_Z|ACT_Y|ACT_X|0x00|R/W|
|0x25|ACT_THRESH_H|ACT_THRESH, Bits[15:8]||||||||0x00|R/W|
|0x26|ACT_THRESH_L|ACT_THRESH, Bits[7:0]||||||||0x00|R/W|
|0x27|ACT_COUNT|ACT_COUNT||||||||0x01|R/W|
|0x28|Filter|Reserved|HPF_CORNER|||ODR_LPF||||0x00|R/W|
|0x29|FIFO_SAMPLES|Reserved|FIFO_SAMPLES|||||||0x60|R/W|
|0x2A|INT_MAP|ACT_EN2|OVR_EN2|FULL_EN2|RDY_EN2|ACT_EN1|OVR_EN1|FULL_EN1|RDY_EN1|0x00|R/W|
|0x2B|Sync|Reserved|||||EXT_CLK|EXT_SYNC||0x00|R/W|
|0x2C|Range|I2C_HS|INT_POL|Reserved||||Range||0x81|R/W|
|0x2D|POWER_CTL|Reserved|||||DRDY_OFF|TEMP_OFF|STANDBY|0x01|R/W|
|0x2E|SELF_TEST|Reserved||||||ST2|ST1|0x00|R/W|
|0x2F|Reset|Reset||||||||0x00|W|



Rev. A | Page 31 of 42 

**Data Sheet** 

## **ADXL354/ADXL355** 

## **REGISTER DEFINITIONS** 

This section describes the functions of the ADXL355 registers. The ADXL355 powers up with the default register values, as shown in the Reset column of Table 14. 

## **ANALOG DEVICES ID REGISTER** 

This register contains the Analog Devices ID, 0xAD. 

## _**Address: 0x00, Reset: 0xAD, Name: DEVID_AD**_ 

## **Table 15. Bit Descriptions for DEVID_AD** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:0]|DEVID_AD||AnalogDevices ID|0xAD|R|



## **ANALOG DEVICES MEMS ID REGISTER** 

This register contains the Analog Devices MEMS ID, 0x1D. 

## _**Address: 0x01, Reset: 0x1D, Name: DEVID_MST**_ 

## **Table 16. Bit Descriptions for DEVID_MST** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:0]|DEVID_MST||Analog Devices MEMS ID|0x1D|R|



## **DEVICE ID REGISTER** 

This register contains the device ID, 0xED (355 octal). 

## _**Address: 0x02, Reset: 0xED, Name: PARTID**_ 

**Table 17. Bit Descriptions for PARTID** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:0]|PARTID||Device ID (355 octal)|0xED|R|



## **PRODUCT REVISION ID REGISTER** 

This register contains the product revision ID, beginning with 0x00 and incrementing for each subsequent revision. 

## _**Address: 0x03, Reset: 0x00, Name: REVID**_ 

**Table 18. Bit Descriptions for REVID** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:0]|REVID||Mask revision|0x01|R|



## **STATUS REGISTER** 

This register includes bits that describe the various conditions of the ADXL355. 

## _**Address: 0x04, Reset: 0x00, Name: STATUS**_ 

**Table 19. Bit Descriptions for STATUS** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:5]|Reserved||Reserved.|0x0|R|
|4|NVM_BUSY||NVM controller is busywith either refresh,programming, or built-in, self test (BIST).|0x0|R|
|3|Activity||Activity, as defined in the THRESH_ACT and COUNT_ACT registers, is detected.|0x0|R|
|2|FIFO_OVR||FIFO has overrun, and the oldest data is lost.|0x0|R|
|1|FIFO_FULL||FIFO watermark is reached.|0x0|R|
|0|DATA_RDY||A complete x-axis,y-axis, and z-axis measurement was made and results can be read.|0x0|R|



Rev. A | Page 32 of 42 

**Data Sheet** 

**ADXL354/ADXL355** 

## **FIFO ENTRIES REGISTER** 

This register indicates the number of valid data samples present in the FIFO buffer. This number ranges from 0 to 96. 

## _**Address: 0x05, Reset: 0x00, Name: FIFO_ENTRIES**_ 

**Table 20. Bit Descriptions for FIFO_ENTRIES** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|7|Reserved||Reserved|0x0|R|
|[6:0]|FIFO_ENTRIES||Number of data samples stored in the FIFO|0x0|R|



## **TEMPERATURE DATA REGISTERS** 

These two registers contain the uncalibrated temperature data. The nominal intercept is 1852 LSB at 25°C and the nominal slope is −9.05 LSB/°C. TEMP2 contains the four most significant bits, and TEMP1 contains the eight least significant bits of the 12-bit value. 

## _**Address: 0x06, Reset: 0x00, Name: TEMP2**_ 

## **Table 21. Bit Descriptions for TEMP2** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:4]|Reserved||Reserved.|||
|[3:0]|Temperature, Bits[11:8]||Uncalibrated temperature data|0x0|R|



## _**Address: 0x07, Reset: 0x00, Name: TEMP1**_ 

## **Table 22. Bit Descriptions for TEMP1** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:0]|Temperature, Bits[7:0]||Uncalibrated temperature data|0x0|R|



## **X-AXIS DATA REGISTERS** 

These three registers contain the x-axis acceleration data. Data is left justified and formatted as twos complement. 

## _**Address: 0x08, Reset: 0x00, Name: XDATA3**_ 

## **Table 23. Bit Descriptions for XDATA3** 

|**Table 23. Bit**|**Descriptions for XDATA3**|||||
|---|---|---|---|---|---|
|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|[7:0]|XDATA, Bits[19:12]||X-axis data|0x0|R|



## _**Address: 0x09, Reset: 0x00, Name: XDATA2**_ 

**Table 24. Bit Descriptions for XDATA2** 

|**Table 24. Bit**|**Descriptions for XDATA2**|||||
|---|---|---|---|---|---|
|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|[7:0]|XDATA, Bits[11:4]||X-axis data|0x0|R|



## _**Address: 0x0A, Reset: 0x00, Name: XDATA1**_ 

**Table 25. Bit Descriptions for XDATA1** 

|**Table 25. Bit**|**Descriptions for XDATA1**|||||
|---|---|---|---|---|---|
|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|[7:4]|XDATA, Bits[3:0]||X-axis data|0x0|R|
|[3:0]|Reserved||Reserved|0x0|R|



Rev. A | Page 33 of 42 

**Data Sheet** 

## **ADXL354/ADXL355** 

## **Y-AXIS DATA REGISTERS** 

These three registers contain the y-axis acceleration data. Data is left justified and formatted as twos complement. 

## _**Address: 0x0B, Reset: 0x00, Name: YDATA3**_ 

## **Table 26. Bit Descriptions for YDATA3** 

|**Table 26. Bit**|**Descriptions for YDATA3**|||||
|---|---|---|---|---|---|
|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|[7:0]|YDATA, Bits[19:12]||Y-axis data|0x0|R|



## _**Address: 0x0C, Reset: 0x00, Name: YDATA2**_ 

## **Table 27. Bit Descriptions for YDATA2** 

|**Table 27. Bit**|**Descriptions for YDATA2**|||||
|---|---|---|---|---|---|
|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|[7:0]|YDATA, Bits[11:4]||Y-axis data|0x0|R|



## _**Address: 0x0D, Reset: 0x00, Name: YDATA1**_ 

## **Table 28. Bit Descriptions for YDATA1** 

|**Table 28. Bit**|**Descriptions for YDATA1**|||||
|---|---|---|---|---|---|
|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|[7:4]|YDATA, Bits[3:0]||Y-axis data|0x0|R|
|[3:0]|Reserved||Reserved|0x0|R|



## **Z-AXIS DATA REGISTERS** 

These three registers contain the z-axis acceleration data. Data is left justified and formatted as twos complement. 

## _**Address: 0x0E, Reset: 0x00, Name: ZDATA3**_ 

**Table 29. Bit Descriptions for ZDATA3** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:0]|ZDATA, Bits[19:12]||Z-axis data|0x0|R|



## _**Address: 0x0F, Reset: 0x00, Name: ZDATA2**_ 

## **Table 30. Bit Descriptions for ZDATA2** 

|**Table 30. Bit**|**Descriptions for ZDATA2**|||||
|---|---|---|---|---|---|
|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|[7:0]|ZDATA, Bits[11:4]||Z-axis data|0x0|R|



## _**Address: 0x10, Reset: 0x00, Name: ZDATA1**_ 

**Table 31. Bit Descriptions for ZDATA1** 

|**Table 31. Bit**|**Descriptions for ZDATA1**|||||
|---|---|---|---|---|---|
|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|[7:4]|ZDATA, Bits[3:0]||Z-axis data|0x0|R|
|[3:0]|Reserved||Reserved|0x0|R|



Rev. A | Page 34 of 42 

**Data Sheet** 

**ADXL354/ADXL355** 

## **FIFO ACCESS REGISTER** 

## _**Address: 0x11, Reset: 0x00, Name: FIFO_DATA**_ 

Read this register to access data stored in the FIFO. 

## **Table 32. Bit Descriptions for FIFO_DATA** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:0]|FIFO_DATA||FIFO data is formatted to 24 bits, 3 bytes, most significant byte first. A read to this<br>address pops an effective three equal byte words of axis data from the FIFO. Two<br>subsequent reads or a multibyte read completes the transaction of this data onto the<br>interface. Continued reading or a sustained multibyte read of this field continues to<br>pop the FIFO every third byte. Multibyte reads to this address do not increment the<br>address pointer. If this address is read due to an autoincrement from the previous<br>address, it does not pop the FIFO. Instead, it returns zeros and increments on to the<br>next address.|0x0|R|



## **X-AXIS OFFSET TRIM REGISTERS** 

## _**Address: 0x1E, Reset: 0x00, Name: OFFSET_X_H**_ 

**Table 33. Bit Descriptions for OFFSET_X_H** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:0]|OFFSET_X,<br>Bits[15:8]||Offset added to x-axis data after all other signal processing. Data is in twos complement<br>format. The significance of OFFSET_X[15:0] matches the significance of XDATA[19:4].|0x0|R/W|



## _**Address: 0x1F, Reset: 0x00, Name: OFFSET_X_L**_ 

**Table 34. Bit Descriptions for OFFSET_X_L** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:0]|OFFSET_X,<br>Bits[7:0]||Offset added to x-axis data after all other signal processing. Data is in twos complement<br>format. The significance of OFFSET_X[15:0] matches the significance of XDATA[19:4].|0x0|R/W|



## **Y-AXIS OFFSET TRIM REGISTERS** 

## _**Address: 0x20, Reset: 0x00, Name: OFFSET_Y_H**_ 

**Table 35. Bit Descriptions for OFFSET_Y_H** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:0]|OFFSET_Y,<br>Bits[15:8]||Offset added to y-axis data after all other signal processing. Data is in twos complement<br>format. The significance of OFFSET_Y[15:0] matches the significance of YDATA[19:4].|0x0|R/W|



## _**Address: 0x21, Reset: 0x00, Name: OFFSET_Y_L**_ 

**Table 36. Bit Descriptions for OFFSET_Y_L** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:0]|OFFSET_Y,<br>Bits[7:0]||Offset added to y-axis data after all other signal processing. Data is in twos complement<br>format. The significance of OFFSET_Y[15:0] matches the significance of YDATA[19:4].|0x0|R/W|



Rev. A | Page 35 of 42 

**ADXL354/ADXL355** 

**Data Sheet** 

## **Z-AXIS OFFSET TRIM REGISTERS** 

## _**Address: 0x22, Reset: 0x00, Name: OFFSET_Z_H**_ 

**Table 37. Bit Descriptions for OFFSET_Z_H** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:0]|OFFSET_Z,<br>Bits[15:8]||Offset added to z-axis data after all other signal processing. Data is in twos complement<br>format. The significance of OFFSET_Z[15:0] matches the significance of ZDATA[19:4].|0x0|R/W|
|**_Address: 0x23, Reset: 0x00, Name: OFFSET_Z_L_**<br>**Table 38. Bit Descriptions for OFFSET_Z_L**||||||
|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|[7:0]|OFFSET_Z,<br>Bits[7:0]||Offset added to z-axis data after all other signal processing. Data is in twos complement<br>format. The significance of OFFSET_Z[15:0] matches the significance of ZDATA[19:4].|0x0|R/W|



## **ACTIVITY ENABLE REGISTER** 

## _**Address: 0x24, Reset: 0x00, Name: ACT_EN**_ 

**Table 39. Bit Descriptions for ACT_EN** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:3]|Reserved||Reserved.|0x0|R|
|2|ACT_Z||Z-axis data is a component of the activitydetection algorithm.|0x0|R/W|
|1|ACT_Y||Y-axis data is a component of the activitydetection algorithm.|0x0|R/W|
|0|ACT_X||X-axis data is a component of the activitydetection algorithm.|0x0|R/W|



## **ACTIVITY THRESHOLD REGISTERS** 

## _**Address: 0x25, Reset: 0x00, Name: ACT_THRESH_H**_ 

**Table 40. Bit Descriptions for ACT_THRESH_H** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:0]|ACT_THRESH[15:8]||Threshold for activity detection. Acceleration magnitude must be above<br>ACT_THRESH to trigger the activity counter. ACT_THRESH is an unsigned<br>magnitude. The significance of ACT_TRESH[15:0] matches the significance of<br>XDATA, YDATA, and ZDATA[18:3].|0x0|R/W|



## _**Address: 0x26, Reset: 0x00, Name: ACT_THRESH_L**_ 

## **Table 41. Bit Descriptions for THRESH_ACT_X_L** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:0]|ACT_THRESH[7:0]||Threshold for activity detection. Acceleration magnitude must be above<br>ACT_THRESH to trigger the activity counter. ACT_THRESH is an unsigned<br>magnitude. The significance of ACT_TRESH[15:0] matches the significance of<br>XDATA, YDATA, and ZDATA[18:3].|0x0|R/W|



## **ACTIVITY COUNT REGISTER** 

## _**Address: 0x27, Reset: 0x01, Name: ACT_COUNT**_ 

**Table 42. Bit Descriptions for ACT_COUNT** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:0]|ACT_COUNT||Number of consecutive events above threshold required to detect activity|0x1|R/W|



Rev. A | Page 36 of 42 

**Data Sheet** 

**ADXL354/ADXL355** 

## **FILTER SETTINGS REGISTER** 

## _**Address: 0x28, Reset: 0x00, Name: Filter**_ 

Use this register to specify parameters for the internal high-pass and low-pass filters. 

**Table 43. Bit Descriptions for Filter** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|7|Reserved||Reserved|0x0|R|
|[6:4]|HPF_CORNER|000<br>001<br>010<br>011<br>100<br>101<br>110|−3 dB flter corner for the frst-order, high-pass filter relative to the ODR<br>Not applicable, no high-pass filter enabled<br>247 × 10−3× ODR<br>62.084 × 10−3× ODR<br>15.545 × 10−3× ODR<br>3.862 × 10−3× ODR<br>0.954 × 10−3× ODR<br>0.238 × 10−3× ODR|0x0|R/W|
|[3:0]|ODR_LPF|0000<br>0001<br>0010<br>0011<br>0100<br>0101<br>0110<br>0111<br>1000<br>1001<br>1010|ODR and low-pass filter corner<br>4000 Hz and 1000 Hz<br>2000 Hz and 500 Hz<br>1000 Hz and 250 Hz<br>500 Hz and 125 Hz<br>250 Hz and 62.5 Hz<br>125 Hz and 31.25 Hz<br>62.5 Hz and 15.625 Hz<br>31.25 Hz and 7.813 Hz<br>15.625 Hz and 3.906 Hz<br>7.813 Hz and 1.953 Hz<br>3.906 Hz and 0.977 Hz|0x0|R/W|



## **FIFO SAMPLES REGISTER** 

## _**Address: 0x29, Reset: 0x60, Name: FIFO_SAMPLES**_ 

Use the FIFO_SAMPLES value to specify the number of samples to store in the FIFO. The default value of this register is 0x60 to avoid triggering the FIFO watermark interrupt. 

**Table 44. Bit Descriptions for FIFO_SAMPLES** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|7|Reserved||Reserved.|0x0|R|
|[6:0]|FIFO_SAMPLES||Watermark number of samples stored in the FIFO that triggers a FIFO_FULL condition.<br>Values range from 1 to 96.|0x60|R/W|



## **INTERRUPT PIN (INTx) FUNCTION MAP REGISTER** 

## _**Address: 0x2A, Reset: 0x00, Name: INT_MAP**_ 

The INT_MAP register configures the interrupt pins. Bits[7:0] select which function(s) generate an interrupt on the INT1 and INT2 pins. Multiple events can be configured. If the corresponding bit is set to 1, the function generates an interrupt on the interrupt pins. 

**Table 45. Bit Descriptions for INT_MAP** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|7|ACT_EN2||Activityinterrupt enable on INT2|0x0|R/W|
|6|OVR_EN2||FIFO_OVR interrupt enable on INT2|0x0|R/W|
|5|FULL_EN2||FIFO_FULL interrupt enable on INT2|0x0|R/W|
|4|RDY_EN2||DATA_RDY interrupt enable on INT2|0x0|R/W|
|3|ACT_EN1||Activityinterrupt enable on INT1|0x0|R/W|
|2|OVR_EN1||FIFO_OVR interrupt enable on INT1|0x0|R/W|
|1|FULL_EN1||FIFO_FULL interrupt enable on INT1|0x0|R/W|
|0|RDY_EN1||DATA_RDY interrupt enable on INT1|0x0|R/W|



Rev. A | Page 37 of 42 

**ADXL354/ADXL355** 

**Data Sheet** 

## **DATA SYNCHRONIZATION** 

## _**Address: 0x2B, Reset: 0x00, Name: Sync**_ 

Use this register to control the external timing triggers. 

**Table 46. Bit Descriptions for Sync** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:3]|Reserved||Reserved.|0x0|R|
|2|EXT_CLK||Enable external clock.|0x0|R/W|
|[1:0]|EXT_SYNC|00<br>01<br>10<br>11|Enable external sync control.<br>Internal sync.<br>External sync, no interpolation filter. After synchronization, and for EXT_SYNC within<br>specification, DATA_RDY occurs on EXT_SYNC.<br>External sync, interpolation filter, next available data indicated by DATA_RDY 14 to<br>8204 oscillator cycles later (longer delay for higher ODR_LPF setting), data represents<br>a sample point group delay earlier in time.<br>Reserved.|0x0|R/W|



## **I[2] C SPEED, INTERRUPT POLARITY, AND RANGE REGISTER** 

## _**Address: 0x2C, Reset: 0x81, Name: Range**_ 

**Table 47. Bit Descriptions for Range** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|7|I2C_HS||I2C speed.<br>1 = high speed mode.<br>0 = fast mode.|0x1|R/W|
|6|INT_POL|0<br>1|Interrupt polarity.<br>INT1 and INT2 are active low.<br>INT1 and INT2 are active high.|0x0|R/W|
|[5:2]|Reserved||Reserved.|0x0|R|
|[1:0]|Range|01<br>10<br>11|Range.<br>±2_g_.<br>±4_g_.<br>±8_g_.|0x1|R/W|



## **POWER CONTROL REGISTER** 

## _**Address: 0x2D, Reset: 0x01, Name: POWER_CTL**_ 

**Table 48. Bit Descriptions for POWER_CTL** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:3]|Reserved||Reserved.|0x0|R|
|2|DRDY_OFF||Set to 1 to force the DRDY output to 0 in modes where it is normallysignal data ready.|0x0|R/W|
|1|TEMP_OFF||Set to 1 to disable temperature processing. Temperature processing is also disabled<br>when STANDBY = 1.|0x0|R/W|
|0|STANDBY|1<br>0|Standby or measurement mode.<br> <br>Standby mode. In standby mode, the device is in a low power state, and the<br>temperature and acceleration datapaths are not operating. In addition, digital<br>functions, including FIFO pointers, reset. Changes to the configuration setting of the<br>device must be made when STANDBY = 1. An exception is a high-pass filter that can<br>be changed when the device is operating.<br> <br>Measurement mode.|0x1|R/W|



Rev. A | Page 38 of 42 

**Data Sheet** 

**ADXL354/ADXL355** 

## **SELF TEST REGISTER** 

## _**Address: 0x2E, Reset: 0x00, Name: SELF_TEST**_ 

Refer to the Self Test section for more information on the operation of the self test feature. 

**Table 49. Bit Descriptions for SELF_TEST** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:2]|Reserved||Reserved.|0x0|R|
|1|ST2||Set to 1 to enable self test force|0x0|R/W|
|0|ST1||Set to 1 to enable self test mode|0x0|R/W|



## **RESET REGISTER** 

## _**Address: 0x2F, Reset: 0x00, Name: Reset**_ 

## **Table 50. Bit Descriptions for Reset** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:0]|Reset||Write Code 0x52 to resets the device, similar to apower-on reset (POR)|0x0|W|



Rev. A | Page 39 of 42 

**ADXL354/ADXL355** 

**Data Sheet** 

## **RECOMMENDED SOLDERING PROFILE** 

Figure 75 and Table 51 provide details about the recommended soldering profile. 

**==> picture [243 x 128] intentionally omitted <==**

**----- Start of picture text -----**<br>
CRITICAL ZONE<br>TP tP TL TO TP<br>RAMP-UP<br>TL TSMAX tL<br>TSMIN<br>PREHEATtS RAMP-DOWN<br>t25°C TO PEAK<br>TIME<br>TEMPERATURE<br>14205-039<br>**----- End of picture text -----**<br>


_Figure 75. Recommended Soldering Profile_ 

**Table 51. Recommended Soldering Profile** 

|**Table 51. Recommended Soldering Profile**|||
|---|---|---|
|**Profile Feature**|**Condition**||
||**Sn63/Pb37**|**Pb-Free**|
|Average Ramp Rate from Liquid Temperature (TL) to Peak Temperature (TP)<br>Preheat<br>Minimum Temperature (TSMIN)<br>Maximum Temperature (TSMAX)<br>Time from TSMINto TSMAX(tS)<br>TSMAXto TLRamp-Up Rate<br>Liquid Temperature (TL)<br>Time Maintained Above TL(tL)<br>Peak Temperature (TP)<br>Time of Actual TP− 5°C (tP)<br>Ramp-Down Rate<br>Time from 25°C to Peak Temperature (t25°C TO PEAK)|3°C/sec maximum<br>100°C<br>150°C<br>60 sec to 120 sec<br>3°C/sec maximum<br>183°C<br>60 sec to 150 sec<br>240°C + 0°C/−5°C<br>10 sec to 30 sec<br>6°C/sec maximum<br>6 minutes maximum|3°C/sec maximum<br>150°C<br>200°C<br>60 sec to 180 sec<br>3°C/sec maximum<br>217°C<br>60 sec to 150 sec<br>260°C + 0°C/−5°C<br>20 sec to 40 sec<br>6°C/sec maximum<br>8 minutes maximum|



Rev. A | Page 40 of 42 

**Data Sheet** 

**ADXL354/ADXL355** 

## **PCB FOOTPRINT PATTERN** 

Figure 76 shows the PCB footprint pattern and dimensions in millimeters. 

**==> picture [295 x 251] intentionally omitted <==**

**----- Start of picture text -----**<br>
3.22mm<br>0.68mm<br>0.70mm 0.70mm<br>14 PLCS<br>1.8mm × 0.68mm<br>3.80mm<br>Figure 76. PCB Footprint Pattern and Dimensions in Millimeters<br>4.5mm 3.80mm<br>14205-040<br>**----- End of picture text -----**<br>


Rev. A | Page 41 of 42 

**ADXL354/ADXL355** 

**Data Sheet** 

## **PACKAGING AND ORDERING INFORMATION** 

## **OUTLINE DIMENSIONS** 

**==> picture [337 x 265] intentionally omitted <==**

**----- Start of picture text -----**<br>
DETAIL A<br>0.80<br>6.25 2.25 BSC<br>6.00 SQ 2.05<br>1.674 BSC<br>5.85 1.85 0.510 REF<br>7 11 12 14 1 0.30 SQ(PIN 1 INDEX) uy<br>DETAIL A<br>5.60<br>(14 PLCS)R 0.103 SQ 3.81REF 0.508<br>BSC<br>8 4<br>7 5<br>R 0.25 S TOP VIEW | SIDE VIEW aa BOTTOM VIEW Lom SH 0.914<br>(4 PLCS)R 0.203 0.10 BSC an 0.15BSC dey 2.20 REF 2.54 REF me BSC<br>(14 PLCS)<br>Figure 77. 14-Terminal Ceramic Leadless Chip Carrier [LCC]<br>(E-14-1)<br>Dimensions shown in millimeters<br>NO BRAND ON THIS LINE PIN ONE LOCATOR, NO OTHER BRAND ON THIS LINE<br>PART NUMBER ADXL354B, ADXL354C, OR ADXL355B<br>#YYWW TWO DIGIT YEAR, TWO DIGIT WEEK ID<br>6 DIGIT LOT NUMBER SIX DIGIT LOT NUMBER<br>| =<br>PKG-004554 05-27-2016-B<br>14205-078<br>**----- End of picture text -----**<br>


## **BRANDING INFORMATION** 

_Figure 78. Branding Information_ 

## **ORDERING GUIDE** 

|**Model1**|**Output**<br>**Mode**|**Measurement**<br>**Range (****_g_) **|**Specified**<br>**Voltage (V)**|**Temperature Range **|**Package Description**|**Package**<br>**Option**|
|---|---|---|---|---|---|---|
|ADXL354BEZ<br>ADXL354BEZ-RL<br>ADXL354BEZ-RL7<br>ADXL354CEZ<br>ADXL354CEZ-RL<br>ADXL354CEZ-RL7|Analog<br>Analog<br>Analog<br>Analog<br>Analog<br>Analog|±2, ±4<br>±2, ±4<br>±2, ±4<br>±2, ±8<br>±2, ±8<br>±2, ±8|3.3<br>3.3<br>3.3<br>3.3<br>3.3<br>3.3|−40°C to +125°C<br>−40°C to +125°C<br>−40°C to +125°C<br>−40°C to +125°C<br>−40°C to +125°C<br>−40°C to +125°C|14-Terminal LCC<br>14-Terminal LCC<br>14-Terminal LCC<br>14-Terminal LCC<br>14-Terminal LCC<br>14-Terminal LCC|E-14-1<br>E-14-1<br>E-14-1<br>E-14-1<br>E-14-1<br>E-14-1|
|ADXL355BEZ<br>ADXL355BEZ-RL<br>ADXL355BEZ-RL7|Digital<br>Digital<br>Digital|±2.048, ±4.096,<br>±8.192<br>±2.048, ±4.096,<br>±8.192<br>±2.048, ±4.096,<br>±8.192|3.3<br>3.3<br>3.3|−40°C to +125°C<br>−40°C to +125°C<br>−40°C to +125°C|14-Terminal LCC<br>14-Terminal LCC<br>14-Terminal LCC|E-14-1<br>E-14-1<br>E-14-1|
|EVAL-ADXL354BZ<br>EVAL-ADXL354CZ<br>EVAL-ADXL355Z|||||Evaluation Board for ADXL354BEZ<br>Evaluation Board for ADXL354CEZ<br>Evaluation Board for ADXL355BEZ||



1 Z = RoHS-Compliant Part. 

**©2016–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D14205-0-4/18(A)** 

Rev. A | Page 42 of 42
Updated at April 28, 2026
Since its inception in 1965, Analog Devices has established itself as a global leader in the design and manufacturing of high-performance analog, mixed-signal, and digital signal processing (DSP) integrated circuits. The company is renowned for solving complex engineering challenges by providing critical technologies that seamlessly convert real-world phenomena into precise electrical signals for the industrial, automotive, communications, and consumer markets. Within its extensive portfolio, Analog Devices provides highly reliable clock, timing, and frequency management solutions, featuring a comprehensive array of precision timers, oscillators, and pulse generators. Complementing this core lineup is a robust offering of driver and interface ICs, particularly high-performance I/O expanders that enable seamless connectivity and streamline complex electronic system architectures. Beyond these foundational integrated circuits, Analog Devices leads the industry in sensor innovation, delivering advanced MEMS accelerometers and integrated MEMS modules designed for exceptional precision in motion sensing. To support complete hardware designs, the company's specialized offerings also encompass discrete bipolar transistors, sub-2.4GHz RF transceivers, temperature-compensated oscillators, and dedicated power management components such as DC/DC converters and LED driver ICs.
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