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ZWIR4532-U
Wireless LAN Module, 914MHz, I2C, SPI, UART, Home Appliances, Industrial Process Controls, Lights
⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
- Manufacturer: RENESAS
- Product type: WLAN Modules & USB Adaptors
- Frequency RF:914MHz; Module Interface:I2C, SPI, UART; Module Applications:Smart Home Devices/Appliances, Industrial Process Controls/Environmental Monito; Available until stocks are exhausted
- SVHC: No SVHC (12-Jan-2017)
- Frequency RF: 914MHz
- Product Range: -
- Module Interface: I2C, SPI, UART
- Module Applications: Smart Home Devices/Appliances, Industrial Process Controls/Environmental Monitoring, Street Lights
| Delivery and price | |
|---|---|
| Units per pack | 10 |
| Price | 17.55 € |
| Current stock | 10+ |
| Lead time | 30 days |
Datasheet
Low Power 6LoWPAN Communication Module
ZWIR4532 Datasheet
## Description
The ZWIR4532 is a programmable low-power secure IPv6 communication module for Internet-of-things (IOT) device networks. Sensors and devices can operate autonomously or connect to local or global IPv6 networks using the ZWIR4532. The ZWIR4532 serves as a universal secure radio communication module for applications with low-bandwidth requirements.
The module incorporates an ultra-low-power ARM[®] Cortex™-M0+ 32-bit microcontroller that runs the network stack. In addition, the user application can run on the microcontroller. This helps minimize the size, complexity, and overall BOM. A rich set of digital and analog peripherals is available for interfacing with external application components. Approximately 128kB of flash and 4kB of RAM are available for user applications.
IDT offers the SensorShare[TM] user programmable royalty-free 6LoWPAN network stack with mesh routing capability for the ZWIR4532. 6LoWPAN is an Internet Engineering Task Force (IETF) standard for wireless low-power IPv6-based sensor and device networks.
Secure communication is provided by a standard-compliant implementation of the Internet Protocol Security (IPSec) protocol suite.
## Features
- License-free 868/915 MHz frequency bands
- 4 channels in EU frequency band (865.3 to 868.3 MHz)
- 10 channels in US frequency band (906 to 924 MHz)
- BPSK or O-QPSK modulation selectable
- BPSK with 20kBps EU and 40kBps US
- ARM[®] Cortex™-M0+ 32-bit ultra-low-power microcontroller
- 192kB flash and 20kB RAM
- 6 Kbyte EEPROM
- 5 UART interfaces
- 1 SPI interface
- 3 I2C interfaces
- 10 pulse-width-modulation (PWM) outputs
- 12-bit ADC with 10 input channels
- 2 analog comparators
- 31 general purpose I/O (GPIO) pins
- Network Stack
- UDP/IPv6 communication
- Mesh networking with hundreds of nodes
- Self-healing defective routes
- Over-the-Air update (OTAU) capable
## Typical Applications
- Industrial automation
- Home and building automation
- Health monitoring
- Telemetry
- Network layer security
- Ultra-low power Stop Mode: < 1µA with full RAM retention
- Supply voltage: 1.8V to 3.3V
- -40°C to +85°C ambient operating temperature
- 15.6 × 12 mm 43-LGA package
## Block Diagram
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June 5, 2019
ZWIR4532 Datasheet
## Contents
|1.|Pin Assignments ...........................................................................................................................................................................................3|
|---|---|
|2.|Pin Descriptions ............................................................................................................................................................................................4|
|3.|Absolute Maximum Ratings ..........................................................................................................................................................................7|
|4.|Recommended Operating Conditions ..........................................................................................................................................................8|
|5.|Functional Overview .....................................................................................................................................................................................9|
||5.1 Low Power Modes .............................................................................................................................................................................10|
||5.2 Device Programming and Debugging ................................................................................................................................................10|
|6.|Package Outline Drawing ...........................................................................................................................................................................10|
|7.|Soldering Information .................................................................................................................................................................................11|
|8.|Certification .................................................................................................................................................................................................12|
||8.1 European RED Statement .................................................................................................................................................................12|
||8.2 Federal Communication Commission Certification Statements .........................................................................................................12|
||8.2.1<br>Statements .........................................................................................................................................................................12|
||8.2.2<br>Requirements .....................................................................................................................................................................12|
||8.2.3<br>Supported Antennas ...........................................................................................................................................................13|
|9.|Ordering Information ...................................................................................................................................................................................13|
|10.|Revision History ..........................................................................................................................................................................................14|
## List of Figures
|Figure 1.|Figure 1.|Pin Assignments for 15.6mm12.0mm 43-LGA Package – Top View ..............................................................................................3|
|---|---|---|
|Figure 2.|Figure 2.|Serial-Wire Debug Connection with Standard ARM Connectors .......................................................................................................10|
|Figure 3.|Figure 3.|Recommended Temperature Profile for Reflow Soldering (according to J-STD-020D) ....................................................................11|
|Figure 4.|Figure 4.|FCC Compliance Statement to be Printed on Equipment Incorporating ZWIR4532 Devices ............................................................13|
## List of Tables
|Table 1.|Table 1.|Pin Descriptions ...................................................................................................................................................................................4|
|---|---|---|
|Table 2.|Table 2.|Module Pins Peripheral Function Mapping ..........................................................................................................................................6|
|Table 3.|Table 3.|Absolute Maximum Ratings .................................................................................................................................................................7|
|Table 4.|Table 4.|Recommended Operating Conditions .................................................................................................................................................8|
|Table 5.|Table 5.|Soldering Profile Parameters (according to J-STD-020D) .................................................................................................................11|
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ZWIR4532 Datasheet
## 1. Pin Assignments
Figure 1. Pin Assignments for 15.6mm 12.0mm 43-LGA Package – Top View
**==> picture [482 x 378] intentionally omitted <==**
**----- Start of picture text -----**<br>
A0 A1 A2 C15 C14 C13 VDDA<br>FU 7 6 UU 5 4 UO 3 2 1<br>A6 B8 B9 A11 A12 A15 B14<br>RST DIG1<br>8 33 32 31 30 29 28 27 26<br>FP] [JU<br>GND GND<br>= 9 = 25<br>A7<br>34<br>A10 ANT<br>10 24<br>ait =<br>B2<br>35<br>A9 GND<br>11 23<br>ait =<br>B10<br>36<br>VDD PA+<br>a 12 = 22<br>37 38 39 40 41 42 43<br>BSEL PA-<br>13 B0 B1 A8 B3 B4 B6 B7 21<br>Pl [JU<br>14 15 16 17 18 19 20<br>A3 A4 A5 A13 A14 B5 VREF+<br>PTTL<br>EL EI Peed<br>**----- End of picture text -----**<br>
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ZWIR4532 Datasheet
## 2. Pin Descriptions
## Table 1. Pin Descriptions
|**Pin**<br>**Number**<br>~~PR~~|**Name**|**Type**|**5V**|**Description**|
|---|---|---|---|---|
|1<br>~~PR~~<br>~~PR~~|VDDA|Supply||Analog supply voltage.|
|2<br>~~PR~~<br>~~PR~~|C13|GPIO|Y|RTC Tamper, TRC Timestamp, RTC Output, Wakeup 2.|
|3<br>~~PR~~<br>~~PD~~|C14<br>~~PD~~|GPIO|Y|OSC32 In.|
|4<br>~~PD~~<br>~~a~~|C15<br>~~PD~~<br>~~a~~|GPIO<br>~~a~~|N|OSC32 Out.|
|5<br>~~a~~<br>~~a~~|A2<br>~~a~~<br>~~a~~|GPIO<br>~~a~~<br>~~a~~|Y|Timer21 Ch1, Timer2 Ch3, USRT2 TX, LPUART1 TX, COMP2 Output, COMP2 INM, ADC Ch2.|
|6<br>~~a~~|A1<br>~~a~~|GPIO<br>~~a~~|Y|Event Out, Timer2 Ch2, USART2 RTS/DE, TIM21 ETR, USART4 RX, COMP1 Input, ADC Ch1.|
|7<br>~~a~~<br>~~PR~~|A0<br>~~a~~|GPIO<br>~~a~~|N|Timer 2 Ch1, Timer 2 ETR, USART2 CTS, USART4 TX, COMP1 OUT, COMP1 INM, ADC Ch 0,<br>RTC Tamper 2, Wakeup 1.|
|8<br>~~PR~~<br>~~PR~~|RST|I/O|N|Device reset, active low.|
|9<br>~~PR~~<br>~~PR~~<br>~~PR~~|GND|Ground|||
|10<br>~~PR~~<br>~~PR~~|A10|GPIO|Y[a]|USART1 RX, I2C1 SDA.|
|11<br>~~PR~~<br>~~PD~~|A9<br>~~PD~~|GPIO|Y[a]|MCO, USART1 TX, I2C1 SCL, I2C3 SMBA.|
|12<br>~~PD~~<br>~~a~~<br>~~SR~~|VDD<br>~~PD~~<br>|Supply<br>|||
|13<br>~~a~~<br>~~SR~~|BSEL<br>|I<br>|N<br>||
|14<br>~~SRaa~~|A3<br>~~aa~~|GPIO<br>~~aa~~|Y<br>~~aa~~|Timer21 Ch2, Timer2 Ch4, USART2 RX, LPUART1 RX, COMP2 INP, ADC Ch3.<br>~~aa~~|
|15<br>~~aa~~<br>~~a~~|A4<br>~~aa~~<br>~~a~~<br>~~a~~|GPIO<br>~~aa~~<br>~~a~~<br>~~a~~|N<br>~~aa~~<br>~~a~~|SPI1 NSS, USART2 CK, Timer22 ETR, COMP1 INM, COMP2 INM, ADC Ch4.<br>~~aa~~|
|16<br>~~a~~<br>~~Pe~~|A5<br>~~a~~<br>~~a ~~<br>~~Pe~~|GPIO<br>~~a~~<br> ~~a ~~|N<br> ~~a~~|SPI1 SCK, Timer2 ETR, Timer2 Ch1, COMP1 INM, COMP2 INM, ADC Ch5.|
|17<br>~~A~~|A13[b]<br>~~A~~|GPIO<br>~~A~~|Y|SWDIO, LPUART1 RX.|
|18|A14[b]|GPIO|Y|SWCLK, USART2 TX, LPUART1 TX.|
|19<br>~~i~~<br>~~a~~|B5<br>~~i~~<br>~~a~~|GPIO<br>~~i~~<br>~~a~~|Y<br>~~ae~~|SPI1 MOSI, LPTimer1 In1, I2C1 SMBA, Timer3 Ch2, Timer22 Ch2, USART1 CK, USART5 CK,<br>USART5 RTS/DE, Comp2 INP.|
|20<br>~~i~~<br>~~a~~<br>~~a~~|VREF+<br>~~i~~<br>~~a~~<br>~~a~~|Supply<br>~~i~~<br>~~a~~<br>~~a~~|~~ae~~||
|21<br>~~a~~<br>~~a~~<br>~~a~~|PA-<br>~~a~~<br>~~a~~<br>~~ee~~|O<br>~~a~~<br>~~a~~<br>~~ee~~|~~ae~~<br>~~ee~~|Differential power amplifier control output, internally tied to ground if not used. Leave unconnected if<br>not used.|
|22<br>~~a~~<br>~~a~~|PA+<br>~~a~~<br>~~ee~~|O<br>~~a~~<br>~~ee~~|~~ae~~<br>~~ee~~||
|23<br>~~a~~<br>~~Pe~~|GND<br>~~ee~~<br>~~Pe~~|Ground<br>~~ee~~|~~ee~~||
|24<br>~~A~~|ANT|Antenna||Antenna pin.|
|25<br>~~A~~<br>~~PR~~|GND|Ground|||
|26<br>~~PR~~<br>~~PR~~|DIG1|O||Unused in application – leave unconnected.|
|27<br>~~PR~~<br>~~PR~~|B14|GPIO|Y[a]|SPI2 MISO, I2S2 MCK, RTC Out, LPUART1 RTS/DE, I2C2 SDA, Timer21 Ch2.|
|28<br>~~PR~~<br>~~OR~~|A15<br>~~OR~~|GPIO<br>~~a~~|Y|SPI1 NSS, Timer2 ETR, Event Out, USART2 RX, Timer2 Ch1, USART4 RTS/DE.|
|29<br>~~OR~~<br>~~a~~|A12<br>~~OR ~~<br>~~a~~<br>~~a~~|GPIO<br> ~~a~~<br>~~a~~<br>~~a~~<br>~~a~~|Y<br>~~a~~<br>~~a~~|SPI1 MOSI, Event Out, USART1 RTS/DE, COMP2 Out.<br>~~a~~<br>~~a~~|
|30<br>~~a~~<br>~~a~~|A11<br>~~a~~<br>~~a~~<br>~~a~~|GPIO<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~|Y<br>~~a~~<br>~~a~~|SPI1 MISO, Event Out, USART1 CTS, COMP1 Out.<br>~~a~~<br>~~a~~|
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ZWIR4532 Datasheet
|**Pin**<br>**Number**|**Name**|**Type**|**5V**|**Description**|
|---|---|---|---|---|
|31<br>~~a ~~<br>~~PR~~|B9<br> ~~a~~|GPIO<br>~~i~~|Y[a]<br>~~i~~|Event Out, I2C1 SDA, SPI2 NSS, I2S2 WS.|
|32<br>~~PR~~<br>~~PR~~|B8|GPIO|Y[a]|I2C1 SCL.|
|33<br>~~PR~~<br>~~PR~~<br>~~PR~~|A6|GPIO|Y|SPI1 MISO, Timer3 Ch1, LPUART1 CTS, Timer22 Ch1, Event Out, COMP1 Out, ADC Ch6.|
|34<br>~~PR~~<br>~~PR~~<br>~~PR~~|A7|GPIO|Y|SPI1 MOSI, Timer3 Ch2, Timer22 Ch2, Event Out, COMP2 Out, ADC Ch7.|
|35<br>~~PR~~<br>~~PR~~|B2|GPIO|Y|LPTimer 1 Out, I2C3 SMBA.|
|36<br>~~PR~~<br>~~PD~~|B10<br>~~PD~~|GPIO|Y|Timer 2 Ch3, LPUART1 TX, SPI2 SCK, I2C2 SCL, LPUART1 RX.|
|37<br>~~PD~~<br>~~a~~<br>~~SR~~|B0<br>~~PD~~|GPIO|Y|Event Out, Timer3 Ch3, ADC Ch8, VREF Out.|
|38<br>~~a~~<br>~~SR~~<br>~~PR~~|B1|GPIO|Y|Timer3 Ch4, LPART1 RTS/DE, ADC Ch9, VREF Out.|
|39<br>~~SR~~<br>~~PR~~<br>~~PR~~|A8|GPIO|Y[a]|MCO, Event Out, USART1 CK, I2C3 SCL.|
|40<br>~~PR~~<br>~~PR~~<br>~~PR~~|B3|GPIO|Y|SPI1 SCK, Timer2 Ch2, Event Out, USART2 RTS/DE, USART5 TX, COMP2 INM.|
|41<br>~~PR~~<br>~~PR~~<br>~~PR~~|B4<br>|GPIO|Y[a]|SPI1 MISO, Timer3 Ch1, Timer22 Ch1, USART1 CTS, USART5 RX, I2C3 SDA, COMP2 INP.|
|42<br>~~PR~~<br>~~PR~~|B6<br>|GPIO|Y[a]|USART1 TX, I2C1 SCL, LPTimer1 ETR, COMP2 INP.|
|43<br>~~PRPR~~|B7<br>~~PR~~|GPIO|Y[a]|USART1 RX, I2C1 SDA, LPTimer1 In2, USART4 CTS, COMP2 INP, VREF PVD In.|
[a] This pin has support for I2C Fast-Mode Plus support. Refer to the datasheet for the STM32L071xZ for more detailed information.
[b] Pins A13 and A14 are configured as Serial Wire Debug pins SWDIO and SWCLK on startup.
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ZWIR4532 Datasheet
Table 2. Module Pins Peripheral Function Mapping
|MCU Port<br>~~a~~|MCU Port<br>~~a~~|Port A|Port A|Port A|Port A|Port A|Port A|Port A|Port A|Port A|Port A|Port A|Port A|Port A|Port A|Port A|Port A|Port B|Port B|Port B|Port B|Port B|Port B|Port B|Port B|Port B|Port B|Port B|Port B|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|MCU Port Pin<br>~~a ~~<br>~~Po~~||0<br> ~~a ~~|1<br> ~~ee~~|2<br>~~ee~~|3<br>~~ee~~|4<br>~~ee~~|5|6|7|8<br>~~ee~~|9<br>~~ee~~|10<br>~~ee~~|11<br>~~ee~~|12<br>~~ee~~|13<br>~~ee~~|14|15<br>~~ee~~|0<br>~~ee~~|1<br>~~ee ~~|2<br> ~~ee~~|3<br>~~ee~~|4<br>~~ee ~~|5<br> ~~eee~~|6<br>~~eee~~|7<br>~~eee~~|8<br>~~eee ~~|9<br> ~~eee~~|10<br>~~eee~~|14<br>~~eee~~|
|Module Pin<br>~~Po~~<br>~~a~~||7<br>~~a~~|6<br>~~a~~|5<br>~~a~~|14|15<br>~~ee~~|16<br>~~ee~~|33<br>~~a~~|34<br>~~a~~|39<br>~~i~~|11<br>~~ae~~|10<br>~~ae~~|30<br>~~ie~~|29<br>~~i~~|17<br>~~ee~~|18<br>~~ee~~|28<br>~~ee~~|37<br>~~ee~~|38<br>~~ee~~|35<br>~~ee~~|40<br>~~ee~~|41<br>~~ee~~|19|42|43|32|31|36|27|
|USART1<br>~~Po~~|TX<br>~~Po~~<br>~~a~~|~~a~~|~~a~~|~~a~~||~~ee~~|~~ee~~|~~a~~|~~a~~|~~i~~|4<br>~~ae~~|~~ae~~|~~ie~~|~~i~~|~~ee~~|~~ee~~|~~ee~~|~~ee~~|~~ee~~|~~ee~~|~~ee~~|~~ee~~||0||||||
||RX<br>~~a ~~<br>~~a~~|~~a ~~<br>~~a ~~|~~a ~~<br> ~~a~~|~~a~~<br> a|a|~~ee~~<br>a|~~ee ~~<br>~~ea~~|~~a ~~<br>~~ea~~|~~a ~~|~~i ~~<br>~~a~~|~~ae~~<br>~~a~~|4<br>~~ae ~~<br>~~ee~~|~~ie ~~<br>~~ee i~~|~~i ~~<br>~~i~~|~~ee~~<br>~~ee~~|~~ee ~~<br>~~ee ~~|~~ee~~<br> ~~ee~~|~~ee~~<br>~~ee~~|~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~|~~ee~~|0|||||
||RTS<br>~~a~~|~~a ~~|~~a ~~|~~a~~|a|a|~~a~~|a|~~i ~~|~~i~~||~~se~~|~~se~~|4<br>~~se~~|~~se~~||~~QQ~~|~~QQ~~|~~QQ~~|~~GG~~|5<br>~~GG~~|~~GG~~|~~GG~~|~~GG~~|~~GG~~|~~GG~~|~~GG~~|~~GG~~||
||CTS<br>~~a~~<br>~~es~~<br>~~a~~|~~a~~<br>~~ee~~<br>~~a~~|~~a~~<br>~~ee~~<br>~~a~~|~~a~~<br>~~ee~~<br>|~~eee~~<br>~~ee~~<br>|~~eee~~<br>~~ee~~<br>|~~eee~~<br>~~ee~~|~~eee~~<br>~~ee~~|~~eee~~<br>~~ee~~|~~eee~~<br>~~ee~~|~~eee~~<br>~~ee~~|~~eee~~<br>~~ee~~|4<br>~~eee~~<br>~~ee~~|~~eee~~<br>~~ee~~|~~eee~~<br>~~ee~~|~~eee~~<br>~~ee~~|~~eee~~<br>~~ee~~|~~eee~~<br>~~ee~~<br>~~eee~~|~~eee~~<br>~~ee~~<br>~~eee~~|~~eee~~<br>~~ee~~<br>~~eee~~|~~eee~~<br>~~ee~~<br>~~eee~~|5<br>~~eee~~<br>~~ee~~<br>~~eee~~|~~eee~~<br>~~ee~~<br>~~eee~~|~~eee~~<br>~~ee~~<br>~~eee~~|~~eee~~<br>~~ee~~<br>~~eee~~|~~eee~~<br>~~ee~~<br>~~eee~~|~~eee~~<br>~~ee~~<br>~~eee~~|~~eee~~<br>~~ee~~<br>~~eee~~|~~eee~~<br>~~ee~~<br>~~eee~~|
||CK<br>~~a ~~<br>~~es~~<br>~~a~~<br>~~a~~|~~a~~<br>~~ee~~<br>~~a~~<br>|~~a ~~<br>~~ee~~<br>~~a a~~|~~a~~<br>~~ee~~<br>~~a~~|~~eee~~<br>~~ee~~<br>~~a~~|~~eee~~<br>~~ee~~<br>~~a~~|~~eee~~<br>~~ee~~|~~eee~~<br>~~ee~~<br>~~a~~|~~eee~~<br>~~ee~~<br>~~i~~|4<br>~~eee~~<br>~~ee~~<br>~~i~~|~~eee~~<br>~~ee~~<br>~~a~~|~~eee~~<br>~~ee~~<br>~~ee~~|~~eee~~<br>~~ee~~<br>~~ee~~|~~eee~~<br>~~ee~~<br>~~se~~|~~eee~~<br>~~ee~~<br>~~se~~|~~eee~~<br>~~ee~~|~~eee~~<br>~~ee~~<br>~~Qe~~|~~eee~~<br>~~ee~~<br>~~eee~~<br>~~Qe~~|~~eee~~<br>~~ee~~<br>~~eee~~|~~eee~~<br>~~ee~~<br>~~eee~~<br>~~OG~~|~~eee~~<br>~~ee~~<br>~~eee~~<br>~~OG~~|~~eee~~<br>~~ee~~<br>~~eee~~<br>~~OG~~|5<br>~~eee~~<br>~~ee~~<br>~~eee~~<br>~~QO~~|~~eee~~<br>~~ee~~<br>~~eee~~<br>~~QO GG~~|~~eee~~<br>~~ee~~<br>~~eee~~<br>~~GG~~|~~eee~~<br>~~ee~~<br>~~eee~~<br>~~GG~~|~~eee~~<br>~~ee~~<br>~~eee~~<br>~~GG~~|~~eee~~<br>~~ee~~<br>~~eee~~|~~eee~~<br>~~ee~~<br>~~eee~~|
|USART2|TX<br>~~es~~<br>~~a~~<br>~~a~~|~~ee~~<br>~~a~~<br>~~a~~|~~ee~~<br>~~a a~~|4<br>~~ee~~<br>~~a~~|~~ee~~<br>~~a~~|~~ee~~<br>~~a~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~a~~<br>~~ee~~|~~ee~~<br>~~i~~<br>~~ee~~|~~ee~~<br>~~i~~<br>~~ee~~|~~ee~~<br>~~a~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~se~~|~~ee~~<br>~~se~~<br>~~eee~~|4<br>~~ee~~<br>~~eee~~|~~ee~~<br>~~Qe~~<br>~~eee~~|~~ee~~<br>~~eee~~<br>~~Qe~~<br>~~ee~~|~~ee~~<br>~~eee~~<br>~~ee~~|~~ee~~<br>~~eee ~~<br>~~OG~~<br>~~ee~~|~~ee~~<br> ~~eee~~<br>~~OG~~<br>~~ee~~|~~ee~~<br>~~eee~~<br>~~OG~~<br>~~ee~~|~~ee~~<br>~~eee ~~<br>~~QO~~<br>~~ee~~|~~ee~~<br> ~~eee~~<br>~~QO GG~~<br>~~eee~~|~~ee~~<br>~~eee~~<br>~~GG~~<br>~~eee~~|~~ee~~<br>~~eee ~~<br>~~GG~~<br>~~eee eee~~|~~ee~~<br> ~~eee~~<br>~~GG~~<br>~~eee~~|~~ee~~<br>~~eee~~<br>~~eee~~|~~ee~~<br>~~eee~~<br>~~eee~~|
||RX<br><br>~~a~~ <br>~~a~~|~~a~~<br>~~a~~|~~a~~<br>~~a~~|~~a ~~<br>~~a~~|4<br> ~~a ~~|~~a~~<br>~~a~~|~~ee~~|~~a ~~<br>~~ee~~<br>~~a~~|~~i~~<br>~~ee~~<br>~~i~~|~~i ~~<br>~~ee~~<br>~~ie~~|~~a~~<br>~~ee~~<br>~~i~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee ~~<br>~~ee~~<br>~~ee~~|~~se~~<br>~~ee~~|~~se~~<br>~~eee~~<br>~~ee~~|~~eee~~<br>~~ee~~|4<br>~~Qe~~<br>~~eee~~<br>~~eG~~|~~Qe~~<br>~~ee~~<br>~~eG~~|~~ee~~<br>~~eG~~|~~OG~~<br>~~ee~~<br>~~eG~~|~~OG~~<br>~~ee~~<br>~~eG~~|~~OG~~<br>~~ee~~<br>~~eG~~|~~QO~~<br>~~ee~~|~~QO GG~~<br>~~eee~~|~~GG~~<br>~~eee~~|~~GG~~<br>~~eee eee~~|~~GG~~<br>~~eee~~|~~eee~~|~~eee~~|
||RTS<br> <br>~~a~~<br>~~a~~|~~a~~<br>~~a~~<br>~~a~~|4<br>~~a~~<br>~~a~~|~~a~~<br>|~~a~~|~~a~~<br>~~a~~|~~ee~~|~~ee~~<br>~~a~~<br>~~a~~|~~ee~~<br>~~i~~|~~ee~~<br>~~ie~~|~~ee~~<br>~~i~~<br>~~es~~|~~ee~~<br>~~ee~~<br>~~es~~|~~ee~~<br>~~ee~~<br>~~es~~|~~ee~~<br>~~es~~|~~eee~~<br>~~ee~~<br>~~ee~~|~~eee~~<br>~~ee~~|~~eee ~~<br>~~eG~~<br>~~Qe~~|~~ee~~<br>~~eG~~<br>~~Qe~~|~~ee~~<br>~~eG~~|~~ee ~~<br>~~eG~~<br>~~Qs~~|~~ee ~~<br>~~eG~~<br>~~Qs~~|~~ee~~<br>~~eG~~<br>~~GG~~|~~ee ~~<br>~~GG~~|~~eee~~<br>~~GG~~|~~eee~~<br>~~GO~~|~~eee eee~~<br>~~GO~~|~~eee~~<br>~~GO~~|~~eee~~|~~eee~~|
||CTS<br>~~a~~<br>~~a~~<br>~~ee~~|4<br>~~a ~~<br>~~a~~|~~a ~~<br>~~a~~|~~a~~<br>|~~a~~|~~a~~<br>~~a~~|~~ee~~|~~a ~~<br>~~a~~<br>~~ee~~|~~i ~~<br>~~ee~~|~~ie ~~<br>~~ee~~|~~i ~~<br>~~es~~<br>~~ee~~|~~ee~~<br>~~es~~<br>~~ee~~|~~ee~~<br>~~es~~<br>~~ee~~|~~ee~~<br>~~es~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~eee~~|~~ee ~~<br>~~eee~~|~~eG~~<br>~~Qe~~<br>~~eee~~|~~eG~~<br>~~Qe~~<br>~~ee~~|~~eG~~<br>~~ee~~|~~eG~~<br>~~Qs~~<br>~~ee~~|~~eG~~<br>~~Qs~~<br>~~eee~~|~~eG~~<br>~~GG~~<br>~~eee~~|~~GG~~<br>~~eee~~|~~GG~~<br>~~ee~~|~~GO~~<br>~~eeeee~~|~~GO~~<br>~~eee~~|~~GO~~<br>~~eee~~|~~eee~~|~~eee~~|
||CK<br>~~a~~<br>~~ee~~|~~a ~~|~~a ~~||~~a~~|4<br>~~a~~|~~ee~~|~~a~~<br>~~ee~~|~~ee~~|~~ee~~|~~es~~<br>~~ee~~|~~es~~<br>~~ee~~|~~es~~<br>~~ee~~|~~es ~~<br>~~ee~~|~~ee~~<br>~~eee~~|~~eee~~|~~Qe~~<br>~~eee~~|~~Qe~~<br>~~ee~~|~~ee~~|~~Qs~~<br>~~ee~~|~~Qs~~<br>~~eee~~|~~GG~~<br>~~eee~~|~~GG~~<br>~~eee~~|~~GG ~~<br>~~ee~~|~~GO~~<br>~~eeeee~~|~~GO~~<br>~~eee~~|~~GO~~<br>~~eee~~|~~eee~~|~~eee~~|
|USART4|TX<br>~~ee~~<br>~~a~~|6<br>~~a~~|~~a~~|~~a~~||~~a~~|~~ee~~|~~ee~~<br>~~a~~|~~ee~~|~~ee~~<br>~~a~~|~~ee~~<br>~~a~~|~~ee~~<br>~~i~~|~~ee~~<br>~~i~~|~~ee ~~|~~eee~~<br>~~ee~~|~~eee~~<br>~~ee~~|~~eee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee ~~<br>~~ee~~|~~eee~~<br>~~ee~~|~~eee~~<br>~~ee~~|~~eee ~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee eee~~|~~eee ~~<br>~~eee~~|~~eee~~<br>~~eee~~|~~eee~~<br>~~eee~~|~~eee~~<br>~~eee~~|
||RX<br>~~a~~<br>~~a~~<br>~~a~~|~~a ~~<br>~~a ~~<br>~~a~~|6<br> ~~a ~~<br> ~~a ~~|~~a~~<br> ~~a~~|a|~~a~~<br>a|~~a~~ <br>~~ee~~|~~a~~<br> a<br>~~ee~~|~~i ~~<br>~~ee~~|~~a~~<br> ~~i~~<br>~~ee~~|~~a~~<br>~~ee~~|~~i~~<br>~~se~~<br>~~ee~~|~~i~~<br>~~se~~<br>~~ee~~|~~se~~|~~ee~~<br>~~se~~<br>~~eee~~|~~ee~~<br>~~eee~~|~~ee~~<br>~~QQ~~<br>~~eee~~|~~ee~~<br>~~QQ~~<br>~~ee~~|~~ee~~<br>~~QQ~~<br>~~ee~~|~~ee ~~<br>~~GG~~<br>~~ee~~|~~ee~~<br>~~GG~~<br>~~ee~~|~~ee~~<br>~~GG~~<br>~~ee~~|~~ee ~~<br>~~GG~~<br>~~ee~~|~~ee~~<br>~~GG~~<br>~~eee~~|~~GG~~<br>~~eee~~|~~eee~~<br>~~GG~~<br>~~eee eee~~|~~eee~~<br>~~GG~~<br>~~eee~~|~~eee~~<br>~~GG~~<br>~~eee~~|~~eee~~<br>~~eee~~|
||RTS<br>~~a~~|~~a~~|||||~~ee~~|~~ee~~|~~ee~~|~~ee~~|~~ee~~|~~ee~~|~~ee~~||~~eee~~|~~eee~~|6<br>~~eee~~|~~ee~~|~~ee~~|~~ee~~|~~ee~~|~~ee~~|~~ee~~|~~eee~~|~~eee~~|~~eee eee~~|~~eee~~|~~eee~~|~~eee~~|
||CTS<br>~~a ~~<br>~~a~~<br>~~a~~|~~a~~<br>~~a ~~<br>~~a~~|~~a ~~|~~a~~||~~a~~|~~ee~~<br>~~ee~~|~~ee~~<br>a<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~a~~<br>~~ee~~|~~ee~~<br>~~a~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~ <br>~~ae~~|a<br>~~Be~~|~~eee~~<br>~~ee~~<br>~~Be~~|~~eee~~<br>~~ee ~~|~~eee ~~<br> ~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee ~~<br>~~ee~~<br>~~ee~~|~~ee ~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee ~~<br>~~ee ~~<br>~~ee~~|~~eee~~<br> ~~ee~~<br>~~ee~~|6<br>~~eee~~<br>~~ee~~<br>~~ee~~|~~eee eee~~<br>~~ee ~~|~~eee~~<br> ~~ee~~|~~eee~~<br>~~ee~~|~~eee~~<br>~~ee~~|
|USART5|TX<br>~~a~~|~~a~~|||||~~ee~~|~~ee~~|~~ee~~|~~ee~~|~~ee~~|~~ee~~|~~ae~~|~~Be~~|~~Be~~||||~~ee~~|~~ee~~|6<br>~~ee~~|~~ee~~|~~ee~~|~~ee~~|~~ee~~|||||
||RX<br>~~a ~~<br>~~a~~|~~a~~<br>~~a~~|~~a~~|a|~~a~~|~~a~~|~~ee~~|~~ee~~|~~ee~~|~~ee~~|~~ee~~<br>~~ee~~|~~ee ~~<br>~~ee~~|~~ae ~~<br>~~ee~~|~~Be ~~<br>~~ee~~|~~Be~~<br>~~ee~~|~~ee~~|~~ee ~~|~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee ~~|~~ee~~<br> ~~ee~~|6<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee ~~|~~ee~~<br> ~~ee~~|~~ee~~<br>~~ee~~|~~ee ~~|~~ee~~|~~ee~~|~~ee~~|
||CK<br>~~a~~<br>~~a~~|~~a ~~<br>~~a~~|~~a ~~|~~a~~||~~a~~|~~ee~~|a<br>~~ee~~|~~ee~~|~~a~~<br>~~ee~~|~~a~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~ <br>~~ae~~|a<br>~~Be~~|~~ee~~<br>~~Be~~|~~ee ~~|~~ee~~|~~ee~~|~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|6<br>~~ee ~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee ~~|~~ee~~|~~ee~~|~~ee~~|
|LPUART1<br>~~a~~|TX<br>~~a~~|~~a~~||6|||~~ee~~|~~ee~~|~~ee~~|~~ee~~|~~ee~~|~~ee~~|~~ae~~|~~Be~~|~~Be~~|6|||~~ee~~|~~ee~~|~~ee~~|~~ee~~|~~ee~~|~~ee~~|~~ee~~|||4||
||RX<br>~~a ~~<br>~~a~~|~~a~~<br>~~a~~|~~a~~|a|6<br>~~a~~|~~a~~|~~ee~~|~~ee~~|~~ee~~|~~ee~~|~~ee~~<br>~~ee~~|~~ee ~~<br>~~ee~~|~~ae ~~<br>~~ee~~|~~Be ~~<br>~~ee~~|6<br> ~~Be~~<br>~~ee~~|~~ee~~|~~ee ~~|~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee ~~|~~ee~~<br> ~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee ~~|~~ee~~<br> ~~ee~~|~~ee~~<br>~~ee~~|~~ee ~~|~~ee~~|~~ee~~|~~ee~~|
||RTS<br>~~a~~<br>~~a~~|~~a~~ <br>~~a~~|a<br>~~a~~|~~a~~|~~a~~<br>~~a~~|~~a~~<br>~~a~~|~~a~~|a<br>~~a~~|~~i ~~<br>~~a~~|~~i ~~|~~i ~~|~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|4<br>~~ee~~|~~ee~~|||~~eee~~|~~eee~~|~~eee~~|~~eee~~|~~eee~~|7<br>~~eee~~|~~eee~~|
||CTS<br>~~a~~|~~a~~|~~a~~|~~a~~|~~a~~|~~a~~|~~a~~|4<br>~~a~~|~~a~~||||~~ee~~|~~ee~~|~~ee~~|~~ee~~|~~ee~~|~~ee~~|~~ee~~|~~ee~~|||~~eee~~|~~eee~~|~~eee~~|~~eee~~|~~eee~~|~~eee~~|~~eee~~|
|SPI1<br>~~a~~<br>~~Ne~~|MOSI<br>~~a~~<br>~~es~~<br>~~a~~|~~a~~<br>~~a~~|~~a~~<br>~~a~~|~~a~~<br>~~a~~|~~a ~~<br>~~a~~|~~a ~~<br>~~a~~|~~a ~~<br>~~ee~~|~~a ~~<br>~~ee~~<br>~~a~~|0<br> ~~a~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~i~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|0<br>~~ee~~<br>~~rs~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~eee~~<br>~~ee~~|~~ee~~<br>~~eee~~|~~ee~~<br>~~eee~~<br>~~se~~|~~eee~~<br>~~se~~|~~eee~~<br>~~QQ~~|0<br>~~eee~~<br>~~eee~~<br>~~QQ~~|~~eee~~<br>~~eee~~<br>~~QQ~~|~~eee ~~<br>~~eee~~<br>~~QQ~~|~~eee~~<br>~~eee~~|~~eee~~<br>~~eee~~|~~eee~~<br>~~eee~~|~~eee~~<br>~~eee~~|
||MISO<br>~~es~~<br>~~a~~<br>~~a~~|~~a~~<br>~~a~~|~~a~~<br>~~a~~|~~a~~<br>~~a~~|~~a~~|~~a~~<br>~~a~~|~~ee~~<br>~~a~~|0<br>~~ee~~<br>~~a~~<br>~~a~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~i~~<br>~~a~~|~~ee~~<br>~~ee~~<br>~~ee~~|0<br>~~ee~~<br>~~ee~~<br>~~ee~~|~~rs~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee ~~<br>~~ee~~<br>~~ee~~|~~eee~~<br>~~ee~~<br>~~ee~~|~~eee~~<br>~~ee~~|~~eee ~~<br>~~se~~|~~eee~~<br>~~se~~|0<br>~~eee~~<br>~~QQ~~<br>~~ee~~|~~eee ~~<br>~~QQ~~<br>~~ee~~|~~eee~~<br>~~QQ~~<br>~~ee~~|~~eee~~<br>~~QQ~~<br>~~ee~~|~~eee ~~|~~eee~~<br>~~ee~~|~~eee~~<br>~~ee~~|~~eee~~<br>~~ee~~|
||SCK<br>~~a~~<br>~~a~~<br>~~Ne~~|~~a ~~<br>~~a~~|~~a ~~<br>~~a~~|~~a ~~<br>~~a~~|~~a~~|~~a~~<br>~~a~~|0<br>~~a~~|~~a ~~<br>~~a~~|~~ee~~<br>~~ee~~|~~ee ~~<br>~~ee~~|~~i ~~<br>~~a~~|~~ee~~<br>~~ee~~|~~ee ~~<br>~~ee~~|~~rs~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~eee~~|~~ee ~~<br>~~ee~~<br>~~eee~~|~~ee~~<br>~~ee~~<br>~~eee ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~se~~<br>~~ee e~~|0<br>~~se~~<br>~~e~~|~~QQ~~<br>~~ee~~<br>~~e~~~~**e**e~~|~~QQ~~<br>~~ee~~<br>~~e eee~~|~~QQ~~<br>~~ee~~<br>~~eee~~|~~QQ~~<br>~~ee~~<br>~~eee~~|~~eee~~|~~ee~~<br>~~eee~~|~~ee~~<br>~~eee~~|~~ee~~<br>~~eee~~|
||NSS<br>~~a ~~<br>~~ee~~<br>~~Ne~~|~~a ~~<br>~~ee~~|~~a ~~<br>~~ee~~|~~a~~<br>~~ee~~|~~ee~~|0<br>~~a ~~<br>~~ee~~|~~a ~~<br>~~ee~~|~~a ~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee ~~<br>~~ee~~|~~a ~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~eee~~|~~ee~~<br>~~ee~~<br>~~eee~~|0<br>~~ee ~~<br>~~ee~~<br>~~eee ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee e~~|~~ee~~<br>~~e~~|~~ee~~<br>~~ee~~<br>~~e~~~~**e**e~~|~~ee~~<br>~~ee~~<br>~~e eee~~|~~ee~~<br>~~ee~~<br>~~eee~~|~~ee~~<br>~~ee~~<br>~~eee~~|~~ee~~<br>~~eee~~|~~ee~~<br>~~ee~~<br>~~eee~~|~~ee~~<br>~~ee~~<br>~~eee~~|~~ee~~<br>~~ee~~<br>~~eee~~|
|I2C1<br>~~Ne~~<br>~~F~~|SCL<br>~~Ne~~<br>~~ee~~<br>||||~~ee~~<br>|~~ee~~<br>|~~ee~~<br>~~ee~~<br>|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|6<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee eee~~|~~eee~~<br>~~ee~~<br>~~eee~~|~~eee~~<br>~~ee~~<br>~~eee~~|~~eee ee~~<br>~~ee~~<br>~~eee~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee e~~<br>~~ee~~<br>~~ee eee~~|~~e~~<br>~~ee~~<br>~~eee~~|~~e~~~~**e**e~~<br>~~eee~~|~~e eee~~<br>~~eee~~|1<br>~~eee~~<br>~~e~~~~**e**~~|~~eee~~<br>~~**e** eee~~|4<br>~~eee~~<br>~~eee eee~~|~~eee~~<br>~~eee~~|~~eee~~<br>~~eee~~|~~eee~~<br>~~eee~~|
||SDA<br>~~Ne~~<br>~~ee~~<br>||||~~ee~~<br>|~~ee~~<br>|~~ee~~<br>~~ee~~<br>|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|6<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee eee~~|~~eee~~<br>~~ee~~<br>~~eee~~|~~eee~~<br>~~ee~~<br>~~eee~~|~~eee ee~~<br>~~ee~~<br>~~eee~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee e~~<br>~~ee~~<br>~~ee eee~~|~~e~~<br>~~ee~~<br>~~eee~~|~~e~~~~**e**e~~<br>~~eee~~|~~e eee~~<br>~~eee~~|~~eee~~<br>~~e~~~~**e**~~|1<br>~~eee~~<br>~~**e** eee~~|~~eee ~~<br>~~eee eee~~|4<br> ~~eee~~<br>~~eee~~|~~eee~~<br>~~eee~~|~~eee~~<br>~~eee~~|
|I2C2<br>~~F ~~|SCL<br>~~ee~~<br>~~-—,~~|~~-—,|~~|~~|~~|~~|~~|~~ee~~<br>~~||~~|~~ee~~<br>~~||~~|~~ee~~<br>~~ee~~<br>~~||~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~|}~~|~~ee~~<br>~~ee~~<br>~~|}~~|~~ee~~<br>~~ee~~<br>~~|}~~|~~ee~~<br>~~ee~~<br>|~~ee~~<br>~~ee~~<br>~~J~~|~~ee~~<br>~~ee eee~~<br>~~J~~|~~ee~~<br>~~eee~~<br>~~J~~|~~ee~~<br>~~eee~~|~~ee~~<br>~~eee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee eee~~|~~ee~~<br>~~eee~~|~~eee~~|~~eee~~|~~e~~~~**e**~~|~~**e** eee~~|~~eee eee~~|~~eee~~|6<br>~~eee~~|~~eee~~|
||SDA<br> ~~-—,~~<br>~~a~~|~~-—,|~~<br>~~a~~|~~|~~<br>~~a~~|~~|~~<br>~~a a~~|~~||~~<br>~~a~~|~~||~~<br>~~a~~|~~ee~~<br>~~||~~|~~ee~~<br>~~a ~~|~~ee~~<br>~~|}~~<br> ~~ee~~|~~ee~~<br>~~|}~~<br>~~ee~~|~~ee~~<br>~~|}~~<br>~~ee~~|~~ee~~<br><br>~~ee~~|~~ee~~<br>~~J~~<br>~~ee~~|~~ee eee~~<br>~~J~~<br>~~ee~~|~~eee~~<br>~~J~~<br>~~ee ~~|~~eee~~<br> ~~ee~~|~~eee ~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee eee~~<br>~~ee~~|~~eee~~|~~eee~~<br>~~Q~~|~~eee ~~<br>~~Q~~|~~e~~~~**e**~~<br>~~Q~~|~~**e** eee~~|~~eee eee~~|~~eee~~|~~eee~~|5<br>~~eee~~|
|I2C3<br> <br>~~FP~~<br>~~Ltt~~|SCL<br> ~~-—,~~<br>~~KH]~~<br>~~Ltt~~|~~-—, | ~~<br>~~KH]~~<br>~~7]~~<br>~~Ltt|~~|~~|~~<br>~~7]fF)~~<br>~~||~~|~~| ~~<br>~~fF)~~<br>~~|~~<br>~~fj~~|~~||~~<br>~~fF)4].~~<br>~~fj~~<br>~~|~~|~~||~~<br>~~4].~~<br>~~||~~|~~||~~<br>~~4].~~<br>~~|~~<br>~~tf~~|~~4].~~<br>~~tf|~~|~~|}~~<br>~~}~~<br>~~|~~<br>~~|~~|7<br>~~|}~~<br>~~ttt~~<br>~~|~~<br>~~ft~~|~~|} ~~<br>~~ttt~~<br>~~ft~~<br>~~ft~~|<br>~~ttt~~<br>~~ft~~<br>~~ft~~|~~J~~<br>~~ttt yt~~<br>~~ft~~<br>~~ft~~|~~J~~<br>~~yt~~<br>~~fttt~~|~~J~~<br>~~ytfee~~<br>~~tt~~|~~fee~~<br>~~tt~~|~~feetee~~|~~tee~~|~~tee~~|~~tee~~|~~ye~~|~~ye~~|~~ye~~|~~ye~~|~~ye~~|||||
||SDA<br>~~KH]~~<br>~~Ltt~~<br>~~a~~|~~KH]~~<br>~~7]~~<br>~~Ltt|~~|~~7]fF)~~<br>~~||~~|~~fF)~~<br>~~|~~<br>~~fj~~|~~fF)4].~~<br>~~fj~~<br>~~|~~|~~4].~~<br>~~||~~<br>~~ee~~|~~4].~~<br>~~|~~<br>~~tf~~<br>~~ee~~|~~4].~~<br>~~tf|~~<br>~~ee~~|~~}~~<br>~~|~~<br>~~|~~<br>~~ee~~|~~ttt~~<br>~~|~~<br>~~ft~~<br>~~ee~~|~~ttt~~<br>~~ft~~<br>~~ft~~<br>~~ee~~|~~ttt~~<br>~~ft~~<br>~~ft~~<br>~~ee~~|~~ttt yt~~<br>~~ft~~<br>~~ft~~<br>~~ee~~|~~yt~~<br>~~fttt~~<br>~~Be~~|~~ytfee~~<br>~~tt~~<br>~~ee~~|~~fee~~<br>~~tt~~<br>~~ee~~|~~feetee~~<br>~~ee~~|~~tee~~<br>~~ee~~|~~tee~~<br>~~ee~~|~~tee~~<br>~~ee~~|~~ye~~|7<br>~~ye~~<br>~~GG~~|~~ye~~<br>~~GG~~|~~ye~~<br>~~GG~~|~~ye~~<br>~~GG~~|~~GG~~||||
|TIM2<br>~~FP ~~<br>~~Ltt~~|Ch1<br> ~~KH]~~<br>~~Ltt~~<br>~~a~~|2<br>~~KH]~~<br>~~7]~~<br>~~Ltt |~~|~~7] fF)~~<br>~~| |~~|~~fF)~~<br>~~|~~<br>~~fj~~|~~fF) 4].~~<br>~~fj~~<br>~~|~~|~~4].~~<br>~~| |~~<br>~~ee~~|5<br>~~4].~~<br>~~|~~<br>~~tf~~<br>~~ee~~|~~4].~~<br>~~tf |~~<br>~~ee~~|~~} ~~<br>~~|~~<br>~~|~~<br>~~ee~~|~~ttt~~<br>~~|~~<br>~~ft~~<br>~~ee~~|~~ttt~~<br>~~ft~~<br>~~ft~~<br>~~ee~~|~~ttt~~<br>~~ft~~<br>~~ft~~<br>~~ee~~|~~ttt yt~~<br>~~ft~~<br>~~ft~~<br>~~ee~~|~~yt~~<br>~~ft tt~~<br>~~Be~~|~~yt fee~~<br>~~tt~~<br>~~ee~~|~~fee~~<br>~~tt~~<br>~~ee~~|5<br>~~fee tee~~<br>~~ee~~|~~tee~~<br>~~ee~~|~~tee~~<br>~~ee~~|~~tee ~~<br>~~ee~~|~~ye~~|~~ye~~<br>~~GG~~|~~ye~~<br>~~GG~~|~~ye~~<br>~~GG~~|~~ye~~<br>~~GG~~|~~GG~~||||
||Ch2<br>~~a~~<br>~~a~~ <br>~~a~~|a <br>~~a~~|2<br> ~~a ~~<br>~~a~~|~~a~~<br>~~a~~|~~a~~|~~ee~~<br>a<br>~~a~~|~~ee~~<br>~~a~~<br>~~a~~|~~ee~~<br>~~a~~<br>~~a~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee ~~<br>~~ee~~|~~ee~~<br> ~~i ~~<br>~~i~~|~~ee ~~<br> ~~ee~~<br>~~ee~~|~~ee ~~<br>~~ee~~<br>~~ee~~|~~Be ~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee ~~<br>~~ee~~|~~ee ~~<br> ~~ee~~<br>~~fe~~|~~ee ~~<br>~~ee~~<br>~~fe~~|~~ee~~|~~ee~~<br>~~ee~~<br>~~eG~~|2<br>~~ee~~<br>~~eG~~|~~GG~~<br>~~ee~~<br>~~eG~~|~~GG~~<br>~~sO~~|~~GG~~<br>~~ee~~<br>~~sO~~|~~GG~~<br>~~ee~~<br>~~GO~~|~~GG~~<br>~~ee~~<br>~~GO~~|~~ee~~<br>~~GO~~|~~ee~~|~~ee~~|
||Ch3<br>~~a~~<br>~~a~~|~~a~~|~~a~~|2<br>~~a~~|~~a~~|~~a~~<br>~~ee~~|~~a~~<br>~~ee~~|~~a~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~i~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~re~~|~~ee~~<br>~~re~~|~~ee~~<br>~~es~~|~~fe~~<br>~~sd~~|~~fe~~<br>~~sd~~||~~eG~~|~~eG~~<br>~~GG~~|~~eG~~<br>~~GG~~|~~sO~~<br>~~GG~~|~~sO~~<br>~~GG~~|~~GO~~<br>~~GOGO~~|~~GO~~<br>~~GOGO~~|~~GO~~<br>~~GOGO~~|2<br>~~GOGO~~||
||Ch4<br>~~a~~<br>~~a~~<br>~~a~~|~~a ~~|~~a ~~|~~a~~|2<br>~~a~~|~~a~~<br>~~ee~~|~~a~~<br>~~ee~~|~~a ~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee ~~<br>~~ee~~|~~i~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee ~~<br>~~re~~|~~ee~~<br>~~re~~|~~ee ~~<br>~~es~~|~~fe~~<br>~~sd~~|~~fe~~<br>~~sd~~<br>~~ee~~|~~ee~~|~~eG~~<br>~~ee~~|~~eG~~<br>~~GG~~<br>~~eee~~|~~eG~~<br>~~GG~~<br>~~eee~~|~~sO~~<br>~~GG~~<br>~~eee~~|~~sO ~~<br>~~GG~~<br>~~eee~~|~~GO~~<br>~~GOGO~~<br>~~eee~~|~~GO~~<br>~~GOGO~~<br>~~eee~~|~~GO~~<br>~~GOGO~~<br>~~eee~~|~~GOGO~~<br>~~eee~~|~~eee~~|
||ETR<br>~~a~~<br>~~ee~~<br>~~a~~<br>~~a~~|5<br>~~ee~~|~~ee~~|~~ee~~|~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|2<br>~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee ~~<br>~~ee~~<br>~~ee~~|~~ee ~~<br>~~ee~~<br>~~ee~~|~~re~~<br>~~ee~~<br>~~Be~~|~~re ~~<br>~~ee~~<br>~~Be~~|~~es ~~<br>~~ee~~|2<br> ~~sd~~<br>~~ee~~<br>~~ee~~|~~sd~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~GG~~<br>~~ee~~<br>~~eee~~<br>~~e~~|~~GG~~<br>~~ee~~<br>~~eee~~<br>~~e~~~~**e** ee~~|~~GG~~<br>~~ee~~<br>~~eee~~<br>~~ee~~|~~GG ~~<br>~~ee~~<br>~~eee~~<br>~~ee~~|~~GOGO~~<br>~~ee~~<br>~~eee~~<br>~~ee~~|~~GOGO~~<br>~~ee~~<br>~~eee~~<br>~~ee~~|~~GOGO~~<br>~~ee~~<br>~~eee~~<br>~~ee~~|~~GOGO~~<br>~~ee~~<br>~~eee~~<br>~~ee~~|~~ee~~<br>~~eee~~<br>~~ee~~|
|TIM3|Ch1<br>~~a~~<br>~~a~~|||||~~ee~~|~~ee~~|2<br>~~ee~~|~~ee~~|~~ee~~|~~ee~~|~~ee~~|~~ee~~|~~Be~~|~~Be~~||~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee ~~<br>~~ee~~|~~eee~~<br>~~e~~|2<br>~~eee~~<br>~~e~~~~**e** ee~~|~~eee ~~<br>~~ee~~|~~eee~~<br>~~ee~~|~~eee~~<br>~~ee~~|~~eee ~~<br>~~ee~~|~~eee~~<br>~~ee~~|~~eee~~<br>~~ee~~|~~eee~~<br>~~ee~~|
||Ch2<br>~~a~~<br>~~a~~|~~a~~<br>~~a~~|~~a~~<br>~~a~~|~~a~~<br>~~a~~||~~ee~~<br>~~a~~<br>~~a~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~a~~|2<br>~~ee~~<br>~~ee~~<br>~~i~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ie~~|~~Be~~<br>~~i~~|~~Be~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>|~~ee~~<br>~~e~~<br>~~ee~~|~~e~~<br>~~e~~<br>~~ee~~|~~e~~~~**e** ee~~<br>~~e~~<br>~~ee~~|4<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~eee~~|~~ee~~<br>~~eee~~|~~ee~~<br>~~eee~~|
||Ch3<br>~~a~~<br>~~a~~|~~a ~~<br>~~a~~|~~a ~~<br>~~a~~|~~a~~<br>~~a~~||~~ee~~<br>~~a ~~<br>~~a~~|~~ee~~<br> ~~ee~~|~~ee~~<br>~~ee~~<br>~~a~~|~~ee~~<br>~~ee~~<br>~~i~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee ~~<br>~~ee~~<br>~~ie~~|~~Be ~~<br>~~i~~|~~Be~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee ~~<br>~~ee~~|2<br>~~ee~~<br> ~~ee~~<br>~~ee~~|~~ee~~<br>~~ee ~~<br>|~~ee ~~<br> ~~e~~<br>~~ee~~|~~e~~<br>~~e~~<br>~~ee~~|~~e~~~~**e** ee~~<br>~~e~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee ~~|~~ee~~<br> ~~eee~~|~~ee~~<br>~~eee~~|~~ee~~<br>~~eee~~|
||Ch4<br>~~a ~~<br>~~a~~<br>~~a~~|~~a ~~<br>~~a~~|~~a ~~<br>~~a ~~|~~a~~<br> ~~a~~||~~a~~<br>a <br>~~se~~|~~a~~ <br>~~se~~|~~a ~~<br> a<br>~~se~~|~~i ~~<br>a<br>~~se~~|~~ee~~<br>~~a~~<br>~~se~~|~~ee~~<br>~~a~~<br>~~se~~|~~ee ~~<br>~~i ~~<br>~~ee~~|~~ie ~~<br> ~~ee~~<br>~~ee~~|~~i ~~<br>~~ee~~<br>~~ie~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee ~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee ~~<br>~~ee~~|2<br>|~~ee~~<br>~~GG~~|~~ee~~<br>~~GG~~|~~ee~~<br>~~GG~~|~~ee~~<br>~~GG~~|~~ee~~<br>~~GG~~|~~ee~~<br>~~GG~~|~~GG~~||||
|TIM21|Ch1<br>~~a~~|||0||~~se~~|~~se~~|~~se~~|~~se~~|~~se~~|~~se~~|~~ee~~|~~ee~~|~~ie~~|~~ee~~|~~ee~~||||~~GG~~|~~GG~~|~~GG~~|~~GG~~|~~GG~~|~~GG~~|~~GG~~||||
||Ch2<br>~~a~~<br>~~a~~ <br>~~a~~|a<br>~~a~~|~~a ~~<br>|~~a~~<br>|0<br>|~~se~~<br>~~a~~<br>|~~se~~|~~se~~<br>a|~~se~~<br>~~i ~~|~~se~~<br> ~~ee~~|~~se ~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ie ~~|~~ee~~|~~ee~~<br>~~ee~~|~~ee~~|~~ee~~|~~ee~~|~~GG~~<br>~~ee~~|~~GG~~<br>~~ee~~<br>~~eee~~|~~GG~~<br>~~ee~~<br>~~eee~~|~~GG~~<br>~~eee~~|~~GG~~<br>~~ee~~<br>~~eee~~|~~GG~~<br>~~ee~~<br>~~eee~~|~~GG~~<br>~~ee~~<br>~~eee~~|~~ee~~<br>~~eee~~|~~eee~~|~~eee~~|
||ETR<br>~~ee~~<br>~~a~~|~~ee~~<br>~~a~~|5<br>~~ee~~<br>|~~ee~~<br>|~~ee~~<br>|~~ee~~<br>|~~ee~~|~~ee~~|~~ee~~|~~ee~~|~~ee~~|~~ee~~|~~ee~~|~~ee~~|~~ee~~|~~ee~~|~~ee~~|~~ee~~|~~ee~~|~~ee~~|~~ee~~<br>~~eee~~|~~ee~~<br>~~eee~~|~~ee~~<br>~~eee~~|~~ee~~<br>~~eee~~|~~ee~~<br>~~eee~~|~~ee~~<br>~~eee~~|~~ee~~<br>~~eee~~|~~ee~~<br>~~eee~~|~~ee~~<br>~~eee~~|
|TIM22|Ch1<br>~~a~~<br>~~a~~|~~a~~<br>~~a~~|~~a~~<br>~~a~~|~~a~~|~~a~~|~~a~~<br>~~a~~|~~a~~|5<br>~~a~~|~~ee~~|~~ee~~|~~ee~~<br>~~a~~|~~ee~~<br>~~i~~|~~ee~~<br>~~i~~|~~ee~~<br>~~a~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~|~~eee~~<br>~~ee~~<br>~~ee~~|4<br>~~eee~~<br>~~ee~~<br>~~ee~~|~~eee~~<br>~~ee~~<br>~~ee~~|~~eee~~<br>~~ee~~<br>~~ee~~|~~eee~~<br>~~eee~~|~~eee~~<br>~~eee~~<br>~~eee~~|~~eee~~<br>~~eee~~<br>~~eee~~|~~eee~~<br>~~eee~~<br>~~ee~~|~~eee~~<br>~~eee~~<br>~~ee~~|
||Ch2<br>~~a~~<br>~~a~~<br>~~es~~|~~a ~~<br>~~a ~~|~~a ~~<br> ~~a~~|<br>~~a~~|~~a~~|~~a~~<br>~~a~~|~~a~~|~~a~~|5<br>~~ee~~|~~ee~~|~~ee~~<br>~~a~~|~~ee~~<br>~~i~~|~~ee~~<br>~~i~~|~~ee~~<br>~~a~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee ~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~eee~~<br>~~ee ~~<br>~~ee~~<br>~~ee~~|~~eee~~<br> ~~ee~~<br>~~ee~~<br>~~ee~~|4<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>~~ee eee~~|~~eee ~~<br>~~ee~~<br>~~ee~~<br>~~eee~~|~~eee~~<br>~~eee~~<br>~~eee~~|~~eee~~<br>~~eee~~<br>~~eee~~<br>~~eee eee~~|~~eee ~~<br>~~eee~~<br>~~eee~~<br>~~eee~~|~~eee~~<br>~~eee~~<br>~~ee~~<br>~~eee~~|~~eee~~<br>~~eee~~<br>~~ee~~<br>~~eee~~|
||ETR<br><br>~~ee~~<br>~~es~~|<br>~~ee~~|~~a ~~<br>~~ee~~|~~a~~<br>~~ee~~|~~ee~~|5<br>~~a~~<br>~~ee~~|~~a~~<br>~~ee~~|~~a ~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee ~~<br>~~ee~~|~~a ~~<br>~~ee~~|~~i ~~<br>~~ee~~|~~i ~~<br>~~ee~~|~~a ~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee ~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee ~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee ~~<br>~~ee~~<br>~~ee eee~~|~~ee~~<br>~~ee~~<br>~~eee~~|~~eee~~<br>~~ee~~<br>~~eee~~|~~eee~~<br>~~ee~~<br>~~eee eee~~|~~eee ~~<br>~~ee~~<br>~~eee~~|~~ee~~<br>~~ee~~<br>~~eee~~|~~ee~~<br>~~ee~~<br>~~eee~~|
|LPTIM1<br>~~F~~|IN1<br>~~es~~<br>~~a~~<br>~~a~~|~~a~~|~~a~~|~~a~~|~~a~~|~~a~~|~~ee~~<br>~~a~~|~~ee~~<br>~~a~~|~~ee~~<br>~~ie~~|~~ee~~<br>~~ie i~~|~~ee~~<br>~~i~~|~~ee~~<br>~~es~~|~~ee~~<br>~~es~~|~~es~~|~~eee~~<br>~~ee~~|~~eee~~<br>~~ee~~|~~eee~~<br>~~fe~~|~~ee~~<br>~~eee~~<br>~~fe~~|~~ee~~<br>~~eee~~|~~ee~~<br>~~eee~~<br>~~eG~~|~~ee~~<br>~~eee~~<br>~~eG~~|~~ee~~<br>~~eee~~<br>~~eG~~|2<br>~~ee eee~~<br>~~eee~~<br>~~QO~~|~~eee~~<br>~~eee~~<br>~~QO~~|~~eee~~<br>~~eee~~<br>~~QO~~|~~eee eee~~<br>~~eee~~<br>~~QO~~|~~eee~~<br>~~eee~~<br>~~QO~~|~~eee~~<br>~~eee~~|~~eee~~<br>~~eee~~|
||IN2<br>~~es~~<br>~~a~~<br>~~a~~|~~a~~|~~a~~|~~a~~|~~a~~|~~a~~|~~ee~~<br>~~a~~<br>~~ee~~|~~ee~~<br>~~a~~<br>~~ee~~|~~ee~~<br>~~ie~~<br>~~ee~~|~~ee~~<br>~~ie i~~<br>~~ee~~|~~ee~~<br>~~i~~<br>~~ee~~|~~ee~~<br>~~es~~<br>~~ee~~|~~ee~~<br>~~es~~<br>~~ee~~|~~es~~<br>~~G~~~~**e**~~|~~eee~~<br>~~ee~~<br>~~Gee~~|~~eee~~<br>~~ee~~<br>~~Gee~~|~~eee ~~<br>~~fe~~<br>~~Qe~~|~~ee~~<br> ~~eee~~<br>~~fe~~<br>~~QO~~|~~ee~~<br>~~eee~~<br>~~QO~~|~~ee~~<br>~~eee ~~<br>~~eG~~|~~ee~~<br> ~~eee~~<br>~~eG~~|~~ee~~<br>~~eee~~<br>~~eG~~<br>~~GG~~|~~ee eee~~<br>~~eee ~~<br>~~QO~~<br>~~GG~~|~~eee~~<br> ~~eee~~<br>~~QO~~<br>~~GG~~|2<br>~~eee~~<br>~~eee~~<br>~~QO~~<br>~~GG~~|~~eee eee~~<br>~~eee ~~<br>~~QO~~<br>~~GG~~|~~eee~~<br> ~~eee~~<br>~~QO~~<br>~~QO~~|~~eee~~<br>~~eee~~<br>~~QO~~|~~eee~~<br>~~eee~~|
||OUT<br><br>~~a~~<br>|<br>|~~a ~~<br>|~~a~~<br>|~~a ~~<br>|~~a ~~<br>|~~a~~<br>~~ee~~<br>|~~a~~<br>~~ee~~<br>|~~ie~~<br>~~ee~~<br>|~~ie i~~<br>~~ee~~<br>|~~i~~<br>~~ee~~<br>|~~es~~<br>~~ee~~<br>|~~es~~<br>~~ee~~<br>|~~es ~~<br>~~G~~~~**e**~~<br>|~~ee~~<br>~~Gee~~<br>|~~ee ~~<br>~~Gee~~<br>|~~fe~~<br>~~Qe~~<br>|~~fe~~<br>~~QO~~<br>~~eee~~<br>|~~QO~~<br>~~eee~~<br>|2<br>~~eG~~<br>~~eee~~<br>|~~eG~~<br>~~eee~~|~~eG ~~<br>~~GG~~<br>~~eee~~|~~QO~~<br>~~GG~~<br>~~eee~~|~~QO~~<br>~~GG~~<br>~~eee~~|~~QO~~<br>~~GG~~<br>~~eee~~|~~QO~~<br>~~GG~~<br>~~eee eee~~|~~QO~~<br>~~QO~~<br>~~eee~~|~~QO~~<br>~~eee~~|~~eee~~|
||ETR<br>~~e~~<br>|~~e~~<br>|~~e~~<br>|~~e~~<br>|~~e~~<br>|~~e~~<br>|~~ee~~<br>~~e~~<br>|~~ee~~<br>~~e~~<br>|~~ee~~<br>~~e~~<br>|~~ee~~<br>~~e~~<br>|~~ee~~<br>~~e~~<br>|~~ee~~<br>~~e~~<br>|~~ee~~<br>~~e~~<br>|~~G~~~~**e**~~<br>~~e~~<br>|~~Gee~~<br>|~~Gee ~~<br>|~~Qe~~<br>|~~QO~~<br>~~eee~~<br>|~~QO~~<br>~~eee~~<br>|~~eee~~<br>|~~eee~~|~~GG~~<br>~~eee~~|~~GG~~<br>~~eee~~|2<br>~~GG ~~<br>~~eee~~|~~GG~~<br>~~eee~~|~~GG ~~<br>~~eee eee~~|~~QO~~<br>~~eee~~|~~QO~~<br>~~eee~~|~~eee~~|
|COMP<br>1<br>~~F~~<br>~~PF~~|IN<br>~~-—_->-+--}-}--~~<br>~~**a**~~<br>|M<br>~~-—_->-+--}-}--~~<br><br>|P<br>~~-—_->-+--}-}--~~<br>|~~-—_->-+--}-}--~~<br>~~a~~|P*<br>~~-—_->-+--}-}--~~<br>~~a~~|M<br>~~-—_->-+--}-}--~~<br>~~a~~|M<br>~~-—_->-+--}-}--~~<br>~~a~~|~~-—_->-+--}-}--~~<br>~~a~~|||~~J~~<br>~~ee~~|~~J~~<br>~~ee~~|~~J~~<br>~~ee~~|~~J~~<br>~~ee De~~|~~J~~<br>~~De~~|~~J~~|~~J~~|~~eee~~<br>~~J~~|~~eee~~<br>~~J~~<br>~~eee~~|~~eee~~<br>~~J~~<br>~~eee~~|~~eee~~<br>~~eee~~|P*<br>~~eee~~<br>~~eee~~|P*<br>~~eee~~<br>~~eee~~|P*<br>~~eee~~<br>~~eee~~|P*<br>~~eee~~<br>~~eee~~|~~eee eee~~<br>~~eee eee~~|~~eee~~<br>~~eee~~|~~eee~~<br>~~eee~~|~~eee~~<br>~~eee~~|
||OUT<br>~~-—_->-+--}-}--~~<br>~~**a**~~<br>|7<br>~~-—_->-+--}-}--~~<br><br>|~~-—_->-+--}-}--~~<br>|~~-—_->-+--}-}--~~<br>~~a~~|~~-—_->-+--}-}--~~<br>~~a~~|~~-—_->-+--}-}--~~<br>~~a~~|~~-—_->-+--}-}--~~<br>~~a~~|7<br>~~-—_->-+--}-}--~~<br>~~a~~|||~~J~~<br>~~ee~~|~~J~~<br>~~ee~~|7<br>~~J~~<br>~~ee~~|~~J~~<br>~~ee De~~|~~J~~<br>~~De~~|~~J~~|~~J~~|~~eee~~<br>~~J~~|~~eee~~<br>~~J~~<br>~~eee~~|~~eee~~<br>~~J~~<br>~~eee~~|~~eee~~<br>~~eee~~|~~eee~~<br>~~eee~~|~~eee~~<br>~~eee~~|~~eee~~<br>~~eee~~|~~eee~~<br>~~eee~~|~~eee eee~~<br>~~eee eee~~|~~eee~~<br>~~eee~~|~~eee~~<br>~~eee~~|~~eee~~<br>~~eee~~|
|COMP<br>2<br>~~F ~~<br>~~PF~~<br>~~a~~|IN<br> ~~-—_->-+--}-}--~~<br>~~**a**~~<br>~~KH]~~|~~-—_->-+--}-}--~~<br><br>~~KH]~~|~~-—_->-+--}-}--~~<br><br>~~}~~<br>~~a~~|M<br>~~-—_->-+--}-}--~~<br>~~a~~<br>~~>]~~<br>~~a~~|P<br>~~-—_->-+--}-}--~~<br>~~a~~<br>~~>]~~|M<br>~~-—_->-+--}-}--~~<br>~~a~~<br>~~>]])-~~<br>~~a~~|M<br>~~-—_->-+--}-}--~~<br>~~a~~<br>~~])-~~<br>~~a~~|~~-—_->-+--}-}-- ~~<br>~~a~~<br>~~])-~~<br>~~>.~~<br>~~a~~|<br>~~>.4}~~<br>~~a~~|<br>~~4}~~<br>~~>~~<br>~~ee~~|~~J~~<br>~~ee~~<br>~~444)~~<br>~~a~~|~~J~~<br>~~ee~~<br>~~444)~~<br>~~ee~~|~~J~~<br>~~ee~~<br>~~444)~~<br>~~ee~~|~~J~~<br>~~ee De~~<br>~~444)~~<br>~~ee~~|~~J~~<br>~~De~~<br>~~444)fe~~<br>~~ee~~|~~J~~<br>~~fe~~<br>~~ee~~|~~J~~<br>~~fete~~<br>~~ee~~|~~eee~~<br>~~J~~<br>~~te~~<br>~~ee~~|~~eee~~<br>~~J~~<br>~~eee~~<br>~~te~~<br>~~ee~~|~~eee ~~<br>~~J~~<br>~~eee~~|M<br> ~~eee~~<br>~~eee~~|P<br>~~eee~~<br>~~eee~~|P<br>~~eee ~~<br>~~eee~~|P<br> ~~eee~~<br>~~eee~~|P<br>~~eee~~<br>~~eee~~|~~eee eee~~<br>~~eee eee~~|~~eee~~<br>~~eee~~|~~eee~~<br>~~eee~~|~~eee~~<br>~~eee~~|
||OUT<br>~~**a**~~<br>~~KH]~~<br>~~a~~|~~KH]~~<br>~~a~~|~~}~~<br>~~a~~<br>|7<br>~~a~~<br>~~>]~~<br>~~a~~|~~a~~<br>~~>]~~|~~a~~<br>~~>]])-~~<br>~~a~~|~~a~~<br>~~])-~~<br>~~a~~|~~a~~<br>~~])-~~<br>~~>.~~<br>~~a~~|7<br>~~>.4}~~<br>~~a~~|~~4}~~<br>~~>~~<br>~~ee~~|~~ee~~<br>~~444)~~<br>~~a~~|~~ee~~<br>~~444)~~<br>~~ee~~|~~ee~~<br>~~444)~~<br>~~ee~~|7<br>~~ee De~~<br>~~444)~~<br>~~ee~~|~~De~~<br>~~444)fe~~<br>~~ee~~|~~fe~~<br>~~ee~~|~~fete~~<br>~~ee~~|~~te~~<br>~~ee~~|~~eee~~<br>~~te~~<br>~~ee~~|~~eee~~|~~eee~~|~~eee~~|~~eee~~|~~eee~~|~~eee~~<br>~~**e**ee~~|~~eee eee~~<br>~~ee eee~~|~~eee~~<br>~~eee~~|~~eee~~<br>~~eee~~|~~eee~~<br>~~eee~~|
|ADC_IN<br>~~**a** ~~<br>~~PF KH]~~<br>~~a~~<br>~~a~~||0<br> <br>~~KH]~~<br>~~a~~<br>~~a~~|1<br> <br>~~} ~~<br>~~a ~~<br>~~a~~<br>|2<br> ~~a~~<br> ~~>]~~<br> ~~a~~<br>~~ee~~|3<br>~~a~~<br>~~>]~~<br>~~ee~~|4<br>~~a~~<br>~~>] ])-~~<br>~~a ~~<br>~~ee~~|5<br>~~a~~<br>~~])-~~<br> ~~a ~~<br>~~ee~~|6<br>~~a~~<br>~~])-~~<br>~~>.~~<br> ~~a ~~<br>~~ee~~|7<br>~~>. 4}~~<br> ~~a ~~<br>~~ee~~|~~4}~~<br>~~> ~~<br> ~~ee ~~<br>~~ee~~|~~ee~~<br> ~~444)~~<br> ~~a ~~<br>~~ee~~|~~ee ~~<br>~~444)~~<br> ~~ee~~<br>~~ee~~|~~ee~~<br>~~444)~~<br>~~ee~~<br>~~ee~~|~~ee De~~<br>~~444)~~<br>~~ee~~<br>~~ee~~|~~De~~<br>~~444) fe~~<br>~~ee~~<br>~~ee~~|~~fe~~<br>~~ee ~~<br>~~ee~~|~~fe te~~<br> ~~ee~~<br>~~ee~~|8<br>~~te~~<br>~~ee~~<br>~~ee~~|9<br>~~eee~~<br>~~te~~<br>~~ee~~<br>~~ee~~|~~eee~~<br>~~ee~~|~~eee~~<br>~~ee~~|~~eee~~<br>~~ee~~|~~eee~~<br>~~ee~~|~~eee ~~<br>~~ee~~|~~eee~~<br>~~ee~~<br>~~**e**ee~~|~~eee eee~~<br>~~ee~~<br>~~ee eee~~|~~eee~~<br>~~ee~~<br>~~eee~~|~~eee~~<br>~~ee~~<br>~~eee~~|~~eee~~<br>~~ee~~<br>~~eee~~|
|EVENTOUT<br>~~a~~<br>~~a~~||~~a ~~<br>~~a~~|0<br> ~~a~~<br>~~a~~|~~a~~<br>|~~Be~~|~~Be~~|~~Be~~|6<br>~~ee~~<br>~~Be~~|6<br>~~ee~~<br>~~Be~~|3<br>~~ee~~<br>~~Be~~|~~ee~~<br>~~Be~~|~~ee~~<br>~~ee~~|2<br>~~ee~~<br>~~ee~~|2<br>~~ee i~~<br>~~ee~~|~~i~~<br>~~ee~~|~~ee~~<br>~~ee~~|3<br>~~ee~~<br>~~ee~~|0<br>~~Ge~~|~~ee~~<br>~~Ge~~|~~ee~~|4<br>~~ee~~|~~ee~~|~~ee~~<br>~~GGG~~|~~GGG~~|~~**e**ee~~<br>~~GGG~~|~~ee eee~~<br>~~GGG~~|2<br>~~eee~~<br>~~e~~<br>~~QO~~|~~eee~~<br>~~e~~<br>~~QO~~|~~eee~~<br>~~e~~|
|MCO_OUT<br>~~a~~<br>~~F-—~~||~~a~~<br>~~7~~|~~a~~<br>~~fo~~|~~fo~~|~~Be~~<br>~~fo fp}~~|~~Be~~<br>~~fp}~~|~~Be~~<br>~~fp}~~|~~Be~~<br>~~fp}~~|~~Be~~<br>~~fp}~~|0<br>~~Be~~<br>~~fp}~~|0<br>~~Be~~<br>~~fp}~~|~~ee~~<br>~~fp}~~|~~ee~~<br>~~fp}~~|~~ee~~<br>~~fp}~~|~~ee~~<br>~~fp}~~|~~ee~~<br>~~fp}~~|~~ee~~<br>~~fp}~~|~~Ge~~<br>~~fp}~~|~~Ge~~||||~~GGG~~|~~GGG~~|~~GGG~~|~~GGG~~|~~QO~~|~~QO~~||
|SWD<br>~~a~~<br>~~F~~|IO<br>~~a ~~<br>~~-—~~|~~a ~~<br>~~7~~|~~a ~~<br>~~fo~~|<br>~~fo~~|~~Be~~<br>~~fo fp}~~|~~Be~~<br>~~fp}~~|~~Be~~<br>~~fp}~~|~~Be~~<br>~~fp}~~|~~Be~~<br>~~fp}~~|~~Be~~<br>~~fp}~~|~~Be ~~<br>~~fp}~~|~~ee~~<br>~~fp}~~|~~ee ~~<br>~~fp}~~|~~ee~~<br>~~fp}~~|0<br>~~ee ~~<br>~~fp}~~|~~ee ~~<br>~~fp}~~|~~ee~~<br>~~fp}~~|~~Ge~~<br>~~fp}~~|~~Ge~~||||~~GGG~~|~~GGG~~|~~GGG~~|~~GGG ~~|~~QO~~|~~QO~~||
||CLK<br>~~-—~~<br>~~a~~|~~7~~<br>~~a~~|~~fo~~|~~fo~~<br>~~a~~|~~fo fp}~~<br>~~a~~|~~fp}~~|~~fp}~~|~~fp}~~<br>~~ee~~|~~fp}~~<br>~~ee~~|~~fp}~~<br>~~ee~~|~~fp}~~<br>~~ee ~~|~~fp}~~<br> ~~eG~~|~~fp}~~<br>~~eG~~|~~fp}~~<br>~~eG~~|~~fp}~~<br>~~eG~~|0<br>~~fp}~~<br>~~eG~~|~~fp}~~<br>~~GG~~|~~fp}~~<br>~~GG~~|~~GG~~|~~GG~~|~~GG~~|~~GG~~|~~GG~~|~~GG~~|~~GG~~|~~GG~~|~~GG~~|~~GG~~||
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## 3. Absolute Maximum Ratings
The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the device. Functional operation of the ZWIR4532 at absolute maximum ratings is not implied. Exposure to absolute maximum rating conditions might affect device reliability.
## Table 3. Absolute Maximum Ratings
|**Symbol**|**Parameter**|**Minimum**|**Maximum**|**Units**|
|---|---|---|---|---|
|TS|Storage temperature|-50|150|°C|
|VESD|ESD – Human Body Model|–|2000|V|
||ESD – Charged Device Model|–|500|V|
|VDD– VSS|External supply voltage|-0.3|3.6|V|
|VIN|Voltage on 5V tolerant input pin|VSS– 0.3|VDD+ 4.0|V|
||Voltage on BSEL|VSS|VDD+ 4.0|V|
||Voltage on any other input pin|VSS– 0.3|4|V|
||VDDA– VDD||Variation allowed between VDDAand VDD|–|300|mV|
|VREF+– VDDA|Maximum voltage difference if VREF+> VDDA|–|400|mV|
|IVDD|Maximum total current consumption|–|140|mA|
|IGPIO|Output current sunk by any I/O or control pin without 5V Fast-<br>Mode Plus support|–|16|mA|
||Output current sunk by any I/O pin with 5V Fast-Mode Plus<br>support|–|22|mA|
||Output current that is sourced by any control or I/O pin|–|-16|mA|
|∑IGPIO|The sum of all output current that is sunk by all control pins and<br>I/O pins, except PA11 and PA12.|–|90|mA|
||Sum of the output current that is sunk by the A11 and A12 pins|–|25|mA|
||Sum of the output current that is sourced by all control and I/O<br>pins|–|-90|mA|
|IINJ|Injected current on any 5V tolerant GPIO pin, BSEL and RST|–|-5 / +0|mA|
||Injected current on any non 5V tolerant GPIO pin|–|±5|mA|
|∑IINJ|Sum of the injected current for all control and I/O pins|–|±25|mA|
June 5, 2019
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ZWIR4532 Datasheet
## 4. Recommended Operating Conditions
Table 4. Recommended Operating Conditions
|**Parameter**<br>~~se~~|**Parameter**<br>~~se~~|**Symbol**<br>~~se~~|**Minimum**<br>~~se~~|**Typical**<br>~~se~~|**Maximum**<br>~~se~~|**Units**<br>~~se~~|
|---|---|---|---|---|---|---|
|**Electrical Characteristics**<br>~~Ce~~|||||||
|Main supply voltage – ADC used<br>~~DGG~~||VDD<br>~~DGG~~|1.8<br>~~DGG~~|~~DGG~~|3.6<br>~~DGG~~|V<br>~~DGG~~|
|Digital I/O high level input voltage<br>~~PG~~||VIH<br>~~PG~~|0.7VDD<br>~~PG~~|~~PG~~|~~PG~~|V<br>~~PG~~|
|Digital I/O low level input voltage<br>~~PG~~||VIL<br>~~PG~~|~~PG~~|~~PG~~|0.3VDD<br>~~PG~~|V<br>~~PG~~|
|Digital I/O high level output voltage<br>~~OG~~||VOH<br>~~OG~~|VDD– 0.4<br>~~OG~~|~~OG~~|~~OG~~|V<br>~~OG~~|
|Digital I/O low level output voltage<br>~~OG~~<br>~~PG~~<br>~~CC~~||VOL<br>~~OG~~<br>~~PG~~<br>|~~OG~~<br>~~PG~~<br>|~~OG~~<br>~~PG~~<br>|0.4<br>~~OG~~<br>~~PG~~<br>|V<br>~~OG~~<br>~~PG~~<br>|
|**MCU Clock Characteristics**<br>~~PG~~<br>~~CC~~|||||||
|MCU core clock frequency[a]<br>~~CCse~~||fAHB<br>~~se~~|8<br>~~se~~|~~se~~|32<br>~~se~~|MHz<br>~~se~~|
|MCU core clock frequency accuracy range<br>~~Ge~~<br>~~a~~||∆fAHB<br>~~Ge~~|-2<br>~~Ge~~|~~Ge~~|2.5<br>~~Ge~~|%<br>~~Ge~~|
|MCU peripheral bus 1 clock frequency[b]<br>~~aPa~~||fAPB1||4||MHz|
|MCU peripheral bus 2 clock frequency[b]<br>~~aPa~~||fAPB2||8||MHz|
|**RF Parameters**<br>~~Pa~~|||||||
|Frequency range<br>~~GG~~||fRF<br>~~GG~~|865<br>~~GG~~|~~GG~~|928<br>~~GG~~|MHz<br>~~GG~~|
|Output power <br>~~OG~~||~~OG~~|-11<br>~~OG~~|~~OG~~|~~OG~~|dBm<br>~~OG~~|
|Output power tolerance<br>~~OG~~<br>~~PG~~<br>~~ee~~||~~OG~~<br>~~PG~~|-3<br>~~OG~~<br>~~PG~~|~~OG~~<br>~~PG~~|+3<br>~~OG~~<br>~~PG~~|dB<br>~~OG~~<br>~~PG~~|
|Receiver sensitivity<br>~~PG~~<br>~~RR~~<br>~~RR~~|BPSK, EU Mode<br>~~PG~~<br>~~ee~~<br>~~ee~~|~~PG~~<br>~~ss~~|~~PG~~<br>~~ss~~|-110<br>~~PG~~<br>~~ss~~|~~PG~~<br>~~ss~~|dBm<br>~~PG~~<br>~~ss~~|
||BPSK, US Mode<br>~~ee~~<br>~~ee~~<br>~~RR~~|~~ss~~|~~ss~~|-108<br>~~ss~~|~~ss~~|dBm<br>~~ss~~|
||QPSK, EU Mode<br>~~ee~~<br>~~RRes~~|~~ss~~|~~ss~~|-101<br>~~ss~~|~~ss~~|dBm<br>~~ss~~|
||QPSK, US Mode<br>~~RRes~~<br>~~RR~~|||-101<br>||dBm<br>|
|Gross data rate<br><br>~~RR~~<br>~~ES~~|BPSK, EU Mode<br>~~es~~<br>~~RR~~|||20<br>||kBit/s<br>|
||BPSK, US Mode<br>~~RR~~|||40<br>||kBit/s<br>|
||QPSK, EU Mode<br>~~ee~~|~~ee~~|~~ee~~|100<br>~~ee~~|~~ee~~|kBit/s<br>~~ee~~|
||QPSK, US Mode<br>~~ee~~<br>~~ES~~|~~ee~~<br>~~ES~~|~~ee~~|250<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|kBit/s<br>~~ee~~<br>~~ee~~|
|Channel spacing<br>~~ES~~<br>~~_———————E~~|EU Mode<br>~~ES~~|~~ES~~||1<br>~~ee~~|~~ee~~|MHz<br>~~ee~~|
||US Mode<br>~~ES~~<br>~~ee~~<br>~~_———————E~~|~~ES~~<br>~~ee~~<br>~~_———————E~~|~~ee~~<br>~~_———————E~~|2<br>~~ee~~<br>~~ee~~<br>~~_———————E~~|~~ee~~<br>~~ee~~<br>~~_———————E~~|MHz<br>~~ee~~<br>~~ee~~<br>~~_———————E~~|
|Number of channels<br>~~ES~~<br>~~_———————E~~<br>~~De~~|EU Mode[c]<br>~~ES~~<br>~~ee~~<br>~~_———————E~~<br>~~De~~|~~ES~~<br>~~ee~~<br>~~_———————E~~<br>~~ss~~|~~ee~~<br>~~_———————E~~<br>~~ss~~|1 (+3)<br>~~ee~~<br>~~ee~~<br>~~_———————E~~|~~ee~~<br>~~ee~~<br>~~_———————E~~|~~ee~~<br>~~ee~~<br>~~_———————E~~|
||US Mode<br>~~_———————E~~<br>~~De~~|~~_———————E~~<br>~~ss~~|~~_———————E~~<br>~~ss~~|10<br>~~_———————E~~|~~_———————E~~|~~_———————E~~|
|Input/output impedance<br>~~_———————E~~<br>~~De ~~<br>~~eG~~<br>~~a~~||~~_———————E~~<br> ~~ss~~<br>~~eG~~|~~_———————E~~<br>~~ss~~<br>~~eG~~|50<br>~~_———————E~~<br>~~eG~~|~~_———————E~~<br>~~eG~~|Ω<br>~~_———————E~~<br>~~eG~~|
|Frequency offset<br>~~eG~~<br>~~a~~||~~eG~~|-10<br>~~eG~~|~~eG~~|+10<br>~~eG~~|kHz<br>~~eG~~|
[a] The fCORE clock can be configured to be 8, 16, or 32 MHz. After reset, the clock is set to 8MHz.
[b] fAPB1 and fAPB2 are derived from fAHB. Therefore, the same tolerances apply to these clocks.
[c] The IEEE802.15.4 standard defines only 1 channel for EU Mode, but extension channels are available in almost all EU countries.
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## 5. Functional Overview
The ZWIR4532 is a programmable wireless IPv6 communication module that can host the user application. This removes the need for an external application processor, consequently minimizing space requirements, BOM cost, and the potential for communication errors. Applications benefit from the mesh networking functionality, which allows covering large areas with a single network, even if the communicating nodes have no direct radio link. The mesh network stack takes care of routing packets through the network transparently for the application. Routing failures are detected and repaired automatically; thus a failing node will not impair the overall network.
ZWIR4532 modules communicate using the User Datagram Protocol (UDP) over IPv6 (Internet Protocol version 6). They are interoperable with ZWIR45xx based networks. ZWIR45xx networks operate autonomously or integrate with nearly any existing computer network or the Internet. If integrated in an existing network, ZWIR45xx based devices are accessible in the same way as any other IPv6 networking device. As opposed to many competing solutions, gateway devices connecting ZWIR45xx networks are application-independent and do not limit the network functionality to a certain scope.
IDT provides a C-based Application Programming Interface (API) which is linked with the user application. In addition to standard networking, different supplemental and advanced functionalities are provided using a modular approach. This allows tailoring the network stack to the application’s requirements. The list of features below summarizes the functionalities provided by IDT’s network stack components.
- UDP/IPv6 network layer
- Packet-oriented communication with an arbitrary number of communication partners
- Support for multicast communication (communication targeted for more than one receiver)
- Event-based reception – incoming packets are handled in dedicated user-defined callbacks
- Highly configurable mesh-layer
- Allows hundreds of nodes per network
- Works out of the box for simple networks; allows tailoring for complex networks
- IPSec based security
- Authentication and encryption
- Allows real end-to-end secure communication (ZWIR-to-ZWIR, ZWIR-to-LAN, or ZWIR-to-Internet)
- Same technology as typically used in Virtual Private Networks (VPNs)
- Over-the-Air updates
- Updates enabled simply by linking the OTAU library into the application
- Host library provided for easy update transmission from user applications
- Standalone graphical frontend for update transmission provided
- Network monitoring and administration protocol
- IDT protocol to analyze network topology and query device parameters and status
- Extended version allowing remote configuration of devices
- Hardware abstraction libraries
- Different libraries providing high-level interfaces for the microcontroller (MCU) hardware components
The prime design goal of the API has been ease of use. Detailed documentation of all network stack features can be found in the _ZWIR45xx Programming Guide_ and the accompanying application notes.
The application firmware is executed on an ARM Cortex-M0+ 32 bit MCU. Applications have full access to the rich set of peripherals provided by this microcontroller. The list below summarizes the MCU features. Table 2 provides a detailed mapping of peripherals to GPIO pins.
- Internal RC or external crystal clock with up to 32MHz frequency
- 192kB of flash and 20kB of RAM memory – approximately 128kB flash and 4kB RAM available for user applications
- Communication interfaces: 4x U(S)ART, 1x UART, 1x SPI, 3x I2C
- 4 timers with up to 12 PWM inputs/outputs
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ZWIR4532 Datasheet
- 12-bit ADC (10 channels accessible), 2 comparators
- RTC and watchdog timer
- 7-channel DMA controller
## 5.1 Low Power Modes
The network stack provided for ZWIR4532 modules is designed to consume minimal power, even in Active Mode. If the module is idle in the active operating mode, the MCU enters a low power mode to minimize its current consumption. All peripherals and the transceiver remain active and wake up the MCU from Sleep Mode as soon as an event occurs that needs to be serviced. Power consumption in Active Mode can be optimized further by adapting the clock frequency to the application needs.
For battery-operated devices, the ultra-low-power Suspend Mode is provided. In this mode, the transceiver and most of the MCUs peripherals are turned off. The MCU core resides in the ARM Corex-M0 Stop Mode. The total power consumption is lowered to less than 1µA while all RAM contents and the application state are retained. Wake-up from Suspend Mode is possible through external GPIOs or the internal real-time clock.
## 5.2 Device Programming and Debugging
In-system programming and debugging are supported through ARM’s Serial Wire Debug (SWD) interface. SWD is a two-wire interface designed as an alternative to the 4-wire JTAG interface. Figure 2 shows how SWD is connected to the ARM standard connectors. These connectors are supported by a wide variety of debug adaptors. Alternatively the microcontroller can be programmed using its embedded serial boot loader, which allows programming through the UART or SPI. However, no debugging functionality is available through this interface.
## Figure 2. Serial-Wire Debug Connection with Standard ARM Connectors
A) 20 Pin ARM Header
**==> picture [446 x 210] intentionally omitted <==**
**----- Start of picture text -----**<br>
A) 20 Pin ARM Header B) 10 Pin Cortex Debug Connector<br>VDD<br>VDD 12 1 2<br>3 4 VDD<br>O Q<br>5 6 12 VDD<br>SWDIO 17 7 8 1 2 17<br>SWDIO<br>SWCLK 18 9 10 3 4 18<br>SWCLK<br>11 12 5 6<br>oo P d<br>13 o o 14 l 7 8<br>RESET 8 15 16 9 10 8 RESET<br>17 18<br>19 ©on o f 20 l ——d eS 9 7 GND<br>GND<br>GND u 9 =<br>GND<br>**----- End of picture text -----**<br>
## 6. Package Outline Drawing
The package outline drawings are appended at the end of this document and are accessible from the link below. The package information is the most current data available.
www.idt.com/document/psc/zwir4532-package-outline-drawing-120-x-156-x-215-mm-body08mm-pitch-mod0
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ZWIR4532 Datasheet
## 7. Soldering Information
To ensure that soldered connections do not break during the reflow soldering process of the application printed circuit board (PCB), the soldering profile described in Table 5 and Figure 3 must be maintained. This profile is aligned with the profile defined in the IPC/JEDEC standard J-STD-020D.
Table 5. Soldering Profile Parameters (according to J-STD-020D)
|**Profile Feature**<br>~~a~~<br>~~a~~|**Symbol**<br>~~a~~|**Minimum**<br>~~a~~|**Maximum**<br>~~a~~|**Units**<br>~~a~~|
|---|---|---|---|---|
|Time 25°C to TP<br>~~a~~<br>~~a~~|tH||8|min|
|Peak package body temperature<br>~~a~~<br>~~a~~<br>~~Cn~~|TP||260|°C|
|**Preheat / Soak**<br>~~a~~<br>~~Cn~~<br>~~a~~|||||
|Soak temperature<br>~~Cn~~<br>~~a~~|TS|100|150|°C|
|Soak time<br>~~a~~<br>~~es~~<br>~~Cn~~|tS<br>~~es~~<br>|60<br>~~es~~<br>|120<br>~~es~~<br>|s<br>~~es~~<br>|
|**Ramp-up**<br>~~Cn~~|||||
|Ramp-up rate[a]<br>~~Cnss~~|TLto TP<br>~~ss~~|~~ss~~|3<br>~~ss~~|°C/s<br>~~ss~~|
|Time maintained above TL<br>~~en~~<br>~~a~~|tL<br>~~en~~<br>|~~en~~<br>|150<br>~~en~~<br>|s<br>~~en~~<br>|
|Time within 5°C of TP<br>~~a~~|tP<br>||30<br>|s<br>|
|**Ramp-down**<br>~~a|~~|||||
|Ramp-down rate<br>~~I~~|TPto TL<br>~~I~~|~~I~~|6<br>~~I~~|°C/s<br>~~I~~|
[a] TL is the smelting point of the solder paste.
Figure 3. Recommended Temperature Profile for Reflow Soldering (according to J-STD-020D)
**==> picture [384 x 214] intentionally omitted <==**
**----- Start of picture text -----**<br>
TP<br>TP-5°C<br>tP<br>TL<br><_—).<br>TSmax<br>TSmin<br>tS<br>tH<br>Time 9<br>Temperature<br>**----- End of picture text -----**<br>
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ZWIR4532 Datasheet
## 8. Certification
## 8.1 European RED Statement
The ZWIR4532 module has been tested and found to comply with the Radio Equipment Directive (RED) and is the subject of a notified body opinion. The module has been approved for antennas with gains of 4 dBi or less. If the module should be used with antennas with higher gain, the modular approval is void and the end product must be fully certified.
**Important Notice** : End products targeted for geographic regions that are covered by the RED must ensure that a transmission duty cycle of less than 1% is maintained during normal operation. The duty cycle observation period is one hour. That means the cumulated transmission time of all transmissions during normal operation must not exceed 36 seconds when observed over one hour. IDT’s network stack provides duty-cycle monitoring and alarm mechanisms to support software developers in meeting the duty-cycle requirements. For detailed information, refer to the _ZWIR45xx Programming Guide._
## 8.2 Federal Communication Commission Certification Statements
## 8.2.1 Statements
This equipment has been tested and found to comply with the limits for a **Class B Digital Device** , pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, might cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures:
- Reorient or relocate the receiving antenna.
- Increase the separation between the equipment and receiver.
- Connect the equipment into an outlet on a circuit different from where the receiver is connected.
- Consult the dealer or an experienced radio/TV technician for help.
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device must not cause harmful interference, and (2) this device must accept any interference received, including interference that might cause undesired operation.
Modifications not expressly approved by IDT could void the user's authority to operate the equipment.
The internal/external antennas used for this mobile transmitter must provide a separation distance of at least 20cm from all persons and must not be co-located or operating in conjunction with any other antenna or transmitter.
## 8.2.2 Requirements
The ZWIR4532 complies with Part 15 of the FCC rules and regulations. In order to retain compliance with the FCC certification requirements, the following conditions must be met:
1. Modules must be installed by original equipment manufacturers (OEM) only.
2. The module must only be operated with antennas adhering to the requirements defined in section 8.2.3
3. The OEM must place a clearly visible text label on the outside of the end-product containing the text shown in Figure 4.
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ZWIR4532 Datasheet
**IMPORTANT:** The compliance statement as shown in Figure 4 must be used without modifications for the ZWIR4532 product.
## Figure 4. FCC Compliance Statement to be Printed on Equipment Incorporating ZWIR4532 Devices
Contains FCC ID: COR-ZWIR4532
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation.
## 8.2.3 Supported Antennas
The FCC compliance testing of the ZWIR4532 has been carried out using the MEXE902RPSM antenna from PCTEL, Inc. This antenna has an omnidirectional radiation pattern at an antenna gain of 2dBi. In order to be allowed to use the module without re-certification, the product incorporating the ZWIR4532 module must either use the antenna identified above or must use an antenna with an omnidirectional radiation pattern and a gain being less than or equal to 2dBi.
## 9. Ordering Information
|**Orderable Part Number**|**Description and Package**|**Carrier Type**|**Temperature**|
|---|---|---|---|
|ZWIR4532-U|6LoWPAN wireless radio module, unprogrammed,15.6 × 12 × 2.5 mm 43-LGA|Cut Tape|-40°C to +85°C|
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ZWIR4532 Datasheet
**==> picture [88 x 14] intentionally omitted <==**
## 10. Revision History
|**Revision Date**|**Description of Change**|
|---|---|
|June 5, 2019|<br>Updated drawings<br><br>Removed unsupported part number ZWIR4532-S001<br><br>Corrected carrier type forZWIR4532-U<br><br>Minor edits for pin names.<br><br>Minor edits forTable 3.|
|August 30, 2018|Initial release.|
Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road 1-800-345-7015 or 408-284-8200 www.IDT.com/go/support San Jose, CA 95138 Fax: 408-284-2775 www.IDT.com www.IDT.com/go/sales
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trade marks used herein are the property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. All contents of this document are copyright of Integrated Device Technology, Inc. All rights reserved.
© 2019 Integrated Device Technology, Inc.
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ZWIR4532 Package Outline Drawing 12.0 x 15.6 x 2.15 mm Body,0.8mm Pitch MOD0, PSC-4747-01, Rev 00, Page 1
© Integrated Device Technology, Inc. © Renesas Electronics Corporation
ZWIR4532 Package Outline Drawing 12.0 x 15.6 x 2.15 mm Body,0.8mm Pitch MOD0, PSC-4747-01, Rev 00, Page 2
||||Package Revision History|Package Revision History|Package Revision History|
|---|---|---|---|---|---|
|Date Created|Rev No.||||Description|
|||||||
|July 13, 2018||Rev 00<br>Initial Release||||
© Integrated Device Technology, Inc. © Renesas Electronics Corporation
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Updated at March 31, 2026
Renesas Electronics is a premier global supplier of advanced semiconductor solutions, driving innovation across automotive, industrial, infrastructure, and Internet of Things (IoT) applications. Recognized for a comprehensive portfolio that spans the entire signal chain, Renesas empowers engineers to design secure, intelligent, and highly efficient embedded systems for a rapidly evolving technological landscape. Our selection of Renesas components features a strong emphasis on precision timing and frequency management solutions. We offer a robust range of standard oscillators, timers, and pulse generators engineered to deliver exceptional accuracy and stability. These reliable clocking devices are essential for synchronizing complex digital operations and ensuring optimal performance in demanding circuit designs. In addition to timing components, our inventory includes essential discrete semiconductors and interface solutions. This encompasses high-performance single MOSFETs and bipolar transistors for efficient power routing, alongside versatile I/O expanders that simplify system connectivity. To support modern wireless integration, we also provide select Renesas RF transceivers, WLAN adaptors, and Bluetooth modules, equipping developers with the critical building blocks needed for advanced communication systems.
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