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ZGM230SB27HGN2R
RF Transceiver, 868.4 to 916 MHz, 100 kbps, -110.9dBm, SIP-44, -40 °C to 85 °C
⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
- Manufacturer: SILICON LABS
- Product type: RF Transceivers - Sub 2.4GHz ISM Band
- Data Rate: 100Kbps
- No. of Pins: 44Pins
- Frequency Max: 916MHz
- Frequency Min: 868.4MHz
- Sensitivity dBm: -110.9dBm
- RF IC Case Style: SIP
- Receiving Current: 5.1mA
- Output Power (dBm): 14dBm
- RF / IF Modulation: FSK, GFSK, O-QPSK
- Supply Voltage Max: 3.8V
- Supply Voltage Min: 1.8V
- Transmitting Current: 30mA
- Operating Temperature Max: 85°C
- Operating Temperature Min: -40°C
- RF Transceiver Applications: Building Automation, Lighting, Security, Smart Home
| Delivery and price | |
|---|---|
| Units per pack | 250 |
| Price | 6.56 € |
| Current stock | 200+ |
| Lead time | 7 days |
Datasheet
## **ZGM230S Z-Wave 800 SiP Module Data Sheet**
The ZGM230S is a system-in-package (SiP) module for Z-Wave connectivity and networking built for the performance, security, and energy demands of the Smart Home.
Based on the EFR32ZG23 SoC, it delivers robust RF performance, long-range, industryleading security features, low-current consumption, a rich set of MCU peripherals, and ample memory, all in a 6.5 x 6.5 mm package.
## **KEY FEATURES**
- Z-Wave connectivity
- RF pin for external antenna
- +14 dBm TX power
- -110.9 dBm RX sensitivity @100 kbps
- 32-bit ARM Cortex-M33 core at 39 MHz
The ZGM230S is a complete solution supported by powerful and fully-upgradeable software, advanced development and debugging tools, and documentation that will simplify and minimize the development cycle, certification process, and deployment of your endproduct, helping to accelerate its time-to-market significantly.
- 512/64 kB of Flash/RAM memory
- Advanced security features
- Rich set of MCU peripherals
- Integrated DC-DC converter
The ZGM230S is targeted for a broad range of applications, including:
- Smart Home
- Security
- Up to 34 GPIO pins
- -40 to 85 °C
- 6.5 mm x 6.5 mm
- Lighting
- Building Automation
**==> picture [522 x 263] intentionally omitted <==**
**----- Start of picture text -----**<br>
Core / Memory Crystal Clock Management Power Management Supply Security<br>39 MHz HF Crystal DC-DC Converter DC-DC LC Crypto DPA Counter-<br>ARM Cortex [TM] M33 processor Oscillator Acceleration measures<br>Flash Program<br>with DSP extensions,FPU and TrustZone Memory Fast Startup Precision LF Voltage Regulator Decoupling TRNG Secure Debug<br>RC Oscillator RC Oscillator Authentication<br>Power-On Reset<br>ETM InterfaceDebug MemoryRAM ControllerLDMA LF Crystal Oscillator Ultra LF RC Oscillator Brown-Out Detector ElementSecure<br>32-bit Bus<br>Peripheral Reflex System<br>RF Radio Subsystem Serial I/O Ports Timers and Triggers Analog I/F<br>Front-End Interfaces<br>RF Pin DEMOD ARM Cortex [TM] USART LCD Timer/Counter Protocol Timer ADC<br>M0+ Radio<br>RX/TX Front-End Controller External<br>Matching with Integrated +14 dBm PA IFADC BUFC RAM EUSART Interrupts Low Energy Timer Watchdog Timer ACMP<br>General<br>AGC EUSART Purpose I/O System Real Back-Up Real VDAC<br>FRC Time Counter Time Counter<br>Pin Reset<br>Frequency<br>Synthesizer MOD CRC I [2] C Pin Wakeup Temperature Sensor<br>Lowest power mode with peripheral operational:<br>EM0—Active EM1—Sleep EM2—Deep Sleep EM3—Stop EM4—Shutoff<br>**----- End of picture text -----**<br>
**Copyright © 2021 by Silicon Laboratories**
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Rev. 0.5
ZGM230S Z-Wave 800 SiP Module Data Sheet Features
## **1. Features**
- **Supported Protocols**
- Z-Wave
- Z-Wave Long Range
- **Wireless System-on-Chip**
- Sub-GHz radio
- TX power up to +14 dBm
- 32-bit ARM Cortex[®] -M33 with DSP instruction and floatingpoint unit for efficient signal processing
- 512 kB flash program memory
- 64 kB RAM data memory
- Embedded Trace Macrocell (ETM) for advanced debugging
- **Operating Range**
- 1.8 to 3.8 V
- -40 to +85°C
- **Dimensions**
- 6.5 mm x 6.5 mm
- **Security**
- Hardware Cryptographic Acceleration for AES128/192/256, ChaCha20-Poly1305, SHA-1, SHA-2/256/384/512, ECDSA +ECDH(P-192, P-256, P-384, P-521), Ed25519 and Curve25519, J-PAKE, PBKDF2
- True Random Number Generator (TRNG)
- ARM® TrustZone®
- **Receiver Performance**
- -110 dBm sensitivity at 9.6 kbps FSK, 868.42 MHz
- -110 dBm sensitivity at 40 kbps FSK, 868.4 MHz
- -108.8 dBm sensitivity at 100 kbps GFSK, 869.85 MHz
- -109.4 dBm sensitivity at 9.6 kbps FSK, 908.42 MHz
- -109.7 dBm sensitivity at 40 kbps FSK, 908.4 MHz
- -108.3 dBm sensitivity at 100 kbps GFSK, 916 MHz
- -110.9 dBm sensitivity at 100 kbps O-QPSK, 912 MHz
- **Current Consumption**
- 4.8 mA RX current at 9.6 kbps FSK, 868.42 MHz
- 4.8 mA RX current at 100 kbps GFSK, 869.85 MHz
- 4.8 mA RX current at 9.6 kbps FSK, 908.4 MHz
- 4.8 mA RX current at 100 kbps GFSK, 916 MHz
- 5.1 mA RX current at 100 kbps O-QPSK, 912 MHz
- 10.7 mA TX current at 0 dBm, 916 MHz
- 20.8 mA TX current at +10 dBm, 916 MHz
- 30.0 mA TX current at +14 dBm, 916 MHz
- 26 µA/MHz in Active Mode (EM0) at 39.0 MHz
- 1.5 µA in Deep Sleep (EM2) at 64 kB RAM retention and RTC running from LFRCO
- 0.7 µA in Shutoff Mode (EM4)
- Secure Boot (Root of Trust Secure Loader)
- Secure Debug Unlock
- DPA Countermeasures
- Secure Key Management with PUF
- Anti-Tamper
- Secure Attestation
- **MCU Peripherals**
- 12-bit 1 Msps or 16-bit 76.9 ksps SAR Analog to Digital Converter (ADC)
- 2 × Analog Comparator (ACMP)
- 2 × Digital to Analog Converter (VDAC)
- Low-Energy Sensor Interface (LESENSE)
- Up to 34 General Purpose I/O pins with output state retention and asynchronous interrupts
- 8 Channel DMA Controller
- 12 Channel Peripheral Reflex System (PRS)
- 4 × 16-bit Timer/Counter with 3 Compare/Capture/PWM channels
- 1 × 32-bit Timer/Counter with 3 Compare/Capture/PWM channels
- 32-bit Real Time Counter
- 24-bit Low Energy Timer for waveform generation
- 2 × Watchdog Timer
- 2× Enhanced Universal Synchronous/Asynchronous Receiver/Transmitter (EUSART)
- 1× Universal Synchronous/Asynchronous Receiver/Transmitter (UART/SPI/SmartCard (ISO 7816)/IrDA/I[2] S)
- 2 × I[2] C interface with SMBus support
- Integrated Low-Energy LCD Controller supporting up to 80 segments
- Die temperature sensor
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Rev. 0.5 | 2
ZGM230S Z-Wave 800 SiP Module Data Sheet Ordering Information
## **2. Ordering Information**
## **Table 2.1. ZGM230S Ordering Part Numbers**
|**Ordering Code**|**Protocol Stack**|**TX Power**|**Freq Band**|**Antenna**|**Flash**<br>**(kB)**|**RAM**<br>**(kB)**|**Security**|**Temp Range**|**Carrier**|
|---|---|---|---|---|---|---|---|---|---|
|ZGM230SA27HGN2|• Z-Wave<br>• Z-Wave Long<br>Range|+14 dBm|Sub-GHz|RF pin|512|64|Vault-Mid|-40 to 85 °C|Tray|
|ZGM230SB27HGN2|• Z-Wave<br>• Z-Wave Long<br>Range|+14 dBm|Sub-GHz|RF pin|512|64|Vault-High|-40 to 85 °C|Tray|
See Section 4.5 Sub-GHz RF Transceiver Characteristics of the Electrical Specifications for maximum TX power figures.
ZGM230S modules are not pre-programmed with a bootloader.
Throughout this document, the modules may be referred to by their product family name (ZGM230S), by their model name (ZGM230S), or by their full ordering code as seen in the table above.
The **ZWAVE-PK800A Z-Wave 800 Series Pro Kit** is available for ZGM230S evaluation and development, as well as **ZGM230RB4205B** radio boards.
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Rev. 0.5 | 3
## **Table of Contents**
|**1.**|**Features .**<br>**.**<br>**.**<br>**.**<br>**.**<br>**.**<br>**.**|**.**|**.**|**.**|**.**||**.**|**.**||**.**|**.**|**.**|**.**|**.**|**.**|**.**||**.**||**.**||**.**||**.**||**.**||**.**||**.**||**.**||**.**||**.**||**.**||**.**|**. 2**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**2.**|**Ordering Information**<br>**.**<br>**.**|**.**|**.**|**.**|**.**||**.**|**.**||**.**|**.**|**.**|**.**|**.**|**.**|**.**||**.**||**.**||**.**||**.**||**.**||**.**||**.**||**.**||**.**||**.**||**.**||**.**|**. 3**|
|**3.**|**System Overview .**<br>**.**<br>**.**<br>**.**|**.**|**.**|**.**|**.**||**.**|**.**||**.**|**.**|**.**|**.**|**.**|**.**|**.**||**.**||**.**||**.**||**.**||**.**||**.**||**.**||**.**||**.**||**.**||**.**||**.**|**. 6**|
||3.1 Block Diagram .<br>.<br>.<br>.|.|.|.|.||.|.||.|.|.|.|.|.|.||.||.||.||.||.||.||.||.||.||.||.||.|. 6|
||3.2 EFR32ZG23 SoC .<br>.<br>.|.|.|.|.||.|.||.|.|.|.|.|.|.||.||.||.||.||.||.||.||.||.||.||.||.|. 6|
||3.3 Antenna .<br>.<br>.<br>.<br>.<br>.|.|.|.|.||.|.||.|.|.|.|.|.|.||.||.||.||.||.||.||.||.||.||.||.||.|. 6|
||3.4 Power Supply<br>.<br>.<br>.<br>.|.|.|.|.||.|.||.|.|.|.|.|.|.||.||.||.||.||.||.||.||.||.||.||.||.|. 6|
||3.5 Security<br>.<br>.<br>.<br>.<br>.<br>.|.|.|.|.||.|.||.|.|.|.|.|.|.||.||.||.||.||.||.||.||.||.||.||.||.|. 6|
||3.5.1 Secure Boot with Root|of Trust|||and Secure||||||Loader (RTSL)|||||||.||.||.||.||.||.||.||.||.||.||.||.|. 7|
||3.5.2 Cryptographic Accelerator.|||.|.||.|.||.|.|.|.|.|.|.||.||.||.||.||.||.||.||.||.||.||.||.|. 7|
||3.5.3 True Random Number|Generator|||||.|.||.|.|.|.|.|.|.||.||.||.||.||.||.||.||.||.||.||.||.|. 7|
||3.5.4 Secure Debug with Lock/Unlock.||||||.|.||.|.|.|.|.|.|.||.||.||.||.||.||.||.||.||.||.||.||.|. 8|
||3.5.5 DPA Countermeasures.||.|.|.||.|.||.|.|.|.|.|.|.||.||.||.||.||.||.||.||.||.||.||.||.|. 8|
||3.5.6 Secure Key Management||with||PUF|||.||.|.|.|.|.|.|.||.||.||.||.||.||.||.||.||.||.||.||.|. 8|
||3.5.7 Anti-Tamper<br>.<br>.<br>.|.|.|.|.||.|.||.|.|.|.|.|.|.||.||.||.||.||.||.||.||.||.||.||.||.|. 8|
||3.5.8 Secure Attestation<br>.|.|.|.|.||.|.||.|.|.|.|.|.|.||.||.||.||.||.||.||.||.||.||.||.||.|. 8|
||3.6 Memory Map<br>.<br>.<br>.<br>.|.|.|.|.||.|.||.|.|.|.|.|.|.||.||.||.||.||.||.||.||.||.||.||.||.|. 9|
|**4.**|**Electrical Specifications**<br>**.**|**.**|**.**||**.**|**.**|**.**||**.**|**.**|**.**|**.**|**.**|**.**||**.**|**.**||**.**||**.**||**.**||**.**||**.**||**.**||**.**||**.**||**.**||**.**||**.**||**. 10**|
||4.1 Electrical Characteristics|.|.|.|.||.|.||.|.|.|.|.|.|.||.||.||.||.||.||.||.||.||.||.||.||.|.10|
||4.2 Absolute Maximum Ratings.||.|.|.||.|.||.|.|.|.|.|.|.||.||.||.||.||.||.||.||.||.||.||.||.|.10|
||4.3 General Operating Conditions||.|.|.||.|.||.|.|.|.|.|.|.||.||.||.||.||.||.||.||.||.||.||.||.|.11|
||4.4 Current Consumption.<br>.|.|.|.|.||.|.||.|.|.|.|.|.|.||.||.||.||.||.||.||.||.||.||.||.||.|.12|
||4.4.1 MCU Current Consumption at 3.3|||||V input|||||.|.|.|.|.|.||.||.||.||.||.||.||.||.||.||.||.||.|.12|
||4.4.2 MCU Current Consumption at 1.8|||||V input|||||.|.|.|.|.|.||.||.||.||.||.||.||.||.||.||.||.||.|.13|
||4.4.3 Z-Wave Radio Current|Consumption at|||||||3.3||V|.|.|.|.|.||.||.||.||.||.||.||.||.||.||.||.||.|.14|
||4.4.4 Z-Wave Radio Current|Consumption at|||||||1.8||V|.|.|.|.|.||.||.||.||.||.||.||.||.||.||.||.||.|.15|
||4.5 Sub-GHz RF Transceiver Characteristics|||||||.||.|.|.|.|.|.|.||.||.||.||.||.||.||.||.||.||.||.||.|.16|
||4.5.1 RF Transmitter Characteristics||||.||.|.||.|.|.|.|.|.|.||.||.||.||.||.||.||.||.||.||.||.||.|.16|
||4.5.2 RF Receiver Characteristics|||.|.||.|.||.|.|.|.|.|.|.||.||.||.||.||.||.||.||.||.||.||.||.|.19|
||4.6 High-Frequency Crystal .|.|.|.|.||.|.||.|.|.|.|.|.|.||.||.||.||.||.||.||.||.||.||.||.||.|.23|
||4.7 GPIO Pins<br>.<br>.<br>.<br>.<br>.|.|.|.|.||.|.||.|.|.|.|.|.|.||.||.||.||.||.||.||.||.||.||.||.||.|.24|
||4.8 Microcontroller Peripherals|.|.|.|.||.|.||.|.|.|.|.|.|.||.||.||.||.||.||.||.||.||.||.||.||.|.25|
|**5.**|**Reference Diagrams.**<br>**.**<br>**.**|**.**|**.**|**.**|**.**||**.**|**.**||**.**|**.**|**.**|**.**|**.**|**.**|**.**||**.**||**.**||**.**||**.**||**.**||**.**||**.**||**.**||**.**||**.**||**.**||**.**|**26**|
||5.1 Standalone Application .|.|.|.|.||.|.||.|.|.|.|.|.|.||.||.||.||.||.||.||.||.||.||.||.||.|.26|
||5.2 Network Co-Processor (NCP)||Application|||||with UART|||||Host||.|.||.||.||.||.||.||.||.||.||.||.||.||.|.27|
|**6.**|**Pin Definitions .**<br>**.**<br>**.**<br>**.**<br>**.**|**.**|**.**|**.**|**.**||**.**|**.**||**.**|**.**|**.**|**.**|**.**|**.**|**.**||**.**||**.**||**.**||**.**||**.**||**.**||**.**||**.**||**.**||**.**||**.**||**.**|**28**|
||6.1 Module Pinout .<br>.<br>.<br>.|.|.|.|.||.|.||.|.|.|.|.|.|.||.||.||.||.||.||.||.||.||.||.||.||.|.28|
||6.2 Alternate Pin Functions .|.|.|.|.||.|.||.|.|.|.|.|.|.||.||.||.||.||.||.||.||.||.||.||.||.|.30|
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Rev. 0.5 | 4
|6.3 Analog Peripheral Connectivity|6.3 Analog Peripheral Connectivity|6.3 Analog Peripheral Connectivity|6.3 Analog Peripheral Connectivity|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.31|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|6.4 Digital Peripheral Connectivity .||||.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.32|
|**7. Design Guidelines**<br>**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**. 36**|
|7.1 Layout and Placement|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.36|
|7.2 Proximity to Other Materials|||.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.38|
|7.3 Reset .<br>.<br>.<br>.<br>.<br>.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.38|
|7.4 Debug .<br>.<br>.<br>.<br>.<br>.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.39|
|7.5 Packet Trace Interface|(PTI)||.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.39|
|**8. Package Specifications**||**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.40**|
|8.1 Package Outline<br>.<br>.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.40|
|8.2 PCB Land Pattern .<br>.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.43|
|8.3 Package Marking .<br>.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.|.44|
|**9. Soldering Recommendations**||||**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**. 45**|
|**10. Tape and Reel**<br>**.**<br>**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.46**|
|**11. Certifications .**<br>**.**<br>**.**<br>**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**47**|
|**12. Revision History.**<br>**.**<br>**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**.**|**48**|
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Rev. 0.5 | 5
ZGM230S Z-Wave 800 SiP Module Data Sheet System Overview
## **3. System Overview**
## **3.1 Block Diagram**
The ZGM230S module is a highly-integrated, high-performance system in a package with all the hardware components needed to enable Sub-GHz wireless connectivity and support robust networking capabilities via the Z-Wave protocol.
Built around the EFR32ZG23 Wireless Gecko SoC, the ZGM230S includes a 50 Ω RF pin to attach an external antenna, a matching network optimized for transmit power efficiency, supply decoupling and filtering components, an LC tank for DCDC conversion, and a 39 MHz crystal.
**==> picture [292 x 181] intentionally omitted <==**
**----- Start of picture text -----**<br>
VREGVDD<br>Supply Decoupling<br>IOVDD<br>DCDC<br>LC<br>Silicon Labs<br>RFIO RF Match<br>EFR32ZG23 GP IO<br>(up to 34)<br>HF XTAL<br>RESET GND<br>**----- End of picture text -----**<br>
**Figure 3.1. ZGM230S Block Diagram**
## **3.2 EFR32ZG23 SoC**
The EFR32ZG23 SoC features a 32-bit ARM Cortex M33 core, a Sub-GHz high-performance radio, 512 kB of Flash memory, a dedicated core for security, a rich set of MCU peripherals, and various clock management and serial interfacing options. Consult the EFR32xG23 Reference Manual and the EFR32ZG23 Data Sheet for details.
## **3.3 Antenna**
The ZGM230S modules include a 50 Ω-matched RFIO pin to attach an external antenna to the module.
## **3.4 Power Supply**
The nominal supply level of the ZGM230S is 3.3 V, but due to its integrated DCDC converter and built-in LDOs, the device can operate over a supply range of 1.8—3.8 V.
Only a few external decoupling capacitors are required (see Reference Diagrams). Since all smaller caps are integrated in the module, there is no need for fast decoupling externally. L and C for the DCDC converter are integrated in the module as well.
## **3.5 Security**
ZGM230S modules support one of two levels in the Security Portfolio offered by Silicon Labs: Secure Vault Mid or Secure Vault High.
Secure Vault is a collection of technologies that deliver state-of-the-art security and upgradability features to protect and future-proof IoT devices against costly threats, attacks and tampering. A dedicated security CPU enables the Secure Vault functions and isolates cryptographic functions and data from the Cortex-M33 core. ZGM230SB part numbers support Secure Vault High and ZGM230SA part numbers support Secure Vault Mid.
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Rev. 0.5 | 6
ZGM230S Z-Wave 800 SiP Module Data Sheet System Overview
## **Table 3.1. Security Features and Levels**
|**Feature**|**Secure Vault Mid**|**Secure Vault High**|
|---|---|---|
|Secure Boot with Root of Trust and Secure Loader (RTSL)|X|X|
|Cryptographic Accelerator|X|X|
|True Random Number Generator (TRNG)|X|X|
|Secure Debug with Lock/Unlock|X|X|
|DPA Countermeasures|X|X|
|Secure Key Management with PUF||X|
|Anti-Tamper||X|
|Secure Attestation||X|
## **3.5.1 Secure Boot with Root of Trust and Secure Loader (RTSL)**
The Secure Boot with RTSL authenticates a chain of trusted firmware that begins from an immutable memory (ROM).
It prevents malware injection, prevents rollback, ensures that only authentic firmware is executed, and protects Over The Air updates.
For more information about this feature, see _AN1218: Series 2 Secure Boot with RTSL_ .
## **3.5.2 Cryptographic Accelerator**
The Cryptographic Accelerator is an autonomous hardware accelerator with Differential Power Analysis (DPA) countermeasures to protect keys.
It supports AES encryption and decryption with 128/192/256-bit keys, ChaCha20 encryption, and Elliptic Curve Cryptography (ECC) to support public key operations, and hashes.
Supported block cipher modes of operation for AES include:
- ECB (Electronic Code Book)
- CTR (Counter Mode)
- CBC (Cipher Block Chaining)
- CFB (Cipher Feedback)
- GCM (Galois Counter Mode)
- CCM (Counter with CBC-MAC)
- CBC-MAC (Cipher Block Chaining Message Authentication Code)
- GMAC (Galois Message Authentication Code)
The Cryptographic Accelerator accelerates Elliptical Curve Cryptography and supports the NIST (National Institute of Standards and Technology) recommended curves including P-192, P-256, P-384, and P-521 for ECDH (Elliptic Curve Diffie-Hellman) key derivation, and ECDSA (Elliptic Curve Digital Signature Algorithm) sign and verify operations. Also supported is the non-NIST Curve25519 for ECDH and Ed25519 for EdDSA (Edwards-curve Digital Signature Algorithm) sign and verify operations.
Secure Vault also supports ECJ-PAKE (Elliptic Curve variant of Password Authenticated Key Exchange by Juggling) and PBKDF2 (Password-Based Key Derivation Function 2).
Supported hashes include SHA-1, SHA-2/256/384/512 and Poly1305.
This implementation provides a fast and energy efficient solution to state of the art cryptographic needs.
## **3.5.3 True Random Number Generator**
The True Random Number Generator module is a non-deterministic random number generator that harvests entropy from a thermal energy source. It includes start-up health tests for the entropy source as required by NIST SP800-90B and AIS-31 as well as online health tests required for NIST SP800-90C.
The TRNG is suitable for periodically generating entropy to seed an approved pseudo random number generator.
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Rev. 0.5 | 7
ZGM230S Z-Wave 800 SiP Module Data Sheet System Overview
## **3.5.4 Secure Debug with Lock/Unlock**
For obvious security reasons, it is critical for a product to have its debug interface locked before being released in the field.
In addition, Secure Vault High also provides a secure debug unlock function that allows authenticated access based on public key cryptography. This functionality is particularly useful for supporting failure analysis while maintaining confidentiality of IP and sensitive enduser data.
For more information about this feature, see _AN1190: Series 2 Secure Debug_ .
## **3.5.5 DPA Countermeasures**
The AES and ECC accelerators have Differential Power Analysis (DPA) countermeasures support. This makes it very expensive from a time and effort standpoint to use DPA to recover secret keys.
## **3.5.6 Secure Key Management with PUF**
Key material in Secure Vault High products is protected by "key wrapping" with a standardized symmetric encryption mechanism. This method has the advantage of protecting a virtually unlimited number of keys, limited only by the storage that is accessible by the Cortex-M33, which includes off-chip storage as well. The symmetric key used for this wrapping and unwrapping must be highly secure because it can expose all other key materials in the system. The Secure Vault Key Management system uses a Physically Unclonable Function (PUF) to generate a persistent device-unique seed key on power up to dynamically generate this critical wrapping/unwrapping key which is only visible to the AES encryption engine and is not retained when the device loses power.
## **3.5.7 Anti-Tamper**
Secure Vault High devices provide internal tampers monitoring the system such as voltage, temperature, and electromagnetic pulses as well as detecting tamper of the security sub-system itself. Additionally, 8 external configurable tamper pins support external tamper sources, such as case tamper switches.
For each tamper event, the user is able to select the severity of the tamper response ranging from an interrupt, to a reset, to destroying the PUF reconstruction data which will make all protected key materials un-recoverable and effectively render the device inoperable. The tamper system also has an internal resettable event counter with programmable trigger threshold and refresh periods to mitigate false positive tamper events.
For more information about this feature, see _AN1247: Anti-Tamper Protection Configuration and Use_ .
## **3.5.8 Secure Attestation**
Secure Vault High products support Secure Attestation, which begins with a secure identity that is created during the Silicon Labs manufacturing process. During device production, each device generates its own public/private keypair and securely stores the wrapped private key into immutable OTP memory and this key never leaves the device. The corresponding public key is extracted from the device and inserted into a binary DER-encoded X.509 device certificate, which is signed into a Silicon Labs CA chain and then programmed back into the chip into an immutable OTP memory.
The secure identity can be used to authenticate the chip at any time in the life of the product. The production certification chain can be requested remotely from the product. This certification chain can be used to verify that the device was authentically produced by Silicon Labs. The device unique public key is also bound to the device certificate in the certification chain. A challenge can be sent to the chip at any point in time to be signed by the device private key. The public key in the device certificate can then be used to verify the challenge response, proving that the device has access to the securely-stored private key, which prevents counterfeit products or impersonation attacks.
For more information about this feature, see _AN1268: Authenticating Silicon Labs Devices Using Device Certificates_ .
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ZGM230S Z-Wave 800 SiP Module Data Sheet System Overview
## **3.6 Memory Map**
The ZGM230S memory map is shown in the figures below.
**==> picture [540 x 406] intentionally omitted <==**
**Figure 3.2. ZGM230S Memory Map — Core Peripherals and Code Space**
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ZGM230S Z-Wave 800 SiP Module Data Sheet Electrical Specifications
## **4. Electrical Specifications**
## **4.1 Electrical Characteristics**
All electrical parameters in all tables are specified under the following conditions, unless stated otherwise:
- Typical values are based on TA=25 °C and all supplies at 3.3 V, by production test and/or technology characterization.
- Radio performance numbers are measured in conducted mode, based on Silicon Laboratories reference designs using output power-specific external RF impedance-matching networks for interfacing to a 50 Ω antenna.
- Minimum and maximum values represent the worst conditions across supply voltage, process variation, and operating temperature, unless stated otherwise.
## **4.2 Absolute Maximum Ratings**
Stresses beyond those listed below may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions beyond those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. For more information on the available quality and reliability data, see the Quality and Reliability Monitor Report at http://www.silabs.com/support/quality/pages/default.aspx.
**Table 4.1. Absolute Maximum Ratings**
|**Parameter**|**Symbol**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|Storage temperature range|TSTG||-50|—|+150|°C|
|Voltage on any supply pin|VDDMAX||-0.3|—|3.8|V|
|Voltage ramp rate on any<br>supply pin|VDDRAMPMAX||—|—|1.0|V / µs|
|DC voltage on any GPIO<br>pin1|VDIGPIN||-0.3|—|VIOVDD+<br>0.3|V|
|DC voltage on RESETn pin2|VRESETn||-0.3|—|3.8|V|
|Total current into VDD power<br>lines|IVDDMAX|Source|—|—|200|mA|
|Total current into VSS<br>ground lines|IVSSMAX|Sink|—|—|200|mA|
|Current per I/O pin|IIOMAX|Sink|—|—|50|mA|
|||Source|—|—|50|mA|
|Current for all I/O pins|IIOALLMAX|Sink|—|—|200|mA|
|||Source|—|—|200|mA|
|**Note:**<br>1. When operating as an LCD driver, the output voltage on a GPIO may safely exceed this specification. The pin output voltage may<br>be up to 3.8 V in this case.<br>2. The RESETn pin has a pull-up device to the internally-regulated DVDD supply, which is generated by the DC-DC converter.<br>DVDD is equal to 1.8 V when DC-DC is active and bypassed to VREGVDD when DC-DC is inactive. For minimum leakage, it is<br>recommended to not drive RESETn high, and instead rely on the internall pull-up.|||||||
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ZGM230S Z-Wave 800 SiP Module Data Sheet Electrical Specifications
## **4.3 General Operating Conditions**
## **Table 4.2. General Operating Conditions**
|**Parameter**|**Symbol**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|Operating ambient tempera-<br>ture range|TA||-40|—|+85|°C|
|IOVDDx operating supply<br>voltage (All IOVDD pins)|VIOVDDx||1.8|3.3|3.8|V|
|VREGVDD operating supply<br>voltage|VVREGVDD||1.8|3.3|3.8|V|
|HCLK and SYSCLK frequen-<br>cy|fHCLK|VSCALE1, MODE = WS0|—|—|39|MHz|
|PCLK frequency|fPCLK|VSCALE1|—|—|39|MHz|
|EM01 Group A clock fre-<br>quency|fEM01GRPACLK|VSCALE1|—|—|39|MHz|
|HCLK Radio frequency|fHCLKRADIO|VSCALE1|—|39.0|—|MHz|
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ZGM230S Z-Wave 800 SiP Module Data Sheet Electrical Specifications
## **4.4 Current Consumption**
## **4.4.1 MCU Current Consumption at 3.3 V input**
Unless otherwise indicated, typical conditions are: VREGVDD = IOVDD = 3.3V. Voltage scaling level = VSCALE1. TA = 25 °C. Minimum and maximum values in this table represent the worst conditions across process variation at TA = 25 °C.
**Table 4.3. MCU Current Consumption at 3.3 V input**
|**Parameter**|**Symbol**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|Current consumption in EM0<br>mode with all peripherals dis-<br>abled|IACTIVE|39 MHz crystal, CPU running<br>Prime from flash|—|27|—|µA/MHz|
|||39 MHz crystal, CPU running<br>while loop from flash|—|26|—|µA/MHz|
|||39 MHz crystal, CPU running<br>CoreMark loop from flash|—|36|—|µA/MHz|
|Current consumption in EM1<br>mode with all peripherals dis-<br>abled|IEM1|39 MHz crystal|—|18|—|µA/MHz|
|Current consumption in EM2<br>mode, VSCALE0|IEM2_VS|64 kB RAM and full Radio RAM<br>retention, RTC running from<br>LFXO|—|1.5|—|µA|
|||64 kB RAM and full Radio RAM<br>retention, RTC running from<br>LFRCO|—|1.5|—|µA|
|Current consumption in EM4<br>mode|IEM4|BURTC with LFRCO|—|0.7|—|µA|
|Current consumption for re-<br>tained RAM bank in EM2 or<br>EM3|IRAM|Per 16 kB RAM bank|—|0.1|—|µA|
|Additional current in EM2 or<br>EM3 when any peripheral in<br>PD0B is enabled1|IPD0B_VS||—|0.85|—|µA|
|Additional current in EM2 or<br>EM3 when any peripheral in<br>PD0C is enabled1|IPD0C_VS||—|0.13|—|µA|
|Additional current in EM2 or<br>EM3 when any peripheral in<br>PD0D is enabled1|IPD0D_VS||—|0.98|—|µA|
|Additional current in EM2 or<br>EM3 when any peripheral in<br>PD0E is enabled1|IPD0E_VS||—|0.06|—|µA|
|**Note:**<br>1. Extra current consumed by power domain. Does not include current associated with the enabled peripherals. See the "Power<br>Domains" section in the SoC datasheet for a list of the peripherals in each power domain.|||||||
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ZGM230S Z-Wave 800 SiP Module Data Sheet Electrical Specifications
## **4.4.2 MCU Current Consumption at 1.8 V input**
Unless otherwise indicated, typical conditions are: VREGVDD = IOVDD = 1.8 V. Voltage scaling level = VSCALE1. TA = 25 °C. Minimum and maximum values in this table represent the worst conditions across process variation at TA = 25 °C.
**Table 4.4. MCU Current Consumption at 1.8 V input**
|**Parameter**|**Symbol**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|Current consumption in EM0<br>mode with all peripherals dis-<br>abled|IACTIVE|39 MHz crystal, CPU running<br>Prime from flash|—|44|—|µA/MHz|
|||39 MHz crystal, CPU running<br>while loop from flash|—|42|—|µA/MHz|
|||39 MHz crystal, CPU running<br>CoreMark loop from flash|—|58|—|µA/MHz|
|Current consumption in EM1<br>mode with all peripherals dis-<br>abled|IEM1|39 MHz crystal|—|29|—|µA/MHz|
|Current consumption in EM2<br>mode, VSCALE0|IEM2_VS|64 kB RAM and full Radio RAM<br>retention, RTC running from<br>LFXO|—|2.2|—|µA|
|||64 kB RAM and full Radio RAM<br>retention, RTC running from<br>LFRCO|—|2.2|—|µA|
|Current consumption for re-<br>tained RAM bank in EM2 or<br>EM3|IRAM|Per 16 kB RAM bank|—|0.15|—|µA|
|Current consumption in EM4<br>mode|IEM4|BURTC with LFRCO|—|0.52|—|µA|
|Current consumption during<br>reset|IRST|Hard pin reset held|—|384|—|µA|
|Additional current in EM2 or<br>EM3 when any peripheral in<br>PD0B is enabled1|IPD0B_VS||—|1.38|—|µA|
|Additional current in EM2 or<br>EM3 when any peripheral in<br>PD0C is enabled1|IPD0C_VS||—|0.21|—|µA|
|Additional current in EM2 or<br>EM3 when any peripheral in<br>PD0D is enabled1|IPD0D_VS||—|1.59|—|µA|
|Additional current in EM2 or<br>EM3 when any peripheral in<br>PD0E is enabled1|IPD0E_VS||—|0.10|—|µA|
|**Note:**<br>1. Extra current consumed by power domain. Does not include current associated with the enabled peripherals. See the "Power<br>Domains" section in the SoC datasheet for a list of the peripherals in each power domain.|||||||
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ZGM230S Z-Wave 800 SiP Module Data Sheet Electrical Specifications
## **4.4.3 Z-Wave Radio Current Consumption at 3.3 V**
RF current consumption measured with MCU in EM1, HCLK = 39.0 MHz, and all MCU peripherals disabled. Unless otherwise indicated, typical conditions are: VREGVDD = IOVDD = 3.3 V. TA = 25 °C. Minimum and maximum values in this table represent the worst conditions across process variation at TA = 25 °C.
**Table 4.5. Z-Wave Radio Current Consumption at 3.3 V**
|**Parameter**|**Symbol**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|Current consumption in re-<br>ceive mode, active packet<br>reception, VSCALE1, EM1P1|IRX_ACTIVE|f = 868.4 MHz, 2-FSK, 40 kbps|—|4.8|—|mA|
|||f = 868.42 MHz, 2-FSK, 9.6 kbps|—|4.8|—|mA|
|||f = 869.85 MHz, 2-GFSK, 100<br>kbps|—|4.8|—|mA|
|||f = 908.42 MHz, 2-FSK, 9.6 kbps|—|4.8|—|mA|
|||f = 908.4 MHz, 2-FSK, 40 kbps|—|4.8|—|mA|
|||f = 916 MHz, 2-GFSK, 100 kbps|—|4.8|—|mA|
|||f = 912 MHz, O-QPSK 100 kbps|—|5.1|—|mA|
|Current consumption in re-<br>ceive mode, listening for<br>packet, VSCALE1, EM1P1|IRX_LISTEN|f = 868.4 MHz, 2-FSK, 40 kbps|—|4.9|—|mA|
|||f = 868.42 MHz, 2-FSK, 9.6 kbps|—|4.9|—|mA|
|||f = 869.85 MHz, 2-GFSK, 100<br>kbps|—|4.9|—|mA|
|||f = 908.42 MHz, 2-FSK, 9.6 kbps|—|4.8|—|mA|
|||f = 908.4 MHz, 2-FSK, 40 kbps|—|4.9|—|mA|
|||f = 916 MHz, 2-GFSK, 100 kbps|—|4.9|—|mA|
|||f = 912 MHz, O-QPSK 100 kbps|—|5|—|mA|
|Current consumption in<br>transmit mode|ITX|f = 916 MHz, CW, 0 dBm output<br>power|—|10.7|—|mA|
|||f = 916 MHz, CW, 4 dBm output<br>power|—|13.5|—|mA|
|||f = 916 MHz, CW, 10 dBm output<br>power|—|20.8|—|mA|
|||f = 916 MHz, CW, 14 dBm output<br>power|—|30.0|—|mA|
|**Note:**<br>1. EM1P operation is 0.22 mA lower than EM1 operation|||||||
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ZGM230S Z-Wave 800 SiP Module Data Sheet Electrical Specifications
## **4.4.4 Z-Wave Radio Current Consumption at 1.8 V**
RF current consumption measured with MCU in EM1, HCLK = 39.0 MHz, and all MCU peripherals disabled. Unless otherwise indicated, typical conditions are: VREGVDD = IOVDD = 1.8 V. TA = 25 °C. Minimum and maximum values in this table represent the worst conditions across process variation at TA = 25 °C.
**Table 4.6. Z-Wave Radio Current Consumption at 1.8 V**
|**Parameter**|**Symbol**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|Current consumption in re-<br>ceive mode, active packet<br>reception, VSCALE1, EM1P1|IRX_ACTIVE|f = 868.4 MHz, 2-FSK, 40 kbps|—|5.4|—|mA|
|||f = 868.42 MHz, 2-FSK, 9.6 kbps|—|5.4|—|mA|
|||f = 869.85 MHz, 2-GFSK, 100<br>kbps|—|5.4|—|mA|
|||f = 908.42 MHz, 2-FSK, 9.6 kbps|—|5.4|—|mA|
|||f = 908.4 MHz, 2-FSK, 40 kbps|—|5.4|—|mA|
|||f = 916 MHz, 2-GFSK, 100 kbps|—|5.4|—|mA|
|||f = 912 MHz, O-QPSK 100 kbps|—|5.7|—|mA|
|Current consumption in re-<br>ceive mode, listening for<br>packet, VSCALE1, EM1P1|IRX_LISTEN|f = 868.4 MHz, 2-FSK, 40 kbps|—|5.4|—|mA|
|||f = 868.42 MHz, 2-FSK, 9.6 kbps|—|5.5|—|mA|
|||f = 869.85 MHz, 2-GFSK, 100<br>kbps|—|5.5|—|mA|
|||f = 908.42 MHz, 2-FSK, 9.6 kbps|—|5.4|—|mA|
|||f = 908.4 MHz, 2-FSK, 40 kbps|—|5.5|—|mA|
|||f = 916 MHz, 2-GFSK, 100 kbps|—|5.5|—|mA|
|||f = 912 MHz, O-QPSK 100 kbps|—|5.7|—|mA|
|Current consumption in<br>transmit mode|ITX|f = 916 MHz, CW, 0 dBm output<br>power|—|16.8|—|mA|
|||f = 916 MHz, CW, 4 dBm output<br>power|—|21.1|—|mA|
|||f = 916 MHz, CW, 10 dBm output<br>power|—|32.5|—|mA|
|||f = 916 MHz, CW, 14 dBm output<br>power|—|46.8|—|mA|
|**Note:**<br>1. EM1P operation is 0.35 mA lower than EM1 operation|||||||
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ZGM230S Z-Wave 800 SiP Module Data Sheet Electrical Specifications
## **4.5 Sub-GHz RF Transceiver Characteristics**
## **4.5.1 RF Transmitter Characteristics**
## **4.5.1.1 868 MHz Band +14 dBm RF Transmitter Characteristics for Z-Wave**
Unless otherwise indicated, typical conditions are: TA = 25 °C, VREGVDD = IOVDD = 3.3 V, Crystal frequency= 39.0 MHz. RF center frequency 868.4 MHz
**Table 4.7. 868 MHz Band +14 dBm RF Transmitter Characteristics for Z-Wave**
|**Parameter**|**Symbol**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|RF test frequency range|FRANGE||863|—|870|MHz|
|Maximum TX Power|POUTMAX|14 dBm output power12|13.9|14.3|14.5|dBm|
|Minimum active TX Power|POUTMIN||-24.2|-23.9|—|dBm|
|Output power variation vs<br>supply at POUTMAX|POUTVAR_V|1.8 V < VVREGVDD< 3.3 V, T = 25<br>°C|—|0.03|—|dB|
|Output power variation vs<br>temperature, peak to peak|POUTVAR_T|TA= -40 to +85 °C|—|0.3|0.9|dB|
|Output power variation vs RF<br>frequency|POUTVAR_F|T = 25 °C|—|0.05|0.5|dB|
|Spurious emissions of har-<br>monics, Conducted meas-<br>urement, POUT= +14 dBm,<br>868.4 MHz|SPURHARM_ETSI|(frequencies above 1 GHz)3|—|-52|—|dBm|
|Spurious emissions out-of-<br>band, Conducted measure-<br>ment, POUT= +14 dBm,<br>868.4 MHz|SPUROOB_ETSI|Per ETSI EN 300-220, Section<br>7.8.2.1 (47-74 MHz, 87.5-118<br>MHz, 174-230 MHz, and 470-862<br>MHz)|—|-65|—|dBm|
|||Per ETSI EN 300-220, Section<br>7.8.2.1 (other frequencies below 1<br>GHz)|—|-59|—|dBm|
|||Per ETSI EN 300-220, Section<br>7.8.2.1 (frequencies above 1<br>GHz)|—|-59|—|dBm|
|**Note:**<br>1. The output power level can be adjusted to suit specific regulatory requirements for the region in which the device is used.<br>2. The transmit power for the 863 MHz to 870 Band MHz is normally limited to +14 dBm.<br>3. Spurious emission limits per EN 300-220-1 v3.1.1 5.9.2|||||||
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ZGM230S Z-Wave 800 SiP Module Data Sheet Electrical Specifications
## **4.5.1.2 915 MHz Band 0 dBm RF Transmitter Characteristics for Z-Wave**
Unless otherwise indicated, typical conditions are: TA = 25 °C, VREGVDD = IOVDD = 3.3 V, Crystal frequency= 39.0 MHz. RF center frequency 908.4 MHz.
**Table 4.8. 915 MHz Band 0 dBm RF Transmitter Characteristics for Z-Wave**
|**Parameter**|**Symbol**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|RF test frequency range|FRANGE||902|—|928|MHz|
|Maximum TX Power|POUTMAX|0 dBm output power12|-0.2|0.11|0.54|dBm|
|Minimum active TX Power|POUTMIN||-24.5|-24.2|—|dBm|
|Output power variation vs<br>supply at POUTMAX|POUTVAR_V|1.8 V < VVREGVDD< 3.3 V, T = 25<br>°C|—|0.03|—|dB|
|Output power variation vs<br>temperature, peak to peak|POUTVAR_T|TA= -40 to +85 °C|—|1.25|—|dB|
|Output power variation vs RF<br>frequency|POUTVAR_F|TA= 25 °C|—|0.02|—|dB|
|Spurious emissions of har-<br>monics at 0 dBm output pow-<br>er, Conducted measurement,<br>Test Frequency = 908.4 MHz|SPURHARM_FCC|In non-restricted bands, per FCC<br>47 CFR §15.2313|—|-54|-20|dBc|
|||In restricted bands, per FCC 47<br>CFR §15.205 & §15.20945|—|-54|-41.2|dBm|
|Spurious emissions out-of-<br>band at 0 dBm output power,<br>Conducted measurement,<br>Test Frequency = 908.4 MHz|SPUROOB_FCC|In non-restricted bands, per FCC<br>47 CFR §15.2313|—|-61|-20|dBc|
|||In restricted bands (30-88<br>MHz),per FCC 47 CFR §15.205 &<br>§15.2094 5|—|-69|-55.2|dBm|
|||In restricted bands (88-216 MHz),<br>per FCC 47 CFR §15.205 &<br>§15.2094 5|—|-69|-51.7|dBm|
|||In restricted bands (216-960<br>MHz), per FCC 47 CFR §15.205<br>& §15.2094 5|—|-67|-49.2|dBm|
|||In restricted bands (>960 MHz),<br>per FCC 47 CFR §15.205 &<br>§15.2094 5|—|-59|-42|dBm|
|**Note:**<br>1. The transmit power for the 902 MHz to 928 Band MHz is normally limited to +0 dBm when frequency hopping or DSSS is not<br>used.<br>2. The maximum output power can go up to the maximum rating. Emissions are tested with the output power set to 0 dBm.<br>3. FCC Title 47 CFR Part 15 Section 15.231 Periodic operation in the band 40.66-40.70 MHz and above 70 MHz.<br>4. FCC Title 47 CFR Part 15 Section 15.205 Restricted bands of operation.<br>5. FCC Title 47 CFR Part 15 Section 15.209 Radiated emission limits; general requirements.|||||||
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ZGM230S Z-Wave 800 SiP Module Data Sheet Electrical Specifications
## **4.5.1.3 915 MHz Band +14 dBm RF Transmitter Characteristics for Z-Wave**
Unless otherwise indicated, typical conditions are: TA = 25 °C, VREGVDD = IOVDD = 3.3 V, Crystal frequency= 39.0 MHz. RF center frequency 912 MHz.
**Table 4.9. 915 MHz Band +14 dBm RF Transmitter Characteristics for Z-Wave**
|**Parameter**|**Symbol**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|RF test frequency range|FRANGE||902|—|928|MHz|
|Maximum TX Power|POUTMAX|14 dBm output power1|14.7|14.8|14.9|dBm|
|Minimum active TX Power|POUTMIN||-24.5|-24.3|—|dBm|
|Output power variation vs<br>supply at POUTMAX|POUTVAR_V|1.8 V < VVREGVDD< 3.3 V, T = 25<br>°C|—|0.02|—|dB|
|Output power variation vs<br>temperature, peak to peak|POUTVAR_T|TA= -40 to +85 °C|—|0.5|1|dB|
|Output power variation vs RF<br>frequency|POUTVAR_F|TA= 25 °C|—|0.1|0.6|dB|
|Spurious emissions of har-<br>monics at +14 dBm output<br>power, Conducted measure-<br>ment, Test Frequency = 912<br>MHz|SPURHARM_FCC<br>_14|In restricted bands, per FCC 47<br>CFR §15.205 & §15.20923|—|-52|-51|dBm|
|||In non-restricted bands, per FCC<br>47 CFR §15.2314|—|-62|-20|dBc|
|Spurious emissions out-of-<br>band at +14 dB output pow-<br>er, Conducted measurement,<br>Test Frequency = 912 MHz|SPUROOB_FCC_<br>14|In non-restricted bands, per FCC<br>47 CFR §15.2314|—|-69|-20|dBc|
|||In restricted bands (30-88<br>MHz),per FCC 47 CFR §15.205 &<br>§15.2092 3|—|-68.3|-55.2|dBm|
|||In restricted bands (88-216 MHz),<br>per FCC 47 CFR §15.205 &<br>§15.2092 3|—|-68.3|-51.7|dBm|
|||In restricted bands (216-960<br>MHz), per FCC 47 CFR §15.205<br>& §15.2092 3|—|-66|-49.2|dBm|
|||In restricted bands (>960 MHz),<br>per FCC 47 CFR §15.205 &<br>§15.2092 3|—|-56.4|-41.2|dBm|
|Error Vector Magnitude, Off-<br>set at +14 dBm output power|EVM|Reference Signal is 100 kbps<br>DSSS-OQPSK, continuous pseu-<br>do random binary sequence.<br>Modulated according to Z-Wave<br>Long Range PHY/MAC Layer<br>specification from the Z-Wave Alli-<br>ance|—|0.31|0.32|%rms|
|Power spectral density limit|PSD14|PSD per FCC Part 15.247, 100<br>kbps O-QPSK|—|-0.31|—|dBm/<br>3kHz|
|**Note:**<br>1. The maximum output power can go up to the maximum rating. Emissions are tested with the output power set to 14 dBm.<br>2. FCC Title 47 CFR Part 15 Section 15.205 Restricted bands of operation.<br>3. FCC Title 47 CFR Part 15 Section 15.209 Radiated emission limits; general requirements.<br>4. FCC Title 47 CFR Part 15 Section 15.231 Periodic operation in the band 40.66-40.70 MHz and above 70 MHz.|||||||
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ZGM230S Z-Wave 800 SiP Module Data Sheet Electrical Specifications
## **4.5.2 RF Receiver Characteristics**
## **4.5.2.1 868 MHz Band RF Receiver Characteristics for Z-Wave**
Unless otherwise indicated, typical conditions are: TA = 25 °C, VREGVDD = IOVDD = 3.3 V, Crystal frequency= 39.0 MHz. RF center frequency 868.4 MHz
**Table 4.10. 868 MHz Band RF Receiver Characteristics for Z-Wave**
|**Parameter**|**Symbol**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|RF test frequency range|FRANGE||863|—|870|MHz|
|Max usable input level, 1%<br>FER|SAT100k|Desired is reference 100 kbps<br>GFSK signal1|—|—|10.0|dBm|
|Sensitivity|SENS|Desired is reference 9.6 kbps<br>2FSK signal2, 1% FER, frequency<br>= 868.42 MHz, T ≤ 85 °C|—|-110|—|dBm|
|||Desired is reference 40 kbps<br>2FSK signal3, 1% FER, frequency<br>= 868.4 MHz, T ≤ 85 °C|—|-110|—|dBm|
|||Desired is reference 100 kbps<br>GFSK signal1, 1% FER, frequen-<br>cy = 869.85 MHz, T ≤ 85 °C|—|-108.8|—|dBm|
|Image rejection, Interferer is<br>CW at image frequency|C/IIMAGE|Desired is reference 9.6 kbps<br>2FSK signal2at 3dB above sensi-<br>tivity level, 1% FER, frequency =<br>868.42 MHz|—|49.6|—|dB|
|||Desired is reference 40 kbps<br>2FSK signal3at 3dB above sensi-<br>tivity level, 1% FER, frequency =<br>868.4 MHz|—|49.8|—|dB|
|||Desired is 100kbps GFSK signal1<br>at 3dB above sensitivity level, 1%<br>FER, frequency = 869.85 MHz|—|48.1|—|dB|
|Blocking selectivity, 1% FER.<br>Desired is 9.6 kbps 2FSK<br>signal2at 3 dB above sensi-<br>tivity level, frequency =<br>868.42 MHz|C/IBLOCKER_9p6|Interferer CW at Desired ± 1 MHz|—|59.4|—|dB|
|||Interferer CW at Desired ± 2 MHz|—|64.2|—|dB|
|||Interferer CW at Desired ± 5 MHz|—|73.7|—|dB|
|||Interferer CW at Desired ± 10<br>MHz|—|79.6|—|dB|
|||Interferer CW at Desired ± 100<br>MHz|—|83.3|—|dB|
|Blocking selectivity, 1% FER.<br>Desired is 40 kbps 2FSK sig-<br>nal3at 3 dB above sensitivity<br>level, frequency = 868.4<br>MHz|C/IBLOCKER_40|Interferer CW at Desired ± 1 MHz|—|59.7|—|dB|
|||Interferer CW at Desired ± 2 MHz|—|64.3|—|dB|
|||Interferer CW at Desired ± 5 MHz|—|74.0|—|dB|
|||Interferer CW at Desired ± 10<br>MHz|—|79.8|—|dB|
|||Interferer CW at Desired ± 100<br>MHz|—|83.8|—|dB|
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ZGM230S Z-Wave 800 SiP Module Data Sheet
Electrical Specifications
|**Parameter**|**Symbol**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|Blocking selectivity, 1% FER.<br>Desired is 100 kbps GFSK<br>signal1at 3 dB above sensi-<br>tivity level, frequency =<br>869.85 MHz|C/IBLOCKER_100|Interferer CW at Desired ± 1 MHz|—|48.1|—|dB|
|||Interferer CW at Desired ± 2 MHz|—|63.4|—|dB|
|||Interferer CW at Desired ± 5 MHz|—|72.6|—|dB|
|||Interferer CW at Desired ± 10<br>MHz|—|78.3|—|dB|
|||Interferer CW at Desired ± 100<br>MHz|—|80.6|—|dB|
|Lower limit of input power<br>range over which RSSI reso-<br>lution is maintained|RSSIMIN||-90.0|—|—|dBm|
|Upper limit of input power<br>range over which RSSI reso-<br>lution is maintained|RSSIMAX||—|—|10|dBm|
|RSSI resolution|RSSIRES|Over RSSIMINto RSSIMAXrange|—|0.25|—|dB|
|Max spurious emissions dur-<br>ing active receive mode|SPURRX|30 MHz to 1 GHz|—|-81.7|-57|dBm|
|||1 GHz to 12 GHz|—|-68|-47|dBm|
|**Note:**<br>1. Definition of reference signal is 100 kbps 2GFSK, BT=0.6, Δf = 58 kHz, NRZ, '0' = F_center + Δf/2, '1' = F_center - Δf/2<br>2. Definition of reference signal is 9.6 kbps 2FSK, Δf = 40 kHz, Manchester, '0' = Transition from (F_center + Δf/2), '1' = Transition<br>from (F_center - Δf/2)<br>3. Definition of reference signal is 40 kbps 2FSK, Δf = 40 kHz, NRZ, '0' = F_center + Δf/2, '1' = F_center - Δf/2|||||||
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ZGM230S Z-Wave 800 SiP Module Data Sheet Electrical Specifications
## **4.5.2.2 915 MHz Band RF Receiver Characteristics for Z-Wave**
Unless otherwise indicated, typical conditions are: TA = 25 °C, VREGVDD = IOVDD = 3.3 V, Crystal frequency= 39.0 MHz. RF center frequency 916 MHz
**Table 4.11. 915 MHz Band RF Receiver Characteristics for Z-Wave**
|**Parameter**|**Symbol**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|RF test frequency range|FRANGE||902|—|928|MHz|
|Max usable input level, 1%<br>FER|SAT100K|Desired is reference 100 kbps<br>GFSK signal1|—|—|10.0|dBm|
|Sensitivity|SENS|Desired is reference 9.6 kbps<br>2FSK signal2, 1% FER, frequency<br>= 908.42 MHz, T ≤ 85 °C|—|-109.4|—|dBm|
|||Desired is reference 40 kbps<br>2FSK signal3, 1% FER, frequency<br>= 908.4 MHz, T ≤ 85 °C|—|-109.7|—|dBm|
|||Desired is reference 100 kbps<br>GFSK signal1, 1% FER, frequen-<br>cy = 916 MHz, T ≤ 85 °C|—|-108.3|—|dBm|
|||Desired is reference 100 kbps O-<br>QPSK signal4, 1% FER, frequen-<br>cy = 912 MHz, T ≤ 85 °C|—|-110.9|—|dBm|
|Image rejection, Interferer is<br>CW at image frequency|C/IIMAGE|Desired is reference 9.6 kbps<br>2FSK signal2at 3dB above sensi-<br>tivity level, 1% FER, frequency =<br>908.42 MHz|—|50.7|—|dB|
|||Desired is reference 40 kbps<br>2FSK signal3at 3dB above sensi-<br>tivity level, 1% FER, frequency =<br>908.4 MHz|—|50.9|—|dB|
|||Desired is 100 kbps GFSK signal1<br>at 3dB above sensitivity level, 1%<br>FER, frequency = 916 MHz|—|49.6|—|dB|
|||Desired is reference 100 kbps O-<br>QPSK signal4, 1% FER, frequen-<br>cy = 912 MHz|—|53.3|—|dB|
|Blocking selectivity, 1% FER.<br>Desired is 9.6 kbps 2FSK<br>signal2at 3dB above sensi-<br>tivity level, frequency =<br>908.42 MHz|C/IBLOCKER_9p6|Interferer CW at Desired ± 1 MHz|—|58.7|—|dB|
|||Interferer CW at Desired ± 2 MHz|—|63.5|—|dB|
|||Interferer CW at Desired ± 5 MHz|—|73.0|—|dB|
|||Interferer CW at Desired ± 10<br>MHz|—|79.0|—|dB|
|||Interferer CW at Desired ± 100<br>MHz|—|82.5|—|dB|
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ZGM230S Z-Wave 800 SiP Module Data Sheet
Electrical Specifications
|**Parameter**|**Symbol**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|Blocking selectivity, 1% FER.<br>Desired is 40 kbps 2FSK sig-<br>nal3at 3dB above sensitivity<br>level, frequency = 908.4<br>MHz|C/IBLOCKER_40|Interferer CW at Desired ± 1 MHz|—|59.3|—|dB|
|||Interferer CW at Desired ± 2 MHz|—|63.7|—|dB|
|||Interferer CW at Desired ± 5 MHz|—|73.6|—|dB|
|||Interferer CW at Desired ± 10<br>MHz|—|79.4|—|dB|
|||Interferer CW at Desired ± 100<br>MHz|—|82.1|—|dB|
|Blocking selectivity, 1% FER.<br>Desired is 100 kbps GFSK<br>signal1at 3dB above sensi-<br>tivity level, frequency = 916<br>MHz|C/IBLOCKER_100|Interferer CW at Desired ± 1 MHz|—|49.6|—|dB|
|||Interferer CW at Desired ± 2 MHz|—|63.1|—|dB|
|||Interferer CW at Desired ± 5 MHz|—|72.3|—|dB|
|||Interferer CW at Desired ± 10<br>MHz|—|78.0|—|dB|
|||Interferer CW at Desired ± 100<br>MHz|—|80.3|—|dB|
|Blocking selectivity, 1% FER.<br>Desired is reference 100<br>kbps O-QPSK signal4, 1%<br>FER, frequency = 912 MHz,<br>P_in = -89 dBm|C/BLOCK-<br>EROQPSK|Interferer CW at Desired ± 2 MHz|—|58.4|—|dB|
|||Interferer CW at Desired ± 5 MHz|—|72.2|—|dB|
|||Interferer CW at Desired ± 10<br>MHz|—|78.9|—|dB|
|||Interferer CW at Desired ± 100<br>MHz|—|84.3|—|dB|
|Intermod selectivity, 1%<br>FER. CW interferers at 400<br>kHz and 800 kHz offsets|C/IIM|Desired is 100 kbps GFSK signal1<br>at 3dB above sensitivity level|—|43.4|—|dB|
|Lower limit of input power<br>range over which RSSI reso-<br>lution is maintained|RSSIMIN||-90.0|—|—|dBm|
|Upper limit of input power<br>range over which RSSI reso-<br>lution is maintained|RSSIMAX||—|—|10.0|dBm|
|RSSI resolution|RSSIRES|Over RSSIMINto RSSIMAXrange|—|0.25|—|dB|
|Max spurious emissions dur-<br>ing active receive mode, per<br>FCC Part 15.109(a)|SPURRX_FCC|216-960 MHz|—|-81.7|-49.2|dBm|
|||Above 960 MHz|—|-78.7|-41.2|dBm|
|**Note:**<br>1. Definition of reference signal is 100 kbps 2GFSK, BT=0.6, Δf = 58 kHz, NRZ, '0' = F_center + Δf/2, '1' = F_center - Δf/2<br>2. Definition of reference signal is 9.6 kbps 2FSK, Δf = 40 kHz, Manchester, '0' = Transition from (F_center + Δf/2), '1' = Transition<br>from (F_center - Δf/2)<br>3. Definition of reference signal is 40 kbps 2FSK, Δf = 40 kHz, NRZ, '0' = F_center + Δf/2, '1' = F_center - Δf/2<br>4. Definition of reference signal is 100 kbps O-QPSK, 800 kcps chip rate, 8x spreading factor, 32 bit chip length, 4 bits per symbol|||||||
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ZGM230S Z-Wave 800 SiP Module Data Sheet Electrical Specifications
## **4.6 High-Frequency Crystal**
## **Table 4.12. High-Frequency Crystal**
|**Parameter**|**Symbol**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|Crystal frequency|fHFXTAL||—|39.0|—|MHz|
|Initial calibrated accuracy|ACCHFXTAL||-3|—|3|ppm|
|Aging|AGINGHFXTAL||-2|—|2|ppm/5<br>years|
|Temperature drift|DRIFTHFXTAL|Across specified temperature<br>range|-16|—|16|ppm|
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ZGM230S Z-Wave 800 SiP Module Data Sheet Electrical Specifications
## **4.7 GPIO Pins**
## **Table 4.13. GPIO Pins**
|**Parameter**|**Symbol**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|Leakage current|ILEAK_IO|MODEx = DISABLED, IOVDD =<br>1.8 V|—|1.9|—|nA|
|||MODEx = DISABLED, IOVDD =<br>3.3 V|—|2.5|—|nA|
|||LCD segment and common pins,<br>IOVDD = 2.7 V, VLCD = 3.6 V, TA<br>= 85 °C1|—|—|TBD|nA|
|Input low voltage2|VIL|Any GPIO pin|—|—|0.3*IOVDD|V|
|||RESETn|—|—|0.3*DVDD|V|
|Input high voltage2|VIH|Any GPIO pin|0.7*IOVDD|—|—|V|
|||RESETn|0.7*DVDD|—|—|V|
|Hysteresis of input voltage|VHYS|Any GPIO pin|0.05*IOVD<br>D|—|—|V|
|||RESETn|0.05*DVDD|—|—|V|
|Output high voltage|VOH|Sourcing 20mA, IOVDD = 3.3 V|0.8 *<br>IOVDD|—|—|V|
|||Sourcing 8mA, IOVDD = 1.8 V|0.6 *<br>IOVDD|—|—|V|
|Output low voltage|VOL|Sinking 20mA, IOVDD = 3.3 V|—|—|0.2 *<br>IOVDD|V|
|||Sinking 8mA, IOVDD = 1.8 V|—|—|0.4 *<br>IOVDD|V|
|GPIO rise time|TGPIO_RISE|IOVDD = 3.3 V, Cload= 50pF,<br>SLEWRATE = 4, 10% to 90%|—|8.4|—|ns|
|||IOVDD = 1.8 V, Cload= 50pF,<br>SLEWRATE = 4, 10% to 90%|—|13|—|ns|
|GPIO fall time|TGPIO_FALL|IOVDD = 3.3 V, Cload= 50pF,<br>SLEWRATE = 4, 90% to 10%|—|7.1|—|ns|
|||IOVDD = 1.8 V, Cload= 50pF,<br>SLEWRATE = 4, 90% to 10%|—|11.9|—|ns|
|Pull up/down resistance3|RPULL|Any GPIO pin. Pull-up to IOVDD:<br>MODEn = DISABLE DOUT=1.<br>Pull-down to VSS: MODEn =<br>WIREDORPULLDOWN DOUT =<br>0.|33|44|55|kΩ|
|||RESETn pin. Pull-up to DVDD|33|44|55|kΩ|
|Maximum filtered glitch width|TGF|MODE = INPUT, DOUT = 1|—|27|—|ns|
|RESETn low time to ensure<br>pin reset|TRESET||100|—|—|ns|
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ZGM230S Z-Wave 800 SiP Module Data Sheet Electrical Specifications
|**Parameter**|**Symbol**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|**Note:**<br>1. MODEx = DISABLED, LCD pins selected by setting the corresponding bits in the VGPIO_SEG or GPIO_COM register.<br>2. GPIO input thresholds are proportional to the IOVDD pin. RESETn input thresholds are proportional to DVDD, which is generated<br>by the DC-DC converter. DVDD is equal to 1.8 V when DC-DC is active and bypassed to VREGVDD when DC-DC is inactive.<br>3. GPIO pull-ups connect to IOVDD supply, pull-downs connect to VSS. RESETn pull-up connects to DVDD, which is generated by<br>the DC-DC converter. DVDD is equal to 1.8 V when DC-DC is active and bypassed to VREGVDD when DC-DC is inactive.|||||||
## **4.8 Microcontroller Peripherals**
The MCU peripherals set available in ZGM230S modules includes:
- 12-bit 1 Msps or 16-bit 76.9 ksps SAR Analog to Digital Converter (ADC)
- 2 × Analog Comparator (ACMP)
- 2 × 12-bit 500 ksps Digital to Analog Converter (VDAC)
- Low-Energy Sensor Interface (LESENSE)
- Up to 34 General Purpose I/O pins with output state retention and asynchronous interrupts
- 8 Channel DMA Controller
- 12 Channel Peripheral Reflex System (PRS)
- 4 × 16-bit Timer/Counter with 3 Compare/Capture/PWM channels
- 1 × 32-bit Timer/Counter with 3 Compare/Capture/PWM channels
- 32-bit Real Time Counter
- 24-bit Low Energy Timer for waveform generation
- 2 × Watchdog Timer
- 2× Enhanced Universal Synchronous/Asynchronous Receiver/Transmitter (EUSART)
- 1× Universal Synchronous/Asynchronous Receiver/Transmitter (UART/SPI/SmartCard (ISO 7816)/IrDA/I[2] S)
- 2 × I[2] C interface with SMBus support
- Integrated Low-Energy LCD Controller supporting up to 80 segments
- Die temperature sensor
For details on their electrical performance, see the relevant portions of Section 4 in the EFR32ZG23 SoC data sheet.
To learn which GPIO ports provide access to every peripheral, see 6.3 Analog Peripheral Connectivity and 6.4 Digital Peripheral Connectivity.
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ZGM230S Z-Wave 800 SiP Module Data Sheet Reference Diagrams
## **5. Reference Diagrams**
## **5.1 Standalone Application**
If the ZGM230S SiP module is going to be used in an application without any host CPU system, e.g., in an end-device application such as a sensor, a light switch/dimmer, or a simple controller application such as a remote control, the typical connections to note are shown in the figure below.
**==> picture [345 x 243] intentionally omitted <==**
**----- Start of picture text -----**<br>
MINI SIMPLICITY DEBUG CONNECTOR<br>VDD<br>1 2<br>3 4<br>RESETn VCOM_RX<br>5 6<br>VCOM_TX SWO<br>7 8<br>RESETn RESETn PD00 SWDIO SWLCK<br>9 10<br>GND PD01 PTI_FRAME PTI_DATA<br>ANTENNA<br>RFIO PD02<br>MATCHING ZGM230S<br>GND PD03<br>PB06 PD04 PTI_DATA<br>PB05 GND PD05 PTI_FRAME<br>PB04 GND (Optional) VDD<br>PB03 IOVDD<br>PB02 VREGVDD<br>PB01 VDCDC<br>PB00 PA10 10µF 10µF<br>SWCLK<br>SWDIO<br>SWO<br>GND PC09 PC08 PC07 PC06 PC05 PC04 PC03 PC02 PC01 PC00<br>PA00 PA01 PA02 PA03 PA04 PA05 DECOUPLE PA06 PA07 PA08 PA09<br>**----- End of picture text -----**<br>
**Figure 5.1. Typical Connections for a Standalone Application**
**Power Supplies** : The two power supply pins of the SiP module: IOVDD and VREGVDD, should each be decoupled using a minimum of 10 µF. For applications with quiet GPIO activity, a single 10 µF cap can be used to decouple both IOVDD and VREGVDD. All ground connections on the SiP module should be connected to a common ground plane.
**Note:** The pins called “DECOUPLE” and “VDCDC” are internal test connections and they must be left “not connected”.
**Flash Programming Connections** : The application program of the ZGM230S can be programmed in two ways:
- _Offline Programming_ : Where the flash memory of the SiP modules is programmed by an external programming rig prior of product assembly.
- _Inline Programming_ : Where the product is assembled and then the application program is downloaded to the flash program memory of the SiP module.
In the latter case, inline programming, the programming interface: RESETn, SWDIO, SWCLK, SWO and the supply/ground must be made available for the programming rig. This can be implemented as test-pads on the application PCB accessible for a bed-of-nails, or the programming interface can be realized in form of a Mini Simplicity header or the footprint of a Mini Simplicity header.
The Packet Trace Interface, which can be used in RF debugging to analyze received RF packets, can also be made available in the application hardware.
For additional details on programming and debugging interfaces supported by Silicon Labs products, refer to AN958: Debugging and Programming Interfaces for Custom Designs.
**RF Interface** : The RF interface of the ZGM230S SiP module is a 50Ω matched pin, “RFIO,” which must be connected to an antenna for the RF energy to be radiated / received. The antenna can either be a PCB-trace antenna or an external antenna like a whip antenna or a piece of bent wire. If the antenna is naturally matched to 50Ω, no matching circuit is needed, but in the cases where the antenna does not have a 50Ω impedance, a matching circuit must be implemented to ensure impedance matching between the antenna and the RFIO pin of the SiP module. See Section 7. Design Guidelines for more information about where to place the SiP module on the host PCB and to learn how the antenna can be implemented.
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ZGM230S Z-Wave 800 SiP Module Data Sheet Reference Diagrams
## **5.2 Network Co-Processor (NCP) Application with UART Host**
If the ZGM230S SiP module is going to be used in an application with a Host CPU, e.g., a smart home gateway, an advanced door lock, etc., the typical connections to note are shown in the figure below.
**==> picture [365 x 221] intentionally omitted <==**
**----- Start of picture text -----**<br>
VDD<br>GPIO<br>RESETn RESETn PD00 RESETn<br>GND PD01 Host CPU<br>ANTENNA TX RX<br>RFIO PD02 system<br>MATCHING ZGM230S RX TX<br>GND PD03<br>PB06 PD04 PTI_DATA<br>PB05 GND PD05 PTI_FRAME<br>PB04 GND (Optional)<br>PB03 IOVDD<br>PB02 VREGVDD<br>PB01 VDCDC<br>PB00 PA10 10µF 10µF<br>SWCLK TX<br>SWDIO RX<br>SWO<br>GND PC09 PC08 PC07 PC06 PC05 PC04 PC03 PC02 PC01 PC00<br>PA00 PA01 PA02 PA03 PA04 PA05 DECOUPLE PA06 PA07 PA08 PA09<br>**----- End of picture text -----**<br>
**Figure 5.2. Typical ZGM230S Host CPU Connections**
**Communication Lines** : In many applications, the UART is the means of communication between the Host CPU and the ZGM230S. The location of the UART pins of the ZGM230S is software configurable, and if handshake signals are required, this can be enabled too, but in its most simple form, only the RX and TX pins are required for the UART communication.
**Power Supplies** : The two power supply pins of the SiP module: IOVDD and VREGVDD, should each be decoupled using a minimum of 10 µF, and since the Host CPU system and the ZGM230S SiP module share supply lines, care must be taken to avoid supply noise being coupled from the Host CPU system to the ZGM230S. It is therefore important that the Host CPU system has adequate supply noise suppression. All ground connections on the SiP module should be connected to a common ground plane shared with the Host CPU.
**Note:** The pins called “DECOUPLE” and “VDCDC” are internal test connections, and they must be left “not connected”.
**Flash Programming Connections** : The application program of the ZGM230S can be programmed in three ways:
- _Offline Programming_ : Where the flash memory of the SiP modules is programmed by an external programming rig prior of product assembly.
- _Inline Programming_ : Where the product is assembled and then the application program is downloaded to the flash program memory of the SiP module. For inline programming, the programming interface: RESETn, SWDIO, SWCLK, SWO, and the supply/ground must be made available for the programming rig by some means, e.g., test-pads on the PCB.
- _Host CPU Programming_ : Where GPIO’s of the Host CPU are connected to the programming interface of the ZGM230S module. This enables in-field upgrade possibilities, where the Host CPU can re-program the flash program memory of the ZGM230S.
In the latter case, Host CPU programming, the programming interface: RESETn, SWDIO, SWCLK, and SWO must be connected to GPIOs of the Host CPU.
**RF Interface** : The RF interface of the ZGM230S SiP module is a 50Ω matched pin, “RFIO,” which must be connected to an antenna for the RF energy to be radiated / received. The antenna can either be a PCB-trace antenna or an external antenna like a whip antenna or a piece of bent wire. If the antenna is naturally matched to 50Ω, no matching circuit is needed, but in the cases where the antenna does not have a 50Ω impedance, a matching circuit must be implemented in order to ensure impedance matching between the antenna and the RFIO pin of the SiP module. See Section 7. Design Guidelines for more information about where to place the SiP module on the host PCB and to learn how the antenna can be implemented.
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ZGM230S Z-Wave 800 SiP Module Data Sheet Pin Definitions
## **6. Pin Definitions**
## **6.1 Module Pinout**
**==> picture [432 x 325] intentionally omitted <==**
**Figure 6.1. ZGM230S Module Pinout**
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the supported features for each GPIO pin, see 6.2 Alternate Pin Functions, 6.3 Analog Peripheral Connectivity, and 6.4 Digital Peripheral Connectivity.
Note that GPIO and Peripheral capabilities may differ by part number or be limited by the API or software stack.
**Table 6.1. ZGM230S SiP Module Pin Definitions**
|**Pin Name**|**Pin(s)**|**Description**|**Pin Name**|**Pin(s)**|**Description**|
|---|---|---|---|---|---|
|RESETn|1|Reset Pin. The RESETn pin is internally<br>pulled up to the DVDD supply on the<br>SoC.|GND|2|Ground|
|RFIO|3|RF input/output|GND|4|Ground|
|PB06|5|GPIO|PB05|6|GPIO|
|PB04|7|GPIO|PB03|8|GPIO|
|PB02|9|GPIO|PB01|10|GPIO|
|PB00|11|GPIO|PA00|12|GPIO|
|PA01|13|GPIO|PA02|14|GPIO|
|PA03|15|GPIO|PA04|16|GPIO|
|PA05|17|GPIO|DECOUPLE|18|Do Not Connect|
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ZGM230S Z-Wave 800 SiP Module Data Sheet Pin Definitions
|**Pin Name**|**Pin(s)**|**Description**||**Pin Name**|**Pin(s)**|**Description**|
|---|---|---|---|---|---|---|
|PA06|19|GPIO||PA07|20|GPIO|
|PA08|21|GPIO||PA09|22|GPIO|
|PA10|23|GPIO||VDCDC|24|Do Not Connect|
|VREGVDD|25|Module input power supply.||IOVDD|26|Module I/O pin supply. This pin is inter-<br>nally connected to the SoC IOVDD and<br>AVDD supply lines.|
|GND|27|Ground||PD05|28|GPIO|
|PD04|29|GPIO||PD03|30|GPIO|
|PD02|31|GPIO||PD01|32|GPIO|
|PD00|33|GPIO||PC00|34|GPIO|
|PC01|35|GPIO||PC02|36|GPIO|
|PC03|37|GPIO||PC04|38|GPIO|
|PC05|39|GPIO||PC06|40|GPIO|
|PC07|41|GPIO||PC08|42|GPIO|
|PC09|43|GPIO||GND|44|Ground|
|GND|45|Ground||GND|46|Ground|
|GND|47|Ground||GND|48|Ground|
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ZGM230S Z-Wave 800 SiP Module Data Sheet Pin Definitions
## **6.2 Alternate Pin Functions**
Some GPIOs support alternate functions like debugging, wake-up from EM4, external low frequency crystal access, etc. The following table shows which module pins have alternate capabilities and the functions they support.
**Table 6.2. GPIO Alternate Function Table**
|**GPIO**|**Alternate Functions**|**Alternate Functions**|**Alternate Functions**|**Alternate Functions**|
|---|---|---|---|---|
|PB03|GPIO.EM4WU4||LCD.SEG17||
|PB02|||LCD.SEG16||
|PB01|GPIO.EM4WU3|VDAC0.CH1_MAIN_OUT|LCD.SEG15||
|PB00||VDAC0.CH0_MAIN_OUT|LCD.SEG14||
|PA00||IADC0.VREFP|LCD.SEG8||
|PA01|GPIO.SWCLK||LCD.SEG9||
|PA02|GPIO.SWDIO||||
|PA03|GPIO.SWV<br>GPIO.TDO<br>GPIO.TRACEDATA0|LESENSE.LESENSE_EN_0|||
|PA04|GPIO.TDI<br>GPIO.TRACECLK|LESENSE.LESENSE_EN_1|LCD.SEG10||
|PA05|GPIO.TRACEDATA1<br>GPIO.EM4WU0|LESENSE.LESENSE_EN_2|LCD.SEG11||
|PA06|GPIO.TRACEDATA2||LCD.LCD_CP||
|PA07|GPIO.TRACEDATA3||LCD.SEG12||
|PA08|||LCD.SEG13||
|PD05|GPIO.EM4WU10||LCD.COM3||
|PD04|||LCD.COM2||
|PD03|||LCD.COM1||
|PD02|GPIO.EM4WU9||LCD.COM0||
|PD01||LFXO.LFXTAL_I<br>LFXO.LF_EXTCLK|||
|PD00||LFXO.LFXTAL_O|||
|PC00|GPIO.EM4WU6||LCD.SEG0||
|PC01|||LCD.SEG1||
|PC02|||LCD.SEG2||
|PC03|||LCD.SEG3||
|PC04|||LCD.SEG4||
|PC05|GPIO.EM4WU7||LCD.SEG5||
|PC06|||LCD.SEG6||
|PC07|GPIO.EM4WU8||LCD.SEG7||
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ZGM230S Z-Wave 800 SiP Module Data Sheet
Pin Definitions
|**GPIO**|**Alternate Functions**|**Alternate Functions**|**Alternate Functions**|**Alternate Functions**|
|---|---|---|---|---|
|PC08|||LCD.SEG18||
|PC09|GPIO.THMSW_EN||LCD.SEG19||
## **6.3 Analog Peripheral Connectivity**
Many analog resources are routable and can be connected to numerous GPIOs. The table below indicates which peripherals are avaliable on each GPIO port. When a differential connection is used, Positive inputs are restricted to the EVEN pins and Negative inputs are restricted to the ODD pins. When a single ended connection is used, positive input is avaliable on all pins. See the device Reference Manual for more details on the ABUS and analog peripherals.
## **Table 6.3. ABUS Routing Table**
|**Peripheral**|**Signal**|**PA**|**PA**|**PB**|**PB**|**PC**|**PC**|**PD**|**PD**|
|---|---|---|---|---|---|---|---|---|---|
|||**EVEN**|**ODD**|**EVEN**|**ODD**|**EVEN**|**ODD**|**EVEN**|**ODD**|
|ACMP0|ANA_NEG|Yes|Yes|Yes|Yes|Yes|Yes|Yes|Yes|
||ANA_POS|Yes|Yes|Yes|Yes|Yes|Yes|Yes|Yes|
|ACMP1|ANA_NEG|Yes|Yes|Yes|Yes|Yes|Yes|Yes|Yes|
||ANA_POS|Yes|Yes|Yes|Yes|Yes|Yes|Yes|Yes|
|IADC0|ANA_NEG|Yes|Yes|Yes|Yes|Yes|Yes|Yes|Yes|
||ANA_POS|Yes|Yes|Yes|Yes|Yes|Yes|Yes|Yes|
|VDAC0|CH0_ABUS_OUT|Yes|Yes|Yes|Yes|Yes|Yes|Yes|Yes|
||CH1_ABUS_OUT|Yes|Yes|Yes|Yes|Yes|Yes|Yes|Yes|
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ZGM230S Z-Wave 800 SiP Module Data Sheet Pin Definitions
## **6.4 Digital Peripheral Connectivity**
Many digital resources are routable and can be connected to numerous GPIO's. The table below indicates which peripherals are avaliable on each GPIO port.
**Table 6.4. DBUS Routing Table**
|**Peripheral.Resource**|**PORT**|**PORT**|**PORT**|**PORT**|
|---|---|---|---|---|
||**PA**|**PB**|**PC**|**PD**|
|ACMP0.DIGOUT|Available|Available|Available|Available|
|ACMP1.DIGOUT|Available|Available|Available|Available|
|CMU.CLKIN0|||Available|Available|
|CMU.CLKOUT0|||Available|Available|
|CMU.CLKOUT1|||Available|Available|
|CMU.CLKOUT2|Available|Available|||
|EUSART0.CS|Available|Available|||
|EUSART0.CTS|Available|Available|||
|EUSART0.RTS|Available|Available|||
|EUSART0.RX|Available|Available|||
|EUSART0.SCLK|Available|Available|||
|EUSART0.TX|Available|Available|||
|EUSART1.CS|Available|Available|Available|Available|
|EUSART1.CTS|Available|Available|Available|Available|
|EUSART1.RTS|Available|Available|Available|Available|
|EUSART1.RX|Available|Available|Available|Available|
|EUSART1.SCLK|Available|Available|Available|Available|
|EUSART1.TX|Available|Available|Available|Available|
|EUSART2.CS|||Available|Available|
|EUSART2.CTS|||Available|Available|
|EUSART2.RTS|||Available|Available|
|EUSART2.RX|||Available|Available|
|EUSART2.SCLK|||Available|Available|
|EUSART2.TX|||Available|Available|
|FRC.DCLK|||Available|Available|
|FRC.DFRAME|||Available|Available|
|FRC.DOUT|||Available|Available|
|HFXO0.BUFOUT_REQ_IN_ASYNC|Available|Available|||
|I2C0.SCL|Available|Available|Available|Available|
|I2C0.SDA|Available|Available|Available|Available|
|I2C1.SCL|||Available|Available|
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ZGM230S Z-Wave 800 SiP Module Data Sheet
Pin Definitions
|**Peripheral.Resource**|**PORT**|**PORT**|**PORT**|**PORT**|
|---|---|---|---|---|
||**PA**|**PB**|**PC**|**PD**|
|I2C1.SDA|||Available|Available|
|KEYSCAN.COL_OUT_0|Available|Available|Available|Available|
|KEYSCAN.COL_OUT_1|Available|Available|Available|Available|
|KEYSCAN.COL_OUT_2|Available|Available|Available|Available|
|KEYSCAN.COL_OUT_3|Available|Available|Available|Available|
|KEYSCAN.COL_OUT_4|Available|Available|Available|Available|
|KEYSCAN.COL_OUT_5|Available|Available|Available|Available|
|KEYSCAN.COL_OUT_6|Available|Available|Available|Available|
|KEYSCAN.COL_OUT_7|Available|Available|Available|Available|
|KEYSCAN.ROW_SENSE_0|Available|Available|||
|KEYSCAN.ROW_SENSE_1|Available|Available|||
|KEYSCAN.ROW_SENSE_2|Available|Available|||
|KEYSCAN.ROW_SENSE_3|Available|Available|||
|KEYSCAN.ROW_SENSE_4|Available|Available|||
|KEYSCAN.ROW_SENSE_5|Available|Available|||
|LESENSE.CH0OUT|Available|Available|||
|LESENSE.CH10OUT|Available|Available|||
|LESENSE.CH11OUT|Available|Available|||
|LESENSE.CH12OUT|Available|Available|||
|LESENSE.CH13OUT|Available|Available|||
|LESENSE.CH14OUT|Available|Available|||
|LESENSE.CH15OUT|Available|Available|||
|LESENSE.CH1OUT|Available|Available|||
|LESENSE.CH2OUT|Available|Available|||
|LESENSE.CH3OUT|Available|Available|||
|LESENSE.CH4OUT|Available|Available|||
|LESENSE.CH5OUT|Available|Available|||
|LESENSE.CH6OUT|Available|Available|||
|LESENSE.CH7OUT|Available|Available|||
|LESENSE.CH8OUT|Available|Available|||
|LESENSE.CH9OUT|Available|Available|||
|LETIMER0.OUT0|Available|Available|||
|LETIMER0.OUT1|Available|Available|||
|MODEM.ANT0|Available|Available|Available|Available|
|MODEM.ANT1|Available|Available|Available|Available|
|MODEM.ANT_ROLL_OVER|||Available|Available|
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ZGM230S Z-Wave 800 SiP Module Data Sheet
Pin Definitions
|**Peripheral.Resource**|**PORT**|**PORT**|**PORT**|**PORT**|
|---|---|---|---|---|
||**PA**|**PB**|**PC**|**PD**|
|MODEM.ANT_RR0|||Available|Available|
|MODEM.ANT_RR1|||Available|Available|
|MODEM.ANT_RR2|||Available|Available|
|MODEM.ANT_RR3|||Available|Available|
|MODEM.ANT_RR4|||Available|Available|
|MODEM.ANT_RR5|||Available|Available|
|MODEM.ANT_SW_EN|||Available|Available|
|MODEM.ANT_SW_US|||Available|Available|
|MODEM.ANT_TRIG|||Available|Available|
|MODEM.ANT_TRIG_STOP|||Available|Available|
|MODEM.DCLK|Available|Available|||
|MODEM.DIN|Available|Available|||
|MODEM.DOUT|Available|Available|||
|PCNT0.S0IN|Available|Available|||
|PCNT0.S1IN|Available|Available|||
|PRS.ASYNCH0|Available|Available|||
|PRS.ASYNCH1|Available|Available|||
|PRS.ASYNCH10|||Available|Available|
|PRS.ASYNCH11|||Available|Available|
|PRS.ASYNCH2|Available|Available|||
|PRS.ASYNCH3|Available|Available|||
|PRS.ASYNCH4|Available|Available|||
|PRS.ASYNCH5|Available|Available|||
|PRS.ASYNCH6|||Available|Available|
|PRS.ASYNCH7|||Available|Available|
|PRS.ASYNCH8|||Available|Available|
|PRS.ASYNCH9|||Available|Available|
|PRS.SYNCH0|Available|Available|Available|Available|
|PRS.SYNCH1|Available|Available|Available|Available|
|PRS.SYNCH2|Available|Available|Available|Available|
|PRS.SYNCH3|Available|Available|Available|Available|
|TIMER0.CC0|Available|Available|Available|Available|
|TIMER0.CC1|Available|Available|Available|Available|
|TIMER0.CC2|Available|Available|Available|Available|
|TIMER0.CDTI0|Available|Available|Available|Available|
|TIMER0.CDTI1|Available|Available|Available|Available|
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ZGM230S Z-Wave 800 SiP Module Data Sheet
Pin Definitions
|**Peripheral.Resource**|**PORT**|**PORT**|**PORT**|**PORT**|
|---|---|---|---|---|
||**PA**|**PB**|**PC**|**PD**|
|TIMER0.CDTI2|Available|Available|Available|Available|
|TIMER1.CC0|Available|Available|Available|Available|
|TIMER1.CC1|Available|Available|Available|Available|
|TIMER1.CC2|Available|Available|Available|Available|
|TIMER1.CDTI0|Available|Available|Available|Available|
|TIMER1.CDTI1|Available|Available|Available|Available|
|TIMER1.CDTI2|Available|Available|Available|Available|
|TIMER2.CC0|Available|Available|||
|TIMER2.CC1|Available|Available|||
|TIMER2.CC2|Available|Available|||
|TIMER2.CDTI0|Available|Available|||
|TIMER2.CDTI1|Available|Available|||
|TIMER2.CDTI2|Available|Available|||
|TIMER3.CC0|||Available|Available|
|TIMER3.CC1|||Available|Available|
|TIMER3.CC2|||Available|Available|
|TIMER3.CDTI0|||Available|Available|
|TIMER3.CDTI1|||Available|Available|
|TIMER3.CDTI2|||Available|Available|
|TIMER4.CC0|Available|Available|||
|TIMER4.CC1|Available|Available|||
|TIMER4.CC2|Available|Available|||
|TIMER4.CDTI0|Available|Available|||
|TIMER4.CDTI1|Available|Available|||
|TIMER4.CDTI2|Available|Available|||
|USART0.CLK|Available|Available|Available|Available|
|USART0.CS|Available|Available|Available|Available|
|USART0.CTS|Available|Available|Available|Available|
|USART0.RTS|Available|Available|Available|Available|
|USART0.RX|Available|Available|Available|Available|
|USART0.TX|Available|Available|Available|Available|
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ZGM230S Z-Wave 800 SiP Module Data Sheet Design Guidelines
## **7. Design Guidelines**
## **7.1 Layout and Placement**
For in-depth information about antenna design and antenna structures, see the below application notes available from http:// www.silabs.com:
- AN853: Single-Ended Antenna Matrix Design Guide
- AN768: Antenna Selection Guide for the 868MHz EZRadio and EZRadioPRO Designs
- AN847: 915MHz Single-Ended Antenna Matrix Selection Guide
For general layout consideration and recommendations, see this application note available from http://www.silabs.com:
- AN928.2: EFR32 Series 2 Layout Design Guide
For optimal performance of the ZGM230S SiP module, use the following guidelines:
- Place the ZGM230S on the host PCB where the antenna of the ZGM230S system will have its best possible performance:
- For an external antenna type, see Figure 7.1 ZGM230S Implementation with External Antenna on page 37, the location of the ZGM230S and its antenna is fairly flexible, but as described in AN853, the performance of the antenna will depend on the ground plane of the entire application PCB.
- For a PCB trace antenna type, see Figure 7.2 ZGM230S Implementation with PCB Trace Antenna on page 37, the location of the ZGM230S and its antenna must be at a edge of the host PCB, with no copper or signal routing underneath the antenna structure and sufficient copper clearance around the antenna structure to ensure a good antenna performance. See AN853, AN768, and AN847 for detailed implementation guidelines and a description of various PCB trace antenna structures
- Place the ZGM230S and all RF traces above a solid ground plane with good via connectivity to a top layer ground plane.
- Locate the ZGM230S and the antenna / antenna structure as far away from any electrical noise sources on the host PCB as possible, such as:
- High-speed memory busses of a host CPU system
- High-power switching noise sources like switch mode power supplies, triac circuits, electric motor control circuits etc.
- Other radio systems
- Fast switching circuits
- If the antenna is external, avoid placing the antenna above the ZGM230S since the SiP module contains both fast switching signals (the crystal oscillator) and high-power switch noise sources (the DCDC circuit).
- As a general rule: Use a 50 Ω transmissions line to route the RF signal, especially if the RF trace is longer than λ/16 of the fundamental frequency, which for 868 MHz is 21.6mm and for 915 MHz is 20.6 mm. The impedance of the RF trace depends on the stack-up of the host PCB, see Figure 7.3 RF Trace Design Example on page 38.
- A U.FL connector or a SMA connector can be used to connect to an external antenna. The use of a U.FL or a SMA connector is also recommended for conductive tests. If there is not room enough for a connector foot-print in the application, ensure that there is as a minimum room enough to attached an RF pig-tail to the application in order to enable conducted measurements on the product.
- Connect all ground pads directly to a solid ground plane
- Do not place plastic or any other dielectric material in contact with the antenna
- Do not locate the antenna inside an enclosure made of an electrically conductive material.
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ZGM230S Z-Wave 800 SiP Module Data Sheet Design Guidelines
**==> picture [161 x 175] intentionally omitted <==**
**----- Start of picture text -----**<br>
External antenna<br>Matching<br>Circuit<br>50Ω transmission line<br>ZGM230S<br>**----- End of picture text -----**<br>
**Figure 7.1. ZGM230S Implementation with External Antenna**
**==> picture [195 x 128] intentionally omitted <==**
**----- Start of picture text -----**<br>
PCB trace antenna<br>Matching<br>Circuit<br>50Ω transmission line<br>ZGM230S<br>**----- End of picture text -----**<br>
**Figure 7.2. ZGM230S Implementation with PCB Trace Antenna**
Independently of the type of antenna selected, the efficiency of the antenna and the radiation pattern of the antenna depend on the surrounding ground plane. The clearance distances from an antenna structure to the ground-plane and the size of the ground plane is significant and must always be evaluated when the type of antenna to use is to be selected. See AN853: Single-Ended Antenna Matrix Design Guide for detailed information.
The impedance of the RF trace, which is the impedance of a coplanar trace above a ground plane, can be calculated using freely available web calculators:
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ZGM230S Z-Wave 800 SiP Module Data Sheet Design Guidelines
## **Figure 7.3. RF Trace Design Example**
The impedance of a PCB trace depends on the following:
- The dielectric constant of the PCB material
- The width of the RF trace
- The distance from the RF trace to the top-level ground plane
- The thickness of the PCB core material.
## **7.2 Proximity to Other Materials**
Because this will degrade the performance of the antenna, ideally, an antenna should not be:
- Surrounded by any dielectric or conductive material
- Located in close proximity to dielectric or conductive material
However, for most products with antennas, the antenna will be located inside an enclosure, so the following precautions must be taken:
- Avoid placing plastic or any other dielectric material closer than 5 mm to the antenna. If the dielectric material is too close to the antenna, a retune of the antenna may be required.
- Avoid placing metallic objects in close proximity to the antenna because it will prevent the antenna from radiating freely:
- The minimum recommended distance for large metallic and/or conductive objects is 50 mm in any direction from the antenna, except in the directions of the application PCB ground planes. If a large metallic object gets close to the antenna, losses of 1-3 dB may be expected, with an increase in loss for closer distances.
- Metallic objects with a maximum dimension < 10 mm, such as cabinet screws etc., should be located > 10 mm from the antenna in any direction, except in the directions of the applications PCB ground plane
Because of the sensitivity of the antenna to its surroundings, it is advised that one always test the product as an assembled unit. If detuning of the antenna due to enclosure-effects are observed, a retune of the antenna is advised. It is also possible to simulate the entire system in an electro-magnetic field simulator, if such software is available, in order to find the best possible shape or location of the antenna.
## **7.3 Reset**
The ZGM230S SiP module can be reset by:
- Pulling the RESETn pin low
- The internal watchdog timer
- A software command
The reset state does not provide any power saving advantages. Therefore, it is not recommended that the device is kept in its reset state to save power.
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ZGM230S Z-Wave 800 SiP Module Data Sheet Design Guidelines
## **7.4 Debug**
For detailed information about debugging, see AN958: Debugging and Programming Interfaces for Custom Designs.
The ZGM230S supports hardware debugging via either a 4-pin JTAG or a 2-pin serial-wire debug (SWD) interface. Expose the debug pins in the application for both programming purposes and debug purposes.
The table below lists the required pins for the JTAG and SWD debug interfacing.
If the JTAG interface is enabled, the module must be power cycled to return to the SWD configuration.
## **Table 7.1. Debug Pins**
|**Pin Name**|**Pin Number**|**JTAG signal**|**SWD Signal**|**Comments**|
|---|---|---|---|---|
|PA04|16|TDI|N/A|Pin disabled after reset. Once enabled, pull-up|
|PA03|15|TDO|N/A|Disabled after reset|
|PA02|14|TMS|SWDIO|Enabled after reset and has built-in pull-up|
|PA01|13|TCK|SWCLK|Enabled after reset and has built-in pull-up|
## **7.5 Packet Trace Interface (PTI)**
The ZGM230S integrates a true PHY-level packet trace interface, which can be used with a Z-Wave Zniffer application to capture and analyze received RF packets non-intrusively and without burdening the embedded processor of the ZGM230S SiP module. The PTI generates two output signals: PTI_DATA and PTI_FRAME, and the signals can be accessed through any GPIO on the ports C and D (search for FRC.DOUT and FRC.DFRAME peripheral resources in Table 6.4 DBUS Routing Table on page 32.
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ZGM230S Z-Wave 800 SiP Module Data Sheet Package Specifications
## **8. Package Specifications**
## **8.1 Package Outline**
**Figure 8.1. Top and Side Views**
**Figure 8.2. Bottom View**
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ZGM230S Z-Wave 800 SiP Module Data Sheet Package Specifications
**Figure 8.3. Package Edge Detail**
|**Dimension**|**MIN**|**NOM**|**MAX**|
|---|---|---|---|
|A|1.080|1.180|1.280|
|A1|0.140|0.180|0.220|
|A2|0.950|1.000|1.050|
|b|0.200|0.250|0.300|
|D|6.500 BSC|||
|D1|5.000 BSC|||
|e|0.500 BSC|||
|E|6.500 BSC|||
|E1|5.000 BSC|||
|L|0.300|0.350|0.400|
|L1|0.125|0.175|0.225|
|L2|0.575|0.625|0.675|
|L3|0.450|0.500|0.550|
|eD1|0.450 BSC|||
|eD2|0.900 BSC|||
|eE1|0.450 BSC|||
|eE2|0.900 BSC|||
|aaa|0.100|||
|bbb|0.100|||
|ccc|0.100|||
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ZGM230S Z-Wave 800 SiP Module Data Sheet Package Specifications
|**Dimension**|**MIN**|**NOM**|**MAX**|
|---|---|---|---|
|ddd|0.100|||
|eee|0.100|||
|**Note:**<br>1. The dimensions in parenthesis are reference.<br>2. All dimensions in millimeters (mms).<br>3. Unless otherwise specified tolerances are:<br>a. Decimal:<br>• X.X = ±0.1<br>• X.XX =±0.05<br>• X.XXX=±0.003<br>b. Angular:<br>• ±0.1 (In Deg)<br>4. Hatching lines means package shielding area.||||
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ZGM230S Z-Wave 800 SiP Module Data Sheet Package Specifications
## **8.2 PCB Land Pattern**
**Figure 8.4. Recommended Land Pattern**
|**Dimension**|**NOM**|
|---|---|
|D1|5.00|
|D2|2.90|
|E1|5.00|
|E2|2.90|
|eD1|0.45|
|eD2|0.90|
|b|0.25|
|e|0.50|
|L|0.35|
|L1|0.50|
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ZGM230S Z-Wave 800 SiP Module Data Sheet Package Specifications
**Dimension NOM**
**Note:** *
## **General**
1. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
## **Stencil**
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.100 mm (4 mils).
3. The stencil aperture to land pad size recommendation is 80% paste coverage.
*Above notes and stencil design are shared as recommendations only. A customer or user may find it necessary to use different parameters and fine tune their SMT process as required for their application and tooling
## **8.3 Package Marking**
**Figure 8.5. ZGM230S Top Marking**
## **Mark Description**
The package marking consists of:
- PPPPPPPPPPPP - Part number designation
- YYWWTTTTTT
- YY – Last two digits of the assembly year
- WW – Two-digit workweek when the device was assembled
- TTTTTT – A trace or manufacturing code. The first letter is the device revision
- CC - Country of origin
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ZGM230S Z-Wave 800 SiP Module Data Sheet Soldering Recommendations
## **9. Soldering Recommendations**
The ZGM230S is compatible with industrial standard reflow profile for Pb-free solders. The reflow profile used is dependent on the thermal mass of the entire populated PCB, heat transfer efficiency of the oven, and particular type of solder paste used.
- See technical documentation of your particular solder paste for profile configurations.
- Avoid using more than two reflow cycles.
- A no-clean, type-3 solder paste is recommended.
- A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
- Recommended stencil thickness is 0.100 mm (4 mils).
- General SMT application notes are provided in the AN1223 document.
- See the JEDEC/IPC J-STD-020, IPC-SM-782 and IPC 7351 guidelines for further recommendations.
- The above notes are recommendations only. A customer or user may find it necessary to use different parameters and fine tune their SMT process as required for their application and tooling.
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ZGM230S Z-Wave 800 SiP Module Data Sheet Tape and Reel
## **10. Tape and Reel**
ZGM230S modules are delivered to the customer in Tray (260 pcs) or Tape and Reel (2500 pcs) packing with the dimensions below. All dimensions are given in mm unless otherwise indicated.
**Figure 10.1. Carrier Tape Dimensions**
**Figure 10.2. Reel Dimensions**
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ZGM230S Z-Wave 800 SiP Module Data Sheet Certifications
## **11. Certifications**
Both the manufacturer of the ZGM230S modules and the applicant indicated in the test reports is:
## SILICON LABORATORIES FINLAND OY
Alberga Business Park, Bertel Jungin aukio 3, 02600 Espoo, Finland
The ZGM230S modules come with test reports proving compliance to the standards, rules and directives that are applicable for regulatory radio approvals in the following regions: EU (CE), USA (FCC), Canada (ISED) and Japan (MIC). The test reports cover typical use cases where modules are used with the standard Z-Wave protocol.
The reports are available at https://www.silabs.com/.
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ZGM230S Z-Wave 800 SiP Module Data Sheet Revision History
## **12. Revision History**
## **Revision 0.5**
October, 2021
- Corrected operating voltage range higher limit to 3.8 V
- Updated spec values in 1. Features
- Added hyperlinks to Pro Kit and radio board in 2. Ordering Information
- Replaced TBDs with spec values in 4.1 Electrical Characteristics
- Added Table 4.12 High-Frequency Crystal on page 23
- Updated 4.8 Microcontroller Peripherals
- Removed DCDC peripheral resources from Table 6.4 DBUS Routing Table on page 32
- Updated Figure 8.5 ZGM230S Top Marking on page 44
- Corrected number of pieces per carrier described in 10. Tape and Reel
- Updated text in 11. Certifications
## **Revision 0.4**
September, 2021
- Updated front page Key Features
- Updated temperature range, list of security features, and replaced TBDs with spec values in 1. Features
- Updated list of part numbers and added Security column in Table 2.1 ZGM230S Ordering Part Numbers on page 3
- Removed LF XTAL references in 3.1 Block Diagram
- Added text in 3.4 Power Supply to clarify that external fast decoupling not necessary
- Added 3.5 Security
- Replaced most TBDs with spec values and updated structure/notes for some tables in 4.1 Electrical Characteristics
- Added text in 5.1 Standalone Application about supply decoupling for quiet GPIO activity; also added reference to AN958
- Added 10. Tape and Reel
## **Revision 0.1**
September, 2020
- Initial Release
**silabs.com** | Building a more connected world.
Rev. 0.5 | 48
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IoT Portfolio SW/HW Quality Support & Community<br>www.silabs.com/IoT www.silabs.com/simplicity www.silabs.com/quality www.silabs.com/community<br>**----- End of picture text -----**<br>
## **Disclaimer**
Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and “Typical” parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes without further notice to the product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. Without prior notification, Silicon Labs may update product firmware during the manufacturing process for security or reliability reasons. Such changes will not alter the specifications or the performance of the product. Silicon Labs shall have no liability for the consequences of use of the information supplied in this document. This document does not imply or expressly grant any license to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any FDA Class III devices, applications for which FDA premarket approval is required or Life Support Systems without the specific written consent of Silicon Labs. A “Life Support System” is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant personal injury or death. Silicon Labs products are not designed or authorized for military applications. Silicon Labs products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons. Silicon Labs disclaims all express and implied warranties and shall not be responsible or liable for any injuries or damages related to use of a Silicon Labs product in such unauthorized applications. **Note: This content may contain offensive terminology that is now obsolete. Silicon Labs is replacing these terms with inclusive language wherever possible. For more information, visit www.silabs.com/about-us/inclusive-lexicon-project**
## **Trademark Information**
Silicon Laboratories Inc.[®] , Silicon Laboratories[®] , Silicon Labs[®] , SiLabs[®] and the Silicon Labs logo[®] , Bluegiga[®] , Bluegiga Logo[®] , EFM[®] , EFM32[®] , EFR, Ember[®] , Energy Micro, Energy Micro logo and combinations thereof, “the world’s most energy friendly microcontrollers”, Redpine Signals[®] , WiSeConnect , n-Link, ThreadArch[®] , EZLink[®] , EZRadio[®] , EZRadioPRO[®] , Gecko[®] , Gecko OS, Gecko OS Studio, Precision32[®] , Simplicity Studio[®] , Telegesis, the Telegesis Logo[®] , USBXpress[®] , Zentri, the Zentri logo and Zentri DMS, Z-Wave[®] , and others are trademarks or registered trademarks of Silicon Labs. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or registered trademarks of ARM Holdings. Keil is a registered trademark of ARM Limited. Wi-Fi is a registered trademark of the Wi-Fi Alliance. All other products or brand names mentioned herein are trademarks of their respective holders.
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Updated at February 9, 2023
Silicon Labs is a recognized industry leader in secure, intelligent wireless technology and precision timing solutions. Renowned for driving innovation in the Internet of Things (IoT) and industrial automation, the company develops electronic components that deliver the performance, energy savings, and design simplicity required to build a seamlessly connected world. Our extensive portfolio of Silicon Labs components prominently features their robust wireless connectivity and timing products. This includes a comprehensive selection of Bluetooth modules and adaptors engineered for reliable, low-power communication in smart devices. Complementing these wireless offerings is a broad array of precision timing devices, particularly standard and advanced MEMS oscillators, which are critical for ensuring exact synchronization and stable frequency control in demanding circuit designs. To support a wider spectrum of networking and communication requirements, the lineup also encompasses versatile WLAN modules and USB adaptors. Additionally, engineers will find highly integrated sub-2.4GHz ISM band RF transceivers, available as both standalone integrated circuits and complete RF modules, providing exceptional range and signal resilience for complex wireless deployments.
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