XTP332156.250000I
Oscillator, 156 MHz, 13 ppm, SMD, 3.2mm x 2.5mm, 3.3 VDC, XT Series
- Manufacturer: RENESAS
- Product type: Standard Oscillators
- Available until stocks are exhausted
- SVHC: No SVHC (27-Jun-2024)
- Frequency Nom: 156MHz
- Product Range: XT Series
- Supply Voltage Nom: 3.3VDC
- Frequency Stability + / -: 13ppm
- Operating Temperature Max: 85°C
- Operating Temperature Min: -40°C
- Oscillator Case / Package: SMD, 3.2mm x 2.5mm
- Oscillator Output Compatibility: LVPECL
| Delivery and price | |
|---|---|
| Units per pack | 100 |
| Price | 9.07 € |
| Current stock | 100+ |
| Lead time | 7 days |
XT Family of Ultra-low Phase Noise XT Quartz-based PLL Oscillators Datasheet
## Description
The XT devices are ultra-low phase noise quartz-based PLL oscillators supporting a large range of frequencies and output interface types.
The XT devices can be programmed to generate an output frequency from 15MHz to 2100MHz with a resolution as low as 1Hz accuracy. The configurability of this family of devices provides fast delivery times for both sample and large production orders.
Parts may be factory programmed for fixed frequency applications, or may be field configured using the I2C interface.
## Features
- Output types: LVDS, LVPECL, CML
- Frequency range: 15MHz to 2100MHz
- Output type: HCSL
- Frequency range: 15MHz to 725MHz
- Supply voltage options: 1.8V, 2.5V, 3.3V
- Phase jitter (12kHz to 20MHz): 135 fs typical
- Package options:
- 3.2 × 2.5 × 0.85 mm
- Operating temperature and stability:
- -40°C to +85°C, ±3ppm
- Frequency stability for life:
- -40°C to +85°C, ±13ppm
## Pin Assignments
## Figure 1. 3.2 × 2.5 mm Package – Top View
**==> picture [122 x 131] intentionally omitted <==**
**----- Start of picture text -----**<br>
SDA<br>7<br>OE 1 6 VDD<br>NC 2 5 OUT0b<br>GND 3 4 OUT0<br>8<br>SCL<br>**----- End of picture text -----**<br>
Table 1. Pin Descriptions
|**Pin #**|**Pin Name**|**Description**|
|---|---|---|
|1|OE|Output Enable (0 = output disabled, pulled high internally)|
|2|NC|No connect|
|3|GND|Connect to ground|
|4|OUT0|Output|
|5|OUT0b|Complementary output|
|6|VDD<br>|Supply voltage|
|7|SDA1|Serial data|
|8|SCL1|Serial clock|
1 Pins 7 and 8 are no connect for non-I2C applications.
See Ordering Information for more details.
©2021 Renesas Electronics Corporation
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## Ordering Information
|||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||**XT**||||**L**||||||**3**|||**1**|||**2**||**125.000000**<br>**I**|||
||Family and ASIC||||Output Type|||||Package||||Voltage|||Precision||Frequency<br>Temperature Range|||
|||||||||||||||||||||||
|||||||||||||||||||||||
|||||||||||||||**1:**1.8 VDC ±5%|||||**I:**Extended industrial range: ‐40 to +85°C|||
|||||||||||||||**2:**2.5 VDC ±5%||||||||
|||||||||||||||**3:**3.3 VDC ±5%||||||||
|||||||||||||||||||||||
||||||||||**3:**|3.2 x 2.5 mm|||||||||**125.000000 Listed in MHz as example**|||
||||||||||||||||||||3 digits before decimal and 6 digits past decimal|||
|||||**C:**CML Enable/Disable Pin 1|||||||||||||||**015.000000 to 099.999999**15MHz to 99.999999MHz|||
|||||**L:**LVDS Enable/Disable Pin 1|||||||||||||||**100.000000 to 999.999999**100MHz to 999.999999MHz|||
|||||**P:**LVPECL Enable/Disable Pin|||||1||||||||||**A00.000000 to A99.999999**1000MHz to 1099.999999MHz|||
|||||**N:**HCSL Enable/Disable|||Pin 1||||||||||||**B00.000000 to B99.999999**1100MHz to 1199.999999MHz|||
||||||||||||||||||||**C00.000000 to C99.999999**1200MHz to 1299.999999MHz|||
|||**XT:**150fs jitter|||||||||||||||||**D00.000000 to D99.999999**1300MHz to 1399.999999MHz|||
||||||||||||||||||||**E00.000000 to E99.999999**1400MHz to 1499.999999MHz|||
||||||||||||||||||||**F00.000000 to F99.999999**1500MHz to 1599.999999MHz|||
||||||||||||||||||||**G00.000000 to G99.999999**1600MHz to 1699.999999MHz|||
||||||||||||||||||||**H00.000000 to H99.999999**1700MHz to 1799.999999MHz|||
||||||||||||||||||||**I00.000000 to I99.999999**1800MHz to 1899.999999MHz|||
||||||||||||||||||||**J00.000000 to J99.999999**1900MHz to 1999.999999MHz|||
||||||||||||||||||||**K00.000000 to K99.999999**2000MHz to 2099.999999MHz|||
||||||||||||||||||||**L00.000000**2100MHz|||
|||||||||||||||||||||||
||||||||||||||||||||**2:**±13ppm for life (±3ppm|||
||||||||||||||||||||for temperature stability)|||
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## Contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ~~.~~ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ESD Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Mechanical Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Solder Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Output Phase Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Output Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3V LVPECL Output Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.5V LVPECL Output Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.8V LVPECL Output Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 LVDS Output Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 HCSL Output Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 CML Output Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Package Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Marking Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
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## Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the device. These ratings, which are standard values for Renesas commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure t ~~o~~ absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Thermal characteristics, in actual applications, should be assessed case by case to guarantee junction temperature does not exceed 125°C.
Table 2. Absolute Maximum Ratings
|**Item**|**Rating**|**Rating**|
|---|---|---|
|VDD|-0.5V to +3.8V||
|OE|-0.5V to +3.8V||
|Storage Temperature|-55°C to 125°C||
|Maximum Junction Temperature<br>|125°C||
|Theta JA<br>1<br>|LNG8|131.47 °C/W|
|Theta JB<br>1||92.89 °C/W|
- 1 Thermal characteristics are based on simulation in standard condition.
## ESD Compliance
Table 3. ESD Compliance
Human Body Model (HBM) 2000V
## Mechanical Testing
Table 4. Mechanical Testing
|**Parameter**|**Test Method**|
|---|---|
|Mechanical Shock|Half-sine wave with 0.3ms 3000G. X, Y, Z each direction 1 time.|
|Mechanical Vibration|Frequency: 10 to 55MHz amplitude: 1.5mm.<br>Frequency: 55–2000Hz peak value: 20G.<br>Duration time: 4H for each X, Y, Z axis; total 12hours.|
|High Temp Operating Life (HTOL)|1000 hours at 125°C (under power).|
|MSL Level 3|J-STD-020E, Moisture/Reflow Sensitivity Classification for Nonhermetic Surface Mount Devices,<br>December 2014.|
## Solder Reflow Profile
**==> picture [361 x 149] intentionally omitted <==**
**----- Start of picture text -----**<br>
tP 10 seconds Max within 5°C of<br>260°C peak<br>260°C<br>Ramp up 3°C/s Max<br>225°C Ramp down not to<br>180°C 50 ±10 seconds exceed 6°C/s<br>above 225°C<br>reflow area<br>160°C<br>120 ±20 seconds in<br>pre-heating area<br>25°C<br>400 seconds Max from +25°C to 260°C peak<br>**----- End of picture text -----**<br>
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## DC Electrical Characteristics
## Table 5. 3.3V IDD DC Electrical Characteristics
VDD = 3.3V ± 5%, TA = -40°C to +85°C, typical at 156.25MHz.
|**Symbol**|**Parameter**|**Output Type**|**Conditions**|**Minimum**|**Typical**|**Maximum**|**Units**|
|---|---|---|---|---|---|---|---|
|IDD|Current Consumption|LVDS|15MHz to 400MHz.|—|59|67|mA|
||||400MHz to 2.1GHz.|—|—|85||
|||LVPECL|15MHz to 212.5MHz.|—|84|94||
||||212.5MHz to 400MHz.|—|—|110||
||||212.5MHz to 2.1GHz.|—|—|110||
|||HCSL|15MHz to 400MHz.|—|—|95||
||||400MHz to 725MHz.|—|74|83||
|||CML|15MHz to 2.1GHz.|—|54|61||
## Table 6. 2.5V IDD DC Electrical Characteristics
VDD = 2.5V ± 5%, TA = -40°C to +85°C, typical at 156.25MHz.
|**Symbol**|**Parameter**|**Output Type**|**Conditions**|**Minimum**|**Typical**|**Maximum**|**Units**|
|---|---|---|---|---|---|---|---|
|IDD|Current Consumption|LVDS|15MHz to 400MHz.|—|59|66|mA|
||||400MHz to 2.1GHz.|—|—|85||
|||LVPECL|15MHz to 156.25MHz.|—|84|94||
||||156.25MHz to 400MHz.|—|—|110||
||||400MHz to 2.1GHz.|—|—|110||
|||HCSL|15MHz to 400MHz.|—|—|95||
||||400MHz to 725MHz.|—|74|82||
|||CML|15MHz to 2.1GHz.|—|54|61||
Table 7. 1.8V DD DC Electrical Characteristics
VDD = 1.8V ± 5%, TA = -40°C to +85°C, typical at 156.25MHz.
|**Symbol**|**Parameter**|**Output Type**|**Conditions**|**Minimum**|**Typical**|**Maximum**|**Units**|
|---|---|---|---|---|---|---|---|
|IDD|Current Consumption|LVDS|15MHz to 400MHz.|—|59|66|mA|
||||400MHz to 2.1GHz.|—|—|85||
|||LVPECL|15MHz to 250MHz.|—|84|93||
||||250MHz to 2.1GHz.|—|—|110||
|||HCSL|15MHz to 400MHz.|—|—|95||
||||400MHz to 725MHz.|—|74|81||
|||CML|15MHz to 2.1GHz.|—|54|61||
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## Table 8. LVCMOS DC Electrical Characteristics
VDD = 1.8V, 2.5V, 3.3V ±5%, TA = -40°C to +85°C.
|**Symbol**|**Parameter**|**Conditions**|**Minimum**|**Typical**|**Maximum**|**Units**|
|---|---|---|---|---|---|---|
|VIH|Input High Voltage (OE pin only)|VDD= 1.8V, 2.5V, 3.3V ± 5%.|0.7 × VDD|—|VDD+ 0.3|V|
|VIL|Input Low Voltage (OE pin only)|VDD= 1.8V, 2.5V, 3.3V ± 5%.|GND - 0.3|—|0.3 × VDD|V|
## Table 9. LVDS DC Electrical Characteristics
VDD = 1.8V, 2.5V, 3.3V ±5%, TA = -40°C to +85°C.
|**Symbol**|**Parameter**|**Conditions**|**Minimum**|**Typical**|**Maximum**|**Units**|
|---|---|---|---|---|---|---|
|VOD|Differential Output Voltage|VDD= 1.8V, 2.5V, 3.3V ± 5%.|0.30|0.44|0.60|V|
|VOS|Output Offset Voltage|VDD= 1.8V ± 5%|0.75|0.88|1.01||
|||VDD= 2.5V ± 5%|1.08|1.25|1.41||
|||VDD= 3.3V ± 5%|1.11|1.26|1.41||
## Table 10. LVPECL DC Electrical Characteristics
VDD = 1.8V, 2.5V, 3.3V ± 5%, TA = -40°C to +85°C.
|**Symbol**|**Parameter**|**Conditions**|**Minimum**|**Typical**|**Maximum**|**Units**|
|---|---|---|---|---|---|---|
|VOH|Output High Voltage|VDD= 1.8V ± 5%.|0.83|0.96|1.11|V|
|||VDD= 2.5V ± 5%.|1.52|1.69|1.87||
|||VDD= 3.3V ± 5%.|2.28|2.49|2.72||
|VOL|Output Low Voltage|VDD= 1.8V ± 5%.|0.19|0.30|0.42||
|||VDD= 2.5V ± 5%.|0.92|1.04|1.17||
|||VDD= 3.3V ± 5%.|1.68|1.84|2.01||
## Table 11. HCSL DC Electrical Characteristics
VDD = 1.8V, 2.5V, 3.3V ± 5%, TA = -40°C to +85°C.
|**Symbol**|**Parameter**|**Conditions**|**Minimum**|**Typical**|**Maximum**|**Units**|
|---|---|---|---|---|---|---|
|VOH|Output High Voltage|VDD= 1.8V ± 5%.|0.67|0.81|0.95|V|
|||VDD= 2.5V ± 5%.|0.74|0.88|1.03||
|||VDD= 3.3V ± 5%.|0.78|0.92|1.07||
|VOL|Output Low Voltage|—|-0.06|0.07|0.20||
©2021 Renesas Electronics Corporation
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XT Datasheet
## Table 12. CML DC Electrical Characteristics
VDD = 1.8V, 2.5V, 3.3V ± 5%, TA = -40°C to +85°C.
|**Symbol**|**Parameter**|**Conditions**|**Minimum**|**Typical**|**Maximum**|**Units**|
|---|---|---|---|---|---|---|
|VOH|Output High Voltage|VDD= 1.8V ± 5%.|1.61|1.76|1.91|V|
|||VDD= 2.5V ± 5%.|2.33|2.46|2.59||
|||VDD= 3.3V ± 5%.|3.09|3.26|3.43||
|VOL|Output Low Voltage|VDD= 1.8V ± 5%.|1.24|1.37|1.52||
|||VDD= 2.5V ± 5%.|1.95|2.06|2.17||
|||VDD= 3.3V ± 5%.|2.70|2.85|3.00||
Table 13. DC Electrical Characteristics – Leakage Current
VDD = 1.8V, 2.5V, 3.3V ± 5%, TA = -40°C to +85°C, typical at 156.25MHz.
|**Symbol**|**Parameter**|**Conditions**|**Input**|**Minimum**|**Typical**|**Maximum**|**Units**|
|---|---|---|---|---|---|---|---|
|IIH|Input Leakage High|VDD= 3.3V ±5%.|OE|-5|0.8|5|µA|
||||SCLK|-5|1.4|5||
||||SDATA|-5|1.4|5||
|IIL|Input Leakage Low|VDD= 3.3V ±5%.|OE|-20|-17.4|-14|µA|
||||SCLK|-37|-33.5|-30||
||||SDATA|-20|-17|-14||
|IIH|Input Leakage High|VDD= 1.8V ±5%.|OE|-5|0.8|5|µA|
||||SCLK|-5|1.4|5||
||||SDATA|-5|1.4|5||
|IIL|Input Leakage Low|VDD= 1.8V ±5%.|OE|-11.5|-9.5|-7.5|µA|
||||SCLK|-20.8|-18.3|-15.7||
||||SDATA|-11.5|-9.3|-7.5||
©2021 Renesas Electronics Corporation
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## AC Electrical Characteristics
Note for all AC Electrical Characteristics tables:
1. Installation should include a 0.01μF bypass capacitor placed between VDD and GND to minimize power supply line noise.
## Table 14. 3.3V AC Electrical Characteristics
VDD = 3.3V ± 5%, TA = -40°C to +85°C.
|**Symbol**|**Parameter**|**Test Condition**|**Test Condition**|**Minimum**|**Typical**|**Maximum**|**Units**|
|---|---|---|---|---|---|---|---|
|F|Output Frequency Range|LVDS, LVPECL, CML.||15|—|2100|MHz|
|||HCSL.||15|—|725||
||Frequency Stability|Temperature = -40°C to +85°C.||—|—|±3|PPM|
||Frequency Tolerance (25°C)|TA= 25°C.||—|—|±2||
||Aging (1 year)|TA= 25°C.||—|—|±1||
||Aging (10 years)|TA= 25°C.||—|—|±7||
||Output Load|LVDS.|Differential.|—|100|—|Ω|
|||LVPECL.|Thevenin equivalent.|—|50|—||
|||HCSL.|To GND.|—|50|—||
|TST|Start-up Time|Output valid time after VDDmeets minimum<br>specified level.||—|5|—|ms|
|tR|Output Rise Time|LVDS.|20% – 80%,<br>156.25MHz|—|299|400|ps|
|||LVPECL.||—|287|400||
|||HCSL.||—|306|400||
|||CML||—|301|400||
|tF|Output Fall Time|LVDS.|80% – 20%,<br>156.25MHz|—|279|400|ps|
|||LVPECL.||—|274|400||
|||HCSL.||—|284|400||
|||CML||—|279|400||
|ODC|Output Clock Duty Cycle|LVDS.|156.25MHz|45|—|55|%|
|||LVPECL.|156.25MHz|45|—|55||
|||HCSL.|156.25MHz|45|—|55||
|||CML|156.25MHz|45|—|55||
|TOE|Output Enable/Disable Time|—|—|—|1|—|ms|
©2021 Renesas Electronics Corporation
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XT Datasheet
## Table 15. 2.5V AC Electrical Characteristics
VDD = 2.5V ± 5%, TA = -40°C to +85°C.
|**Symbol**|**Parameter**|**Test Condition**|**Test Condition**|**Minimum**|**Typical**|**Maximum**|**Units**|
|---|---|---|---|---|---|---|---|
|F|Output Frequency Range|LVDS, LVPECL, CML.||15|—|2100|MHz|
|||HCSL.||15|—|725||
||Frequency Stability|Temperature = -40°C to +85°C.||—|—|±3|ppm|
||Frequency Tolerance (25°C)|TA= 25°C.||—|—|±2||
||Aging (1 year)|TA= 25°C.||—|—|±1||
||Aging (10 years)|TA= 25°C.||—|—|±7||
||Output Load|LVDS.|Differential.|—|100|—|Ω|
|||LVPECL.|Thevenin equivalent.|—|50|—||
|||HCSL.|To GND.|—|50|—||
|TST|Start-up Time|Output valid time after VDDmeets minimum<br>specified level.||—|5|—|ms|
|tR|Output Rise Time|LVDS.|20% – 80%,<br>156.25MHz|—|303|400|ps|
|||LVPECL.||—|292|400||
|||HCSL.||—|310|400||
|||CML||—|304|400||
|tF|Output Fall Time|LVDS.|80% – 20%,<br>156.25MHz|—|282|400|ps|
|||LVPECL.||—|278|400||
|||HCSL.||—|288|400||
|||CML||—|281|400||
|ODC|Output Clock Duty Cycle|LVDS.|156.25MHz|45|—|55|%|
|||LVPECL.|156.25MHz|45|—|55||
|||HCSL.|156.25MHz|45|—|55||
|||CML|156.25MHz|45|—|55||
|TOE|Output Enable/Disable Time|—|—|—|1|—|ms|
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## Table 16. 1.8V AC Electrical Characteristics
VDD = 1.8V ±5%, TA = -40°C to +85°C.
|**Symbol**|**Parameter**|**Test Condition**|**Test Condition**|**Minimum**|**Typical**|**Maximum**|**Units**|
|---|---|---|---|---|---|---|---|
|F|Output Frequency Range|LVDS, LVPECL, CML.||15|—|2100|MHz|
|||HCSL.||15|—|725||
||Frequency Stability|Temperature = -40°C to +85°C.||—|—|±3|PPM|
||Frequency Tolerance (25°C)|TA= 25°C.||—|—|±2||
||Aging (1 year)|TA= 25°C.||—|—|±1||
||Aging (10 years)|TA= 25°C.||—|—|±7||
||Output Load|LVDS.|Differential.|—|100|—|Ω|
|||LVPECL.|Thevenin equivalent.|—|50|—||
|||HCSL.|To GND.|—|50|—||
|TST|Start-up Time|Output valid time after VDDmeets minimum<br>specified level.||—|5|—|ms|
|tR|Output Rise Time|LVDS.|20% – 80%,<br>312.5MHz|—|300|450|ps|
|||LVPECL.||—|260|450||
|||HCSL.||—|260|450||
|||CML||—|270|450||
|tF|Output Fall Time|LVDS.|80% – 20%,<br>312.5MHz|—|280|450|ps|
|||LVPECL.||—|250|450||
|||HCSL.||—|250|450||
|||CML||—|270|450||
|ODC|Output Clock Duty Cycle|LVDS.|312.5MHz|45|—|55|%|
|||LVPECL.|312.5MHz|45|—|55||
|||HCSL.|312.5MHz|45|—|55||
|||CML|312.5MHz|45|—|55||
|TOE|Output Enable/Disable Time|—|—|—|1|—|ms|
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Table 17. Phase Jitter Characteristics
VDD = 1.8V, 2.5V, 3.3V ± 5%, TA = -40°C to +85°C.
|**Symbol**|**Parameter**|**Conditions**|**Typical**<br>**(LVPECL)**|**Typical**<br>**(LVDS)**|**Typical**<br>**(CML)**|**Typical**<br>**(HSCL)**|**Units**|
|---|---|---|---|---|---|---|---|
|fJITTER|Phase Jitter (12kHz – 20MHz)|312.50MHz|124|159|131|126|fsec|
|||625.00MHz|130|132|133|131|fsec|
|||644.53MHz|134|137|133|130|fsec|
|||779.215MHz|140|140|139|—|fsec|
|||818.991MHz|143|144|140|—|fsec|
|||822.128MHz|164|167|164|—|fsec|
|||840.759MHz|146|152|151|—|fsec|
|||1588.430MHz|147|144|143|—|fsec|
|||1681.518MHz|156|153|151|—|fsec|
|||1644.256MHz|157|154|155|—|fsec|
|||1637.982MHz|147|148|148|—|fsec|
## Output Phase Noise
Figure 2. 625MHz LVDS Output
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## Output Waveforms
## Figure 3. LVDS/LVPECL/HCSL/CML Output Waveforms
## **Output Levels /Rise Time/Fall Time Measurements**
**==> picture [388 x 270] intentionally omitted <==**
**----- Start of picture text -----**<br>
TR TF<br>OUT0b<br>20% to 80% VOS VOD<br>OUT0<br>Oscillator Symmetry<br>OUT0b VOH<br>OUT0 VOL<br>½ Period<br>Period<br>**----- End of picture text -----**<br>
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## 3.3V LVPECL Output Termination
Figure 4 shows an example of termination for 3.3V LVPECL driver.
## Figure 4. 3.3V LVPECL Driver Termination Example
## 2.5V LVPECL Output Termination
Figure 5 shows an example of termination for 2.5V LVPECL driver.
## Figure 5. 2.5V LVPECL Driver Termination Example
## 1.8V LVPECL Output Termination
Figure 6 shows an example of termination for 1.8V LVPECL driver.
## Fi ~~gure 6.~~ 1.8V LVPECL Driver Termination Example
**==> picture [184 x 90] intentionally omitted <==**
**----- Start of picture text -----**<br>
Vcco = 1.8V 1.8V<br>50Ω<br>50Ω<br>1.8V LVPECL Driver<br>R1 R2<br>50 50<br>**----- End of picture text -----**<br>
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## LVDS Output Termination
For a general LVDS interface, the recommended value for the termination impedance (ZT) is between 90Ω and 132Ω. The actual value should be selected to match the differential impedance (Z0) of your transmission line. A typical point-to-point LVDS design uses a 100Ω parallel resistor at the receiver and a 100Ω differential transmission-line environment. In ~~o~~ rder to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. Renesas offers a full line of LVDS compliant devices with two types of output structures: current source and voltage source.
The standard termination schematic as shown in Figure 7 can be used with either type of output structure. Figure 8, which can also be used with both output types, is an optional termination with center tap capacitance to help filter common mode noise. The capacitor value should be approximately 50pF. If using a non-standard termination, it is recommended to contact Renesas and confirm if the output structure is current source or voltage source type. In addition, since these outputs are LVDS compatible, the input receiver’s amplitude and common-mode input range should be verified for compatibility with the output.
Figure 7. Standard LVDS Termination
Figure 8. Optional LVDS Termination
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## HCSL Output Termination
Figure 9 is the recommended source termination for applications where the driver and receiver will be on a separate PCBs. This termination is the standard for PCI Express™ and HCSL output types. All traces should be 50Ω impedance single-ended or 100Ω differential. Figure 10 is the recommended termination for applications where a point-to- ~~po~~ int connection can be used. A point-to-point connection contains both the driver and the receiver on the same PCB. With a matched termination at the receiver, transmission-line reflections will be minimized. In addition, a series resistor (Rs) at the driver offers flexibility and can help dampen unwanted reflections. The optional resistor can range from 0Ω to 33Ω. All traces should be 50 Ω impedance single-ended or 100Ω differential.
Figure 9. Recommended Source Termination (where the driver and receiver will be on separate PCBs)
**==> picture [500 x 179] intentionally omitted <==**
**----- Start of picture text -----**<br>
Rs<br>0.5" Max 0-0.2" 1-14" 0.5 - 3.5"<br>22 to 33 +/-5%<br>L1 L2 L4 L5<br>L1 L2 L4 L5<br>PCI Express<br>PCI Express<br>Connector<br>Driver PCI Express<br>0-0.2" L3 L3<br>Add-in Card<br>Rt 49.9 +/- 5%<br>**----- End of picture text -----**<br>
Figure 10. Recommended Termination (where a point-to-point connection can be used)
**==> picture [420 x 138] intentionally omitted <==**
**----- Start of picture text -----**<br>
Rs<br>0.5" Max 0-18" 0-0.2"<br>0 to 33<br>L1 L2 L3<br>0 to 33<br>L1 L2 L3<br>PCI Express<br>Driver Rt 49.9 +/- 5%<br>**----- End of picture text -----**<br>
## CML Output Termination
Figure 11 shows an example of the termination for a CML driver. In this example, the transmission line characteristic impedance is 50Ω. The R1 and R2 50Ω matched load terminations are pulled up to VDDO. The matched loads are located close to the receiver.
Figure 11. CML Driver Termination Example
**==> picture [257 x 132] intentionally omitted <==**
**----- Start of picture text -----**<br>
VDDO<br>VDDO<br>R1 R2<br>50 50<br>Zo = 50<br>Zo = 50<br>CML Driv er<br>**----- End of picture text -----**<br>
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XT Datasheet
## Package Outline Drawings
The package outline drawings are located at the end of this document and are accessible from the Renesas website. The package information is the most current data available and is subject to change without revision of this document.
## Marking Diagram
## Figure 12. Marking Configuration for the 3.2 × 2.5 mm (LNG8) Package (example based on XTL312625.000000I)
▪ Line 1 denotes the truncated part number as follows:
- Dxxxxxx • “D” = a combination of the 3rd digit (output type, e.g. “ **L** ”) and the 5th digit (voltage supply, e.g. “ **3** ”), in accordance with the mapping key as follows:
- YWW**$
- C1 = A, C2 = B, C3 = C, **L1 = D** , L2 = E, L3 = F, N1 = G, N2 = H, N3 = J, P1 = K, P2 = L, P3 = M
- “xxxxxx” = the first three digits to the left of the decimal point and the last three digits to the left of the decimal point as shown in the above example. This number will vary depending upon the frequency value selected in the orderable part number. (e.g. 625000).
## ▪ Line 2 indicates the following:
- “YWW” denotes the last digit of the year and week when the part was assembled.
- “**” denotes the sequential lot number.
- “$” denotes the mark location.
## Revision History
|**Revision Date**|**Description of Change**|
|---|---|
|April 8, 2021|Initial release.|
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8-LGA, Package Outline Drawing 2.50 x 3.20 x 0.85 mm Body, 1.25mm Pitch LNG8D1, PSC-4837-01, Rev 00, Page 1
© Integrated Device Technology, Inc.
8-LGA, Package Outline Drawing 2.50 x 3.20 x 0.85 mm Body, 1.25mm Pitch LNG8D1, PSC-4837-01, Rev 00, Page 2
Package Revision History Date Created Rev No. Description Nov. 12, 2019 00 Initial Release
© Integrated Device Technology, Inc.
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(Rev.1.0 Mar 2020)
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For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: www.renesas.com/contact/
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Updated at March 11, 2026
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