XP4N4R2MT

## **XP4N4R2MT** ~~Po~~ **Halogen-Free Product** _**N-CHANNEL ENHANCEMENT MODE**_ 

_**POWER MOSFET**_ 

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D BVDSS 40V<br>RDS(ON) 4.2m Ω<br>G<br>S D<br>D<br>D<br>D<br>process<br>and fast<br>an extreme<br>S<br>converters<br>with backside<br>SS G<br>PMPAK [®]  5x6<br>**----- End of picture text -----**<br>


- **100% Rg & UIS Test** 

- **Simple Drive Requirement** 

- **Ultra Low On-resistance** 

- **RoHS Compliant & Halogen-Free** 

## **Description** 

XP4N4R2 series are innovated design and silicon process technology to achieve the lowest possible on-resistance and fast switching performance. It provides the designer with an extreme efficient device for use in a wide range of power applications. The PMPAK[®] 5x6 package is special for DC-DC converters application and the foot print is compatible with SO-8 with backside heat sink and lower profile. 

## **Absolute Maximum Ratings@Tj=25[o] C(unless otherwise specified)** 

|Symbol<br>~~es~~<br>~~es~~|Parameter|Rating|Units|
|---|---|---|---|
|VDS<br>~~es~~<br>~~es~~<br>~~es~~|Drain-Source Voltage<br>~~en~~|40<br>~~en~~|V<br>~~en~~|
|VGS<br>~~es~~<br>~~es~~|Gate-Source Voltage<br>~~en~~|+<br>20<br>~~en~~|V<br>~~en~~|
|ID@TC=25℃<br>~~es~~<br>~~es~~<br>~~es~~|Drain Current, VGS@ 10V4(Silicon Limited)<br>~~en~~<br>|83<br>~~en~~<br>|A<br>~~en~~<br>|
|ID@TC=25℃<br>~~es~~<br>~~es~~|Drain Current, VGS@ 10V4(Package Limited)<br>|60<br>|A<br>|
|ID@TA=25℃<br>~~esI~~<br>~~es~~|Drain Current, VGS@ 10V3<br>~~I~~|25.8<br>~~I~~|A<br>~~I~~|
|ID@TA=70℃<br>~~es~~<br>~~es~~|Drain Current, VGS@ 10V3|20.7|A|
|IDM<br>~~es~~<br>~~es~~<br>~~es~~|Pulsed Drain Current1|240|A|
|PD@TC=25℃<br>~~es~~<br>~~es~~<br>~~es~~|Total Power Dissipation<br>|52<br>|W<br>|
|PD@TA=25℃<br>~~es~~<br>~~es~~|Total Power Dissipation3<br>|5<br>|W<br>|
|EAS<br>~~esa~~|Single Pulse Avalanche Energy5<br>~~a~~|80<br>~~a~~|mJ<br>~~a~~|
|TSTG<br>~~I~~<br>~~es~~|Storage Temperature Range<br>~~I~~|-55 to 150<br>~~I~~|℃<br>~~I~~|
|TJ<br>~~es~~|OperatingJunction Temperature Range|-55 to 150|℃|



## **Thermal Data** 

|Symbol|Parameter|Value|Unit|
|---|---|---|---|
|Rthj-c|Maximum Thermal Resistance,Junction-case|2.4|℃/W|
|Rthj-a|Maximum Thermal Resistance,Junction-ambient3|25|℃/W|



**1** 

**202311172YAGEO** 

**XP4N4R2MT** 

## **Electrical Characteristics@Tj=25[o] C(unless otherwise specified)** 

|Symbol<br>~~a~~|Parameter<br>~~se~~|Test Conditions<br>~~se~~|Min.<br>~~se~~|Typ.<br>~~se~~|Max.<br>~~se~~|Units<br>~~se~~|
|---|---|---|---|---|---|---|
|BVDSS|Drain-Source Breakdown Voltage|VGS=0V, ID=250uA|40|-|-|V|
|RDS(ON)<br>~~eee~~|Static Drain-Source On-Resistance2<br>~~eee~~|VGS=10V, ID=20A<br>~~eee~~|-<br>~~eee~~|-<br>~~eee~~|4.2<br>~~eee~~|mΩ<br>~~eee~~|
|||VGS=4.5V, ID=20A<br>~~eee~~|-<br>~~eee~~|-<br>~~eee~~|7.2<br>~~eee~~|mΩ<br>~~eee~~|
|VGS(th)|Gate Threshold Voltage|VDS=VGS, ID=250uA|1|-|3|V|
|gfs|Forward Transconductance|VDS=5V, ID=20A|-|90|-|S|
|IDSS<br>~~a a~~|Drain-Source Leakage Current<br>~~a~~|VDS=32V, VGS=0V<br>~~OO~~|-<br>~~OO~~|-<br>~~OO~~|10<br>~~OO~~|uA<br>~~OO~~|
|IGSS<br>~~a~~|Gate-Source Leakage<br>~~OOO~~|VGS=+<br>20V, VDS=0V<br>~~OOO~~|-<br>~~OOO~~|-<br>~~OOO~~|+<br>100<br>~~OOO~~|nA<br>~~OOO~~|
|Qg<br>~~a ~~<br>~~a~~|Total Gate Charge<br> ~~OOO~~|ID=20A<br>VDS=20V<br>VGS=4.5V<br>~~OOO~~<br>~~CT~~|-<br>~~OOO~~<br>~~ry~~|26<br>~~OOO~~<br>~~ry~~|41.6<br>~~OOO~~<br>~~ry~~|nC<br>~~OOO~~<br>~~ry~~|
|Qgs<br>~~a~~|Gate-Source Charge||-<br>~~Py~~|8<br>~~Py~~|-<br>~~Py~~|nC<br>~~Py~~|
|Qgd<br>~~a~~<br>~~a~~|Gate-Drain("Miller")Charge||-<br>~~Ty~~<br>~~CT~~|10.5<br>~~Ty~~|-<br>~~Ty~~|nC<br>~~Ty~~|
|td(on)<br>~~a~~|Turn-on DelayTime|VDS=20V<br>ID=20A<br>RG=3.3Ω<br>VGS=10V<br>~~CT~~<br>~~CT~~<br>~~CT~~|-<br>~~CT~~|9|-|ns|
|tr<br>~~a~~<br>~~a~~<br>~~a~~|Rise Time||-<br>~~CT~~<br>~~Ty~~<br>~~CT~~|40<br>~~Ty~~|-<br>~~Ty~~|ns<br>~~Ty~~|
|td(off)<br>~~a~~<br>~~a~~|Turn-off DelayTime||-<br>~~CT~~<br>~~CT~~|39|-|ns|
|tf<br>~~a~~<br>~~a~~|Fall Time||-<br>~~CT~~<br>~~CT~~|65|-|ns|
|Ciss<br>~~a~~<br>~~a~~|Input Capacitance|VGS=0V<br>VDS=20V<br>f=1.0MHz<br>~~CT~~|-<br>~~CT~~<br>~~Pr~~|2750<br>~~Pr~~|4400<br>~~Pr~~|pF<br>~~Pr~~|
|Coss<br>~~a~~|Output Capacitance||-<br>~~pf~~|315<br>~~pf~~|-<br>~~pf~~|pF<br>~~pf~~|
|Crss<br>~~a~~|Reverse Transfer Capacitance||-<br>~~Py~~|195<br>~~Py~~|-<br>~~Py~~|pF<br>~~Py~~|
|Rg<br>~~a OO~~|Gate Resistance<br>~~OO~~|f=1.0MHz<br>~~OO~~|-<br>~~OO~~|2<br>~~OO~~|4<br>~~OO~~|Ω<br>~~OO~~|



## **Notes:** 

1.Pulse width limited by Max. junction temperature. 

2.Pulse test 

3.Surface mounted on 1 in[2] copper pad of FR4 board, t <10sec ; 60[o] C/W at steady state. 

- 4.Package limitation current is 60A . 

- 5.Starting Tj=25[o] C , VDD=30V , L=0.1mH , RG=25 Ω 

THIS PRODUCT IS SENSITIVE TO ELECTROSTATIC DISCHARGE, PLEASE HANDLE WITH CAUTION. 

USE OF THIS PRODUCT AS A CRITICAL COMPONENT IN LIFE SUPPORT OR OTHER SIMILAR SYSTEMS IS NOT AUTHORIZED. XSEMI DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS  PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. XSEMI RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. 

**2** 

**XP4N4R2MT** ~~YaseOU~~ 

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300 200<br>T C =25 [o] C 10V T C = 150 [o] C 10V<br>7.0V 7.0V<br>6.0V 160 6.0V<br>5.0V 5.0V<br>200 V GS = 4.0V V  G S = 4.0V<br>120<br>80<br>100<br>40<br>0 AUREL 0 gestaeseeoooos<br>0 2 4 6 8 0 2 4 6 8<br>V DS  , Drain-to-Source Voltage (V) V DS  , Drain-to-Source Voltage (V)<br>              Fig 1. Typical Output Characteristics               Fig 2. Typical Output Characteristics<br>5 2.0<br>I D = 20 A I D =20A<br>T C =25 [o] C V GS  =10V<br>4.6<br>1.6<br>4.2<br>1.2<br>3.8 oe<br>0.8<br>3.4<br>3 ae 0.4 Ee<br>2 4 6 8 10 -100 -50 0 50 100 150<br>V GS  , Gate-to-Source Voltage (V) T j  , Junction Temperature ( [o] C)<br>              Fig 3. On-Resistance  v.s. Gate Voltage               Fig 4. Normalized On-Resistance<br>          v.s. Junction Temperature<br>100 2.0<br>I D =250uA<br>1.6<br>10<br>1.2<br>T j =150 [o] C T j =25 [o] C<br>0.8<br>1 |<br>0.4<br>0.1 AU) 0.0 (Heep<br>0 0.2 0.4 0.6 0.8 1 1.2 -100 -50 0 50 100 150<br>V SD  , Source-to-Drain Voltage (V) T j  , Junction Temperature ( [o] C)<br>              Fig 5. Forward Characteristic of               Fig 6. Gate Threshold Voltage v.s.<br>          Reverse Diode           Junction Temperature<br> , Drain Current (A)ID  , Drain Current (A)ID<br>)<br>Ω DS(ON)<br> (m<br>DS(ON)<br>R<br>Normalized R<br>GS(th)<br>(A)IS<br>Normalized V<br>**----- End of picture text -----**<br>


**3** 

**XP4N4R2MT** 

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10<br>I D = 20 A<br>V DS =20V<br>8<br>6<br>4<br>2<br>0<br>0 10 20 30 40 50 60<br>Q G  , Total Gate Charge (nC)<br> , Gate to Source Voltage (V)<br>GS<br>V<br>**----- End of picture text -----**<br>


**Fig 7. Gate Charge Characteristics** 

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5000 f=1.0MHz<br>4000<br>3000<br>C  iss<br>2000<br>1000<br>C oss<br>C rss<br>0<br>1 11 21 31 41 51<br>V DS  , Drain-to-Source Voltage (V)<br>C (pF)<br>**----- End of picture text -----**<br>


**Fig 8. Typical Capacitance Characteristics** 

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1000 sbaigoh bane, assum soi 1 Se aeeaa<br>100 2E O born peration in this  Sa} itii Sis Higa eX TNmp an ee Duty factor=0.5 |emma call ml||<br>area limited by<br>R DS(ON) Ss pee Soa eM easton a<br>0.2<br>10 tual AT Ra SEU —<f<br>SES Rel E =a ARES Sate ‘ Fa 0.1 0.1 LA<br>100us<br>1 a NN oo 0.05 Wa EAH P DM<br>Se eet See t aot Seer Auli t t | | | i<br>SESTAapSES3naes7SaEN ta SE): /  A 16s T Hl<br>0.1 i 1ms nn 0.02 Y Duty factor = t/T K>1<br>NSS T C =25 [o] C 10ms 0.01 Y Peak Tj = PDM x Rthjc + Tc<br>Single  Pulse DC Single Pulse<br>0.01 0.01<br>0.01 0.1 1 10 100 0.00001 0.0001 0.001 0.01 0.1 1<br>V DS  , Drain-to-Source Voltage (V) t , Pulse Width (s)<br>)thjc<br>(A)<br>ID<br>Normalized Thermal Response (R<br>**----- End of picture text -----**<br>


**Fig 9. Maximum Safe Operating Area** 

**Fig 10. Effective Transient Thermal Impedance** 

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100<br>80<br>Limited by package<br>6040 aN es<br>20<br>0<br>25 50 75 100 125 150<br>T C  , Case Temperature (  [o] C )<br> , Drain Current (A)<br>ID<br>**----- End of picture text -----**<br>


**Fig 11. Drain Current v.s. Case Temperature** 

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160<br>V DS =5V<br>120<br>80<br>j<br>f |<br>T j =150 [o] C<br>40<br>T j =25 [o] C<br>T j = -55 [o] C<br>0<br>0 1 2 3 4 5 6<br>V GS , Gate-to-Source Voltage (V)<br> , Drain Current (A)<br>ID<br>**----- End of picture text -----**<br>


**Fig 12. Transfer Characteristics** 

**4** 

**XP4N4R2MT** 

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2 80<br>I D  =1mA<br>1.6<br>poe 60 eee<br>1.2<br>eR 40<br>0.8<br>20<br>0.4<br>0 SU 0 EBPP S<br>-100 -50 0 50 100 150 0 50 100 150<br>T  j  , Junction Temperature ( [o] C) T C , Case Temperature( [o] C)<br>              Fig 13. Normalized BVDSS  v.s. JunctionDSS  v.s. Junction  v.s. Junction               Fig 14. Total Power Dissipation<br>            Temperature<br>20<br>T j =25 [o] C<br>16<br>12<br>8<br>4.5V<br>4 V GS =10V<br>0<br>0 20 40 60 80 100<br>I D  , Drain Current (A)<br>DSS<br>Normalized BV<br>, Power Dissipation(W)<br>D<br>P<br>Ω )<br>(m<br>DS(ON)<br>R<br>**----- End of picture text -----**<br>


**Fig 13. Normalized BVDSS  v.s. JunctionDSS  v.s. Junction  v.s. Junction Temperature** 

**Fig 15. Typ. Drain-Source on State Resistance** 

**5** 

**XP4N4R2MT** 

## **MARKING INFORMATION** 

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Part Number<br>4N4R2<br>YWWSSS<br>Date Code (YWWSSS)<br>          Y ： Last Digit Of  The Year<br>          WW ： Week<br>          SSS ： Sequence<br>**----- End of picture text -----**<br>


**6** 

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YAGEO<br>Packa e  Outline  :  PMPAK 5x6<br>g<br>D1<br>D2<br>H<br>i<br>SYMBOLS Millimeters<br>MIN NOM MAX<br>E2 A 0.90 1.10 1.30<br>E1 E b 0.33 0.41 0.51<br>C 0.254(Ref.)<br>mail == D1 4.80 4.90 5.10<br>D2 3.61 4.00 4.40<br>K<br>E 5.80 6.03 6.25<br>L 1 E1 (Ref.) 5.60 5.75 5.90<br>a E2 (Ref.) 3.30 3.55 3.80<br>e b L1<br>e 1.27 BSC<br>BACKSIDE VIEW<br>H 0.35 － 0.90<br>K (Ref.) 1.00 1.275 －<br>α( Reference) L 0.35 0.55 0.75<br>L1 0.06 0.13 0.20<br>α( Ref.) 0° － 12°<br>A .<br>C<br>**----- End of picture text -----**<br>


1.All dimension are in millimeters. 

2.Dimension does not include burrs and mold flash/protrusions. 

- 3.The outline schematic is not to scale and slightly different from the actual product appearance. 

Draw No.  M1-MT-8-EIFMRL-G-v08 

## **PMPAK 5x6 (E-TYPE)** 

## **PMPAK 5X6(E-TYPE)  FOOTPRINT** ： 

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Draw No.  M1-MT-8-EIFMRL-G-v08