XDPL8220XUMA1

LED Driver AC/DC, Flyback Controller, Digital PFC, 90V to 305V In, 10MHz, 20W to 150W/1 Out, DSO-16

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Manufacturer: INFINEON
Product type: AC / DC LED Driver ICs
Device Topology:Flyback; Input Voltage Min:90V; Input Voltage Max:305V; Output Voltage Max:-; Output Current Max:-; Switching Frequency:10MHz; No. of Outputs:1Outputs; IC Mounting:SMD;
SVHC: No SVHC (25-Jun-2025)
Topology: Flyback
IC Mounting: Surface Mount
No. of Pins: 16Pins
Product Range: XDP
Qualification: -
No. of Outputs: 1Outputs
Device Topology: Flyback
LED Driver Type: Isolated
Driver Case Style: DSO
IC Case / Package: DSO
Input Voltage Max: 305V
Input Voltage Min: 90V
Output Current Max: -
Output Voltage Max: -
Switching Frequency: 10MHz
Switching Frequency Typ: 10MHz
Operating Temperature Max: 85°C
Operating Temperature Min: -40°C
Automotive Qualification Standard: -
Delivery and price
Units per pack	2500
Price	1.02 €
Current stock	10+
Lead time	30 days
Datasheet
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## **XDPL8220 Digital PFC+Flyback Controller IC** 

## **XDP[™] Digital Power** 

## **Data Sheet Revision 1.0** 

**Quality Requirement Category: Industrial** 

## **Features** 

- Universal AC input (90 - 305 VAC) or DC input (90 - 305 VDC) 

- Applicable power range of 20 W to 150 W 

- Small number of external parts optimizes _**Bill of Materials (BOM)**_ and form factor 

- • High efficiency (> 90%) 

- Multicontrol mode ( _**Constant Current (CC)**_ / _**Constant Voltage (CV)**_ / _**Limited Power (LP)**_ ) reduces required product variety 

- Important parameters can be configured after manufacturing 

- Low harmonic distortion ( _**Total Harmonic Distortion (THD)**_ < 15%) 

- Low output ripple current 

- Integrated startup cell ensures fast time to light (< 250 ms) 

- Adaptive Temperature Protection 

- Ambient operating temperature -40 °C to 85 °C 

- Automatic switching between _**Quasi-Resonant Mode (QRM)**_ and _**Discontinuous Conduction Mode (DCM)**_ 

- • Wide output voltage range 

- _**Pulse Width Modulation (PWM)**_ dimming control 

- Output dimming by analog reduction of driving current down to 5% 

For safe operation, the XDPL8220 contains a comprehensive set of protection features: 

- Output overvoltage protection (open load) 

- Output undervoltage protection (output short) 

- VCC over- and undervoltage lockout 

- Input over- and undervoltage protection 

- Bus over- and undervoltage protection 

- Overcurrent protection for _**Power Factor Correction (PFC)**_ and _**Flyback (FB)**_ stage 

## **Applications** 

- Integrated _**Electronic Control Gear (ECG)**_ for _**Light Emitting Diode (LED)**_ luminaires 

Please read the Important Notice and Warnings at the end of this document 

Data Sheet **www.infineon.com** 

Revision 1.0 2016-11-4 

**XDPL8220 Digital PFC+Flyback Controller IC XDP[™] Digital Power** 

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## **Description** 

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L<br>Input<br>voltage<br>GDPFC<br>LED+<br>CSPFC<br>GDFB<br>N<br>TEMP CSFB<br>LED-<br>XDPL8220<br>HV VCC<br>VS ZCD<br>GND<br>UART PWM PWM<br>UART GND Vsupply<br>**----- End of picture text -----**<br>


## **Figure 1 Typical Application for XDPL8220** 

|**Product Type**|**Package**|
|---|---|
|XDPL8220|PG-DSO-16|



## **Description** 

XDPL8220 is a highly integrated next-generation device combining a boundary mode _**PFC**_ plus a quasi-resonant _**FB**_ controller with primary-side regulation. The integration of these functions enables saving of external parts and optimizes performance by harmonized operation of the two stages. 

XDPL8220 uses a constant on-time scheme with a _**THD**_ improvement algorithm to provide a high power factor and excellent _**THD**_ performance. 

With its unique control scheme of _**CV**_ , _**CC**_ and _**LP**_ , the _**LED**_ driver designer is provided with a large degree of flexibility and can utilize the system hardware to its limits. 

The on-chip _**One Time Programmable Memory (OTP)**_ memory has an area for parameters that control the behavior of the circuit, e. g. the output current or the maximum output power. This enables the user of the device to create a platform concept with significantly fewer different hardware versions while still covering the same application range. 

The two-stage approach reduces any variation in the output current (flicker) to a non-visible level. By separating the _**PFC**_ from the power conversion part ( _**FB**_ ), both stages operate in a more stable manner and require fewer margins, which has a positive influence on the cost. 

Lighting requires more and more 24/7 operation, making it necessary to have a stand-by mode with short wakeup times and low power consumption. The power consumption of less than 100 mW of the XDPL8220-based systems defines the new standard for stand-by power in lighting _**ECG**_ s. 

XDPL8220 enables adaptive temperature protection using either the internal sensor or an external _**Negative Temperature Coefficient Thermistor (NTC)**_ , or both. 

Futureproof flexibility with application-oriented programmable operating windows enables management of _**LED**_ generations and portfolio complexity . 

Data Sheet 

Revision 1.0 2016-11-4 

2 

**XDPL8220 Digital PFC+Flyback Controller IC XDP[™] Digital Power** 

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## **Table of contents** 

## **Table of contents** 

||**Features**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1|
|---|---|
||**Applications**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1|
||**Description**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2|
||**Table of contents**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3|
|**1**|**Functional Block Diagram**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5|
|**2**|**Pin Configuration**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6|
|**3**|**Functional Description**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8|
|3.1|PFC Controller Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9|
|3.1.1|Shared CS/ZCD Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9|
|3.1.2|Quasi-resonant Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9|
|3.1.3|Bus Voltage Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10|
|3.1.4|Input Voltage Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11|
|3.1.5|Control Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12|
|3.1.5.1|Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12|
|3.1.6|Multimode Control Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13|
|3.1.6.1|Frequency Law . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13|
|3.1.6.2|THD Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14|
|3.1.7|Peak Current Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14|
|3.1.8|Bus Undervoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14|
|3.1.9|Bus Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15|
|3.1.10|Input Undervoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15|
|3.1.11|Input Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15|
|3.1.12|Other PFC Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16|
|3.2|Flyback Controller Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17|
|3.2.1|Primary Side Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17|
|3.2.1.1|Primary Side Current Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18|
|3.2.1.2|Primary Side Output Voltage Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19|
|3.2.1.3|Flyback Bus Voltage Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20|
|3.2.1.4|Output Current Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20|
|3.2.1.5|Output Control Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21|
|3.2.1.6|Multimode Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22|
|3.2.2|Flyback Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23|
|3.2.3|Protection Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24|
|3.2.3.1|Primary Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24|
|3.2.3.2|Output Undervoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24|
|3.2.3.3|Output Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24|
|3.2.3.4|Output Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25|
|3.2.3.5|Output Overpower Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25|



Data Sheet 

Revision 1.0 2016-11-4 

3 

**XDPL8220 Digital PFC+Flyback Controller IC XDP[™] Digital Power** 

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## **Table of contents** 

|3.2.3.6|Other Flyback Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25|
|---|---|
|3.3|General Controller Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26|
|3.3.1|External Temperature Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26|
|3.3.2|Adaptive Temperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26|
|3.3.3|PWM Dimming Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27|
|3.3.4|Protection Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28|
|3.3.4.1|Overtemperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28|
|3.3.4.2|VCC Undervoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29|
|3.3.4.3|VCC Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29|
|3.3.4.4|Other General Controller Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29|
|3.3.5|Protection Reactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29|
|3.3.5.1|Auto restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30|
|3.3.5.2|Fast Auto Restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30|
|3.3.5.3|Latch Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31|
|3.3.5.4|Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31|
|**4**|**Design Support**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32|
|4.1|Design Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32|
|4.2|List of Configurable Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32|
|4.3|List of Fixed Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39|
|**5**|**Electrical Characteristics and Parameters**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40|
|5.1|Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40|
|5.2|Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40|
|5.3|Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41|
|5.4|DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42|
|**6**|**Package Dimensions**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55|
|**7**|**References**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56|
||**Abbreviations**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56|
||**Revision History**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59|
||**Trademarks**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60|



Data Sheet 

Revision 1.0 2016-11-4 

4 

**XDPL8220 Digital PFC+Flyback Controller IC XDP[™] Digital Power** 

**==> picture [105 x 47] intentionally omitted <==**

## **Functional Block Diagram** 

## **1 Functional Block Diagram** 

The functional block diagram shows the basic data flow from input pins via signal processing to the output pins. 

**==> picture [384 x 262] intentionally omitted <==**

**----- Start of picture text -----**<br>
Power Factor Correction Flyback<br>Input Voltage Output Voltage<br>HV Sensing and  Sensing and Zero  ZCD<br>Startup Crossing Detection<br>PFC Control Output Current<br>GDPFC CSFB<br>Loop Calculation<br>Current Sensing and<br>CSPFC Zero Crossing  FB Control Loop GDFB<br>Detection<br>Bus Voltage<br>VS Adaptive<br>Sensing PWM Dimming<br>Temperature  PWM<br>Sensing<br>Protection<br>VCC UART<br>VCC UART<br>Management Parametrization<br>External Internal<br>TEMP Temperature  Temperature<br>Sensing Sensing<br>**----- End of picture text -----**<br>


**Figure 2 XDPL8220 Simplified Functional Block Diagram** 

Data Sheet 

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**XDPL8220 Digital PFC+Flyback Controller IC XDP[™] Digital Power** 

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## **Pin Configuration** 

## **2 Pin Configuration** 

Pin assignments and basic pin description information are shown below. 

|||||||||||
|---|---|---|---|---|---|---|---|---|---|
|GDFB||||1|16||||N.C.|
|||||||||||
|CSFB||||2|15||||N.C.|
|||||||||||
|VCC||||3|14||||N.U.|
|||||||||||
|GND||||4|13||||GDPFC|
|||||||||||
|ZCD||||5|12||||UART|
|||||||||||
|VS||||6|11||||CSPFC|
|||||||||||
|N.U.||||7|10||||TEMP|
|||||||||||
|HV||||8|9||||PWM|
|||||||||||
||||PG-DSO-16(150mil)|||||||



## **Figure 3 Pinning of XDPL8220** 

## **Table 1 Pin Definitions and Functions** 

|**Name**|**Pin**|**Type**|**Function**|
|---|---|---|---|
|GDFB|1|O|Gate driver for**_FB_**:<br>The GDFB pin is an output for directly driving a power MOSFET of the**_FB_**<br>stage.|
|CSFB|2|I|Current sensing for**_FB_**:<br>The CSFB pin is connected to an external shunt resistor and the source of the<br>power MOSFET of the**_FB_**stage.|
|VCC|3|I|Voltage supply|
|GND|4|-|Power and signal ground|
|ZCD|5|I|Zero-crossing detection of the**_FB_**:<br>The ZCD pin is connected to an auxiliary winding of the**_FB_**stage for zero-<br>crossing detection as well as primary-side output voltage and backup bus<br>voltage sensing for safety.|
|VS|6|I|Bus voltage sensing|
|N.U.|7|-|Not used. Externally to be connected to GND.|
|HV|8|I|High voltage:<br>The HV pin is connected to the rectified input voltage via an external resistor.<br>An internal 600 V HV startup-cell is used to initially charge VCC. In addition,<br>sampled high-voltage sensing is also used for synchronization with the input<br>frequency.|
|PWM|9|I|**_PWM_**dimming:<br>The PWM pin is used as a dimming input.|
|TEMP|10|I|External temperature sensor:<br>Measurement of external temperature using an**_NTC_**.|
|CSPFC|11|I|Current sensing for**_PFC_**:<br>The CSPFC pin is connected to an external shunt resistor and the source of<br>the power MOSFET of the**_PFC_**stage.|



Data Sheet 

Revision 1.0 2016-11-4 

6 

**XDPL8220 Digital PFC+Flyback Controller IC XDP[™] Digital Power** 

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## **Pin Configuration** 

## **Table 1 Pin Definitions and Functions (continued)** 

|**Name**|**Pin**|**Type**|**Function**|
|---|---|---|---|
|UART|12|I/O|**_Universal Asynchronous Receiver Transmitter (UART)_**communication:<br>The UART pin is used for the**_UART_**interface to support parameterization.|
|GDPFC|13|O|Gate driver for**_PFC_**:<br>The GDPFC pin is an output for directly driving a power MOSFET of the**_PFC_**<br>stage.|
|N.U.|14|-|Not used. Externally to be connected to GND.|
|N.C.|15|-|Not connected.|
|N.C.|16|-|Not connected.|



Data Sheet 

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**XDPL8220 Digital PFC+Flyback Controller IC XDP[™] Digital Power** 

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## **Functional Description** 

## **3 Functional Description** 

This chapter provides a summary of the integrated functions and features, and describes the relationships between them. The parameters and equations are based on typical values at TA = 25 °C. 

XDPL8220 is a digital dual-stage _**PFC**_ and _**FB**_ controller IC supporting _**PWM**_ dimming functionality. Both stages use configurable multimode operation to select the best mode of operation for every operation condition. Multimode operation automatically switches between _**Quasi-Resonant Mode, switching in valley n (QRMn)**_ and _**DCM**_ . 

XDPL8220 features a comprehensive set of configurable protection modes to detect fault conditions. XDPL8220 provides a high degree of flexibility in design-in of the application. A _**Graphic User Interface (GUI)**_ tool supports users in the configuration of the operational and protection parameters. 

Data Sheet 

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## **Functional Description** 

## **3.1 PFC Controller Features** 

The _**PFC**_ stage ensures high power quality by maximizing the power factor and minimizing harmonic distortion. The _**PFC**_ stage operates in _**Quasi-Resonant Mode, switching in valley 1 (QRM1)**_ and _**QRMn**_ , to support low load conditions and ensure efficient operation. 

The _**PFC**_ stage is implemented as a boost converter. It drains a sinusoidal current from the single-phase line supply and provides stabilized _**Direct Current (DC)**_ voltage at the internal bus voltage rail. The power factor of the single-phase line supply is almost one. Fluctuations in line voltage as well as voltage drops of short duration are compensated. 

## **3.1.1 Shared CS/ZCD Function** 

The _**PFC**_ stage makes use of combined CS/ZCD functionality at the CSPFC pin. 

During the gate driver on-time the pin acts as a current sense (CS), while during the gate driver off-time the pin acts as a zero-crossing-detector (ZCD). The CS senses the on-time current and implements overcurrent limitation; the ZCD exploits the quasi-resonant function to minimize conduction losses. 

The CSPFC pin is connected via a resistor divider composed of RZCD,1,PFC and RZCD,2,PFC and a set of diodes to an auxiliary winding of the _**PFC**_ choke inductor. It is used for detecting the valleys of the quasi-resonant oscillation to turn on the _**PFC**_ MOSFET based on the desired valley computed by the multimode _**PFC**_ control. The diode D1 allows positive voltage at the CSPFC pin as the valley detection is implemented by the internal hysteretic comparator with a positive reference of nominal THRHYS for falling edges. The CSPFC pin senses the drain source current of the switching MOSFET. The CS voltage is measured after a programmable blanking time after turn-on of the switch. An appropriate current sensing resistor RCS,PFC is selected on the basis of the maximum current flowing in the switching MOSFET and the dynamic voltage range of the input pin CSPFC. 

**==> picture [272 x 203] intentionally omitted <==**

**----- Start of picture text -----**<br>
Vg L Vbus<br>RZCD,1,PFC<br>D1<br>GDPFC<br>CSPFC<br>RCS,PFC RZCD,2,PFC<br>VCC<br>**----- End of picture text -----**<br>


**Figure 4 Shared CS/ZCD Schematic** 

## **3.1.2 Quasi-resonant Mode** 

The quasi-resonant mode maintains a high efficiency level. 

For _**PFC**_ operating in _**QRM1**_ , the main switch is turned on with a constant on-time for a line and load condition, while the off-time/demagnetization time varies within an _**Alternating Current (AC)**_ half-cycle depending on the instantaneously rectified _**AC**_ input voltage Vg. Subsequently, the switching frequency varies within each _**AC**_ halfcycle with the lowest switching frequency at the peak of the _**AC**_ input voltage and the highest switching frequency near the zero crossings of the input voltage. A new switching cycle starts immediately when the first QR valley is reached. 

Data Sheet 

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## **Functional Description** 

_**QRM1**_ is ideal for full-load operation, where the on-time is large. However, the on-time reduces at light loads, resulting in very high switching frequencies, particularly near the zero crossings of the input voltage. The high switching frequency will increase switching losses, resulting in poor efficiency at light loads. The _**PFC**_ multimode control can lower the switching frequency by selecting further valleys to achieve QRM2 up to N valley,max,PFC operation. The switching frequency is limited within a defined range and the efficiency at light loads improves. 

**==> picture [221 x 190] intentionally omitted <==**

**----- Start of picture text -----**<br>
tsw tsw<br>iL<br>1 iL,pk<br>2 [i] L , pk tw iL,ave<br>0<br>t on t 1stV t<br>vCSPFC tosc<br>4<br>vL,pk<br>vL,sampled<br>0<br>ton t disch t<br>2<br>QRM1 QRM2 QRM1<br>**----- End of picture text -----**<br>


## **Figure 5 PFC QRM2 Waveforms** 

The equations for the quasi-resonant operation are shown below, where tw is an additional delay in each switching cycle when selecting subsequent valleys after the first QR valley and n is the valley number in _**QRMn**_ . 

_i V g_ · _ton L_ , _pk_ = _L i L tdisch_ = _V L_ , _pk_ · _V bus_ − _g t_ 1 _stV_ = _tdisch_ + _tosc_ /2 _t t n_ −1 _w_ = _osc_ · _tsw_ = _ton_ + _t_ 1 _stV_ + _tw t_ = _t t off_ 1 _stV_ + _w_ 

## **Equation 1** 

## **3.1.3** 

## **Bus Voltage Sensing** 

The bus voltage is measured at the VS pin. 

The VS pin implements _**PFC**_ bus voltage sensing for bus voltage regulation. The bus voltage is scaled down using a simple resistor divider. A capacitor could in certain cases be added at the pin to ground to filter highfrequency switching noise. The bus voltage sensing is a low leakage input and no additional measures are needed to reduce the current consumption. 

Data Sheet 

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## **Functional Description** 

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**----- Start of picture text -----**<br>
Vbus<br>RVS,1<br>VS<br>RVS,2<br>**----- End of picture text -----**<br>


## **Figure 6 Bus Voltage Sensing Schematic** 

The _**Analog-to-Digital Converter (ADC)**_ input at the VS pin utilizes two voltage ranges. The wider voltage range from 0 to VREF results in lower resolution. The narrower voltage range from 5/6 VREF to 7/6 VREF gives better voltage resolution. Steady state operation therefore normally takes place in the high-resolution range and soft start operation in the low-resolution range. 

**==> picture [342 x 190] intentionally omitted <==**

**----- Start of picture text -----**<br>
VS<br>7/6 VREF<br>High<br>VREF resolution<br>range<br>5/6 VREF<br>Low<br>resolution<br>range<br>0 V<br>t<br>**----- End of picture text -----**<br>


**Figure 7 Sensing Ranges** 

## **3.1.4 Input Voltage Sensing** 

The input voltage is sensed using the HV pin. 

The input voltage is used for protection, to generate _**AC**_ zero-crossing signals and to detect the AC/DC source. 

Data Sheet 

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## **Functional Description** 

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**----- Start of picture text -----**<br>
iac<br>vac<br>Input<br>voltage<br>RHV<br>Vin<br>HV<br>C1 C2<br>{<br>**----- End of picture text -----**<br>


## **Figure 8 Input Voltage Sensing Schematic** 

The RHV probing resistor is usually split into two, or three or more resistors for safety purposes. In fact in case of a resistor being shorted by damage, the high resistive path is maintained by the other resistors avoiding fire, shock to the user and further damage to the application. 

A RC filter structure making use of the split resistors filters the unwanted noise for the high voltage input voltage measurement. The filtering effect is kept high due to the usage of the high impedance split resistors and the addition of small capacitance high voltage capacitors. 

## **3.1.5** 

## **Control Scheme** 

The _**PFC**_ bus voltage controller embeds a PIT1 controller that calculates a control output representing load and line conditions from the bus voltage error signal. 

The bus voltage controller implements regulation during both soft start and steady states. 

## **3.1.5.1** 

## **Startup** 

At system startup, the _**PFC**_ initiates a soft start to minimize the switching stress for the power MOSFET, diode and inductor. 

The soft start is executed when the bus voltage is higher than the Vbus,start,PFC threshold. This is the brown-in condition. The soft start is aborted if the input under- or overvoltage protection fire. During soft start, the _**PFC**_ stays in _**QRM1**_ operation. Once the Vbus,stdy,entr,UV threshold is reached, the steady state _**PFC**_ operation starts. 

Data Sheet 

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## **Functional Description** 

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**----- Start of picture text -----**<br>
Vbus<br>Vbus,set<br>Vbus,stdy,entr,UV<br>Vbus,start,PFC<br>t<br>VCC startup steady state<br>passive charging<br>charging<br>**----- End of picture text -----**<br>


**Figure 9 Vbus Soft Start and Regulation** 

## **3.1.6** 

## **Multimode Control Scheme** 

The multimode control scheme provides a _**PFC**_ option to dynamically change the operating point by switching between the MOSFET Vds voltage valleys while following a frequency law and applying _**THD**_ optimization. The multimode controller uses two different modes of operation: 

- _**QRM1**_ : This operation maximizes the efficiency by switching on the 1st valley of the _**PFC**_ ZCD signal. This ensures zero current switching with a minimum of switching losses. 

- _**QRMn**_ : The controller will extend to the next switching valley after the 1st valley to control the bus voltage following a frequency law. 

The multimode optimization consists of the following: 

- Frequency law 

- THD optimization 

## **3.1.6.1 Frequency Law** 

The output of the _**PFC**_ PIT1 bus voltage controller gives the desired on-time, which is constant within each _**AC**_ half cycle. A _**PFC**_ is used to emulate a resistive load re to the _**AC**_ input such that iac follows vac in both wave shape and phase. The output of the _**PFC**_ bus voltage controller ton,des,PFC is inversely proportional to the emulated resistive load re such that a smaller re or a higher Iac,rms will give a larger ton,des,PFC. Thus, ton,des,PFC is different for the same load at different line voltages and is proportional to the RMS input current Iac,rms. 

The rule for selecting _**QRMn**_ is based on the frequency law. A maximum switching frequency fswmax and a minimum switching frequency fswmin are defined for the complete ton,des,PFC/Iac,rms range. The frequency law ensures that the switching frequency is within the desired frequency range. The frequency law is depicted in the figure below. 

Data Sheet 

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## **Functional Description** 

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**----- Start of picture text -----**<br>
fsw<br>fswmax<br>fswmin<br>sample ton,des,PFC<br>operating   / Iac,rms<br>point<br>QRM5QRM4QRM3QRM2QRM1<br>**----- End of picture text -----**<br>


## **Figure 10 PFC Frequency Law** 

As long as the _**PFC**_ controller operating mode fulfills the frequency law, the operating mode does not change. The QR-valley is increased when the highest frequency limit is reached. The QR-valley is decremented when the lowest frequency limit is reached. 

To ensure good ZCD detection before the ZCD signal becomes too small in amplitude, only the first up to Nvalley,max,PFC valleys operations are supported. 

## **3.1.6.2** 

## **THD Optimization** 

_**THD**_ optimization reduces the _**THD**_ in the case of light loads and in the case of high _**AC**_ input voltages. 

The selection of higher valleys helps to reduce the switching frequency but it also distorts the input current waveform with constant on-time control and thus affects the _**PFC THD**_ performance. The multimode _**PFC**_ control also consists of a _**THD**_ optimization algorithm that optimizes the applied on-time in order to ensure good input current shaping and improved _**PFC THD**_ performance. 

## **3.1.7** 

## **Peak Current Limitation** 

The peak current through the switching MOSFET is read via the _**PFC**_ shunt resistor RCS,PFC to limit the maximum current through the MOSFET, the choke, and freewheeling diode so as to avoid potential hard failure or lifetime stress. 

The OCP causes the current to be limited to cases in which an overcurrent condition occurs. _**Overcurrent Protection Level 1 (OCP1)**_ is implemented by hardware. If the voltage VCS,PFC across the shunt resistor exceeds the overcurrent threshold VCS,OCP1, PFC for longer than the blanking time tblank,OCP1,PFC, the MOSFET is turned off. The MOSFET is turned on when ZCD occurs or the PFC maximum period time-out signal triggers the start of the next switching cycle. _**Overcurrent Protection Level 2 (OCP2)**_ is a second-level overcurrent protection implemented by hardware. The _**OCP2**_ overcurrent threshold is fixed. The _**OCP2**_ blanking time is tblank,OCP2,PFC. 

## **3.1.8** 

## **Bus Undervoltage Protection** 

Undervoltage detection of the bus voltage Vbus is provided by measurement using the VS pin. The bus voltage is compared to a configurable undervoltage protection threshold Vbus,UV. If the threshold is exceeded for longer than the blanking time tblank,Vbus,UV, the protection will be triggered. 

Data Sheet 

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## **Functional Description** 

## **3.1.9 Bus Overvoltage Protection** 

Overvoltage detection of the bus voltage Vbus is provided by the measurement using the VS pin. 

The bus voltage is compared to a configurable overvoltage protection threshold Vbus,OVP1 in _**Firmware (FW)**_ . If a threshold is exceeded for longer than the blanking time tblank,Vbus,OVP1, the gate driver stops. The gate driver operation is resumed when Vbus falls below Vbus,stdy,entr,OV. 

Vbus,OVP2 is implemented in _**Hardware (HW)**_ and it is fixed at a voltage which is represented as 2.8 V at the bus voltage sensing pin (VS). The HW permits a blanking time tblank,Vbus,OVP2 to be programmed. 

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**----- Start of picture text -----**<br>
Vbus<br>Vbus,ovp2<br>Vbus,ovp1<br>Vbus,stdy,entr,OV<br>Vbus,set<br>Vbus,uv<br>t<br>**----- End of picture text -----**<br>


## **Figure 11 Vbus protections** 

## **3.1.10 Input Undervoltage Protection** 

Undervoltage detection of the input voltage Vin is provided by measurement using the HV pin. 

Values of Vin,rms are compared to a configurable input undervoltage protection threshold Vin,UV. If the threshold is exceeded for longer than the blanking time tblank,Vin,UV, the protection will be triggered. XDPL8220 features a configurable startup threshold Vin,start,min to create hysteresis for flicker-free operation before the second stage starts switching. After startup checks when trms,reset,PFC expires, the comparison is restored to the threshold value Vin,UV. 

## **3.1.11 Input Overvoltage Protection** 

Overvoltage detection of the input voltage Vin is provided by measurement using the HV pin. 

Values of Vin,rms are compared to a configurable input overvoltage protection threshold Vin,OV. If the threshold is exceeded for longer than the blanking time tblank,Vin,OV, the protection will be triggered. XDPL8220 features a configurable startup threshold Vin,start,max to create hysteresis for flicker-free operation before the second stage starts switching. After startup checks when trms,reset,PFC expires, the comparison is restored to the threshold value Vin,OV. 

_Note_ : _In the csv file the input OVP shall be disabled by default._ 

Data Sheet 

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## **Functional Description** 

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**----- Start of picture text -----**<br>
Vin<br>Vin,OV<br>Vin,start,max<br>Vin,start,min<br>Vin,UV<br>t<br>trms,reset,PFC<br>**----- End of picture text -----**<br>


**Figure 12 Vin protections** 

## **3.1.12 Other PFC Protections** 

## **CS Resistor Short Protection** 

The input circuit breaker (fuse) shall be chosen appropriately in order to protect in case of current-sense resistor short. 

## **CS Resistor Open Protection** 

The external circuitry for shared CS/ZCD pulls the CSPFC pin high in case of CS resistor missing so that the OCP2 protection is triggered. 

## **CSPFC Pin Short to GND Protection** 

In case of CSPFC pin short to ground the lack of quasi-resonant oscillations shall trigger the CCM Protection. 

## **CCM Protection** 

Continuous conduction mode (CCM) operation may occur during _**PFC**_ startup for a limited time. It is considered as a failure in the system only if CCM operation of the _**PFC**_ converter is observed over a longer period of time. The _**PFC**_ converter may run into CCM operation for a longer period due to a shorted bypass diode, a heavy load step that is out of specification or very low input voltage outside the normal operating range. 

When CCM occurs, the magnetizing current in the _**PFC**_ choke does not have the chance to decay to zero before the MOSFET turns on. No quasi-resonant oscillation will be seen at the ZCD signal before the maximum switching period time-out is reached that turns the MOSFET on. This turn-on event without ZCD oscillation is monitored to protect the _**PFC**_ converter from continuous CCM operation. The CCM protection is implemented by firmware. 

If any quasi-resonant oscillation is seen at the ZCD signal for longer than the blanking time tblank,CCM,PFC, the protection is triggered. 

## **Soft Start Failure** 

The soft start may take a long time, potentially never reaching steady state operation due to heavy loads or very low input voltages. If tstart,PFC reaches tstart,max,PFC before the soft start has ended, the protection is triggered. 

Data Sheet 

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## **Functional Description** 

## **3.2 Flyback Controller Features** 

The _**FB**_ stage provides primary side control that avoids secondary side control feedback loop circuitry usually needed in isolated power converters. This approach supports a low part count to reduce costs. 

The _**FB**_ stage features multi-mode operation and it selects the best mode of operation based on operating conditions. 

## **3.2.1 Primary Side Regulation** 

The _**FB**_ in XDPL8220 provides primary side control of output current and output voltage. No external feedback components are necessary for the current control as the primary side regulation control loop is fully integrated. 

_**Figure 13**_ shows typical current and voltage waveforms of the _**FB**_ application operating in _**QRM1**_ . 

In _**DCM**_ , the next switching cycle will not start at the first valley of VAUX, but is instead delayed. As a consequence, the switching losses in _**DCM**_ will be higher. 

The primary peak current Ip,pk, the period of conduction of the output diode tdemag and the switching period tsw,FB are used to calculate the average output current. 

The voltage signal VAUX of the auxiliary winding of the transformer contains information on the reflected output voltage Vout. The reflected output voltage is measured at the ZCD pin using a resistor divider. 

Data Sheet 

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## **Functional Description** 

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**----- Start of picture text -----**<br>
VAUX<br>Output voltage<br>sampling<br>Zero crossing detection<br>0 V<br>Bus voltage<br>Valley switching<br>sampling<br>Ip Is<br>time<br>Vbus Vout<br>tCS,sample tZCD,sample<br>Itransformer Np Ns<br>tsw,FB Na<br>Ip,pk<br>VAUX<br>Ip Ip<br>Is<br>time<br>tdemag<br>VGD<br>time<br>**----- End of picture text -----**<br>


**Figure 13 Typical Waveforms of a Flyback Converter** 

## **3.2.1.1 Primary Side Current Sensing** 

The primary side peak current Ip,pk is controlled by the control loop using the VCS,OCP1 level at the CSFB pin. This control scheme ensures suppression of any variation in the bus voltage. 

Several delays exist from the time at which the _**OCP1**_ level VCS,OCP1 is exceeded at the CSFB pin until the gate switches off and the transformer current finally reaches its peak value. For a higher accuracy, the primary peak current VCS,SH is sampled a fixed time before turn-off of the gate. The primary side peak current is used to calculate the secondary side current and for protection. The propagation delay compensation parameter tPDC allows optimization of the accuracy of the primary side peak current: 

**==> picture [147 x 25] intentionally omitted <==**

## **Equation 2** 

Data Sheet 

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## **Functional Description** 

_Note_ : _If an RC low pass filter is added in front of the CSFB pin, the related low pass filter delay has to be included in t_ PDC _._ 

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**----- Start of picture text -----**<br>
Ip<br>VCS,pk<br>Ip,pk =<br>RCS,FB<br>VCS,SH<br>RCS,FB<br>t<br>tPDC<br>VGD<br>tCSFB,offset<br>t<br>ton,FB<br>**----- End of picture text -----**<br>


**Figure 14 Propagation Delay Compensation for accurate Primary Peak Current Calculation** 

## **3.2.1.2 Primary Side Output Voltage Sensing** 

The output voltage is determined by measuring the reflected output voltage on the auxiliary winding. A resistor divider adapts the voltage to the operating range of the ZCD pin. 

The output voltage is measured at the ZCD pin using the voltage VZCD,SH at the end of the demagnetization time at the time tZCD,sample. The voltage measured at the ZCD pin, the dimensioning of the resistor dividers _R_ ZCD,FB,1 and _R_ ZCD,FB,2 , transformer turns _Ns_ and _Na_ as well as an offset _V_ out,offset (caused by the secondary diode, for example) are used to calculate the output voltage Vout as follows: 

**==> picture [210 x 25] intentionally omitted <==**

## **Equation 3** 

Vout is used for _**Primary Side Regulated (PSR)**_ control loops in _**CV**_ and _**LP**_ modes as well as for output over- and undervoltage protections. 

**==> picture [239 x 98] intentionally omitted <==**

**----- Start of picture text -----**<br>
Vout,offset<br>Na Ns<br>RZCD,FB,1 VOut<br>ZCD<br>VZCD,SH RZCD,FB,2<br>**----- End of picture text -----**<br>


## **Figure 15 Primary Side Output Voltage Sensing using ZCD S&H** 

_Note_ : _Any relation between VCC and ZCD in self-supplied applications can be decoupled – e.g. by adding a linear regulator for VCC._ 

Data Sheet 

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## **Functional Description** 

_**Attention**_ : _**Please note that the time (t**_ **demag** _**) has to be longer than 2.0**_ **μ** _**s to ensure that the reflected output voltage can be sensed correctly at the ZCD pin.**_ 

## **3.2.1.3 Flyback Bus Voltage Sensing** 

The _**FB**_ can sense the bus voltage using the reflection of bus voltage on the auxiliary winding while the gate is turned on. A resistor divider adapts the negative voltage to the operating range of the ZCD pin. This second measurement path is required to protect against component failures in the VS measurement path (open loop protection for the _**PFC**_ stage). 

The reflected bus voltage appears as a negative voltage at VAUX. This negative voltage is internally clamped at the ZCD pin to the negative voltage VINPCLN. The internal clamping current IZCD is measured at the end of the ontime at the time tCS,sample. The measured clamping current of the ZCD pin, the dimensioning of the resistor dividers RZCD,FB,1 and RZCD,FB,2 as well as the number of transformer turns Na and Np are used to calculate the bus voltage Vbus,FB as follows: 

**==> picture [216 x 26] intentionally omitted <==**

## **Equation 4** 

Vbus,FB is used for plausibility checks with the voltage Vbus as measured using the VS pin. 

**==> picture [173 x 84] intentionally omitted <==**

**----- Start of picture text -----**<br>
Na Np<br>RZCD,FB,1 Vbus,FB<br>IZCD<br>ZCD<br>VINPCLN RZCD,FB,2<br>**----- End of picture text -----**<br>


## **Figure 16 Voltage Sensing using ZCD Clamp Current** 

## **3.2.1.4 Output Current Calculation** 

The output current is calculated based on the primary side peak current and the timing of the switching cycle. 

The output current Iout is calculated using the duration of conduction of the output diode tdemag, the switching period tsw,FB as well as the number of transformer turns Np, Ns and the transformer coupling Kcoupling. The following equation is valid both in _**QRM1**_ and _**DCM**_ : 

**==> picture [157 x 26] intentionally omitted <==**

## **Equation 5** 

The coupling of the transformer can be approximated using the transformer primary inductance Lp and the transformer primary leakage inductance Lp,lk as follows: 

**==> picture [83 x 26] intentionally omitted <==**

## **Equation 6** 

The calculated current Iout is used for the control loop in the modes _**CC**_ and _**LP**_ . The calculated current is also used for output overcurrent protection. 

Data Sheet 

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## **Functional Description** 

## **3.2.1.5 Output Control Scheme** 

The XDPL8220 includes three different control schemes for a _**CC**_ , _**CV**_ or _**LP**_ output. 

Different use cases require the controller to operate according to different operation schemes: 

- In the case of typical LED strings, the forward voltage of the LED string determines the output voltage of the driver. XDPL8220 operates in _**CC**_ and drives a constant output current Iout,full to the load. The forward voltage of the connected LED string has to be below a configurable maximum value Vout,set. 

- In the case of LED loads including a power stage (e.g. Infineon BCR linear regulators or Infineon DC/DC buck ILD2111), XDPL8220 operates in _**CV**_ , ensuring a constant voltage Vout,set to the load. The total output current drawn by the load has to be below a configurable maximum value Iout,full. 

- In the case of a high output current setpoint Iout,full and an overly long LED string which exceeds the configurable power limit Pout,set, XDPL8220 operates in _**LP**_ to ensure that the power limit of the driver is not exceeded. The controller reduces the output current automatically, ensuring light output without any interruption even for overly long LED strings. The forward voltage of the connected LED string has to be below a configurable maximum value Vout,set. 

For every update of the control loop, the control scheme is selected on the basis of the current operation conditions (output voltage Vout and output current Iout) and their distance to the three limiting setpoints (Vout,set, Pout,set and Iout,full): 

- For _**CC**_ schemes, the internal reference current Iout,full is weighted according to thermal management and a dimming curve to yield Iout,set. The calculated output current Iout is compared with the weighted reference current Iout,set to generate an error signal for the output current. 

- For _**CV**_ schemes, the sensed output voltage Vout at the ZCD pin is compared to a reference voltage Vout,set to generate an error signal for the output voltage. 

- For _**LP**_ schemes, the output current is limited to a maximum of Iout,set = Pout,set / Vout. 

- Out of these three schemes, for each step the most critical error is selected (see _**Figure 17**_ ): 

**1.** If any setpoint is exceeded, the largest error for power decrease is selected to bring the controller back to the desired operating point as quickly as possible. 

**2.** If the current operating conditions are below all three setpoints, the smallest error for power increase is selected to avoid overshooting any setpoint. 

The selected error signal is fed into a compensator to control the gate driver switching parameters (i.e. duty cycle and frequency) for the power MOSFET of the _**FB**_ . 

**==> picture [336 x 191] intentionally omitted <==**

**----- Start of picture text -----**<br>
Output<br>voltage Output<br>open<br>Vout,OV Pout,set<br>Vout,set Pout,OPP<br>Constant voltage<br>Limited<br>power<br>Constant<br>current<br>Vout,start Output<br>Vout,UV short<br>Output current<br>Iout,min Iout,full Iout,OCP<br>**----- End of picture text -----**<br>


## **Figure 17 Control Scheme for CC/CV/LP Modes (Non-Dimmed)** 

In dimming cases, the output current setpoint Iout,set is located between Iout,min and Iout,full and varies according to the sensed _**PWM**_ duty cycle DDIM. Dimming can be visualized by moving the vertical line for the output current setpoint in _**Figure 18**_ from right to left. 

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## **Functional Description** 

_Note_ : _An operation in limited power mode can cause dimmer dead-travel until the controller enters constant current mode._ 

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**----- Start of picture text -----**<br>
Output<br>voltage Output<br>Legend:<br>open<br>Vout,OV Pout,set Operating range<br>Constant voltage<br>Vout,set<br>Limited<br>power<br>Dimming Constant<br>current<br>Vout,start Output<br>Vout,UV short<br>Dim-to-Off<br>Output current<br>Iout,min Iout,full<br>**----- End of picture text -----**<br>


## **Figure 18 Control Scheme for CC/CV/LP Modes (including Dimming)** 

One or more of the output control schemes can be deactivated by configuration of the setpoints. Some examples are given below: 

- The _**LP**_ scheme is not active for Pout,set > Vout,set * Iout,full. For such a configuration, the controller will only select between a _**CC**_ and _**CV**_ scheme. 

- The _**CV**_ scheme is not active for Vout,set = Vout,OV as the output overvoltage protection will be triggered. 

- The _**CC**_ scheme is not active for Iout,full = Iout,OC as the output overcurrent protection will be triggered. 

## **3.2.1.6 Multimode Scheme** 

The control loop of XDPL8220 uses two different switching modes. _**QRM1**_ is optimized for high efficiency at high loads while _**DCM**_ is used in light load conditions. 

**==> picture [240 x 151] intentionally omitted <==**

**----- Start of picture text -----**<br>
Power<br>VCS,max,FB<br>Peak-current controlled<br>Pmax QRM1<br>VCS,min,FB<br>tsw,min,FB<br>Frequency controlled<br>DCM<br>Pmin tsw,max,FB<br>Bus Voltage<br>Vbus,UV Vbus,OVP1<br>**----- End of picture text -----**<br>


## **Figure 19 Flyback Multimode Operation Scheme** 

- _**QRM1**_ : This mode maximizes the efficiency by switching on the 1st valley of the VAUX signal. This ensures zero current switching with a minimum of switching losses. The power is controlled by regulating the primary peak current using VCS,OCP1. 

- _**DCM**_ : This mode is used if VCS,OCP1has reached its minimum value VCS,min,FB. To allow lower output power, the controller extends the switching period later than the 1st valley . 

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## **Functional Description** 

The minimum power is limited by the transformer primary inductance Lp, maximum switching period tsw,max,FB and minimum primary peak current Ip,pk,min: 

**==> picture [159 x 21] intentionally omitted <==**

**----- Start of picture text -----**<br>
1 2 1<br>P  ⋅<br>min = 2 [⋅] [L][p] [⋅] [I][p] [, pk, min] t<br>sw, max, FB<br>**----- End of picture text -----**<br>


## **Equation 7** 

The minimum primary peak current Ip,pk,min is restricted by: 

|_Ip_, pk, min=_t_demag, min⋅<br>_Np_<br>_Ns_ ⋅|_V_out,OV|
|---|---|
||_Lp_|



## **Equation 8** 

_Note_ : _If the load drops below the minimum load of P_ min _, the output voltage will rise up to the output overvoltage threshold V_ out,OV _and trigger the protection. An auto-restart can be used to keep the output voltage close to V_ out,OV _until the load increases again._ 

## **3.2.2 Flyback Startup** 

_**FB**_ After startup, the of the XDPL8220 initiates a soft start to minimize the switching stress for the power MOSFET and secondary diode. 

The cycle-by-cycle current limit is increased in steps of VCS,step with a configurable duration tsoftstart for each step. After the final VCS,OCP1,start limit level has been reached, the output will be charged until the minimum output voltage Vout,start, which ensures self-supply has been reached. At this condition, _**Continuous Conduction Mode (CCM)**_ protection as well as output undervoltage protection are activated and the control loop takes over. The starting point for the control loop is to operate in DCM at lowest switching frequency and shortest on-time. These switching parameters avoid any overshoot of output current for short LED string in dimmed conditions. 

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**----- Start of picture text -----**<br>
Output voltage<br>Peak current<br>Startup Control loop<br>Output active<br>Soft start phase charging<br>phase<br>Vout<br>Vout,start<br>VCS,OCP1<br>VCS,OCP1,start<br>Startup Check<br>VCS,step<br>time<br>tsoftstart<br>**----- End of picture text -----**<br>


**Figure 20 Flyback Startup Sequence** 

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## **Functional Description** 

## **3.2.3 Protection Features** 

Protections ensure the operation of the controller under restricted conditions. Protections are triggered if fault conditions are present longer than the blanking times configured for each protection _**[3)]**_ . The controller will react to a triggered protection as configured. 

_**Attention**_ : _**The controller may continue operation after exceeding protection thresholds because of blanking times. All protection thresholds have to be set with respect to tolerances, blanking times and worst case transients.**_ 

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**----- Start of picture text -----**<br>
Value Value<br>Upper<br>Threshold<br>Lower<br>Threshold<br>Time Time<br>tblank tblank<br>**----- End of picture text -----**<br>


**Figure 21 Blanking Times cause Excess of Threshold** 

## **3.2.3.1 Primary Overcurrent Protection** 

The primary side overcurrent protection implemented in hardware covers fault conditions like a short in the transformer primary winding or an open CS pin. 

The primary side current is compared to a configurable overcurrent protection threshold VCS,OCP2. If the threshold is exceeded for longer than the blanking time tOCP2,FB, the protection will be triggered. 

## **3.2.3.2 Output Undervoltage Protection** 

In the case of a short in the output, the output voltage may drop to a very low level. Detection of undervoltage in the output voltage Vout is enabled by measurement of the reflected voltage at the ZCD pin. 

During operation, the output voltage is compared to a configurable undervoltage protection threshold Vout,UV. If the threshold is exceeded for longer than the blanking time tblank,out,UV, the protection will be triggered. This protection threshold Vout,UV is disabled during startup. 

During startup, the protection operates differently: In case the _**FB**_ cannot charge the output voltage to Vout,start during a timeout of tstart,max,FB, the protection will be triggered. This timeout starts when the _**FB**_ is started. 

_Note_ : _The startup threshold V_ out,start _has to be configured over and above the undervoltage threshold V_ out,UV _to allow undershoots at startup which may occur, especially for resistive loads._ 

## **3.2.3.3 Output Overvoltage Protection** 

In case of a open output, the output voltage may rise to a high level. Overvoltage detection of the output voltage Vout is provided by measurement at the ZCD pin. 

The output voltage is compared to a configurable overvoltage protection threshold Vout,OV. If the threshold is exceeded for longer than the blanking time tblank,out,OV, the protection will be triggered. 

> 3 except VCC undervoltage protection 

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## **Functional Description** 

_Note_ : _The blanking time t_ blank,Vout,OV _should be set to the minimum value to minimize overshoots of the output voltage above the protection threshold._ 

_Note_ : _This protection is usually triggered if the output is open or the output load drops below the minimum load P_ min _._ 

## **3.2.3.4 Output Overcurrent Protection** 

Overcurrent detection in the output current Iout is provided on the basis of the calculated output current. 

The calculated output current is compared to a configurable overcurrent protection threshold Iout,OC. If the threshold is exceeded for longer than the blanking time tblank,out,OC, the protection will be triggered. 

## **3.2.3.5 Output Overpower Protection** 

Overpower detection in the output power Pout is provided on the basis of the calculated output power. 

The calculated output power is compared to a configurable overpower protection threshold Pout,OP. If the threshold is exceeded for longer than the blanking time tblank,out,OP, the protection will be triggered. 

## **3.2.3.6 Other Flyback Protections** 

XDPL8220 includes additional protections to ensure the integrity and correct flow of the firmware. 

- A hardware weak pull-up protects against an open CSFB pin. 

- A firmware watchdog protects against the CSFB pin becoming shorted to GND. 

- A firmware state monitor supervises correct operation of the flyback in _**QRM1**_ or _**DCM**_ . A protection is triggered if the flyback enters _**CCM**_ . 

- A firmware check ensures that the _**PFC**_ has already boosted the bus voltage sufficiently before the _**FB**_ starts. 

- A firmware plausibility check ensures that the bus voltage measurement using the VS pin is correct. 

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## **Functional Description** 

## **3.3 General Controller Features** 

XDPL8220 provides general features for firmware task scheduling, VCC control and temperature control which are independent of the target application. 

## **3.3.1 External Temperature Sensing** 

The external temperature is measured by measuring the voltage of an _**NTC**_ with respect to the internal VREF voltage. 

**==> picture [157 x 112] intentionally omitted <==**

**----- Start of picture text -----**<br>
Controller<br>VREF<br>RPU<br>TEMP<br>VTEMP RNTC<br>**----- End of picture text -----**<br>


## **Figure 22 External Temperature Sensing using NTC** 

The controller calculates the resistance of the NTC based on the measured voltage VTemp, the internal reference voltage VREF and the internal pull-up resistance RPU: 

_R_ NTC = _VV_ Tem−p ⋅ _V R_ PU REF Temp 

## **Equation 9** 

## **3.3.2 Adaptive Temperature Protection** 

XDPL8220 offers adaptive temperature protection using internal and/or external temperature sensors. This feature reduces the output current according to temperature to protect the load and driver against overtemperature. 

Whenever the temperature Thot is exceeded, the current is gradually reduced from the maximum current Iout,set, as shown in _**Figure 23**_ . If the temperature drops below Thot, the output current is increased again. This allows the controller to ensure operation at or below a temperature of Thot. 

If a reduction down to a minimum current Iout,red is not able to compensate for any continued increase in temperature, XDPL8220 will eventually trigger overtemperature protection if Tcritical is exceeded. If the controller is configured to react with auto-restart to the overtemperature protection, it will only restart after the temperature dropped below Thot. 

**==> picture [407 x 105] intentionally omitted <==**

**----- Start of picture text -----**<br>
Output Current Output Current<br>Iout,full Iout,full<br>Iout,red Iout,red<br>T≤Thot T>Thot T=Thot T≤Thot T=Thot<br>Temperature Time<br>Thot Tcritical<br>**----- End of picture text -----**<br>


**Figure 23 Adaptive Temperature Protection** 

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## **Functional Description** 

_Note_ : _Please note that the internal temperature sensor can only protect external components which have sufficient thermal coupling to XDPL8220. The external temperature sensor can be used to protect the temperature of external components (e.g. power MOSFETs or linear regulators)._ 

## **3.3.3 PWM Dimming Interface** 

The duty cycle sensed at the PWM pin is used to determine the output current level. The XDPL8220 can be configured to use either a linear or a quadratic dimming curve. Either normal or inverted dimming curves can be selected. 

_**Figure 24**_ shows the relationship of the _**PWM**_ duty cycle to the output current target value. Configurable levels DDIM,min and DDIM,max ensure that the minimum current Iout,min and maximum current Iout,set can always be achieved, thereby making the application robust against component tolerances. 

An optional hysteresis can be enabled for the sensing of the PWM signal. This hysteresis can suppress jitter in the PWM signal. Any change of the PWM duty cycle within the hysteresis will not affect the output current. 

**==> picture [462 x 311] intentionally omitted <==**

**----- Start of picture text -----**<br>
Output current Output current<br>Iout,full Iout,full<br>Iout,min Iout,min<br>PWM duty cycle PWM duty cycle<br>DDIM,off DDIM,min DDIM,max DDIM,off DDIM,min DDIM,max<br>DDIM,on DDIM,on<br>Output current Output current<br>Iout,full Iout,full<br>Iout,min Iout,min<br>PWM duty cycle PWM duty cycle<br>DDIM,max DDIM,min DDIM,off DDIM,max DDIM,min DDIM,off<br>DDIM,on DDIM,on<br>**----- End of picture text -----**<br>


**Figure 24 Selectable Dimming Curves** 

Using the optional Dim-to-Off feature, the light output can be stopped without removal of input voltage. In Dimto-Off, the controller will enter auto-restart operation to minimize power consumption. The auto-restart recharges the output voltage to a minimum output voltage of Vout,start to measure the PWM duty cycle. With this feature, the output voltage can be maintained in a specific range by configuration of the startup voltage Vout,start and auto-restart time tAR, and by dimensioning of an active or passive output bleeder. If Vout,start is configured to be low enough below the minimum forward voltage of the _**LED**_ string, the _**LED**_ s will show no light in this state. 

_Note_ : _Either an active or passive output bleeder is required to allow the controller to maintain the output voltage if the Dim-to-Off feature is enabled._ 

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## **Functional Description** 

Dim-to-Off is entered if the _**PWM**_ duty cycle exceeds the configurable threshold DDIM,off (see purple line in _**Figure 24**_ ). As soon as the duty cycle exceeds DDIM,on, the controller will start to continuously regulate output voltage or output current again. 

## **3.3.4** 

## **Protection Features** 

Protections ensure the operation of the controller under restricted conditions. Protections are triggered if fault conditions are present longer than the blanking times configured for each protection _**[4)]**_ . The controller will react to a triggered protection as configured. 

_**Attention**_ : _**The controller may continue operation after exceeding protection thresholds because of blanking times. All protection thresholds have to be set with respect to tolerances, blanking times and worst case transients.**_ 

**==> picture [447 x 134] intentionally omitted <==**

**----- Start of picture text -----**<br>
Value Value<br>Upper<br>Threshold<br>Lower<br>Threshold<br>Time Time<br>tblank tblank<br>**----- End of picture text -----**<br>


## **Figure 25 Blanking Times cause Excess of Threshold** 

## **3.3.4.1 Overtemperature Protection** 

Overtemperature protection initiates a shutdown once the critical temperature level Tcritical is exceeded. _**Figure 26**_ shows the temperature hysteresis formed by the critical temperature Tcritical and maximum turn-on threshold Thot if auto-restart is enabled for temperature protection. 

If latch mode is selected instead, the IC will turn off and only restart after recycling of input power with a temperature below Tcritical. 

**==> picture [214 x 106] intentionally omitted <==**

**----- Start of picture text -----**<br>
Output current<br>Iout,full<br>Temperature<br>Thot T critical<br>**----- End of picture text -----**<br>


**Figure 26 Temperature Protection** 

> 4 except VCC undervoltage protection 

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## **Functional Description** 

## **3.3.4.2 VCC Undervoltage Protection** 

A _**Undervoltage Lockout (UVLO)**_ is implemented in hardware. It ensures defined enabling and disabling of the _**Integrated Circuit (IC)**_ operation depending on the supply voltage VVCC at the VCC pin in accordance with defined thresholds. 

The _**UVLO**_ contains a hysteresis with the voltage thresholds VVCC,on for enabling the _**IC**_ and VVCC,off for disabling the IC. Once the mains input voltage is applied, current flows through an external resistor into the HV pin via the integrated depletion cell and diode to the VCC pin. The _**IC**_ is enabled once VVCC exceeds the threshold VVCC,on and enters normal operation if no fault condition is detected. In this phase, VVCC will drop until either external supply or the self-supply via the auxiliary winding takes over the supply at the VCC pin. 

In the case of output short or strong capacitive loading, the auxiliary winding cannot provide power to VVCC. A timeout of tstart,max is available to respond to this failure condition. 

_Note_ : _The self-supply via the auxiliary winding must be in place before the output short timeout occurs or before V_ VCC _falls below the V_ VCC,off _threshold. Otherwise, the system will perform a fast restart._ 

_Note_ : _It is possible to supply VCC externally from an auxiliary power supply. In this case, the VCC also needs initially to ramp to V_ VCC,on _to enable the IC._ 

## **3.3.4.3** 

## **VCC Overvoltage Protection** 

Overvoltage protection ensures that the voltage at the VCC pin is not exceeded. 

The VCC voltage is compared to a configurable overvoltage protection threshold VVCC,OV. If the threshold is exceeded for longer than the blanking time tblank,VCC,OV, the protection will be triggered. 

_Note_ : _The reaction to this protection is fixed to stop mode to ensure a discharge of VCC._ 

## **3.3.4.4 Other General Controller Protections** 

XDPL8220 includes several protections to ensure the integrity and correct flow of the firmware. 

- A hardware watchdog checks correct execution of firmware. A protection is triggered in the event that the firmware does not service the watchdog within a defined period. 

- A hardware _**Random Access Memory (RAM)**_ parity check triggers a protection if a bit in the memory changes unintentionally. 

- A hardware clock check watchdog checks that no clock oscillator is failing. 

- A firmware _**Cyclic Redundancy Check (CRC)**_ at each startup verifies the integrity of firmware code and its parameters. 

- A firmware task execution watchdog triggers a protection if the firmware tasks are not executed as expected. 

## **3.3.5 Protection Reactions** 

The reaction to each protection can be separately selected. Available reactions may include auto restart, fast auto restart, latch or stop mode. 

_**Figure 27**_ depicts the timing of an auto-restart reaction: 

**1.** If a protection threshold is exceeded for longer than the related blanking time tblank, the protection is triggered. 

**2.** Within a maximum t1 = 4 * 32 µs, the gate driver of the power stage related to the protection is disabled. 

**3.** Within a maximum t2 = 4 * 32 µs, the gate drivers of other stages are disabled. 

**4.** The reaction depends on the configuration of the protection: 

   - In case of latch mode, the application will enter latch mode at this time. No further steps are done, the reaction ends here. 

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## **Functional Description** 

   - In case of stop mode, the application will stop and enter UART parametrization mode which allows to read out the error code. No further steps are done, the reaction ends here. 

   - In case of a (fast) auto-restart reaction, the controller will enter a power saving mode for the auto-restart time tAR or tAR,fast respectively. 

**5.** The auto restart may include a new VCC charging cycle. The time t3 typically depends on the input voltage. 

**6.** The first power stage will enable its gate driver according to its startup sequence (soft start) again. 

**7.** The second power stage will enable its gate driver according to its startup sequence (soft start) again. The startup of a subsequent power stage may be delayed by a time t4 depending on any startup condition for the subsequent stage. 

**==> picture [426 x 289] intentionally omitted <==**

**----- Start of picture text -----**<br>
Threshold is exceeded<br>Protection is triggered<br>Related gate driver is disabled<br>Other gate drivers are disabled<br>Startup, charging of VCC<br>Restart of the first stage<br>Value Restart of the second stage<br>Threshold<br>Other gate driver<br>Related gate driver<br>Time<br>tblank t1 t2 tAR t3 t4<br>**----- End of picture text -----**<br>


**Figure 27 Protection Reaction for auto-restart** 

## **3.3.5.1** 

## **Auto restart** 

When auto restart mode is activated, XDPL8220 stops switching at the GD pins. After a configurable auto restart time tAR, XDPL8220 initiates a new startup with soft start. 

During the time in which the gate is not switching, the internal HV startup cell is automatically enabled and disabled to keep the VCC voltage between the VUVLO and VOVLO thresholds for the supply of XDPL8220. 

## **3.3.5.2 Fast Auto Restart** 

When fast auto restart mode is activated, XDPL8220 stops switching at the GD pins. After a configurable fast auto restart time tAR,fast, XDPL8220 initiates a new startup with soft start. 

During the time in which the gate is not switching, the internal HV startup cell is automatically enabled and disabled to keep the VCC voltage between the VUVLO and VOVLO thresholds for the supply of XDPL8220. 

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## **Functional Description** 

## **3.3.5.3 Latch Mode** 

When latch mode is activated, XDPL8220 stops switching at the GD pins. The device stays in this state until input voltage is completely removed and the VCC voltage drops below the VUVLO threshold. Only then can XDPL8220 be restarted by applying input voltage. 

To maintain this state, the internal HV startup cell is automatically enabled and disabled to keep the VCC voltage between the VUVLO and VOVLO thresholds for the supply of XDPL8220. The current consumption is reduced to a minimum. 

## **3.3.5.4** 

## **Stop Mode** 

When stop mode is activated, XDPL8220 stops switching at the GD pins. XDPL8220 enters _**UART**_ communication mode to allow debugging of the system state. 

_Note_ : 

_The VCC for XDPL8220 needs to be supplied by an external source. Without an external supply, VCC will drain to V_ UVLO _and XDPL8220 performs a restart._ 

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## **Design Support** 

## **4 Design Support** 

XDPL8220 is a configurable digital platform product. It can be configured to meet a wide range of application requirements. 

## **4.1** 

## **Design Procedure** 

Infineon provides support of the design procedure for lighting applications using Infineon's digital platform _**IC**_ s. 

A lighting application is designed in a few simple steps using Infineon's digital platform _**IC**_ s as follows: 

**1.** The Infineon XDPL8220 reference board and the _XDPL8220 Reference Board Test Report_ demonstrate the features and performance of the XDPL8220 in a typical application. 

**2.** Parameters of the XDPL8220 reference board can easily be fitted to any application's requirements. The isolated _.dp Interface Gen2_ is connected to XDPL8220 via _**Universal Serial Bus (USB)**_ . The _**GUI**_ tool .dp Vision is included with the _.dp Interface Gen2_ . .dp Vision allows interactive changing of parameters. The usage of .dp Vision is explained in the _.dp Vision User Manual_ . 

**3.** To further adapt the XDPL8220 to application requirements, customers can design their own specific boards. The steps used to design a board are explained in the _XDPL8220 Design Guide_ . .dp Vision can be used together with the _.dp Interface Gen2_ to connect to customer-specific designs based on XDPL8220. This setup can be used for rapid prototyping. The tooling allows fine-tuning of parameters and development of multiple parameter sets – e.g. to reuse the same for different product variants of an application. 

**4.** For mass production, the _XDPL8220 Programming Manual_ documents the necessary interfacing and procedures to integrate the parameter configuration of XDPL8220 into the production line. _**Figure 28**_ shows two options to easily apply the configuration of the _**IC**_ during production tests: 

   - One option is to use the isolated _.dp Interface Gen2_ , which can be accessed with _**USB**_ commands. 

   - Another option is to directly use the _**UART**_ interface of the XDPL8220. The correct VCC voltage and _**UART**_ communication have to be controlled by the production process in this case. 

**==> picture [273 x 137] intentionally omitted <==**

**----- Start of picture text -----**<br>
PC with USB Isolated .dp VCCUART IC<br>GUI tool Interface Gen2<br>GND<br>Production USB Isolated .dp VCCUART IC<br>process Interface Gen2 GND<br>Production VCC<br>UART IC<br>process GND<br>**----- End of picture text -----**<br>


**Figure 28 Setup for Parametrization using .dp Interface Gen2 for Interactive Development (top) and Production (middle and bottom)** 

## **4.2 List of Configurable Parameters** 

This list provides information about configurable parameters, including their permitted range and granularity. Typical example values are also provided. 

## **Table 2 Parameters for Hardware Configuration** 

|**Symbol**|**Description**|**Example**|**Minimum**<br>**Value**|**Maximum**<br>**Value**|**Granularity**|
|---|---|---|---|---|---|
|Na|**_FB_**auxiliary winding turns|34|1|300|1|
|Np|**_FB_**primary winding turns|60|1|300|1|



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## **Design Support** 

|**Table 2**<br>**Parameters for Hardware Configuration (continued)**|**Table 2**<br>**Parameters for Hardware Configuration (continued)**|**Table 2**<br>**Parameters for Hardware Configuration (continued)**|**Table 2**<br>**Parameters for Hardware Configuration (continued)**|**Table 2**<br>**Parameters for Hardware Configuration (continued)**|**Table 2**<br>**Parameters for Hardware Configuration (continued)**|
|---|---|---|---|---|---|
|**Symbol**|**Description**|**Example**|**Minimum**<br>**Value**|**Maximum**<br>**Value**|**Granularity**|
|Ns|**_FB_**secondary winding turns|44|1|300|1|
|RCS,FB|**_FB_**current sense resistance|410/2048 Ω|200/2048 Ω|3 Ω|1/2048 Ω|
|RZCD,FB,1|**_FB_**ZCD upper resistor|120 kΩ|50 Ω|200 kΩ|50 Ω|
|RZCD,FB,2|**_FB_**ZCD shunt resistor|7.5 kΩ|50 Ω|100 kΩ|50 Ω|
|RVS,1|VS upper resistor for bus voltage<br>measurement|9.96 MΩ|500 kΩ|15 MΩ|500 Ω|
|RVS,2|VS shunt resistor for bus voltage<br>measurement|52.3 kΩ|22 kΩ|100 kΩ|50 Ω|
|RHV|HV resistor|100 kΩ|47 kΩ|130 kΩ|50 Ω|
|Vout,ofset|Output voltage ofset (e.g. voltage drop<br>from secondary diode)|-0.625 V|-4.000 V|4.000 V|0.125 V|
|VGBFB|FB gate driver voltage high level|10.5 V|4.5 V|15 V**_1)_**|1.5 V|
|IGBFB|FB gate driver strength|100 mA|100 mA|500 mA|Selected<br>steps|
|VGBPFC|PFC gate driver voltage high level|10.5 V|4.5 V|15 V**_2)_**|1.5 V|
|IGBPFC|PFC gate driver strength|100 mA|30 mA|150 mA|Selected<br>steps|
|||||||
|**Table 3**<br>**Parameters for PFC Protections**||||||
|**Symbol**|**Description**|**Example**|**Minimum**<br>**Value**|**Maximum**<br>**Value**|**Granularity**|
|tblank,Vbus,OVP<br>2|Blanking time for bus overvoltage<br>threshold, level 2|200 ns|0 s|640 ns|1 / fmclk|
|tblank,Vbus,OVP<br>1|Blanking time for bus overvoltage<br>threshold, level 1|400 us|0 s|1 ms|tslot|
|Vbus,OVP1|Bus overvoltage threshold, level 1|490 V|Vbus,stdy,entr,<br>OV|600 V**_3)_**|1/16 V|
|tblank,Vbus,UV|Blanking time for bus undervoltage<br>threshold|500 us|0 s|1 ms|tslot|
|Vbus,UV|Bus undervoltage threshold|300 V|Vbus,start,PFC|Vbus,stdy,entr,U<br>V|1/16 V|
|tstart,max,PFC|Maximum**_PFC_**sof start time to settle<br>the bus voltage at startup|200 ms|0 s|500 ms|tslot|
|tblank,Vin,OV|Blanking time for input overvoltage<br>threshold|100 ms|0 s|200 ms|tslot|
|tblank,Vin,UV|Blanking time for input undervoltage<br>threshold|100 ms|0 s|200 ms|tslot|



> 1 Limited by VCC - 0.5 V 

> 2 Limited by VCC - 0.5 V 

> 3 Limited by the voltage rating of the bus capacitors 

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## **Design Support** 

**Table 3 Parameters for PFC Protections (continued)** 

|**Symbol**|**Description**|**Example**|**Minimum**<br>**Value**|**Maximum**<br>**Value**|**Granularity**|
|---|---|---|---|---|---|
|Vin,OV|Input overvoltage threshold|319 Vrms|Vin,start,max|424 Vrms|1/16 Vrms|
|Vin,UV|Input undervoltage threshold|76 Vrms|0 V|Vin,start,min|1/16 Vrms|
|Vin,start,max|Maximum input voltage at startup|307 Vrms|Vin,start,min|Vin,OV|1/16 Vrms|
|Vin,start,min|Minimum input voltage at startup|88 Vrms|Vin,UV|Vin,start,max|1/16 Vrms|
|tblank,OCP2,PFC|Blanking time for the peak current<br>limitation, level 2|200 ns|1 / fmclk|600 ns|1 / fmclk|
|tblank,OCP1,PFC|Blanking time for the peak current<br>limitation, level 1|200 ns|1 / fmclk|600 ns|1 / fmclk|
|VCS,OCP1, PFC|Maximum peak current voltage|0.75 V|0.1 V|1.08 V|0.125 mV|
|tblank,CCM,PFC|Blanking time for CCM protection|12 ms|0 s|30 ms|tslot|
|ProtectionPF<br>C,EN|Bit-coded enabling per protection: If set<br>to 1, protection is enabled.||0|65535|One-hot<br>coded|
|ProtectionPF<br>C,conf1|Bit-coded reaction per protection: If set<br>to 1, auto-restart is selected. If set to 0,<br>either latch mode or stop is selected.||0|65535|One-hot<br>coded|
|ProtectionPF<br>C,conf2|Bit-coded reaction per protection: If set<br>to 1, fast auto restart or stop is selected.<br>If set to 0, normal auto-restart or latch<br>mode is enabled.||0|65535|One-hot<br>coded|
|ProtectionPF<br>C,conf3|Bit-coded reaction per protection: If set<br>to 1, limited number of restarts are<br>enabled. If set to zero, unlimited restarts<br>will be done.||0|65535|One-hot<br>coded|
|ProtectionPF<br>C,conf4|Bit-coded reaction per protection: If set<br>to 1, VCC charging will be enabled for<br>auto-restarts.||0|65535|One-hot<br>coded|
|||||||
|**Table 4**<br>**Parameters for Flyback Protections**||||||
|**Symbol**|**Description**|**Example**|**Minimum**<br>**Value**|**Maximum**<br>**Value**|**Granularity**|
|Vout,UV|Output undervoltage threshold|15 V|0 V|Vout,start|0.125 V|
|tblank,Vout,UV|Blanking time for output undervoltage|500 us|0 s|1 ms|tslot|
|tstart,max,FB|Maximum**_FB_**startup time to detect an<br>output short at startup|5 ms|0 s|200 ms|tslot|
|Vout,OV|Output overvoltage threshold|55 V|Vout,start|200 V|0.125 V|
|tblank,Vout,OV|Blanking time for output overvoltage|500 us|0 s|1 ms|tslot|
|tblank,CCM|Blanking time for CCM protection|500 us|0 s|1 ms|tslot|
|Iout,OC|Output overcurrent threshold|3 A|Iout,full|10 A|0.5 mA|
|tblank,Iout,OC|Blanking time for output overcurrent|500 us|0 s|1 ms|tslot|
|Pout,OP|Output overpower threshold|120 W|Pout,set|300 W|0.5 W|
|tblank,Pout,OP|Blanking time for output overpower|500 us|0 s|1 ms|tslot|



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## **Design Support** 

## **Table 4 Parameters for Flyback Protections (continued)** 

|**Symbol**|**Description**|**Example**|**Minimum**<br>**Value**|**Maximum**<br>**Value**|**Granularity**|
|---|---|---|---|---|---|
|tblank,Vbus,FB|Blanking time for bus voltage<br>plausibility check|500 us|0 s|1 ms|tslot|
|tblank,CSFB2GN<br>D|Blanking time for the CSFB-to-GND-<br>short check|100 us|0 s|500 us|tslot|
|tblank,TOSC,FB|Blanking time for the tOSC,FBbeing<br>overly long check|40 ms|0 ms|100 ms|20 ms|
|ProtectionFB,<br>EN|Bit-coded enabling per protection: If set<br>to 1, protection is enabled.||0|65535|One-hot<br>coded|
|ProtectionFB,<br>conf1|Bit-coded reaction per protection: If set<br>to 1, auto-restart is selected. If set to 0,<br>either latch mode or stop is selected.||0|65535|One-hot<br>coded|
|ProtectionFB,<br>conf2|Bit-coded reaction per protection: If set<br>to 1, Fast Auto-restart or Stop is<br>selected. If set to 0, normal Auto-restart<br>or latch mode is enabled)||0|65535|One-hot<br>coded|
|ProtectionFB,<br>conf3|Bit-coded reaction per protection: If set<br>to 1, limited number of restarts are<br>enabled. If set to zero, unlimited restarts<br>are enabled.||0|65535|One-hot<br>coded|
|ProtectionFB,<br>conf4|Bit-coded reaction per protection: If set<br>to 1, VCC charging will be enabled for<br>auto-restarts.||0|65535|One-hot<br>coded|
|||||||
|**Table 5**<br>**Parameters for General Protections**||||||
|**Symbol**|**Description**|**Example**|**Minimum**<br>**Value**|**Maximum**<br>**Value**|**Granularity**|
|VVCC,OV|VCC overvoltage threshold|24.75 V|6 V|24.75 V|0.125 V|
|tblank,VCC,OV|Blanking time for VCC overvoltage|5 ms|0 s|10 ms|tslot|
|Protectionge<br>n,EN|Bit-coded enabling per protection: If set<br>to 1, protection is enabled.||0|65535|One-hot<br>coded|
|Protectionge<br>n,conf1|Bit-coded reaction per protection: If set<br>to 1, auto-restart is selected. If set to 0,<br>either latch mode or stop is selected.||0|65535|One-hot<br>coded|
|Protectionge<br>n,conf2|Bit-coded reaction per protection: If set<br>to 1, fast auto-restart or stop is selected.<br>If set to 0, normal auto-restart or latch<br>mode is enabled)||0|65535|One-hot<br>coded|
|Protectionge<br>n,conf3|Bit-coded reaction per protection: If set<br>to 1, limited number of restarts are<br>enabled. If set to zero, unlimited restarts<br>are enabled.||0|65535|One-hot<br>coded|
|Protectionge<br>n,conf4|Bit-coded reaction per protection: If set<br>to 1, VCC charging will be enabled for<br>auto-restarts.||0|65535|One-hot<br>coded|



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## **Design Support** 

## **Table 5 Parameters for General Protections (continued)** 

|**Symbol**|**Description**|**Example**|**Minimum**<br>**Value**|**Maximum**<br>**Value**|**Granularity**|
|---|---|---|---|---|---|
|tAR|Auto-restart time|1 s|250 ms|4 s|250 ms|
|tAR,fast|Fast auto-restart time|40 ms|5 ms|4 s|5 ms|
|NAR,max|Maximum number of restarts,<br>aferwards latch|10|0|15|1|



## **Table 6 Parameters for Adaptive Temperature Protection** 

|**Symbol**|**Description**|**Example**|**Minimum**<br>**Value**|**Maximum**<br>**Value**|**Granularity**|
|---|---|---|---|---|---|
|Tcritical|Shutof temperature|110°C|Thot|125°C|1°C|
|Thot|Temperature for thermal management|100°C|60°C|Tcritical|1°C|
|RNTC,hot|**_NTC_**resistance at Thot|1500 Ω|1 Ω|30000 Ω|1 Ω|
|RNTC,critical|**_NTC_**resistance at Tcritical|800 Ω|1 Ω|30000 Ω|1 Ω|
|tstep|Current reduction time step|2 s|1 s|20 s|214tslot|
|Iout,red|Lowest reduced current for thermal<br>management|200 mA|Iout,min|Iout,full|0.5 mA|
|Iout,step|Output current step|5 mA|0.5 mA|Iout,full-<br>Iout,red|0.5 mA|



## **Table 7 Parameters for Startup and Shutdown** 

|**Symbol**|**Description**|**Example**|**Minimum**<br>**Value**|**Maximum**<br>**Value**|**Granularity**|
|---|---|---|---|---|---|
|tsofstart|Sof start time step|0.5 ms|0.1 ms|2 ms|tslot|
|V|Maximum peak current voltage during<br>startupCS, max,start,FB|0.9 V|VCS,min,FB|VCS,max,FB|0.125 mV|
|VCS,CS,step|Sof start voltage limit step|0.3 V|0.1 V|VCS,OCP1, start|0.125 mV|
|Vout,start|Output startup voltage|10 V|Vout,UV|Vout,set|0.125 V|
|tsw,start,FB|Minimum switching period during<br>startup|1 / 20 kHz|tsw,min|tsw,max,FB|1 / fmclk|
|Vbus,start,FB|Bus voltage**_FB_**startup threshold|350 V|0 V|Vbus,set|1/16 V|
|Vbus,start,PFC|Bus voltage**_PFC_**startup threshold in<br>case of DC input|75 V|0 V|Vbus,UV|1/16 V|



## **Table 8 Parameters for PFC Control Loop** 

|**Symbol**|**Description**|**Example**|**Minimum**<br>**Value**|**Maximum**<br>**Value**|**Granularity**|
|---|---|---|---|---|---|
|SVPstartup|PIT1 proportional gain in sof start|4|0|15|1|
|SVIstartup|PIT1 integral gain in sof start|7|0|15|1|
|SVPstdy|PIT1 proportional gain in steady state|4|0|15|1|
|SVIstdy|PIT1 integral gain in steady state|7|0|15|1|



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## **Design Support** 

## **Table 8 Parameters for PFC Control Loop (continued)** 

|**Symbol**|**Description**|**Example**|**Minimum**<br>**Value**|**Maximum**<br>**Value**|**Granularity**|
|---|---|---|---|---|---|
|SVT|PIT1 gain of the T1 filter|6|0|15|1|
|ESAT|PIT1 error limitation in sof start|16384|0|32767|1|
|ton,max,PFC|PIT1 maximum on-time limit|35 us|15 us|40 us|1 / fmclk|
|ton,min,PFC|PIT1 minimum on-time limit|200 ns|0 us|tLEB,PFC|1 / fmclk|
|tsw,max,PFC|Maximum switching period|1 / 22 kHz|tsw,min,PFC|1 / 20 kHz|1 / fmclk|
|tsw,min,PFC|Minimum switching period|1 / 120 kHz|1 / 200 kHz|tsw,max,PFC|1 / fmclk|
|Nvalley,max,PFC|Upper boundary for valley number|5|1|5|1|
|tvalley,blanking,<br>PFC|Blanking time for valley change|500 us|0 s|1 ms|tslot|
|Vbus,set|Bus voltage setpoint|460 V|Vbus,UV|Vbus,OVP1|1/16 V|
|Vbus,stdy,entr,O<br>V|Bus voltage steady state entry<br>overvoltage threshold|472 V|Vbus,set|Vbus,OVP1|1/16 V|
|Vbus,stdy,entr,U<br>V|Bus voltage steady state entry under-<br>voltage threshold|448 V|Vbus,UV|Vbus,set|1/16 V|



|**Table 9**<br>**Parameters for Flyback Control Loop**|**Table 9**<br>**Parameters for Flyback Control Loop**|**Table 9**<br>**Parameters for Flyback Control Loop**|**Table 9**<br>**Parameters for Flyback Control Loop**|**Table 9**<br>**Parameters for Flyback Control Loop**|**Table 9**<br>**Parameters for Flyback Control Loop**|
|---|---|---|---|---|---|
|**Symbol**|**Description**|**Example**|**Minimum**<br>**Value**|**Maximum**<br>**Value**|**Granularity**|
|b0,DCM|b0gain of control loop in**_DCM_**|5353 /<br>fmclk/256|0|8192 /<br>fmclk/256|1 / fmclk/256|
|b1,DCM|b1gain of control loop in**_DCM_**|-53 /<br>fmclk/256|-8192 /<br>fmclk/256|0|1 / fmclk/256|
|b0,QRM1|b0gain of control loop in**_QRM1_**|6060 / 65536<br>V|0 V|16384 /<br>65536 V|1 / 65536 V|
|b1,QRM1|b1gain of control loop in**_QRM1_**|-60 / 65536<br>V|-16384 /<br>65536 V|0 V|1 / 65536 V|
|KP,CV|Proportional gain for**_CV_**mode|1.9|0|16|0.125|
|KD,CV|Derivative gain for**_CV_**mode||28|128|0.125|
|Pout,set|Output power limit|100 W|0|150 W|0.5 W|
|Iout,full|Non-dimmed output current|2.0 A|Iout,min|3 A|0.5 mA|
|Vout,set|Output voltage setpoint|48 V|Vout,UV|Vout,OV|0.125 V|
|ton,max,FB|Maximum on-time limit|15 us|VCS,max,FB/<br>RCS,FB* Lp/<br>Vbus,UV**_4)_**|25 us|1 / fmclk|
|tsw,max,FB|Maximum switching period|1 / 20 kHz|tsw,min,FB|1 / 16 kHz|1 / fmclk|
|tsw,min,FB|Minimum switching period|1 / 150 kHz|1 / 150 kHz|tsw,max,FB|1 / fmclk|
|VCS,max,FB|Maximum peak current voltage|1.09 V|VCS,min,FB|92% * 1.214<br>V|0.125 mV|



> 4 Maximum on-time occurs if maximum power is transferred at minimum bus voltage. 

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## **Design Support** 

|**Table 9**<br>**Parameters for Flyback Control Loop (continued)**|**Table 9**<br>**Parameters for Flyback Control Loop (continued)**|**Table 9**<br>**Parameters for Flyback Control Loop (continued)**|**Table 9**<br>**Parameters for Flyback Control Loop (continued)**|**Table 9**<br>**Parameters for Flyback Control Loop (continued)**|**Table 9**<br>**Parameters for Flyback Control Loop (continued)**|
|---|---|---|---|---|---|
|**Symbol**|**Description**|**Example**|**Minimum**<br>**Value**|**Maximum**<br>**Value**|**Granularity**|
|VCS,min,FB|Minimum peak current voltage|0.4 V|tdemag,min,FB<br>* Np/ Ns*<br>Vout,OV/ Lp*<br>RCS,FB **_5)_**|VCS,max,FB|0.125 mV|
|||||||
|**Table 10**<br>**Parameters for Dimming**||||||
|**Symbol**|**Description**|**Example**|**Minimum**<br>**Value**|**Maximum**<br>**Value**|**Granularity**|
|DDIM,max|**_PWM_**duty cycle for maximum current|90%|5%|95%|0.25%|
|DDIM,min|**_PWM_**duty cycle for minimum current|10%|5%|95%|0.25%|
|DDIM,on|**_PWM_**duty cycle to exit dim-to-of|5%|5%|95%|0.25%|
|DDIM,of|**_PWM_**duty cycle to enter dim-to-of|5%|5%|95%|0.25%|
|tblank,DIM,of|Blanking time until when the**_PWM_**input<br>has to be available before dim-to-of is<br>triggered|1 ms|0 ms|10 ms|tslot|
|NDIM|Integer dimming curve coeficient|1|1|2|1|
|Iout,min|Minimum output current|20 mA|20 mA|Iout,full|0.5 mA|
|n_PWM_hys|PWM detection hysteresis to suppress<br>jitter in the PWM signal|0|6|40|1|
|||||||
|**Table 11**<br>**Parameters for Fine Tuning**||||||
|**Symbol**|**Description**|**Example**|**Minimum**<br>**Value**|**Maximum**<br>**Value**|**Granularity**|
|Kcoupling|**_FB_**transformer coupling coeficient|0.98|0.5|2|0.001|
|tLEB,FB|**_FB_**Current sense leading edge blanking|200 ns|1 / fmclk|600 ns|1 / fmclk|
|tOCP2,FB|**_FB_**OCP2 blanking time|250 ns|1 / fmclk|63 / fmclk|1 / fmclk|
|tPDC|**_FB_**Propagation delay compensation|500 ns|tOCP1,FB|2 us|1 / fmclk|
|tOCP1,FB|**_FB_**OCP1 spike suppression filter|100 ns|50 ns|500 ns|1 / fmclk|
|tCSFB,ofset|**_FB_**sampling ofset|200 ns|50 ns|500 ns|1 / fmclk|
|tsw,hysteresis|**_FB_**switching period hysteresis for<br>QRM/DCM mode changes|600 ns|20 ns|1000 ns|1 / fmclk|
|trsup,FB|**_FB_**ZCD ringing suppression|1.2 us|1 / fmclk|2 us|1 / fmclk|
|tZCD,PD,FB|**_FB_**Delay of zero-crossing signal|200 ns|0 s|1 us|1 / fmclk|
|tZCD,PD,RE,FB|**_FB_**Rising edge delay of zero-crossing<br>signal|450 ns|0 s|1 us|1 / fmclk|
|tgate,on|**_FB_**Turn-on delay of MOSFET|100 ns|0 s|1 us|1 / fmclk|
|tLEB,PFC|**_PFC_**On-time leading edge blanking|200 ns|1 / fmclk|600 ns|1 / fmclk|



> 5 The minimum peak current must ensure that tdemag,min,FB is maintained. 

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## **Design Support** 

## **Table 11 Parameters for Fine Tuning (continued)** 

|**Symbol**|**Description**|**Example**|**Minimum**<br>**Value**|**Maximum**<br>**Value**|**Granularity**|
|---|---|---|---|---|---|
|tZCD,PD,PFC|**_PFC_**Delay of 0.5 V crossing to real zero-<br>crossing signal|42 ns|-1 us|1 us|1 / fmclk|
|Ntosc,upd,PFC|**_PFC_**AC half cycle number to take<br>oscillation measurement|0|0|255|1|
|tosc,init,PFC|**_PFC_**Oscillation period initialization<br>value|1.5 us|0 s|8 us|1 / fmclk|
|tosc,delay,PFC|**_PFC_**Delay afer zero-crossing to<br>measure oscillation period|2 ms|0 s|12 ms|tslot|
|ki,PFC|**_PFC_**THD optimization coeficient|0.75|0|16|0.125|
|tsrc,blanking,PF<br>C|Blanking time for AC/DC source change|12 ms|12 ms|30 ms|1 ms|
|trms,reset,PFC|Reset time of RMS search|20 ms|tsrc,blanking,PF<br>C|30 ms|1 ms|



## **4.3 List of Fixed Parameters** 

This list shows the fixed parameters and their associated values – i.e. parameters whose values cannot be changed. 

## **Table 12 List of Fixed Parameters** 

|**Symbol**|**Description**|**Value**|
|---|---|---|
|VCS,OCP2|Primary overcurrent protection|1.619 V|
|tdemag,min,FB|**_FB_**minimum demagnetizing time|2.0 us|
|VUVOFF|VCC undervoltage threshold|6.07 V|
|fmclk|Main clock frequency|50.0 MHz|
|tslot|Firmware task scheduling interval|32 us|
|VREF|Internal reference voltage|2.428 V|
|kpktorms|Constant to convert from peak to RMS values|0.707_(approx._<br>_181/256)_|
|CIIR,PFC|Coeficient of the IIR LP filter for bus voltage|4|



Data Sheet 

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## **Electrical Characteristics and Parameters** 

## **5 Electrical Characteristics and Parameters** 

All signals are measured with respect to the ground pin, GND. The voltage levels are valid provided other ratings are not violated. 

## **5.1 Package Characteristics** 

## **Table 13 Package Characteristics** 

|**Parameter**|**Symbol**|**Limit Values**|**Limit Values**|**Unit**|**Remarks**|
|---|---|---|---|---|---|
|||**min**|**max**|||
|Thermal resistance for PG-<br>DSO-16|RthJA|—|119|K/W||



## **5.2 Absolute Maximum Ratings** 

_**Attention**_ : _**Stresses above the values listed above may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. These values are not tested during production test.**_ 

## **Table 14 Absolute Maximum Ratings** 

|**Parameter**|**Symbol**|**Limit Values**|**Limit Values**|**Unit**|**Remarks**|
|---|---|---|---|---|---|
|||**min**|**max**|||
|Voltage externally supplied<br>to pin VCC|VVCCEXT|–0.5|26|V|voltage that can be applied<br>to pin VCC by an external<br>voltage source|
|Voltage at pin GDx|VGDx|–0.5|VVCC+ 0.3|V|if gate driver is not<br>configured for digital I/O|
|Junction temperature|TJ|–40|125|°C|max. operating frequency<br>66 MHz fMCLK|
|Storage temperature|TS|–55|150|°C||
|Soldering temperature|TSOLD|—|260|°C|Wave Soldering**_1)_**|
|Latch-up capability|ILU|—|150|mA|**_2)_**Pin voltages acc. to abs.<br>max. ratings|
|ESD capability HBM|VHBM|—|2000|V|**_3)_**|
|ESD capability CDM|VCDM|—|500|V|**_4)_**|



- 1 According to JESD22-A111 Rev A. 

- 2 Latch-up capability according to JEDEC JESD78D, TA= 85°C. 

- 3 ESD-HBM according to ANSI/ESDA/JEDEC JS-001-2012. 

- 4 ESD-CDM according to JESD22-C101F. 

Data Sheet 

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## **Electrical Characteristics and Parameters** 

## **Table 14 Absolute Maximum Ratings (continued)** 

|**Parameter**|**Symbol**|**Limit Values**|**Limit Values**|**Unit**|**Remarks**|
|---|---|---|---|---|---|
|||**min**|**max**|||
|Input Voltage Limit|VIN|–0.5|3.6|V|Voltage externally supplied<br>to pins GPIO, MFIO, CS, ZCD,<br>GPIO, VS, GDx (if GDx is<br>configured as digital I/O). (If<br>not stated diferent)|
|Maximum permanent<br>negative clamping current<br>for ZCD and CS|–ICLN_DC|—|2.5|mA|RMS|
|Maximum transient negative<br>clamping current for ZCD<br>and CS|–ICLN_TR|—|10|mA|pulse < 500ns|
|Maximum negative transient<br>input voltage for ZCD|–VIN_ZCD|—|1.5|V|pulse < 500ns|
|Maximum negative transient<br>input voltage for CS|–VIN_CS|—|3.0|V|pulse < 500ns|
|Maximum permanent<br>positive clamping current for<br>CS|ICLP_DC|—|2.5|mA|RMS|
|Maximum transient positive<br>clamping current for CS|ICLP_TR|—|10|mA|pulse < 500ns|
|Maximum current into pin<br>VIN|IAC|—|10|mA|for charging operation|
|Maximum sum of input<br>clamping high currents for<br>digital input stages of device|ICLH_sum|—|300|µA|limits for each individual<br>digital input stage have to<br>be respected|
|Voltage at HV pin|VHV|-0.5|600|V||



## **5.3 Operating Conditions** 

The recommended operating conditions are shown for which the DC Electrical Characteristics are valid. 

## **Table 15 Operating Range** 

|**Parameter**|**Symbol**|**Limit Values**|**Limit Values**|**Unit**|**Remarks**|
|---|---|---|---|---|---|
|||**min**|**max**|||
|Ambient temperature|TA|–40|85|°C||
|Junction Temperature|TJ|–40|125|°C|max. 66 MHz fMCLK|
|Lower VCC limit|VVCC|VUVOFF|—|V|device is held in reset when<br>VVCC< VUVOFF|
|Voltage externally supplied<br>to VCC pin|VVCCEXT|—|24|V|maximum voltage that can<br>be applied to pin VCC by an<br>external voltage source|
|Gate driver pin voltage|VGD|–0.5|VVCC+ 0.3|V||



Data Sheet 

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## **Electrical Characteristics and Parameters** 

## **5.4 DC Electrical Characteristics** 

The electrical characteristics provide the spread of values applicable within the specified supply voltage and junction temperature range, TJ from -40 °C to +125 °C. 

Devices are tested in protection at TA = 25 °C. Values have been verified either with simulation models or by device characterization up to 125 °C. 

Typical values represent the median values related to TA = 25 °C. All voltages refer to GND, and the assumed supply voltage is VVCC = 18 V if not otherwise specified. 

_Note_ : _Not all values given in the tables are tested during production testing. Values not tested are explicitly marked._ 

- _**Attention**_ : _**The Vcc pin voltage must be higher than 3.4V before the voltage of any other pins (except GND and HV pins) exceeds 1.2V.**_ 

## **Table 16 Power Supply Characteristics** 

|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|VCC_ON threshold|VVCCon|—|VSELF|—|V|Self-powered startup<br>(default)|
|VCC_ON_SELF threshold|VSELF|19|20.5|22|V|dVVCC/dt = 0.2 V/ms|
|VCC_ON_SELF delay|tSELF|—|—|2.1|µs|Reaction time of VVCC<br>monitor|
|VCC_UVOFF current|IVCCUVOFF|5|20|40|µA|VVCC< VSELF(min) - 0.3 V<br>or VVCC< VEXT(min) -<br>0.3 V**_5)_**|
|UVOFF threshold|VUVOFF|—|6.0|—|V|SYS_CFG0.SELUVTHR = 0<br>0B|
|UVOFF threshold<br>tolerance|ΔUVOFF|—|—|±5|%|This value defines the<br>tolerance of VUVOFF|
|UVOFF filter constant|tUVOFF|600|—|—|ns|1V overdrive|
|UVLO (UVWAKE)<br>threshold|VUVLO|—|VUVOFF·<br>1.25|—|V||
|UVWAKE threshold<br>tolerance|ΔUVLO|—|—|±5|%|This value defines the<br>tolerance of VUVLO|
|UVLO (UVWAKE) filter<br>constant|tUVLO|0.6|—|2.2|µs|1 V overdrive|
|OVLO (OVWAKE)<br>threshold|VOVLO|—|VSELF|—|V||
|OVLO (OVWAKE) filter<br>constant|tOVLO|0.6|—|2.4|µs|1 V overdrive|



> 5 Tested at VVCC = 5.5 V 

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## **Electrical Characteristics and Parameters** 

## **Table 16 Power Supply Characteristics (continued)** 

|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|VDDP voltage|VVDDP|3.04|3.20|3.36|V|At PMD0/PSMD1. Some<br>internal values refer to<br>VVDDP/ VVDDAand<br>VVDDPPS/ VVDDAPS<br>respectively.|
|VDDA voltage|VVDDA|3.20|3.31|3.42|V|At PMD0/PSMD1. Some<br>internal values refer to<br>VVDDP/ VVDDAand<br>VVDDPPS/ VVDDAPS<br>respectively.|
|Nominal range 0% to<br>100%|VADCVCC|0|—|VREF|V|VADCVCC= 0.09 · VVCC**_6)_**|
|Reduced VCC range for<br>ADC measurement|RADCVCC|8|—|92|%|**_7)8)_**|
|Maximum error for ADC<br>measurement (8-bit<br>result)|TET0VCC|—|—|3.8|LSB8||
|Maximum error for ADC<br>measurement (8-bit<br>result)|TET256VCC|—|—|5.2|LSB8||
|Gate driver current<br>consumption excl. gate<br>charge current|IVCCGD|—|0.26|0.35|mA|Tj≤ 125°C|
|VCC quiescent current in<br>PMD0|IVCCPMD0|—|11|13|mA|All registers have reset<br>values, clock is active at<br>66 MHz, CPU is stopped,<br>Tj≤ 85 °C|
|VCC quiescent current in<br>PMD0|IVCCPMD0|—|—|14.5|mA|All registers have reset<br>values, clock is active at<br>66 MHz, CPU is stopped,<br>Tj≤ 125 °C|
|VCC quiescent current in<br>power saving mode<br>PSDM3 with standby<br>logic active|IVCCPSMD3|—|0.25|0.45|mA|Tj≤ 125 °C<br>WU_PWD_CFG = 28H|
|VCC quiescent current in<br>power saving mode<br>PSDM4 with standby<br>logic active|IVCCPSMD4|—|0.14|0.23|mA|Tj≤ 125 °C<br>WU_PWD_CFG = 00H|



- 6 Theoretical minimum value, real minimum value is related to VUVOFF threshold. 

> 7 Operational values. 

- 8 Note that the system is turned off if VVCC < VUFOFF. 

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## **Electrical Characteristics and Parameters** 

## **Table 17 Electrical Characteristics of the GDFB Pin** 

|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|Input clamping current,<br>low|–ICLL|—|—|100|µA|only digital input|
|Input clamping current,<br>high|ICLH|—|—|100|µA|only digital input|
|APD low voltage (active<br>pull-down while device is<br>not powered or gate<br>driver is not enabled)|VAPD|—|—|1.6|V|IGD= 5 mA|
|RPPDvalue|RPPD|—|600|—|kΩ|Permanent pull-down<br>resistor inside gate<br>driver|
|RPPDtolerance|ΔPPD|—|—|±25|%|Permanent pull-down<br>resistor inside gate<br>driver|
|Driver output low<br>impedance for GD0|RGDL|—|—|4.4|Ω|TJ≤ 125 °C, IGD=  0.1 A|
|Nominal output high<br>voltage in PWM mode|VGDH|—|10.5|—|V|GDx_CFG.VOL = 3,<br>IGDH= –1 mA|
|Output voltage tolerance|ΔVGDH|—|—|±5|%|Tolerance of<br>programming options if<br>VGDH> 10 V, IGDH= –1 mA|
|Rail-to-rail output high<br>voltage|VGDHRR|VVCC– 0.5|—|VVCC|V|If VVCC< programmed<br>VGDHand output at high<br>state|
|Output high current in<br>PWM mode for GD0|–IGDH|—|100|—|mA|GDx_CFG.CUR = 8|
|Output high current<br>tolerance in PWM mode|ΔIGDH|—||±15|%|Calibrated**_9)_**|
|Discharge current for<br>GD0|IGDDIS|800|—|—|mA|VGD= 4 V and driver at<br>low state|
|Output low reverse<br>current|–IGDREVL|—|—|100|mA|Applies if VGD< 0 V and<br>driver at low state|
|Output high reverse<br>current in PWM mode|IGDREVH|—|1/6 of IGDH|—||Applies if<br>VGD> VGDH+ 0.5 V (typ)<br>and driver at high state|



> 9 referred to GDx_CFG.CUR = 16 

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## **Electrical Characteristics and Parameters** 

## **Table 18 Electrical Characteristics of the CSFB Pin** 

|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|Input voltage operating<br>range|VINP|–0.5|—|3.0|V||
|OCP2 comparator<br>reference voltage,<br>derived from VVDDA, given<br>values assuming<br>VVDDA= VVDDA,typ|VOCP2|—|1.6|—|V|SYS_CFG0.OCP2 = 00B|
|Threshold voltage<br>tolerance|ΔVOCP2|—|—|±5|%|Voltage divider tolerance|
|Comparator propagation<br>delay|tOCP2PD|15|—|35|ns||
|Minimum comparator<br>input pulse width|tOCP2PW|—|—|30|ns||
|OCP2F comparator<br>propagation delay|tOCP2FPD|70|—|170|ns|dVCS/dt = 100 V/µs|
|Delay from VCScrossing<br>VCSOCP2to begin of GDx<br>turn-of (IGD0> 2mA)|tCSGDxOCP2|125|135|190|ns|dVCS/dt = 100 V/µs;<br>fMCLK= 66 MHz. GDx<br>driven by QR_GATE<br>FIL_OCP2.STABLE = 3|
|OCP1 operating range|VOCP1|0|—|VREF/2|V|RANGE =00B|
|OCP1 threshold at full<br>scale setting<br>(CS_OCP1LVL=FFH) for<br>CS0|VOCP1FS|1192|1229|1266|mV|RANGE =00B|
|Delay from VCScrossing<br>VCSOCP1to CS_OCP1<br>rising edge, 1.2 V range|tCSOCP1|90|170|250|ns|Input signal slope dVCS/<br>dt = 150 mV/µs. This<br>slope represents a use<br>case of a switch-mode<br>power supply with<br>minimum input voltage.|
|Delay from CS_OCP1<br>rising edge to QR_GATE<br>falling edge|tOCP1GATE|—|—|12|ns|STB_RET31.<br>OCP_ASM_SEL=0|
|Delay from QR_GATE<br>falling edge to start of<br>GDx turn-of|tGATEGDx|1|3|5|ns|GDx driven by QR_GATE.<br>Measured up to<br>IGDx> 2 mA|
|OCP1 comparator input<br>single pulse width filter|tOCP1PW|60|—|95|ns|Shorter pulses than min.<br>are suppressed, longer<br>pulses than max. are<br>passed|



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## **Electrical Characteristics and Parameters** 

## **Table 18 Electrical Characteristics of the CSFB Pin (continued)** 

|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|Nominal S&H operating<br>range 0% to 100%|VCSH|0|—|VREF/2|V|CS_ICR.RANGE =00B|
|Reduced S&H operating<br>range|RRCVSH|8|—|92|%|CS_ICR.RANGE =00B<br>Operational values|
|Maximum error of CS0<br>S&H for corrected<br>measurement (8-bit<br>result)|TET0CS0S|—|—|4.7|LSB|CS_ICR.RANGE =00B|
|Maximum error of CS0<br>S&H for corrected<br>measurement (8-bit<br>result)|TET256CS0S|—|—|6.0|LSB|CS_ICR.RANGE =00B|
|Nominal S&H operating<br>range 0% to 100%|VCSH|0|—|VREF/6|V|CS_ICR.RANGE =11B|
|Reduced S&H operating<br>range|RRCVSH|20|—|80|%|CS_ICR.RANGE =11B<br>Operational values|
|Maximum error of CS0<br>S&H for corrected<br>measurement (8-bit<br>result)|TET0CS0S|—|—|8.0|LSB|CS_ICR.RANGE =11B|
|Maximum error of CS0<br>S&H for corrected<br>measurement (8-bit<br>result)|TET256CS0S|—|—|8.7|LSB|CS_ICR.RANGE =11B|
|S&H delay of input bufer|tCSHST|—|—|510|ns|Referring to jump in<br>input voltage. Limits the<br>minimum gate driver Ton<br>time.|



## **Table 19 Electrical Characteristics of the ZCD Pin** 

|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|Input voltage operating<br>range|VINP|–0.5|—|3.3|V||
|Input clamping current,<br>high|ICLH|—|—|100|µA||
|Zero-crossing threshold|VZCTHR|15|40|70|mV||
|Comparator propagation<br>delay|tZCPD|30|50|70|ns|dVZCD/dt = 4 V/µs|



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## **Electrical Characteristics and Parameters** 

## **Table 19 Electrical Characteristics of the ZCD Pin (continued)** 

|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|Input voltage negative<br>clamping level|–VINPCLN|140|180|220|mV|Analog clamp activated|
|Nominal I/V-conversion<br>operating range 0% to<br>100%|–IIV|0|—|4|mA|CRNG =00BGain = 600<br>mV/mA|
|Reduced I/V-conversion<br>operating range|RRIV|5|—|80|%||
|Maximum error for<br>corrected ADC<br>measurement (8-bit<br>result)|TET0IV|—|—|4.1|LSB8|CRNG =00B|
|Maximum error for<br>corrected ADC<br>measurement (8-bit<br>result)|TET256IV|—|—|9.7|LSB8|CRNG =00B|
|Maximum deviation<br>between ZCD clamp<br>voltage and trim result<br>stored in OTP|EZCDClp|—|—|±5|%|–IIV> 0.25 mA|
|IV-conversion delay of<br>input bufer|tIVST|—|—|900|ns|Refers to jump in input<br>current**_10)_**|
|Nominal S&H input<br>voltage range 0% to<br>100%|VZSH|0|—|2/3 · VREF|V|SHRNG =0B|
|Nominal S&H input<br>voltage range 0% to<br>100%|VZSH|VREF/2|—|7/6 · VREF|V|SHRNG =1B|
|Reduced S&H input<br>voltage range|RRZVSH|4|—|95|%||
|Maximum error for<br>corrected ADC<br>measurement (8-bit<br>result)|TET0ZVS0|—|—|3.7|LSB8|SHRNG =0B|
|Maximum error for<br>corrected ADC<br>measurement (8-bit<br>result)|TET256ZVS0|—|—|4.9|LSB8|SHRNG =0B|



> 10 Limits the minimum gate driver Ton time. 

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## **Electrical Characteristics and Parameters** 

## **Table 19 Electrical Characteristics of the ZCD Pin (continued)** 

|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|Maximum error for<br>corrected ADC<br>measurement (8-bit<br>result)|TET0ZVS1|—|—|4.2|LSB8|SHRNG =1B|
|Maximum error for<br>corrected ADC<br>measurement (8-bit<br>result)|TET256ZVS1|—|—|5.8|LSB8|SHRNG =1B|
|S&H delay of input bufer<br>referring to jump of input<br>voltage|tZSHST|—|—|1.0|µs|SHRNG =0BTj≤ 125 °C|
|S&H delay of input bufer<br>referring to jump of input<br>voltage|tZSHST|—|—|1.6|µs|SHRNG =1BTj≤ 125 °C|



## **Table 20 Electrical Characteristics of the VS Pin** 

|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|Nominal measurement<br>range 0% to 100%|VVS|0|—|VREF|V|Gain 1, no ofset|
|Nominal measurement<br>range 0% to 100%|VVS|5/6·VREF|—|7/6·VREF|V|Gain 3, with ofset|
|Reduced operating range|RRVVS|5|—|95|%|Gain 1, no ofset|
|Reduced operating range|RRVVS|10|—|90|%|Gain 3, with ofset|
|Maximum error for<br>corrected measurement<br>(8-bit result)|TET0VS|—|—|4.1|LSB8|Range 1, no ofset|
|Maximum error for<br>corrected measurement<br>(8-bit result)|TET256VS|—|—|5.6|LSB8|Range 1, no ofset|
|Maximum error for<br>corrected measurement<br>(8-bit result)|TET0VS|—|—|12.0|LSB8|Range 2, with ofset|
|Maximum error for<br>corrected measurement<br>(8-bit result)|TET256VS|—|—|12.9|LSB8|Range 2, with ofset|
|Overvoltage comparator<br>threshold|THROV|2.70|2.8|2.90|V||
|Overvoltage comparator<br>propagation delay|tPDOV|—|—|300|µs|Step at input|



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## **Electrical Characteristics and Parameters** 

## **Table 21 Electrical Characteristics of the HV Pin** 

|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|Leakage current at HV<br>pin|IHVleak|—|—|10|µA|VHV= 600 V HV startup<br>cell disabled|
|Nominal current for<br>measurement path 0% to<br>100%|IMEAS|0|—|4.8|mA|CURRNG = 10B|
|Reduced measurement<br>range for current path|RRIMEAS|5|—|80|%|CURRNG = 10B.<br>Operational values.|
|Maximum error for<br>corrected ADC<br>measurement (8-bit<br>result, temperature gain<br>correction applied)|TET0DP|—|—|3.7|LSB8|CURRNG = 10B|
|Maximum error for<br>corrected ADC<br>measurement (8-bit<br>result, temperature gain<br>correction applied)|TET256DP|—|—|7.9|LSB8|CURRNG = 10B|
|Comparator threshold (in<br>% of full range of IMEAS)|THRCOMP|15|20|25|%|COMPTHR= 00B|
|Comparator threshold (in<br>% of full range of IMEAS)|THRCOMP|25|30|35|%|COMPTHR= 01B|
|Comparator threshold (in<br>% of full range of IMEAS)|THRCOMP|35|40|45|%|COMPTHR= 10B|
|Comparator threshold (in<br>% of full range of IMEAS)|THRCOMP|45|50|55|%|COMPTHR= 11B|



## **Table 22 Electrical Characteristics of the PWM Pin** 

|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|Input capacitance|CINPUT|—|—|10|pF||
|Input low voltage|VIL|—|—|1.0|V||
|Input high voltage|VIH|2.0|—|—|V||
|Input leakage current, no<br>pull device|ILK|–5|—|+1|µA|VMFIO= 0 V / 3 V|
|Input low current with<br>active weak pull-up WPU|–ILPU|30|—|90|µA|Measured at max. VIL|
|Input high current with<br>active weak pull-down<br>WPD|IHPD|90|—|300|µA|Measured at min. VIH|



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## **Electrical Characteristics and Parameters** 

## **Table 22 Electrical Characteristics of the PWM Pin (continued)** 

|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|Max. input frequency|fINPUT|15|—|—|MHz||
|Pull-up resistor value|RPU|—|2.25|—|kΩ|RPU=1111B|
|Pull-up resistor tolerance|ΔRPU|—|—|±20|%|Overall tolerance|
|PWM input frequency|fPWM|500|—|2000|Hz||
|PWM duty cycle|DPWM|5|—|95|%||



## **Table 23 Electrical Characteristics of the TEMP Pin** 

|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|MFIO reference voltage|VMFIOREF|—|VREF|—|V|Selection = VREF|
|Nominal range 0% to<br>100%|VMFIO|0|—|VREF|V|Gain = 1|
|Reduced operating range|RRVMFIO|4|—|96|%|Gain = 1. Operational<br>values.|
|Maximum error for<br>corrected measurement<br>(8-bit result)|TET0MFI0|—|—|4.0|LSB8|Gain = 1|
|Maximum error for<br>corrected measurement<br>(8-bit result)|TET256MFI0|—|—|4.8|LSB8|Gain = 1|
|Ofset calibration voltage|VCAL|—|VMFIOREF/8|—|V||
|Ofset calibration voltage<br>absolute tolerance|ΔVCAL|—|—|±3|LSB|Ref. to VMFIOREF=VREF,<br>Gain = 1|
|Ofset calibration voltage<br>variation over<br>temperature|ΔVCAL_TMP|—|—|±1|LSB|Ref. to VMFIOREF=VREF,<br>Gain = 1|
|Pull-up resistor value|RPU|—|11|—|kΩ|RPU=0110B|
|Pull-up resistor tolerance|ΔRPU|—|—|±20|%|Overall tolerance|



## **Table 24 Electrical Characteristics of the CSPFC Pin** 

|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|Input voltage operating<br>range|VINP|–0.5|—|3.0|V||
|OCP1 operating range|VOCP1|0|—|VREF/2|V|RANGE =00B|



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## **Electrical Characteristics and Parameters** 

## **Table 24 Electrical Characteristics of the CSPFC Pin (continued)** 

|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|OCP2 comparator<br>reference voltage,<br>derived from VVDDA, given<br>values assuming<br>VVDDA= VVDDA,typ|VOCP2|—|1.6|—|V|SYS_CFG0.OCP2 = 00B|
|Threshold voltage<br>tolerance|ΔVOCP2|—|—|±5|%|Voltage divider tolerance|
|Comparator propagation<br>delay|tOCP2PD|15|—|35|ns||
|Minimum comparator<br>input pulse width|tOCP2PW|—|—|30|ns||
|OCP2F comparator<br>propagation delay|tOCP2FPD|70|—|170|ns|dVCS/dt = 100 V/µs|
|Delay from VCScrossing<br>VCSOCP2to begin of GDx<br>turn-of (IGD0> 2mA)|tCSGDxOCP2|125|135|190|ns|dVCS/dt = 100 V/µs;<br>fMCLK= 66 MHz. GDx<br>driven by QR_GATE<br>FIL_OCP2.STABLE = 3|
|Nominal S&H operating<br>range 0% to 100%|VCSH|0|—|VREF/2|V|CS_ICR.RANGE =00B|
|Reduced S&H operating<br>range|RRCVSH|4|—|90|%|Operational values|
|Hysteretic comparator<br>threshold|THRHYS|—|0.54|—|V|1 → 0 transition|
|Hysteretic comparator<br>threshold|THRHYS|—|1.53|—|V|0 → 1 transition|
|Hysteretic comparator<br>threshold tolerance|ΔTHRHYS|—|—|±120|mV||
|Hysteretic comparator<br>propagation delay|tPDHYS|—|90|—|ns|Rising edge|
|Hysteretic comparator<br>propagation delay|tPDHYS|—|40|—|ns|Falling edge|
|Hysteretic comparator<br>minimum input pulse<br>width|tPWHYS|—|—|300|ns||



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## **Electrical Characteristics and Parameters** 

## **Table 25 Electrical Characteristics of the UART Pin** 

|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|Input clamping current,<br>low|–ICLL|—|—|100|µA|only digital input|
|Input clamping current,<br>high|ICLH|—|—|100|µA|only digital input|
|APD low voltage (active<br>pull-down while device is<br>not powered or gate<br>driver is not enabled)|VAPD|—|—|1.6|V|IGD= 5 mA|
|Input capacitance|CINPUT|—|—|25|pF||
|Input low voltage|VIL|—|—|1.0|V||
|Input high voltage|VIH|2.1|—|—|V||
|Input low current with<br>active weak pull-up WPU|–ILPU|30|—|90|µA|Measured at max. VIL|
|Max. input frequency|fINPUT|15|—|—|MHz||
|Output low voltage|VOL|—|—|0.8|V|IOL= 2 mA|
|Output high voltage|VOH|2.4|—|—|V|IOH= –2 mA|
|Output sink current|IOL|—|—|2|mA||
|Output source current|-IOH|—|—|2|mA||
|Output rise time (0 → 1)|tRISE|—|—|50|ns|20 pF load, push/pull<br>output|
|Output fall time (1 → 0)|tFALL|—|—|50|ns|20 pF load, push/pull or<br>open-drain output|
|Max. output switching<br>frequency|fSWITCH|10|—|—|MHz||
|UART baudrate|fUART|9600||105000|baud||



## **Table 26 Electrical Characteristics of the GDPFC Pin** 

|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|Input clamping current,<br>low|–ICLL|—|—|100|µA|only digital input|
|Input clamping current,<br>high|ICLH|—|—|100|µA|only digital input|
|APD low voltage (active<br>pull-down while device is<br>not powered or gate<br>driver is not enabled)|VAPD|—|—|1.6|V|IGD= 5 mA|



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## **Electrical Characteristics and Parameters** 

## **Table 26 Electrical Characteristics of the GDPFC Pin (continued)** 

|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|RPPDvalue|RPPD|—|600|—|kΩ|Permanent pull-down<br>resistor inside gate<br>driver|
|RPPDtolerance|ΔPPD|—|—|±25|%|Permanent pull-down<br>resistor inside gate<br>driver|
|Driver output low<br>impedance for GD1/2|RGDL|—|—|7.0|Ω|TJ≤ 125 °C, IGD=  0.1 A|
|Nominal output high<br>voltage in PWM mode|VGDH|—|10.5|—|V|GDx_CFG.VOL = 3,<br>IGDH= –1 mA|
|Output voltage tolerance|ΔVGDH|—|—|±5|%|Tolerance of<br>programming options if<br>VGDH> 10 V, IGDH= –1 mA|
|Rail-to-rail output high<br>voltage|VGDHRR|VVCC– 0.5|—|VVCC|V|If VVCC< programmed<br>VGDHand output at high<br>state|
|Output high current in<br>PWM mode for GD1/2|–IGDH|—|104|—|mA|GDx_CFG.CUR = 24|
|Output high current<br>tolerance in PWM mode|ΔIGDH|—||±15|%|Calibrated**_11)_**|
|Discharge current for<br>GD1/2|IGDDIS|500|—|—|mA|VGD= 4 V and driver at<br>low state|
|Output low reverse<br>current|–IGDREVL|—|—|100|mA|Applies if VGD< 0 V and<br>driver at low state|
|Output high reverse<br>current in PWM mode|IGDREVH|—|1/6 of IGDH|—||Applies if<br>VGD> VGDH+ 0.5 V (typ)<br>and driver at high state|



## **Table 27 Electrical Characteristics of the A/D Converter** 

|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|Integral non-linearity|INL|—|—|1|LSB8|**_12)_**|



- 11 referred to GDx_CFG.CUR = 16 

- 12 ADC capability measured via channel MFIO without errors due to switching of neighbouring pins, e.g. gate drivers, measured with STC = 5. MFIO buffer non-linearity masked out by taking ADC output values ≥ 30 only. 

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## **Electrical Characteristics and Parameters** 

## **Table 28 Electrical Characteristics of the Reference Voltage** 

|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|Reference voltage|VREF|—|2.428|—|V||
|VREF overall tolerance|ΔVREF|—|—|±1.5|%|Trimmed, Tj≤ 125 °C and<br>aging|



## **Table 29 Electrical Characteristics of the OTP Programming** 

|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|OTP programming<br>voltage at the VCC pin for<br>range C000Hto CFFFH|VPP|7.35|7.5|7.65|V|Operational values|
|OTP programming<br>voltage at the VCC pin for<br>range D000Hto DFFFH|VPP|9.0|—|VVCC|V|Operational values|
|OTP programming<br>current|IPP|—|1.6|—|mA|Programming of 4 bits in<br>parallel|



## **Table 30 Electrical Characteristics of the Clock Oscillators** 

|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|Master clock oscillation<br>period including all<br>variations|tMCLK|19.2|20.0|21.1|ns|In reference to 50 MHz<br>fMCLK|
|Main clock oscillator<br>frequency variation of<br>stored DPARAM<br>frequency|ΔMCLK|–3.2|—|+2.0|%|Temperature drif and<br>aging only, 50 MHz fMCLK|
|Standby clock oscillator<br>frequency|fSTBCLK|96|100|104|kHz|Trimming tolerance at<br>TA= 25 °C|
|Standby clock oscillator<br>frequency|fSTBCLK|90|100|110|kHz|Overall tolerance|



## **Table 31 Electrical Characteristics of the Temperature Sensor** 

|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|Temperature sensor ADC<br>output operating range|ADCTEMP|0|—|190|LSB|ADCTEMP= 40 +<br>temperature / °C)|
|Temperature sensor<br>tolerance|ΔTEMP|—|—|±6|K|Incl. ADC conversion<br>accuracy at 3 σ|



Data Sheet 

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## **Package Dimensions** 

## **6 Package Dimensions** 

The package dimensions of PG-DSO-16 are provided. 

**==> picture [120 x 89] intentionally omitted <==**

**==> picture [89 x 81] intentionally omitted <==**

**==> picture [40 x 98] intentionally omitted <==**

**==> picture [89 x 48] intentionally omitted <==**

## **Figure 29 Package Dimensions for PG-DSO-16** 

_Note_ : _Dimensions in mm._ 

_Note_ : _You can find all of our packages, packing types and other package information on our Infineon Internet page “Products”: http://www.infineon.com/products._ 

Data Sheet 

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## **References** 

## **7 References** 

**1.** Infineon Technologies AG: _XDPL8220 Reference Board Test Report_ 

**2.** Infineon Technologies AG: _.dp Interface Gen2_ : Can be ordered at _**http://ehitex.com/programmer/486/.dpinterface-board-gen2**_ 

**3.** Infineon Technologies AG: _.dp Vision User Manual_ 

**4.** Infineon Technologies AG: _.dp Interface Gen2 User Manual_ 

**5.** Infineon Technologies AG: _XDPL8220 Design Guide_ 

**6.** Infineon Technologies AG: _XDPL8220 Programming Manual_ 

## **Abbreviations** 

## **AC** 

## _Alternating Current (AC)_ 

An Alternating Current is a form of power supply in which the flow of electric charge periodically reverses direction. 

## **ADC** 

_Analog-to-Digital Converter (ADC)_ 

An analog-to-digital converter is a device that converts a continuous physical quantity (usually voltage) to a digital number that represents the quantity's amplitude. 

## **BOM** 

## _Bill of Materials (BOM)_ 

A bill of materials is a list of the raw materials, sub-assemblies, intermediate assemblies, sub-components, parts and the quantities of each needed to manufacture an end product. 

## **CC** 

## _Constant Current (CC)_ 

Constant Current is a mode of a power supply in which the output current is kept constant regardless of the load. 

## **CCM** 

_Continuous Conduction Mode (CCM)_ 

Continuous Conduction Mode is an operational mode of a switching power supply in which the current is continuously flowing and does not return to zero. 

## **CRC** 

## _Cyclic Redundancy Check (CRC)_ 

A cyclic redundancy check is an error-detecting code commonly used to detect accidental changes to raw data. 

## **CV** 

## _Constant Voltage (CV)_ 

Constant Voltage is a mode of a power supply in which the output voltage is kept constant regardless of the load. 

## **DAC** 

## _Digital-to-Analog Converter (DAC)_ 

A digital-to-analog converter is a device that converts digital data into an analog signal (typically voltage). 

## **DC** 

## _Direct Current (DC)_ 

A Direct Current is a form of power supply in which the flow of electric charge is only into one direction. 

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## **Abbreviations** 

## **DCM** 

## _Discontinuous Conduction Mode (DCM)_ 

Discontinuous Conduction Mode is an operational mode of a switching power supply in which the current starts and returns to zero. 

## **ECG** 

## _Electronic Control Gear (ECG)_ 

An electronic control gear is a power supply which provides one or more light module(s) with the appropriate voltage or current. 

## **FB** 

## _Flyback (FB)_ 

A flyback converter is a power converter with the inductor split to form a transformer, so that the voltage ratios are multiplied with an additional advantage of galvanic isolation between the input and any outputs. 

## **FW** 

_Firmware (FW)_ 

A proprietary software exploiting a set of functions. 

## **GUI** 

## _Graphic User Interface (GUI)_ 

A graphical user interface is a type of interface that allows users to interact with electronic devices through graphical icons and visual indicators. 

## **HW** 

## _Hardware (HW)_ 

The collection of physical elements that comprise a computer system. 

## **IC** 

## _Integrated Circuit (IC)_ 

A miniaturized electronic circuit that has been manufactured in the surface of a thin substrate of semiconductor material. An IC may also be referred to as micro-circuit, microchip, silicon chip, or chip. 

## **IIR** 

## _Infinite Impulse Response (IIR)_ 

Infinite impulse response is a property applying to many linear time-invariant systems. Common examples of linear time-invariant systems are most electronic and digital filters. Systems with this property have an impulse response which does not become exactly zero past a certain point, but continues indefinitely. 

## **LED** 

## _Light Emitting Diode (LED)_ 

A light-emitting diode is a two-lead semiconductor light source which emits light when activated. 

## **LP** 

## _Limited Power (LP)_ 

Limited Power is a mode of a power supply in which the output power is limited regardless of the load. 

## **NTC** 

## _Negative Temperature Coefficient Thermistor (NTC)_ 

A negative temperature coefficient thermistor is a type of resistor whose resistance declines over temperature. 

## **OCP1** 

## _Overcurrent Protection Level 1 (OCP1)_ 

The Overcurrent Protection Level 1 is limiting the current in a switched-mode power supply to limit the power delivered to the output of the power supply. 

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## **Abbreviations** 

## **OCP2** 

## _Overcurrent Protection Level 2 (OCP2)_ 

The Overcurrent Protection Level 2 is protecting the current in a switched-mode power supply from exceeding a maximum threshold. 

## **OTP** 

_One Time Programmable Memory (OTP)_ 

A One-Time Programmable memory is a form of memory to which data can be written once. After writing, the data is stored permanently and cannot be further changed. 

## **PF** 

_Power Factor (PF)_ 

Power factor is the ratio between the real power and the apparent power. 

## **PFC** 

## _Power Factor Correction (PFC)_ 

Power factor correction increases the power factor of an AC power circuit closer to 1 which corresponds to minimizing the reactive power of the power circuit. 

## **PSR** 

## _Primary Side Regulated (PSR)_ 

A Primary Side Regulated power supply is controlling its operation based on a property sensed on primary side of an isolated power supply. 

## **PWM** 

_Pulse Width Modulation (PWM)_ 

Pulse-width modulation is a technique to encode an analog value into the duty cycle of a pulsing signal with arbitrary amplitude. 

## **QRM** 

_Quasi-Resonant Mode (QRM)_ 

Quasi-Resonant Mode is an operating mode of a switched-mode power supply which maximizes efficiency. This is achieved by only switching at preferred times when switching losses are low. 

## **QRM1** 

## _Quasi-Resonant Mode, switching in valley 1 (QRM1)_ 

Quasi-Resonant Mode is an operating mode of a switched-mode power supply which maximizes efficiency. This is achieved by switching at the occurrence of the first valley of a signal which corresponds to a time when switching losses are low. 

## **QRMn** 

## _Quasi-Resonant Mode, switching in valley n (QRMn)_ 

Quasi-Resonant Mode is an operating mode of a switched-mode power supply which maximizes efficiency. This is achieved by switching at the occurence of an nth valley of a signal which corresponds to a time when switching losses are low. 

## **RAM** 

## _Random Access Memory (RAM)_ 

Random-access memory is a form of computer data storage which allows data items to be read and written regardless of the order in which data items are accessed. 

## **THD** 

## _Total Harmonic Distortion (THD)_ 

The total harmonic distortion of a signal is a measurement of the harmonic distortion present and is defined as the ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency. 

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## **Revision History** 

## **UART** 

_Universal Asynchronous Receiver Transmitter (UART)_ 

A universal asynchronous receiver transmitter is used for serial communications over a peripheral device serial port by translating data between parallel and serial forms. 

## **USB** 

_Universal Serial Bus (USB)_ 

Universal Serial Bus is an industry standard that defines cables, connectors and communications protocols used in a bus for connection, communication, and power supply between computers and electronic devices. 

## **UVLO** 

## _Undervoltage Lockout (UVLO)_ 

The Undervoltage-Lockout is an electronic circuit used to turn off the power of an electronic device in the event of the voltage dropping below the operational value. 

## **Revision History** 

Major changes since previous revision 

|**Revision History**<br>Major changes since previous revision|**Revision History**<br>Major changes since previous revision|
|---|---|
|||
|**Revision History**||
|**Revision**|**Description**|
|1.0|•<br>Added the attention that the Vcc must be higher than 3.4V before any other pins<br>exceeds 1.2V|
|0.7|•<br>Added a description of the input filter for the PWM sensing|
|0.6|•<br>Corrected for English language<br>•<br>Minor update of the PFC and FB content<br>•<br>Updated electrical characteristics|



Data Sheet 

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## **Trademarks of Infineon Technologies AG** 

µHVIC[™] , µIPM[™] , µPFC[™] , AU-ConvertIR[™] , AURIX[™] , C166[™] , CanPAK[™] , CIPOS[™] , CIPURSE[™] , CoolDP[™] , CoolGaN[™] , COOLiR[™] , CoolMOS[™] , CoolSET[™] , CoolSiC[™] , DAVE[™] , DI-POL[™] , DirectFET[™] , DrBlade[™] , EasyPIM[™] , EconoBRIDGE[™] , EconoDUAL[™] , EconoPACK[™] , EconoPIM[™] , EiceDRIVER[™] , eupec[™] , FCOS[™] , GaNpowIR[™] , HEXFET[™] , HITFET[™] , HybridPACK[™] , iMOTION[™] , IRAM[™] , ISOFACE[™] , IsoPACK[™] , LEDrivIR[™] , LITIX[™] , MIPAQ[™] , ModSTACK[™] , my-d[™] , NovalithIC[™] , OPTIGA[™] , OptiMOS[™] , ORIGA[™] , PowIRaudio[™] , PowIRStage[™] , PrimePACK[™] , PrimeSTACK[™] , PROFET[™] , PRO-SIL[™] , RASIC[™] , REAL3[™] , SmartLEWIS[™] , SOLID FLASH[™] , SPOC[™] , StrongIRFET[™] , SupIRBuck[™] , TEMPFET[™] , TRENCHSTOP[™] , TriCore[™] , UHVIC[™] , XHP[™] , XMC[™] . 

Trademarks Update 2015-12-22 

## **Other Trademarks** 

All referenced product or service names and trademarks are the property of their respective owners. 

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|**© 2016 Infineon Technologies AG**<br>**All Rights Reserved.**|application of the product, Infineon Technologies<br>hereby disclaims any and all warranties and liabilities of<br>any kind, including without limitation warranties of|Technologies in a written document signed by<br>authorized representatives of Infineon Technologies,<br>Infineon Technologies’ products may not be used in|
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|**Do you have a question about any**|third party.|any consequences of the use thereof can reasonably|
|**aspect of this document?**|In addition, any information given in this document is|be expected to result in personal injury|
|**Email:erratum@infineon.com**|subject to customer’s compliance with its obligations<br>stated in this document and any applicable legal||
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|**IFX-sch1429523754663**|Infineon Technologies in customer’s applications.||
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||intended for technically trained staf. It is the||
||responsibility of customer’s technical departments to||
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||information given in this document with respect to such||
||application.||
Updated at March 15, 2026
Infineon Technologies is a globally recognized leader in semiconductor solutions, renowned for driving innovation in power management, energy efficiency, and modern mobility. With a strong legacy of engineering excellence, the company provides highly reliable components designed to meet the rigorous demands of industrial, automotive, and advanced commercial applications. The core of our Infineon portfolio is centered on their industry-leading discrete semiconductors. We offer an extensive selection of single and dual MOSFETs, alongside a robust range of single IGBTs and advanced IGBT modules. These flagship power transistors are essential for high-efficiency power conversion and motor control, providing engineers with superior thermal performance and minimized switching losses. Beyond advanced field-effect transistors, the selection includes a comprehensive array of diodes and rectifiers, heavily featuring Schottky diodes, as well as fast-recovery and RF/PIN diodes. This power foundation is further supported by bipolar transistors, intelligent power modules, and thyristor SCR modules, delivering the critical building blocks required for complex power system designs. To support broader system integration, the portfolio also encompasses specialized solutions such as solid-state relays, AC/DC LED driver ICs, and Bluetooth communications modules. From high-power industrial rectifiers to wireless connectivity adapters, Infineon equips designers with the precision components needed to build efficient, scalable, and fully connected electronic systems.
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