XDPL8219XUMA1

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## **XDPL8219 Digital Flyback Controller IC** 

## **XDP[™] Digital Power** 

## **Features** 

- Flyback controller with _**Power Factor Correction (PFC)**_ 

- _**Secondary Side Regulated (SSR) Constant Voltage (CV)**_ output 

- Integrated 600 V high voltage startup cell 

- Supports universal AC input (90 Vrms to 305 Vrms) and DC input (127 V to 431 V) 

- Enhanced _**Total Harmonic Distortion (THD)**_ correction 

- Enhanced _**Power Factor (PF)**_ correction 

- PF > 0.9 and THD < 10% across a wide load range, for AC input up to 277 Vrms 

- High efficiency and low _**Electro-Magnetic Interference (EMI)**_ , with _**Quasi-Resonant Mode, switching in valley n (QRMn)**_ 

- No-load standby power as low as < 100 mW and low audible noise, with _**Active Burst Mode (ABM)**_ 

- Low EMI with switching frequency dithering for constant DC input 

- Reporting of the input voltage, line frequency, controller temperature, input voltage loss, and error code of last triggered protection, via uni-directional _**Universal Asynchronous Receiver Transmitter**_ communication 

- Protection features: input over-voltage, input under-voltage, output over-voltage, output short, _VCC_ overvoltage, _VCC_ under-voltage and _**Integrated Circuit (IC)**_ over-temperature protections 

- UL1310 safety feature: Adaptive _CS_ pin maximum voltage and QRMn minimum valley number limits based on estimated input voltage, to prevent excessive output power at higher input voltage 

- Digitally configurable parameters: maximum switching frequency, ABM burst frequency, protection threshold and reaction (auto-restart/latch), etc. 

## **Product validation** 

Qualified for industrial applications according to the relevant tests of JEDEC47/20/22. 

## **Potential applications** 

- Front-stage _**PFC**_ converter of the Electronic Control Gear for LED luminaires 

Please read the Important Notice and Warnings at the end of this document 

Data Sheet **www.infineon.com** 

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**XDPL8219 Digital Flyback Controller IC XDP[™] Digital Power** 

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## **Description** 

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Output<br>AC Input<br>voltage<br>VCC ZCD<br>GD CoolMOS™<br>HV Flyback  CS<br>Controller IC<br>GND UART FB Feedback<br>Circuit<br>**----- End of picture text -----**<br>


## **Figure 1 Typical Application for XDPL8219** 

_Note: The_ _**SSR CV** output in_ _**Figure 1** should not be used to directly drive the LEDs. For LED lighting application, it should be converted to constant current output by a second-stage DC-DC switching or linear regulator._ 

|**Product type**|**Package**|**Marking**|**Firmware version**|**Ordering code**|
|---|---|---|---|---|
|XDPL8219|PG-DSO-8|L8219|0.0.1.1|SP002990946|



## **Description** 

The XDPL8219 is a high performance _**SSR CV**_ controller for the high power factor flyback converter. The device operates in _**QRMn**_ to maximize the efficiency and minimize the _**EMI**_ , across a wide load range. It enters _**ABM**_ at light load to prevent audible noise and at the same time achieving no-load standby power as low as < 100 mW. 

The XDPL8219 detects the input voltage type (AC or constant DC) and adapts its proprietary voltage mode pulse modulator accordingly to enhance the system performance. For AC input, it adapts the pulse modulation to achieve high _**PF**_ (>0.9) and low _**THD**_ (<10%) over wide input and load range. For constant DC input, it adapts the pulse modulation which dithers the switching frequency to lower the EMI over the entire operating range. 

Infineon's innovative digital power platform maximizes the XDPL8219 performance in a standard DSO-8 package. The XDPL8219 transmits _**UART**_ signals to report the estimated input voltage, estimated line frequency, controller temperature, last error code and input voltage loss indication. In addition, it provides the maximum design flexibility and performance optimization with parameter configuration via UART. Infineon offers the programming tools including an user friendly _**Graphic User Interface**_ for _**Personal Computer**_ s, to configure the XDPL8219 parameters. 

The device has a built-in 600 V _HV_ start-up cell and also a proprietary start-up sequence to ensure a fast output voltage rise with minimal overshoot. 

Data Sheet 

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## **Table of contents** 

## **Table of contents** 

||**Features**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1|
|---|---|
||**Product validation**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1|
||**Potential applications**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1|
||**Description**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2|
||**Table of contents**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3|
|**1**|**Pin configuration**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5|
|**2**|**Functional block diagram**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6|
|**3**|**Functional description**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7|
|3.1|Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7|
|3.2|Regulated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7|
|3.3|Operation cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11|
|3.4|Line synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11|
|3.5|Enhanced power quality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11|
|3.6|Switching frequency dithering for constant DC input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12|
|3.7|Configurable gate voltage rising slope at GD pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12|
|3.8|UART reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12|
|3.9|Input voltage and output voltage estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13|
|3.9.1|Output voltage estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13|
|3.9.2|Input voltage estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14|
|3.10|Protection features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15|
|3.10.1|Primary MOSFET overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15|
|3.10.2|Output undervoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15|
|3.10.3|Output overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16|
|3.10.4|Transformer demagnetization time shortage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17|
|3.10.5|Minimum input voltage startup check and input undervoltage protection . . . . . . . . . . . . . . . . . . 17|
|3.10.6|Maximum input voltage startup check and input overvoltage protection . . . . . . . . . . . . . . . . . . . 18|
|3.10.7|VCC undervoltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18|
|3.10.8|VCC undervoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18|
|3.10.9|VCC overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19|
|3.10.10|IC overtemperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19|
|3.10.11|Other protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19|
|3.10.12|Protection reactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20|
|3.11|Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20|
|**4**|**List of Parameters**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21|
|**5**|**Electrical Characteristics and Parameters**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27|
|5.1|Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27|
|5.2|Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27|



Data Sheet 

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## **Table of contents** 

|5.3|Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28|
|---|---|
|5.4|DC Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29|
|**6**|**Package Dimensions**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40|
|**7**|**References**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41|
|**8**|**Revision History**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41|
||**Glossary**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41|
||**Disclaimer**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45|



Data Sheet 

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## **1 Pin configuration** 

## **1 Pin configuration** 

Pin assignments and basic pin description information are shown below. 

|||||||||||
|---|---|---|---|---|---|---|---|---|---|
|ZCD||||1|8||||GND|
|||||||||||
|FB||||2|7||||VCC|
|||||||||||
|CS||||3|6||||UART|
|||||||||||
|GD||||4|5||||HV|
|||||||||||
||||PG-DSO-8||(150mil)|||||



|**Figure 2**<br>**Pinning of XDPL8219**|**Figure 2**<br>**Pinning of XDPL8219**|**Figure 2**<br>**Pinning of XDPL8219**|**Figure 2**<br>**Pinning of XDPL8219**|
|---|---|---|---|
|**Table 1**<br>**Pin definitions and functions**||||
|**Name**|**Pin**|**Type**|**Function**|
|_ZCD_|1|I|Zero-crossing detection:<br>The_ZCD_pin is connected to the transformer auxiliary winding via external<br>resistors divider. It is used for zero-crossing detection, primary-side output<br>voltage sensing and input voltage sensing.|
|_FB_|2|I|Secondary Side Feedback:<br>The_FB_pin is used as a feedback pin for**_SSR_**.|
|_CS_|3|I|Current sensing:<br>The_CS_pin is used for Flyback MOSFET current sensing via external shunt<br>resistor.|
|_GD_|4|O|Gate driver:<br>The_GD_pin is used for Flyback MOSFET gate drive control via external series<br>resistor.|
|_HV_|5|I|High voltage:<br>The_HV_pin is connected to the rectified input voltage via external series<br>resistor. The_HV_pin is used to charge_VCC_pin voltage during startup and<br>protection, via an internal 600 V startup cell. In addition, it is also used for<br>line synchronization.|
|_UART_|6|I/O|**_UART_**configuration:<br>The_UART_pin is used as the digital interface for IC parameter configuration. It<br>can also be used for the information reporting based on the uni-directional<br>_UART_communication (when_UART_reporting is enabled).|
|_VCC_|7|I|Operating voltage supply and sensing|
|_GND_|8|-|**_IC_**grounding|



Data Sheet 

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## **2 Functional block diagram** 

## **2 Functional block diagram** 

The functional block diagram shows the basic data flow from input pins via signal processing to the output pins. 

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**----- Start of picture text -----**<br>
Flyback (with PFC)<br>Input voltage<br>VCC charging estimation<br>Line<br>HV ZCD<br>synchronization<br>VCC VCC  Output voltage  Output current  CS<br>management estimation estimation<br>UART<br>PFC and THD<br>UART parametrization  GD<br>correction<br>and reporting<br>Feedback<br>Temperature  Multimode<br>protection controller sensing & FB<br>filter<br>**----- End of picture text -----**<br>


**Figure 3 XDPL8219 functional block diagram** 

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## **3 Functional description** 

## **3 Functional description** 

The functional description provides an overview about the integrated functions and features as well as their relationship. The mentioned parameters and equations are based on typical values at _T_ A = 25°C. The corresponding min. and max. values are shown in the electrical characteristics. 

## **3.1 Startup** 

The XDPL8219 enters startup phase upon checking the pre-startup conditions (e.g. estimated input voltage, _**IC**_ temperature) are within limits. During the startup phase, the soft start phase is initiated and followed by the output charging phase. The soft start phase is to minimize the component stress during startup, while the output charging phase is to fast charge the output voltage to Vout,start parameter for fast _VCC_ voltage self supply takeover from the primary auxiliary winding. 

After the startup phase is ended without any protection triggering, the regulated mode will be entered for output regulation based on the feedback voltage mapping. 

## **3.2 Regulated mode** 

In regulated mode, the _FB_ pin voltage signal is periodically sampled and digitally filtered. Based on the filtered feedback voltage _V_ FB,filtered mapping in _**Figure 4**_ , the mode of operation ( _**QRMn**_ , _**Discontinuous Conduction Mode (DCM)**_ or _**ABM**_ ) and the respective switching parameters (on-time _t_ on, valley number _N_ valley, minimum switching period _t_ sw,min, pulse number _n_ ABM) are periodically updated in each _**Operation cycle**_ . The update rate of each switching parameter is independent, and can differ based on the operating mode and conditions. 

## _**FB**_ **pin voltage pull-up and sampling** 

The controller has a typical voltage reference _V_ REF of 2.428 V, which is internally connected to its _FB_ pin via an internal pull-up resistor. The internal pull-up resistor value is configurable between 2.25 kohm and 7.5 kohm, based on the _R_ FB,pull,up parameter. For the power savings in ABM, the controller disables the internal pull-up during sleep. 

To have a high signal-to-noise ratio, the _FB_ pin voltage is periodically sampled, at the end of the _CS_ leading edge blanking time _t_ CS,LEB. 

## **Feedback voltage filtering** 

The filtering of the sampled feedback voltage depends on the operating mode and conditions: 

- QRMn/DCM: 

   - When the _HV_ pin _**Line synchronization**_ is properly in place with an AC input, or when a constant DC input voltage is detected by the controller, for a duration more than the _n_ notch,blank parameter, a digital notch filter is enabled. Otherwise, the sampled feedback voltage is processed by a digital low pass filter, to reduce the high frequency component. 

The digital notch filter suppresses either the double-line-frequency sine-wave component of an AC input, or the sine-wave component generated by the _**Switching frequency dithering for constant DC input voltage**_ , to stabilize the filtered feedback voltage _V_ FB,filtered. 

- ABM: 

The sampled feedback voltage is processed by a digital low pass filter during the burst pulsing, to reduce the high frequency component. 

Data Sheet 

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## **3 Functional description** 

## **Filtered feedback voltage mapping** 

## **Figure 4 Filtered feedback voltage mapping** 

- QRMn/DCM: 

   - The _t_ on, _t_ sw,min and _N_ valley in _**Figure 4**_ are mapped from the filtered feedback voltage _V_ FB,filtered. 

   - In QRMn, to switch on the MOSFET at the _N_ valley of the drain voltage, the system-dependent QRMn switching period tsw,QRMn has to be more than _t_ sw,min. If the drain voltage valley of _N_ valley happens before _t_ sw,min is reached, the controller operates in DCM and the DCM switching period tsw,DCM follows _t_ sw,min. 

For a smoother transition when the _N_ valley changes, the device can compensate the _t_ on curve using _c_ valley,comp parameter. To stabilize the _N_ valley in steady state operation, a hysteresis on _N_ valley change is applied, and the _N_ valley is only updated once in each _**Operation cycle**_ . If the _N_ valley change is more than a _N_ valley,fast parameter, the controller can speed up the _N_ valley update for a better dynamic load response. 

_Note: Either t_ on _or t_ sw,min _, or both can be modulated over every_ _**Operation cycle** to achieve either the_ _**Enhanced power quality** for AC input, or the_ _**Switching frequency dithering for constant DC input voltage** ._ 

- ABM: 

   - _t_ on and _n_ burst are mapped from _V_ FB,filtered taken at the last pulse of previous burst cycle. 

   - Typically, the controller has a burst interval which is approximately the configured 1/ _f_ burst and enters the sleep mode for power saving after completing the last pulse of each burst cycle, as shown in _**Figure 5**_ . 

However, if the UART reporting feature is enabled with _EN_ UART,reporting parameter, either a longer than typical burst interval or a delayed sleep mode entry, or both can occur occasionally, for instance when the UART signal transmission can not be completed within the typical burst interval or before the last pulse of a burst cycle. 

Data Sheet 

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## **3 Functional description** 

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**----- Start of picture text -----**<br>
VFB VFB,filtered ton = α<br>nABM = 4 ton = β   ton = β<br>nABM = 3 nABM = 3<br>wake wake wake<br>sleep sleep sleep<br>up up up<br>t<br>T≈1/fburst T≈1/fburst<br>VGD<br>1/fsw,min 1/fsw,min 1/fsw,min<br>ton = α  ton = β<br>nABM = 4 nABM = 3<br>t<br>Approx. Approx. Approx.<br>nwakeup nwakeup nwakeup<br>x 19 µs x 19 µs x 19 µs<br>Figure 5 Typical ABM switching waveforms<br>**----- End of picture text -----**<br>


_Note: The ABM switching pulse frequency typically follows the minimum switching frequency parameter f_ sw,min _(26.9 kHz typ.) but it can be modulated over every_ _**Operation cycle** to achieve the_ _**Switching frequency dithering for constant DC input voltage** ._ 

## **Regualted mode** _**CS**_ **pin maximum voltage and minimum valley number limits** 

In regulated mode, the minimum valley number limit _N_ valley,min _(V_ in _)_ and _CS_ pin maximum voltage limit _V_ OCP1 _(V_ in _)_ are both adaptive based on the estimated input voltage _V_ in, as shown in _**Figure 6**_ , to prevent excessive output power at higher input voltage. The effective on-time is lower than the mapped _t_ on in _**Figure 4**_ , if the conducting MOSFET current rises to a level of _V_ OCP1 _(V_ in _)_ after the _CS_ leading edge blanking time _t_ CS,LEB (480 ns typ.). 

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**----- Start of picture text -----**<br>
VOCP1(Vin) Nvalley,min(Vin)<br>VOCP1,at,V,in,low<br>VOCP1,at,V,in,high<br>Nvalley,min,at,V,in,high<br>1<br>Vin,low Vin,high Vin<br>**----- End of picture text -----**<br>


**Figure 6 Regulated mode CS pin maximum voltage and minimum valley number limits adaptation based on estimated input voltage Vin** 

_Note: V_ OCP1 _(V_ in _) and N_ valley,min _(V_ in _) are adapted once in every_ _**Operation cycle** ._ 

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## **3 Functional description** 

## **On-time limits** 

The on-time limits in _**Figure 4**_ are adaptive based on the estimated input voltage _V_ in. 

- QRMn/DCM: 

   - To sense the output over-voltage level of _V_ outOV parameter, the device calculates a _t_ on,min,V,out,sense _(V_ in _)_ variable, which is the estimated minimum on-time to achieve the desired minimum transformer demagnetization time of _t_ min,demag parameter, at the peak of the estimated input voltage _V_ in,peak. The minimum on-time limit _t_ on,min _(V_ in _)_ is based on the _t_ on,min parameter or the _t_ on,min,V,out,sense _(V_ in _)_ variable, whichever is higher, as shown in _**Figure 7**_ . 

For _V_ in between the lowest operational input voltage parameter _V_ in,low and the input over-voltage protection level parameter _V_ inOV, the maximum on-time limit _t_ on,max _(V_ in _)_ is scaled to compensate the influence of input voltage on feedback gain. 

For _V_ in from _V_ in,low to the input under-voltage protection level parameter _V_ in,UV, _t_ on,max _(V_ in _)_ can be linearly reduced from _t_ on,max,at,V,in,low parameter to _t_ on,max,at, Vin,UV parameter, to limit the maximum power during brown-out. 

- ABM: 

For _V_ in decreased from _V_ in,high, the ABM minimum on-time limit _t_ on,min,ABM _(V_ in _)_ is increased from _t_ on,min,ABM parameter, to reduce the burst pulse number for a lower standby power at lower input voltage. 

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**----- Start of picture text -----**<br>
ton,max(Vin) ton,min(Vin)<br>ton,min,V,out,sense(Vin)<br>ton,min,ABM(Vin)<br>ton,max,at,V,in,low<br>Nvalley =1<br>ton,max,at,V,in,UV<br>Nvalley = Nvalley,min,at,V,in,high<br>(E.g. Using 4 as example)<br>ton,min<br>ton,min,ABM<br>VinUV Vin,low Vin,high VinOV Vin<br>**----- End of picture text -----**<br>


## **Figure 7 On-time limits adaptation based on estimated input voltage Vin** 

_Note: t_ on,min _(V_ in _), t_ on,max _(V_ in _), and t_ on,min,ABM _(V_ in _) are adapted once in every_ _**Operation cycle** ._ 

## **Feedback voltage maximum limit** 

When the regulated mode is entered, the filtered feedback voltage maximum limit _V_ FB,filtered,max is ramped up from _V_ FB,limit,start (1.2 V typ.) to _V_ REF (2.428 V typ.), with an incremental voltage step of _V_ FB,limit,step parameter after every _t_ FB,limit,step. 

As shown in _**Figure 8**_ , when _V_ FB,filtered is higher than _V_ FB,filtered,max initially in the regulated mode entering, the feedback voltage mapping is based on _V_ FB,filtered,max ramp, to prevent the excessive output voltage overshoot during output rise. When _V_ FB,filtered gets lower than _V_ FB,filtered,max, the feedback voltage mapping then follows _V_ FB,filtered, for the steady-state output regulation. 

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## **3 Functional description** 

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Voltage<br>Regulated mode entering<br>VREF Filtered feedback voltage max. limit<br>(2.428V typ.) VFB,filtered,max<br>Filtered feedback voltage<br>VFB,filtered<br>VFB,limit,start VFB,limit,step<br>(1.2V typ.) Note:  tFB,limit,step is either the<br>tFB,limit,step synchronized AC input half<br>sine wave period, or 9.823 ms<br>time<br>Feedback voltage mapping<br>based on VFB,filtered,max<br>(when VFB,filtered > VFB,filtered,max)<br>**----- End of picture text -----**<br>


## **Figure 8 Feedback voltage maximum limit** 

## **3.3 Operation cycle** 

The period of every XDPL8219 operation cycle is 9.823 ms by default. When the _HV_ pin _**line synchronization**_ is enabled and properly in place with an AC input, it is approximately the half-sine-wave period of an AC input, else it follows the default value. 

## **3.4 Line synchronization** 

Depending on the operation conditions, the XDPL8219 enables the line synchronization which senses the _HV_ pin signal, to detect the input voltage type and the double-line-frequency of an AC input voltage. 

If the _HV_ pin line synchronization detected input voltage type is AC, the _HV_ pin line synchronization is enabled in _**QRMn**_ and _**DCM**_ , and disabled in _**ABM**_ . It takes some time for the initially enabled _HV_ pin line synchronization to be properly in place with an AC input. When the _HV_ pin line synchronization is properly in place with an AC input, the double-line-frequency or the half-sine-wave period detected by the controller is synchronized with the AC input, and the _HV_ pin signal sensing duty cycle is lowered to reduce the _HV_ pin series resistor power consumption. 

If the _HV_ pin line synchronization detected input voltage type is a constant DC, the _HV_ pin line synchronization is disabled, and can only be re-enabled in QRMn and DCM, when an input voltage type change to AC is detected from the _**Input voltage estimation**_ via _ZCD_ pin and _CS_ pin signals. 

If the _**UART reporting**_ feature is enabled and ABM is entered immediately upon start-up, the _HV_ pin line synchronization is enabled initially for a short period of time to detect the initial line frequency. 

_**Attention** :_ _**To ensure the HV pin line synchronization can be established and properly in place with an AC input, the AC input should be a stable sinusoidal waveform with frequency between 45 Hz and 66 Hz. Additionally, the rectified AC input connected to the HV pin via external resistor also should not have excessive noise.**_ 

## **3.5 Enhanced power quality** 

In _**QRMn**_ and _**DCM**_ , the _HV_ pin synchronized double-line-frequency of the AC input is used as the digital filter notch frequency, to suppress the double-line-frequency sine-wave component of the feedback voltage, to achieve good _**PFC**_ and _**THD**_ correction. In QRMn and DCM, by synchronizing the regulated mode _**Operation cycle**_ with the AC input half-sine-wave period, the controller can also modulate the switching parameters depending on the phase angle, to enhance the PFC and THD correction. 

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## **3 Functional description** 

## **Enhanced THD correction** 

By enabling the _EN_ ETHDC parameter, the controller compensates the input current distortion caused by the changing QRMn duty cycle over the AC input half-sine-wave period. 

## **Enhanced power factor correction** 

For better PFC, the patented enhanced PFC (EPFC) feature can be enabled by configuring _C_ EMI parameter value above zero and fine-tuning the value, to compensate the input current displacement effect which is mainly caused by the DC link filter capacitor _C_ DC,filter and the line filter. 

## **3.6 Switching frequency dithering for constant DC input voltage** 

To lower the _**EMI**_ while operating with a constant DC input voltage, the switching frequency dithering feature can be enabled by configuring _c_ dither parameter above zero. Based on the modulation gain parameter _c_ dither, _t_ on and _t_ sw,min are modulated in _**QRMn**_ and _**DCM**_ , while _t_ sw,min is modulated in _**ABM**_ , to dither the switching frequency. 

## **3.7 Configurable gate voltage rising slope at GD pin** 

The typical gate drive peak voltage _V_ GD,pk is 12 V. To achieve a good balance of switching loss and _**EMI**_ , the gate voltage rising slope which determines the MOSFET switching on speed can be controlled, by configuring the gate driver peak source current parameter _I_ GD,pk. 

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VGD<br>Dfastoff<br>VGD,pk<br>IGD,pk GD RG Rslowon<br>=118mA<br>Not needed<br>IGD,pk RCS<br>= 30mA<br>t<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
Figure 9 Configurable gate voltage rising slope and component saving<br>**----- End of picture text -----**<br>


## **3.8 UART reporting** 

XDPL8219 _**UART**_ reporting can be enabled to transmit data packet which contains the following data, at specific timings and conditions: 

- Last estimated input voltage rms value _V_ in, based on the _**Input voltage estimation**_ 

- Last detected line frequency or input voltage type, based on the _HV_ pin _**Line synchronization**_ 

- Last measured _**IC**_ junction temperature, based on its internal sensor 

- Indication of an input voltage loss, if the consecutive number of too low _ZCD_ pin _-I_ IV sampling value has exceeded the limit 

- Error code of the last triggered protection before auto-restart 

The UART reporting is based on the uni-directional UART communication with a fixed baud rate of 9600 bps. 

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## **3 Functional description** 

## **3.9 Input voltage and output voltage estimation** 

XDPL8219 estimates the input voltage and output voltage based on the _ZCD_ pin switching signal. As shown in the waveform example in _**Figure 10**_ , the transformer primary auxiliary winding voltage _V_ AUX contains information on the reflected input voltage and reflected output voltage, which can be measured at _ZCD_ pin using a resistor divider. 

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**----- Start of picture text -----**<br>
VAUX<br>Tosc Tosc<br>4 4<br>Reflected output<br>voltage sampling<br>1 [st]  Zero crossing detection<br>0 V<br>Reflected input  1 [st]  Valley switching<br>voltage sampling<br>Ip Is<br>time<br>Np Ns<br>tCS,sample tZCD,sample<br>Itransformer<br>tsw,QR1<br>Ip,pk<br>VAUX Na<br>Ip Ip<br>Is<br>time<br>tdemag<br>VGD<br>time<br>**----- End of picture text -----**<br>


**Figure 10 Flyback switching waveform example in QRM1** 

## **3.9.1 Output voltage estimation** 

The output voltage is estimated by sensing the reflected output voltage signal from the transformer primary auxiliary winding voltage _V_ AUX, when the MOSFET is switched off and near the end of transformer demagnetization. A resistor divider with _R_ ZCD,1 and _R_ ZCD,2 adapts the voltage at _ZCD_ pin based on its operational range, while a _ZCD_ pin filter capacitor CZCD is needed for noise filtering, as shown in _**Figure 11**_ . 

Based on the sampled _ZCD_ pin voltage _V_ ZCD,SH at the timing of tZCD,sample shown in _**Figure 10**_ , which is approximately a quarter of oscillation period ( _T_ osc/4) before the 1[st] zero crossing of _V_ AUX, a ratio of the reflected output voltage signal from _V_ AUX is sensed. In _**QRMn**_ and _**DCM**_ ,the typical interval of each _V_ ZCD,SH sampling is 

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## **3 Functional description** 

approximately 1/64 of the regulated mode _**Operation cycle**_ , while the oscillation period _T_ osc is measured once during startup and updated every 7[th] regulated mode _**Operation cycle**_ . 

- _Note: As V_ AUX _zero crossing can only be detected by the_ _**IC** via ZCD pin upon its internal analog delay plus external delay caused by C_ ZCD _, t_ ZCDPD _parameter fine-tuning is needed to compensate such delays, to have the proper timing of t_ ZCD,sample _for output voltage estimation._ 

- _**Attention** :_ _**Please note that the transformer demagnetization time t**_ **demag** _**has to be at least 2.0**_ **μ** _**s at the peak of input voltage, to ensure that the reflected output voltage can be sensed properly at the ZCD pin.**_ 

The estimated output voltage _V_ out is based on: 

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## **Equation 1** 

Where _N_ s is the transformer secondary main winding turns, _N_ a is the transformer primary auxiliary winding turns and _V_ d is the secondary main output diode forward voltage (assumed by the controller as 0.7 V). 

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Vd<br>Na Ns<br>RZCD,1 Cout Vout<br>ZCD VAUX<br>CZCD VZCD,SH RZCD,2<br>**----- End of picture text -----**<br>


## **Figure 11 Output voltage estimation based on** _**V**_ **ZCD,SH** 

The estimated output voltage _V_ out is used for output voltage protections, so it is important to ensure that IC parameters _R_ ZCD,1, _R_ ZCD,2, _N_ s and _N_ a are configured as per the actual system hardware dimensioning. 

## **3.9.2 Input voltage estimation** 

The input voltage is estimated by sensing the reflected input voltage signal from the transformer primary auxiliary winding voltage VAUX, when the MOSFET is switched on. As the reflected input voltage signal is a negative voltage which cannot be sensed directly, the voltage at _ZCD_ pin is clamped to a negative voltage of _V_ INPCLN. A resistor divider with _R_ ZCD,1 and _R_ ZCD,2 adapts _-I_ IV which is the clamping current flowing out of _ZCD_ pin, based on its operational range, while a _ZCD_ pin filter capacitor CZCD is needed for noise filtering, as shown in _**Figure 12**_ . 

Based on the sampled clamping current _-I_ IV at the timing of _t_ CS,sample shown in _**Figure 10**_ , which is at the end of on-time, the reflected input voltage signal from VAUX is sensed. The typical interval of each _-I_ IV sample is approximately 1/64 of the regulated mode _**Operation cycle**_ , when the XDPL8219 is awake and gate driver output is switching. 

The estimated peak input voltage _V_ in,peak over every regulated mode _**Operation cycle**_ is based on: 

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## **Equation 2** 

Where _N_ p is the primary main winding turns, _N_ a is the primary auxiliary winding turns, _R_ CS is the _CS_ pin shunt resistor value, _V_ CS,peak is the peak _CS_ pin voltage, and _R_ in is the fine-tuning parameter for input voltage sensing accuracy improvement by compensating the switching frequency voltage ripple on CDC,filter. 

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## **3 Functional description** 

Regardless of the input voltage type is AC or a constant DC, the estimated input voltage _V_ in in rms value is assumed by the controller as 0.707 of _V_ in,peak based on a filtered value over a few regulated mode operation cycles. The update rate of _V_ in is once per regulated mode operation cycle. 

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Na Np VDC,filter<br>V in,peak<br>V in<br>ZCD IIV RZCD,1 VDC,filter CDC,filter<br>VAUX<br>CZCD RZCD,2 RG GD<br>VINPCLN<br>RCS VCS<br>**----- End of picture text -----**<br>


## **Figure 12 Input voltage estimation based on** _**-I**_ **IV** 

The estimated input voltage _V_ in is used for input voltage protections, so it is important to ensure that _**IC**_ parameters _R_ ZCD,1, _R_ ZCD,2, _N_ p, _N_ a and _R_ CS are configured as per the actual system hardware dimensioning. 

## **3.10 Protection features** 

Protections ensure the operation of the controller under restricted conditions. The protection monitoring signal(s) sampling rate, protection triggering condition(s) and protection reaction are described in this section. 

_**Attention** :_ _**The sampled protection monitoring signal accuracy is subjective to the digital quantization, tolerances of components (including IC) and estimations with indirect sensing (e.g. input and output voltage estimations based on ZCD, CS pin signals), while the protection level triggering accuracy is subjective to the sampled signal accuracy, sampling delay, indirect sensing delay (e.g. reflected output voltage signal cannot be sensed by ZCD pin near AC input phase angle of 0° and 180°) and blanking time.**_ 

## **3.10.1 Primary MOSFET overcurrent protection** 

_V_ OCP2 denotes the _CS_ pin voltage level 2 for primary MOSFET overcurrent protection. Under the single fault condition of shorted primary main winding, the primary MOSFET overcurrent protection is triggered when the _CS_ pin voltage exceeds _V_ OCP2 for longer than a blanking time based on _t_ CSOCP2 parameter. The level of _V_ OCP2 is automatically selected based on _**Table 2**_ . 

|**VOCP1,at,V,in,low (V)**|**VOCP2 (V)**|
|---|---|
|0.34 to 0.36|0.6|
|0.37 to 0.54|0.8|
|0.55 to 0.72|1.2|
|0.73 to 1.08|1.6|



The reaction of primary MOSFET overcurrent protection is fixed as auto-restart. 

## **3.10.2 Output undervoltage protection** 

In case of a short or an overload on the output, the output voltage may drop to a low level. The output undervoltage protection can be triggered, if the condition is met by monitoring the estimated output voltage _V_ out based on the _ZCD_ pin switching signal (see _**Output voltage estimation**_ for details). 

_EN_ UVP,Vout parameter refers to the enable switch for the regulated mode output undervoltage protection. In regulated mode, if _EN_ UVP,Vout parameter is enabled and the estimated output voltage _V_ out is lower than _V_ outUV 

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## **3 Functional description** 

parameter for longer than a blanking time of _t_ VoutUV,blank parameter, the regulated mode output undervoltage protection is triggered. The reaction of regulated mode output undervoltage protection is configurable to either auto-restart or latch mode based on _Reaction_ UVP,Vout parameter. 

_**Attention** :_ _**Regulated mode output undervoltage protection is not available while the controller operates in ABM.**_ 

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Vout<br>Output load current<br>too high causing<br>power limit and<br>Output setpoint<br>Start of regulation  Vout drop below<br>according to feedback  set-point Output under-<br>voltage mapping voltage protection<br>Vout,start triggered after<br>VoutUV tVoutUV,blank<br>Turn-on<br>time<br>Startup Regulated Mode Regulated Mode<br>phase (Vout > VoutUV) (Vout < VoutUV for tVoutUV,blank)<br>**----- End of picture text -----**<br>


## **Figure 13 Regulated mode output undervoltage protection triggering waveform example** 

In startup phase, if the estimated output voltage _V_ out is lower than the _V_ out,start parameter level after a timeout period of _t_ start,max parameter, the startup output undervoltage protection is triggered. _t_ start,max parameter refers to the maximum allowable duration of the startup phase, which consists of soft-start phase and output charging phase. It can be indirectly configured with _VCC_ capacitance parameter _C_ VCC. 

The reaction of startup output undervoltage protection is fixed as auto-restart. 

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**----- Start of picture text -----**<br>
Normal startup Output short startup<br>Voltage Voltage<br>tstart,max tstart,max<br>tout,charge<br>Output setpoint Output setpoint<br>Vout,start Vout Vout,start<br>VVCCON VVCCON Startup output undervoltage<br>(20.5V typ.) VVCC (20.5V typ.) VVCC protection triggered<br>(Vout < Vout,start at tstart,max)<br>VUVOFF VUVOFF<br>(6V typ.) time (6V typ.) V out time<br>tVCCON,charge tVCC,holdup tVCCON,charge tVCC,holdup<br>**----- End of picture text -----**<br>


**Figure 14 Normal startup and startup output undervoltage (short) protection waveform example** 

## **3.10.3 Output overvoltage protection** 

In case of _FB_ pin open, the output voltage may rise to a high level. The output overvoltage protection can be triggered, if the condition is met by monitoring the estimated output voltage _V_ out based on the _ZCD_ pin switching signal (see _**Output voltage estimation**_ for details). 

If the estimated output voltage _V_ out is higher than _V_ outOV for longer than a blanking time, the output overvoltage protection is triggered. The output overvoltage protection blanking time is typically a quarter of the _**Operation cycle**_ . The reaction of the output overvoltage protection is configurable to auto-restart or latch-mode based on _Reaction_ OVP,Vout parameter. 

_**Attention** :_ _**Output overvoltage protection is not available while the controller operates in ABM.**_ 

_**Attention** :_ _**It is mandatory to ensure that V**_ **outOV** _**is configured well below the actual output capacitor voltage rating V**_ **out,cap,rating** _**,while the V**_ **out,cap,rating** _**is not exceeded in actual testing with all the necessary test conditions. The protection level triggering accuracy is subjective to the sampled**_ 

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## **3 Functional description** 

_**signal accuracy, sampling delay, indirect sensing delay (e.g. reflected output voltage signal cannot be sensed by ZCD pin near AC input phase angle of 0° and 180°) and blanking time.**_ 

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Vout<br>VoutOV protection triggered<br>Vout,cap,rating after blanking time<br>VoutOV ReactionOVP,Vout = Auto-restart<br>Output setpoint FB pin Open ReactionOVP,Vout = Latch-Mode<br>Vout,start<br>Start of regulation<br>according to<br>feedback voltage<br>mapping<br>Turn-on<br>time<br>Startup Regulated Mode Auto-restart time<br>phase<br>(based on tauto,restart)<br>**----- End of picture text -----**<br>


**Figure 15** 

**Output overvoltage protection** 

## **3.10.4 Transformer demagnetization time shortage protection** 

In case of insufficient transformer demagnetization time, the reflected output voltage signal cannot be properly sensed via the _ZCD_ pin. If such condition presents for longer than 50% of the regulated mode operation cycle, the protection will be triggered. The reaction of this protection is fixed as auto-restart. 

## _**Attention** :_ _**Transformer demagnetization time shortage protection is not available while the controller operates in ABM.**_ 

## **3.10.5 Minimum input voltage startup check and input undervoltage protection** 

By monitoring the estimated input voltage _V_ in mainly based on the _ZCD_ pin switching signal (see _**Input voltage estimation**_ for details), the minimum input voltage startup check can be performed, and the input undervoltage protection can be triggered if the condition is met. 

_EN_ UVP,In parameter refers to the enable switch for the minimum input voltage startup check (based on _V_ in,start,min) and input undervoltage protection (based on _V_ inUV). 

_Note: V_ in,start,min _parameter refers to the minimum input voltage level for startup, while V_ inUV _parameter refers to the input undervoltage protection level._ 

During pre-startup check, if _EN_ UVP,In parameter is enabled and the estimated input voltage _V_ in is lower than _V_ in,start,min, the startup phase will not be entered and the protection reaction of auto-restart will be performed. Upon startup and in the regulated mode, the input undervoltage protection triggering condition depends on the operating mode: 

- _**QRMn**_ / _**DCM**_ : 

   - If _EN_ UVP,In parameter is enabled and the estimated input voltage _V_ in is lower than _V_ inUV for longer than a blanking time _t_ VinUV,blank, the input undervoltage protection will be triggered. _t_ VinUV,blank is typically 10 times of the regulated mode _**Operation cycle**_ . 

- _**ABM**_ : 

   - If _EN_ UVP,In parameter is enabled, _EN_ VIN,ABM parameter is enabled and the estimated input voltage _V_ in is lower than _V_ inUV for longer than a blanking time, the input undervoltage protection will be triggered. The blanking time of the input undervoltage protection may deviate from the blanking time in other modes due to a integer rounding to a number of bursts. 

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## **3 Functional description** 

_Note: EN_ VIN,ABM _refers to the enable switch for input voltage protections in Active Burst Mode (ABM)._ 

The reaction of the input undervoltage protection is fixed as auto-restart. 

## **3.10.6 Maximum input voltage startup check and input overvoltage protection** 

By monitoring the estimated input voltage _V_ in mainly based on the _ZCD_ pin switching signal (see _**Input voltage estimation**_ for details), the maximum input voltage startup check can be performed, and the input overvoltage protection can be triggered if the condition is met. 

_EN_ OVP,In parameter refers to the enable switch for the maximum input voltage startup check (based on _V_ in,start,max) and input overvoltage protection (based on _V_ inOV). 

_Note: V_ in,start,max _parameter refers to the maximum input voltage level for startup, while V_ inOV _parameter refers to the input overvoltage protection level._ 

During pre-startup check, if _EN_ OVP,In parameter is enabled and the estimated input voltage _V_ in is higher than _V_ in,start,max, the startup phase will not be entered and the protection reaction of auto-restart will be performed. Upon startup and in the regulated mode, the input overvoltage protection triggering condition depends on the operating mode: 

- _**QRMn**_ / _**DCM**_ : 

   - If _EN_ OVP,In parameter is enabled and the estimated input voltage _V_ in is higher than _V_ inOV for longer than a blanking time _t_ VinOV,blank, the input overvoltage protection will be triggered. _t_ VinOV,blank is typically 1 regulated mode _**Operation cycle**_ . 

- _**ABM**_ : 

   - If _EN_ OVP,In parameter is enabled, _EN_ VIN,ABM parameter is enabled and the estimated input voltage _V_ in is higher than _V_ inOV for longer than a blanking time, the input overvoltage protection will be triggered. The blanking time of the input overvoltage protection may deviate from the blanking time in other modes due to a integer rounding to a number of bursts. 

_Note: EN_ VIN,ABM _refers to the enable switch for input voltage protections in Active Burst Mode (ABM)_ 

The reaction of the input overvoltage protection is fixed as auto-restart. 

## **3.10.7 VCC undervoltage lockout** 

The _**Undervoltage Lockout (UVLO)**_ is implemented in the hardware. It ensures the enabling and disabling of the _**IC**_ operation based on the defined thresholds of the operating supply voltage _V_ VCC at the _VCC_ pin. 

The UVLO contains a hysteresis with the voltage thresholds _V_ VCCon for enabling the controller and _V_ UVOFF for disabling the controller. Once the mains input voltage is applied, current flows through an external resistor into the _HV_ pin via the integrated depletion cell and diode to the _VCC_ pin. The controller is enabled once _V_ VCC exceeds the _V_ VCCon threshold and _V_ VCC will then start to drop. For normal startup, _V_ VCC supply should be taken over by either external supply or the self-supply via the auxiliary winding before _V_ VCC drops to _V_ UVOFF. 

## **3.10.8 VCC undervoltage protection** 

The _VCC_ voltage sampling interval is approximately 1/64 of the regulated mode _**Operation cycle**_ , when the XDPL8219 is awake and the gate driver output is switching. In regulated mode, if _EN_ VCC,UVP parameter is enabled and the filtered value out of the _VCC_ sampling is lower than the _VCC_ undervoltage protection level _V_ VCC,min for longer than a blanking time, the _VCC_ undervoltage protection will be triggered. The _VCC_ undervoltage protection reaction is fixed as auto-restart. 

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## **3 Functional description** 

## **3.10.9 VCC overvoltage protection** 

The _VCC_ voltage sampling interval is approximately 1/64 of the _**Operation cycle**_ , when the XDPL8219 is awake and the gate driver output is switching. If the filtered value out of the _VCC_ voltage sampling data is higher than the _VCC_ overvoltage protection level _V_ VCC,max, the _VCC_ overvoltage protection will be triggered. The _VCC_ overvoltage protection reaction is configurable to auto-restart or latch-mode based on _Reaction_ VCC,OVP parameter. 

## **3.10.10 IC overtemperature protection** 

The _**IC**_ junction temperature _T_ j is sampled 1 time every regulated mode _**Operation cycle**_ . If the sampled IC junction temperature _T_ j is higher than _T_ critical parameter, the IC overtemperature protection will be triggered. The protection reaction is fixed as auto-restart, while the maximum junction temperature for startup and restart _T_ start,max is fixed as 4°C below _T_ critical. 

If _T_ critical is configured above 119°C, the maximum switching frequency parameter _f_ sw,max cannot be configured above 186.4 kHz. If _T_ critical is 119°C or below, the maximum configurable _f_ sw,max value is 247.2 kHz. 

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**----- Start of picture text -----**<br>
Pout<br>Over-temperature<br>Protection triggered<br>TJ<br>4°C typ.<br>Tstart,max Tcritical<br>**----- End of picture text -----**<br>


## **Figure 16 IC overtemperature protection** 

## **3.10.11 Other protections** 

- A hardware weak pull-up protects against an open _CS_ pin. The reaction of this protection reaction is auto-restart. 

- A firmware watchdog triggers a protection if the ADC hardware cannot provide all necessary information within a defined time period. This may occur if timing requirements for the ADC are exceeded. The reaction of this protection is fast auto-restart. 

- A hardware watchdog checks correct execution of firmware. A protection is triggered in the event that the firmware does not service the watchdog within a defined period. The reaction of this protection is auto-restart. 

- A hardware _**Random Access Memory**_ parity check triggers a protection if a bit in the memory changes unintentionally. The reaction of this protection is auto-restart. 

- A firmware _**Cyclic Redundancy Check**_ at each startup verifies the integrity of firmware and parameters. The reaction of this protection is stop mode. 

- A firmware task execution watchdog triggers a protection if the firmware tasks are not executed as expected. The reaction of this protection is auto-restart. 

- A protection is triggered if the configurable parameter values are empty at startup. The reaction of this protection is stop mode. 

- A protection is triggered if no reflected input voltage signal sensed from the _ZCD_ pin at startup. The reaction of this protection is stop mode. 

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## **3 Functional description** 

## **3.10.12** 

## **Protection reactions** 

The sequence of a protection reaction (not including hardware restart reaction) is as follows: 

**1.** Upon triggering a protection, the gate driver is disabled within a maximum time, which is 1/512 of the regulated mode operation cycle. 

**2.** The reaction depends on the triggered protection: 

   - In case of latch mode, the application will enter latch mode at this time. No further sequence is done until _VCC_ voltage drops below _V_ UVOFF. 

   - In case of auto-restart reaction, the controller will enter power saving mode PSMD2 with the auto-restart time based on _t_ auto,restart. 

   - In case of fast auto-restart reaction, the controller will enter power saving mode PSMD2 with the fast auto-restart time of 0.4 s typically. 

   - _Note: For latch mode, auto-restart and fast auto-restart reactions, the internal HV startup cell is automatically enabled and disabled during this sequence, in order to keep the VCC voltage between the V_ UVLO _and V_ OVLO _thresholds._ 

_Note: For stop mode, if there is no external voltage supply for the VCC, the VCC voltage will drain to V_ UVOFF _and a hardware restart will be performed._ 

**3.** After the (fast) auto-restart time is expired, the controller executes a single discharge pulse of duration _t_ pw. This pulse partially discharges the capacitance after the bridge rectifier to improve accuracy of the next pre-startup input voltage check. 

**4.** Any auto restart may include a new _VCC_ charging cycle. The recharging time of _VCC_ via _HV_ pin current depends on the input voltage level and _VCC_ level at the time when the (fast) auto-restart time is expired. 

**5.** The power stage will enable its gate driver for pre-startup check. If the conditions for pre-startup check are within limits, the startup phase is entered and followed by the regulated mode. During this time, if any protection is triggered, the sequence of a protection reaction (not including hardware restart reaction) starts again from step number 1 above. 

## **3.11 Debug mode** 

The _Debug_ Mode parameter can be enabled to enter stop mode reaction upon the protection triggering (except for _VCC_ undervoltage lockout), to read out the error code of the protection. For example in _**Figure 17**_ , the error code readout in the _**GUI**_ shows a number of 0040H (in red color), which indicates that the input undervoltage protection has been triggered. 

_Note: Debug_ Mode _parameter should only be enabled for debugging purpose. For the final application, it has to be disabled._ 

**Figure 17** 

**Error status code readout for debugging** 

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## **4 List of Parameters** 

## **4 List of Parameters** 

This list provides information about the configurable and fixed parameters. 

This document uses symbols to ease the readability of formulas. As some tools do not support this format, the symbols are translated into plain text using underscores. For example, the parameter _f_ sw,max translates to f_sw_max. 

All parameter values are typical settings. The accuracy might vary due to digital quantization and tolerances. 

_Note: By default, the configurable parameters of a new XDPL8219 chip from Infineon are empty, so it is necessary to configure them digitally via UART pin before any application testing._ 

## **List of configurable parameters** 

|**Table 3**<br>**Configurable parameters for hardware configuration**|**Table 3**<br>**Configurable parameters for hardware configuration**|**Table 3**<br>**Configurable parameters for hardware configuration**|**Table 3**<br>**Configurable parameters for hardware configuration**|**Table 3**<br>**Configurable parameters for hardware configuration**|
|---|---|---|---|---|
|**Symbol**|**Basic description**|**Example**|**Minimum**<br>**value**|**Maximum**<br>**value**|
|_N_p|Transformer primary main winding turns|32|1|300|
|_N_s|Transformer secondary main winding turns|10|1|300|
|_N_a|Transformer primary auxiliary winding turns|3|1|300|
|_L_p|Transformer nominal primary main winding<br>inductance|0.544 mH|Refer GUI|3 mH|
|_R_CS|Current sense resistor value|0.2 Ω|0.1 Ω|3 Ω|
|_R_ZCD,1|_ZCD_series resistor value|27 kΩ|Refer GUI|Refer GUI|
|_R_ZCD,2|_ZCD_shunt resistor value|3.9 kΩ|Refer GUI|Refer GUI|
|_C_VCC|_VCC_capacitor value|22 µF|21.94 µF|100 µF|
|_V_out,cap,rating|Main output capacitor voltage rating|80 V|10 V|450 V|
|_R_HV|_HV_series resistor value|52 kΩ|Refer GUI|255 kΩ|
|_I_GD,pk|Gate driver peak source current|30 mA|30 mA|108 mA|
||||||
|**Table 4**<br>**Configurable parameters for startup**|||||
|**Symbol**|**Basic description**|**Example**|**Minimum**<br>**value**|**Maximum**<br>**value**|
|_n_ss|Number of sof start steps|3|1|Refer GUI|
|_V_out,start|Output charging phase output voltage set-point|33 V|Refer GUI|_V_outOV|
|_V_start,OCP1|Output charging phase_CS_pin maximum voltage<br>limit|0.52 V|Refer GUI|_V_OCP1,at,V,in,low|
|_V_OCP1,init|Initial_CS_pin maximum voltage limit for the input<br>voltage measurement pulse before startup|0.3 V|Refer GUI|_V_start,OCP1|
||||||
|**Table 5**<br>**Configurable parameters for protections**|||||
|**Symbol**|**Basic description**|**Example**|**Minimum**<br>**value**|**Maximum**<br>**value**|
|_t_auto,restart|Auto-restart time|1.2 s|0.4 s|4 s|
|_V_OCP1,at,V,in,low|Regulated mode_CS_pin maximum voltage limit at<br>lowest operational input voltage (_V_in,low)|0.52 V|Refer GUI|1.08 V|



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## **4 List of Parameters** 

|**Table 5**<br>**Configurable parameters for protections (continued)**|**Table 5**<br>**Configurable parameters for protections (continued)**|**Table 5**<br>**Configurable parameters for protections (continued)**|**Table 5**<br>**Configurable parameters for protections (continued)**|**Table 5**<br>**Configurable parameters for protections (continued)**|
|---|---|---|---|---|
|**Symbol**|**Basic description**|**Example**|**Minimum**<br>**value**|**Maximum**<br>**value**|
|_V_OCP1,at,V,in,high|Regulated mode_CS_pin maximum voltage limit at<br>highest operational input voltage (_V_in,high)|0.40 V|Refer GUI|_V_OCP1,at,V,in,low|
|_V_in,low|Lowest operational input voltage (rms in case of<br>AC input)|82 V|_V_inUV|_V_in,high|
|_V_in,high|Highest operational input voltage (rms in case of<br>AC input)|326 V|_V_in,low|_V_inOV|
|_t_CSOCP2|MOSFET overcurrent protection blanking time|240 ns|100 ns|Refer GUI|
|_Reaction_OVP,Vou<br>t|Output overvoltage protection reaction|Auto-<br>Restart|Auto-Restart|Latch-Mode|
|_V_outOV|Output overvoltage protection threshold|65 V|_V_out,start|Refer GUI|
|_EN_UVP,Vout|Enable switch for regulated mode output<br>undervoltage protection|Enabled|Enabled|Disabled|
|_Reaction_UVP,Vou<br>t|Regulated mode output undervoltage protection<br>reaction|Auto-<br>Restart|Auto-Restart|Latch-Mode|
|_V_outUV|Regulated mode output undervoltage protection<br>threshold|33 V|Refer GUI|Refer GUI|
|_t_VoutUV,blank|Blanking time for regulated mode output<br>undervoltage protection|500 ms|5 ms|1000 ms|
|_EN_OVP,In|Enable switch for maximum input voltage startup<br>check and input overvoltage protection|Enabled|Enabled|Disabled|
|_EN_UVP,In|Enable switch for minimum input voltage startup<br>check and input undervoltage protection|Enabled|Enabled|Disabled|
|_EN_VIN,ABM|Enable switch for**_ABM_**input voltage protections|Enabled|Enabled|Disabled|
|_V_inOV|Input overvoltage protection threshold (rms in<br>case of AC input)|350 V|_V_in,start,max|Refer GUI|
|_V_in,start,max|Maximum input voltage for startup (rms in case of<br>AC input)|325 V|_V_in,start,min|_V_inOV|
|_V_in,start,min|Minimum input voltage at startup (rms in case of<br>AC input)|82 V|_V_inUV|_V_in,start,max|
|_V_inUV|Input undervoltage protection threshold (rms in<br>case of AC input)|70 V|Refer GUI|_V_in,start,min|
|_t_on,max,at,V,in,UV|Maximum on-time at input undervoltage<br>protection threshold|13 µs|Refer GUI|_t_on,max,at,V,in,lo<br>w|
|_Reaction_VCC,OV<br>P|_VCC_overvoltage protection reaction|Latch-<br>Mode|Auto-Restart|Latch-Mode|
|_V_VCC,max|_VCC_overvoltage protection threshold|23 V|23 V|24.9 V|
|_EN_VCC,UVP|Enable switch for regulated mode_VCC_<br>undervoltage protection|Enabled|Enabled|Disabled|
|_V_VCC,min|Regulated mode_VCC_undervoltage protection<br>threshold|7.5 V|7.5 V|11 V|
|_T_critical|Temperature threshold for IC overtemperature<br>protection|119°C|Refer GUI|143°C|



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## **4 List of Parameters** 

|**Table 5**<br>**Configurable parameters for protections (continued)**|**Table 5**<br>**Configurable parameters for protections (continued)**|**Table 5**<br>**Configurable parameters for protections (continued)**|**Table 5**<br>**Configurable parameters for protections (continued)**|**Table 5**<br>**Configurable parameters for protections (continued)**|
|---|---|---|---|---|
|**Symbol**|**Basic description**|**Example**|**Minimum**<br>**value**|**Maximum**<br>**value**|
|_Debug_Mode|Enable switch for debug mode|Disabled|Enabled|Disabled|
||||||
|**Table 6**<br>**Configurable parameters for multimode**|||||
|**Symbol**|**Basic description**|**Example**|**Minimum**<br>**value**|**Maximum**<br>**value**|
|_R_FB,pull,up|_FB_pin internal pull-up resistor value|5.5 kohm|2.25 kohm|7.5 kohm|
|_N_quality|Quality factor of the notch filter|1.6|0|2.0|
|_n_notch,blank|Number of operation cycles as a timeout between<br>the line synchronization being established and the<br>notch filter output being applied as the filtered<br>feedback voltage.**_1)_**|2|1|10|
|_f_sw,max|Maximum switching frequency when_V_FB,filteredis<br>_V_FB,swor more|247.2 kHz|26.9 kHz|Refer GUI|
|_t_on,min|Minimum on-time_t_on,min_(V_in_)_value when<br>_t_on,min,V,out,sense_(V_in_)_is lower than_t_on,min|1.38 µs|Refer GUI|_t_on,max,at,V,in,lo<br>w|
|_t_min,demag|Minimum transformer demagnetizing time value<br>used for_t_on,min,V,out,sense_(V_in_)_variable calculation<br>internally|2.0 µs|2.0 µs|5.0 µs|
|_t_on,max,at,V,in,low|Maximum on-time when_V_inis_V_in,low|15 µs|Refer GUI|30 µs|
|_EN_Burst,Exit,Filter,<br>Feedback|Enable switch for ABM burst exit based on the<br>filtered feedback voltage|Enabled|Enabled|Disabled|
|_f_burst|ABM burst frequency|130 Hz|130 Hz|1000 Hz|
|_n_ABM,min|Minimum number of pulses per burst in ABM|3|3|Refer GUI|
|_t_on,min,ABM|Minimum on-time in ABM|1 µs|Refer GUI|_t_on,min|
|_t_ABM,blank|Timeout for ABM entrance|6.5 ms|0 ms|Refer GUI|
|_n_wakeup|Number of scheduler intervals between wakeup<br>and start of the burst|1|1|20|
|_N_valley,max|Maximum valley number|14|3|14|
|_N_valley,fast|Valley number diference which triggers the fast<br>valley adaptation|9|1|_N_valley,max- 1|
|_N_valley,min,at,V,in,<br>high|Minimum valley number at highest operational<br>input voltage (_V_in,high)|4|1|_N_valley,max- 1|
|_c_valley,comp|On time compensation factor for every valley<br>change|3.00|0.01|5.00|
|_V_FB,valley,1|Feedback voltage for the end of the valley<br>mapping (valley 1)|1.5 V|Refer GUI|_V_FB,max,map|
|_V_FB,max,map|_V_FB,filteredthreshold which represents the<br>maximum power transfer of the system|2.0 V|Refer GUI|2.403 V|



> 1 It is essential for the notch filter to have line synchronization in order to work properly. This timeout enables the notch filter to converge. During this timeout, a low pass filter is used as the feedback voltage filtration. 

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## **4 List of Parameters** 

|**Table 6**<br>**Configurable parameters for multimode (continued)**|**Table 6**<br>**Configurable parameters for multimode (continued)**|**Table 6**<br>**Configurable parameters for multimode (continued)**|**Table 6**<br>**Configurable parameters for multimode (continued)**|**Table 6**<br>**Configurable parameters for multimode (continued)**|
|---|---|---|---|---|
|**Symbol**|**Basic description**|**Example**|**Minimum**<br>**value**|**Maximum**<br>**value**|
|_V_FB,sw|_V_FB,filteredthreshold for the end of the maximum<br>switching frequency ramp up|2.0 V|0.8 V|2.2 V|
|_V_FB,min|_V_FB,filteredthreshold which represents the minimum<br>power transfer of the system|0.3 V|0.2 V|0.5 V|
|_V_FB,limit,step|Voltage step size of filtered feedback voltage max.<br>limit_V_FB,filtered,maxramp|800 mV|Refer GUI|Refer GUI|
||||||
|**Table 7**<br>**Configurable parameters for power factor correction**|||||
|**Symbol**|**Basic description**|**Default**|**Minimum**<br>**value**|**Maximum**<br>**value**|
|_C_EMI|Input current displacement compensation gain<br>parameter for enhanced PFC|0.16 µF|0 µF|1 µF|
|_V_EPFC,on|_V_FB,filteredthreshold for_C_EMIgain reduction towards<br>_V_FB,filtered= 0.8 V|1.0 V|0.8 V|2.403 V|
||||||
|**Table 8**<br>**Configurable parameters for UART reporting**|||||
|**Symbol**|**Basic description**|**Default**|**Minimum**<br>**value**|**Maximum**<br>**value**|
|_EN_UART,REPORTIN<br>G|Enable switch for UART reporting|Enabled|Enabled|Disabled|
|_EN_SEND,LAST,ERR<br>OR,CODE|Enable switch for error code signal transmission|Enabled|Enabled|Disabled|
|_EN_SEND,V,IN,LOSS|Enable switch for input voltage loss signal<br>transmission|Enabled|Enabled|Disabled|
|_UART_POLARITY|Idle level of the UART reporting bus|Low|Low|High|
||||||
|**Table 9**<br>**Configurable parameters for fine tuning**|||||
|**Symbol**|**Basic description**|**Default**|**Minimum**<br>**value**|**Maximum**<br>**value**|
|_t_ZCDPD|_ZCD_pin propagation delay compensation<br>parameter|370 ns|0 ns|1000 ns|
|_R_in|DC link filter capacitor voltage ripple<br>compensation parameter to improve input voltage<br>estimation accuracy|10.5 Ω|0 Ω|30 Ω|
|_EN_ETHDC|Enable switch for Enhanced THD correction|Enabled|Enabled|Disabled|
|_c_dither|Percentage of switching parameter modulation for<br>switching frequency dithering with a constant DC<br>input voltage|10%|0%|20%|
||||||
|**Table 10**<br>**Configurable parameters for user ID**|||||
|**Symbol**|**Basic description**|**Default**|**Minimum**<br>**value**|**Maximum**<br>**value**|
|_User_ID,A|User ID A|0|-|-|



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## **4 List of Parameters** 

## **List of Fixed Parameters** 

|**Table 11**<br>**Fixed parameters for hardware configuration**|**Table 11**<br>**Fixed parameters for hardware configuration**|**Table 11**<br>**Fixed parameters for hardware configuration**|**Table 11**<br>**Fixed parameters for hardware configuration**|**Table 11**<br>**Fixed parameters for hardware configuration**|
|---|---|---|---|---|
|**Symbol**|**Basic description**|**Default**|**Minimum**<br>**value**|**Maximum**<br>**value**|
|_V_|Secondary main output diode forward voltage<br>assumption for output voltage estimation|0.7 V|-|-|
|_V_GD|_GD_pin peak voltage|12 V|-|-|
||||||
|**Table 12**<br>**Fixed parameters for protections**|||||
|**Symbol**|**Basic description**|**Default**|**Minimum**<br>**value**|**Maximum**<br>**value**|
|_t_start,max|Maximum allowable duration for startup phase|967 *_C_VCC|-|-|
|_T_start,max|Maximum IC junction temperature for startup|_T_critical-<br>4°C|-|-|
||||||
|**Table 13**<br>**Fixed parameters for startup**|||||
|**Symbol**|**Basic description**|**Default**|**Minimum**<br>**value**|**Maximum**<br>**value**|
|_t_ss|Sof start time step|0.5 ms|-|-|
|_V_FB,limit,start|Start voltage for filtered feedback voltage max.<br>limit_V_FB,filtered,maxramp|1.2 V|-|-|
||||||
|**Table 14**<br>**Fixed parameters for multimode**|||||
|**Symbol**|**Basic description**|**Default**|**Minimum**<br>**value**|**Maximum**<br>**value**|
|_V_FB,ABM|_V_FB,filteredthreshold for the ABM/**_DCM_**transition|0.8 V|-|-|
|_V_FB,on|_V_FB,filteredthreshold for the start of the on-time<br>ramp up|0.8 V|-|-|
|_f_sw,min|Minimum switching frequency|26.9 kHz|-|-|
||||||
|**Table 15**<br>**Fixed parameters for power factor correction**|||||
|**Symbol**|**Basic description**|**Default**|**Minimum**<br>**value**|**Maximum**<br>**value**|
|_t_on,min,EPFC|Minimum on time for enhanced**_PFC_**modulation|_t_CS,LEB+<br>24/_f_MCLK|-|-|
|_t_on,max,EPFC|Maximum on time for enhanced PFC modulation|_t_on,max,at,V,i<br>n,low|-|-|
||||||
|**Table 16**<br>**Other fixed parameters**|||||
|**Symbol**|**Basic description**|**Default**|**Minimum**<br>**value**|**Maximum**<br>**value**|
|_t_CS,LEB|_CS_leading edge blanking time|480 ns|-|-|
|_t_ZCD,ring|_ZCD_ringing suppression|1.2 µs|-|-|
|_t_pw|Discharge pulse duration|1.5 µs|-|-|



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## **4 List of Parameters** 

|**Table 16**<br>**Other fixed parameters (continued)**|**Table 16**<br>**Other fixed parameters (continued)**|**Table 16**<br>**Other fixed parameters (continued)**|**Table 16**<br>**Other fixed parameters (continued)**|**Table 16**<br>**Other fixed parameters (continued)**|
|---|---|---|---|---|
|**Symbol**|**Basic description**|**Default**|**Minimum**<br>**value**|**Maximum**<br>**value**|
|_n_OSC,ZCD|Selection of zero-crossings for the oscillation<br>period measurement at pre-startup|Second<br>and Third<br>zero-<br>crossings|-|-|
|_T_OSC,max|Maximum limit of the measured oscillation period<br>(If exceeded at pre-startup,_T_OSC,presetis used; If<br>exceeded afer startup, the last valid measured<br>oscillation period is used)|6.6 µs|-|-|
|_T_OSC,preset|Oscillation period used by the controller if the<br>measured oscillation period at pre-startup exceeds<br>_T_OSC,max|3.3 µs|-|-|



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## **5 Electrical Characteristics and Parameters** 

## **5 Electrical Characteristics and Parameters** 

All signals are measured with respect to the ground pin, GND. The voltage levels are valid provided other ratings are not violated. 

## **5.1 Package Characteristics** 

## **Table 17** 

## **Package Characteristics** 

|**Parameter**|**Symbol**|**Limit Values**|**Limit Values**|**Unit**|**Remarks**|
|---|---|---|---|---|---|
|||**min**|**max**|||
|Thermal resistance for PG-<br>DSO-8-58|RthJA|—|178|K/W|JEDEC 1s0p for 140 mW<br>power dissipation|



## **5.2 Absolute Maximum Ratings** 

_**Attention** :_ _**Stresses above the values listed below may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. These values are not tested during production test.**_ 

## **Table 18 Absolute Maximum Ratings** 

|**Parameter**|**Symbol**|**Limit Values**|**Limit Values**|**Unit**|**Remarks**|
|---|---|---|---|---|---|
|||**min**|**max**|||
|Voltage externally supplied<br>to pin VCC|VVCCEXT|–0.5|26|V|voltage that can be applied<br>to pin VCC by an external<br>voltage source|
|Voltage at pin GDx|VGDx|–0.5|VVCC+ 0.3|V|if gate driver is not<br>configured for digital I/O|
|Junction temperature|TJ|–40|125|°C|_f_sw,max≤ 247.2 kHz|
|Junction temperature|TJ|–40|150|°C|**_2)_**_f_sw,max≤ 186.4 kHz|
|Storage temperature|TS|–55|150|°C||
|Soldering temperature|TSOLD|—|260|°C|Wave Soldering**_3)_**|
|Latch-up capability|ILU|—|150|mA|**_4)_**Pin voltages acc. to abs.<br>max. ratings|
|ESD capability HBM|VHBM|—|1500|V|**_5)_**|
|ESD capability CDM|VCDM|—|500|V|**_6)_**|



- 2 The device guarantees general functionality between 125°C and 150°C. A degradation of performance may apply. 

- 3 According to JESD22-A111 Rev A. 

- 4 Latch-up capability according to JEDEC JESD78D, TA= 85°C. 

- 5 ESD-HBM according to ANSI/ESDA/JEDEC JS-001-2012. 

- 6 ESD-CDM according to JESD22-C101F. 

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## **5 Electrical Characteristics and Parameters** 

|**Table 18**<br>**Absolute Maximum Ratings (continued)**|**Table 18**<br>**Absolute Maximum Ratings (continued)**|**Table 18**<br>**Absolute Maximum Ratings (continued)**|**Table 18**<br>**Absolute Maximum Ratings (continued)**|**Table 18**<br>**Absolute Maximum Ratings (continued)**|**Table 18**<br>**Absolute Maximum Ratings (continued)**|
|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Limit Values**||**Unit**|**Remarks**|
|||**min**|**max**|||
|Input Voltage Limit|_V_pin_DC|-0.5|3.6|V|Voltage externally supplied<br>to pins FB, CS, ZCD, UART (If<br>not stated diferent)|
|Maximum permanent<br>negative clamping current<br>for ZCD and CS|–ICLN_DC|—|2.5|mA|RMS|
|Maximum transient negative<br>clamping current for ZCD<br>and CS|–ICLN_TR|—|10|mA|pulse < 500ns|
|Maximum negative transient<br>input voltage for ZCD|–VIN_ZCD|—|1.5|V|pulse < 500ns|
|Maximum negative transient<br>input voltage for CS|–VIN_CS|—|3.0|V|pulse < 500ns|
|Maximum permanent<br>positive clamping current for<br>CS|ICLP_DC|—|2.5|mA|RMS|
|Maximum transient positive<br>clamping current for CS|ICLP_TR|—|10|mA|pulse < 500ns|
|Maximum current into pin<br>VIN|IAC|—|10|mA|for charging operation|
|Maximum sum of input<br>clamping high currents for<br>digital input stages of device|ICLH_sum|—|300|µA|limits for each individual<br>digital input stage have to<br>be respected|
|Voltage at HV pin|VHV|-0.5|600|V||



## **5.3 Operating Conditions** 

The recommended operating conditions are shown for which the DC Electrical Characteristics are valid. 

|**Table 19**<br>**Operating Range**|**Table 19**<br>**Operating Range**|||||
|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Limit Values**||**Unit**|**Remarks**|
|||**min**|**max**|||
|Ambient temperature|TA|–40|85|°C||
|Junction Temperature|TJ|–40|125|°C|max. 66 MHz fMCLK|
|Lower VCC limit|VVCC|VUVOFF|—|V|device is held in reset when<br>VVCC< VUVOFF|
|Voltage externally supplied<br>to VCC pin|VVCCEXT|—|24|V|maximum voltage that can<br>be applied to pin VCC by an<br>external voltage source|
|Gate driver pin voltage|VGD|–0.5|VVCC+ 0.3|V||
|Line frequency|fin|45|66|Hz||



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## **5 Electrical Characteristics and Parameters** 

## **5.4 DC Electrical characteristics** 

The electrical characteristics provide the spread of values applicable within the specified supply voltage and junction temperature range, TJ from -40 °C to +150 °C. Any necessary differentiation in value between Tj ≤ 125 °C and Tj > 125 °C is explicitly shown. 

Values have been verified either with simulation models up to Tj = 150 °C or by device characterization up to 140 °C. 

Typical values represent the median values related to TA = 25 °C. All voltages refer to GND, and the assumed supply voltage is VVCC = 18 V if not otherwise specified. 

_Note: Not all values given in the tables are tested during production testing. Values not tested are explicitly marked._ 

|**Table 20**<br>**Power supply characteristics**|**Table 20**<br>**Power supply characteristics**|**Table 20**<br>**Power supply characteristics**|**Table 20**<br>**Power supply characteristics**|**Table 20**<br>**Power supply characteristics**|**Table 20**<br>**Power supply characteristics**|**Table 20**<br>**Power supply characteristics**|
|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Values**|||**Unit**|**Note or Test Condition**|
|||**Min.**|**Typ.**|**Max.**|||
|VCC_ON threshold|VVCCon|—|VSELF|—|V|Self-powered startup<br>(default)|
|VCC_ON_SELF threshold|VSELF|19|20.5|22|V|dVVCC/dt = 0.2 V/ms|
|VCC_ON_SELF delay|tSELF|—|—|2.1|µs|Reaction time of VVCC<br>monitor|
|VCC_UVOFF current|IVCCUVOFF|5|20|40|µA|VVCC< VSELF(min) - 0.3 V<br>or VVCC< VEXT(min) -<br>0.3 V**_7)_**|
|UVOFF threshold|VUVOFF|—|6.0|—|V|SYS_CFG0.SELUVTHR = 0<br>0B|
|UVOFF threshold<br>tolerance|ΔUVOFF|—|—|±5|%|This value defines the<br>tolerance of VUVOFF|
|UVOFF filter constant|tUVOFF|600|—|—|ns|1V overdrive|
|UVLO (UVWAKE)<br>threshold|VUVLO|—|VUVOFF·<br>1.25|—|V||
|UVWAKE threshold<br>tolerance|ΔUVLO|—|—|±5|%|This value defines the<br>tolerance of VUVLO|
|UVLO (UVWAKE) filter<br>constant|tUVLO|0.6|—|2.2|µs|1 V overdrive|
|OVLO (OVWAKE)<br>threshold|VOVLO|—|VSELF|—|V||
|OVLO (OVWAKE) filter<br>constant|tOVLO|0.6|—|2.4|µs|1 V overdrive|
|VDDP voltage|VVDDP|3.04|3.20|3.36|V|At PMD0/PSMD1. Some<br>internal values refer<br>to VVDDP/ VVDDA|



> 7 Tested at VVCC = 5.5 V 

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## **5 Electrical Characteristics and Parameters** 

|**Table 20**<br>**Power supply characteristics (continued)**|**Table 20**<br>**Power supply characteristics (continued)**|**Table 20**<br>**Power supply characteristics (continued)**|**Table 20**<br>**Power supply characteristics (continued)**|**Table 20**<br>**Power supply characteristics (continued)**|**Table 20**<br>**Power supply characteristics (continued)**|**Table 20**<br>**Power supply characteristics (continued)**|
|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Values**|||**Unit**|**Note or Test Condition**|
|||**Min.**|**Typ.**|**Max.**|||
|||||||and VVDDPPS/ VVDDAPS<br>respectively.|
|VDDA voltage|VVDDA|3.20|3.31|3.42|V|At PMD0/PSMD1. Some<br>internal values refer<br>to VVDDP/ VVDDA<br>and VVDDPPS/ VVDDAPS<br>respectively.|
|Nominal range 0% to<br>100%|VADCVCC|0|—|VREF|V|VADCVCC= 0.09 · VVCC**_8)_**|
|Reduced VCC range for<br>ADC measurement|RADCVCC|8|—|92|%|**_9)10)_**|
|Maximum error for<br>ADC measurement (8-bit<br>result)|TET0VCC|—|—|3.8|LSB8||
|Maximum error for<br>ADC measurement (8-bit<br>result)|TET256VCC|—|—|5.2|LSB8||
|Gate driver current<br>consumption excl. gate<br>charge current|IVCCGD|—|0.26|0.35|mA|Tj≤ 125°C|
|Gate driver current<br>consumption excl. gate<br>charge current|IVCCGD|—|—|0.5|mA|Tj> 125°C|
|VCC quiescent current in<br>PMD0|IVCCPMD0|—|3.5|4.7|mA|All registers have reset<br>values, clock is active,<br>CPU is stopped|
|VCC quiescent current in<br>PSMD2|IVCCPSMD2|—|0.3|0.48|mA|Tj≤ 85 °CWU_PWD_CFG<br>= 2CH|
|VCC quiescent current in<br>PSMD2|IVCCPSMD2|—|—|1.2|mA|Tj≤ 125 °CWU_PWD_CFG<br>= 2CH|
|VCC quiescent current in<br>PSMD2|IVCCPSMD2|—|—|1.8|mA|Tj>125 °CWU_PWD_CFG<br>= 2CH|
|VCC quiescent current<br>in power saving mode<br>PSDM4 with standby<br>logic active|IVCCPSMD4|—|0.13|0.18|mA|Tj≤ 125 °C<br>WU_PWD_CFG = 00H|



> 8 Theoretical minimum value, real minimum value is related to VUVOFF threshold. 

> 9 Operational values. 

> 10 Note that the system is turned off if VVCC < VUFOFF. 

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## **5 Electrical Characteristics and Parameters** 

|**Table 20**<br>**Power supply characteristics (continued)**|**Table 20**<br>**Power supply characteristics (continued)**|**Table 20**<br>**Power supply characteristics (continued)**|**Table 20**<br>**Power supply characteristics (continued)**|**Table 20**<br>**Power supply characteristics (continued)**|**Table 20**<br>**Power supply characteristics (continued)**|**Table 20**<br>**Power supply characteristics (continued)**|
|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Values**|||**Unit**|**Note or Test Condition**|
|||**Min.**|**Typ.**|**Max.**|||
|VCC quiescent current<br>in power saving mode<br>PSDM4 with standby<br>logic active|IVCCPSMD4|—|—|0.25|mA|Tj>125 °C WU_PWD_CFG<br>= 00H|
||||||||
|**Table 21**<br>**Electrical characteristics of the GD pin**|||||||



|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|Input clamping current,<br>low|–ICLL|—|—|100|µA|only digital input|
|Input clamping current,<br>high|ICLH|—|—|100|µA|only digital input|
|APD low voltage (active<br>pull-down while device<br>is not powered or gate<br>driver is not enabled)|VAPD|—|—|1.6|V|IGD= 5 mA|
|RPPDvalue|RPPD|—|600|—|kΩ|Permanent pull-down<br>resistor inside gate<br>driver|
|RPPDtolerance|ΔPPD|—|—|±25|%|Permanent pull-down<br>resistor inside gate<br>driver|
|Driver output low<br>impedance|RGDL|—|—|7.0|Ω|TJ≤ 125 °C, IGD= 0.1 A|
|Driver output low<br>impedance|RGDL|—|—|7.5|Ω|TJ> 125 °C,  =  0.1 A|
|Nominal output high<br>voltage in PWM mode|VGDH|—|12|—|V|GDx_CFG.VOL = 2,<br>IGDH= –1 mA|
|Output voltage tolerance|ΔVGDH|—|—|±5|%|Tolerance of<br>programming options if<br>VGDH> 10 V, IGDH= –1 mA|
|Rail-to-rail output high<br>voltage|VGDHRR|VVCC– 0.5|—|VVCC|V|If VVCC< programmed<br>VGDHand output at high<br>state|
|Output high current in<br>PWM mode for GD0|–IGDH|—|100|—|mA|GDx_CFG.CUR = 8|
|Output high current<br>tolerance in PWM mode|ΔIGDH|—||±15|%|Calibrated**_11)_**|



> 11 referred to GDx_CFG.CUR = 16 

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## **5 Electrical Characteristics and Parameters** 

|**Table 21**<br>**Electrical characteristics of the GD pin (continued)**|**Table 21**<br>**Electrical characteristics of the GD pin (continued)**|**Table 21**<br>**Electrical characteristics of the GD pin (continued)**|**Table 21**<br>**Electrical characteristics of the GD pin (continued)**|**Table 21**<br>**Electrical characteristics of the GD pin (continued)**|**Table 21**<br>**Electrical characteristics of the GD pin (continued)**|**Table 21**<br>**Electrical characteristics of the GD pin (continued)**|
|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Values**|||**Unit**|**Note or Test Condition**|
|||**Min.**|**Typ.**|**Max.**|||
|Discharge current for<br>GD0|IGDDIS|800|—|—|mA|VGD= 4 V and driver at<br>low state|
|Output low reverse<br>current|–IGDREVL|—|—|100|mA|Applies if VGD< 0 V and<br>driver at low state|
|Output high reverse<br>current in PWM mode|IGDREVH|—|1/6 of IGDH|—||Applies if<br>VGD> VGDH+ 0.5 V (typ)<br>and driver at high state|



## **Table 22 Electrical characteristics of the CS pin** 

|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|Input voltage operating<br>range|VINP|–0.5|—|3.0|V||
|OCP2 comparator<br>reference voltage,<br>derived from VVDDA,<br>given values assuming<br>VVDDA= VVDDA,typ|VOCP2|—|1.6|—|V|SYS_CFG0.OCP2 = 00B|
|OCP2 comparator<br>reference voltage,<br>derived from VVDDA,<br>given values assuming<br>VVDDA= VVDDA,typ|VOCP2|—|1.2|—|V|SYS_CFG0.OCP2 = 01B|
|OCP2 comparator<br>reference voltage,<br>derived from VVDDA,<br>given values assuming<br>VVDDA= VVDDA,typ|VOCP2|—|0.8|—|V|SYS_CFG0.OCP2 = 10B|
|OCP2 comparator<br>reference voltage,<br>derived from VVDDA,<br>given values assuming<br>VVDDA= VVDDA,typ|VOCP2|—|0.6|—|V|SYS_CFG0.OCP2 = 11B|
|Threshold voltage<br>tolerance|ΔVOCP2|—|—|±5|%|Voltage divider tolerance|
|Comparator propagation<br>delay|tOCP2PD|15|—|35|ns||
|Minimum comparator<br>input pulse width|tOCP2PW|—|—|30|ns||
|OCP2F comparator<br>propagation delay|tOCP2FPD|70|—|170|ns|dVCS/dt = 100 V/µs|



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## **5 Electrical Characteristics and Parameters** 

**Table 22 Electrical characteristics of the CS pin (continued)** 

|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|Delay from VCScrossing<br>VCSOCP2to begin of GDx<br>turn-of (IGD0> 2mA)|tCSGDxOCP2|125|135|190|ns|dVCS/dt = 100 V/µs;<br>fMCLK= 66 MHz. GDx<br>driven by QR_GATE<br>FIL_OCP2.STABLE = 3|
|OCP1 operating range|VOCP1|0|—|VREF/2|V|RANGE =00B|
|OCP1 threshold at<br>full scale setting<br>(CS_OCP1LVL=FFH)|VOCP1FS|1187|1209|1243|mV|RANGE =00B|
|Delay from VCScrossing<br>VCSOCP1to CS_OCP1<br>rising edge, 1.2 V range|tCSOCP1|90|170|250|ns|Input signal slope dVCS/<br>dt = 150 mV/µs. This<br>slope represents a use<br>case of a switch-mode<br>power supply with<br>minimum input voltage.|
|Delay from CS_OCP1<br>rising edge to QR_GATE<br>falling edge|tOCP1GATE|—|—|130|ns||
|Delay from QR_GATE<br>falling edge to start of<br>GDx turn-of|tGATEGDx|1|3|5|ns|GDx driven by QR_GATE.<br>Measured up to<br>IGDx> 2 mA|
|OCP1 comparator input<br>single pulse width filter|tOCP1PW|60|—|95|ns|Shorter pulses than min.<br>are suppressed, longer<br>pulses than max. are<br>passed|
|Nominal S&H operating<br>range 0% to 100%|VCSH|0|—|VREF/2|V|CS_ICR.RANGE =00B|
|Reduced S&H operating<br>range|RRCVSH|8|—|92|%|CS_ICR.RANGE =00B<br>Operational values|
|Maximum error of<br>CS0 S&H for corrected<br>measurement (8-bit<br>result)|TET0CS0S|—|—|4.7|LSB|CS_ICR.RANGE =00B|
|Maximum error of<br>CS0 S&H for corrected<br>measurement (8-bit<br>result)|TET256CS0S|—|—|6.0|LSB|CS_ICR.RANGE =00B|
|Nominal S&H operating<br>range 0% to 100%|VCSH|0|—|VREF/6|V|CS_ICR.RANGE =11B|
|Reduced S&H operating<br>range|RRCVSH|20|—|80|%|CS_ICR.RANGE =11B<br>Operational values|



Data Sheet 

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## **5 Electrical Characteristics and Parameters** 

|**Table 22**<br>**Electrical characteristics of the CS pin (continued)**|**Table 22**<br>**Electrical characteristics of the CS pin (continued)**|**Table 22**<br>**Electrical characteristics of the CS pin (continued)**|**Table 22**<br>**Electrical characteristics of the CS pin (continued)**|**Table 22**<br>**Electrical characteristics of the CS pin (continued)**|**Table 22**<br>**Electrical characteristics of the CS pin (continued)**|**Table 22**<br>**Electrical characteristics of the CS pin (continued)**|
|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Values**|||**Unit**|**Note or Test Condition**|
|||**Min.**|**Typ.**|**Max.**|||
|Maximum error of<br>CS0 S&H for corrected<br>measurement (8-bit<br>result)|TET0CS0S|—|—|8.0|LSB|CS_ICR.RANGE =11B|
|Maximum error of<br>CS0 S&H for corrected<br>measurement (8-bit<br>result)|TET256CS0S|—|—|8.7|LSB|CS_ICR.RANGE =11B|
|S&H delay of input bufer|tCSHST|—|—|510|ns|Referring to jump in<br>input voltage. Limits the<br>minimum gate driver Ton<br>time.|
||||||||
|**Table 23**<br>**Electrical characteristics of the ZCD pin**|||||||
|**Parameter**|**Symbol**|**Values**|||**Unit**|**Note or Test Condition**|
|||**Min.**|**Typ.**|**Max.**|||
|Input voltage operating<br>range|VINP|–0.5|—|3.3|V||
|Input clamping current,<br>high|ICLH|—|—|100|µA||
|Zero-crossing threshold|VZCTHR|15|40|70|mV||
|Comparator propagation<br>delay|tZCPD|30|50|70|ns|dVZCD/dt = 4 V/µs|
|Input voltage negative<br>clamping level|–VINPCLN|140|180|220|mV|Analog clamp activated|
|Nominal I/V-conversion<br>operating range 0% to<br>100%|–IIV|0|—|0.5|mA|CRNG =11BGain = 4800<br>mV/mA|
|Nominal I/V-conversion<br>operating range 0% to<br>100%|–IIV|0|—|1|mA|CRNG =10BGain = 2400<br>mV/mA|
|Nominal I/V-conversion<br>operating range 0% to<br>100%|–IIV|0|—|2|mA|CRNG =01BGain = 1200<br>mV/mA|
|Nominal I/V-conversion<br>operating range 0% to<br>100%|–IIV|0|—|4|mA|CRNG =00BGain = 600<br>mV/mA|
|Reduced I/V-conversion<br>operating range|RRIV|5|—|80|%||



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## **5 Electrical Characteristics and Parameters** 

|**Table 23**<br>**Electrical characteristics of the ZCD pin (continued)**|**Table 23**<br>**Electrical characteristics of the ZCD pin (continued)**|**Table 23**<br>**Electrical characteristics of the ZCD pin (continued)**|**Table 23**<br>**Electrical characteristics of the ZCD pin (continued)**|**Table 23**<br>**Electrical characteristics of the ZCD pin (continued)**|**Table 23**<br>**Electrical characteristics of the ZCD pin (continued)**|**Table 23**<br>**Electrical characteristics of the ZCD pin (continued)**|
|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Values**|||**Unit**|**Note or Test Condition**|
|||**Min.**|**Typ.**|**Max.**|||
|Overall tolerance of the<br>ZCD IV measurement|ΔIIV|-4.7|—|4.7|%|T<125°C, –IIV>375 µA ,<br>by design, not ensured<br>by production test|
|Maximum deviation<br>between ZCD clamp<br>voltage and trim result<br>stored in OTP|EZCDClp|—|—|±5|%|–IIV> 0.25 mA|
|IV-conversion delay of<br>input bufer|tIVST|—|—|900|ns|Refers to jump in input<br>current**_12)_**|
|Nominal S&H input<br>voltage range 0% to<br>100%|VZSH|0|—|2/3 · VREF|V|SHRNG =0B|
|Nominal S&H input<br>voltage range 0% to<br>100%|VZSH|VREF/2|—|7/6 · VREF|V|SHRNG =1B|
|Reduced S&H input<br>voltage range|RRZVSH|4|—|95|%||
|Maximum error<br>for corrected ADC<br>measurement (8-bit<br>result)|TET0ZVS0|—|—|3.7|LSB8|SHRNG =0B|
|Maximum error<br>for corrected ADC<br>measurement (8-bit<br>result)|TET256ZVS0|—|—|4.9|LSB8|SHRNG =0B|
|Maximum error<br>for corrected ADC<br>measurement (8-bit<br>result)|TET0ZVS1|—|—|4.2|LSB8|SHRNG =1B|
|Maximum error<br>for corrected ADC<br>measurement (8-bit<br>result)|TET256ZVS1|—|—|5.8|LSB8|SHRNG =1B|
|S&H delay of input bufer<br>referring to jump of input<br>voltage|tZSHST|—|—|1.0|µs|SHRNG =0BTj≤ 125 °C|
|S&H delay of input bufer<br>referring to jump of input<br>voltage|tZSHST|—|—|1.2|µs|SHRNG =0BTj> 125 °C|



> 12 Limits the minimum gate driver Ton time. 

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## **5 Electrical Characteristics and Parameters** 

## **Table 23 Electrical characteristics of the ZCD pin (continued)** 

|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|S&H delay of input bufer<br>referring to jump of input<br>voltage|tZSHST|—|—|1.6|µs|SHRNG =1BTj≤ 125 °C|
|S&H delay of input bufer<br>referring to jump of input<br>voltage|tZSHST|—|—|1.8|µs|SHRNG =1BTj> 125 °C|



## **Table 24 Electrical characteristics of the HV pin** 

|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|Current for VCCcap<br>charging|ILD|3.0|5|7.5|mA|VHV= 30 V; VVCC< VVCCon–<br>0.3 V; Tj≥ 0°C|
|Current for VCCcap<br>charging|ILD|2.4|5|7.5|mA|VHV= 30 V; VVCC< VVCCon–<br>0.3 V;-25°C < Tj< 0°C|
|Current for VCCcap<br>charging|ILD|2.0|5|7.5|mA|VHV= 30 V; VVCC< VVCCon–<br>0.3 V;Tj< -25°C|
|Nominal current for<br>measurement path 0% to<br>100%|IMEAS|0|—|9.6|mA|CURRNG = 11B|
|Nominal current for<br>measurement path 0% to<br>100%|IMEAS|0|—|4.8|mA|CURRNG = 10B|
|Nominal current for<br>measurement path 0% to<br>100%|IMEAS|0|—|1.6|mA|CURRNG = 01B|
|Comparator threshold (in<br>% of full range of IMEAS)|THRCOMP|15|20|25|%|COMPTHR= 00B|
|Comparator threshold (in<br>% of full range of IMEAS)|THRCOMP|25|30|35|%|COMPTHR= 01B|
|Comparator threshold (in<br>% of full range of IMEAS)|THRCOMP|45|50|55|%|COMPTHR= 11B|



**Table 25 Electrical characteristics of the FB pin** 

|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|MFIO reference voltage|VMFIOREF|—|VREF|—|V|Selection = VREF|
|Nominal range 0% to<br>100%|VMFIO|0|—|VREF|V|Gain = 1|



Data Sheet 

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## **5 Electrical Characteristics and Parameters** 

|**Table 25**<br>**Electrical characteristics of the FB pin (continued)**|**Table 25**<br>**Electrical characteristics of the FB pin (continued)**|**Table 25**<br>**Electrical characteristics of the FB pin (continued)**|**Table 25**<br>**Electrical characteristics of the FB pin (continued)**|**Table 25**<br>**Electrical characteristics of the FB pin (continued)**|**Table 25**<br>**Electrical characteristics of the FB pin (continued)**|**Table 25**<br>**Electrical characteristics of the FB pin (continued)**|
|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Values**|||**Unit**|**Note or Test Condition**|
|||**Min.**|**Typ.**|**Max.**|||
|Reduced operating range|RRVMFIO|4|—|96|%|Gain = 1. Operational<br>values.|
|Maximum error for<br>corrected measurement<br>(8-bit result)|TET0MFI0|—|—|4.0|LSB8|Gain = 1|
|Maximum error for<br>corrected measurement<br>(8-bit result)|TET256MFI0|—|—|4.8|LSB8|Gain = 1|
|Delay of input bufer|tMFIOST|—|—|2.7|µs|Refers to jump in input<br>voltage 0% to 90%.<br>Applicable for MFIO0<br>and MFIO1 only.|
|Pull-up resistor tolerance|ΔRPU|—|—|±20|%|Overall tolerance|



|**Table 26**<br>**Electrical characteristics of the UART pin**|**Table 26**<br>**Electrical characteristics of the UART pin**|**Table 26**<br>**Electrical characteristics of the UART pin**|**Table 26**<br>**Electrical characteristics of the UART pin**|**Table 26**<br>**Electrical characteristics of the UART pin**|**Table 26**<br>**Electrical characteristics of the UART pin**|**Table 26**<br>**Electrical characteristics of the UART pin**|
|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Values**|||**Unit**|**Note or Test Condition**|
|||**Min.**|**Typ.**|**Max.**|||
|Input clamping current,<br>low|–ICLL|—|—|100|µA|only digital input|
|Input clamping current,<br>high|ICLH|—|—|100|µA|only digital input|
|Input capacitance|CINPUT|—|—|25|pF||
|Input low voltage|VIL|—|—|1.0|V||
|Input high voltage|VIH|2.1|—|—|V||
|Input low current with<br>active weak pull-up WPU|–ILPU|30|—|90|µA|Measured at max. VIL|
|Max. input frequency|fINPUT|15|—|—|MHz||
|Output low voltage|VOL|—|—|0.8|V|IOL= 2 mA|
|Output high voltage|VOH|2.4|—|—|V|IOH= –2 mA|
|Output sink current|IOL|—|—|2|mA||
|Output source current|-IOH|—|—|2|mA||
|Output rise time (0 → 1)|tRISE|—|—|50|ns|20 pF load, push/pull<br>output|
|Output fall time (1 → 0)|tFALL|—|—|50|ns|20 pF load, push/pull or<br>open-drain output|
|Max. output switching<br>frequency|fSWITCH|10|—|—|MHz||



Data Sheet 

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## **5 Electrical Characteristics and Parameters** 

|**Table 26**<br>**Electrical characteristics of the UART pin (continued)**|**Table 26**<br>**Electrical characteristics of the UART pin (continued)**|**Table 26**<br>**Electrical characteristics of the UART pin (continued)**|**Table 26**<br>**Electrical characteristics of the UART pin (continued)**|**Table 26**<br>**Electrical characteristics of the UART pin (continued)**|**Table 26**<br>**Electrical characteristics of the UART pin (continued)**|**Table 26**<br>**Electrical characteristics of the UART pin (continued)**|
|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Values**|||**Unit**|**Note or Test Condition**|
|||**Min.**|**Typ.**|**Max.**|||
|UART baudrate for<br>parameter configuration|fUART|-10%|57600|+10%|baud||
|UART baudrate for<br>reporting|fUART,report|-10%|9600|+10%|baud||
||||||||
|**Table 27**<br>**Electrical characteristics of the A/D converter**|||||||
|**Parameter**|**Symbol**|**Values**|||**Unit**|**Note or Test Condition**|
|||**Min.**|**Typ.**|**Max.**|||
|Integral non-linearity|INL|—|—|1|LSB8|**_13)_**|
||||||||
|**Table 28**<br>**Electrical characteristics of the reference voltage**|||||||
|**Parameter**|**Symbol**|**Values**|||**Unit**|**Note or Test Condition**|
|||**Min.**|**Typ.**|**Max.**|||
|Reference voltage|VREF|—|2.428|—|V||
|VREF overall tolerance|ΔVREF|—|—|±1.5|%|Trimmed, Tj≤ 125 °C and<br>aging|
|VREF overall tolerance|ΔVREF|—|—|±2.0|%|Trimmed, full<br>temperature range and<br>aging|



## **Table 29 Electrical characteristics of the OTP programming** 

|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|OTP programming<br>voltage at the VCC pin for<br>range C000Hto CFFFH|VPP|7.35|7.5|7.65|V|Operational values|
|OTP programming<br>current|IPP|—|1.6|—|mA|Programming of 4 bits in<br>parallel|



## **Table 30 Electrical characteristics of the clock oscillators** 

|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|Master clock oscillation<br>period including all<br>variations|tMCLK|15.0|15.8|16.6|ns|In reference to 66 MHz<br>fMCLK|



> 13 ADC capability measured via channel MFIO without errors due to switching of neighbouring pins, e.g. gate drivers, measured with STC = 5. MFIO buffer non-linearity masked out by taking ADC output values ≥ 30 only. 

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## **5 Electrical Characteristics and Parameters** 

## **Table 30 Electrical characteristics of the clock oscillators (continued)** 

|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|Main clock oscillator<br>frequency variation<br>of stored DPARAM<br>frequency|ΔMCLK|–3.2|—|+3.5|%|Temperature drif and<br>aging only, 66 MHz fMCLK|
|Standby clock oscillator<br>frequency|fSTBCLK|96|100|104|kHz|Trimming tolerance at<br>TA= 25 °C|
|Standby clock oscillator<br>frequency|fSTBCLK|90|100|110|kHz|Overall tolerance, Tj≤<br>125 °C|
|Standby clock oscillator<br>frequency|fSTBCLK|85|100|110|kHz|Overall tolerance, Tj<br>>125 °C|



|**Table 31**<br>**Electrical characteristics of the temperature sensor**|**Table 31**<br>**Electrical characteristics of the temperature sensor**|**Table 31**<br>**Electrical characteristics of the temperature sensor**|**Table 31**<br>**Electrical characteristics of the temperature sensor**|**Table 31**<br>**Electrical characteristics of the temperature sensor**|**Table 31**<br>**Electrical characteristics of the temperature sensor**|**Table 31**<br>**Electrical characteristics of the temperature sensor**|
|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Values**|||**Unit**|**Note or Test Condition**|
|||**Min.**|**Typ.**|**Max.**|||
|Temperature sensor ADC<br>output operating range|ADCTEMP|0|—|190|LSB|ADCTEMP= 40 +<br>temperature / °C)|
|Temperature sensor<br>tolerance|ΔTEMP|—|—|±6|K|Incl. ADC conversion<br>accuracy at 3 σ|



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**6 Package Dimensions** 

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## **6 Package Dimensions** 

The package dimensions of PG-DSO-8 are provided. 

**==> picture [115 x 58] intentionally omitted <==**

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## **Figure 18 Package Dimensions for PG-DSO-8** 

_Note: Dimensions in mm._ 

_Note: You can find all of our packages, packing types and other package information on our Infineon Internet page “Products”: http://www.infineon.com/products._ 

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## **7 References** 

## **7 References** 

**1.** Infineon: _XDPL8219 Design Guide_ 

**2.** Infineon: _XDPL8219 Reference Board Engineering Report_ 

**3.** Infineon: _CoolMOS P7 power MOSFETs_ , _**http://www.infineon.com/P7**_ 

## **8 Revision History** 

Major changes since previous revision 

|**3.**<br>Infineon:_CoolMOS P7 power MOSFETs_,**_http://www.infineon.com/P7_**<br>**8**<br>**Revision History**<br>Major changes since previous revision|**3.**<br>Infineon:_CoolMOS P7 power MOSFETs_,**_http://www.infineon.com/P7_**<br>**8**<br>**Revision History**<br>Major changes since previous revision|
|---|---|
|||
|**Revision History**||
|**Revision**|**Description**|
|1.0|Initial version|
|1.1|**_Figure 1_**: Text improvement from "XDPL8219" to "Flyback Controller IC".<br>**_Figure 4_**: Correction of ton,min(Vin) alignment with the reference point.|



## **Glossary** 

## **ABM** 

## _Active Burst Mode (ABM)_ 

Active Burst Mode is an operating mode of a switched-mode power supply for very light load conditions. The controller switches in bursts of pulses with a pause between bursts in which no switching is done. 

## **ADC** 

## _Analog-to-Digital Converter (ADC)_ 

An analog-to-digital converter is a device that converts a continuous physical quantity (usually voltage) to a digital number that represents the quantity's amplitude. 

## **BOM** 

## _Bill of Materials (BOM)_ 

A bill of materials is a list of the raw materials, sub-assemblies, intermediate assemblies, sub-components, parts and the quantities of each needed to manufacture an end product. 

## **CCM** 

## _Continuous Conduction Mode (CCM)_ 

Continuous Conduction Mode is an operational mode of a switching power supply in which the current is continuously flowing and does not return to zero. 

## **CRC** 

## _Cyclic Redundancy Check_ 

A cyclic redundancy check is an error-detecting code commonly used to detect accidental changes to raw data. 

## **CV** 

## _Constant Voltage (CV)_ 

Constant Voltage is a mode of a power supply in which the output voltage is kept constant regardless of the load. 

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## **Glossary** 

## **DCM** 

## _Discontinuous Conduction Mode (DCM)_ 

Discontinuous Conduction Mode is an operational mode of a switching power supply in which the current starts and returns to zero. 

## **EMI** 

## _Electro-Magnetic Interference (EMI)_ 

Also called Radio Frequency Interference (RFI), this is a (usually undesirable) disturbance that affects an electrical circuit due to electromagnetic radiation emitted from an external source. The disturbance may interrupt, obstruct, or otherwise degrade or limit the effective performance of the circuit. 

## **FB** 

## _Flyback (FB)_ 

A flyback converter is a power converter with the inductor split to form a transformer, so that the voltage ratios are multiplied with an additional advantage of galvanic isolation between the input and any outputs. 

## **GUI** 

## _Graphic User Interface_ 

A graphical user interface is a type of interface that allows users to interact with electronic devices through graphical icons and visual indicators. 

## **HID** 

_Human Interface Device (HID)_ 

A Human Interface Device is a type of computer device that interacts directly with, and most often takes input from, humans and may deliver output to humans. The term HID most commonly refers to the USB-HID specification. 

## **IC** 

_Integrated Circuit (IC)_ 

A miniaturized electronic circuit that has been manufactured in the surface of a thin substrate of semiconductor material. An IC may also be referred to as micro-circuit, microchip, silicon chip, or chip. 

## **IIR** 

## _Infinite Impulse Response (IIR)_ 

Infinite impulse response is a property applying to many linear time-invariant systems. Common examples of linear time-invariant systems are most electronic and digital filters. Systems with this property have an impulse response which does not become exactly zero past a certain point, but continues indefinitely. 

## **OCP1** 

## _Overcurrent Protection Level 1 (OCP1)_ 

The Overcurrent Protection Level 1 is limiting the current in a switched-mode power supply to limit the power delivered to the output of the power supply. 

## **OTP** 

## _One-Time Programmable memory_ 

A one-time programmable memory is a form of memory to which data can be written once. After writing, the data is stored permanently and cannot be further changed. 

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## **Glossary** 

## **PCB** 

## _Printed Circuit Board (PCB)_ 

A Printed Circuit Board mechanically supports and electrically connects electronic components using conductive tracks, pads and other features etched from copper sheets laminated onto a non-conductive substrate. 

## **PC** 

## _Personal Computer_ 

A personal computer is a general-purpose computer whose size, capabilities, and original sale price make it useful for individuals, and which is intended to be operated directly by an end-user with no intervening computer time-sharing models that allowed larger, more expensive minicomputer and mainframe systems to be used by many people, usually at the same time. 

## **PFC** 

## _Power Factor Correction (PFC)_ 

Power factor correction increases the power factor of an AC power circuit closer to 1 which corresponds to minimizing the reactive power of the power circuit. 

## **PF** 

## _Power Factor (PF)_ 

Power factor is the ratio between the real power and the apparent power. 

## **PWM** 

## _Pulse Width Modulation (PWM)_ 

Pulse-width modulation is a technique to encode an analog value into the duty cycle of a pulsing signal with arbitrary amplitude. 

## **QRM1** 

## _Quasi-Resonant Mode, switching in first valley (QRM1)_ 

Quasi-Resonant Mode is an operating mode of a switched-mode power supply which maximizes efficiency. This is achieved by switching at the occurrence of the first valley of a signal which corresponds to a time when switching losses are low. 

## **QRMn** 

## _Quasi-Resonant Mode, switching in valley n (QRMn)_ 

Quasi-Resonant Mode is an operating mode of a switched-mode power supply which maximizes efficiency. This is achieved by switching at the occurence of an nth valley of a signal which corresponds to a time when switching losses are low. 

## **RAM** 

## _Random Access Memory_ 

Random-access memory is a form of computer data storage that allows data items to be read and written regardless of the order in which they are accessed. 

## **SSR** 

## _Secondary Side Regulated (SSR)_ 

A Secondary Side Regulated power supply is controls its operation based on feedback from the secondary side of an isolated power supply. 

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## **Glossary** 

## **THD** 

## _Total Harmonic Distortion (THD)_ 

The total harmonic distortion of a signal is a measurement of the harmonic distortion present and is defined as the ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency. 

## **UART** 

_Universal Asynchronous Receiver Transmitter_ 

A universal asynchronous receiver transmitter is used for serial communications over a peripheral device serial port by translating data between parallel and serial forms. 

## **USB** 

_Universal Serial Bus_ 

Universal Serial Bus is an industry standard that defines cables, connectors and communications protocols used in a bus for connection, communication, and power supply between computers and electronic devices. 

## **UVLO** 

_Undervoltage Lockout (UVLO)_ 

The Undervoltage-Lockout is an electronic circuit used to turn off the power of an electronic device in the event of the voltage dropping below the operational value. 

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## **Trademarks** 

All referenced product or service names and trademarks are the property of their respective owners. 

**Edition 2020-08-26 IMPORTANT NOTICE Published by** The information given in this document shall in no event be regarded as a guarantee of conditions or **Infineon Technologies AG** characteristics (“Beschaffenheitsgarantie”) . **81726 Munich, Germany** With respect to any examples, hints or any typical values stated herein and/or any information regarding **© 2020 Infineon Technologies AG** the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities **All Rights Reserved.** of any kind, including without limitation warranties of non-infringement of intellectual property rights of any **Do you have a question about any** third party. **aspect of this document?** In addition, any information given in this document is **Email: erratum@infineon.com** subject to customer’s compliance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning **Document reference** customer’s products and any use of the product of **IFX-upn1544165930598** Infineon Technologies in customer’s applications. 

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