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XDPL8218XUMA1
LED Driver AC/DC, Flyback, 90V to 305V Input, 180 kHz, 1 Output, SOIC-8
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- Manufacturer: INFINEON
- Product type: AC / DC LED Driver ICs
- IC Mounting: Surface Mount
| Delivery and price | |
|---|---|
| Units per pack | 1000 |
| Price | 0.474 € |
| Current stock | 10+ |
| Lead time | 30 days |
Datasheet
**==> picture [584 x 65] intentionally omitted <==** ## **XDPL8218 Digital Flyback Controller IC** ## **XDP[™] Digital Power** ## **Data Sheet Revision 1.0** ## **Features** - Single stage flyback controller with _**Power Factor Correction (PFC)**_ - _**Secondary Side Regulated (SSR) Constant Voltage (CV)**_ output - Supports universal AC input (90 Vrms to 305 Vrms) and DC input - High power quality from 33% to 100% load, with AC input up to 277 Vrms - Typical _**Power Factor (PF)**_ > 0.98 and _**Total Harmonic Distortion (THD)**_ < 10% - High efficiency with _**Quasi-Resonant Mode, switching in valley 1 (QRM1)**_ at high output power and frequency controlled _**Discontinuous Conduction Mode (DCM)**_ at medium output power - • Typical efficiency > 90% - Low standby power with _**Active Burst Mode (ABM)**_ - Typical standby power < 100 mW (under flyback output no load condition) - Low audible noise in _**ABM**_ - Input overvoltage and undervoltage (Brown-in / Brown-out) protection - Power limitation during brown-out, to better protect primary components from overheating and saturation - Output power limitation and output undervoltage protection - Output overvoltage protection and _VCC_ overvoltage protection - Configurable parameters, e.g. brown-out power limitation slope, protection thresholds and reaction (autorestart / latch-mode) - Supports design of Class 2 drivers - Low Bill of Materials ## **Product validation** Qualified for industrial applications according to the relevant tests of JEDEC47/20/22. ## **Potential applications** - Front-stage _**PFC**_ converter of the Electronic Control Gear for LED luminaires Please read the Important Notice and Warnings at the end of this document Datasheet **www.infineon.com** Revision 1.0 2018-06-06 **XDPL8218 Digital Flyback Controller IC XDP[™] Digital Power** **==> picture [105 x 47] intentionally omitted <==** ## **Description** **==> picture [454 x 262] intentionally omitted <==** **----- Start of picture text -----**<br> Vd<br>(0.7V typ.)<br>Lp<br>Np Ns Output<br>AC Input Vout,cap,rating<br>voltage CDC,filter<br>RZCD,1 Na<br>CVCC<br>RZCD,2<br>RHV<br>VCC ZCD<br>GD IGD,pk CoolMOS™<br>HV CS<br>XDPL8218<br>RCS<br>GND UART FB Feedback<br>Circuit<br>**----- End of picture text -----**<br> ## **Figure 1 Typical Application for XDPL8218** _Note: The_ _**SSR CV** output in_ _**Figure 1** should not be used to directly drive the LEDs. For LED lighting application, it should be converted to constant current output by a second-stage DC-DC switching or linear regulator._ |**Product type**|**Package**|**Marking**|**Firmware version**|**Ordering code**| |---|---|---|---|---| |XDPL8218|PG-DSO-8|L8218|0.1.1.7|SP001707258| ## **Description** The XDPL8218 is a high performance configurable single-stage _**SSR**_ flyback controller with high power factor, excellent standby power performance (< 100 mW typ.) and constant voltage output. The digital core of the XDPL8218 and its advanced control algorithms provide multiple operation modes such as _**QRM1**_ , _**DCM**_ or _**ABM**_ . In addition, XDPL8218 includes an enhanced _**PFC**_ function which can partially compensate the effect of the input capacitance on power factor and harmonic distortion. With this functionality and smooth transition between the operation modes, the controller delivers high efficiency, high power factor and low harmonic distortion over wide load range. Operating parameters such as protection features are digitally configurable. Infineon offers a user friendly _**Graphic User Interface (GUI)**_ for _**Personal Computer (PC)**_ s, allowing rapid engineering changes without the need for complex component design iterations. Functionality can be defined at the end of the production line. Multiple different power supplies can be built with the same hardware using different XDPL8218 parameter sets. _Note: By default, the configurable parameters of a new XDPL8218 chip from Infineon are empty, so it is necessary to configure them before any application testing._ The system performance and efficiency can be optimized using Infineon _CoolMOS P7 power MOSFETs_ . Datasheet Revision 1.0 2018-06-06 2 **XDPL8218 Digital Flyback Controller IC XDP[™] Digital Power** **==> picture [105 x 47] intentionally omitted <==** ## **Table of contents** ## **Table of contents** ||**Features**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1| |---|---| ||**Product validation**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1| ||**Potential applications**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1| ||**Description**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2| ||**Table of contents**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3| |**1**|**Pin configuration**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5| |**2**|**Functional block diagram**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6| |**3**|**Functional description**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7| |3.1|Regulated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7| |3.2|Configurable gate voltage rising slope at GD pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12| |3.3|Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13| |3.4|Line synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14| |3.5|Input voltage and output voltage estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14| |3.5.1|Output voltage estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15| |3.5.2|Input voltage estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16| |3.6|Power factor correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17| |3.7|Protection features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18| |3.7.1|Primary MOSFET overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18| |3.7.2|Output undervoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18| |3.7.3|Output overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19| |3.7.4|Transformer demagnetization time shortage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20| |3.7.5|Minimum input voltage startup check and input undervoltage protection . . . . . . . . . . . . . . . . . . 20| |3.7.6|Maximum input voltage startup check and input overvoltage protection . . . . . . . . . . . . . . . . . . . 20| |3.7.7|VCC undervoltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21| |3.7.8|VCC undervoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21| |3.7.9|VCC overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21| |3.7.10|IC overtemperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22| |3.7.11|Other protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22| |3.7.12|Protection reactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22| |3.8|Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23| |**4**|**List of Parameters**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24| |**5**|**Electrical Characteristics and Parameters**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29| |5.1|Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29| |5.2|Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29| |5.3|Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30| |5.4|DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31| Datasheet Revision 1.0 2018-06-06 3 **XDPL8218 Digital Flyback Controller IC XDP[™] Digital Power** **==> picture [105 x 47] intentionally omitted <==** ## **Table of contents** |**6**|**Package Dimensions**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41| |---|---| |**7**|**References**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42| ||**Revision History**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42| ||**Glossary**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42| ||**Disclaimer**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45| Datasheet Revision 1.0 2018-06-06 4 **XDPL8218 Digital Flyback Controller IC XDP[™] Digital Power** **==> picture [105 x 47] intentionally omitted <==** ## **Pin configuration** ## **1 Pin configuration** Pin assignments and basic pin description information are shown below. ||||||||||| |---|---|---|---|---|---|---|---|---|---| |ZCD||||1|8||||GND| ||||||||||| |FB||||2|7||||VCC| ||||||||||| |CS||||3|6||||UART| ||||||||||| |GD||||4|5||||HV| ||||||||||| ||||PG-DSO-8||(150mil)||||| ## **Figure 2 Pinning of XDPL8218** ## **Table 1 Pin definitions and functions** |**Name**|**Pin**|**Type**|**Function**| |---|---|---|---| |_ZCD_|1|I|Zero-crossing detection:<br>The_ZCD_pin is connected to the transformer auxiliary winding via external<br>resistors divider. It is used for zero-crossing detection, primary-side output<br>voltage sensing and input voltage sensing| |_FB_|2|I|Secondary Side Feedback:<br>The_FB_pin is used as a feedback pin for**_SSR_**.| |_CS_|3|I|Current sensing:<br>The_CS_pin is used for Flyback MOSFET current sensing via external shunt<br>resistor| |_GD_|4|O|Gate driver:<br>The_GD_pin is used for Flyback MOSFET gate drive control via external series<br>resistor.| |_HV_|5|I|High voltage:<br>The_HV_pin is connected to the rectified input voltage via external series<br>resistor. The_HV_pin is used to charge_VCC_pin voltage during startup and<br>protection, via an internal 600 V startup cell. In addition, it is also used for<br>line synchronization.| |_UART_|6|I/O|**_Universal Asynchronous Receiver Transmitter (UART)_**configuration:<br>The_UART_pin is used as the digital interface for IC parameter configuration.| |_VCC_|7|I|Operating voltage supply and sensing| |_GND_|8|-|**_Integrated Circuit (IC)_**grounding| Datasheet Revision 1.0 2018-06-06 5 **XDPL8218 Digital Flyback Controller IC XDP[™] Digital Power** **==> picture [105 x 47] intentionally omitted <==** ## **Functional block diagram** ## **2 Functional block diagram** The functional block diagram shows the basic data flow from input pins via signal processing to the output pins. **==> picture [318 x 211] intentionally omitted <==** **----- Start of picture text -----**<br> Flyback (with PFC)<br>Input Voltage<br>VCC Charging Estimation<br>Line<br>HV ZCD<br>synchronization<br>VCC VCC Output Voltage Output Current CS<br>Management Estimation Estimation<br>UART PFC and THD<br>UART GD<br>Parametrization correction<br>Feedback<br>Temperature Multimode<br>Protection Controller Sensing & FB<br>Filter<br>**----- End of picture text -----**<br> **Figure 3 XDPL8218 functional block diagram** Datasheet Revision 1.0 2018-06-06 6 **XDPL8218 Digital Flyback Controller IC XDP[™] Digital Power** **==> picture [105 x 47] intentionally omitted <==** ## **Functional description** ## **3 Functional description** The functional description provides an overview about the integrated functions and features as well as their relationship. The mentioned parameters and equations are based on typical values at _T_ A = 25°C. The corresponding min. and max. values are shown in the electrical characteristics. ## **3.1 Regulated mode** In regulated mode, the _FB_ pin voltage is periodically sampled and digitally filtered. Based on the filtered feedback voltage _V_ FB,filtered mapping, the mode of operation ( _**QRM1**_ , _**DCM**_ or _**ABM**_ ) and the respective switching parameters (on-time, minimum switching period, pulse number) are selected. Whenever the regulated mode is entered after the startup phase, the filtered feedback voltage maximum limit _V_ FB,filtered,max ramp is applied initially on the voltage mapping to prevent excessive output rise overshoot. ## _**FB**_ **pin voltage sampling** To have a high signal-to-noise ratio, the _FB_ pin voltage is sampled instantly after the leading edge blanking time _t_ CS,LEB, with the sampling rate based on the mode of operation. - _**QRM1**_ / _**DCM**_ : - With the line synchronization established, the _FB_ pin voltage is sampled 64 times per the synchronized AC input half sine wave period. For instance, with AC input frequency of 50 Hz, the synchronized half sine wave period should be approximately 10 ms. If the line synchronization is not established while operating in these modes, for example with DC input, the sampling rate would be 64 times per 9.823 ms. - • _**ABM**_ : - During _**ABM**_ sleep, the _FB_ pin voltage cannot be sampled as the _FB_ pin internal pull-up is deactivated in power saving mode PSMD2. During _**ABM**_ active time, the pull-up is re-enabled at a timing (based on _n_ wakeup parameter) before the start of both burst pulsing and _FB_ pin voltage sampling. If the line synchronization was established before _**ABM**_ entering, the sampling rate during burst pulsing would be 64 times per the last synchronized AC input half sine wave period. Otherwise, it would be 64 times per 9.823 ms. ## **Feedback voltage filtering** The filtering of the sampled feedback voltage depends on the mode of operation: - _**QRM1**_ / _**DCM**_ : After the controller is synchronized to the AC input half sine wave period for at least a duration based on _n_ notch,blank parameter, the sampled feedback voltage is processed by a digital notch-filter with quality factor based on _N_ quality parameter, to suppress the double AC input frequency component of the feedback voltage. The notch filter has a transfer function of: **==> picture [200 x 37] intentionally omitted <==** ## **Equation 1** Whenever the condition above for notch filter activation is not met, the sampled feedback voltage is processed by a digital low pass filter. This low pass filter reduces the high frequency component, but cannot suppress the double AC input frequency component of the feedback voltage. • _**ABM**_ : - In this mode, the sampled feedback voltage is processed by a digital low pass filter during the _**ABM**_ burst pulsing, to reduce the high frequency component. ## **Filtered feedback voltage mapping** _**Figure 4**_ shows how the filtered feedback voltage VFB,filtered is mapped to the mode of operation ( _**QRM1**_ , _**DCM**_ , _**ABM**_ ) and switching parameters (on-time, minimum switching period, pulse number). Datasheet Revision 1.0 2018-06-06 7 **XDPL8218 Digital Flyback Controller IC XDP[™] Digital Power** **==> picture [105 x 47] intentionally omitted <==** ## **Functional description** **==> picture [467 x 255] intentionally omitted <==** **----- Start of picture text -----**<br> nABM ton<br>tsw,ABM tsw,DCM tsw,QR1 ton<br>ABM DCM QRM1<br>1/fsw,min<br>(20kHz typ.)<br>nABM,max ≈ fsw,min/fburst<br>(20kHz typ.)<br>ton,max(Vin)<br>1/fsw,max<br>ton,min(Vin)<br>ton,min,ABM<br>nABM,min<br>VFB,filtered<br>VFB,min VFB,on VFB,sw VREF<br>(1.2V typ.) (2.0V typ.) (2.428V typ.)<br>VFB,ABM VFB,max,map<br>(0.8V typ.)<br>**----- End of picture text -----**<br> **Figure 4 Filtered feedback voltage mapping** _Note: With the enhanced_ _**PFC** feature enabled and V_ FB,filtered _being stable, in_ _**QRM1** and_ _**DCM** , the V_ FB,filtered _mapped on-time is not constant, but modulated with a function based on the estimated input voltage V_ in _, estimated output voltage V_ out _, estimated output current, phase angle and a gain parameter named C_ EMI _. For more details, see_ _**Power factor correction** ._ - _**QRM1**_ : - This mode maximizes the efficiency by switching on the MOSFET at the 1[st] valley of the primary auxiliary winding voltage _V_ AUX, as shown in _**Figure 5**_ . When _V_ FB,filtered is _V_ FB,on (1.2 V) or more, and its corresponding minimum switching period (based on the purple curve in _**Figure 4**_ ) is lower than the system 1[st] valley switching period _t_ sw,QR1 (see cyan curve in _**Figure 4**_ as an example), the controller operates in _**QRM1**_ and the power transfer is controlled by regulating the on-time. **==> picture [222 x 159] intentionally omitted <==** **----- Start of picture text -----**<br> VGD<br>time<br>t on<br>VAUX tsw,QR1<br>Zero crossing<br>detection<br>0 V time<br>Valley<br>switching<br>**----- End of picture text -----**<br> **Figure 5 Switching waveforms in QRM1** - _**DCM**_ : This mode switches on the MOSFET after the 1[st] valley of the primary auxiliary winding voltage _V_ AUX, as shown in _**Figure 6**_ . Datasheet Revision 1.0 2018-06-06 8 **XDPL8218 Digital Flyback Controller IC XDP[™] Digital Power** **==> picture [105 x 47] intentionally omitted <==** ## **Functional description** When _V_ FB,filtered is between _V_ FB,ABM (0.8 V) and _V_ FB,on (1.2 V), the _**DCM**_ power transfer is controlled by regulating the switching period(frequency), with minimum on-time of _t_ on,min _(V_ in _)_ which is adapted based on the estimated input voltage _V_ in. When _V_ FB,filtered is _V_ FB,on (1.2 V) or more, and its corresponding minimum switching period (based on the purple curve in _**Figure 4**_ ) is higher than the system 1[st] valley switching period _t_ sw,QR1 (see cyan curve in _**Figure 4**_ as an example), the controller operates in _**DCM**_ and the power transfer is controlled by regulating the on-time and switching period(frequency). • **==> picture [245 x 174] intentionally omitted <==** **----- Start of picture text -----**<br> VGD<br>time<br>ton<br>VAUX tsw,DCM<br>0 V time<br>**----- End of picture text -----**<br> ## **Figure 6 Switching waveforms in DCM** - _**ABM**_ : During _**DCM**_ or _**QRM1**_ , if _V_ FB,filtered is below _V_ FB,ABM (0.8 V) for at least a duration based on _t_ blank,ABM parameter, the controller enters _**ABM**_ . In _**ABM**_ , the switching period _t_ sw,ABM is fixed to a maximum value (50 μs) based on _f_ sw,min (20 kHz), while the burst frequency is fixed based on _f_ burst parameter to minimize the audible noise. The power transfer in _**ABM**_ is controlled by regulating the pulse number and the on-time, based on _V_ FB,filtered taken at the last pulse of previous burst cycle, as shown in _**Figure 7**_ . If _V_ FB,filtered exceeds _V_ FB,ABM (0.8 V), the controller enters _**DCM**_ or _**QRM1**_ . **==> picture [336 x 174] intentionally omitted <==** **----- Start of picture text -----**<br> VFB VFB,filtered ton = α<br>nABM = 4 ton = β<br>nABM = 3 ton = γ<br>nABM = 2<br>wake wake wake wake<br>sleep sleep sleep sleep<br>up up up up<br>1/fburst 1/fburst 1/fburst t<br>VGD<br>1/fsw,min 1/fsw,min 1/fsw,min 1/fsw,min<br>ton = α ton = β ton = γ<br>nABM = 4 nABM = 3 nABM = 2<br>t<br>Approx. Approx. Approx. Approx.<br>nwakeup nwakeup nwakeup nwakeup<br>x 19 µs x 19 µs x 19 µs x 19 µs<br>**----- End of picture text -----**<br> ## **Figure 7 Switching waveforms in ABM** When _V_ FB,filtered is _V_ FB,min or lower, the power transfer is minimum with ABM minimum on-time _t_ on,min,ABM and minimum number of pulses per burst cycle _n_ ABM,min being applied. As _t_ on,min,ABM could be too short to ensure sufficient transformer demagnetization time, the output and input voltages may not be reflected and sensed correctly via _ZCD_ pin. Hence, the output voltage protections are not available in _**ABM**_ and the input voltage protections can optionally be enabled using _EN_ Vin,ABM parameter. Datasheet Revision 1.0 2018-06-06 9 **XDPL8218 Digital Flyback Controller IC XDP[™] Digital Power** **==> picture [105 x 47] intentionally omitted <==** ## **Functional description** ## **On-time limits adaptation based on estimated input voltage** In _**DCM**_ and _**QRM1**_ , _t_ on,min,V,out,sense _(V_ in _)_ variable is scaled to allow a desired minimum transformer demagnetization time based on _t_ min,demag parameter at the peak of input voltage _V_ in,peak for output voltage sensing up to the output overvoltage level parameter _V_ outOV via _ZCD_ pin. _N V t V_ = _t p_ outOV on, min, _V_ , out, sense in min, demag ⋅ _Ns_[⋅] _V_ in, peak ## **Equation 2** In _**DCM**_ and _**QRM1**_ , the minimum on-time of _t_ on,min _(V_ in _)_ in _**Figure 4**_ is based on _t_ on,min parameter or _t_ on,min,V,out,sense _(V_ in _)_ variable, whichever is higher, as shown in _**Figure 8**_ . _t_ on > _t_ on, min _V_ in = max _t_ on, min, _V_ , out, sense _V_ in , _t_ on, min ## **Equation 3** In _**DCM**_ and _**QRM1**_ , for estimated input voltage _V_ in between lowest operational input voltage parameter _V_ in,low and input overvoltage protection level parameter _V_ inOV, the maximum on-time of _t_ on,max _(V_ in _)_ in _**Figure 4**_ is scaled to compensate the influence of input voltage on feedback gain, based on: _V t_ on < _t_ on, max _V_ in = _t_ on, max, at, _V_ , in, low ⋅ in _V_ , low in ## **Equation 4** Also, in _**DCM**_ and _**QRM1**_ , for estimated input voltage _V_ in below _V_ in,low, the maximum on-time of _t_ on,max _(V_ in _)_ in _**Figure 4**_ is scaled based on the maximum on-time foldback gain parameter _P_ foldback,gain, for power limitation during brown-out. **==> picture [512 x 298] intentionally omitted <==** **----- Start of picture text -----**<br> V V<br>t on < t on, max V in = t on, max, at, V , in, low ⋅ 1 − P foldback, gain ⋅ in V , low − in<br>in, low<br>Equation 5<br>ton,max(Vin) ton,min(Vin)<br>ton,min,V,out,sense(Vin)<br>ton,max,at,V,in,low Pfoldback,gain =0<br>Pfoldback,gain =1<br>Pfoldback,gain >1<br>ton,min<br>0 VinUV Vin,low VinOV Vin<br>**----- End of picture text -----**<br> **Figure 8 On-time limit adaptation based on estimated input voltage** Datasheet Revision 1.0 2018-06-06 10 **XDPL8218 Digital Flyback Controller IC XDP[™] Digital Power** **==> picture [105 x 47] intentionally omitted <==** ## **Functional description** _Note: t_ on,min _(V_ in _) and t_ on,max _(V_ in _) are adapted once per half sine wave period. The half sine wave period is either 9.823 ms or the inverse of the rectified AC input frequency, based on the operation conditions, as explained in_ _**Line synchronization** ._ ## **Minimum switching period based on filtered feedback voltage** In _**DCM**_ and _**QRM1**_ , the minimum switching period or maximum switching frequency is not constant but dependent on the filtered feedback voltage _V_ FB,filtered, as shown in the purple curve in _**Figure 4**_ . _f_ sw,max parameter denotes the maximum switching frequency when _V_ FB,filtered is same as or higher than than _V_ FB,sw (2.0 V). When _V_ FB,filtered is increased from _V_ FB,ABM (0.8 V) to _V_ FB,sw (2.0 V), the minimum switching period reduces from 1/ fsw,min (50 μs) to 1/ _f_ sw,max. During this change, the _**DCM**_ switching period _t_ sw,DCM follows the minimum switching period, and the transition from _**DCM**_ to _**QRM1**_ occurs when the minimum switching period becomes lower than the system _1_[st] valley switching period _t_ sw,QR1. ## **MOSFET maximum current cycle by cycle limit adaptation based on estimated input voltage** For estimated input voltage _V_ in between the lowest operational input voltage parameter _V_ in,low and highest operational input voltage parameter _V_ in,high, the regulated mode _CS_ voltage level 1 for MOSFET maximum current cycle by cycle limit _V_ OCP1 _(V_ in _)_ is scaled between _V_ OCP1,at,V,in,low and _V_ OCP1,at,V,in,high parameters based on: |_V_OCP1<br>_V_in<br>=_V_OCP1 , at,_V_, in, low−<br>_V_OCP1 , at,_V_, in, low−_V_OCP , at,_V_, in, high<br>⋅|_V_in −_V_in,low| |---|---| ||_V_in, high −_V_in, low| ## **Equation 6** For estimated input voltage _V_ in below _V_ in,low and above _V_ in,high, _V_ OCP1 _(V_ in _)_ is _V_ OCP1,at,V,in,low and _V_ OCP1,at,V,in,high respectively. When _V_ FB,filtered is same as or higher than _V_ FB,max,map parameter in _**Figure 4**_ , the power transfer is maximum, with the primary peak current based on maximum on-time of _t_ on,max _(V_ in _)_ or _CS_ voltage limit of _V_ OCP1 _(V_ in _)_ . By configuring _V_ OCP1,at,V,in,high lower than _V_ OCP1,at,V,in,low, as shown in _**Figure 9**_ , the maximum output power can be better limited at high input voltage. **==> picture [206 x 116] intentionally omitted <==** **----- Start of picture text -----**<br> VOCP1(Vin)<br>VOCP1,at,V,in,low<br>VOCP1,at,V,in,high<br>Vin,low Vin,high Vin<br>**----- End of picture text -----**<br> ## **Figure 9 Adaptive CS pin voltage level 1 for MOSFET maximum current cycle by cycle limit based on estimated input voltage** _Note: A typical leading edge blanking time t_ CS,LEB _of 480 ns applies on V_ OCP1 _(V_ in _)._ _Note: V_ OCP1 _(V_ in _) is adapted once per half sine wave period. The half sine wave period is either 9.823 ms or the inverse of the rectified AC input frequency, based on the operation conditions, as explained in_ _**Line synchronization** ._ Datasheet Revision 1.0 2018-06-06 11 **XDPL8218 Digital Flyback Controller IC XDP[™] Digital Power** **==> picture [105 x 47] intentionally omitted <==** ## **Functional description** ## **Feedback voltage maximum limit** Whenever the regulated mode is entered, the filtered feedback voltage maximum limit _V_ FB,filtered,max is ramped up from _V_ FB,limit,start (1.2 V) to _V_ REF (2.428 V), with incremental voltage step based on _V_ FB,limit,step parameter and time step based on the half sine wave period. _Note: The half sine wave period is either 9.823 ms or the inverse of the rectified AC input frequency, based on the operation conditions, as explained in_ _**Line synchronization** ._ As shown in _**Figure 10**_ , when _V_ FB,filtered is higher than _V_ FB,filtered,max initially in the regulated mode entering, the feedback voltage mapping is based on _V_ FB,filtered,max ramp, in order to prevent excessive output rise overshoot during startup. When _V_ FB,filtered gets lower than _V_ FB,filtered,max, the feedback voltage mapping is then based on _V_ FB,filtered. **==> picture [334 x 160] intentionally omitted <==** **----- Start of picture text -----**<br> Voltage<br>Regulated mode entering<br>VREF Filtered feedback voltage max. limit<br>(2.428V typ.) VFB,filtered,max<br>Filtered feedback voltage<br>VFB,filtered<br>VFB,limit,start VFB,limit,step<br>(1.2V typ.)<br>half sine<br>wave period<br>time<br>Feedback voltage mapping<br>based on VFB,filtered,max<br>(when VFB,filtered > VFB,filtered,max)<br>**----- End of picture text -----**<br> ## **Figure 10 Feedback voltage maximum limit** ## **3.2 Configurable gate voltage rising slope at GD pin** The gate drive peak voltage _V_ GD,pk is 12 V with sufficient Vcc voltage supply. To achieve a good balance of switching loss and _**Electro-Magnetic Interference (EMI)**_ , the gate voltage rising slope which determines the MOSFET switching on speed can be controlled, by configuring the gate driver peak source current _I_ GD,pk parameter (Configurable range: 30 mA to 180 mA). This saves two components (see _D_ fastoff, _R_ slowon in _**Figure 11**_ ), which are conventionally added for the same purpose. **==> picture [437 x 133] intentionally omitted <==** **----- Start of picture text -----**<br> VGD<br>Dfastoff<br>VGD,pk<br>(12V typ.)<br>IGD,pk GD RG Rslowon<br>=118mA<br>Not needed<br>IGD,pk RCS<br>= 30mA<br>t<br>**----- End of picture text -----**<br> **Figure 11 Configurable gate voltage rising slope and component saving** Datasheet Revision 1.0 2018-06-06 12 **XDPL8218 Digital Flyback Controller IC XDP[™] Digital Power** **==> picture [105 x 47] intentionally omitted <==** ## **Functional description** ## **3.3 Startup** The startup phase is entered upon checking the startup conditions (e.g. input voltage, _**IC**_ temperature) are within limits. During the startup phase, the soft start phase is initiated and followed by the output charging phase. After the startup phase is ended without any protection triggering, the regulated mode is entered for output regulation based on the feedback voltage mapping. To estimate the input voltage level before startup, _ZCD_ pin signal is measured during a single pulse generated on GD pin. This single pulse has an on-time based on the pre-start _CS_ pin maximum voltage limit of _V_ OCP1,init or 8 times of the leading edge blanking time _t_ CS,LEB (e.g. 8 * 480 ns = 3.84 μs typ.). If the estimated input voltage or any other startup conditions are not within limits, startup phase is not entered and this single pulse will be generated again after an auto-restart duration. The startup phase consists of soft start phase and output charging phase. The soft start phase is to minimize the component stress during startup, while the output charging phase is to fast charge the output voltage for fast _VCC_ voltage self supply takeover from the primary auxiliary winding. **==> picture [434 x 205] intentionally omitted <==** **----- Start of picture text -----**<br> Voltage Startup phase Regulated Mode<br>Output<br>Soft start phase Vout<br>charging<br>(based on nss = 3 configuration as example)<br>phase<br>Vout,start<br>VoutUV,start Start of regulation according to<br>feedback voltage mapping<br>VOCP1(Vin)<br>CS pin voltage level 1 for MOSFET<br>Pre-Startup Check max current cycle by cycle limit<br>(e.g. input voltage,<br>IC temperature) Vstart,OCP1<br>VOCP1,init<br>Startup with 1 [st]<br>soft start step<br>time<br>0 tSS 2 tSS 3 tSS tout,charge tstart,max<br>(0.5ms typ.) (1.0ms typ.) (1.5ms typ.)<br>**----- End of picture text -----**<br> ## **Figure 12 Startup phase with soft start step nss=3** During soft start phase, the switching frequency is fixed as 20 kHz. The MOSFET current is limited in the first soft start step based on _CS_ pin maximum voltage limit of _V_ start,OCP1/( _n_ ss + 1), where _V_ start,OCP1 is the parameter for the output charging phase _CS_ pin maximum voltage limit and _n_ ss is the parameter for the number of soft start steps. The soft start phase CS pin maximum voltage limit is increased by _V_ start,OCP1/( _n_ ss + 1) after each soft start step until _V_ start,OCP1 is reached, and the typical duration of each soft start step is 0.5 ms. During output charging phase, the output voltage is fast charged with MOSFET switching pulses based on either the output charging phase _CS_ pin maximum voltage limit of _V_ start,OCP1 or the maximum on time of _t_ on,max _(V_ in _)_ in _**QRM1**_ . To exit the startup phase and enter the regulated mode without triggering the startup output undervoltage protection, the _ZCD_ pin estimated output voltage _V_ out has to either reach the output charging voltage set-point of _V_ out,start before the maximum allowable startup phase duration of _t_ start,max is reached (see example in _**Figure 12**_ ), or reach at least the startup output undervoltage protection level of _V_ outUV,start at the timing of _t_ start,max. _t_ start,max parameter can be indirectly configured with _VCC_ capacitance parameter _C_ VCC, based on: _t_ start, max = 967 ⋅ _C_ VCC ## **Equation 7** Datasheet Revision 1.0 2018-06-06 13 **XDPL8218 Digital Flyback Controller IC XDP[™] Digital Power** **==> picture [105 x 47] intentionally omitted <==** ## **Functional description** _Note: A typical leading edge blanking time t_ CS,LEB _of 480 ns applies on V_ OCP1,init _, V_ start,OCP1 _and the CS pin maximum voltage limit for every soft start step starting from V_ start,OCP1 _/(n_ ss _+ 1)._ ## **3.4 Line synchronization** In _**QRM1**_ and _**DCM**_ , the XDPL8218 synchronizes most of its operation to the AC input half sine wave period or the rectified AC input frequency, via the _HV_ pin. For instance, based on AC input frequency of 50 Hz, the line synchronization should be based on the rectified AC input frequency of 100 Hz or AC input half sine wave period of 10 ms. Such line synchronization is necessary for the digital notch filter in suppressing the double AC input frequency component of the feedback voltage, to achieve good _**PFC**_ . It is also used for the enhanced _**PFC**_ in compensating the input current displacement caused by the line filter and DC link filter capacitor. If the line synchronization is not established while operating in these modes, for example with DC input or during startup, the controller would synchronize its operation based on an internally preset half sine wave period of approximately 9.823 ms. Line synchronization is not possible while the controller operates in _**ABM**_ , due to the sleep mode entering for power saving. In _**ABM**_ , the controller would synchronize its operation based on an internally preset half sine wave period of approximately 9.823 ms. _**Attention** :_ _**For proper line synchronization, the VCC voltage needs to be below V**_ **SELF** _**, while the AC input should be a stable sine wave with frequency between 45 Hz and 66 Hz. Additionally, the rectified AC input connected to the HV pin via external resistor also should not have excessive noise.**_ ## **3.5 Input voltage and output voltage estimation** XDPL8218 estimates the input voltage and output voltage based on the _ZCD_ pin switching signal. As shown in the waveform example in _**Figure 13**_ , the transformer primary auxiliary winding voltage _V_ AUX contains information on the reflected input voltage and reflected output voltage, which can be measured at _ZCD_ pin using a resistor divider. Datasheet Revision 1.0 2018-06-06 14 **XDPL8218 Digital Flyback Controller IC XDP[™] Digital Power** **==> picture [105 x 47] intentionally omitted <==** ## **Functional description** **==> picture [449 x 432] intentionally omitted <==** **----- Start of picture text -----**<br> VAUX<br>Tosc Tosc<br>4 4<br>Reflected output<br>voltage sampling<br>1 [st] Zero crossing detection<br>0 V<br>Reflected input 1 [st] Valley switching<br>voltage sampling<br>Ip Is<br>time<br>Np Ns<br>tCS,sample tZCD,sample<br>Itransformer<br>tsw,QR1<br>Ip,pk<br>VAUX Na<br>Ip Ip<br>Is<br>time<br>tdemag<br>VGD<br>time<br>**----- End of picture text -----**<br> **Figure 13 Flyback switching waveform example in QRM1** ## **3.5.1 Output voltage estimation** The output voltage is estimated by sensing the reflected output voltage signal from the transformer primary auxiliary winding voltage _V_ AUX, when the MOSFET is switched off and near the end of transformer demagnetization. A resistor divider with _R_ ZCD,1 and _R_ ZCD,2 adapts the voltage at _ZCD_ pin based on its operational range, while a _ZCD_ pin filter capacitor _C_ ZCD is needed for noise filtering, as shown in _**Figure 14**_ . Based on the sampled _ZCD_ pin voltage _V_ ZCD,SH at the timing of tZCD,sample shown in _**Figure 13**_ , which is approximately a quarter of oscillation period ( _T_ osc/4) before the 1[st] zero crossing of _V_ AUX, a ratio of the reflected output voltage signal from _V_ AUX is sensed. The interval of each _V_ ZCD,SH sampling is approximately 1/64 of the half sine wave period, while the oscillation period _T_ osc is measured once before startup and updated every 7[th] half sine wave period after entering the regulated mode. _Note: The half sine wave period is either 9.823 ms or the inverse of the rectified AC input frequency, based on the operating conditions, as explained in_ _**Line synchronization** ._ Datasheet Revision 1.0 2018-06-06 15 **XDPL8218 Digital Flyback Controller IC XDP[™] Digital Power** **==> picture [105 x 47] intentionally omitted <==** ## **Functional description** _Note: As V_ AUX _zero crossing can only be detected by the_ _**IC** via ZCD pin upon its internal analog delay plus external delay caused by C_ ZCD _, t_ ZCDPD _parameter fine-tuning is needed to compensate such delays, to have the proper timing of t_ ZCD,sample _for output voltage estimation._ _**Attention** :_ _**Please note that the transformer demagnetization time t**_ **demag** _**has to be longer than 2.0**_ **μ** _**s to ensure that the reflected output voltage can be sensed properly at the ZCD pin.**_ The estimated output voltage _V_ out is based on: |_V_out=_V_ZCD, SH⋅|_R_ZCD,1 +_R_ZCD,2<br>_R_ZCD, 2<br>⋅<br>_Ns_<br>_Na_ −_Vd_| |---|---| ## **Equation 8** Where _N_ s is the transformer secondary main winding turns, _N_ a is the transformer primary auxiliary winding turns and _V_ d is the secondary main output diode forward voltage (assumed by the controller as 0.7 V). **==> picture [268 x 97] intentionally omitted <==** **----- Start of picture text -----**<br> Vd<br>Na Ns<br>RZCD,1 Cout Vout<br>ZCD VAUX<br>CZCD VZCD,SH RZCD,2<br>**----- End of picture text -----**<br> ## **Figure 14 Output voltage estimation based on** _**V**_ **ZCD,SH** The estimated output voltage _V_ out is used for output voltage protections and the enhanced _**PFC**_ (EPFC). Therefore, it is important to ensure that _**IC**_ parameters _R_ ZCD,1, _R_ ZCD,2, _N_ s and _N_ a are configured as per the actual system hardware dimensioning. _**Attention** :_ _**Output voltage estimation and its related protections are not available while the controller operates in ABM. As an indirect overvoltage protection for the output, the VCC overvoltage protection can be used.**_ ## **3.5.2 Input voltage estimation** The input voltage is estimated by sensing the reflected input voltage signal from the transformer primary auxiliary winding voltage _V_ AUX, when the MOSFET is switched on. As the reflected input voltage signal is a negative voltage which cannot be sensed directly, the voltage at _ZCD_ pin is clamped to a negative voltage of _V_ INPCLN. A resistor divider with _R_ ZCD,1 and _R_ ZCD,2 adapts _-I_ IV which is the clamping current flowing out of _ZCD_ pin, based on its operational range, while a _ZCD_ pin filter capacitor _C_ ZCD is needed for noise filtering, as shown in _**Figure 15**_ . Based on the sampled clamping current _-I_ IV at the timing of _t_ CS,sample shown in _**Figure 13**_ , which is at the end of on-time, the reflected input voltage signal from _V_ AUX is sensed. The interval of each _-I_ IV sample is approximately 1/64 of the half sine wave period. _Note: The half sine wave period is either 9.823 ms or the inverse of the rectified AC input frequency, based on the operation conditions, as explained in_ _**Line synchronization** ._ The estimated peak input voltage _V_ in,peak over a half sine wave period is based on: Datasheet Revision 1.0 2018-06-06 16 **XDPL8218 Digital Flyback Controller IC XDP[™] Digital Power** ## **Functional description** |_V_in, peak|in, peak= max|= max|= max|_Np_<br>_Na_|⋅<br>−_I_IV−|−|_V_INPCLN<br>_R_ZCD, 2|⋅_R_ZCD, 1−_V_INPCLN|+|_R_in<br>_R_CS ⋅_V_CS, peak| |---|---|---|---|---|---|---|---|---|---|---| ## **Equation 9** Where _N_ p is the primary main winding turns, _N_ a is the primary auxiliary winding turns, _R_ CS is the _CS_ pin shunt resistor value, _V_ CS,peak is the peak _CS_ pin voltage, and _R_ in is the fine-tuning parameter for input voltage sensing accuracy improvement by compensating the switching frequency voltage ripple on _C_ DC,filter. Regardless of the actual input voltage is AC or DC, the estimated input voltage _V_ in in rms value is assumed by the controller as 0.707 of _V_ in,peak. The update rate of _V_ in is once per half sine wave period. **==> picture [511 x 171] intentionally omitted <==** **----- Start of picture text -----**<br> V ⋅ V<br>in = 0.707 in, peak<br>|<br>Equation 10<br>Na Np VDC,filter<br>V in,peak<br>V in<br>ZCD IIV RZCD,1 VDC,filter CDC,filter<br>VAUX<br>CZCD RZCD,2 RG GD<br>VINPCLN<br>“+4 ft t r aaa<br>RCS VCS<br>T I th.<br>**----- End of picture text -----**<br> ## **Figure 15 Input voltage estimation based on** _**-I**_ **IV** The estimated input voltage _V_ in is used for input voltage protections and the enhanced _**PFC**_ (EPFC). Therefore, it is important to ensure that _**IC**_ parameters _R_ ZCD,1, _R_ ZCD,2, _N_ p, _N_ a and _R_ CS are configured as per the actual system hardware dimensioning. ## _**Attention** :_ _**Input voltage protections in ABM can optionally be enabled using EN**_ **Vin,ABM** _**parameter.**_ ## **3.6** ## **Power factor correction** Upon the line synchronization is established in _**QRM1**_ and _**DCM**_ for at least a duration based on _n_ notch,blank parameter, the double AC input frequency component of the feedback voltage is suppressed by the digital notch filter, to achieve good _**PFC**_ , while regulating the output based on Voltage Mode Control. The notch filter quality factor is based on _N_ quality parameter. For better _**PFC**_ , the patented enhanced _**PFC**_ (EPFC) feature can be enabled by configuring _C_ EMI parameter value above zero and fine-tuning the value, to compensate the input current displacement effect which is mainly caused by the DC link filter capacitor _C_ DC,filter. With this feature enabled and _V_ FB,filtered being stable, in _**QRM1**_ and _**DCM**_ , the _V_ FB,filtered mapped on-time is not constant, but modulated with a function based on the estimated input voltage _V_ in, estimated output voltage _V_ out, estimated output current, phase angle and modulation gain of _C_ EMI parameter value. The enhanced _**PFC**_ (EPFC) feature can also be disabled by configuring _C_ EMI parameter as zero. Datasheet Revision 1.0 2018-06-06 17 **XDPL8218 Digital Flyback Controller IC XDP[™] Digital Power** **==> picture [105 x 47] intentionally omitted <==** ## **Functional description** ## **3.7 Protection features** Protections ensure the operation of the controller under restricted conditions. The protection monitoring signal(s) sampling rate, protection triggering condition(s) and protection reaction are described in this section. - _**Attention** :_ _**The sampled protection monitoring signal accuracy is subjective to the digital quantization, tolerances of components (including IC) and estimations with indirect sensing (e.g. input and output voltage estimations based on ZCD, CS pin signals), while the protection level triggering accuracy is subjective to the sampled signal accuracy, sampling delay, indirect sensing delay (e.g. reflected output voltage signal cannot be sensed by ZCD pin near AC input phase angle of 0° and 180°) and blanking time.**_ ## **3.7.1 Primary MOSFET overcurrent protection** _V_ OCP2 denotes the _CS_ pin voltage level 2 for primary MOSFET overcurrent protection. Under the single fault condition of shorted primary main winding, the primary MOSFET overcurrent protection is triggered when the _CS_ pin voltage exceeds _V_ OCP2 for longer than a blanking time based on _t_ CSOCP2 parameter. The level of _V_ OCP2 is automatically selected out of 0.6 V, 0.8 V, 1.2 V and 1.6 V, whichever is higher than and the closest to the _V_ OCP1,at,V,in,low parameter value. The reaction of primary MOSFET overcurrent protection is fixed as auto-restart. ## **3.7.2 Output undervoltage protection** In case of a short or an overload on the output, the output voltage may drop to a low level. The output undervoltage protection can be triggered, if the condition is met by monitoring the estimated output voltage _V_ out based on the _ZCD_ pin switching signal (see _**Output voltage estimation**_ for details). _EN_ UVP,Vout parameter refers to the enable switch for the regulated mode output undervoltage protection. In regulated mode, if _EN_ UVP,Vout parameter is enabled and the estimated output voltage _V_ out is lower than _V_ outUV parameter for longer than a blanking time of _t_ VoutUV,blank parameter, the regulated mode output undervoltage protection is triggered. The reaction of regulated mode output undervoltage protection is configurable to either auto-restart or latch mode based on _Reaction_ UVP,Vout parameter. ## _**Attention** :_ _**Regulated mode output undervoltage protection is not available while the controller operates in ABM.**_ **==> picture [304 x 118] intentionally omitted <==** **----- Start of picture text -----**<br> Vout<br>Output load current<br>too high causing<br>power limit and<br>Output setpoint<br>Start of regulation Vout drop below<br>according to feedback set-point Output under-<br>voltage mapping voltage protection<br>Vout,start triggered after<br>VoutUV tVoutUV,blank<br>Turn-on<br>time<br>Startup Regulated Mode Regulated Mode<br>phase (Vout > VoutUV) (Vout < VoutUV for tVoutUV,blank)<br>**----- End of picture text -----**<br> ## **Figure 16 Regulated mode output undervoltage protection** In startup phase, if the estimated output voltage _V_ out is lower than _V_ outUV,start parameter over a timeout period of _t_ start,max parameter, the startup output undervoltage protection is triggered. _t_ start,max parameter refers to the maximum allowable duration of the startup phase, which consists of soft-start phase and output charging phase. It can be indirectly configured with _VCC_ capacitance parameter _C_ VCC, based on _**Equation 7**_ . The reaction of startup output undervoltage protection is fixed as auto-restart. Datasheet Revision 1.0 2018-06-06 18 **XDPL8218 Digital Flyback Controller IC XDP[™] Digital Power** **==> picture [105 x 47] intentionally omitted <==** ## **Functional description** **==> picture [486 x 141] intentionally omitted <==** **----- Start of picture text -----**<br> Normal startup Output short startup<br>Voltage Voltage<br>tstart,max tstart,max<br>tout,charge<br>Output setpoint Output setpoint<br>Vout,start Vout Vout,start<br>VoutUV,start VoutUV,start<br>VVCCON VVCCON Startup output undervoltage<br>(20.5V typ.) VVCC (20.5V typ.) VVCC protection triggered<br>(Vout < VoutUV,start ,at tstart,max)<br>VUVOFF VUVOFF<br>(6V typ.) time (6V typ.) V out time<br>tVCCON,charge tVCC,holdup tVCCON,charge tVCC,holdup<br>**----- End of picture text -----**<br> **Figure 17 Normal startup and startup output undervoltage (short) protection waveforms** ## **3.7.3 Output overvoltage protection** In case of _FB_ pin open, the output voltage may rise to a high level. The output overvoltage protection can be triggered, if the condition is met by monitoring the estimated output voltage _V_ out based on the _ZCD_ pin switching signal (see _**Output voltage estimation**_ for details). If the estimated output voltage _V_ out is higher than _V_ outOV for longer than a blanking time, the output overvoltage protection is triggered. The output overvoltage protection blanking time is typically a quarter of the half sine wave period. The reaction of the output overvoltage protection is configurable to auto-restart or latch-mode based on _Reaction_ OVP,Vout parameter. _Note: The half sine wave period is either 9.823 ms or the inverse of the rectified AC input frequency, based on the operating conditions, as explained in_ _**Line synchronization** ._ - _**Attention** :_ _**Output overvoltage protection is not available while the controller operates in ABM.**_ - _**Attention** :_ _**It is mandatory to ensure that V**_ **outOV** _**is configured well below the actual output capacitor voltage rating V**_ **out,cap,rating** _**,while the V**_ **out,cap,rating** _**is not exceeded in actual testing with all the necessary test conditions. The protection level triggering accuracy is subjective to the sampled signal accuracy, sampling delay, indirect sensing delay (e.g. reflected output voltage signal cannot be sensed by ZCD pin near AC input phase angle of 0° and 180°) and blanking time.**_ **==> picture [323 x 160] intentionally omitted <==** **----- Start of picture text -----**<br> Vout<br>VoutOV protection triggered<br>Vout,cap,rating after blanking time<br>VoutOV ReactionOVP,Vout = Auto-restart<br>Output setpoint FB pin Open ReactionOVP,Vout = Latch-Mode<br>Vout,start<br>Start of regulation<br>according to<br>feedback voltage<br>mapping<br>Turn-on<br>time<br>Startup Regulated Mode Auto-restart time<br>phase<br>(based on tauto,restart)<br>**----- End of picture text -----**<br> **Figure 18 Output overvoltage protection** Datasheet Revision 1.0 2018-06-06 19 **XDPL8218 Digital Flyback Controller IC XDP[™] Digital Power** **==> picture [105 x 47] intentionally omitted <==** ## **Functional description** ## **3.7.4 Transformer demagnetization time shortage protection** In case of insufficient transformer demagnetization time, the reflected output voltage signal cannot be properly sensed via the _ZCD_ pin. If such condition presents for longer than 50% of a half sine wave period, the protection will be triggered. The reaction of this protection is fixed as auto-restart. _Note: The half sine wave period is either 9.823 ms or the inverse of the rectified AC input frequency, based on the operating conditions, as explained in_ _**Line synchronization** ._ - _**Attention** :_ _**Transformer demagnetization time shortage protection is not available while the controller operates in ABM.**_ ## **3.7.5 Minimum input voltage startup check and input undervoltage protection** By monitoring the estimated input voltage _V_ in based on the _ZCD_ pin and _CS_ pin switching signals (see _**Input voltage estimation**_ for details), the minimum input voltage startup check can be performed, and the input undervoltage protection can be triggered if the condition is met. _EN_ UVP,In parameter refers to the enable switch for the minimum input voltage startup check (based on _V_ in,start,min) and input undervoltage protection (based on _V_ inUV). _Note: V_ in,start,min _parameter refers to the minimum input voltage level for startup, while V_ inUV _parameter refers to the input undervoltage protection level._ During pre-startup check, if _EN_ UVP,In parameter is enabled and the estimated input voltage _V_ in is lower than _V_ in,start,min, the startup phase will not be entered and the protection reaction of auto-restart will be performed. Upon startup and in the regulated mode, the input undervoltage protection triggering condition depends on the operating mode: - _**QRM1**_ / _**DCM**_ : - If _EN_ UVP,In parameter is enabled and the estimated input voltage _V_ in is lower than _V_ inUV for longer than a blanking time, the input undervoltage protection will be triggered. The blanking time of the input undervoltage protection is typically 10 half sine wave periods. _Note: The half sine wave period is either 9.823 ms or the inverse of the rectified AC input frequency, based on the operating conditions, as explained in_ _**Line synchronization** ._ - _**ABM**_ : - If _EN_ UVP,In parameter is enabled, _EN_ VIN,ABM parameter is enabled and the estimated input voltage _V_ in is lower than _V_ inUV for longer than a blanking time, the input undervoltage protection will be triggered. The blanking time of the input undervoltage protection is typically 10 burst periods. _Note: EN_ VIN,ABM _refers to the enable switch for input voltage protections in Active Burst Mode (ABM)._ The reaction of the input undervoltage protection is fixed as auto-restart. ## **3.7.6 Maximum input voltage startup check and input overvoltage protection** By monitoring the estimated input voltage _V_ in based on the _ZCD_ pin and _CS_ pin switching signals (see _**Input voltage estimation**_ for details), the maximum input voltage startup check can be performed, and the input overvoltage protection can be triggered if the condition is met. _EN_ OVP,In parameter refers to the enable switch for the maximum input voltage startup check (based on _V_ in,start,max) and input overvoltage protection (based on _V_ inOV). Datasheet Revision 1.0 2018-06-06 20 **XDPL8218 Digital Flyback Controller IC XDP[™] Digital Power** **==> picture [105 x 47] intentionally omitted <==** ## **Functional description** _Note: V_ in,start,max _parameter refers to the maximum input voltage level for startup, while V_ inOV _parameter refers to the input overvoltage protection level._ During pre-startup check, if _EN_ OVP,In parameter is enabled and the estimated input voltage _V_ in is higher than _V_ in,start,max, the startup phase will not be entered and the protection reaction of auto-restart will be performed. Upon startup and in the regulated mode, the input overvoltage protection triggering condition depends on the operating mode: - _**QRM1**_ / _**DCM**_ : If _EN_ OVP,In parameter is enabled and the estimated input voltage _V_ in is higher than _V_ inOV for longer than a blanking time, the input overvoltage protection will be triggered. The blanking time of the input overvoltage protection is typically 10 half sine wave periods. _Note: The half sine wave period is either 9.823 ms or the inverse of the rectified AC input frequency, based on the operating conditions, as explained in_ _**Line synchronization** ._ - _**ABM**_ : - If _EN_ OVP,In parameter is enabled, _EN_ VIN,ABM parameter is enabled and the estimated input voltage _V_ in is higher than _V_ inOV for longer than a blanking time, the input overvoltage protection will be triggered. The blanking time of the input overvoltage protection is typically 10 burst periods. _Note: EN_ VIN,ABM _refers to the enable switch for input voltage protections in Active Burst Mode (ABM)_ The reaction of the input overvoltage protection is fixed as auto-restart. ## **3.7.7 VCC undervoltage lockout** The _**Undervoltage Lockout (UVLO)**_ is implemented in the hardware. It ensures the enabling and disabling of the _**IC**_ operation based on the defined thresholds of the operating supply voltage _V_ VCC at the _VCC_ pin. The _**UVLO**_ contains a hysteresis with the voltage thresholds _V_ VCCon for enabling the controller and _V_ UVOFF for disabling the controller. Once the mains input voltage is applied, current flows through an external resistor into the _HV_ pin via the integrated depletion cell and diode to the _VCC_ pin. The controller is enabled once _V_ VCC exceeds the _V_ VCCon threshold and _V_ VCC will then start to drop. For normal startup, _V_ VCC supply should be taken over by either external supply or the self-supply via the auxiliary winding before _V_ VCC drops to _V_ UVOFF. ## **3.7.8 VCC undervoltage protection** In regulated mode, if _EN_ VCC,UVP parameter is enabled and the sampled _VCC_ voltage is lower than the _VCC_ undervoltage protection level _V_ VCC,min for longer than the blanking time of _t_ VCCUV,blank parameter, the _VCC_ undervoltage protection will be triggered. The _VCC_ undervoltage protection reaction is fixed as auto-restart. The _VCC_ voltage is sampled 63 times per half sine wave period. _Note: The half sine wave period is either 9.823 ms or the inverse of the rectified AC input frequency, based on the operating conditions, as explained in_ _**Line synchronization** ._ ## **3.7.9 VCC overvoltage protection** If the sampled _VCC_ voltage is higher than the _VCC_ overvoltage protection level _V_ VCC,max, the _VCC_ overvoltage protection will be triggered. The _VCC_ overvoltage protection reaction is configurable to auto-restart or latchmode based on _Reaction_ VCC,OVP parameter. The _VCC_ voltage is sampled 63 times per half sine wave period. _Note: The half sine wave period is either 9.823 ms or the inverse of the rectified AC input frequency, based on the operating conditions, as explained in_ _**Line synchronization** ._ Datasheet Revision 1.0 2018-06-06 21 **XDPL8218 Digital Flyback Controller IC XDP[™] Digital Power** **==> picture [105 x 47] intentionally omitted <==** ## **Functional description** ## **3.7.10 IC overtemperature protection** If the sampled _**IC**_ junction temperature _T_ j is higher than _T_ critical parameter, the _**IC**_ overtemperature protection will be triggered. The protection reaction is fixed as auto-restart, while the maximum junction temperature for startup and restart _T_ start,max is fixed as 4°C below _T_ critical. The _**IC**_ junction temperature _T_ j is sampled 1 time per half sine wave period. _Note: The half sine wave period is either 9.823 ms or the inverse of the rectified AC input frequency, based on the operating conditions, as explained in_ _**Line synchronization** ._ If _T_ critical is configured above 119°C, the maximum switching frequency parameter _f_ sw,max cannot be configured above 136.4 kHz. If _T_ critical is 119°C or below, the maximum configurable _f_ sw,max value is 180.8 kHz. _**Attention** :_ _**IC lifetime is not guaranteed when operating junction temperature is above 125°C, which is possible if T**_ **critical** _**is configured above 119°C, with temperature sensing tolerance of ± 6°C.**_ **==> picture [193 x 130] intentionally omitted <==** **----- Start of picture text -----**<br> Pout<br>Over-temperature<br>Protection triggered<br>TJ<br>4°C typ.<br>Tstart,max Tcritical<br>**----- End of picture text -----**<br> ## **Figure 19 IC overtemperature protection** ## **3.7.11 Other protections** - A hardware weak pull-up protects against an open _CS_ pin. The reaction of this protection reaction is autorestart. - A firmware watchdog triggers a protection if the ADC hardware cannot provide all necessary information within a defined time period. This may occur if timing requirements for the ADC are exceeded. The reaction of this protection is fast auto-restart. - A hardware watchdog checks correct execution of firmware. A protection is triggered in the event that the firmware does not service the watchdog within a defined period. The reaction of this protection is autorestart. - A hardware parity check triggers a protection if a bit in the memory changes unintentionally. The reaction of this protection is auto-restart. - A firmware _**Cyclic Redundancy Check (CRC)**_ at each startup verifies the integrity of firmware and parameters. The reaction of this protection is stop mode. - A firmware task execution watchdog triggers a protection if the firmware tasks are not executed as expected. The reaction of this protection is auto-restart. - A protection is triggered if the configurable parameter values are empty at startup. The reaction of this protection is stop mode. - A protection is triggered if no reflected input voltage signal sensed from the _ZCD_ pin at startup. The reaction of this protection is stop mode. ## **3.7.12 Protection reactions** The sequence of a protection reaction (not including hardware restart reaction) is as follows: Datasheet Revision 1.0 2018-06-06 22 **XDPL8218 Digital Flyback Controller IC XDP[™] Digital Power** ## **Functional description** **1.** Upon triggering a protection, the gate driver is disabled within a maximum time, which is 1/512 of the half sine wave period. _Note: The half sine wave period is either 9.823 ms or the inverse of the rectified AC input frequency, based on the operating conditions, as explained in_ _**Line synchronization** ._ **2.** The reaction depends on the triggered protection: - In case of latch mode, the application will enter latch mode at this time. No further sequence is done until _VCC_ voltage drops below _V_ UVOFF. - In case of auto-restart reaction, the controller will enter power saving mode PSMD2 with the autorestart time based on _t_ auto,restart parameter. - In case of fast auto-restart reaction, the controller will enter power saving mode PSMD2 with the fast auto-restart time of 0.4 sec. _Note: For latch mode, auto-restart and fast auto-restart reactions, the internal HV startup cell is automatically enabled and disabled during this sequence, in order to keep the VCC voltage between the V_ UVLO _and V_ OVLO _thresholds._ _Note: For stop mode, if there is no external voltage supply for the VCC, the VCC voltage will drain to V_ UVOFF _and a hardware restart will be performed._ **3.** After the (fast) auto-restart time is expired, the controller executes a single discharge pulse of duration _t_ pw. This pulse partially discharges the capacitance after the bridge rectifier to improve accuracy of the next prestartup input voltage check. **4.** Any auto restart may include a new _VCC_ charging cycle. The recharging time of _VCC_ via _HV_ pin current depends on the input voltage level and _VCC_ level at the time when the (fast) auto-restart time is expired. **5.** The power stage will enable its gate driver for pre-startup check. If the conditions for pre-startup check are within limits, the startup phase is entered and followed by the regulated mode. During this time, if any protection is triggered, the sequence of a protection reaction (not including hardware restart reaction) starts again from step number 1 above. ## **3.8 Debug mode** If an unexpected system protection was triggered during testing, the _Debug_ Mode parameter can be enabled to enter stop mode reaction upon the protection triggering (except for _VCC_ undervoltage lockout), to read out the firmware status code. For example in _**Figure 20**_ , the firmware status code readout in the _**GUI**_ shows a number of 0040H (in red color), which indicates that the input undervoltage protection has been triggered. _Note: If there is no protection being triggered, the firmware status code should be 0000_ H _(in black color)._ _Note: Debug_ Mode _parameter should only be enabled for debugging purpose. For actual application running, it has to be disabled._ **Figure 20 Firmware status code readout for debugging** Please refer the design guide for the recommended setup & procedures to read out the firmware status code in debug mode. Datasheet Revision 1.0 2018-06-06 23 **XDPL8218 Digital Flyback Controller IC XDP[™] Digital Power** **==> picture [105 x 47] intentionally omitted <==** ## **List of Parameters** ## **4 List of Parameters** This list provides information about the configurable and fixed parameters. This document uses symbols to ease the readability of formulas. As some tools do not support this format, the symbols are translated into plain text using underscores. For example, the parameter _f_ sw,max translates to f_sw_max. All parameter values are typical settings. The accuracy might vary due to digital quantization and tolerances. _Note: By default, the configurable parameters of a new XDPL8218 chip from Infineon are empty, so it is necessary to configure them before any application testing._ ## **List of configurable parameters** ## **Table 2 Configurable parameters for hardware configuration** |**Symbol**|**Basic description**|**Example**|**Minimum**<br>**value**|**Maximum**<br>**value**| |---|---|---|---|---| |_N_p|Transformer primary main winding turns|32|1|300| |_N_s|Transformer secondary main winding turns|10|1|300| |_N_a|Transformer primary auxiliary winding turns|3|1|300| |_L_p|Transformer nominal primary main winding<br>inductance|0.544 mH|Refer GUI|3 mH| |_R_CS|Current sense resistor value|0.2 Ω|0.1 Ω|3 Ω| |_R_ZCD,1|_ZCD_series resistor value|27 kΩ|Refer GUI|Refer GUI| |_R_ZCD,2|_ZCD_shunt resistor value|3.9 kΩ|Refer GUI|Refer GUI| |_C_VCC|_VCC_capacitor value|22 µF|Refer GUI|100 µF| |_V_out,cap,rating|Main output capacitor voltage rating|80 V|10 V|450 V| |_R_HV|_HV_series resistor value|52 kΩ|Refer GUI|255 kΩ| |_I_GD,pk|Gate driver peak source current|30 mA|30 mA|108 mA| |||||| |**Table 3**<br>**Configurable parameters for startup**||||| |**Symbol**|**Basic description**|**Example**|**Minimum**<br>**value**|**Maximum**<br>**value**| |_n_ss|Number of sof start steps|3|1|Refer GUI| |_V_out,start|Output charging phase output voltage set-point|27 V|_V_outUV,start|_V_outOV| |_V_start,OCP1|Output charging phase_CS_pin voltage level 1 for<br>MOSFET max. current cycle by cycle limit|0.52 V|Refer GUI|_V_OCP1,at,V,in,low| |_V_OCP1,init|Initial_CS_pin voltage level 1 for MOSFET max.<br>current limit on the input voltage measurement<br>pulse before startup|0.3 V|Refer GUI|_V_start,OCP1| |||||| |**Table 4**<br>**Configurable parameters for protections**||||| |**Symbol**|**Basic description**|**Example**|**Minimum**<br>**value**|**Maximum**<br>**value**| |_t_auto,restart|Auto-restart time|1.2 s|0.4 s|4 s| Datasheet Revision 1.0 2018-06-06 24 **XDPL8218 Digital Flyback Controller IC XDP[™] Digital Power** **==> picture [105 x 47] intentionally omitted <==** ## **List of Parameters** |**Table 4**<br>**Configurable parameters for protections (continued)**|**Table 4**<br>**Configurable parameters for protections (continued)**|**Table 4**<br>**Configurable parameters for protections (continued)**|**Table 4**<br>**Configurable parameters for protections (continued)**|**Table 4**<br>**Configurable parameters for protections (continued)**| |---|---|---|---|---| |**Symbol**|**Basic description**|**Example**|**Minimum**<br>**value**|**Maximum**<br>**value**| |_V_OCP1,at,V,in,low|Regulated mode_CS_pin voltage level 1 for MOSFET<br>max. current cycle by cycle limit at lowest<br>operational input voltage (_V_in,low)|0.52 V|Refer GUI|1.08 V| |_V_OCP1,at,V,in,high|Regulated mode_CS_pin voltage level 1 for MOSFET<br>max. current cycle by cycle limit at highest<br>operational input voltage (_V_in,high)|0.34 V|Refer GUI|_V_OCP1,at,V,in,low| |_V_in,low|Lowest operational input voltage (rms in case of<br>AC input)|82 V|_V_inUV|_V_in,high| |_V_in,high|Highest operational input voltage (rms in case of<br>AC input)|325 V|_V_in,low|_V_inOV| |_t_CSOCP2|MOSFET overcurrent protection blanking time|240 ns|100 ns|Refer GUI| |_Reaction_OVP,Vou<br>t|Output overvoltage protection reaction|Auto-<br>Restart|Auto-Restart|Latch-Mode| |_V_outOV|Output overvoltage protection threshold|65 V|_V_out,start|Refer GUI| |_V_outUV,start|Startup output undervoltage protection threshold|27 V|Refer GUI|_V_out,start| |_EN_UVP,Vout|Enable switch for regulated mode output<br>undervoltage protection|Enabled|Enabled|Disabled| |_Reaction_UVP,Vou<br>t|Regulated mode output undervoltage protection<br>reaction|Auto-<br>Restart|Auto-Restart|Latch-Mode| |_V_outUV|Regulated mode output undervoltage protection<br>threshold|33 V|Refer GUI|Refer GUI| |_t_VoutUV,blank|Blanking time for regulated mode output<br>undervoltage protection|500 ms|5 ms|1000 ms| |_EN_OVP,In|Enable switch for maximum input voltage startup<br>check and input overvoltage protection|Enabled|Enabled|Disabled| |_EN_UVP,In|Enable switch for minimum input voltage startup<br>check and input undervoltage protection|Enabled|Enabled|Disabled| |_EN_VIN,ABM|Enable switch for**_ABM_**input voltage protections|Enabled|Enabled|Disabled| |_V_inOV|Input overvoltage protection threshold (rms in<br>case of AC input)|350 V|_V_in,start,max|Refer GUI| |_V_in,start,max|Maximum input voltage for startup (rms in case of<br>AC input)|325 V|_V_in,start,min|_V_inOV| |_V_in,start,min|Minimum input voltage at startup (rms in case of<br>AC input)|82 V|_V_inUV|_V_in,start,max| |_V_inUV|Input undervoltage protection threshold (rms in<br>case of AC input)|70 V|Refer GUI|_V_in,start,min| |_P_foldback,gain|Maximum on-time foldback gain for power<br>limitation at brown-out|1|0|Refer GUI| |_Reaction_VCC,OV<br>P|_VCC_overvoltage protection reaction|Latch-<br>Mode|Auto-Restart|Latch-Mode| |_V_VCC,max|_VCC_overvoltage protection threshold|23 V|23 V|24.9 V| Datasheet Revision 1.0 2018-06-06 25 **XDPL8218 Digital Flyback Controller IC XDP[™] Digital Power** **==> picture [105 x 47] intentionally omitted <==** ## **List of Parameters** ## **Table 4 Configurable parameters for protections (continued)** |**Symbol**|**Basic description**|**Example**|**Minimum**<br>**value**|**Maximum**<br>**value**| |---|---|---|---|---| |_EN_VCC,UVP|Enable switch for regulated mode_VCC_<br>undervoltage protection|Enabled|Enabled|Disabled| |_V_VCC,min|Regulated mode_VCC_undervoltage protection<br>threshold|7.5 V|6.3 V|_V_VCC,max| |_t_VCCUV,blank|Blanking time for regulated mode VCC<br>undervoltage protection|1.5 ms|0 s|Refer GUI| |_T_critical|Temperature threshold for IC overtemperature<br>protection|119°C|Refer GUI|143°C| |_Debug_Mode|Enable switch for debug mode|Disabled|Enabled|Disabled| |||||| |**Table 5**<br>**Configurable parameters for multimode**||||| |**Symbol**|**Basic description**|**Example**|**Minimum**<br>**value**|**Maximum**<br>**value**| |_R_FB,pull,up|_FB_pin internal pull-up resistor value|5.5 kohm|2.25 kohm|7.5 kohm| |_N_quality|Quality factor of the notch filter|1.6|0|2.0| |_n_notch,blank|Number of half sine wave period as a timeout<br>between the line synchronization being<br>established and the notch filter output being<br>applied as the filtered feedback voltage.**_1)_**|2|1|10| |_f_sw,max|Maximum switching frequency when_V_FB,filteredis<br>_V_FB,sw(2.0 V) or above|136 kHz|20 kHz|Refer GUI| |_t_on,min|Minimum on-time_t_on,min_(V_in_)_value when<br>_t_on,min,V,out,sense_(V_in_)_is lower than_t_on,min|1.38 µs|Refer GUI|_t_on,max,at,V,in,lo<br>w| |_t_min,demag|Minimum transformer demagnetizing time value<br>used for_t_on,min,V,out,sense_(V_in_)_variable calculation<br>internally|4 µs|3 µs|5 µs| |_t_on,max,at,V,in,low|Maximum on-time when_V_inis_V_in,low|15 µs|Refer GUI|30 µs| |_f_burst|ABM burst frequency|130 Hz|130 Hz|400 Hz| |_n_ABM,min|Minimum number of pulses per burst|1|1|Refer GUI| |_t_on,min,ABM|Minimum on-time in**_ABM_**|1 µs|Refer GUI|_t_on,min| |_t_ABM,blank|Timeout for**_ABM_**entrance|6.5 ms|0 ms|Refer GUI| |_n_wakeup|Number of scheduler intervals between wakeup<br>and start of the burst|5|1|20| |_V_FB,max,map|_V_FB,filteredthreshold which represents the<br>maximum power transfer of the system|2.0 V|Refer GUI|2.428 V| |_V_FB,min|_V_FB,filteredthreshold which represents the minimum<br>power transfer of the system|0.3 V|0.2 V|0.5 V| > 1 It is essential for the notch filter to have line synchronization in order to work properly. This timeout enables the notch filter to converge. During this timeout, a low pass filter is used as the feedback voltage filtration. Datasheet Revision 1.0 2018-06-06 26 **XDPL8218 Digital Flyback Controller IC XDP[™] Digital Power** **==> picture [105 x 47] intentionally omitted <==** ## **List of Parameters** |**Table 5**<br>**Configurable parameters for multimode (continued)**|**Table 5**<br>**Configurable parameters for multimode (continued)**|**Table 5**<br>**Configurable parameters for multimode (continued)**|**Table 5**<br>**Configurable parameters for multimode (continued)**|**Table 5**<br>**Configurable parameters for multimode (continued)**| |---|---|---|---|---| |**Symbol**|**Basic description**|**Example**|**Minimum**<br>**value**|**Maximum**<br>**value**| |_V_FB,limit,step|Voltage step size of filtered feedback voltage max.<br>limit_V_FB,filtered,maxramp|800 mV|Refer GUI|Refer GUI| |||||| |**Table 6**<br>**Configurable parameters for power factor correction**||||| |**Symbol**|**Basic description**|**Default**|**Minimum**<br>**value**|**Maximum**<br>**value**| |_C_EMI|Input current displacement compensation gain<br>parameter for enhanced PFC|0.2 µF|0 µF|1 µF| |||||| |**Table 7**<br>**Configurable parameters for fine tuning**||||| |**Symbol**|**Basic description**|**Default**|**Minimum**<br>**value**|**Maximum**<br>**value**| |_t_ZCDPD|_ZCD_pin propagation delay compensation<br>parameter|370 ns|0 s|1000 ns| |_R_in|DC link filter capacitor voltage ripple<br>compensation parameter to improve input voltage<br>estimation accuracy|10.5 Ω|0 Ω|30 Ω| |||||| |**Table 8**<br>**Configurable parameters for user ID**||||| |**Symbol**|**Basic description**|**Default**|**Minimum**<br>**value**|**Maximum**<br>**value**| |_User_ID,A|User ID A|0|-|-| |**List of Fixed Parameters**||||| |**Table 9**<br>**Fixed parameters for hardware configuration**||||| |**Symbol**|**Basic description**|**Default**|**Minimum**<br>**value**|**Maximum**<br>**value**| |_V_d|Secondary main output diode forward voltage<br>assumption for output voltage estimation|0.7 V|-|-| |_V_GD|_GD_pin peak voltage|12 V|-|-| |||||| |**Table 10**<br>**Fixed parameters for protections**||||| |**Symbol**|**Basic description**|**Default**|**Minimum**<br>**value**|**Maximum**<br>**value**| |_T_start,max|Maximum IC junction temperature for startup|_T_critical-<br>4°C|-|-| |||||| |**Table 11**<br>**Fixed parameters for startup**||||| |**Symbol**|**Basic description**|**Default**|**Minimum**<br>**value**|**Maximum**<br>**value**| |_t_ss|Sof start time step|0.5 ms|-|-| Datasheet Revision 1.0 2018-06-06 27 **XDPL8218 Digital Flyback Controller IC XDP[™] Digital Power** **==> picture [105 x 47] intentionally omitted <==** ## **List of Parameters** |**Table 11**<br>**Fixed parameters for startup (continued)**|**Table 11**<br>**Fixed parameters for startup (continued)**|**Table 11**<br>**Fixed parameters for startup (continued)**|**Table 11**<br>**Fixed parameters for startup (continued)**|**Table 11**<br>**Fixed parameters for startup (continued)**| |---|---|---|---|---| |**Symbol**|**Basic description**|**Default**|**Minimum**<br>**value**|**Maximum**<br>**value**| |_V_FB,limit,start|Start voltage for filtered feedback voltage max.<br>limit_V_FB,filtered,maxramp|1.2 V|-|-| |||||| |**Table 12**<br>**Fixed parameters for multimode**||||| |**Symbol**|**Basic description**|**Default**|**Minimum**<br>**value**|**Maximum**<br>**value**| |_V_FB,ABM|_V_FB,filteredthreshold for the**_ABM_**/**_DCM_**transition|800 mV|-|-| |_V_FB,sw|_V_FB,filteredthreshold for the end of the maximum<br>switching frequency ramp up|2 V|-|-| |_V_FB,on|_V_FB,filteredthreshold for the start of the on-time<br>ramp up|1.2 V|-|-| |_f_sw,min|Minimum switching frequency|20 kHz|-|-| |||||| |**Table 13**<br>**Fixed parameters for power factor correction**||||| |**Symbol**|**Basic description**|**Default**|**Minimum**<br>**value**|**Maximum**<br>**value**| |_V_EPFC,of|Above this_V_FB,filteredthreshold, the enhanced**_PFC_**<br>is fully enabled.|1.2 V|-|-| |_V_EPFC,of|Below this_V_FB,filteredthreshold, the enhanced**_PFC_**<br>is disabled.|0.8 V|-|-| |_t_on,min,EPFC|Minimum on time for enhanced**_PFC_**modulation|_t_CS,LEB<br>+ 24/_f_MCLK|-|-| |_t_on,max,EPFC|Maximum on time for enhanced**_PFC_**modulation|1.5*_t_on,max<br>,at,V,in,low|-|-| |||||| |**Table 14**<br>**Other fixed parameters**||||| |**Symbol**|**Basic description**|**Default**|**Minimum**<br>**value**|**Maximum**<br>**value**| |_t_CS,LEB|_CS_leading edge blanking time|480 ns|-|-| |_t_ZCD,ring|_ZCD_ringing suppression|1.2 µs|-|-| |_t_pw|Discharge pulse duration|1.5 µs|-|-| |_n_OSC,ZCD|Selection of zero-crossings for the oscillation<br>period measurement at pre-startup|Second<br>and Third<br>zero-<br>crossings|-|-| |_T_OSC,max|Maximum limit of the measured oscillation period<br>(If exceeded at pre-startup,_T_OSC,presetis used; If<br>exceeded afer startup, the last valid measured<br>oscillation period is used)|6.6 µs|-|-| |_T_OSC,preset|Oscillation period used by the controller if the<br>measured oscillation period at pre-startup exceeds<br>_T_OSC,max|3.3 µs|-|-| Datasheet Revision 1.0 2018-06-06 28 **XDPL8218 Digital Flyback Controller IC XDP[™] Digital Power** **==> picture [105 x 47] intentionally omitted <==** ## **Electrical Characteristics and Parameters** ## **5 Electrical Characteristics and Parameters** All signals are measured with respect to the ground pin, GND. The voltage levels are valid provided other ratings are not violated. ## **5.1 Package Characteristics** ## **Table 15 Package Characteristics** |**Parameter**|**Symbol**|**Limit Values**|**Limit Values**|**Unit**|**Remarks**| |---|---|---|---|---|---| |||**min**|**max**||| |Thermal resistance for PG-<br>DSO-8-58|RthJA|—|178|K/W|JEDEC 1s0p for 140 mW<br>power dissipation| ## **5.2 Absolute Maximum Ratings** _**Attention** :_ _**Stresses above the values listed below may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. These values are not tested during production test.**_ ## **Table 16 Absolute Maximum Ratings** |**Parameter**|**Symbol**|**Limit Values**|**Limit Values**|**Unit**|**Remarks**| |---|---|---|---|---|---| |||**min**|**max**||| |Voltage externally supplied<br>to pin VCC|VVCCEXT|–0.5|26|V|voltage that can be applied<br>to pin VCC by an external<br>voltage source| |Voltage at pin GDx|VGDx|–0.5|VVCC+ 0.3|V|if gate driver is not<br>configured for digital I/O| |Junction temperature|TJ|–40|125|°C|max. operating frequency<br>66 MHz fMCLK| |Junction temperature|TJ|–40|150**_1)_**|°C|_f_sw,max≤ 136 kHz| |Storage temperature|TS|–55|150|°C|| |Soldering temperature|TSOLD|—|260|°C|Wave Soldering**_2)_**| |Latch-up capability|ILU|—|150|mA|**_3)_**Pin voltages acc. to abs.<br>max. ratings| |ESD capability HBM|VHBM|—|1500|V|**_4)5)_**| |ESD capability CDM|VCDM|—|500|V|**_6)_**| - 1 Auto-restart may be delayed at low input voltage condition when junction temperature is above 125°C. The lifetime is not guaranteed when IC operating junction temperature is above 125°C. - 2 According to JESD22-A111 Rev A. - 3 Latch-up capability according to JEDEC JESD78D, TA= 85°C. - 4 ESD-HBM according to ANSI/ESDA/JEDEC JS-001-2012. - 5 product resp. package specific rating up to 2000 V - 6 ESD-CDM according to JESD22-C101F. Datasheet Revision 1.0 2018-06-06 29 **XDPL8218 Digital Flyback Controller IC XDP[™] Digital Power** **==> picture [105 x 47] intentionally omitted <==** ## **Electrical Characteristics and Parameters** ## **Table 16 Absolute Maximum Ratings (continued)** |**Parameter**|**Symbol**|**Limit Values**|**Limit Values**|**Unit**|**Remarks**| |---|---|---|---|---|---| |||**min**|**max**||| |Input Voltage Limit|VIN|–0.5|3.6|V|Voltage externally supplied<br>to pins GPIO, MFIO, CS, ZCD,<br>GPIO, VS, GDx (if GDx is<br>configured as digital I/O). (If<br>not stated diferent)| |Maximum permanent<br>negative clamping current<br>for ZCD and CS|–ICLN_DC|—|2.5|mA|RMS| |Maximum transient negative<br>clamping current for ZCD<br>and CS|–ICLN_TR|—|10|mA|pulse < 500ns| |Maximum negative transient<br>input voltage for ZCD|–VIN_ZCD|—|1.5|V|pulse < 500ns| |Maximum negative transient<br>input voltage for CS|–VIN_CS|—|3.0|V|pulse < 500ns| |Maximum permanent<br>positive clamping current for<br>CS|ICLP_DC|—|2.5|mA|RMS| |Maximum transient positive<br>clamping current for CS|ICLP_TR|—|10|mA|pulse < 500ns| |Maximum current into pin<br>VIN|IAC|—|10|mA|for charging operation| |Maximum sum of input<br>clamping high currents for<br>digital input stages of device|ICLH_sum|—|300|µA|limits for each individual<br>digital input stage have to<br>be respected| |Voltage at HV pin|VHV|-0.5|600|V|| ## **5.3 Operating Conditions** The recommended operating conditions are shown for which the DC Electrical Characteristics are valid. ## **Table 17 Operating Range** |**Parameter**|**Symbol**|**Limit Values**|**Limit Values**|**Unit**|**Remarks**| |---|---|---|---|---|---| |||**min**|**max**||| |Ambient temperature|TA|–40|85|°C|| |Junction Temperature|TJ|–40|125|°C|max. 66 MHz fMCLK| |Lower VCC limit|VVCC|VUVOFF|—|V|device is held in reset when<br>VVCC< VUVOFF| |Voltage externally supplied<br>to VCC pin|VVCCEXT|—|24|V|maximum voltage that can<br>be applied to pin VCC by an<br>external voltage source| |Gate driver pin voltage|VGD|–0.5|VVCC+ 0.3|V|| |Line frequency|fin|45|66|Hz|| Datasheet Revision 1.0 2018-06-06 30 **XDPL8218 Digital Flyback Controller IC XDP[™] Digital Power** **==> picture [105 x 47] intentionally omitted <==** ## **Electrical Characteristics and Parameters** ## **5.4 DC Electrical Characteristics** The electrical characteristics provide the spread of values applicable within the specified supply voltage and junction temperature range, TJ from -40 °C to +125 °C. Devices are tested in production at TA = 25 °C. Values have been verified either with simulation models or by device characterization up to 125 °C. Typical values represent the median values related to TA = 25 °C. All voltages refer to GND, and the assumed supply voltage is VVCC = 18 V if not otherwise specified. _Note: Not all values given in the tables are tested during production testing. Values not tested are explicitly marked._ ## **Table 18 Power Supply Characteristics** |**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**| |---|---|---|---|---|---|---| |||**Min.**|**Typ.**|**Max.**||| |VCC_ON threshold|VVCCon|—|VSELF|—|V|Self-powered startup<br>(default)| |VCC_ON_SELF threshold|VSELF|19|20.5|22|V|dVVCC/dt = 0.2 V/ms| |VCC_ON_SELF delay|tSELF|—|—|2.1|µs|Reaction time of VVCC<br>monitor| |VCC_UVOFF current|IVCCUVOFF|5|20|40|µA|VVCC< VSELF(min) - 0.3 V<br>or VVCC< VEXT(min) -<br>0.3 V**_7)_**| |UVOFF threshold|VUVOFF|—|6.0|—|V|SYS_CFG0.SELUVTHR = 0<br>0B| |UVOFF threshold<br>tolerance|ΔUVOFF|—|—|±5|%|This value defines the<br>tolerance of VUVOFF| |UVOFF filter constant|tUVOFF|600|—|—|ns|1V overdrive| |UVLO (UVWAKE)<br>threshold|VUVLO|—|VUVOFF·<br>1.25|—|V|| |UVWAKE threshold<br>tolerance|ΔUVLO|—|—|±5|%|This value defines the<br>tolerance of VUVLO| |UVLO (UVWAKE) filter<br>constant|tUVLO|0.6|—|2.2|µs|1 V overdrive| |OVLO (OVWAKE)<br>threshold|VOVLO|—|VSELF|—|V|| |OVLO (OVWAKE) filter<br>constant|tOVLO|0.6|—|2.4|µs|1 V overdrive| |VDDP voltage|VVDDP|3.04|3.20|3.36|V|At PMD0/PSMD1. Some<br>internal values refer to<br>VVDDP/ VVDDAand<br>VVDDPPS/ VVDDAPS<br>respectively.| > 7 Tested at VVCC = 5.5 V Datasheet Revision 1.0 2018-06-06 31 **XDPL8218 Digital Flyback Controller IC XDP[™] Digital Power** **==> picture [105 x 47] intentionally omitted <==** ## **Electrical Characteristics and Parameters** ## **Table 18 Power Supply Characteristics (continued)** |**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**| |---|---|---|---|---|---|---| |||**Min.**|**Typ.**|**Max.**||| |VDDA voltage|VVDDA|3.20|3.31|3.42|V|At PMD0/PSMD1. Some<br>internal values refer to<br>VVDDP/ VVDDAand<br>VVDDPPS/ VVDDAPS<br>respectively.| |Nominal range 0% to<br>100%|VADCVCC|0|—|VREF|V|VADCVCC= 0.09 · VVCC**_8)_**| |Reduced VCC range for<br>ADC measurement|RADCVCC|8|—|92|%|**_9)10)_**| |Maximum error for ADC<br>measurement (8-bit<br>result)|TET0VCC|—|—|3.8|LSB8|| |Maximum error for ADC<br>measurement (8-bit<br>result)|TET256VCC|—|—|5.2|LSB8|| |Gate driver current<br>consumption excl. gate<br>charge current|IVCCGD|—|0.26|0.35|mA|Tj≤ 125°C| |VCC quiescent current in<br>PMD0|IVCCPMD0|—|3.5|4.7|mA|All registers have reset<br>values, clock is active,<br>CPU is stopped| |VCC quiescent current in<br>PSMD2|IVCCPSMD2|—|0.3|0.48|mA|Tj≤ 85 °CWU_PWD_CFG<br>= 2CH| |VCC quiescent current in<br>PSMD2|IVCCPSMD2|—|—|1.2|mA|Tj≤ 125 °CWU_PWD_CFG<br>= 2CH| |VCC quiescent current in<br>power saving mode<br>PSDM4 with standby<br>logic active|IVCCPSMD4|—|0.13|0.18|mA|Tj≤ 125 °C<br>WU_PWD_CFG = 00H| ## **Table 19 Electrical Characteristics of the GD Pin** |**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**| |---|---|---|---|---|---|---| |||**Min.**|**Typ.**|**Max.**||| |Input clamping current,<br>low|–ICLL|—|—|100|µA|only digital input| |Input clamping current,<br>high|ICLH|—|—|100|µA|only digital input| > 8 Theoretical minimum value, real minimum value is related to VUVOFF threshold. > 9 Operational values. > 10 Note that the system is turned off if VVCC < VUFOFF. Datasheet Revision 1.0 2018-06-06 32 **XDPL8218 Digital Flyback Controller IC XDP[™] Digital Power** **==> picture [105 x 47] intentionally omitted <==** ## **Electrical Characteristics and Parameters** ## **Table 19 Electrical Characteristics of the GD Pin (continued)** |**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**| |---|---|---|---|---|---|---| |||**Min.**|**Typ.**|**Max.**||| |APD low voltage (active<br>pull-down while device is<br>not powered or gate<br>driver is not enabled)|VAPD|—|—|1.6|V|IGD= 5 mA| |RPPDvalue|RPPD|—|600|—|kΩ|Permanent pull-down<br>resistor inside gate<br>driver| |RPPDtolerance|ΔPPD|—|—|±25|%|Permanent pull-down<br>resistor inside gate<br>driver| |Driver output low<br>impedance|RGDL|—|—|7.0|Ω|TJ≤ 125 °C, IGD= 0.1 A| |Nominal output high<br>voltage in PWM mode|VGDH|—|12|—|V|GDx_CFG.VOL = 2,<br>IGDH= –1 mA| |Output voltage tolerance|ΔVGDH|—|—|±5|%|Tolerance of<br>programming options if<br>VGDH> 10 V, IGDH= –1 mA| |Rail-to-rail output high<br>voltage|VGDHRR|VVCC– 0.5|—|VVCC|V|If VVCC< programmed<br>VGDHand output at high<br>state| |Output high current in<br>PWM mode for GD0|–IGDH|—|100|—|mA|GDx_CFG.CUR = 8| |Output high current<br>tolerance in PWM mode|ΔIGDH|—||±15|%|Calibrated**_11)_**| |Discharge current for<br>GD0|IGDDIS|800|—|—|mA|VGD= 4 V and driver at<br>low state| |Output low reverse<br>current|–IGDREVL|—|—|100|mA|Applies if VGD< 0 V and<br>driver at low state| |Output high reverse<br>current in PWM mode|IGDREVH|—|1/6 of IGDH|—||Applies if<br>VGD> VGDH+ 0.5 V (typ)<br>and driver at high state| ## **Table 20 Electrical Characteristics of the CS Pin** |**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**| |---|---|---|---|---|---|---| |||**Min.**|**Typ.**|**Max.**||| |Input voltage operating<br>range|VINP|–0.5|—|3.0|V|| > 11 referred to GDx_CFG.CUR = 16 Datasheet Revision 1.0 2018-06-06 33 **XDPL8218 Digital Flyback Controller IC XDP[™] Digital Power** **==> picture [105 x 47] intentionally omitted <==** ## **Electrical Characteristics and Parameters** ## **Table 20 Electrical Characteristics of the CS Pin (continued)** |**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**| |---|---|---|---|---|---|---| |||**Min.**|**Typ.**|**Max.**||| |OCP2 comparator<br>reference voltage,<br>derived from VVDDA, given<br>values assuming<br>VVDDA= VVDDA,typ|VOCP2|—|1.6|—|V|SYS_CFG0.OCP2 = 00B| |OCP2 comparator<br>reference voltage,<br>derived from VVDDA, given<br>values assuming<br>VVDDA= VVDDA,typ|VOCP2|—|1.2|—|V|SYS_CFG0.OCP2 = 01B| |OCP2 comparator<br>reference voltage,<br>derived from VVDDA, given<br>values assuming<br>VVDDA= VVDDA,typ|VOCP2|—|0.8|—|V|SYS_CFG0.OCP2 = 10B| |OCP2 comparator<br>reference voltage,<br>derived from VVDDA, given<br>values assuming<br>VVDDA= VVDDA,typ|VOCP2|—|0.6|—|V|SYS_CFG0.OCP2 = 11B| |Threshold voltage<br>tolerance|ΔVOCP2|—|—|±5|%|Voltage divider tolerance| |Comparator propagation<br>delay|tOCP2PD|15|—|35|ns|| |Minimum comparator<br>input pulse width|tOCP2PW|—|—|30|ns|| |OCP2F comparator<br>propagation delay|tOCP2FPD|70|—|170|ns|dVCS/dt = 100 V/µs| |Delay from VCScrossing<br>VCSOCP2to begin of GDx<br>turn-of (IGD0> 2mA)|tCSGDxOCP2|125|135|190|ns|dVCS/dt = 100 V/µs;<br>fMCLK= 66 MHz. GDx<br>driven by QR_GATE<br>FIL_OCP2.STABLE = 3| |OCP1 operating range|VOCP1|0|—|VREF/2|V|RANGE =00B| |OCP1 threshold at full<br>scale setting<br>(CS_OCP1LVL=FFH)|VOCP1FS|1187|1209|1243|mV|RANGE =00B| |Delay from VCScrossing<br>VCSOCP1to CS_OCP1<br>rising edge, 1.2 V range|tCSOCP1|90|170|250|ns|Input signal slope dVCS/<br>dt = 150 mV/µs. This<br>slope represents a use<br>case of a switch-mode<br>power supply with<br>minimum input voltage.| Datasheet Revision 1.0 2018-06-06 34 **XDPL8218 Digital Flyback Controller IC XDP[™] Digital Power** **==> picture [105 x 47] intentionally omitted <==** ## **Electrical Characteristics and Parameters** ## **Table 20 Electrical Characteristics of the CS Pin (continued)** |**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**| |---|---|---|---|---|---|---| |||**Min.**|**Typ.**|**Max.**||| |Delay from CS_OCP1<br>rising edge to QR_GATE<br>falling edge|tOCP1GATE|—|—|130|ns|| |Delay from QR_GATE<br>falling edge to start of<br>GDx turn-of|tGATEGDx|1|3|5|ns|GDx driven by QR_GATE.<br>Measured up to<br>IGDx> 2 mA| |OCP1 comparator input<br>single pulse width filter|tOCP1PW|60|—|95|ns|Shorter pulses than min.<br>are suppressed, longer<br>pulses than max. are<br>passed| |Nominal S&H operating<br>range 0% to 100%|VCSH|0|—|VREF/2|V|CS_ICR.RANGE =00B| |Reduced S&H operating<br>range|RRCVSH|8|—|92|%|CS_ICR.RANGE =00B<br>Operational values| |Maximum error of CS0<br>S&H for corrected<br>measurement (8-bit<br>result)|TET0CS0S|—|—|4.7|LSB|CS_ICR.RANGE =00B| |Maximum error of CS0<br>S&H for corrected<br>measurement (8-bit<br>result)|TET256CS0S|—|—|6.0|LSB|CS_ICR.RANGE =00B| |Nominal S&H operating<br>range 0% to 100%|VCSH|0|—|VREF/6|V|CS_ICR.RANGE =11B| |Reduced S&H operating<br>range|RRCVSH|20|—|80|%|CS_ICR.RANGE =11B<br>Operational values| |Maximum error of CS0<br>S&H for corrected<br>measurement (8-bit<br>result)|TET0CS0S|—|—|8.0|LSB|CS_ICR.RANGE =11B| |Maximum error of CS0<br>S&H for corrected<br>measurement (8-bit<br>result)|TET256CS0S|—|—|8.7|LSB|CS_ICR.RANGE =11B| |S&H delay of input bufer|tCSHST|—|—|510|ns|Referring to jump in<br>input voltage. Limits the<br>minimum gate driver Ton<br>time.| Datasheet Revision 1.0 2018-06-06 35 **XDPL8218 Digital Flyback Controller IC XDP[™] Digital Power** **==> picture [105 x 47] intentionally omitted <==** ## **Electrical Characteristics and Parameters** ## **Table 21 Electrical Characteristics of the ZCD Pin** |**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**| |---|---|---|---|---|---|---| |||**Min.**|**Typ.**|**Max.**||| |Input voltage operating<br>range|VINP|–0.5|—|3.3|V|| |Input clamping current,<br>high|ICLH|—|—|100|µA|| |Zero-crossing threshold|VZCTHR|15|40|70|mV|| |Comparator propagation<br>delay|tZCPD|30|50|70|ns|dVZCD/dt = 4 V/µs| |Input voltage negative<br>clamping level|–VINPCLN|140|180|220|mV|Analog clamp activated| |Nominal I/V-conversion<br>operating range 0% to<br>100%|–IIV|0|—|0.5|mA|CRNG =11BGain = 4800<br>mV/mA| |Nominal I/V-conversion<br>operating range 0% to<br>100%|–IIV|0|—|1|mA|CRNG =10BGain = 2400<br>mV/mA| |Nominal I/V-conversion<br>operating range 0% to<br>100%|–IIV|0|—|2|mA|CRNG =01BGain = 1200<br>mV/mA| |Nominal I/V-conversion<br>operating range 0% to<br>100%|–IIV|0|—|4|mA|CRNG =00BGain = 600<br>mV/mA| |Reduced I/V-conversion<br>operating range|RRIV|5|—|80|%|| |Maximum error for<br>corrected ADC<br>measurement (8-bit<br>result)|TET0IV|—|—|4.1|LSB8|CRNG =00B| |Maximum error for<br>corrected ADC<br>measurement (8-bit<br>result)|TET256IV|—|—|9.7|LSB8|CRNG =00B| |Maximum deviation<br>between ZCD clamp<br>voltage and trim result<br>stored in OTP|EZCDClp|—|—|±5|%|–IIV> 0.25 mA| |IV-conversion delay of<br>input bufer|tIVST|—|—|900|ns|Refers to jump in input<br>current**_12)_**| > 12 Limits the minimum gate driver Ton time. Datasheet Revision 1.0 2018-06-06 36 **XDPL8218 Digital Flyback Controller IC XDP[™] Digital Power** **==> picture [105 x 47] intentionally omitted <==** ## **Electrical Characteristics and Parameters** ## **Table 21 Electrical Characteristics of the ZCD Pin (continued)** |**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**| |---|---|---|---|---|---|---| |||**Min.**|**Typ.**|**Max.**||| |Nominal S&H input<br>voltage range 0% to<br>100%|VZSH|0|—|2/3 · VREF|V|SHRNG =0B| |Nominal S&H input<br>voltage range 0% to<br>100%|VZSH|VREF/2|—|7/6 · VREF|V|SHRNG =1B| |Reduced S&H input<br>voltage range|RRZVSH|4|—|95|%|| |Maximum error for<br>corrected ADC<br>measurement (8-bit<br>result)|TET0ZVS0|—|—|3.7|LSB8|SHRNG =0B| |Maximum error for<br>corrected ADC<br>measurement (8-bit<br>result)|TET256ZVS0|—|—|4.9|LSB8|SHRNG =0B| |Maximum error for<br>corrected ADC<br>measurement (8-bit<br>result)|TET0ZVS1|—|—|4.2|LSB8|SHRNG =1B| |Maximum error for<br>corrected ADC<br>measurement (8-bit<br>result)|TET256ZVS1|—|—|5.8|LSB8|SHRNG =1B| |S&H delay of input bufer<br>referring to jump of input<br>voltage|tZSHST|—|—|1.0|µs|SHRNG =0BTj≤ 125 °C| |S&H delay of input bufer<br>referring to jump of input<br>voltage|tZSHST|—|—|1.6|µs|SHRNG =1BTj≤ 125 °C| ## **Table 22 Electrical Characteristics of the HV Pin** |**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**| |---|---|---|---|---|---|---| |||**Min.**|**Typ.**|**Max.**||| |Current for VCCcap<br>charging|ILD|3.0|5|7.5|mA|VHV= 30 V; VVCC< VVCCon–<br>0.3 V; Tj≥ 0°C| |Current for VCCcap<br>charging|ILD|2.4|5|7.5|mA|VHV= 30 V; VVCC< VVCCon–<br>0.3 V;-25°C < Tj< 0°C| |Current for VCCcap<br>charging|ILD|2.0|5|7.5|mA|VHV= 30 V; VVCC< VVCCon–<br>0.3 V;Tj< -25°C| Datasheet Revision 1.0 2018-06-06 37 **XDPL8218 Digital Flyback Controller IC XDP[™] Digital Power** **==> picture [105 x 47] intentionally omitted <==** ## **Electrical Characteristics and Parameters** ## **Table 22 Electrical Characteristics of the HV Pin (continued)** |**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**| |---|---|---|---|---|---|---| |||**Min.**|**Typ.**|**Max.**||| |Nominal current for<br>measurement path 0% to<br>100%|IMEAS|0|—|9.6|mA|CURRNG = 11B| |Nominal current for<br>measurement path 0% to<br>100%|IMEAS|0|—|4.8|mA|CURRNG = 10B| |Nominal current for<br>measurement path 0% to<br>100%|IMEAS|0|—|1.6|mA|CURRNG = 01B| |Comparator threshold (in<br>% of full range of IMEAS)|THRCOMP|15|20|25|%|COMPTHR= 00B| |Comparator threshold (in<br>% of full range of IMEAS)|THRCOMP|25|30|35|%|COMPTHR= 01B| |Comparator threshold (in<br>% of full range of IMEAS)|THRCOMP|45|50|55|%|COMPTHR= 11B| ## **Table 23 Electrical Characteristics of the FB Pin** |**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**| |---|---|---|---|---|---|---| |||**Min.**|**Typ.**|**Max.**||| |MFIO reference voltage|VMFIOREF|—|VREF|—|V|Selection = VREF| |Nominal range 0% to<br>100%|VMFIO|0|—|VREF|V|Gain = 1| |Reduced operating range|RRVMFIO|4|—|96|%|Gain = 1. Operational<br>values.| |Maximum error for<br>corrected measurement<br>(8-bit result)|TET0MFI0|—|—|4.0|LSB8|Gain = 1| |Maximum error for<br>corrected measurement<br>(8-bit result)|TET256MFI0|—|—|4.8|LSB8|Gain = 1| |Delay of input bufer|tMFIOST|—|—|2.7|µs|Refers to jump in input<br>voltage 0% to 90%.<br>Applicable for MFIO0<br>and MFIO1 only.| Datasheet Revision 1.0 2018-06-06 38 **XDPL8218 Digital Flyback Controller IC XDP[™] Digital Power** **==> picture [105 x 47] intentionally omitted <==** ## **Electrical Characteristics and Parameters** ## **Table 24 Electrical Characteristics of the UART Pin** |**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**| |---|---|---|---|---|---|---| |||**Min.**|**Typ.**|**Max.**||| |Input clamping current,<br>low|–ICLL|—|—|100|µA|only digital input| |Input clamping current,<br>high|ICLH|—|—|100|µA|only digital input| |Input capacitance|CINPUT|—|—|25|pF|| |Input low voltage|VIL|—|—|1.0|V|| |Input high voltage|VIH|2.1|—|—|V|| |Input low current with<br>active weak pull-up WPU|–ILPU|30|—|90|µA|Measured at max. VIL| |Max. input frequency|fINPUT|15|—|—|MHz|| |Output low voltage|VOL|—|—|0.8|V|IOL= 2 mA| |Output high voltage|VOH|2.4|—|—|V|IOH= –2 mA| |Output sink current|IOL|—|—|2|mA|| |Output source current|-IOH|—|—|2|mA|| |Output rise time (0 → 1)|tRISE|—|—|50|ns|20 pF load, push/pull<br>output| |Output fall time (1 → 0)|tFALL|—|—|50|ns|20 pF load, push/pull or<br>open-drain output| |Max. output switching<br>frequency|fSWITCH|10|—|—|MHz|| |UART baudrate|fUART|-10%|57600|+10%|baud|| ## **Table 25 Electrical Characteristics of the A/D Converter** |**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**| |---|---|---|---|---|---|---| |||**Min.**|**Typ.**|**Max.**||| |Integral non-linearity|INL|—|—|1|LSB8|**_13)_**| ## **Table 26 Electrical Characteristics of the Reference Voltage** |**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**| |---|---|---|---|---|---|---| |||**Min.**|**Typ.**|**Max.**||| |Reference voltage|VREF|—|2.428|—|V|| |VREF overall tolerance|ΔVREF|—|—|±1.5|%|Trimmed, Tj≤ 125 °C and<br>aging| > 13 ADC capability measured via channel MFIO without errors due to switching of neighbouring pins, e.g. gate drivers, measured with STC = 5. MFIO buffer non-linearity masked out by taking ADC output values ≥ 30 only. Datasheet Revision 1.0 2018-06-06 39 **XDPL8218 Digital Flyback Controller IC XDP[™] Digital Power** **==> picture [105 x 47] intentionally omitted <==** ## **Electrical Characteristics and Parameters** ## **Table 27 Electrical Characteristics of the OTP Programming** |**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**| |---|---|---|---|---|---|---| |||**Min.**|**Typ.**|**Max.**||| |OTP programming<br>voltage at the VCC pin for<br>range C000Hto CFFFH|VPP|7.35|7.5|7.65|V|Operational values| |OTP programming<br>current|IPP|—|1.6|—|mA|Programming of 4 bits in<br>parallel| ## **Table 28 Electrical Characteristics of the Clock Oscillators** |**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**| |---|---|---|---|---|---|---| |||**Min.**|**Typ.**|**Max.**||| |Master clock oscillation<br>period including all<br>variations|tMCLK|15.0|15.8|16.6|ns|In reference to 66 MHz<br>fMCLK| |Main clock oscillator<br>frequency variation of<br>stored DPARAM<br>frequency|ΔMCLK|–3.2|—|+3.5|%|Temperature drif and<br>aging only, 66 MHz fMCLK| |Standby clock oscillator<br>frequency|fSTBCLK|96|100|104|kHz|Trimming tolerance at<br>TA= 25 °C| |Standby clock oscillator<br>frequency|fSTBCLK|90|100|110|kHz|Overall tolerance, Tj≤<br>125 °C| ## **Table 29 Electrical Characteristics of the Temperature Sensor** |**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**| |---|---|---|---|---|---|---| |||**Min.**|**Typ.**|**Max.**||| |Temperature sensor ADC<br>output operating range|ADCTEMP|0|—|190|LSB|ADCTEMP= 40 +<br>temperature / °C)| |Temperature sensor<br>tolerance|ΔTEMP|—|—|±6|K|Incl. ADC conversion<br>accuracy at 3 σ| Datasheet Revision 1.0 2018-06-06 40 **XDPL8218 Digital Flyback Controller IC XDP[™] Digital Power** **==> picture [105 x 47] intentionally omitted <==** ## **Package Dimensions** ## **6 Package Dimensions** The package dimensions of PG-DSO-8 are provided. **==> picture [115 x 58] intentionally omitted <==** **==> picture [413 x 219] intentionally omitted <==** ## **Figure 21 Package Dimensions for PG-DSO-8** _Note: Dimensions in mm._ _Note: You can find all of our packages, packing types and other package information on our Infineon Internet page “Products”: http://www.infineon.com/products._ Datasheet Revision 1.0 2018-06-06 41 **XDPL8218 Digital Flyback Controller IC XDP[™] Digital Power** **==> picture [105 x 47] intentionally omitted <==** ## **References** ## **7 References** **1.** Infineon: _XDPL8218 Design Guide_ **2.** Infineon: _XDPL8218 Reference Board Engineering Report_ **3.** Infineon: _CoolMOS P7 power MOSFETs_ , _**http://www.infineon.com/P7**_ **4.** Infineon: _.dp Vision User Manual_ **5.** Infineon: _.dp Interface Gen2_ which can be ordered at _**http://www.ehitex.de/en/programmer/2527/.dpinterface-board-gen2.dp-digital-power-2.0-infineon**_ **6.** Infineon: _.dp Interface Gen2 User Manual_ **7.** Infineon: _Programming manual for XDPL controllers with PG-DSO-8 package_ ## **Revision History** Major changes since previous revision |**7.**<br>Infineon:_Programming manual for XDPL controllers with PG-DSO-8 package_<br>**Revision History**<br>Major changes since previous revision|**7.**<br>Infineon:_Programming manual for XDPL controllers with PG-DSO-8 package_<br>**Revision History**<br>Major changes since previous revision| |---|---| ||| |**Revision History**|| |**Revision**|**Description**| |1.0|•<br>Initial version| ## **Glossary** ## **ABM** ## _Active Burst Mode (ABM)_ Active Burst Mode is an operating mode of a switched-mode power supply for very light load conditions. The controller switches in bursts of pulses with a pause between bursts in which no switching is done. ## **CCM** _Continuous Conduction Mode (CCM)_ Continuous Conduction Mode is an operational mode of a switching power supply in which the current is continuously flowing and does not return to zero. ## **CRC** ## _Cyclic Redundancy Check (CRC)_ A cyclic redundancy check is an error-detecting code commonly used to detect accidental changes to raw data. ## **CV** ## _Constant Voltage (CV)_ Constant Voltage is a mode of a power supply in which the output voltage is kept constant regardless of the load. ## **DCM** _Discontinuous Conduction Mode (DCM)_ Discontinuous Conduction Mode is an operational mode of a switching power supply in which the current starts and returns to zero. ## **ECG** ## _Electronic Control Gear (ECG)_ An electronic control gear is a power supply which provides one or more light module(s) with the appropriate voltage or current. Datasheet Revision 1.0 2018-06-06 42 **XDPL8218 Digital Flyback Controller IC XDP[™] Digital Power** **==> picture [105 x 47] intentionally omitted <==** ## **Glossary** ## **EMI** ## _Electro-Magnetic Interference (EMI)_ Also called Radio Frequency Interference (RFI), this is a (usually undesirable) disturbance that affects an electrical circuit due to electromagnetic radiation emitted from an external source. The disturbance may interrupt, obstruct, or otherwise degrade or limit the effective performance of the circuit. ## **GUI** ## _Graphic User Interface (GUI)_ A graphical user interface is a type of interface that allows users to interact with electronic devices through graphical icons and visual indicators. ## **IC** ## _Integrated Circuit (IC)_ A miniaturized electronic circuit that has been manufactured in the surface of a thin substrate of semiconductor material. An IC may also be referred to as micro-circuit, microchip, silicon chip, or chip. ## **LED** ## _Light Emitting Diode (LED)_ A light-emitting diode is a two-lead semiconductor light source which emits light when activated. ## **OCP1** _Overcurrent Protection Level 1 (OCP1)_ The Overcurrent Protection Level 1 is limiting the current in a switched-mode power supply to limit the power delivered to the output of the power supply. ## **PC** ## _Personal Computer (PC)_ A personal computer is a general-purpose computer whose size, capabilities, and original sale price make it useful for individuals, and is intended to be operated directly by an end-user with no intervening computer time-sharing models that allowed larger, more expensive minicomputer and mainframe systems to be used by many people, usually at the same time. ## **PF** ## _Power Factor (PF)_ Power factor is the ratio between the real power and the apparent power. ## **PFC** ## _Power Factor Correction (PFC)_ Power factor correction increases the power factor of an AC power circuit closer to 1 which corresponds to minimizing the reactive power of the power circuit. ## **QRM1** ## _Quasi-Resonant Mode, switching in valley 1 (QRM1)_ Quasi-Resonant Mode is an operating mode of a switched-mode power supply which maximizes efficiency. This is achieved by switching at the occurrence of the first valley of a signal which corresponds to a time when switching losses are low. ## **SSR** ## _Secondary Side Regulated (SSR)_ A Secondary Side Regulated power supply is controls its operation based on feedback from the secondary side of an isolated power supply. ## **THD** ## _Total Harmonic Distortion (THD)_ The total harmonic distortion of a signal is a measurement of the harmonic distortion present and is defined as the ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency. Datasheet Revision 1.0 2018-06-06 43 **XDPL8218 Digital Flyback Controller IC XDP[™] Digital Power** **==> picture [105 x 47] intentionally omitted <==** ## **Glossary** ## **UART** _Universal Asynchronous Receiver Transmitter (UART)_ A universal asynchronous receiver transmitter is used for serial communications over a peripheral device serial port by translating data between parallel and serial forms. ## **USB** _Universal Serial Bus (USB)_ Universal Serial Bus is an industry standard that defines cables, connectors and communications protocols used in a bus for connection, communication, and power supply between computers and electronic devices. ## **UVLO** ## _Undervoltage Lockout (UVLO)_ The Undervoltage-Lockout is an electronic circuit used to turn off the power of an electronic device in the event of the voltage dropping below the operational value. Datasheet Revision 1.0 2018-06-06 44 ## **Trademarks** All referenced product or service names and trademarks are the property of their respective owners. **Edition 2018-06-06 IMPORTANT NOTICE Published by** The information given in this document shall in no event be regarded as a guarantee of conditions or **Infineon Technologies AG** characteristics (“Beschaffenheitsgarantie”) . **81726 Munich, Germany** With respect to any examples, hints or any typical values stated herein and/or any information regarding the **© 2018 Infineon Technologies AG** application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of **All Rights Reserved.** any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. **Do you have a question about any aspect of this document?** In addition, any information given in this document is **Email: erratum@infineon.com** subject to customer’s compliance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning **Document reference** customer’s products and any use of the product of **IFX-nvt1488278225586** Infineon Technologies in customer’s applications. ## **WARNINGS** Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office. Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer’s technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application.
Updated at February 9, 2023
Infineon Technologies is a globally recognized leader in semiconductor solutions, renowned for driving innovation in power management, energy efficiency, and modern mobility. With a strong legacy of engineering excellence, the company provides highly reliable components designed to meet the rigorous demands of industrial, automotive, and advanced commercial applications. The core of our Infineon portfolio is centered on their industry-leading discrete semiconductors. We offer an extensive selection of single and dual MOSFETs, alongside a robust range of single IGBTs and advanced IGBT modules. These flagship power transistors are essential for high-efficiency power conversion and motor control, providing engineers with superior thermal performance and minimized switching losses. Beyond advanced field-effect transistors, the selection includes a comprehensive array of diodes and rectifiers, heavily featuring Schottky diodes, as well as fast-recovery and RF/PIN diodes. This power foundation is further supported by bipolar transistors, intelligent power modules, and thyristor SCR modules, delivering the critical building blocks required for complex power system designs. To support broader system integration, the portfolio also encompasses specialized solutions such as solid-state relays, AC/DC LED driver ICs, and Bluetooth communications modules. From high-power industrial rectifiers to wireless connectivity adapters, Infineon equips designers with the precision components needed to build efficient, scalable, and fully connected electronic systems.
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