XDPL8210XUMA1

LED DRIVER, SOIC-8, SMD

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Manufacturer: INFINEON
Product type: AC / DC LED Driver ICs
SVHC: No SVHC (25-Jun-2025)
Topology: Constant Current, Flyback
IC Mounting: Surface Mount
No. of Pins: 8Pins
Product Range: -
Qualification: -
No. of Outputs: 1Outputs
Device Topology: Constant Current, Flyback
LED Driver Type: Isolated
Driver Case Style: SOIC
IC Case / Package: SOIC
Input Voltage Max: 3.42V
Input Voltage Min: 3.2V
Output Current Max: -
Output Voltage Max: -
Switching Frequency: 10MHz
Switching Frequency Typ: 10MHz
Operating Temperature Max: 85°C
Operating Temperature Min: -40°C
Automotive Qualification Standard: -
Delivery and price
Units per pack	1000
Price	0.589 €
Current stock	10+
Lead time	30 days
Datasheet
**XDPL8210** 

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## **XDPL8210 Digital Flyback Controller IC** 

## **XDP[™] Digital Power** 

## **Datasheet Revision 1.1** 

## **Features** 

- Single stage flyback controller with _**Power Factor Correction (PFC)**_ 

- Primary side regulated _**Constant Current (CC)**_ output with high precision 

- Supports universal AC input (90 Vrms to 305 Vrms) 

- Supports wide LED load voltage range (up to 4 times of the minimum LED load voltage) 

- Excellent line and load regulation (typical within +/- 2%) 

- High power quality (Typical _**Power Factor (PF)**_ up to 0.99 and _**Total Harmonic Distortion (THD)**_ < 10%) 

- High efficiency with _**Quasi-Resonant Mode, switching in first valley (QRM1)**_ at high output power and frequency controlled _**Discontinuous Conduction Mode (DCM)**_ at medium output power 

- Dim-to-off operation (with typical standby power as low as 60 mW) 

- Dedicated PWM input pin for dimming control by either a micro-controller or a transformer-less IEC60929compliant isolated 0 - 10 V dimming circuit (based on CDM10VD) 

- Dimming down to 1% 

- _**Limited Power (LP)**_ mode 

- Input overvoltage and undervoltage (Brown-in/Brown-out) protection with configurable threshold for output on/off 

- Brown-out maximum power reduction, to better protect primary components from overheating and saturation 

- Adaptive output overvoltage protection to meet UL1310 standard (Class 2) for the 54 V LED driver design. 

- Output and _VCC_ undervoltage protection 

- Configurable dimming parameters, e.g. dimming curve (linear/quadratic), minimum current, dim-to-off option (enabled/disabled) 

## **Product validation** 

Qualified for industrial applications according to the relevant tests of JEDEC47/20/22. 

## **Potential applications** 

- Electronic control gear for LED luminaires 

Please read the Important Notice and Warnings at the end of this document 

Datasheet **www.infineon.com** 

Revision 1.1 2021-06-25 

**XDPL8210 Digital Flyback Controller IC XDP[™] Digital Power** 

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## **Potential applications** 

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Lp<br>Np Ns<br>AC Input Output<br>voltage CDC,filter Vout,cap,rating<br>Optional VCC<br>regulator<br>RZCD,1 Na<br>CVCC<br>RZCD,2<br>CZCD<br>RHV<br>VCC ZCD<br>GD IGD,pk CoolMOS™<br>Optional VCC<br>HV CS<br>XDPL8210 regulator<br>RCS Vcc<br>CHV GND UART PWM Iout CDM10VD Rdim+<br>Gnd 0 – 10 V<br>CPWM input<br>**----- End of picture text -----**<br>


## **Figure 1 Potential application 1 for XDPL8210** 

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Vd<br>(0.7V typ.)<br>Lp<br>Np Ns<br>AC Input Output<br>voltage CDC,filter External  Vout,cap,rating<br>Vcc<br>supply<br>RZCD,1 Na<br>CVCC<br>CZCD RZCD,2<br>RHV<br>VCC ZCD<br>GD IGD,pk CoolMOS™<br>HV CS<br>XDPL8210<br>RCS<br>CHV GND UART PWM<br>Primary side<br>PWM Micro-controller<br>CPWM Dimmingsignal<br>**----- End of picture text -----**<br>


## **Figure 2 Potential application 2 for XDPL8210** 

|**Product type**<br>|**Package**|**Marking**|**Firmware version**|**Ordering code**|
|---|---|---|---|---|
|XDPL8210<br>|PG-DSO-8|XDPL8210|4.2.0.0|SP001643692|



Datasheet 

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**XDPL8210 Digital Flyback Controller IC XDP[™] Digital Power** 

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## **Description** 

## **Description** 

The XDPL8210 is a high performance configurable single-stage flyback controller with high power factor, primary side regulated constant current output and _**LP**_ mode. 

The primary side control saves external components especially an opto coupler, thus reducing cost and effort and increasing reliability. With its integrated functionality, XDPL8210 enables an increase set of features without external parts. 

The digital core of the XDPL8210 and its advanced control algorithms provide multiple operation modes such as _**QRM1**_ , _**DCM**_ or _**Active Burst Mode (ABM)**_ . In addition, XDPL8210 includes an enhanced _**PFC**_ function which can partially compensate the effect of the input capacitance on power factor and harmonic distortion. With this functionality and smooth transition between the operation modes, the controller delivers high efficiency, high power factor and low harmonic distortion over wide load range. The active burst mode control scheme significantly extends the dimming range and is synchronized with the line frequency avoiding effects like flicker while reducing audible noise. 

Operation parameters such as the output current, dimming curve and the protection features are digitally configurable. Infineon offers a user friendly _**Graphic User Interface**_ for _**Personal Computer**_ s, allowing rapid engineering changes without the need for complex component design iterations. Functionality can be defined at the end of the production line. Multiple different _**Light Emitting Diode (LED)**_ drivers can be built with the same hardware using different XDPL8210 parameter sets. 

For instance, the dimming curve shape is configurable to linear or quadratic (eye-adaptive) and can optionally be inverted. Additionally, dim-to-off can be enabled or disabled. 

_Note: By default, the configurable parameters of a new XDPL8210 chip from Infineon are empty, so it is necessary to configure them before any application testing._ 

The system performance and efficiency can be optimized using Infineon _CoolMOS P7 power MOSFETs_ . 

Datasheet 

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## **Table of contents** 

## **Table of contents** 

||**Features**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1|
|---|---|
||**Product validation**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1|
||**Potential applications**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1|
||**Description**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3|
||**Table of contents**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4|
|**1**|**Pin configuration**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6|
|**2**|**Functional block diagram**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7|
|**3**|**Functional description**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8|
|3.1|Regulated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8|
|3.1.1|Constant current and limited power set-point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8|
|3.1.2|Multimode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9|
|3.1.3|Control loop initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11|
|3.2|Configurable gate voltage rising slope at GD pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12|
|3.3|Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12|
|3.4|Line synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13|
|3.5|Input voltage, output voltage and output current estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14|
|3.5.1|Input voltage estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15|
|3.5.2|Output voltage estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15|
|3.5.3|Output current estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16|
|3.6|Power factor correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18|
|3.7|Dimming control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18|
|3.8|Protection features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19|
|3.8.1|Primary MOSFET overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20|
|3.8.2|Output undervoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20|
|3.8.3|Output overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21|
|3.8.4|Transformer demagnetization time shortage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23|
|3.8.5|Regulated mode peak output overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23|
|3.8.6|Minimum input voltage startup check and input undervoltage protection . . . . . . . . . . . . . . . . . . 24|
|3.8.7|Maximum input voltage startup check and input overvoltage protection . . . . . . . . . . . . . . . . . . . 24|
|3.8.8|VCC undervoltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24|
|3.8.9|VCC overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25|
|3.8.10|IC overtemperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25|
|3.8.11|Other protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25|
|3.8.12|Protection reactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26|
|**4**|**Debug mode**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26|
|**5**|**List of Parameters**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28|



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## **Table of contents** 

|**6**|**Electrical Characteristics and Parameters**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34|
|---|---|
|6.1|Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34|
|6.2|Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34|
|6.3|Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35|
|6.4|DC Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36|
|**7**|**Package dimensions**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46|
|**8**|**References**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48|
||**Revision History**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48|
||**Glossary**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48|
||**Disclaimer**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51|



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## **Pin configuration** 

## **1 Pin configuration** 

Pin assignments and basic pin description information are shown below. 

|||||||||||
|---|---|---|---|---|---|---|---|---|---|
|ZCD||||1|8||||GND|
|||||||||||
|PWM||||2|7||||VCC|
|||||||||||
|CS||||3|6||||UART|
|||||||||||
|GD||||4|5||||HV|
|||||||||||
||||PG-DSO-8||(150mil)|||||



|**Figure 3**<br>**Pinning of XDPL8210**|**Figure 3**<br>**Pinning of XDPL8210**|**Figure 3**<br>**Pinning of XDPL8210**|**Figure 3**<br>**Pinning of XDPL8210**|
|---|---|---|---|
|**Table 1**<br>**Pin definitions and functions**||||
|**Name**|**Pin**|**Type**|**Function**|
|_ZCD_|1|I|Zero-crossing detection:<br>The_ZCD_pin is connected to the auxiliary winding via external resistors<br>divider. It is used for zero-crossing detection, primary-side output voltage<br>sensing and input voltage sensing.|
|_PWM_|2|I|**_Pulse Width Modulation (PWM)_**dimming:<br>The_PWM_pin is used as a dimming input. The PWM frequency should be fixed<br>in the range from 500 Hz to 2 kHz.|
|_CS_|3|I|Current sensing:<br>The_CS_pin is used for Flyback MOSFET current sensing via external shunt<br>resistor.|
|_GD_|4|O|Gate driver:<br>The_GD_pin is used for Flyback MOSFET gate drive control via external series<br>resistor.|
|_HV_|5|I|High voltage:<br>The_HV_pin is connected to the rectified input voltage via external series<br>resistor. The_HV_pin is used to charge_VCC_pin voltage during startup and<br>protection, via an internal 600 V startup cell. In addition, it is also used for<br>line synchronization.|
|_UART_|6|I/O|**_Universal Asynchronous Receiver Transmitter_**configuration:<br>The_UART_pin is used as the digital interface for parameter configuration.|
|_VCC_|7|I|Operating voltage supply and sensing|
|_GND_|8|-|**_Integrated Circuit (IC)_**grounding|



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## **Functional block diagram** 

## **2 Functional block diagram** 

The functional block diagram shows the basic data flow from input pins via signal processing to the output pins. 

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**----- Start of picture text -----**<br>
Flyback (with PFC)<br>Input Voltage<br>Sensing<br>Output Voltage<br>HV Startup ZCD<br>Sensing<br>VCC  Output Current<br>VCC Power limitation CS<br>Management Calculation<br>UART<br>UART FB Control Loop GD<br>Parametrization<br>Temperature  PWM Dimming<br>PWM<br>Protection Sensing<br>**----- End of picture text -----**<br>


**Figure 4 XDPL8210 functional block diagram** 

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## **Functional description** 

## **3 Functional description** 

The functional description provides an overview about the integrated functions and features as well as their relationship. The mentioned parameters and equations are based on typical values at _T_ A = 25°C. The corresponding min. and max. values are shown in the electrical characteristics. 

## **3.1 Regulated mode** 

The XDPL8210 regulated mode provides a primary side control of the output current. The secondary side feedback components are not necessary for the output current control as the primary side regulation control loop is fully integrated. 

## **3.1.1 Constant current and limited power set-point** 

Under non-dimming condition, the regulated mode _**CC**_ output current set-point is based on the maximum output current set-point _I_ out,full. Under dimming condition, the regulated mode CC output current set-point is selected between _I_ out,full and minimum output current set-point _I_ out,min, depending on the dimming level. Both _I_ out,min and _I_ out,full parameters are configurable. 

If the output power produced by the regulated mode CC output current set-point and the connected LED voltage _V_ LED exceeds the configurable maximum output power limit set-point _P_ out,set, the regulated mode _**LP**_ set point based on _P_ out,set parameter would take over and reduce the output current set-point to _P_ out,set / _V_ LED. 

To achieve a full CC output dimming range between _I_ out,min and _I_ out,full, the connected LED voltage _V_ LED should not exceed _P_ out,set / _I_ out,full, as shown in _**Figure 5**_ . 

If only the CC regulation is desired, the LP regulation can be disabled by configuring _P_ out,set = 0. 

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Iout set-point<br>Pout,set<br>Iout,full<br>Pout,set / VLED,max<br>Iout,min<br>LED voltage<br>Output  VLED,min,dimmed Pout,set VLED,max Output<br>UVP Iout,full OVP<br>**----- End of picture text -----**<br>


## **Figure 5 Operating window with constant current and limited power regulation** 

_Note: V_ LED,max _refers to the desired maximum operating LED voltage when output current is I_ out,full _. V_ LED,max _should be designed well below the output overvoltage protection level._ 

_Note: V_ LED,min,dimmed _refers to the desired minimum operating LED voltage when output current is I_ out,min _. V_ LED,min,dimmed _should be designed well above the output undervoltage protection level._ 

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## **Functional description** 

## **3.1.2 Multimode operation** 

In regulated mode, there are three different switching modes ( _**QRM1**_ , _**DCM**_ and _**ABM**_ ). The integrated primary side control loop selects the switching mode depending on the operating condition. 

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**----- Start of picture text -----**<br>
Power<br>ton,max<br>Pmax On-time controlled<br>QRM1<br>ton,min (Vin)<br>fsw,max or fsw,QR1, whichever is lower<br>Frequency controlled<br>DCM<br>Pmin,DCM fsw,min,DCM<br>fsw,min,DCM/fline/2<br>Pulse number controlled<br>ABM Pmin,ABM NABM,min<br>Input Voltage<br>VinUV VinOV<br>**----- End of picture text -----**<br>


## **Figure 6** 

## **Multimode operation scheme** 

- QRM1: This mode minimizes the switching loss by switching on the MOSFET at the quasi-resonant 1[st] valley of the primary auxiliary winding voltage VAUX signal, to maximize the efficiency. The power is controlled by regulating the on-time of the MOSFET. 

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**----- Start of picture text -----**<br>
VGD<br>time<br>t on<br>VAUX tsw,QR1<br>Zero crossing<br>detection<br>0 V time<br>Valley<br>switching<br>Figure 7 Switching waveforms in QRM1<br>**----- End of picture text -----**<br>


_Note: If the quasi-resonant 1_[st] _valley switching period t_ sw,QR1 _is lower than the minimum switching period of 1/f_ sw,max _, the MOSFET can only be switched on after the quasi-resonant 1_[st] _valley._ 

- DCM: This mode minimizes the switching loss by reducing the switching frequency when the output power is reduced. The on-time is kept at the minimum value, while the power is controlled by regulating the switching frequency. The minimum power transfer in DCM Pmin,DCM happens when the minimum switching frequency _f_ sw,min is reached. 

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## **Functional description** 

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**----- Start of picture text -----**<br>
VGD<br>time<br>ton<br>VAUX tsw,DCM<br>0 V time<br>**----- End of picture text -----**<br>


## **Figure 8 Switching waveforms in DCM** 

- ABM: This mode can be enabled with _EN_ ABM parameter to deliver a lower output power than in _**DCM**_ , for a lower minimum output current. The on-time and switching frequency are kept at the minimum value, while the power is controlled by regulating the switching pulse number of each burst period. The burst frequency in this mode is synchronized to the rectified AC input frequency, to ensure good light quality and low audible noise. The minimum power transfer in _**ABM**_ Pmin,ABM happens when the minimum switching pulse number _N_ ABM,min is reached. 

## **Minimum on-time adaptation based on estimated input voltage** 

In all switching modes, _t_ on,min,V,out,sense _(V_ in _)_ variable is scaled to allow a desired minimum transformer demagnetization time based on _t_ min,demag parameter at the peak of input voltage _V_ in,peak, for output voltage sensing. 

ton, min, V, out, sense Vin = tmin, demag ⋅ NNsp[⋅] VinV,out peak 

## **Equation 1** 

The minimum on-time of _t_ on,min _(V_ in _)_ is based on _t_ on,min parameter or _t_ on,min,V,out,sense _(V_ in _)_ variable, whichever is higher. 

ton > ton, min Vin = max ton, min, V, out, sense Vin , ton, min 

## **Equation 2** 

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## **Functional description** 

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**----- Start of picture text -----**<br>
ton,min(Vin)<br>ton,min,V,out,sense(Vin)<br>ton,min<br>0 VinUV VinOV Vin<br>Note:<br>ton,min,V,out,sense(Vin) = tmin,demag · (Np / Ns) · (Vout / Vin,peak)<br>**----- End of picture text -----**<br>


## **Figure 9 Minimum on-time depending on the estimated input voltage** 

## **3.1.3 Control loop initialization** 

When the regulated mode is entered initially after the startup phase, the control loop initialization is necessary. To ensure a fast and smooth startup with minimal output current overshoot, XDPL8210 features an adaptive control loop switching parameter initialization depending on the _EN_ ABM parameter and estimated input voltage _V_ in: 

- If _**ABM**_ is enabled with _EN_ ABM parameter, ABM is selected as the initial switching mode for the control loop. The initial controlled ABM switching pulse number _N_ ABM,init is scaled between _N_ ABM,min and _N_ ABM,init,VinUV parameters, depending on _V_ in. 

- If ABM is disabled with _EN_ ABM parameter, _**DCM**_ is selected as the initial switching mode for the control loop. The initial controlled DCM switching frequency number _f_ DCM,init is scaled between _f_ sw,min,DCM parameter and _f_ DCM,init,VinUV (20 kHz typ.), depending on _V_ in. 

**==> picture [312 x 155] intentionally omitted <==**

**----- Start of picture text -----**<br>
fDCM,init NABM,init<br>fDCM,init,VinUV<br>(20 kHz typ.)<br>fsw,min,DCM Initial control loop in DCM<br>when ENABM = “Disabled”<br>NABM,init,VinUV<br>NABM,min Initial control loop in ABM<br>when ENABM = “Enabled”<br>VinUV Vin,high VinOV Vin<br>**----- End of picture text -----**<br>


## **Figure 10 Adaptive control loop parameter initialization** 

_Note: V_ inUV _and V_ inOV _refer to the input undervoltage protection level and input overvoltage level parameter respectively._ 

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## **Functional description** 

_Note: V_ in,high _refers to the high input voltage parameter. If the estimated input voltage V_ in _is V_ in,high _or more, N_ ABM,init _= N_ ABM,min _or f_ DCM,init _= f_ sw,min,DCM _is applied._ 

## **3.2 Configurable gate voltage rising slope at GD pin** 

The gate drive peak voltage _V_ GD,pk is 12 V with sufficient Vcc voltage supply. To achieve a good balance of switching loss and _**Electro-Magnetic Interference (EMI)**_ , the gate voltage rising slope which determines the MOSFET switching on speed can be controlled, by configuring the gate driver peak source current _I_ GD,pk parameter (Configurable range: 30 mA to 118 mA). This saves two components (see _D_ fastoff, _R_ slowon in _**Figure 11**_ ), which are conventionally added for the same purpose. 

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**----- Start of picture text -----**<br>
VGD<br>Dfastoff<br>VGD,pk<br>(12V typ.)<br>IGD,pk GD RG Rslowon<br>=118mA<br>Not needed<br>IGD,pk RCS<br>= 30mA<br>t<br>**----- End of picture text -----**<br>


**Figure 11 Configurable gate voltage rising slope and component saving** 

## **3.3 Startup** 

The startup phase is entered upon checking the startup conditions (e.g. input voltage, _**IC**_ temperature) are within limits. 

To estimate the input voltage level before startup, _ZCD_ pin signal is measured during a single pulse generated on _GD_ pin. This single pulse has an on-time based on the pre-start _CS_ pin maximum voltage limit of _V_ OCP1,init or 8 times of the leading edge blanking time _t_ CS,LEB (e.g. 8 * 480 ns = 3.84 μs typ.). If the estimated input voltage or any other startup conditions are not within limits, startup phase is not entered and this single pulse will be generated again after an auto-restart duration. 

The startup phase consists of soft start phase, output charging phase and _**PWM**_ duty cycle measuring phase. The soft start phase is to minimize the component stress during startup. The output charging phase is to fast charge the output voltage for fast _VCC_ voltage self supply takeover from the primary auxiliary winding, while the PWM duty cycle measuring phase is to determine the regulated mode output current set-point. 

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## **Functional description** 

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**----- Start of picture text -----**<br>
Startup phase Regulated Mode<br>Voltage<br>Output  PWM duty<br>Soft start phase<br>charging  cycle<br>(based on nss = 3 configuration as example)     phase measuring Vout<br>Vout,dim,min phase<br>Vout,start<br>Control loop<br>initialization<br>VOCP1<br>CS pin voltage level 1 for MOSFET<br>Pre-Startup Check max current cycle by cycle limit<br>(e.g. input voltage,<br>IC temperature) Vstart,OCP1<br>VOCP1,init<br>Startup with 1 [st]<br>soft start step<br>time<br>0 tSS 2 tSS 3 tSS tout,charge tstart,max<br>**----- End of picture text -----**<br>


## **Figure 12 Start up phase with soft start step nss=3** 

During soft start phase, the switching frequency is fixed at 20 kHz. The MOSFET current is limited in the first soft start step based on _CS_ pin maximum voltage limit of _V_ start,OCP1/( _n_ ss + 1), where _V_ start,OCP1 is the parameter for the output charging phase _CS_ pin maximum voltage limit and _n_ ss is the parameter for the number of soft start steps. The soft start phase CS pin maximum voltage limit is increased by _V_ start,OCP1/( _n_ ss + 1) after each soft start step until _V_ start,OCP1 is reached, and the typical duration of each soft start step _t_ ss is 3.2/ _n_ ss ms or 0.5 ms, whichever is lower. 

During output charging phase, the output voltage is fast charged with MOSFET switching pulses based on either the output charging phase _CS_ pin maximum voltage limit of _V_ start,OCP1 or the maximum on time of _t_ on,max in _**QRM1**_ . To exit the startup phase and enter the regulated mode without triggering the startup output undervoltage protection, the _ZCD_ pin estimated output voltage _V_ out has to reach the output charging voltage set-point of _V_ out,start before the maximum allowable startup phase duration of _t_ start,max is reached (see example in _**Figure 12**_ ). To avoid output overshoot, _V_ out,start should be designed below the fully dimmed minimum output LED voltage _V_ out,dim,min. 

_t_ start,max parameter can be indirectly configured with _VCC_ capacitance parameter _C_ VCC, based on: 

tstart, max = 967 ⋅CVCC 

## **Equation 3** 

_Note: A typical leading edge blanking time t_ CS,LEB _of 480 ns applies on V_ OCP1,init _, V_ start,OCP1 _and the CS pin maximum voltage limit for every soft start step starting from V_ start,OCP1 _/(n_ ss _+ 1)._ 

During the PWM duty cycle measurement phase, the MOSFET switching pulses are based on very short on-time and switching frequency of _f_ sw,DIM,DCM (1 kHz typically). 

After the startup phase is ended with neither protection triggering nor dim-to-off entering, the control loop is initialized for output current regulation in the regulated mode. 

## **3.4 Line synchronization** 

The XDPL8210 synchronizes most of its operation to the AC input half sine wave period or the rectified AC input frequency, via the _HV_ pin. For instance, based on AC input frequency of 50 Hz, the line synchronization 

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## **Functional description** 

should be based on the rectified AC input frequency of 100 Hz or AC input half sine wave period of 10 ms. Such line synchronization is used for the enhanced _**PFC**_ in compensating the input current displacement caused by the line filter and DC link filter capacitor. If the line synchronization is not established, for example during startup, the controller would synchronize its operation based on an internally preset half sine wave period of approximately 9.823 ms. 

## **3.5 Input voltage, output voltage and output current estimation** 

As shown in _**Figure 13**_ , the auxiliary winding voltage signal VAUX sensed via _ZCD_ pin contains information of the transformer demagnetization time _t_ demag, reflected output voltage and reflected input voltage, while the primary peak current signal _I_ p,pk sensed via _CS_ pin contains the secondary peak current _I_ s,pk information. To estimate the output current, the _t_ demag and _I_ s,pk information are necessary. 

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VAUX<br>Reflected output<br>voltage sampling<br>Zero crossing detection<br>time<br>Reflected input  Valley switching<br>voltage sampling Ip Is<br>Vin Vout<br>Itransformer<br>Np Ns<br>Is,pk Na<br>Ip,pk<br>VAUX<br>Ip Ip<br>Is<br>time<br>tdemag<br>tsw,FB<br>VGD<br>time<br>tCS,sample tZCD,sample<br>**----- End of picture text -----**<br>


**Figure 13** 

**Flyback switching waveform example in QRM1** 

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## **Functional description** 

## **3.5.1 Input voltage estimation** 

The input voltage is estimated by sensing the reflected input voltage signal from the transformer primary auxiliary winding voltage _V_ AUX, when the MOSFET is switched on. As the reflected input voltage signal is a negative voltage which cannot be sensed directly, the voltage at _ZCD_ pin is clamped to a negative voltage of _V_ INPCLN. A resistor divider with _R_ ZCD,1 and _R_ ZCD,2 adapts _-I_ IV which is the clamping current flowing out of _ZCD_ pin, based on its operational range, while a _ZCD_ pin filter capacitor _C_ ZCD is needed for noise filtering, as shown in _**Figure 14**_ . 

Based on the sampled clamping current _-I_ IV at the timing of _t_ CS,sample shown in _**Figure 13**_ , which is at the end of on-time, the reflected input voltage signal from _V_ AUX is sensed. The interval of each _-I_ IV sample is approximately 1/64 of the half sine wave period. 

_Note: The half sine wave period is either 9.823 ms or the inverse of the rectified AC input frequency, based on the operating conditions, as explained in_ _**Line synchronization** ._ 

The estimated peak input voltage _V_ in,peak over a half sine wave period is based on: 

**==> picture [347 x 21] intentionally omitted <==**

## **Equation 4** 

Where _N_ p is the primary main winding turns, _N_ a is the primary auxiliary winding turns, _R_ CS is the _CS_ pin shunt resistor value, _V_ CS,peak is the peak _CS_ pin voltage, and _R_ in is the fine-tuning parameter for input voltage sensing accuracy improvement by compensating the switching frequency voltage ripple on _C_ DC,filter. 

The estimated input voltage _V_ in in rms value is assumed by the controller as 0.707 of _V_ in,peak based on a filtered value over a few half sine wave periods. The update rate of _V_ in is once per half sine wave period. 

Vin = 0.707 ⋅Vin, peak Co **Equation 5** 

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**----- Start of picture text -----**<br>
Na Np VDC,filter<br>V in,peak<br>V in<br>ZCD IIV RZCD,1 VDC,filter CDC,filter<br>VAUX<br>CZCD RZCD,2 RG GD<br>VINPCLN<br>RCS VCS<br>**----- End of picture text -----**<br>


## **Figure 14** 

## **Input voltage estimation based on** _**-I**_ **IV** 

The estimated input voltage _V_ in is used for input voltage protections and the enhanced _**PFC**_ (EPFC). Therefore, it is important to ensure that _**IC**_ parameters _R_ ZCD,1, _R_ ZCD,2, _N_ p, _N_ a and _R_ CS are configured as per the actual system hardware dimensioning. 

## **3.5.2 Output voltage estimation** 

The output voltage is estimated by sensing the reflected output voltage signal from the transformer primary auxiliary winding voltage _V_ AUX, when the MOSFET is switched off and near the end of transformer demagnetization. A resistor divider with _R_ ZCD,1 and _R_ ZCD,2 adapts the voltage at _ZCD_ pin based on its operational range, while a _ZCD_ pin filter capacitor _C_ ZCD is needed for noise filtering, as shown in _**Figure 15**_ . 

Based on the sampled _ZCD_ pin voltage _V_ ZCD,SH at the timing of tZCD,sample shown in _**Figure 13**_ , which is approximately a quarter of oscillation period ( _T_ osc/4) before the 1[st] zero crossing of _V_ AUX, a ratio of the reflected 

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## **Functional description** 

output voltage signal from _V_ AUX is sensed. The interval of each _V_ ZCD,SH sampling is approximately 1/64 of the half sine wave period, while the oscillation period _T_ osc is measured once before startup and updated every 7[th] half sine wave period after entering the regulated mode. 

_Note: The half sine wave period is either 9.823 ms or the inverse of the rectified AC input frequency, based on the operating conditions, as explained in_ _**Line synchronization** ._ 

- _Note: As V_ AUX _zero crossing can only be detected by the_ _**IC** via ZCD pin upon its internal analog delay plus external delay caused by C_ ZCD _, t_ ZCDPD _parameter fine-tuning is needed to compensate such delays, to have the proper timing of t_ ZCD,sample _for output voltage estimation._ 

_**Attention** :_ _**Please note that the transformer demagnetization time t**_ **demag** _**has to be longer than 2.0**_ **μ** _**s to ensure that the reflected output voltage can be sensed properly at the ZCD pin.**_ 

The estimated output voltage _V_ out is based on: 

Vout = VZCD, SH ⋅ RZCDR, 1ZCD + R, 2ZCD, 2 ⋅ NaNs[−V][d] 

## **Equation 6** 

Where _N_ s is the transformer secondary main winding turns, _N_ a is the transformer primary auxiliary winding turns and _V_ d is the secondary main output diode forward voltage (assumed by the controller as 0.7 V). 

**==> picture [268 x 98] intentionally omitted <==**

**----- Start of picture text -----**<br>
Vd<br>Na Ns<br>RZCD,1 Cout Vout<br>ZCD VAUX<br>CZCD VZCD,SH RZCD,2<br>**----- End of picture text -----**<br>


## **Figure 15 Output voltage estimation based on** _**V**_ **ZCD,SH** 

The estimated output voltage _V_ out is used for output voltage protections and the enhanced _**PFC**_ (EPFC). Therefore, it is important to ensure that IC parameters _R_ ZCD,1, _R_ ZCD,2, _N_ s and _N_ a are configured as per the actual system hardware dimensioning. 

## **3.5.3 Output current estimation** 

Based on the sampled _CS_ pin voltage _V_ CS,SH at the timing of _t_ CS,sample shown in _**Figure 13**_ , which is at the end of on-time, the primary peak current signal _I_ p,pk is sensed. The interval of each _V_ CS,SH sample is approximately 1/64 of the half sine wave period. 

_Note: The half sine wave period is either 9.823 ms or the inverse of the rectified AC input frequency, based on the operating conditions, as explained in_ _**Line synchronization** ._ 

To compensate the propagation delay between the falling edges of _GD_ pin voltage and _I_ p,pk, as shown in _**Figure 16**_ , a more accurate primary peak current _I_ p,pk can be estimated by optimizing the propagation delay compensation parameter _t_ PDC value: 

**==> picture [118 x 19] intentionally omitted <==**

## **Equation 7** 

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## **Functional description** 

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**----- Start of picture text -----**<br>
Ip<br>VCS,pk<br>Ip,pk =<br>VCS,SH RCS<br>RCS<br>t<br>tPDC<br>VGD<br>t<br>ton<br>**----- End of picture text -----**<br>


## **Figure 16 Propagation delay compensation for more accurate primary peak current estimation** 

The secondary peak current _I_ s,pk can be estimated based on _I_ p,pk, transformer turns ratio _N_ p/ _N_ s, transformer coupling coefficient _K_ coupling, primary main winding inductance _L_ p and primary leakage inductance _L_ p,lk: 

N L Is, pk = Ip, pk ⋅ Nsp[⋅K][coupling][ ⋅] Lp + pLp, lk 

## **Equation 8** 

_Note: L_ p,lk _is 1% of L_ p _by default._ 

The average output current per switching cycle _I_ out _(n)_ can be estimated based on _I_ s,pk, transformer demagnetization time _t_ demag, switching period _t_ sw, _**ABM**_ pulse number _N_ ABM, line frequency _f_ line, _**DCM**_ minimum switching frequency parameter _f_ sw,min,DCM, the estimated output voltage _V_ out, output undervoltage protection level _V_ outUV and the auxiliary loss compensation parameter _G_ loss which is to achieve better load regulation at low output current. 

- _I_ out _(n)_ in _**QRM1**_ and _**DCM**_ : 

Iout, QRM1, DCM n = 12[⋅I][s,][ pk][ ⋅] tdematsw g −Gout, loss ⋅ Vout −VoutUV 

## **Equation 9** 

- _I_ out _(n)_ in _**ABM**_ : 

Iout, ABM n = 12[⋅I][s,][ pk][ ⋅] tdematsw g ⋅NABM ⋅ fsw2, min ⋅fline, DCM[−G][out][,][ loss][ ⋅] Vout −VoutUV 

## **Equation 10** 

The interval of each _I_ out _(n)_ sample is approximately 1/64 of the half sine wave period. The average output current per half sine wave period for output regulation is obtained from the moving average filter based on 64 _I_ out _(n)_ samples. 

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## **Functional description** 

_Note: The half sine wave period is either 9.823 ms or the inverse of the rectified AC input frequency, based on the operating conditions, as explained in_ _**Line synchronization** ._ 

## **3.6 Power factor correction** 

For better _**PFC**_ , the patented enhanced PFC (EPFC) feature can be enabled by configuring _C_ EMI parameter value above zero and fine-tuning the value, to compensate the input current displacement effect which is mainly caused by the DC link filter capacitor _C_ DC,filter. With this feature enabled, in _**QRM1**_ , the regulated on-time is not constant, but modulated with a function based on the estimated input voltage _V_ in, estimated output voltage _V_ out, estimated output current, phase angle and modulation gain of _C_ EMI parameter value. 

The enhanced PFC (EPFC) feature can also be disabled by configuring _C_ EMI parameter as zero. 

## **3.7 Dimming control** 

The XDPL8210 senses the duty cycle of the _PWM_ pin voltage signal, to determine the output current set-point based on the configured dimming curve and maximum power limit setting. In regulated mode, the output current is analogue (except for _**ABM**_ ) and the output ripple frequency is synchronized to the double line frequency, to achieve flicker-free operation. 

## **PWM pin internal pull up resistor** 

The _PWM_ pin internal pull up resistor can be optionally enabled by configuring _PWM_ R,pull,up parameter between 2.25 kohm and 30 kohm. The internal pull up voltage is 3.2 V typically. 

## **PWM pin duty cycle sensing and frequency range** 

The XDPL8210 can sense the duty cycle based on either a normal _**PWM**_ signal or an inverted PWM signal, by configuring the _PWM_ type parameter. 

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**----- Start of picture text -----**<br>
VPWM PWMtype parameter setting<br>Normal Inverted<br>VIH PWM  100% 0%<br>duty cycle<br>time<br>VPWM TPWM PWMtype parameter setting<br>tPWM,L Normal Inverted<br>VIH PWM  tPWM,H tPWM,L<br>VIL duty cycle TPWM TPWM<br>time<br>tPWM,H<br>VPWM PWMtype parameter setting<br>Normal Inverted<br>PWM<br>VIL duty cycle 0% 100%<br>time<br>**----- End of picture text -----**<br>


## **Figure 17 Duty cycle based on the selectable PWM type** 

To sense a stable PWM duty cycle level for the regulation based on a stable output current set-point, a hysteresis level for PWM duty cycle jittering suppression is configurable based on _PWM_ Duty,hyst parameter. Any change of the PWM duty cycle within the hysteresis will not affect the output current. 

The PWM frequency should be fixed in the range of 500 Hz and 2 kHz. 

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## **Functional description** 

## **Dimming curve** 

The XDPL8210 can be configured based on _C_ DIM parameter, to use either a linear or a quadratic dimming curve for the mapping of the PWM duty cycle to the output current set-point, as shown in _**Figure 18**_ . The PWM duty cycle levels of _D_ DIM,min and _D_ DIM,max ensure that the minimum current _I_ out,min and maximum current _I_ out,full can always be achieved, thereby making the application robust against component tolerances. 

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**----- Start of picture text -----**<br>
Iout set-point Iout set-point<br>Iout,full Non power limiting Iout,full Non power limiting<br>(Pout < Pout,set) (Pout < Pout,set)<br>Power limiting Power limiting<br>CDIM=”Linear” (Pout = Pout,set) CDIM=”Quadratic” (Pout = Pout,set)<br>Iout,min PWM  Iout,min PWM<br>DDIM,off DDIM,min 100% duty cycle DDIM,off DDIM,min 100% duty cycle<br>DDIM,on DDIM,max DDIM,on DDIM,max<br>(90% typ.) (90% typ.)<br>**----- End of picture text -----**<br>


## **Figure 18 Selectable Dimming Curves** 

If the _DIM_ type parameter is configured as "Dim (to off)", dim-to-off is entered to turn off the light output when the measured PWM duty cycle gets below _D_ DIM,off (see purple line in _**Figure 18**_ ). During dim-to-off, if the measured PWM duty cycle gets above _D_ DIM,on, the regulated mode is entered to turn on the light output. After hardware reset, if the first measured PWM duty cycle is above _D_ DIM,off, the regulated mode is entered to turn on the light output. 

During dim-to-off, the output voltage is recharged (based on _V_ out,start parameter) to measure the PWM duty cycle, every fast auto-restart period _t_ auto,restart,fast of 400 ms approximately. While the PWM duty cycle measurement is ongoing, the controller _GD_ pin switching frequency is based on _f_ sw,DIM,DCM of 1 kHz typically. To achieve low standby power during dim-to-off, the sleep mode is entered if the measured PWM duty cycle gets below _D_ . DIM,off 

_Note: A weak passive bleeder on the output is required for proper dim-to-off operation._ 

If the _DIM_ type parameter is configured as "Dim (without off)", the light output is not turned off and the output current set-point is based on _I_ out,min when the measured PWM duty cycle gets below either _D_ DIM,min or _D_ DIM,off (see green line in _**Figure 18**_ ). 

If the output power is limited by _P_ out,set, the output current set-point follows the cyan line in _**Figure 18**_ which would result to extended dead travel below _D_ DIM,max. As soon as the product of output current and output voltage drops below _P_ out,set, the output current will follow the green line, as shown in _**Figure 18**_ )). 

## **3.8** 

## **Protection features** 

Protections ensure the operation of the controller under restricted conditions. The protection monitoring signal(s) sampling rate, protection triggering condition(s) and protection reaction are described in this section. 

_**Attention** :_ _**The sampled protection monitoring signal accuracy is subjective to the digital quantization, tolerances of components (including IC) and estimations with indirect sensing (e.g. input and output voltage estimations based on ZCD, CS pin signals), while the protection level triggering accuracy is subjective to the sampled signal accuracy, sampling delay, indirect sensing delay (e.g. reflected output voltage signal cannot be sensed by ZCD pin near AC input phase angle of 0° and 180°) and blanking time.**_ 

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## **Functional description** 

## **3.8.1 Primary MOSFET overcurrent protection** 

_V_ OCP2 denotes the _CS_ pin voltage level 2 for primary MOSFET overcurrent protection. Under the single fault condition of shorted primary main winding, the primary MOSFET overcurrent protection is triggered when the _CS_ pin voltage exceeds _V_ OCP2 for longer than a blanking time based on _t_ CSOCP2 parameter. 

_Note: t_ CSOCP2 _parameter is 240 ns by default._ 

The level of _V_ OCP2 is automatically selected based on _**#unique_39/unique_39_Connect_42_table_dxh_gzl_jhb**_ . 

|The level of_V_OCP2is automatically selected based on**_#unique_39/unique_39_Connect_42_table_dxh_gzl_jhb_**.|The level of_V_OCP2is automatically selected based on**_#unique_39/unique_39_Connect_42_table_dxh_gzl_jhb_**.|
|---|---|
|**Table 2**<br>**VOCP2 level selection depending on VOCP1 parameter value**||
|**VOCP1 (V)**|**VOCP2 (V)**|
|0.40 to 0.54|0.8|
|0.55 to 0.72|1.2|
|0.73 to 1.08|1.6|



The reaction of primary MOSFET overcurrent protection is fixed as auto-restart. 

## **3.8.2 Output undervoltage protection** 

In case of a short or too low LED load voltage, the output voltage would drop to a low level. The output undervoltage protection can be triggered, if the condition is met by monitoring the estimated output voltage _V_ out based on the _ZCD_ pin switching signal (see _**Output voltage estimation**_ for details). 

In regulated mode, if the estimated output voltage _V_ out is lower than the _V_ outUV parameter for longer than a blanking time of _t_ VoutUV,blank parameter, the regulated mode output undervoltage protection is triggered. The reaction of the regulated mode output undervoltage protection is fixed as auto-restart. 

_Note: By default, V_ outUV _is fixed as 50% of the configurable V_ out,dim,min _parameter. V_ out,dim,min _denotes the fully dimmed minimum output LED voltage._ 

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**----- Start of picture text -----**<br>
Vout<br>Output under-<br>voltage protection<br>triggered after<br>VoutUV tVoutUV,blank<br>time<br>Regulated Mode Regulated Mode<br>(Vout > VoutUV) (Vout < VoutUV for tVoutUV,blank)<br>Note: VoutUV level is fixed as 50% of Vout,dim,min parameter.<br>**----- End of picture text -----**<br>


## **Figure 19 Regulated mode output undervoltage protection** 

In startup phase, if the estimated output voltage _V_ out is lower than _V_ out,start parameter over a timeout period of _t_ start,max parameter, the startup output undervoltage protection is triggered. _t_ start,max parameter refers to the maximum allowable duration of the soft-start phase and output charging phase. It can be indirectly configured with _VCC_ capacitance parameter _C_ VCC. 

The reaction of startup output undervoltage protection is fixed as auto-restart. 

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## **Functional description** 

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**----- Start of picture text -----**<br>
Normal startup Output short startup<br>Voltage Voltage<br>tstart,max tstart,max<br>tout,charge<br>Vout,start Vout Vout,start<br>VVCCON VVCCON Startup output undervoltage<br>(20.5V typ.) VVCC (20.5V typ.) VVCC protection triggered<br>(Vout < Vout,start at tstart,max)<br>VUVOFF VUVOFF<br>(6V typ.) time (6V typ.) V out time<br>tVCCON,charge tVCC,holdup tVCCON,charge tVCC,holdup<br>Note:<br>tstart,max = 0.8 · (VVCCON - VUVOFF) / IIC,avg,est.<br>= 0.8 · CVCC · (20.5 V – 6 V) / 12 mA<br>= 967 · CVCC<br>**----- End of picture text -----**<br>


**Figure 20 Normal startup and startup output undervoltage (short) protection waveforms** 

## **3.8.3 Output overvoltage protection** 

In case of output open, the output voltage may rise to a high level. The output overvoltage protection can be triggered, if the condition is met by monitoring the estimated output voltage _V_ out based on the _ZCD_ pin switching signal (see _**Output voltage estimation**_ for details). 

If the estimated output voltage _V_ out is higher than _V_ outOV for longer than a blanking time, the output overvoltage protection is triggered. 

_Note: In_ _**QRM1** and_ _**DCM** , the blanking time is typically a quarter of the half sine wave period. In_ _**ABM** , the blanking time is configurable based on t_ VoutOV,blank,ABM _parameter._ 

_Note: The half sine wave period is either 9.823 ms or the inverse of the rectified AC input frequency, based on the operating conditions, as explained in_ _**Line synchronization** ._ 

The reaction of the output overvoltage protection is configurable to auto-restart or latch-mode based on _Reaction_ OVP,Vout parameter. _**Figure 21**_ shows an example of the output overvoltage protection and recovery waveform, based on the auto-restart reaction. 

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## **Functional description** 

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**----- Start of picture text -----**<br>
Vout [Max. I][out ]<br>set-point<br>First triggering of<br>output OVP Subsequent triggerings of output OVP<br>VoutO V Effective output<br>OVP level<br>Reconnect of LED load<br>tauto-restart<br>Removal of LED load<br>Iout,full<br>time<br>Regulated  Auto-restart protection Regulated<br>Mode Mode<br>**----- End of picture text -----**<br>


## **Figure 21 Output overvoltage protection and recovery waveform** 

- _**Attention** :_ _**It is mandatory to ensure that V**_ **outOV** _**is configured well below the actual output capacitor voltage rating V**_ **out,cap,rating** _**,while the V**_ **out,cap,rating** _**is not exceeded in actual testing with all the necessary test conditions. The protection level triggering accuracy is subjective to the sampled signal accuracy, sampling delay, indirect sensing delay (e.g. reflected output voltage signal cannot be sensed by ZCD pin near AC input phase angle of 0° and 180°) and blanking time.**_ 

- _**Attention** :_ _**If the minimum ABM switching pulses number parameter N**_ **ABM,min** _**and minimum output current parameter I**_ **out,min** _**configured values are both very low, the output overvoltage protection actual triggering level might drift up when output current set-point is I**_ **out,min** _**.**_ 

## **Adaptive output overvoltage protection level** 

To have lower output open load voltage during auto-restart, the adaptive output overvoltage protection can be enabled with the _EN_ adaptive,OVP,Vout parameter, as shown in _**Figure 22**_ . 

Upon triggering the enabled adaptive output overvoltage protection for the first time, the protection level is reduced from _V_ out,OV to _V_ out,OV,red and the output current set-point maximum limit is reduced from _I_ out,full to _I_ out,OVP,red. 

For a successful output recovery, the estimated output voltage _V_ out upon auto-restart has to be lower than _V_ out,OV,red for a number of half sine wave periods based on _N_ Vout,restore parameter, in order to restore the protection level and the output current set-point maximum limit to _V_ out,OV and _I_ out,full, respectively. 

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## **Functional description** 

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**----- Start of picture text -----**<br>
Max. Iout<br>Vout<br>set-point<br>First triggering of<br>output OVP<br>VoutO V Subsequent triggerings of output OVP Effective output<br>VoutOV,red OVP level<br>Reconnect of LED load<br>tauto-restart<br>Removal of LED load<br>Iout,full<br>Iout,OVP,red<br>NVout,restore<br>time<br>Regulated  Auto-restart protection Regulated<br>Mode Mode<br>**----- End of picture text -----**<br>


## **Figure 22 Adaptive output overvoltage protection and recovery waveform** 

_Note: The half sine wave period is either 9.823 ms or the inverse of the rectified AC input frequency, based on the operating conditions, as explained in_ _**Line synchronization** ._ 

## **3.8.4 Transformer demagnetization time shortage protection** 

In case of insufficient transformer demagnetization time, the reflected output voltage signal cannot be properly sensed via the _ZCD_ pin. If such condition presents for longer than 50% of a half sine wave period, the protection will be triggered. The reaction of this protection is fixed as auto-restart. 

_Note: The half sine wave period is either 9.823 ms or the inverse of the rectified AC input frequency, based on the operating conditions, as explained in_ _**Line synchronization** ._ 

## **3.8.5 Regulated mode peak output overcurrent protection** 

By monitoring the estimated average output current per switching cycle based on the switching signals (see _**Output current estimation**_ for details), the regulated mode peak output overcurrent protection can be triggered if the condition is met. 

_EN_ Iout,max,peak parameter refers to the enable switch for the regulated mode peak output overcurrent protection. Upon startup and in the regulated mode, if _EN_ Iout,max,peak parameter is enabled and the average output current per switching cycle is higher than _I_ out,max,peak for longer than a blanking time, the regulated mode peak output current protection will be triggered. The blanking time is based on _I_ out,max,peak,blank parameter. 

The reaction of the regulated mode peak output overcurrent protection is fixed as auto-restart. The auto-restart speed is configurable based on _Speed_ OCP,Iout parameter: 

- If _Speed_ OCP,Iout is configured as "fast", the auto-restart time is approximately 0.4 second. 

- If _Speed_ OCP,Iout is configured as "slow", the auto-restart time is based on the configurable _t_ auto,restart parameter. 

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## **Functional description** 

## **3.8.6 Minimum input voltage startup check and input undervoltage protection** 

By monitoring the estimated input voltage _V_ in based on the _ZCD_ pin and _CS_ pin switching signals (see _**Input voltage estimation**_ for details), the minimum input voltage startup check can be performed, and the input undervoltage protection can be triggered if the condition is met. 

_EN_ UVP,In parameter refers to the enable switch for the minimum input voltage startup check (based on _V_ in,start,min) and input undervoltage protection (based on _V_ inUV). 

_Note: V_ in,start,min _parameter refers to the minimum input voltage level for startup, while V_ inUV _parameter refers to the input undervoltage protection level._ 

During pre-startup check, if _EN_ UVP,In parameter is enabled and the estimated input voltage _V_ in is lower than _V_ in,start,min, the startup phase will not be entered and the protection reaction of auto-restart will be performed. Upon startup and in the regulated mode, if _EN_ UVP,In parameter is enabled and the estimated input voltage _V_ in is lower than _V_ inUV for longer than a blanking time, the input undervoltage protection will be triggered. The blanking time of the input undervoltage protection is typically 10 half sine wave periods. 

_Note: The half sine wave period is either 9.823 ms or the inverse of the rectified AC input frequency, based on the operating conditions, as explained in_ _**Line synchronization** ._ 

The reaction of the input undervoltage protection is fixed as auto-restart. 

## **3.8.7 Maximum input voltage startup check and input overvoltage protection** 

By monitoring the estimated input voltage _V_ in based on the _ZCD_ pin and _CS_ pin switching signals (see _**Input voltage estimation**_ for details), the maximum input voltage startup check can be performed, and the input overvoltage protection can be triggered if the condition is met. 

_EN_ OVP,In parameter refers to the enable switch for the maximum input voltage startup check (based on _V_ in,start,max) and input overvoltage protection (based on _V_ inOV). 

_Note: V_ in,start,max _parameter refers to the maximum input voltage level for startup, while V_ inOV _parameter refers to the input overvoltage protection level._ 

During pre-startup check, if _EN_ OVP,In parameter is enabled and the estimated input voltage _V_ in is higher than _V_ in,start,max, the startup phase will not be entered and the protection reaction of auto-restart will be performed. 

Upon startup and in the regulated mode, if _EN_ OVP,In parameter is enabled and the estimated input voltage _V_ in is higher than _V_ inOV for longer than a blanking time, the input overvoltage protection will be triggered. The blanking time of the input overvoltage protection is typically 1 half sine wave period. 

_Note: The half sine wave period is either 9.823 ms or the inverse of the rectified AC input frequency, based on the operating conditions, as explained in_ _**Line synchronization** ._ 

The reaction of the input overvoltage protection is fixed as auto-restart. 

## **3.8.8 VCC undervoltage lockout** 

The _**Undervoltage Lockout (UVLO)**_ is implemented in the hardware. It ensures the enabling and disabling of the _**IC**_ operation based on the defined thresholds of the operating supply voltage _V_ VCC at the _VCC_ pin. 

The UVLO contains a hysteresis with the voltage thresholds _V_ VCCon for enabling the controller and _V_ UVOFF for disabling the controller. Once the mains input voltage is applied, current flows through an external resistor into the _HV_ pin via the integrated depletion cell and diode to the _VCC_ pin. The controller is enabled once _V_ VCC exceeds the _V_ VCCon threshold and _V_ VCC will then start to drop. For normal startup, _V_ VCC supply should be taken over by either external supply or the self-supply via the auxiliary winding before _V_ VCC drops to _V_ UVOFF. 

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## **Functional description** 

## **3.8.9 VCC overvoltage protection** 

If the sampled _VCC_ voltage is higher than the _VCC_ overvoltage protection level _V_ VCC,max, the _VCC_ overvoltage protection will be triggered. The _VCC_ overvoltage protection reaction is fixed as auto-restart. 

The _VCC_ voltage is sampled once per 7 half sine wave periods. 

_Note: The half sine wave period is either 9.823 ms or the inverse of the rectified AC input frequency, based on the operating conditions, as explained in_ _**Line synchronization** ._ 

## **3.8.10 IC overtemperature protection** 

If the sampled _**IC**_ junction temperature _T_ j is higher than _T_ critical parameter, the IC overtemperature protection will be triggered. The protection reaction is fixed as auto-restart, while the maximum junction temperature for startup and restart _T_ start,max is fixed as 4°C below _T_ critical. 

The IC junction temperature _T_ j is sampled once per 7 half sine wave periods. 

_Note: The half sine wave period is either 9.823 ms or the inverse of the rectified AC input frequency, based on the operating conditions, as explained in_ _**Line synchronization** ._ 

_**Attention** :_ _**IC lifetime is not guaranteed when operating junction temperature is above 125°C, which is possible if T**_ **critical** _**is configured above 119°C, with temperature sensing tolerance of ± 6°C.**_ 

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**----- Start of picture text -----**<br>
Pout<br>Over-temperature<br>Protection triggered<br>TJ<br>4°C typ.<br>Tstart,max Tcritical<br>**----- End of picture text -----**<br>


## **Figure 23 IC overtemperature protection** 

## **3.8.11 Other protections** 

- A hardware weak pull-up protects against an open _CS_ pin. The reaction of this protection reaction is auto-restart. 

- A firmware watchdog triggers a protection if the ADC hardware cannot provide all necessary information within a defined time period. This may occur if timing requirements for the ADC are exceeded. The reaction of this protection is fast auto-restart. 

- A hardware watchdog checks correct execution of firmware. A protection is triggered in the event that the firmware does not service the watchdog within a defined period. The reaction of this protection is auto-restart. 

- A hardware parity check triggers a protection if a bit in the memory changes unintentionally. The reaction of this protection is auto-restart. 

- A firmware _**Cyclic Redundancy Check**_ at each startup verifies the integrity of firmware and parameters. The reaction of this protection is stop mode. 

- A firmware task execution watchdog triggers a protection if the firmware tasks are not executed as expected. The reaction of this protection is auto-restart. 

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## **Debug mode** 

- A protection is triggered if the configurable parameter values are empty at startup. The reaction of this protection is stop mode. 

- A protection is triggered if no reflected input voltage signal sensed from the _ZCD_ pin at startup. The reaction of this protection is stop mode. 

## **3.8.12** 

## **Protection reactions** 

The sequence of a protection reaction (not including hardware restart reaction) is as follows: 

**1.** Upon triggering a protection, the gate driver is disabled within a maximum time, which is 1/512 of the half sine wave period. 

_Note: The half sine wave period is either 9.823 ms or the inverse of the rectified AC input frequency, based on the operating conditions, as explained in_ _**Line synchronization** ._ 

**2.** The reaction depends on the triggered protection: 

   - In case of latch mode, the application will enter latch mode at this time. No further sequence is done until _VCC_ voltage drops below _V_ UVOFF. 

   - In case of auto-restart reaction, the controller will enter power saving mode PSMD2 with the auto-restart time based on _t_ auto,restart parameter. 

   - In case of fast auto-restart reaction, the controller will enter power saving mode PSMD2 with the fast auto-restart time of 0.4 sec. 

_Note: For latch mode, auto-restart and fast auto-restart reactions, the internal HV startup cell is automatically enabled and disabled during this sequence, in order to keep the VCC voltage between the V_ UVLO _and V_ OVLO _thresholds._ 

_Note: For stop mode, if there is no external voltage supply for the VCC, the VCC voltage will drain to V_ UVOFF _and a hardware restart will be performed._ 

**3.** After the (fast) auto-restart time is expired, the controller executes a single discharge pulse of duration _t_ pw. This pulse partially discharges the capacitance after the bridge rectifier to improve accuracy of the next pre-startup input voltage check. 

**4.** Any auto restart may include a new _VCC_ charging cycle. The recharging time of _VCC_ via _HV_ pin current depends on the input voltage level and _VCC_ level at the time when the (fast) auto-restart time is expired. 

**5.** The power stage will enable its gate driver for pre-startup check. If the conditions for pre-startup check are within limits, the startup phase is entered and followed by the regulated mode. During this time, if any protection is triggered, the sequence of a protection reaction (not including hardware restart reaction) starts again from step number 1 above. 

## **4 Debug mode** 

If an unexpected system protection was triggered during testing, the _Debug_ Mode parameter can be enabled to enter stop mode reaction upon the protection triggering (except for _VCC_ undervoltage lockout), to read out the firmware status code. For example in _**Figure 24**_ , the firmware status code readout in the _**GUI**_ shows a number of 0040H (in red color), which indicates that the input undervoltage protection has been triggered. 

_Note: If there is no protection being triggered, the firmware status code should be 0000_ H _(in black color)._ 

_Note: Debug_ Mode _parameter should only be enabled for debugging purpose. For actual application running, it has to be disabled._ 

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## **Debug mode** 

## **Figure 24 Firmware status code readout for debugging** 

Please refer to the design guide for the recommended setup & procedures to read out the firmware status code in debug mode. 

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## **List of Parameters** 

## **5 List of Parameters** 

This list provides information about the configurable and fixed parameters. 

This document uses symbols to ease the readability of formulas. As some tools do not support this format, the symbols are translated into plain text using underscores. For example, the parameter _f_ sw,max translates to f_sw_max. 

All parameter values are typical settings. The accuracy might vary due to digital quantization and tolerances. 

_Note: By default, the configurable parameters of a new XDPL8210 chip from Infineon are empty, so it is necessary to configure them digitally via UART pin before any application testing._ 

## **List of configurable parameters** 

|**Table 3**<br>**Configurable parameters for output set-points**|**Table 3**<br>**Configurable parameters for output set-points**|**Table 3**<br>**Configurable parameters for output set-points**|**Table 3**<br>**Configurable parameters for output set-points**|**Table 3**<br>**Configurable parameters for output set-points**|
|---|---|---|---|---|
|**Symbol**|**Basic description**|**Example**|**Minimum**<br>**value**|**Maximum**<br>**value**|
|_I_out,full|Steady-state maximum output current set-point|830 mA|Refer GUI|Refer GUI|
|_P_out,set|Steady-state maximum output power limit set-<br>point|34.5 W|Refer GUI|Refer GUI|
||||||
|**Table 4**<br>**Configurable parameters for dimming**|||||
|**Symbol**|**Basic description**|**Example**|**Minimum**<br>**value**|**Maximum**<br>**value**|
|_DIM_type|Dimming type via_PWM_pin|Dim (to<br>of)|•<br>Non-dim<br>•<br>Dim (without of)<br>•<br>Dim (to of)||
|_I_out,min|Minimum output current set-point|41.5 mA|Refer GUI|_I_out,full|
|_C_DIM|Shape of the dimming curve|Linear|•<br>Linear<br>•<br>Quadratic||
|_PWM_type|_PWM_type|Inverted|•<br>Normal<br>•<br>Inverted||
|_f_PWM,max|Maximum switching frequency of PWM dimming<br>signal|1050 Hz|_f_PWM,min|2000 Hz|
|_f_PWM,min|Minimum switching frequency of PWM dimming<br>signal|950 Hz|500 Hz|_f_PWM,max|
|_D_DIM,max|_PWM_duty cycle level for maximum output current|90%|_D_DIM,min|Refer GUI|
|_D_DIM,min|_PWM_duty cycle level for minimum output current|15%|_D_DIM,of|_D_DIM,max|
|_D_DIM,on|_PWM_duty cycle level for exiting dim-to-of|11%|_D_DIM,of|_D_DIM,min|
|_D_DIM,of|_PWM_duty cycle level for entering dim-to-of|10%|Refer GUI|_D_DIM,min|
|_PWM_Duty,hyst|Hysteresis level for_PWM_duty cycle jittering<br>suppression|0.1%|0%|2%|



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## **List of Parameters** 

|**Table 5**<br>**Configurable parameters for hardware configuration**|**Table 5**<br>**Configurable parameters for hardware configuration**|**Table 5**<br>**Configurable parameters for hardware configuration**|**Table 5**<br>**Configurable parameters for hardware configuration**|**Table 5**<br>**Configurable parameters for hardware configuration**|
|---|---|---|---|---|
|**Symbol**|**Basic description**|**Example**|**Minimum**<br>**value**|**Maximum**<br>**value**|
|_N_p|Transformer primary main winding turns|58|1|300|
|_N_s|Transformer secondary main winding turns|17|1|300|
|_N_a|Transformer primary auxiliary winding turns|15|1|300|
|_L_p|Transformer primary main winding inductance|0.566 mH|Refer GUI|3 mH|
|_R_CS|Current sense resistor value|0.22 Ω|0.1 Ω|3 Ω|
|_R_ZCD,1|_ZCD_series resistor|56.2 kΩ|Refer GUI|255 kΩ|
|_R_ZCD,2|_ZCD_shunt resistor|2.7 kΩ|Refer GUI|Refer GUI|
|_VCC_supply|_VCC_voltage supply|Wide|•<br>Wide<br>•<br>Narrow<br>•<br>External||
|_C_VCC|_VCC_capacitor value|15 µF|Refer GUI|100 µF|
|_V_out,cap,rating|Output capacitor voltage rating|80 V|10 V|450 V|
|_R_HV|_HV_series resistor|100 kΩ|Refer GUI|255 kΩ|
|_I_GD,pk|Gate driver peak source current|30 mA|30 mA|118 mA|
|_PWM_R,pull,up|_PWM_pin internal pull up resistor|2.25 kΩ|2.25 kΩ to 30 kΩ, or Disabled||
||||||
|**Table 6**<br>**Configurable parameters for startup**|||||
|**Symbol**|**Basic description**|**Example**|**Minimum**<br>**value**|**Maximum**<br>**value**|
|_n_ss|Number of sof start steps|20|1|20|
|_V_out,dim,min|Minimum output voltage when fully dimmed|12 V|_V_out,start|_V_outOV|
|_V_out,start|Output charging phase output voltage set-point|10.5 V|_50% of_<br>_V_out,dim,min|_V_out,dim,min|
|_V_start,OCP1|Output charging phase_CS_pin voltage level 1 for<br>MOSFET max. current cycle by cycle limit|0.5 V|Refer GUI|_V_OCP1|
|_V_OCP1,init|Initial_CS_pin voltage level 1 for MOSFET max.<br>current limit on the input voltage measurement<br>pulse before startup|0.3 V|Refer GUI|_V_OCP1|
||||||
|**Table 7**<br>**Configurable parameters for protections**|||||
|**Symbol**|**Basic description**|**Example**|**Minimum**<br>**value**|**Maximum**<br>**value**|
|_t_auto,restart|Auto-restart time|1.6 s|0.4 s|4.0 s|
|_V_OCP1|Regulated mode_CS_pin voltage level 1 for MOSFET<br>max. current cycle by cycle limit|0.5 V|Refer GUI|1.08 V|
|_Reaction_OVP,Vou<br>t|Output overvoltage protection reaction|Auto-<br>restart|Auto-restart|Latch-Mode|
|_V_outOV|Output overvoltage protection level|56.9 V|_V_out,dim,min|Refer GUI|
|**(table continues...)**|||||



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## **List of Parameters** 

|**Table 7**<br>**(continued) Configurable parameters for protections**|**Table 7**<br>**(continued) Configurable parameters for protections**|**Table 7**<br>**(continued) Configurable parameters for protections**|**Table 7**<br>**(continued) Configurable parameters for protections**|**Table 7**<br>**(continued) Configurable parameters for protections**|
|---|---|---|---|---|
|**Symbol**|**Basic description**|**Example**|**Minimum**<br>**value**|**Maximum**<br>**value**|
|_t_VoutOV,blank,ABM|Output overvoltage protection blanking time in<br>**_ABM_**|0.5 ms|0.2 ms|5.0 ms|
|_EN_adaptive,OVP,Vo<br>ut|Enable switch for adaptive output overvoltage<br>protection level|Enabled|Enabled|Disabled|
|_V_outOV,red|Output overvoltage protection level applied<br>during auto-restart when the last triggered<br>protection is output overvoltage protection with<br>_EN_adaptive,OVP,Voutenabled.|51.3 V|_V_out,dim,min|_V_outOV|
|_I_out,OVP,red|Output current set point max. limit applied<br>during auto-restart when the last triggered<br>protection is output overvoltage protection with<br>_EN_adaptive,OVP,Voutenabled.|41.5 mA|_I_out,min|_I_out,full|
|_N_Vout, restore|Blanking time for output voltage below_V_outOV,red<br>to exit output overvoltage protection with<br>_EN_adaptive,OVP,Voutenabled.|500|0|5000|
|_t_VoutUV,blank|Blanking time for regulated mode output<br>undervoltage protection|40 ms|40 ms|1000 ms|
|_EN_Iout,max,peak|Enable switch for peak output overcurrent<br>protection|Enabled|Enabled|Disabled|
|_I_out,max,peak|Peak output overcurrent protection level|2100 mA|Refer GUI|Refer GUI|
|_t_Iout,max,peak,bla<br>nk|Blanking time for peak output overcurrent<br>protection|1 ms|0 ms|5 ms|
|_Speed_OCP,Iout|Auto-restart speed for peak output overcurrent<br>protection|Fast|Slow|Fast|
|_EN_OVP,In|Enable switch for maximum input voltage startup<br>check and input overvoltage protection|Enabled|Enabled|Disabled|
|_EN_UVP,In|Enable switch for minimum input voltage startup<br>check and input undervoltage protection|Enabled|Enabled|Disabled|
|_V_inOV|Input overvoltage protection level (rms in case of<br>AC input)|352 Vrms|_V_in,start,max|Refer GUI|
|_V_in,start,max|Maximum input voltage level at startup (rms in<br>case of AC input)|326 Vrms|_V_in,start,min|_V_inOV|
|_V_in,start,min|Minimum input voltage level at startup (rms in<br>case of AC input)|80 Vrms|_V_inUV|Refer GUI|
|_V_inUV|Input undervoltage protection level (rms in case of<br>AC input)|63 Vrms|Refer GUI|_V_in,start,min|
|_T_critical|Temperature threshold for IC overtemperature<br>protection|119°C|Refer GUI|143°C|
|_Debug_Mode|Enable switch for debug mode|Disabled|Enabled|Disabled|



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## **List of Parameters** 

|**Table 8**<br>**Configurable parameters for multimode**|**Table 8**<br>**Configurable parameters for multimode**|**Table 8**<br>**Configurable parameters for multimode**|**Table 8**<br>**Configurable parameters for multimode**|**Table 8**<br>**Configurable parameters for multimode**|
|---|---|---|---|---|
|**Symbol**|**Basic description**|**Example**|**Minimum**<br>**value**|**Maximum**<br>**value**|
|_f_sw,max|Maximum switching frequency for**_QRM1_**and**_DCM_**|70 kHz|20 kHz|Refer GUI|
|_N_DCM,mod,gain|Switching period modulation attenuation|16|0 (disabled), 4, 8, 16, 32||
|_t_on,min|Minimum on-time_t_on,min_(V_in_)_value when<br>_t_on,min,V,out,sense_(V_in_)_is lower than_t_on,min|2 µs|Refer GUI|_t_on,max|
|_t_min,demag|Minimum transformer demagnetizing time value<br>used for_t_on,min,V,out,sense_(V_in_)_variable calculation<br>internally|3 µs|3 µs|Refer GUI|
|_t_on,max|Maximum on-time|11.5 µs|Refer GUI|30 µs|
|_f_sw,min,DCM|Minimum switching frequency in DCM|20 kHz|Refer GUI|20 kHz|
|_EN_ABM|Enable switch for ABM|Enabled|Enabled|Disabled|
|_N_ABM,min|Minimum number of pulses per burst|11|4|Refer GUI|
|_N_ABM,init,VinUV|Initial number of pulses per burst when_EN_ABM<br>is enabled and_V_inis near to input undervoltage<br>protection level_V_inUV|132|_N_ABM,min|Refer GUI|
|_V_in,high|Input voltage level which when exceeded, the<br>initial number of pulses per burst is fixed as<br>_N_ABM,minif_EN_ABMis enabled|277 Vrms|_V_in,start,min|_V_inOV|
||||||
|**Table 9**<br>**Configurable parameters for control loop response**|||||
|**Symbol**|**Basic description**|**Example**|**Minimum**<br>**value**|**Maximum**<br>**value**|
|_K_P,QRM|Proportional gain of control loop in QRM1|512|10|3000|
|_K_I,QRM|Integral gain of control loop in QRM1|32|1|1000|
|_K_P,DCM|Proportional gain of control loop in DCM|2048|100|30000|
|_K_I,DCM|Integral gain of control loop in DCM|512|10|10000|
|_K_P,ABM|Proportional gain of control loop in ABM|128|1|600|
|_K_I,ABM|Integral gain of control loop in ABM|32|1|200|
|_ABM_thrs,multiplie<br>r|Minimum set-point error threshold multiplier to<br>activate control loop response in ABM|3|0|10|
||||||
|**Table 10**<br>**Parameters for power factor correction**|||||
|**Symbol**|**Basic description**|**Example**|**Minimum**<br>**value**|**Maximum**<br>**value**|
|_C_EMI|Input current displacement compensation gain<br>parameter for enhanced PFC|0.1 µF|0 µF|1 µF|
||||||
|**Table 11**<br>**Configurable parameters for fine tuning**|||||
|**Symbol**|**Basic description**|**Example**|**Minimum**<br>**value**|**Maximum**<br>**value**|
|_t_ZCD,PD|_ZCD_pin propagation delay compensation<br>parameter|270 ns|0 ns|1000 ns|



**(table continues...)** 

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## **List of Parameters** 

|**Table 11**<br>**(continued) Configurable parameters for fine tuning**|**Table 11**<br>**(continued) Configurable parameters for fine tuning**|**Table 11**<br>**(continued) Configurable parameters for fine tuning**|**Table 11**<br>**(continued) Configurable parameters for fine tuning**|**Table 11**<br>**(continued) Configurable parameters for fine tuning**|
|---|---|---|---|---|
|**Symbol**|**Basic description**|**Example**|**Minimum**<br>**value**|**Maximum**<br>**value**|
|_t_zcddel|Rising edge delay of_ZCD_signal afer gated turn of|380 ns|0 ns|1000 ns|
|_t_PDC|_CS_pin propagation delay compensation parameter|200 ns|0 ns|1000 ns|
|_K_coupling|Transformer coupling coeficient parameter|0.96|0|2|
|_G_out,loss|Auxiliary loss compensation parameter|11.9 Ω|0 mS|2 mS|
|_R_in|DC link filter capacitor voltage ripple<br>compensation parameter to improve input voltage<br>estimation accuracy|11.0 Ω|0 Ω|30 Ω|
||||||
|**Table 12**<br>**Configurable parameter for user ID**|||||
|**Symbol**|**Basic description**|**Example**|**Minimum**<br>**value**|**Maximum**<br>**value**|
|_User_ID,A|User ID A|1018|0|65535|



## **List of fixed parameters** 

|**Table 13**<br>**Fixed parameters for hardware configuration**|**Table 13**<br>**Fixed parameters for hardware configuration**|**Table 13**<br>**Fixed parameters for hardware configuration**|**Table 13**<br>**Fixed parameters for hardware configuration**|**Table 13**<br>**Fixed parameters for hardware configuration**|
|---|---|---|---|---|
|**Symbol**|**Basic description**|**Default**|**Minimum**<br>**value**|**Maximum**<br>**value**|
|_L_p,lk|Transformer primary leakage inductance|1% of_L_p|-|-|
|_V_d|Secondary main output diode forward voltage<br>assumption for output voltage estimation|0.7 V|-|-|
|_V_GD|_GD_pin peak voltage|12 V|-|-|
||||||
|**Table 14**<br>**Fixed parameter for startup**|||||
|**Symbol**|**Basic description**|**Default**|**Minimum**<br>**value**|**Maximum**<br>**value**|
|_t_ss|Sof start time step|0.5 ms or<br>3.2/_t_ss,<br>whichever<br>is lower|-|-|
||||||
|**Table 15**<br>**Fixed parameters for protections**|||||
|**Symbol**|**Basic description**|**Default**|**Minimum**<br>**value**|**Maximum**<br>**value**|
|_V_outUV|Regulated mode output undervoltage protection<br>level|_V_out,dim,min<br>/ 2|-|-|
|_V_VCC,max|_VCC_overvoltage protection level|24 V|-|-|
|_T_start,max|Maximum IC junction temperature for startup|_T_critical-4°C|-|-|
|tblank,Vin,OV|Blanking time for input overvoltage threshold|1/(2fline)|-|-|
|tblank,Vin,UV|Blanking time for input undervoltage threshold|10/(2fline)|-|-|



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## **List of Parameters** 

|**Table 16**<br>**Fixed parameters for multimode**|**Table 16**<br>**Fixed parameters for multimode**|**Table 16**<br>**Fixed parameters for multimode**|**Table 16**<br>**Fixed parameters for multimode**|**Table 16**<br>**Fixed parameters for multimode**|
|---|---|---|---|---|
|**Symbol**|**Basic description**|**Default**|**Minimum**<br>**value**|**Maximum**<br>**value**|
|_f_sw,min,QRM|Minimum switching frequency in QRM1|20 kHz|-|-|
|_f_DCM,init,VinUV|Initial DCM switching frequency when_EN_ABMis<br>disabled and_V_inis near to input undervoltage<br>protection level_V_inUV|20 kHz|-|-|
||||||
|**Table 17**<br>**Other fixed parameters**|||||
|**Symbol**|**Basic description**|**Default**|**Minimum**<br>**value**|**Maximum**<br>**value**|
|_t_CS,LEB|_CS_leading edge blanking time|480 ns|-|-|
|_t_CSOCP2|MOSFET overcurrent protection blanking time|240 ns|-|-|
|_t_ZCD,ring|_ZCD_ringing suppression|1200 ns|-|-|
|_t_blank,CCM|Blanking time for protection|10 ms|-|-|
|_t_pw|Discharge pulse duration|1.5 µs|-|-|



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## **Electrical Characteristics and Parameters** 

## **6 Electrical Characteristics and Parameters** 

All signals are measured with respect to the ground pin, GND. The voltage levels are valid provided other ratings are not violated. 

## **6.1 Package Characteristics** 

## **Package Characteristics** 

|||||||
|---|---|---|---|---|---|
|**Table 18**<br>**Package Characteristics**||||||
|**Parameter**|**Symbol**|**Limit Values**||**Unit**|**Remarks**|
|||**min**|**max**|||
|Thermal resistance for PG-<br>DSO-8-58|RthJA|—|178|K/W|JEDEC 1s0p for 140 mW<br>power dissipation|



## **6.2 Absolute Maximum Ratings** 

_**Attention** :_ _**Stresses above the values listed below may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. These values are not tested during production test.**_ 

## **Table 19 Absolute Maximum Ratings** 

|**Parameter**|**Symbol**|**Limit Values**|**Limit Values**|**Unit**|**Remarks**|
|---|---|---|---|---|---|
|||**min**|**max**|||
|Voltage externally supplied<br>to pin VCC|VVCCEXT|–0.5|26|V|voltage that can be applied<br>to pin VCC by an external<br>voltage source|
|Voltage at pin GDx|VGDx|–0.5|VVCC+ 0.3|V|if gate driver is not<br>configured for digital I/O|
|Junction temperature|TJ|–40|125|°C|max. operating frequency<br>66 MHz fMCLK|
|Junction temperature|TJ|–40|150**_1)_**|°C|_f_sw,max≤ 136 kHz|
|Storage temperature|TS|–55|150|°C||
|Soldering temperature|TSOLD|—|260|°C|Wave Soldering**_2)_**|
|Latch-up capability|ILU|—|150|mA|**_3)_**Pin voltages acc. to abs.<br>max. ratings|
|ESD capability HBM|VHBM|—|1500|V|**_4)5)_**|
|ESD capability CDM|VCDM|—|500|V|**_6)_**|



## **(table continues...)** 

> 1 Auto-restart may be delayed at low input voltage condition when junction temperature is above 125°C. The lifetime is not guaranteed when IC operating junction temperature is above 125°C. 

> 2 According to JESD22-A111 Rev A. 

- 3 Latch-up capability according to JEDEC JESD78D, TA= 85°C. 

- 4 ESD-HBM according to ANSI/ESDA/JEDEC JS-001-2012. 

- 5 product resp. package specific rating up to 2000 V 

- 6 ESD-CDM according to JESD22-C101F. 

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## **Electrical Characteristics and Parameters** 

|**Table 19**<br>**(continued) Absolute Maximum Ratings**|**Table 19**<br>**(continued) Absolute Maximum Ratings**|**Table 19**<br>**(continued) Absolute Maximum Ratings**|**Table 19**<br>**(continued) Absolute Maximum Ratings**|**Table 19**<br>**(continued) Absolute Maximum Ratings**|**Table 19**<br>**(continued) Absolute Maximum Ratings**|
|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Limit Values**||**Unit**|**Remarks**|
|||**min**|**max**|||
|Input Voltage Limit|VIN|–0.5|3.6|V|Voltage externally supplied<br>to pins GPIO, MFIO, CS, ZCD,<br>GPIO, VS, GDx (if GDx is<br>configured as digital I/O). (If<br>not stated diferent)|
|Maximum permanent<br>negative clamping current<br>for ZCD and CS|–ICLN_DC|—|2.5|mA|RMS|
|Maximum transient negative<br>clamping current for ZCD<br>and CS|–ICLN_TR|—|10|mA|pulse < 500ns|
|Maximum negative transient<br>input voltage for ZCD|–VIN_ZCD|—|1.5|V|pulse < 500ns|
|Maximum negative transient<br>input voltage for CS|–VIN_CS|—|3.0|V|pulse < 500ns|
|Maximum permanent<br>positive clamping current for<br>CS|ICLP_DC|—|2.5|mA|RMS|
|Maximum transient positive<br>clamping current for CS|ICLP_TR|—|10|mA|pulse < 500ns|
|Maximum current into pin<br>VIN|IAC|—|10|mA|for charging operation|
|Maximum sum of input<br>clamping high currents for<br>digital input stages of device|ICLH_sum|—|300|µA|limits for each individual<br>digital input stage have to<br>be respected|
|Voltage at HV pin|VHV|-0.5|600|V||



## **6.3 Operating conditions** 

The recommended operating conditions are shown for which the DC Electrical Characteristics are valid. 

|**Table 20**<br>**Operating range**|**Table 20**<br>**Operating range**|||||
|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Limit Values**||**Unit**|**Remarks**|
|||**min**|**max**|||
|Ambient temperature|TA|–40|85|°C||
|Junction Temperature|TJ|–40|125|°C|max. 66 MHz fMCLK|
|Lower VCC limit|VVCC|VUVOFF|—|V|device is held in reset when<br>VVCC< VUVOFF|
|Voltage externally supplied<br>to VCC pin|VVCCEXT|—|24|V|maximum voltage that can<br>be applied to pin VCC by an<br>external voltage source|
|Gate driver pin voltage|VGD|–0.5|VVCC+ 0.3|V||
|Line frequency|fline|45|66|Hz||



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## **Electrical Characteristics and Parameters** 

## **6.4 DC Electrical characteristics** 

The electrical characteristics provide the spread of values applicable within the specified supply voltage and junction temperature range, TJ from -40 °C to +125 °C. 

Devices are tested in production at TA = 25 °C. Values have been verified either with simulation models or by device characterization up to 125 °C. 

Typical values represent the median values related to TA = 25 °C. All voltages refer to GND, and the assumed supply voltage is VVCC = 18 V if not otherwise specified. 

_Note: Not all values given in the tables are tested during production testing. Values not tested are explicitly marked._ 

## **Table 21 Power supply characteristics** 

|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|VCC_ON threshold|VVCCon|—|VSELF|—|V|Self-powered startup<br>(default)|
|VCC_ON_SELF threshold|VSELF|19|20.5|22|V|dVVCC/dt = 0.2 V/ms|
|VCC_ON_SELF delay|tSELF|—|—|2.1|µs|Reaction time of VVCC<br>monitor|
|VCC_UVOFF current|IVCCUVOFF|5|20|40|µA|VVCC< VSELF(min) - 0.3 V<br>or VVCC< VEXT(min) -<br>0.3 V**_7)_**|
|UVOFF threshold|VUVOFF|—|6.0|—|V|SYS_CFG0.SELUVTHR = 0<br>0B|
|UVOFF threshold<br>tolerance|ΔUVOFF|—|—|±5|%|This value defines the<br>tolerance of VUVOFF|
|UVOFF filter constant|tUVOFF|600|—|—|ns|1V overdrive|
|UVLO (UVWAKE)<br>threshold|VUVLO|—|VUVOFF·<br>1.25|—|V||
|UVWAKE threshold<br>tolerance|ΔUVLO|—|—|±5|%|This value defines the<br>tolerance of VUVLO|
|UVLO (UVWAKE) filter<br>constant|tUVLO|0.6|—|2.2|µs|1 V overdrive|
|OVLO (OVWAKE)<br>threshold|VOVLO|—|VSELF|—|V||
|OVLO (OVWAKE) filter<br>constant|tOVLO|0.6|—|2.4|µs|1 V overdrive|
|VDDP voltage|VVDDP|3.04|3.20|3.36|V|At PMD0/PSMD1. Some<br>internal values refer<br>to VVDDP/ VVDDA<br>and VVDDPPS/ VVDDAPS<br>respectively.|



## **(table continues...)** 

> 7 Tested at VVCC = 5.5 V 

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## **Electrical Characteristics and Parameters** 

|**Table 21**<br>**(continued) Power supply characteristics**|**Table 21**<br>**(continued) Power supply characteristics**|**Table 21**<br>**(continued) Power supply characteristics**|**Table 21**<br>**(continued) Power supply characteristics**|**Table 21**<br>**(continued) Power supply characteristics**|**Table 21**<br>**(continued) Power supply characteristics**|**Table 21**<br>**(continued) Power supply characteristics**|
|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Values**|||**Unit**|**Note or Test Condition**|
|||**Min.**|**Typ.**|**Max.**|||
|VDDA voltage|VVDDA|3.20|3.31|3.42|V|At PMD0/PSMD1. Some<br>internal values refer<br>to VVDDP/ VVDDA<br>and VVDDPPS/ VVDDAPS<br>respectively.|
|Nominal range 0% to<br>100%|VADCVCC|0|—|VREF|V|VADCVCC= 0.09 · VVCC**_8)_**|
|Reduced VCC range for<br>ADC measurement|RADCVCC|8|—|92|%|**_9)10)_**|
|Maximum error for<br>ADC measurement (8-bit<br>result)|TET0VCC|—|—|3.8|LSB8||
|Maximum error for<br>ADC measurement (8-bit<br>result)|TET256VCC|—|—|5.2|LSB8||
|Gate driver current<br>consumption excl. gate<br>charge current|IVCCGD|—|0.26|0.35|mA|Tj≤ 125°C|
|VCC quiescent current in<br>PMD0|IVCCPMD0|—|3.5|4.7|mA|All registers have reset<br>values, clock is active,<br>CPU is stopped|
|VCC quiescent current in<br>PSMD2|IVCCPSMD2|—|0.3|0.48|mA|Tj≤ 85 °CWU_PWD_CFG<br>= 2CH|
|VCC quiescent current in<br>PSMD2|IVCCPSMD2|—|—|1.2|mA|Tj≤ 125 °CWU_PWD_CFG<br>= 2CH|
|VCC quiescent current<br>in power saving mode<br>PSDM4 with standby<br>logic active|IVCCPSMD4|—|0.13|0.18|mA|Tj≤ 125 °C<br>WU_PWD_CFG = 00H|
||||||||
|**Table 22**<br>**Electrical characteristics of the GD pin**|||||||
|**Parameter**|**Symbol**|**Values**|||**Unit**|**Note or Test Condition**|
|||**Min.**|**Typ.**|**Max.**|||
|Input clamping current,<br>low|–ICLL|—|—|100|µA|only digital input|
|Input clamping current,<br>high|ICLH|—|—|100|µA|only digital input|



## **(table continues...)** 

> 8 Theoretical minimum value, real minimum value is related to VUVOFF threshold. 

> 9 Operational values. 

> 10 Note that the system is turned off if VVCC < VUFOFF. 

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## **Electrical Characteristics and Parameters** 

|**Table 22**<br>**(continued) Electrical characteristics of the GD pin**|**Table 22**<br>**(continued) Electrical characteristics of the GD pin**|**Table 22**<br>**(continued) Electrical characteristics of the GD pin**|**Table 22**<br>**(continued) Electrical characteristics of the GD pin**|**Table 22**<br>**(continued) Electrical characteristics of the GD pin**|**Table 22**<br>**(continued) Electrical characteristics of the GD pin**|**Table 22**<br>**(continued) Electrical characteristics of the GD pin**|
|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Values**|||**Unit**|**Note or Test Condition**|
|||**Min.**|**Typ.**|**Max.**|||
|APD low voltage (active<br>pull-down while device<br>is not powered or gate<br>driver is not enabled)|VAPD|—|—|1.6|V|IGD= 5 mA|
|RPPDvalue|RPPD|—|600|—|kΩ|Permanent pull-down<br>resistor inside gate<br>driver|
|RPPDtolerance|ΔPPD|—|—|±25|%|Permanent pull-down<br>resistor inside gate<br>driver|
|Driver output low<br>impedance|RGDL|—|—|7.0|Ω|TJ≤ 125 °C, IGD= 0.1 A|
|Nominal output high<br>voltage in PWM mode|VGDH|—|12|—|V|GDx_CFG.VOL = 2,<br>IGDH= –1 mA|
|Output voltage tolerance|ΔVGDH|—|—|±5|%|Tolerance of<br>programming options if<br>VGDH> 10 V, IGDH= –1 mA|
|Rail-to-rail output high<br>voltage|VGDHRR|VVCC– 0.5|—|VVCC|V|If VVCC< programmed<br>VGDHand output at high<br>state|
|Output high current in<br>PWM mode for GD0|–IGDH|—|100|—|mA|GDx_CFG.CUR = 8|
|Output high current<br>tolerance in PWM mode|ΔIGDH|—||±15|%|Calibrated**_11)_**|
|Discharge current for<br>GD0|IGDDIS|800|—|—|mA|VGD= 4 V and driver at<br>low state|
|Output low reverse<br>current|–IGDREVL|—|—|100|mA|Applies if VGD< 0 V and<br>driver at low state|
|Output high reverse<br>current in PWM mode|IGDREVH|—|1/6 of IGDH|—||Applies if<br>VGD> VGDH+ 0.5 V (typ)<br>and driver at high state|
||||||||
|**Table 23**<br>**Electrical characteristics of the CS pin**|||||||
|**Parameter**|**Symbol**|**Values**|||**Unit**|**Note or Test Condition**|
|||**Min.**|**Typ.**|**Max.**|||
|Input voltage operating<br>range|VINP|–0.5|—|3.0|V||
|**(table continues...)**|||||||



> 11 referred to GDx_CFG.CUR = 16 

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## **Electrical Characteristics and Parameters** 

|**Table 23**<br>**(continued) Electrical characteristics of the CS pin**|**Table 23**<br>**(continued) Electrical characteristics of the CS pin**|**Table 23**<br>**(continued) Electrical characteristics of the CS pin**|**Table 23**<br>**(continued) Electrical characteristics of the CS pin**|**Table 23**<br>**(continued) Electrical characteristics of the CS pin**|**Table 23**<br>**(continued) Electrical characteristics of the CS pin**|**Table 23**<br>**(continued) Electrical characteristics of the CS pin**|
|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Values**|||**Unit**|**Note or Test Condition**|
|||**Min.**|**Typ.**|**Max.**|||
|OCP2 comparator<br>reference voltage,<br>derived from VVDDA,<br>given values assuming<br>VVDDA= VVDDA,typ|VOCP2|—|1.6|—|V|SYS_CFG0.OCP2 = 00B|
|OCP2 comparator<br>reference voltage,<br>derived from VVDDA,<br>given values assuming<br>VVDDA= VVDDA,typ|VOCP2|—|1.2|—|V|SYS_CFG0.OCP2 = 01B|
|OCP2 comparator<br>reference voltage,<br>derived from VVDDA,<br>given values assuming<br>VVDDA= VVDDA,typ|VOCP2|—|0.8|—|V|SYS_CFG0.OCP2 = 10B|
|OCP2 comparator<br>reference voltage,<br>derived from VVDDA,<br>given values assuming<br>VVDDA= VVDDA,typ|VOCP2|—|0.6|—|V|SYS_CFG0.OCP2 = 11B|
|Threshold voltage<br>tolerance|ΔVOCP2|—|—|±5|%|Voltage divider tolerance|
|Comparator propagation<br>delay|tOCP2PD|15|—|35|ns||
|Minimum comparator<br>input pulse width|tOCP2PW|—|—|30|ns||
|OCP2F comparator<br>propagation delay|tOCP2FPD|70|—|170|ns|dVCS/dt = 100 V/µs|
|Delay from VCScrossing<br>VCSOCP2to begin of GDx<br>turn-of (IGD0> 2mA)|tCSGDxOCP2|125|135|190|ns|dVCS/dt = 100 V/µs;<br>fMCLK= 66 MHz. GDx<br>driven by QR_GATE<br>FIL_OCP2.STABLE = 3|
|OCP1 operating range|VOCP1|0|—|VREF/2|V|RANGE =00B|
|OCP1 threshold at<br>full scale setting<br>(CS_OCP1LVL=FFH)|VOCP1FS|1187|1209|1243|mV|RANGE =00B|
|Delay from VCScrossing<br>VCSOCP1to CS_OCP1<br>rising edge, 1.2 V range|tCSOCP1|90|170|250|ns|Input signal slope dVCS/<br>dt = 150 mV/µs. This<br>slope represents a use<br>case of a switch-mode<br>power supply with<br>minimum input voltage.|



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## **Electrical Characteristics and Parameters** 

|**Table 23**<br>**(continued) Electrical characteristics of the CS pin**|**Table 23**<br>**(continued) Electrical characteristics of the CS pin**|**Table 23**<br>**(continued) Electrical characteristics of the CS pin**|**Table 23**<br>**(continued) Electrical characteristics of the CS pin**|**Table 23**<br>**(continued) Electrical characteristics of the CS pin**|**Table 23**<br>**(continued) Electrical characteristics of the CS pin**|**Table 23**<br>**(continued) Electrical characteristics of the CS pin**|
|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Values**|||**Unit**|**Note or Test Condition**|
|||**Min.**|**Typ.**|**Max.**|||
|Delay from CS_OCP1<br>rising edge to QR_GATE<br>falling edge|tOCP1GATE|—|—|130|ns||
|Delay from QR_GATE<br>falling edge to start of<br>GDx turn-of|tGATEGDx|1|3|5|ns|GDx driven by QR_GATE.<br>Measured up to<br>IGDx> 2 mA|
|OCP1 comparator input<br>single pulse width filter|tOCP1PW|60|—|95|ns|Shorter pulses than min.<br>are suppressed, longer<br>pulses than max. are<br>passed|
|Nominal S&H operating<br>range 0% to 100%|VCSH|0|—|VREF/2|V|CS_ICR.RANGE =00B|
|Reduced S&H operating<br>range|RRCVSH|8|—|92|%|CS_ICR.RANGE =00B<br>Operational values|
|Maximum error of<br>CS0 S&H for corrected<br>measurement (8-bit<br>result)|TET0CS0S|—|—|4.7|LSB|CS_ICR.RANGE =00B|
|Maximum error of<br>CS0 S&H for corrected<br>measurement (8-bit<br>result)|TET256CS0S|—|—|6.0|LSB|CS_ICR.RANGE =00B|
|Nominal S&H operating<br>range 0% to 100%|VCSH|0|—|VREF/6|V|CS_ICR.RANGE =11B|
|Reduced S&H operating<br>range|RRCVSH|20|—|80|%|CS_ICR.RANGE =11B<br>Operational values|
|Maximum error of<br>CS0 S&H for corrected<br>measurement (8-bit<br>result)|TET0CS0S|—|—|8.0|LSB|CS_ICR.RANGE =11B|
|Maximum error of<br>CS0 S&H for corrected<br>measurement (8-bit<br>result)|TET256CS0S|—|—|8.7|LSB|CS_ICR.RANGE =11B|
|S&H delay of input bufer|tCSHST|—|—|510|ns|Referring to jump in<br>input voltage. Limits the<br>minimum gate driver Ton<br>time.|



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## **Electrical Characteristics and Parameters** 

## **Table 24 Electrical characteristics of the ZCD pin** 

|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|Input voltage operating<br>range|VINP|–0.5|—|3.3|V||
|Input clamping current,<br>high|ICLH|—|—|100|µA||
|Zero-crossing threshold|VZCTHR|15|40|70|mV||
|Comparator propagation<br>delay|tZCPD|30|50|70|ns|dVZCD/dt = 4 V/µs|
|Input voltage negative<br>clamping level|–VINPCLN|140|180|220|mV|Analog clamp activated|
|Nominal I/V-conversion<br>operating range 0% to<br>100%|–IIV|0|—|0.5|mA|CRNG =11BGain = 4800<br>mV/mA|
|Nominal I/V-conversion<br>operating range 0% to<br>100%|–IIV|0|—|1|mA|CRNG =10BGain = 2400<br>mV/mA|
|Nominal I/V-conversion<br>operating range 0% to<br>100%|–IIV|0|—|2|mA|CRNG =01BGain = 1200<br>mV/mA|
|Nominal I/V-conversion<br>operating range 0% to<br>100%|–IIV|0|—|4|mA|CRNG =00BGain = 600<br>mV/mA|
|Reduced I/V-conversion<br>operating range|RRIV|5|—|80|%||
|Maximum error<br>for corrected ADC<br>measurement (8-bit<br>result)|TET0IV|—|—|4.1|LSB8|CRNG =00B|
|Maximum error<br>for corrected ADC<br>measurement (8-bit<br>result)|TET256IV|—|—|9.7|LSB8|CRNG =00B|
|Maximum deviation<br>between ZCD clamp<br>voltage and trim result<br>stored in OTP|EZCDClp|—|—|±5|%|–IIV> 0.25 mA|
|IV-conversion delay of<br>input bufer|tIVST|—|—|900|ns|Refers to jump in input<br>current**_12)_**|
|**(table continues...)**|||||||



> 12 Limits the minimum gate driver Ton time. 

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## **Electrical Characteristics and Parameters** 

|**Table 24**<br>**(continued) Electrical characteristics of the ZCD pin**|**Table 24**<br>**(continued) Electrical characteristics of the ZCD pin**|**Table 24**<br>**(continued) Electrical characteristics of the ZCD pin**|**Table 24**<br>**(continued) Electrical characteristics of the ZCD pin**|**Table 24**<br>**(continued) Electrical characteristics of the ZCD pin**|**Table 24**<br>**(continued) Electrical characteristics of the ZCD pin**|**Table 24**<br>**(continued) Electrical characteristics of the ZCD pin**|
|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Values**|||**Unit**|**Note or Test Condition**|
|||**Min.**|**Typ.**|**Max.**|||
|Nominal S&H input<br>voltage range 0% to<br>100%|VZSH|0|—|2/3 · VREF|V|SHRNG =0B|
|Nominal S&H input<br>voltage range 0% to<br>100%|VZSH|VREF/2|—|7/6 · VREF|V|SHRNG =1B|
|Reduced S&H input<br>voltage range|RRZVSH|4|—|95|%||
|Maximum error<br>for corrected ADC<br>measurement (8-bit<br>result)|TET0ZVS0|—|—|3.7|LSB8|SHRNG =0B|
|Maximum error<br>for corrected ADC<br>measurement (8-bit<br>result)|TET256ZVS0|—|—|4.9|LSB8|SHRNG =0B|
|Maximum error<br>for corrected ADC<br>measurement (8-bit<br>result)|TET0ZVS1|—|—|4.2|LSB8|SHRNG =1B|
|Maximum error<br>for corrected ADC<br>measurement (8-bit<br>result)|TET256ZVS1|—|—|5.8|LSB8|SHRNG =1B|
|S&H delay of input bufer<br>referring to jump of input<br>voltage|tZSHST|—|—|1.0|µs|SHRNG =0BTj≤ 125 °C|
|S&H delay of input bufer<br>referring to jump of input<br>voltage|tZSHST|—|—|1.6|µs|SHRNG =1BTj≤ 125 °C|



## **Table 25 Electrical characteristics of the HV pin** 

|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|Current for VCCcap<br>charging|ILD|3.0|5|7.5|mA|VHV= 30 V; VVCC< VVCCon–<br>0.3 V; Tj≥ 0°C|
|Current for VCCcap<br>charging|ILD|2.4|5|7.5|mA|VHV= 30 V; VVCC< VVCCon–<br>0.3 V;-25°C < Tj< 0°C|
|Current for VCCcap<br>charging|ILD|2.0|5|7.5|mA|VHV= 30 V; VVCC< VVCCon–<br>0.3 V;Tj< -25°C|



**(table continues...)** 

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## **Electrical Characteristics and Parameters** 

**Table 25 (continued) Electrical characteristics of the HV pin** 

|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|Nominal current for<br>measurement path 0% to<br>100%|IMEAS|0|—|9.6|mA|CURRNG = 11B|
|Nominal current for<br>measurement path 0% to<br>100%|IMEAS|0|—|4.8|mA|CURRNG = 10B|
|Nominal current for<br>measurement path 0% to<br>100%|IMEAS|0|—|1.6|mA|CURRNG = 01B|
|Comparator threshold (in<br>% of full range of IMEAS)|THRCOMP|15|20|25|%|COMPTHR= 00B|
|Comparator threshold (in<br>% of full range of IMEAS)|THRCOMP|25|30|35|%|COMPTHR= 01B|
|Comparator threshold (in<br>% of full range of IMEAS)|THRCOMP|45|50|55|%|COMPTHR= 11B|



## **Table 26** 

## **Electrical characteristics of the PWM pin** 

|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|MFIO reference voltage|VMFIOREF|—|VVDDP|—|V|Selection = VVDDP, not<br>power down|
|Input low voltage|VIL|—|—|1.0|V||
|Input high voltage|VIH|2.0|—|—|V||
|Pull-up resistor tolerance|ΔRPU|—|—|±20|%|Overall tolerance|
|PWM frequency|fPWM|500|—|2000|Hz||



## **Table 27 Electrical characteristics of the UART pin** 

|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|Input clamping current,<br>low|–ICLL|—|—|100|µA|only digital input|
|Input clamping current,<br>high|ICLH|—|—|100|µA|only digital input|
|Input capacitance|CINPUT|—|—|25|pF||
|Input low voltage|VIL|—|—|1.0|V||
|Input high voltage|VIH|2.1|—|—|V||
|Input low current with<br>active weak pull-up WPU|–ILPU|30|—|90|µA|Measured at max. VIL|



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## **Electrical Characteristics and Parameters** 

|**Table 27**<br>**(continued) Electrical characteristics of the UART pin**|**Table 27**<br>**(continued) Electrical characteristics of the UART pin**|**Table 27**<br>**(continued) Electrical characteristics of the UART pin**|**Table 27**<br>**(continued) Electrical characteristics of the UART pin**|**Table 27**<br>**(continued) Electrical characteristics of the UART pin**|**Table 27**<br>**(continued) Electrical characteristics of the UART pin**|**Table 27**<br>**(continued) Electrical characteristics of the UART pin**|
|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Values**|||**Unit**|**Note or Test Condition**|
|||**Min.**|**Typ.**|**Max.**|||
|Max. input frequency|fINPUT|15|—|—|MHz||
|Output low voltage|VOL|—|—|0.8|V|IOL= 2 mA|
|Output high voltage|VOH|2.4|—|—|V|IOH= –2 mA|
|Output sink current|IOL|—|—|2|mA||
|Output source current|-IOH|—|—|2|mA||
|Output rise time (0 → 1)|tRISE|—|—|50|ns|20 pF load, push/pull<br>output|
|Output fall time (1 → 0)|tFALL|—|—|50|ns|20 pF load, push/pull or<br>open-drain output|
|Max. output switching<br>frequency|fSWITCH|10|—|—|MHz||
|UART baudrate|fUART|-10%|57600|+10%|baud||



|**Table 28**<br>**Electrical characteristics of the A/D converter**|**Table 28**<br>**Electrical characteristics of the A/D converter**|**Table 28**<br>**Electrical characteristics of the A/D converter**|**Table 28**<br>**Electrical characteristics of the A/D converter**|**Table 28**<br>**Electrical characteristics of the A/D converter**|**Table 28**<br>**Electrical characteristics of the A/D converter**|**Table 28**<br>**Electrical characteristics of the A/D converter**|
|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Values**|||**Unit**|**Note or Test Condition**|
|||**Min.**|**Typ.**|**Max.**|||
|Integral non-linearity|INL|—|—|1|LSB8|**_13)_**|



## **Electrical characteristics of the reference voltage** 

||||||||
|---|---|---|---|---|---|---|
|**Table 29**<br>**Electrical characte**||**ristics of the reference voltage**|||||
|**Parameter**|**Symbol**|**Values**|||**Unit**|**Note or Test Condition**|
|||**Min.**|**Typ.**|**Max.**|||
|Reference voltage|VREF|—|2.428|—|V||
|VREF overall tolerance|ΔVREF|—|—|±1.5|%|Trimmed, Tj≤ 125 °C and<br>aging|



## **Table 30 Electrical characteristics of the OTP programming** 

|**Parameter**|**Symbol**|**Values**|**Values**|**Values**|**Unit**|**Note or Test Condition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|OTP programming<br>voltage at the VCC pin for<br>range C000Hto CFFFH|VPP|7.35|7.5|7.65|V|Operational values|
|OTP programming<br>current|IPP|—|1.6|—|mA|Programming of 4 bits in<br>parallel|



> 13 ADC capability measured via channel MFIO without errors due to switching of neighbouring pins, e.g. gate drivers, measured with STC = 5. MFIO buffer non-linearity masked out by taking ADC output values ≥ 30 only. 

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## **Electrical Characteristics and Parameters** 

|**Table 31**<br>**Electrical characteristics of the clock oscillators**|**Table 31**<br>**Electrical characteristics of the clock oscillators**|**Table 31**<br>**Electrical characteristics of the clock oscillators**|**Table 31**<br>**Electrical characteristics of the clock oscillators**|**Table 31**<br>**Electrical characteristics of the clock oscillators**|**Table 31**<br>**Electrical characteristics of the clock oscillators**|**Table 31**<br>**Electrical characteristics of the clock oscillators**|
|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Values**|||**Unit**|**Note or Test Condition**|
|||**Min.**|**Typ.**|**Max.**|||
|Master clock oscillation<br>period including all<br>variations|tMCLK|15.0|15.8|16.6|ns|In reference to 66 MHz<br>fMCLK|
|Main clock oscillator<br>frequency variation<br>of stored DPARAM<br>frequency|ΔMCLK|–3.2|—|+3.5|%|Temperature drif and<br>aging only, 66 MHz fMCLK|
|Standby clock oscillator<br>frequency|fSTBCLK|96|100|104|kHz|Trimming tolerance at<br>TA= 25 °C|
|Standby clock oscillator<br>frequency|fSTBCLK|90|100|110|kHz|Overall tolerance, Tj≤<br>125 °C|



|**Table 32**<br>**Electrical characteristics of the temperature sensor**|**Table 32**<br>**Electrical characteristics of the temperature sensor**|**Table 32**<br>**Electrical characteristics of the temperature sensor**|**Table 32**<br>**Electrical characteristics of the temperature sensor**|**Table 32**<br>**Electrical characteristics of the temperature sensor**|**Table 32**<br>**Electrical characteristics of the temperature sensor**|**Table 32**<br>**Electrical characteristics of the temperature sensor**|
|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Values**|||**Unit**|**Note or Test Condition**|
|||**Min.**|**Typ.**|**Max.**|||
|Temperature sensor ADC<br>output operating range|ADCTEMP|0|—|190|LSB|ADCTEMP= 40 +<br>temperature / °C)|
|Temperature sensor<br>tolerance|ΔTEMP|—|—|±6|K|Incl. ADC conversion<br>accuracy at 3 σ|



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**7 Package dimensions** 

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## **Package dimensions** 

The package dimensions of PG-DSO-8 are provided. 

**==> picture [213 x 101] intentionally omitted <==**

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**Figure 25 Package dimensions for PG-DSO-8** 

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## **Package dimensions** 

**==> picture [196 x 98] intentionally omitted <==**

## **Figure 26 Tape and reel for PG-DSO-8** 

_Note: You can find all of our packages, packing types and other package information on our Infineon Internet page “Products”: http://www.infineon.com/products._ 

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## **References** 

## **8 References** 

**1.** Infineon Technologies AG: _XDPL8210 Design Guide_ 

**2.** Infineon Technologies AG: _XDPL8210 CDM10VD 35 W reference design with IPN80R900P7_ 

**3.** Infineon Technologies AG: _CoolMOS P7 power MOSFETs_ , _**http://www.infineon.com/P7**_ 

**4.** Infineon Technologies AG: _.dp Vision User Manual_ 

**5.** Infineon Technologies AG: _.dp Interface Gen2_ which can be ordered at _**https:// www.infineon.com/cms/en/product/evaluation-boards/if-board.dp-gen2/**_ 

**6.** Infineon Technologies AG: _.dp Interface Gen2 User Manual_ 

**7.** Infineon Technologies AG: _XDP Programming Manual_ 

## **Revision History** 

Major changes since previous revision 

|**7.**<br>Infineon Technologies AG:_XDP Programming Manual_<br>**Revision History**<br>Major changes since previous revision|**7.**<br>Infineon Technologies AG:_XDP Programming Manual_<br>**Revision History**<br>Major changes since previous revision|
|---|---|
|||
|**Revision History**||
|**Revision**|**Description**|
|1.1|•<br>Remove DC input related text<br>•<br>Update .dp Interface Gen2 ordering link<br>•<br>Remove_D_DIM,maxfrom list of fixed parameters<br>•<br>Add_D_DIM,max,_f_PWM,maxand_f_PWM,minto list of configurable parameters<br>•<br>Change maximum value of configurable parameter_D_DIM,min<br>•<br>Change minimum value of configurable parameter_D_DIM,of|
|1.0|Initial release|



## **Glossary** 

## **ABM** 

## _Active Burst Mode (ABM)_ 

Active Burst Mode is an operating mode of a switched-mode power supply for very light load conditions. The controller switches in bursts of pulses with a pause between bursts in which no switching is done. 

## **CC** 

## _Constant Current (CC)_ 

Constant Current is a mode of a power supply in which the output current is kept constant regardless of the load. 

## **CRC** 

## _Cyclic Redundancy Check_ 

A cyclic redundancy check is an error-detecting code commonly used to detect accidental changes to raw data. 

## **DCM** 

## _Discontinuous Conduction Mode (DCM)_ 

Discontinuous Conduction Mode is an operational mode of a switching power supply in which the current starts and returns to zero. 

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## **Glossary** 

## **ECG** 

## _Electronic Control Gear (ECG)_ 

An electronic control gear is a power supply which provides one or more light module(s) with the appropriate voltage or current. 

## **EMI** 

## _Electro-Magnetic Interference (EMI)_ 

Also called Radio Frequency Interference (RFI), this is a (usually undesirable) disturbance that affects an electrical circuit due to electromagnetic radiation emitted from an external source. The disturbance may interrupt, obstruct, or otherwise degrade or limit the effective performance of the circuit. 

## **FB** 

## _Flyback (FB)_ 

A flyback converter is a power converter with the inductor split to form a transformer, so that the voltage ratios are multiplied with an additional advantage of galvanic isolation between the input and any outputs. 

## **GUI** 

## _Graphic User Interface_ 

A graphical user interface is a type of interface that allows users to interact with electronic devices through graphical icons and visual indicators. 

## **IC** 

## _Integrated Circuit (IC)_ 

A miniaturized electronic circuit that has been manufactured in the surface of a thin substrate of semiconductor material. An IC may also be referred to as micro-circuit, microchip, silicon chip, or chip. 

## **LED** 

## _Light Emitting Diode (LED)_ 

A light-emitting diode is a two-lead semiconductor light source which emits light when activated. 

## **LP** 

## _Limited Power (LP)_ 

Limited Power is a mode of a power supply in which the output power is limited regardless of the load. 

## **MCU** 

## _Microcontroller Unit (MCU)_ 

A microcontroller is a small computer on a single integrated circuit containing a processor core, memory, and programmable input/output peripherals. 

## **PC** 

## _Personal Computer_ 

A personal computer is a general-purpose computer whose size, capabilities, and original sale price make it useful for individuals, and which is intended to be operated directly by an end-user with no intervening computer time-sharing models that allowed larger, more expensive minicomputer and mainframe systems to be used by many people, usually at the same time. 

## **PFC** 

## _Power Factor Correction (PFC)_ 

Power factor correction increases the power factor of an AC power circuit closer to 1 which corresponds to minimizing the reactive power of the power circuit. 

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## **Glossary** 

## **PF** 

_Power Factor (PF)_ 

Power factor is the ratio between the real power and the apparent power. 

## **PWM** 

## _Pulse Width Modulation (PWM)_ 

Pulse-width modulation is a technique to encode an analog value into the duty cycle of a pulsing signal with arbitrary amplitude. 

## **QRM1** 

_Quasi-Resonant Mode, switching in first valley (QRM1)_ 

Quasi-Resonant Mode is an operating mode of a switched-mode power supply which maximizes efficiency. This is achieved by switching at the occurrence of the first valley of a signal which corresponds to a time when switching losses are low. 

## **THD** 

## _Total Harmonic Distortion (THD)_ 

The total harmonic distortion of a signal is a measurement of the harmonic distortion present and is defined as the ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency. 

## **UART** 

## _Universal Asynchronous Receiver Transmitter_ 

A universal asynchronous receiver transmitter is used for serial communications over a peripheral device serial port by translating data between parallel and serial forms. 

## **USB** 

## _Universal Serial Bus_ 

Universal Serial Bus is an industry standard that defines cables, connectors and communications protocols used in a bus for connection, communication, and power supply between computers and electronic devices. 

## **UVLO** 

## _Undervoltage Lockout (UVLO)_ 

The Undervoltage-Lockout is an electronic circuit used to turn off the power of an electronic device in the event of the voltage dropping below the operational value. 

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## **Trademarks** 

All referenced product or service names and trademarks are the property of their respective owners. 

**Edition 2021-06-25 IMPORTANT NOTICE Published by** The information given in this document shall in no event be regarded as a guarantee of conditions or **Infineon Technologies AG** characteristics (“Beschaffenheitsgarantie”). **81726 Munich, Germany** With respect to any examples, hints or any typical values stated herein and/or any information regarding **© 2021 Infineon Technologies AG** the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities **All Rights Reserved.** of any kind, including without limitation warranties of non-infringement of intellectual property rights of any **Do you have a question about any** third party. **aspect of this document?** In addition, any information given in this document is **Email: erratum@infineon.com** subject to customer’s compliance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning **Document reference** customer’s products and any use of the product of **IFX-jtr1464681287355** Infineon Technologies in customer’s applications. 

## **WARNINGS** 

Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office. 

Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury. 

The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer’s technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application.
Updated at March 15, 2026
Infineon Technologies is a globally recognized leader in semiconductor solutions, renowned for driving innovation in power management, energy efficiency, and modern mobility. With a strong legacy of engineering excellence, the company provides highly reliable components designed to meet the rigorous demands of industrial, automotive, and advanced commercial applications. The core of our Infineon portfolio is centered on their industry-leading discrete semiconductors. We offer an extensive selection of single and dual MOSFETs, alongside a robust range of single IGBTs and advanced IGBT modules. These flagship power transistors are essential for high-efficiency power conversion and motor control, providing engineers with superior thermal performance and minimized switching losses. Beyond advanced field-effect transistors, the selection includes a comprehensive array of diodes and rectifiers, heavily featuring Schottky diodes, as well as fast-recovery and RF/PIN diodes. This power foundation is further supported by bipolar transistors, intelligent power modules, and thyristor SCR modules, delivering the critical building blocks required for complex power system designs. To support broader system integration, the portfolio also encompasses specialized solutions such as solid-state relays, AC/DC LED driver ICs, and Bluetooth communications modules. From high-power industrial rectifiers to wireless connectivity adapters, Infineon equips designers with the precision components needed to build efficient, scalable, and fully connected electronic systems.
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