XCVU7P-2FLVA2104I

FPGA, Virtex UltraScale, 832 I/O's, 1724100 Logic Cells, 2 Speed Grade, -40 to 100°C, FCBGA-2104

⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
Manufacturer: AMD
Product type: FPGAs
No. of Logic Blocks:788160; No. of Macrocells:1724100; FPGA Family:Virtex UltraScale+; Logic Case Style:FCBGA; No. of Pins:2104Pins; No. of Speed Grades:2; Total RAM Bits:51814.4Kbit
SVHC: No SVHC (15-Jan-2018)
FPGA Type: -
FPGA Family: Virtex UltraScale+
IC Mounting: Surface Mount
No. of Pins: 2104Pins
Speed Grade: 2
No. of I/O's: 832I/O's
Product Range: Virtex UltraScale+ XCVU7P
Qualification: -
Total RAM Bits: 51814.4Kbit
No.of User I/Os: 832I/O's
Clock Management: MMCM, PLL
Logic Case Style: FCBGA
IC Case / Package: FCBGA
No. of Macrocells: 1724100Macrocells
I/O Supply Voltage: 3.3V
No. of Logic Cells: 1724100Logic Cells
Process Technology: -
No. of Logic Blocks: 1724100
No. of Speed Grades: 2
Core Supply Voltage Max: 876mV
Core Supply Voltage Min: 825mV
Operating Frequency Max: 775MHz
Operating Temperature Max: 100°C
Operating Temperature Min: -40°C
Delivery and price
Units per pack	1
Price	29893.2 €
Current stock	10+
Lead time	30 days
Datasheet
## **Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics** 

DS923 (v1.10) April 26, 2019 

**Product Specification** 

## **Summary** 

The Xilinx[®] Virtex[®] UltraScale+™ FPGAs are available in -3, -2, -1 speed grades, with -3E devices having the highest performance. The -2LE devices can operate at a VCCINT voltage at 0.85V or 0.72V and provide lower maximum static power. When operated at VCCINT = 0.85V, using -2LE devices, the speed specification for the L devices is the same as the -2I speed grade. When operated at VCCINT = 0.72V, the -2LE performance and static and dynamic power is reduced. 

DC and AC characteristics are specified in extended (E), industrial (I), and military (M) temperature ranges. Except the operating temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -1 speed grade extended device are the same as for a -1 speed grade industrial device). However, only selected speed grades and/or devices are available in each temperature range. 

The XQ references in this data sheet are specific to the devices available in XQ Ruggedized packages. See the _Defense-Grade UltraScale Architecture Data Sheet: Overview_ (DS895) for further information on XQ Defensegrade part numbers, packages, and ordering information. 

All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters included are common to popular designs and typical applications. 

This data sheet, part of an overall set of documentation on the Virtex UltraScale+ FPGAs, is available on the Xilinx website at www.xilinx.com/documentation. 

## **DC Characteristics** 

## **Absolute Maximum Ratings** 

|**Absolute Maximum Ratings**|**Absolute Maximum Ratings**|**Absolute Maximum Ratings**|**Absolute Maximum Ratings**|**Absolute Maximum Ratings**|
|---|---|---|---|---|
|_Table 1:_**Absolute Maximum Ratings**|||||
|**Symbol**|**Description**1|**Min**|**Max**|**Units**|
|**FPGA Logic**|||||
|VCCINT|Internal supply voltage|–0.500|1.000|V|
|VCCINT_IO2|Internal supply voltage for the I/O banks|–0.500|1.000|V|
|VCCAUX|Auxiliary supply voltage|–0.500|2.000|V|



> © Copyright 2016–2019 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, ISE, Kintex, Spartan, Versal, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI, PCIe, and PCI Express are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners. DS923 (v1.10) April 26, 2019 www.xilinx.com 

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Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|
|_Table 1:_**Absolute Maximum Ratings**_(cont'd)_|||||
|**Symbol**|**Description**1|**Min**|**Max**|**Units**|
|VCCBRAM|Supply voltage for the block RAM memories|–0.500|1.000|V|
|VCCO|Output drivers supply voltage for HP I/O banks|–0.500|2.000|V|
|VCCAUX_IO3|Auxiliary supply voltage for the I/O banks|–0.500|2.000|V|
|VREF|Input reference voltage|–0.500|2.000|V|
|VIN4,5,6|I/O input voltage for HP I/O banks|–0.550|VCCO+ 0.550|V|
|VBATT|Key memory battery backup supply|–0.500|2.000|V|
|IDC|Available output current at the pad|–20|20|mA|
|IRMS|Available RMS output current at the pad|–20|20|mA|
|High Bandwidth Memory (HBM)|||||
|VCC_HBM|Supply voltage for the high-bandwidth memory|–0.300|1.500|V|
|VCC_IO_HBM|I/O supply voltage for the high-bandwidth memory|–0.300|1.500|V|
|VCCAUX_HBM|Auxiliary supply voltage for the high-bandwidth memory|–0.300|3.000|V|
|GTY or GTM Transceiver7|||||
|VCCINT_GT|Digital supply voltage for select modules in the GTM transceivers|–0.500|1.000|V|
|VMGTAVCC|Analog supply voltage for transceiver circuits|–0.500|1.000|V|
|VMGTAVTT|Analog supply voltage for transceiver termination circuits|–0.500|1.300|V|
|VMGTVCCAUX|Auxiliary analog Quad PLL (QPLL) voltage supply for transceivers|–0.500|1.900|V|
|VMGTREFCLK|Transceiver reference clock absolute input voltage|–0.500|1.300|V|
|VMGTAVTTRCAL|Analog supply voltage for the resistor calibration circuit of the<br>transceiver column|–0.500|1.300|V|
|VIN|Receiver (RXP/RXN) and transmitter (TXP/TXN) absolute input<br>voltage|–0.500|1.200|V|
|IDCIN-FLOAT|DC input current for receiver input pins DC coupled RX<br>termination = floating8|–|10|mA|
|IDCIN-MGTAVTT|DC input current for receiver input pins DC coupled RX<br>termination = VMGTAVTT|–|10|mA|
|IDCIN-GND|DC input current for receiver input pins DC coupled RX<br>termination = GND9|–|0|mA|
|IDCIN-PROG|DC input current for receiver input pins DC coupled RX<br>termination = programmable10|–|0|mA|
|IDCOUT-FLOAT|DC output current for transmitter pins DC coupled RX<br>termination = floating|–|6|mA|
|IDCOUT-MGTAVTT|DC output current for transmitter pins DC coupled RX<br>termination = VMGTAVTT|–|6|mA|
|**System Monitor**|||||
|VCCADC|System Monitor supply relative to GNDADC|–0.500|2.000|V|
|VREFP|System Monitor reference input relative to GNDADC|–0.500|2.000|V|
|**Temperature**11|||||
|TSTG|Storage temperature for XCVU31P, XCVU33P, XCVU35P, XCVU37P12|–55|120|°C|
||Storage temperature (ambient) for all other devices|–65|150|°C|
|TSOL|Maximum dry rework soldering temperature|–|260|°C|
||Maximum reflow soldering temperature for FFVC1517, FLGF1924,<br>FHGA2104, FHGB2104, FHGC2104, FLGA2104, FLGB2104, FLGC2104,<br>FLVA2104, FLVB2104, FLVC2104, FLGA2577|–|245|°C|
||Maximum reflow soldering temperature for lidless packages with<br>stiffener ring (FIGD2104, FSGD2104, FSVH1924, FSVH2104,<br>FSGA2577, FSVH2892)|–|240|°C|



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Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## _Table 1:_ **Absolute Maximum Ratings** _(cont'd)_ 

|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|
|_Table 1:_**Absolute Maximum Ratings**_(cont'd)_|||||
|**Symbol**|**Description**1|**Min**|**Max**|**Units**|
|Tj|Maximum junction temperature for XCVU31P, XCVU33P, XCVU35P,<br>XCVU37P|–|120|°C|
||Maximum junction temperature for all other devices|–|125|°C|
|**Notes:**<br>1.<br>Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings<br>only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not<br>implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.<br>2.<br>VCCINT_IOmust be connected to VCCBRAM.<br>3.<br>VCCAUX_IOmust be connected to VCCAUX.<br>4.<br>The lower absolute voltage specification always applies.<br>5.<br>For I/O operation, see the_UltraScale Architecture SelectIO Resources User Guide_(UG571).<br>6.<br>When operating outside of the recommended operating conditions, refer toTable 4for maximum overshoot and undershoot<br>specifications.<br>7.<br>For more information on supported GTY transceiver terminations see the_UltraScale Architecture GTY Transceivers User Guide_(UG578) or<br>_Virtex UltraScale+ FPGAs GTM Transceivers User Guide_(UG581).<br>8.<br>AC coupled operation is not supported for RX termination = floating.<br>9.<br>For GTY transceivers, DC coupled operation is not supported for RX termination = GND.<br>10.<br>DC coupled operation is not supported for RX termination = programmable.<br>11.<br>For soldering guidelines and thermal considerations, see the_UltraScale and UltraScale+ FPGAs Packaging and Pinouts Product Specification_<br>(UG575).<br>12.<br>For devices with high-bandwidth memory (HBM), the storage temperature is the case surface temperature on the center/top side of the<br>device. For the measurement conditions, refer to the JESD51-2 standard.|||||



## **Recommended Operating Conditions** 

|**Recommended Operating Conditions**|**Recommended Operating Conditions**|**Recommended Operating Conditions**|**Recommended Operating Conditions**|**Recommended Operating Conditions**|**Recommended Operating Conditions**|
|---|---|---|---|---|---|
|_Table 2:_**Recommended Operating Conditions**||||||
|**Symbol**|**Description**1**,**2|**Min**|**Typ**|**Max**|**Units**|
|**FPGA Logic**||||||
|VCCINT|Internal supply voltage|0.825|0.850|0.876|V|
||For -2LE (VCCINT= 0.72V) devices: internal supply voltage|0.698|0.720|0.742|V|
||For -3E devices: internal supply voltage|0.873|0.900|0.927|V|
|VCCINT_IO3|Internal supply voltage for the I/O banks|0.825|0.850|0.876|V|
||For -2LE (VCCINT= 0.72V) devices: internal supply voltage for the<br>I/O banks|0.825|0.850|0.876|V|
||For -3E devices: internal supply voltage for the I/O banks|0.873|0.900|0.927|V|
|VCCBRAM|Block RAM supply voltage|0.825|0.850|0.876|V|
||For -3E devices: block RAM supply voltage|0.873|0.900|0.927|V|
|VCCAUX|Auxiliary supply voltage|1.746|1.800|1.854|V|
|VCCO4,5|Supply voltage for I/O banks|0.950|–|1.900|V|
|VCCAUX_IO6|Auxiliary I/O supply voltage|1.746|1.800|1.854|V|
|VIN7|I/O input voltage|–0.200|–|VCCO+ 0.200|V|
|IIN8|Maximum current through any pin in a powered or unpowered<br>bank when forward biasing the clamp diode|–|–|10|mA|
|VBATT9|Battery voltage|1.000|–|1.890|V|
|High Bandwidth Memory||||||
|VCC_HBM|Supply voltage for the high-bandwidth memory (HBM)|1.164|1.200|1.236|V|



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Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|
|_Table 2:_**Recommended Operating Conditions**_(cont'd)_||||||
|**Symbol**|**Description**1**,**2|**Min**|**Typ**|**Max**|**Units**|
|VCC_IO_HBM|I/O supply voltage for the high-bandwidth memory|1.164|1.200|1.236|V|
|VCCAUX_HBM|Auxiliary supply voltage for the high-bandwidth memory|2.425|2.500|2.575|V|
|**GTY or GTM Transceiver**||||||
|VCCINT_GT|Digital supply voltage for select modules in the GTM<br>transceivers|0.825|0.850|0.876|V|
||For -3E devices: Digital supply voltage for select modules in the<br>GTM transceivers supply voltage|0.873|0.900|0.927|V|
|VMGTAVCC10|Analog supply voltage for the GTY or GTM transceiver|0.873|0.900|0.927|V|
|VMGTAVTT10|Analog supply voltage for the GTY or GTM transmitter and<br>receiver termination circuits|1.164|1.200|1.236|V|
|VMGTVCCAUX10|Auxiliary analog QPLL voltage supply for the transceivers|1.746|1.800|1.854|V|
|VMGTAVTTRCAL10|Analog supply voltage for the resistor calibration circuit of the<br>GTY or GTM transceiver column|1.164|1.200|1.236|V|
|**System Monitor**||||||
|VCCADC|System Monitor supply relative to GNDADC|1.746|1.800|1.854|V|
|VREFP|System Monitor externally supplied reference voltage relative to<br>GNDADC|1.200|1.250|1.300|V|



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Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|
|_Table 2:_**Recommended Operating Conditions**_(cont'd)_||||||
|**Symbol**|**Description**1**,**2|**Min**|**Typ**|**Max**|**Units**|
|**Temperature**||||||
|Tj11|Junction temperature operating range for XCVU31P, XCVU33P,<br>XCVU35P, and XCVU37P extended (E) temperature devices12,13,<br>14|0|–|100|°C|
||Junction temperature operating range for all other extended (E)<br>temperature devices12|0|–|100|°C|
||Junction temperature operating range for industrial (I)<br>temperature devices|–40|–|100|°C|
||Junction temperature operating range for eFUSE<br>programming15|–40|–|125|°C|
|**Notes:**<br>1.<br>All voltages are relative to GND.<br>2.<br>For the design of the power distribution system consult the_UltraScale Architecture PCB Design User Guide_(UG583).<br>3.<br>VCCINT_IOmust be connected to VCCBRAM.<br>4.<br>For VCCO_0, the minimum recommended operating voltage for power on and during configuration is 1.425V. After configuration, data is<br>retained even if VCCOdrops to 0V.<br>5.<br>Includes VCCOof 1.0V, 1.2V, 1.35V, 1.5V, and1.8V.<br>6.<br>VCCAUX_IOmust be connected to VCCAUX.<br>7.<br>The lower absolute voltage specification always applies.<br>8.<br>A total of 200 mA per bank should not be exceeded.<br>9.<br>If battery is not used, connect VBATTto either GND or VCCAUX.<br>10.<br>Each voltage listed requires filtering as described in the_UltraScale Architecture GTY Transceivers User Guide_(UG578) or the_Virtex UltraScale_<br>_+ FPGAs GTM Transceivers User Guide_(UG581).<br>11.<br>Xilinx recommends measuring the Tjof a device using the system monitor as described in the_UltraScale Architecture System Monitor User_<br>_Guide_(UG580). The system monitor temperature measurement errors (that are described inTable 74) must be accounted for in your<br>design. For example, when using the system monitor with an external reference of 1.25V, and when the system monitor reports 97°C,<br>there is a measurement error ±3°C. A reading of 97°C is considered the maximum adjusted Tj(100°C – 3°C = 97°C).<br>12.<br>Devices labeled with the speed/temperature grade of -2LE can operate for a limited time at a junction temperature between 100°C and<br>110°C. Timing parameters adhere to the same speed file at 110°C as they do below 110°C, regardless of operating voltage (nominal<br>voltage of 0.85V or a low-voltage of 0.72V). Operation up to Tj= 110°C is limited to 1% of the device lifetime and can occur sequentially or<br>at regular intervals as long as the total time does not exceed 1% of the device lifetime.<br>13.<br>The recommended maximum operating temperature for high-bandwidth memory is 95°C.<br>14.<br>Devices with HBM and labeled with the speed/temperature grade of -2LE can operate for a limited time at a junction temperature<br>between 95°C and 105°C. HBM operation up to Tj= 105°C is limited to 4.1% of the device lifetime and can occur sequentially or at regular<br>intervals as long as the total time does not exceed 4.1% of the device lifetime, and for no longer than 96 hours at a time. While operating<br>the HBM above 95°C, the refresh rate must be at least 4x the refresh rate at 95°C.<br>15.<br>Do not program eFUSE during device configuration (e.g., during configuration, during configuration readback, or when readback CRC is<br>active).||||||



## **DC Characteristics Over Recommended Operating Conditions** 

## _Table 3:_ **DC Characteristics Over Recommended Operating Conditions** 

|**DC Characteristics Over Recommended Operating Conditions**|**DC Characteristics Over Recommended Operating Conditions**|**DC Characteristics Over Recommended Operating Conditions**|**DC Characteristics Over Recommended Operating Conditions**|**DC Characteristics Over Recommended Operating Conditions**|**DC Characteristics Over Recommended Operating Conditions**|
|---|---|---|---|---|---|
|_Table 3:_**DC Characteristics Over Recommended Operating Conditions**||||||
|**Symbol**|**Description**|**Min**|**Typ**1|**Max**|**Units**|
|VDRINT|Data retention VCCINTvoltage (below which configuration data<br>might be lost)|0.68|–|–|V|
|VDRAUX|Data retention VCCAUXvoltage (below which configuration data<br>might be lost)|1.5|–|–|V|
|IREF|VREFleakage current per pin|–|–|15|µA|
|IL|Input or output leakage current per pin (sample-tested)2|–|–|15|µA|
|CIN3|Die input capacitance at the pad|–|–|3.1|pF|



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Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

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|---|---|---|---|---|---|
|_Table 3:_**DC Characteristics Over Recommended Operating Conditions**_(cont'd)_||||||
|**Symbol**|**Description**|**Min**|**Typ**1|**Max**|**Units**|
|IRPU|Pad pull-up (when selected) at VIN= 0V, VCCO= 1.8V|60|–|120|µA|
||Pad pull-up (when selected) at VIN= 0V, VCCO= 1.5V|30|–|120|µA|
||Pad pull-up (when selected) at VIN= 0V, VCCO= 1.2V|10|–|100|µA|
|IRPD|Pad pull-down (when selected) at VIN= 1.8V|29|–|120|µA|
|ICCADCON|Analog supply current for the SYSMON circuits in the power-up<br>state|–|–|8|mA|
|ICCADCOFF|Analog supply current for the SYSMON circuits in the power-down<br>state|–|–|1.5|mA|
|IBATT4,5|Battery supply current at VBATT= 1.89V|–|–|650|nA|
||Battery supply current at VBATT= 1.20V|–|–|150|nA|
|IPFS6|VCCAUXadditional supply current during eFUSE programming|–|–|115|mA|
|Calibrated programmable on-die termination (DCI) in I/O banks7(measured per JEDEC specification)||||||
|R9|Thevenin equivalent resistance of programmable input<br>termination to VCCO/2 where ODT = RTT_40|–10%8|40|+10%8|Ω|
||Thevenin equivalent resistance of programmable input<br>termination to VCCO/2 where ODT = RTT_48|–10%8|48|+10%8|Ω|
||Thevenin equivalent resistance of programmable input<br>termination to VCCO/2 where ODT = RTT_60|–10%8|60|+10%8|Ω|
||Programmable input termination to VCCOwhere ODT = RTT_40|–10%8|40|+10%8|Ω|
||Programmable input termination to VCCOwhere ODT = RTT_48|–10%8|48|+10%8|Ω|
||Programmable input termination to VCCOwhere ODT = RTT_60|–10%8|60|+10%8|Ω|
||Programmable input termination to VCCOwhere ODT = RTT_120|–10%8|120|+10%8|Ω|
||Programmable input termination to VCCOwhere ODT = RTT_240|–10%8|240|+10%8|Ω|
|Uncalibrated programmable on-die termination in HP I/Os banks (measured per JEDEC specification)||||||
|R9|Thevenin equivalent resistance of programmable input<br>termination to VCCO/2 where ODT = RTT_40|–50%|40|+50%|Ω|
||Thevenin equivalent resistance of programmable input<br>termination to VCCO/2 where ODT = RTT_48|–50%|48|+50%|Ω|
||Thevenin equivalent resistance of programmable input<br>termination to VCCO/2 where ODT = RTT_60|–50%|60|+50%|Ω|
||Programmable input termination to VCCOwhere ODT = RTT_40|–50%|40|+50%|Ω|
||Programmable input termination to VCCOwhere ODT = RTT_48|–50%|48|+50%|Ω|
||Programmable input termination to VCCOwhere ODT = RTT_60|–50%|60|+50%|Ω|
||Programmable input termination to VCCOwhere ODT = RTT_120|–50%|120|+50%|Ω|
||Programmable input termination to VCCOwhere ODT = RTT_240|–50%|240|+50%|Ω|
|Internal VREF|50% VCCO|VCCOx 0.49|VCCOx 0.50|VCCOx 0.51|V|
||70% VCCO|VCCOx 0.69|VCCOx 0.70|VCCOx 0.71|V|
|Differential termination|Programmable differential termination (TERM_100) for HP I/O<br>banks|–35%|100|+35%|Ω|
|n|Temperature diode ideality factor|–|1.026|–|–|



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Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

_Table 3:_ **DC Characteristics Over Recommended Operating Conditions** _(cont'd)_ 

|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|
|_Table 3:_**DC Characteristics Over Recommended Operating Conditions**_(cont'd)_||||||
|**Symbol**|**Description**|**Min**|**Typ**1|**Max**|**Units**|
|r|Temperature diode series resistance|–|2|–|Ω|
|**Notes:**<br>1.<br>Typical values are specified at nominal voltage, 25°C.<br>2.<br>For the I/O banks with a VCCOof 1.8V and separated VCCOand VCCAUX_IOpower supplies, the ILmaximum current is 70 µA.<br>3.<br>This measurement represents the die capacitance at the pad, not including the package.<br>4.<br>Maximum value specified for worst case process at 25°C. For the XCVU5P, XCVU7P, XCVU9P, XCVU11P, XCVU13P, XCVU27P, XCVU29P,<br>XCVU35P, and XCVU37P devices, multiply the value by the number of super-logic regions (SLRs) in the device.<br>5.<br>IBATTis measured when the battery-backed RAM (BBRAM) is enabled.<br>6.<br>Do not program eFUSE during device configuration (e.g., during configuration, during configuration readback, or when readback CRC is<br>active).<br>7.<br>VRP resistor tolerance is (240Ω ±1%).<br>8.<br>If VRP resides at a different bank (DCI cascade), the range increases to ±15%.<br>9.<br>On-die input termination resistance, for more information see the_UltraScale Architecture SelectIO Resources User Guide_(UG571).||||||



## **VIN Maximum Allowed AC Voltage Overshoot and Undershoot** 

_Table 4:_ **VIN Maximum Allowed AC Voltage Overshoot and Undershoot for HP I/O Banks** 

|**VIN Maximum Allowed AC Voltage Overshoot and Undershoot**|**VIN Maximum Allowed AC Voltage Overshoot and Undershoot**|**VIN Maximum Allowed AC Voltage Overshoot and Undershoot**|**VIN Maximum Allowed AC Voltage Overshoot and Undershoot**|
|---|---|---|---|
|_Table 4:_**VIN Maximum Allowed AC Voltage Overshoot and Undershoot for HP I/O Banks**||||
|**AC Voltage Overshoot**1|**% of UI**2**at –40°C to 100°C**|**AC Voltage Undershoot**1|**% of UI**2**at –40°C to 100°C**|
|VCCO+ 0.30|100%|–0.30|100%|
|VCCO+ 0.35|100%|–0.35|100%|
|VCCO+ 0.40|92%|–0.40|92%|
|VCCO+ 0.45|50%|–0.45|50%|
|VCCO+ 0.50|20%|–0.50|20%|
|VCCO+ 0.55|10%|–0.55|10%|
|VCCO+ 0.60|6%|–0.60|6%|
|VCCO+ 0.65|2%|–0.65|2%|
|VCCO+ 0.70|2%|–0.70|2%|
|**Notes:**<br>1.<br>A total of 200 mA per bank should not be exceeded.<br>2.<br>For UI smaller than 20 µs.<br>3.<br>For the -1M devices, the temperature limits are –55°C to 125°C.||||



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Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## **Quiescent Supply Current** 

## _Table 5:_ **Typical Quiescent Supply Current** 

|**Quiescent Supply Current**|**Quiescent Supply Current**|**Quiescent Supply Current**|**Quiescent Supply Current**|**Quiescent Supply Current**|**Quiescent Supply Current**|**Quiescent Supply Current**|**Quiescent Supply Current**|
|---|---|---|---|---|---|---|---|
|_Table 5:_**Typical Quiescent Supply Current**||||||||
|**Symbol**|**Description**1**,**2**,**3|**Device**|**Speed Grade and VCCINT Operating Voltages**||||**Units**|
||||**0.90V**|**0.85V**||**0.72V**||
||||**-3**|**-2**|**-1**|**-2**||
|ICCINTQ|Quiescent VCCINTsupply current|XCVU3P|2384|2276|2276|2017|mA|
|||XCVU5P|4769|4552|4552|4034|mA|
|||XCVU7P|4769|4552|4552|4034|mA|
|||XCVU9P|7153|6828|6828|6050|mA|
|||XCVU11P|7567|7202|7202|6332|mA|
|||XCVU13P|10090|9602|9602|8442|mA|
|||XCVU31P|2528|2406|2406|2115|mA|
|||XCVU33P|2528|2406|2406|2115|mA|
|||XCVU35P|5051|4807|4807|4226|mA|
|||XCVU37P|7573|7207|7207|6336|mA|
|||XCVU27P|9962|9516|9516|8449|mA|
|||XCVU29P|9962|9516|9516|8449|mA|
|ICCINT_IOQ|Quiescent VCCINT_IOsupply current|XCVU3P|149|144|144|144|mA|
|||XCVU5P|298|287|287|287|mA|
|||XCVU7P|298|287|287|287|mA|
|||XCVU9P|447|431|431|431|mA|
|||XCVU11P|182|176|176|176|mA|
|||XCVU13P|243|234|234|234|mA|
|||XCVU31P|747|723|723|723|mA|
|||XCVU33P|747|723|723|723|mA|
|||XCVU35P|776|750|750|750|mA|
|||XCVU37P|804|778|778|778|mA|
|||XCVU27P|241|232|232|232|mA|
|||XCVU29P|241|232|232|232|mA|
|ICCOQ|Quiescent VCCOsupply current|All devices|1|1|1|1|mA|
|ICCAUXQ|Quiescent VCCAUXsupply current|XCVU3P|268|268|268|268|mA|
|||XCVU5P|535|535|535|535|mA|
|||XCVU7P|535|535|535|535|mA|
|||XCVU9P|1015|1015|1015|1015|mA|
|||XCVU11P|819|819|819|819|mA|
|||XCVU13P|1091|1091|1091|1091|mA|
|||XCVU31P|223|223|223|223|mA|
|||XCVU33P|223|223|223|223|mA|
|||XCVU35P|444|444|444|444|mA|
|||XCVU37P|665|665|665|665|mA|
|||XCVU27P|1091|1091|1091|1091|mA|
|||XCVU29P|1091|1091|1091|1091|mA|



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Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## _Table 5:_ **Typical Quiescent Supply Current** _(cont'd)_ 

|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|---|---|
|_Table 5:_**Typical Quiescent Supply Current**_(cont'd)_||||||||
|**Symbol**|**Description**1**,**2**,**3|**Device**|**Speed Grade and VCCINT Operating Voltages**||||**Units**|
||||**0.90V**|**0.85V**||**0.72V**||
||||**-3**|**-2**|**-1**|**-2**||
|ICCAUX_IOQ|Quiescent VCCAUX_IOsupply current|XCVU3P|62|62|62|62|mA|
|||XCVU5P|124|124|124|124|mA|
|||XCVU7P|124|124|124|124|mA|
|||XCVU9P|187|187|187|187|mA|
|||XCVU11P|79|79|79|79|mA|
|||XCVU13P|105|105|105|105|mA|
|||XCVU31P|27|27|27|27|mA|
|||XCVU33P|27|27|27|27|mA|
|||XCVU35P|53|53|53|53|mA|
|||XCVU37P|80|80|80|80|mA|
|||XCVU27P|105|105|105|105|mA|
|||XCVU29P|105|105|105|105|mA|
|ICCBRAMQ|Quiescent VCCBRAMsupply current|XCVU3P|45|43|43|43|mA|
|||XCVU5P|90|85|85|85|mA|
|||XCVU7P|90|85|85|85|mA|
|||XCVU9P|134|128|128|128|mA|
|||XCVU11P|130|124|124|124|mA|
|||XCVU13P|174|165|165|165|mA|
|||XCVU31P|43|41|41|41|mA|
|||XCVU33P|43|41|41|41|mA|
|||XCVU35P|87|83|83|83|mA|
|||XCVU37P|130|124|124|124|mA|
|||XCVU27P|174|165|165|165|mA|
|||XCVU29P|174|165|165|165|mA|
|**Notes:**<br>1.<br>Typical values are specified at nominal voltage, 85°C junction temperatures (Tj) with single-ended SelectIO™ resources.<br>2.<br>Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, and all I/O pins are 3-state<br>and floating.<br>3.<br>Use the Xilinx®Power Estimator (XPE) spreadsheet tool (download atwww.xilinx.com/power) to estimate static power consumption for<br>conditions or supplies other than those specified.||||||||



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Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## **Power Supply Sequencing** 

## **Power-On/Off Power Supply Sequencing** 

The recommended power-on sequence is VCCINT, VCCINT_IO/VCCBRAM, VCCAUX/VCCAUX_IO, and VCCO to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on. The recommended power-off sequence is the reverse of the power-on sequence. If VCCINT and VCCINT_IO/VCCBRAM have the same recommended voltage levels, they can be powered by the same supply and ramped simultaneously. VCCINT_IO must be connected to VCCBRAM. If VCCAUX/VCCAUX_IO and VCCO have the same recommended voltage levels, they can be powered by the same supply and ramped simultaneously. VCCAUX and VCCAUX_IO must be connected together. VCCADC and VREF can be powered at any time and have no power-up sequencing requirements. 

For devices with HBM, the HBM power supplies can be powered on/off after or in-parallel with the core power supplies. The required power-on sequence is VCCAUX_HBM and VCCINT_IO followed by VCC_HBM/VCC_IO_HBM. VCC_IO_HBM must be connected to VCC_HBM. VCCAUX_HBM must be equal to or higher than VCC_HBM at all times. The recommended power-off sequence is the reverse of the power-on sequence. 

The recommended power-on sequence to achieve minimum current draw for the GTY or GTM transceivers is VCCINT, VCCINT_GT, VMGTAVCC, VMGTAVTT OR VMGTAVCC, VCCINT, VCCINT_GT, VMGTAVTT. There is no recommended sequencing for VMGTVCCAUX. Both VMGTAVCC and VCCINT can be ramped simultaneously. The recommended power-off sequence is the reverse of the power-on sequence to achieve minimum current draw. If these recommended sequences are not met, current drawn from VMGTAVTT can be higher than specifications during power-up and power-down. 

## **Power Supply Requirements** 

Table 6 shows the minimum current, in addition to ICCQ maximum, required by each Virtex UltraScale+ FPGA for proper power-on and configuration. If these current minimums are met, the device powers on after all supplies have passed through their power-on reset threshold voltages. The device must not be configured until after VCCINT is applied. Once initialized and configured, use the Xilinx Power Estimator (XPE) tools to estimate current drain on these supplies. The XPE spreadsheet tool (download at http://www.xilinx.com/power) is also used to estimate power-on current for all supplies. 

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Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## _Table 6:_ **Power-on Current by Device** 

|_Table 6:_**Power-on Current by Device**|_Table 6:_**Power-on Current by Device**|_Table 6:_**Power-on Current by Device**|_Table 6:_**Power-on Current by Device**|_Table 6:_**Power-on Current by Device**|_Table 6:_**Power-on Current by Device**|
|---|---|---|---|---|---|
|**Device**|**ICCINTMIN**|**ICCINT_IOMIN + ICCBRAMMIN**|**ICCOMIN**|**ICCAUXMIN + ICCAUX_IOMIN**|**Units**|
|XCVU3P,<br>XQVU3P|ICCINTQ+ 2000|ICCBRAMQ+ ICCINT_IOQ+ 670|ICCOQ+ 50|ICCAUXQ+ ICCAUX_IOQ+ 350|mA|
|XCVU5P|ICCINTQ+ 4000|ICCBRAMQ+ ICCINT_IOQ+ 1340|ICCOQ+ 100|ICCAUXQ+ ICCAUX_IOQ+ 700|mA|
|XCVU7P,<br>XQVU7P|ICCINTQ+ 4000|ICCBRAMQ+ ICCINT_IOQ+ 1340|ICCOQ+ 100|ICCAUXQ+ ICCAUX_IOQ+ 700|mA|
|XCVU9P|ICCINTQ+ 6000|ICCBRAMQ+ ICCINT_IOQ+ 2010|ICCOQ+ 150|ICCAUXQ+ ICCAUX_IOQ+ 1050|mA|
|XCVU11P,<br>XQVU11P|ICCINTQ+ 6549|ICCBRAMQ+ ICCINT_IOQ+ 2194|ICCOQ+ 164|ICCAUXQ+ ICCAUX_IOQ+ 1146|mA|
|XCVU13P|ICCINTQ+ 8731|ICCBRAMQ+ ICCINT_IOQ+ 2925|ICCOQ+ 219|ICCAUXQ+ ICCAUX_IOQ+ 1528|mA|
|XCVU27P|||||mA|
|XCVU29P|||||mA|
|XCVU31P|ICCINTQ+ 2232|ICCBRAMQ+ ICCINT_IOQ+ 2500|ICCOQ+ 56|ICCAUXQ+ ICCAUX_IOQ+ 500|mA|
|XCVU33P|ICCINTQ+ 2232|ICCBRAMQ+ ICCINT_IOQ+ 2500|ICCOQ+ 56|ICCAUXQ+ ICCAUX_IOQ+ 500|mA|
|XCVU35P|ICCINTQ+ 4424|ICCBRAMQ+ ICCINT_IOQ+ 3537|ICCOQ+ 111|ICCAUXQ+ ICCAUX_IOQ+ 882|mA|
|XCVU37P|ICCINTQ+ 6617|ICCBRAMQ+ ICCINT_IOQ+ 4574|ICCOQ+ 166|ICCAUXQ+ ICCAUX_IOQ+ 1264|mA|



## _Table 7:_ **Power Supply Ramp Time** 

|_Table 7:_**Power Supply Ramp Time**|_Table 7:_**Power Supply Ramp Time**|_Table 7:_**Power Supply Ramp Time**|_Table 7:_**Power Supply Ramp Time**|_Table 7:_**Power Supply Ramp Time**|
|---|---|---|---|---|
|**Symbol**|**Description**|**Min**|**Max**|**Units**|
|TVCCINT|Ramp time from GND to 95% of VCCINT|0.2|40|ms|
|TVCCINT_IO|Ramp time from GND to 95% of VCCINT_IO|0.2|40|ms|
|TVCCO|Ramp time from GND to 95% of VCCO|0.2|40|ms|
|TVCCAUX|Ramp time from GND to 95% of VCCAUX|0.2|40|ms|
|TVCCBRAM|Ramp time from GND to 95% of VCCBRAM|0.2|40|ms|
|TVCC_HBM|Ramp time from GND to 95% of VCC_HBM|0.2|40|ms|
|TVCC_IO_HBM|Ramp time from GND to 95% of VCC_IO_HBM|0.2|40|ms|
|TVCCAUX_HBM|Ramp time from GND to 95% of VCCAUX_HBM|0.2|40|ms|
|TMGTAVCC|Ramp time from GND to 95% of VMGTAVCC|0.2|40|ms|
|TMGTAVTT|Ramp time from GND to 95% of VMGTAVTT|0.2|40|ms|
|TMGTVCCAUX|Ramp time from GND to 95% of VMGTVCCAUX|0.2|40|ms|



## **DC Input and Output Levels** 

Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the recommended operating conditions at the VOL and VOH test points. Only selected standards are tested. These are chosen to ensure that all standards meet their specifications. The selected standards are tested at a minimum VCCO with the respective VOL and VOH voltage levels shown. Other standards are sample tested. 

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Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## **I/O Levels** 

## _Table 8:_ **SelectIO DC Input and Output Levels for I/O Banks** 

|**I/O Levels**|**I/O Levels**|**I/O Levels**|**I/O Levels**|**I/O Levels**|**I/O Levels**|**I/O Levels**|**I/O Levels**|**I/O Levels**|
|---|---|---|---|---|---|---|---|---|
|_Table 8:_**SelectIO DC Input and Output Levels for I/O Banks**|||||||||
|**I/O Standard**1**,**2**,**3|**VIL**||**VIH**||**VOL**|**VOH**|**IOL**|**IOH**|
||**V, Min**|**V, Max**|**V, Min**|**V, Max**|**V, Max**|**V, Min**|**mA**|**mA**|
|HSTL_I|–0.300|VREF– 0.100|VREF+ 0.100|VCCO+ 0.300|0.400|VCCO– 0.400|5.8|–5.8|
|HSTL_I_12|–0.300|VREF– 0.080|VREF+ 0.080|VCCO+ 0.300|25% VCCO|75% VCCO|4.1|–4.1|
|HSTL_I_18|–0.300|VREF– 0.100|VREF+ 0.100|VCCO+ 0.300|0.400|VCCO– 0.400|6.2|–6.2|
|HSUL_12|–0.300|VREF– 0.130|VREF+ 0.130|VCCO+ 0.300|20% VCCO|80% VCCO|0.1|–0.1|
|LVCMOS12|–0.300|35% VCCO|65% VCCO|VCCO+ 0.300|0.400|VCCO– 0.400|Note4|Note4|
|LVCMOS15|–0.300|35% VCCO|65% VCCO|VCCO+ 0.300|0.450|VCCO– 0.450|Note5|Note5|
|LVCMOS18|–0.300|35% VCCO|65% VCCO|VCCO+ 0.300|0.450|VCCO– 0.450|Note5|Note5|
|LVDCI_15|–0.300|35% VCCO|65% VCCO|VCCO+ 0.300|0.450|VCCO– 0.450|7.0|–7.0|
|LVDCI_18|–0.300|35% VCCO|65% VCCO|VCCO+ 0.300|0.450|VCCO– 0.450|7.0|–7.0|
|SSTL12|–0.300|VREF– 0.100|VREF+ 0.100|VCCO+ 0.300|VCCO/2 – 0.150|VCCO/2 + 0.150|8.0|–8.0|
|SSTL135|–0.300|VREF– 0.090|VREF+ 0.090|VCCO+ 0.300|VCCO/2 – 0.150|VCCO/2 + 0.150|9.0|–9.0|
|SSTL15|–0.300|VREF– 0.100|VREF+ 0.100|VCCO+ 0.300|VCCO/2 – 0.175|VCCO/2 + 0.175|10.0|–10.0|
|SSTL18_I|–0.300|VREF– 0.125|VREF+ 0.125|VCCO+ 0.300|VCCO/2 – 0.470|VCCO/2 + 0.470|7.0|–7.0|
|MIPI_DPHY_ DCI_LP6|–0.300|0.550|0.880|VCCO+ 0.300|0.050|1.100|0.01|–0.01|
|**Notes:**<br>1.<br>Tested according to relevant specifications.<br>2.<br>Standards specified using the default I/O standard configuration. For details, see the_UltraScale Architecture SelectIO Resources User Guide_<br>(UG571).<br>3.<br>POD10 and POD12 DC input and output levels are shown inTable 9,Table 13, andTable 14.<br>4.<br>Supported drive strengths of 2, 4, 6, or 8 mA in I/O banks.<br>5.<br>Supported drive strengths of 2, 4, 6, 8, or 12 mA in I/O banks.<br>6.<br>Low-power option for MIPI_DPHY_DCI.|||||||||



## _Table 9:_ **DC Input Levels for Single-ended POD10 and POD12 I/O Standards** 

|_Table 9:_**DC Input Levels for Single-ended POD10 and POD12 I/O Standards**|_Table 9:_**DC Input Levels for Single-ended POD10 and POD12 I/O Standards**|_Table 9:_**DC Input Levels for Single-ended POD10 and POD12 I/O Standards**|_Table 9:_**DC Input Levels for Single-ended POD10 and POD12 I/O Standards**|_Table 9:_**DC Input Levels for Single-ended POD10 and POD12 I/O Standards**|
|---|---|---|---|---|
|**I/O Standard**1**,**2|**VIL**||**VIH**||
||**V, Min**|**V, Max**|**V, Min**|**V, Max**|
|POD10|–0.300|VREF– 0.068|VREF+ 0.068|VCCO+ 0.300|
|POD12|–0.300|VREF– 0.068|VREF+ 0.068|VCCO+ 0.300|
|**Notes:**<br>1.<br>Tested according to relevant specifications.<br>2.<br>Standards specified using the default I/O standard configuration. For details, see the_UltraScale Architecture SelectIO Resources User Guide_<br>(UG571).|||||



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Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

_Table 10:_ **Differential SelectIO DC Input and Output Levels** 

|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|_Table 10:_**Differential SelectIO DC Input and Output Levels**|||||||||||||||
|**I/O Standard**|**VICM(V)**1|||**VID (V)**2|||**VILHS**3|**VIHHS**3|**VOCM (V)**4|||**VOD (V)**5|||
||**Min**|**Typ**|**Max**|**Min**|**Typ**|**Max**|**Min**|**Max**|**Min**|**Typ**|**Max**|**Min**|**Typ**|**Max**|
|SUB_LVDS|0.500|0.900|1.300|0.070|–|–|–|–|0.700|0.900|1.100|0.100|0.150|0.200|
|SLVS_400_18|0.070|0.200|0.330|0.140|–|0.450|–|–|–|–|–|–|–|–|
|MIPI_DPHY_<br>DCI_HS7|0.070|–|0.330|0.070|–|–|–0.040|0.460|0.150|0.200|0.250|0.140|0.200|0.270|
|**Notes:**<br>1.<br>VICMis the input common mode voltage.<br>2.<br>VIDis the input differential voltage (Q –<br>Q).<br>3.<br>VIHHSand VILHSare the single-ended input high and low voltages, respectively.<br>4.<br>VOCMis the output common mode voltage.<br>5.<br>VODis the output differential voltage (Q –<br>Q).<br>6.<br>LVDS is specified inTable 15.<br>7.<br>High-speed option for MIPI_DPHY_DCI. The VIDmaximum is aligned with the standard’s specification. A higher VIDis acceptable as long<br>as the VINspecification is also met.|||||||||||||||



_Table 11:_ **Complementary Differential SelectIO DC Input and Output Levels for I/O Banks** 

|_Table 11:_**Complementary Differential SelectIO DC Input and Output Levels for I/O Banks**|_Table 11:_**Complementary Differential SelectIO DC Input and Output Levels for I/O Banks**|_Table 11:_**Complementary Differential SelectIO DC Input and Output Levels for I/O Banks**|_Table 11:_**Complementary Differential SelectIO DC Input and Output Levels for I/O Banks**|_Table 11:_**Complementary Differential SelectIO DC Input and Output Levels for I/O Banks**|_Table 11:_**Complementary Differential SelectIO DC Input and Output Levels for I/O Banks**|_Table 11:_**Complementary Differential SelectIO DC Input and Output Levels for I/O Banks**|_Table 11:_**Complementary Differential SelectIO DC Input and Output Levels for I/O Banks**|_Table 11:_**Complementary Differential SelectIO DC Input and Output Levels for I/O Banks**|_Table 11:_**Complementary Differential SelectIO DC Input and Output Levels for I/O Banks**|
|---|---|---|---|---|---|---|---|---|---|
|**I/O Standard**1|**VICM (V)**2|||**VID (V)**3||**VOL(V)**4|**VOH(V)**5|**IOL**|**IOH**|
||**Min**|**Typ**|**Max**|**Min**|**Max**|**Max**|**Min**|**mA**|**mA**|
|DIFF_HSTL_I|0.680|VCCO/2|(VCCO/2) + 0.150|0.100|–|0.400|VCCO– 0.400|5.8|–5.8|
|DIFF_HSTL_I_12|0.400 x VCCO|VCCO/2|0.600 x VCCO|0.100|–|0.250 x VCCO|0.750 x VCCO|4.1|–4.1|
|DIFF_HSTL_I_18|(VCCO/2) – 0.175|VCCO/2|(VCCO/2) + 0.175|0.100|–|0.400|VCCO– 0.400|6.2|–6.2|
|DIFF_HSUL_12|(VCCO/2) – 0.120|VCCO/2|(VCCO/2) + 0.120|0.100|–|20% VCCO|80% VCCO|0.1|–0.1|
|DIFF_SSTL12|(VCCO/2) – 0.150|VCCO/2|(VCCO/2) + 0.150|0.100|–|(VCCO/2) – 0.150|(VCCO/2) + 0.150|8.0|–8.0|
|DIFF_SSTL135|(VCCO/2) – 0.150|VCCO/2|(VCCO/2) + 0.150|0.100|–|(VCCO/2) – 0.150|(VCCO/2) + 0.150|9.0|–9.0|
|DIFF_SSTL15|(VCCO/2) – 0.175|VCCO/2|(VCCO/2) + 0.175|0.100|–|(VCCO/2) – 0.175|(VCCO/2) + 0.175|10.0|–10.0|
|DIFF_SSTL18_I|(VCCO/2) – 0.175|VCCO/2|(VCCO/2) + 0.175|0.100|–|(VCCO/2) – 0.470|(VCCO/2) + 0.470|7.0|–7.0|
|**Notes:**<br>1.<br>DIFF_POD10 and DIFF_POD12 HP I/O bank specifications are shown inTable 12,Table 13,Table 14.<br>2.<br>VICMis the input common mode voltage.<br>3.<br>VIDis the input differential voltage.<br>4.<br>VOLis the single-ended low-output voltage.<br>5.<br>VOHis the single-ended high-output voltage.||||||||||



## _Table 12:_ **DC Input Levels for Differential POD10 and POD12 I/O Standards** 

|_Table 12:_**DC Input Levels for Differential POD10 and POD12 I/O Standards**|_Table 12:_**DC Input Levels for Differential POD10 and POD12 I/O Standards**|_Table 12:_**DC Input Levels for Differential POD10 and POD12 I/O Standards**|_Table 12:_**DC Input Levels for Differential POD10 and POD12 I/O Standards**|_Table 12:_**DC Input Levels for Differential POD10 and POD12 I/O Standards**|_Table 12:_**DC Input Levels for Differential POD10 and POD12 I/O Standards**|
|---|---|---|---|---|---|
|**I/O Standard**1**,**2|**VICM(V)**|||**VID (V)**||
||**Min**|**Typ**|**Max**|**Min**|**Max**|
|DIFF_POD10|0.63|0.70|0.77|0.14|–|
|DIFF_POD12|0.76|0.84|0.92|0.16|–|
|**Notes:**<br>1.<br>Tested according to relevant specifications.<br>2.<br>Standards specified using the default I/O standard configuration. For details, see the_UltraScale Architecture SelectIO Resources User Guide_<br>(UG571).||||||



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Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## _Table 13:_ **DC Output Levels for Single-ended and Differential POD10 and POD12 Standards** 

|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|---|
|_Table 13:_**DC Output Levels for Single-ended and Differential POD10 and POD12 Standards**|||||||
|**Symbol**|**Description**1**,**2|**VOUT**|**Min**|**Typ**|**Max**|**Units**|
|ROL|Pull-down resistance|VOM_DC(as described inTable 14)|36|40|44|Ω|
|ROH|Pull-up resistance|VOM_DC(as described inTable 14)|36|40|44|Ω|
|**Notes:**<br>1.<br>Tested according to relevant specifications.<br>2.<br>Standards specified using the default I/O standard configuration. For details, see the_UltraScale Architecture SelectIO Resources User Guide_<br>(UG571).|||||||



## _Table 14:_ **Definitions for DC Output Levels for Single-ended and Differential POD10 and POD12 Standards** 

|<br>**Standards**|||||
|---|---|---|---|---|
|**Symbol**|**Description**|**All Speed Grades**|**Units**||
|VOM_DC|DC output Mid measurement level (for IV curve linearity)|0.8 x VCCO|V||



## **LVDS DC Specifications (LVDS)** 

_Table 15:_ **LVDS DC Specifications** 

|**LVDS DC Specifications (LVDS)**|**LVDS DC Specifications (LVDS)**|**LVDS DC Specifications (LVDS)**|**LVDS DC Specifications (LVDS)**|**LVDS DC Specifications (LVDS)**|**LVDS DC Specifications (LVDS)**|**LVDS DC Specifications (LVDS)**|
|---|---|---|---|---|---|---|
|_Table 15:_**LVDS DC Specifications**|||||||
|**Symbol**|**DC Parameter**|**Conditions**|**Min**|**Typ**|**Max**|**Units**|
|VCCO1|Supply voltage||1.710|1.800|1.890|V|
|VODIFF2|Differential output voltage:<br>(Q –<br>Q), Q = High<br>(<br>Q – Q),<br>Q = High|RT= 100Ω across Q and<br>Q signals|247|350|454|mV|
|VOCM2|Output common-mode voltage|RT= 100Ω across Q and<br>Q signals|1.000|1.250|1.425|V|
|VIDIFF3|Differential input voltage:<br>(Q –<br>Q), Q = High<br>(<br>Q – Q),<br>Q = High||100|350|6003|mV|
|VICM_DC4|Input common-mode voltage (DC coupling)||0.300|1.200|1.425|V|
|VICM_AC5|Input common-mode voltage (AC coupling)||0.600|–|1.100|V|
|**Notes:**<br>1.<br>In I/O banks, when LVDS is used with input-only functionality, it can be placed in a bank where the VCCOlevels are different from the<br>specified level only if internal differential termination is not used. In this scenario, VCCOmust be chosen to ensure the input pin voltage<br>levels do not violate the Recommended Operating Condition (Table 2) specification for the VINI/O pin voltage.<br>2.<br>VOCMand VODIFFvalues are for LVDS_PRE_EMPHASIS = FALSE.<br>3.<br>Maximum VIDIFFvalue is specified for the maximum VICMspecification. With a lower VICM, a higher VDIFFis tolerated only when the<br>recommended operating conditions and overshoot/undershoot VINspecifications are maintained.<br>4.<br>Input common mode voltage for DC coupled configurations. EQUALIZATION = EQ_NONE (Default).<br>5.<br>External input common mode voltage specification for AC coupled configurations. EQUALIZATION = EQ_LEVEL0, EQ_LEVEL1, EQ_LEVEL2,<br>EQ_LEVEL3, EQ_LEVEL4.|||||||



## **AC Switching Characteristics** 

All values represented in this data sheet are based on the speed specifications in the Vivado[®] Design Suite as outlined in the following table. 

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Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## _Table 16:_ **Speed Specification Version By Device** 

|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|
|_Table 16:_**Speed Specification Version By Device**||
|**2018.3.1**|**Device**|
|1.23|XCVU3P, XCVU7P, XCVU9P, XCVU5P, XCVU11P, XCVU13P<br>XQVU3P, XQVU7P, XQVU11P|
|1.01|XCVU27P, XCVU29P|
|1.24|XCVU31P, XCVU33P, XCVU35P, XCVU37P|



Switching characteristics are specified on a per-speed-grade basis and can be designated as Advance, Preliminary, or Production. Each designation is defined as follows: 

- **Advance Product Specification:** These specifications are based on simulations only and are typically available soon after device design specifications are frozen. Although speed grades with this designation are considered relatively stable and conservative, some under-reporting might still occur. 

- **Preliminary Product Specification:** These specifications are based on complete ES (engineering sample) silicon characterization. Devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon. The probability of under-reporting delays is greatly reduced as compared to Advance data. 

- **Product Specification:** These specifications are released once enough production silicon of a particular device family member has been characterized to provide full correlation between specifications and devices over numerous production lots. There is no under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest speed grades transition to production before faster speed grades. 

## **Testing of AC Switching Characteristics** 

Internal timing parameters are derived from measuring internal test patterns. All AC switching characteristics are representative of worst-case supply voltage and junction temperature conditions. 

For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer and back-annotate to the simulation net list. Unless otherwise noted, values apply to all Virtex UltraScale+ FPGAs. 

## **Speed Grade Designations** 

Because individual family members are produced at different times, the migration from one category to another depends completely on the status of the fabrication process for each device. Table 17 correlates the current status of the Virtex UltraScale+ FPGA on a per speed grade basis. 

_Table 17:_ **Speed Grade Designations by Device** 

|Because individual family members are produced at diferent tmes, the migraton from one category to another<br>depends completely on the status of the fabricaton process for each device.Table 17correlates the current<br>status of the Virtex UltraScale+ FPGA on a per speed grade basis.|Because individual family members are produced at diferent tmes, the migraton from one category to another<br>depends completely on the status of the fabricaton process for each device.Table 17correlates the current<br>status of the Virtex UltraScale+ FPGA on a per speed grade basis.|Because individual family members are produced at diferent tmes, the migraton from one category to another<br>depends completely on the status of the fabricaton process for each device.Table 17correlates the current<br>status of the Virtex UltraScale+ FPGA on a per speed grade basis.|Because individual family members are produced at diferent tmes, the migraton from one category to another<br>depends completely on the status of the fabricaton process for each device.Table 17correlates the current<br>status of the Virtex UltraScale+ FPGA on a per speed grade basis.|
|---|---|---|---|
|_Table 17:_**Speed Grade Designations by Device**||||
|**Device**|**Speed Grade, Temperature Ranges, and VCCINT Operating Voltages**|||
||**Advance**|**Preliminary**|**Production**|
|XCVU3P|||-3E (VCCINT= 0.90V)<br>-2E (VCCINT= 0.85V), -2I (VCCINT= 0.85V)<br>-1E (VCCINT= 0.85V), -1I (VCCINT= 0.85V)<br>-2LE (VCCINT= 0.85V), -2LE (VCCINT= 0.72V)1|



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Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## _Table 17:_ **Speed Grade Designations by Device** _(cont'd)_ 

|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|
|_Table 17:_**Speed Grade Designations by Device**_(cont'd)_||||
|**Device**|**Speed Grade, Temperature Ranges, and VCCINT Operating Voltages**|||
||**Advance**|**Preliminary**|**Production**|
|XCVU5P|||-3E (VCCINT= 0.90V)<br>-2E (VCCINT= 0.85V), -2I (VCCINT= 0.85V)<br>-1E (VCCINT= 0.85V), -1I (VCCINT= 0.85V)<br>-2LE (VCCINT= 0.85V), -2LE (VCCINT= 0.72V)1|
|XCVU7P|||-3E (VCCINT= 0.90V)<br>-2E (VCCINT= 0.85V), -2I (VCCINT= 0.85V)<br>-1E (VCCINT= 0.85V), -1I (VCCINT= 0.85V)<br>-2LE (VCCINT= 0.85V), -2LE (VCCINT= 0.72V)1|
|XCVU9P|||-3E (VCCINT= 0.90V)<br>-2E (VCCINT= 0.85V), -2I (VCCINT= 0.85V)<br>-1E (VCCINT= 0.85V), -1I (VCCINT= 0.85V)<br>-2LE (VCCINT= 0.85V), -2LE (VCCINT= 0.72V)1|
|XCVU11P|||-3E (VCCINT= 0.90V)<br>-2E (VCCINT= 0.85V), -2I (VCCINT= 0.85V)<br>-1E (VCCINT= 0.85V), -1I (VCCINT= 0.85V)<br>-2LE (VCCINT= 0.85V), -2LE (VCCINT= 0.72V)1|
|XCVU13P|||-3E (VCCINT= 0.90V)<br>-2E (VCCINT= 0.85V), -2I (VCCINT= 0.85V)<br>-1E (VCCINT= 0.85V), -1I (VCCINT= 0.85V)<br>-2LE (VCCINT= 0.85V), -2LE (VCCINT= 0.72V)1|
|XCVU27P|-3E (VCCINT= 0.90V)<br>-2E (VCCINT= 0.85V)<br>-2I (VCCINT= 0.85V)<br>-1E (VCCINT= 0.85V)<br>-1I (VCCINT= 0.85V)<br>-2LE (VCCINT= 0.85V)<br>-2LE (VCCINT= 0.72V)1|||
|XCVU29P|-3E (VCCINT= 0.90V)<br>-2E (VCCINT= 0.85V)<br>-2I (VCCINT= 0.85V)<br>-1E (VCCINT= 0.85V)<br>-1I (VCCINT= 0.85V)<br>-2LE (VCCINT= 0.85V)<br>-2LE (VCCINT= 0.72V)1|||
|XCVU31P|-3E (VCCINT= 0.90V)||-2E (VCCINT= 0.85V)<br>-2LE (VCCINT= 0.85V)<br>-1E (VCCINT= 0.85V)<br>-2LE (VCCINT= 0.72V)1|
|XCVU33P|-3E (VCCINT= 0.90V)||-2E (VCCINT= 0.85V)<br>-2LE (VCCINT= 0.85V)<br>-1E (VCCINT= 0.85V)<br>-2LE (VCCINT= 0.72V)1|
|XCVU35P|-3E (VCCINT= 0.90V)||-2E (VCCINT= 0.85V)<br>-2LE (VCCINT= 0.85V)<br>-1E (VCCINT= 0.85V)<br>-2LE (VCCINT= 0.72V)1|



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Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## _Table 17:_ **Speed Grade Designations by Device** _(cont'd)_ 

|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|
|_Table 17:_**Speed Grade Designations by Device**_(cont'd)_||||
|**Device**|**Speed Grade, Temperature Ranges, and VCCINT Operating Voltages**|||
||**Advance**|**Preliminary**|**Production**|
|XCVU37P|-3E (VCCINT= 0.90V)||-2E (VCCINT= 0.85V)<br>-2LE (VCCINT= 0.85V)<br>-1E (VCCINT= 0.85V)<br>-2LE (VCCINT= 0.72V)1|
|XQVU3P|||-2I (VCCINT= 0.85V)<br>-1I (VCCINT= 0.85V), -1M (VCCINT= 0.85V)<br>-2LE (VCCINT= 0.85V), -2LE (VCCINT= 0.72V)1|
|XQVU7P|||-2I (VCCINT= 0.85V)<br>-1I (VCCINT= 0.85V)<br>-2LE (VCCINT= 0.85V), -2LE (VCCINT= 0.72V)1|
|XQVU11P|||-2I (VCCINT= 0.85V)<br>-1I (VCCINT= 0.85V)<br>-2LE (VCCINT= 0.85V), -2LE (VCCINT= 0.72V)1|
|**Notes:**<br>1.<br>The lowest power -2L devices, where VCCINT= 0.72V, are listed in the Vivado Design Suite as -2LV.||||



## **Production Silicon and Software Status** 

In some cases, a particular family member (and speed grade) is released to production before a speed specification is released with the correct label (Advance, Preliminary, Production). Any labeling discrepancies are corrected in subsequent speed specification releases. 

Table 18 lists the production released Virtex UltraScale+ FPGA, speed grade, and the minimum corresponding supported speed specification version and Vivado software revisions. The Vivado software and speed specifications listed are the minimum releases required for production. All subsequent releases of software and speed specifications are valid. 

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Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## _Table 18:_ **Virtex UltraScale+ FPGA Device Production Software and Speed Specification Release** 

|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|
|_Table 18:_**Virtex UltraScale+ FPGA Device Production Software and Speed Specification Release**||||||
|**Device**|**Speed Grade and VCCINT Operating Voltages**1|||||
||**0.90V**|**0.85V**|||**0.72V**|
||**-3**|**-2**|**-1**|**-2L**|**-2L**|
|XCVU3P|Vivado tools 2018.1<br>v1.19|Vivado tools 2017.1 v1.10||Vivado tools 2017.3.1 v1.16||
|XCVU5P|Vivado tools 2018.1<br>v1.19|Vivado tools 2017.2 v1.12||Vivado tools 2017.3.1 v1.16||
|XCVU7P|Vivado tools 2018.1<br>v1.19|Vivado tools 2017.2 v1.12||Vivado tools 2017.3.1 v1.16||
|XCVU9P|Vivado tools 2018.1<br>v1.19|Vivado tools 2017.2 v1.12||Vivado tools 2017.3.1 v1.16||
|XCVU11P|Vivado tools 2017.4.1<br>v1.18|Vivado tools 2017.2.1 v1.13||Vivado tools 2017.3.1 v1.16||
|XCVU13P|Vivado tools 2017.4.1<br>v1.18|Vivado tools 2017.2.1 v1.13||Vivado tools 2017.3.1 v1.16||
|XCVU27P||||||
|XCVU29P||||||
|XCVU31P||Vivado tools 2018.3.1 v1.24||Vivado tools 2018.3.1 v1.24||
|XCVU33P||Vivado tools 2018.3.1 v1.24||Vivado tools 2018.3.1 v1.24||
|XCVU35P||Vivado tools 2018.3.1 v1.24||Vivado tools 2018.3.1 v1.24||
|XCVU37P||Vivado tools 2018.3.1 v1.24||Vivado tools 2018.3.1 v1.24||
|XQVU3P|N/A|Vivado tools 2018.3 v1.23||Vivado tools 2018.3 v1.23||
|XQVU7P|N/A|Vivado tools 2018.3.1 v1.23||Vivado tools 2018.3.1 v1.23||
|XQVU11P|N/A|Vivado tools 2018.3.1 v1.23||Vivado tools 2018.3.1 v1.23||
|**Notes:**<br>1.<br>Blank entries indicate a device and/or speed grade in Advance or Preliminary status.||||||



## **FPGA Logic Performance Characteristics** 

This section provides the performance characteristics of some common functions and designs implemented in the Virtex UltraScale+ FPGAs. These values are subject to the same guidelines as the AC Switching Characteristics section. 

In LVDS component mode: 

- For the input/output registers in HP I/O banks, the Vivado tools limit clock frequencies to 312.9 MHz for all speed grades. 

- For IDDR in HP I/O banks, Vivado tools limit clock frequencies to 625.0 MHz for all speed grades. 

- For ODDR in HP I/O banks, Vivado tools limit clock frequencies to 625.0 MHz for all speed grades. 

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Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## _Table 19:_ **LVDS Component Mode Performance** 

|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|---|---|---|---|
|_Table 19:_**LVDS Component Mode Performance**||||||||||
|**Description**|**Speed Grade and VCCINT Operating Voltages**||||||||**Units**|
||**0.90V**||**0.85V**||||**0.72V**|||
||**-3**||**-2**||**-1**||**-2**|||
||**Min**|**Max**|**Min**|**Max**|**Min**|**Max**|**Min**|**Max**||
|LVDS TX DDR (OSERDES 4:1, 8:1)|0|1250|0|1250|0|1250|0|1250|Mb/s|
|LVDS TX SDR (OSERDES 2:1, 4:1)|0|625|0|625|0|625|0|625|Mb/s|
|LVDS RX DDR (ISERDES 1:4, 1:8)1|0|1250|0|1250|0|1250|0|1250|Mb/s|
|LVDS RX SDR (ISERDES 1:2, 1:4)1|0|625|0|625|0|625|0|625|Mb/s|
|**Notes:**<br>1.<br>LVDS receivers are typically bounded with certain applications to achieve maximum performance. Package skews are not included and<br>should be removed through PCB routing.||||||||||



## _Table 20:_ **LVDS Native Mode Performance** 

|_Table 20:_**LVDS Native Mode Performance**|_Table 20:_**LVDS Native Mode Performance**|_Table 20:_**LVDS Native Mode Performance**|_Table 20:_**LVDS Native Mode Performance**|_Table 20:_**LVDS Native Mode Performance**|_Table 20:_**LVDS Native Mode Performance**|_Table 20:_**LVDS Native Mode Performance**|_Table 20:_**LVDS Native Mode Performance**|_Table 20:_**LVDS Native Mode Performance**|_Table 20:_**LVDS Native Mode Performance**|_Table 20:_**LVDS Native Mode Performance**|
|---|---|---|---|---|---|---|---|---|---|---|
|**Description**1**,**2|**DATA_WIDTH**|**Speed Grade and VCCINT Operating Voltages**||||||||**Units**|
|||**0.90V**||**0.85V**||||**0.72V**|||
|||**-3**||**-2**||**-1**||**-2**|||
|||**Min**|**Max**|**Min**|**Max**|**Min**|**Max**|**Min**|**Max**||
|LVDS TX DDR (TX_BITSLICE)|4|375|1600|375|1600|375|1600|375|1400|Mb/s|
||8|375|1600|375|1600|375|1600|375|1600|Mb/s|
|LVDS TX SDR (TX_BITSLICE)|4|187.5|800|187.5|800|187.5|800|187.5|700|Mb/s|
||8|187.5|800|187.5|800|187.5|800|187.5|800|Mb/s|
|LVDS RX DDR (RX_BITSLICE)3|4|375|16004|375|16004|375|16004|375|14004|Mb/s|
||8|375|16004|375|16004|375|16004|375|16004|Mb/s|
|LVDS RX SDR (RX_BITSLICE)3|4|187.5|800|187.5|800|187.5|800|187.5|700|Mb/s|
||8|187.5|800|187.5|800|187.5|800|187.5|800|Mb/s|
|**Notes:**<br>1.<br>Native mode is supported through theHigh-Speed SelectIO Interface Wizardavailable with the Vivado Design Suite. The performance<br>values assume a source-synchronous interface.<br>2.<br>PLL settings can restrict the minimum allowable data rate. For example, when using the PLL with CLKOUTPHY_MODE = VCO_HALF the<br>minimum frequency is PLL_FVCOMIN/2.<br>3.<br>LVDS receivers are typically bounded with certain applications to achieve maximum performance. Package skews are not included and<br>should be removed through PCB routing.<br>4.<br>Asynchronous receiver performance is limited to 1300 Mb/s for -3/-2 speed grades and to 1250 Mb/s for -1 speed grades.|||||||||||



## _Table 21:_ **MIPI D-PHY Performance** 

|_Table 21:_**MIPI D-PHY Performance**|_Table 21:_**MIPI D-PHY Performance**|_Table 21:_**MIPI D-PHY Performance**|_Table 21:_**MIPI D-PHY Performance**|_Table 21:_**MIPI D-PHY Performance**|_Table 21:_**MIPI D-PHY Performance**|
|---|---|---|---|---|---|
|**Description**|**Speed Grade and VCCINT Operating Voltages**||||**Units**|
||**0.90V**|**0.85V**||**0.72V**||
||**-3**|**-2**|**-1**|**-2**||
|MIPI D-PHY transmitter or receiver|1500|1500|1260|1260|Mb/s|



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Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## _Table 22:_ **LVDS Native-Mode 1000BASE-X Support** 

|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|
|_Table 22:_**LVDS Native-Mode 1000BASE-X Support**|||||
|**Description**1|**Speed Grade and VCCINT Operating Voltages**||||
||**0.90V**|**0.85V**||**0.72V**|
||**-3**|**-2**|**-1**|**-2**|
|1000BASE-X|Yes||||
|**Notes:**<br>1.<br>1000BASE-X support is based on the_IEEE Standard for CSMA/CD Access Method and Physical Layer Specifications_(IEEE Std 802.3-2008).|||||



The following table provides the maximum data rates for applicable memory standards using the Virtex UltraScale+ FPGA memory PHY. Refer to Memory Interfaces for the complete list of memory interface standards supported and detailed specifications. The final performance of the memory interface is determined through a complete design implemented in the Vivado Design Suite, following guidelines in the _UltraScale Architecture PCB Design User Guide_ (UG583), electrical analysis, and characterization of the system. 

_Table 23:_ **Maximum Physical Interface (PHY) Rate for Memory Interfaces** 

|_Table 23:_**Maximum Physical Interface (PHY) Rate for Memory Interfaces**|_Table 23:_**Maximum Physical Interface (PHY) Rate for Memory Interfaces**|_Table 23:_**Maximum Physical Interface (PHY) Rate for Memory Interfaces**|_Table 23:_**Maximum Physical Interface (PHY) Rate for Memory Interfaces**|_Table 23:_**Maximum Physical Interface (PHY) Rate for Memory Interfaces**|_Table 23:_**Maximum Physical Interface (PHY) Rate for Memory Interfaces**|_Table 23:_**Maximum Physical Interface (PHY) Rate for Memory Interfaces**|
|---|---|---|---|---|---|---|
|**Memory**<br>**Standard**|**DRAM Type**|**Speed Grade and VCCINT Operating Voltages**||||**Units**|
|||**0.90V**|**0.85V**||**0.72V**||
|||**-3**|**-2**|**-1**|**-2**||
|DDR4|Single rank component|2666|2666|2400|2400|Mb/s|
||1 rank DIMM1,2,3|2400|2400|2133|2133|Mb/s|
||2 rank DIMM1,4|2133|2133|1866|1866|Mb/s|
||4 rank DIMM1,5|1600|1600|1333|1333|Mb/s|
|DDR3|Single rank component|2133|2133|2133|2133|Mb/s|
||1 rank DIMM1,2|1866|1866|1866|1866|Mb/s|
||2 rank DIMM1,4|1600|1600|1600|1600|Mb/s|
||4 rank DIMM1,5|1066|1066|1066|1066|Mb/s|
|DDR3L|Single rank component|1866|1866|1866|1866|Mb/s|
||1 rank DIMM1,2|1600|1600|1600|1600|Mb/s|
||2 rank DIMM1,4|1333|1333|1333|1333|Mb/s|
||4 rank DIMM1,5|800|800|800|800|Mb/s|
|QDR II+|Single rank component6|633|633|600|600|MHz|
|RLDRAM 3|Single rank component|1200|1200|1066|1066|MHz|
|QDR IV XP|Single rank component|1066|1066|1066|933|MHz|
|LPDDR3|Single rank component|1600|1600|1600|1600|Mb/s|
|**Notes:**<br>1.<br>Dual in-line memory module (DIMM) includes RDIMM, SODIMM, UDIMM, and LRDIMM.<br>2.<br>Includes: 1 rank 1 slot, DDP 2 rank, LRDIMM 2 or 4 rank 1 slot.<br>3.<br>For the DDR4 DDP components at -3 and -2 (VCCINT= 0.85V) speed grades, the maximum data rate is 2133 Mb/s for six or more DDP<br>devices. For five or less DDP devices, use the single rank DIMM data rates for the -3 and -2 (VCCINT= 0.85V) speed grades.<br>4.<br>Includes: 2 rank 1 slot, 1 rank 2 slot, LRDIMM 2 rank 2 slot.<br>5.<br>Includes: 2 rank 2 slot, 4 rank 1 slot.<br>6.<br>The QDRII+ performance specifications are for burst-length 4 (BL = 4) implementations.|||||||



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Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## **FPGA Logic Switching Characteristics** 

The following IOB high-performance (HP) table summarizes the values of standard-specific data input delay adjustments, output delays terminating at pads (based on standard) and 3-state delays. 

- TINBUF_DELAY_PAD_I is the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The delay varies depending on the capability of the SelectIO input buffer. 

- TOUTBUF_DELAY_O_PAD is the delay from the O pin to the IOB pad through the output buffer of an IOB pad. The delay varies depending on the capability of the SelectIO output buffer. 

- TOUTBUF_DELAY_TD_PAD is the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is disabled. The delay varies depending on the SelectIO capability of the output buffer. In I/O banks, the internal DCI termination turn-on time is always faster than TOUTBUF_DELAY_TD_PAD when the DCITERMDISABLE pin is used. 

## **IOB High Performance (HP) Switching Characteristics** 

## _Table 24:_ **IOB High Performance (HP) Switching Characteristics** 

|**IOB High Performance (HP) Switching Characteristics**|**IOB High Performance (HP) Switching Characteristics**|**IOB High Performance (HP) Switching Characteristics**|**IOB High Performance (HP) Switching Characteristics**|**IOB High Performance (HP) Switching Characteristics**|**IOB High Performance (HP) Switching Characteristics**|**IOB High Performance (HP) Switching Characteristics**|**IOB High Performance (HP) Switching Characteristics**|**IOB High Performance (HP) Switching Characteristics**|**IOB High Performance (HP) Switching Characteristics**|**IOB High Performance (HP) Switching Characteristics**|**IOB High Performance (HP) Switching Characteristics**|**IOB High Performance (HP) Switching Characteristics**|**IOB High Performance (HP) Switching Characteristics**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|_Table 24:_**IOB High Performance (HP) Switching Characteristics**||||||||||||||
|**I/O Standards**|**TINBUF_DELAY_PAD_I**||||**TOUTBUF_DELAY_O_PAD**||||**TOUTBUF_DELAY_TD_PAD**||||**Units**|
||**0.90V**|**0.85V**||**0.72V**|**0.90V**|**0.85V**||**0.72V**|**0.90V**|**0.85V**||**0.72V**||
||**-3**|**-2**|**-1**|**-2**|**-3**|**-2**|**-1**|**-2**|**-3**|**-2**|**-1**|**-2**||
|DIFF_HSTL_I_12_F|0.288|0.394|0.402|0.394|0.410|0.423|0.443|0.423|0.514|0.553|0.582|0.553|ns|
|DIFF_HSTL_I_12_M|0.288|0.394|0.402|0.394|0.552|0.552|0.583|0.552|0.632|0.641|0.679|0.641|ns|
|DIFF_HSTL_I_12_S|0.288|0.394|0.402|0.394|0.752|0.752|0.800|0.752|0.813|0.813|0.868|0.813|ns|
|DIFF_HSTL_I_18_F|0.259|0.319|0.339|0.319|0.439|0.456|0.474|0.456|0.549|0.576|0.606|0.576|ns|
|DIFF_HSTL_I_18_M|0.259|0.319|0.339|0.319|0.563|0.570|0.603|0.570|0.636|0.653|0.692|0.653|ns|
|DIFF_HSTL_I_18_S|0.259|0.319|0.339|0.319|0.782|0.782|0.834|0.782|0.816|0.816|0.871|0.816|ns|
|DIFF_HSTL_I_DCI_12_F|0.288|0.394|0.402|0.394|0.393|0.406|0.429|0.406|0.502|0.534|0.564|0.534|ns|
|DIFF_HSTL_I_DCI_12_M|0.288|0.394|0.402|0.394|0.546|0.557|0.587|0.557|0.636|0.653|0.694|0.653|ns|
|DIFF_HSTL_I_DCI_12_S|0.288|0.394|0.402|0.394|0.755|0.755|0.806|0.755|0.842|0.842|0.907|0.842|ns|
|DIFF_HSTL_I_DCI_18_F|0.259|0.323|0.339|0.323|0.422|0.445|0.461|0.445|0.509|0.566|0.595|0.566|ns|
|DIFF_HSTL_I_DCI_18_M|0.259|0.323|0.339|0.323|0.546|0.555|0.586|0.555|0.626|0.643|0.684|0.643|ns|
|DIFF_HSTL_I_DCI_18_S|0.259|0.323|0.339|0.323|0.762|0.762|0.818|0.762|0.836|0.836|0.900|0.836|ns|
|DIFF_HSTL_I_DCI_F|0.335|0.397|0.417|0.397|0.407|0.431|0.445|0.431|0.517|0.555|0.575|0.555|ns|
|DIFF_HSTL_I_DCI_M|0.335|0.397|0.417|0.397|0.549|0.553|0.583|0.553|0.634|0.644|0.684|0.644|ns|
|DIFF_HSTL_I_DCI_S|0.335|0.397|0.417|0.397|0.767|0.767|0.823|0.767|0.848|0.848|0.912|0.848|ns|
|DIFF_HSTL_I_F|0.304|0.404|0.417|0.404|0.409|0.423|0.443|0.423|0.514|0.549|0.581|0.549|ns|
|DIFF_HSTL_I_M|0.304|0.404|0.417|0.404|0.549|0.555|0.586|0.555|0.624|0.640|0.677|0.640|ns|
|DIFF_HSTL_I_S|0.304|0.404|0.417|0.404|0.767|0.767|0.818|0.767|0.811|0.811|0.866|0.811|ns|
|DIFF_HSUL_12_DCI_F|0.320|0.381|0.400|0.381|0.411|0.425|0.443|0.425|0.520|0.558|0.586|0.558|ns|
|DIFF_HSUL_12_DCI_M|0.320|0.381|0.400|0.381|0.546|0.557|0.587|0.557|0.636|0.653|0.694|0.653|ns|
|DIFF_HSUL_12_DCI_S|0.320|0.381|0.400|0.381|0.737|0.737|0.787|0.737|0.822|0.822|0.885|0.822|ns|
|DIFF_HSUL_12_F|0.322|0.394|0.402|0.394|0.394|0.412|0.430|0.412|0.494|0.538|0.566|0.538|ns|
|DIFF_HSUL_12_M|0.322|0.394|0.402|0.394|0.552|0.552|0.583|0.552|0.632|0.641|0.679|0.641|ns|
|DIFF_HSUL_12_S|0.322|0.394|0.402|0.394|0.752|0.752|0.800|0.752|0.813|0.813|0.868|0.813|ns|



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21 

Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## _Table 24:_ **IOB High Performance (HP) Switching Characteristics** _(cont'd)_ 

|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|_Table 24:_**IOB High Performance (HP) Switching Characteristics**_(cont'd)_||||||||||||||
|**I/O Standards**|**TINBUF_DELAY_PAD_I**||||**TOUTBUF_DELAY_O_PAD**||||**TOUTBUF_DELAY_TD_PAD**||||**Units**|
||**0.90V**|**0.85V**||**0.72V**|**0.90V**|**0.85V**||**0.72V**|**0.90V**|**0.85V**||**0.72V**||
||**-3**|**-2**|**-1**|**-2**|**-3**|**-2**|**-1**|**-2**|**-3**|**-2**|**-1**|**-2**||
|DIFF_POD10_DCI_F|0.289|0.411|0.430|0.411|0.407|0.425|0.444|0.425|0.512|0.555|0.584|0.555|ns|
|DIFF_POD10_DCI_M|0.289|0.411|0.430|0.411|0.533|0.542|0.571|0.542|0.618|0.640|0.681|0.640|ns|
|DIFF_POD10_DCI_S|0.289|0.411|0.430|0.411|0.754|0.754|0.815|0.754|0.850|0.850|0.917|0.850|ns|
|DIFF_POD10_F|0.288|0.411|0.433|0.411|0.425|0.438|0.459|0.438|0.531|0.569|0.601|0.569|ns|
|DIFF_POD10_M|0.288|0.411|0.433|0.411|0.519|0.538|0.568|0.538|0.589|0.630|0.667|0.630|ns|
|DIFF_POD10_S|0.288|0.411|0.433|0.411|0.752|0.766|0.821|0.766|0.821|0.836|0.894|0.836|ns|
|DIFF_POD12_DCI_F|0.320|0.407|0.432|0.407|0.411|0.425|0.443|0.425|0.519|0.558|0.586|0.558|ns|
|DIFF_POD12_DCI_M|0.320|0.407|0.432|0.407|0.516|0.543|0.572|0.543|0.602|0.638|0.678|0.638|ns|
|DIFF_POD12_DCI_S|0.320|0.407|0.432|0.407|0.740|0.772|0.822|0.772|0.833|0.862|0.929|0.862|ns|
|DIFF_POD12_F|0.305|0.409|0.430|0.409|0.438|0.455|0.476|0.455|0.549|0.595|0.626|0.595|ns|
|DIFF_POD12_M|0.305|0.409|0.430|0.409|0.551|0.551|0.582|0.551|0.632|0.641|0.679|0.641|ns|
|DIFF_POD12_S|0.305|0.409|0.430|0.409|0.749|0.767|0.817|0.767|0.818|0.832|0.889|0.832|ns|
|DIFF_SSTL12_DCI_F|0.303|0.381|0.400|0.381|0.411|0.425|0.443|0.425|0.520|0.558|0.586|0.558|ns|
|DIFF_SSTL12_DCI_M|0.303|0.381|0.400|0.381|0.549|0.557|0.587|0.557|0.643|0.654|0.694|0.654|ns|
|DIFF_SSTL12_DCI_S|0.303|0.381|0.400|0.381|0.754|0.754|0.803|0.754|0.842|0.842|0.908|0.842|ns|
|DIFF_SSTL12_F|0.288|0.394|0.402|0.394|0.394|0.412|0.430|0.412|0.494|0.538|0.566|0.538|ns|
|DIFF_SSTL12_M|0.288|0.394|0.402|0.394|0.550|0.553|0.584|0.553|0.630|0.641|0.676|0.641|ns|
|DIFF_SSTL12_S|0.288|0.394|0.402|0.394|0.758|0.758|0.808|0.758|0.823|0.823|0.879|0.823|ns|
|DIFF_SSTL135_DCI_F|0.303|0.371|0.402|0.371|0.392|0.411|0.428|0.411|0.494|0.537|0.565|0.537|ns|
|DIFF_SSTL135_DCI_M|0.303|0.371|0.402|0.371|0.551|0.551|0.582|0.551|0.643|0.645|0.685|0.645|ns|
|DIFF_SSTL135_DCI_S|0.303|0.371|0.402|0.371|0.746|0.746|0.799|0.746|0.829|0.829|0.893|0.829|ns|
|DIFF_SSTL135_F|0.289|0.375|0.402|0.375|0.393|0.408|0.428|0.408|0.491|0.528|0.561|0.528|ns|
|DIFF_SSTL135_M|0.289|0.375|0.402|0.375|0.548|0.555|0.585|0.555|0.621|0.641|0.679|0.641|ns|
|DIFF_SSTL135_S|0.289|0.375|0.402|0.375|0.772|0.772|0.823|0.772|0.827|0.827|0.878|0.827|ns|
|DIFF_SSTL15_DCI_F|0.335|0.397|0.417|0.397|0.394|0.412|0.429|0.412|0.497|0.531|0.563|0.531|ns|
|DIFF_SSTL15_DCI_M|0.335|0.397|0.417|0.397|0.549|0.553|0.583|0.553|0.632|0.645|0.685|0.645|ns|
|DIFF_SSTL15_DCI_S|0.335|0.397|0.417|0.397|0.768|0.768|0.822|0.768|0.847|0.847|0.912|0.847|ns|
|DIFF_SSTL15_F|0.304|0.404|0.417|0.404|0.409|0.424|0.445|0.424|0.513|0.551|0.577|0.551|ns|
|DIFF_SSTL15_M|0.304|0.404|0.417|0.404|0.547|0.554|0.585|0.554|0.624|0.639|0.677|0.639|ns|
|DIFF_SSTL15_S|0.304|0.404|0.417|0.404|0.767|0.767|0.817|0.767|0.813|0.813|0.867|0.813|ns|
|DIFF_SSTL18_I_DCI_F|0.256|0.320|0.336|0.320|0.422|0.445|0.461|0.445|0.540|0.566|0.595|0.566|ns|
|DIFF_SSTL18_I_DCI_M|0.256|0.320|0.336|0.320|0.552|0.554|0.585|0.554|0.629|0.644|0.683|0.644|ns|
|DIFF_SSTL18_I_DCI_S|0.256|0.320|0.336|0.320|0.762|0.762|0.818|0.762|0.837|0.837|0.899|0.837|ns|
|DIFF_SSTL18_I_F|0.256|0.316|0.336|0.316|0.439|0.454|0.476|0.454|0.549|0.578|0.608|0.578|ns|
|DIFF_SSTL18_I_M|0.256|0.316|0.336|0.316|0.567|0.571|0.603|0.571|0.535|0.652|0.692|0.652|ns|
|DIFF_SSTL18_I_S|0.256|0.316|0.336|0.316|0.782|0.782|0.835|0.782|0.816|0.816|0.870|0.816|ns|
|HSLVDCI_15_F|0.336|0.393|0.415|0.393|0.407|0.425|0.443|0.425|0.513|0.548|0.579|0.548|ns|
|HSLVDCI_15_M|0.336|0.393|0.415|0.393|0.548|0.552|0.581|0.552|0.635|0.644|0.684|0.644|ns|
|HSLVDCI_15_S|0.336|0.393|0.415|0.393|0.748|0.748|0.802|0.748|0.827|0.827|0.890|0.827|ns|
|HSLVDCI_18_F|0.367|0.424|0.447|0.424|0.424|0.445|0.461|0.445|0.541|0.566|0.595|0.566|ns|



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Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## _Table 24:_ **IOB High Performance (HP) Switching Characteristics** _(cont'd)_ 

|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|_Table 24:_**IOB High Performance (HP) Switching Characteristics**_(cont'd)_||||||||||||||
|**I/O Standards**|**TINBUF_DELAY_PAD_I**||||**TOUTBUF_DELAY_O_PAD**||||**TOUTBUF_DELAY_TD_PAD**||||**Units**|
||**0.90V**|**0.85V**||**0.72V**|**0.90V**|**0.85V**||**0.72V**|**0.90V**|**0.85V**||**0.72V**||
||**-3**|**-2**|**-1**|**-2**|**-3**|**-2**|**-1**|**-2**|**-3**|**-2**|**-1**|**-2**||
|HSLVDCI_18_M|0.367|0.424|0.447|0.424|0.563|0.567|0.598|0.567|0.647|0.658|0.699|0.658|ns|
|HSLVDCI_18_S|0.367|0.424|0.447|0.424|0.761|0.761|0.817|0.761|0.836|0.836|0.900|0.836|ns|
|HSTL_I_12_F|0.322|0.378|0.399|0.378|0.410|0.423|0.443|0.423|0.514|0.553|0.582|0.553|ns|
|HSTL_I_12_M|0.322|0.378|0.399|0.378|0.551|0.551|0.582|0.551|0.632|0.642|0.679|0.642|ns|
|HSTL_I_12_S|0.322|0.378|0.399|0.378|0.750|0.750|0.799|0.750|0.813|0.813|0.868|0.813|ns|
|HSTL_I_18_F|0.258|0.322|0.339|0.322|0.439|0.456|0.474|0.456|0.549|0.576|0.606|0.576|ns|
|HSTL_I_18_M|0.258|0.322|0.339|0.322|0.562|0.569|0.602|0.569|0.637|0.653|0.692|0.653|ns|
|HSTL_I_18_S|0.258|0.322|0.339|0.322|0.781|0.781|0.833|0.781|0.816|0.816|0.871|0.816|ns|
|HSTL_I_DCI_12_F|0.322|0.378|0.399|0.378|0.393|0.406|0.429|0.406|0.502|0.534|0.564|0.534|ns|
|HSTL_I_DCI_12_M|0.322|0.378|0.399|0.378|0.551|0.556|0.586|0.556|0.644|0.654|0.694|0.654|ns|
|HSTL_I_DCI_12_S|0.322|0.378|0.399|0.378|0.754|0.754|0.803|0.754|0.842|0.842|0.907|0.842|ns|
|HSTL_I_DCI_18_F|0.258|0.321|0.339|0.321|0.422|0.445|0.461|0.445|0.509|0.566|0.595|0.566|ns|
|HSTL_I_DCI_18_M|0.258|0.321|0.339|0.321|0.551|0.554|0.585|0.554|0.634|0.643|0.684|0.643|ns|
|HSTL_I_DCI_18_S|0.258|0.321|0.339|0.321|0.761|0.761|0.817|0.761|0.836|0.836|0.900|0.836|ns|
|HSTL_I_DCI_F|0.288|0.393|0.415|0.393|0.407|0.431|0.445|0.431|0.517|0.555|0.575|0.555|ns|
|HSTL_I_DCI_M|0.288|0.393|0.415|0.393|0.548|0.552|0.581|0.552|0.635|0.644|0.684|0.644|ns|
|HSTL_I_DCI_S|0.288|0.393|0.415|0.393|0.766|0.766|0.821|0.766|0.847|0.847|0.912|0.847|ns|
|HSTL_I_F|0.322|0.378|0.399|0.378|0.409|0.423|0.443|0.423|0.514|0.549|0.581|0.549|ns|
|HSTL_I_M|0.322|0.378|0.399|0.378|0.548|0.554|0.585|0.554|0.624|0.640|0.677|0.640|ns|
|HSTL_I_S|0.322|0.378|0.399|0.378|0.766|0.766|0.816|0.766|0.811|0.811|0.866|0.811|ns|
|HSUL_12_DCI_F|0.319|0.378|0.399|0.378|0.411|0.425|0.443|0.425|0.520|0.558|0.586|0.558|ns|
|HSUL_12_DCI_M|0.319|0.378|0.399|0.378|0.551|0.556|0.586|0.556|0.644|0.654|0.694|0.654|ns|
|HSUL_12_DCI_S|0.319|0.378|0.399|0.378|0.736|0.736|0.784|0.736|0.821|0.821|0.886|0.821|ns|
|HSUL_12_F|0.305|0.378|0.399|0.378|0.394|0.412|0.430|0.412|0.494|0.538|0.566|0.538|ns|
|HSUL_12_M|0.305|0.378|0.399|0.378|0.551|0.551|0.582|0.551|0.632|0.642|0.679|0.642|ns|
|HSUL_12_S|0.305|0.378|0.399|0.378|0.750|0.750|0.799|0.750|0.813|0.813|0.868|0.813|ns|
|LVCMOS12_F_2|0.443|0.512|0.555|0.512|0.657|0.672|0.692|0.672|0.862|0.898|0.922|0.898|ns|
|LVCMOS12_F_4|0.443|0.512|0.555|0.512|0.486|0.504|0.521|0.504|0.645|0.664|0.693|0.664|ns|
|LVCMOS12_F_6|0.443|0.512|0.555|0.512|0.469|0.485|0.507|0.485|0.585|0.634|0.669|0.634|ns|
|LVCMOS12_F_8|0.443|0.512|0.555|0.512|0.457|0.465|0.489|0.465|0.592|0.611|0.666|0.611|ns|
|LVCMOS12_M_2|0.443|0.512|0.555|0.512|0.687|0.708|0.727|0.708|0.889|0.916|0.945|0.916|ns|
|LVCMOS12_M_4|0.443|0.512|0.555|0.512|0.533|0.550|0.573|0.550|0.629|0.664|0.690|0.664|ns|
|LVCMOS12_M_6|0.443|0.512|0.555|0.512|0.520|0.527|0.554|0.527|0.608|0.622|0.652|0.622|ns|
|LVCMOS12_M_8|0.443|0.512|0.555|0.512|0.532|0.540|0.571|0.540|0.606|0.614|0.649|0.614|ns|
|LVCMOS12_S_2|0.443|0.512|0.555|0.512|0.767|0.767|0.803|0.767|0.981|0.990|1.024|0.990|ns|
|LVCMOS12_S_4|0.443|0.512|0.555|0.512|0.666|0.666|0.704|0.666|0.803|0.803|0.848|0.803|ns|
|LVCMOS12_S_6|0.443|0.512|0.555|0.512|0.657|0.657|0.695|0.657|0.732|0.732|0.774|0.732|ns|
|LVCMOS12_S_8|0.443|0.512|0.555|0.512|0.708|0.708|0.761|0.708|0.745|0.745|0.790|0.745|ns|
|LVCMOS15_F_12|0.368|0.414|0.445|0.414|0.485|0.500|0.522|0.500|0.584|0.647|0.682|0.647|ns|
|LVCMOS15_F_2|0.368|0.414|0.445|0.414|0.686|0.702|0.722|0.702|0.893|0.919|0.940|0.919|ns|



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Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## _Table 24:_ **IOB High Performance (HP) Switching Characteristics** _(cont'd)_ 

|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|_Table 24:_**IOB High Performance (HP) Switching Characteristics**_(cont'd)_||||||||||||||
|**I/O Standards**|**TINBUF_DELAY_PAD_I**||||**TOUTBUF_DELAY_O_PAD**||||**TOUTBUF_DELAY_TD_PAD**||||**Units**|
||**0.90V**|**0.85V**||**0.72V**|**0.90V**|**0.85V**||**0.72V**|**0.90V**|**0.85V**||**0.72V**||
||**-3**|**-2**|**-1**|**-2**|**-3**|**-2**|**-1**|**-2**|**-3**|**-2**|**-1**|**-2**||
|LVCMOS15_F_4|0.368|0.414|0.445|0.414|0.567|0.579|0.601|0.579|0.727|0.755|0.781|0.755|ns|
|LVCMOS15_F_6|0.368|0.414|0.445|0.414|0.533|0.547|0.569|0.547|0.684|0.711|0.742|0.711|ns|
|LVCMOS15_F_8|0.368|0.414|0.445|0.414|0.500|0.518|0.538|0.518|0.635|0.686|0.703|0.686|ns|
|LVCMOS15_M_12|0.368|0.414|0.445|0.414|0.607|0.607|0.644|0.607|0.637|0.637|0.676|0.637|ns|
|LVCMOS15_M_2|0.368|0.414|0.445|0.414|0.736|0.741|0.770|0.741|0.929|0.938|0.962|0.938|ns|
|LVCMOS15_M_4|0.368|0.414|0.445|0.414|0.610|0.625|0.651|0.625|0.733|0.754|0.786|0.754|ns|
|LVCMOS15_M_6|0.368|0.414|0.445|0.414|0.564|0.576|0.604|0.576|0.655|0.674|0.710|0.674|ns|
|LVCMOS15_M_8|0.368|0.414|0.445|0.414|0.565|0.568|0.601|0.568|0.634|0.639|0.681|0.639|ns|
|LVCMOS15_S_12|0.368|0.414|0.445|0.414|0.788|0.788|0.855|0.788|0.695|0.695|0.733|0.695|ns|
|LVCMOS15_S_2|0.368|0.414|0.445|0.414|0.829|0.829|0.864|0.829|1.038|1.039|1.079|1.039|ns|
|LVCMOS15_S_4|0.368|0.414|0.445|0.414|0.687|0.687|0.725|0.687|0.813|0.813|0.851|0.813|ns|
|LVCMOS15_S_6|0.368|0.414|0.445|0.414|0.671|0.671|0.710|0.671|0.726|0.726|0.763|0.726|ns|
|LVCMOS15_S_8|0.368|0.414|0.445|0.414|0.704|0.704|0.755|0.704|0.721|0.721|0.758|0.721|ns|
|LVCMOS18_F_12|0.352|0.418|0.445|0.418|0.564|0.573|0.601|0.573|0.696|0.731|0.769|0.731|ns|
|LVCMOS18_F_2|0.352|0.418|0.445|0.418|0.723|0.739|0.760|0.739|0.918|0.945|0.971|0.945|ns|
|LVCMOS18_F_4|0.352|0.418|0.445|0.418|0.598|0.609|0.630|0.609|0.749|0.778|0.802|0.778|ns|
|LVCMOS18_F_6|0.352|0.418|0.445|0.418|0.598|0.603|0.633|0.603|0.781|0.781|0.808|0.781|ns|
|LVCMOS18_F_8|0.352|0.418|0.445|0.418|0.567|0.573|0.600|0.573|0.712|0.733|0.767|0.733|ns|
|LVCMOS18_M_12|0.352|0.418|0.445|0.418|0.640|0.640|0.678|0.640|0.670|0.670|0.709|0.670|ns|
|LVCMOS18_M_2|0.352|0.418|0.445|0.418|0.785|0.798|0.822|0.798|0.986|0.991|1.016|0.991|ns|
|LVCMOS18_M_4|0.352|0.418|0.445|0.418|0.658|0.664|0.693|0.664|0.786|0.798|0.836|0.798|ns|
|LVCMOS18_M_6|0.352|0.418|0.445|0.418|0.625|0.629|0.663|0.629|0.727|0.735|0.775|0.735|ns|
|LVCMOS18_M_8|0.352|0.418|0.445|0.418|0.626|0.626|0.661|0.626|0.705|0.705|0.746|0.705|ns|
|LVCMOS18_S_12|0.352|0.418|0.445|0.418|0.795|0.795|0.861|0.795|0.683|0.683|0.721|0.683|ns|
|LVCMOS18_S_2|0.352|0.418|0.445|0.418|0.861|0.862|0.897|0.862|1.061|1.076|1.098|1.076|ns|
|LVCMOS18_S_4|0.352|0.418|0.445|0.418|0.716|0.716|0.758|0.716|0.829|0.829|0.872|0.829|ns|
|LVCMOS18_S_6|0.352|0.418|0.445|0.418|0.682|0.682|0.724|0.682|0.724|0.724|0.762|0.724|ns|
|LVCMOS18_S_8|0.352|0.418|0.445|0.418|0.707|0.707|0.760|0.707|0.709|0.709|0.745|0.709|ns|
|LVDCI_15_F|0.369|0.425|0.462|0.425|0.407|0.426|0.443|0.426|0.514|0.548|0.581|0.548|ns|
|LVDCI_15_M|0.369|0.425|0.462|0.425|0.549|0.553|0.582|0.553|0.632|0.645|0.685|0.645|ns|
|LVDCI_15_S|0.369|0.425|0.462|0.425|0.749|0.749|0.803|0.749|0.821|0.821|0.890|0.821|ns|
|LVDCI_18_F|0.367|0.414|0.447|0.414|0.422|0.441|0.459|0.441|0.541|0.560|0.589|0.560|ns|
|LVDCI_18_M|0.367|0.414|0.447|0.414|0.546|0.554|0.585|0.554|0.622|0.644|0.683|0.644|ns|
|LVDCI_18_S|0.367|0.414|0.447|0.414|0.760|0.760|0.818|0.760|0.837|0.837|0.899|0.837|ns|
|LVDS|0.508|0.539|0.620|0.539|0.626|0.626|0.662|0.626|960.447|960.447|960.447|960.447|ns|
|MIPI_DPHY_DCI_HS|0.305|0.386|0.415|0.386|0.489|0.502|0.522|0.502|N/A|N/A|N/A|N/A|ns|
|MIPI_DPHY_DCI_LP|8.438|8.438|8.792|8.438|0.895|0.914|0.937|0.914|N/A|N/A|N/A|N/A|ns|
|POD10_DCI_F|0.336|0.408|0.430|0.408|0.407|0.425|0.444|0.425|0.512|0.555|0.584|0.555|ns|
|POD10_DCI_M|0.336|0.408|0.430|0.408|0.533|0.542|0.571|0.542|0.618|0.640|0.681|0.640|ns|
|POD10_DCI_S|0.336|0.408|0.430|0.408|0.724|0.754|0.815|0.754|0.815|0.850|0.917|0.850|ns|



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Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## _Table 24:_ **IOB High Performance (HP) Switching Characteristics** _(cont'd)_ 

|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|_Table 24:_**IOB High Performance (HP) Switching Characteristics**_(cont'd)_||||||||||||||
|**I/O Standards**|**TINBUF_DELAY_PAD_I**||||**TOUTBUF_DELAY_O_PAD**||||**TOUTBUF_DELAY_TD_PAD**||||**Units**|
||**0.90V**|**0.85V**||**0.72V**|**0.90V**|**0.85V**||**0.72V**|**0.90V**|**0.85V**||**0.72V**||
||**-3**|**-2**|**-1**|**-2**|**-3**|**-2**|**-1**|**-2**|**-3**|**-2**|**-1**|**-2**||
|POD10_F|0.336|0.407|0.430|0.407|0.425|0.438|0.459|0.438|0.531|0.569|0.601|0.569|ns|
|POD10_M|0.336|0.407|0.430|0.407|0.519|0.538|0.568|0.538|0.589|0.630|0.667|0.630|ns|
|POD10_S|0.336|0.407|0.430|0.407|0.752|0.766|0.821|0.766|0.821|0.836|0.894|0.836|ns|
|POD12_DCI_F|0.336|0.409|0.431|0.409|0.411|0.425|0.443|0.425|0.519|0.558|0.586|0.558|ns|
|POD12_DCI_M|0.336|0.409|0.431|0.409|0.516|0.543|0.572|0.543|0.602|0.638|0.678|0.638|ns|
|POD12_DCI_S|0.336|0.409|0.431|0.409|0.740|0.772|0.822|0.772|0.833|0.862|0.929|0.862|ns|
|POD12_F|0.336|0.409|0.431|0.409|0.438|0.455|0.476|0.455|0.549|0.595|0.626|0.595|ns|
|POD12_M|0.336|0.409|0.431|0.409|0.551|0.551|0.582|0.551|0.632|0.641|0.679|0.641|ns|
|POD12_S|0.336|0.409|0.431|0.409|0.749|0.767|0.817|0.767|0.818|0.832|0.889|0.832|ns|
|SLVS_400_18|0.492|0.539|0.620|0.539|N/A|N/A|N/A|N/A|N/A|N/A|N/A|N/A|ns|
|SSTL12_DCI_F|0.331|0.381|0.399|0.381|0.411|0.425|0.443|0.425|0.520|0.558|0.586|0.558|ns|
|SSTL12_DCI_M|0.331|0.381|0.399|0.381|0.549|0.557|0.587|0.557|0.643|0.654|0.694|0.654|ns|
|SSTL12_DCI_S|0.331|0.381|0.399|0.381|0.754|0.754|0.803|0.754|0.842|0.842|0.908|0.842|ns|
|SSTL12_F|0.320|0.403|0.403|0.403|0.394|0.412|0.430|0.412|0.494|0.538|0.566|0.538|ns|
|SSTL12_M|0.320|0.403|0.403|0.403|0.550|0.553|0.584|0.553|0.630|0.641|0.676|0.641|ns|
|SSTL12_S|0.320|0.403|0.403|0.403|0.758|0.758|0.808|0.758|0.823|0.823|0.879|0.823|ns|
|SSTL135_DCI_F|0.341|0.366|0.399|0.366|0.392|0.411|0.428|0.411|0.494|0.537|0.565|0.537|ns|
|SSTL135_DCI_M|0.341|0.366|0.399|0.366|0.551|0.551|0.582|0.551|0.643|0.645|0.685|0.645|ns|
|SSTL135_DCI_S|0.341|0.366|0.399|0.366|0.746|0.746|0.799|0.746|0.829|0.829|0.893|0.829|ns|
|SSTL135_F|0.321|0.378|0.399|0.378|0.393|0.408|0.428|0.408|0.491|0.528|0.561|0.528|ns|
|SSTL135_M|0.321|0.378|0.399|0.378|0.548|0.555|0.585|0.555|0.621|0.641|0.679|0.641|ns|
|SSTL135_S|0.321|0.378|0.399|0.378|0.772|0.772|0.823|0.772|0.827|0.827|0.878|0.827|ns|
|SSTL15_DCI_F|0.319|0.402|0.417|0.402|0.394|0.412|0.429|0.412|0.497|0.531|0.563|0.531|ns|
|SSTL15_DCI_M|0.319|0.402|0.417|0.402|0.549|0.553|0.583|0.553|0.632|0.645|0.685|0.645|ns|
|SSTL15_DCI_S|0.319|0.402|0.417|0.402|0.768|0.768|0.822|0.768|0.847|0.847|0.912|0.847|ns|
|SSTL15_F|0.320|0.371|0.400|0.371|0.393|0.408|0.428|0.408|0.494|0.530|0.556|0.530|ns|
|SSTL15_M|0.320|0.371|0.400|0.371|0.547|0.554|0.585|0.554|0.624|0.639|0.677|0.639|ns|
|SSTL15_S|0.320|0.371|0.400|0.371|0.767|0.767|0.817|0.767|0.813|0.813|0.867|0.813|ns|
|SSTL18_I_DCI_F|0.256|0.329|0.336|0.329|0.422|0.445|0.461|0.445|0.540|0.566|0.595|0.566|ns|
|SSTL18_I_DCI_M|0.256|0.329|0.336|0.329|0.552|0.554|0.585|0.554|0.629|0.644|0.683|0.644|ns|
|SSTL18_I_DCI_S|0.256|0.329|0.336|0.329|0.762|0.762|0.818|0.762|0.837|0.837|0.899|0.837|ns|
|SSTL18_I_F|0.259|0.316|0.337|0.316|0.439|0.454|0.476|0.454|0.549|0.578|0.608|0.578|ns|
|SSTL18_I_M|0.259|0.316|0.337|0.316|0.567|0.571|0.603|0.571|0.535|0.652|0.692|0.652|ns|
|SSTL18_I_S|0.259|0.316|0.337|0.316|0.782|0.782|0.835|0.782|0.816|0.816|0.870|0.816|ns|
|SUB_LVDS|0.508|0.539|0.620|0.539|0.658|0.660|0.692|0.660|907.387|969.863|969.863|969.863|ns|



## **IOB 3-state Output Switching Characteristics** 

Table 25 specifies the values of TOUTBUF_DELAY_TE_PAD and TINBUF_DELAY_IBUFDIS_O. 

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Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

- TOUTBUF_DELAY_TE_PAD is the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is enabled (i.e., a high impedance state). 

- TINBUF_DELAY_IBUFDIS_O is the IOB delay from IBUFDISABLE to O output. 

- In I/O banks, the internal DCI termination turn-off time is always faster than TOUTBUF_DELAY_TE_PAD when the DCITERMDISABLE pin is used. 

_Table 25:_ **IOB 3-state Output Switching Characteristics** 

|• In I/O banks, the internal DCI terminaton turn-of tme is always faster than TOUTBUF_DELAY_TE_PADwhen the<br>DCITERMDISABLE pin is used.|• In I/O banks, the internal DCI terminaton turn-of tme is always faster than TOUTBUF_DELAY_TE_PADwhen the<br>DCITERMDISABLE pin is used.|• In I/O banks, the internal DCI terminaton turn-of tme is always faster than TOUTBUF_DELAY_TE_PADwhen the<br>DCITERMDISABLE pin is used.|• In I/O banks, the internal DCI terminaton turn-of tme is always faster than TOUTBUF_DELAY_TE_PADwhen the<br>DCITERMDISABLE pin is used.|• In I/O banks, the internal DCI terminaton turn-of tme is always faster than TOUTBUF_DELAY_TE_PADwhen the<br>DCITERMDISABLE pin is used.|• In I/O banks, the internal DCI terminaton turn-of tme is always faster than TOUTBUF_DELAY_TE_PADwhen the<br>DCITERMDISABLE pin is used.|• In I/O banks, the internal DCI terminaton turn-of tme is always faster than TOUTBUF_DELAY_TE_PADwhen the<br>DCITERMDISABLE pin is used.|
|---|---|---|---|---|---|---|
|_Table 25:_**IOB 3-state Output Switching Characteristics**|||||||
|**Symbol**|**Description**|**Speed Grade and VCCINT Operating Voltages**||||**Units**|
|||**0.90V**|**0.85V**||**0.72V**||
|||**-3**|**-2**|**-1**|**-2**||
|TOUTBUF_DELAY_TE_PAD|T input to pad high-impedance for the<br>I/O banks|5.330|5.330|5.341|5.330|ns|
|TINBUF_DELAY_IBUFDIS_O|IBUF turn-on time from IBUFDISABLE to<br>O output for the I/O banks|0.873|0.936|1.037|0.936|ns|



## **Input Delay Measurement Methodology** 

The following table shows the test setup parameters used for measuring input delay. 

## _Table 26:_ **Input Delay Measurement Methodology** 

|The following table shows the test setup parameters used for measuring input delay.|The following table shows the test setup parameters used for measuring input delay.|The following table shows the test setup parameters used for measuring input delay.|The following table shows the test setup parameters used for measuring input delay.|The following table shows the test setup parameters used for measuring input delay.|The following table shows the test setup parameters used for measuring input delay.|
|---|---|---|---|---|---|
|_Table 26:_**Input Delay Measurement Methodology**||||||
|**Description**|**I/O Standard Attribute**|**VL**1**,**2|**VH**1**,**2|**VMEAS**1**,**4|**VREF **1**,**3**,**5|
|LVCMOS, 1.2V|LVCMOS12|0.1|1.1|0.6|–|
|LVCMOS, LVDCI, HSLVDCI, 1.5V|LVCMOS15, LVDCI_15,<br>HSLVDCI_15|0.1|1.4|0.75|–|
|LVCMOS, LVDCI, HSLVDCI, 1.8V|LVCMOS18, LVDCI_18,<br>HSLVDCI_18|0.1|1.7|0.9|–|
|HSTL (high-speed transceiver logic), class I, 1.2V|HSTL_I_12|VREF– 0.25|VREF+ 0.25|VREF|0.6|
|HSTL, class I, 1.5V|HSTL_I|VREF– 0.325|VREF+ 0.325|VREF|0.75|
|HSTL, class I, 1.8V|HSTL_I_18|VREF– 0.4|VREF+ 0.4|VREF|0.9|
|HSUL (high-speed unterminated logic), 1.2V|HSUL_12|VREF– 0.25|VREF+ 0.25|VREF|0.6|
|SSTL12 (stub series terminated logic), 1.2V|SSTL12|VREF– 0.25|VREF+ 0.25|VREF|0.6|
|SSTL135, 1.35V|SSTL135|VREF– 0.2875|VREF+ 0.2875|VREF|0.675|
|SSTL15, 1.5V|SSTL15|VREF– 0.325|VREF+ 0.325|VREF|0.75|
|SSTL18, class I, 1.8V|SSTL18_I|VREF– 0.4|VREF+ 0.4|VREF|0.9|
|POD10, 1.0V|POD10|VREF– 0.2|VREF+ 0.2|VREF|0.7|
|POD12, 1.2V|POD12|VREF– 0.24|VREF+ 0.24|VREF|0.84|
|DIFF_HSTL, class I, 1.2V|DIFF_HSTL_I_12|0.6 – 0.25|0.6 + 0.25|06|–|
|DIFF_HSTL, class I, 1.5V|DIFF_HSTL_I|0.75 – 0.325|0.75 + 0.325|06|–|
|DIFF_HSTL, class I, 1.8V|DIFF_HSTL_I_18|0.9 – 0.4|0.9 + 0.4|06|–|
|DIFF_HSUL, 1.2V|DIFF_HSUL_12|0.6 – 0.25|0.6 + 0.25|06|–|
|DIFF_SSTL, 1.2V|DIFF_SSTL12|0.6 – 0.25|0.6 + 0.25|06|–|
|DIFF_SSTL135, 1.35V|DIFF_SSTL135|0.675 – 0.2875|0.675 + 0.2875|06|–|
|DIFF_SSTL15, 1.5V|DIFF_SSTL15|0.75 – 0.325|0.75 + 0.325|06|–|
|DIFF_SSTL18_I, 1.8V|DIFF_SSTL18_I|0.9 – 0.4|0.9 + 0.4|06|–|
|DIFF_POD10, 1.0V|DIFF_POD10|0.5 – 0.2|0.5 + 0.2|06|–|



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Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## _Table 26:_ **Input Delay Measurement Methodology** _(cont'd)_ 

|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|
|_Table 26:_**Input Delay Measurement Methodology**_(cont'd)_||||||
|**Description**|**I/O Standard Attribute**|**VL**1**,**2|**VH**1**,**2|**VMEAS**1**,**4|**VREF **1**,**3**,**5|
|DIFF_POD12, 1.2V|DIFF_POD12|0.6 – 0.25|0.6 + 0.25|06|–|
|LVDS (low-voltage differential signaling), 1.8V|LVDS|0.9 – 0.125|0.9 + 0.125|06|–|
|SUB_LVDS, 1.8V|SUB_LVDS|0.9 – 0.125|0.9 + 0.125|06|–|
|SLVS, 1.8V|SLVS_400_18|0.9 – 0.125|0.9 + 0.125|06|–|
|MIPI D-PHY (high speed) 1.2V|MIPI_DPHY_DCI_HS|0.2 – 0.125|0.2 + 0.125|06|–|
|MIPI D-PHY (low power) 1.2V|MIPI_DPHY_DCI_LP|0.715 – 0.2|0.715 + 0.2|06|–|
|**Notes:**<br>1.<br>The input delay measurement methodology parameters for LVDCI/HSLVDCI are the same for LVCMOS standards of the same voltage.<br>Parameters for all other DCI standards are the same for the corresponding non-DCI standards.<br>2.<br>Input waveform switches between VLand VH.<br>3.<br>Measurements are made at typical, minimum, and maximum VREFvalues. Reported delays reflect worst case of these measurements.<br>VREFvalues listed are typical.<br>4.<br>Input voltage level from which measurement starts.<br>5.<br>This is an input voltage reference that bears no relation to the VREF/VMEASparameters found in IBIS models and/or noted inFigure 1.<br>6.<br>The value given is the differential input voltage.||||||



## **Output Delay Measurement Methodology** 

Output delays are measured with short output traces. Standard termination was used for all testing. The propagation delay of the trace is characterized separately and subtracted from the final measurement, and is therefore not included in the generalized test setups shown in Figure 1 and Figure 2. 

## _Figure 1:_ **Single-Ended Test Setup** 

**==> picture [333 x 173] intentionally omitted <==**

**----- Start of picture text -----**<br>
VREF<br>Output RREF<br>VMEAS (voltage level when taking delay measurement)<br>CREF (probe capacitance)<br>X16654-072117<br>**----- End of picture text -----**<br>


_Figure 2:_ **Differential Test Setup** 

**==> picture [180 x 75] intentionally omitted <==**

**----- Start of picture text -----**<br>
Output<br>+<br>CREF RREF VMEAS<br>–<br>X16640-072117<br>**----- End of picture text -----**<br>


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Parameters VREF, RREF, CREF, and VMEAS fully describe the test conditions for each I/O standard. The most accurate prediction of propagation delay in any given application can be obtained through IBIS simulation, using this method: 

1. Simulate the output driver of choice into the generalized test setup using values from Table 27. 

2. Record the time to VMEAS. 

3. Simulate the output driver of choice into the actual PCB trace and load using the appropriate IBIS model or capacitance value to represent the load. 

4. Record the time to VMEAS. 

5. Compare the results of step 2 and step 4. The increase or decrease in delay yields the actual propagation delay of the PCB trace. 

_Table 27:_ **Output Delay Measurement Methodology** 

|4.<br>Record the tme to VMEAS.<br>5.<br>Compare the results of step2and step4. The increase or decrease in delay yields the actual propagaton<br>delay of the PCB trace.|4.<br>Record the tme to VMEAS.<br>5.<br>Compare the results of step2and step4. The increase or decrease in delay yields the actual propagaton<br>delay of the PCB trace.|4.<br>Record the tme to VMEAS.<br>5.<br>Compare the results of step2and step4. The increase or decrease in delay yields the actual propagaton<br>delay of the PCB trace.|4.<br>Record the tme to VMEAS.<br>5.<br>Compare the results of step2and step4. The increase or decrease in delay yields the actual propagaton<br>delay of the PCB trace.|4.<br>Record the tme to VMEAS.<br>5.<br>Compare the results of step2and step4. The increase or decrease in delay yields the actual propagaton<br>delay of the PCB trace.|4.<br>Record the tme to VMEAS.<br>5.<br>Compare the results of step2and step4. The increase or decrease in delay yields the actual propagaton<br>delay of the PCB trace.|
|---|---|---|---|---|---|
|_Table 27:_**Output Delay Measurement Methodology**||||||
|**Description**|**I/O Standard Attribute**|**RREF**<br>**(Ω)**|**CREF**1**(pF)**|**VMEAS**<br>**(V)**|**VREF (V)**|
|LVCMOS, 1.2V|LVCMOS12|1M|0|0.6|0|
|LVCMOS, 1.5V|LVCMOS15|1M|0|0.75|0|
|LVCMOS, 1.8V|LVCMOS18|1M|0|0.9|0|
|LVDCI, HSLVDCI, 1.5V|LVDCI_15, HSLVDCI_15|50|0|VREF|0.75|
|LVDCI, HSLVDCI, 1.8V|LVDCI_15, HSLVDCI_18|50|0|VREF|0.9|
|HSTL (high-speed transceiver logic), class I, 1.2V|HSTL_I_12|50|0|VREF|0.6|
|HSTL, class I, 1.5V|HSTL_I|50|0|VREF|0.75|
|HSTL, class I, 1.8V|HSTL_I_18|50|0|VREF|0.9|
|HSUL (high-speed unterminated logic), 1.2V|HSUL_12|50|0|VREF|0.6|
|SSTL12 (stub series terminated logic), 1.2V|SSTL12|50|0|VREF|0.6|
|SSTL135, 1.35V|SSTL135|50|0|VREF|0.675|
|SSTL15, 1.5V|SSTL15|50|0|VREF|0.75|
|SSTL18, class I, 1.8V|SSTL18_I|50|0|VREF|0.9|
|POD10, 1.0V|POD10|50|0|VREF|1.0|
|POD12, 1.2V|POD12|50|0|VREF|1.2|
|DIFF_HSTL, class I, 1.2V|DIFF_HSTL_I_12|50|0|VREF|0.6|
|DIFF_HSTL, class I, 1.5V|DIFF_HSTL_I|50|0|VREF|0.75|
|DIFF_HSTL, class I, 1.8V|DIFF_HSTL_I_18|50|0|VREF|0.9|
|DIFF_HSUL, 1.2V|DIFF_HSUL_12|50|0|VREF|0.6|
|DIFF_SSTL12, 1.2V|DIFF_SSTL12|50|0|VREF|0.6|
|DIFF_SSTL135, 1.35V|DIFF_SSTL135|50|0|VREF|0.675|
|DIFF_SSTL15, 1.5V|DIFF_SSTL15|50|0|VREF|0.75|
|DIFF_SSTL18, 1.8V|DIFF_SSTL18_I|50|0|VREF|0.9|
|DIFF_POD10, 1.0V|DIFF_POD10|50|0|VREF|1.0|
|DIFF_POD12, 1.2V|DIFF_POD12|50|0|VREF|1.2|
|LVDS (low-voltage differential signaling), 1.8V|LVDS|100|0|02|0|
|SUB_LVDS, 1.8V|SUB_LVDS|100|0|02|0|
|MIPI D-PHY (high speed) 1.2V|MIPI_DPHY_DCI_HS|100|0|02|0|



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Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## _Table 27:_ **Output Delay Measurement Methodology** _(cont'd)_ 

|_Table 27:_**Output Delay Measurement Methodology**_(cont'd)_|_Table 27:_**Output Delay Measurement Methodology**_(cont'd)_|_Table 27:_**Output Delay Measurement Methodology**_(cont'd)_|_Table 27:_**Output Delay Measurement Methodology**_(cont'd)_|_Table 27:_**Output Delay Measurement Methodology**_(cont'd)_|_Table 27:_**Output Delay Measurement Methodology**_(cont'd)_|
|---|---|---|---|---|---|
|**Description**|**I/O Standard Attribute**|**RREF**<br>**(Ω)**|**CREF**1**(pF)**|**VMEAS**<br>**(V)**|**VREF (V)**|
|MIPI D-PHY (low power) 1.2V|MIPI_DPHY_DCI_LP|1M|0|0.6|0|
|**Notes:**<br>1.<br>CREFis the capacitance of the probe, nominally 0 pF.<br>2.<br>The value given is the differential output voltage.||||||



## **Block RAM and FIFO Switching Characteristics** 

## _Table 28:_ **Block RAM and FIFO Switching Characteristics** 

|**Block RAM and FIFO Switching Characteristics**|**Block RAM and FIFO Switching Characteristics**|**Block RAM and FIFO Switching Characteristics**|**Block RAM and FIFO Switching Characteristics**|**Block RAM and FIFO Switching Characteristics**|**Block RAM and FIFO Switching Characteristics**|**Block RAM and FIFO Switching Characteristics**|
|---|---|---|---|---|---|---|
|_Table 28:_**Block RAM and FIFO Switching Characteristics**|||||||
|**Symbol**|**Description**|**Speed Grade and VCCINT Operating Voltages**||||**Units**|
|||**0.90V**|**0.85V**||**0.72V**||
|||**-3**|**-2**|**-1**|**-2**||
|Maximum Frequency|||||||
|FMAX_WF_NC|Block RAM (WRITE_FIRST and NO_CHANGE<br>modes)|825|737|645|585|MHz|
|FMAX_RF|Block RAM (READ_FIRST mode)|718|637|575|510|MHz|
|FMAX_FIFO|FIFO in all modes without ECC|825|737|645|585|MHz|
|FMAX_ECC|Block RAM and FIFO in ECC configuration<br>without PIPELINE|718|637|575|510|MHz|
||Block RAM and FIFO in ECC configuration with<br>PIPELINE and Block RAM in WRITE_FIRST or<br>NO_CHANGE mode|825|737|645|585|MHz|
|TPW1|Minimum pulse width|495|542|543|577|ps|
|Block RAM and FIFO Clock-to-Out Delays|||||||
|TRCKO_DO|Clock CLK to DOUT output (without output<br>register)|0.91|1.02|1.11|1.46|ns, Max|
|TRCKO_DO_REG|Clock CLK to DOUT output (with output register)|0.27|0.29|0.30|0.42|ns, Max|
|**Notes:**<br>1.<br>The MMCM and PLL DUTY_CYCLE attribute should be set to 50% to meet the pulse-width requirements at the higher frequencies.|||||||



## **UltraRAM Switching Characteristics** 

The _UltraScale Architecture and Product Data Sheet: Overview_ (DS890) lists the Virtex UltraScale+ FPGAs that include this memory. 

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_Table 29:_ **UltraRAM Switching Characteristics** 

|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|---|
|_Table 29:_**UltraRAM Switching Characteristics**|||||||
|**Symbol**|**Description**|**Speed Grade and VCCINT Operating Voltages**||||**Units**|
|||**0.90V**|**0.85V**||**0.72V**||
|||**-3**|**-2**|**-1**|**-2**||
|Maximum Frequency|||||||
|FMAX|UltraRAM maximum frequency with<br>OREG_B = True|650|600|575|500|MHz|
|FMAX_ECC_NOPIPELINE|UltraRAM maximum frequency with<br>OREG_B = False and EN_ECC_RD_B = True|435|400|386|312|MHz|
|FMAX_NOPIPELINE|UltraRAM maximum frequency with<br>OREG_B = False and EN_ECC_RD_B = False|528|500|478|404|MHz|
|TPW1|Minimum pulse width|650|700|730|800|ps|
|TRSTPW|Asynchronous reset minimum pulse width. One<br>cycle required|1 clock cycle|||||
|**Notes:**<br>1.<br>The MMCM and PLL DUTY_CYCLE attribute should be set to 50% to meet the pulse-width requirements at the higher frequencies.|||||||



## **Input/Output Delay Switching Characteristics** 

_Table 30:_ **Input/Output Delay Switching Characteristics** 

|**Input/Output Delay Switching Characteristics**|**Input/Output Delay Switching Characteristics**|**Input/Output Delay Switching Characteristics**|**Input/Output Delay Switching Characteristics**|**Input/Output Delay Switching Characteristics**|**Input/Output Delay Switching Characteristics**|**Input/Output Delay Switching Characteristics**|
|---|---|---|---|---|---|---|
|_Table 30:_**Input/Output Delay Switching Characteristics**|||||||
|**Symbol**|**Description**|**Speed Grade and VCCINT Operating Voltages**||||**Units**|
|||**0.90V**|**0.85V**||**0.72V**||
|||**-3**|**-2**|**-1**|**-2**||
|FREFCLK|Reference clock frequency for IDELAYCTRL<br>(component mode)|300 to 800||||MHz|
||Reference clock frequency when using<br>BITSLICE_CONTROL with REFCLK (in native mode (for<br>RX_BITSLICE only))|300 to 800||||MHz|
||Reference clock frequency for BITSLICE_CONTROL<br>with PLL_CLK (in native mode)1|300 to<br>2666.67|300 to<br>2666.67|300 to 2400|300 to 2400|MHz|
|TMINPER_CLK|Minimum period for IODELAY clock|3.195|3.195|3.195|3.195|ns|
|TMINPER_RST|Minimum reset pulse width|52.00||||ns|
|TIDELAY_RESOLUTION/<br>TODELAY_RESOLUTION|IDELAY/ODELAY chain resolution|2.1 to 12||||ps|
|**Notes:**<br>1.<br>PLL settings could restrict the minimum allowable data rate. For example, when using a PLL with CLKOUTPHY_MODE = VCO_HALF, the<br>minimum frequency is PLL_FVCOMIN/2.|||||||



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## **DSP48 Slice Switching Characteristics** 

_Table 31:_ **DSP48 Slice Switching Characteristics** 

|**DSP48 Slice Switching Characteristics**|**DSP48 Slice Switching Characteristics**|**DSP48 Slice Switching Characteristics**|**DSP48 Slice Switching Characteristics**|**DSP48 Slice Switching Characteristics**|**DSP48 Slice Switching Characteristics**|**DSP48 Slice Switching Characteristics**|
|---|---|---|---|---|---|---|
|_Table 31:_**DSP48 Slice Switching Characteristics**|||||||
|**Symbol**|**Description**|**Speed Grade and VCCINT Operating Voltages**||||**Units**|
|||**0.90V**|**0.85V**||**0.72V**1||
|||**-3**|**-2**|**-1**|**-2**||
|Maximum Frequency|||||||
|FMAX|With all registers used|891|775|645|644|MHz|
|FMAX_PATDET|With pattern detector|794|687|571|562|MHz|
|FMAX_MULT_NOMREG|Two register multiply without MREG|635|544|456|440|MHz|
|FMAX_MULT_NOMREG_PATDET|Two register multiply without MREG<br>with pattern detect|577|492|410|395|MHz|
|FMAX_PREADD_NOADREG|Without ADREG|655|565|468|453|MHz|
|FMAX_NOPIPELINEREG|Without pipeline registers (MREG,<br>ADREG)|483|410|338|323|MHz|
|FMAX_NOPIPELINEREG_PATDET|Without pipeline registers (MREG,<br>ADREG) with pattern detect|448|379|314|299|MHz|
|**Notes:**<br>1.<br>For devices operating at the lower power VCCINT= 0.72V voltages, DSP cascades that cross the clock region center might operate below<br>the specified FMAX.|||||||



## **Clock Buffers and Networks** 

## _Table 32:_ **Clock Buffers Switching Characteristics** 

|_Table 32:_**Clock Buffers Switching Characteristics**|_Table 32:_**Clock Buffers Switching Characteristics**|_Table 32:_**Clock Buffers Switching Characteristics**|_Table 32:_**Clock Buffers Switching Characteristics**|_Table 32:_**Clock Buffers Switching Characteristics**|_Table 32:_**Clock Buffers Switching Characteristics**|_Table 32:_**Clock Buffers Switching Characteristics**|
|---|---|---|---|---|---|---|
|**Symbol**|**Description**|**Speed Grade and VCCINT Operating Voltages**||||**Units**|
|||**0.90V**|**0.85V**||**0.72V**||
|||**-3**|**-2**|**-1**|**-2**||
|Global Clock Switching Characteristics (Including BUFGCTRL)|||||||
|FMAX|Maximum frequency of a global clock tree (BUFG)|891|775|667|725|MHz|
|Global Clock Buffer with Input Divide Capability (BUFGCE_DIV)|||||||
|FMAX|Maximum frequency of a global clock buffer with input<br>divide capability (BUFGCE_DIV)|891|775|667|725|MHz|
|Global Clock Buffer with Clock Enable (BUFGCE)|||||||
|FMAX|Maximum frequency of a global clock buffer with clock<br>enable (BUFGCE)|891|775|667|725|MHz|
|Leaf Clock Buffer with Clock Enable (BUFCE_LEAF)|||||||
|FMAX|Maximum frequency of a leaf clock buffer with clock<br>enable (BUFCE_LEAF)|891|775|667|725|MHz|
|GTY or GTM Clock Buffer with Clock Enable and Clock Input Divide Capability (BUFG_GT)|||||||
|FMAX|Maximum frequency of a serial transceiver clock buffer<br>with clock enable and clock input divide capability|512|512|512|512|MHz|



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## **MMCM Switching Characteristics** 

## _Table 33:_ **MMCM Specification** 

|**MMCM Switching Characteristics**|**MMCM Switching Characteristics**|**MMCM Switching Characteristics**|**MMCM Switching Characteristics**|**MMCM Switching Characteristics**|**MMCM Switching Characteristics**|**MMCM Switching Characteristics**|
|---|---|---|---|---|---|---|
|_Table 33:_**MMCM Specification**|||||||
|**Symbol**|**Description**|**Speed Grade and VCCINT Operating Voltages**||||**Units**|
|||**0.90V**|**0.85V**||**0.72V**||
|||**-3**|**-2**|**-1**|**-2**||
|MMCM_FINMAX|Maximum input clock frequency|1066|933|800|933|MHz|
|MMCM_FINMIN|Minimum input clock frequency|10|10|10|10|MHz|
|MMCM_FINJITTER|Maximum input clock period jitter|< 20% of clock input period or 1 ns Max|||||
|MMCM_FINDUTY|Input duty cycle range: 10–49 MHz|25–75||||%|
||Input duty cycle range: 50–199 MHz|30–70||||%|
||Input duty cycle range: 200–399 MHz|35–65||||%|
||Input duty cycle range: 400–499 MHz|40–60||||%|
||Input duty cycle range: >500 MHz|45–55||||%|
|MMCM_FMIN_PSCLK|Minimum dynamic phase shift clock<br>frequency|0.01|0.01|0.01|0.01|MHz|
|MMCM_FMAX_PSCLK|Maximum dynamic phase shift clock<br>frequency|550|500|450|500|MHz|
|MMCM_FVCOMIN|Minimum MMCM VCO frequency|800|800|800|800|MHz|
|MMCM_FVCOMAX|Maximum MMCM VCO frequency|1600|1600|1600|1600|MHz|
|MMCM_FBANDWIDTH|Low MMCM bandwidth at typical1|1.00|1.00|1.00|1.00|MHz|
||High MMCM bandwidth at typical1|4.00|4.00|4.00|4.00|MHz|
|MMCM_TSTATPHAOFFSET|Static phase offset of the MMCM outputs2|0.12|0.12|0.12|0.12|ns|
|MMCM_TOUTJITTER|MMCM output jitter|Note3|||||
|MMCM_TOUTDUTY|MMCM output clock duty cycle precision4|0.165|0.20|0.20|0.20|ns|
|MMCM_TLOCKMAX|MMCM maximum lock time for<br>MMCM_FPFDMIN|100|100|100|100|µs|
|MMCM_FOUTMAX|MMCM maximum output frequency|891|775|667|725|MHz|
|MMCM_FOUTMIN|MMCM minimum output frequency4,5|6.25|6.25|6.25|6.25|MHz|
|MMCM_TEXTFDVAR|External clock feedback variation|< 20% of clock input period or 1 ns Max|||||
|MMCM_RSTMINPULSE|Minimum reset pulse width|5.00|5.00|5.00|5.00|ns|
|MMCM_FPFDMAX|Maximum frequency at the phase<br>frequency detector|550|500|450|500|MHz|
|MMCM_FPFDMIN|Minimum frequency at the phase<br>frequency detector|10|10|10|10|MHz|
|MMCM_TFBDELAY|Maximum delay in the feedback path|5 ns Max or one clock cycle|||||
|MMCM_FDPRCLK_MAX|Maximum DRP clock frequency|250|250|250|250|MHz|
|**Notes:**<br>1.<br>The MMCM does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies.<br>2.<br>The static offset is measured between any MMCM outputs with identical phase.<br>3.<br>Values for this parameter are available in the Clocking Wizard.<br>4.<br>Includes global clock buffer.<br>5.<br>Calculated as FVCO/128 assuming output duty cycle is 50%.|||||||



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## **PLL Switching Characteristics** 

## _Table 34:_ **PLL Specification** 

|**PLL Switching Characteristics**|**PLL Switching Characteristics**|**PLL Switching Characteristics**|**PLL Switching Characteristics**|**PLL Switching Characteristics**|**PLL Switching Characteristics**|**PLL Switching Characteristics**|
|---|---|---|---|---|---|---|
|_Table 34:_**PLL Specification**|||||||
|**Symbol**|**Description**1|**Speed Grade and VCCINT Operating Voltages**||||**Units**|
|||**0.90V**|**0.85V**||**0.72V**||
|||**-3**|**-2**|**-1**|**-2**||
|PLL_FINMAX|Maximum input clock frequency|1066|933|800|933|MHz|
|PLL_FINMIN|Minimum input clock frequency|70|70|70|70|MHz|
|PLL_FINJITTER|Maximum input clock period jitter|< 20% of clock input period or 1 ns Max|||||
|PLL_FINDUTY|Input duty cycle range: 70–399 MHz|35–65||||%|
||Input duty cycle range: 400–499 MHz|40–60||||%|
||Input duty cycle range: >500 MHz|45–55||||%|
|PLL_FVCOMIN|Minimum PLL VCO frequency|750|750|750|750|MHz|
|PLL_FVCOMAX|Maximum PLL VCO frequency|1500|1500|1500|1500|MHz|
|PLL_TSTATPHAOFFSET|Static phase offset of the PLL outputs2|0.12|0.12|0.12|0.12|ns|
|PLL_TOUTJITTER|PLL output jitter|Note3|||||
|PLL_TOUTDUTY|PLL CLKOUT0, CLKOUT0B, CLKOUT1, CLKOUT1B<br>duty-cycle precision4|0.165|0.20|0.20|0.20|ns|
|PLL_TLOCKMAX|PLL maximum lock time|100||||µs|
|PLL_FOUTMAX|PLL maximum output frequency at CLKOUT0,<br>CLKOUT0B, CLKOUT1, CLKOUT1B|891|775|667|725|MHz|
||PLL maximum output frequency at CLKOUTPHY|2667|2667|2400|2400|MHz|
|PLL_FOUTMIN|PLL minimum output frequency at CLKOUT0,<br>CLKOUT0B, CLKOUT1, CLKOUT1B5|5.86|5.86|5.86|5.86|MHz|
||PLL minimum output frequency at CLKOUTPHY|2 x VCO mode: 1500, 1 x VCO mode: 750, 0.5 x VCO mode: 375||||MHz|
|PLL_RSTMINPULSE|Minimum reset pulse width|5.00|5.00|5.00|5.00|ns|
|PLL_FPFDMAX|Maximum frequency at the phase frequency<br>detector|667.5|667.5|667.5|667.5|MHz|
|PLL_FPFDMIN|Minimum frequency at the phase frequency<br>detector|70|70|70|70|MHz|
|PLL_FBANDWIDTH|PLL bandwidth at typical|14|14|14|14|MHz|
|PLL_FDPRCLK_MAX|Maximum DRP clock frequency|250|250|250|250|MHz|
|**Notes:**<br>1.<br>The PLL does not filter typical spread-spectrum input clocks because they are usually far below the loop filter frequencies.<br>2.<br>The static offset is measured between any PLL outputs with identical phase.<br>3.<br>Values for this parameter are available in the Clocking Wizard.<br>4.<br>Includes global clock buffer.<br>5.<br>Calculated as FVCO/128 assuming output duty cycle is 50%.|||||||



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Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## **Device Pin-to-Pin Output Parameter Guidelines** 

The pin-to-pin numbers in the following tables are based on the clock root placement in the center of the device. The actual pin-to-pin values will vary if the root placement selected is different. Consult the Vivado Design Suite timing report for the actual pin-to-pin values. 

## _Table 35:_ **Global Clock Input to Output Delay Without MMCM (Near Clock Region)** 

|The pin-to-pin numbers in the following tables are based on the clock root placement in the center of the<br>device. The actual pin-to-pin values will vary if the root placement selected is diferent. Consult the Vivado<br>Design Suite tming report for the actual pin-to-pin values.|The pin-to-pin numbers in the following tables are based on the clock root placement in the center of the<br>device. The actual pin-to-pin values will vary if the root placement selected is diferent. Consult the Vivado<br>Design Suite tming report for the actual pin-to-pin values.|The pin-to-pin numbers in the following tables are based on the clock root placement in the center of the<br>device. The actual pin-to-pin values will vary if the root placement selected is diferent. Consult the Vivado<br>Design Suite tming report for the actual pin-to-pin values.|The pin-to-pin numbers in the following tables are based on the clock root placement in the center of the<br>device. The actual pin-to-pin values will vary if the root placement selected is diferent. Consult the Vivado<br>Design Suite tming report for the actual pin-to-pin values.|The pin-to-pin numbers in the following tables are based on the clock root placement in the center of the<br>device. The actual pin-to-pin values will vary if the root placement selected is diferent. Consult the Vivado<br>Design Suite tming report for the actual pin-to-pin values.|The pin-to-pin numbers in the following tables are based on the clock root placement in the center of the<br>device. The actual pin-to-pin values will vary if the root placement selected is diferent. Consult the Vivado<br>Design Suite tming report for the actual pin-to-pin values.|The pin-to-pin numbers in the following tables are based on the clock root placement in the center of the<br>device. The actual pin-to-pin values will vary if the root placement selected is diferent. Consult the Vivado<br>Design Suite tming report for the actual pin-to-pin values.|The pin-to-pin numbers in the following tables are based on the clock root placement in the center of the<br>device. The actual pin-to-pin values will vary if the root placement selected is diferent. Consult the Vivado<br>Design Suite tming report for the actual pin-to-pin values.|
|---|---|---|---|---|---|---|---|
|_Table 35:_**Global Clock Input to Output Delay Without MMCM (Near Clock Region)**||||||||
|**Symbol**|**Description**1|**Device**|**Speed Grade and VCCINT Operating Voltages**||||**Units**|
||||**0.90V**|**0.85V**||**0.72V**||
||||**-3**|**-2**|**-1**|**-2**||
|SSTL15 Global Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate,_without_MMCM||||||||
|TICKOF|Global clock input and output flip-flop_without_<br>MMCM (near clock region)|XCVU3P|4.41|4.77|5.09|5.48|ns|
|||XCVU5P|4.41|4.77|5.09|5.48|ns|
|||XCVU7P|4.41|4.77|5.09|5.48|ns|
|||XCVU9P|4.41|4.77|5.09|5.48|ns|
|||XCVU11P|4.22|4.59|4.90|5.27|ns|
|||XCVU13P|4.22|4.59|4.90|5.27|ns|
|||XCVU27P|4.22|4.59|4.90|5.27|ns|
|||XCVU29P|4.22|4.59|4.90|5.27|ns|
|||XCVU31P|4.22|4.59|4.90|5.27|ns|
|||XCVU33P|4.22|4.59|4.90|5.27|ns|
|||XCVU35P|4.22|4.59|4.90|5.27|ns|
|||XCVU37P|4.22|4.59|4.90|5.27|ns|
|||XQVU3P|N/A|4.77|5.09|5.48|ns|
|||XQVU7P|N/A|4.77|5.09|5.48|ns|
|||XQVU11P|N/A|4.59|4.90|5.27|ns|
|**Notes:**<br>1.<br>This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all<br>accessible I/O and CLB flip-flops are clocked by the global clock net in a single SLR.||||||||



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Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## _Table 36:_ **Global Clock Input to Output Delay Without MMCM (Far Clock Region)** 

|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|---|---|
|_Table 36:_**Global Clock Input to Output Delay Without MMCM (Far Clock Region)**||||||||
|**Symbol**|**Description**1|**Device**|**Speed Grade and VCCINT Operating Voltages**||||**Units**|
||||**0.90V**|**0.85V**||**0.72V**||
||||**-3**|**-2**|**-1**|**-2**||
|SSTL15 Global Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate,_without_MMCM||||||||
|TICKOF_FAR|Global clock input and output flip-flop_without_<br>MMCM (far clock region)|XCVU3P|4.90|5.33|5.69|6.24|ns|
|||XCVU5P|4.90|5.33|5.69|6.24|ns|
|||XCVU7P|4.90|5.33|5.69|6.24|ns|
|||XCVU9P|4.90|5.33|5.69|6.24|ns|
|||XCVU11P|4.40|4.79|5.11|5.54|ns|
|||XCVU13P|4.40|4.79|5.11|5.54|ns|
|||XCVU27P|4.40|4.79|5.11|5.54|ns|
|||XCVU29P|4.40|4.79|5.11|5.54|ns|
|||XCVU31P|4.40|4.79|5.11|5.54|ns|
|||XCVU33P|4.40|4.79|5.11|5.54|ns|
|||XCVU35P|4.40|4.79|5.11|5.54|ns|
|||XCVU37P|4.40|4.79|5.11|5.54|ns|
|||XQVU3P|N/A|5.33|5.69|6.24|ns|
|||XQVU7P|N/A|5.33|5.69|6.24|ns|
|||XQVU11P|N/A|4.79|5.11|5.54|ns|
|**Notes:**<br>1.<br>This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all<br>accessible I/O and CLB flip-flops are clocked by the global clock net in a single SLR.||||||||



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Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## _Table 37:_ **Global Clock Input to Output Delay With MMCM** 

|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|---|---|
|_Table 37:_**Global Clock Input to Output Delay With MMCM**||||||||
|**Symbol**|**Description**1**,**2|**Device**|**Speed Grade and VCCINT Operating Voltages**||||**Units**|
||||**0.90V**|**0.85V**||**0.72V**||
||||**-3**|**-2**|**-1**|**-2**||
|SSTL15 Global Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate,_with_MMCM||||||||
|TICKOFMMCMCC|Global clock input and output flip-flop_with_<br>MMCM|XCVU3P|1.51|1.80|1.94|1.80|ns|
|||XCVU5P|1.51|1.80|1.94|1.80|ns|
|||XCVU7P|1.51|1.80|1.94|1.80|ns|
|||XCVU9P|1.51|1.80|1.94|1.80|ns|
|||XCVU11P|1.29|1.56|1.68|1.56|ns|
|||XCVU13P|1.29|1.56|1.68|1.56|ns|
|||XCVU27P|1.29|1.56|1.68|1.56|ns|
|||XCVU29P|1.29|1.56|1.68|1.56|ns|
|||XCVU31P|1.29|1.56|1.68|1.56|ns|
|||XCVU33P|1.29|1.56|1.68|1.56|ns|
|||XCVU35P|1.29|1.56|1.68|1.56|ns|
|||XCVU37P|1.29|1.56|1.68|1.56|ns|
|||XQVU3P|N/A|1.80|1.94|1.80|ns|
|||XQVU7P|N/A|1.80|1.94|1.80|ns|
|||XQVU11P|N/A|1.56|1.68|1.56|ns|
|**Notes:**<br>1.<br>This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all<br>accessible I/O and CLB flip-flops are clocked by the global clock net in a single SLR.<br>2.<br>MMCM output jitter is already included in the timing calculation.||||||||



## _Table 38:_ **Source Synchronous Output Characteristics (Component Mode)** 

|_Table 38:_**Source Synchronous Output Characteristics (Component Mode)**|_Table 38:_**Source Synchronous Output Characteristics (Component Mode)**|_Table 38:_**Source Synchronous Output Characteristics (Component Mode)**|_Table 38:_**Source Synchronous Output Characteristics (Component Mode)**|_Table 38:_**Source Synchronous Output Characteristics (Component Mode)**|_Table 38:_**Source Synchronous Output Characteristics (Component Mode)**|
|---|---|---|---|---|---|
|**Description**|**Speed Grade and VCCINT Operating Voltages**||||**Units**|
||**0.90V**|**0.85V**||**0.72V**||
||**-3**|**-2**|**-1**|**-2**||
|TOUTPUT_LOGIC_DELAY_VARIATION1|80||||ps|
|**Notes:**<br>1.<br>Delay mismatch across a transmit bus when using component mode output logic (ODDRE1, OSERDESE3) within a bank.||||||



## **Device Pin-to-Pin Input Parameter Guidelines** 

The pin-to-pin numbers in the following table are based on the clock root placement in the center of the device. The actual pin-to-pin values will vary if the root placement selected is different. Consult the Vivado Design Suite timing report for the actual pin-to-pin values. 

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Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## _Table 39:_ **Global Clock Input Setup and Hold With MMCM** 

|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|---|---|---|
|_Table 39:_**Global Clock Input Setup and Hold With MMCM**|||||||||
|**Symbol**|**Description**||**Device**|**Speed Grade and VCCINT Operating Voltages**||||**Units**|
|||||**0.90V**|**0.85V**||**0.72V**||
|||||**-3**|**-2**|**-1**|**-2**||
|Input Setup and Hold Time Relative to Global Clock||Input Signal using SSTL15 Standard.1,2,3|||||||
|TPSMMCMCC_VU3P|Global clock input and input<br>flip-flop (or latch) with MMCM|Setup|XCVU3P|1.86|1.86|1.99|1.86|ns|
|TPHMMCMCC_VU3P||Hold||–0.13|–0.13|–0.13|–0.17|ns|
|TPSMMCMCC_VU5P||Setup|XCVU5P|1.86|1.86|1.99|1.86|ns|
|TPHMMCMCC_VU5P||Hold||–0.13|–0.13|–0.13|–0.17|ns|
|TPSMMCMCC_VU7P||Setup|XCVU7P|1.86|1.86|1.99|1.86|ns|
|TPHMMCMCC_VU7P||Hold||–0.13|–0.13|–0.13|–0.17|ns|
|TPSMMCMCC_VU9P||Setup|XCVU9P|1.86|1.86|1.99|1.86|ns|
|TPHMMCMCC_VU9P||Hold||–0.13|–0.13|–0.13|–0.17|ns|
|TPSMMCMCC_VU11P||Setup|XCVU11P|1.91|1.92|2.05|1.92|ns|
|TPHMMCMCC_VU11P||Hold||–0.13|–0.13|–0.13|–0.18|ns|
|TPSMMCMCC_VU13P||Setup|XCVU13P|1.91|1.92|2.05|1.92|ns|
|TPHMMCMCC_VU13P||Hold||–0.13|–0.13|–0.13|–0.18|ns|
|TPSMMCMCC_VU31P||Setup|XCVU31P|1.91|1.92|2.05|1.92|ns|
|TPHMMCMCC_VU31P||Hold||–0.13|–0.13|–0.13|–0.18|ns|
|TPSMMCMCC_VU33P||Setup|XCVU33P|1.91|1.92|2.05|1.92|ns|
|TPHMMCMCC_VU33P||Hold||–0.13|–0.13|–0.13|–0.18|ns|
|TPSMMCMCC_VU35P||Setup|XCVU35P|1.91|1.92|2.05|1.92|ns|
|TPHMMCMCC_VU35P||Hold||–0.13|–0.13|–0.13|–0.18|ns|
|TPSMMCMCC_VU37P||Setup|XCVU37P|1.91|1.92|2.05|1.92|ns|
|TPHMMCMCC_VU37P||Hold||–0.13|–0.13|–0.13|–0.18|ns|
|TPSMMCMCC_VU27P||Setup|XCVU27P|1.91|1.92|2.05|1.92|ns|
|TPHMMCMCC_VU27P||Hold||–0.13|–0.13|–0.13|–0.18|ns|
|TPSMMCMCC_VU29P||Setup|XCVU29P|1.91|1.92|2.05|1.92|ns|
|TPHMMCMCC_VU29P||Hold||–0.13|–0.13|–0.13|–0.18|ns|
|**Notes:**<br>1.<br>Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the<br>global clock input signal using the slowest process, slowest temperature, and slowest voltage. Hold time is measured relative to the<br>global clock input signal using the fastest process, fastest temperature, and fastest voltage.<br>2.<br>This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all<br>accessible I/O and CLB flip-flops are clocked by the global clock net in a single SLR.<br>3.<br>Use IBIS to determine any duty-cycle distortion incurred using various standards.|||||||||



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Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## _Table 40:_ **Sampling Window** 

|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|
|_Table 40:_**Sampling Window**||||||
|**Description**|**Speed Grade and VCCINT Operating Voltages**||||**Units**|
||**0.90V**|**0.85V**||**0.72V**||
||**-3**|**-2**|**-1**|**-2**||
|TSAMP_BUFG1|510|610|610|610|ps|
|TSAMP_NATIVE_DPA2|100|100|125|125|ps|
|TSAMP_NATIVE_BISC3|60|60|85|85|ps|
|**Notes:**<br>1.<br>This parameter indicates the total sampling error of the Virtex UltraScale+ FPGA DDR input registers, measured across voltage,<br>temperature, and process. The characterization methodology uses the MMCM to capture the DDR input registers' edges of operation.<br>These measurements include: CLK0 MMCM jitter, MMCM accuracy (phase offset), and MMCM phase shift resolution. These<br>measurements do not include package or clock tree skew.<br>2.<br>This parameter is the receive sampling error for RX_BITSLICE when using dynamic phase alignment.<br>3.<br>This parameter is the receive sampling error for RX_BITSLICE when using built-in self-calibration (BISC).||||||



_Table 41:_ **Input Logic Characteristics for Dynamic Phase Aligned Applications (Component Mode)** 

|_Table 41:_**Input Logic Characteristics for Dynamic Phase Aligned Applications (Component Mode)**|_Table 41:_**Input Logic Characteristics for Dynamic Phase Aligned Applications (Component Mode)**|_Table 41:_**Input Logic Characteristics for Dynamic Phase Aligned Applications (Component Mode)**|_Table 41:_**Input Logic Characteristics for Dynamic Phase Aligned Applications (Component Mode)**|_Table 41:_**Input Logic Characteristics for Dynamic Phase Aligned Applications (Component Mode)**|_Table 41:_**Input Logic Characteristics for Dynamic Phase Aligned Applications (Component Mode)**|
|---|---|---|---|---|---|
|**Description**|**Speed Grade and VCCINT Operating Voltages**||||**Units**|
||**0.90V**|**0.85V**||**0.72V**||
||**-3**|**-2**|**-1**|**-2**||
|TINPUT_LOGIC_UNCERTAINTY1|40||||ps|
|TCAL_ERROR2|24||||ps|
|**Notes:**<br>1.<br>Input_logic_uncertainty accounts for the setup/hold and any pattern dependent jitter for the input logic (input register, IDDRE1, or<br>ISERDESE3).<br>2.<br>Calibration error associated with quantization effects based on the IDELAY resolution. Calibration must be performed for each input pin<br>to ensure optimal performance.||||||



## **Package Parameter Guidelines** 

The parameters in this section provide the necessary values for calculating timing budgets for clock transmitter and receiver data-valid windows. 

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Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## _Table 42:_ **Package Skew** 

|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|
|_Table 42:_**Package Skew**||||||
|**Symbol**|**Description**|**Device**|**Package**|**Value**|**Units**|
|PKGSKEW|Package Skew1,2|XCVU3P|FFVC1517|197|ps|
|||XCVU5P|FLVA2104|175|ps|
||||FLVB2104|225|ps|
||||FLVC2104|216|ps|
|||XCVU7P|FLVA2104|175|ps|
||||FLVB2104|225|ps|
||||FLVC2104|216|ps|
|||XCVU9P|FLGA2104|217|ps|
||||FLGB2104|275|ps|
||||FLGC2104|299|ps|
||||FSGD2104|229|ps|
||||FLGA2577|149|ps|
|||XCVU11P|FLGF1924|180|ps|
||||FLGB2104|216|ps|
||||FLGC2104|175|ps|
||||FSGD2104|224|ps|
||||FLGA2577|154|ps|
|||XCVU13P|FHGA2104|215|ps|
||||FHGB2104|259|ps|
||||FHGC2104|182|ps|
||||FIGD2104|198|ps|
||||FLGA2577|140|ps|
|||XCVU27P|FIGD2104|198|ps|
||||FSGA2577|139|ps|
|||XCVU29P|FIGD2104|198|ps|
||||FSGA2577|139|ps|
|||XCVU31P|FSVH1924|165|ps|
|||XCVU33P|FSVH2104|194|ps|
|||XCVU35P|FSVH2104|200|ps|
||||FSVH2892|241|ps|
|||XCVU37P|FSVH2892|278|ps|
|||XQVU3P|FFRC1517|176|ps|
|||XQVU7P|FLRA2104|175|ps|
||||FLRA2104|224|ps|
|||XQVU11P|FLRC2104|174|ps|
|**Notes:**<br>1.<br>These values represent the worst-case skew between any two SelectIO resources in the package: shortest delay to longest delay from die<br>pad to ball.<br>2.<br>Package delay information is available for these device/package combinations. This information can be used to deskew the package.||||||



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Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## **GTY Transceiver Specifications** 

The _UltraScale Architecture and Product Data Sheet: Overview_ (DS890) lists the Virtex UltraScale+ FPGAs that include the GTY transceivers. 

## **GTY Transceiver DC Input and Output Levels** 

Table 43 summarizes the DC specifications of the GTY transceivers in Virtex UltraScale+ FPGAs. Consult the _UltraScale Architecture GTY Transceivers User Guide_ (UG578) for further details. 

**GTY Transceiver DC Specifications** 

_Table 43:_ 

|Table 43 summarizes the DC specifications of the GTY transceivers in Virtex UltraScale+ FPGAs. Consult thesummarizes the DC specifications of the GTY transceivers in Virtex UltraScale+ FPGAs. Consult the<br>_UltraScale Architecture GTY Transceivers User Guide_(UG578) for further details.UG578) for further details.) for further details.|Table 43 summarizes the DC specifications of the GTY transceivers in Virtex UltraScale+ FPGAs. Consult thesummarizes the DC specifications of the GTY transceivers in Virtex UltraScale+ FPGAs. Consult the<br>_UltraScale Architecture GTY Transceivers User Guide_(UG578) for further details.UG578) for further details.) for further details.|Table 43 summarizes the DC specifications of the GTY transceivers in Virtex UltraScale+ FPGAs. Consult thesummarizes the DC specifications of the GTY transceivers in Virtex UltraScale+ FPGAs. Consult the<br>_UltraScale Architecture GTY Transceivers User Guide_(UG578) for further details.UG578) for further details.) for further details.|Table 43 summarizes the DC specifications of the GTY transceivers in Virtex UltraScale+ FPGAs. Consult thesummarizes the DC specifications of the GTY transceivers in Virtex UltraScale+ FPGAs. Consult the<br>_UltraScale Architecture GTY Transceivers User Guide_(UG578) for further details.UG578) for further details.) for further details.|Table 43 summarizes the DC specifications of the GTY transceivers in Virtex UltraScale+ FPGAs. Consult thesummarizes the DC specifications of the GTY transceivers in Virtex UltraScale+ FPGAs. Consult the<br>_UltraScale Architecture GTY Transceivers User Guide_(UG578) for further details.UG578) for further details.) for further details.|Table 43 summarizes the DC specifications of the GTY transceivers in Virtex UltraScale+ FPGAs. Consult thesummarizes the DC specifications of the GTY transceivers in Virtex UltraScale+ FPGAs. Consult the<br>_UltraScale Architecture GTY Transceivers User Guide_(UG578) for further details.UG578) for further details.) for further details.|Table 43 summarizes the DC specifications of the GTY transceivers in Virtex UltraScale+ FPGAs. Consult thesummarizes the DC specifications of the GTY transceivers in Virtex UltraScale+ FPGAs. Consult the<br>_UltraScale Architecture GTY Transceivers User Guide_(UG578) for further details.UG578) for further details.) for further details.|
|---|---|---|---|---|---|---|
|_Table 43:_**GTY Transceiver DC Specifications**|||||||
|**Symbol**<br>~~a CO~~|**DC Parameter**<br>~~CO~~|**Conditions**<br>~~CO~~|**Min**<br>~~CO~~|**Typ**<br>~~CO~~|**Max**<br>~~CO~~|**Units**<br>~~CO~~|
|DVPPIN<br>~~A~~|Differential peak-to-peak input voltage<br>(external AC coupled)<br>~~A~~|>10.3125 Gb/s<br>~~es~~|150<br>~~es~~<br>es|–<br>~~es~~|1250<br>~~es~~|mV<br>~~es~~|
|||6.6 Gb/s to 10.3125 Gb/s<br>~~es~~|150<br>~~es~~<br>es|–<br>~~es~~|1250<br>~~es~~|mV<br>~~es~~|
|||≤ 6.6 Gb/s<br>~~A~~|150<br>es<br>~~A~~|–<br>~~A~~|2000<br>~~A~~|mV<br>~~A~~|
|VIN<br>~~A~~|Single-ended input voltage. Voltage<br>measured at the pin referenced to<br>GND.<br>~~A~~|DC coupled VMGTAVTT= 1.2V<br>~~A~~|–400<br>~~A~~|–<br>~~A~~|VMGTAVTT<br>~~A~~|mV<br>~~A~~|
|VCMIN|Common mode input voltage|DC coupled VMGTAVTT= 1.2V|–|2/3 VMGTAVTT|–|mV|
|DVPPOUT<br>~~a~~|Differential peak-to-peak output<br>voltage1<br>~~a~~|Transmitter output swing is set<br>to11111<br>~~a~~|800<br>~~a~~|–<br>~~a~~|–<br>~~a~~|mV<br>~~a~~|
|VCMOUTDC|Common mode output voltage: DC<br>coupled (equation based)|When remote RX is terminated to<br>GND|VMGTAVTT/2 – DVPPOUT/4|||mV|
|||When remote RX termination is<br>floating|VMGTAVTT– DVPPOUT/2|||mV|
|||When remote RX is terminated to<br>VRX_TERM2||||mV|
|VCMOUTAC|Common mode output voltage: AC<br>coupled|Equation based|VMGTAVTT– DVPPOUT/2|||mV|
|RIN<br>~~a~~|Differential input resistance<br>~~a~~||–<br>~~a~~|100<br>~~a~~|–<br>~~a~~|Ω<br>~~a~~|
|ROUT<br>~~a~~|Differential output resistance<br>~~a~~<br>~~CO~~||–<br>~~a~~<br>~~CO~~|100<br>~~a~~<br>~~CO~~|–<br>~~a~~<br>~~CO~~|Ω<br>~~a~~<br>~~CO~~|
|TOSKEW<br>a|Transmitter output pair (TXP and TXN) intra-pair skew<br> ~~GO~~||–<br>~~GO~~|–<br>~~GO~~|10<br>~~GO~~|ps<br>~~GO~~|
|CEXT<br>a|Recommended external AC coupling capacitor3||–|100|–|nF|
|**Notes:**<br>1.<br>The output swing and pre-emphasis levels are programmable using the GTY transceiver attributes discussed in the_UltraScale Architecture_<br>_GTY Transceivers User Guide_(UG578) and can result in values lower than reported in this table.<br>2.<br>VRX_TERMis the remote RX termination voltage.<br>3.<br>Other values can be used as appropriate to conform to specific protocols and standards.|||||||



## **Notes:** 

1. The output swing and pre-emphasis levels are programmable using the GTY transceiver attributes discussed in the _UltraScale Architecture GTY Transceivers User Guide_ (UG578) and can result in values lower than reported in this table. 

2. VRX_TERM is the remote RX termination voltage. 

3. Other values can be used as appropriate to conform to specific protocols and standards. 

## _Figure 3:_ **Single-Ended Peak-to-Peak Voltage** 

**==> picture [487 x 56] intentionally omitted <==**

**----- Start of picture text -----**<br>
+V P<br>Single-Ended<br>Peak-to-Peak<br>N Voltage<br>0<br>**----- End of picture text -----**<br>


**==> picture [36 x 4] intentionally omitted <==**

**----- Start of picture text -----**<br>
X16653-072117<br>**----- End of picture text -----**<br>


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_Figure 4:_ **Differential Peak-to-Peak Voltage** 

**==> picture [389 x 89] intentionally omitted <==**

**----- Start of picture text -----**<br>
+V<br>Differential<br>0 Peak-to-Peak<br>Voltage<br>–V P–N<br>Differential peak-to-peak voltage = (Single-ended peak-to-peak voltage) x 2<br>X16639-072117<br>**----- End of picture text -----**<br>


The following tables summarize the DC specifications of the clock input/output levels of the GTY transceivers in Virtex UltraScale+ FPGAs. Consult the _UltraScale Architecture GTY Transceivers User Guide_ (UG578) for further details. 

_Table 44:_ **GTY Transceiver Clock DC Input Level Specification** 

|The following tables summarize the DC specifcatons of the clock input/output levels of the GTY transceivers in<br>Virtex UltraScale+ FPGAs. Consult the_UltraScale Architecture GTY Transceivers User Guide_(UG578) for further<br>details.|The following tables summarize the DC specifcatons of the clock input/output levels of the GTY transceivers in<br>Virtex UltraScale+ FPGAs. Consult the_UltraScale Architecture GTY Transceivers User Guide_(UG578) for further<br>details.|The following tables summarize the DC specifcatons of the clock input/output levels of the GTY transceivers in<br>Virtex UltraScale+ FPGAs. Consult the_UltraScale Architecture GTY Transceivers User Guide_(UG578) for further<br>details.|The following tables summarize the DC specifcatons of the clock input/output levels of the GTY transceivers in<br>Virtex UltraScale+ FPGAs. Consult the_UltraScale Architecture GTY Transceivers User Guide_(UG578) for further<br>details.|The following tables summarize the DC specifcatons of the clock input/output levels of the GTY transceivers in<br>Virtex UltraScale+ FPGAs. Consult the_UltraScale Architecture GTY Transceivers User Guide_(UG578) for further<br>details.|The following tables summarize the DC specifcatons of the clock input/output levels of the GTY transceivers in<br>Virtex UltraScale+ FPGAs. Consult the_UltraScale Architecture GTY Transceivers User Guide_(UG578) for further<br>details.|
|---|---|---|---|---|---|
|_Table 44:_**GTY Transceiver Clock DC Input Level Specification**||||||
|**Symbol**|**DC Parameter**|**Min**|**Typ**|**Max**|**Units**|
|VIDIFF|Differential peak-to-peak input voltage|250|–|2000|mV|
|RIN|Differential input resistance|–|100|–|Ω|
|CEXT|Required external AC coupling capacitor|–|10|–|nF|



_Table 45:_ **GTY Transceiver Clock Output Level Specification** 

|_Table 45:_**GTY Transceiver Clock Output Level Specification**|_Table 45:_**GTY Transceiver Clock Output Level Specification**|_Table 45:_**GTY Transceiver Clock Output Level Specification**|_Table 45:_**GTY Transceiver Clock Output Level Specification**|_Table 45:_**GTY Transceiver Clock Output Level Specification**|_Table 45:_**GTY Transceiver Clock Output Level Specification**|_Table 45:_**GTY Transceiver Clock Output Level Specification**|
|---|---|---|---|---|---|---|
|**Symbol**|**Description**|**Conditions**|**Min**|**Typ**|**Max**|**Units**|
|VOL|Output Low voltage for P and N|RT= 100Ω across P and N signals|100|–|330|mV|
|VOH|Output High voltage for P and N|RT= 100Ω across P and N signals|500|–|700|mV|
|VDDOUT|Differential output voltage (P–N), P  =<br>High (N–P), N = High|RT= 100Ω across P and N signals|300|–|430|mV|
|VCMOUT|Common mode voltage|RT= 100Ω across P and N signals|300|–|500|mV|



## **GTY Transceiver Switching Characteristics** 

Consult the _UltraScale Architecture GTY Transceivers User Guide_ (UG578) for further information. 

## _Table 46:_ **GTY Transceiver Performance** 

|_Table 46:_**GTY Transceiver Performance**|_Table 46:_**GTY Transceiver Performance**|_Table 46:_**GTY Transceiver Performance**|_Table 46:_**GTY Transceiver Performance**|_Table 46:_**GTY Transceiver Performance**|_Table 46:_**GTY Transceiver Performance**|_Table 46:_**GTY Transceiver Performance**|_Table 46:_**GTY Transceiver Performance**|
|---|---|---|---|---|---|---|---|
|**Symbol**|**Description**|**Output**<br>**Divider**|**Speed Grade and VCCINT Operating Voltages**||||**Units**|
||||**0.90V**|**0.85V**||**0.72V**||
||||**-3**|**-2**|**-1**|**-2**||
|FGTYMAX|GTY maximum line rate||32.751|28.211|25.7851|28.211|Gb/s|
|FGTYMIN|GTY minimum line rate||0.5|0.5|0.5|0.5|Gb/s|



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Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## _Table 46:_ **GTY Transceiver Performance** _(cont'd)_ 

|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|---|---|---|---|---|---|
|_Table 46:_**GTY Transceiver Performance**_(cont'd)_||||||||||||
|**Symbol**|**Description**|**Output**<br>**Divider**|**Speed Grade and VCCINT Operating Voltages**||||||||**Units**|
||||**0.90V**||**0.85V**||||**0.72V**|||
||||**-3**||**-2**||**-1**||**-2**|||
||||Min|Max|Min|Max|Min|Max|Min|Max||
|FGTYCRANGE|CPLL line rate<br>range2|1|4.0|12.5|4.0|12.5|4.0|8.5|4.0|12.5|Gb/s|
|||2|2.0|6.25|2.0|6.25|2.0|4.25|2.0|6.25|Gb/s|
|||4|1.0|3.125|1.0|3.125|1.0|2.125|1.0|3.125|Gb/s|
|||8|0.5|1.5625|0.5|1.5625|0.5|1.0625|0.5|1.5625|Gb/s|
|||16|N/A||||||||Gb/s|
|||32|N/A||||||||Gb/s|
||||Min|Max|Min|Max|Min|Max|Min|Max||
|FGTYQRANGE1|QPLL0 line rate<br>range3|1|19.6|32.75|19.6|28.21|19.6|25.785|19.6|28.21|Gb/s|
|||1|9.8|16.375|9.8|16.375|9.8|12.5|9.8|16.375|Gb/s|
|||2|4.9|8.1875|4.9|8.1875|4.9|8.1875|4.9|8.1875|Gb/s|
|||4|2.45|4.0938|2.45|4.0938|2.45|4.0938|2.45|4.0938|Gb/s|
|||8|1.225|2.0469|1.225|2.0469|1.225|2.0469|1.225|2.0469|Gb/s|
|||16|0.6125|1.0234|0.6125|1.0234|0.6125|1.0234|0.6125|1.0234|Gb/s|
||||Min|Max|Min|Max|Min|Max|Min|Max||
|FGTYQRANGE2|QPLL1 line rate<br>range4|1|16.0|26.0|16.0|26.0|16.0|25.785|16.0|26.0|Gb/s|
|||1|8.0|13.0|8.0|13.0|8.0|12.5|8.0|13.0|Gb/s|
|||2|4.0|6.5|4.0|6.5|4.0|6.5|4.0|6.5|Gb/s|
|||4|2.0|3.25|2.0|3.25|2.0|3.25|2.0|3.25|Gb/s|
|||8|1.0|1.625|1.0|1.625|1.0|1.625|1.0|1.625|Gb/s|
|||16|0.5|0.8125|0.5|0.8125|0.5|0.8125|0.5|0.8125|Gb/s|
||||Min|Max|Min|Max|Min|Max|Min|Max||
|FCPLLRANGE|CPLL frequency range||2.0|6.25|2.0|6.25|2.0|4.25|2.0|6.25|GHz|
|FQPLL0RANGE|QPLL0 frequency range||9.8|16.375|9.8|16.375|9.8|16.375|9.8|16.375|GHz|
|FQPLL1RANGE|QPLL1 frequency range||8.0|13.0|8.0|13.0|8.0|13.0|8.0|13.0|GHz|
|**Notes:**<br>1.<br>XCVU11P devices in the FLGF1924 package have a maximum GTY transceiver line rate of 16.3 Gb/s.<br>2.<br>The values listed are the rounded results of the calculated equation (2 × CPLL_Frequency)/Output_Divider.<br>3.<br>The values listed are the rounded results of the calculated equation (2 × QPLL0_Frequency)/Output_Divider.<br>4.<br>The values listed are the rounded results of the calculated equation (2 × QPLL1_Frequency)/Output_Divider.||||||||||||



_Table 47:_ **GTY Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics** 

|**Symbol**|**Description**|**All Speed Grades**|**Units**||
|---|---|---|---|---|
|FGTYDRPCLK|GTYDRPCLK maximum frequency|250|MHz||



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## _Table 48:_ **GTY Transceiver Reference Clock Switching Characteristics** 

|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|---|
|_Table 48:_**GTY Transceiver Reference Clock Switching Characteristics**|||||||
|**Symbol**|**Description**|**Conditions**|**All Speed Grades**|||**Units**|
||||**Min**|**Typ**|**Max**||
|FGCLK|Reference clock frequency range||60|–|820|MHz|
|TRCLK|Reference clock rise time|20% – 80%|–|200|–|ps|
|TFCLK|Reference clock fall time|80% – 20%|–|200|–|ps|
|TDCREF|Reference clock duty cycle|Transceiver PLL only|40|50|60|%|



## _Table 49:_ **GTY Transceiver Reference Clock Oscillator Selection Phase Noise Mask** 

|_Table 49:_**GTY Transceiver Reference Clock Oscillator Selection Phase Noise Mask**|_Table 49:_**GTY Transceiver Reference Clock Oscillator Selection Phase Noise Mask**|_Table 49:_**GTY Transceiver Reference Clock Oscillator Selection Phase Noise Mask**|_Table 49:_**GTY Transceiver Reference Clock Oscillator Selection Phase Noise Mask**|_Table 49:_**GTY Transceiver Reference Clock Oscillator Selection Phase Noise Mask**|_Table 49:_**GTY Transceiver Reference Clock Oscillator Selection Phase Noise Mask**|_Table 49:_**GTY Transceiver Reference Clock Oscillator Selection Phase Noise Mask**|
|---|---|---|---|---|---|---|
|**Symbol**|**Description**1**,**2|**Offset**<br>**Frequency**|**Min**|**Typ**|**Max**|**Units**|
|QPLLREFCLKMASK|QPLL0/QPLL1 reference clock select phase noise<br>mask at REFCLK frequency = 156.25 MHz|10 kHz|–|–|–112|dBc/Hz|
|||100 kHz|–|–|–128||
|||1 MHz|–|–|–145||
||QPLL0/QPLL1 reference clock select phase noise<br>mask at REFCLK frequency = 312.5 MHz|10 kHz|–|–|–103|dBc/Hz|
|||100 kHz|–|–|–123||
|||1 MHz|–|–|–143||
||QPLL0/QPLL1 reference clock select phase noise<br>mask at REFCLK frequency = 625 MHz|10 kHz|–|–|–98|dBc/Hz|
|||100 kHz|–|–|–117||
|||1 MHz|–|–|–140||
|CPLLREFCLKMASK|CPLL reference clock select phase noise mask at<br>REFCLK frequency = 156.25 MHz|10 kHz|–|–|–112|dBc/Hz|
|||100 kHz|–|–|–128||
|||1 MHz|–|–|–145||
|||50 MHz|–|–|–145||
||CPLL reference clock select phase noise mask at<br>REFCLK frequency = 312.5 MHz|10 kHz|–|–|–103|dBc/Hz|
|||100 kHz|–|–|–123||
|||1 MHz|–|–|–143||
|||50 MHz|–|–|–145||
||CPLL reference clock select phase noise mask at<br>REFCLK frequency = 625 MHz|10 kHz|–|–|–98|dBc/Hz|
|||100 kHz|–|–|–117||
|||1 MHz|–|–|–140||
|||50 MHz|–|–|–144||
|**Notes:**<br>1.<br>For reference clock frequencies not in this table, use the phase-noise mask for the nearest reference clock frequency.<br>2.<br>This reference clock phase-noise mask is superseded by any reference clock phase-noise mask that is specified in a supported protocol,<br>e.g., PCIe.|||||||



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## _Table 50:_ **GTY Transceiver PLL/Lock Time Adaptation** 

|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|---|
|_Table 50:_**GTY Transceiver PLL/Lock Time Adaptation**|||||||
|**Symbol**|**Description**|**Conditions**|**All Speed Grades**|||**Units**|
||||**Min**|**Typ**|**Max**||
|TLOCK|Initial PLL lock.||–|–|1|ms|
|TDLOCK|Clock recovery phase acquisition and<br>adaptation time for decision feedback<br>equalizer (DFE)|After the PLL is locked to the<br>reference clock, this is the<br>time it takes to lock the clock<br>data recovery (CDR) to the<br>data present at the input.|–|50,000|37 x 106|UI|
||Clock recovery phase acquisition and<br>adaptation time for low-power mode (LPM)<br>when the DFE is disabled||–|50,000|2.3 x 106|UI|



## _Table 51:_ **GTY Transceiver User Clock Switching Characteristics** 

|_Table 51:_**GTY Transceiver User Clock Switching Characteristics**|_Table 51:_**GTY Transceiver User Clock Switching Characteristics**|_Table 51:_**GTY Transceiver User Clock Switching Characteristics**|_Table 51:_**GTY Transceiver User Clock Switching Characteristics**|_Table 51:_**GTY Transceiver User Clock Switching Characteristics**|_Table 51:_**GTY Transceiver User Clock Switching Characteristics**|_Table 51:_**GTY Transceiver User Clock Switching Characteristics**|_Table 51:_**GTY Transceiver User Clock Switching Characteristics**|_Table 51:_**GTY Transceiver User Clock Switching Characteristics**|
|---|---|---|---|---|---|---|---|---|
|**Symbol**|**Description**1|**Data Width Conditions (Bit)**||**Speed Grade and VCCINT Operating Voltages**||||**Units**|
|||||**0.90V**|**0.85V**||**0.72V**||
|||**Internal**<br>**Logic**|**Interconnect**<br>**Logic**|**-3**|**-2**|**-1**2|**-2**||
|FTXOUTPMA|TXOUTCLK maximum frequency sourced from OUTCLKPMA|||511.719|511.719|402.891|402.832|MHz|
|FRXOUTPMA|RXOUTCLK maximum frequency sourced from OUTCLKPMA|||511.719|511.719|402.891|402.832|MHz|
|FTXOUTPROGDIV|TXOUTCLK maximum frequency sourced from<br>TXPROGDIVCLK|||511.719|511.719|511.719|511.719|MHz|
|FRXOUTPROGDIV|RXOUTCLK maximum frequency sourced from<br>RXPROGDIVCLK|||511.719|511.719|511.719|511.719|MHz|
|FTXIN|TXUSRCLK3maximum<br>frequency|16|16, 32|511.719|511.719|390.625|390.625|MHz|
|||32|32, 64|511.719|511.719|390.625|390.625|MHz|
|||64|64, 128|511.719|440.781|402.891|402.832|MHz|
|||20|20, 40|409.375|409.375|312.500|312.500|MHz|
|||40|40, 80|409.375|409.375|312.500|350.000|MHz|
|||80|80, 160|409.375|352.625|322.313|352.625|MHz|
|FRXIN|RXUSRCLK3maximum<br>frequency|16|16, 32|511.719|511.719|390.625|390.625|MHz|
|||32|32, 64|511.719|511.719|390.625|390.625|MHz|
|||64|64, 128|511.719|440.781|402.891|402.832|MHz|
|||20|20, 40|409.375|409.375|312.500|312.500|MHz|
|||40|40, 80|409.375|409.375|312.500|350.000|MHz|
|||80|80, 160|409.375|352.625|322.313|352.625|MHz|



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_Table 51:_ **GTY Transceiver User Clock Switching Characteristics** _(cont'd)_ 

|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|---|---|---|
|_Table 51:_**GTY Transceiver User Clock Switching Characteristics**_(cont'd)_|||||||||
|**Symbol**|**Description**1|**Data Width Conditions (Bit)**||**Speed Grade and VCCINT Operating Voltages**||||**Units**|
|||||**0.90V**|**0.85V**||**0.72V**||
|||**Internal**<br>**Logic**|**Interconnect**<br>**Logic**|**-3**|**-2**|**-1**2|**-2**||
|FTXIN2|TXUSRCLK23maximum<br>frequency|16|16|511.719|511.719|390.625|390.625|MHz|
|||16|32|255.859|255.859|195.313|195.313|MHz|
|||32|32|511.719|511.719|390.625|390.625|MHz|
|||32|64|255.859|255.859|195.313|195.313|MHz|
|||64|64|511.719|440.781|402.891|402.832|MHz|
|||64|128|255.859|220.391|201.445|201.416|MHz|
|||20|20|409.375|409.375|312.500|312.500|MHz|
|||20|40|204.688|204.688|156.250|156.250|MHz|
|||40|40|409.375|409.375|312.500|350.000|MHz|
|||40|80|204.688|204.688|156.250|175.000|MHz|
|||80|80|409.375|352.625|322.313|352.625|MHz|
|||80|160|204.688|176.313|161.156|176.313|MHz|
|FRXIN2|RXUSRCLK23maximum<br>frequency|16|16|511.719|511.719|390.625|390.625|MHz|
|||16|32|255.859|255.859|195.313|195.313|MHz|
|||32|32|511.719|511.719|390.625|390.625|MHz|
|||32|64|255.859|255.859|195.313|195.313|MHz|
|||64|64|511.719|440.781|402.891|402.832|MHz|
|||64|128|255.859|220.391|201.445|201.416|MHz|
|||20|20|409.375|409.375|312.500|312.500|MHz|
|||20|40|204.688|204.688|156.250|156.250|MHz|
|||40|40|409.375|409.375|312.500|350.000|MHz|
|||40|80|204.688|204.688|156.250|175.000|MHz|
|||80|80|409.375|352.625|322.313|352.625|MHz|
|||80|160|204.688|176.313|161.156|176.313|MHz|
|**Notes:**<br>1.<br>Clocking must be implemented as described in the_UltraScale Architecture GTY Transceivers User Guide_(UG578).<br>2.<br>For the speed grades -1E, -1I, and -1M, only a 64- or 80-bit internal data path can be used for line rates above 12.5 Gb/s.<br>3.<br>When the gearbox is used, these maximums refer to the XCLK. For more information, see the Valid Data Width Combinations for TX<br>Asynchronous Gearbox table in the_UltraScale Architecture GTY Transceivers User Guide_(UG578).|||||||||



## _Table 52:_ **GTY Transceiver Transmitter Switching Characteristics** 

|_Table 52:_**GTY Transceiver Transmitter Switching Characteristics**|_Table 52:_**GTY Transceiver Transmitter Switching Characteristics**|_Table 52:_**GTY Transceiver Transmitter Switching Characteristics**|_Table 52:_**GTY Transceiver Transmitter Switching Characteristics**|_Table 52:_**GTY Transceiver Transmitter Switching Characteristics**|_Table 52:_**GTY Transceiver Transmitter Switching Characteristics**|_Table 52:_**GTY Transceiver Transmitter Switching Characteristics**|
|---|---|---|---|---|---|---|
|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Units**|
|FGTYTX|Serial data rate range||0.500|–|FGTYMAX|Gb/s|
|TRTX|TX rise time|20%–80%|–|21|–|ps|
|TFTX|TX fall time|80%–20%|–|21|–|ps|
|TLLSKEW|TX lane-to-lane skew1||–|–|500.00|ps|
|TJ32.75|Total jitter2,4|32.75 Gb/s|–|–|0.35|UI|
|DJ32.75|Deterministic jitter2,4||–|–|0.19|UI|



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## _Table 52:_ **GTY Transceiver Transmitter Switching Characteristics** _(cont'd)_ 

|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|---|
|_Table 52:_**GTY Transceiver Transmitter Switching Characteristics**_(cont'd)_|||||||
|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Units**|
|TJ28.21|Total jitter2,4|28.21 Gb/s|–|–|0.28|UI|
|DJ28.21|Deterministic jitter2,4||–|–|0.17|UI|
|TJ16.375|Total jitter2,4|16.375 Gb/s|–|–|0.28|UI|
|DJ16.375|Deterministic jitter2,4||–|–|0.17|UI|
|TJ15.0|Total jitter2,4|15.0 Gb/s|–|–|0.28|UI|
|DJ15.0|Deterministic jitter2,4||–|–|0.17|UI|
|TJ14.1|Total jitter2,4|14.1 Gb/s|–|–|0.28|UI|
|DJ14.1|Deterministic jitter2,4||–|–|0.17|UI|
|TJ14.1|Total jitter2,4|14.025 Gb/s|–|–|0.28|UI|
|DJ14.1|Deterministic jitter2,4||–|–|0.17|UI|
|TJ13.1|Total jitter2,4|13.1 Gb/s|–|–|0.28|UI|
|DJ13.1|Deterministic jitter2,4||–|–|0.17|UI|
|TJ12.5_QPLL|Total jitter2,4|12.5 Gb/s|–|–|0.28|UI|
|DJ12.5_QPLL|Deterministic jitter2,4||–|–|0.17|UI|
|TJ12.5_CPLL|Total jitter3,4|12.5 Gb/s|–|–|0.33|UI|
|DJ12.5_CPLL|Deterministic jitter3,4||–|–|0.17|UI|
|TJ11.3_QPLL|Total jitter2,4|11.3 Gb/s|–|–|0.28|UI|
|DJ11.3_QPLL|Deterministic jitter2,4||–|–|0.17|UI|
|TJ10.3125_QPLL|Total jitter2,4|10.3125 Gb/s|–|–|0.28|UI|
|DJ10.3125_QPLL|Deterministic jitter2,4||–|–|0.17|UI|
|TJ10.3125_CPLL|Total jitter3,4|10.3125 Gb/s|–|–|0.33|UI|
|DJ10.3125_CPLL|Deterministic jitter3,4||–|–|0.17|UI|
|TJ9.953_QPLL|Total jitter2,4|9.953 Gb/s|–|–|0.28|UI|
|DJ9.953_QPLL|Deterministic jitter2,4||–|–|0.17|UI|
|TJ9.953_CPLL|Total jitter3,4|9.953 Gb/s|–|–|0.33|UI|
|DJ9.953_CPLL|Deterministic jitter3,4||–|–|0.17|UI|
|TJ8.0|Total jitter3,4|8.0 Gb/s|–|–|0.32|UI|
|DJ8.0|Deterministic jitter3,4||–|–|0.17|UI|
|TJ6.6|Total jitter3,4|6.6 Gb/s|–|–|0.30|UI|
|DJ6.6|Deterministic jitter3,4||–|–|0.15|UI|
|TJ5.0|Total jitter3,4|5.0 Gb/s|–|–|0.30|UI|
|DJ5.0|Deterministic jitter3,4||–|–|0.15|UI|
|TJ4.25|Total jitter3,4|4.25 Gb/s|–|–|0.30|UI|
|DJ4.25|Deterministic jitter3,4||–|–|0.15|UI|
|TJ3.20|Total jitter3,4|3.20 Gb/s5|–|–|0.20|UI|
|DJ3.20|Deterministic jitter3,4||–|–|0.10|UI|
|TJ2.5|Total jitter3,4|2.5 Gb/s6|–|–|0.20|UI|
|DJ2.5|Deterministic jitter3,4||–|–|0.10|UI|
|TJ1.25|Total jitter3,4|1.25 Gb/s7|–|–|0.15|UI|
|DJ1.25|Deterministic jitter3,4||–|–|0.06|UI|



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Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

_Table 52:_ **GTY Transceiver Transmitter Switching Characteristics** _(cont'd)_ 

|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|---|
|_Table 52:_**GTY Transceiver Transmitter Switching Characteristics**_(cont'd)_|||||||
|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Units**|
|TJ500|Total jitter3,4|500 Mb/s8|–|–|0.10|UI|
|DJ500|Deterministic jitter3,4||–|–|0.03|UI|
|**Notes:**<br>1.<br>Using same REFCLK input with TX phase alignment enabled for up to four consecutive transmitters (one fully populated GTY Quad) at<br>maximum line rate.<br>2.<br>Using QPLL_FBDIV = 40, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations.<br>3.<br>Using CPLL_FBDIV = 2, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations.<br>4.<br>All jitter values are based on a bit-error ratio of 10–12.<br>5.<br>CPLL frequency at 3.2 GHz and TXOUT_DIV = 2.<br>6.<br>CPLL frequency at 2.5 GHz and TXOUT_DIV = 2.<br>7.<br>CPLL frequency at 2.5 GHz and TXOUT_DIV = 4.<br>8.<br>CPLL frequency at 2.0 GHz and TXOUT_DIV = 8.|||||||



_Table 53:_ **GTY Transceiver Receiver Switching Characteristics** 

|_Table 53:_**GTY Transceiver Receiver Switching Characteristics**|_Table 53:_**GTY Transceiver Receiver Switching Characteristics**|_Table 53:_**GTY Transceiver Receiver Switching Characteristics**|_Table 53:_**GTY Transceiver Receiver Switching Characteristics**|_Table 53:_**GTY Transceiver Receiver Switching Characteristics**|_Table 53:_**GTY Transceiver Receiver Switching Characteristics**|_Table 53:_**GTY Transceiver Receiver Switching Characteristics**|
|---|---|---|---|---|---|---|
|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Units**|
|FGTYRX|Serial data rate||0.500|–|FGTYMAX|Gb/s|
|RXSST|Receiver spread-spectrum tracking1|Modulated at 33 kHz|–5000|–|0|ppm|
|RXRL|Run length (CID)||–|–|256|UI|
|RXPPMTOL|Data/REFCLK PPM offset tolerance|Bit rates ≤ 6.6 Gb/s|–1250|–|1250|ppm|
|||Bit rates > 6.6 Gb/s and<br>≤ 8.0 Gb/s|–700|–|700|ppm|
|||Bit rates > 8.0 Gb/s|–200|–|200|ppm|
|SJ Jitter Tolerance2|||||||
|JT_SJ32.75|Sinusoidal jitter (QPLL)3|32.75 Gb/s|0.25|–|–|UI|
|JT_SJ28.21|Sinusoidal jitter (QPLL)3|28.21 Gb/s|0.30|–|–|UI|
|JT_SJ16.375|Sinusoidal jitter (QPLL)3|16.375 Gb/s|0.30|–|–|UI|
|JT_SJ15.0|Sinusoidal jitter (QPLL)3|15.0 Gb/s|0.30|–|–|UI|
|JT_SJ14.1|Sinusoidal jitter (QPLL)3|14.1 Gb/s|0.30|–|–|UI|
|JT_SJ13.1|Sinusoidal jitter (QPLL)3|13.1 Gb/s|0.30|–|–|UI|
|JT_SJ12.5|Sinusoidal jitter (QPLL)3|12.5 Gb/s|0.30|–|–|UI|
|JT_SJ11.3|Sinusoidal jitter (QPLL)3|11.3 Gb/s|0.30|–|–|UI|
|JT_SJ10.32_QPLL|Sinusoidal jitter (QPLL)3|10.32 Gb/s|0.30|–|–|UI|
|JT_SJ10.32_CPLL|Sinusoidal jitter (CPLL)3|10.32 Gb/s|0.30|–|–|UI|
|JT_SJ9.953_QPLL|Sinusoidal jitter (QPLL)3|9.953 Gb/s|0.30|–|–|UI|
|JT_SJ9.953_CPLL|Sinusoidal jitter (CPLL)3|9.953 Gb/s|0.30|–|–|UI|
|JT_SJ8.0|Sinusoidal jitter (CPLL)3|8.0 Gb/s|0.42|–|–|UI|
|JT_SJ6.6|Sinusoidal jitter (CPLL)3|6.6 Gb/s|0.44|–|–|UI|
|JT_SJ5.0|Sinusoidal jitter (CPLL)3|5.0 Gb/s|0.44|–|–|UI|
|JT_SJ4.25|Sinusoidal jitter (CPLL)3|4.25 Gb/s|0.44|–|–|UI|
|JT_SJ3.2|Sinusoidal jitter (CPLL)3|3.2 Gb/s4|0.45|–|–|UI|
|JT_SJ2.5|Sinusoidal jitter (CPLL)3|2.5 Gb/s5|0.30|–|–|UI|
|JT_SJ1.25|Sinusoidal jitter (CPLL)3|1.25 Gb/s6|0.30|–|–|UI|
|JT_SJ500|Sinusoidal jitter (CPLL)3|500 Mb/s7|0.30|–|–|UI|



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Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

_Table 53:_ **GTY Transceiver Receiver Switching Characteristics** _(cont'd)_ 

|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|---|
|_Table 53:_**GTY Transceiver Receiver Switching Characteristics**_(cont'd)_|||||||
|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Units**|
|SJ Jitter Tolerance with Stressed Eye2|||||||
|JT_TJSE3.2|Total jitter with stressed eye8|3.2 Gb/s|0.70|–|–|UI|
|JT_TJSE6.6||6.6 Gb/s|0.70|–|–|UI|
|JT_SJSE3.2|Sinusoidal jitter with stressed eye8|3.2 Gb/s|0.10|–|–|UI|
|JT_SJSE6.6||6.6 Gb/s|0.10|–|–|UI|
|**Notes:**<br>1.<br>Using RXOUT_DIV = 1, 2, and 4.<br>2.<br>All jitter values are based on a bit error ratio of 10–12.<br>3.<br>The frequency of the injected sinusoidal jitter is 80 MHz.<br>4.<br>CPLL frequency at 3.2 GHz and RXOUT_DIV = 2.<br>5.<br>CPLL frequency at 2.5 GHz and RXOUT_DIV = 2.<br>6.<br>CPLL frequency at 2.5 GHz and RXOUT_DIV = 4.<br>7.<br>CPLL frequency at 2.0 GHz and RXOUT_DIV = 8.<br>8.<br>Composite jitter with RX equalizer enabled. DFE disabled.|||||||



## **GTY Transceiver Electrical Compliance** 

The _UltraScale Architecture GTY Transceivers User Guide_ (UG578) contains recommended use modes that ensure compliance for the protocols listed in the following table. The transceiver wizard provides the recommended settings for those use cases and for protocol specific characteristics. 

_Table 54:_ **GTY Transceiver Protocol List** 

|The_UltraScale Architecture GTY Transceivers User Guide_(UG578) contains recommended use modes that ensure<br>compliance for the protocols listed in the following table. The transceiver wizard provides the recommended<br>setngs for those use cases and for protocol specifc characteristcs.|The_UltraScale Architecture GTY Transceivers User Guide_(UG578) contains recommended use modes that ensure<br>compliance for the protocols listed in the following table. The transceiver wizard provides the recommended<br>setngs for those use cases and for protocol specifc characteristcs.|The_UltraScale Architecture GTY Transceivers User Guide_(UG578) contains recommended use modes that ensure<br>compliance for the protocols listed in the following table. The transceiver wizard provides the recommended<br>setngs for those use cases and for protocol specifc characteristcs.|The_UltraScale Architecture GTY Transceivers User Guide_(UG578) contains recommended use modes that ensure<br>compliance for the protocols listed in the following table. The transceiver wizard provides the recommended<br>setngs for those use cases and for protocol specifc characteristcs.|
|---|---|---|---|
|_Table 54:_**GTY Transceiver Protocol List**||||
|**Protocol**|**Specification**|**Serial Rate (Gb/s)**|**Electrical**<br>**Compliance**|
|CAUI-4|IEEE 802.3-2012|25.78125|Compliant|
|28 Gb/s backplane|CEI-25G-LR|25–28.05|Compliant|
|Interlaken|OIF-CEI-6G, OIF-CEI-11GSR, OIF-CEI-28G-MR|4.25–25.78125|Compliant|
|100GBASE-KR4|IEEE 802.3bj-2014, CEI-25G-LR|25.78125|Compliant1|
|100GBASE-CR4|IEEE 802.3bj-2014, CEI-25G-LR|25.78125|Compliant1|
|50GBASE-KR4|IEEE 802.3by-2014, CEI-25G-LR|25.78125|Compliant1|
|50GBASE-CR4|IEEE 802.3by-2014, CEI-25G-LR|25.78125|Compliant1|
|25GBASE-KR4|IEEE 802.3by-2014, CEI-25G-LR|25.78125|Compliant1|
|25GBASE-CR4|IEEE 802.3by-2014, CEI-25G-LR|25.78125|Compliant1|
|OTU4 (OTL4.4) CFP2|OIF-CEI-28G-VSR|27.952493–32.75|Compliant|
|OTU4 (OTL4.4) CFP|OIF-CEI-11G-MR|11.18–13.1|Compliant|
|CAUI-10|IEEE 802.3-2012|10.3125|Compliant|
|nPPI|IEEE 802.3-2012|10.3125|Compliant|
|10GBASE-KR2|IEEE 802.3-2012|10.3125|Compliant|
|SFP+|SFF-8431 (SR and LR)|9.95328–11.10|Compliant|
|XFP|INF-8077i, revision 4.5|10.3125|Compliant|
|RXAUI|CEI-6G-SR|6.25|Compliant|
|XAUI|IEEE 802.3-2012|3.125|Compliant|
|1000BASE-X|IEEE 802.3-2012|1.25|Compliant|



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## _Table 54:_ **GTY Transceiver Protocol List** _(cont'd)_ 

|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|
|_Table 54:_**GTY Transceiver Protocol List**_(cont'd)_||||
|**Protocol**|**Specification**|**Serial Rate (Gb/s)**|**Electrical**<br>**Compliance**|
|5.0G Ethernet|IEEE 802.3bx (PAR)|5|Compliant|
|2.5G Ethernet|IEEE 802.3bx (PAR)|2.5|Compliant|
|HiGig, HiGig+, HiGig2|IEEE 802.3-2012|3.74, 6.6|Compliant|
|QSGMII|QSGMII v1.2 (Cisco System, ENG-46158)|5|Compliant|
|OTU2|ITU G.8251|10.709225|Compliant|
|OTU4 (OTL4.10)|OIF-CEI-11G-SR|11.180997|Compliant|
|OC-3/12/48/192|GR-253-CORE|0.1555–9.956|Compliant|
|PCIe Gen1, 2, 3|PCI Express base 3.0|2.5, 5.0, and 8.0|Compliant|
|SDI3|SMPTE 424M-2006|0.27–2.97|Compliant|
|UHD-SDI3|SMPTE ST-2081 6G, SMPTE ST-2082 12G|6 and 12|Compliant|
|Hybrid memory cube (HMC)|HMC-15G-SR|10, 12.5, and 15.0|Compliant|
|MoSys bandwidth engine|CEI-11-SR and CEI-11-SR (overclocked)|10.3125, 15.5|Compliant|
|CPRI|CPRI_v_6_1_2014-07-01|0.6144–12.165|Compliant|
|Passive optical network (PON)|10G-EPON, 1G-EPON, NG-PON2, XG-PON, and 2.5G-PON|0.155–10.3125|Compliant|
|JESD204a/b|OIF-CEI-6G, OIF-CEI-11G|3.125–12.5|Compliant|
|Serial RapidIO|RapidIO specification 3.1|1.25–10.3125|Compliant|
|DisplayPort|DP 1.2B CTS|1.62–5.4|Compliant3|
|Fibre channel|FC-PI-4|1.0625–14.025|Compliant|
|SATA Gen1, 2, 3|Serial ATA revision 3.0 specification|1.5, 3.0, and 6.0|Compliant|
|SAS Gen1, 2, 3|T10/BSR INCITS 519|3.0, 6.0, and 12.0|Compliant|
|SFI-5|OIF-SFI5-01.0|0.625 - 12.5|Compliant|
|Aurora|CEI-6G, CEI-11G-LR|All rates|Compliant|
|**Notes:**<br>1.<br>25 dB loss at Nyquist without FEC.<br>2.<br>The transition time of the transmitter is faster than the IEEE Std 802.3-2012 specification.<br>3.<br>This protocol requires external circuitry to achieve compliance.||||



## **GTM Transceiver Specifications** 

The _UltraScale Architecture and Product Data Sheet: Overview_ (DS890) lists the Virtex UltraScale+ FPGAs that include the GTM transceivers. 

## **GTM Transceiver DC Input and Output Levels** 

Table 55 summarizes the DC specifications of the GTM transceivers in Virtex UltraScale+ FPGAs. Consult the _Virtex UltraScale+ FPGAs GTM Transceivers User Guide_ (UG581) for further details. 

## _Table 55:_ **GTM Transceiver DC Specifications** 

|_Table 55:_|**GTM Transceiver DC Specifications**||||||
|---|---|---|---|---|---|---|
|**Symbol**|**DC Parameter**<br>**Conditions**|**Min**|**Typ**|**Max**|**Units**||
|DVPPIN|Differential peak-to-peak input voltage (external AC coupled)|150|–|1250|mV||



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Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

_Table 55:_ **GTM Transceiver DC Specifications** _(cont'd)_ 

|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics<br>&. XILINX.|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics<br>&. XILINX.|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics<br>&. XILINX.|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics<br>&. XILINX.|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics<br>&. XILINX.|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics<br>&. XILINX.|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics<br>&. XILINX.|
|---|---|---|---|---|---|---|
|_Table 55:_**GTM Transceiver DC Specifications**_(cont'd)_|||||||
|**Symbol**<br>~~QO~~|**DC Parameter**<br>~~QO~~|**Conditions**<br>~~QO~~|**Min**<br>~~QO~~|**Typ**<br>~~QO~~|**Max**<br>~~QO~~|**Units**<br>~~QO~~|
|VIN<br>~~a~~|Single-ended input voltage. Voltage<br>measured at the pin referenced to<br>GND.<br>~~a~~|DC coupled VMGTAVTT= 1.2V|–400|–|VMGTAVTT|mV|
|VCMIN<br>~~a~~|Common mode input voltage<br>~~a~~|DC coupled VMGTAVTT= 1.2V|–|2/3 VMGTAVTT|–|mV|
|DVPPOUT<br>~~a~~|Differential peak-to-peak output<br>voltage1<br>~~ase~~|Transmitter output swing is set<br>to11111<br>~~se~~<br>~~r~~e|800<br>~~se~~|–<br>~~se~~<br>e~~e~~|–<br>~~se~~<br>~~e~~|mV<br>~~se~~<br>e~~e~~|
|VCMOUTDC<br>a<br>a|Common mode output voltage: DC<br>coupled (equation based)<br>es<br>|When remote RX is terminated to<br>GND<br>~~r~~e|VMGTAVTT/2 – DVPPOUT/4<br>e~~e~~|||mV<br>e~~e~~|
|||When remote RX termination is<br>floating<br>~~r~~e<br>~~e~~e|VMGTAVTT– DVPPOUT/2<br>e~~e ~~<br>cee|||mV<br> e~~e~~|
|||When remote RX is terminated to<br>VRX_TERM2<br>~~e~~e<br>|cee<br>|||mV<br>|
|VCMOUTAC<br>a<br>a|Common mode output voltage: AC<br>coupled<br>es<br>|Equation based<br>~~e~~e <br>|VMGTAVTT– DVPPOUT/2<br> cee<br>|||mV<br>|
|RIN<br>a<br>a|Differential input resistance<br>es<br>||–<br>|100<br><br>I|–<br>|Ω<br>|
|ROUT<br>~~(OO~~<br>a<br>a|Differential output resistance<br>~~(OO~~<br>a||–<br>~~(OO~~|100<br>~~(OO~~<br>I|–<br>~~(OO~~|Ω<br>~~(OO~~|
|TOSKEW<br>a<br>a|Transmitter output pair (TXP and TXN) intra-pair skew<br>a||–|–<br>I|10|ps|
|CEXT<br>a|Recommended external AC coupling capacitor3<br>a||–|100|–|nF|
|**Notes:**<br>1.<br>The output swing and pre-emphasis levels are programmable using the GTM transceiver attributes discussed in the_Virtex UltraScale+_<br>_FPGAs GTM Transceivers User Guide_(UG581) and can result in values lower than reported in this table.<br>2.<br>VRX_TERMis the remote RX termination voltage.<br>3.<br>Other values can be used as appropriate to conform to specific protocols and standards.|||||||



**Notes:** 

1. The output swing and pre-emphasis levels are programmable using the GTM transceiver attributes discussed in the _Virtex UltraScale+ FPGAs GTM Transceivers User Guide_ (UG581) and can result in values lower than reported in this table. 

2. VRX_TERM is the remote RX termination voltage. 

**==> picture [513 x 271] intentionally omitted <==**

**----- Start of picture text -----**<br>
3. Other values can be used as appropriate to conform to specific protocols and standards.<br>Figure 5:    Single-Ended Peak-to-Peak Voltage<br>+V P<br>Single-Ended<br>Peak-to-Peak<br>N Voltage<br>0<br>O M AMEX T<br>X16653-072117<br>Figure 6:    Differential Peak-to-Peak Voltage<br>+V<br>7<br>Differential<br>0 Peak-to-Peak<br>Voltage<br>–V P–N<br>Differential peak-to-peak voltage = (Single-ended peak-to-peak voltage) x 2<br>X16639-072117<br>**----- End of picture text -----**<br>


The following tables summarize the DC specifications of the clock input/output levels of the GTM transceivers in Virtex UltraScale+ FPGAs. Consult the _Virtex UltraScale+ FPGAs GTM Transceivers User Guide_ (UG581) for further details. 

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## _Table 56:_ **GTM Transceiver Clock DC Input Level Specification** 

|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|
|_Table 56:_**GTM Transceiver Clock DC Input Level Specification**||||||
|**Symbol**|**DC Parameter**|**Min**|**Typ**|**Max**|**Units**|
|VIDIFF|Differential peak-to-peak input voltage|250|–|2000|mV|
|RIN|Differential input resistance|–|100|–|Ω|
|CEXT|Required external AC coupling capacitor|–|10|–|nF|



_Table 57:_ **GTM Transceiver Clock Output Level Specification** 

|_Table 57:_**GTM Transceiver Clock Output Level Specification**|_Table 57:_**GTM Transceiver Clock Output Level Specification**|_Table 57:_**GTM Transceiver Clock Output Level Specification**|_Table 57:_**GTM Transceiver Clock Output Level Specification**|_Table 57:_**GTM Transceiver Clock Output Level Specification**|_Table 57:_**GTM Transceiver Clock Output Level Specification**|_Table 57:_**GTM Transceiver Clock Output Level Specification**|
|---|---|---|---|---|---|---|
|**Symbol**|**Description**|**Conditions**|**Min**|**Typ**|**Max**|**Units**|
|VOL|Output Low voltage for P and N|RT= 100Ω across P and N signals|100|–|330|mV|
|VOH|Output High voltage for P and N|RT= 100Ω across P and N signals|500|–|700|mV|
|VDDOUT|Differential output voltage (P–N), P  =<br>High (N–P), N = High|RT= 100Ω across P and N signals|300|–|430|mV|
|VCMOUT|Common mode voltage|RT= 100Ω across P and N signals|300|–|500|mV|



## **GTM Transceiver Switching Characteristics** 

Consult the _Virtex UltraScale+ FPGAs GTM Transceivers User Guide_ (UG581) for further information. 

_Table 58:_ **GTM Transceiver Performance** 

|Consult the_Virtex UltraScale+ FPGAs GTM Transceivers User Guide_(UG581) for further informaton.|Consult the_Virtex UltraScale+ FPGAs GTM Transceivers User Guide_(UG581) for further informaton.|Consult the_Virtex UltraScale+ FPGAs GTM Transceivers User Guide_(UG581) for further informaton.|Consult the_Virtex UltraScale+ FPGAs GTM Transceivers User Guide_(UG581) for further informaton.|Consult the_Virtex UltraScale+ FPGAs GTM Transceivers User Guide_(UG581) for further informaton.|Consult the_Virtex UltraScale+ FPGAs GTM Transceivers User Guide_(UG581) for further informaton.|Consult the_Virtex UltraScale+ FPGAs GTM Transceivers User Guide_(UG581) for further informaton.|Consult the_Virtex UltraScale+ FPGAs GTM Transceivers User Guide_(UG581) for further informaton.|
|---|---|---|---|---|---|---|---|
|_Table 58:_**GTM Transceiver Performance**||||||||
|**Symbol**|**Description**|**Modulation**|**Speed Grade and VCCINT Operating Voltages**||||**Units**|
||||**0.90V**|**0.85V**||**0.72V**||
||||**-3**|**-2**|**-1**|**-2**||
|FGTMMAX|GTM maximum line rate|PAM41|58.00|56.42|53.20|56.42|Gb/s|
|||NRZ2|29.00|28.21|26.60|28.21|Gb/s|
|FGTMMIN|GTM minimum line rate|PAM41|19.6|19.6|19.6|19.6|Gb/s|
|||NRZ2|9.8|9.8|9.8|9.8|Gb/s|
|**Notes:**<br>1.<br>For PAM4, data rates from 29 Gb/s to 39.2 Gb/s are not available.<br>2.<br>For NRZ, data rates from 14.5 Gb/s to 19.6 Gb/s are not available.||||||||



_Table 59:_ **GTM Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics** 

|**Symbol**|**Description**|**All Speed Grades**|**Units**||
|---|---|---|---|---|
|FGTMDRPCLK|GTMDRPCLK maximum frequency|250|MHz||



## _Table 60:_ **GTM Transceiver Reference Clock Switching Characteristics** 

|_Table 60:_**GTM Transceiver Reference Clock Switching Characteristics**|_Table 60:_**GTM Transceiver Reference Clock Switching Characteristics**|_Table 60:_**GTM Transceiver Reference Clock Switching Characteristics**|_Table 60:_**GTM Transceiver Reference Clock Switching Characteristics**|_Table 60:_**GTM Transceiver Reference Clock Switching Characteristics**|_Table 60:_**GTM Transceiver Reference Clock Switching Characteristics**|_Table 60:_**GTM Transceiver Reference Clock Switching Characteristics**|
|---|---|---|---|---|---|---|
|**Symbol**|**Description**|**Conditions**|**All Speed Grades**|||**Units**|
||||**Min**|**Typ**|**Max**||
|FGCLK|Reference clock frequency range||60|–|820|MHz|
|TRCLK|Reference clock rise time|20% – 80%|–|200|–|ps|
|TFCLK|Reference clock fall time|80% – 20%|–|200|–|ps|
|TDCREF|Reference clock duty cycle|Transceiver PLL only|40|50|60|%|



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_Table 61:_ **GTM Transceiver Reference Clock Oscillator Selection Phase Noise Mask** 

|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|---|
|_Table 61:_**GTM Transceiver Reference Clock Oscillator Selection Phase Noise Mask**|||||||
|**Symbol**|**Description**1**,**2|**Offset**<br>**Frequency**|**Min**|**Typ**|**Max**|**Units**|
|LCPLLREFCLKMASK|LCPLL reference clock select phase noise mask at<br>REFCLK frequency = 156.25 MHz|10 kHz|–|–|–112|dBc/Hz|
|||100 kHz|–|–|–128||
|||1 MHz|–|–|–145||
||LCPLL0 reference clock select phase noise mask<br>at REFCLK frequency = 312.5 MHz|10 kHz|–|–|–103|dBc/Hz|
|||100 kHz|–|–|–123||
|||1 MHz|–|–|–143||
||LCPLL0 reference clock select phase noise mask<br>at REFCLK frequency = 625 MHz|10 kHz|–|–|–98|dBc/Hz|
|||100 kHz|–|–|–117||
|||1 MHz|–|–|–140||
|**Notes:**<br>1.<br>For reference clock frequencies not in this table, use the phase-noise mask for the nearest reference clock frequency.<br>2.<br>This reference clock phase-noise mask is superseded by any reference clock phase-noise mask that is specified in a supported protocol.|||||||



## _Table 62:_ **GTM Transceiver PLL/Lock Time Adaptation** 

|_Table 62:_**GTM Transceiver PLL/Lock Time Adaptation**|_Table 62:_**GTM Transceiver PLL/Lock Time Adaptation**|_Table 62:_**GTM Transceiver PLL/Lock Time Adaptation**|_Table 62:_**GTM Transceiver PLL/Lock Time Adaptation**|_Table 62:_**GTM Transceiver PLL/Lock Time Adaptation**|_Table 62:_**GTM Transceiver PLL/Lock Time Adaptation**|_Table 62:_**GTM Transceiver PLL/Lock Time Adaptation**|
|---|---|---|---|---|---|---|
|**Symbol**|**Description**|**Conditions**|**All Speed Grades**|||**Units**|
||||**Min**|**Typ**|**Max**||
|TLOCK|Initial PLL lock.||–|–|1|ms|
|TDLOCK|Clock recovery phase acquisition and<br>adaptation time for decision feedback<br>equalizer (DFE)|After the PLL is locked to the<br>reference clock, this is the<br>time it takes to lock the clock<br>data recovery (CDR) to the<br>data present at the input.|–|||UI|
||Clock recovery phase acquisition and<br>adaptation time for low-power mode (LPM)<br>when the DFE is disabled||–|||UI|



## _Table 63:_ **GTM Transceiver User Clock Switching Characteristics** 

|_Table 63:_**GTM Transceiver User Clock Switching Characteristics**|_Table 63:_**GTM Transceiver User Clock Switching Characteristics**|_Table 63:_**GTM Transceiver User Clock Switching Characteristics**|_Table 63:_**GTM Transceiver User Clock Switching Characteristics**|_Table 63:_**GTM Transceiver User Clock Switching Characteristics**|_Table 63:_**GTM Transceiver User Clock Switching Characteristics**|_Table 63:_**GTM Transceiver User Clock Switching Characteristics**|_Table 63:_**GTM Transceiver User Clock Switching Characteristics**|_Table 63:_**GTM Transceiver User Clock Switching Characteristics**|_Table 63:_**GTM Transceiver User Clock Switching Characteristics**|
|---|---|---|---|---|---|---|---|---|---|
|**Symbol**|**Description**1||**Data Width Conditions (Bit)**||**Speed Grade and VCCINT Operating Voltages**||||**Units**|
||||||**0.90V**|**0.85V**||**0.72V**||
||||**Internal**<br>**Logic**|**Interconnect**<br>**Logic**|**-3**|**-2**|**-1**|**-2**||
|FTXOUTPMA|TXOUTCLK maximum frequency sourced from OUTCLKPMA||||453.13|440.78|415.63|440.78|MHz|
|FRXOUTPMA|RXOUTCLK maximum frequency sourced from OUTCLKPMA||||453.13|440.78|415.63|440.78|MHz|
|FTXOUTPROGDIV|TXOUTCLK maximum frequency sourced from TXPROGDIVCLK||||725.00|705.25|665.00|705.25|MHz|
|FRXOUTPROGDIV|RXOUTCLK maximum frequency sourced from RXPROGDIVCLK||||725.00|705.25|665.00|705.25|MHz|
|FTXIN|TXUSRCLK<br>maximum<br>frequency|PAM4|80|80|725.00|705.25|665.00|705.25|MHz|
||||128|128|453.13|440.78|415.63|440.78|MHz|
||||80|160|725.00|705.25|665.00|705.25|MHz|
||||128|256|453.13|440.78|415.63|440.78|MHz|
|||NRZ|64|64|453.13|440.78|415.63|440.78|MHz|
||||64|128|453.13|440.78|415.63|440.78|MHz|



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_Table 63:_ **GTM Transceiver User Clock Switching Characteristics** _(cont'd)_ 

|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|---|---|---|---|
|_Table 63:_**GTM Transceiver User Clock Switching Characteristics**_(cont'd)_||||||||||
|**Symbol**|**Description**1||**Data Width Conditions (Bit)**||**Speed Grade and VCCINT Operating Voltages**||||**Units**|
||||||**0.90V**|**0.85V**||**0.72V**||
||||**Internal**<br>**Logic**|**Interconnect**<br>**Logic**|**-3**|**-2**|**-1**|**-2**||
|FRXIN|RXUSRCLK<br>maximum<br>frequency|PAM4|80|80|725.00|705.25|665.00|705.25|MHz|
||||128|128|453.13|440.78|415.63|440.78|MHz|
||||80|160|725.00|705.25|665.00|705.25|MHz|
||||128|256|453.13|440.78|415.63|440.78|MHz|
|||NRZ|64|64|453.13|440.78|415.63|440.78|MHz|
||||64|128|453.13|440.78|415.63|440.78|MHz|
|FTXIN2|TXUSRCLK2<br>maximum<br>frequency|PAM4|80|80|725.00|705.25|665.00|705.25|MHz|
||||128|128|453.13|440.78|415.63|440.78|MHz|
||||80|160|362.50|352.63|332.50|352.63|MHz|
||||128|256|226.56|220.39|207.81|220.39|MHz|
|||NRZ|64|64|453.13|440.78|415.63|440.78|MHz|
||||64|128|226.56|220.39|207.81|220.39|MHz|
|FRXIN2|RXUSRCLK2<br>maximum<br>frequency|PAM4|80|80|725.00|705.25|665.00|705.25|MHz|
||||128|128|453.13|440.78|415.63|440.78|MHz|
||||80|160|362.50|352.63|332.50|352.63|MHz|
||||128|256|226.56|220.39|207.81|220.39|MHz|
|||NRZ|64|64|453.13|440.78|415.63|440.78|MHz|
||||64|128|226.56|220.39|207.81|220.39|MHz|
|**Notes:**<br>1.<br>Clocking must be implemented as||described in the_Virtex UltraScale+ FPGAs GTM_|||_Transceivers User Guide_(UG581).|||||



_Table 64:_ **GTM Transceiver Transmitter Switching Characteristics** 

|_Table 64:_**GTM Transceiver Transmitter Switching Characteristics**|_Table 64:_**GTM Transceiver Transmitter Switching Characteristics**|_Table 64:_**GTM Transceiver Transmitter Switching Characteristics**|_Table 64:_**GTM Transceiver Transmitter Switching Characteristics**|_Table 64:_**GTM Transceiver Transmitter Switching Characteristics**|_Table 64:_**GTM Transceiver Transmitter Switching Characteristics**|_Table 64:_**GTM Transceiver Transmitter Switching Characteristics**|_Table 64:_**GTM Transceiver Transmitter Switching Characteristics**|
|---|---|---|---|---|---|---|---|
|**Symbol**|**Description**|**Condition**||**Min**|**Typ**|**Max**|**Units**|
|FGTMTX|Serial data rate range|||FGTMMIN|–|FGTMMAX|Gb/s|
|TRTX|TX rise time|20%–80%||–||–|ps|
|TFTX|TX fall time|80%–20%||–||–|ps|
|TLLSKEW|TX lane-to-lane skew1|||–|–||ps|
|TJ58_PAM4|Total jitter2,3|PAM4|58 Gb/s|–|–||UI|
|DJ58_PAM4|Deterministic jitter2,|||–|–||UI|
|TJ56.42_PAM4|Total jitter2,|PAM4|56.42 Gb/s|–|–||UI|
|DJ56.42_PAM4|Deterministic jitter2,|||–|–||UI|
|TJ53.125_PAM4|Total jitter2,|PAM4|53.125 Gb/s|–|–||UI|
|DJ53.125_PAM4|Deterministic jitter2,|||–|–||UI|
|TJ52.125_PAM4|Total jitter2,|PAM4|52.125 Gb/s|–|–||UI|
|DJ52.125_PAM4|Deterministic jitter2,|||–|–||UI|
|TJ48_PAM4|Total jitter2,|PAM4|48 Gb/s|–|–||UI|
|DJ48_PAM4|Deterministic jitter2,|||–|–||UI|
|TJ28.21_PAM4|Total jitter2,|PAM4|28.21 Gb/s|–|–||UI|
|DJ28.21_PAM4|Deterministic jitter2,|||–|–||UI|



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_Table 64:_ **GTM Transceiver Transmitter Switching Characteristics** _(cont'd)_ 

|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|---|---|
|_Table 64:_**GTM Transceiver Transmitter Switching Characteristics**_(cont'd)_||||||||
|**Symbol**|**Description**|**Condition**||**Min**|**Typ**|**Max**|**Units**|
|TJ19.6_PAM4|Total jitter2,|PAM4|19.6 Gb/s|–|–||UI|
|DJ19.6_PAM4|Deterministic jitter2,|||–|–||UI|
|TJ29_NRZ|Total jitter2,3|NRZ|29 Gb/s|–|–||UI|
|DJ29_NRZ|Deterministic jitter2,3|||–|–||UI|
|TJ28.21_NRZ|Total jitter2,3|NRZ|28.21 Gb/s|–|–||UI|
|DJ28.21_NRZ|Deterministic jitter2,3|||–|–||UI|
|TJ26.5625_NRZ|Total jitter2,3|NRZ|26.5625 Gb/s|–|–||UI|
|DJ26.5625_NRZ|Deterministic jitter2,3|||–|–||UI|
|TJ25.78125_NRZ|Total jitter23|NRZ|25.78125 Gb/<br>s|–|–||UI|
|DJ25.78125_NRZ|Deterministic jitter23|||–|–||UI|
|TJ24_NRZ|Total jitter23|NRZ|24 Gb/s|–|–||UI|
|DJ24_NRZ|Deterministic jitter23|||–|–||UI|
|TJ15_NRZ|Total jitter23|NRZ|15 Gb/s|–|–||UI|
|DJ15_NRZ|Deterministic jitter23|||–|–||UI|
|TJ12_NRZ|Total jitter23|NRZ|12 Gb/s|–|–||UI|
|DJ12_NRZ|Deterministic jitter23|||–|–||UI|
|TJ10.1_NRZ|Total jitter23|NRZ|10.1 Gb/s|–|–||UI|
|DJ10.1_NRZ|Deterministic jitter23|||–|–||UI|
|TJ9.8_NRZ|Total jitter23|NRZ|9.8 Gb/s|–|–||UI|
|DJ9.8_NRZ|Deterministic jitter23|||–|–||UI|
|**Notes:**<br>1.<br>Using same REFCLK input with TX phase alignment enabled for up to two consecutive transmitters (one fully populated GTM dual) at<br>maximum line rate.<br>2.<br>Using LCPLL_FBDIV = 40, 80-bit internal data width. These values are NOT intended for protocol specific compliance determinations.<br>3.<br>All jitter values are based on a bit-error ratio of 10–12.||||||||



_Table 65:_ **GTM Transceiver Receiver Switching Characteristics** 

|_Table 65:_**GTM Transceiver Receiver Switching Characteristics**|_Table 65:_**GTM Transceiver Receiver Switching Characteristics**|_Table 65:_**GTM Transceiver Receiver Switching Characteristics**|_Table 65:_**GTM Transceiver Receiver Switching Characteristics**|_Table 65:_**GTM Transceiver Receiver Switching Characteristics**|_Table 65:_**GTM Transceiver Receiver Switching Characteristics**|_Table 65:_**GTM Transceiver Receiver Switching Characteristics**|_Table 65:_**GTM Transceiver Receiver Switching Characteristics**|
|---|---|---|---|---|---|---|---|
|**Symbol**|**Description**|**Condition**||**Min**|**Typ**|**Max**|**Units**|
|FGTMRX|Serial data rate|||0.500|–|FGTMMAX|Gb/s|
|RXRL|Run length (CID)|||–|–|256|UI|
|RXPPMTOL|Data/REFCLK PPM offset tolerance|||–200|–|200|ppm|
|SJ Jitter Tolerance2||||||||
|JT_SJ58_PAM4|Sinusoidal jitter|PAM4|58 Gb/s||–|–|UI|
|JT_SJ56.42_PAM4|Sinusoidal jitter|PAM4|56.42 Gb/s||–|–|UI|
|JT_SJ53.125_PAM4|Sinusoidal jitter|PAM4|53.125 Gb/s||–|–|UI|
|JT_SJ52.125_PAM4|Sinusoidal jitter|PAM4|52.125 Gb/s||–|–|UI|
|JT_SJ48_PAM4|Sinusoidal jitter|PAM4|48 Gb/s||–|–|UI|
|JT_SJ28.21_PAM4|Sinusoidal jitter|PAM4|28.21 Gb/s||–|–|UI|
|JT_SJ19.6_PAM4|Sinusoidal jitter|PAM4|19.6 Gb/s||–|–|UI|
|JT_SJ29_NRZ|Sinusoidal jitter3|NRZ|29 Gb/s||–|–|UI|
|JT_SJ28.21_NRZ|Sinusoidal jitter3|NRZ|28.21 Gb/s||–|–|UI|
|JT_SJ26.5625_NRZ|Sinusoidal jitter3|NRZ|26.5625 Gb/s||–|–|UI|



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_Table 65:_ **GTM Transceiver Receiver Switching Characteristics** _(cont'd)_ 

|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|---|---|
|_Table 65:_**GTM Transceiver Receiver Switching Characteristics**_(cont'd)_||||||||
|**Symbol**|**Description**|**Condition**||**Min**|**Typ**|**Max**|**Units**|
|JT_SJ25.78125_NRZ|Sinusoidal jitter3|NRZ|25.78125 Gb/s||–|–|UI|
|JT_SJ24_NRZ|Sinusoidal jitter3|NRZ|24.0 Gb/s||–|–|UI|
|JT_SJ15_NRZ|Sinusoidal jitter3|NRZ|15.0 Gb/s||–|–|UI|
|JT_SJ12_NRZ|Sinusoidal jitter3|NRZ|12.0 Gb/s||–|–|UI|
|JT_SJ10.1_NRZ|Sinusoidal jitter3|NRZ|10.1 Gb/s||–|–|UI|
|JT_SJ9.8_NRZ|Sinusoidal jitter3|NRZ|9.8 Gb/s||–|–|UI|
|**Notes:**<br>1.<br>Using RXOUT_DIV = 1, 2, and 4.<br>2.<br>All jitter values are based on a bit error ratio of 10–12.<br>3.<br>The frequency of the injected sinusoidal jitter is 80 MHz.||||||||



## **GTM Transceiver Electrical Compliance** 

The _Virtex UltraScale+ FPGAs GTM Transceivers User Guide_ (UG581) contains recommended use modes that ensure compliance for the protocols listed in the following table. The transceiver wizard provides the recommended settings for those use cases and for protocol specific characteristics. 

_Table 66:_ **GTM Transceiver Protocol List** 

|The_Virtex UltraScale+ FPGAs GTM Transceivers User Guide_(UG581) contains recommended use modes that<br>ensure compliance for the protocols listed in the following table. The transceiver wizard provides the<br>recommended setngs for those use cases and for protocol specifc characteristcs.|The_Virtex UltraScale+ FPGAs GTM Transceivers User Guide_(UG581) contains recommended use modes that<br>ensure compliance for the protocols listed in the following table. The transceiver wizard provides the<br>recommended setngs for those use cases and for protocol specifc characteristcs.|The_Virtex UltraScale+ FPGAs GTM Transceivers User Guide_(UG581) contains recommended use modes that<br>ensure compliance for the protocols listed in the following table. The transceiver wizard provides the<br>recommended setngs for those use cases and for protocol specifc characteristcs.|The_Virtex UltraScale+ FPGAs GTM Transceivers User Guide_(UG581) contains recommended use modes that<br>ensure compliance for the protocols listed in the following table. The transceiver wizard provides the<br>recommended setngs for those use cases and for protocol specifc characteristcs.|The_Virtex UltraScale+ FPGAs GTM Transceivers User Guide_(UG581) contains recommended use modes that<br>ensure compliance for the protocols listed in the following table. The transceiver wizard provides the<br>recommended setngs for those use cases and for protocol specifc characteristcs.|
|---|---|---|---|---|
|_Table 66:_**GTM Transceiver Protocol List**|||||
|**Protocol**|**Specification**|**Modulation**|**Serial Rate**<br>**(Gb/s)**|**Electrical**<br>**Compliance**|
|400GE (CDAUI8)|IEEE 802.3bs (400GE), OIF-CEI-56G-VSR|PAM4|53.125|Compliant|
|200GE (CCAUI4)|QSFP561|PAM4|53.125|Compliant|
|100GE (CAUI2) chip-to-optics|IEEE802.3ba (100GE), OIF-CEI-56G-VSR|PAM4|53.125|Compliant|
|100GE (CAUI4) chip-to-chip|OIF-CEI-56G-MR|PAM4|53.125|Compliant|
|100GE (CAUI4)|IEEE 802.3bm2|NRZ|25.78125|Compliant|
|50G LAUI|IEEE (50GE) LAUI, OIF-CEI-VSR|PAM4|52.125|Compliant|
|50GE LAUI2 (2 x 25G) chip-to-optics|OIF-CEI-28G-VSR|NRZ|26.5625|Compliant|
|10G-15G backplane capability|10G NRZ interfaces over customer backplane<br>including high-confident region|NRZ|15|Compliant|
|Ethernet AN/LT (autonegotiation/<br>link training)|IEEE802.3an3|NRZ||Compliant|
|28.21G PAM4 backplanes|Insertion loss @ Nyquist (7.05 GHz) at BER < 10e-17<br>with FEC|PAM4|28.21|Compliant|
|58G PAM4 backplanes|GTM supports 802.3bj style backplanes at 58 Gb/s<br>(35 dB with RS (544, 514) FEC)|PAM4|58|Compliant|
|OTU4 optical modules NRZ optical<br>7% FEC|100G OTU4 and OTUCn requirements to CFP2, CFP4,<br>and QSFP28 optics, OIF-CEI28-VSR|NRZ|28.21|Compliant|
|OTU4 optical module PAM4 optical<br>7% FEC|100G QSFP56, OIF-CEI56-VSR|PAM4|56.4|Compliant|
|Interlaken 25.78125G|OIF-CEI-25G-MR @ 20 dB loss|NRZ|25.78125|Compliant|
|Interlaken 12.5G|OIF-CEI-11G-SR (extended)|NRZ|12.5|Compliant|
|CPRI 48G PAM4|Fibre channel datapath and 1-lane FEC mode with<br>customer alignment with 64/66 encoding|PAM4|48|Compliant|



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_Table 66:_ **GTM Transceiver Protocol List** _(cont'd)_ 

|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|
|_Table 66:_**GTM Transceiver Protocol List**_(cont'd)_|||||
|**Protocol**|**Specification**|**Modulation**|**Serial Rate**<br>**(Gb/s)**|**Electrical**<br>**Compliance**|
|CPRI 24G, 12G, and 10.1G NRZ|CPRI_v_6_1_2014-07-01|NRZ|24, 12, 10.1|Compliant|
|**Notes:**<br>1.<br>FEC, PCS, and MAC are soft.<br>2.<br>Specified with loss target of 15 dB @ Nyquist.<br>3.<br>Requires lock to reference on aper-lane basis and oversampling logic in the device logic to capture the slower autonegotiation.|||||



## **Integrated Interface Block for Interlaken** 

More information and documentation on solutions using the integrated interface block for Interlaken can be found at UltraScale+ Interlaken. The _UltraScale Architecture and Product Data Sheet: Overview_ (DS890) lists how many blocks are in each Virtex UltraScale+ FPGA. This section describes the following Interlaken configurations. 

- 12 x 12.5 Gb/s protocol and lane logic mode (Table 67). 

- 6 x 25.78125 Gb/s and 6 x 28.21 Gb/s protocol and lane logic mode (Table 68). 

- 12 x 25.78125 Gb/s lane logic only mode (Table 69). 

Virtex UltraScale+ FPGAs in the FLVF1924 package are only supported using the 12 x 12.5 Gb/s Interlaken configuration. See the FGTYMAX maximum line rates. 

## _Table 67:_ **Maximum Performance for Interlaken 12 x 12.5 Gb/s Protocol and Lane Logic Mode Designs** 

|_Table 67:_**Maximum Performance for Interlaken 12 x 12.5 Gb/s Protocol and Lane Logic Mode**<br>**Designs**|_Table 67:_**Maximum Performance for Interlaken 12 x 12.5 Gb/s Protocol and Lane Logic Mode**<br>**Designs**|_Table 67:_**Maximum Performance for Interlaken 12 x 12.5 Gb/s Protocol and Lane Logic Mode**<br>**Designs**|_Table 67:_**Maximum Performance for Interlaken 12 x 12.5 Gb/s Protocol and Lane Logic Mode**<br>**Designs**|_Table 67:_**Maximum Performance for Interlaken 12 x 12.5 Gb/s Protocol and Lane Logic Mode**<br>**Designs**|_Table 67:_**Maximum Performance for Interlaken 12 x 12.5 Gb/s Protocol and Lane Logic Mode**<br>**Designs**|_Table 67:_**Maximum Performance for Interlaken 12 x 12.5 Gb/s Protocol and Lane Logic Mode**<br>**Designs**|_Table 67:_**Maximum Performance for Interlaken 12 x 12.5 Gb/s Protocol and Lane Logic Mode**<br>**Designs**|_Table 67:_**Maximum Performance for Interlaken 12 x 12.5 Gb/s Protocol and Lane Logic Mode**<br>**Designs**|_Table 67:_**Maximum Performance for Interlaken 12 x 12.5 Gb/s Protocol and Lane Logic Mode**<br>**Designs**|_Table 67:_**Maximum Performance for Interlaken 12 x 12.5 Gb/s Protocol and Lane Logic Mode**<br>**Designs**|
|---|---|---|---|---|---|---|---|---|---|---|
|**Symbol**|**Description**|**Speed Grade and VCCINT Operating Voltages**||||||||**Units**|
|||**0.90V**||**0.85V**||||**0.72V**|||
|||**-3**||**-2**||**-1**||**-2**|||
|FRX_SERDES_CLK|Receive serializer/ deserializer clock|195.32||195.32||195.32||195.32||MHz|
|FTX_SERDES_CLK|Transmit serializer/ deserializer clock|195.32||195.32||195.32||195.32||MHz|
|FDRP_CLK|Dynamic reconfiguration port clock|250.00||250.00||250.00||250.00||MHz|
|||Min1|Max|Min1|Max|Min1|Max|Min1|Max||
|FCORE_CLK|Interlaken core clock|300.00|322.27|300.00|322.27|300.00|322.27|300.00|322.27|MHz|
|FLBUS_CLK|Interlaken local bus clock|300.00|322.27|300.00|322.27|300.00|322.27|300.00|322.27|MHz|
|**Notes:**<br>1.<br>These are the minimum clock frequencies at the maximum lane performance.|||||||||||



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Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## _Table 68:_ **Maximum Performance for Interlaken 6 x 25.78125 Gb/s and 6 x 28.21 Gb/s Protocol and Lane Logic Mode Designs** 

|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|---|---|---|---|---|
|_Table 68:_**Maximum Performance for Interlaken 6 x 25.78125 Gb/s and 6 x 28.21 Gb/s Protocol and**<br>**Lane Logic Mode Designs**|||||||||||
|**Symbol**|**Description**|**Speed Grade and VCCINT Operating Voltages**||||||||**Units**|
|||**0.90V**||**0.85V**||||**0.72V**|||
|||**-3**1||**-2**1||**-1**||**-2**|||
|FRX_SERDES_CLK|Receive serializer/ deserializer clock|440.79||440.79||N/A||402.84||MHz|
|FTX_SERDES_CLK|Transmit serializer/ deserializer clock|440.79||440.79||N/A||402.84||MHz|
|FDRP_CLK|Dynamic reconfiguration port clock|250.00||250.00||N/A||250.00||MHz|
|||Min2|Max|Min2|Max|Min|Max|Min2|Max||
|FCORE_CLK|Interlaken core clock|412.503|479.20|412.503|479.20|N/A||412.50|429.69|MHz|
|FLBUS_CLK|Interlaken local bus clock|300.004|349.52|300.004|349.52|N/A||300.00|349.52|MHz|
|**Notes:**<br>1.<br>6 x 28.21 mode is only supported in the -2 (VCCINT= 0.85V) and -3 (VCCINT= 0.90V) speed grades.<br>2.<br>These are the minimum clock frequencies at the maximum lane performance.<br>3.<br>The minimum value for CORE_CLK is 451.36 MHz for the 6 x 28.21 Gb/s protocol.<br>4.<br>The minimum value for LBUS_CLK is 330.00 MHz for the 6 x 28.21 Gb/s protocol.|||||||||||



## _Table 69:_ **Maximum Performance for Interlaken 12 x 25.78125 Gb/s Lane Logic Only Mode Designs** 

|_Table 69:_**Maximum Performance for Interlaken 12 x 25.78125 Gb/s Lane Logic Only Mode Designs**|_Table 69:_**Maximum Performance for Interlaken 12 x 25.78125 Gb/s Lane Logic Only Mode Designs**|_Table 69:_**Maximum Performance for Interlaken 12 x 25.78125 Gb/s Lane Logic Only Mode Designs**|_Table 69:_**Maximum Performance for Interlaken 12 x 25.78125 Gb/s Lane Logic Only Mode Designs**|_Table 69:_**Maximum Performance for Interlaken 12 x 25.78125 Gb/s Lane Logic Only Mode Designs**|_Table 69:_**Maximum Performance for Interlaken 12 x 25.78125 Gb/s Lane Logic Only Mode Designs**|_Table 69:_**Maximum Performance for Interlaken 12 x 25.78125 Gb/s Lane Logic Only Mode Designs**|
|---|---|---|---|---|---|---|
|**Symbol**|**Description**|**Speed Grade and VCCINT Operating Voltages**||||**Units**|
|||**0.90V**|**0.85V**||**0.72V**||
|||**-3**|**-2**|**-1**|**-2**||
|FRX_SERDES_CLK|Receive serializer/ deserializer clock|402.84|402.84|N/A|N/A|MHz|
|FTX_SERDES_CLK|Transmit serializer/ deserializer clock|402.84|402.84|N/A|N/A|MHz|
|FDRP_CLK|Dynamic reconfiguration port clock|250.00|250.00|N/A|N/A|MHz|
|FCORE_CLK|Interlaken core clock|412.50|412.50|N/A|N/A|MHz|
|FLBUS_CLK|Interlaken local bus clock|349.52|349.52|N/A|N/A|MHz|



## **Integrated Interface Block for 100G Ethernet MAC and PCS** 

More information and documentation on solutions using the integrated 100 Gb/s Ethernet block can be found at UltraScale+ Integrated 100G Ethernet MAC/PCS. The _UltraScale Architecture and Product Data Sheet: Overview_ (DS890) lists how many blocks are in each Virtex UltraScale+ FPGA. 

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Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## _Table 70:_ **Maximum Performance for 100G Ethernet Designs** 

|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|---|
|_Table 70:_**Maximum Performance for 100G Ethernet Designs**|||||||
|**Symbol**|**Description**|**Speed Grade and VCCINT Operating Voltages**||||**Units**|
|||**0.90V**|**0.85V**||**0.72V**||
|||**-3**|**-2**|**-1**|**-2**||
|CAUI-10 Mode|||||||
|FTX_CLK|Transmit clock|390.625|390.625|322.266|322.266|MHz|
|FRX_CLK|Receive clock|390.625|390.625|322.266|322.266|MHz|
|FRX_SERDES_CLK|Receive serializer/deserializer clock|390.625|390.625|322.266|322.266|MHz|
|FDRP_CLK|Dynamic reconfiguration port clock|250.00|250.00|250.00|250.00|MHz|
|CAUI-4, CAUI-4 + RS-FEC, and RS-FEC Transcode Bypass Modes|||||||
|FTX_CLK|Transmit clock|390.625|322.266|322.266|322.266|MHz|
|FRX_CLK|Receive clock|390.625|322.266|322.266|322.266|MHz|
|FRX_SERDES_CLK|Receive serializer/deserializer clock|390.625|322.266|322.266|322.266|MHz|
|FDRP_CLK|Dynamic reconfiguration port clock|250.00|250.00|250.00|250.00|MHz|



## **Integrated Interface Block for PCI Express Designs** 

More information and documentation on solutions for PCI Express[®] designs can be found at PCI Express. The _UltraScale Architecture and Product Data Sheet: Overview_ (DS890) lists how many blocks are in each Virtex UltraScale+ FPGA. Devices with HBM contain a mixture of PCIE4 and PCIE4C blocks. The PCIE4C blocks are augmented with support for the CCIX protocol and additional timing enhancements allowing the PCIE4C blocks to run Gen3 x16 when VCCINT = 0.72V. 

_Table 71:_ **Maximum Performance for PCIE4-based PCI Express Designs** 

|_Table 71:_**Maximum Performance for PCIE4-based PCI Express Designs**|_Table 71:_**Maximum Performance for PCIE4-based PCI Express Designs**|_Table 71:_**Maximum Performance for PCIE4-based PCI Express Designs**|_Table 71:_**Maximum Performance for PCIE4-based PCI Express Designs**|_Table 71:_**Maximum Performance for PCIE4-based PCI Express Designs**|_Table 71:_**Maximum Performance for PCIE4-based PCI Express Designs**|_Table 71:_**Maximum Performance for PCIE4-based PCI Express Designs**|
|---|---|---|---|---|---|---|
|**Symbol**|**Description**|**Speed Grade and VCCINT Operating Voltages**||||**Units**|
|||**0.90V**|**0.85V**||**0.72V**||
|||**-3**|**-2**|**-1**|**-2**||
|FPIPECLK|Pipe clock maximum frequency|250.00|250.00|250.00|250.00|MHz|
|FCORECLK|Core clock maximum frequency|500.00|500.00|500.00|250.00|MHz|
|FDRPCLK|DRP clock maximum frequency|250.00|250.00|250.00|250.00|MHz|
|FMCAPCLK|MCAP clock maximum frequency|125.00|125.00|125.00|125.00|MHz|



## _Table 72:_ **Maximum Performance for PCIE4C-based PCI Express and CCIX Designs** 

|_Table 72:_**Maximum Performance for PCIE4C-based PCI Express and CCIX Designs**|_Table 72:_**Maximum Performance for PCIE4C-based PCI Express and CCIX Designs**|_Table 72:_**Maximum Performance for PCIE4C-based PCI Express and CCIX Designs**|_Table 72:_**Maximum Performance for PCIE4C-based PCI Express and CCIX Designs**|_Table 72:_**Maximum Performance for PCIE4C-based PCI Express and CCIX Designs**|_Table 72:_**Maximum Performance for PCIE4C-based PCI Express and CCIX Designs**|_Table 72:_**Maximum Performance for PCIE4C-based PCI Express and CCIX Designs**|
|---|---|---|---|---|---|---|
|**Symbol**|**Description**|**Speed Grade and VCCINT Operating Voltages**||||**Units**|
|||**0.90V**|**0.85V**||**0.72V**||
|||**-3**|**-2**|**-1**|**-2**||
|FPIPECLK|Pipe clock maximum frequency|250.00|250.00|250.00|250.00|MHz|
|FCORECLK|Core clock maximum frequency|500.00|500.00|500.00|500.00|MHz|
|FCORECLKCCIX|CCIX TL interface clock maximum frequency|500.00|500.00|500.00|N/A|MHz|
|FDRPCLK|DRP clock maximum frequency|250.00|250.00|250.00|250.00|MHz|
|FMCAPCLK|MCAP clock maximum frequency|125.00|125.00|125.00|125.00|MHz|



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Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## **High Bandwidth Memory Controller** 

The _UltraScale Architecture and Product Data Sheet: Overview_ (DS890) lists the Virtex UltraScale+ FPGAs with integrated high-bandwidth memory (HBM). 

_Table 73:_ **Maximum Performance for High Bandwidth Memory Controller** 

|**High Bandwidth Memory Controller**<br>The_UltraScale Architecture and Product Data Sheet: Overview_(DS890) lists the Virtex UltraScale+ FPGAs with<br>integrated high-bandwidth memory (HBM).|**High Bandwidth Memory Controller**<br>The_UltraScale Architecture and Product Data Sheet: Overview_(DS890) lists the Virtex UltraScale+ FPGAs with<br>integrated high-bandwidth memory (HBM).|**High Bandwidth Memory Controller**<br>The_UltraScale Architecture and Product Data Sheet: Overview_(DS890) lists the Virtex UltraScale+ FPGAs with<br>integrated high-bandwidth memory (HBM).|**High Bandwidth Memory Controller**<br>The_UltraScale Architecture and Product Data Sheet: Overview_(DS890) lists the Virtex UltraScale+ FPGAs with<br>integrated high-bandwidth memory (HBM).|**High Bandwidth Memory Controller**<br>The_UltraScale Architecture and Product Data Sheet: Overview_(DS890) lists the Virtex UltraScale+ FPGAs with<br>integrated high-bandwidth memory (HBM).|**High Bandwidth Memory Controller**<br>The_UltraScale Architecture and Product Data Sheet: Overview_(DS890) lists the Virtex UltraScale+ FPGAs with<br>integrated high-bandwidth memory (HBM).|**High Bandwidth Memory Controller**<br>The_UltraScale Architecture and Product Data Sheet: Overview_(DS890) lists the Virtex UltraScale+ FPGAs with<br>integrated high-bandwidth memory (HBM).|
|---|---|---|---|---|---|---|
|_Table 73:_**Maximum Performance for High Bandwidth Memory Controller**|||||||
|**Symbol**|**Description**|**Speed Grade and VCCINT Operating Voltages**||||**Units**|
|||**0.90V**|**0.85V**||**0.72V**||
|||**-3**|**-2**|**-1**|**-2**||
|FHBM_REF_CLK|HBM controller reference clock maximum frequency|450.00|450.00|450.00|450.00|MHz|
|FACLK|AXI interface clock maximum frequency|450.00|450.00|400.00|400.00|MHz|
|FAPB|Advance peripheral bus (APB) clock maximum<br>frequency|100.00|100.00|100.00|100.00|MHz|
|FHBM|HBM maximum line rate interface to DRAM|1800|1800|1600|1800|Mb/s|



## **System Monitor Specifications** 

_Table 74:_ **System Monitor Specifications** 

|**System Monitor Specifications**|**System Monitor Specifications**|**System Monitor Specifications**|**System Monitor Specifications**|**System Monitor Specifications**|**System Monitor Specifications**|**System Monitor Specifications**|
|---|---|---|---|---|---|---|
|_Table 74:_**System Monitor Specifications**|||||||
|**Parameter**|**Symbol**|**Comments/Conditions**|**Min**|**Typ**|**Max**|**Units**|
|VCCADC= 1.8V ±3%, VREFP= 1.25V, VREFN= 0V, ADCCLK = 5.2 MHz, Tj= –40°C to 100°C, typical values at Tj= 40°C|||||||
|ADC Accuracy1|||||||
|Resolution|||10|–|–|Bits|
|Integral nonlinearity2|INL||–|–|±1.5|LSBs|
|Differential nonlinearity|DNL|No missing codes, guaranteed monotonic|–|–|±1|LSBs|
|Offset error||Offset calibration enabled|–|–|±2|LSBs|
|Gain error|||–|–|±0.4|%|
|Sample rate|||–|–|0.2|MS/s|
|RMS code noise||External 1.25V reference|–|–|1|LSBs|
|||On-chip reference|–|1|–|LSBs|
|ADC Accuracy at Extended Temperatures|||||||
|Resolution||Tj= –55°C to 125°C|10|–|–|Bits|
|Integral nonlinearity2|INL|Tj= –55°C to 125°C|–|–|±1.5|LSBs|
|Differential nonlinearity|DNL|No missing codes, guaranteed monotonic<br>Tj= –55°C to 125°C|–|–|±1||
|Analog Inputs2|||||||
|ADC input ranges||Unipolar operation|0|–|1|V|
|||Bipolar operation|–0.5|–|+0.5|V|
|||Unipolar common mode range (FS input)|0|–|+0.5|V|
|||Bipolar common mode range (FS input)|+0.5|–|+0.6|V|
|Maximum external channel input ranges||Adjacent channels set within these ranges should<br>not corrupt measurements on adjacent channels|–0.1|–|VCCADC|V|



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Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## _Table 74:_ **System Monitor Specifications** _(cont'd)_ 

|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|---|
|_Table 74:_**System Monitor Specifications**_(cont'd)_|||||||
|**Parameter**|**Symbol**|**Comments/Conditions**|**Min**|**Typ**|**Max**|**Units**|
|On-Chip Sensor Accuracy|||||||
|Temperature sensor error1,3||Tj= –55°C to 125°C (with external REF)|–|–|±3|°C|
|||Tj= –55°C to 110°C (with internal REF)|–|–|±3.5|°C|
|||Tj= 110°C to 125°C (with internal REF)|–|–|±5|°C|
|Supply sensor error4||Supply voltages 0.72V to 1.2V,<br>Tj= –40°C to 100°C (with external REF)|–|–|±0.5|%|
|||Supply voltages 0.72V to 1.2V,<br>Tj= –55°C to 125°C (with external REF)|–|–|±1.0|%|
|||All other supply voltages,<br>Tj= –40°C to 100°C (with external REF)|–|–|±1.0|%|
|||All other supply voltages,<br>Tj= –55°C to 125°C (with external REF)|–|–|±2.0|%|
|||Supply voltages 0.72V to 1.2V,<br>Tj= –40°C to 100°C (with internal REF)|–|–|±1.0|%|
|||Supply voltages 0.72V to 1.2V,<br>Tj= –55°C to 125°C (with internal REF)|–|–|±2.0|%|
|||All other supply voltages,<br>Tj= –40°C to 100°C (with internal REF)|–|–|±1.5|%|
|||All other supply voltages,<br>Tj= –55°C to 125°C (with internal REF)|–|–|±2.5|%|
|Conversion Rate5|||||||
|Conversion time—continuous|tCONV|Number of ADCCLK cycles|26|–|32|Cycles|
|Conversion time—event|tCONV|Number of ADCCLK cycles|–|–|21|Cycles|
|DRP clock frequency|DCLK|DRP clock frequency|8|–|250|MHz|
|ADC clock frequency|ADCCLK|Derived from DCLK|1|–|5.2|MHz|
|DCLK duty cycle|||40|–|60|%|
|SYSMON Reference6|||||||
|External reference|VREFP|Externally supplied reference voltage|1.20|1.25|1.30|V|
|On-chip reference||Ground VREFPpin to AGND, Tj= –40°C to 100°C|1.2375|1.25|1.2625|V|
|||Ground VREFPpin to AGND, Tj= –55°C to 125°C|1.225|1.25|1.275|V|
|**Notes:**<br>1.<br>ADC offset errors are removed by enabling the ADC automatic offset calibration feature. The values are specified for when this feature is<br>enabled.<br>2.<br>See the Analog Input section in the_UltraScale Architecture System Monitor User Guide_(UG580).<br>3.<br>When reading temperature values directly from the PMBus interface, the SYSMON has a +4°C offset due to the transfer function used by<br>the PMBus application. For example, the external REF temperature sensor error’s range of ±3°C becomes +1°C to +7°C when the<br>temperature is read through the PMBus interface.<br>4.<br>Supply sensor offset and gain errors are removed by enabling the automatic offset and gain calibration feature. The values are specified<br>for when this feature is enabled.<br>5.<br>See the Adjusting the Acquisition Settling Time section in the_UltraScale Architecture System Monitor User Guide_(UG580).<br>6.<br>Any variation in the reference voltage from the nominal VREFP= 1.25V and VREFN= 0V will result in a deviation from the ideal transfer<br>function. This also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). However, for<br>external ratiometric type applications allowing reference to vary by ±4% is permitted.|||||||



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Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## **SYSMON I2C/PMBus Interfaces** 

## _Table 75:_ **SYSMON I2C Fast Mode Interface Switching Characteristics** 

|**SYSMON I2C/PMBus Interfaces**|**SYSMON I2C/PMBus Interfaces**|**SYSMON I2C/PMBus Interfaces**|**SYSMON I2C/PMBus Interfaces**|**SYSMON I2C/PMBus Interfaces**|
|---|---|---|---|---|
|_Table 75:_**SYSMON I2C Fast Mode Interface Switching Characteristics**|||||
|**Symbol**|**Description**1|**Min**|**Max**|**Units**|
|TSMFCKL|SCL Low time|1.3|–|µs|
|TSMFCKH|SCL High time|0.6|–|µs|
|TSMFCKO|SDAO clock-to-out delay|–|900|ns|
|TSMFDCK|SDAI setup time|100|–|ns|
|FSMFCLK|SCL clock frequency|–|400|kHz|
|**Notes:**<br>1.<br>The test conditions are configured to the LVCMOS 1.8V I/O standard.|||||



_Table 76:_ **SYSMON I2C Standard Mode Interface Switching Characteristics** 

|_Table 76:_**SYSMON I2C Standard Mode Interface Switching Characteristics**|_Table 76:_**SYSMON I2C Standard Mode Interface Switching Characteristics**|_Table 76:_**SYSMON I2C Standard Mode Interface Switching Characteristics**|_Table 76:_**SYSMON I2C Standard Mode Interface Switching Characteristics**|_Table 76:_**SYSMON I2C Standard Mode Interface Switching Characteristics**|
|---|---|---|---|---|
|**Symbol**|**Description**1|**Min**|**Max**|**Units**|
|TSMSCKL|SCL Low time|4.7|–|µs|
|TSMSCKH|SCL High time|4.0|–|µs|
|TSMSCKO|SDAO clock-to-out delay|–|3450|ns|
|TSMSDCK|SDAI setup time|250|–|ns|
|FSMSCLK|SCL clock frequency|–|100|kHz|
|**Notes:**<br>1.<br>The test conditions are configured to the LVCMOS 1.8V I/O standard.|||||



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Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## **Configuration Switching Characteristics** 

## _Table 77:_ **Configuration Switching Characteristics** 

|_Table 77:_**Configuration Switching Characteristics**|_Table 77:_**Configuration Switching Characteristics**|_Table 77:_**Configuration Switching Characteristics**|_Table 77:_**Configuration Switching Characteristics**|_Table 77:_**Configuration Switching Characteristics**|_Table 77:_**Configuration Switching Characteristics**|_Table 77:_**Configuration Switching Characteristics**|_Table 77:_**Configuration Switching Characteristics**|
|---|---|---|---|---|---|---|---|
|**Symbol**|**Description**||**Speed Grade and VCCINTOperating Voltages**||||**Units**|
||||**0.90V**|**0.85V**||**0.72V**||
||||**-3**|**-2**|**-1**|**-2**||
|Power-up Timing Characteristics||||||||
|TPL|Program latency||8.5|8.5|8.5|8.5|ms, Max|
|TPOR|Power-on reset (40 ms maximum ramp rate)||65|65|65|65|ms, Max|
||||0|0|0|0|ms, Min|
||Power-on reset with POR override (2 ms<br>maximum ramp rate)||15|15|15|15|ms, Max|
||||5|5|5|5|ms, Min|
|TPROGRAM|Program pulse width||250|250|250|250|ns, Min|
|CCLK Output (Master Mode)||||||||
|TICCK|Master CCLK output delay from INIT_B||150|150|150|150|ns, Min|
|TMCCKL1|Master CCLK clock Low time duty cycle||40/60|40/60|40/60|40/60|%, Min/Max|
|TMCCKH|Master CCLK clock High time duty cycle||40/60|40/60|40/60|40/60|%, Min/Max|
|FMCCK|Master BPI (x8/x16)<br>SPI (x1/x2/x4)<br>CCLK frequency|XCVU3P, XQVU3P,<br>XCVU5P, XCVU7P,<br>XQVU7P, XCVU9P|125|125|125|100|MHz, Max|
||Master SPI (x1/x2/x4)<br>CCLK frequency|XCVU11P, XQVU11P,<br>XCVU13P, XCVU27P,<br>XCVU29P, XCVU31P,<br>XCVU33P, XCVU35P,<br>XCVU37P|125|125|125|100|MHz, Max|
||Master BPI (x8/x16)<br>SPI (x8)<br>CCLK frequency|XCVU11P, XQVU11P,<br>XCVU13P, XCVU27P,<br>XCVU29P, XCVU31P,<br>XCVU33P, XCVU35P,<br>XCVU37P|125|125|125|60|MHz, Max|
|FMCCK_START|Master CCLK frequency at start of<br>configuration||2.7|2.7|2.7|2.7|MHz, Typ|
|FMCCKTOL|Frequency tolerance, master mode with<br>respect to nominal CCLK||±15|±15|±15|±15|%, Max|
|CCLK Input (Slave Mode)||||||||
|TSCCKL|Slave CCLK clock minimum Low time||2.5|2.5|2.5|2.5|ns, Min|
|TSCCKH|Slave CCLK clock minimum High time||2.5|2.5|2.5|2.5|ns, Min|



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Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

_Table 77:_ **Configuration Switching Characteristics** _(cont'd)_ 

|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|---|---|
|_Table 77:_**Configuration Switching Characteristics**_(cont'd)_||||||||
|**Symbol**|**Description**||**Speed Grade and VCCINTOperating Voltages**||||**Units**|
||||**0.90V**|**0.85V**||**0.72V**||
||||**-3**|**-2**|**-1**|**-2**||
|FSCCK|Slave Serial/<br>Slave SelectMAP<br>CCLK frequency|XCVU3P, XQVU3P,<br>XCVU5P, XCVU7P,<br>XQVU7P, XCVU9P|125|125|125|100|MHz, Max|
||Slave Serial CCLK<br>frequency|XCVU11P, XQVU11P,<br>XCVU13P, XCVU27P,<br>XCVU29P, XCVU31P,<br>XCVU33P, XCVU35P,<br>XCVU37P|125|125|125|100|MHz, Max|
||Slave SelectMAP CCLK<br>frequency|XCVU11P, XQVU11P,<br>XCVU13P, XCVU27P,<br>XCVU29P, XCVU31P,<br>XCVU33P, XCVU35P,<br>XCVU37P|125|125|125|60|MHz, Max|
|EMCCLK Input (Master Mode)||||||||
|TEMCCKL|External master CCLK Low time||2.5|2.5|2.5|2.5|ns, Min|
|TEMCCKH|External master CCLK High time||2.5|2.5|2.5|2.5|ns, Min|
|FEMCCK|External master CCLK<br>frequency|XCVU3P, XQVU3P,<br>XCVU5P, XCVU7P,<br>XQVU7P, XCVU9P|125|125|125|100|MHz, Max|
|||XCVU11P, XQVU11P,<br>XCVU13P, XCVU27P,<br>XCVU29P, XCVU31P,<br>XCVU33P, XCVU35P,<br>XCVU37P|125|125|125|60|MHz, Max|
|Internal Configuration Access Port||||||||
|FICAPCK|Internal configuration<br>access port (ICAPE3)|XCVU3P, XQVU3P|200|200|200|150|MHz, Max|
||Master SLR ICAPE3<br>accessing entire device|XCVU5P, XCVU7P,<br>XQVU7P, XCVU9P,<br>XCVU11P, XQVU11P,<br>XCVU13P, XCVU27P,<br>XCVU29P, XCVU31P,<br>XCVU33P, XCVU35P,<br>XCVU37P|125|125|125|125|MHz, Max|
||SLR ICAPE3 accessing<br>local SLR|XCVU5P, XCVU7P,<br>XQVU7P, XCVU9P,<br>XCVU11P, XQVU11P,<br>XCVU13P, XCVU27P,<br>XCVU29P, XCVU31P,<br>XCVU33P, XCVU35P,<br>XCVU37P|200|200|200|150|MHz, Max|
|Slave Serial Mode Programming Switching||||||||
|TDCCK/TCCKD|DINsetup/hold||3.0/0|3.0/0|3.0/0|4.0/0|ns, Min|
|TCCO|DOUTclock to out||8.0|8.0|8.0|9.0|ns, Max|
|SelectMAP Mode Programming Switching||||||||
|TSMDCCK/TSMCCKD|D[31:00] setup/hold|XCVU3P, XQVU3P,<br>XCVU5P, XCVU7P,<br>XQVU7P, XCVU9P|4.0/0|4.0/0|4.0/0|5.0/0|ns, Min|
|||XCVU11P, XQVU11P,<br>XCVU13P, XCVU27P,<br>XCVU29P, XCVU31P,<br>XCVU33P, XCVU35P,<br>XCVU37P|4.5/0|4.5/0|4.5/0|8.0/0|ns, Min|



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Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

_Table 77:_ **Configuration Switching Characteristics** _(cont'd)_ 

|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|---|---|
|_Table 77:_**Configuration Switching Characteristics**_(cont'd)_||||||||
|**Symbol**|**Description**||**Speed Grade and VCCINTOperating Voltages**||||**Units**|
||||**0.90V**|**0.85V**||**0.72V**||
||||**-3**|**-2**|**-1**|**-2**||
|TSMCSCCK/TSMCCKCS|CSI_B setup/hold|XCVU3P, XQVU3P,<br>XCVU5P, XCVU7P,<br>XQVU7P, XCVU9P|4.0/0|4.0/0|4.0/0|5.0/0|ns, Min|
|||XCVU11P, XQVU11P,<br>XCVU13P, XCVU27P,<br>XCVU29P, XCVU31P,<br>XCVU33P, XCVU35P,<br>XCVU37P|4.5/0|4.5/0|4.5/0|7.5/0|ns, Min|
|TSMWCCK/TSMCCKW|RDWR_B setup/hold|XCVU3P, XQVU3P,<br>XCVU5P, XCVU7P,<br>XQVU7P, XCVU9P|10.0/0|10.0/0|10.0/0|11.0/0|ns, Min|
|||XCVU11P, XQVU11P,<br>XCVU13P, XCVU27P,<br>XCVU29P, XCVU31P,<br>XCVU33P, XCVU35P,<br>XCVU37P|11.0/0|11.0/0|11.0/0|17.0/0|ns, Min|
|TSMCKCSO|CSO_B clock to out<br>(330Ω pull-up resistor<br>required)|XCVU3P, XQVU3P,<br>XCVU5P, XCVU7P,<br>XQVU7P, XCVU9P|7.0|7.0|7.0|7.0|ns, Max|
|||XCVU11P, XQVU11P,<br>XCVU13P, XCVU27P,<br>XCVU29P, XCVU31P,<br>XCVU33P, XCVU35P,<br>XCVU37P|7.0|7.0|7.0|10.0|ns, Max|
|TSMCO|D[31:00] clock to out in<br>readback|XCVU3P, XQVU3P,<br>XCVU5P, XCVU7P,<br>XQVU7P, XCVU9P|8.0|8.0|8.0|8.0|ns, Max|
|||XCVU11P, XQVU11P,<br>XCVU13P, XCVU27P,<br>XCVU29P, XCVU31P,<br>XCVU33P, XCVU35P,<br>XCVU37P|8.0|8.0|8.0|10.0|ns, Max|
|FRBCCK|Readback frequency|XCVU3P, XQVU3P,<br>XCVU5P, XCVU7P,<br>XQVU7P, XCVU9P|125|125|125|100|MHz, Max|
|||XCVU11P, XQVU11P,<br>XCVU13P, XCVU27P,<br>XCVU29P, XCVU31P,<br>XCVU33P, XCVU35P,<br>XCVU37P|125|125|125|60|MHz, Max|
|Boundary-Scan Port Timing Specifications||||||||
|TTAPTCK/TTCKTAP|TMS and TDI setup/<br>hold|XCVU3P, XQVU3P|3.0/2.0|3.0/2.0|3.0/2.0|3.0/2.0|ns, Min|
|||XCVU5P, XCVU7P,<br>XQVU7P, XCVU9P,<br>XCVU11P, XQVU11P,<br>XCVU13P, XCVU27P,<br>XCVU29P, XCVU31P,<br>XCVU33P, XCVU35P,<br>XCVU37P|8.5/2.0|8.5/2.0|8.5/2.0|8.5/2.0|ns, Min|



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Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

_Table 77:_ **Configuration Switching Characteristics** _(cont'd)_ 

|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|---|---|
|_Table 77:_**Configuration Switching Characteristics**_(cont'd)_||||||||
|**Symbol**|**Description**||**Speed Grade and VCCINTOperating Voltages**||||**Units**|
||||**0.90V**|**0.85V**||**0.72V**||
||||**-3**|**-2**|**-1**|**-2**||
|TTCKTDO|TCK falling edge to<br>TDO output|XCVU3P, XQVU3P|7.0|7.0|7.0|7.0|ns, Max|
|||XCVU5P, XCVU7P,<br>XQVU7P, XCVU9P,<br>XCVU11P, XQVU11P,<br>XCVU13P, XCVU27P,<br>XCVU29P, XCVU31P,<br>XCVU33P, XCVU35P,<br>XCVU37P|15.0|15.0|15.0|15.0|ns, Max|
|FTCK|TCK frequency|XCVU3P, XQVU3P|66|66|66|66|MHz, Max|
|||XCVU5P, XCVU7P,<br>XQVU7P, XCVU9P,<br>XCVU11P, XQVU11P,<br>XCVU13P, XCVU27P,<br>XCVU29P, XCVU31P,<br>XCVU33P, XCVU35P,<br>XCVU37P|20|20|20|20|MHz, Max|
|BPI Master Flash Mode Programming Switching||||||||
|TBPICCO|A[28:00], RS[1:0], FCS_B, FOE_B, FWE_B, ADV_B<br>clock to out||10|10|10|10|ns, Max|
|TBPIDCC/TBPICCD|D[15:00] setup/hold|XCVU3P, XQVU3P,<br>XCVU5P, XCVU7P,<br>XQVU7P, XCVU9P|4.0/0|4.0/0|4.0/0|5.0/0|ns, Min|
|||XCVU11P, XQVU11P,<br>XCVU13P, XCVU27P,<br>XCVU29P, XCVU31P,<br>XCVU33P, XCVU35P,<br>XCVU37P|4.5/0|4.5/0|4.5/0|8.0/0|ns, Min|
|SPI Master Flash Mode Programming Switching||||||||
|TSPIDCC/TSPICCD|D[03:00] setup/hold||3.0/0|3.0/0|3.0/0|4.0/0|ns, Min|
|TSPIDCC/TSPICCD|D[07:04] setup/hold|XCVU3P, XQVU3P,<br>XCVU5P, XCVU7P,<br>XQVU7P, XCVU9P|4.0/0|4.0/0|4.0/0|5.0/0|ns, Min|
|||XCVU11P, XQVU11P,<br>XCVU13P, XCVU27P,<br>XCVU29P, XCVU31P,<br>XCVU33P, XCVU35P,<br>XCVU37P|4.5/0|4.5/0|4.5/0|8.0/0|ns, Min|
|TSPICCM|MOSI clock to out||8.0|8.0|8.0|8.0|ns, Max|
|TSPICCM2|D[04] clock to out||10.0|10.0|10.0|10.0|ns, Max|
|TSPICCFC|FCS_B clock to out||8.0|8.0|8.0|8.0|ns, Max|
|TSPICCFC2|FCS2_B clock to out||10.0|10.0|10.0|10.0|ns, Max|
|DNA Port Switching||||||||
|FDNACK|DNA port frequency||200|200|200|175|MHz, Max|
|STARTUPE3 Ports||||||||
|TUSRCCLKO|STARTUPE3 USRCCLKO input port to CCLK pin<br>output delay||0.25/6.00|0.25/6.50|0.25/7.50|0.25/9.00|ns, Min/Max|
|TDO|DO[3:0] ports to D03-D00 pins output delay||0.25/6.70|0.25/7.70|0.25/8.40|0.25/10.00|ns, Min/Max|
|TDTS|DTS[3:0] ports to D03-D00 pins 3-state delays||0.25/6.70|0.25/7.70|0.25/8.40|0.25/10.00|ns, Min/Max|
|TFCSBO|FCSBO port to FCS_B pin output delay||0.25/6.90|0.25/7.50|0.25/8.40|0.25/9.80|ns, Min/Max|
|TFCSBTS|FCSBTS port to FCS_B pin 3-state delay||0.25/6.90|0.25/7.50|0.25/8.40|0.25/9.80|ns, Min/Max|



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Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## _Table 77:_ **Configuration Switching Characteristics** _(cont'd)_ 

|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|---|
|_Table 77:_**Configuration Switching Characteristics**_(cont'd)_|||||||
|**Symbol**|**Description**|**Speed Grade and VCCINTOperating Voltages**||||**Units**|
|||**0.90V**|**0.85V**||**0.72V**||
|||**-3**|**-2**|**-1**|**-2**||
|TUSRDONEO|USRDONEO port to DONE pin output delay|0.25/8.60|0.25/9.40|0.25/10.50|0.25/12.10|ns, Min/Max|
|TUSRDONETS|USRDONETS port to DONE pin 3-state delay|0.25/8.60|0.25/9.40|0.25/10.50|0.25/12.10|ns, Min/Max|
|TDI|D03-D00 pins to DI[3:0] ports input delay|0.5/2.6|0.5/3.1|0.5/3.5|0.5/4.0|ns, Min/Max|
|FCFGMCLK|STARTUPE3 CFGMCLK output frequency|50|50|50|50|MHz, Typ|
|FCFGMCLKTOL|STARTUPE3 CFGMCLK output frequency<br>tolerance|±15|±15|±15|±15|%, Max|
|TDCI_MATCH|Specifies a stall in the startup cycle until the<br>digitally controlled impedance (DCI) match<br>signals are asserted|4|4|4|4|ms, Max|
|**Notes:**<br>1.<br>When the CCLK is sourced from the EMCCLK pin with a divide-by-one setting, the external EMCCLK must meet this duty-cycle<br>requirement.|||||||



## **Revision History** 

|**Date**|**Version**|**Description of Revisions**|
|---|---|---|
|04/26/2019|1.10|UpdatedTable 16,Table 17, andTable 18to production release the following devices in the Vivado<br>Design Suite.<br>XCVU31P: 2018.3.1 v1.24 (-2E, -2LE, -1E (VCCINT= 0.85V) and -2LE (VCCINT= 0.72V))<br>XCVU33P: 2018.3.1 v1.24 (-2E, -2LE, -1E (VCCINT= 0.85V) and -2LE (VCCINT= 0.72V))<br>XCVU37P: 2018.3.1 v1.24 (-2E, -2LE, -1E (VCCINT= 0.85V) and -2LE (VCCINT= 0.72V))<br>XCVU39P: 2018.3.1 v1.24 (-2E, -2LE, -1E (VCCINT= 0.85V) and -2LE (VCCINT= 0.72V))<br>XQVU3P: 2018.3 v1.23<br>XQVU7P: 2018.3.1 v1.23<br>XQVU11P: 2018.3.1 v1.23<br>InTable 1, revised the TSTG.<br>Added Note14inTable 2.<br>Updated the VU3xP values inTable 6.<br>Added LVDS component mode notes toFPGA Logic Performance Characteristics.|
|01/04/2019|1.9|Added the XCVU27P and XCVU29P devices. Also added theGTM Transceiver Specifications.<br>Updated the calculations inTable 6: Power-on Current by Device<br>Updated the speed specification version by device forTable 16to Vivado Design Suite 2018.3.<br>Updated the VIDIFFdescription inTable 15.<br>InTable 51, updated Note2.<br>Removed PCI Express Gen4 support inTable 71: Maximum Performance for PCIE4-based PCI Express<br>Designsand Notes 1, Note 2, and Note 3. InTable 72: Maximum Performance for PCIE4C-based PCI<br>Express and CCIX Designs, removed Notes 1, 2, 3, 4, and 5.|
|08/01/2018|1.8|Added XCVU3xP data toTable 5.<br>Updated the speed specification version by device forTable 16to Vivado Design Suite 2018.2.1.<br>InTable 20, added Note4to the LVDS RX DDR maximum data.<br>InTable 70, revised the calculated values from 322.223 to 322.266.|
|06/18/2018|1.7|Revised the speed grade -1 (VCCINT= 0.85)FGTYMAXinTable 46, which also revised values inTable 51and<br>added Note2.<br>RevisedFACLKand addedFHBMtoTable 73.|



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Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

|**Date**|**Version**|**Description of Revisions**|
|---|---|---|
|04/09/2018|1.6|Added the XCVU31P, XCVU33P, XCVU35P, and XCVU37P devices throughout the data sheet. Added the<br>specifications for High Bandwidth Memory toTable 1,Table 2,Table 5, thePower-On/Off Power Supply<br>Sequencingsection,Table 6,Table 7, andTable 73.<br>UpdatedTable 16,Table 17, andTable 18to production release the following devices in Vivado Design<br>Suite 2018.1 v1.19.<br>XCVU3P: -3E (VCCINT= 0.90V)<br>XCVU5P: -3E (VCCINT= 0.90V)<br>XCVU7P: -3E (VCCINT= 0.90V)<br>XCVU9P: -3E (VCCINT= 0.90V)<br>AddedTable 38andTable 41. Added Note2and Note3toTable 40. RevisedTable 70to add specifc mode<br>specifications and remove Note 1. AddedTable 72.|
|02/07/2018|1.5|UpdatedTable 16,Table 17, andTable 18to production release the following devices in Vivado Design<br>Suite 2017.4.1 v1.18.<br>XCVU11P: -3E (VCCINT= 0.90V)<br>XCVU13P: -3E (VCCINT= 0.90V)<br>Revised some of the -3E (VCCINT= 0.90V) speed files inTable 35,Table 36,Table 37, andTable 39.<br>Revised the DVPPOUTcontrol signal inTable 43.|
|11/28/2017|1.4|InTable 1, corrected the minimum voltage for theSystem Monitorsection.<br>UpdatedTable 16,Table 17, andTable 18to production release all the -2LE (VCCINT= 0.85V) and -2LE<br>(VCCINT= 0.72V) devices/speed/temperature grades in Vivado Design Suite 2017.3.1.<br>Revised theFREFCLKdescriptions inTable 30.<br>Revised some of the -3E and -2LE (VCCINT= 0.72V) speed files inTable 35,Table 36,Table 37,Table 39, and<br>added package values toTable 42.<br>Revised theFGTYQRANGE2-1 speed grade minimum inTable 46. AddedTSPICCM2andTSPICCFC2toTable 77.|
|10/02/2017|1.3|UpdatedTable 1to include maximum TSOL<br>UpdatedTable 16,Table 17, and for dry rework and reflow soldering.Table 18to production release the<br>following devices/speed/temperature grades in Vivado Design Suite 2017.2.1.<br>XCVU11P: -2E, -2I, -1E, -1I<br>XCVU13P: -2E, -2I, -1E, -1I<br>InTable 24, revised the TOUTBUF_DELAY_O_PAD-2 (VCCINTfor dry r = 0.85V) values for DIFF_SSTL135_S,<br>DIFF_SSTL15_DCI_S, DIFF_SSTL15_S, DIFF_SSTL18_I_DCI_S, and DIFF_SSTL18_I_S.<br>Revised some of the -3E and -2LE (VCCINT= 0.72V) speed files inTable 24,Table 35,Table 36, andTable 37.|
|06/27/2017|1.2|UpdatedTable 16,Table 17, andTable 18to production release the following devices/speed/temperature<br>grades in Vivado Design Suite 2017.2.<br>XCVU5P: -2E, -2I, -1E, -1I<br>XCVU7P: -2E, -2I, -1E, -1I<br>XCVU9P: -2E, -2I, -1E, -1I<br>Updated Note 12 inTable 2for clarity. InTable 3, removed unsupported voltages (2.5V and 3.3V) from<br>IRPUand IRPD. Added Note 3 toTable 23. Revised the -3E and -2LE (VCCINT= 0.72V) speed files inTable 24,<br>Table 25,Table 35,Table 36,Table 37, andTable 39. InTable 26removed from the input delay<br>measurement methodology section the following class II I/O standards: SSTL135_II, SSTL15_II, SSTL18_II,<br>DIFF_SSTL135_II, DIFF_SSTL15_II and DIFF_SSTL18_II. Updated the FMAXsymbol names and values inTable<br>29. Added Note 1 toTable 31. Added Note 3 toTable 71. InTable 77, updated the -2LE (VCCINT= 0.72V)<br>specifications for FMCCK, FSCCK, FEMCCK, FICAPCK, TSMDCCK/TSMCCKD, TSMCKCSO, TSMCO, FRBCCK, TBPIDCC/TBPICCD,<br>and TSPIDCC/TSPICCD.|
|04/19/2017|1.1|Updated theSummarydescription. InTable 1, updated Note 6, added data, and added Note 7, Note 8,<br>and Note 9. Updated and added data toTable 2throughTable 6.<br>Removed the -1LI speed grade.<br>UpdatedTable 16,Table 17, andTable 18to production release in Vivado Design Suite 2017.1 for the<br>XCVU3P: -2E, -2I, -1E, -1I.<br>UpdatedTable 15. Added Note 1 toTable 17. UpdatedTable 19,Table 20,Table 24,Table 25,Table 26,<br>Table 28,Table 29, andTable 30. AddedTable 21. Added MMCM_FDPRCLK_MAXtoTable 33and<br>PLL_FDPRCLK_MAXtoTable 34. Updated to Vivado Design Suite 2017.1Table 35,Table 36,Table 37, and<br>Table 39. Added data toTable 40andTable 42. Updated theGTY Transceiver Specificationssection.<br>Revised theIntegrated Interface Block for Interlakensection. Updated theSystem Monitor Specifications<br>section adding notes to the tables. Updated theConfiguration Switching Characteristicssection.<br>Removed the eFUSE Programming Conditions table and added the specifications toTable 2andTable 3.<br>Updated the Automotive Applications Disclaimer.|
|04/20/2016|1.0|Initial Xilinx release.|



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legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in such critical applications, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos. 

## **AUTOMOTIVE APPLICATIONS DISCLAIMER** 

AUTOMOTIVE PRODUCTS (IDENTIFIED AS "XA" IN THE PART NUMBER) ARE NOT WARRANTED FOR USE IN THE DEPLOYMENT OF AIRBAGS OR FOR USE IN APPLICATIONS THAT AFFECT CONTROL OF A VEHICLE ("SAFETY APPLICATION") UNLESS THERE IS A SAFETY CONCEPT OR REDUNDANCY FEATURE CONSISTENT WITH THE ISO 26262 AUTOMOTIVE SAFETY STANDARD ("SAFETY DESIGN"). CUSTOMER SHALL, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE PRODUCTS, THOROUGHLY TEST SUCH SYSTEMS FOR SAFETY PURPOSES. USE OF PRODUCTS IN A SAFETY APPLICATION WITHOUT A SAFETY DESIGN IS FULLY AT THE RISK OF CUSTOMER, SUBJECT ONLY TO APPLICABLE LAWS AND REGULATIONS GOVERNING LIMITATIONS ON PRODUCT LIABILITY. 

DS923 (v1.10) April 26, 2019 Product Specification 

www.xilinx.com 

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Updated at June 5, 2026
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