XCSU35P-1CMVA361E

FPGA, Spartan UltraScale+, 304 I/O's, 35700 Logic Cells, 1 Speed Grade, 0 to 110°C, CSBGA-361

⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
Manufacturer: AMD
Product type: FPGAs
SVHC: No SVHC (21-Jan-2025)
FPGA Type: SRAM based FPGA
IC Mounting: Surface Mount
No. of Pins: 361Pins
Speed Grade: 1
Product Range: Spartan UltraScale+ Series
Qualification: -
No.of User I/Os: 304I/O's
IC Case / Package: CSBGA
No. of Logic Cells: 35700Logic Cells
Process Technology: 16nm
Operating Temperature Max: 110°C
Operating Temperature Min: 0°C
Delivery and price
Units per pack	1
Price	29.97 €
Current stock	200+
Lead time	30 days
Datasheet
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# **Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics** 

DS930 (v1.0) January 24, 2025 

**Advance Product Specification** 

## **Summary** 

The AMD Spartan™ UltraScale+™ FPGAs are available in -2 and -1 speed grades, with -2E and -2I devices having the highest performance. Some -1LI devices can operate at a VCCINT voltage at 0.85V or 0.72V and provide lower maximum static power. When operated at VCCINT = 0.85V, using a -1LI device, the speed specification for the L devices is the same as the -1I speed grade. When operated at VCCINT = 0.72V, the -1LI performance and static and dynamic power is reduced. 

DC and AC characteristics are specified in extended (E) and industrial (I) temperature ranges. Except the operating temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -1 speed grade extended device are the same as for a -1 speed grade industrial device). However, only selected speed grades and/or devices are available in each temperature range. 

All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters included are common to popular designs and typical applications. 

This data sheet, part of an overall set of documentation on the Spartan UltraScale+ FPGAs, is available on the AMD Technical Information Portal. 

## **DC Characteristics** 

## **Absolute Maximum Ratings** 

_Table 1:_ **Absolute Maximum Ratings** 

|**Absolute Maximum Ratings**|**Absolute Maximum Ratings**|**Absolute Maximum Ratings**|**Absolute Maximum Ratings**|**Absolute Maximum Ratings**|
|---|---|---|---|---|
|_Table 1:_**Absolute Maximum Ratings**|||||
|**Symbol**|**Description1**|**Min**|**Max**|**Units**|
|**FPGA Logic**|||||
|VCCINT|Internal supply voltage|–0.500|1.000|V|
|VCCINT_IO2|Internal supply voltage for the I/O banks|–0.500|0.980|V|
|VCCAUX3|Auxiliary supply voltage|–0.500|1.960|V|
|VCCBRAM2|Supply voltage for the block RAM and UltraRAM|–0.500|0.980|V|



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Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## _Table 1:_ **Absolute Maximum Ratings** _(cont'd)_ 

|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|
|_Table 1:_**Absolute Maximum Ratings**_(cont'd)_|||||
|**Symbol**|**Description1**|**Min**|**Max**|**Units**|
|VCCO|Output drivers supply voltage for HD I/O banks|–0.500|3.400|V|
||Output drivers supply voltage for HP I/O banks and configuration<br>bank 0|–0.500|1.960|V|
||Output drivers supply voltage for XP5IO banks|–0.500|1.650|V|
|VCCAUX_IO3|Auxiliary supply voltage for the I/O banks. Available as VCCAUX_HDIO<br>for HD I/O banks and VCCAUX_HPIOfor HP I/O banks.|–0.500|1.960|V|
|VREF|Input reference voltage for HP I/O banks|–0.500|2.000|V|
|VIN4,5,6,7|I/O input voltage for HD I/O, HP I/O, and XP5IO I/O banks|–0.550|VCCO+ 0.550|V|
|IDC|Available output current at the pad|–20|20|mA|
|IRMS|Available RMS output current at the pad|–20|20|mA|
|**GTH Transceiver8**|||||
|VMGTAVCC|Analog supply voltage for transceiver circuits|–0.500|1.000|V|
|VMGTAVTT|Analog supply voltage for transceiver termination circuits|–0.500|1.300|V|
|VMGTVCCAUX|Auxiliary analog Quad PLL (QPLL) voltage supply for transceivers|–0.500|1.900|V|
|VMGTREFCLK|Transceiver reference clock absolute input voltage|–0.500|1.300|V|
|VMGTAVTTRCAL|Analog supply voltage for the resistor calibration circuit of the<br>transceiver column|–0.500|1.300|V|
|VIN|Receiver (RXP/RXN) and transmitter (TXP/TXN) absolute input<br>voltage|–0.500|1.200|V|
|IDCIN-FLOAT|DC input current for receiver input pins DC coupled RX<br>termination = floating9|–|10|mA|
|IDCIN-MGTAVTT|DC input current for receiver input pins DC coupled RX<br>termination = VMGTAVTT|–|10|mA|
|IDCIN-GND|DC input current for receiver input pins DC coupled RX<br>termination = GND|–|0|mA|
|IDCIN-PROG|DC input current for receiver input pins DC coupled RX<br>termination = programmable10|–|0|mA|
|IDCOUT-FLOAT|DC output current for transmitter pins DC coupled RX<br>termination = floating|–|6|mA|
|IDCOUT-MGTAVTT|DC output current for transmitter pins DC coupled RX<br>termination = VMGTAVTT|–|6|mA|
|**System Monitor**|||||
|VCCADC|System Monitor supply relative to GNDADC|–0.500|2.000|V|
|VREFP|System Monitor reference input relative to GNDADC|–0.500|2.000|V|
|**Temperature11**|||||
|TSTG|Storage temperature (ambient)|–65|150|°C|
|TSOL|Maximum dry rework soldering temperature|–|260|°C|
||Maximum reflow soldering temperature for SBVC529, SBVB625,<br>SBVF784, SBVG784, SBVA1024, and FSVG1156 packages|–|250|°C|
||Maximum reflow soldering temperature for CMVA361, CMVA529,<br>and CMVB529 packages|–|245|°C|



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Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## _Table 1:_ **Absolute Maximum Ratings** _(cont'd)_ 

|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|
|_Table 1:_**Absolute Maximum Ratings**_(cont'd)_|||||
|**Symbol**|**Description1**|**Min**|**Max**|**Units**|
|Tj|Maximum junction temperature|–|125|°C|
|**Notes:**<br>1.<br>Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings<br>only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not<br>implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.<br>2.<br>VCCINT_IOmust be connected to VCCBRAM.<br>3.<br>VCCAUX_HPIOand VCCAUX_HDIOmust be connected to VCCAUX.<br>4.<br>The lower absolute voltage specification always applies.<br>5.<br>For I/O operation, see the_Spartan UltraScale+ FPGAs SelectIO Resources User Guide_(UG861).<br>6.<br>When operating outside of the recommended operating conditions, refer toTable 4andTable 5for maximum overshoot and<br>undershoot specifications.<br>7.<br>VINfor the POR_OVERRIDE pin is unique. POR_OVERRIDE must be connected to either GND (default) or VCCINT. See TPORinConfiguration<br>Switching Characteristicsfor additional information.<br>8.<br>For more information on supported GTH transceiver terminations see the_UltraScale Architecture GTH Transceivers User Guide_(UG576).<br>9.<br>AC coupled operation is not supported for RX termination = floating.<br>10.<br>DC coupled operation is not supported for RX termination = programmable.<br>11.<br>For soldering guidelines and thermal considerations, see the_UltraScale and UltraScale+ FPGAs Packaging and Pinouts Product Specification_<br>(UG575).|||||



## **Recommended Operating Conditions** 

_Table 2:_ **Recommended Operating Conditions** 

|**Recommended Operating Conditions**|**Recommended Operating Conditions**|**Recommended Operating Conditions**|**Recommended Operating Conditions**|**Recommended Operating Conditions**|**Recommended Operating Conditions**|
|---|---|---|---|---|---|
|_Table 2:_**Recommended Operating Conditions**||||||
|**Symbol**|**Description1, 2**|**Min**|**Typ**|**Max**|**Units**|
|**FPGA Logic**||||||
|VCCINT|Internal supply voltage|0.825|0.850|0.876|V|
||For -1LI (VCCINT= 0.72V) devices: internal supply voltage|0.698|0.720|0.742|V|
|VCCINT_IO3|Internal supply voltage for the I/O banks|0.825|0.850|0.876|V|
|VCCBRAM3|Block RAM and UltraRAM supply voltage|0.825|0.850|0.876|V|
|VCCAUX8|Auxiliary supply voltage|1.746|1.800|1.854|V|
|VCCO4|Supply voltage for HD I/O banks5|1.164|–|3.400|V|
||Supply voltage for HP I/O banks and configuration bank 06|0.970|–|1.854|V|
||Supply voltage for XP5IO I/O banks7|0.970|–|1.545|V|
|VCCAUX_IO8|Auxiliary I/O supply voltage. Available as VCCAUX_HDIOfor HD I/O<br>banks and VCCAUX_HPIOfor HP I/O banks.|1.746|1.800|1.854|V|
|VIN9,10|I/O input voltage|–0.200|–|VCCO+ 0.200|V|
|IIN11|Maximum current through any pin in a powered or unpowered<br>bank when forward biasing the clamp diode|–|–|10|mA|
|**GTH Transceiver**||||||
|VMGTAVCC12|Analog supply voltage for the GTH transceiver|0.873|0.900|0.927|V|
|VMGTAVTT12|Analog supply voltage for the GTH transmitter and receiver<br>termination circuits|1.164|1.200|1.236|V|
|VMGTVCCAUX12|Auxiliary analog QPLL voltage supply for the transceivers|1.746|1.800|1.854|V|
|VMGTAVTTRCAL12|Analog supply voltage for the resistor calibration circuit of the<br>GTH transceiver column|1.164|1.200|1.236|V|
|**System Monitor**||||||
|VCCADC|System Monitor supply relative to GNDADC|1.746|1.800|1.854|V|



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Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

_Table 2:_ **Recommended Operating Conditions** _(cont'd)_ 

|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|
|_Table 2:_**Recommended Operating Conditions**_(cont'd)_||||||
|**Symbol**|**Description1, 2**|**Min**|**Typ**|**Max**|**Units**|
|VREFP|System Monitor externally supplied reference voltage relative to<br>GNDADC|1.200|1.250|1.300|V|
|**Temperature**||||||
|Tj13|Junction temperature operating range for extended (E)<br>temperature devices|0|–|100|°C|
||Junction temperature operating range for industrial (I)<br>temperature devices|–40|–|100|°C|
||Junction temperature operating range for eFUSE programming14|–40|–|125|°C|
|**Notes:**<br>1.<br>All voltages are relative to GND, assuming supplies are present.<br>2.<br>For the design of the power distribution system consult the_UltraScale Architecture PCB Design User Guide_(UG583).<br>3.<br>VCCINT_IOmust be connected to VCCBRAM.<br>4.<br>For VCCO_0, the recommended nominal operating voltage is 1.5V or 1.8V, and the minimum voltage for power on and during<br>configuration is 1.455V.<br>5.<br>Includes VCCOof 1.2V, 1.35V, 1.5V, 1.8V, 2.5V, and 3.3V at ±3%.<br>6.<br>Includes VCCOof 1.0V, 1.2V, 1.35V, 1.5V, and 1.8V at ±3%.<br>7.<br>Includes VCCOof 1.0V, 1.1V, 1.2V, 1.35V, and 1.5V at ±3%.<br>8.<br>VCCAUX_IOmust be connected to VCCAUX.<br>9.<br>The lower absolute voltage specification always applies.<br>10.<br>VINfor the POR_OVERRIDE pin is unique. POR_OVERRIDE must be connected to either GND (default) or VCCINT. See TPORinConfiguration<br>Switching Characteristicsfor additional information.<br>11.<br>A total of 200 mA per bank should not be exceeded.<br>12.<br>Each voltage listed requires filtering as described in the_UltraScale Architecture GTH Transceivers User Guide_(UG576).<br>13.<br>AMD recommends measuring the Tjof a device using the system monitor as described in the_UltraScale Architecture System Monitor User_<br>_Guide_(UG580). The system monitor temperature measurement errors (that are described inTable 58) must be accounted for in your<br>design. For example, when using the system monitor with an external reference of 1.25V, and when the system monitor reports 97°C,<br>there is a measurement error ±3°C. A reading of 97°C is considered the maximum adjusted Tj(100°C – 3°C = 97°C).<br>14.<br>Do not program eFUSE during device configuration (e.g., during configuration, during configuration readback, or when readback CRC is<br>active).||||||



## **DC Characteristics Over Recommended Operating Conditions** 

## _Table 3:_ **DC Characteristics Over Recommended Operating Conditions** 

|**DC Characteristics Over Recommended Operating Conditions**|**DC Characteristics Over Recommended Operating Conditions**|**DC Characteristics Over Recommended Operating Conditions**|**DC Characteristics Over Recommended Operating Conditions**|**DC Characteristics Over Recommended Operating Conditions**|**DC Characteristics Over Recommended Operating Conditions**|
|---|---|---|---|---|---|
|_Table 3:_**DC Characteristics Over Recommended Operating Conditions**||||||
|**Symbol**|**Description**|**Min**|**Typ1**|**Max**|**Units**|
|VDRINT|Data retention VCCINTvoltage (below which configuration data<br>might be lost)|0.68|–|–|V|
|VDRAUX|Data retention VCCAUXvoltage (below which configuration data<br>might be lost)|1.5|–|–|V|
|IREF|VREFleakage current per pin|–|–|15|µA|
|IL|Input or output leakage current per pin (HD I/O and HP I/O2)<br>(sample-tested)|–|–|15|µA|
||Input or output leakage current per pin (XP5IO I/O) (sample-<br>tested)|–|–|100|µA|
|CIN3|Die input capacitance at the pad (HP I/O)|–|–|3.1|pF|
||Die input capacitance at the pad (HD I/O)|–|–|4.75|pF|
||Die input capacitance at the pad (XP5IO I/O)|–|–|1.90|pF|



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Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## _Table 3:_ **DC Characteristics Over Recommended Operating Conditions** _(cont'd)_ 

|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|
|_Table 3:_**DC Characteristics Over Recommended Operating Conditions**_(cont'd)_||||||
|**Symbol**|**Description**|**Min**|**Typ1**|**Max**|**Units**|
|IRPU|Pad pull-up (when selected) at VIN= 0V, VCCO= 3.3V|75|–|190|µA|
||Pad pull-up (when selected) at VIN= 0V, VCCO= 2.5V|50|–|169|µA|
||Pad pull-up (when selected) at VIN= 0V, VCCO= 1.8V|60|–|120|µA|
||Pad pull-up (when selected) at VIN= 0V, VCCO= 1.5V|30|–|120|µA|
||Pad pull-up (when selected) at VIN= 0V, VCCO= 1.2V|10|–|100|µA|
|IRPD|Pad pull-down (when selected) at VIN= 3.3V|60|–|200|µA|
||Pad pull-down (when selected) at VIN= 1.8V|29|–|120|µA|
|ICCADCON|Analog supply current for the SYSMON circuits in the power-up<br>state|–|–|8|mA|
|ICCADCOFF|Analog supply current for the SYSMON circuits in the power-down<br>state|–|–|1.5|mA|
|IPFS4|VCCAUXadditional supply current during eFUSE programming|–|–|115|mA|
|Internal VREF|50% VCCO|VCCOx 0.49|VCCOx 0.50|VCCOx 0.51|V|
||70% VCCO|VCCOx 0.69|VCCOx 0.70|VCCOx 0.71|V|
||1/6 VCCO(XP5IO I/O banks only)||VCCOx 1/6||V|
||1/8 VCCO(XP5IO I/O banks only)||VCCOx 1/8||V|
|Differential termination|Programmable differential termination (TERM_100) for HP I/O<br>and XP5IO I/O banks|–35%|100|+35%|Ω|
|n|Temperature diode ideality factor|–|1.026|–|–|
|r|Temperature diode series resistance|–|2|–|Ω|
|**Calibrated programmable on-die termination (DCI) in HP I/O banks5 (measured per JEDEC specification)**||||||
|R7|Thevenin equivalent resistance of programmable input<br>termination to VCCO/2 where ODT = RTT_40|–10%6|40|+10%6|Ω|
||Thevenin equivalent resistance of programmable input<br>termination to VCCO/2 where ODT = RTT_48|–10%6|48|+10%6|Ω|
||Thevenin equivalent resistance of programmable input<br>termination to VCCO/2 where ODT = RTT_60|–10%6|60|+10%6|Ω|
||Programmable input termination to VCCOwhere ODT = RTT_40|–10%6|40|+10%6|Ω|
||Programmable input termination to VCCOwhere ODT = RTT_48|–10%6|48|+10%6|Ω|
||Programmable input termination to VCCOwhere ODT = RTT_60|–10%6|60|+10%6|Ω|
||Programmable input termination to VCCOwhere ODT = RTT_120|–10%6|120|+10%6|Ω|
||Programmable input termination to VCCOwhere ODT = RTT_240|–10%6|240|+10%6|Ω|
|**Uncalibrated programmable on-die termination in HP I/Os banks (measured per JEDEC specification)**||||||
|R7|Thevenin equivalent resistance of programmable input<br>termination to VCCO/2 where ODT = RTT_40|–50%|40|+50%|Ω|
||Thevenin equivalent resistance of programmable input<br>termination to VCCO/2 where ODT = RTT_48|–50%|48|+50%|Ω|
||Thevenin equivalent resistance of programmable input<br>termination to VCCO/2 where ODT = RTT_60|–50%|60|+50%|Ω|
||Programmable input termination to VCCOwhere ODT = RTT_40|–50%|40|+50%|Ω|
||Programmable input termination to VCCOwhere ODT = RTT_48|–50%|48|+50%|Ω|
||Programmable input termination to VCCOwhere ODT = RTT_60|–50%|60|+50%|Ω|
||Programmable input termination to VCCOwhere ODT = RTT_120|–50%|120|+50%|Ω|
||Programmable input termination to VCCOwhere ODT = RTT_240|–50%|240|+50%|Ω|



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Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

_Table 3:_ **DC Characteristics Over Recommended Operating Conditions** _(cont'd)_ 

|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|
|_Table 3:_**DC Characteristics Over Recommended Operating Conditions**_(cont'd)_||||||
|**Symbol**|**Description**|**Min**|**Typ1**|**Max**|**Units**|
|**Uncalibrated programmable on-die termination in HD I/O banks (measured per JEDEC specification)**||||||
|R7|Thevenin equivalent resistance of programmable input<br>termination to VCCO/2 where ODT = RTT_48|–50%|48|+50%|Ω|
|**Calibrated programmable on-die termination (DCI) in XP5IO I/O banks5 (measured per JEDEC specification)**||||||
|R7|Thevenin equivalent resistance of programmable input<br>termination where x = target impedance of 8, 60, 120, or 240||||Ω|
|**Notes:**<br>1.<br>Typical values are specified at nominal voltage, 25°C.<br>2.<br>For the I/O banks with a VCCOof 1.8V and separated VCCOand VCCAUX_IOpower supplies, the ILmaximum current is 70 µA.<br>3.<br>This measurement represents the die capacitance at the pad, not including the package.<br>4.<br>Do not program eFUSE during device configuration (e.g., during configuration, during configuration readback, or when readback CRC is<br>active).<br>5.<br>VRP resistor tolerance is (240Ω ±1%).<br>6.<br>If VRP resides at a different bank (DCI cascade), the range increases to ±15%.<br>7.<br>On-die input termination resistance, for more information see the_Spartan UltraScale+ FPGAs SelectIO Resources User Guide_(UG861).||||||



## **VIN Maximum Allowed AC Voltage Overshoot and Undershoot** 

## _Table 4:_ **VIN Maximum Allowed AC Voltage Overshoot and Undershoot for HD I/O Banks** 

|**VIN Maximum Allowed AC Voltage Overshoot and Undershoot**|**VIN Maximum Allowed AC Voltage Overshoot and Undershoot**|**VIN Maximum Allowed AC Voltage Overshoot and Undershoot**|**VIN Maximum Allowed AC Voltage Overshoot and Undershoot**|
|---|---|---|---|
|_Table 4:_**VIN Maximum Allowed AC Voltage Overshoot and Undershoot for HD I/O Banks**||||
|**AC Voltage Overshoot1**|**% of UI2 at –40°C to 100°C**|**AC Voltage Undershoot1**|**% of UI2 at –40°C to 100°C**|
|VCCO+ 0.30|100%|–0.30|100%|
|VCCO+ 0.35|100%|–0.35|90%|
|VCCO+ 0.40|100%|–0.40|78%|
|VCCO+ 0.45|100%|–0.45|40%|
|VCCO+ 0.50|100%|–0.50|24%|
|VCCO+ 0.55|100%|–0.55|18.0%|
|VCCO+ 0.60|100%|–0.60|13.0%|
|VCCO+ 0.65|100%|–0.65|10.8%|
|VCCO+ 0.70|92%|–0.70|9.0%|
|VCCO+ 0.75|92%|–0.75|7.0%|
|VCCO+ 0.80|92%|–0.80|6.0%|
|VCCO+ 0.85|92%|–0.85|5.0%|
|VCCO+ 0.90|92%|–0.90|4.0%|
|VCCO+ 0.95|92%|–0.95|2.5%|
|**Notes:**<br>1.<br>A total of 200 mA per bank should not be exceeded.<br>2.<br>For UI smaller than 20 µs.||||



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Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## _Table 5:_ **VIN Maximum Allowed AC Voltage Overshoot and Undershoot for HP I/O Banks** 

|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|
|_Table 5:_**VIN Maximum Allowed AC Voltage Overshoot and Undershoot for HP I/O Banks**||||
|**AC Voltage Overshoot1**|**% of UI2 at –40°C to 100°C**|**AC Voltage Undershoot1**|**% of UI2 at –40°C to 100°C**|
|VCCO+ 0.30|100%|–0.30|100%|
|VCCO+ 0.35|100%|–0.35|100%|
|VCCO+ 0.40|92%|–0.40|92%|
|VCCO+ 0.45|50%|–0.45|50%|
|VCCO+ 0.50|20%|–0.50|20%|
|VCCO+ 0.55|10%|–0.55|10%|
|VCCO+ 0.60|6%|–0.60|6%|
|VCCO+ 0.65|2%|–0.65|2%|
|VCCO+ 0.70|2%|–0.70|2%|
|**Notes:**<br>1.<br>A total of 200 mA per bank should not be exceeded.<br>2.<br>For UI smaller than 20 µs.||||



## _Table 6:_ **VIN Maximum Allowed AC Voltage Overshoot and Undershoot for XP5IO I/O Banks** 

**AC Voltage Overshoot % of UI at –40°C to 100°C AC Voltage Undershoot % of UI at –40°C to 100°C** 

## **Quiescent Supply Current** 

_Table 7:_ **Typical Quiescent Supply Current** 

|**Quiescent Supply Current**|**Quiescent Supply Current**|**Quiescent Supply Current**|**Quiescent Supply Current**|**Quiescent Supply Current**|**Quiescent Supply Current**|**Quiescent Supply Current**|
|---|---|---|---|---|---|---|
|_Table 7:_**Typical Quiescent Supply Current**|||||||
|**Symbol**|**Description1, 2, 3**|**Device**|**Speed Grade and VCCINT Operating**<br>**Voltages**|||**Units**|
||||**0.85V**||**0.72V**||
||||**-2**|**-1**|**-1**||
|ICCINTQ|Quiescent VCCINTsupply current|XCSU10P||||mA|
|||XCSU25P||||mA|
|||XCSU35P||||mA|
|||XCSU50P||||mA|
|||XCSU55P||||mA|
|||XCSU65P||||mA|
|||XCSU100P||||mA|
|||XCSU150P||||mA|
|||XCSU200P||||mA|



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Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## _Table 7:_ **Typical Quiescent Supply Current** _(cont'd)_ 

|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|---|
|_Table 7:_**Typical Quiescent Supply Current**_(cont'd)_|||||||
|**Symbol**|**Description1, 2, 3**|**Device**|**Speed Grade and VCCINT Operating**<br>**Voltages**|||**Units**|
||||**0.85V**||**0.72V**||
||||**-2**|**-1**|**-1**||
|ICCINT_IOQ|Quiescent VCCINT_IOsupply current|XCSU10P||||mA|
|||XCSU25P||||mA|
|||XCSU35P||||mA|
|||XCSU50P||||mA|
|||XCSU55P||||mA|
|||XCSU65P||||mA|
|||XCSU100P||||mA|
|||XCSU150P||||mA|
|||XCSU200P||||mA|
|ICCOQ|Quiescent VCCOsupply current|All devices||||mA|
|ICCAUXQ|Quiescent VCCAUXsupply current|XCSU10P||||mA|
|||XCSU25P||||mA|
|||XCSU35P||||mA|
|||XCSU50P||||mA|
|||XCSU55P||||mA|
|||XCSU65P||||mA|
|||XCSU100P||||mA|
|||XCSU150P||||mA|
|||XCSU200P||||mA|
|ICCAUX_IOQ|Quiescent VCCAUX_IOsupply current|XCSU10P||||mA|
|||XCSU25P||||mA|
|||XCSU35P||||mA|
|||XCSU50P||||mA|
|||XCSU55P||||mA|
|||XCSU65P||||mA|
|||XCSU100P||||mA|
|||XCSU150P||||mA|
|||XCSU200P||||mA|



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Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

_Table 7:_ **Typical Quiescent Supply Current** _(cont'd)_ 

|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|---|
|_Table 7:_**Typical Quiescent Supply Current**_(cont'd)_|||||||
|**Symbol**|**Description1, 2, 3**|**Device**|**Speed Grade and VCCINT Operating**<br>**Voltages**|||**Units**|
||||**0.85V**||**0.72V**||
||||**-2**|**-1**|**-1**||
|ICCBRAMQ|Quiescent VCCBRAMsupply current|XCSU10P||||mA|
|||XCSU25P||||mA|
|||XCSU35P||||mA|
|||XCSU50P||||mA|
|||XCSU55P||||mA|
|||XCSU65P||||mA|
|||XCSU100P||||mA|
|||XCSU150P||||mA|
|||XCSU200P||||mA|
|**Notes:**<br>1.<br>Typical values are specified at nominal voltage, 85°C junction temperatures (Tj) with single-ended SelectIO™ resources.<br>2.<br>Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, and all I/O pins are 3-state<br>and floating.<br>3.<br>Use the Power Design Manager (PDM) tool (download atwww.amd.com/power) to estimate static power consumption for conditions or<br>supplies other than those specified.|||||||



## **Power Supply Sequencing Power-On/Off Power Supply Sequencing** 

The recommended power-on sequence is VCCINT, VCCINT_IO/VCCBRAM, VCCAUX/VCCAUX_IO, and VCCO to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on. The recommended power-off sequence is the reverse of the power-on sequence. If VCCINT and VCCINT_IO/VCCBRAM have the same recommended voltage levels, they can be powered by the same supply and ramped simultaneously. VCCINT_IO must be connected to VCCBRAM. If VCCAUX/VCCAUX_IO and VCCO have the same recommended voltage levels, they can be powered by the same supply and ramped simultaneously. VCCAUX and VCCAUX_IO must be connected together. VCCADC and VREF can be powered at any time and have no power-up sequencing requirements. 

The recommended power-on sequence to achieve minimum current draw for the GTH transceivers is VCCINT, VMGTAVCC, VMGTAVTT OR VMGTAVCC, VCCINT, VMGTAVTT. There is no recommended sequencing for VMGTVCCAUX. Both VMGTAVCC and VCCINT can be ramped simultaneously. The recommended power-off sequence is the reverse of the power-on sequence to achieve minimum current draw. If these recommended sequences are not met, current drawn from VMGTAVTT can be higher than specifications during power-up and power-down. 

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Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## **Power Supply Requirements** 

Table 8 shows the minimum current, in addition to ICCQ maximum, required by each Spartan UltraScale+ FPGA for proper power-on and configuration. If these current minimums are met, the device powers on after all supplies have passed through their power-on reset threshold voltages. The device must not be configured until after VCCINT is applied. Once initialized and configured, use the Power Design Manager (PDM) tool (download at www.amd.com/power) to estimate current drain on these supplies. PDM is also used to estimate power-on current for all supplies. 

_Table 8:_ **Power-on Current by Device** 

|_Table 8:_**Power-on Current by Device**|_Table 8:_**Power-on Current by Device**|_Table 8:_**Power-on Current by Device**|_Table 8:_**Power-on Current by Device**|_Table 8:_**Power-on Current by Device**|_Table 8:_**Power-on Current by Device**|
|---|---|---|---|---|---|
|**Device**|**ICCINTMIN**|**ICCBRAMMIN + ICCINT_IOMIN**|**ICCOMIN**|**ICCAUXMIN + ICCAUX_IOMIN**|**Units**|
|XCSU10P|464|155|50|111|mA|
|XCSU25P|464|155|50|111|mA|
|XCSU35P|464|155|50|111|mA|
|XCSU50P||||||
|XCSU55P||||||
|XCSU65P||||||
|XCSU100P||||||
|XCSU150P||||||
|XCSU200P||||||



_Table 9:_ **Power Supply Ramp Time** 

|_Table 9:_**Power Supply Ramp Time**|_Table 9:_**Power Supply Ramp Time**|_Table 9:_**Power Supply Ramp Time**|_Table 9:_**Power Supply Ramp Time**|_Table 9:_**Power Supply Ramp Time**|
|---|---|---|---|---|
|**Symbol**|**Description**|**Min**|**Max**|**Units**|
|TVCCINT|Ramp time from GND to 95% of VCCINT|0.2|40|ms|
|TVCCINT_IO|Ramp time from GND to 95% of VCCINT_IO|0.2|40|ms|
|TVCCO|Ramp time from GND to 95% of VCCO|0.2|40|ms|
|TVCCAUX|Ramp time from GND to 95% of VCCAUX|0.2|40|ms|
|TVCCBRAM|Ramp time from GND to 95% of VCCBRAM|0.2|40|ms|
|TMGTAVCC|Ramp time from GND to 95% of VMGTAVCC|0.2|40|ms|
|TMGTAVTT|Ramp time from GND to 95% of VMGTAVTT|0.2|40|ms|
|TMGTVCCAUX|Ramp time from GND to 95% of VMGTVCCAUX|0.2|40|ms|



## **DC Input and Output Levels** 

Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the recommended operating conditions at the VOL and VOH test points. Only selected standards are tested. These are chosen to ensure that all standards meet their specifications. The selected standards are tested at a minimum VCCO with the respective VOL and VOH voltage levels shown. Other standards are sample tested. 

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Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## **I/O Levels** 

## _Table 10:_ **SelectIO DC Input and Output Levels For HD I/O Banks** 

|**I/O Levels**|**I/O Levels**|**I/O Levels**|**I/O Levels**|**I/O Levels**|**I/O Levels**|**I/O Levels**|**I/O Levels**|**I/O Levels**|
|---|---|---|---|---|---|---|---|---|
|_Table 10:_**SelectIO DC Input and Output Levels For HD I/O Banks**|||||||||
|**I/O Standard1, 2**|**VIL**||**VIH**||**VOL**|**VOH**|**IOL**|**IOH**|
||**V, Min**|**V, Max**|**V, Min**|**V, Max**|**V, Max**|**V, Min**|**mA**|**mA**|
|HSTL_I|–0.200|VREF– 0.100|VREF+ 0.100|VCCO+ 0.200|0.400|VCCO– 0.400|8.0|–8.0|
|HSTL_I_18|–0.200|VREF– 0.100|VREF+ 0.100|VCCO+ 0.200|0.400|VCCO– 0.400|8.0|–8.0|
|HSUL_12|–0.200|VREF– 0.130|VREF+ 0.130|VCCO+ 0.200|20% VCCO|80% VCCO|0.1|–0.1|
|LVCMOS12|–0.200|35% VCCO|65% VCCO|VCCO+ 0.200|0.400|VCCO– 0.400|Note3|Note3|
|LVCMOS15|–0.200|35% VCCO|65% VCCO|VCCO+ 0.200|0.450|VCCO– 0.450|Note4|Note4|
|LVCMOS18|–0.200|35% VCCO|65% VCCO|VCCO+ 0.200|0.450|VCCO– 0.450|Note4|Note4|
|LVCMOS25|–0.200|0.700|1.700|VCCO+ 0.200|0.400|VCCO– 0.400|Note4|Note4|
|LVCMOS33|–0.200|0.800|2.000|3.400|0.400|VCCO– 0.400|Note4|Note4|
|LVTTL|–0.200|0.800|2.000|3.400|0.400|2.400|Note4|Note4|
|SSTL135|–0.200|VREF– 0.090|VREF+ 0.090|VCCO+ 0.200|VCCO/2 – 0.150|VCCO/2 + 0.150|8.9|–8.9|
|SSTL15|–0.200|VREF– 0.100|VREF+ 0.100|VCCO+ 0.200|VCCO/2 – 0.175|VCCO/2 + 0.175|8.9|–8.9|
|SSTL18_I|–0.200|VREF– 0.125|VREF+ 0.125|VCCO+ 0.200|VCCO/2 – 0.470|VCCO/2 + 0.470|8.0|–8.0|
|**Notes:**<br>1.<br>Tested according to relevant specifications.<br>2.<br>Standards specified using the default I/O standard configuration. For details, see the_Spartan UltraScale+ FPGAs SelectIO Resources User_<br>_Guide_(UG861).<br>3.<br>Supported drive strengths of 4 or 8 mA in HD I/O banks.<br>4.<br>Supported drive strengths of 4, 8, or 12 mA in HD I/O banks.|||||||||



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Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## _Table 11:_ **SelectIO DC Input and Output Levels for HP I/O Banks** 

|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|---|---|---|
|_Table 11:_**SelectIO DC Input and Output Levels for HP I/O Banks**|||||||||
|**I/O Standard1, 2, 3**|**VIL**||**VIH**||**VOL**|**VOH**|**IOL**|**IOH**|
||**V, Min**|**V, Max**|**V, Min**|**V, Max**|**V, Max**|**V, Min**|**mA**|**mA**|
|HSTL_I|–0.200|VREF– 0.100|VREF+ 0.100|VCCO+ 0.200|0.400|VCCO– 0.400|5.8|–5.8|
|HSTL_I_12|–0.200|VREF– 0.080|VREF+ 0.080|VCCO+ 0.200|25% VCCO|75% VCCO|4.1|–4.1|
|HSTL_I_18|–0.200|VREF– 0.100|VREF+ 0.100|VCCO+ 0.200|0.400|VCCO– 0.400|6.2|–6.2|
|HSUL_12|–0.200|VREF– 0.130|VREF+ 0.130|VCCO+ 0.200|20% VCCO|80% VCCO|0.1|–0.1|
|LVCMOS12|–0.200|35% VCCO|65% VCCO|VCCO+ 0.200|0.400|VCCO– 0.400|Note4|Note4|
|LVCMOS15|–0.200|35% VCCO|65% VCCO|VCCO+ 0.200|0.450|VCCO– 0.450|Note5|Note5|
|LVCMOS18|–0.200|35% VCCO|65% VCCO|VCCO+ 0.200|0.450|VCCO– 0.450|Note5|Note5|
|LVDCI_15|–0.200|35% VCCO|65% VCCO|VCCO+ 0.200|0.450|VCCO– 0.450|7.0|–7.0|
|LVDCI_18|–0.200|35% VCCO|65% VCCO|VCCO+ 0.200|0.450|VCCO– 0.450|7.0|–7.0|
|SSTL12|–0.200|VREF– 0.100|VREF+ 0.100|VCCO+ 0.200|VCCO/2 – 0.150|VCCO/2 + 0.150|8.0|–8.0|
|SSTL135|–0.200|VREF– 0.090|VREF+ 0.090|VCCO+ 0.200|VCCO/2 – 0.150|VCCO/2 + 0.150|9.0|–9.0|
|SSTL15|–0.200|VREF– 0.100|VREF+ 0.100|VCCO+ 0.200|VCCO/2 – 0.175|VCCO/2 + 0.175|10.0|–10.0|
|SSTL18_I|–0.200|VREF– 0.125|VREF+ 0.125|VCCO+ 0.200|VCCO/2 – 0.470|VCCO/2 + 0.470|7.0|–7.0|
|MIPI_DPHY_ DCI_LP6|–0.200|0.550|0.880|VCCO+ 0.200|0.050|1.100|0.01|–0.01|
|**Notes:**<br>1.<br>Tested according to relevant specifications.<br>2.<br>Standards specified using the default I/O standard configuration. For details, see the_Spartan UltraScale+ FPGAs SelectIO Resources User_<br>_Guide_(UG861).<br>3.<br>POD10 and POD12 DC input and output levels are shown inTable 13,Table 21, andTable 23.<br>4.<br>Supported drive strengths of 2, 4, 6, or 8 mA in HP I/O banks.<br>5.<br>Supported drive strengths of 2, 4, 6, 8, or 12 mA in HP I/O banks.<br>6.<br>Low-power option for MIPI_DPHY_DCI.<br>7.<br>When operating at data rates greater than 1500 Mb/s, the minimum VIHis 0.790V. MIPI D-PHY data rates are outlined inTable 36.|||||||||



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Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## _Table 12:_ **SelectIO DC Input and Output Levels for XP5IO I/O Banks** 

|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|---|---|---|
|_Table 12:_**SelectIO DC Input and Output Levels for XP5IO I/O Banks**|||||||||
|**I/O Standard1, 2, 3**|**VIL**||**VIH**||**VOL**|**VOH**|**IOL**|**IOH**|
||**V, Min**|**V, Max**|**V, Min**|**V, Max**|**V, Max**|**V, Min**|**mA**|**mA**|
|HSTL_I|–0.200|50% VCCO–<br>0.100|50%<br>VCCO+ 0.100|VCCO+ 0.200|0.400|VCCO– 0.400|5.8|–5.8|
|HSTL_I_12|–0.200|50% VCCO–<br>0.080|50%<br>VCCO+ 0.080|VCCO+ 0.200|25% VCCO|75% VCCO|4.1|–4.1|
|HSUL_12|–0.200|50% VCCO–<br>0.130|50%<br>VCCO+ 0.130|VCCO+ 0.200|20% VCCO|80% VCCO|0.1|–0.1|
|LVCMOS10|–0.100|30% VCCO|70% VCCO|VCCO|0.400|VCCO– 0.400|Note4|Note4|
|LVCMOS11|–0.100|35% VCCO|65% VCCO|VCCO|0.400|VCCO– 0.400|Note4|Note4|
|LVCMOS12|–0.200|35% VCCO|65% VCCO|VCCO+ 0.200|0.400|VCCO– 0.400|Note4|Note4|
|LVCMOS135|–0.200|35% VCCO|65% VCCO|VCCO+ 0.200|0.400|VCCO– 0.400|Note4|Note4|
|LVCMOS15|–0.200|35% VCCO|65% VCCO|VCCO+ 0.200|0.450|VCCO– 0.450|Note5|Note5|
|LVDCI_15/HSLVDCI_15|–0.200|35% VCCO|65% VCCO|VCCO+ 0.200|0.450|VCCO– 0.450|7.0|–7.0|
|SSTL12|–0.200|50% VCCO–<br>0.100|50%<br>VCCO+ 0.100|VCCO+ 0.200|VCCO/2 – 0.150|VCCO/2 + 0.150|8.0|–8.0|
|SSTL135|–0.200|50% VCCO–<br>0.090|50%<br>VCCO+ 0.090|VCCO+ 0.200|VCCO/2 – 0.150|VCCO/2 + 0.150|9.0|–9.0|
|SSTL15|–0.200|50% VCCO–<br>0.100|50%<br>VCCO+ 0.100|VCCO+ 0.200|VCCO/2 – 0.175|VCCO/2 + 0.175|10.0|–10.0|
|**Notes:**<br>1.<br>Tested according to relevant specifications.<br>2.<br>Standards specified using the default I/O standard configuration. For details, see the_Spartan UltraScale+ FPGAs SelectIO Resources User_<br>_Guide_(UG861).<br>3.<br>POD10 and POD12 DC input and output levels are shown inTable 14,Table 20, andTable 22.<br>4.<br>Supported drive strengths of 2, 4, 6, or 8 mA in XP5IO I/O banks.<br>5.<br>Supported drive strengths of 2, 4, 6, 8, or 12 mA in XP5IO I/O banks.|||||||||



## _Table 13:_ **DC Input Levels for Single-ended POD10 and POD12 I/O Standards for HP I/O Banks** 

|_Table 13:_**DC Input Levels for Single-ended POD10 and POD12 I/O Standards for HP I/O Banks**|_Table 13:_**DC Input Levels for Single-ended POD10 and POD12 I/O Standards for HP I/O Banks**|_Table 13:_**DC Input Levels for Single-ended POD10 and POD12 I/O Standards for HP I/O Banks**|_Table 13:_**DC Input Levels for Single-ended POD10 and POD12 I/O Standards for HP I/O Banks**|_Table 13:_**DC Input Levels for Single-ended POD10 and POD12 I/O Standards for HP I/O Banks**|
|---|---|---|---|---|
|**I/O Standard1, 2**|**VIL**||**VIH**||
||**V, Min**|**V, Max**|**V, Min**|**V, Max**|
|POD10|–0.200|VREF– 0.068|VREF+ 0.068|VCCO+ 0.200|
|POD12|–0.200|VREF– 0.068|VREF+ 0.068|VCCO+ 0.200|
|**Notes:**<br>1.<br>Tested according to relevant specifications.<br>2.<br>Standards specified using the default I/O standard configuration. For details, see the_Spartan UltraScale+ FPGAs SelectIO Resources User_<br>_Guide_(UG861).|||||



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Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

_Table 14:_ **DC Input Levels for Single-ended POD10, POD12, LVSTL_11, LVSTL06_12, and LVSTL05_10 I/O Standards for XP5IO I/O Banks** 

|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|
|_Table 14:_**DC Input Levels for Single-ended POD10, POD12, LVSTL_11, LVSTL06_12, and LVSTL05_10**<br>**I/O Standards for XP5IO I/O Banks**|||||
|**I/O Standard1, 2**|**VIL**||**VIH**||
||**V, Min**|**V, Max**|**V, Min**|**V, Max**|
|POD10|–0.200|70% VCCO– 0.068|70% VCCO+ 0.068|VCCO+ 0.200|
|POD12|–0.200|70% VCCO– 0.068|70% VCCO+ 0.068|VCCO+ 0.200|
|LVSTL05_10|||||
|LVSTL06_12|||||
|LVSTL11|||||
|**Notes:**<br>1.<br>Tested according to relevant specifications.<br>2.<br>Standards specified using the default I/O standard configuration. For details, see the_Spartan UltraScale+ FPGAs SelectIO Resources User_<br>_Guide_(UG861).|||||



_Table 15:_ **Differential SelectIO DC Input and Output Levels for HP I/O Banks** 

|_Table 15:_**Differential SelectIO DC Input and Output Levels for HP I/O Banks**|_Table 15:_**Differential SelectIO DC Input and Output Levels for HP I/O Banks**|_Table 15:_**Differential SelectIO DC Input and Output Levels for HP I/O Banks**|_Table 15:_**Differential SelectIO DC Input and Output Levels for HP I/O Banks**|_Table 15:_**Differential SelectIO DC Input and Output Levels for HP I/O Banks**|_Table 15:_**Differential SelectIO DC Input and Output Levels for HP I/O Banks**|_Table 15:_**Differential SelectIO DC Input and Output Levels for HP I/O Banks**|_Table 15:_**Differential SelectIO DC Input and Output Levels for HP I/O Banks**|_Table 15:_**Differential SelectIO DC Input and Output Levels for HP I/O Banks**|_Table 15:_**Differential SelectIO DC Input and Output Levels for HP I/O Banks**|_Table 15:_**Differential SelectIO DC Input and Output Levels for HP I/O Banks**|_Table 15:_**Differential SelectIO DC Input and Output Levels for HP I/O Banks**|_Table 15:_**Differential SelectIO DC Input and Output Levels for HP I/O Banks**|_Table 15:_**Differential SelectIO DC Input and Output Levels for HP I/O Banks**|_Table 15:_**Differential SelectIO DC Input and Output Levels for HP I/O Banks**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**I/O Standard**|**VICM (V)1**|||**VID (V)2**|||**VILHS3**|**VIHHS3**|**VOCM (V)4**|||**VOD (V)5**|||
||**Min**|**Typ**|**Max**|**Min**|**Typ**|**Max**|**Min**|**Max**|**Min**|**Typ**|**Max**|**Min**|**Typ**|**Max**|
|SUB_LVDS8|0.500|0.900|1.300|0.070|–|–|–|–|0.700|0.900|1.100|0.100|0.150|0.200|
|LVPECL|0.300|1.200|1.425|0.100|0.350|0.600|–|–|–|–|–|–|–|–|
|SLVS_400_18|0.070|0.200|0.330|0.140|–|0.450|–|–|–|–|–|–|–|–|
|SLVS_400_25|0.070|0.200|0.330|0.140|–|0.450|–|–|–|–|–|–|–|–|
|MIPI_DPHY for<br>operation < 1.5 GB/s9|0.070|–|0.330|0.070|–|–|–0.040|0.460|0.150|0.200|0.250|0.140|0.200|0.270|
|MIPI_DPHY for<br>operation > 1.5 GB/s9|0.070|–|0.330|0.040|–|–|–0.040|0.460|0.150|0.200|0.250|0.140|0.200|0.270|
|**Notes:**<br>1.<br>VICMis the input common mode voltage.<br>2.<br>VIDis the input differential voltage (Q –<br>Q).<br>3.<br>VIHHSand VILHSare the single-ended input high and low voltages, respectively.<br>4.<br>VOCMis the output common mode voltage.<br>5.<br>VODis the output differential voltage (Q –<br>Q).<br>6.<br>LVDS_25 is specified inTable 25.<br>7.<br>LVDS is specified inTable 27.<br>8.<br>The SUB_LVDS receiver is supported in HP I/O and HD I/O banks. The SUB_LVDS transmitter is supported only in HP I/O banks.<br>9.<br>High-speed option for MIPI_DPHY. The VIDmaximum is aligned with the standard's specification. A higher VIDis acceptable as long as<br>the VINspecification is also met.|||||||||||||||



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Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## _Table 16:_ **Complementary Differential SelectIO DC Input and Output Levels for HD I/O Banks** 

|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|---|---|---|---|
|_Table 16:_**Complementary Differential SelectIO DC Input and Output Levels for HD I/O Banks**||||||||||
|**I/O Standard**|**VICM (V)1**|||**VID (V)2**||**VOL (V)3**|**VOH (V)4**|**IOL**|**IOH**|
||**Min**|**Typ**|**Max**|**Min**|**Max**|**Max**|**Min**|**mA**|**mA**|
|DIFF_HSTL_I|0.300|0.750|1.125|0.100|–|0.400|VCCO– 0.400|8.0|–8.0|
|DIFF_HSTL_I_18|0.300|0.900|1.425|0.100|–|0.400|VCCO– 0.400|8.0|–8.0|
|DIFF_HSUL_12|0.300|0.600|0.850|0.100|–|20% VCCO|80% VCCO|0.1|–0.1|
|DIFF_SSTL135|0.300|0.675|1.000|0.100|–|(VCCO/2) – 0.150|(VCCO/2) + 0.150|8.9|–8.9|
|DIFF_SSTL15|0.300|0.750|1.125|0.100|–|(VCCO/2) – 0.175|(VCCO/2) + 0.175|8.9|–8.9|
|DIFF_SSTL18_I|0.300|0.900|1.425|0.100|–|(VCCO/2) – 0.470|(VCCO/2) + 0.470|8.0|–8.0|
|**Notes:**<br>1.<br>VICMis the input common mode voltage.<br>2.<br>VIDis the input differential voltage.<br>3.<br>VOLis the single-ended low-output voltage.<br>4.<br>VOHis the single-ended high-output voltage.||||||||||



_Table 17:_ **Complementary Differential SelectIO DC Input and Output Levels for HP I/O Banks** 

|_Table 17:_**Complementary Differential SelectIO DC Input and Output Levels for HP I/O Banks**|_Table 17:_**Complementary Differential SelectIO DC Input and Output Levels for HP I/O Banks**|_Table 17:_**Complementary Differential SelectIO DC Input and Output Levels for HP I/O Banks**|_Table 17:_**Complementary Differential SelectIO DC Input and Output Levels for HP I/O Banks**|_Table 17:_**Complementary Differential SelectIO DC Input and Output Levels for HP I/O Banks**|_Table 17:_**Complementary Differential SelectIO DC Input and Output Levels for HP I/O Banks**|_Table 17:_**Complementary Differential SelectIO DC Input and Output Levels for HP I/O Banks**|_Table 17:_**Complementary Differential SelectIO DC Input and Output Levels for HP I/O Banks**|_Table 17:_**Complementary Differential SelectIO DC Input and Output Levels for HP I/O Banks**|_Table 17:_**Complementary Differential SelectIO DC Input and Output Levels for HP I/O Banks**|
|---|---|---|---|---|---|---|---|---|---|
|**I/O Standard1**|**VICM (V)2**|||**VID (V)3**||**VOL (V)4**|**VOH (V)5**|**IOL**|**IOH**|
||**Min**|**Typ**|**Max**|**Min**|**Max**|**Max**|**Min**|**mA**|**mA**|
|DIFF_HSTL_I|0.680|VCCO/2|(VCCO/2) + 0.150|0.100|–|0.400|VCCO– 0.400|5.8|–5.8|
|DIFF_HSTL_I_12|0.400 x VCCO|VCCO/2|0.600 x VCCO|0.100|–|0.250 x VCCO|0.750 x VCCO|4.1|–4.1|
|DIFF_HSTL_I_18|(VCCO/2) – 0.175|VCCO/2|(VCCO/2) + 0.175|0.100|–|0.400|VCCO– 0.400|6.2|–6.2|
|DIFF_HSUL_12|(VCCO/2) – 0.120|VCCO/2|(VCCO/2) + 0.120|0.100|–|20% VCCO|80% VCCO|0.1|–0.1|
|DIFF_SSTL12|(VCCO/2) – 0.150|VCCO/2|(VCCO/2) + 0.150|0.100|–|(VCCO/2) – 0.150|(VCCO/2) + 0.150|8.0|–8.0|
|DIFF_SSTL135|(VCCO/2) – 0.150|VCCO/2|(VCCO/2) + 0.150|0.100|–|(VCCO/2) – 0.150|(VCCO/2) + 0.150|9.0|–9.0|
|DIFF_SSTL15|(VCCO/2) – 0.175|VCCO/2|(VCCO/2) + 0.175|0.100|–|(VCCO/2) – 0.175|(VCCO/2) + 0.175|10.0|–10.0|
|DIFF_SSTL18_I|(VCCO/2) – 0.175|VCCO/2|(VCCO/2) + 0.175|0.100|–|(VCCO/2) – 0.470|(VCCO/2) + 0.470|7.0|–7.0|
|**Notes:**<br>1.<br>DIFF_POD10 and DIFF_POD12 HP I/O bank specifications are shown inTable 19,Table 21, andTable 23.<br>2.<br>VICMis the input common mode voltage.<br>3.<br>VIDis the input differential voltage.<br>4.<br>VOLis the single-ended low-output voltage.<br>5.<br>VOHis the single-ended high-output voltage.||||||||||



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Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## _Table 18:_ **Complementary Differential SelectIO DC Input and Output Levels for XP5IO I/O Banks** 

|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|---|---|---|---|
|_Table 18:_**Complementary Differential SelectIO DC Input and Output Levels for XP5IO I/O Banks**||||||||||
|**I/O Standard**|**VICM (V)1**|||**VID (V)2**||**VOL (V)3**|**VOH (V)4**|**IOL**|**IOH**|
||**Min**|**Typ**|**Max**|**Min**|**Max**|**Max**|**Min**|**mA**|**mA**|
|DIFF_HSTL_I|0.680|VCCO/2|(VCCO/2) + 0.150|0.100|–|0.400|VCCO– 0.400|5.8|–5.8|
|DIFF_HSTL_I_12|0.400 x VCCO|VCCO/2|0.600 x VCCO|0.100|–|0.250 x VCCO|0.750 x VCCO|4.1|–4.1|
|DIFF_HSUL_12|(VCCO/2) – 0.120|VCCO/2|(VCCO/2) + 0.120|0.100|–|20% VCCO|80% VCCO|0.1|–0.1|
|DIFF_SSTL12|(VCCO/2) – 0.150|VCCO/2|(VCCO/2) + 0.150|0.100|–|(VCCO/2) – 0.150|(VCCO/2) + 0.150|8.0|–0.8|
|DIFF_SSTL135|(VCCO/2) – 0.150|VCCO/2|(VCCO/2) + 0.150|0.100|–|(VCCO/2) – 0.150|(VCCO/2) + 0.150|9.0|–9.0|
|DIFF_SSTL15|(VCCO/2) – 0.175|VCCO/2|(VCCO/2) + 0.175|0.100|–|(VCCO/2) – 0.175|(VCCO/2) + 0.175|10.0|–10.0|
|**Notes:**<br>1.<br>VICMis the input common mode voltage.<br>2.<br>VIDis the input differential voltage.<br>3.<br>VOLis the single-ended low-output voltage.<br>4.<br>VOHis the single-ended high-output voltage.||||||||||



_Table 19:_ **DC Input Levels for Differential POD10 and POD12 I/O Standards for HP I/O Banks** 

|_Table 19:_**DC Input Levels for Differential POD10 and POD12 I/O Standards for HP I/O Banks**|_Table 19:_**DC Input Levels for Differential POD10 and POD12 I/O Standards for HP I/O Banks**|_Table 19:_**DC Input Levels for Differential POD10 and POD12 I/O Standards for HP I/O Banks**|_Table 19:_**DC Input Levels for Differential POD10 and POD12 I/O Standards for HP I/O Banks**|_Table 19:_**DC Input Levels for Differential POD10 and POD12 I/O Standards for HP I/O Banks**|_Table 19:_**DC Input Levels for Differential POD10 and POD12 I/O Standards for HP I/O Banks**|
|---|---|---|---|---|---|
|**I/O Standard1, 2**|**VICM (V)**|||**VID (V)**||
||**Min**|**Typ**|**Max**|**Min**|**Max**|
|DIFF_POD10|0.630|0.700|0.770|0.140|–|
|DIFF_POD12|0.756|0.840|0.924|0.160|–|
|**Notes:**<br>1.<br>Tested according to relevant specifications.<br>2.<br>Standards specified using the default I/O standard configuration. For details, see the_Spartan UltraScale+ FPGAs SelectIO Resources User_<br>_Guide_(UG861).||||||



## _Table 20:_ **DC Input Levels for Differential POD10, POD12, LVSTL_11, LVSTL06_12, and LVSTL05_10 I/O Standards for XP5IO I/O Banks** 

|_Table 20:_**DC Input Levels for Differential POD10, POD12, LVSTL_11, LVSTL06_12, and LVSTL05_10 I/O**<br>**Standards for XP5IO I/O Banks**|_Table 20:_**DC Input Levels for Differential POD10, POD12, LVSTL_11, LVSTL06_12, and LVSTL05_10 I/O**<br>**Standards for XP5IO I/O Banks**|_Table 20:_**DC Input Levels for Differential POD10, POD12, LVSTL_11, LVSTL06_12, and LVSTL05_10 I/O**<br>**Standards for XP5IO I/O Banks**|_Table 20:_**DC Input Levels for Differential POD10, POD12, LVSTL_11, LVSTL06_12, and LVSTL05_10 I/O**<br>**Standards for XP5IO I/O Banks**|_Table 20:_**DC Input Levels for Differential POD10, POD12, LVSTL_11, LVSTL06_12, and LVSTL05_10 I/O**<br>**Standards for XP5IO I/O Banks**|_Table 20:_**DC Input Levels for Differential POD10, POD12, LVSTL_11, LVSTL06_12, and LVSTL05_10 I/O**<br>**Standards for XP5IO I/O Banks**|
|---|---|---|---|---|---|
|**I/O Standard1, 2**|**VICM (V)**|||**VID (V)**||
||**Min**|**Typ**|**Max**|**Min**|**Max**|
|DIFF_POD10|0.630|0.700|0.770|0.140|–|
|DIFF_POD12|0.756|0.840|0.924|0.160|–|
|DIFF_LVSTL05_10|||||–|
|DIFF_LVSTL06_12|||||–|
|DIFF_LVSTL_11|||||–|
|**Notes:**<br>1.<br>Tested according to relevant specifications.<br>2.<br>Standards specified using the default I/O standard configuration. For details, see the_Spartan UltraScale+ FPGAs SelectIO Resources User_<br>_Guide_(UG861).||||||



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Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

_Table 21:_ **DC Output Levels for Single-ended and Differential POD10 and POD12 Standards for HP I/O Banks** 

|_Table 21:_**DC Output Levels for Single-ended and Differential POD10 and POD12 Standards for HP**<br>**I/O Banks**|_Table 21:_**DC Output Levels for Single-ended and Differential POD10 and POD12 Standards for HP**<br>**I/O Banks**|_Table 21:_**DC Output Levels for Single-ended and Differential POD10 and POD12 Standards for HP**<br>**I/O Banks**|_Table 21:_**DC Output Levels for Single-ended and Differential POD10 and POD12 Standards for HP**<br>**I/O Banks**|_Table 21:_**DC Output Levels for Single-ended and Differential POD10 and POD12 Standards for HP**<br>**I/O Banks**|_Table 21:_**DC Output Levels for Single-ended and Differential POD10 and POD12 Standards for HP**<br>**I/O Banks**|_Table 21:_**DC Output Levels for Single-ended and Differential POD10 and POD12 Standards for HP**<br>**I/O Banks**|
|---|---|---|---|---|---|---|
|**Symbol**|**Description1, 2**|**VOUT**|**Min**|**Typ**|**Max**|**Units**|
|ROL|Pull-down resistance|VOM_DC(as described inTable 23)|36|40|44|Ω|
|ROH|Pull-up resistance|VOM_DC(as described inTable 23)|36|40|44|Ω|
|**Notes:**<br>1.<br>Tested according to relevant specifications.<br>2.<br>Standards specified using the default I/O standard configuration. For details, see the_Spartan UltraScale+ FPGAs SelectIO Resources User_<br>_Guide_(UG861).|||||||



## _Table 22:_ **DC Output Levels for Single-ended and Differential POD10, POD12, LVSTL_11, LVSTL06_12, and LVSTL05_10 Standards for XP5IO I/O Banks** 

|_Table 22:_**DC Output Levels for Single-ended and Differential POD10, POD12, LVSTL_11, LVSTL06_12,**<br>**and LVSTL05_10 Standards for XP5IO I/O Banks**|_Table 22:_**DC Output Levels for Single-ended and Differential POD10, POD12, LVSTL_11, LVSTL06_12,**<br>**and LVSTL05_10 Standards for XP5IO I/O Banks**|_Table 22:_**DC Output Levels for Single-ended and Differential POD10, POD12, LVSTL_11, LVSTL06_12,**<br>**and LVSTL05_10 Standards for XP5IO I/O Banks**|_Table 22:_**DC Output Levels for Single-ended and Differential POD10, POD12, LVSTL_11, LVSTL06_12,**<br>**and LVSTL05_10 Standards for XP5IO I/O Banks**|_Table 22:_**DC Output Levels for Single-ended and Differential POD10, POD12, LVSTL_11, LVSTL06_12,**<br>**and LVSTL05_10 Standards for XP5IO I/O Banks**|_Table 22:_**DC Output Levels for Single-ended and Differential POD10, POD12, LVSTL_11, LVSTL06_12,**<br>**and LVSTL05_10 Standards for XP5IO I/O Banks**|_Table 22:_**DC Output Levels for Single-ended and Differential POD10, POD12, LVSTL_11, LVSTL06_12,**<br>**and LVSTL05_10 Standards for XP5IO I/O Banks**|_Table 22:_**DC Output Levels for Single-ended and Differential POD10, POD12, LVSTL_11, LVSTL06_12,**<br>**and LVSTL05_10 Standards for XP5IO I/O Banks**|
|---|---|---|---|---|---|---|---|
|**I/O**<br>**Standard**|**Symbol**|**Description1, 2**|**VOUT**|**Min**|**Typ**|**Max**|**Units**|
|POD10,<br>POD12|ROL|Pull-down resistance|VOM_DC(as described inTable 24)|32|40|48|Ω|
||ROH|Pull-up resistance|VOM_DC(as described inTable 24)|32|40|48|Ω|
|LVSTL05_10|ROL|Pull-down resistance|VOCM_DC_LOW||||Ω|
||ROH|Pull-up resistance|VOCM_DC_HIGH||||Ω|
|LVSTL06_12|ROL|Pull-down resistance|VOCM_DC_LOW||||Ω|
||ROH|Pull-up resistance|VOCM_DC_HIGH||||Ω|
|LVSTL11|ROL|Pull-down resistance|VOM_DC(as described inTable 24)||||Ω|
||ROH|Pull-up resistance|VOM_DC(as described inTable 24)||||Ω|
|**Notes:**<br>1.<br>Tested according to relevant specifications.<br>2.<br>Standards specified using the default I/O standard configuration. For details, see the_Spartan UltraScale+ FPGAs SelectIO Resources User_<br>_Guide_(UG861).||||||||



## _Table 23:_ **Definitions for DC Output Levels for Single-ended and Differential POD10 and POD12 Standards for HP I/O Banks** 

|**Symbol**|**Description**|**All Speed Grades**|**Units**||
|---|---|---|---|---|
|VOM_DC|DC output Mid measurement level (for IV curve linearity)|0.8 x VCCO|V||



## _Table 24:_ **Definitions for DC Output Levels for Single-ended and Differential POD10, POD12, LVSTL_11, LVSTL06_12, and LVSTL05_10 Standards for XP5IO I/O Banks** 

|_Table 24:_**Definitions for DC Output Levels for Single-ended and Differential POD10, POD12,**<br>**LVSTL_11, LVSTL06_12, and LVSTL05_10 Standards for XP5IO I/O Banks**|_Table 24:_**Definitions for DC Output Levels for Single-ended and Differential POD10, POD12,**<br>**LVSTL_11, LVSTL06_12, and LVSTL05_10 Standards for XP5IO I/O Banks**|_Table 24:_**Definitions for DC Output Levels for Single-ended and Differential POD10, POD12,**<br>**LVSTL_11, LVSTL06_12, and LVSTL05_10 Standards for XP5IO I/O Banks**|_Table 24:_**Definitions for DC Output Levels for Single-ended and Differential POD10, POD12,**<br>**LVSTL_11, LVSTL06_12, and LVSTL05_10 Standards for XP5IO I/O Banks**|_Table 24:_**Definitions for DC Output Levels for Single-ended and Differential POD10, POD12,**<br>**LVSTL_11, LVSTL06_12, and LVSTL05_10 Standards for XP5IO I/O Banks**|
|---|---|---|---|---|
|**I/O Standard**|**Symbol**|**Description**|**All Speed Grades**|**Units**|
|POD10, POD12|VOM_DC|DC output Mid measurement level (for IV curve linearity)||V|
|LVSTL_11|VOM_DC|DC output Mid measurement level (for IV curve linearity)||V|
|LVSTL05_10|VOM_DC|DC output Mid measurement level (for IV curve linearity)||V|
|LVSTL06_12|VOM_DC_LOW|DC output Mid measurement level (for IV curve linearity),<br>drive logic Low||V|
||VOM_DC_HIGH|DC output Mid measurement level (for IV curve linearity),<br>drive logic High||V|



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Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## **LVDS DC Specifications (LVDS_25)** 

The LVDS_25 standard is available in the HD I/O banks. See the _Spartan UltraScale+ FPGAs SelectIO Resources User Guide_ (UG861) for more information. 

## _Table 25:_ **LVDS_25 DC Specifications** 

|The LVDS_25 standard is available in the HD I/O banks. See the_Spartan UltraScale+ FPGAs SelectIO Resources_<br>_User Guide_(UG861) for more informaton.|The LVDS_25 standard is available in the HD I/O banks. See the_Spartan UltraScale+ FPGAs SelectIO Resources_<br>_User Guide_(UG861) for more informaton.|The LVDS_25 standard is available in the HD I/O banks. See the_Spartan UltraScale+ FPGAs SelectIO Resources_<br>_User Guide_(UG861) for more informaton.|The LVDS_25 standard is available in the HD I/O banks. See the_Spartan UltraScale+ FPGAs SelectIO Resources_<br>_User Guide_(UG861) for more informaton.|The LVDS_25 standard is available in the HD I/O banks. See the_Spartan UltraScale+ FPGAs SelectIO Resources_<br>_User Guide_(UG861) for more informaton.|The LVDS_25 standard is available in the HD I/O banks. See the_Spartan UltraScale+ FPGAs SelectIO Resources_<br>_User Guide_(UG861) for more informaton.|
|---|---|---|---|---|---|
|_Table 25:_**LVDS_25 DC Specifications**||||||
|**Symbol**|**DC Parameter**|**Min**|**Typ**|**Max**|**Units**|
|VCCO|Supply voltage|2.425|2.500|2.575|V|
|VIDIFF|Differential input voltage:<br>(Q –<br>Q), Q = High<br>(<br>Q – Q),<br>Q = High|100|350|600|mV|
|VICM|Input common-mode voltage|0.300|1.200|1.425|V|
|**Notes:**<br>1.<br>LVDS_25 in HD I/O banks supports inputs only. LVDS_25 inputs without internal termination have no VCCOrequirements. Any VCCOcan be<br>chosen as long as the input voltage levels do not violate the_Recommended Operating Condition_(Table 2) specification for the VINI/O pin<br>voltage.<br>2.<br>Maximum VIDIFFvalue is specified for the maximum VICMspecification. With a lower VICM, a higher VDIFFis tolerated only when the<br>recommended operating conditions and overshoot/undershoot VINspecifications are maintained.||||||



## **LVDS DC Specifications (LVDS15)** 

The LVDS15 standard is available in the XP5IO I/O banks. See the _Spartan UltraScale+ FPGAs SelectIO Resources User Guide_ (UG861) for more information. 

_Table 26:_ **LVDS_15 DC Specifications** 

|The LVDS15 standard is available in the XP5IO I/O banks. See the_Spartan UltraScale+ FPGAs SelectIO Resources_<br>_User Guide_(UG861) for more informaton.|The LVDS15 standard is available in the XP5IO I/O banks. See the_Spartan UltraScale+ FPGAs SelectIO Resources_<br>_User Guide_(UG861) for more informaton.|The LVDS15 standard is available in the XP5IO I/O banks. See the_Spartan UltraScale+ FPGAs SelectIO Resources_<br>_User Guide_(UG861) for more informaton.|The LVDS15 standard is available in the XP5IO I/O banks. See the_Spartan UltraScale+ FPGAs SelectIO Resources_<br>_User Guide_(UG861) for more informaton.|The LVDS15 standard is available in the XP5IO I/O banks. See the_Spartan UltraScale+ FPGAs SelectIO Resources_<br>_User Guide_(UG861) for more informaton.|The LVDS15 standard is available in the XP5IO I/O banks. See the_Spartan UltraScale+ FPGAs SelectIO Resources_<br>_User Guide_(UG861) for more informaton.|The LVDS15 standard is available in the XP5IO I/O banks. See the_Spartan UltraScale+ FPGAs SelectIO Resources_<br>_User Guide_(UG861) for more informaton.|
|---|---|---|---|---|---|---|
|_Table 26:_**LVDS_15 DC Specifications**|||||||
|**Symbol**|**DC Parameter**|**Conditions**|**Min**|**Typ**|**Max**|**Units**|
|VCCO1|Supply voltage||1.455|1.500|1.545|V|
|VODIFF2|Differential output voltage:<br>(Q –<br>Q), Q = High<br>(<br>Q – Q),<br>Q = High|RT= 100Ω across Q and<br>Q signals|247|350|454|mV|
|VOCM2|Output common-mode voltage|RT= 100Ω across Q and<br>Q signals|1.000|1.200|1.320|V|
|VIDIFF3|Differential input voltage:<br>(Q –<br>Q), Q = High<br>(<br>Q – Q),<br>Q = High||100|350|6003|mV|
|VICM_DC4|Input common-mode voltage (DC coupling)||0.300|1.200|1.320|V|
|VICM_AC5|Input common-mode voltage (AC coupling)||200|–|330|mV|
|**Notes:**<br>1.<br>In XP5IO banks, when LVDS is used with input-only functionality, it can be placed in a bank where the VCCOlevels are different from the<br>specified level only if internal differential termination is not used. In this scenario, VCCOmust be chosen to ensure the input pin voltage<br>levels do not violate the Recommended Operating Condition (Table 2) specification for the VINI/O pin voltage.<br>2.<br>VOCMand VODIFFvalues are for LVDS_PRE_EMPHASIS = FALSE.<br>3.<br>Maximum VIDIFFvalue is specified for the maximum VICMspecification. With a lower VICM, a higher VDIFFis tolerated only when the<br>recommended operating conditions and overshoot/undershoot VINspecifications are maintained.<br>4.<br>Input common mode voltage for DC coupled configurations. EQUALIZATION = EQ_NONE (Default).<br>5.<br>AC coupling with external bias and external differential termination with EQUALIZATION settings enabled. EQUALIZATION = EQ_LEVEL0,<br>EQ_LEVEL1, EQ_LEVEL2, EQ_LEVEL3, or EQ_LEVEL4, any setting except EQ_NONE.|||||||



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Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## **LVDS DC Specifications (LVDS)** 

The LVDS standard is available in the HP I/O banks. See the _Spartan UltraScale+ FPGAs SelectIO Resources User Guide_ (UG861) for more information. 

_Table 27:_ **LVDS DC Specifications** 

|_Table 27:_**LVDS DC Specifications**|_Table 27:_**LVDS DC Specifications**|_Table 27:_**LVDS DC Specifications**|_Table 27:_**LVDS DC Specifications**|_Table 27:_**LVDS DC Specifications**|_Table 27:_**LVDS DC Specifications**|_Table 27:_**LVDS DC Specifications**|
|---|---|---|---|---|---|---|
|**Symbol**|**DC Parameter**|**Conditions**|**Min**|**Typ**|**Max**|**Units**|
|VCCO1|Supply voltage||1.746|1.800|1.854|V|
|VODIFF2|Differential output voltage:<br>(Q –<br>Q), Q = High<br>(<br>Q – Q),<br>Q = High|RT= 100Ω across Q and<br>Q signals|247|350|454|mV|
|VOCM2|Output common-mode voltage|RT= 100Ω across Q and<br>Q signals|1.000|1.250|1.425|V|
|VIDIFF3|Differential input voltage:<br>(Q –<br>Q), Q = High<br>(<br>Q – Q),<br>Q = High||100|350|6003|mV|
|VICM_DC4|Input common-mode voltage (DC coupling)||0.300|1.200|1.425|V|
|VICM_AC5|Input common-mode voltage (AC coupling)||0.600|–|1.100|V|
|**Notes:**<br>1.<br>In HP I/O banks, when LVDS is used with input-only functionality, it can be placed in a bank where the VCCOlevels are different from the<br>specified level only if internal differential termination is not used. In this scenario, VCCOmust be chosen to ensure the input pin voltage<br>levels do not violate the Recommended Operating Condition (Table 2) specification for the VINI/O pin voltage.<br>2.<br>VOCMand VODIFFvalues are for LVDS_PRE_EMPHASIS = FALSE.<br>3.<br>Maximum VIDIFFvalue is specified for the maximum VICMspecification. With a lower VICM, a higher VDIFFis tolerated only when the<br>recommended operating conditions and overshoot/undershoot VINspecifications are maintained.<br>4.<br>Input common mode voltage for DC coupled configurations. EQUALIZATION = EQ_NONE (Default).<br>5.<br>External input common mode voltage specification for AC coupled configurations. EQUALIZATION = EQ_LEVEL0, EQ_LEVEL1, EQ_LEVEL2,<br>EQ_LEVEL3, EQ_LEVEL4.|||||||



## **AC Switching Characteristics** 

All values represented in this data sheet are based on the speed specifications in the AMD Vivado™ Design Suite as outlined in the following table. 

## _Table 28:_ **Speed Specification Version By Device** 

|**2024.2.1**||**Device**||
|---|---|---|---|
|1.10|XCSU10P, XCSU25P, XCSU35P|||



Switching characteristics are specified on a per-speed-grade basis and can be designated as Advance, Preliminary, or Production. Each designation is defined as follows: 

- **Advance Product Specification:** These specifications are based on simulations only and are typically available soon after device design specifications are frozen. Although speed grades with this designation are considered relatively stable and conservative, some under-reporting might still occur. 

- **Preliminary Product Specification:** These specifications are based on complete ES (engineering sample) silicon characterization. Devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon. The probability of under-reporting delays is greatly reduced as compared to Advance data. 

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- **Product Specification:** These specifications are released once enough production silicon of a particular device family member has been characterized to provide full correlation between specifications and devices over numerous production lots. There is no under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest speed grades transition to production before faster speed grades. 

## **Testing of AC Switching Characteristics** 

Internal timing parameters are derived from measuring internal test patterns. All AC switching characteristics are representative of worst-case supply voltage and junction temperature conditions. 

For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer and back-annotate to the simulation net list. Unless otherwise noted, values apply to all Spartan UltraScale+ FPGAs. 

## **Speed Grade Designations** 

Because individual family members are produced at different times, the migration from one category to another depends completely on the status of the fabrication process for each device. Table 29 correlates the current status of the Spartan UltraScale+ FPGAs on a per speed grade basis. 

_Table 29:_ **Speed Grade Designations by Device** 

|Because individual family members are produced at diferent tmes, the migraton from one category to another<br>depends completely on the status of the fabricaton process for each device.Table 29correlates the current<br>status of the Spartan UltraScale+ FPGAs on a per speed grade basis.|Because individual family members are produced at diferent tmes, the migraton from one category to another<br>depends completely on the status of the fabricaton process for each device.Table 29correlates the current<br>status of the Spartan UltraScale+ FPGAs on a per speed grade basis.|Because individual family members are produced at diferent tmes, the migraton from one category to another<br>depends completely on the status of the fabricaton process for each device.Table 29correlates the current<br>status of the Spartan UltraScale+ FPGAs on a per speed grade basis.|Because individual family members are produced at diferent tmes, the migraton from one category to another<br>depends completely on the status of the fabricaton process for each device.Table 29correlates the current<br>status of the Spartan UltraScale+ FPGAs on a per speed grade basis.|
|---|---|---|---|
|_Table 29:_**Speed Grade Designations by Device**||||
|**Device**|**Speed Grade, Temperature Ranges, and VCCINT Operating Voltages**|||
||**Advance**|**Preliminary**|**Production**|
|XCSU10P|-2E (VCCINT= 0.85V), -2I (VCCINT= 0.85V)<br>-1E (VCCINT= 0.85V), -1I (VCCINT= 0.85V)<br>-1LI (VCCINT= 0.85V)1<br>-1LI (VCCINT= 0.72V)1|||
|XCSU25P|-2E (VCCINT= 0.85V), -2I (VCCINT= 0.85V)<br>-1E (VCCINT= 0.85V), -1I (VCCINT= 0.85V)<br>-1LI (VCCINT= 0.85V)1<br>-1LI (VCCINT= 0.72V)1|||
|XCSU35P|-2E (VCCINT= 0.85V), -2I (VCCINT= 0.85V)<br>-1E (VCCINT= 0.85V), -1I (VCCINT= 0.85V)<br>-1LI (VCCINT= 0.85V)1<br>-1LI (VCCINT= 0.72V)1|||
|XCSU50P|-2E (VCCINT= 0.85V), -2I (VCCINT= 0.85V)<br>-1E (VCCINT= 0.85V), -1I (VCCINT= 0.85V)<br>-1LI (VCCINT= 0.85V)1<br>-1LI (VCCINT= 0.72V)1|||
|XCSU55P|-2E (VCCINT= 0.85V), -2I (VCCINT= 0.85V)<br>-1E (VCCINT= 0.85V), -1I (VCCINT= 0.85V)<br>-1LI (VCCINT= 0.85V)1<br>-1LI (VCCINT= 0.72V)1|||
|XCSU65P|-2E (VCCINT= 0.85V), -2I (VCCINT= 0.85V)<br>-1E (VCCINT= 0.85V), -1I (VCCINT= 0.85V)<br>-1LI (VCCINT= 0.85V)1<br>-1LI (VCCINT= 0.72V)1|||



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Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

_Table 29:_ **Speed Grade Designations by Device** _(cont'd)_ 

|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|
|_Table 29:_**Speed Grade Designations by Device**_(cont'd)_||||
|**Device**|**Speed Grade, Temperature Ranges, and VCCINT Operating Voltages**|||
||**Advance**|**Preliminary**|**Production**|
|XCSU100P|-2E (VCCINT= 0.85V), -2I (VCCINT= 0.85V)<br>-1E (VCCINT= 0.85V), -1I (VCCINT= 0.85V)<br>-1LI (VCCINT= 0.85V)1<br>-1LI (VCCINT= 0.72V)1|||
|XCSU150P|-2E (VCCINT= 0.85V), -2I (VCCINT= 0.85V)<br>-1E (VCCINT= 0.85V), -1I (VCCINT= 0.85V)<br>-1LI (VCCINT= 0.85V)1<br>-1LI (VCCINT= 0.72V)1|||
|XCSU200P|-2E (VCCINT= 0.85V), -2I (VCCINT= 0.85V)<br>-1E (VCCINT= 0.85V), -1I (VCCINT= 0.85V)<br>-1LI (VCCINT= 0.85V)1<br>-1LI (VCCINT= 0.72V)1|||
|**Notes:**<br>1.<br>The lowest power -1L devices, where VCCINT= 0.72V, are listed in the Vivado Design Suite as -1LV. Otherwise, the -1L devices, where<br>VCCINT= 0.85V, are listed in the Vivado Design Suite as -1L.||||



## **Production Silicon and Software Status** 

In some cases, a particular family member (and speed grade) is released to production before a speed specification is released with the correct label (Advance, Preliminary, Production). Any labeling discrepancies are corrected in subsequent speed specification releases. 

Table 30 lists the production released Spartan UltraScale+ FPGA, speed grade, and the minimum corresponding supported speed specification version and Vivado software revisions. The Vivado software and speed specifications listed are the minimum releases required for production. All subsequent releases of software and speed specifications are valid. 

_Table 30:_ **Spartan UltraScale+ FPGA Device Production Software and Speed Specification Release** 

|Table 30lists the producton released Spartan UltraScale+ FPGA, speed grade, and the minimum corresponding<br>supported speed specifcaton version and Vivado sofware revisions. The Vivado sofware and speed<br>specifcatons listed are the minimum releases required for producton. All subsequent releases of sofware and<br>speed specifcatons are valid.|Table 30lists the producton released Spartan UltraScale+ FPGA, speed grade, and the minimum corresponding<br>supported speed specifcaton version and Vivado sofware revisions. The Vivado sofware and speed<br>specifcatons listed are the minimum releases required for producton. All subsequent releases of sofware and<br>speed specifcatons are valid.|Table 30lists the producton released Spartan UltraScale+ FPGA, speed grade, and the minimum corresponding<br>supported speed specifcaton version and Vivado sofware revisions. The Vivado sofware and speed<br>specifcatons listed are the minimum releases required for producton. All subsequent releases of sofware and<br>speed specifcatons are valid.|Table 30lists the producton released Spartan UltraScale+ FPGA, speed grade, and the minimum corresponding<br>supported speed specifcaton version and Vivado sofware revisions. The Vivado sofware and speed<br>specifcatons listed are the minimum releases required for producton. All subsequent releases of sofware and<br>speed specifcatons are valid.|Table 30lists the producton released Spartan UltraScale+ FPGA, speed grade, and the minimum corresponding<br>supported speed specifcaton version and Vivado sofware revisions. The Vivado sofware and speed<br>specifcatons listed are the minimum releases required for producton. All subsequent releases of sofware and<br>speed specifcatons are valid.|
|---|---|---|---|---|
|_Table 30:_**Spartan UltraScale+ FPGA Device Production Software and Speed Specification Release**|||||
|**Device**|**Speed Grade and VCCINT Operating Voltages**||||
||**0.85V**|||**0.72V**|
||**-2**|**-1**|**-1L**|**-1L**|
|XCSU10P|||||
|XCSU25P|||||
|XCSU35P|||||
|XCSU50P|||||
|XCSU55P|||||
|XCSU65P|||||
|XCSU100P|||||
|XCSU150P|||||
|XCSU200P|||||
|**Notes:**<br>1.<br>Blank entries indicate a|device and/or speed grade in Advance or Preliminary status.||||



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Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## **FPGA Logic Performance Characteristics** 

This section provides the performance characteristics of some common functions and designs implemented in the Spartan UltraScale+ FPGAs. These values are subject to the same guidelines as the AC Switching Characteristics section. 

In each of the following LVDS performance tables, the I/O bank type is either high performance (HP), high density (HD), or XP5IO. 

In LVDS component mode: 

- For the input/output registers in HP I/O banks, the Vivado tools limit clock frequencies to 312.9 MHz for all speed grades. 

- For IDDR in HP I/O banks, Vivado tools limit clock frequencies to 625.0 MHz for all speed grades. 

- For ODDR in HP I/O banks, Vivado tools limit clock frequencies to 625.0 MHz for all speed grades. 

_Table 31:_ **LVDS Component Mode Performance** 

|_Table 31:_**LVDS Component Mode Performance**|_Table 31:_**LVDS Component Mode Performance**|_Table 31:_**LVDS Component Mode Performance**|_Table 31:_**LVDS Component Mode Performance**|_Table 31:_**LVDS Component Mode Performance**|_Table 31:_**LVDS Component Mode Performance**|_Table 31:_**LVDS Component Mode Performance**|_Table 31:_**LVDS Component Mode Performance**|_Table 31:_**LVDS Component Mode Performance**|
|---|---|---|---|---|---|---|---|---|
|**Description**|**I/O Bank**<br>**Type**|**Speed Grade and VCCINT Operating Voltages**||||||**Units**|
|||**0.85V**||||**0.72V**|||
|||**-2**||**-1**||**-1**|||
|||**Min**|**Max**|**Min**|**Max**|**Min**|**Max**||
|LVDS TX DDR (OSERDES 4:1, 8:1)|HP|0|1250|0|1250|0|1250|Mb/s|
|LVDS TX SDR (OSERDES 2:1, 4:1)|HP|0|625|0|625|0|625|Mb/s|
|LVDS RX DDR (ISERDES 1:4, 1:8)1|HP|0|1250|0|1250|0|1250|Mb/s|
|LVDS RX DDR|HD|0|250|0|250|0|250|Mb/s|
|LVDS RX SDR (ISERDES 1:2, 1:4)1|HP|0|625|0|625|0|625|Mb/s|
|LVDS RX SDR|HD|0|125|0|125|0|125|Mb/s|
|**Notes:**<br>1.<br>LVDS receivers are typically bounded with certain applications to achieve maximum performance. Package skews are not included and<br>should be removed through PCB routing.|||||||||



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Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## _Table 32:_ **LVDS Native Mode Performance** 

|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|---|---|---|---|
|_Table 32:_**LVDS Native Mode Performance**||||||||||
|**Description1, 2**|**DATA_WIDTH**|**I/O Bank**<br>**Type**|**Speed Grade and VCCINT Operating Voltages**||||||**Units**|
||||**0.85V**||||**0.72V**|||
||||**-23**||**-13**||**-13**|||
||||**Min**|**Max**|**Min**|**Max**|**Min**|**Max**||
|LVDS TX DDR<br>(TX_BITSLICE)|4|HP|375|1600|375|1600|375|1260|Mb/s|
||8||375|1600|375|1600|375|1600|Mb/s|
|LVDS TX SDR<br>(TX_BITSLICE)|4|HP|187.5|800|187.5|800|187.5|630|Mb/s|
||8||187.5|800|187.5|800|187.5|800|Mb/s|
|LVDS RX DDR<br>(RX_BITSLICE)4|4|HP|375|16005|375|16005|375|12605|Mb/s|
||8||375|16005|375|16005|375|16005|Mb/s|
|LVDS RX SDR<br>(RX_BITSLICE)4|4|HP|187.5|800|187.5|800|187.5|630|Mb/s|
||8||187.5|800|187.5|800|187.5|800|Mb/s|
|**Notes:**<br>1.<br>Native mode is supported through theHigh-Speed SelectIO Interface Wizardavailable with the Vivado Design Suite. The performance<br>values assume a source-synchronous interface.<br>2.<br>PLL settings can restrict the minimum allowable data rate. For example, when using the PLL with CLKOUTPHY_MODE = VCO_HALF the<br>minimum frequency is PLL_FVCOMIN/2.<br>3.<br>In the CMVA361, CMVA529, CMVB529, SBVC529, and SBVB625 packages, the maximum data rate is 1260 Mb/s for DDR interfaces and<br>630 Mb/s for SDR interfaces.<br>4.<br>LVDS receivers are typically bounded with certain applications to achieve maximum performance. Package skews are not included and<br>should be removed through PCB routing.<br>5.<br>Asynchronous receiver performance is limited to 1300 Mb/s for -2 speed grades and to 1250 Mb/s for -1 speed grades.||||||||||



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Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## _Table 33:_ **MIPI D-PHY Performance** 

|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|---|
|_Table 33:_**MIPI D-PHY Performance**|||||||
|**Description**|**I/O Bank Type**|**Packages**|**Speed Grade and VCCINT**<br>**Operating Voltages**|||**Units**|
||||**0.85V**||**0.72V**||
||||**-2**|**-1**|**-1**||
|Maximum MIPI D-PHY transmitter or receiver<br>data rate per lane1|XP5IO I/O|SBVF784<br>SBVG784<br>SBVA1024<br>FSVG1156|3200|3200|–|Mb/s|
|||CMVB529<br>SBVC529|2500|2500|–|Mb/s|
||HP I/O|FSVG1156|2500|2500|2500|Mb/s|
|||SBVF784<br>SBVG784<br>SBVA1024|2500|2500|2500|Mb/s|
|||CMVA361<br>CMVA529<br>CMVB529<br>SBVC529<br>SBVB625|1500|1500|1500|Mb/s|
|**Notes:**<br>1.<br>For applicable conditions, the lower maximum data rate applies.|||||||



_Table 34:_ **LVDS Native-Mode 1000BASE-X Support** 

|_Table 34:_**LVDS Native-Mode 1000BASE-X Support**|_Table 34:_**LVDS Native-Mode 1000BASE-X Support**|_Table 34:_**LVDS Native-Mode 1000BASE-X Support**|_Table 34:_**LVDS Native-Mode 1000BASE-X Support**|_Table 34:_**LVDS Native-Mode 1000BASE-X Support**|
|---|---|---|---|---|
|**Description1**|**I/O Bank Type**|**Speed Grade and VCCINT Operating Voltages**|||
|||**0.85V**||**0.72V**|
|||**-2**|**-1**|**-1**|
|1000BASE-X|HP|Yes|||
|**Notes:**<br>1.<br>1000BASE-X support is based on the_IEEE Standard for CSMA/CD Access Method and Physical Layer Specifications_(IEEE Std 802.3-2008).|||||



The following table provides the maximum data rates for applicable memory standards using the Spartan UltraScale+ FPGA memory PHY. Refer to Memory Solutions for the complete list of memory interface standards supported and detailed specifications. The final performance of the memory interface is determined through a complete design implemented in the Vivado Design Suite, following guidelines in the _UltraScale Architecture PCB Design User Guide_ (UG583), electrical analysis, and characterization of the system. 

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Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

_Table 35:_ **Maximum Physical Interface (PHY) Rate for Integrated Memory Interface Controller** 

|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|---|---|
|_Table 35:_**Maximum Physical Interface (PHY) Rate for Integrated Memory Interface Controller**||||||||
|**Memory Standard**|**I/O Bank Type**|**DRAM Type**|**Packages**|**Speed Grade and VCCINT Operating**<br>**Voltages**|||**Units**|
|||||**0.85V**||**0.72V**||
|||||**-2**|**-1**|**-1**||
|LPDDR5/LPDDR5x|XP5IO|Single rank component|SBVF784<br>SBVG784<br>SBVA1024<br>FSVG1156|4267|3733||Mb/s|
||||CMVB529<br>SBVC529|2667|2667||Mb/s|
|LPDDR4X|XP5IO|Single rank component|FSVG1156|4267|3733||Mb/s|
||||SBVF784<br>SBVG784<br>SBVA1024|4267|3733||Mb/s|
||||CMVB529<br>SBVC529|2667|2667||Mb/s|



_Table 36:_ **Maximum Physical Interface (PHY) Rate for Soft Memory Interface Controller** 

|_Table 36:_**Maximum Physical Interface (PHY) Rate for Soft Memory Interface Controller**|_Table 36:_**Maximum Physical Interface (PHY) Rate for Soft Memory Interface Controller**|_Table 36:_**Maximum Physical Interface (PHY) Rate for Soft Memory Interface Controller**|_Table 36:_**Maximum Physical Interface (PHY) Rate for Soft Memory Interface Controller**|_Table 36:_**Maximum Physical Interface (PHY) Rate for Soft Memory Interface Controller**|_Table 36:_**Maximum Physical Interface (PHY) Rate for Soft Memory Interface Controller**|_Table 36:_**Maximum Physical Interface (PHY) Rate for Soft Memory Interface Controller**|_Table 36:_**Maximum Physical Interface (PHY) Rate for Soft Memory Interface Controller**|
|---|---|---|---|---|---|---|---|
|**Memory Standard**|**I/O Bank Type**|**DRAM Type**|**Packages**|**Speed Grade and VCCINT Operating**<br>**Voltages**|||**Units**|
|||||**0.85V**||**0.72V**||
|||||**-2**|**-1**|**-1**||
|DDR4|HP I/O|Single rank component|SBVF784<br>SBVG784<br>SBVA1024<br>FSVG1156|2400|2133|1866|Mb/s|
||||CMVA361<br>CMVA529<br>CMVB529<br>SBVC529<br>SBVB625|1866|1866|1866|Mb/s|



## **FPGA Logic Switching Characteristics** 

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Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## **Block RAM and FIFO Switching Characteristics** 

## _Table 37:_ **Block RAM and FIFO Switching Characteristics** 

|**Block RAM and FIFO Switching Characteristics**|**Block RAM and FIFO Switching Characteristics**|**Block RAM and FIFO Switching Characteristics**|**Block RAM and FIFO Switching Characteristics**|**Block RAM and FIFO Switching Characteristics**|**Block RAM and FIFO Switching Characteristics**|
|---|---|---|---|---|---|
|_Table 37:_**Block RAM and FIFO Switching Characteristics**||||||
|**Symbol**|**Description**|**Speed Grade and VCCINT Operating Voltages**|||**Units**|
|||**0.85V**||**0.72V**||
|||**-2**|**-1**|**-1**||
|**Maximum Frequency**||||||
|FMAX_WF_NC|Block RAM (WRITE_FIRST and NO_CHANGE modes)||||MHz|
|FMAX_RF|Block RAM (READ_FIRST mode)||||MHz|
|FMAX_FIFO|FIFO in all modes without ECC||||MHz|
|FMAX_ECC|Block RAM and FIFO in ECC configuration without<br>PIPELINE||||MHz|
||Block RAM and FIFO in ECC configuration with<br>PIPELINE and Block RAM in WRITE_FIRST or<br>NO_CHANGE mode||||MHz|
|TPW1|Minimum pulse width||||ps|
|**Block RAM and FIFO Clock-to-Out Delays**||||||
|TRCKO_DO|Clock CLK to DOUT output (without output register)|1.02|1.103|1.529|ns, Max|
|TRCKO_DO_REG|Clock CLK to DOUT output (with output register)|0.281|0.299|0.433|ns, Max|
|**Notes:**<br>1.<br>The MMCM and PLL DUTY_CYCLE attribute should be set to 50% to meet the pulse-width requirements at the higher frequencies.||||||



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Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## **UltraRAM Switching Characteristics** 

_Table 38:_ **UltraRAM Switching Characteristics** 

|**UltraRAM Switching Characteristics**|**UltraRAM Switching Characteristics**|**UltraRAM Switching Characteristics**|**UltraRAM Switching Characteristics**|**UltraRAM Switching Characteristics**|**UltraRAM Switching Characteristics**|
|---|---|---|---|---|---|
|_Table 38:_**UltraRAM Switching Characteristics**||||||
|**Symbol**|**Description**|**Speed Grade and VCCINT Operating Voltages**|||**Units**|
|||**0.85V**||**0.72V**||
|||**-2**|**-1**|**-1**||
|**Maximum Frequency**||||||
|FMAX|UltraRAM maximum frequency with OREG_B = True|600|575|481|MHz|
|FMAX_ECC_NOPIPELINE|UltraRAM maximum frequency with OREG_B = False<br>and EN_ECC_RD_B = True|400|386|303|MHz|
|FMAX_NOPIPELINE|UltraRAM maximum frequency with OREG_B = False<br>and EN_ECC_RD_B = False|500|478|389|MHz|
|TPW1|Minimum pulse width|700|730|832|ps|
|TRSTPW|Asynchronous reset minimum pulse width. One cycle<br>required|1 clock cycle||||
|**Notes:**<br>1.<br>The MMCM and PLL DUTY_CYCLE attribute should be set to 50% to meet the pulse-width requirements at the higher frequencies.||||||



## **Input/Output Delay Switching Characteristics** 

## _Table 39:_ **Input/Output Delay Switching Characteristics** 

|**Input/Output Delay Switching Characteristics**|**Input/Output Delay Switching Characteristics**|**Input/Output Delay Switching Characteristics**|**Input/Output Delay Switching Characteristics**|**Input/Output Delay Switching Characteristics**|**Input/Output Delay Switching Characteristics**|
|---|---|---|---|---|---|
|_Table 39:_**Input/Output Delay Switching Characteristics**||||||
|**Symbol**|**Description**|**Speed Grade and VCCINT Operating Voltages**|||**Units**|
|||**0.85V**||**0.72V**||
|||**-2**|**-1**|**-1**||
|FREFCLK|Reference clock frequency for IDELAYCTRL<br>(component mode)|300 to 800|||MHz|
||Reference clock frequency when using<br>BITSLICE_CONTROL with REFCLK (in native<br>mode (for RX_BITSLICE only))|300 to 800|||MHz|
||Reference clock frequency for<br>BITSLICE_CONTROL with PLL_CLK (in native<br>mode)1|300 to 2666.67|300 to 2400|300 to 2133|MHz|
|TMINPER_CLK|Minimum period for IODELAY clock|3.195|3.195|3.195|ns|
|TMINPER_RST|Minimum reset pulse width|52.00|||ns|
|TIDELAY_RESOLUTION/<br>TODELAY_RESOLUTION|IDELAY/ODELAY chain resolution|2.1 to 12|||ps|
|**Notes:**<br>1.<br>PLL settings could restrict the minimum allowable data rate. For example, when using a PLL with CLKOUTPHY_MODE = VCO_HALF, the<br>minimum frequency is PLL_FVCOMIN/2.||||||



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## **DSP48 Slice Switching Characteristics** 

_Table 40:_ **DSP48 Slice Switching Characteristics** 

|**DSP48 Slice Switching Characteristics**|**DSP48 Slice Switching Characteristics**|**DSP48 Slice Switching Characteristics**|**DSP48 Slice Switching Characteristics**|**DSP48 Slice Switching Characteristics**|**DSP48 Slice Switching Characteristics**|
|---|---|---|---|---|---|
|_Table 40:_**DSP48 Slice Switching Characteristics**||||||
|**Symbol**|**Description**|**Speed Grade and VCCINT Operating Voltages**|||**Units**|
|||**0.85V**||**0.72V1**||
|||**-2**|**-1**|**-1**||
|**Maximum Frequency**||||||
|FMAX|With all registers used|775|645|600|MHz|
|FMAX_PATDET|With pattern detector|687|571|524|MHz|
|FMAX_MULT_NOMREG|Two register multiply without MREG|544|456|413|MHz|
|FMAX_MULT_NOMREG_PATDET|Two register multiply without MREG with<br>pattern detect|492|410|371|MHz|
|FMAX_PREADD_NOADREG|Without ADREG|565|468|423|MHz|
|FMAX_NOPIPELINEREG|Without pipeline registers (MREG, ADREG)|410|338|304|MHz|
|FMAX_NOPIPELINEREG_PATDET|Without pipeline registers (MREG, ADREG)<br>with pattern detect|379|314|280|MHz|
|**Notes:**<br>1.<br>For devices operating at the lower power VCCINT= 0.72V voltages, DSP cascades that cross the clock region center might operate below<br>the specified FMAX.||||||



## **Clock Buffers and Networks** 

_Table 41:_ **Clock Buffers Switching Characteristics** 

|_Table 41:_**Clock Buffers Switching Characteristics**|_Table 41:_**Clock Buffers Switching Characteristics**|_Table 41:_**Clock Buffers Switching Characteristics**|_Table 41:_**Clock Buffers Switching Characteristics**|_Table 41:_**Clock Buffers Switching Characteristics**|_Table 41:_**Clock Buffers Switching Characteristics**|
|---|---|---|---|---|---|
|**Symbol**|**Description**|**Speed Grade and VCCINT Operating Voltages**|||**Units**|
|||**0.85V**||**0.72V**||
|||**-2**|**-1**|**-1**||
|**Global Clock Switching Characteristics (Including BUFGCTRL)**||||||
|FMAX|Maximum frequency of a global clock tree (BUFG)|775|667|667|MHz|
|**Global Clock Buffer with Input Divide Capability (BUFGCE_DIV)**||||||
|FMAX|Maximum frequency of a global clock buffer with input<br>divide capability (BUFGCE_DIV)|775|667|667|MHz|
|**Global Clock Buffer with Clock Enable (BUFGCE)**||||||
|FMAX|Maximum frequency of a global clock buffer with clock<br>enable (BUFGCE)|775|667|667|MHz|
|**Leaf Clock Buffer with Clock Enable (BUFCE_LEAF)**||||||
|FMAX|Maximum frequency of a leaf clock buffer with clock enable<br>(BUFCE_LEAF)|775|667|667|MHz|
|**GTH Clock Buffer with Clock Enable and Clock Input Divide Capability (BUFG_GT)**||||||
|FMAX|Maximum frequency of a serial transceiver clock buffer<br>with clock enable and clock input divide capability|512|512|512|MHz|



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## **MMCM Switching Characteristics** 

## _Table 42:_ **MMCM Specification** 

|**MMCM Switching Characteristics**|**MMCM Switching Characteristics**|**MMCM Switching Characteristics**|**MMCM Switching Characteristics**|**MMCM Switching Characteristics**|**MMCM Switching Characteristics**|
|---|---|---|---|---|---|
|_Table 42:_**MMCM Specification**||||||
|**Symbol**|**Description**|**Speed Grade and VCCINT Operating Voltages**|||**Units**|
|||**0.85V**||**0.72V**||
|||**-2**|**-1**|**-1**||
|MMCM_FINMAX|Maximum input clock frequency|933|800|800|MHz|
|MMCM_FINMIN|Minimum input clock frequency|10|10|10|MHz|
|MMCM_FINJITTER|Maximum input clock period jitter|< 20% of clock input period or 1 ns Max||||
|MMCM_FINDUTY|Input duty cycle range: 10–49 MHz|25–75|||%|
||Input duty cycle range: 50–199 MHz|30–70|||%|
||Input duty cycle range: 200–399 MHz|35–65|||%|
||Input duty cycle range: 400–499 MHz|40–60|||%|
||Input duty cycle range: >500 MHz|45–55|||%|
|MMCM_FMIN_PSCLK|Minimum dynamic phase shift clock frequency|0.01|0.01|0.01|MHz|
|MMCM_FMAX_PSCLK|Maximum dynamic phase shift clock<br>frequency|500|450|450|MHz|
|MMCM_FVCOMIN|Minimum MMCM VCO frequency|800|800|800|MHz|
|MMCM_FVCOMAX|Maximum MMCM VCO frequency|1600|1600|1600|MHz|
|MMCM_FBANDWIDTH|Low MMCM bandwidth at typical1|1.00|1.00|1.00|MHz|
||High MMCM bandwidth at typical1|4.00|4.00|4.00|MHz|
|MMCM_TSTATPHAOFFSET|Static phase offset of the MMCM outputs2|0.12|0.12|0.12|ns|
|MMCM_TOUTJITTER|MMCM output jitter.|Note3||||
|MMCM_TOUTDUTY|MMCM output clock duty cycle precision4|0.20|0.20|0.20|ns|
|MMCM_TLOCKMAX|MMCM maximum lock time for<br>MMCM_FPFDMIN|100|100|100|µs|
|MMCM_FOUTMAX|MMCM maximum output frequency|775|667|667|MHz|
|MMCM_FOUTMIN|MMCM minimum output frequency4,5|6.25|6.25|6.25|MHz|
|MMCM_TEXTFDVAR|External clock feedback variation|< 20% of clock input period or 1 ns Max||||
|MMCM_RSTMINPULSE|Minimum reset pulse width|5.00|5.00|5.00|ns|
|MMCM_FPFDMAX|Maximum frequency at the phase frequency<br>detector|500|450|450|MHz|
|MMCM_FPFDMIN|Minimum frequency at the phase frequency<br>detector|10|10|10|MHz|
|MMCM_TFBDELAY|Maximum delay in the feedback path|5 ns Max or one clock cycle||||
|MMCM_FDPRCLK_MAX|Maximum DRP clock frequency|250|250|250|MHz|
|**Notes:**<br>1.<br>The MMCM does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies.<br>2.<br>The static offset is measured between any MMCM outputs with identical phase.<br>3.<br>Values for this parameter are available in the Clocking Wizard.<br>4.<br>Includes global clock buffer.<br>5.<br>Calculated as FVCO/128 assuming output duty cycle is 50%.||||||



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## **PLL Switching Characteristics** 

## _Table 43:_ **PLL Specification** 

|**PLL Switching Characteristics**|**PLL Switching Characteristics**|**PLL Switching Characteristics**|**PLL Switching Characteristics**|**PLL Switching Characteristics**|**PLL Switching Characteristics**|
|---|---|---|---|---|---|
|_Table 43:_**PLL Specification**||||||
|**Symbol**|**Description1**|**Speed Grade and VCCINT Operating Voltages**|||**Units**|
|||**0.85V**||**0.72V**||
|||**-2**|**-1**|**-1**||
|PLL_FINMAX|Maximum input clock frequency|933|800|800|MHz|
|PLL_FINMIN|Minimum input clock frequency|70|70|70|MHz|
|PLL_FINJITTER|Maximum input clock period jitter|< 20% of clock input period or 1 ns Max||||
|PLL_FINDUTY|Input duty cycle range: 70–399 MHz|35–65|||%|
||Input duty cycle range: 400–499 MHz|40–60|||%|
||Input duty cycle range: >500 MHz|45–55|||%|
|PLL_FVCOMIN|Minimum PLLE4 VCO frequency2|750|750|750|MHz|
|PLL_FVCOMAX|Maximum PLLE4 VCO frequency2|1500|1500|1500|MHz|
|PLL_FVCOHRMIN|Minimum PLLE4XP high range VCO frequency3|1075|1075|1075|MHz|
|PLL_FVCOHRMAX|Maximum PLLE4XP high range VCO frequency3|1600|1600|1600|MHz|
|PLL_FVCOLRMIN|Minimum PLLE4XP low range VCO frequency3|537.5|537.5|537.5|MHz|
|PLL_FVCOLRMAX|Maximum PLLE4XP low range VCO frequency3|1075|1075|1075|MHz|
|PLL_TSTATPHAOFFSET|Static phase offset of the PLL outputs4|0.12|0.12|0.12|ns|
|PLL_TOUTJITTER|PLL output jitter.|Note5||||
|PLL_TOUTDUTY|PLL CLKOUT0, CLKOUT0B, CLKOUT1, CLKOUT1B<br>duty-cycle precision6|0.20|0.20|0.20|ns|
|PLL_TLOCKMAX|PLL maximum lock time|100|||µs|
|PLL_FOUTMAX|PLL maximum output frequency at CLKOUT0,<br>CLKOUT0B, CLKOUT1, CLKOUT1B|775|667|667|MHz|
||PLL maximum output frequency at CLKOUTPHY|2667|2400|2133|MHz|
|PLL_FOUTMIN|PLL minimum output frequency at CLKOUT0,<br>CLKOUT0B, CLKOUT1, CLKOUT1B7|5.86|5.86|5.86|MHz|
||PLL minimum output frequency at CLKOUTPHY|2 x VCO mode: 1500, 1 x VCO mode: 750, 0.5 x VCO mode:<br>375|||MHz|
|PLL_RSTMINPULSE|Minimum reset pulse width|5.00|5.00|5.00|ns|
|PLL_FPFDMAX|Maximum frequency at the phase frequency<br>detector|667.5|667.5|667.5|MHz|
|PLL_FPFDMIN|Minimum frequency at the phase frequency<br>detector|70|70|70|MHz|
|PLL_FBANDWIDTH|PLL bandwidth at typical|14|14|14|MHz|
|PLL_FDPRCLK_MAX|Maximum DRP clock frequency|250|250|250|MHz|
|**Notes:**<br>1.<br>The PLL does not filter typical spread-spectrum input clocks because they are usually far below the loop filter frequencies.<br>2.<br>PLLE4 has one VCO range.<br>3.<br>PLLE4XP has two VCO ranges which are selected using the VCO_RANGE attribute. FVCOHRshould be used when VCO_RANGE = High and<br>FVCOLRshould be used when VCO_RANGE = Low.<br>4.<br>The static offset is measured between any PLL outputs with identical phase.<br>5.<br>Values for this parameter are available in the Clocking Wizard.<br>6.<br>Includes global clock buffer.<br>7.<br>Calculated as FVCO/128 assuming output duty cycle is 50%.||||||



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## **Package Parameter Guidelines** 

The parameters in this section provide the necessary values for calculating timing budgets for clock transmitter and receiver data-valid windows. 

_Table 44:_ **Package Skew** 

|_Table 44:_**Package Skew**|_Table 44:_**Package Skew**|_Table 44:_**Package Skew**|_Table 44:_**Package Skew**|_Table 44:_**Package Skew**|_Table 44:_**Package Skew**|
|---|---|---|---|---|---|
|**Symbol**|**Description**|**Device**|**Package**|**Value**|**Units**|
|PKGSKEW|Package Skew1,2|XCSU10P|CMVA361|56|ps|
||||CMVA529|58|ps|
||||SBVB625|81|ps|
|||XCSU25P|CMVA361|56|ps|
||||CMVA529|58|ps|
||||SBVB625|81|ps|
|||XCSU35P|CMVA361|56|ps|
||||CMVA529|58|ps|
||||SBVB625|81|ps|
|||XCSU50P||||
|||XCSU55P||||
|||XCSU65P||||
|||XCSU100P||||
|||XCSU150P||||
|||XCSU200P||||
|**Notes:**<br>1.<br>These values represent the worst-case skew between any two SelectIO resources in the package: shortest delay to longest delay from<br>die pad to ball.<br>2.<br>Package delay information is available for these device/package combinations. This information can be used to deskew the package.||||||



## **GTH Transceiver Specifications** 

The _UltraScale Architecture and Product Data Sheet: Overview_ (DS890) lists the Spartan UltraScale+ FPGAs that include the GTH transceivers. 

## **GTH Transceiver DC Input and Output Levels** 

The following table summarizes the DC specifications of the GTH transceivers in Spartan UltraScale+ FPGAs. Consult the _UltraScale Architecture GTH Transceivers User Guide_ (UG576) for further details. 

_Table 45:_ **GTH Transceiver DC Specifications** 

|_Table 45:_**GTH Transceiver DC Specifications**|_Table 45:_**GTH Transceiver DC Specifications**|_Table 45:_**GTH Transceiver DC Specifications**|_Table 45:_**GTH Transceiver DC Specifications**|_Table 45:_**GTH Transceiver DC Specifications**|_Table 45:_**GTH Transceiver DC Specifications**|_Table 45:_**GTH Transceiver DC Specifications**|
|---|---|---|---|---|---|---|
|**Symbol**|**DC Parameter**|**Conditions**|**Min**|**Typ**|**Max**|**Units**|
|DVPPIN|Differential peak-to-peak input voltage<br>(external AC coupled)|>10.3125 Gb/s|150|–|1250|mV|
|||6.6 Gb/s to 10.3125 Gb/s|150|–|1250|mV|
|||≤ 6.6 Gb/s|150|–|2000|mV|
|VIN|Single-ended input voltage. Voltage<br>measured at the pin referenced to<br>GND|DC coupled VMGTAVTT= 1.2V|–400|–|VMGTAVTT|mV|



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_Table 45:_ **GTH Transceiver DC Specifications** _(cont'd)_ 

|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics<br>AMDg¢l\|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics<br>AMDg¢l\|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics<br>AMDg¢l\|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics<br>AMDg¢l\|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics<br>AMDg¢l\|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics<br>AMDg¢l\|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics<br>AMDg¢l\|
|---|---|---|---|---|---|---|
|_Table 45:_**GTH Transceiver DC Specifications**_(cont'd)_<br>~~rs Ges Rees~~GR<br>~~GE~~|||||||
|**Symbol**<br>~~ee~~|**DC Parameter**<br>~~ee~~|**Conditions**<br>~~ee~~<br>~~rs Ges~~|**Min**<br>~~ee~~<br>~~Ges Rees~~|**Typ**<br>~~ee~~<br>~~Rees~~|**Max**<br>~~ee~~<br>GR|**Units**<br>~~ee~~<br>~~GE~~|
|VCMIN<br>~~Pee~~|Common mode input voltage<br>~~Pee~~|DC coupled VMGTAVTT= 1.2V<br>~~rs Ges~~<br>~~Pee~~|–<br>~~Ges Rees~~<br>~~Pee~~|2/3 VMGTAVTT<br>~~Rees ~~<br>~~Pee~~|–<br> GR<br>~~Pee~~|mV<br>~~GE~~<br>~~Pee~~|
|DVPPOUT<br>~~ee~~|Differential peak-to-peak output<br>voltage1<br>~~ee~~|Transmitter output swing is set to<br>11111<br>~~ee~~|800<br>~~ee~~|–<br>~~ee~~|–<br>~~ee~~|mV<br>~~ee~~|
|VCMOUTDC<br>~~P~~|Common mode output voltage: DC<br>coupled (equation based)<br>~~S~~<br>~~Pf~~|When remote RX is terminated to<br>GND<br>~~ee~~<br>~~S~~e|VMGTAVTT/2 – DVPPOUT/4<br>~~ee~~<br>eee|||mV<br>~~ee~~|
|||When remote RX termination is<br>floating<br>~~S~~e|VMGTAVTT– DVPPOUT/2<br>eee|||mV|
|||When remote RX is terminated to<br>VRX_TERM2<br>~~S~~e<br>~~f}~~|eee<br>~~}~~<br>—_—_~~_~~|||mV<br>~~_~~—|
|VCMOUTAC<br>~~P~~<br>ee<br>ee|Common mode output voltage: AC coupled (equation based)<br>~~S~~e<br>~~Pf}~~<br>~~ener~~<br>||VMGTAVTT– DVPPOUT/2<br>eee<br>~~}~~<br>—_—_~~_~~<br>~~er~~<br>(nentsGn<br>Rn<br>|||mV<br>~~_~~—<br>~~er~~<br>GR<br>|
|RIN<br>~~P~~<br>ee<br>ee|Differential input resistance<br>~~Pf}~~<br>~~ener~~<br>||–<br>~~}~~<br>~~er~~<br>(nents<br><br>Gs|100<br>—_—_<br>~~er~~<br>Gn<br><br>eens|–<br>—_—_~~_~~<br>~~er~~<br>Rn<br><br>GO|Ω<br>~~_~~—<br>~~er~~<br>GR<br>|
|ROUT<br>ee<br>ee|Differential output resistance<br>~~ener~~<br>~~en~~||–<br>~~er~~<br>(nents<br>~~en~~<br>Gs|100<br>~~er~~<br>Gn<br>~~en~~<br>eens|–<br>~~er~~<br>Rn<br>~~en~~<br>GO|Ω<br>~~er~~<br>GR<br>~~en~~|
|TOSKEW<br>ee<br>~~Pee~~|Transmitter output pair (TXP and TXN) intra-pair skew (all packages)<br><br>~~Pee~~||–<br>(nents<br><br>Gs<br>~~Pee~~|–<br>Gn<br><br>eens <br>~~Pee~~|10<br>Rn <br><br> GO<br>~~Pee~~|ps<br> GR<br><br>~~Pee~~|
|CEXT<br>~~Pe~~|Recommended external AC coupling capacitor3<br>~~Pe~~||–<br>~~Pe~~|100<br>~~Pe~~|–<br>~~Pe~~|nF<br>~~Pe~~|
|**Notes:**<br>1.<br>The output swing and pre-emphasis levels are programmable using the attributes discussed in the_UltraScale Architecture GTH_<br>_Transceivers User Guide_(UG576), and can result in values lower than reported in this table.<br>2.<br>VRX_TERMis the remote RX termination voltage.<br>3.<br>Other values can be used as appropriate to conform to specific protocols and standards.|||||||



1. The output swing and pre-emphasis levels are programmable using the attributes discussed in the _UltraScale Architecture GTH Transceivers User Guide_ (UG576), and can result in values lower than reported in this table. 

2. VRX_TERM is the remote RX termination voltage. 

3. Other values can be used as appropriate to conform to specific protocols and standards. 

_Figure 1:_ **Single-Ended Peak-to-Peak Voltage** 

**==> picture [487 x 56] intentionally omitted <==**

**----- Start of picture text -----**<br>
+V P<br>Single-Ended<br>Peak-to-Peak<br>N Voltage<br>0<br>**----- End of picture text -----**<br>


**==> picture [36 x 4] intentionally omitted <==**

**----- Start of picture text -----**<br>
X16653-072117<br>**----- End of picture text -----**<br>


_Figure 2:_ **Differential Peak-to-Peak Voltage** 

**==> picture [389 x 87] intentionally omitted <==**

**----- Start of picture text -----**<br>
+V<br>fe<br>Differential<br>0 Peak-to-Peak<br>Voltage<br>="<br>–V P–N<br>Differential peak-to-peak voltage = (Single-ended peak-to-peak voltage) x 2<br>X16639-072117<br>**----- End of picture text -----**<br>


Table 46 and Table 47 summarize the DC specifications of the GTH transceivers input and output clocks in Spartan UltraScale+ FPGAs. Consult the _UltraScale Architecture GTH Transceivers User Guide_ (UG576) for further details. 

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Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

_Table 46:_ **GTH Transceiver Clock Input Level Specification** 

|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|
|_Table 46:_**GTH Transceiver Clock Input Level Specification**||||||
|**Symbol**|**DC Parameter**|**Min**|**Typ**|**Max**|**Units**|
|VIDIFF|Differential peak-to-peak input voltage|250|–|2000|mV|
|RIN|Differential input resistance|–|100|–|Ω|
|CEXT|Required external AC coupling capacitor|–|10|–|nF|



## _Table 47:_ **GTH Transceiver Clock Output Level Specification** 

|_Table 47:_**GTH Transceiver Clock Output Level Specification**|_Table 47:_**GTH Transceiver Clock Output Level Specification**|_Table 47:_**GTH Transceiver Clock Output Level Specification**|_Table 47:_**GTH Transceiver Clock Output Level Specification**|_Table 47:_**GTH Transceiver Clock Output Level Specification**|_Table 47:_**GTH Transceiver Clock Output Level Specification**|_Table 47:_**GTH Transceiver Clock Output Level Specification**|
|---|---|---|---|---|---|---|
|**Symbol**|**Description**|**Conditions**|**Min**|**Typ**|**Max**|**Units**|
|VOL|Output Low voltage for P and N|RT= 100Ω across P and N signals|100|–|330|mV|
|VOH|Output High voltage for P and N|RT= 100Ω across P and N signals|500|–|700|mV|
|VDDOUT|Differential output voltage (P–N),<br>P  =  High (N–P), N = High|RT= 100Ω across P and N signals|300|–|430|mV|
|VCMOUT|Common mode voltage|RT= 100Ω across P and N signals|300|–|500|mV|



## **GTH Transceiver Switching Characteristics** 

Consult the _UltraScale Architecture GTH Transceivers User Guide_ (UG576) for further information. 

_Table 48:_ **GTH Transceiver Performance** 

|Consult the_UltraScale Architecture GTH Transceivers User Guide_(UG576) for further informaton.|Consult the_UltraScale Architecture GTH Transceivers User Guide_(UG576) for further informaton.|Consult the_UltraScale Architecture GTH Transceivers User Guide_(UG576) for further informaton.|Consult the_UltraScale Architecture GTH Transceivers User Guide_(UG576) for further informaton.|Consult the_UltraScale Architecture GTH Transceivers User Guide_(UG576) for further informaton.|Consult the_UltraScale Architecture GTH Transceivers User Guide_(UG576) for further informaton.|Consult the_UltraScale Architecture GTH Transceivers User Guide_(UG576) for further informaton.|Consult the_UltraScale Architecture GTH Transceivers User Guide_(UG576) for further informaton.|Consult the_UltraScale Architecture GTH Transceivers User Guide_(UG576) for further informaton.|Consult the_UltraScale Architecture GTH Transceivers User Guide_(UG576) for further informaton.|
|---|---|---|---|---|---|---|---|---|---|
|_Table 48:_**GTH Transceiver Performance**||||||||||
|**Symbol**|**Description**|**Output Divider**|**Speed Grade and VCCINT Operating Voltages**||||||**Units**|
||||**0.85V**||||**0.72V**|||
||||**-2**||**-1**||**-1**|||
|FGTHMAX|GTH maximum line rate||16.3751||12.5||10.3125||Gb/s|
|FGTHMIN|GTH minimum line rate||0.5||0.5||0.5||Gb/s|
||||**Min**|**Max**|**Min**|**Max**|**Min**|**Max**||
|FGTHCRANGE|CPLL line rate range2|1|4|12.5|4|8.5|4|8.5|Gb/s|
|||2|2|6.25|2|4.25|2|4.25|Gb/s|
|||4|1|3.125|1|2.125|1|2.125|Gb/s|
|||8|0.5|1.5625|0.5|1.0625|0.5|1.0625|Gb/s|
|||16|N/A||||||Gb/s|
||||**Min**|**Max**|**Min**|**Max**|**Min**|**Max**||
|FGTHQRANGE1|QPLL0 line rate range3|1|9.8|16.375|9.8|12.5|9.8|10.3125|Gb/s|
|||2|4.9|8.1875|4.9|8.15|4.9|8.15|Gb/s|
|||4|2.45|4.0938|2.45|4.075|2.45|4.075|Gb/s|
|||8|1.225|2.0469|1.225|2.0375|1.225|2.0375|Gb/s|
|||16|0.6125|1.0234|0.6125|1.0188|0.6125|1.0188|Gb/s|
||||**Min**|**Max**|**Min**|**Max**|**Min**|**Max**||
|FGTHQRANGE2|QPLL1 line rate range4|1|8.0|13.0|8.0|12.5|8.0|10.3125|Gb/s|
|||2|4.0|6.5|4.0|6.5|4.0|6.5|Gb/s|
|||4|2.0|3.25|2.0|3.25|2.0|3.25|Gb/s|
|||8|1.0|1.625|1.0|1.625|1.0|1.625|Gb/s|
|||16|0.5|0.8125|0.5|0.8125|0.5|0.8125|Gb/s|



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_Table 48:_ **GTH Transceiver Performance** _(cont'd)_ 

|_Table 48:_**GTH Transceiver Performance**_(cont'd)_|_Table 48:_**GTH Transceiver Performance**_(cont'd)_|_Table 48:_**GTH Transceiver Performance**_(cont'd)_|_Table 48:_**GTH Transceiver Performance**_(cont'd)_|_Table 48:_**GTH Transceiver Performance**_(cont'd)_|_Table 48:_**GTH Transceiver Performance**_(cont'd)_|_Table 48:_**GTH Transceiver Performance**_(cont'd)_|_Table 48:_**GTH Transceiver Performance**_(cont'd)_|_Table 48:_**GTH Transceiver Performance**_(cont'd)_|_Table 48:_**GTH Transceiver Performance**_(cont'd)_|
|---|---|---|---|---|---|---|---|---|---|
|**Symbol**|**Description**|**Output Divider**|**Speed Grade and VCCINT Operating Voltages**||||||**Units**|
||||**0.85V**||||**0.72V**|||
||||**-2**||**-1**||**-1**|||
||||**Min**|**Max**|**Min**|**Max**|**Min**|**Max**||
|FCPLLRANGE|CPLL frequency range||2|6.25|2|4.25|2|4.25|GHz|
|FQPLL0RANGE|QPLL0 frequency range||9.8|16.375|9.8|16.375|9.8|16.375|GHz|
|FQPLL1RANGE|QPLL1 frequency range||8|13|8|13|8|13|GHz|
|**Notes:**<br>1.<br>GTH transceivers in the CMVA361, CMVA529, and CMVB529 packages support data rates up to 12.5 Gb/s.<br>2.<br>The values listed are the rounded results of the calculated equation (2 × CPLL_Frequency)/Output_Divider.<br>3.<br>The values listed are the rounded results of the calculated equation (QPLL0_Frequency)/Output_Divider.<br>4.<br>The values listed are the rounded results of the calculated equation (QPLL1_Frequency)/Output_Divider.||||||||||



## _Table 49:_ **GTH Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics** 

|**Symbol**|**Description**|**All Speed Grades**|**Units**||
|---|---|---|---|---|
|FGTHDRPCLK|GTHDRPCLK maximum frequency|250|MHz||



_Table 50:_ **GTH Transceiver Reference Clock Switching Characteristics** 

|_Table 50:_**GTH Transceiver Reference Clock Switching Characteristics**|_Table 50:_**GTH Transceiver Reference Clock Switching Characteristics**|_Table 50:_**GTH Transceiver Reference Clock Switching Characteristics**|_Table 50:_**GTH Transceiver Reference Clock Switching Characteristics**|_Table 50:_**GTH Transceiver Reference Clock Switching Characteristics**|_Table 50:_**GTH Transceiver Reference Clock Switching Characteristics**|_Table 50:_**GTH Transceiver Reference Clock Switching Characteristics**|
|---|---|---|---|---|---|---|
|**Symbol**|**Description**|**Conditions**|**All Speed Grades**|||**Units**<br>MHz|
||||**Min**|**Typ**|**Max**||
|FGCLK|Reference clock frequency range||60|–|820||
|TRCLK|Reference clock rise time|20% – 80%|–|200|–|ps|
|TFCLK|Reference clock fall time|80% – 20%|–|200|–|ps|
|TDCREF|Reference clock duty cycle|Transceiver PLL only|40|50|60|%|



_Table 51:_ **GTH Transceiver Reference Clock Oscillator Selection Phase Noise Mask** 

|_Table 51:_**GTH Transceiver Reference Clock Oscillator Selection Phase Noise Mask**|_Table 51:_**GTH Transceiver Reference Clock Oscillator Selection Phase Noise Mask**|_Table 51:_**GTH Transceiver Reference Clock Oscillator Selection Phase Noise Mask**|_Table 51:_**GTH Transceiver Reference Clock Oscillator Selection Phase Noise Mask**|_Table 51:_**GTH Transceiver Reference Clock Oscillator Selection Phase Noise Mask**|_Table 51:_**GTH Transceiver Reference Clock Oscillator Selection Phase Noise Mask**|_Table 51:_**GTH Transceiver Reference Clock Oscillator Selection Phase Noise Mask**|
|---|---|---|---|---|---|---|
|**Symbol**|**Description**|**Offset**<br>**Frequency**|**Min**|**Typ**|**Max**|**Units**|
|QPLLREFCLKMASK1,2|QPLL0/QPLL1 reference clock select phase noise<br>mask at REFCLK frequency = 312.5 MHz|10 kHz|–|–|–105|dBc/Hz|
|||100 kHz|–|–|–124||
|||1 MHz|–|–|–130||
|CPLLREFCLKMASK1,2|CPLL reference clock select phase noise mask at<br>REFCLK frequency = 312.5 MHz|10 kHz|–|–|–105|dBc/Hz|
|||100 kHz|–|–|–124||
|||1 MHz|–|–|–130||
|||50 MHz|–|–|–140||
|**Notes:**<br>1.<br>For reference clock frequencies other than 312.5 MHz, adjust the phase-noise mask values by 20 × Log(N/312.5) where N is the new<br>reference clock frequency in MHz.<br>2.<br>This reference clock phase-noise mask is superseded by any reference clock phase-noise mask that is specified in a supported protocol,<br>e.g., PCIe.|||||||



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Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

_Table 52:_ **GTH Transceiver PLL/Lock Time Adaptation** 

|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|---|
|_Table 52:_**GTH Transceiver PLL/Lock Time Adaptation**|||||||
|**Symbol**|**Description**|**Conditions**|**All Speed Grades**|||**Units**|
||||**Min**|**Typ**|**Max**||
|TLOCK|Initial PLL lock||–|–|1|ms|
|TDLOCK|Clock recovery phase acquisition and<br>adaptation time for decision feedback<br>equalizer (DFE)|After the PLL is locked to the<br>reference clock, this is the time<br>it takes to lock the clock data<br>recovery (CDR) to the data<br>present at the input.|–|50,000|37 x 106|UI|
||Clock recovery phase acquisition and<br>adaptation time for low-power mode (LPM)<br>when the DFE is disabled||–|50,000|2.3 x 106|UI|



_Table 53:_ **GTH Transceiver User Clock Switching Characteristics** 

|_Table 53:_**GTH Transceiver User Clock Switching Characteristics**|_Table 53:_**GTH Transceiver User Clock Switching Characteristics**|_Table 53:_**GTH Transceiver User Clock Switching Characteristics**|_Table 53:_**GTH Transceiver User Clock Switching Characteristics**|_Table 53:_**GTH Transceiver User Clock Switching Characteristics**|_Table 53:_**GTH Transceiver User Clock Switching Characteristics**|_Table 53:_**GTH Transceiver User Clock Switching Characteristics**|_Table 53:_**GTH Transceiver User Clock Switching Characteristics**|
|---|---|---|---|---|---|---|---|
|**Symbol**|**Description1**|**Data Width Conditions**<br>**(Bit)**||**Speed Grade and VCCINT**<br>**Operating Voltages**|||**Units**|
|||||**0.85V**||**0.72V**||
|||**Internal**<br>**Logic**|**Interconnect**<br>**Logic**|**-22**|**-13, 4**|**-14**||
|FTXOUTPMA|TXOUTCLK maximum frequency sourced from OUTCLKPMA|||511.719|390.625|322.266|MHz|
|FRXOUTPMA|RXOUTCLK maximum frequency sourced from OUTCLKPMA|||511.719|390.625|322.266|MHz|
|FTXOUTPROGDIV|TXOUTCLK maximum frequency sourced from TXPROGDIVCLK|||511.719|511.719|511.719|MHz|
|FRXOUTPROGDIV|RXOUTCLK maximum frequency sourced from RXPROGDIVCLK|||511.719|511.719|511.719|MHz|
|FTXIN|TXUSRCLK5maximum frequency|16|16, 32|511.719|390.625|322.266|MHz|
|||32|32, 64|511.719|390.625|322.266|MHz|
|||20|20, 40|409.375|312.500|257.813|MHz|
|||40|40, 80|409.375|312.500|257.813|MHz|
|FRXIN|RXUSRCLK5maximum frequency|16|16, 32|511.719|390.625|322.266|MHz|
|||32|32, 64|511.719|390.625|322.266|MHz|
|||20|20, 40|409.375|312.500|257.813|MHz|
|||40|40, 80|409.375|312.500|257.813|MHz|
|FTXIN2|TXUSRCLK25maximum frequency|16|16|511.719|390.625|322.266|MHz|
|||16|32|255.859|195.313|161.133|MHz|
|||32|32|511.719|390.625|322.266|MHz|
|||32|64|255.859|195.313|161.133|MHz|
|||20|20|409.375|312.500|257.813|MHz|
|||20|40|204.688|156.250|128.906|MHz|
|||40|40|409.375|312.500|257.813|MHz|
|||40|80|204.688|156.250|128.906|MHz|



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Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

_Table 53:_ **GTH Transceiver User Clock Switching Characteristics** _(cont'd)_ 

|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|---|---|
|_Table 53:_**GTH Transceiver User Clock Switching Characteristics**_(cont'd)_||||||||
|**Symbol**|**Description1**|**Data Width Conditions**<br>**(Bit)**||**Speed Grade and VCCINT**<br>**Operating Voltages**|||**Units**|
|||||**0.85V**||**0.72V**||
|||**Internal**<br>**Logic**|**Interconnect**<br>**Logic**|**-22**|**-13, 4**|**-14**||
|FRXIN2|RXUSRCLK25maximum frequency|16|16|511.719|390.625|322.266|MHz|
|||16|32|255.859|195.313|161.133|MHz|
|||32|32|511.719|390.625|322.266|MHz|
|||32|64|255.859|195.313|161.133|MHz|
|||20|20|409.375|312.500|257.813|MHz|
|||20|40|204.688|156.250|128.906|MHz|
|||40|40|409.375|312.500|257.813|MHz|
|||40|80|204.688|156.250|128.906|MHz|
|**Notes:**<br>1.<br>Clocking must be implemented as described in_UltraScale Architecture GTH Transceivers User Guide_(UG576).<br>2.<br>For speed grades -2E and -2I, a 16-bit and 20-bit internal data path can only be used for line rates less than 8.1875 Gb/s.<br>3.<br>For speed grades -1E, -1I, and -1Q, a 16-bit and 20-bit internal data path can only be used for line rates less than 6.25 Gb/s.<br>4.<br>For speed grade -1LI, a 16-bit and 20-bit internal data path can only be used for line rates less than 6.25 Gb/s when VCCINT= 0.85V or<br>5.15625 Gb/s when VCCINT= 0.72V.<br>5.<br>When the gearbox is used, these maximums refer to the XCLK. For more information, see the_UltraScale Architecture GTH Transceivers User_<br>_Guide_(UG576).||||||||



## _Table 54:_ **GTH Transceiver Transmitter Switching Characteristics** 

|_Table 54:_**GTH Transceiver Transmitter Switching Characteristics**|_Table 54:_**GTH Transceiver Transmitter Switching Characteristics**|_Table 54:_**GTH Transceiver Transmitter Switching Characteristics**|_Table 54:_**GTH Transceiver Transmitter Switching Characteristics**|_Table 54:_**GTH Transceiver Transmitter Switching Characteristics**|_Table 54:_**GTH Transceiver Transmitter Switching Characteristics**|_Table 54:_**GTH Transceiver Transmitter Switching Characteristics**|
|---|---|---|---|---|---|---|
|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Units**|
|FGTHTX|Serial data rate range||0.500|–|FGTHMAX|Gb/s|
|TRTX|TX rise time|20%–80%|–|21|–|ps|
|TFTX|TX fall time|80%–20%|–|21|–|ps|
|TLLSKEW|TX lane-to-lane skew1||–|–|500.00|ps|
|TJ16.375|Total jitter2,4|16.375 Gb/s|–|–|0.28|UI|
|DJ16.375|Deterministic jitter2,4||–|–|0.17|UI|
|TJ15.0|Total jitter2,4|15.0 Gb/s|–|–|0.28|UI|
|DJ15.0|Deterministic jitter2,4||–|–|0.17|UI|
|TJ14.1|Total jitter2,4|14.1 Gb/s|–|–|0.28|UI|
|DJ14.1|Deterministic jitter2,4||–|–|0.17|UI|
|TJ14.1|Total jitter2,4|14.025 Gb/s|–|–|0.28|UI|
|DJ14.1|Deterministic jitter2,4||–|–|0.17|UI|
|TJ13.1|Total jitter2,4|13.1 Gb/s|–|–|0.28|UI|
|DJ13.1|Deterministic jitter2,4||–|–|0.17|UI|
|TJ12.5_QPLL|Total jitter2,4|12.5 Gb/s|–|–|0.28|UI|
|DJ12.5_QPLL|Deterministic jitter2,4||–|–|0.17|UI|
|TJ12.5_CPLL|Total jitter3,4|12.5 Gb/s|–|–|0.33|UI|
|DJ12.5_CPLL|Deterministic jitter3,4||–|–|0.17|UI|
|TJ11.3_QPLL|Total jitter2,4|11.3 Gb/s|–|–|0.28|UI|
|DJ11.3_QPLL|Deterministic jitter2,4||–|–|0.17|UI|



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_Table 54:_ **GTH Transceiver Transmitter Switching Characteristics** _(cont'd)_ 

|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|---|
|_Table 54:_**GTH Transceiver Transmitter Switching Characteristics**_(cont'd)_|||||||
|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Units**|
|TJ10.3125_QPLL|Total jitter2,4|10.3125 Gb/s|–|–|0.28|UI|
|DJ10.3125_QPLL|Deterministic jitter2,4||–|–|0.17|UI|
|TJ10.3125_CPLL|Total jitter3,4|10.3125 Gb/s|–|–|0.33|UI|
|DJ10.3125_CPLL|Deterministic jitter3,4||–|–|0.17|UI|
|TJ9.953_QPLL|Total jitter2,4|9.953 Gb/s|–|–|0.28|UI|
|DJ9.953_QPLL|Deterministic jitter2,4||–|–|0.17|UI|
|TJ9.953_CPLL|Total jitter3,4|9.953 Gb/s|–|–|0.33|UI|
|DJ9.953_CPLL|Deterministic jitter3,4||–|–|0.17|UI|
|TJ8.0|Total jitter3,4|8.0 Gb/s|–|–|0.32|UI|
|DJ8.0|Deterministic jitter3,4||–|–|0.17|UI|
|TJ6.6|Total jitter3,4|6.6 Gb/s|–|–|0.30|UI|
|DJ6.6|Deterministic jitter3,4||–|–|0.15|UI|
|TJ5.0|Total jitter3,4|5.0 Gb/s|–|–|0.30|UI|
|DJ5.0|Deterministic jitter3,4||–|–|0.15|UI|
|TJ4.25|Total jitter3,4|4.25 Gb/s|–|–|0.30|UI|
|DJ4.25|Deterministic jitter3,4||–|–|0.15|UI|
|TJ4.0|Total jitter3,4|4.0 Gb/s|–|–|0.32|UI|
|DJ4.0|Deterministic jitter3,4||–|–|0.16|UI|
|TJ3.20|Total jitter3,4|3.20 Gb/s5|–|–|0.20|UI|
|DJ3.20|Deterministic jitter3,4||–|–|0.10|UI|
|TJ2.5|Total jitter3,4|2.5 Gb/s6|–|–|0.20|UI|
|DJ2.5|Deterministic jitter3,4||–|–|0.10|UI|
|TJ1.25|Total jitter3,4|1.25 Gb/s7|–|–|0.15|UI|
|DJ1.25|Deterministic jitter3,4||–|–|0.06|UI|
|TJ500|Total jitter3,4|500 Mb/s8|–|–|0.10|UI|
|DJ500|Deterministic jitter3,4||–|–|0.03|UI|
|**Notes:**<br>1.<br>Using same REFCLK input with TX phase alignment enabled for up to four consecutive transmitters (one fully populated GTH Quad) at<br>the maximum line rate.<br>2.<br>Using QPLL_FBDIV = 40, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations.<br>3.<br>Using CPLL_FBDIV = 2, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations.<br>4.<br>All jitter values are based on a bit-error ratio of 10–12.<br>5.<br>CPLL frequency at 3.2 GHz and TXOUT_DIV = 2.<br>6.<br>CPLL frequency at 2.5 GHz and TXOUT_DIV = 2.<br>7.<br>CPLL frequency at 2.5 GHz and TXOUT_DIV = 4.<br>8.<br>CPLL frequency at 2.0 GHz and TXOUT_DIV = 8.|||||||



_Table 55:_ **GTH Transceiver Receiver Switching Characteristics** 

|_Table 55:_**GTH Transceiver Receiver Switching Characteristics**|_Table 55:_**GTH Transceiver Receiver Switching Characteristics**|_Table 55:_**GTH Transceiver Receiver Switching Characteristics**|_Table 55:_**GTH Transceiver Receiver Switching Characteristics**|_Table 55:_**GTH Transceiver Receiver Switching Characteristics**|_Table 55:_**GTH Transceiver Receiver Switching Characteristics**|_Table 55:_**GTH Transceiver Receiver Switching Characteristics**|
|---|---|---|---|---|---|---|
|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Units**|
|FGTHRX|Serial data rate||0.500|–|FGTHMAX|Gb/s|
|RXSST|Receiver spread-spectrum tracking1|Modulated at 33 kHz|–5000|–|0|ppm|
|RXRL|Run length (CID)||–|–|256|UI|



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Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

_Table 55:_ **GTH Transceiver Receiver Switching Characteristics** _(cont'd)_ 

|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|---|
|_Table 55:_**GTH Transceiver Receiver Switching Characteristics**_(cont'd)_|||||||
|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Units**|
|RXPPMTOL|Data/REFCLK PPM offset tolerance|Bit rates ≤ 6.6 Gb/s|–1250|–|1250|ppm|
|||Bit rates > 6.6 Gb/s and<br>≤ 8.0 Gb/s|–700|–|700|ppm|
|||Bit rates > 8.0 Gb/s|–200|–|200|ppm|
|**SJ Jitter Tolerance2**|||||||
|JT_SJ16.375|Sinusoidal jitter (QPLL)3|16.375 Gb/s|0.30|–|–|UI|
|JT_SJ15.0|Sinusoidal jitter (QPLL)3|15.0 Gb/s|0.30|–|–|UI|
|JT_SJ14.1|Sinusoidal jitter (QPLL)3|14.1 Gb/s|0.30|–|–|UI|
|JT_SJ13.1|Sinusoidal jitter (QPLL)3|13.1 Gb/s|0.30|–|–|UI|
|JT_SJ12.5|Sinusoidal jitter (QPLL)3|12.5 Gb/s|0.30|–|–|UI|
|JT_SJ11.3|Sinusoidal jitter (QPLL)3|11.3 Gb/s|0.30|–|–|UI|
|JT_SJ10.32_QPLL|Sinusoidal jitter (QPLL)3|10.32 Gb/s|0.30|–|–|UI|
|JT_SJ10.32_CPLL|Sinusoidal jitter (CPLL)3|10.32 Gb/s|0.30|–|–|UI|
|JT_SJ9.953_QPLL|Sinusoidal jitter (QPLL)3|9.953 Gb/s|0.30|–|–|UI|
|JT_SJ9.953_CPLL|Sinusoidal jitter (CPLL)3|9.953 Gb/s|0.30|–|–|UI|
|JT_SJ8.0|Sinusoidal jitter (QPLL)3|8.0 Gb/s|0.42|–|–|UI|
|JT_SJ6.6_CPLL|Sinusoidal jitter (CPLL)3|6.6 Gb/s|0.44|–|–|UI|
|JT_SJ5.0|Sinusoidal jitter (CPLL)3|5.0 Gb/s|0.44|–|–|UI|
|JT_SJ4.25|Sinusoidal jitter (CPLL)3|4.25 Gb/s|0.44|–|–|UI|
|JT_SJ3.2|Sinusoidal jitter (CPLL)3|3.2 Gb/s4|0.45|–|–|UI|
|JT_SJ2.5|Sinusoidal jitter (CPLL)3|2.5 Gb/s5|0.30|–|–|UI|
|JT_SJ1.25|Sinusoidal jitter (CPLL)3|1.25 Gb/s6|0.30|–|–|UI|
|JT_SJ500|Sinusoidal jitter (CPLL)3|500 Mb/s7|0.30|–|–|UI|
|**SJ Jitter Tolerance with Stressed Eye2**|||||||
|JT_TJSE3.2|Total jitter with stressed eye8|3.2 Gb/s|0.70|–|–|UI|
|JT_TJSE6.6||6.6 Gb/s|0.70|–|–|UI|
|JT_SJSE3.2|Sinusoidal jitter with stressed eye8|3.2 Gb/s|0.10|–|–|UI|
|JT_SJSE6.6||6.6 Gb/s|0.10|–|–|UI|
|**Notes:**<br>1.<br>Using RXOUT_DIV = 1, 2, and 4.<br>2.<br>All jitter values are based on a bit error ratio of 10–12.<br>3.<br>The frequency of the injected sinusoidal jitter is 80 MHz.<br>4.<br>CPLL frequency at 3.2 GHz and RXOUT_DIV = 2.<br>5.<br>CPLL frequency at 2.5 GHz and RXOUT_DIV = 2.<br>6.<br>CPLL frequency at 2.5 GHz and RXOUT_DIV = 4.<br>7.<br>CPLL frequency at 2.0 GHz and RXOUT_DIV = 8.<br>8.<br>Composite jitter with RX equalizer enabled. DFE disabled.|||||||



## **GTH Transceiver Electrical Compliance** 

The _UltraScale Architecture GTH Transceivers User Guide_ (UG576) contains recommended use modes that ensure compliance for the protocols listed in the following table. The transceiver wizard provides the recommended settings for those use cases and for protocol specific characteristics. 

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Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## _Table 56:_ **GTH Transceiver Protocol List** 

|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|
|_Table 56:_**GTH Transceiver Protocol List**||||
|**Protocol**|**Specification**|**Serial Rate (Gb/s)**|**Electrical**<br>**Compliance**|
|CAUI-10|IEEE 802.3-2012|10.3125|Compliant|
|nPPI|IEEE 802.3-2012|10.3125|Compliant|
|10GBASE-KR1|IEEE 802.3-2012|10.3125|Compliant|
|40GBASE-KR|IEEE 802.3-2012|10.3125|Compliant|
|SFP+|SFF-8431 (SR and LR)|9.95328–11.10|Compliant|
|XFP|INF-8077i, revision 4.5|10.3125|Compliant|
|RXAUI|CEI-6G-SR|6.25|Compliant|
|XAUI|IEEE 802.3-2012|3.125|Compliant|
|1000BASE-X|IEEE 802.3-2012|1.25|Compliant|
|5.0G Ethernet|IEEE 802.3bx (PAR)|5|Compliant|
|2.5G Ethernet|IEEE 802.3bx (PAR)|2.5|Compliant|
|HiGig, HiGig+, HiGig2|IEEE 802.3-2012|3.74, 6.6|Compliant|
|OTU2|ITU G.8251|10.709225|Compliant|
|OTU4 (OTL4.10)|OIF-CEI-11G-SR|11.180997|Compliant|
|OC-3/12/48/192|GR-253-CORE|0.1555–9.956|Compliant|
|TFI-5|OIF-TFI5-0.1.0|2.488|Compliant|
|Interlaken|OIF-CEI-6G, OIF-CEI-11G-SR|4.25–12.5|Compliant|
|PCIe Gen1, 2, 3, 4|PCI Express base 4.0|2.5, 5.0, 8.0, and 16.0|Compliant|
|SDI2|SMPTE 424M-2006|0.27–2.97|Compliant|
|UHD-SDI2|SMPTE ST-2081 6G, SMPTE ST-2082 12G|6 and 12|Compliant|
|Hybrid memory cube (HMC)|HMC-15G-SR|10, 12.5, and 15.0|Compliant|
|MoSys Bandwidth Engine|CEI-11-SR and CEI-11-SR (overclocked)|10.3125, 15.5|Compliant|
|CPRI|CPRI_v_6_1_2014-07-01|0.6144–12.165|Compliant|
|HDMI2|HDMI 2.0|All|Compliant|
|Passive optical network (PON)|10G-EPON, 1G-EPON, NG-PON2, XG-PON, and 2.5G-<br>PON|0.155–10.3125|Compliant|
|JESD204a/b|OIF-CEI-6G, OIF-CEI-11G|3.125–12.5|Compliant|
|Serial RapidIO|RapidIO specification 3.1|1.25–10.3125|Compliant|
|DisplayPort2|DP 1.2B CTS|1.62–5.4|Compliant|
|Fibre channel|FC-PI-4|1.0625–14.025|Compliant|
|SATA Gen1, 2, 3|Serial ATA revision 3.0 specification|1.5, 3.0, and 6.0|Compliant|
|SAS Gen1, 2, 3|T10/BSR INCITS 519|3.0, 6.0, and 12.0|Compliant|
|SFI-5|OIF-SFI5-01.0|0.625–12.5|Compliant|
|Aurora|CEI-6G, CEI-11G-LR|up to 11.180997|Compliant|
|**Notes:**<br>1.<br>The transition time of the transmitter is faster than the IEEE Std 802.3-2012 specification.<br>2.<br>This protocol requires external circuitry to achieve compliance.||||



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Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## **Integrated Interface Block for PCI Express Designs** 

More information and documentation on solutions for PCI Express[®] designs can be found at PCI Express. The _UltraScale Architecture and Product Data Sheet: Overview_ (DS890) lists how many PCIE4CE blocks are in each Spartan UltraScale+ FPGA. For supported modes, link widths, and link speeds, see the _UltraScale+ Devices Integrated Block for PCI Express LogiCORE IP Product Guide_ (PG213). 

_Table 57:_ **Maximum Performance for PCIE4CE-based PCI Express Designs** 

|_Table 57:_**Maximum Performance for PCIE4CE-based PCI Express Designs**|_Table 57:_**Maximum Performance for PCIE4CE-based PCI Express Designs**|_Table 57:_**Maximum Performance for PCIE4CE-based PCI Express Designs**|_Table 57:_**Maximum Performance for PCIE4CE-based PCI Express Designs**|_Table 57:_**Maximum Performance for PCIE4CE-based PCI Express Designs**|_Table 57:_**Maximum Performance for PCIE4CE-based PCI Express Designs**|
|---|---|---|---|---|---|
|**Symbol**|**Description**|**Speed Grade and VCCINT Operating Voltages**|||**Units**|
|||**0.85V**||**0.72V**||
|||**-2**|**-1**|**-1**||
|FPIPECLK|Pipe clock maximum frequency|250.00|250.00|250.00|MHz|
|FCORECLK|Core clock maximum frequency|500.00|500.00|250.00|MHz|
|FDRPCLK|DRP clock maximum frequency|250.00|250.00|250.00|MHz|
|FMCAPCLK|MCAP clock maximum frequency|125.00|125.00|125.00|MHz|



## **System Monitor Specifications** 

_Table 58:_ **System Monitor Specifications** 

|**System Monitor Specifications**|**System Monitor Specifications**|**System Monitor Specifications**|**System Monitor Specifications**|**System Monitor Specifications**|**System Monitor Specifications**|**System Monitor Specifications**|
|---|---|---|---|---|---|---|
|_Table 58:_**System Monitor Specifications**|||||||
|**Parameter**|**Symbol**|**Comments/Conditions**|**Min**|**Typ**|**Max**|**Units**|
|VCCADC= 1.8V ±3%, VREFP= 1.25V, VREFN= 0V, ADCCLK = 5.2 MHz, Tj= –40°C to 100°C, typical values at Tj= 40°C|||||||
|**ADC Accuracy1**|||||||
|Resolution|||10|–|–|Bits|
|Integral nonlinearity2|INL||–|–|±1.5|LSBs|
|Differential nonlinearity|DNL|No missing codes, guaranteed monotonic|–|–|±1|LSBs|
|Offset error||Offset calibration enabled|–|–|±2|LSBs|
|Gain error|||–|–|±0.4|%|
|Sample rate|||–|–|0.2|MS/s|
|RMS code noise||External 1.25V reference|–|–|1|LSBs|
|||On-chip reference|–|1|–|LSBs|
|**ADC Accuracy at Extended Temperatures**|||||||
|Resolution||Tj= –55°C to 125°C|10|–|–|Bits|
|Integral nonlinearity2|INL|Tj= –55°C to 125°C|–|–|±1.5|LSBs|
|Differential nonlinearity|DNL|No missing codes, guaranteed monotonic<br>Tj= –55°C to 125°C|–|–|±1||
|**Analog Inputs2**|||||||
|ADC input ranges||Unipolar operation|0|–|1|V|
|||Bipolar operation|–0.5|–|+0.5|V|
|||Unipolar common mode range (FS input)|0|–|+0.5|V|
|||Bipolar common mode range (FS input)|+0.5|–|+0.6|V|
|Maximum external channel input ranges||Adjacent channels set within these ranges should<br>not corrupt measurements on adjacent channels|–0.1|–|VCCADC|V|



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Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## _Table 58:_ **System Monitor Specifications** _(cont'd)_ 

|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|---|
|_Table 58:_**System Monitor Specifications**_(cont'd)_|||||||
|**Parameter**|**Symbol**|**Comments/Conditions**|**Min**|**Typ**|**Max**|**Units**|
|**On-Chip Sensor Accuracy**|||||||
|Temperature sensor error1,3||Tj= –55°C to 125°C (with external REF)|–|–|±3|°C|
|||Tj= –55°C to 110°C (with internal REF)|–|–|±3.5|°C|
|||Tj= 110°C to 125°C (with internal REF)|–|–|±5|°C|
|Supply sensor error4||Supply voltages 0.72V to 1.2V,<br>Tj= –40°C to 100°C (with external REF)|–|–|±0.5|%|
|||Supply voltages 0.72V to 1.2V,<br>Tj= –55°C to 125°C (with external REF)|–|–|±1.0|%|
|||All other supply voltages,<br>Tj= –40°C to 100°C (with external REF)|–|–|±1.0|%|
|||All other supply voltages,<br>Tj= –55°C to 125°C (with external REF)|–|–|±2.0|%|
|||Supply voltages 0.72V to 1.2V,<br>Tj= –40°C to 100°C (with internal REF)|–|–|±1.0|%|
|||Supply voltages 0.72V to 1.2V,<br>Tj= –55°C to 125°C (with internal REF)|–|–|±2.0|%|
|||All other supply voltages,<br>Tj= –40°C to 100°C (with internal REF)|–|–|±1.5|%|
|||All other supply voltages,<br>Tj= –55°C to 125°C (with internal REF)|–|–|±2.5|%|
|**Conversion Rate5**|||||||
|Conversion time—continuous|tCONV|Number of ADCCLK cycles|26|–|32|Cycles|
|Conversion time—event|tCONV|Number of ADCCLK cycles|–|–|21|Cycles|
|DRP clock frequency|DCLK|DRP clock frequency|8|–|250|MHz|
|ADC clock frequency|ADCCLK|Derived from DCLK|1|–|5.2|MHz|
|DCLK duty cycle|||40|–|60|%|
|**SYSMON Reference6**|||||||
|External reference|VREFP|Externally supplied reference voltage|1.20|1.25|1.30|V|
|On-chip reference||Ground VREFPpin to AGND, Tj= –40°C to 100°C|1.2375|1.25|1.2625|V|
|||Ground VREFPpin to AGND, Tj= –55°C to 125°C|1.225|1.25|1.275|V|
|**Notes:**<br>1.<br>ADC offset errors are removed by enabling the ADC automatic offset calibration feature. The values are specified for when this feature is<br>enabled.<br>2.<br>See the Analog Input section in the_UltraScale Architecture System Monitor User Guide_(UG580).<br>3.<br>When reading temperature values directly from the PMBus interface, the SYSMON has a +4°C offset due to the transfer function used by<br>the PMBus application. For example, the external REF temperature sensor error’s range of ±3°C becomes +1°C to +7°C when the<br>temperature is read through the PMBus interface.<br>4.<br>Supply sensor offset and gain errors are removed by enabling the automatic offset and gain calibration feature. The values are specified<br>for when this feature is enabled.<br>5.<br>See the Adjusting the Acquisition Settling Time section in the_UltraScale Architecture System Monitor User Guide_(UG580).<br>6.<br>Any variation in the reference voltage from the nominal VREFP= 1.25V and VREFN= 0V will result in a deviation from the ideal transfer<br>function. This also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). However, for<br>external ratiometric type applications allowing reference to vary by ±4% is permitted.|||||||



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Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## **SYSMON I2C/PMBus Interfaces** 

## _Table 59:_ **SYSMON I2C Fast Mode Interface Switching Characteristics** 

|**SYSMON I2C/PMBus Interfaces**|**SYSMON I2C/PMBus Interfaces**|**SYSMON I2C/PMBus Interfaces**|**SYSMON I2C/PMBus Interfaces**|**SYSMON I2C/PMBus Interfaces**|
|---|---|---|---|---|
|_Table 59:_**SYSMON I2C Fast Mode Interface Switching Characteristics**|||||
|**Symbol**|**Description1**|**Min**|**Max**|**Units**|
|TSMFCKL|SCL Low time|1.3|–|µs|
|TSMFCKH|SCL High time|0.6|–|µs|
|TSMFCKO|SDAO clock-to-out delay|–|900|ns|
|TSMFDCK|SDAI setup time|100|–|ns|
|FSMFCLK|SCL clock frequency|–|400|kHz|
|**Notes:**<br>1.<br>The test conditions are configured to the LVCMOS 1.8V I/O standard.|||||



## _Table 60:_ **SYSMON I2C Standard Mode Interface Switching Characteristics** 

|_Table 60:_**SYSMON I2C Standard Mode Interface Switching Characteristics**|_Table 60:_**SYSMON I2C Standard Mode Interface Switching Characteristics**|_Table 60:_**SYSMON I2C Standard Mode Interface Switching Characteristics**|_Table 60:_**SYSMON I2C Standard Mode Interface Switching Characteristics**|_Table 60:_**SYSMON I2C Standard Mode Interface Switching Characteristics**|
|---|---|---|---|---|
|**Symbol**|**Description1**|**Min**|**Max**|**Units**|
|TSMSCKL|SCL Low time|4.7|–|µs|
|TSMSCKH|SCL High time|4.0|–|µs|
|TSMSCKO|SDAO clock-to-out delay|–|3450|ns|
|TSMSDCK|SDAI setup time|250|–|ns|
|FSMSCLK|SCL clock frequency|–|100|kHz|
|**Notes:**<br>1.<br>The test conditions are configured to the LVCMOS 1.8V I/O standard.|||||



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Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

## **Configuration Switching Characteristics** 

_Table 61:_ **Configuration Switching Characteristics** 

|_Table 61:_**Configuration Switching Characteristics**|_Table 61:_**Configuration Switching Characteristics**|_Table 61:_**Configuration Switching Characteristics**|_Table 61:_**Configuration Switching Characteristics**|_Table 61:_**Configuration Switching Characteristics**|_Table 61:_**Configuration Switching Characteristics**|
|---|---|---|---|---|---|
|**Symbol**|**Description**|**Speed Grade and VCCINT Operating**<br>**Voltages**|||**Units**|
|||**0.85V**||**0.72V**||
|||**-2**|**-1**|**-1**||
|**Power-up Timing Characteristics**||||||
|TPL|Program latency time from PROGRAM_B Low to output<br>High-Z|10|10|10|ms, Max|
|TPOR1,2|Power-on reset time from start of power-up ramp to<br>INIT_B High-Z (40 ms maximum ramp rate)|65|65|65|ms, Max|
|||0|0|0|ms, Min|
||Power-on reset time from start of power-up ramp to<br>INIT_B High-Z with POR override (2 ms maximum ramp<br>rate)|15|15|15|ms, Max|
|||5|5|5|ms, Min|
|TPROGRAM|PROGRAM_B Low pulse width|250|250|250|ns, Min|
|**OSC Core and IRO Clock Switching**||||||
|FOSC_CORE_CLK|Internal clock source core configuration frequency|510|510|510|MHz, Typ|
||Internal clock source core configuration tolerance|±15|±15|±15|%|
|FCCU_IRO_CLK|Internal configuration control unit clock frequency|170|170|170|MHz, Max|
|FPMC_IRO_CLK|Internal PMC control clock frequency|255|255|255|MHz, Max|
|**AXI32 Clock Switching**||||||
|FAXI_CLK|PL AXI32 clock (AXICLK) to PMC|200|200|200|MHz, Max|
|**CCLK Output (Master Configuration Modes)**||||||
|TMCCKDC|Master CCLK clock duty cycle|45/55|45/55|45/55|%, Min/Max|
|FMCCK|Master SPI (x1/x2/x4) CCLK frequency|150|150|125|MHz, Max|
||Master OSPI (x8) CCLK frequency|150|150|125||
|FMCCK_START|Master CCLK frequency at start of configuration|21|21|21|MHz, Typ|
|FMCCKTOL|Frequency tolerance, master mode with respect to<br>nominal CCLK|±15|±15|±15|%, Max|
|**CCLK Input (Slave Configuration Modes)**||||||
|TSCCKL|Slave CCLK clock minimum Low time|2.5|2.5|2.5|ns, Min|
|TSCCKH|Slave CCLK clock minimum High time|2.5|2.5|2.5|ns, Min|
|FSCCK|Slave serial CCLK frequency|125|125|125|MHz, Max|
||Slave SelectMAP CCLK frequency|125|125|125||
|**EMCCLK Input (Master Configuration Modes)**||||||
|TEMCCKDC|External master CCLK duty cycle|45/55|45/55|45/55|ns, Min|
|FEMCCK|External master configuration clock (EMCCLK) frequency<br>with master SPI (x1/x2/x4)|150|150|125|MHz, Max|
||External master configuration clock (EMCCLK) frequency<br>with master OSPI (x1/x8)|150|150|125||
|**Internal Configuration Access Port**||||||
|FICAPCK|Internal configuration access port (ICAPE3)|200|200|150|MHz, Max|



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Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

_Table 61:_ **Configuration Switching Characteristics** _(cont'd)_ 

|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|
|_Table 61:_**Configuration Switching Characteristics**_(cont'd)_||||||
|**Symbol**|**Description**|**Speed Grade and VCCINT Operating**<br>**Voltages**|||**Units**|
|||**0.85V**||**0.72V**||
|||**-2**|**-1**|**-1**||
|**Slave Serial Mode Programming Switching**||||||
|TDCCK/TCCKD|DINsetup/hold from CCLK rising edge|3.0/0|3.0/0|4.0/0|ns, Min|
|TCCO|CCLK falling edge to DOUT|8.0|8.0|8.0|ns, Max|
|TSCSCLK/SCLKCS|Serial chip select (CS_B) setup and hold to CCLK rising<br>edge||||ns, Min|
|CREADYCS|READY deassertion to chip select deassertion|24|24|24|clock cycles,<br>Max|
|**Slave SelectMAP Mode Programming Switching**||||||
|TSMAPDCLK/SMAPCLKD|SelectMAP data (D[31:00]) setup and hold to CCLK rising<br>edge|4.0/0.0|4.0/0.0|4.5/0.0|ns, Min|
|TSMAPCSCLK/<br>SMAPCLKCS|SelectMAP chip select (CSI_B) setup and hold to CCLK<br>rising edge|4.0/0.0|4.0/0.0|4.5/0.0|ns, Min|
|TSMAPRWCLK/<br>SMAPCLKRW|SelectMAP read write (RDWR_B) setup and hold to CCLK<br>rising edge|9.0/0.0|9.0/0.0|10.0/0.0|ns, Min|
|TSMAPCLKO|SelectMAP CCLK rising edge to data output|8|8|8|ns, Max|
|CSMAPBUSYCS|SelectMAP BUSY assertion to CSI_B deassertion|24|24|24|clock cycles,<br>Max|
|**Boundary-Scan Port Timing Specifications**||||||
|TTAPTCK/TTCKTAP|TMS and TDI setup/hold to/from TCK rising edge|3.0/2.0|3.0/2.0|4.0/2.0|ns, Min|
|TTCKTDO|TCK falling edge to TDO output|7|7|8|ns, Max|
|FTCK|TCK frequency|66|66|50|MHz, Max|
|**eFUSE Clock Switching**||||||
|FFUSE_CLK|Internal eFUSE clock for programming source from<br>FUSE_CLK or EMCCLK|25/200|25/200|25/200|MHz,<br>Min/Max|
|**DNA_PORTE2 Switching**||||||
|FDNACK|DNA_PORTE2 CLK frequency|200|200|175|MHz, Max|
|**STARTUPE3 Ports**||||||
|TUSRCCLKO|STARTUPE3 USRCCLKO input port to CCLK pin output<br>delay|0.25/6.50|0.25/7.50|0.25/9.00|ns, Min/Max|
|TDO|DO[3:0] ports to D03-D00 pins output delay|0.25/7.70|0.25/8.40|0.25/10.00|ns, Min/Max|
|TDTS|DTS[3:0] ports to D03-D00 pins 3-state delays|0.25/7.70|0.25/8.40|0.25/10.00|ns, Min/Max|
|TFCSBO|FCSBO port to FCS_B pin output delay|0.25/7.50|0.25/8.40|0.25/9.80|ns, Min/Max|
|TFCSBTS|FCSBTS port to FCS_B pin 3-state delay|0.25/7.50|0.25/8.40|0.25/9.80|ns, Min/Max|
|TUSRDONEO|USRDONEO port to DONE pin output delay|0.25/9.40|0.25/10.50|0.25/12.10|ns, Min/Max|
|TUSRDONETS|USRDONETS port to DONE pin 3-state delay|0.25/9.40|0.25/10.50|0.25/12.10|ns, Min/Max|
|TDI|D03-D00 pins to DI[3:0] ports input delay|0.5/3.1|0.5/3.5|0.5/4.0|ns, Min/Max|
|FCFGMCLK|STARTUPE3 CFGMCLK output frequency|50|50|50|MHz, Typ|
|FCFGMCLKTOL|STARTUPE3 CFGMCLK output frequency tolerance|±15|±15|±15|%, Max|



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_Table 61:_ **Configuration Switching Characteristics** _(cont'd)_ 

|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|---|
|_Table 61:_**Configuration Switching Characteristics**_(cont'd)_||||||
|**Symbol**|**Description**|**Speed Grade and VCCINT Operating**<br>**Voltages**|||**Units**|
|||**0.85V**||**0.72V**||
|||**-2**|**-1**|**-1**||
|TDCI_MATCH|Specifies a stall in the start-up cycle until the digitally<br>controlled impedance (DCI) match signals are asserted|4|4|4|ms, Max|
|**Notes:**<br>1.<br>The TPORspecification begins when the last of the monitored supplies (VCCINT, VCCBRAM, VCCAUX, VCCO_0) reaches 95% of its recommended<br>operating condition voltage.<br>2.<br>The TPORtime is determined by the POR_OVERRIDE input pin which must be tied to VCCINTor GND. The POR_OVERRIDE pin can be tied to<br>VCCINTfor POR override only when the monitored supplies ramp within the specified 2 ms maximum ramp rate. Otherwise,<br>POR_OVERRIDE must be tied to GND.||||||



_Table 62:_ **Master SPI Mode Programming Switching** 

|_Table 62:_**Master SPI Mode Programming Switching**|_Table 62:_**Master SPI Mode Programming Switching**|_Table 62:_**Master SPI Mode Programming Switching**|_Table 62:_**Master SPI Mode Programming Switching**|_Table 62:_**Master SPI Mode Programming Switching**|
|---|---|---|---|---|
|**Symbol**|**Description1, 2**|**Min**|**Max**|**Units**|
|**SPI clock frequency operating at ≥ 51 MHz**|||||
|FQSPI_CLK|SPI clock frequency|51|150|MHz|
|TSPIIVW|Input valid data window|||UI|
|TQSPICKO|Clock to output delay, all outputs|||ns|
|TQSPICSCLK|Chip select asserted to next clock edge|||ns|
|TQSPICLKCS|Clock edge to chip select deasserted|||ns|
|**SPI clock frequency operating at < 51 MHz**|||||
|FQSPI_CLK|SPI clock frequency||50|MHz|
|TQSPIDCK|Setup time, all inputs|||ns|
|TQSPICKD|Hold time, all inputs|||ns|
|TQSPICKO|Clock to output delay, all outputs|||ns|
|TQSPICSCLK|Chip select asserted to next clock edge|||ns|
|TQSPICLKCS|Clock edge to chip select deasserted|||ns|
|**Notes:**<br>1.<br>The test conditions are configured for the Master SPI configuration mode 4-bit interface with a 12 mA drive strength, fast slew rate, and<br>load conditions (15 pF/30 pF for an SPI 4-bit interface clock frequency up to 100 MHz and 15 pF for clock frequency >100 MHz), tested at<br>1.8V.<br>2.<br>30 pF loads are for QSPI dual-stacked.|||||



_Table 63:_ **Master Octal-SPI Mode Programming Switching** 

|_Table 63:_**Master Octal-SPI Mode Programming Switching**|_Table 63:_**Master Octal-SPI Mode Programming Switching**|_Table 63:_**Master Octal-SPI Mode Programming Switching**|_Table 63:_**Master Octal-SPI Mode Programming Switching**|_Table 63:_**Master Octal-SPI Mode Programming Switching**|
|---|---|---|---|---|
|**Symbol**|**Description1**|**Min**|**Max**|**Units**|
|**Octal-SPI clock frequency operating at DDR > 51 MHz**|||||
|FOSPI_CLK|Octal-SPI clock frequency|51|150|MHz|
|TOSPIIVW|Input valid data window|||UI|
|TOSPICKO|Clock edge to OSPID[07:00] and FCS_B outputs|||ns|
|TOSPICSCLK|Chip select asserted to next clock edge|||ns|
|TOSPICLKCS|CCLK edge to chip select deasserted|||ns|
|**Octal-SPI clock frequency operating at SDR > 51 MHz**|||||
|FOSPI_CLK|Octal-SPI clock frequency|51|150|MHz|



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Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics 

_Table 63:_ **Master Octal-SPI Mode Programming Switching** _(cont'd)_ 

|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics|
|---|---|---|---|---|
|_Table 63:_**Master Octal-SPI Mode Programming Switching**_(cont'd)_|||||
|**Symbol**|**Description1**|**Min**|**Max**|**Units**|
|TOSPIIVW|Input valid data window|||UI|
|TOSPICKO|Clock edge to OSPID[07:00] and FCS_B outputs|||ns|
|TOSPICSCLK|Chip select asserted to next clock edge|||ns|
|TOSPICLKCS|Clock edge to chip select deasserted|||ns|
|**Octal-SPI clock frequency operating at SDR < 51 MHz**|||||
|FOSPI_CLK|Octal-SPI clock frequency||50|MHz|
|TOSPIDCK|Setup time, all data inputs|||ns|
|TOSPICKD|Hold time, all data inputs|||ns|
|TOSPICKO|Clock edge to OSPID[07:00] and FCS_B outputs|||ns|
|TOSPICSCLK|Chip select asserted to next clock edge|||ns|
|TOSPICLKCS|Clock edge to chip select deasserted|||ns|
|**Notes:**<br>1.<br>The test conditions are configured for the Octal-SPI interface with a 12 mA drive strength, fast slew rate, and 12 pF load. The maximum<br>Octal-SPI device clock frequency under different load conditions are 150 MHz for a 20 pF load and 100 MHz for a 40 pF load.|||||



## **Revision History** 

The following table shows the revision history for this document. 

|**Section**|**Revision Summary**|
|---|---|
|**01/24/2025 Version 1.0**||
|Initial release.|N/A|



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APPLICATION WITHOUT A SAFETY DESIGN IS FULLY AT THE RISK OF CUSTOMER, SUBJECT ONLY TO APPLICABLE LAWS AND REGULATIONS GOVERNING LIMITATIONS ON PRODUCT LIABILITY. 

## **Copyright** 

© Copyright 2025 Advanced Micro Devices, Inc. AMD, the AMD Arrow logo, Spartan, UltraScale, UltraScale+, Vivado, and combinations thereof are trademarks of Advanced Micro Devices, Inc. PCI, PCIe, and PCI Express are trademarks of PCI-SIG and used under license. The DisplayPort Icon is a trademark of the Video Electronics Standards Association, registered in the U.S. and other countries. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. 

DS930 (v1.0) January 24, 2025 Advance Product Specification 

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Updated at June 5, 2026
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