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XCKU5P-1FFVB676I
FPGA, KIntex UltraScale+, MMCM, PLL, 280 I/O's, 630 MHz, 474600 Cells, 825-876 mV, FCBGA-676, NCNR
⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
- Manufacturer: AMD
- Product type: FPGAs
- No. of Logic Blocks:216960; No. of Macrocells:474600; FPGA Family:Kintex UltraScale+; Logic Case Style:FCBGA; No. of Pins:676Pins; No. of Speed Grades:-1; Total RAM Bits:16900Kbi
- MSL: -
- SVHC: No SVHC (15-Jan-2018)
- FPGA Type: -
- FPGA Family: Kintex UltraScale+
- IC Mounting: Surface Mount
- No. of Pins: 676Pins
- Speed Grade: 1
- No. of I/O's: 280I/O's
- Product Range: Kintex UltraScale+ XCKU5P
- Qualification: -
- Total RAM Bits: 16900Kbit
- No.of User I/Os: 280I/O's
- Clock Management: MMCM, PLL
- Logic Case Style: FCBGA
- IC Case / Package: FCBGA
- No. of Macrocells: 474600Macrocells
- I/O Supply Voltage: 3.3V
- No. of Logic Cells: 474600Logic Cells
- Process Technology: -
- No. of Logic Blocks: 474600
- No. of Speed Grades: 1
- Core Supply Voltage Max: 876mV
- Core Supply Voltage Min: 825mV
- Operating Frequency Max: 630MHz
- Operating Temperature Max: 100°C
- Operating Temperature Min: -40°C
| Delivery and price | |
|---|---|
| Units per pack | 1 |
| Price | 1945.65 € |
| Current stock | 10+ |
| Lead time | 30 days |
Datasheet
**Preliminary Product Specification**
**==> picture [164 x 47] intentionally omitted <==**
## **Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
DS922 (v1.3) May 8, 2017
## **Summary**
The Xilinx® Kintex® UltraScale+™ FPGAs are available in -3, -2, -1 speed grades, with -3E devices having the highest performance. The -2LE and -1LI devices can operate at a VCCINT voltage at 0.85V or 0.72V and = provide lower maximum static power. When operated at VCCINT 0.85V, using -2LE and -1LI devices, the speed specification for the L devices is the same as the -2I or -1I speed grades. When operated at VCCINT = 0.72V, the -2LE and -1LI performance and static and dynamic power is reduced.
DC and AC characteristics are specified in extended (E) and industrial (I) temperature ranges. Except the operating temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -1 speed grade extended device are the same as for a -1 speed grade industrial device). However, only selected speed grades and/or devices are available in each temperature range.
All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters included are common to popular designs and typical applications.
This data sheet, part of an overall set of documentation on the Kintex UltraScale+ FPGAs, is available on the Xilinx website at www.xilinx.com/documentation.
## **DC Characteristics**
## **Absolute Maximum Ratings**
_Table 1:_ **Absolute Maximum Ratings[(1)]**
|**Symbol**|**Description**|**Min**|**Max**|**Units**|
|---|---|---|---|---|
|**FPGA Logic**|||||
|VCCINT|Internal supply voltage.|–0.500|1.000|V|
|VCCINT_IO(2)|Internal supply voltage for the I/O banks.|–0.500|1.000|V|
|VCCAUX|Auxiliary supply voltage.|–0.500|2.000|V|
|VCCBRAM|Supply voltage for the block RAM memories.|–0.500|1.000|V|
|VCCO|Output drivers supply voltage for HD I/O banks.|–0.500|3.400|V|
||Output drivers supply voltage for HP I/O banks.|–0.500|2.000|V|
|VCCAUX_IO(3)|Auxiliary supply voltage for the I/O banks.|–0.500|2.000|V|
|VREF|Input reference voltage.|–0.500|2.000|V|
|VIN(4)(6)(7)|I/O input voltage for HD I/O banks.(5)|–0.550|VCCO + 0.550|V|
||I/O input voltage for HP I/O banks.|–0.550|VCCO + 0.550|V|
© Copyright 2015–2017 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries.
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**Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 1:_ **Absolute Maximum Ratings[(1)]** _**(Cont’d)**_
|**Symbol**|**Description**|**Min**|**Max**|**Units**|
|---|---|---|---|---|
|VBATT|Key memory battery backup supply.|–0.500|2.000|V|
|IDC|Available output current at the pad.|–20|20|mA|
|IRMS|Available RMS output current at the pad.|–20|20|mA|
|**GTH or GTY Transceiver**|||||
|VMGTAVCC|Analog supply voltage for transceiver circuits.|–0.500|1.000|V|
|VMGTAVTT|Analog supply voltage for transceiver termination circuits.|–0.500|1.300|V|
|VMGTVCCAUX|Auxiliary analog Quad PLL (QPLL) voltage supply for<br>transceivers.|–0.500|1.900|V|
|VMGTREFCLK|Transceiver reference clock absolute input voltage.|–0.500|1.300|V|
|VMGTAVTTRCAL|Analog supply voltage for the resistor calibration circuit of<br>the transceiver column.|–0.500|1.300|V|
|VIN|Receiver (RXP/RXN) and transmitter (TXP/TXN) absolute<br>input voltage.|–0.500|1.200|V|
|IDCIN-FLOAT|DC input current for receiver input pins DC coupled RX<br>termination = floating.(8)|–|10|mA|
|IDCIN-MGTAVTT|DC input current for receiver input pins DC coupled RX<br>termination = VMGTAVTT.|–|10|mA|
|IDCIN-GND|DC input current for receiver input pins DC coupled RX<br>termination = GND.(9)|–|0|mA|
|IDCIN-PROG|DC input current for receiver input pins DC coupled RX<br>termination = programmable.(10)|–|0|mA|
|IDCOUT-FLOAT|DC output current for transmitter pins DC coupled RX<br>termination = floating.|–|6|mA|
|IDCOUT-MGTAVTT|DC output current for transmitter pins DC coupled RX<br>termination = VMGTAVTT.|–|6|mA|
|**System Monitor**|||||
|VCCADC|System Monitor supply relative to GNDADC.|0.500|2.000|V|
|VREFP|System Monitor reference input relative to GNDADC.|0.500|2.000|V|
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**Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 1:_ **Absolute Maximum Ratings[(1)]** _**(Cont’d)**_
|**Symbol**|**Description**|**Min**|**Max**|**Units**|
|---|---|---|---|---|
|**Temperature**|||||
|TSTG|Storage temperature (ambient).|–65|150|°C|
|TSOL|Maximum soldering temperature.(12)|–|260|°C|
|Tj|Maximum junction temperature.(12)|–|125|°C|
## **Notes:**
1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
2. VCCINT_IO must be connected to VCCBRAM.
3. VCCAUX_IO must be connected to VCCAUX.
4. The lower absolute voltage specification always applies.
5. If VCCO is 3.3V, the maximum voltage is 3.4V.
6. For I/O operation, see the _UltraScale Architecture SelectIO Resources User Guide_ (UG571).
7. When operating outside of the recommended operating conditions, refer to Table 4 and Table 5 for maximum overshoot and undershoot specifications.
8. AC coupled operation is not supported for RX termination = floating.
9. For GTY transceivers, DC coupled operation is not supported for RX termination = GND.
10. DC coupled operation is not supported for RX termination = programmable.
11. For more information on supported GTH or GTY transceiver terminations see the _UltraScale Architecture GTH Transceiver User Guide_ (UG576) or _UltraScale Architecture GTY Transceiver User Guide_ (UG578).
12. For soldering guidelines and thermal considerations, see the _UltraScale and UltraScale+ FPGAs Packaging and Pinout Specifications_ (UG575).
## **Recommended Operating Conditions**
_Table 2:_ **Recommended Operating Conditions[(1)(2)]**
|**Symbol**|**Description**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|
|**FPGA Logic**||||||
|VCCINT|Internal supply voltage.|0.825|0.850|0.876|V|
||For -1LI and -2LE devices (VCCINT = 0.72V):<br>internal supply voltage.|0.698|0.720|0.742|V|
||For -3E devices: internal supply voltage.|0.873|0.900|0.927|V|
|VCCINT_IO(3)|Internal supply voltage for the I/O banks.|0.825|0.850|0.876|V|
||For -1LI and -2LE devices (VCCINT = 0.72V):<br>internal supply voltage for the I/O banks.|0.825|0.850|0.876|V|
||For -3E devices: internal supply voltage for the I/O banks.|0.873|0.900|0.927|V|
|VCCBRAM|Block RAM supply voltage.|0.825|0.850|0.876|V|
||For -3E devices: block RAM supply voltage.|0.873|0.900|0.927|V|
|VCCAUX|Auxiliary supply voltage.|1.746|1.800|1.854|V|
|VCCO(4)(5)|Supply voltage for HD I/O banks.|1.140|–|3.400|V|
||Supply voltage for HP I/O banks.|0.950|–|1.900|V|
|VCCAUX_IO(6)|Auxiliary I/O supply voltage.|1.746|1.800|1.854|V|
|VIN(7)|I/O input voltage.|–0.200|–|VCCO + 0.200|V|
|IIN(8)|Maximum current through any pin in a powered or<br>unpowered bank when forward biasing the clamp diode.|–|–|10|mA|
|VBATT(9)|Battery voltage|1.000|–|1.890|V|
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**Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 2:_ **Recommended Operating Conditions[(1)(2)]** _**(Cont’d)**_
|**Symbol**|**Description**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|
|**GTH or GTY Transceiver**||||||
|VMGTAVCC(10)|Analog supply voltage for the GTH or GTY transceiver.|0.873|0.900|0.927|V|
|VMGTAVTT(10)|Analog supply voltage for the GTH or GTY transmitter and<br>receiver termination circuits.|1.164|1.200|1.236|V|
|VMGTVCCAUX(10)|Auxiliary analog QPLL voltage supply for the transceivers.|1.746|1.800|1.854|V|
|VMGTAVTTRCAL(10)|Analog supply voltage for the resistor calibration circuit of<br>the GTH or GTY transceiver column.|1.164|1.200|1.236|V|
|**SYSMON**||||||
|VCCADC|SYSMON supply relative to GNDADC.|1.746|1.800|1.854|V|
|VREFP|SYSMON externally supplied reference voltage relative to<br>GNDADC.|1.200|1.250|1.300|V|
|**Temperature**||||||
|Tj(12)|Junction temperature operating range for extended (E)<br>temperature devices.(11)|0|–|100|°C|
||Junction temperature operating range for industrial (I)<br>temperature devices.|–40|–|100|°C|
||Junction temperature operating range for eFUSE<br>programming.(13)|–40|–|125|°C|
## **Notes:**
1. All voltages are relative to GND.
2. For the design of the power distribution system consult _UltraScale Architecture PCB Design Guide_ (UG583).
3. VCCINT_IO must be connected to VCCBRAM.
4. For VCCO_0, the minimum recommended operating voltage for power on and during configuration is 1.425V. After configuration, data is retained even if VCCO drops to 0V.
5. Includes VCCO of 1.0V (HP I/O only), 1.2V, 1.35V, 1.5V, 1.8V, 2.5V (HD I/O only) at ±5%, and 3.3V (HD I/O only) at +3/–5%.
6. VCCAUX_IO must be connected to VCCAUX.
7. The lower absolute voltage specification always applies.
8. A total of 200 mA per bank should not be exceeded.
9. If battery is not used, connect VBATT to either GND or VCCAUX.
10. Each voltage listed requires filtering as described in _UltraScale Architecture GTH Transceiver User Guide_ (UG576) or _UltraScale Architecture GTY Transceiver User Guide_ (UG578).
11. Devices labeled with the speed/temperature grade of -2LE normally operate under Extended (E) temperature grade specifications with a maximum junction temperature of 100°C. However, E temperature grade devices can operate for a for a limited time at a junction temperature of 110°C. Timing parameters adhere to the same speed file at 110°C as they do at 100°C, regardless of operating voltage (nominal voltage of 0.85V or a low-voltage of 0.72V). Operation at Tj = 110°C is limited to 1% of the device lifetime and can occur sequentially or at regular intervals as long as the total time does not exceed 1% of the device lifetime.
12. Xilinx recommends measuring the Tj of a device using the system monitor as described in the _UltraScale Architecture System Monitor User Guide_ (UG580). The SYSMON temperature measurement errors (that are described in Table 76) must be accounted for in your design. For example, by using an external reference of 1.25V, when SYSMON reports 97°C, there is a measurement error ±3°C. A reading of 97°C is considered the maximum adjusted Tj (100°C – 3°C = 97°C).
13. Do not program eFUSE during device configuration (e.g., during configuration, during configuration readback, or when readback CRC is active).
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**Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
## **DC Characteristics Over Recommended Operating Conditions**
_Table 3:_ **DC Characteristics Over Recommended Operating Conditions**
|**Symbol**|**Description**|**Min**|**Typ(1)**|**Max**|**Units**|
|---|---|---|---|---|---|
|VDRINT|Data retention VCCINTvoltage (below which configuration<br>data might be lost).|0.68|–|–|V|
|VDRAUX|Data retention VCCAUXvoltage (below which configuration<br>data might be lost).|1.5|–|–|V|
|IREF|VREFleakage current per pin.|–|–|15|µA|
|IL|Input or output leakage current per pin (sample-tested).(2)|–|–|15|µA|
|CIN(3)|Die input capacitance at the pad (HP I/O).|–|–|3.1|pF|
||Die input capacitance at the pad (HD I/O).|–|–|4.75|pF|
|IRPU|Pad pull-up (when selected) at VIN = 0V, VCCO = 3.3V.|75|–|190|µA|
||Pad pull-up (when selected) at VIN = 0V, VCCO = 2.5V.|50|–|169|µA|
||Pad pull-up (when selected) at VIN = 0V, VCCO = 1.8V.|60|–|120|µA|
||Pad pull-up (when selected) at VIN = 0V, VCCO = 1.5V.|30|–|120|µA|
||Pad pull-up (when selected) at VIN = 0V, VCCO = 1.2V.|10|–|100|µA|
|IRPD|Pad pull-down (when selected) at VIN = 3.3V.|60|–|200|µA|
||Pad pull-down (when selected) at VIN = 1.8V.|29|–|120|µA|
|ICCADCON|Analog supply current for the SYSMON circuits in the<br>power-up state.|–|–|8|mA|
|ICCADCOFF|Analog supply current for the SYSMON circuits in the<br>power-down state.|–|–|1.5|mA|
|IBATT(4)(5)|Battery supply current at VBATT = 1.89V.|–|–|650|nA|
||Battery supply current at VBATT = 1.20V.|–|–|150|nA|
|IPFS(6)|VCCAUXadditional supply current during eFUSE programming.|–|–|115|mA|
|_Calibrated programmable on-die termination (DCI) in HP I/O banks(7) (measured per JEDEC specification)._||||||
|R(9)|Thevenin equivalent resistance of programmable input<br>termination to VCCO/2 where ODT = RTT_40.|–10%(8)|40|+10%(8)|Ω|
||Thevenin equivalent resistance of programmable input<br>termination to VCCO/2 where ODT = RTT_48.|–10%(8)|48|+10%(8)|Ω|
||Thevenin equivalent resistance of programmable input<br>termination to VCCO/2 where ODT = RTT_60.|–10%(8)|60|+10%(8)|Ω|
||Programmable input termination to VCCOwhere<br>ODT = RTT_40.|–10%(8)|40|+10%(8)|Ω|
||Programmable input termination to VCCOwhere<br>ODT = RTT_48.|–10%(8)|48|+10%(8)|Ω|
||Programmable input termination to VCCOwhere<br>ODT = RTT_60.|–10%(8)|60|+10%(8)|Ω|
||Programmable input termination to VCCOwhere<br>ODT = RTT_120.|–10%(8)|120|+10%(8)|Ω|
||Programmable input termination to VCCOwhere<br>ODT = RTT_240.|–10%(8)|240|+10%(8)|Ω|
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**Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 3:_ **DC Characteristics Over Recommended Operating Conditions** _**(Cont’d)**_
|**Symbol**|**Description**|**Min**|**Typ(1)**|**Max**|**Units**|
|---|---|---|---|---|---|
|_Uncalibrated programmable on-die termination in HP I/O banks (measured per JEDEC specification)._||||||
|R(9)|Thevenin equivalent resistance of programmable input<br>termination to VCCO/2 where ODT = RTT_40.|–50%|40|+50%|Ω|
||Thevenin equivalent resistance of programmable input<br>termination to VCCO/2 where ODT = RTT_48.|–50%|48|+50%|Ω|
||Thevenin equivalent resistance of programmable input<br>termination to VCCO/2 where ODT = RTT_60.|–50%|60|+50%|Ω|
||Programmable input termination to VCCOwhere<br>ODT = RTT_40.|–50%|40|+50%|Ω|
||Programmable input termination to VCCOwhere<br>ODT = RTT_48.|–50%|48|+50%|Ω|
||Programmable input termination to VCCOwhere<br>ODT = RTT_60.|–50%|60|+50%|Ω|
||Programmable input termination to VCCOwhere<br>ODT = RTT_120.|–50%|120|+50%|Ω|
||Programmable input termination to VCCOwhere<br>ODT = RTT_240.|–50%|240|+50%|Ω|
|_Uncalibrated programmable on-die termination in HD I/O banks (measured per JEDEC specification)._||||||
|R(9)|Thevenin equivalent resistance of programmable input<br>termination to VCCO/2 where ODT = RTT_48.|–50%|48|+50%|Ω|
|Internal VREF|50% VCCO|VCCO x<br>0.49|VCCO x<br>0.50|VCCO x<br>0.51|V|
||70% VCCO|VCCO x<br>0.69|VCCO x<br>0.70|VCCO x<br>0.71|V|
|Differential<br>termination|Programmable differential termination (TERM_100)<br>for HP I/O banks.|–35%|100|+35%|Ω|
|n|Temperature diode ideality factor.|–|1.026|–|–|
|r|Temperature diode series resistance.|–|2|–|Ω|
## **Notes:**
1. Typical values are specified at nominal voltage, 25°C.
2. For HP I/O banks with a VCCO of 1.8V and separated VCCO and VCCAUX_IO power supplies, the IL maximum current is 70 µA.
3. This measurement represents the die capacitance at the pad, not including the package.
4. Maximum value specified for worst case process at 25°C.
5. IBATT is measured when the battery-backed RAM (BBRAM) is enabled.
6. Do not program eFUSE during device configuration (e.g., during configuration, during configuration readback, or when readback CRC is active).
7. If VRP resides at a different bank (DCI cascade), the range increases to ±15%.
8. VRP resistor tolerance is (240 Ω ±1%)
9. On-die input termination resistance, for more information see the _UltraScale Architecture SelectIO Resources User Guide_ (UG571).
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**Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
## **VIN Maximum Allowed AC Voltage Overshoot and Undershoot**
_Table 4:_ **VIN Maximum Allowed AC Voltage Overshoot and Undershoot for HD I/O Banks[(1)]**
|_Table 4:_ **VIN Maximu**|**m Allowed AC Voltage Over**|**shoot and Undershoot**|**for HD I/O Banks()**|
|---|---|---|---|
|**AC Voltage Overshoot **|**% of UI at –40°C to 100°C **|**AC Voltage Undershoot **|**% of UI at –40°C to 100°C**|
|VCCO + 0.30|100%|–0.30|100%|
|VCCO + 0.35|100%|–0.35|90%|
|VCCO + 0.40|100%|–0.40|78%|
|VCCO + 0.45|100%|–0.45|40%|
|VCCO + 0.50|100%|–0.50|24%|
|VCCO + 0.55|100%|–0.55|18.0%|
|VCCO + 0.60|100%|–0.60|13.0%|
|VCCO + 0.65|100%|–0.65|10.8%|
|VCCO + 0.70|92%|–0.70|9.0%|
|VCCO + 0.75|92%|–0.75|7.0%|
|VCCO + 0.80|92%|–0.80|6.0%|
|VCCO + 0.85|92%|–0.85|5.0%|
|VCCO + 0.90|92%|–0.90|4.0%|
|VCCO + 0.95|92%|–0.95|2.5%|
## **Notes:**
1. A total of 200 mA per bank should not be exceeded.
_Table 5:_ **VIN Maximum Allowed AC Voltage Overshoot and Undershoot for HP I/O Banks[(1)(2)]**
|**AC Voltage Overshoot **|**% of UI at –40°C to 100°C **|**AC Voltage Undershoot **|**% of UI at –40°C to 100°C**|
|---|---|---|---|
|VCCO + 0.30|100%|–0.30|100%|
|VCCO + 0.35|100%|–0.35|90%|
|VCCO + 0.40|92%|–0.40|92%|
|VCCO + 0.45|50%|–0.45|50%|
|VCCO + 0.50|20%|–0.50|20%|
|VCCO + 0.55|10%|–0.55|10%|
|VCCO + 0.60|6%|–0.60|6%|
|VCCO + 0.65|2%|–0.65|2%|
|VCCO + 0.70|2%|–0.70|2%|
## **Notes:**
1. A total of 200 mA per bank should not be exceeded.
2. For UI smaller than 20 µs.
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**Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
## **Quiescent Supply Current**
_Table 6:_ **Typical Quiescent Supply Current[(1)(2)(3)]**
|**Symbol**|**Description**|**Device**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Units**|
|---|---|---|---|---|---|---|---|---|
||||**0.90V**|**0.85V**||**0.72V**|||
||||**-3**|**-2**|**-1**|**-2**|**-1**||
|ICCINTQ|Quiescent VCCINTsupply current.|XCKU3P|1242|1181|1181|1037|1037|mA|
|||XCKU5P|1242|1181|1181|1037|1037|mA|
|||XCKU9P|1592|1523|1523|1356|1356|mA|
|||XCKU11P|1780|1693|1693|1486|1486|mA|
|||XCKU13P|1950|1864|1864|1658|1658|mA|
|||XCKU15P|2677|2559|2559|2275|2275|mA|
|ICCINT_IOQ|Quiescent VCCINT_IOsupply current.|XCKU3P|61|59|59|59|59|mA|
|||XCKU5P|61|59|59|59|59|mA|
|||XCKU9P|61|59|59|59|59|mA|
|||XCKU11P|120|115|115|115|115|mA|
|||XCKU13P|61|59|59|59|59|mA|
|||XCKU15P|164|158|158|158|158|mA|
|ICCOQ|Quiescent VCCOsupply current.|All devices|1|1|1|1|1|mA|
|ICCAUXQ|Quiescent VCCAUXsupply current.|XCKU3P|153|153|153|153|153|mA|
|||XCKU5P|153|153|153|153|153|mA|
|||XCKU9P|227|227|227|227|227|mA|
|||XCKU11P|255|255|255|255|255|mA|
|||XCKU13P|266|266|266|266|266|mA|
|||XCKU15P|396|396|396|396|396|mA|
|ICCAUX_IOQ|Quiescent VCCAUX_IOsupply current.|XCKU3P|32|32|32|32|32|mA|
|||XCKU5P|32|32|32|32|32|mA|
|||XCKU9P|33|33|33|33|33|mA|
|||XCKU11P|56|56|56|56|56|mA|
|||XCKU13P|33|33|33|33|33|mA|
|||XCKU15P|74|74|74|74|74|mA|
|ICCBRAMQ|Quiescent VCCBRAMsupply current.|XCKU3P|18|17|17|17|17|mA|
|||XCKU5P|18|17|17|17|17|mA|
|||XCKU9P|25|24|24|24|24|mA|
|||XCKU11P|23|22|22|22|22|mA|
|||XCKU13P|29|28|28|28|28|mA|
|||XCKU15P|37|35|35|35|35|mA|
## **Notes:**
1. Typical values are specified at nominal voltage, 85°C junction temperatures (Tj) with single-ended SelectIO™ resources.
2. Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and floating.
3. Use the Xilinx Power Estimator (XPE) spreadsheet tool (download at www.xilinx.com/power) to estimate static power consumption for conditions other than those specified.
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**Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
## **Power-On/Off Power Supply Sequencing**
The recommended power-on sequence is VCCINT, VCCINT_IO/VCCBRAM, VCCAUX/VCCAUX_IO, and VCCO to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on. The recommended power-off sequence is the reverse of the power-on sequence. If VCCINT and VCCINT_IO/VCCBRAM have the same recommended voltage levels, they can be powered by the same supply and ramped simultaneously. VCCINT_IO must be connected to VCCBRAM. If VCCAUX/VCCAUX_IO and VCCO have the same recommended voltage levels, they can be powered by the same supply and ramped simultaneously. VCCAUX and VCCAUX_IO must be connected together. VCCADC and VREF can be powered at any time and have no power-up sequencing requirements.
The recommended power-on sequence to achieve minimum current draw for the GTH or GTY transceivers is VCCINT, VMGTAVCC, VMGTAVTT OR VMGTAVCC, VCCINT, VMGTAVTT. There is no recommended sequencing for VMGTVCCAUX. Both VMGTAVCC and VCCINT can be ramped simultaneously. The recommended power-off sequence is the reverse of the power-on sequence to achieve minimum current draw.
If these recommended sequences are not met, current drawn from VMGTAVTT can be higher than specifications during power-up and power-down.
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**Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
## **Power Supply Requirements**
Table 7 shows the minimum current, in addition to ICCQ maximum, required by each Kintex UltraScale+ FPGA for proper power-on and configuration. If the current minimums shown in Table 7 are met, the device powers on after all supplies have passed through their power-on reset threshold voltages. The device must not be configured until after VCCINT is applied. Once initialized and configured, use the Xilinx Power Estimator (XPE) tools to estimate current drain on these supplies.
_Table 7:_ **Power-on Current by Device[(1)]**
|**Device**|**ICCINTMIN**|**ICCINT_IOMIN + ICCBRAMMIN**|**ICCOMIN**|**ICCAUXMIN + ICCAUX_IOMIN**|**Units**|
|---|---|---|---|---|---|
|XCKU3P|ICCINTQ + 770|ICCBRAMQ + ICCINT_IOQ + 229|ICCOQ + 50|ICCAUXQ + ICCAUX_IOQ + 386|mA|
|XCKU5P|ICCINTQ + 770|ICCBRAMQ + ICCINT_IOQ + 305|ICCOQ + 50|ICCAUXQ + ICCAUX_IOQ + 515|mA|
|XCKU9P|ICCINTQ + 1800|ICCBRAMQ + ICCINT_IOQ + 600|ICCOQ + 50|ICCAUXQ + ICCAUX_IOQ + 650|mA|
|XCKU11P|ICCINTQ + 1961|ICCBRAMQ + ICCINT_IOQ + 654|ICCOQ + 55|ICCAUXQ + ICCAUX_IOQ + 709|mA|
|XCKU13P|ICCINTQ + 2242|ICCBRAMQ + ICCINT_IOQ + 748|ICCOQ + 63|ICCAUXQ + ICCAUX_IOQ + 810|mA|
|XCKU15P|ICCINTQ + 3433|ICCBRAMQ + ICCINT_IOQ + 1145|ICCOQ + 96|ICCAUXQ + ICCAUX_IOQ + 1240|mA|
## **Notes:**
1. Use the Xilinx Power Estimator (XPE) spreadsheet tool (download at www.xilinx.com/power) to estimate power-on current for all supplies.
Table 8 shows the power supply ramp time.
_Table 8:_ **Power Supply Ramp Time**
|**Symbol**|**Description**|**Min**|**Max**|**Units**|
|---|---|---|---|---|
|TVCCINT|Ramp time from GND to 95% of VCCINT.|0.2|40|ms|
|TVCCINT_IO|Ramp time from GND to 95% of VCCINT_IO.|0.2|40|ms|
|TVCCO|Ramp time from GND to 95% of VCCO.|0.2|40|ms|
|TVCCAUX|Ramp time from GND to 95% of VCCAUX.|0.2|40|ms|
|TVCCBRAM|Ramp time from GND to 95% of VCCBRAM.|0.2|40|ms|
|TMGTAVCC|Ramp time from GND to 95% of VMGTAVCC.|0.2|40|ms|
|TMGTAVTT|Ramp time from GND to 95% of VMGTAVTT.|0.2|40|ms|
|TMGTVCCAUX|Ramp time from GND to 95% of VMGTVCCAUX.|0.2|40|ms|
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**Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
## **DC Input and Output Levels**
Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the recommended operating conditions at the VOL and VOH test points. Only selected standards are tested. These are chosen to ensure that all standards meet their specifications. The selected standards are tested at a minimum VCCO with the respective VOL and VOH voltage levels shown. Other standards are sample tested.
_Table 9:_ **SelectIO DC Input and Output Levels For HD I/O Banks[(1)(2)(3)]**
|**I/O**<br>**Standard**|**VIL**|**VIL**|**VIH**|**VIH**|**VOL**|**VOH**|**IOL**|**IOH**|
|---|---|---|---|---|---|---|---|---|
||**V, Min**|**V, Max**|**V, Min**|**V, Max**|**V, Max**|**V, Min**|**mA**|**mA**|
|HSTL_I|–0.300|VREF – 0.100|VREF + 0.100|VCCO + 0.300|0.400|VCCO – 0.400|8.0|–8.0|
|HSTL_I_18|–0.300|VREF – 0.100|VREF + 0.100|VCCO + 0.300|0.400|VCCO – 0.400|8.0|–8.0|
|HSUL_12|–0.300|VREF – 0.130|VREF + 0.130|VCCO + 0.300|20% VCCO|80% VCCO|0.1|–0.1|
|LVCMOS12|–0.300|35% VCCO|65% VCCO|VCCO + 0.300|0.400|VCCO – 0.400|Note 4|Note 4|
|LVCMOS15|–0.300|35% VCCO|65% VCCO|VCCO + 0.300|0.450|VCCO – 0.450|Note 5|Note 5|
|LVCMOS18|–0.300|35% VCCO|65% VCCO|VCCO + 0.300|0.450|VCCO – 0.450|Note 5|Note 5|
|LVCMOS25|–0.300|0.700|1.700|VCCO + 0.300|0.400|VCCO – 0.400|Note 5|Note 5|
|LVCMOS33|–0.300|0.800|2.000|3.400|0.400|VCCO – 0.400|Note 5|Note 5|
|LVTTL|–0.300|0.800|2.000|3.400|0.400|2.400|Note 5|Note 5|
|SSTL12|–0.300|VREF – 0.100|VREF + 0.100|VCCO + 0.300|VCCO/2 – 0.150|VCCO/2 + 0.150|14.25|–14.25|
|SSTL135|–0.300|VREF – 0.090|VREF + 0.090|VCCO + 0.300|VCCO/2 – 0.150|VCCO/2 + 0.150|8.9|–8.9|
|SSTL135_II|–0.300|VREF – 0.090|VREF + 0.090|VCCO + 0.300|VCCO/2 – 0.150|VCCO/2 + 0.150|13.0|–13.0|
|SSTL15|–0.300|VREF – 0.100|VREF + 0.100|VCCO + 0.300|VCCO/2 – 0.175|VCCO/2 + 0.175|8.9|–8.9|
|SSTL15_II|–0.300|VREF – 0.100|VREF + 0.100|VCCO + 0.300|VCCO/2 – 0.175|VCCO/2 + 0.175|13.0|–13.0|
|SSTL18_I|–0.300|VREF – 0.125|VREF + 0.125|VCCO + 0.300|VCCO/2 – 0.470|VCCO/2 + 0.470|8.0|–8.0|
|SSTL18_II|–0.300|VREF – 0.125|VREF + 0.125|VCCO + 0.300|VCCO/2 – 0.600|VCCO/2 + 0.600|13.4|–13.4|
## **Notes:**
1. Tested according to relevant specifications.
2. Standards specified using the default I/O standard configuration. For details, see the _UltraScale Architecture SelectIO Resources User Guide_ (UG571).
3. POD10 and POD12 DC input and output levels are shown in Table 11, Table 15, Table 16, and Table 17.
4. Supported drive strengths of 4, 8, or 12 mA in HD I/O banks.
5. Supported drive strengths of 4, 8, 12, or 16 mA in HD I/O banks.
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**Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 10:_ **SelectIO DC Input and Output Levels for HP I/O Banks[(1)(2)(3)]**
|**I/O**<br>**Standard**|**VIL**|**VIL**|**VIH**|**VIH**|**VOL**|**VOH**|**IOL**|**IOH**|
|---|---|---|---|---|---|---|---|---|
||**V, Min**|**V, Max**|**V, Min**|**V, Max**|**V, Max**|**V, Min**|**mA**|**mA**|
|HSTL_I|–0.300|VREF – 0.100|VREF + 0.100|VCCO + 0.300|0.400|VCCO – 0.400|5.8|–5.8|
|HSTL_I_12|–0.300|VREF – 0.080|VREF + 0.080|VCCO + 0.300|25% VCCO|75% VCCO|4.1|–4.1|
|HSTL_I_18|–0.300|VREF – 0.100|VREF + 0.100|VCCO + 0.300|0.400|VCCO – 0.400|6.2|–6.2|
|HSUL_12|–0.300|VREF – 0.130|VREF + 0.130|VCCO + 0.300|20% VCCO|80% VCCO|0.1|–0.1|
|LVCMOS12|–0.300|35% VCCO|65% VCCO|VCCO + 0.300|0.400|VCCO – 0.400|Note 4|Note 4|
|LVCMOS15|–0.300|35% VCCO|65% VCCO|VCCO + 0.300|0.450|VCCO – 0.450|Note 5|Note 5|
|LVCMOS18|–0.300|35% VCCO|65% VCCO|VCCO + 0.300|0.450|VCCO – 0.450|Note 5|Note 5|
|LVDCI_15|–0.300|35% VCCO|65% VCCO|VCCO + 0.300|0.450|VCCO – 0.450|7.0|–7.0|
|LVDCI_18|–0.300|35% VCCO|65% VCCO|VCCO + 0.300|0.450|VCCO – 0.450|7.0|–7.0|
|SSTL12|–0.300|VREF – 0.100|VREF + 0.100|VCCO + 0.300|VCCO/2 – 0.150|VCCO/2 + 0.150|8.0|–8.0|
|SSTL135|–0.300|VREF – 0.090|VREF + 0.090|VCCO + 0.300|VCCO/2 – 0.150|VCCO/2 + 0.150|9.0|–9.0|
|SSTL15|–0.300|VREF – 0.100|VREF + 0.100|VCCO + 0.300|VCCO/2 – 0.175|VCCO/2 + 0.175|10.0|–10.0|
|SSTL18_I|–0.300|VREF – 0.125|VREF + 0.125|VCCO + 0.300|VCCO/2 – 0.470|VCCO/2 + 0.470|7.0|–7.0|
|MIPI_DPHY_<br>DCI_LP(6)|–0.300|0.550|0.880|VCCO + 0.300|0.050|1.100|0.01|–0.01|
## **Notes:**
1. Tested according to relevant specifications.
2. Standards specified using the default I/O standard configuration. For details, see the _UltraScale Architecture SelectIO Resources User Guide_ (UG571).
3. POD10 and POD12 DC input and output levels are shown in Table 11, Table 15, Table 16, and Table 17.
4. Supported drive strengths of 2, 4, 6, or 8 mA in HP I/O banks.
5. Supported drive strengths of 2, 4, 6, 8, or 12 mA in HP I/O banks.
6. Low-power option for MIPI_DPHY_DCI.
_Table 11:_ **DC Input Levels for Single-ended POD10 and POD12 I/O Standards[(1)(2)]**
|**I/O**<br>**Standard**|**VIL**|**VIL**|**VIH**|**VIH**|
|---|---|---|---|---|
||**V, Min**|**V, Max**|**V, Min**|**V, Max**|
|POD10|–0.300|VREF – 0.068|VREF + 0.068|VCCO + 0.300|
|POD12|–0.300|VREF – 0.068|VREF + 0.068|VCCO + 0.300|
## **Notes:**
1. Tested according to relevant specifications.
2. Standards specified using the default I/O standard configuration. For details, see the _UltraScale Architecture SelectIO Resources User Guide_ (UG571).
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_Table 12:_ **Differential SelectIO DC Input and Output Levels**
|**I/O**<br>**Standard**|**VICM(V)(1)**|**VICM(V)(1)**|**VICM(V)(1)**|**VID(V)(2)**|**VID(V)(2)**|**VID(V)(2)**|**VILHS(3)**|**VIHHS(3)**|**VOCM(V)(4)**|**VOCM(V)(4)**|**VOCM(V)(4)**|**VOD(V)(5)**|**VOD(V)(5)**|**VOD(V)(5)**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||**Min**|**Typ**|**Max**|**Min**|**Typ**|**Max**|**Min**|**Max**|**Min**|**Typ**|**Max**|**Min**|**Typ**|**Max**|
|SUB_LVDS(8)|0.500|0.900|1.300|0.070|–|–|–|–|0.700|0.900|1.100|0.100|0.150|0.200|
|LVPECL|0.300|1.200|1.425|0.100|0.350|0.600|–|–|–|–|–|–|–|–|
|SLVS_400_18|0.070|0.200|0.330|0.140|–|0.450|–|–|–|–|–|–|–|–|
|SLVS_400_25|0.070|0.200|0.330|0.140|–|0.450|–|–|–|–|–|–|–|–|
|MIPI_DPHY_<br>DCI_HS(9)|0.070|–|0.330|0.070|–|–|–0.040|0.460|0.150|0.200|0.250|0.140|0.200|0.270|
## **Notes:**
1. VICM is the input common mode voltage.
2. VID is the input differential voltage (Q – Q).
3. VIHHS and VILHS are the single-ended input high and low voltages, respectively.
4. VOCM is the output common mode voltage.
5. VOD is the output differential voltage (Q – Q).
6. LVDS_25 is specified in Table 18.
7. LVDS is specified in Table 19.
8. Only the SUB_LVDS receiver is supported in HD I/O banks.
9. High-speed option for MIPI_DPHY_DCI. The VID maximum is aligned with the standard’s specification. A higher VID is acceptable as long as the VIN specification is also met.
_Table 13:_ **Complementary Differential SelectIO DC Input and Output Levels for HD I/O Banks**
|**I/O Standard**|**VICM(V)(1)**|**VICM(V)(1)**|**VICM(V)(1)**|**VID (V)(2)**|**VID (V)(2)**|**VOL(V)(3)**|**VOH(V)(4)**|**IOL**|**IOH**|
|---|---|---|---|---|---|---|---|---|---|
||**Min**|**Typ**|**Max**|**Min**|**Max**|**Max**|**Min**|**mA**|**mA**|
|DIFF_HSTL_I|0.300|0.750|1.125|0.100|–|0.400|VCCO – 0.400|8.0|–8.0|
|DIFF_HSTL_I_18|0.300|0.900|1.425|0.100|–|0.400|VCCO – 0.400|8.0|–8.0|
|DIFF_HSUL_12|0.300|0.600|0.850|0.100|–|20% VCCO|80% VCCO|0.1|–0.1|
|DIFF_SSTL12|0.300|0.600|0.850|0.100|–|(VCCO/2) – 0.150|(VCCO/2) + 0.150|14.25|–14.25|
|DIFF_SSTL135|0.300|0.675|1.000|0.100|–|(VCCO/2) – 0.150|(VCCO/2) + 0.150|8.9|–8.9|
|DIFF_SSTL135_II|0.300|0.675|1.000|0.100|–|(VCCO/2) – 0.150|(VCCO/2) + 0.150|13.0|–13.0|
|DIFF_SSTL15|0.300|0.750|1.125|0.100|–|(VCCO/2) – 0.175|(VCCO/2) + 0.175|8.9|–8.9|
|DIFF_SSTL15_II|0.300|0.750|1.125|0.100|–|(VCCO/2) – 0.175|(VCCO/2) + 0.175|13.0|–13.0|
|DIFF_SSTL18_I|0.300|0.900|1.425|0.100|–|(VCCO/2) – 0.470|(VCCO/2) + 0.470|8.0|–8.0|
|DIFF_SSTL18_II|0.300|0.900|1.425|0.100|–|(VCCO/2) – 0.600|(VCCO/2) + 0.600|13.4|–13.4|
## **Notes:**
1. VICM is the input common mode voltage.
2. VID is the input differential voltage.
3. VOL is the single-ended low-output voltage.
4. VOH is the single-ended high-output voltage.
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_Table 14:_ **Complementary Differential SelectIO DC Input and Output Levels for HP I/O Banks[(1)]**
|**I/O Standard**|**VICM(V)(2)**|**VICM(V)(2)**|**VICM(V)(2)**|**VID (V)(3)**|**VID (V)(3)**|**VOL(V)(4)**|**VOH(V)(5)**|**IOL**|**IOH**|
|---|---|---|---|---|---|---|---|---|---|
||**Min**|**Typ**|**Max**|**Min**|**Max**|**Max**|**Min**|**mA**|**mA**|
|DIFF_HSTL_I|0.680|VCCO/2|(VCCO/2) + 0.150|0.100|–|0.400|VCCO – 0.400|5.8|–5.8|
|DIFF_HSTL_I_12|0.400 x VCCO|VCCO/2|0.600 x VCCO|0.100|–|0.250 x VCCO|0.750 x VCCO|4.1|–4.1|
|DIFF_HSTL_I_18|(VCCO/2) – 0.175|VCCO/2|(VCCO/2) + 0.175|0.100|–|0.400|VCCO – 0.400|6.2|–6.2|
|DIFF_HSUL_12|(VCCO/2) – 0.120|VCCO/2|(VCCO/2) + 0.120|0.100|–|20% VCCO|80% VCCO|0.1|–0.1|
|DIFF_SSTL12|(VCCO/2) – 0.150|VCCO/2|(VCCO/2) + 0.150|0.100|–|(VCCO/2) – 0.150|(VCCO/2) + 0.150|8.0|–8.0|
|DIFF_SSTL135|(VCCO/2) – 0.150|VCCO/2|(VCCO/2) + 0.150|0.100|–|(VCCO/2) – 0.150|(VCCO/2) + 0.150|9.0|–9.0|
|DIFF_SSTL15|(VCCO/2) – 0.175|VCCO/2|(VCCO/2) + 0.175|0.100|–|(VCCO/2) – 0.175|(VCCO/2) + 0.175|10.0|–10.0|
|DIFF_SSTL18_I|(VCCO/2) – 0.175|VCCO/2|(VCCO/2) + 0.175|0.100|–|(VCCO/2) – 0.470|(VCCO/2) + 0.470|7.0|–7.0|
## **Notes:**
1. DIFF_POD10 and DIFF_POD12 HP I/O bank specifications are shown in Table 15, Table 16, and Table 17.
2. VICM is the input common mode voltage.
3. VID is the input differential voltage.
4. VOL is the single-ended low-output voltage.
5. VOH is the single-ended high-output voltage.
_Table 15:_ **DC Input Levels for Differential POD10 and POD12 I/O Standards[(1)(2)]**
|**I/O Standard**|**VICM(V)**|**VICM(V)**|**VICM(V)**|**VID (V)**|**VID (V)**|
|---|---|---|---|---|---|
||**Min**|**Typ**|**Max**|**Min**|**Max**|
|DIFF_POD10|0.63|0.70|0.77|0.14|–|
|DIFF_POD12|0.76|0.84|0.92|0.16|–|
## **Notes:**
1. Tested according to relevant specifications.
2. Standards specified using the default I/O standard configuration. For details, see the _UltraScale Architecture SelectIO Resources User Guide_ (UG571).
_Table 16:_ **DC Output Levels for Single-ended and Differential POD10 and POD12 Standards[(1)(2)]**
|**Symbol**|**Description**|**VOUT**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|ROL|Pull-down resistance.|VOM_DC(as described inTable 17)|36|40|44|Ω|
|ROH|Pull-up resistance.|VOM_DC(as described inTable 17)|36|40|44|Ω|
## **Notes:**
1. Tested according to relevant specifications.
2. Standards specified using the default I/O standard configuration. For details, see the _UltraScale Architecture SelectIO Resources User Guide_ (UG571).
_Table 17:_ **Table 16 Definitions for DC Output Levels for POD Standards**
|**Symbol**|**Description**|**All Speed Grades**|**Units**|
|---|---|---|---|
|VOM_DC|DC output Mid measurement level (for IV curve linearity).|0.8 x VCCO|V|
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**Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
## **LVDS DC Specifications (LVDS_25)**
The LVDS_25 standard is available in the HD I/O banks. See the _UltraScale Architecture SelectIO Resources User Guide_ (UG571) for more information.
_Table 18:_ **LVDS_25 DC Specifications**
|_Table 18:_|**LVDS_25 DC Specifications**||||||
|---|---|---|---|---|---|---|
|**Symbol**|**DC Parameter**|**Conditions**|**Min**|**Typ**|**Max**|**Units**|
|VCCO(1)|Supply voltage.||2.375|2.500|2.625|V|
|VIDIFF|Differential input voltage:<br>(Q – Q<br>),Q = High<br>(Q<br>– Q), Q<br>= High||100|350|600(2)|mV|
|VICM|Input common-mode voltage.||0.300|1.200|1.425|V|
## **Notes:**
1. LVDS_25 in HD I/O banks supports inputs only. LVDS_25 inputs without internal termination have no VCCO requirements. Any VCCO can be chosen as long as the input voltage levels do not violate the _Recommended Operating Condition_ (Table 2) specification for the VIN I/O pin voltage.
2. Maximum VIDIFF value is specified for the maximum VICM specification. With a lower VICM, a higher VDIFF is tolerated only when the recommended operating conditions and overshoot/undershoot VIN specifications are maintained.
## **LVDS DC Specifications (LVDS)**
The LVDS standard is available in the HP I/O banks. See the _UltraScale Architecture SelectIO Resources User Guide_ (UG571) for more information.
_Table 19:_ **LVDS DC Specifications**
|**Symbol**|**DC Parameter**|**Conditions**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|VCCO(1)|Supply voltage.||1.710|1.800|1.890|V|
|VODIFF(2)|Differential output voltage:<br>(Q – Q<br>),Q = High<br>(Q<br>– Q), Q<br>= High|RT = 100Ωacross Q and Q<br>signals|247|350|454|mV|
|VOCM(2)|Output common-mode voltage.|RT = 100Ωacross Q and Q<br>signals|1.000|1.250|1.425|V|
|VIDIFF(3)|Differential input voltage:<br>(Q – Q<br>),Q = High<br>(Q<br>– Q), Q<br>= High||100|350|600(3)|mV|
|VICM_DC(4)|Input common-mode voltage (DC coupling).||0.300|1.200|1.425|V|
|VICM_AC(5)|Input common-mode voltage (AC coupling).||0.600|–|1.100|V|
## **Notes:**
1. In HP I/O banks, when LVDS is used with input-only functionality, it can be placed in a bank where the VCCO levels are different from the specified level only if internal differential termination is not used. In this scenario, VCCO must be chosen to ensure the input pin voltage levels do not violate the _Recommended Operating Condition_ (Table 2) specification for the VIN I/O pin voltage.
2. VOCM and VODIFF values are for LVDS_PRE_EMPHASIS = FALSE.
3. Maximum VIDIFF value is specified for the maximum VICM specification. With a lower VICM, a higher VDIFF is tolerated only when the recommended operating conditions and overshoot/undershoot VIN specifications are maintained.
4. Input common mode voltage for DC coupled configurations. EQUALIZATION = EQ_NONE (Default).
5. External input common mode voltage specification for AC coupled configurations. EQUALIZATION = EQ_LEVEL0, EQ_LEVEL1, EQ_LEVEL2, EQ_LEVEL3, EQ_LEVEL4.
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**Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
## **AC Switching Characteristics**
All values represented in this data sheet are based on the speed specifications in the Vivado® Design Suite as outlined in Table 20.
_Table 20:_ **Speed Specification Version By Device**
|**2017.1**|**Device**|
|---|---|
|1.08|XCKU11P|
|1.10|XCKU3P, XCKU5P, XCKU9P, XCKU13P, and XCKU15P|
Switching characteristics are specified on a per-speed-grade basis and can be designated as Advance, Preliminary, or Production. Each designation is defined as follows:
## **Advance Product Specification**
These specifications are based on simulations only and are typically available soon after device design specifications are frozen. Although speed grades with this designation are considered relatively stable and conservative, some under-reporting might still occur.
## **Preliminary Product Specification**
These specifications are based on complete ES (engineering sample) silicon characterization. Devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon. The probability of under-reporting delays is greatly reduced as compared to Advance data.
## **Product Specification**
These specifications are released once enough production silicon of a particular device family member has been characterized to provide full correlation between specifications and devices over numerous production lots. There is no under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest speed grades transition to production before faster speed grades.
## **Testing of AC Switching Characteristics**
Internal timing parameters are derived from measuring internal test patterns. All AC switching characteristics are representative of worst-case supply voltage and junction temperature conditions.
For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer and back-annotate to the simulation net list. Unless otherwise noted, values apply to all Kintex UltraScale+ FPGAs.
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**Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
## **Speed Grade Designations**
Since individual family members are produced at different times, the migration from one category to another depends completely on the status of the fabrication process for each device. Table 21 correlates the current status of the Kintex UltraScale+ FPGAs on a per speed grade basis.
_Table 21:_ **Speed Grade Designations by Device**
|**Device**|**Speed Grade, Temperature Ranges, and VCCINTOperating Voltages**|**Speed Grade, Temperature Ranges, and VCCINTOperating Voltages**|**Speed Grade, Temperature Ranges, and VCCINTOperating Voltages**|
|---|---|---|---|
||**Advance**|**Preliminary**|**Production**|
|XCKU3P|-3E (VCCINT = 0.90V)<br>-2LE (VCCINT = 0.85V), -2LE (VCCINT = 0.72V)(1)<br>-1LI (VCCINT = 0.85V), -1LI (VCCINT = 0.72V)(1)||-2E (VCCINT = 0.85V)<br>-2I (VCCINT = 0.85V)<br>-1E (VCCINT = 0.85V)<br>-1I (VCCINT = 0.85V)|
|XCKU5P|-3E (VCCINT = 0.90V)<br>-2LE (VCCINT = 0.85V), -2LE (VCCINT = 0.72V)(1)<br>-1LI (VCCINT = 0.85V), -1LI (VCCINT = 0.72V)(1)||-2E (VCCINT = 0.85V)<br>-2I (VCCINT = 0.85V)<br>-1E (VCCINT = 0.85V)<br>-1I (VCCINT = 0.85V)|
|XCKU9P|-3E (VCCINT = 0.90V)<br>-2LE (VCCINT = 0.85V), -2LE (VCCINT = 0.72V)(1)<br>-1LI (VCCINT = 0.85V), -1LI (VCCINT = 0.72V)(1)||-2E (VCCINT = 0.85V)<br>-2I (VCCINT = 0.85V)<br>-1E (VCCINT = 0.85V)<br>-1I (VCCINT = 0.85V)|
|XCKU11P|-3E (VCCINT = 0.90V)<br>-2E (VCCINT = 0.85V), -2I (VCCINT = 0.85V)<br>-2LE (VCCINT = 0.85V)<br>-1E (VCCINT = 0.85V), -1I (VCCINT = 0.85V)<br>-1LI (VCCINT = 0.85V)<br>-2LE (VCCINT = 0.72V)(1), -1LI (VCCINT = 0.72V)(1)|||
|XCKU13P|-3E (VCCINT = 0.90V)<br>-2E (VCCINT = 0.85V), -2I (VCCINT = 0.85V)<br>-2LE (VCCINT = 0.85V)<br>-1E (VCCINT = 0.85V), -1I (VCCINT = 0.85V)<br>-1LI (VCCINT = 0.85V)<br>-2LE (VCCINT = 0.72V)(1), -1LI (VCCINT = 0.72V)(1)|||
|XCKU15P|-3E (VCCINT = 0.90V)<br>-2E (VCCINT = 0.85V), -2I (VCCINT = 0.85V)<br>-2LE (VCCINT = 0.85V)<br>-1E (VCCINT = 0.85V), -1I (VCCINT = 0.85V)<br>-1LI (VCCINT = 0.85V)<br>-2LE (VCCINT = 0.72V)(1), -1LI (VCCINT = 0.72V)(1)|||
## **Notes:**
1. The lowest power -1L and -2L devices, where VCCINT = 0.72V, are listed in the Vivado Design Suite as -1LV and -2LV respectively.
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**Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
## **Production Silicon and Software Status**
In some cases, a particular family member (and speed grade) is released to production before a speed specification is released with the correct label (Advance, Preliminary, Production). Any labeling discrepancies are corrected in subsequent speed specification releases.
Table 22 lists the production released Kintex UltraScale+ FPGAs, speed grade, and the minimum corresponding supported speed specification version and Vivado software revisions. The Vivado software and speed specifications listed are the minimum releases required for production. All subsequent releases of software and speed specifications are valid.
_Table 22:_ **Kintex UltraScale+ FPGA Device Production Software and Speed Specification Release**
|**Device**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|
|---|---|---|---|---|---|---|---|
||**0.90V**|**0.85V**||||**0.72V**||
||**-3**|**-2**|**-1**|**-2L**|**-1L**|**-2L**|**-1L**|
|XCKU3P||Vivado tools 2017.1 v1.10||||||
|XCKU5P||Vivado tools 2017.1 v1.10||||||
|XCKU9P||Vivado tools 2017.1 v1.10||||||
|XCKU11P||||||||
|XCKU13P||||||||
|XCKU15P||||||||
## **Notes:**
1. Blank entries indicate a device and/or speed grade in Advance or Preliminary status.
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**Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
## **FPGA Logic Performance Characteristics**
This section provides the performance characteristics of some common functions and designs implemented in Kintex UltraScale+ FPGAs. These values are subject to the same guidelines as the AC Switching Characteristics, page 16. In each table, the I/O bank type is either high performance (HP) or high density (HD).
_Table 23:_ **LVDS Component Mode Performance**
|**Description**|**I/O**<br>**Bank**<br>**Type**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|||<br>**0.90V**||**0.85V**||||**0.72V**|||||
|||<br>**-3**||**-2**||**-1**||**-2**||**-1**|||
|||**Min**|**Max**|**Min**|**Max**|**Min**|**Max**|**Min**|**Max**|**Min**|**Max**||
|LVDS TX DDR (OSERDES 4:1, 8:1)|HP|0|1250|0|1250|0|1250|0|1250|0|1250|Mb/s|
|LVDS TX SDR (OSERDES 2:1, 4:1)|HP|0|625|0|625|0|625|0|625|0|625|Mb/s|
|LVDS RX DDR (ISERDES 1:4, 1:8)(1)|HP|0|1250|0|1250|0|1250|0|1250|0|1250|Mb/s|
|LVDS RX DDR|HD|0|250|0|250|0|250|0|250|0|250|Mb/s|
|LVDS RX SDR (ISERDES 1:2, 1:4)(1)|HP|0|625|0|625|0|625|0|625|0|625|Mb/s|
|LVDS RX SDR|HD|0|125|0|125|0|125|0|125|0|125|Mb/s|
## **Notes:**
1. LVDS receivers are typically bounded with certain applications to achieve maximum performance. Package skews are not included and should be removed through PCB routing.
_Table 24:_ **LVDS Native Mode Performance[(1)(2)]**
|**Description**|**DATA_WIDTH**|**I/O**<br>**Bank**<br>**Type**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||||<br>**0.90V**||**0.85V**||||**0.72V**|||||
||||<br>**-3**||**-2**||**-1**||**-2**||**-1**|||
||||**Min**|**Max**|**Min**|**Max**|**Min**|**Max**|**Min**|**Max**|**Min**|**Max**||
|LVDS TX DDR<br>(TX_BITSLICE)|4|HP|375|1600|375|1600|375|1260|375|1400|375|1260|Mb/s|
||8||375|1600|375|1600|375|1260|375|1600|375|1260|Mb/s|
|LVDS TX SDR<br>(TX_BITSLICE)|4|HP|187.5|800|187.5|800|187.5|630|187.5|700|187.5|630|Mb/s|
||8||187.5|800|187.5|800|187.5|630|187.5|800|187.5|630|Mb/s|
|LVDS RX DDR<br>(RX_BITSLICE)(3)|4|HP|375|1600|375|1600|375|1260|375|1400|375|1260|Mb/s|
||8||375|1600|375|1600|375|1260|375|1600|375|1260|Mb/s|
|LVDS RX SDR<br>(RX_BITSLICE)(3)|4|HP|187.5|800|187.5|800|187.5|630|187.5|700|187.5|630|Mb/s|
||8||187.5|800|187.5|800|187.5|630|187.5|800|187.5|630|Mb/s|
## **Notes:**
1. Native mode is supported through the High-Speed SelectIO Interface Wizard available with the Vivado Design Suite. The performance values assume a source-synchronous interface.
2. PLL settings can restrict the minimum allowable data rate. For example, when using the PLL with CLKOUTPHY_MODE = VCO_HALF the minimum frequency is PLL_FVCOMIN/2.
3. LVDS receivers are typically bounded with certain applications to achieve maximum performance. Package skews are not included and should be removed through PCB routing.
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**Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 25:_ **MIPI D-PHY Performance**
|**Description**|**I/O**<br>**Bank**<br>**Type**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Units**|
|---|---|---|---|---|---|---|---|
|||**0.90V**|**0.85V**||**0.72V**|||
|||**-3**|**-2**|**-1**|**-2**|**-1**||
|MIPI D-PHY transmitter or receiver.|HP|1500|1500|1260|1260|1260|Mb/s|
_Table 26:_ **LVDS Native-Mode 1000BASE-X Support[(1)]**
|**Description**|**I/O Bank Type**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|
|---|---|---|---|---|---|---|
|||**0.90V**|**0.85V**||**0.72V**||
|||**-3**|**-2**|**-1**|**-2**|**-1**|
|1000BASE-X|HP|Yes|||||
## **Notes:**
1. 1000BASE-X support is based on the _IEEE Standard for CSMA/CD Access Method and Physical Layer Specifications_ (IEEE Std 802.3-2008).
Table 27 provides the maximum data rates for applicable memory standards using the Kintex UltraScale+ FPGA memory PHY. Refer to Memory Interfaces for the complete list of memory interface standards supported and detailed specifications. The final performance of the memory interface is determined through a complete design implemented in the Vivado Design Suite, following guidelines in the _UltraScale Architecture PCB Design Guide_ (UG583), electrical analysis, and characterization of the system.
_Table 27:_ **Maximum Physical Interface (PHY) Rate for Memory Interfaces**
|**Memory**<br>**Standard**|**Package**|**DRAM Type**|**Speed Grade and VCCINTOperating**<br>**Voltages**|**Speed Grade and VCCINTOperating**<br>**Voltages**|**Speed Grade and VCCINTOperating**<br>**Voltages**|**Speed Grade and VCCINTOperating**<br>**Voltages**|**Speed Grade and VCCINTOperating**<br>**Voltages**|**Units**|
|---|---|---|---|---|---|---|---|---|
||||**0.90V**|**0.85V**||**0.72V**|||
||||**-3**|**-2**|**-1**|**-2**|**-1**||
|DDR4|All FFV packages|Single rank component|2666|2666|2400|2400|2133|Mb/s|
|||1 rank DIMM(1)(2)(3)|2400|2400|2133|2133|1866|Mb/s|
|||2 rank DIMM(1)(4)|2133|2133|1866|1866|1600|Mb/s|
|||4 rank DIMM(1)(5)|1600|1600|1333|1333|N/A|Mb/s|
||SFVB784|Single rank component|2400|2400|2133|2133|1866|Mb/s|
|||1 rank DIMM(1)(2)|2133|2133|1866|1866|1600|Mb/s|
|||2 rank DIMM(1)(4)|1866|1866|1600|1600|1600|Mb/s|
|DDR3|All FFV packages|Single rank component|2133|2133|2133|2133|1866|Mb/s|
|||1 rank DIMM(1)(2)|1866|1866|1866|1866|1600|Mb/s|
|||2 rank DIMM(1)(4)|1600|1600|1600|1600|1333|Mb/s|
|||4 rank DIMM(1)(5)|1066|1066|1066|1066|800|Mb/s|
||SFVB784|Single rank component|1866|1866|1866|1866|1600|Mb/s|
|||1 rank DIMM(1)(2)|1600|1600|1600|1600|1600|Mb/s|
|||2 rank DIMM(1)(4)|1600|1600|1600|1600|1333|Mb/s|
|||4 rank DIMM(1)(5)|1066|1066|1066|1066|800|Mb/s|
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**Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 27:_ **Maximum Physical Interface (PHY) Rate for Memory Interfaces** _**(Cont’d)**_
|**Memory**<br>**Standard**|**Package**|**DRAM Type**|**Speed Grade and VCCINTOperating**<br>**Voltages**|**Speed Grade and VCCINTOperating**<br>**Voltages**|**Speed Grade and VCCINTOperating**<br>**Voltages**|**Speed Grade and VCCINTOperating**<br>**Voltages**|**Speed Grade and VCCINTOperating**<br>**Voltages**|**Units**|
|---|---|---|---|---|---|---|---|---|
||||**0.90V**|**0.85V**||**0.72V**|||
||||**-3**|**-2**|**-1**|**-2**|**-1**||
|DDR3L|All FFV packages|Single rank component|1866|1866|1866|1866|1600|Mb/s|
|||1 rank DIMM(1)(2)|1600|1600|1600|1600|1333|Mb/s|
|||2 rank DIMM(1)(4)|1333|1333|1333|1333|1066|Mb/s|
|||4 rank DIMM(1)(5)|800|800|800|800|606|Mb/s|
||SFVB784|Single rank component|1600|1600|1600|1600|1600|Mb/s|
|||1 rank DIMM(1)(2)|1600|1600|1600|1600|1333|Mb/s|
|||2 rank DIMM(1)(4)|1333|1333|1333|1333|1066|Mb/s|
|||4 rank DIMM(1)(5)|800|800|800|800|606|Mb/s|
|QDR II+|All|Single rank component(6)|633|633|600|600|550|MHz|
|RLDRAM 3|All FFV packages|Single rank component|1200|1200|1066|1066|933|MHz|
||SFVB784|Single rank component|1066|1066|933|933|800|MHz|
|QDR IV XP|All|Single rank component|1066|1066|1066|933|933|MHz|
|LPDDR3|All|Single rank component|1600|1600|1600|1600|1600|Mb/s|
## **Notes:**
1. Dual in-line memory module (DIMM) includes RDIMM, SODIMM, UDIMM, and LRDIMM.
2. Includes: 1 rank 1 slot, DDP 2 rank, LRDIMM 2 or 4 rank 1 slot.
3. For the DDR4 DDP components at -3 and -2 (VCCINT = 0.85V) speed grades, the maximum data rate is 2133 Mb/s for six or more DDP devices. For five or less DDP devices, use the single rank DIMM data rates for the -3 and -2 speed grades at 0.85V.
4. Includes: 2 rank 1 slot, 1 rank 2 slot, LRDIMM 2 rank 2 slot.
5. Includes: 2 rank 2 slot, 4 rank 1 slot.
6. The QDRII+ performance specifications are for burst-length 4 (BL = 4) implementations.
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**Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
## **FPGA Logic Switching Characteristics**
Table 28 (high-density IOB (HD)) and Table 29 (high-performance IOB (HP)) summarizes the values of standard-specific data input delay adjustments, output delays terminating at pads (based on standard) and 3-state delays.
- TINBUF_DELAY_PAD_I is the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The delay varies depending on the capability of the SelectIO input buffer.
- TOUTBUF_DELAY_O_PAD is the delay from the O pin to the IOB pad through the output buffer of an IOB pad. The delay varies depending on the capability of the SelectIO output buffer.
- TOUTBUF_DELAY_TD_PAD is the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is disabled. The delay varies depending on the SelectIO capability of the output buffer. In HP I/O banks, the internal DCI termination turn-on time is always faster than TOUTBUF_DELAY_TD_PAD when the DCITERMDISABLE pin is used. In HD I/O banks, the on-die termination turn-on time is always faster than TOUTBUF_DELAY_TD_PAD when the INTERMDISABLE pin is used.
## **IOB High Density (HD) Switching Characteristics**
_Table 28:_ **IOB High Density (HD) Switching Characteristics**
|**I/O Standards**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||**0.90V**|**0.85V**||**0.72V**||**0.90V**|**0.85V**||**0.72V**||**0.90V**|**0.85V**||**0.72V**|||
||**-3**|**-2**|**-1**|**-2**|**-1**|**-3**|**-2**|**-1**|**-2**|**-1**|**-3**|**-2**|**-1**|**-2**|**-1**||
|DIFF_HSTL_I_18_F|0.978|0.978|1.058|0.978|1.058|1.574|1.574|1.718|1.574|1.718|1.160|1.160|1.271|1.160|1.271|ns|
|DIFF_HSTL_I_18_S|0.978|0.978|1.058|0.978|1.058|1.805|1.805|1.950|1.805|1.950|1.748|1.748|1.867|1.748|1.867|ns|
|DIFF_HSTL_I_F|0.978|0.978|1.058|0.978|1.058|1.611|1.611|1.762|1.611|1.762|1.313|1.313|1.417|1.313|1.417|ns|
|DIFF_HSTL_I_S|0.978|0.978|1.058|0.978|1.058|1.798|1.798|1.913|1.798|1.913|1.630|1.630|1.780|1.630|1.780|ns|
|DIFF_HSUL_12_F|0.911|0.911|0.977|0.911|0.977|1.573|1.573|1.703|1.573|1.703|1.222|1.222|1.335|1.222|1.335|ns|
|DIFF_HSUL_12_S|0.911|0.911|0.977|0.911|0.977|1.711|1.711|1.864|1.711|1.864|1.536|1.536|1.665|1.536|1.665|ns|
|DIFF_SSTL12_F|0.906|0.906|0.977|0.906|0.977|1.643|1.643|1.792|1.643|1.792|1.285|1.285|1.423|1.285|1.423|ns|
|DIFF_SSTL12_S|0.906|0.906|0.977|0.906|0.977|1.784|1.784|1.948|1.784|1.948|1.567|1.567|1.706|1.567|1.706|ns|
|DIFF_SSTL135_F|0.927|0.927|0.995|0.927|0.995|1.625|1.625|1.765|1.625|1.765|1.341|1.341|1.458|1.341|1.458|ns|
|DIFF_SSTL135_II_F|0.927|0.927|0.995|0.927|0.995|1.623|1.623|1.770|1.623|1.770|1.325|1.325|1.470|1.325|1.470|ns|
|DIFF_SSTL135_II_S|0.927|0.927|0.995|0.927|0.995|1.768|1.768|1.916|1.768|1.916|1.722|1.722|1.911|1.722|1.911|ns|
|DIFF_SSTL135_S|0.927|0.927|0.995|0.927|0.995|1.869|1.869|2.025|1.869|2.025|1.814|1.814|1.976|1.814|1.976|ns|
|DIFF_SSTL15_F|0.928|0.928|1.020|0.928|1.020|1.628|1.628|1.771|1.628|1.771|1.374|1.374|1.483|1.374|1.483|ns|
|DIFF_SSTL15_II_F|0.928|0.928|1.020|0.928|1.020|1.622|1.622|1.778|1.622|1.778|1.356|1.356|1.442|1.356|1.442|ns|
|DIFF_SSTL15_II_S|0.928|0.928|1.020|0.928|1.020|1.821|1.821|1.987|1.821|1.987|1.895|1.895|2.047|1.895|2.047|ns|
|DIFF_SSTL15_S|0.928|0.928|1.020|0.928|1.020|1.824|1.824|1.977|1.824|1.977|1.743|1.743|1.907|1.743|1.907|ns|
|DIFF_SSTL18_II_F|0.961|0.961|1.038|0.961|1.038|1.729|1.729|1.880|1.729|1.880|1.377|1.377|1.492|1.377|1.492|ns|
|DIFF_SSTL18_II_S|0.961|0.961|1.038|0.961|1.038|1.796|1.796|1.965|1.796|1.965|1.616|1.616|1.800|1.616|1.800|ns|
|DIFF_SSTL18_I_F|0.961|0.961|1.038|0.961|1.038|1.609|1.609|1.755|1.609|1.755|1.220|1.220|1.313|1.220|1.313|ns|
|DIFF_SSTL18_I_S|0.961|0.961|1.038|0.961|1.038|1.786|1.786|1.942|1.786|1.942|1.677|1.677|1.836|1.677|1.836|ns|
|HSTL_I_18_F|0.947|0.947|1.021|0.947|1.021|1.574|1.574|1.718|1.574|1.718|1.160|1.160|1.271|1.160|1.271|ns|
|HSTL_I_18_S|0.947|0.947|1.021|0.947|1.021|1.805|1.805|1.950|1.805|1.950|1.748|1.748|1.867|1.748|1.867|ns|
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**Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 28:_ **IOB High Density (HD) Switching Characteristics** _**(Cont’d)**_
|**I/O Standards**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||**0.90V**|**0.85V**||**0.72V**||**0.90V**|**0.85V**||**0.72V**||**0.90V**|**0.85V**||**0.72V**|||
||**-3**|**-2**|**-1**|**-2**|**-1**|**-3**|**-2**|**-1**|**-2**|**-1**|**-3**|**-2**|**-1**|**-2**|**-1**||
|HSTL_I_F|0.856|0.856|0.900|0.856|0.900|1.611|1.611|1.762|1.611|1.762|1.313|1.313|1.417|1.313|1.417|ns|
|HSTL_I_S|0.856|0.856|0.900|0.856|0.900|1.798|1.798|1.913|1.798|1.913|1.630|1.630|1.780|1.630|1.780|ns|
|HSUL_12_F|0.780|0.780|0.867|0.780|0.867|1.573|1.573|1.703|1.573|1.703|1.222|1.222|1.335|1.222|1.335|ns|
|HSUL_12_S|0.780|0.780|0.867|0.780|0.867|1.711|1.711|1.864|1.711|1.864|1.536|1.536|1.665|1.536|1.665|ns|
|LVCMOS12_F_12|0.918|0.918|0.976|0.918|0.976|1.689|1.689|1.856|1.689|1.856|1.202|1.202|1.317|1.202|1.317|ns|
|LVCMOS12_F_4|0.918|0.918|0.976|0.918|0.976|1.742|1.742|1.922|1.742|1.922|1.353|1.353|1.478|1.353|1.478|ns|
|LVCMOS12_F_8|0.918|0.918|0.976|0.918|0.976|1.714|1.714|1.879|1.714|1.879|1.292|1.292|1.432|1.292|1.432|ns|
|LVCMOS12_S_12|0.918|0.918|0.976|0.918|0.976|2.073|2.073|2.247|2.073|2.247|1.581|1.581|1.717|1.581|1.717|ns|
|LVCMOS12_S_4|0.918|0.918|0.976|0.918|0.976|1.979|1.979|2.182|1.979|2.182|1.633|1.633|1.772|1.633|1.772|ns|
|LVCMOS12_S_8|0.918|0.918|0.976|0.918|0.976|2.205|2.205|2.406|2.205|2.406|1.767|1.767|1.928|1.767|1.928|ns|
|LVCMOS15_F_12|0.905|0.905|0.958|0.905|0.958|1.713|1.713|1.892|1.713|1.892|1.275|1.275|1.428|1.275|1.428|ns|
|LVCMOS15_F_16|0.905|0.905|0.958|0.905|0.958|1.722|1.722|1.881|1.722|1.881|1.260|1.260|1.407|1.260|1.407|ns|
|LVCMOS15_F_4|0.905|0.905|0.958|0.905|0.958|1.825|1.825|1.959|1.825|1.959|1.453|1.453|1.557|1.453|1.557|ns|
|LVCMOS15_F_8|0.905|0.905|0.958|0.905|0.958|1.778|1.778|1.930|1.778|1.930|1.378|1.378|1.458|1.378|1.458|ns|
|LVCMOS15_S_12|0.905|0.905|0.958|0.905|0.958|1.991|1.991|2.139|1.991|2.139|1.516|1.516|1.648|1.516|1.648|ns|
|LVCMOS15_S_16|0.905|0.905|0.958|0.905|0.958|2.172|2.172|2.389|2.172|2.389|1.707|1.707|1.888|1.707|1.888|ns|
|LVCMOS15_S_4|0.905|0.905|0.958|0.905|0.958|2.313|2.313|2.483|2.313|2.483|1.952|1.952|2.123|1.952|2.123|ns|
|LVCMOS15_S_8|0.905|0.905|0.958|0.905|0.958|2.170|2.170|2.400|2.170|2.400|1.817|1.817|1.984|1.817|1.984|ns|
|LVCMOS18_F_12|0.915|0.915|0.958|0.915|0.958|1.805|1.805|1.962|1.805|1.962|1.383|1.383|1.471|1.383|1.471|ns|
|LVCMOS18_F_16|0.915|0.915|0.958|0.915|0.958|1.785|1.785|1.917|1.785|1.917|1.338|1.338|1.446|1.338|1.446|ns|
|LVCMOS18_F_4|0.915|0.915|0.958|0.915|0.958|1.868|1.868|2.013|1.868|2.013|1.472|1.472|1.599|1.472|1.599|ns|
|LVCMOS18_F_8|0.915|0.915|0.958|0.915|0.958|1.797|1.797|1.979|1.797|1.979|1.384|1.384|1.487|1.384|1.487|ns|
|LVCMOS18_S_12|0.915|0.915|0.958|0.915|0.958|2.201|2.201|2.408|2.201|2.408|1.762|1.762|1.894|1.762|1.894|ns|
|LVCMOS18_S_16|0.915|0.915|0.958|0.915|0.958|2.173|2.173|2.362|2.173|2.362|1.702|1.702|1.834|1.702|1.834|ns|
|LVCMOS18_S_4|0.915|0.915|0.958|0.915|0.958|2.346|2.346|2.567|2.346|2.567|1.951|1.951|2.092|1.951|2.092|ns|
|LVCMOS18_S_8|0.915|0.915|0.958|0.915|0.958|2.292|2.292|2.511|2.292|2.511|1.848|1.848|2.008|1.848|2.008|ns|
|LVCMOS25_F_12|0.988|0.988|1.042|0.988|1.042|2.153|2.153|2.453|2.153|2.453|1.692|1.692|1.856|1.692|1.856|ns|
|LVCMOS25_F_16|0.988|0.988|1.042|0.988|1.042|2.105|2.105|2.406|2.105|2.406|1.623|1.623|1.786|1.623|1.786|ns|
|LVCMOS25_F_4|0.988|0.988|1.042|0.988|1.042|2.344|2.344|2.554|2.344|2.554|1.842|1.842|2.039|1.842|2.039|ns|
|LVCMOS25_F_8|0.988|0.988|1.042|0.988|1.042|2.184|2.184|2.516|2.184|2.516|1.726|1.726|1.910|1.726|1.910|ns|
|LVCMOS25_S_12|0.988|0.988|1.042|0.988|1.042|2.558|2.558|2.840|2.558|2.840|1.971|1.971|2.194|1.971|2.194|ns|
|LVCMOS25_S_16|0.988|0.988|1.042|0.988|1.042|2.449|2.449|2.740|2.449|2.740|1.852|1.852|2.063|1.852|2.063|ns|
|LVCMOS25_S_4|0.988|0.988|1.042|0.988|1.042|2.770|2.770|3.066|2.770|3.066|2.224|2.224|2.458|2.224|2.458|ns|
|LVCMOS25_S_8|0.988|0.988|1.042|0.988|1.042|2.663|2.663|2.963|2.663|2.963|2.091|2.091|2.373|2.091|2.373|ns|
|LVCMOS33_F_12|1.154|1.154|1.213|1.154|1.213|2.415|2.415|2.651|2.415|2.651|1.754|1.754|1.915|1.754|1.915|ns|
|LVCMOS33_F_16|1.154|1.154|1.213|1.154|1.213|2.383|2.383|2.603|2.383|2.603|1.734|1.734|1.869|1.734|1.869|ns|
|LVCMOS33_F_4|1.154|1.154|1.213|1.154|1.213|2.541|2.541|2.765|2.541|2.765|1.932|1.932|2.135|1.932|2.135|ns|
|LVCMOS33_F_8|1.154|1.154|1.213|1.154|1.213|2.603|2.603|2.822|2.603|2.822|1.937|1.937|2.130|1.937|2.130|ns|
|LVCMOS33_S_12|1.154|1.154|1.213|1.154|1.213|2.705|2.705|3.047|2.705|3.047|2.049|2.049|2.318|2.049|2.318|ns|
|LVCMOS33_S_16|1.154|1.154|1.213|1.154|1.213|2.714|2.714|3.024|2.714|3.024|2.028|2.028|2.232|2.028|2.232|ns|
|LVCMOS33_S_4|1.154|1.154|1.213|1.154|1.213|2.999|2.999|3.340|2.999|3.340|2.320|2.320|2.610|2.320|2.610|ns|
DS922 (v1.3) May 8, 2017 **Preliminary Product Specification**
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**Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 28:_ **IOB High Density (HD) Switching Characteristics** _**(Cont’d)**_
|**I/O Standards**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||**0.90V**|**0.85V**||**0.72V**||**0.90V**|**0.85V**||**0.72V**||**0.90V**|**0.85V**||**0.72V**|||
||**-3**|**-2**|**-1**|**-2**|**-1**|**-3**|**-2**|**-1**|**-2**|**-1**|**-3**|**-2**|**-1**|**-2**|**-1**||
|LVCMOS33_S_8|1.154|1.154|1.213|1.154|1.213|2.929|2.929|3.260|2.929|3.260|2.260|2.260|2.532|2.260|2.532|ns|
|LVDS_25|1.003|1.003|1.116|1.003|1.116|N/A|N/A|N/A|N/A|N/A|N/A|N/A|N/A|N/A|N/A|ns|
|LVPECL|1.003|1.003|1.116|1.003|1.116|N/A|N/A|N/A|N/A|N/A|N/A|N/A|N/A|N/A|N/A|ns|
|LVTTL_F_12|1.164|1.164|1.223|1.164|1.223|2.415|2.415|2.651|2.415|2.651|1.754|1.754|1.915|1.754|1.915|ns|
|LVTTL_F_16|1.164|1.164|1.223|1.164|1.223|2.464|2.464|2.732|2.464|2.732|1.750|1.750|1.986|1.750|1.986|ns|
|LVTTL_F_4|1.164|1.164|1.223|1.164|1.223|2.541|2.541|2.765|2.541|2.765|1.932|1.932|2.135|1.932|2.135|ns|
|LVTTL_F_8|1.164|1.164|1.223|1.164|1.223|2.582|2.582|2.787|2.582|2.787|1.910|1.910|2.063|1.910|2.063|ns|
|LVTTL_S_12|1.164|1.164|1.223|1.164|1.223|2.731|2.731|3.075|2.731|3.075|2.072|2.072|2.343|2.072|2.343|ns|
|LVTTL_S_16|1.164|1.164|1.223|1.164|1.223|2.714|2.714|3.024|2.714|3.024|2.028|2.028|2.232|2.028|2.232|ns|
|LVTTL_S_4|1.164|1.164|1.223|1.164|1.223|2.999|2.999|3.340|2.999|3.340|2.320|2.320|2.610|2.320|2.610|ns|
|LVTTL_S_8|1.164|1.164|1.223|1.164|1.223|2.929|2.929|3.260|2.929|3.260|2.260|2.260|2.532|2.260|2.532|ns|
|SLVS_400_25|1.020|1.020|1.136|1.020|1.136|N/A|N/A|N/A|N/A|N/A|N/A|N/A|N/A|N/A|N/A|ns|
|SSTL12_F|0.780|0.780|0.867|0.780|0.867|1.643|1.643|1.792|1.643|1.792|1.285|1.285|1.423|1.285|1.423|ns|
|SSTL12_S|0.780|0.780|0.867|0.780|0.867|1.784|1.784|1.948|1.784|1.948|1.567|1.567|1.706|1.567|1.706|ns|
|SSTL135_F|0.798|0.798|0.881|0.798|0.881|1.625|1.625|1.765|1.625|1.765|1.341|1.341|1.458|1.341|1.458|ns|
|SSTL135_II_F|0.798|0.798|0.881|0.798|0.881|1.623|1.623|1.770|1.623|1.770|1.325|1.325|1.470|1.325|1.470|ns|
|SSTL135_II_S|0.798|0.798|0.881|0.798|0.881|1.768|1.768|1.916|1.768|1.916|1.722|1.722|1.911|1.722|1.911|ns|
|SSTL135_S|0.798|0.798|0.881|0.798|0.881|1.869|1.869|2.025|1.869|2.025|1.814|1.814|1.976|1.814|1.976|ns|
|SSTL15_F|0.838|0.838|0.880|0.838|0.880|1.612|1.612|1.754|1.612|1.754|1.357|1.357|1.464|1.357|1.464|ns|
|SSTL15_II_F|0.838|0.838|0.880|0.838|0.880|1.622|1.622|1.778|1.622|1.778|1.356|1.356|1.442|1.356|1.442|ns|
|SSTL15_II_S|0.838|0.838|0.880|0.838|0.880|1.821|1.821|1.987|1.821|1.987|1.895|1.895|2.047|1.895|2.047|ns|
|SSTL15_S|0.838|0.838|0.880|0.838|0.880|1.824|1.824|1.977|1.824|1.977|1.743|1.743|1.907|1.743|1.907|ns|
|SSTL18_II_F|0.947|0.947|1.021|0.947|1.021|1.729|1.729|1.880|1.729|1.880|1.377|1.377|1.492|1.377|1.492|ns|
|SSTL18_II_S|0.947|0.947|1.021|0.947|1.021|1.796|1.796|1.965|1.796|1.965|1.616|1.616|1.800|1.616|1.800|ns|
|SSTL18_I_F|0.947|0.947|1.021|0.947|1.021|1.609|1.609|1.755|1.609|1.755|1.220|1.220|1.313|1.220|1.313|ns|
|SSTL18_I_S|0.947|0.947|1.021|0.947|1.021|1.786|1.786|1.942|1.786|1.942|1.677|1.677|1.836|1.677|1.836|ns|
|SUB_LVDS|1.002|1.002|1.036|1.002|1.036|N/A|N/A|N/A|N/A|N/A|N/A|N/A|N/A|N/A|N/A|ns|
DS922 (v1.3) May 8, 2017 **Preliminary Product Specification**
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**Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
## **IOB High Performance (HP) Switching Characteristics**
_Table 29:_ **IOB High Performance (HP) Switching Characteristics**
|**I/O Standards**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||**0.90V**|**0.85V**||**0.72V**||**0.90V**|**0.85V**||**0.72V**||**0.90V**|**0.85V**||**0.72V**|||
||**-3**|**-2**|**-1**|**-2**|**-1**|**-3**|**-2**|**-1**|**-2**|**-1**|**-3**|**-2**|**-1**|**-2**|**-1**||
|DIFF_HSTL_I_12_F|0.394|0.394|0.402|0.394|0.402|0.423|0.423|0.443|0.423|0.443|0.553|0.553|0.582|0.553|0.582|ns|
|DIFF_HSTL_I_12_M|0.394|0.394|0.402|0.394|0.402|0.552|0.552|0.583|0.552|0.583|0.641|0.641|0.679|0.641|0.679|ns|
|DIFF_HSTL_I_12_S|0.394|0.394|0.402|0.394|0.402|0.752|0.752|0.800|0.752|0.800|0.813|0.813|0.868|0.813|0.868|ns|
|DIFF_HSTL_I_18_F|0.319|0.319|0.339|0.319|0.339|0.456|0.456|0.474|0.456|0.474|0.576|0.576|0.606|0.576|0.606|ns|
|DIFF_HSTL_I_18_M|0.319|0.319|0.339|0.319|0.339|0.570|0.570|0.603|0.570|0.603|0.653|0.653|0.692|0.653|0.692|ns|
|DIFF_HSTL_I_18_S|0.319|0.319|0.339|0.319|0.339|0.782|0.782|0.834|0.782|0.834|0.816|0.816|0.871|0.816|0.871|ns|
|DIFF_HSTL_I_DCI_12_F|0.394|0.394|0.402|0.394|0.402|0.406|0.406|0.429|0.406|0.429|0.534|0.534|0.564|0.534|0.564|ns|
|DIFF_HSTL_I_DCI_12_M|0.394|0.394|0.402|0.394|0.402|0.557|0.557|0.587|0.557|0.587|0.653|0.653|0.694|0.653|0.694|ns|
|DIFF_HSTL_I_DCI_12_S|0.394|0.394|0.402|0.394|0.402|0.755|0.755|0.806|0.755|0.806|0.842|0.842|0.907|0.842|0.907|ns|
|DIFF_HSTL_I_DCI_18_F|0.323|0.323|0.339|0.323|0.339|0.445|0.445|0.461|0.445|0.461|0.566|0.566|0.595|0.566|0.595|ns|
|DIFF_HSTL_I_DCI_18_M|0.323|0.323|0.339|0.323|0.339|0.555|0.555|0.586|0.555|0.586|0.643|0.643|0.684|0.643|0.684|ns|
|DIFF_HSTL_I_DCI_18_S|0.323|0.323|0.339|0.323|0.339|0.762|0.762|0.818|0.762|0.818|0.836|0.836|0.900|0.836|0.900|ns|
|DIFF_HSTL_I_DCI_F|0.397|0.397|0.417|0.397|0.417|0.431|0.431|0.445|0.431|0.445|0.555|0.555|0.575|0.555|0.575|ns|
|DIFF_HSTL_I_DCI_M|0.397|0.397|0.417|0.397|0.417|0.553|0.553|0.583|0.553|0.583|0.644|0.644|0.684|0.644|0.684|ns|
|DIFF_HSTL_I_DCI_S|0.397|0.397|0.417|0.397|0.417|0.767|0.767|0.823|0.767|0.823|0.848|0.848|0.912|0.848|0.912|ns|
|DIFF_HSTL_I_F|0.404|0.404|0.417|0.404|0.417|0.423|0.423|0.443|0.423|0.443|0.549|0.549|0.581|0.549|0.581|ns|
|DIFF_HSTL_I_M|0.404|0.404|0.417|0.404|0.417|0.555|0.555|0.586|0.555|0.586|0.640|0.640|0.677|0.640|0.677|ns|
|DIFF_HSTL_I_S|0.404|0.404|0.417|0.404|0.417|0.767|0.767|0.818|0.767|0.818|0.811|0.811|0.866|0.811|0.866|ns|
|DIFF_HSUL_12_DCI_F|0.381|0.381|0.400|0.381|0.400|0.425|0.425|0.443|0.425|0.443|0.558|0.558|0.586|0.558|0.586|ns|
|DIFF_HSUL_12_DCI_M|0.381|0.381|0.400|0.381|0.400|0.557|0.557|0.587|0.557|0.587|0.653|0.653|0.694|0.653|0.694|ns|
|DIFF_HSUL_12_DCI_S|0.381|0.381|0.400|0.381|0.400|0.737|0.737|0.787|0.737|0.787|0.822|0.822|0.885|0.822|0.885|ns|
|DIFF_HSUL_12_F|0.394|0.394|0.402|0.394|0.402|0.412|0.412|0.430|0.412|0.430|0.538|0.538|0.566|0.538|0.566|ns|
|DIFF_HSUL_12_M|0.394|0.394|0.402|0.394|0.402|0.552|0.552|0.583|0.552|0.583|0.641|0.641|0.679|0.641|0.679|ns|
|DIFF_HSUL_12_S|0.394|0.394|0.402|0.394|0.402|0.752|0.752|0.800|0.752|0.800|0.813|0.813|0.868|0.813|0.868|ns|
|DIFF_POD10_DCI_F|0.411|0.411|0.430|0.411|0.430|0.425|0.425|0.444|0.425|0.444|0.555|0.555|0.584|0.555|0.584|ns|
|DIFF_POD10_DCI_M|0.411|0.411|0.430|0.411|0.430|0.542|0.542|0.571|0.542|0.571|0.640|0.640|0.681|0.640|0.681|ns|
|DIFF_POD10_DCI_S|0.411|0.411|0.430|0.411|0.430|0.754|0.754|0.815|0.754|0.815|0.850|0.850|0.917|0.850|0.917|ns|
|DIFF_POD10_F|0.411|0.411|0.433|0.411|0.433|0.438|0.438|0.459|0.438|0.459|0.569|0.569|0.601|0.569|0.601|ns|
|DIFF_POD10_M|0.411|0.411|0.433|0.411|0.433|0.538|0.538|0.568|0.538|0.568|0.630|0.630|0.667|0.630|0.667|ns|
|DIFF_POD10_S|0.411|0.411|0.433|0.411|0.433|0.766|0.766|0.821|0.766|0.821|0.836|0.836|0.894|0.836|0.894|ns|
|DIFF_POD12_DCI_F|0.407|0.407|0.432|0.407|0.432|0.425|0.425|0.443|0.425|0.443|0.558|0.558|0.586|0.558|0.586|ns|
|DIFF_POD12_DCI_M|0.407|0.407|0.432|0.407|0.432|0.543|0.543|0.572|0.543|0.572|0.638|0.638|0.678|0.638|0.678|ns|
|DIFF_POD12_DCI_S|0.407|0.407|0.432|0.407|0.432|0.772|0.772|0.822|0.772|0.822|0.862|0.862|0.929|0.862|0.929|ns|
|DIFF_POD12_F|0.409|0.409|0.430|0.409|0.430|0.455|0.455|0.476|0.455|0.476|0.595|0.595|0.626|0.595|0.626|ns|
|DIFF_POD12_M|0.409|0.409|0.430|0.409|0.430|0.551|0.551|0.582|0.551|0.582|0.641|0.641|0.679|0.641|0.679|ns|
|DIFF_POD12_S|0.409|0.409|0.430|0.409|0.430|0.767|0.767|0.817|0.767|0.817|0.832|0.832|0.889|0.832|0.889|ns|
|DIFF_SSTL12_DCI_F|0.381|0.381|0.400|0.381|0.400|0.425|0.425|0.443|0.425|0.443|0.558|0.558|0.586|0.558|0.586|ns|
|DIFF_SSTL12_DCI_M|0.381|0.381|0.400|0.381|0.400|0.557|0.557|0.587|0.557|0.587|0.654|0.654|0.694|0.654|0.694|ns|
|DIFF_SSTL12_DCI_S|0.381|0.381|0.400|0.381|0.400|0.754|0.754|0.803|0.754|0.803|0.842|0.842|0.908|0.842|0.908|ns|
DS922 (v1.3) May 8, 2017 **Preliminary Product Specification**
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**Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 29:_ **IOB High Performance (HP) Switching Characteristics** _**(Cont’d)**_
|**I/O Standards**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||**0.90V**|**0.85V**||**0.72V**||**0.90V**|**0.85V**||**0.72V**||**0.90V**|**0.85V**||**0.72V**|||
||**-3**|**-2**|**-1**|**-2**|**-1**|**-3**|**-2**|**-1**|**-2**|**-1**|**-3**|**-2**|**-1**|**-2**|**-1**||
|DIFF_SSTL12_F|0.394|0.394|0.402|0.394|0.402|0.412|0.412|0.430|0.412|0.430|0.538|0.538|0.566|0.538|0.566|ns|
|DIFF_SSTL12_M|0.394|0.394|0.402|0.394|0.402|0.553|0.553|0.584|0.553|0.584|0.641|0.641|0.676|0.641|0.676|ns|
|DIFF_SSTL12_S|0.394|0.394|0.402|0.394|0.402|0.758|0.758|0.808|0.758|0.808|0.823|0.823|0.879|0.823|0.879|ns|
|DIFF_SSTL135_DCI_F|0.371|0.371|0.402|0.371|0.402|0.411|0.411|0.428|0.411|0.428|0.537|0.537|0.565|0.537|0.565|ns|
|DIFF_SSTL135_DCI_M|0.371|0.371|0.402|0.371|0.402|0.551|0.551|0.582|0.551|0.582|0.645|0.645|0.685|0.645|0.685|ns|
|DIFF_SSTL135_DCI_S|0.371|0.371|0.402|0.371|0.402|0.746|0.746|0.799|0.746|0.799|0.829|0.829|0.893|0.829|0.893|ns|
|DIFF_SSTL135_F|0.375|0.375|0.402|0.375|0.402|0.408|0.408|0.428|0.408|0.428|0.528|0.528|0.561|0.528|0.561|ns|
|DIFF_SSTL135_M|0.375|0.375|0.402|0.375|0.402|0.555|0.555|0.585|0.555|0.585|0.641|0.641|0.679|0.641|0.679|ns|
|DIFF_SSTL135_S|0.375|0.375|0.402|0.375|0.402|0.772|0.772|0.823|0.772|0.823|0.827|0.827|0.878|0.827|0.878|ns|
|DIFF_SSTL15_DCI_F|0.397|0.397|0.417|0.397|0.417|0.412|0.412|0.429|0.412|0.429|0.531|0.531|0.563|0.531|0.563|ns|
|DIFF_SSTL15_DCI_M|0.397|0.397|0.417|0.397|0.417|0.553|0.553|0.583|0.553|0.583|0.645|0.645|0.685|0.645|0.685|ns|
|DIFF_SSTL15_DCI_S|0.397|0.397|0.417|0.397|0.417|0.768|0.768|0.822|0.768|0.822|0.847|0.847|0.912|0.847|0.912|ns|
|DIFF_SSTL15_F|0.404|0.404|0.417|0.404|0.417|0.424|0.424|0.445|0.424|0.445|0.551|0.551|0.577|0.551|0.577|ns|
|DIFF_SSTL15_M|0.404|0.404|0.417|0.404|0.417|0.554|0.554|0.585|0.554|0.585|0.639|0.639|0.677|0.639|0.677|ns|
|DIFF_SSTL15_S|0.404|0.404|0.417|0.404|0.417|0.767|0.767|0.817|0.767|0.817|0.813|0.813|0.867|0.813|0.867|ns|
|DIFF_SSTL18_I_DCI_F|0.320|0.320|0.336|0.320|0.336|0.445|0.445|0.461|0.445|0.461|0.566|0.566|0.595|0.566|0.595|ns|
|DIFF_SSTL18_I_DCI_M|0.320|0.320|0.336|0.320|0.336|0.554|0.554|0.585|0.554|0.585|0.644|0.644|0.683|0.644|0.683|ns|
|DIFF_SSTL18_I_DCI_S|0.320|0.320|0.336|0.320|0.336|0.762|0.762|0.818|0.762|0.818|0.837|0.837|0.899|0.837|0.899|ns|
|DIFF_SSTL18_I_F|0.316|0.316|0.336|0.316|0.336|0.454|0.454|0.476|0.454|0.476|0.578|0.578|0.608|0.578|0.608|ns|
|DIFF_SSTL18_I_M|0.316|0.316|0.336|0.316|0.336|0.571|0.571|0.603|0.571|0.603|0.652|0.652|0.692|0.652|0.692|ns|
|DIFF_SSTL18_I_S|0.316|0.316|0.336|0.316|0.336|0.782|0.782|0.835|0.782|0.835|0.816|0.816|0.870|0.816|0.870|ns|
|HSLVDCI_15_F|0.393|0.393|0.415|0.393|0.415|0.425|0.425|0.443|0.425|0.443|0.548|0.548|0.579|0.548|0.579|ns|
|HSLVDCI_15_M|0.393|0.393|0.415|0.393|0.415|0.552|0.552|0.581|0.552|0.581|0.644|0.644|0.684|0.644|0.684|ns|
|HSLVDCI_15_S|0.393|0.393|0.415|0.393|0.415|0.748|0.748|0.802|0.748|0.802|0.827|0.827|0.890|0.827|0.890|ns|
|HSLVDCI_18_F|0.424|0.424|0.447|0.424|0.447|0.445|0.445|0.461|0.445|0.461|0.566|0.566|0.595|0.566|0.595|ns|
|HSLVDCI_18_M|0.424|0.424|0.447|0.424|0.447|0.567|0.567|0.598|0.567|0.598|0.658|0.658|0.699|0.658|0.699|ns|
|HSLVDCI_18_S|0.424|0.424|0.447|0.424|0.447|0.761|0.761|0.817|0.761|0.817|0.836|0.836|0.900|0.836|0.900|ns|
|HSTL_I_12_F|0.378|0.378|0.399|0.378|0.399|0.423|0.423|0.443|0.423|0.443|0.553|0.553|0.582|0.553|0.582|ns|
|HSTL_I_12_M|0.378|0.378|0.399|0.378|0.399|0.551|0.551|0.582|0.551|0.582|0.642|0.642|0.679|0.642|0.679|ns|
|HSTL_I_12_S|0.378|0.378|0.399|0.378|0.399|0.750|0.750|0.799|0.750|0.799|0.813|0.813|0.868|0.813|0.868|ns|
|HSTL_I_18_F|0.322|0.322|0.339|0.322|0.339|0.456|0.456|0.474|0.456|0.474|0.576|0.576|0.606|0.576|0.606|ns|
|HSTL_I_18_M|0.322|0.322|0.339|0.322|0.339|0.569|0.569|0.602|0.569|0.602|0.653|0.653|0.692|0.653|0.692|ns|
|HSTL_I_18_S|0.322|0.322|0.339|0.322|0.339|0.781|0.781|0.833|0.781|0.833|0.816|0.816|0.871|0.816|0.871|ns|
|HSTL_I_DCI_12_F|0.378|0.378|0.399|0.378|0.399|0.406|0.406|0.429|0.406|0.429|0.534|0.534|0.564|0.534|0.564|ns|
|HSTL_I_DCI_12_M|0.378|0.378|0.399|0.378|0.399|0.556|0.556|0.586|0.556|0.586|0.654|0.654|0.694|0.654|0.694|ns|
|HSTL_I_DCI_12_S|0.378|0.378|0.399|0.378|0.399|0.754|0.754|0.803|0.754|0.803|0.842|0.842|0.907|0.842|0.907|ns|
|HSTL_I_DCI_18_F|0.321|0.321|0.339|0.321|0.339|0.445|0.445|0.461|0.445|0.461|0.566|0.566|0.595|0.566|0.595|ns|
|HSTL_I_DCI_18_M|0.321|0.321|0.339|0.321|0.339|0.554|0.554|0.585|0.554|0.585|0.643|0.643|0.684|0.643|0.684|ns|
|HSTL_I_DCI_18_S|0.321|0.321|0.339|0.321|0.339|0.761|0.761|0.817|0.761|0.817|0.836|0.836|0.900|0.836|0.900|ns|
|HSTL_I_DCI_F|0.393|0.393|0.415|0.393|0.415|0.431|0.431|0.445|0.431|0.445|0.555|0.555|0.575|0.555|0.575|ns|
|HSTL_I_DCI_M|0.393|0.393|0.415|0.393|0.415|0.552|0.552|0.581|0.552|0.581|0.644|0.644|0.684|0.644|0.684|ns|
DS922 (v1.3) May 8, 2017 **Preliminary Product Specification**
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Send Feedback
26
**Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 29:_ **IOB High Performance (HP) Switching Characteristics** _**(Cont’d)**_
|**I/O Standards**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||**0.90V**|**0.85V**||**0.72V**||**0.90V**|**0.85V**||**0.72V**||**0.90V**|**0.85V**||**0.72V**|||
||**-3**|**-2**|**-1**|**-2**|**-1**|**-3**|**-2**|**-1**|**-2**|**-1**|**-3**|**-2**|**-1**|**-2**|**-1**||
|HSTL_I_DCI_S|0.393|0.393|0.415|0.393|0.415|0.766|0.766|0.821|0.766|0.821|0.847|0.847|0.912|0.847|0.912|ns|
|HSTL_I_F|0.378|0.378|0.399|0.378|0.399|0.423|0.423|0.443|0.423|0.443|0.549|0.549|0.581|0.549|0.581|ns|
|HSTL_I_M|0.378|0.378|0.399|0.378|0.399|0.554|0.554|0.585|0.554|0.585|0.640|0.640|0.677|0.640|0.677|ns|
|HSTL_I_S|0.378|0.378|0.399|0.378|0.399|0.766|0.766|0.816|0.766|0.816|0.811|0.811|0.866|0.811|0.866|ns|
|HSUL_12_DCI_F|0.378|0.378|0.399|0.378|0.399|0.425|0.425|0.443|0.425|0.443|0.558|0.558|0.586|0.558|0.586|ns|
|HSUL_12_DCI_M|0.378|0.378|0.399|0.378|0.399|0.556|0.556|0.586|0.556|0.586|0.654|0.654|0.694|0.654|0.694|ns|
|HSUL_12_DCI_S|0.378|0.378|0.399|0.378|0.399|0.736|0.736|0.784|0.736|0.784|0.821|0.821|0.886|0.821|0.886|ns|
|HSUL_12_F|0.378|0.378|0.399|0.378|0.399|0.412|0.412|0.430|0.412|0.430|0.538|0.538|0.566|0.538|0.566|ns|
|HSUL_12_M|0.378|0.378|0.399|0.378|0.399|0.551|0.551|0.582|0.551|0.582|0.642|0.642|0.679|0.642|0.679|ns|
|HSUL_12_S|0.378|0.378|0.399|0.378|0.399|0.750|0.750|0.799|0.750|0.799|0.813|0.813|0.868|0.813|0.868|ns|
|LVCMOS12_F_2|0.512|0.512|0.555|0.512|0.555|0.672|0.672|0.692|0.672|0.692|0.898|0.898|0.922|0.898|0.922|ns|
|LVCMOS12_F_4|0.512|0.512|0.555|0.512|0.555|0.504|0.504|0.521|0.504|0.521|0.664|0.664|0.693|0.664|0.693|ns|
|LVCMOS12_F_6|0.512|0.512|0.555|0.512|0.555|0.485|0.485|0.507|0.485|0.507|0.634|0.634|0.669|0.634|0.669|ns|
|LVCMOS12_F_8|0.512|0.512|0.555|0.512|0.555|0.465|0.465|0.489|0.465|0.489|0.611|0.611|0.666|0.611|0.666|ns|
|LVCMOS12_M_2|0.512|0.512|0.555|0.512|0.555|0.708|0.708|0.727|0.708|0.727|0.916|0.916|0.945|0.916|0.945|ns|
|LVCMOS12_M_4|0.512|0.512|0.555|0.512|0.555|0.550|0.550|0.573|0.550|0.573|0.664|0.664|0.690|0.664|0.690|ns|
|LVCMOS12_M_6|0.512|0.512|0.555|0.512|0.555|0.527|0.527|0.554|0.527|0.554|0.622|0.622|0.652|0.622|0.652|ns|
|LVCMOS12_M_8|0.512|0.512|0.555|0.512|0.555|0.540|0.540|0.571|0.540|0.571|0.614|0.614|0.649|0.614|0.649|ns|
|LVCMOS12_S_2|0.512|0.512|0.555|0.512|0.555|0.767|0.767|0.803|0.767|0.803|0.990|0.990|1.024|0.990|1.024|ns|
|LVCMOS12_S_4|0.512|0.512|0.555|0.512|0.555|0.666|0.666|0.704|0.666|0.704|0.803|0.803|0.848|0.803|0.848|ns|
|LVCMOS12_S_6|0.512|0.512|0.555|0.512|0.555|0.657|0.657|0.695|0.657|0.695|0.732|0.732|0.774|0.732|0.774|ns|
|LVCMOS12_S_8|0.512|0.512|0.555|0.512|0.555|0.708|0.708|0.761|0.708|0.761|0.745|0.745|0.790|0.745|0.790|ns|
|LVCMOS15_F_12|0.414|0.414|0.445|0.414|0.445|0.500|0.500|0.522|0.500|0.522|0.647|0.647|0.682|0.647|0.682|ns|
|LVCMOS15_F_2|0.414|0.414|0.445|0.414|0.445|0.702|0.702|0.722|0.702|0.722|0.919|0.919|0.940|0.919|0.940|ns|
|LVCMOS15_F_4|0.414|0.414|0.445|0.414|0.445|0.579|0.579|0.601|0.579|0.601|0.755|0.755|0.781|0.755|0.781|ns|
|LVCMOS15_F_6|0.414|0.414|0.445|0.414|0.445|0.547|0.547|0.569|0.547|0.569|0.711|0.711|0.742|0.711|0.742|ns|
|LVCMOS15_F_8|0.414|0.414|0.445|0.414|0.445|0.518|0.518|0.538|0.518|0.538|0.686|0.686|0.703|0.686|0.703|ns|
|LVCMOS15_M_12|0.414|0.414|0.445|0.414|0.445|0.607|0.607|0.644|0.607|0.644|0.637|0.637|0.676|0.637|0.676|ns|
|LVCMOS15_M_2|0.414|0.414|0.445|0.414|0.445|0.741|0.741|0.770|0.741|0.770|0.938|0.938|0.962|0.938|0.962|ns|
|LVCMOS15_M_4|0.414|0.414|0.445|0.414|0.445|0.625|0.625|0.651|0.625|0.651|0.754|0.754|0.786|0.754|0.786|ns|
|LVCMOS15_M_6|0.414|0.414|0.445|0.414|0.445|0.576|0.576|0.604|0.576|0.604|0.674|0.674|0.710|0.674|0.710|ns|
|LVCMOS15_M_8|0.414|0.414|0.445|0.414|0.445|0.568|0.568|0.601|0.568|0.601|0.639|0.639|0.681|0.639|0.681|ns|
|LVCMOS15_S_12|0.414|0.414|0.445|0.414|0.445|0.788|0.788|0.855|0.788|0.855|0.695|0.695|0.733|0.695|0.733|ns|
|LVCMOS15_S_2|0.414|0.414|0.445|0.414|0.445|0.829|0.829|0.864|0.829|0.864|1.039|1.039|1.079|1.039|1.079|ns|
|LVCMOS15_S_4|0.414|0.414|0.445|0.414|0.445|0.687|0.687|0.725|0.687|0.725|0.813|0.813|0.851|0.813|0.851|ns|
|LVCMOS15_S_6|0.414|0.414|0.445|0.414|0.445|0.671|0.671|0.710|0.671|0.710|0.726|0.726|0.763|0.726|0.763|ns|
|LVCMOS15_S_8|0.414|0.414|0.445|0.414|0.445|0.704|0.704|0.755|0.704|0.755|0.721|0.721|0.758|0.721|0.758|ns|
|LVCMOS18_F_12|0.418|0.418|0.445|0.418|0.445|0.573|0.573|0.601|0.573|0.601|0.731|0.731|0.769|0.731|0.769|ns|
|LVCMOS18_F_2|0.418|0.418|0.445|0.418|0.445|0.739|0.739|0.760|0.739|0.760|0.945|0.945|0.971|0.945|0.971|ns|
|LVCMOS18_F_4|0.418|0.418|0.445|0.418|0.445|0.609|0.609|0.630|0.609|0.630|0.778|0.778|0.802|0.778|0.802|ns|
|LVCMOS18_F_6|0.418|0.418|0.445|0.418|0.445|0.603|0.603|0.633|0.603|0.633|0.781|0.781|0.808|0.781|0.808|ns|
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**Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 29:_ **IOB High Performance (HP) Switching Characteristics** _**(Cont’d)**_
|**I/O Standards**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||**0.90V**|**0.85V**||**0.72V**||**0.90V**|**0.85V**||**0.72V**||**0.90V**|**0.85V**||**0.72V**|||
||**-3**|**-2**|**-1**|**-2**|**-1**|**-3**|**-2**|**-1**|**-2**|**-1**|**-3**|**-2**|**-1**|**-2**|**-1**||
|LVCMOS18_F_8|0.418|0.418|0.445|0.418|0.445|0.573|0.573|0.600|0.573|0.600|0.733|0.733|0.767|0.733|0.767|ns|
|LVCMOS18_M_12|0.418|0.418|0.445|0.418|0.445|0.640|0.640|0.678|0.640|0.678|0.670|0.670|0.709|0.670|0.709|ns|
|LVCMOS18_M_2|0.418|0.418|0.445|0.418|0.445|0.798|0.798|0.822|0.798|0.822|0.991|0.991|1.016|0.991|1.016|ns|
|LVCMOS18_M_4|0.418|0.418|0.445|0.418|0.445|0.664|0.664|0.693|0.664|0.693|0.798|0.798|0.836|0.798|0.836|ns|
|LVCMOS18_M_6|0.418|0.418|0.445|0.418|0.445|0.629|0.629|0.663|0.629|0.663|0.735|0.735|0.775|0.735|0.775|ns|
|LVCMOS18_M_8|0.418|0.418|0.445|0.418|0.445|0.626|0.626|0.661|0.626|0.661|0.705|0.705|0.746|0.705|0.746|ns|
|LVCMOS18_S_12|0.418|0.418|0.445|0.418|0.445|0.795|0.795|0.861|0.795|0.861|0.683|0.683|0.721|0.683|0.721|ns|
|LVCMOS18_S_2|0.418|0.418|0.445|0.418|0.445|0.862|0.862|0.897|0.862|0.897|1.076|1.076|1.098|1.076|1.098|ns|
|LVCMOS18_S_4|0.418|0.418|0.445|0.418|0.445|0.716|0.716|0.758|0.716|0.758|0.829|0.829|0.872|0.829|0.872|ns|
|LVCMOS18_S_6|0.418|0.418|0.445|0.418|0.445|0.682|0.682|0.724|0.682|0.724|0.724|0.724|0.762|0.724|0.762|ns|
|LVCMOS18_S_8|0.418|0.418|0.445|0.418|0.445|0.707|0.707|0.760|0.707|0.760|0.709|0.709|0.745|0.709|0.745|ns|
|LVDCI_15_F|0.425|0.425|0.462|0.425|0.462|0.426|0.426|0.443|0.426|0.443|0.548|0.548|0.581|0.548|0.581|ns|
|LVDCI_15_M|0.425|0.425|0.462|0.425|0.462|0.553|0.553|0.582|0.553|0.582|0.645|0.645|0.685|0.645|0.685|ns|
|LVDCI_15_S|0.425|0.425|0.462|0.425|0.462|0.749|0.749|0.803|0.749|0.803|0.821|0.821|0.890|0.821|0.890|ns|
|LVDCI_18_F|0.414|0.414|0.447|0.414|0.447|0.441|0.441|0.459|0.441|0.459|0.560|0.560|0.589|0.560|0.589|ns|
|LVDCI_18_M|0.414|0.414|0.447|0.414|0.447|0.554|0.554|0.585|0.554|0.585|0.644|0.644|0.683|0.644|0.683|ns|
|LVDCI_18_S|0.414|0.414|0.447|0.414|0.447|0.760|0.760|0.818|0.760|0.818|0.837|0.837|0.899|0.837|0.899|ns|
|LVDS|0.539|0.539|0.620|0.539|0.620|0.626|0.626|0.662|0.626|0.662|960.447|960.447|960.447|960.447|960.447|ns|
|MIPI_DPHY_DCI_HS|0.386|0.386|0.415|0.386|0.415|0.502|0.502|0.522|0.502|0.522|N/A|N/A|N/A|N/A|N/A|ns|
|MIPI_DPHY_DCI_LP|8.438|8.438|8.792|8.438|8.792|0.914|0.914|0.937|0.914|0.937|N/A|N/A|N/A|N/A|N/A|ns|
|POD10_DCI_F|0.408|0.408|0.430|0.408|0.430|0.425|0.425|0.444|0.425|0.444|0.555|0.555|0.584|0.555|0.584|ns|
|POD10_DCI_M|0.408|0.408|0.430|0.408|0.430|0.542|0.542|0.571|0.542|0.571|0.640|0.640|0.681|0.640|0.681|ns|
|POD10_DCI_S|0.408|0.408|0.430|0.408|0.430|0.754|0.754|0.815|0.754|0.815|0.850|0.850|0.917|0.850|0.917|ns|
|POD10_F|0.407|0.407|0.430|0.407|0.430|0.438|0.438|0.459|0.438|0.459|0.569|0.569|0.601|0.569|0.601|ns|
|POD10_M|0.407|0.407|0.430|0.407|0.430|0.538|0.538|0.568|0.538|0.568|0.630|0.630|0.667|0.630|0.667|ns|
|POD10_S|0.407|0.407|0.430|0.407|0.430|0.766|0.766|0.821|0.766|0.821|0.836|0.836|0.894|0.836|0.894|ns|
|POD12_DCI_F|0.409|0.409|0.431|0.409|0.431|0.425|0.425|0.443|0.425|0.443|0.558|0.558|0.586|0.558|0.586|ns|
|POD12_DCI_M|0.409|0.409|0.431|0.409|0.431|0.543|0.543|0.572|0.543|0.572|0.638|0.638|0.678|0.638|0.678|ns|
|POD12_DCI_S|0.409|0.409|0.431|0.409|0.431|0.772|0.772|0.822|0.772|0.822|0.862|0.862|0.929|0.862|0.929|ns|
|POD12_F|0.409|0.409|0.431|0.409|0.431|0.455|0.455|0.476|0.455|0.476|0.595|0.595|0.626|0.595|0.626|ns|
|POD12_M|0.409|0.409|0.431|0.409|0.431|0.551|0.551|0.582|0.551|0.582|0.641|0.641|0.679|0.641|0.679|ns|
|POD12_S|0.409|0.409|0.431|0.409|0.431|0.767|0.767|0.817|0.767|0.817|0.832|0.832|0.889|0.832|0.889|ns|
|SLVS_400_18|0.539|0.539|0.620|0.539|0.620|N/A|N/A|N/A|N/A|N/A|N/A|N/A|N/A|N/A|N/A|ns|
|SSTL12_DCI_F|0.381|0.381|0.399|0.381|0.399|0.425|0.425|0.443|0.425|0.443|0.558|0.558|0.586|0.558|0.586|ns|
|SSTL12_DCI_M|0.381|0.381|0.399|0.381|0.399|0.557|0.557|0.587|0.557|0.587|0.654|0.654|0.694|0.654|0.694|ns|
|SSTL12_DCI_S|0.381|0.381|0.399|0.381|0.399|0.754|0.754|0.803|0.754|0.803|0.842|0.842|0.908|0.842|0.908|ns|
|SSTL12_F|0.403|0.403|0.403|0.403|0.403|0.412|0.412|0.430|0.412|0.430|0.538|0.538|0.566|0.538|0.566|ns|
|SSTL12_M|0.403|0.403|0.403|0.403|0.403|0.553|0.553|0.584|0.553|0.584|0.641|0.641|0.676|0.641|0.676|ns|
|SSTL12_S|0.403|0.403|0.403|0.403|0.403|0.758|0.758|0.808|0.758|0.808|0.823|0.823|0.879|0.823|0.879|ns|
|SSTL135_DCI_F|0.366|0.366|0.399|0.366|0.399|0.411|0.411|0.428|0.411|0.428|0.537|0.537|0.565|0.537|0.565|ns|
|SSTL135_DCI_M|0.366|0.366|0.399|0.366|0.399|0.551|0.551|0.582|0.551|0.582|0.645|0.645|0.685|0.645|0.685|ns|
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**Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 29:_ **IOB High Performance (HP) Switching Characteristics** _**(Cont’d)**_
|**I/O Standards**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||**0.90V**|**0.85V**||**0.72V**||**0.90V**|**0.85V**||**0.72V**||**0.90V**|**0.85V**||**0.72V**|||
||**-3**|**-2**|**-1**|**-2**|**-1**|**-3**|**-2**|**-1**|**-2**|**-1**|**-3**|**-2**|**-1**|**-2**|**-1**||
|SSTL135_DCI_S|0.366|0.366|0.399|0.366|0.399|0.746|0.746|0.799|0.746|0.799|0.829|0.829|0.893|0.829|0.893|ns|
|SSTL135_F|0.378|0.378|0.399|0.378|0.399|0.408|0.408|0.428|0.408|0.428|0.528|0.528|0.561|0.528|0.561|ns|
|SSTL135_M|0.378|0.378|0.399|0.378|0.399|0.555|0.555|0.585|0.555|0.585|0.641|0.641|0.679|0.641|0.679|ns|
|SSTL135_S|0.378|0.378|0.399|0.378|0.399|0.772|0.772|0.823|0.772|0.823|0.827|0.827|0.878|0.827|0.878|ns|
|SSTL15_DCI_F|0.402|0.402|0.417|0.402|0.417|0.412|0.412|0.429|0.412|0.429|0.531|0.531|0.563|0.531|0.563|ns|
|SSTL15_DCI_M|0.402|0.402|0.417|0.402|0.417|0.553|0.553|0.583|0.553|0.583|0.645|0.645|0.685|0.645|0.685|ns|
|SSTL15_DCI_S|0.402|0.402|0.417|0.402|0.417|0.768|0.768|0.822|0.768|0.822|0.847|0.847|0.912|0.847|0.912|ns|
|SSTL15_F|0.371|0.371|0.400|0.371|0.400|0.408|0.408|0.428|0.408|0.428|0.530|0.530|0.556|0.530|0.556|ns|
|SSTL15_M|0.371|0.371|0.400|0.371|0.400|0.554|0.554|0.585|0.554|0.585|0.639|0.639|0.677|0.639|0.677|ns|
|SSTL15_S|0.371|0.371|0.400|0.371|0.400|0.767|0.767|0.817|0.767|0.817|0.813|0.813|0.867|0.813|0.867|ns|
|SSTL18_I_DCI_F|0.329|0.329|0.336|0.329|0.336|0.445|0.445|0.461|0.445|0.461|0.566|0.566|0.595|0.566|0.595|ns|
|SSTL18_I_DCI_M|0.329|0.329|0.336|0.329|0.336|0.554|0.554|0.585|0.554|0.585|0.644|0.644|0.683|0.644|0.683|ns|
|SSTL18_I_DCI_S|0.329|0.329|0.336|0.329|0.336|0.762|0.762|0.818|0.762|0.818|0.837|0.837|0.899|0.837|0.899|ns|
|SSTL18_I_F|0.316|0.316|0.337|0.316|0.337|0.454|0.454|0.476|0.454|0.476|0.578|0.578|0.608|0.578|0.608|ns|
|SSTL18_I_M|0.316|0.316|0.337|0.316|0.337|0.571|0.571|0.603|0.571|0.603|0.652|0.652|0.692|0.652|0.692|ns|
|SSTL18_I_S|0.316|0.316|0.337|0.316|0.337|0.782|0.782|0.835|0.782|0.835|0.816|0.816|0.870|0.816|0.870|ns|
|SUB_LVDS|0.539|0.539|0.620|0.539|0.620|0.660|0.660|0.692|0.660|0.692|969.863|969.863|969.863|969.863|969.863|ns|
## **IOB 3-state Output Switching Characteristics**
Table 30 specifies the values of TOUTBUF_DELAY_TE_PAD and TINBUF_DELAY_IBUFDIS_O. TOUTBUF_DELAY_TE_PAD is the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is enabled (i.e., a high impedance state). TINBUF_DELAY_IBUFDIS_O is the IOB delay from IBUFDISABLE to O output. In HP I/O banks, the internal DCI termination turn-off time is always faster than TOUTBUF_DELAY_TE_PAD when the DCITERMDISABLE pin is used. In HD I/O banks, the internal IN_TERM termination turn-off time is always faster than TOUTBUF_DELAY_TE_PAD when the INTERMDISABLE pin is used.
_Table 30:_ **IOB 3-state Output Switching Characteristics**
|**Symbol**|**Description**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Units**|
|---|---|---|---|---|---|---|---|
|||**0.90V**|**0.85V**||**0.72V**|||
|||**-3**|**-2**|**-1**|**-2**|**-1**||
|TOUTBUF_DELAY_TE_PAD|T input to pad high-impedance for<br>HD I/O banks<br>T input to pad high-impedance for<br>HP I/O banks|6.318|6.318|6.369|6.318|6.369|ns|
|||5.330|5.330|5.341|5.330|5.341|ns|
|TINBUF_DELAY_IBUFDIS_O|IBUF turn-on time from<br>IBUFDISABLE to O output for HD<br>I/O banks<br>IBUF turn-on time from<br>IBUFDISABLE to O output for HP<br>I/O banks|2.266|2.266|2.430|2.266|2.430|ns|
|||0.936|0.936|1.037|0.936|1.037|ns|
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**Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
## **Input Delay Measurement Methodology**
Table 31 shows the test setup parameters used for measuring input delay.
_Table 31:_ **Input Delay Measurement Methodology**
|**Description**|**I/O Standard**<br>**Attribute**|**VL(1)(2)**|**VH(1)(2)**|**VMEAS**<br>**(1)(4)(6)**|**VREF**<br>**(1)(3)(5)**|
|---|---|---|---|---|---|
|LVCMOS, 1.2V|LVCMOS12|0.1|1.1|0.6|–|
|LVCMOS, LVDCI, HSLVDCI, 1.5V|LVCMOS15,<br>LVDCI_15,<br>HSLVDCI_15|0.1|1.4|0.75|–|
|LVCMOS, LVDCI, HSLVDCI, 1.8V|LVCMOS18,<br>LVDCI_18,<br>HSLVDCI_18|0.1|1.7|0.9|–|
|LVCMOS, 2.5V|LVCMOS25|0.1|2.4|1.25|–|
|LVCMOS, 3.3V|LVCMOS33|0.1|3.2|1.65|–|
|LVTTL, 3.3V|LVTTL|0.1|3.2|1.65|–|
|HSTL (high-speed transceiver logic),<br>class I, 1.2V|HSTL_I_12|VREF – 0.25|VREF + 0.25|VREF|0.6|
|HSTL, class I, 1.5V|HSTL_I|VREF – 0.325|VREF + 0.325|VREF|0.75|
|HSTL, class I, 1.8V|HSTL_I_18|VREF – 0.4|VREF + 0.4|VREF|0.9|
|HSUL (high-speed unterminated logic), 1.2V|HSUL_12|VREF – 0.25|VREF + 0.25|VREF|0.6|
|SSTL12 (stub series terminated logic), 1.2V|SSTL12|VREF – 0.25|VREF + 0.25|VREF|0.6|
|SSTL135 and SSTL135 class II, 1.35V|SSTL135,<br>SSTL135_II|VREF – 0.2875|VREF + 0.2875|VREF|0.675|
|SSTL15 and SSTL15 class II, 1.5V|SSTL15, SSTL15_II|VREF – 0.325|VREF + 0.325|VREF|0.75|
|SSTL18, class I and II, 1.8V|SSTL18_I,<br>SSTL18_II|VREF – 0.4|VREF + 0.4|VREF|0.9|
|POD10, 1.0V|POD10|VREF – 0.2|VREF + 0.2|VREF|0.7|
|POD12, 1.2V|POD12|VREF – 0.24|VREF + 0.24|VREF|0.84|
|DIFF_HSTL, class I, 1.2V|DIFF_HSTL_I_12|0.6 – 0.25|0.6 + 0.25|0(6)|–|
|DIFF_HSTL, class I, 1.5V|DIFF_HSTL_I|0.75 – 0.325|0.75 + 0.325|0(6)|–|
|DIFF_HSTL, class I, 1.8V|DIFF_HSTL_I_18|0.9 – 0.4|0.9 + 0.4|0(6)|–|
|DIFF_HSUL, 1.2V|DIFF_HSUL_12|0.6 – 0.25|0.6 + 0.25|0(6)|–|
|DIFF_SSTL, 1.2V|DIFF_SSTL12|0.6 – 0.25|0.6 + 0.25|0(6)|–|
|DIFF_SSTL135 and DIFF_SSTL135 class II,<br>1.35V|DIFF_SSTL135,<br>DIFF_SSTL135_II|0.675 – 0.2875|0.675 + 0.2875|0(6)|–|
|DIFF_SSTL15 and DIFF_SSTL15 class II,<br>1.5V|DIFF_SSTL15,<br>DIFF_SSTL15_II|0.75 – 0.325|0.75 + 0.325|0(6)|–|
|DIFF_SSTL18_I, DIFF_SSTL18_II, 1.8V|DIFF_SSTL18_I,<br>DIFF_SSTL18_II|0.9 – 0.4|0.9 + 0.4|0(6)|–|
|DIFF_POD10, 1.0V|DIFF_POD10|0.5 – 0.2|0.5 + 0.2|0(6)|–|
|DIFF_POD12, 1.2V|DIFF_POD12|0.6 – 0.25|0.6 + 0.25|0(6)|–|
|LVDS (low-voltage differential signaling),<br>1.8V|LVDS|0.9 – 0.125|0.9 + 0.125|0(6)|–|
|LVDS_25, 2.5V|LVDS_25|1.25 – 0.125|1.25 + 0.125|0(6)|–|
|SUB_LVDS, 1.8V|SUB_LVDS|0.9 – 0.125|0.9 + 0.125|0(6)|–|
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**Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 31:_ **Input Delay Measurement Methodology** _**(Cont’d)**_
|**Description**|**I/O Standard**<br>**Attribute**|**VL(1)(2)**|**VH(1)(2)**|**VMEAS**<br>**(1)(4)(6)**|**VREF**<br>**(1)(3)(5)**|
|---|---|---|---|---|---|
|SLVS, 1.8V|SLVS_400_18|0.9 – 0.125|0.9 + 0.125|0(6)|–|
|SLVS, 2.5V|SLVS_400_25|1.25 – 0.125|1.25 + 0.125|0(6)|–|
|LVPECL, 2.5V|LVPECL|1.25 – 0.125|1.25 + 0.125|0(6)|–|
|MIPI D-PHY (high speed) 1.2V|MIPI_DPHY_DCI_HS|0.2 – 0.125|0.2 + 0.125|0(6)|–|
|MIPI D-PHY (low power) 1.2V|MIPI_DPHY_DCI_LP|0.715 – 0.2|0.715 + 0.2|0(6)|–|
## **Notes:**
1. The input delay measurement methodology parameters for LVDCI/HSLVDCI are the same for LVCMOS standards of the same voltage. Parameters for all other DCI standards are the same for the corresponding non-DCI standards.
2. Input waveform switches between VLand VH.
3. Measurements are made at typical, minimum, and maximum VREF values. Reported delays reflect worst case of these measurements. VREF values listed are typical.
4. Input voltage level from which measurement starts.
5. This is an input voltage reference that bears no relation to the VREF/VMEAS parameters found in IBIS models and/or noted in Figure 1.
6. The value given is the differential input voltage.
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**Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
## **Output Delay Measurement Methodology**
Output delays are measured with short output traces. Standard termination was used for all testing. The propagation delay of the trace is characterized separately and subtracted from the final measurement, and is therefore not included in the generalized test setups shown in Figure 1 and Figure 2.
**==> picture [348 x 187] intentionally omitted <==**
**----- Start of picture text -----**<br>
VREF<br>Output RREF<br>VMEAS (voltage level when taking delay measurement)<br>CREF (probe capacitance)<br>X16654-101316<br>**----- End of picture text -----**<br>
_Figure 1:_ **Single-Ended Test Setup**
**==> picture [180 x 78] intentionally omitted <==**
**----- Start of picture text -----**<br>
Output<br>+<br>CREF RREF VMEAS<br>–<br>X16640-101316<br>**----- End of picture text -----**<br>
_Figure 2:_ **Differential Test Setup**
Parameters VREF, RREF, CREF, and VMEAS fully describe the test conditions for each I/O standard. The most accurate prediction of propagation delay in any given application can be obtained through IBIS simulation, using this method:
1. Simulate the output driver of choice into the generalized test setup using values from Table 32.
2. Record the time to VMEAS.
3. Simulate the output driver of choice into the actual PCB trace and load using the appropriate IBIS model or capacitance value to represent the load.
4. Record the time to VMEAS.
5. Compare the results of step 2 and step 4. The increase or decrease in delay yields the actual propagation delay of the PCB trace.
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**Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 32:_ **Output Delay Measurement Methodology**
|**Description**|**I/O Standard Attribute**|**RREF**<br>**(**Ω**)**|**CREF(1)**<br>**(pF)**|**VMEAS**<br>**(V)**|**VREF**<br>**(V)**|
|---|---|---|---|---|---|
|LVCMOS, 1.2V|LVCMOS12|1M|0|0.6|0|
|LVCMOS, 1.5V|LVCMOS15|1M|0|0.75|0|
|LVCMOS, 1.8V|LVCMOS18|1M|0|0.9|0|
|LVCMOS, 2.5V|LVCMOS25|1M|0|1.25|0|
|LVCMOS, 3.3V|LVCMOS33|1M|0|1.65|0|
|LVTTL, 3.3V|LVTTL|1M|0|1.65|0|
|LVDCI, HSLVDCI, 1.5V|LVDCI_15, HSLVDCI_15|50|0|VREF|0.75|
|LVDCI, HSLVDCI, 1.8V|LVDCI_15, HSLVDCI_18|50|0|VREF|0.9|
|HSTL (high-speed transceiver logic), class I, 1.2V|HSTL_I_12|50|0|VREF|0.6|
|HSTL, class I, 1.5V|HSTL_I|50|0|VREF|0.75|
|HSTL, class I, 1.8V|HSTL_I_18|50|0|VREF|0.9|
|HSUL (high-speed unterminated logic), 1.2V|HSUL_12|50|0|VREF|0.6|
|SSTL12 (stub series terminated logic), 1.2V|SSTL12|50|0|VREF|0.6|
|SSTL135 and SSTL135 class II, 1.35V|SSTL135, SSTL135_II|50|0|VREF|0.675|
|SSTL15 and SSTL15 class II, 1.5V|SSTL15, SSTL15_II|50|0|VREF|0.75|
|SSTL18, class I and class II, 1.8V|SSTL18_I, SSTL18_II|50|0|VREF|0.9|
|POD10, 1.0V|POD10|50|0|VREF|1.0|
|POD12, 1.2V|POD12|50|0|VREF|1.2|
|DIFF_HSTL, class I, 1.2V|DIFF_HSTL_I_12|50|0|VREF|0.6|
|DIFF_HSTL, class I, 1.5V|DIFF_HSTL_I|50|0|VREF|0.75|
|DIFF_HSTL, class I, 1.8V|DIFF_HSTL_I_18|50|0|VREF|0.9|
|DIFF_HSUL, 1.2V|DIFF_HSUL_12|50|0|VREF|0.6|
|DIFF_SSTL12, 1.2V|DIFF_SSTL12|50|0|VREF|0.6|
|DIFF_SSTL135 and DIFF_SSTL135 class II, 1.35V|DIFF_SSTL135,<br>DIFF_SSTL135_II|50|0|VREF|0.675|
|DIFF_SSTL15 and DIFF_SSTL15 class II, 1.5V|DIFF_SSTL15,<br>DIFF_SSTL15_II|50|0|VREF|0.75|
|DIFF_SSTL18, class I and II, 1.8V|DIFF_SSTL18_I,<br>DIFF_SSTL18_II|50|0|VREF|0.9|
|DIFF_POD10, 1.0V|DIFF_POD10|50|0|VREF|1.0|
|DIFF_POD12, 1.2V|DIFF_POD12|50|0|VREF|1.2|
|LVDS (low-voltage differential signaling), 1.8V|LVDS|100|0|0(2)|0|
|SUB_LVDS, 1.8V|SUB_LVDS|100|0|0(2)|0|
|MIPI D-PHY (high speed) 1.2V|MIPI_DPHY_DCI_HS|100|0|0(2)|0|
|MIPI D-PHY (low power) 1.2V|MIPI_DPHY_DCI_LP|1M|0|0.6|0|
## **Notes:**
1. CREF is the capacitance of the probe, nominally 0 pF.
2. The value given is the differential output voltage.
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**Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
## **Block RAM and FIFO Switching Characteristics**
_Table 33:_ **Block RAM and FIFO Switching Characteristics**
|**Symbol**|**Description**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Units**|
|---|---|---|---|---|---|---|---|
|||**0.90V**|**0.85V**||**0.72V**|||
|||**-3**|**-2**|**-1**|**-2**|**-1**||
|**Maximum Frequency**||||||||
|FMAX_WF_NC|Block RAM<br>(WRITE_FIRST and NO_CHANGE modes).|825|738|645|585|516|MHz|
|FMAX_RF|Block RAM (READ_FIRST mode).|718|637|575|510|460|MHz|
|FMAX_FIFO|FIFO in all modes without ECC.|825|738|645|585|516|MHz|
|FMAX_ECC|Block RAM and FIFO in ECC configuration<br>without PIPELINE.|718|637|575|510|460|MHz|
||Block RAM and FIFO in ECC configuration<br>with PIPELINE and Block RAM in<br>WRITE_FIRST or NO_CHANGE mode.|825|738|645|585|516|MHz|
|TPW(1)|Minimum pulse width.|495|542|543|577|578|ps|
|**Block RAM and FIFO Clock-to-Out Delays**||||||||
|TRCKO_DO|Clock CLK to DOUT output (without output<br>register).|0.91|1.02|1.11|1.46|1.53|ns,<br>Max|
|TRCKO_DO_REG|Clock CLK to DOUT output (with output<br>register).|0.27|0.29|0.30|0.42|0.44|ns,<br>Max|
## **Notes:**
1. The MMCM and PLL DUTY_CYCLE attribute should be set to 50% to meet the pulse-width requirements at the higher frequencies.
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**Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
## **UltraRAM Switching Characteristics**
The _UltraScale Architecture and Product Overview_ (DS890) lists the Kintex UltraScale+ FPGAs that include this memory.
_Table 34:_ **UltraRAM Switching Characteristics**
|**Symbol**|**Description**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Units**|
|---|---|---|---|---|---|---|---|
|||**0.90V**|**0.85V**||**0.72V**|||
|||**-3**|**-2**|**-1**|**-2**|**-1**||
|**Maximum Frequency**||||||||
|FMAX|UltraRAM maximum frequency with<br>OREG_B = True.|650|600|575|500|481|MHz|
|FMAX_ECC|UltraRAM maximum frequency with<br>OREG_B = False and EN_ECC_RD_B = True.|450|400|386|325|315|MHz|
|FMAX_NORPIPELINE|UltraRAM maximum frequency with<br>OREG_B = False and<br>EN_ECC_RD_B = False.|550|500|478|425|408|MHz|
|TPW(1)|Minimum pulse width.|650|700|730|800|832|ps|
|TRSTPW|Asynchronous reset minimum pulse width.<br>One cycle required.|1 clock cycle||||||
## **Notes:**
1. The MMCM and PLL DUTY_CYCLE attribute should be set to 50% to meet the pulse-width requirements at the higher frequencies.
## **Input/Output Delay Switching Characteristics**
_Table 35:_ **Input/Output Delay Switching Characteristics**
|**Symbol**|**Description**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Units**|
|---|---|---|---|---|---|---|---|
|||**0.90V**|**0.85V**||**0.72V**|||
|||**-3**|**-2**|**-1**|**-2**|**-1**||
|FREFCLK|REFCLK frequency for IDELAYCTRL<br>(component mode).|300 to 800|||||MHz|
||REFCLK frequency for<br>BITSLICE_CONTROL (native<br>mode).|300 to<br>2666.67|300 to<br>2666.67|300 to<br>2400|300 to<br>2400|300 to<br>2133|MHz|
|TMINPER_CLK|Minimum period for IODELAY<br>clock.|3.195|3.195|3.195|3.195|3.195|ns|
|TMINPER_RST|Minimum reset pulse width.|52.00|||||ns|
|TIDELAY_RESOLUTION/<br>TODELAY_RESOLUTION|IDELAY/ODELAY chain resolution.|2.1 to 12|||||ps|
## **Notes:**
1. PLL settings could restrict the minimum allowable data rate. For example, when using a PLL with CLKOUTPHY = VCO_HALF, the minimum frequency is PLL_FVCOMIN/2.
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**Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
## **DSP48 Slice Switching Characteristics**
_Table 36:_ **DSP48 Slice Switching Characteristics**
|**Symbol**|**Description**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Units**|
|---|---|---|---|---|---|---|---|
|||**0.90V**|**0.85V**||**0.72V**|||
|||**-3**|**-2**|**-1**|**-2**|**-1**||
|**Maximum Frequency**||||||||
|FMAX|With all registers used.|891|775|645|644|600|MHz|
|FMAX_PATDET|With pattern detector.|794|687|571|562|524|MHz|
|FMAX_MULT_NOMREG|Two register multiply<br>without MREG.|635|544|456|440|413|MHz|
|FMAX_MULT_NOMREG_PATDET|Two register multiply<br>without MREG with pattern<br>detect.|577|492|410|395|371|MHz|
|FMAX_PREADD_NOADREG|Without ADREG.|655|565|468|453|423|MHz|
|FMAX_NOPIPELINEREG|Without pipeline registers<br>(MREG, ADREG).|483|410|338|323|304|MHz|
|FMAX_NOPIPELINEREG_PATDET|Without pipeline registers<br>(MREG, ADREG) with<br>pattern detect.|448|379|314|299|280|MHz|
## **Clock Buffers and Networks**
_Table 37:_ **Clock Buffers Switching Characteristics**
|**Symbol**|**Description**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Units**|
|---|---|---|---|---|---|---|---|
|||**0.90V**|**0.85V**||**0.72V**|||
|||**-3**|**-2**|**-1**|**-2**|**-1**||
|**Global Clock Switching Characteristics (Including**||**BUFGCTRL)**||||||
|FMAX|Maximum frequency of a global clock tree<br>(BUFG).|891|775|667|725|667|MHz|
|**Global Clock Buffer with Input Divide Capability (BUFGCE_DIV)**||||||||
|FMAX|Maximum frequency of a global clock buffer with<br>input divide capability (BUFGCE_DIV).|891|775|667|725|667|MHz|
|**Global Clock Buffer with Clock Enable (BUFGCE)**||||||||
|FMAX|Maximum frequency of a global clock buffer with<br>clock enable (BUFGCE).|891|775|667|725|667|MHz|
|**Leaf Clock Buffer with Clock Enable (BUFCE_LEAF)**||||||||
|FMAX|Maximum frequency of a leaf clock buffer with<br>clock enable (BUFCE_LEAF).|891|775|667|725|667|MHz|
|**GTH or GTY Clock Buffer with Clock Enable and Clock Input Divide Capability (BUFG_GT)**||||||||
|FMAX|Maximum frequency of a serial transceiver clock<br>buffer with clock enable and clock input divide<br>capability.|512|512|512|512|512|MHz|
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**Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
## **MMCM Switching Characteristics**
_Table 38:_ **MMCM Specification**
|**Symbol**|**Description**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Units**|
|---|---|---|---|---|---|---|---|
|||**0.90V**|**0.85V**||**0.72V**|||
|||**-3**|**-2**|**-1**|**-2**|**-1**||
|MMCM_FINMAX|Maximum input clock frequency.|1066|933|800|933|800|MHz|
|MMCM_FINMIN|Minimum input clock frequency.|10|10|10|10|10|MHz|
|MMCM_FINJITTER|Maximum input clock period jitter.|< 20% of clock input period or 1 ns Max||||||
|MMCM_FINDUTY|Input duty cycle range: 10–49 MHz.|25–75|||||%|
||Input duty cycle range: 50–199 MHz.|30–70|||||%|
||Input duty cycle range: 200–399 MHz.|35–65|||||%|
||Input duty cycle range: 400–499 MHz.|40–60|||||%|
||Input duty cycle range: >500 MHz.|45–55|||||%|
|MMCM_FMIN_PSCLK|Minimum dynamic phase shift clock<br>frequency.|0.01|0.01|0.01|0.01|0.01|MHz|
|MMCM_FMAX_PSCLK|Maximum dynamic phase shift clock<br>frequency.|550|500|450|500|450|MHz|
|MMCM_FVCOMIN|Minimum MMCM VCO frequency.|800|800|800|800|800|MHz|
|MMCM_FVCOMAX|Maximum MMCM VCO frequency.|1600|1600|1600|1600|1600|MHz|
|MMCM_FBANDWIDTH|Low MMCM bandwidth at typical.(1)|1.00|1.00|1.00|1.00|1.00|MHz|
||High MMCM bandwidth at typical.(1)|4.00|4.00|4.00|4.00|4.00|MHz|
|MMCM_TSTATPHAOFFSET|Static phase offset of the MMCM<br>outputs.(2)|0.12|0.12|0.12|0.12|0.12|ns|
|MMCM_TOUTJITTER|MMCM output jitter.|Note 3||||||
|MMCM_TOUTDUTY|MMCM output clock duty cycle<br>precision.(4)|0.165|0.20|0.20|0.20|0.20|ns|
|MMCM_TLOCKMAX|MMCM maximum lock time for<br>MMCM_FPFDMIN.|100|100|100|100|100|µs|
|MMCM_FOUTMAX|MMCM maximum output frequency.|891|775|667|725|667|MHz|
|MMCM_FOUTMIN|MMCM minimum output frequency.(4)(5)|6.25|6.25|6.25|6.25|6.25|MHz|
|MMCM_TEXTFDVAR|External clock feedback variation.|< 20% of clock input period or 1 ns Max||||||
|MMCM_RSTMINPULSE|Minimum reset pulse width.|5.00|5.00|5.00|5.00|5.00|ns|
|MMCM_FPFDMAX|Maximum frequency at the phase<br>frequency detector.|550|500|450|500|450|MHz|
|MMCM_FPFDMIN|Minimum frequency at the phase<br>frequency detector.|10|10|10|10|10|MHz|
|MMCM_TFBDELAY|Maximum delay in the feedback path.|5 ns Max or one clock cycle||||||
|MMCM_FDPRCLK_MAX|Maximum DRP clock frequency.|250|250|250|250|250|MHz|
## **Notes:**
1. The MMCM does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies.
2. The static offset is measured between any MMCM outputs with identical phase.
3. Values for this parameter are available in the Clocking Wizard.
4. Includes global clock buffer.
5. Calculated as FVCO/128 assuming output duty cycle is 50%.
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**Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
## **PLL Switching Characteristics**
_Table 39:_ **PLL Specification[(1)]**
|**Symbol**|**Description**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Units**|
|---|---|---|---|---|---|---|---|
|||**0.90V**|**0.85V**||**0.72V**|||
|||**-3**|**-2**|**-1**|**-2**|**-1**||
|PLL_FINMAX|Maximum input clock frequency.|1066|933|800|933|800|MHz|
|PLL_FINMIN|Minimum input clock frequency.|70|70|70|70|70|MHz|
|PLL_FINJITTER|Maximum input clock period jitter.|< 20% of clock input period or 1 ns Max||||||
|PLL_FINDUTY|Input duty cycle range: 70–399 MHz.|35–65|||||%|
||Input duty cycle range: 400–499 MHz.|40–60|||||%|
||Input duty cycle range: >500 MHz.|45–55|||||%|
|PLL_FVCOMIN|Minimum PLL VCO frequency.|750|750|750|750|750|MHz|
|PLL_FVCOMAX|Maximum PLL VCO frequency.|1500|1500|1500|1500|1500|MHz|
|PLL_TSTATPHAOFFSET|Static phase offset of the PLL outputs.(2)|0.12|0.12|0.12|0.12|0.12|ns|
|PLL_TOUTJITTER|PLL output jitter.|Note 3||||||
|PLL_TOUTDUTY|PLL CLKOUT0, CLKOUT0B, CLKOUT1,<br>CLKOUT1B duty-cycle precision.(4)|0.165|0.20|0.20|0.20|0.20|ns|
|PLL_TLOCKMAX|PLL maximum lock time.|100|||||µs|
|PLL_FOUTMAX|PLL maximum output frequency at<br>CLKOUT0, CLKOUT0B, CLKOUT1,<br>CLKOUT1B.|891|775|667|725|667|MHz|
||PLL maximum output frequency at<br>CLKOUTPHY.|2667|2667|2400|2400|2133|MHz|
|PLL_FOUTMIN|PLL minimum output frequency at<br>CLKOUT0, CLKOUT0B, CLKOUT1,<br>CLKOUT1B.(5)|5.86|5.86|5.86|5.86|5.86|MHz|
||PLL minimum output frequency at<br>CLKOUTPHY.|2 x VCO mode: 1500,<br>1 x VCO mode: 750<br>0.5 x VCO mode: 375|||||MHz|
|PLL_RSTMINPULSE|Minimum reset pulse width.|5.00|5.00|5.00|5.00|5.00|ns|
|PLL_FPFDMAX|Maximum frequency at the phase<br>frequency detector.|667.5|667.5|667.5|667.5|667.5|MHz|
|PLL_FPFDMIN|Minimum frequency at the phase<br>frequency detector.|70|70|70|70|70|MHz|
|PLL_FBANDWIDTH|PLL bandwidth at typical.|14|14|14|14|14|MHz|
|PLL_FDPRCLK_MAX|Maximum DRP clock frequency|250|250|250|250|250|MHz|
## **Notes:**
1. The PLL does not filter typical spread-spectrum input clocks because they are usually far below the loop filter frequencies.
2. The static offset is measured between any PLL outputs with identical phase.
3. Values for this parameter are available in the Clocking Wizard.
4. Includes global clock buffer.
5. Calculated as FVCO/128 assuming output duty cycle is 50%.
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## **Device Pin-to-Pin Output Parameter Guidelines**
The pin-to-pin numbers in Table 40 through Table 42 are based on the clock root placement in the center of the device. The actual pin-to-pin values will vary if the root placement selected is different. Consult the Vivado Design Suite timing report for the actual pin-to-pin values.
_Table 40:_ **Global Clock Input to Output Delay Without MMCM (Near Clock Region)**
|**Symbol**|**Description**|**Device**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Units**|
|---|---|---|---|---|---|---|---|---|
||||**0.90V**|**0.85V**||**0.72V**|||
||||**-3**|**-2**|**-1**|**-2**|**-1**||
|**SSTL15 Global Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate,****_without_ MMCM.**|||||||||
|TICKOF|Global clock input and output<br>flip-flop_without_MMCM (near clock<br>region).|XCKU3P|4.30|5.09|5.48|5.68|5.99|ns|
|||XCKU5P|4.30|5.09|5.48|5.68|5.99|ns|
|||XCKU9P|5.00|5.91|6.35|6.66|7.09|ns|
|||XCKU11P|5.82|6.96|7.61|7.19|8.36|ns|
|||XCKU13P|5.15|6.09|6.55|6.90|7.38|ns|
|||XCKU15P|5.72|6.90|7.40|7.62|8.07|ns|
## **Notes:**
1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible I/O and CLB flip-flops are clocked by the global clock net.
_Table 41:_ **Global Clock Input to Output Delay Without MMCM (Far Clock Region)**
|**Symbol**|**Description**|**Device**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Units**|
|---|---|---|---|---|---|---|---|---|
||||**0.90V**|**0.85V**||**0.72V**|||
||||**-3**|**-2**|**-1**|**-2**|**-1**||
|**SSTL15 Global Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate,****_without_ MMCM.**|||||||||
|TICKOF_FAR|Global clock input and output<br>flip-flop_without_MMCM (far clock<br>region).|XCKU3P|4.46|5.30|5.70|5.88|6.23|ns|
|||XCKU5P|4.46|5.30|5.70|5.88|6.23|ns|
|||XCKU9P|5.38|6.49|6.97|7.14|7.59|ns|
|||XCKU11P|6.18|7.41|8.11|7.66|8.99|ns|
|||XCKU13P|5.38|6.49|6.96|7.19|7.71|ns|
|||XCKU15P|6.21|7.53|8.07|8.36|8.90|ns|
## **Notes:**
1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible I/O and CLB flip-flops are clocked by the global clock net.
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_Table 42:_ **Global Clock Input to Output Delay With MMCM**
|**Symbol**|**Description**|**Device**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Units**|
|---|---|---|---|---|---|---|---|---|
||||**0.90V**|**0.85V**||**0.72V**|||
||||**-3**|**-2**|**-1**|**-2**|**-1**||
|**SSTL15 Global Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with MMCM.**|||||||||
|TICKOFMMCMCC|Global clock input and output<br>flip-flop_with_MMCM.|XCKU3P|1.98|1.98|2.17|2.66|2.66|ns|
|||XCKU5P|1.98|1.98|2.17|2.66|2.66|ns|
|||XCKU9P|2.15|2.15|2.36|2.86|2.86|ns|
|||XCKU11P|2.64|2.64|2.96|3.25|3.55|ns|
|||XCKU13P|2.18|2.18|2.38|2.88|2.90|ns|
|||XCKU15P|2.44|2.44|2.66|3.19|3.19|ns|
## **Notes:**
1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible I/O and CLB flip-flops are clocked by the global clock net.
2. MMCM output jitter is already included in the timing calculation.
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**Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
## **Device Pin-to-Pin Input Parameter Guidelines**
The pin-to-pin numbers in Table 43 and Table 44 are based on the clock root placement in the center of the device. The actual pin-to-pin values will vary if the root placement selected is different. Consult the Vivado Design Suite timing report for the actual pin-to-pin values.
_Table 43:_ **Global Clock Input Setup and Hold With 3.3V HD I/O without MMCM**
|**Symbol**|**Description**|**Description**|**Device**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Units**|
|---|---|---|---|---|---|---|---|---|---|
|||||**0.90V**|**0.85V**||**0.72V**|||
|||||**-3**|**-2**|**-1**|**-2**|**-1**||
|**Input Setup and Hold Time Relative to Global Clock Input Signal using SSTL15 Standard.(1)(2)(3)**||||||||||
|TPSFD_KU3P|Global clock input and<br>input flip-flop (or latch)<br>without MMCM.|<br>Setup|XCKU3P|1.40|2.28|2.38|2.56|2.65|ns|
|TPHFD_KU3P||<br>Hold||–0.36|–0.36|–0.36|–0.15|–0.15|ns|
|TPSFD_KU5P||Setup|XCKU5P|1.40|2.28|2.38|2.56|2.65|ns|
|TPHFD_KU5P||Hold||–0.36|–0.36|–0.36|–0.15|–0.15|ns|
|TPSFD_KU9P||Setup|XCKU9P|0.96|1.79|1.86|1.93|2.02|ns|
|TPHFD_KU9P||Hold||–0.05|–0.05|–0.05|0.27|0.42|ns|
|TPSFD_KU11P||Setup|XCKU11P|1.28|2.01|2.07|2.59|2.59|ns|
|TPHFD_KU11P||Hold||–0.29|–0.29|–0.29|–0.09|0.19|ns|
|TPSFD_KU13P||Setup|XCKU13P|0.96|1.79|1.85|1.92|2.01|ns|
|TPHFD_KU13P||Hold||–0.04|–0.04|–0.04|0.27|0.43|ns|
|TPSFD_KU15P||Setup|XCKU15P|1.41|2.29|2.38|2.57|2.65|ns|
|TPHFD_KU15P||Hold||–0.38|–0.38|–0.38|–0.19|–0.19|ns|
## **Notes:**
1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global clock input signal using the slowest process, slowest temperature, and slowest voltage. Hold time is measured relative to the global clock input signal using the fastest process, fastest temperature, and fastest voltage.
2. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible I/O and CLB flip-flops are clocked by the global clock net.
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
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_Table 44:_ **Global Clock Input Setup and Hold With MMCM**
|**Symbol**|**Description**|**Description**|**Device**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Units**|
|---|---|---|---|---|---|---|---|---|---|
|||||**0.90V**|**0.85V**||**0.72V**|||
|||||**-3**|**-2**|**-1**|**-2**|**-1**||
|**Input Setup and Hold Time Relative to Global Clock Input Signal using SSTL15 Standard.(1)(2)(3)**||||||||||
|TPSMMCMCC_KU3P|Global clock input and<br>input flip-flop (or latch)<br>with MMCM.|<br>Setup|XCKU3P|2.02|2.04|2.16|2.31|2.48|ns|
|TPHMMCMCC_KU3P||<br>Hold||–0.17|–0.17|–0.17|0.11|0.11|ns|
|TPSMMCMCC_KU5P||Setup|XCKU5P|2.02|2.04|2.16|2.31|2.48|ns|
|TPHMMCMCC_KU5P||Hold||–0.17|–0.17|–0.17|0.11|0.11|ns|
|TPSMMCMCC_KU9P||Setup|XCKU9P|1.97|2.00|2.12|2.26|2.44|ns|
|TPHMMCMCC_KU9P||Hold||–0.11|–0.11|–0.11|0.16|0.18|ns|
|TPSMMCMCC_KU11P||Setup|XCKU11P|2.08|2.08|2.23|2.59|2.75|ns|
|TPHMMCMCC_KU11P||Hold||–0.05|–0.05|0.04|0.35|0.74|ns|
|TPSMMCMCC_KU13P||Setup|XCKU13P|1.96|1.99|2.12|2.26|2.44|ns|
|TPHMMCMCC_KU13P||Hold||–0.10|–0.10|–0.10|0.17|0.19|ns|
|TPSMMCMCC_KU15P||Setup|XCKU15P|1.89|1.89|2.03|2.36|2.55|ns|
|TPHMMCMCC_KU15P||Hold||–0.16|–0.16|–0.16|0.31|0.34|ns|
## **Notes:**
1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global clock input signal using the slowest process, slowest temperature, and slowest voltage. Hold time is measured relative to the global clock input signal using the fastest process, fastest temperature, and fastest voltage.
2. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible I/O and CLB flip-flops are clocked by the global clock net.
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
_Table 45:_ **Sampling Window**
|**Description**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Units**|
|---|---|---|---|---|---|---|
||**0.90V**|**0.85V**||**0.72V**|||
||**-3**|**-2**|**-1**|**-2**|**-1**||
|TSAMP_BUFG(1)|510|610|610|610|610|ps|
|TSAMP_NATIVE_DPA|100|100|125|125|150|ps|
|TSAMP_NATIVE_BISC|60|60|85|85|110|ps|
## **Notes:**
1. This parameter indicates the total sampling error of the Kintex UltraScale+ FPGA DDR input registers, measured across voltage, temperature, and process. The characterization methodology uses the MMCM to capture the DDR input registers’ edges of operation. These measurements include: CLK0 MMCM jitter, MMCM accuracy (phase offset), and MMCM phase shift resolution. These measurements do not include package or clock tree skew.
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**Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
## **Package Parameter Guidelines**
The parameters in this section provide the necessary values for calculating timing budgets for clock transmitter and receiver data-valid windows.
_Table 46:_ **Package Skew**
|**Symbol**|**Description**|**Device**|**Package**|**Value**|**Units**|
|---|---|---|---|---|---|
|PKGSKEW|Package Skew|XCKU3P|SFVB784|75|ps|
||||FFVA676|136|ps|
||||FFVB676|69|ps|
||||FFVD900|179|ps|
|||XCKU5P|SFVB784|75|ps|
||||FFVA676|136|ps|
||||FFVB676|69|ps|
||||FFVD900|179|ps|
|||XCKU9P|FFVE900|212|ps|
|||XCKU11P|FFVD900||ps|
||||FFVA1156||ps|
||||FFVE1517||ps|
|||XCKU13P|FFVE900|197|ps|
|||XCKU15P|FFVA1156|203|ps|
||||FFVE1517|167|ps|
||||FFVA1760|191|ps|
||||FFVE1760|172|ps|
## **Notes:**
1. These values represent the worst-case skew between any two SelectIO resources in the package: shortest delay to longest delay from die pad to ball.
2. Package delay information is available for these device/package combinations. This information can be used to deskew the package.
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**Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
## **GTH Transceiver Specifications**
The _UltraScale Architecture and Product Overview_ (DS890) lists the Kintex UltraScale+ FPGAs that include the GTH transceivers.
## **GTH Transceiver DC Input and Output Levels**
Table 47 summarizes the DC specifications of the GTH transceivers in the Kintex UltraScale+ FPGAs. Consult the _UltraScale Architecture GTH Transceiver User Guide_ (UG576) for further information.
_Table 47:_ **GTH Transceiver DC Specifications**
|**Symbol**|**DC Parameter**|**Conditions**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|DVPPIN|Differential peak-to-peak input<br>voltage (external AC coupled).|>10.3125 Gb/s|150|–|1250|mV|
|||6.6 Gb/s to 10.3125 Gb/s|150|–|1250|mV|
|||≤6.6 Gb/s|150|–|2000|mV|
|VIN|Single-ended input voltage.<br>Voltage measured at the pin<br>referenced to GND.|DC coupled<br>VMGTAVTT = 1.2V|–400|–|VMGTAVTT|mV|
|VCMIN|Common mode input voltage.|DC coupled<br>VMGTAVTT = 1.2V|–|2/3 VMGTAVTT|–|mV|
|DVPPOUT|Differential peak-to-peak output<br>voltage.(1)|Transmitter output swing<br>is set to`11111`|800|–|–|mV|
|VCMOUTDC|Common mode output voltage:<br>DC coupled (equation based).|When remote RX is<br>terminated to GND|VMGTAVTT/2 – DVPPOUT/4|||mV|
|||When remote RX<br>termination is floating|VMGTAVTT– DVPPOUT/2|||mV|
|||When remote RX is<br>terminated to VRX_TERM(2)|VMGTAVTT<br>DVPPOUT<br>4<br>----------------------<br>–<br>VMGTAVTT<br>VRX_TERM<br>–<br>2<br>-----------------------------------------------------**-**<br><br><br><br><br>–|||mV|
|VCMOUTAC|Common mode output voltage: AC coupled (equation based).||VMGTAVTT– DVPPOUT/2|||mV|
|RIN|Differential input resistance.||–|100|–|Ω|
|ROUT|Differential output resistance.||–|100|–|Ω|
|TOSKEW|Transmitter output pair (TXP and TXN) intra-pair skew<br>(All packages).||–|–|10|ps|
|CEXT|Recommended external AC coupling capacitor.(3)||–|100|–|nF|
## **Notes:**
1. The output swing and pre-emphasis levels are programmable using the attributes discussed in the _UltraScale Architecture GTH Transceiver User Guide_ (UG576), and can result in values lower than reported in this table.
2. VRX_TERM is the remote RX termination voltage.
3. Other values can be used as appropriate to conform to specific protocols and standards.
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**Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
**==> picture [498 x 88] intentionally omitted <==**
**----- Start of picture text -----**<br>
+V P<br>Single-Ended<br>Peak-to-Peak<br>N Voltage<br>0<br>X16653-101316<br>**----- End of picture text -----**<br>
_Figure 3:_ **Single-Ended Peak-to-Peak Voltage**
**==> picture [390 x 92] intentionally omitted <==**
**----- Start of picture text -----**<br>
+V<br>Differential<br>0 Peak-to-Peak<br>Voltage<br>–V P–N<br>Differential peak-to-peak voltage = (Single-ended peak-to-peak voltage) x 2<br>X16639-101316<br>**----- End of picture text -----**<br>
_Figure 4:_ **Differential Peak-to-Peak Voltage**
Table 48 and Table 49 summarize the DC specifications of the GTH transceivers input and output clocks in Kintex UltraScale+ FPGAs. Consult the _UltraScale Architecture GTH Transceiver User Guide_ (UG576) for further information.
_Table 48:_ **GTH Transceiver Clock DC Input Level Specification**
|**Symbol**|**DC Parameter**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|
|VIDIFF|Differential peak-to-peak input voltage.|250|–|2000|mV|
|RIN|Differential input resistance.|–|100|–|Ω|
|CEXT|Required external AC coupling capacitor.|–|10|–|nF|
_Table 49:_ **GTH Transceiver Clock Output Level Specification**
|**Symbol**|**Description**|**Conditions**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|VOL|Output Low voltage for P and N.|RT = 100Ωacross P and N signals|100|–|330|mV|
|VOH|Output High voltage for P and N.|RT = 100Ωacross P and N signals|500|–|700|mV|
|VDDOUT|Differential output voltage.<br>(P–N), P = High<br>(N–P), N = High|RT = 100Ωacross P and N signals|300|–|430|mV|
|VCMOUT|Common mode voltage.|RT = 100Ωacross P and N signals|300|–|500|mV|
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**Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
## **GTH Transceiver Switching Characteristics**
Consult the _UltraScale Architecture GTH Transceiver User Guide_ (UG576) for further information.
_Table 50:_ **GTH Transceiver Performance**
|**Symbol**|**Description **|**Output**<br>**Divider**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||||**0.90V**||**0.85V**||||**0.72V**|||||
||||**-3**||**-2**||**-1**||**-2**||**-1**|||
|FGTHMAX|GTH maximum line rate.||16.375||16.375||12.5||12.5||10.3125||Gb/s|
|FGTHMIN|GTH minimum|line rate.|0.5||0.5||0.5||0.5||0.5||Gb/s|
||||Min|Max|Min|Max|Min|Max|Min|Max|Min|Max||
|FGTHCRANGE|CPLL line rate<br>range.(1)|1|4|12.5|4|12.5|4|8.5|4|8.5|4|8.5|Gb/s|
|||<br>2|2|6.25|2|6.25|2|4.25|2|4.25|2|4.25|Gb/s|
|||<br>4|1|3.125|1|3.125|1|2.125|1|2.125|1|2.125|Gb/s|
|||8|0.5|1.5625|0.5|1.5625|0.5|1.0625|0.5|1.0625|0.5|1.0625|Gb/s|
|||16|N/A||||||||||Gb/s|
||||Min|Max|Min|Max|Min|Max|Min|Max|Min|Max||
|FGTHQRANGE1|QPLL0 line<br>rate range.(2)|1|9.8|16.375|9.8|16.375|9.8|12.5|9.8|12.5|9.8|10.3125|Gb/s|
|||2|4.9|8.1875|4.9|8.1875|4.9|8.15|4.9|8.1875|4.9|8.15|Gb/s|
|||4|2.45|4.0938|2.45|4.0938|2.45|4.075|2.45|4.0938|2.45|4.075|Gb/s|
|||8|1.225|2.0469|1.225|2.0469|1.225|2.0375|1.225|2.0469|1.225|2.0375|Gb/s|
|||16|0.6125|1.0234|0.6125|1.0234|0.6125|1.0188|0.6125|1.0234|0.6125|1.0188|Gb/s|
||||Min|Max|Min|Max|Min|Max|Min|Max|Min|Max||
|FGTHQRANGE2|QPLL1 line<br>rate range.(3)|1|8.0|13|8.0|13|8.0|12.5|8.0|12.5|8.0|10.3125|Gb/s|
|||2|4.0|6.5|4.0|6.5|4.0|6.5|4.0|6.5|4.0|6.5|Gb/s|
|||4|2.0|3.25|2.0|3.25|2.0|3.25|2.0|3.25|2.0|3.25|Gb/s|
|||8|1.0|1.625|1.0|1.625|1.0|1.625|1.0|1.625|1.0|1.625|Gb/s|
|||16|0.5|0.8125|0.5|0.8125|0.5|0.8125|0.5|0.8125|0.5|0.8125|Gb/s|
||||Min|Max|Min|Max|Min|Max|Min|Max|Min|Max||
|FCPLLRANGE|CPLL frequency range.||2|6.25|2|6.25|2|4.25|2|4.25|2|4.25|GHz|
|FQPLL0RANGE|QPLL0 frequency<br>range.||9.8|16.375|9.8|16.375|9.8|16.375|9.8|16.375|9.8|16.375|GHz|
|FQPLL1RANGE|QPLL1 frequency<br>range.||8|13|8|13|8|13|8|13|8|13|GHz|
## **Notes:**
1. The values listed are the rounded results of the calculated equation (2 x CPLL_Frequency)/Output_Divider.
2. The values listed are the rounded results of the calculated equation (QPLL0_Frequency)/Output_Divider.
3. The values listed are the rounded results of the calculated equation (QPLL1_Frequency)/Output_Divider.
_Table 51:_ **GTH Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics**
|**Symbol**|**Description**|**All Speed Grades**|**Units**|
|---|---|---|---|
|FGTHDRPCLK|GTHDRPCLK maximum frequency.|250|MHz|
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**Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 52:_ **GTH Transceiver Reference Clock Switching Characteristics**
|**Symbol**|**Description**|**Conditions**|**All Speed Grades**|**All Speed Grades**|**All Speed Grades**|**Units**|
|---|---|---|---|---|---|---|
||||**Min**|**Typ**|**Max**||
|FGCLK|Reference clock frequency range.||60|–|820|MHz|
|TRCLK|Reference clock rise time.|20% – 80%|–|200|–|ps|
|TFCLK|Reference clock fall time.|80% – 20%|–|200|–|ps|
|TDCREF|Reference clock duty cycle.|Transceiver PLL only|40|50|60|%|
_Table 53:_ **GTH Transceiver Reference Clock Oscillator Selection Phase Noise Mask**
|**Symbol**|**Description**|**Offset**<br>**Frequency**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|QPLLREFCLKMASK(1)(2)|QPLL0/QPLL1 reference clock select<br>phase noise mask at<br>REFCLK frequency = 312.5 MHz.|10 kHz|–|–|–105|dBc/Hz|
|||100 kHz|–|–|–124||
|||1 MHz|–|–|–130||
|CPLLREFCLKMASK(1)(2)|CPLL reference clock select phase noise<br>mask at REFCLK frequency = 312.5 MHz.|10 kHz|–|–|–105|dBc/Hz|
|||100 kHz|–|–|–124||
|||1 MHz|–|–|–130||
|||50 MHz|–|–|–140||
## **Notes:**
1. For reference clock frequencies other than 312.5 MHz, adjust the phase-noise mask values by 20 x Log(N/312.5) where N is the new reference clock frequency in MHz.
2. This reference clock phase-noise mask is superseded by any reference clock phase-noise mask that is specified in a supported protocol, e.g., PCIe.
_Table 54:_ **GTH Transceiver PLL/Lock Time Adaptation**
|**Symbol**|**Description**|**Conditions**|**All Speed Grades**|**All Speed Grades**|**All Speed Grades**|**Units**|
|---|---|---|---|---|---|---|
||||**Min**|**Typ**|**Max**||
|TLOCK|Initial PLL lock.||–|–|1|ms|
|TDLOCK|Clock recovery phase acquisition and<br>adaptation time for decision<br>feedback equalizer (DFE).|After the PLL is locked to<br>the reference clock, this is<br>the time it takes to lock<br>the clock data recovery<br>(CDR) to the data present<br>at the input.|–|50,000|37 x 106|UI|
||Clock recovery phase acquisition and<br>adaptation time for low-power mode<br>(LPM) when the DFE is disabled.||–|50,000|2.3 x 106|UI|
_Table 55:_ **GTH Transceiver User Clock Switching Characteristics[(1)]**
|**Symbol**|**Description**|**Data Width Conditions**<br>**(Bit)**|**Data Width Conditions**<br>**(Bit)**|**Speed Grade, Temperature Ranges, and**<br>**VCCINTOperating Voltages**|**Speed Grade, Temperature Ranges, and**<br>**VCCINTOperating Voltages**|**Speed Grade, Temperature Ranges, and**<br>**VCCINTOperating Voltages**|**Speed Grade, Temperature Ranges, and**<br>**VCCINTOperating Voltages**|**Speed Grade, Temperature Ranges, and**<br>**VCCINTOperating Voltages**|**Units**|
|---|---|---|---|---|---|---|---|---|---|
|||||**0.90V**|**0.85V**||**0.72V**|||
|||**Internal**<br>**Logic**|**Interconnect**<br>**Logic**|<br>**-3(2)**|**-2(2)(3) **|**-1(4)(5)**|**-2(3)**|**-1(3)(5)**||
|FTXOUTPMA|TXOUTCLK maximum frequency sourced<br>from OUTCLKPMA.|||511.719|511.719|390.625|390.625|322.266|MHz|
|FRXOUTPMA|RXOUTCLK maximum frequency sourced<br>from OUTCLKPMA.|||511.719|511.719|390.625|390.625|322.266|MHz|
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_Table 55:_ **GTH Transceiver User Clock Switching Characteristics[(1)]** _**(Cont’d)**_
|**Symbol**|**Description**|**Data Width Conditions**<br>**(Bit)**|**Data Width Conditions**<br>**(Bit)**|**Speed Grade, Temperature Ranges, and**<br>**VCCINTOperating Voltages**|**Speed Grade, Temperature Ranges, and**<br>**VCCINTOperating Voltages**|**Speed Grade, Temperature Ranges, and**<br>**VCCINTOperating Voltages**|**Speed Grade, Temperature Ranges, and**<br>**VCCINTOperating Voltages**|**Speed Grade, Temperature Ranges, and**<br>**VCCINTOperating Voltages**|**Units**|
|---|---|---|---|---|---|---|---|---|---|
|||||**0.90V**|**0.85V**||**0.72V**|||
|||**Internal**<br>**Logic**|**Interconnect**<br>**Logic**|<br>**-3(2)**|**-2(2)(3) **|**-1(4)(5)**|**-2(3)**|**-1(3)(5)**||
|FTXOUTPROGDIV|TXOUTCLK maximum frequency sourced<br>from TXPROGDIVCLK.|||511.719|511.719|511.719|511.719|511.719|MHz|
|FRXOUTPROGDIV|RXOUTCLK maximum frequency sourced<br>from RXPROGDIVCLK.|||511.719|511.719|511.719|511.719|511.719|MHz|
|FTXIN|TXUSRCLK(6)<br>maximum<br>frequency|16|16, 32|511.719|511.719|390.625|390.625|322.266|MHz|
|||32|32, 64|511.719|511.719|390.625|390.625|322.266|MHz|
|||20|20, 40|409.375|409.375|312.500|312.500|257.813|MHz|
|||40|40, 80|409.375|409.375|312.500|312.500|257.813|MHz|
|FRXIN|RXUSRCLK(6)<br>maximum<br>frequency|16|16, 32|511.719|511.719|390.625|390.625|322.266|MHz|
|||32|32, 64|511.719|511.719|390.625|390.625|322.266|MHz|
|||20|20, 40|409.375|409.375|312.500|312.500|257.813|MHz|
|||40|40, 80|409.375|409.375|312.500|312.500|257.813|MHz|
|FTXIN2|TXUSRCLK2(6)<br>maximum<br>frequency|16|16|511.719|511.719|390.625|390.625|322.266|MHz|
|||16|32|255.859|255.859|195.313|195.313|161.133|MHz|
|||32|32|511.719|511.719|390.625|390.625|322.266|MHz|
|||32|64|255.859|255.859|195.313|195.313|161.133|MHz|
|||20|20|409.375|409.375|312.500|312.500|257.813|MHz|
|||20|40|204.688|204.688|156.250|156.250|128.906|MHz|
|||40|40|409.375|409.375|312.500|312.500|257.813|MHz|
|||40|80|204.688|204.688|156.250|156.250|128.906|MHz|
|FRXIN2|RXUSRCLK2(6)<br>maximum<br>frequency|16|16|511.719|511.719|390.625|390.625|322.266|MHz|
|||16|32|255.859|255.859|195.313|195.313|161.133|MHz|
|||32|32|511.719|511.719|390.625|390.625|322.266|MHz|
|||32|64|255.859|255.859|195.313|195.313|161.133|MHz|
|||20|20|409.375|409.375|312.500|312.500|257.813|MHz|
|||20|40|204.688|204.688|156.250|156.250|128.906|MHz|
|||40|40|409.375|409.375|312.500|312.500|257.813|MHz|
|||40|80|204.688|204.688|156.250|156.250|128.906|MHz|
## **Notes:**
1. Clocking must be implemented as described in the _UltraScale Architecture GTH Transceiver User Guide_ (UG576).
2. For speed grades -3E, -2E, and -2I, a 16-bit and 20-bit internal data path can only be used for line rates less than 8.1875 Gb/s.
3. For speed grade -2LE, a 16-bit and 20-bit internal data path can only be used for line rates less than 8.1875 Gb/s when VCCINT = 0.85V or 6.25 Gb/s when VCCINT = 0.72V.
4. For speed grades -1E and -1I, a 16-bit and 20-bit internal data path can only be used for line rates less than 6.25 Gb/s. 5. For speed grade -1LI, a 16-bit and 20-bit internal data path can only be used for line rates less than 6.25 Gb/s when VCCINT = 0.85V or 5.15625 Gb/s when VCCINT = 0.72V.
6. When the gearbox is used, these maximums refer to the XCLK. For more information, see the _Valid Data Width Combinations for TX Asynchronous Gearbox_ table in the _UltraScale Architecture GTH Transceiver User Guide_ (UG576).
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_Table 56:_ **GTH Transceiver Transmitter Switching Characteristics**
|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|FGTHTX|Serial data rate range||0.500|–|FGTHMAX|Gb/s|
|TRTX|TX rise time|20%–80%|–|21|–|ps|
|TFTX|TX fall time|80%–20%|–|21|–|ps|
|TLLSKEW|TX lane-to-lane skew(1)||–|–|500.00|ps|
|TJ16.375|Total jitter(2)(4)|16.375 Gb/s|–|–|0.28|UI|
|DJ16.375|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ15.0|Total jitter(2)(4)|15.0 Gb/s|–|–|0.28|UI|
|DJ15.0|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ14.1|Total jitter(2)(4)|14.1 Gb/s|–|–|0.28|UI|
|DJ14.1|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ14.1|Total jitter(2)(4)|14.025 Gb/s|–|–|0.28|UI|
|DJ14.1|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ13.1|Total jitter(2)(4)|13.1 Gb/s|–|–|0.28|UI|
|DJ13.1|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ12.5_QPLL|Total jitter(2)(4)|12.5 Gb/s|–|–|0.28|UI|
|DJ12.5_QPLL|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ12.5_CPLL|Total jitter(3)(4)|12.5 Gb/s|–|–|0.33|UI|
|DJ12.5_CPLL|Deterministic jitter(3)(4)||–|–|0.17|UI|
|TJ11.3_QPLL|Total jitter(2)(4)|11.3 Gb/s|–|–|0.28|UI|
|DJ11.3_QPLL|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ10.3125_QPLL|Total jitter(2)(4)|10.3125 Gb/s|–|–|0.28|UI|
|DJ10.3125_QPLL|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ10.3125_CPLL|Total jitter(3)(4)|10.3125 Gb/s|–|–|0.33|UI|
|DJ10.3125_CPLL|Deterministic jitter(3)(4)||–|–|0.17|UI|
|TJ9.953_QPLL|Total jitter(2)(4)|9.953 Gb/s|–|–|0.28|UI|
|DJ9.953_QPLL|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ9.953_CPLL|Total jitter(3)(4)|9.953 Gb/s|–|–|0.33|UI|
|DJ9.953_CPLL|Deterministic jitter(3)(4)||–|–|0.17|UI|
|TJ8.0|Total jitter(3)(4)|8.0 Gb/s|–|–|0.32|UI|
|DJ8.0|Deterministic jitter(3)(4)||–|–|0.17|UI|
|TJ6.6|Total jitter(3)(4)|6.6 Gb/s|–|–|0.30|UI|
|DJ6.6|Deterministic jitter(3)(4)||–|–|0.15|UI|
|TJ5.0|Total jitter(3)(4)|5.0 Gb/s|–|–|0.30|UI|
|DJ5.0|Deterministic jitter(3)(4)||–|–|0.15|UI|
|TJ4.25|Total jitter(3)(4)|4.25 Gb/s|–|–|0.30|UI|
|DJ4.25|Deterministic jitter(3)(4)||–|–|0.15|UI|
|TJ4.0|Total jitter(3)(4)|4.0 Gb/s|–|–|0.32|UI|
|DJ4.0|Deterministic jitter(3)(4)||–|–|0.16|UI|
|TJ3.20|Total jitter(3)(4)|3.20 Gb/s(5)|–|–|0.20|UI|
|DJ3.20|Deterministic jitter(3)(4)||–|–|0.10|UI|
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_Table 56:_ **GTH Transceiver Transmitter Switching Characteristics** _**(Cont’d)**_
|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|TJ2.5|Total jitter(3)(4)|2.5 Gb/s(6)|–|–|0.20|UI|
|DJ2.5|Deterministic jitter(3)(4)||–|–|0.10|UI|
|TJ1.25|Total jitter(3)(4)|1.25 Gb/s(7)|–|–|0.15|UI|
|DJ1.25|Deterministic jitter(3)(4)||–|–|0.06|UI|
|TJ500|Total jitter(3)(4)|500 Mb/s(8)|–|–|0.10|UI|
|DJ500|Deterministic jitter(3)(4)||–|–|0.03|UI|
## **Notes:**
1. Using same REFCLK input with TX phase alignment enabled for up to four consecutive transmitters (one fully populated GTH Quad) at the maximum line rate.
2. Using QPLL_FBDIV = 40, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations.
3. Using CPLL_FBDIV = 2, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations.
4. All jitter values are based on a bit-error ratio of 10[-12] .
5. CPLL frequency at 3.2 GHz and TXOUT_DIV = 2.
6. CPLL frequency at 2.5 GHz and TXOUT_DIV = 2.
7. CPLL frequency at 2.5 GHz and TXOUT_DIV = 4.
8. CPLL frequency at 2.0 GHz and TXOUT_DIV = 8.
_Table 57:_ **GTH Transceiver Receiver Switching Characteristics**
|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|FGTHRX|Serial data rate||0.500|–|FGTHMAX|Gb/s|
|RXSST|Receiver spread-spectrum tracking(1)|Modulated at 33 kHz|–5000|–|0|ppm|
|RXRL|Run length (CID)||–|–|256|UI|
|RXPPMTOL|Data/REFCLK PPM offset tolerance|Bit rates ≤6.6 Gb/s|–1250|–|1250|ppm|
|||Bit rates > 6.6 Gb/s<br>and≤8.0 Gb/s|–700|–|700|ppm|
|||Bit rates > 8.0 Gb/s|–200|–|200|ppm|
|**SJ Jitter Tolerance(2)**|||||||
|JT_SJ16.375|Sinusoidal jitter (QPLL)(3)|16.375 Gb/s|0.30|–|–|UI|
|JT_SJ15.1|Sinusoidal jitter (QPLL)(3)|15.1 Gb/s|0.30|–|–|UI|
|JT_SJ14.1|Sinusoidal jitter (QPLL)(3)|14.1 Gb/s|0.30|–|–|UI|
|JT_SJ13.1|Sinusoidal jitter (QPLL)(3)|13.1 Gb/s|0.30|–|–|UI|
|JT_SJ12.5|Sinusoidal jitter (QPLL)(3)|12.5 Gb/s|0.30|–|–|UI|
|JT_SJ11.3|Sinusoidal jitter (QPLL)(3)|11.3 Gb/s|0.30|–|–|UI|
|JT_SJ10.32_QPLL|Sinusoidal jitter (QPLL)(3)|10.32 Gb/s|0.30|–|–|UI|
|JT_SJ10.32_CPLL|Sinusoidal jitter (CPLL)(3)|10.32 Gb/s|0.30|–|–|UI|
|JT_SJ9.953_QPLL|Sinusoidal jitter (QPLL)(3)|9.953 Gb/s|0.30|–|–|UI|
|JT_SJ9.953_CPLL|Sinusoidal jitter (CPLL)(3)|9.953 Gb/s|0.30|–|–|UI|
|JT_SJ8.0|Sinusoidal jitter (QPLL)(3)|8.0 Gb/s|0.42|–|–|UI|
|JT_SJ6.6_CPLL|Sinusoidal jitter (CPLL)(3)|6.6 Gb/s|0.44|–|–|UI|
|JT_SJ5.0|Sinusoidal jitter (CPLL)(3)|5.0 Gb/s|0.44|–|–|UI|
|JT_SJ4.25|Sinusoidal jitter (CPLL)(3)|4.25 Gb/s|0.44|–|–|UI|
|JT_SJ3.2|Sinusoidal jitter (CPLL)(3)|3.2 Gb/s(4)|0.45|–|–|UI|
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_Table 57:_ **GTH Transceiver Receiver Switching Characteristics** _**(Cont’d)**_
|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|JT_SJ2.5|Sinusoidal jitter (CPLL)(3)|2.5 Gb/s(5)|0.30|–|–|UI|
|JT_SJ1.25|Sinusoidal jitter (CPLL)(3)|1.25 Gb/s(6)|0.30|–|–|UI|
|JT_SJ500|Sinusoidal jitter (CPLL)(3)|500 Mb/s(7)|0.30|–|–|UI|
|**SJ Jitter Tolerance with Stressed Eye(2)**|||||||
|JT_TJSE3.2|Total jitter with stressed eye(8)|3.2 Gb/s|0.70|–|–|UI|
|JT_TJSE6.6||6.6 Gb/s|0.70|–|–|UI|
|JT_SJSE3.2|Sinusoidal jitter with stressed eye(8)|3.2 Gb/s|0.10|–|–|UI|
|JT_SJSE6.6||6.6 Gb/s|0.10|–|–|UI|
## **Notes:**
1. Using RXOUT_DIV = 1, 2, and 4.
2. All jitter values are based on a bit error ratio of 10[–12] .
3. The frequency of the injected sinusoidal jitter is 80 MHz.
4. CPLL frequency at 3.2 GHz and RXOUT_DIV = 2.
5. CPLL frequency at 2.5 GHz and RXOUT_DIV = 2.
6. CPLL frequency at 2.5 GHz and RXOUT_DIV = 4.
7. CPLL frequency at 2.0 GHz and RXOUT_DIV = 8.
8. Composite jitter with RX equalizer enabled. DFE disabled.
## **GTH Transceiver Electrical Compliance**
The _UltraScale Architecture GTH Transceiver User Guide_ (UG576) contains recommended use modes that ensure compliance for the protocols listed in Table 58. The transceiver wizard provides the recommended settings for those use cases and for protocol specific characteristics.
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**Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 58:_ **GTH Transceiver Protocol List**
|**Protocol**|**Specification**|**Serial Rate (Gb/s)**|**Electrical**<br>**Compliance**|
|---|---|---|---|
|CAUI-10|IEEE 802.3-2012|10.3125|Compliant|
|nPPI|IEEE 802.3-2012|10.3125|Compliant|
|10GBASE-KR(1)|IEEE 802.3-2012|10.3125|Compliant|
|40GBASE-KR|IEEE 802.3-2012|10.3125|Compliant|
|SFP+|SFF-8431 (SR and LR)|9.95328–11.10|Compliant|
|XFP|INF-8077i, revision 4.5|10.3125|Compliant|
|RXAUI|CEI-6G-SR|6.25|Compliant|
|XAUI|IEEE 802.3-2012|3.125|Compliant|
|1000BASE-X|IEEE 802.3-2012|1.25|Compliant|
|5.0G Ethernet|IEEE 802.3bx (PAR)|5|Compliant|
|2.5G Ethernet|IEEE 802.3bx (PAR)|2.5|Compliant|
|HiGig, HiGig+, HiGig2|IEEE 802.3-2012|3.74, 6.6|Compliant|
|OTU2|ITU G.8251|10.709225|Compliant|
|OTU4 (OTL4.10)|OIF-CEI-11G-SR|11.180997|Compliant|
|OC-3/12/48/192|GR-253-CORE|0.1555–9.956|Compliant|
|TFI-5|OIF-TFI5-0.1.0|2.488|Compliant|
|Interlaken|OIF-CEI-6G, OIF-CEI-11G-SR|4.25–12.5|Compliant|
|PCIe Gen1, 2, 3|PCI Express base 3.0|2.5, 5.0, and 8.0|Compliant|
|SDI(2)|SMPTE 424M-2006|0.27–2.97|Compliant|
|UHD-SDI(2)|SMPTE ST-2081 6G, SMPTE ST-2082 12G|6 and 12|Compliant|
|Hybrid memory cube (HMC)|HMC-15G-SR|10, 12.5, and 15.0|Compliant|
|MoSys Bandwidth Engine|CEI-11-SR and CEI-11-SR (overclocked)|10.3125, 15.5|Compliant|
|CPRI|CPRI_v_6_1_2014-07-01|0.6144–12.165|Compliant|
|HDMI(2)|HDMI 2.0|All|Compliant|
|Passive optical network (PON)|10G-EPON, 1G-EPON, NG-PON2, XG-PON,<br>and 2.5G-PON|0.155–10.3125|Compliant|
|JESD204a/b|OIF-CEI-6G, OIF-CEI-11G|3.125–12.5|Compliant|
|Serial RapidIO|RapidIO specification 3.1|1.25–10.3125|Compliant|
|DisplayPort(2)|DP 1.2B CTS|1.62–5.4|Compliant|
|Fibre channel|FC-PI-4|1.0625–14.025|Compliant|
|SATA Gen1, 2, 3|Serial ATA revision 3.0 specification|1.5, 3.0, and 6.0|Compliant|
|SAS Gen1, 2, 3|T10/BSR INCITS 519|3.0, 6.0, and 12.0|Compliant|
|SFI-5|OIF-SFI5-01.0|0.625–12.5|Compliant|
|Aurora|CEI-6G, CEI-11G-LR|up to 11.180997|Compliant|
## **Notes:**
1. The transition time of the transmitter is faster than the IEEE Std 802.3-2012 specification.
2. This protocol requires external circuitry to achieve compliance.
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**Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
## **GTY Transceiver Specifications**
The _UltraScale Architecture and Product Overview_ (DS890) lists the Kintex UltraScale+ FPGAs that include the GTY transceivers.
## **GTY Transceiver DC Input and Output Levels**
Table 59 and Table 60 summarize the DC specifications of the GTY transceivers in Kintex UltraScale+ FPGAs. Consult the _UltraScale Architecture GTY Transceiver User Guide_ (UG578) for further information.
_Table 59:_ **GTY Transceiver DC Specifications**
|**Symbol**|**DC Parameter**|**Conditions**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|DVPPIN|Differential peak-to-peak input<br>voltage (external AC coupled)|>10.3125 Gb/s|150|–|1250|mV|
|||6.6 Gb/s to 10.3125 Gb/s|150|–|1250|mV|
|||≤6.6 Gb/s|150|–|2000|mV|
|VIN|Single-ended input voltage.<br>Voltage measured at the pin<br>referenced to GND.|DC coupled<br>VMGTAVTT = 1.2V|–400|–|VMGTAVTT|mV|
|VCMIN|Common mode input voltage|DC coupled<br>VMGTAVTT = 1.2V|–|2/3 VMGTAVTT|–|mV|
|DVPPOUT|Differential peak-to-peak output<br>voltage(1)|Transmitter output swing<br>is set to`11111`|800|–|–|mV|
|VCMOUTDC|Common mode output voltage:<br>DC coupled (equation based)|When remote RX is<br>terminated to GND|VMGTAVTT/2 – DVPPOUT/4|||mV|
|||When remote RX<br>termination is floating|VMGTAVTT– DVPPOUT/2|||mV|
|||When remote RX is<br>terminated to VRX_TERM(2)|VMGTAVTT<br>DVPPOUT<br>4<br>----------------------<br>–<br>VMGTAVTT<br>VRX_TERM<br>–<br>2<br>-----------------------------------------------------**-**<br><br><br><br><br>–|||mV|
|VCMOUTAC|Common mode output voltage:<br>AC coupled|Equation based|VMGTAVTT– DVPPOUT/2|||mV|
|RIN|Differential input resistance||–|100|–|Ω|
|ROUT|Differential output resistance||–|100|–|Ω|
|TOSKEW|Transmitter output pair (TXP and|TXN) intra-pair skew|–|–|10|ps|
|CEXT|Recommended external AC coupling capacitor(3)||–|100|–|nF|
## **Notes:**
1. The output swing and pre-emphasis levels are programmable using the GTY transceiver attributes discussed in the _UltraScale Architecture GTY Transceiver User Guide_ (UG578) and can result in values lower than reported in this table.
2. VRX_TERM is the remote RX termination voltage.
3. Other values can be used as appropriate to conform to specific protocols and standards.
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**==> picture [498 x 88] intentionally omitted <==**
**----- Start of picture text -----**<br>
+V P<br>Single-Ended<br>Peak-to-Peak<br>N Voltage<br>0<br>X16653-101316<br>**----- End of picture text -----**<br>
_Figure 5:_ **Single-Ended Peak-to-Peak Voltage**
**==> picture [390 x 92] intentionally omitted <==**
**----- Start of picture text -----**<br>
+V<br>Differential<br>0 Peak-to-Peak<br>Voltage<br>–V P–N<br>Differential peak-to-peak voltage = (Single-ended peak-to-peak voltage) x 2<br>X16639-101316<br>**----- End of picture text -----**<br>
_Figure 6:_ **Differential Peak-to-Peak Voltage**
Table 60 and Table 61 summarize the DC specifications of the clock input of the GTY transceivers in Kintex UltraScale+ FPGAs. Consult the _UltraScale Architecture GTY Transceiver User Guide_ (UG578) for further information.
_Table 60:_ **GTY Transceiver Clock DC Input Level Specification**
|**Symbol**|**DC Parameter**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|
|VIDIFF|Differential peak-to-peak input voltage|250|–|2000|mV|
|RIN|Differential input resistance|–|100|–|Ω|
|CEXT|Required external AC coupling capacitor|–|10|–|nF|
_Table 61:_ **GTY Transceiver Clock Output Level Specification**
|**Symbol**|**Description**|**Conditions**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|VOL|Output Low voltage for P and N|RT = 100Ωacross P and N signals|100|–|330|mV|
|VOH|Output High voltage for P and N|RT = 100Ωacross P and N signals|500|–|700|mV|
|VDDOUT|Differential output voltage<br>(P–N), P = High<br>(N–P), N = High|RT = 100Ωacross P and N signals|300|–|430|mV|
|VCMOUT|Common mode voltage|RT = 100Ωacross P and N signals|300|–|500|mV|
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## **GTY Transceiver Switching Characteristics**
Consult the _UltraScale Architecture GTY Transceiver User Guide_ (UG578) for further information.
_Table 62:_ **GTY Transceiver Performance**
|**Symbol**|**Description **|**Output**<br>**Divider**|<br>**Speed Grade and VCCINTOperating Voltages**|<br>**Speed Grade and VCCINTOperating Voltages**|<br>**Speed Grade and VCCINTOperating Voltages**|<br>**Speed Grade and VCCINTOperating Voltages**|<br>**Speed Grade and VCCINTOperating Voltages**|<br>**Speed Grade and VCCINTOperating Voltages**|<br>**Speed Grade and VCCINTOperating Voltages**|<br>**Speed Grade and VCCINTOperating Voltages**|<br>**Speed Grade and VCCINTOperating Voltages**|<br>**Speed Grade and VCCINTOperating Voltages**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||||<br>**0.90V**||**0.85V**||||**0.72V**|||||
||||**-3**||**-2**||**-1**||**-2**||**-1**|||
|FGTYMAX|GTY maximum line<br>rate||32.75(1)||28.21(1)||25.7813||28.21(1)||12.5||Gb/s|
|FGTYMIN|GTY minimum line rate||0.5||0.5||0.5||0.5||0.5||Gb/s|
||||Min|Max|Min|Max|Min|Max|Min|Max|Min|Max||
|FGTYCRANGE|CPLL line<br>rate range(2)|1|4.0|12.5|4.0|12.5|4.0|8.5|4.0|12.5|4.0|8.5|Gb/s|
|||2|2.0|6.25|2.0|6.25|2.0|4.25|2.0|6.25|2.0|4.25|Gb/s|
|||4|1.0|3.125|1.0|3.125|1.0|2.125|1.0|3.125|1.0|2.125|Gb/s|
|||8|0.5|1.5625|0.5|1.5625|0.5|1.0625|0.5|1.5625|0.5|1.0625|Gb/s|
|||16|N/A||||||||||Gb/s|
|||32|N/A||||||||||Gb/s|
||||Min|Max|Min|Max|Min|Max|Min|Max|Min|Max||
|FGTYQRANGE1|QPLL0 line<br>rate range(3)|1|19.6|32.75|19.6|28.21|19.6|25.7813|19.6|28.21|N/A||Gb/s|
|||1|9.8|16.375|9.8|16.375|9.8|12.5|9.8|16.375|9.8|12.5|Gb/s|
|||2|4.9|8.1875|4.9|8.1875|4.9|8.1875|4.9|8.1875|4.9|8.1875|Gb/s|
|||4|2.45|4.09375|2.45|4.09375|2.45|4.09375|2.45|4.09375|2.45|4.09375|Gb/s|
|||8|1.225|2.04688|1.225|2.04688|1.225|2.04688|1.225|2.04688|1.225|2.04688|Gb/s|
|||16|0.6125|1.02344|0.6125|1.02344|0.6125|1.02344|0.6125|1.02344|0.6125|1.02344|Gb/s|
||||Min|Max|Min|Max|Min|Max|Min|Max|Min|Max||
|FGTYQRANGE2|QPLL1 line<br>rate range(4)|1|16.0|26.0|16.0|26.0|19.6|25.7813|16.0|26.0|N/A||Gb/s|
|||1|8.0|13.0|8.0|13.0|8.0|12.5|8.0|13.0|8.0|12.5|Gb/s|
|||2|4.0|6.5|4.0|6.5|4.0|6.5|4.0|6.5|4.0|6.5|Gb/s|
|||4|2.0|3.25|2.0|3.25|2.0|3.25|2.0|3.25|2.0|3.25|Gb/s|
|||8|1.0|1.625|1.0|1.625|1.0|1.625|1.0|1.625|1.0|1.625|Gb/s|
|||16|0.5|0.8125|0.5|0.8125|0.5|0.8125|0.5|0.8125|0.5|0.8125|Gb/s|
||||Min|Max|Min|Max|Min|Max|Min|Max|Min|Max||
|FCPLLRANGE|CPLL frequency range||2.0|6.25|2.0|6.25|2.0|4.25|2.0|6.25|2.0|4.25|GHz|
|FQPLL0RANGE|QPLL0 frequency<br>range||9.8|16.375|9.8|16.375|9.8|16.375|9.8|16.375|9.8|16.375|GHz|
|FQPLL1RANGE|QPLL1 frequency<br>range||8.0|13.0|8.0|13.0|8.0|13.0|8.0|13.0|8.0|13.0|GHz|
## **Notes:**
1. GTY transceiver line rates are package limited: SFVB784 to 12.5 Gb/s; FFVA676, FFVD900, and FFVA1156 to 16.3 Gb/s. 2. The values listed are the rounded results of the calculated equation (2 x CPLL_Frequency)/Output_Divider.
3. The values listed are the rounded results of the calculated equation (2 x QPLL0_Frequency)/Output_Divider. 4. The values listed are the rounded results of the calculated equation (2 x QPLL1_Frequency)/Output_Divider.
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_Table 63:_ **GTY Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics**
|**Symbol**|**Description**|**All Speed Grades**|**Units**|
|---|---|---|---|
|FGTYDRPCLK|GTYDRPCLK maximum frequency.|250|MHz|
## _Table 64:_ **GTY Transceiver Reference Clock Switching Characteristics**
|**Symbol**|**Description**|**Conditions**|**All Speed Grades**|**All Speed Grades**|**All Speed Grades**|**Units**|
|---|---|---|---|---|---|---|
||||**Min**|**Typ**|**Max**||
|FGCLK|Reference clock frequency range.||60|–|820|MHz|
|TRCLK|Reference clock rise time.|20% – 80%|–|200|–|ps|
|TFCLK|Reference clock fall time.|80% – 20%|–|200|–|ps|
|TDCREF|Reference clock duty cycle.|Transceiver PLL only|40|50|60|%|
## _Table 65:_ **GTY Transceiver Reference Clock Oscillator Selection Phase Noise Mask[(1)]**
|**Symbol**|**Description**|**Offset**<br>**Frequency**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|QPLLREFCLKMASK|QPLL0/QPLL1 reference clock select<br>phase noise mask at<br>REFCLK frequency = 156.25 MHz.|10 kHz|–|–|–112|dBc/Hz|
|||100 kHz|–|–|–128||
|||1 MHz|–|–|–145||
||QPLL0/QPLL1 reference clock select<br>phase noise mask at<br>REFCLK frequency = 312.5 MHz.|10 kHz|–|–|–103|dBc/Hz|
|||100 kHz|–|–|–123||
|||1 MHz|–|–|–143||
||QPLL0/QPLL1 reference clock select<br>phase noise mask at<br>REFCLK frequency =625 MHz.|10 kHz|–|–|–98|dBc/Hz|
|||100 kHz|–|–|–117||
|||1 MHz|–|–|–140||
|CPLLREFCLKMASK|CPLL reference clock select phase noise<br>mask at REFCLK<br>frequency = 156.25 MHz.|10 kHz|–|–|–112|dBc/Hz|
|||100 kHz|–|–|–128||
|||1 MHz|–|–|–145||
|||50 MHz|–|–|–145||
||CPLL reference clock select phase noise<br>mask at REFCLK frequency = 312.5 MHz.|10 kHz|–|–|–103|dBc/Hz|
|||100 kHz|–|–|–123||
|||1 MHz|–|–|–143||
|||50 MHz|–|–|–145||
||CPLL reference clock select phase noise<br>mask at REFCLK frequency = 625 MHz.|10 kHz|–|–|–98|dBc/Hz|
|||100 kHz|–|–|–117||
|||1 MHz|–|–|–140||
|||50 MHz|–|–|–144||
## **Notes:**
1. For reference clock frequencies not in this table, use the phase-noise mask for the nearest reference clock frequency.
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_Table 66:_ **GTY Transceiver PLL/Lock Time Adaptation**
|**Symbol**|**Description**|**Conditions**|**All Speed Grades**|**All Speed Grades**|**All Speed Grades**|**Units**|
|---|---|---|---|---|---|---|
||||**Min**|**Typ**|**Max**||
|TLOCK|Initial PLL lock.||–|–|1|ms|
|TDLOCK|Clock recovery phase acquisition and<br>adaptation time for decision<br>feedback equalizer (DFE).|After the PLL is locked to<br>the reference clock, this is<br>the time it takes to lock<br>the clock data recovery<br>(CDR) to the data present<br>at the input.|–|50,000|37 x 106|UI|
||Clock recovery phase acquisition and<br>adaptation time for low-power mode<br>(LPM) when the DFE is disabled.||–|50,000|2.3 x 106|UI|
_Table 67:_ **GTY Transceiver User Clock Switching Characteristics[(1)]**
|**Symbol**|**Description**|**Data Width Conditions**<br>**(Bit)**|**Data Width Conditions**<br>**(Bit)**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Units**|
|---|---|---|---|---|---|---|---|---|---|
|||||**0.90V**|**0.85V**||**0.72V**|||
|||**Internal**<br>**Logic**|**Interconnect**<br>**Logic**|<br>**-3(2)**|**-2(2)(3)**|**-1(4)(5)**|**-2(3)**|**-1(5)**||
|FTXOUTPMA|TXOUTCLK maximum frequency sourced<br>from OUTCLKPMA|||511.719|511.719|402.832|402.832|322.266|MHz|
|FRXOUTPMA|RXOUTCLK maximum frequency sourced<br>from OUTCLKPMA|||511.719|511.719|402.832|402.832|322.266|MHz|
|FTXOUTPROGDIV|TXOUTCLK maximum frequency sourced<br>from TXPROGDIVCLK|||511.719|511.719|511.719|511.719|511.719|MHz|
|FRXOUTPROGDIV|RXOUTCLK maximum frequency sourced<br>from RXPROGDIVCLK|||511.719|511.719|511.719|511.719|511.719|MHz|
|FTXIN|TXUSRCLK(6)<br>maximum<br>frequency|16|16, 32|511.719|511.719|390.625|390.625|322.266|MHz|
|||32|32, 64|511.719|511.719|390.625|390.625|322.266|MHz|
|||64|64, 128|511.719|440.781|402.832|402.832|195.313|MHz|
|||20|20, 40|409.375|409.375|312.500|312.500|257.813|MHz|
|||40|40, 80|409.375|409.375|312.500|350.000|257.813|MHz|
|||80|80, 160|409.375|352.625|322.266|352.625|156.250|MHz|
|FRXIN|RXUSRCLK(6)<br>maximum<br>frequency|16|16, 32|511.719|511.719|390.625|390.625|322.266|MHz|
|||32|32, 64|511.719|511.719|390.625|390.625|322.266|MHz|
|||64|64, 128|511.719|440.781|402.832|402.832|195.313|MHz|
|||20|20, 40|409.375|409.375|312.500|312.500|257.813|MHz|
|||40|40, 80|409.375|409.375|312.500|350.000|257.813|MHz|
|||80|80, 160|409.375|352.625|322.266|352.625|156.250|MHz|
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_Table 67:_ **GTY Transceiver User Clock Switching Characteristics[(1)]** _**(Cont’d)**_
|**Symbol**|**Description**|**Data Width Conditions**<br>**(Bit)**|**Data Width Conditions**<br>**(Bit)**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Units**|
|---|---|---|---|---|---|---|---|---|---|
|||||**0.90V**|**0.85V**||**0.72V**|||
|||**Internal**<br>**Logic**|**Interconnect**<br>**Logic**|<br>**-3(2)**|**-2(2)(3)**|**-1(4)(5)**|**-2(3)**|**-1(5)**||
|FTXIN2|TXUSRCLK2(6)<br>maximum<br>frequency|16|16|511.719|511.719|390.625|390.625|322.266|MHz|
|||16|32|255.859|255.859|195.313|195.313|161.133|MHz|
|||32|32|511.719|511.719|390.625|390.625|322.266|MHz|
|||32|64|255.859|255.859|195.313|195.313|161.133|MHz|
|||64|64|511.719|440.781|402.832|402.832|195.313|MHz|
|||64|128|255.859|220.391|201.416|201.416|97.656|MHz|
|||20|20|409.375|409.375|312.500|312.500|257.813|MHz|
|||20|40|204.688|204.688|156.250|156.250|128.906|MHz|
|||40|40|409.375|409.375|312.500|350.000|257.813|MHz|
|||40|80|204.688|204.688|156.250|175.000|128.906|MHz|
|||80|80|409.375|352.625|322.266|352.625|156.250|MHz|
|||80|160|204.688|176.313|161.133|176.313|78.125|MHz|
|FRXIN2|RXUSRCLK2(6)<br>maximum<br>frequency|16|16|511.719|511.719|390.625|390.625|322.266|MHz|
|||16|32|255.859|255.859|195.313|195.313|161.133|MHz|
|||32|32|511.719|511.719|390.625|390.625|322.266|MHz|
|||32|64|255.859|255.859|195.313|195.313|161.133|MHz|
|||64|64|511.719|440.781|402.832|402.832|195.313|MHz|
|||64|128|255.859|220.391|201.416|201.416|97.656|MHz|
|||20|20|409.375|409.375|312.500|312.500|257.813|MHz|
|||20|40|204.688|204.688|156.250|156.250|128.906|MHz|
|||40|40|409.375|409.375|312.500|350.000|257.813|MHz|
|||40|80|204.688|204.688|156.250|175.000|128.906|MHz|
|||80|80|409.375|352.625|322.266|352.625|156.250|MHz|
|||80|160|204.688|176.313|161.133|176.313|78.125|MHz|
## **Notes:**
1. Clocking must be implemented as described in the _UltraScale Architecture GTY Transceiver User Guide_ (UG578).
2. For speed grades -3E, -2E, and -2I, a 16-bit and 20-bit internal data path can only be used for line rates less than 8.1875 Gb/s.
3. For speed grade -2LE, a 16-bit and 20-bit internal data path can only be used for line rates less than 8.1875 Gb/s when VCCINT = 0.85V or 6.25 Gb/s when VCCINT = 0.72V.
4. For speed grades -1E and -1I, a 16-bit and 20-bit internal data path can only be used for line rates less than 6.25 Gb/s.
5. For speed grade -1LI, a 16-bit and 20-bit internal data path can only be used for line rates less than 6.25 Gb/s when VCCINT = 0.85V or 5.15625 Gb/s when VCCINT = 0.72V.
6. When the gearbox is used, these maximums refer to the XCLK. For more information, see the _Valid Data Width Combinations for TX Asynchronous Gearbox_ table in the _UltraScale Architecture GTY Transceiver User Guide_ (UG578).
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_Table 68:_ **GTY Transceiver Transmitter Switching Characteristics**
|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|FGTYTX|Serial data rate range||0.500|–|FGTYMAX|Gb/s|
|TRTX|TX rise time|20%–80%|–|21|–|ps|
|TFTX|TX fall time|80%–20%|–|21|–|ps|
|TLLSKEW|TX lane-to-lane skew(1)||–|–|500.00|ps|
|TJ32.75|Total jitter(2)(4)|32.75 Gb/s|–|–|0.35|UI|
|DJ32.75|Deterministic jitter(2)(4)||–|–|0.19|UI|
|TJ28.21|Total jitter(2)(4)|28.21 Gb/s|–|–|0.28|UI|
|DJ28.21|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ16.375|Total jitter(2)(4)|16.375 Gb/s|–|–|0.28|UI|
|DJ16.375|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ15.0|Total jitter(2)(4)|15.0 Gb/s|–|–|0.28|UI|
|DJ15.0|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ14.1|Total jitter(2)(4)|14.1 Gb/s|–|–|0.28|UI|
|DJ14.1|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ14.1|Total jitter(2)(4)|14.025 Gb/s|–|–|0.28|UI|
|DJ14.1|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ13.1|Total jitter(2)(4)|13.1 Gb/s|–|–|0.28|UI|
|DJ13.1|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ12.5_QPLL|Total jitter(2)(4)|12.5 Gb/s|–|–|0.28|UI|
|DJ12.5_QPLL|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ12.5_CPLL|Total jitter(2)(4)|12.5 Gb/s|–|–|0.33|UI|
|DJ12.5_CPLL|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ11.3_QPLL|Total jitter(2)(4)|11.3 Gb/s|–|–|0.28|UI|
|DJ11.3_QPLL|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ10.3125_QPLL|Total jitter(2)(4)|10.3125 Gb/s|–|–|0.28|UI|
|DJ10.3125_QPLL|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ10.3125_CPLL|Total jitter(3)(4)|10.3125 Gb/s|–|–|0.33|UI|
|DJ10.3125_CPLL|Deterministic jitter(3)(4)||–|–|0.17|UI|
|TJ9.953_QPLL|Total jitter(2)(4)|9.953 Gb/s|–|–|0.28|UI|
|DJ9.953_QPLL|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ9.953_CPLL|Total jitter(3)(4)|9.953 Gb/s|–|–|0.33|UI|
|DJ9.953_CPLL|Deterministic jitter(3)(4)||–|–|0.17|UI|
|TJ8.0|Total jitter(2)(4)|8.0 Gb/s|–|–|0.32|UI|
|DJ8.0|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ6.6|Total jitter(3)(4)|6.6 Gb/s|–|–|0.30|UI|
|DJ6.6|Deterministic jitter(3)(4)||–|–|0.15|UI|
|TJ5.0|Total jitter(3)(4)|5.0 Gb/s|–|–|0.30|UI|
|DJ5.0|Deterministic jitter(3)(4)||–|–|0.15|UI|
|TJ4.25|Total jitter(3)(4)|4.25 Gb/s|–|–|0.30|UI|
|DJ4.25|Deterministic jitter(3)(4)||–|–|0.15|UI|
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_Table 68:_ **GTY Transceiver Transmitter Switching Characteristics** _**(Cont’d)**_
|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|TJ3.20|Total jitter(3)(4)|3.20 Gb/s(5)|–|–|0.20|UI|
|DJ3.20|Deterministic jitter(3)(4)||–|–|0.10|UI|
|TJ2.5|Total jitter(3)(4)|2.5 Gb/s(6)|–|–|0.20|UI|
|DJ2.5|Deterministic jitter(3)(4)||–|–|0.10|UI|
|TJ1.25|Total jitter(3)(4)|1.25 Gb/s(7)|–|–|0.15|UI|
|DJ1.25|Deterministic jitter(3)(4)||–|–|0.06|UI|
|TJ500|Total jitter(3)(4)|500 Mb/s(8)|–|–|0.10|UI|
|DJ500|Deterministic jitter(3)(4)||–|–|0.03|UI|
## **Notes:**
1. Using same REFCLK input with TX phase alignment enabled for up to four consecutive transmitters (one fully populated GTY Quad) at maximum line rate.
2. Using QPLL_FBDIV = 40, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations.
3. Using CPLL_FBDIV = 2, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations.
4. All jitter values are based on a bit-error ratio of 10[-12] .
5. CPLL frequency at 3.2 GHz and TXOUT_DIV = 2.
6. CPLL frequency at 2.5 GHz and TXOUT_DIV = 2.
7. CPLL frequency at 2.5 GHz and TXOUT_DIV = 4.
8. CPLL frequency at 2.0 GHz and TXOUT_DIV = 8.
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**Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 69:_ **GTY Transceiver Receiver Switching Characteristics**
|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|FGTYRX|Serial data rate||0.500|–|FGTYMAX|Gb/s|
|RXSST|Receiver spread-spectrum tracking(1)|Modulated at 33 kHz|–5000|–|0|ppm|
|RXRL|Run length (CID)||–|–|256|UI|
|RXPPMTOL|Data/REFCLK PPM offset tolerance|Bit rates ≤6.6 Gb/s|–1250|–|1250|ppm|
|||Bit rates > 6.6 Gb/s<br>and≤8.0 Gb/s|–700|–|700|ppm|
|||Bit rates > 8.0 Gb/s|–200|–|200|ppm|
|**SJ Jitter Tolerance(2)**|||||||
|JT_SJ32.75|Sinusoidal jitter (QPLL)(3)|32.75 Gb/s|0.25|–|–|UI|
|JT_SJ28.21|Sinusoidal jitter (QPLL)(3)|28.21 Gb/s|0.30|–|–|UI|
|JT_SJ16.375|Sinusoidal jitter (QPLL)(3)|16.375 Gb/s|0.30|–|–|UI|
|JT_SJ15.0|Sinusoidal jitter (QPLL)(3)|15.0 Gb/s|0.30|–|–|UI|
|JT_SJ14.1|Sinusoidal jitter (QPLL)(3)|14.1 Gb/s|0.30|–|–|UI|
|JT_SJ13.1|Sinusoidal jitter (QPLL)(3)|13.1 Gb/s|0.30|–|–|UI|
|JT_SJ12.5|Sinusoidal jitter (QPLL)(3)|12.5 Gb/s|0.30|–|–|UI|
|JT_SJ11.3|Sinusoidal jitter (QPLL)(3)|11.3 Gb/s|0.30|–|–|UI|
|JT_SJ10.32_QPLL|Sinusoidal jitter (QPLL)(3)|10.32 Gb/s|0.30|–|–|UI|
|JT_SJ10.32_CPLL|Sinusoidal jitter (CPLL)(3)|10.32 Gb/s|0.30|–|–|UI|
|JT_SJ9.953_QPLL|Sinusoidal jitter (QPLL)(3)|9.953 Gb/s|0.30|–|–|UI|
|JT_SJ9.953_CPLL|Sinusoidal jitter (CPLL)(3)|9.953 Gb/s|0.30|–|–|UI|
|JT_SJ8.0|Sinusoidal jitter (CPLL)(3)|8.0 Gb/s|0.42|–|–|UI|
|JT_SJ6.6|Sinusoidal jitter (CPLL)(3)|6.6 Gb/s|0.44|–|–|UI|
|JT_SJ5.0|Sinusoidal jitter (CPLL)(3)|5.0 Gb/s|0.44|–|–|UI|
|JT_SJ4.25|Sinusoidal jitter (CPLL)(3)|4.25 Gb/s|0.44|–|–|UI|
|JT_SJ3.2|Sinusoidal jitter (CPLL)(3)|3.2 Gb/s(4)|0.45|–|–|UI|
|JT_SJ2.5|Sinusoidal jitter (CPLL)(3)|2.5 Gb/s(5)|0.30|–|–|UI|
|JT_SJ1.25|Sinusoidal jitter (CPLL)(3)|1.25 Gb/s(6)|0.30|–|–|UI|
|JT_SJ500|Sinusoidal jitter (CPLL)(3)|500 Mb/s(7)|0.30|–|–|UI|
|**SJ Jitter Tolerance with Stressed Eye(2)**|||||||
|JT_TJSE3.2|Total jitter with stressed eye(8)|3.2 Gb/s|0.70|–|–|UI|
|JT_TJSE6.6||6.6 Gb/s|0.70|–|–|UI|
|JT_SJSE3.2|Sinusoidal jitter with stressed eye(8)|3.2 Gb/s|0.10|–|–|UI|
|JT_SJSE6.6||6.6 Gb/s|0.10|–|–|UI|
## **Notes:**
1. Using RXOUT_DIV = 1, 2, and 4.
2. All jitter values are based on a bit error ratio of 10[–12] .
3. The frequency of the injected sinusoidal jitter is 80 MHz.
4. CPLL frequency at 3.2 GHz and RXOUT_DIV = 2.
5. CPLL frequency at 2.5 GHz and RXOUT_DIV = 2.
6. CPLL frequency at 2.5 GHz and RXOUT_DIV = 4.
7. CPLL frequency at 2.0 GHz and RXOUT_DIV = 8.
8. Composite jitter with RX equalizer enabled. DFE disabled.
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**Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
## **GTY Transceiver Electrical Compliance**
The _UltraScale Architecture GTY Transceiver User Guide_ (UG578) contains recommended use modes that ensure compliance for the protocols listed in Table 70. The transceiver wizard provides the recommended settings for those use cases and for protocol specific characteristics.
_Table 70:_ **GTY Transceiver Protocol List**
|**Protocol**|**Specification**|**Serial Rate**<br>**(Gb/s)**|**Electrical**<br>**Compliance**|
|---|---|---|---|
|CAUI-4|IEEE 802.3-2012|25.78125|Compliant|
|28 Gb/s backplane|CEI-25G-LR|25–28.05|Compliant|
|Interlaken|OIF-CEI-6G, OIF-CEI-11GSR, OIF-CEI-28G-MR|4.25–25.78125|Compliant|
|100GBASE-KR4|IEEE 802.3bj-2014, CEI-25G-LR|25.78125|Compliant(1)|
|100GBASE-CR4|IEEE 802.3bj-2014, CEI-25G-LR|25.78125|Compliant(1)|
|50GBASE-KR4|IEEE 802.3by-2014, CEI-25G-LR|25.78125|Compliant(1)|
|50GBASE-CR4|IEEE 802.3by-2014, CEI-25G-LR|25.78125|Compliant(1)|
|25GBASE-KR4|IEEE 802.3by-2014, CEI-25G-LR|25.78125|Compliant(1)|
|25GBASE-CR4|IEEE 802.3by-2014, CEI-25G-LR|25.78125|Compliant(1)|
|OTU4 (OTL4.4) CFP2|OIF-CEI-28G-VSR|27.952493-32.75|Compliant|
|OTU4 (OTL4.4) CFP|OIF-CEI-11G-MR|11.18–13.1|Compliant|
|CAUI-10|IEEE 802.3-2012|10.3125|Compliant|
|nPPI|IEEE 802.3-2012|10.3125|Compliant|
|10GBASE-KR(2)|IEEE 802.3-2012|10.3125|Compliant|
|SFP+|SFF-8431 (SR and LR)|9.95328–11.10|Compliant|
|XFP|INF-8077i, revision 4.5|10.3125|Compliant|
|RXAUI|CEI-6G-SR|6.25|Compliant|
|XAUI|IEEE 802.3-2012|3.125|Compliant|
|1000BASE-X|IEEE 802.3-2012|1.25|Compliant|
|5.0G Ethernet|IEEE 802.3bx (PAR)|5|Compliant|
|2.5G Ethernet|IEEE 802.3bx (PAR)|2.5|Compliant|
|HiGig, HiGig+, HiGig2|IEEE 802.3-2012|3.74, 6.6|Compliant|
|QSGMII|QSGMII v1.2 (Cisco System, ENG-46158)|5|Compliant|
|OTU2|ITU G.8251|10.709225|Compliant|
|OTU4 (OTL4.10)|OIF-CEI-11G-SR|11.180997|Compliant|
|OC-3/12/48/192|GR-253-CORE|0.1555–9.956|Compliant|
|PCIe Gen1, 2, 3|PCI Express base 3.0|2.5, 5.0, and 8.0|Compliant|
|SDI(3)|SMPTE 424M-2006|0.27–2.97|Compliant|
|UHD-SDI(3)|SMPTE ST-2081 6G, SMPTE ST-2082 12G|6 and 12|Compliant|
|Hybrid memory cube (HMC)|HMC-15G-SR|10, 12.5, and 15.0|Compliant|
|MoSys bandwidth engine|CEI-11-SR and CEI-11-SR (overclocked)|10.3125, 15.5|Compliant|
|CPRI|CPRI_v_6_1_2014-07-01|0.6144–12.165|Compliant|
|Passive optical network (PON)|10G-EPON, 1G-EPON, NG-PON2, XG-PON, and<br>2.5G-PON|0.155–10.3125|Compliant|
|JESD204a/b|OIF-CEI-6G, OIF-CEI-11G|3.125–12.5|Compliant|
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**Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 70:_ **GTY Transceiver Protocol List** _**(Cont’d)**_
|**Protocol**|**Specification**|**Serial Rate**<br>**(Gb/s)**|**Electrical**<br>**Compliance**|
|---|---|---|---|
|Serial RapidIO|RapidIO specification 3.1|1.25–10.3125|Compliant|
|DisplayPort|DP 1.2B CTS|1.62–5.4|Compliant(3)|
|Fibre channel|FC-PI-4|1.0625–14.025|Compliant|
|SATA Gen1, 2, 3|Serial ATA revision 3.0 specification|1.5, 3.0, and 6.0|Compliant|
|SAS Gen1, 2, 3|T10/BSR INCITS 519|3.0, 6.0, and 12.0|Compliant|
|SFI-5|OIF-SFI5-01.0|0.625 - 12.5|Compliant|
|Aurora|CEI-6G, CEI-11G-LR|All rates|Compliant|
## **Notes:**
1. 25 dB loss at Nyquist without FEC.
2. The transition time of the transmitter is faster than the IEEE Std 802.3-2012 specification.
3. This protocol requires external circuitry to achieve compliance.
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**Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
## **Integrated Interface Block for Interlaken**
More information and documentation on solutions using the integrated interface block for Interlaken can be found at UltraScale Interlaken. The _UltraScale Architecture and Product Overview_ (DS890) lists how many blocks are in each Kintex UltraScale+ FPGA. This section describes the following Interlaken configurations.
- 12 x 12.5 Gb/s protocol and lane logic mode (Table 71).
- 6 x 25.78125 Gb/s and 6 x 28.21 Gb/s protocol and lane logic mode (Table 72).
- 12 x 25.78125 Gb/s lane logic only mode (Table 73).
Kintex UltraScale+ FPGAs in the SFVB784, FFVA676, and FFVA1156 packages are only supported using the 12 x 12.5 Gb/s Interlaken configuration. See Table 62 for the FGTYMAX description.
_Table 71:_ **Maximum Performance for Interlaken 12 x 12.5 Gb/s Protocol and Lane Logic Mode Designs**
|_Table 71:_ **Ma**<br>**Designs**|**ximum Perform**|**ance for Interlaken 12 x 12.5 Gb/s Protocol and Lane Logic M**|**ance for Interlaken 12 x 12.5 Gb/s Protocol and Lane Logic M**|**ance for Interlaken 12 x 12.5 Gb/s Protocol and Lane Logic M**|**ance for Interlaken 12 x 12.5 Gb/s Protocol and Lane Logic M**|**ance for Interlaken 12 x 12.5 Gb/s Protocol and Lane Logic M**|**ance for Interlaken 12 x 12.5 Gb/s Protocol and Lane Logic M**|**ance for Interlaken 12 x 12.5 Gb/s Protocol and Lane Logic M**|**ance for Interlaken 12 x 12.5 Gb/s Protocol and Lane Logic M**|**ance for Interlaken 12 x 12.5 Gb/s Protocol and Lane Logic M**|**ance for Interlaken 12 x 12.5 Gb/s Protocol and Lane Logic M**|**ode**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Symbol**|**Description**|**Speed Grade and VCCINTOperating Voltages**||||||||||**Units**|
|||**0.90V**||**0.85V**||||**0.72V**|||||
|||**-3**||**-2**||**-1**||**-2**||**-1**|||
|FRX_SERDES_CLK|Receive serializer/<br>deserializer clock|<br>195.32||195.32||195.32||195.32||195.32||MHz|
|FTX_SERDES_CLK|Transmit<br>serializer/<br>deserializer clock|195.32||195.32||195.32||195.32||195.32||MHz|
|FDRP_CLK|Dynamic<br>reconfiguration<br>port clock|250.00||250.00||250.00||250.00||250.00||MHz|
|||Min(1)|Max|Min(1)|Max|Min(1)|Max|Min(1)|Max|Min(1)|Max||
|FCORE_CLK|Interlaken core<br>clock|300.00|322.27|300.00|322.27|300.00|322.27|300.00|322.27|300.00|322.27|MHz|
|FLBUS_CLK|Interlaken local<br>bus clock|300.00|322.27|300.00|322.27|300.00|322.27|300.00|322.27|300.00|322.27|MHz|
## **Notes:**
1. These are the minimum clock frequencies at the maximum lane performance.
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**Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 72:_ **Maximum Performance for Interlaken 6 x 25.78125 Gb/s and 6 x 28.21 Gb/s Protocol and Lane Logic Mode Designs**
|**Symbol**|**Description**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|||**0.90V**||**0.85V**||||**0.72V**|||||
|||**-3(1)**||**-2(1)**||**-1**||**-2**||**-1**|||
|FRX_SERDES_CLK|Receive serializer/<br>deserializer clock|440.79||440.79||N/A||402.84||N/A||MHz|
|FTX_SERDES_CLK|Transmit serializer/<br>deserializer clock|440.79||440.79||N/A||402.84||N/A||MHz|
|FDRP_CLK|Dynamic reconfiguration<br>port clock|250.00||250.00||N/A||250.00||N/A||MHz|
|||Min(2)|Max|Min(2)|Max|Min|Max|Min(2)|Max|Min|Max||
|FCORE_CLK|Interlaken core clock|412.50(3)|479.20|412.50(3)|479.20|N/A||412.50|429.69|N/A||MHz|
|FLBUS_CLK|Interlaken local bus clock|300.00(4)|349.52|300.00(4)|349.52|N/A||300.00|349.52|N/A||MHz|
## **Notes:**
1. 6 x 28.21 mode is only supported in the -2 (VCCINT=0.85V) and -3 (VCCINT=0.90V) speed grades.
2. These are the minimum clock frequencies at the maximum lane performance.
3. The minimum value for CORE_CLK is 451.36 MHz for the 6 x 28.21 Gb/s protocol.
4. The minimum value for LBUS_CLK is 330.00 MHz for the 6 x 28.21 Gb/s protocol.
_Table 73:_ **Maximum Performance for Interlaken 12 x 25.78125 Gb/s Lane Logic Only Mode Designs**
|_Table 73:_ **Ma**<br>**Designs**|**ximum Performance f**|**or Interlaken 12 x 25.78125 Gb/s Lane Logic Only Mode**|**or Interlaken 12 x 25.78125 Gb/s Lane Logic Only Mode**|**or Interlaken 12 x 25.78125 Gb/s Lane Logic Only Mode**|**or Interlaken 12 x 25.78125 Gb/s Lane Logic Only Mode**|**or Interlaken 12 x 25.78125 Gb/s Lane Logic Only Mode**||
|---|---|---|---|---|---|---|---|
|**Symbol**|**Description**|**Speed Grade and VCCINTOperating Voltages**|||||**Units**|
|||**0.90V**|**0.85V**||**0.72V**|||
|||**-3**|**-2**|**-1**|**-2**|**-1**||
|FRX_SERDES_CLK|Receive serializer/<br>deserializer clock|402.84|402.84|N/A|N/A|N/A|MHz|
|FTX_SERDES_CLK|Transmit serializer/<br>deserializer clock|402.84|402.84|N/A|N/A|N/A|MHz|
|FDRP_CLK|Dynamic reconfiguration<br>port clock|250.00|250.00|N/A|N/A|N/A|MHz|
|FCORE_CLK|Interlaken core clock|412.50|412.50|N/A|N/A|N/A|MHz|
|FLBUS_CLK|Interlaken local bus clock|<br>349.52|349.52|N/A|N/A|N/A|MHz|
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**Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
## **Integrated Interface Block for 100G Ethernet MAC and PCS**
More information and documentation on solutions using the integrated 100 Gb/s Ethernet block can be found at UltraScale Integrated 100G Ethernet MAC/PCS. The _UltraScale Architecture and Product Overview_ (DS890) lists how many blocks are in each Kintex UltraScale+ FPGA.
_Table 74:_ **Maximum Performance for 100G Ethernet Designs**
|**Symbol**|**Description**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Units**|
|---|---|---|---|---|---|---|---|
|||**0.90V**|**0.85V**||**0.72V**|||
|||**-3**|**-2(1)**|**-1**|**-2**|**-1(2)**||
|FTX_CLK|Transmit clock|390.625|390.625|322.223|322.223|322.223|MHz|
|FRX_CLK|Receive clock|390.625|390.625|322.223|322.223|322.223|MHz|
|FRX_SERDES_CLK|Receive serializer/deserializer clock|390.625|390.625|322.223|322.223|322.223|MHz|
|FDRP_CLK|Dynamic reconfiguration port clock|250.00|250.00|250.00|250.00|250.00|MHz|
## **Notes:**
1. The maximum clock frequency of 390.625 MHz only applies to the CAUI-10 interface. The maximum clock frequency for the CAUI-4 interface is 322.223 MHz.
2. The CAUI-4 interface is not supported by -1L speed grade devices where VCCINT=0.72V.
## **Integrated Interface Block for PCI Express Designs**
More information and documentation on solutions for PCI Express designs can be found at PCI Express. The _UltraScale Architecture and Product Overview_ (DS890) lists how many blocks are in each Kintex UltraScale+ FPGA.
_Table 75:_ **Maximum Performance for PCI Express Designs[(1)(2)]**
|**Symbol**|**Description**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Speed Grade and VCCINTOperating Voltages**|**Units**|
|---|---|---|---|---|---|---|---|
|||**0.90V**|**0.85V**||**0.72V**|||
|||**-3**|**-2**|**-1**|**-2**|**-1**||
|FPIPECLK|Pipe clock maximum frequency.|250.00|250.00|250.00|250.00|250.00|MHz|
|FCORECLK|Core clock maximum frequency.|500.00|500.00|500.00|250.00|250.00|MHz|
|FDRPCLK|DRP clock maximum frequency.|250.00|250.00|250.00|250.00|250.00|MHz|
|FMCAPCLK|MCAP clock maximum frequency.|125.00|125.00|125.00|125.00|125.00|MHz|
## **Notes:**
1. PCI Express Gen4 operation is supported for x1, x2, x4, and x8 widths.
2. PCI Express Gen4 operation is supported in -3E, -2E, and -2I speed grades.
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**Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
## **System Monitor Specifications**
_Table 76:_ **System Monitor Specifications**
|**Parameter**|**Symbol**|**Comments/Conditions**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|VCCADC = 1.8V ±3%, VREFP = 1.25V, VREFN = 0V, ADCCLK = 5.2 MHz, Tj = –40°C to 100°C, typical values at Tj = 40°C|||||||
|**ADC Accuracy(1)**|||||||
|Resolution|||10|–|–|Bits|
|Integral nonlinearity(2)|INL||–|–|±1.5|LSBs|
|Differential nonlinearity|DNL|No missing codes, guaranteed<br>monotonic|–|–|±1|LSBs|
|Offset error||Offset calibration enabled|–|–|±2|LSBs|
|Gain error|||–|–|±0.4|%|
|Sample rate|||–|–|0.2|MS/s|
|RMS code noise||External 1.25V reference|–|–|1|LSBs|
|||On-chip reference|–|1|–|LSBs|
|**ADC Accuracy at Extended Temperatures**|||||||
|Resolution||Tj = –55°C to 125°C|10|–|–|Bits|
|Integral nonlinearity(2)|INL|Tj = –55°C to 125°C|–|–|±1.5|LSBs|
|Differential nonlinearity|DNL|No missing codes, guaranteed<br>monotonic<br>Tj = –55°C to 125°C|–|–|±1||
|**Analog Inputs(2)**|||||||
|ADC input ranges||Unipolar operation|0|–|1|V|
|||Bipolar operation|–0.5|–|+0.5|V|
|||Unipolar common mode range (FS input)|0|–|+0.5|V|
|||Bipolar common mode range (FS input)|+0.5|–|+0.6|V|
|Maximum external channel input<br>ranges||Adjacent channels set within these<br>ranges should not corrupt<br>measurements on adjacent channels|–0.1|–|VCCADC|V|
|**On-Chip Sensor Accuracy**|||||||
|Temperature sensor error(1)(3)||Tj = –55°C to 125°C (with external REF)|–|–|±3|°C|
|||Tj = –55°C to 110°C (with internal REF)|–|–|±3.5|°C|
|||Tj = 110°C to 125°C (with internal REF)|–|–|±5|°C|
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_Table 76:_ **System Monitor Specifications** _**(Cont’d)**_
|**Parameter**|**Symbol**|**Comments/Conditions**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|Supply sensor error(4)||Supply voltages 0.72V to 1.2V,<br>Tj = –40°C to 100°C (with external REF)|–|–|±0.5|%|
|||Supply voltages 0.72V to 1.2V,<br>Tj = –55°C to 125°C (with external REF)|–|–|±1.0|%|
|||All other supply voltages,<br>Tj = –40°C to 100°C (with external REF)|–|–|±1.0|%|
|||All other supply voltages,<br>Tj = –55°C to 125°C (with external REF)|–|–|±2.0|%|
|||Supply voltages 0.72V to 1.2V,<br>Tj = –40°C to 100°C (with internal REF)|–|–|±1.0|%|
|||Supply voltages 0.72V to 1.2V,<br>Tj = –55°C to 125°C (with internal REF)|–|–|±2.0|%|
|||All other supply voltages,<br>Tj = –40°C to 100°C (with internal REF)|–|–|±1.5|%|
|||All other supply voltages,<br>Tj = –55°C to 125°C (with internal REF)|–|–|±2.5|%|
|**Conversion Rate(5)**|||||||
|Conversion time—continuous|tCONV|Number of ADCCLK cycles|26|–|32|Cycles|
|Conversion time—event|tCONV|Number of ADCCLK cycles|–|–|21|Cycles|
|DRP clock frequency|DCLK|DRP clock frequency|8|–|250|MHz|
|ADC clock frequency|ADCCLK|Derived from DCLK|1|–|5.2|MHz|
|DCLK duty cycle|||40|–|60|%|
|**SYSMON Reference(6)**|||||||
|External reference|VREFP|Externally supplied reference voltage|1.20|1.25|1.30|V|
|On-chip reference||Ground VREFPpin to AGND,<br>Tj = –40°C to 100°C|1.2375|1.25|1.2625|V|
|||Ground VREFPpin to AGND,<br>Tj = –55°C to 125°C|1.225|1.25|1.275|V|
## **Notes:**
1. ADC offset errors are removed by enabling the ADC automatic offset calibration feature. The values are specified for when this feature is enabled.
2. See the _Analog Input_ section in the _UltraScale Architecture System Monitor User Guide_ (UG580).
3. When reading temperature values directly from the PMBus interface, the SYSMON has a +4°C offset due to the transfer function used by the PMBus application. For example, the external REF temperature sensor error’s range of ±3°C becomes +1°C to +7°C when the temperature is read through the PMBus interface.
4. Supply sensor offset and gain errors are removed by enabling the automatic offset and gain calibration feature. The values are specified for when this feature is enabled.
5. See the _Adjusting the Acquisition Settling Time_ section in the _UltraScale Architecture System Monitor User Guide_ (UG580).
6. Any variation in the reference voltage from the nominal VREFP = 1.25V and VREFN = 0V will result in a deviation from the ideal transfer function. This also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). However, for external ratiometric type applications allowing reference to vary by ±4% is permitted.
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**Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
## **SYSMON I2C/PMBus Interfaces**
_Table 77:_ **SYSMON I2C Fast Mode Interface Switching Characteristics[(1)]**
|**Symbol**|**Description**|**Min**|**Max**|**Units**|
|---|---|---|---|---|
|TSMFCKL|SCL Low time|1.3|–|µs|
|TSMFCKH|SCL High time|0.6|–|µs|
|TSMFCKO|SDAO clock-to-out delay|–|900|ns|
|TSMFDCK|SDAI setup time|100|–|ns|
|FSMFCLK|SCL clock frequency|–|400|kHz|
## **Notes:**
1. The test conditions are configured to the LVCMOS 1.8V I/O standard.
## _Table 78:_ **SYSMON I2C Standard Mode Interface Switching Characteristics[(1)]**
|**Symbol**|**Description**|**Min**|**Max**|**Units**|
|---|---|---|---|---|
|TSMSCKL|SCL Low time|4.7|–|µs|
|TSMSCKH|SCL High time|4.0|–|µs|
|TSMSCKO|SDAO clock-to-out delay|–|3450|ns|
|TSMSDCK|SDAI setup time|250|–|ns|
|FSMSCLK|SCL clock frequency|–|100|kHz|
## **Notes:**
1. The test conditions are configured to the LVCMOS 1.8V I/O standard.
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**Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics**
## **Configuration Switching Characteristics**
_Table 79:_ **Configuration Switching Characteristics**
|**Symbol**|**Description**|**Description**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Units**|
|---|---|---|---|---|---|---|---|---|
||||**0.90V**|**0.85V**||**0.72V**|||
||||**-3**|**-2**|**-1**|**-2**|**-1**||
|**Power-up Timing Characteristics**|||||||||
|TPL|Program latency.||7.5|7.5|7.5|7.5|7.5|ms, Max|
|TPOR|Power-on reset<br>(40 ms maximum ramp rate).||65|65|65|65|65|ms, Max|
||||0|0|0|0|0|ms, Min|
||Power-on reset with POR override<br>(2 ms maximum ramp rate).||15|15|15|15|15|ms, Max|
||||5|5|5|5|5|ms, Min|
|TPROGRAM|Program pulse width.||250|250|250|250|250|ns, Min|
|**CCLK Output (Master Mode)**|||||||||
|TICCK|Master CCLK output delay from INIT_B.||150|150|150|150|150|ns, Min|
|TMCCKL(1)|Master CCLK clock Low time duty cycle.||40/60|40/60|40/60|40/60|40/60|%, Min/Max|
|TMCCKH|Master CCLK clock High time duty cycle.||40/60|40/60|40/60|40/60|40/60|%, Min/Max|
|FMCCK|Master SPI/BPI CCLK<br>frequency.|XCKU3P, XCKU5P|125|125|125|60|60|MHz, Max|
|||All other devices|150|150|150|125|125||
|FMCCK_START|Master CCLK frequency at start of<br>configuration.||2.70|2.70|2.70|2.70|2.70|MHz, Typ|
|FMCCKTOL|Frequency tolerance, master mode with<br>respect to nominal CCLK.||±15|±15|±15|±15|±15|%, Max|
|**CCLK Input (Slave Mode)**|||||||||
|TSCCKL|Slave CCLK clock minimum Low time.||2.5|2.5|2.5|2.5|2.5|ns, Min|
|TSCCKH|Slave CCLK clock minimum High time.||2.5|2.5|2.5|2.5|2.5|ns, Min|
|FSCCK|Slave serial/<br>SelectMap CCLK<br>frequency.|XCKU3P, XCKU5P|125|125|125|60|60|MHz, Max|
|||All other devices|125|125|125|125|125||
|**EMCCLK Input (Master Mode)**|||||||||
|TEMCCKL|External master CCLK Low time.||2.5|2.5|2.5|2.5|2.5|ns, Min|
|TEMCCKH|External master CCLK High time.||2.5|2.5|2.5|2.5|2.5|ns, Min|
|FEMCCK|External master CCLK<br>frequency.|XCKU3P, XCKU5P|125|125|125|60|60|MHz, Max|
|||All other devices|150|150|150|125|125||
|**Internal Configuration Access Port**|||||||||
|FICAPCK|Internal configuration access port<br>(ICAPE3).||200|200|200|150|150|MHz, Max|
|**Slave Serial Mode Programming Switching**|||||||||
|TDCCK/TCCKD|DINsetup/hold.||3.0/0|3.0/0|3.0/0|4.0/0|4.0/0|ns, Min|
|TCCO|DOUTclock to out.||8.0|8.0|8.0|9.0|9.0|ns, Max|
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_Table 79:_ **Configuration Switching Characteristics** _**(Cont’d)**_
|**Symbol**|**Description**|**Description**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Units**|
|---|---|---|---|---|---|---|---|---|
||||**0.90V**|**0.85V**||**0.72V**|||
||||**-3**|**-2**|**-1**|**-2**|**-1**||
|**SelectMAP Mode Programming Switching**|||||||||
|TSMDCCK/TSMCCKD|D[31:00] setup/hold.|XCKU3P, XCKU5P|4.5/0|4.5/0|4.5/0|8.0/0|8.0/0|ns, Min|
|||All other devices|3.5/0|3.5/0|3.5/0|4.5/0|4.5/0||
|TSMCSCCK/TSMCCKCS|CSI_B setup/hold.|XCKU3P, XCKU5P|4.5/0|4.5/0|4.5/0|7.0/0|7.0/0|ns, Min|
|||All other devices|4.0/0|4.0/0|4.0/0|5.0/0|5.0/0||
|TSMWCCK/TSMCCKW|RDWR_B setup/hold.|XCKU3P, XCKU5P|10.0/0|10.0/0|10.0/0|17.0/0|17.0/0|ns, Min|
|||All other devices|10.0/0|10.0/0|10.0/0|11.0/0|11.0/0||
|TSMCKCSO|CSO_B clock to out<br>(330Ωpull-up resistor<br>required).|XCKU3P, XCKU5P|7.0|7.0|7.0|10.0|10.0|ns, Max|
|||All other devices|7.0|7.0|7.0|7.0|7.0||
|TSMCO|D[31:00] clock to out<br>in readback.|XCKU3P, XCKU5P|8.0|8.0|8.0|10.0|10.0|ns, Max|
|||All other devices|8.0|8.0|8.0|8.0|8.0||
|FRBCCK|Readback frequency.|XCKU3P, XCKU5P|125|125|125|60|60|MHz, Max|
|||All other devices|125|125|125|125|125||
|**Boundary-Scan Port Timing Specifications**|||||||||
|TTAPTCK/TTCKTAP|TMS and TDI setup/hold.||3.0/<br>2.0|3.0/<br>2.0|3.0/<br>2.0|3.0/<br>2.0|3.0/<br>2.0|ns, Min|
|TTCKTDO|TCK falling edge to TDO output.||7.0|7.0|7.0|7.0|7.0|ns, Max|
|FTCK|TCK frequency.|XCKU15P|66|66|66|50|50|MHz, Max|
|||All other devices|66|66|66|66|66||
|**BPI Master Flash Mode Programming Switching**|||||||||
|TBPICCO|A[28:00], RS[1:0], FCS_B, FOE_B,<br>FWE_B, ADV_B clock to out.||10|10|10|10|10|ns, Max|
|TBPIDCC/TBPICCD|D[15:00] setup/hold.|XCKU3P, XCKU5P|4.5/0|4.5/0|4.5/0|8.0/0|8.0/0|ns, Min|
|||All other devices|3.5/0|3.5/0|3.5/0|4.5/0|4.5/0||
|**SPI Master Flash Mode Programming Switching**|||||||||
|TSPIDCC/TSPICCD|D[03:00] setup/hold.||3.0/0|3.0/0|3.0/0|4.0/0|4.0/0|ns, Min|
|TSPIDCC/TSPICCD|D[07:04] setup/hold.|XCKU3P, XCKU5P|4.5/0|4.5/0|4.5/0|8.0/0|8.0/0|ns, Min|
|||All other devices|3.5/0|3.5/0|3.5/0|4.5/0|4.5/0||
|TSPICCM|MOSI clock to out.||8.0|8.0|8.0|8.0|8.0|ns, Max|
|TSPICCFC|FCS_B clock to out.||8.0|8.0|8.0|8.0|8.0|ns, Max|
|**DNA Port Switching**|||||||||
|FDNACK|DNA port frequency.||200|200|200|175|175|MHz, Max|
|**STARTUPE3 Ports**|||||||||
|TUSRCCLKO|STARTUPE3 USRCCLKO input port to<br>CCLK pin output delay.||0.25/<br>6.00|0.25/<br>6.50|0.25/<br>7.50|0.25/<br>9.00|0.25/<br>9.00|ns, Min/Max|
|TDO|DO[3:0] ports to D03-D00 pins output<br>delay.||0.25/<br>6.70|0.25/<br>7.70|0.25/<br>8.40|0.25/<br>10.00|0.25/<br>10.00|ns, Min/Max|
|TDTS|DTS[3:0] ports to D03-D00 pins 3-state<br>delays.||0.25/<br>6.70|0.25/<br>7.70|0.25/<br>8.40|0.25/<br>10.00|0.25/<br>10.00|ns, Min/Max|
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_Table 79:_ **Configuration Switching Characteristics** _**(Cont’d)**_
|**Symbol**|**Description**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Speed Grade and**<br>**VCCINTOperating Voltages**|**Units**|
|---|---|---|---|---|---|---|---|
|||**0.90V**|**0.85V**||**0.72V**|||
|||**-3**|**-2**|**-1**|**-2**|**-1**||
|TFCSBO|FCSBO port to FCS_B pin output delay.|0.25/<br>6.90|0.25/<br>7.50|0.25/<br>8.40|0.25/<br>9.80|0.25/<br>9.80|ns, Min/Max|
|TFCSBTS|FCSBTS port to FCS_B pin 3-state delay.|0.25/<br>6.90|0.25/<br>7.50|0.25/<br>8.40|0.25/<br>9.80|0.25/<br>9.80|ns, Min/Max|
|TUSRDONEO|USRDONEO port to DONE pin output<br>delay.|0.25/<br>8.60|0.25/<br>9.40|0.25/<br>10.50|0.25/<br>12.10|0.25/<br>12.10|ns, Min/Max|
|TUSRDONETS|USRDONETS port to DONE pin 3-state<br>delay.|0.25/<br>8.60|0.25/<br>9.40|0.25/<br>10.50|0.25/<br>12.10|0.25/<br>12.10|ns, Min/Max|
|TDI|D03-D00 pins to DI[3:0] ports input<br>delay.|0.5/<br>2.6|0.5/<br>3.1|0.5/<br>3.5|0.5/<br>4.0|0.5/<br>4.0|ns, Min/Max|
|FCFGMCLK|STARTUPE3 CFGMCLK output frequency.|50|50|50|50|50|MHz, Typ|
|FCFGMCLKTOL|STARTUPE3 CFGMCLK output frequency<br>tolerance.|±15|±15|±15|±15|±15|%, Max|
|TDCI_MATCH|Specifies a stall in the startup cycle until<br>the digitally controlled impedance (DCI)<br>match signals are asserted.|4|4|4|4|4|ms, Max|
## **Notes:**
1. When the CCLK is sourced from the EMCCLK pin with a divide-by-one setting, the external EMCCLK must meet this duty-cycle requirement.
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## **Revision History**
The following table shows the revision history for this document.
|**Date**|**Version**|**Description of Revisions**|
|---|---|---|
|05/08/2017|1.3|UpdatedTable 21andTable 22to production release for the following<br>devices/speed/temperature grades in Vivado Design Suite 2017.1.<br>XCKU9P: -2E, -2I, -1E, -1I<br>Removed the MIPI_DPHY_DCI_LP standard fromTable 9(HD I/O banks never supported<br>DCI). Revised the minimum 32.75 Gb/s sinusoidal jitter inTable 69.|
|04/11/2017|1.2|Updated theSummarydescription. InTable 1, updated and added data, and updated<br>Note 7, addedNote 8,Note 9, andNote 10. Updated and added data toTable 2, revised<br>Note 11and addedNote 12andNote 13. UpdatedTable 3and addedNote 6. Added<br>specifications toTable 4thoughTable 6. Updated maximum VICMandNote 1inTable 18.<br>Updated the maximum VODIFFinTable 19.<br>UpdatedTable 20,Table 21, andTable 22to production release for the following<br>devices/speed/temperature grades in Vivado Design Suite 2017.1.<br>XCKU3P: -2E, -2I, -1E, -1I<br>XCKU5P: -2E, -2I, -1E, -1I<br>AddedNote 1toTable 21. UpdatedTable 23. UpdatedTable 24and addedNote 2. Added<br>Table 25. UpdatedTable 27and addedNote 3. Many revisions to the speed specifications<br>inTable 28,Table 29,Table 30,Table 33,Table 34,Table 35,Table 40,Table 41,Table 42,<br>Table 43,Table 44, andTable 45. Updated VLand VHvalues inTable 31. InTable 35,<br>addedTMINPER_CLKandNote 1, and revisedFREFCLK. AddedMMCM_FDPRCLK_MAXto<br>Table 38andPLL_FDPRCLK_MAXtoTable 39. UpdatedTable 46. Revised theGTH<br>Transceiver SpecificationsandGTH Transceiver Specificationssections. Revised the<br>Integrated Interface Block for InterlakenandIntegrated Interface Block for 100G<br>Ethernet MAC and PCSsections. Updated theSystem Monitor Specificationssection<br>includingOn-Chip Sensor Accuracyand addingNote 3toTable 76. Removed timing<br>diagrams from theSYSMON I2C/PMBus Interfacessection. Updated theConfiguration<br>Switching Characteristicssection. Removed the_eFUSE Programming Conditions_table and<br>added the specifications toTable 2andTable 3. UpdatedTable 79. Updated the<br>Automotive Applications Disclaimer.|
|05/09/2016|1.1|InTable 1revised VINfor HP I/O banks. UpdatedNote 5inTable 3. Added values to<br>Table 7. Added MIPI_DPHY_DCI toTable 9,Table 10, andTable 12. Updated and added<br>notes inTable 18andTable 19. UpdatedTable 20speed specifications for Vivado Design<br>Suite 2016.1. Removed Table 23,_Video Codec Unit Performance_. UpdatedTable 24.<br>Expanded and updatedTable 27. UpdatedTable 28andTable 29. UpdatedTable 31and<br>Table 32with MIPI D-PHY values. UpdatedTable 31andTable 32. InTable 33, added the<br>Block RAM and FIFO Clock-to-Out Delayssection. UpdatedTable 40toTable 44. Revised<br>the symbol names inTable 43. Revised typical values inTable 48. Updated the -2 (0.72V)<br>and -1 (0.72V) values inTable 50. AddedTable 53andTable 65. AddedNote 2to<br>Table 59. RevisedTable 67. Revised data and added notes toTable 62,Table 71, and<br>Table 74. Revised INL inTable 76. Added notes toTable 77andTable 78. Many revised<br>sections inTable 79.|
|11/24/2015|1.0|Initial Xilinx release.|
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## **Notice of Disclaimer**
The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of Xilinx’s limited warranty, please refer to Xilinx’s Terms of Sale which can be viewed at www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in such critical applications, please refer to Xilinx’s Terms of Sale which can be viewed at www.xilinx.com/legal.htm#tos.
## **Automotive Applications Disclaimer**
AUTOMOTIVE PRODUCTS (IDENTIFIED AS "XA" IN THE PART NUMBER) ARE NOT WARRANTED FOR USE IN THE DEPLOYMENT OF AIRBAGS OR FOR USE IN APPLICATIONS THAT AFFECT CONTROL OF A VEHICLE ("SAFETY APPLICATION") UNLESS THERE IS A SAFETY CONCEPT OR REDUNDANCY FEATURE CONSISTENT WITH THE ISO 26262 AUTOMOTIVE SAFETY STANDARD ("SAFETY DESIGN"). CUSTOMER SHALL, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE PRODUCTS, THOROUGHLY TEST SUCH SYSTEMS FOR SAFETY PURPOSES. USE OF PRODUCTS IN A SAFETY APPLICATION WITHOUT A SAFETY DESIGN IS FULLY AT THE RISK OF CUSTOMER, SUBJECT ONLY TO APPLICABLE LAWS AND REGULATIONS GOVERNING LIMITATIONS ON PRODUCT LIABILITY.
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