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XCKU040-2FFVA1156E
FPGA, KIntex UltraScale, MMCM, PLL, 520 I/O's, 725 MHz, 530250 Cells, 922-979 mV, FCBGA-1156, NCNR
⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
- Manufacturer: AMD
- Product type: FPGAs
- No. of Logic Blocks:242400; No. of Macrocells:530250; FPGA Family:Kintex UltraScale; Logic Case Style:FCBGA; No. of Pins:1156Pins; No. of Speed Grades:-2; Total RAM Bits:21100Kbit
- MSL: MSL 4 - 72 hours
- SVHC: No SVHC (15-Jan-2018)
- FPGA Type: -
- FPGA Family: Kintex UltraScale
- IC Mounting: Surface Mount
- No. of Pins: 1156Pins
- Speed Grade: 2
- No. of I/O's: 520I/O's
- Product Range: Kintex UltraScale XCKU040
- Qualification: -
- Total RAM Bits: 21100Kbit
- No.of User I/Os: 520I/O's
- Clock Management: MMCM, PLL
- Logic Case Style: FCBGA
- IC Case / Package: FCBGA
- No. of Macrocells: 530250Macrocells
- I/O Supply Voltage: 3.3V
- No. of Logic Cells: 530250Logic Cells
- Process Technology: -
- No. of Logic Blocks: 530250
- No. of Speed Grades: 2
- Core Supply Voltage Max: 979mV
- Core Supply Voltage Min: 922mV
- Operating Frequency Max: 725MHz
- Operating Temperature Max: 100°C
- Operating Temperature Min: 0°C
| Delivery and price | |
|---|---|
| Units per pack | 1 |
| Price | 2168.04 € |
| Current stock | 10+ |
| Lead time | 30 days |
Datasheet
**==> picture [164 x 47] intentionally omitted <==**
## **Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
DS892 (v1.14) February 2, 2017
**Product Specification**
## **Summary**
The Xilinx® Kintex® UltraScale™ FPGAs are available in -3, -2, -1, and -1L speed grades, with -3 having the highest performance. The -1L devices can operate at either of two VCCINT voltages, 0.95V and 0.90V and = are screened for lower maximum static power. When operated at VCCINT 0.95V, the speed specification = of a -1L device is the same as the -1 speed grade. When operated at VCCINT 0.90V, the -1L performance and static and dynamic power is reduced.
DC and AC characteristics are specified in commercial, extended, industrial, and military temperature ranges. Except the operating temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -1 speed grade industrial device are the same as for a -1 speed grade commercial device). However, only selected speed grades and/or devices are available in each temperature range.
All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters included are common to popular designs and typical applications.
This data sheet, part of an overall set of documentation on the UltraScale architecture-based devices, is available on the Xilinx website at www.xilinx.com/documentation.
## **DC Characteristics**
_Table 1:_ **Absolute Maximum Ratings[(1)]**
|**Symbol**|**Description**|**Min**|**Max**|**Units**|
|---|---|---|---|---|
|**FPGA Logic**|||||
|VCCINT|Internal supply voltage|–0.500|1.100|V|
|VCCINT_IO(2)|Internal supply voltage for the I/O banks|–0.500|1.100|V|
|VCCAUX|Auxiliary supply voltage|–0.500|2.000|V|
|VCCBRAM|Supply voltage for the block RAM memories|–0.500|1.100|V|
|VCCO|Output drivers supply voltage for HR I/O banks|–0.500|3.400|V|
||Output drivers supply voltage for HP I/O banks|–0.500|2.000|V|
|VCCAUX_IO(3)|Auxiliary supply voltage for the I/O banks|–0.500|2.000|V|
|VREF|Input reference voltage|–0.500|2.000|V|
|VIN(4)(6)(7)|I/O input voltage for HR I/O banks(5)|–0.400|VCCO + 0.550|V|
||I/O input voltage for HP I/O banks|–0.550|VCCO + 0.550|V|
||I/O input voltage (when VCCO= 3.3V) for VREFand differential I/O<br>standards except TMDS_33(8)|–0.400|2.625|V|
© Copyright 2013–2017 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 1:_ **Absolute Maximum Ratings[(1)]** _**(Cont’d)**_
|**Symbol**|**Description**|**Min**|**Max**|**Units**|
|---|---|---|---|---|
|VBATT|Key memory battery backup supply|–0.500|2.000|V|
|IDC|Available output current at the pad|–20|20|mA|
|IRMS|Available RMS output current at the pad|–20|20|mA|
|**GTH and GTY Transceivers**|||||
|VMGTAVCC|Analog supply voltage for the GTH and GTY transmitter and<br>receiver circuits|–0.500|1.100|V|
|VMGTAVTT|Analog supply voltage for the GTH and GTY transmitter and<br>receiver termination circuits|–0.500|1.320|V|
|VMGTVCCAUX|Auxiliary analog Quad PLL (QPLL) voltage supply for the GTH and<br>GTY transceivers|–0.500|1.935|V|
|VMGTREFCLK|GTH and GTY transceiver reference clocks absolute input voltage|–0.500|1.320|V|
|VMGTAVTTRCAL|Analog supply voltage for the resistor calibration circuit of the<br>GTH and GTY transceiver columns|–0.500|1.320|V|
|VIN|Receiver (RXP/RXN) and Transmitter (TXP/TXN) absolute input<br>voltage|–0.500|1.260|V|
|IDCIN-FLOAT|DC input current for receiver input pins DC coupled RX<br>termination = floating|–|0(9)|mA|
|IDCIN-MGTAVTT|DC input current for receiver input pins DC coupled RX<br>termination = VMGTAVTT|–|10|mA|
|IDCIN-GND|DC input current for receiver input pins DC coupled RX<br>termination = GND|–|10|mA|
|IDCIN-PROG|DC input current for receiver input pins DC coupled RX<br>termination = Programmable|–|N/A(9)|mA|
|IDCOUT-FLOAT|DC output current for transmitter pins DC coupled RX<br>termination = floating|–|0(9)|mA|
|IDCOUT-MGTAVTT|DC output current for transmitter pins DC coupled RX<br>termination = VMGTAVTT|–|6|mA|
|**System Monitor**|||||
|VCCADC|System Monitor supply relative to GNDADC|–0.500|2.000|V|
|VREFP|System Monitor reference input relative to GNDADC|–0.500|2.000|V|
|**Temperature**|||||
|TSTG|Storage temperature (ambient)|–65|150|°C|
|TSOL|Maximum soldering temperature for Pb-free component<br>bodies(10)|–|260|°C|
||Maximum soldering temperature for Pb/Sn component bodies(10)|–|220|°C|
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 1:_ **Absolute Maximum Ratings[(1)]** _**(Cont’d)**_
|**Symbol**|**Description**|**Min**|**Max**|**Units**|
|---|---|---|---|---|
|Tj|Maximum junction temperature(10)|–|125|°C|
## **Notes:**
1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
2. VCCINT_IO must be connected to VCCINT.
3. VCCAUX_IO must be connected to VCCAUX.
4. The lower absolute voltage specification always applies.
5. If VCCO is 3.3V, the maximum voltage is 3.4V.
6. For I/O operation, see the _UltraScale Architecture SelectIO Resources User Guide_ (UG571).
7. The maximum limit applied to DC signals. For maximum undershoot and overshoot AC specifications, see Table 4 and Table 5.
8. See Table 12 for TMDS_33 specifications.
9. For more information on supported GTH or GTY transceiver terminations see the _UltraScale Architecture GTH Transceiver User Guide_ (UG576) or the _UltraScale Architecture GTY Transceiver User Guide_ (UG578).
10. For soldering guidelines and thermal considerations, see the _UltraScale and UltraScale+ FPGAs Packaging and Pinout Specifications_ (UG575).
_Table 2:_ **Recommended Operating Conditions[(1)(2)]**
|**Symbol**|**Description**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|
|**FPGA Logic**||||||
|VCCINT|Internal supply voltage|0.922|0.950|0.979|V|
||For -1L (0.90V) devices: internal supply voltage|0.880|0.900|0.920|V|
||For -3 (1.0V only) devices: internal supply voltage|0.970|1.000|1.030|V|
|VCCINT_IO(3)|Internal supply voltage for the I/O banks|0.922|0.950|0.979|V|
||For -1L (0.90V) devices: internal supply voltage for the I/O<br>banks|0.880|0.900|0.920|V|
||For -3 (1.0V only) devices: internal supply voltage for the<br>I/O banks|0.970|1.000|1.030|V|
|VCCBRAM|Block RAM supply voltage|0.922|0.950|0.979|V|
||For -3 (1.0V only) devices: block RAM supply voltage|0.970|1.000|1.030|V|
|VCCAUX|Auxiliary supply voltage|1.746|1.800|1.854|V|
|VCCO(4)(5)|Supply voltage for HR I/O banks|1.140|–|3.400|V|
||Supply voltage for HP I/O banks|0.950|–|1.890|V|
|VCCAUX_IO(6)|Auxiliary I/O supply voltage|1.746|1.800|1.854|V|
|VIN(7)|I/O input voltage|–0.200|–|VCCO + 0.200|V|
||I/O input voltage (when VCCO = 3.3V) for VREFand<br>differential I/O standards except TMDS_33(8).|–|0.400|2.625|V|
|IIN(9)|Maximum current through any pin in a powered or<br>unpowered bank when forward biasing the clamp diode.|–|–|10.000|mA|
|VBATT(10)|Battery voltage|1.000|–|1.890|V|
|**GTH and GTY Transceivers**||||||
|VMGTAVCC(11)|Analog supply voltage for the GTH and GTY transceivers(10)|0.970|1.000|1.030|V|
|VMGTAVTT(11)|Analog supply voltage for the GTH and GTY transmitter and<br>receiver termination circuits|1.170|1.200|1.230|V|
|VMGTVCCAUX(11)|Auxiliary analog QPLL voltage supply for the transceivers|1.750|1.800|1.850|V|
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 2:_ **Recommended Operating Conditions[(1)(2)]** _**(Cont’d)**_
|**Symbol**|**Description**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|
|VMGTAVTTRCAL(11)|Analog supply voltage for the resistor calibration circuit of<br>the GTH and GTY transceiver columns|1.170|1.200|1.230|V|
|**SYSMON**||||||
|VCCADC|SYSMON supply relative to GNDADC|1.746|1.800|1.854|V|
|VREFP|Externally supplied reference voltage|1.200|1.250|1.300|V|
|**Temperature**||||||
|Tj|Junction temperature operating range for commercial (C)<br>temperature devices|0|–|85|°C|
||Junction temperature operating range for extended (E)<br>temperature devices|0|–|100|°C|
||Junction temperature operating range for industrial (I)<br>temperature devices|–40|–|100|°C|
||Junction temperature operating range for military (M)<br>temperature devices|–55|–|125|°C|
## **Notes:**
1. All voltages are relative to ground.
2. For the design of the power distribution system consult _UltraScale Architecture PCB Design Guide_ (UG583).
3. VCCINT_IO must be connected to VCCINT.
4. For VCCO_0, the minimum recommended operating voltage for power on and during configuration is 1.425V. After configuration, data is retained even if VCCO drops to 0V.
5. Includes VCCO of 1.0V (HP I/O only), 1.2V, 1.35V, 1.5V, 1.8V, 2.5V (HR I/O only) at ±5%, and 3.3V (HR I/O only) at +3/–5%.
6. VCCAUX_IO must be connected to VCCAUX.
7. The lower absolute voltage specification always applies.
8. See Table 12 for TMDS_33 specifications.
9. A total of 200 mA per 52-pin bank should not be exceeded.
10. VBATT is required only when using bitstream encryption. If battery is not used, connect VBATT to either ground or VCCAUX.
11. Each voltage listed requires filtering as described in _UltraScale Architecture GTH Transceiver User Guide_ (UG576).
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 3:_ **DC Characteristics Over Recommended Operating Conditions**
|**Symbol**|**Description**|**Min**|**Typ(1)**|**Max**|**Units**|
|---|---|---|---|---|---|
|VDRINT|Data retention VCCINTvoltage (below which configuration<br>data might be lost)|0.82|–|–|V|
|VDRAUX|Data retention VCCAUXvoltage (below which configuration<br>data might be lost)|1.50|–|–|V|
|IREF|VREFleakage current per pin|–|–|15|µA|
|IL|Input or output leakage current per pin (sample-tested)|–|–|15(2)|µA|
||Input or output leakage current per pin for XQ devices<br>(sample-tested)|–|–|20(2)|µA|
|CIN(3)|Die input capacitance at the pad (HP I/O)|–|–|3.75|pF|
||Die input capacitance at the pad (HR I/O)|–|–|7.00|pF|
|IRPU|Pad pull-up (when selected) at VIN = 0V, VCCO = 3.3V|75|–|175|µA|
||Pad pull-up (when selected) at VIN = 0V, VCCO = 2.5V|50|–|169|µA|
||Pad pull-up (when selected) at VIN = 0V, VCCO = 1.8V|60|–|678|µA|
||Pad pull-up (when selected) at VIN = 0V, VCCO = 1.5V|30|–|450|µA|
||Pad pull-up (when selected) at VIN = 0V, VCCO = 1.2V|10|–|262|µA|
|IRPD|Pad pull-down (when selected) at VIN = 3.3V|60|–|190|µA|
||Pad pull-down (when selected) at VIN = 1.8V|29|–|685|µA|
|ICCADC|Analog supply current per SYSMON instance in powered up<br>state.|–|–|19.2|mA|
|IBATT(4)|Battery supply current|–|–|150|nA|
|_Calibrated programmable on-die termination (DCI) in HP I/O banks(6) (measured per JEDEC specification)_||||||
|R(7)|Thevenin equivalent resistance of programmable input<br>termination to VCCO/2 where ODT = RTT_40|–10%(5)|40|+10%(5)|Ω|
||Thevenin equivalent resistance of programmable input<br>termination to VCCO/2 where ODT = RTT_48|–10%(5)|48|+10%(5)|Ω|
||Thevenin equivalent resistance of programmable input<br>termination to VCCO/2 where ODT = RTT_60|–10%(5)|60|+10%(5)|Ω|
||Programmable input termination to VCCOwhere<br>ODT = RTT_40|–10%(5)|40|+10%(5)|Ω|
||Programmable input termination to VCCOwhere<br>ODT = RTT_48|–10%(5)|48|+10%(5)|Ω|
||Programmable input termination to VCCOwhere<br>ODT = RTT_60|–10%(5)|60|+10%(5)|Ω|
||Programmable input termination to VCCOwhere<br>ODT = RTT_120|–10%(5)|120|+10%(5)|Ω|
||Programmable input termination to VCCOwhere<br>ODT = RTT_240|–10%(5)|240|+10%(5)|Ω|
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 3:_ **DC Characteristics Over Recommended Operating Conditions** _**(Cont’d)**_
|**Symbol**|**Description**|**Min**|**Typ(1)**|**Max**|**Units**|
|---|---|---|---|---|---|
|_Uncalibrated programmable on-die termination in HP I/Os banks (measured per JEDEC specification)_||||||
|R(7)|Thevenin equivalent resistance of programmable input<br>termination to VCCO/2 where ODT = RTT_40|–50%|40|+50%|Ω|
||Thevenin equivalent resistance of programmable input<br>termination to VCCO/2 where ODT = RTT_48|–50%|48|+50%|Ω|
||Thevenin equivalent resistance of programmable input<br>termination to VCCO/2 where ODT = RTT_60|–50%|60|+50%|Ω|
||Programmable input termination to VCCOwhere<br>ODT = RTT_40|–50%|40|+50%|Ω|
||Programmable input termination to VCCOwhere<br>ODT = RTT_48|–50%|48|+50%|Ω|
||Programmable input termination to VCCOwhere<br>ODT = RTT_60|–50%|60|+50%|Ω|
||Programmable input termination to VCCOwhere<br>ODT = RTT_120|–50%|120|+50%|Ω|
||Programmable input termination to VCCOwhere<br>ODT = RTT_240|–50%|240|+50%|Ω|
|_Uncalibrated programmable on-die termination in HR I/O banks (measured per JEDEC specification)_||||||
|R(7)|Thevenin equivalent resistance of programmable input<br>termination to VCCO/2 where ODT = RTT_40|–50%|40|+50%|Ω|
||Thevenin equivalent resistance of programmable input<br>termination to VCCO/2 where ODT = RTT_48|–50%|48|+50%|Ω|
||Thevenin equivalent resistance of programmable input<br>termination to VCCO/2 where ODT = RTT_60|–50%|60|+50%|Ω|
|Internal VREF|50% VCCO|VCCO x<br>0.49|VCCO x<br>0.50|VCCO x<br>0.51|V|
||70% VCCO|VCCO x<br>0.69|VCCO x<br>0.70|VCCO x<br>0.71|V|
|Differential<br>termination|Programmable differential termination (TERM_100)|–|100|–|Ω|
|n|Temperature diode ideality factor|–|1.002|–|–|
|r|Temperature diode series resistance|–|2|–|Ω|
## **Notes:**
1. Typical values are specified at nominal voltage, 25°C.
2. For HP I/O banks with a VCCO of 1.8V and separated VCCO and VCCAUX_IO power supplies, the IL maximum current is 70 µA.
3. This measurement represents the die capacitance at the pad, not including the package.
4. Maximum value specified for worst case process at 25°C.
5. If VRP resides at a different bank (DCI cascade), the range increases to ±15%.
6. VRP resistor tolerance is (240 Ω ±1%)
7. On-die input termination resistance, for more information see the _UltraScale Architecture SelectIO Resources User Guide_ (UG571).
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 4:_ **VIN Maximum Allowed AC Voltage Overshoot and Undershoot for HR I/O Banks[(1)]**
|_Table 4:_ **VIN Maximu**|**m Allowed AC Voltage Over**|**shoot and Undershoot**|**for HR I/O Banks()**|
|---|---|---|---|
|**AC Voltage Overshoot **|**% of UI at –40°C to 100°C **|**AC Voltage Undershoot **|**% of UI at –40°C to 100°C**|
|VCCO + 0.30|100%|–0.30|100%|
|VCCO + 0.35|100%|–0.35|70.00%|
|VCCO + 0.40|100%|–0.40|27.00%|
|VCCO + 0.45|100%|–0.45|10.00%|
|VCCO + 0.50|85.00%|–0.50|5.00%|
|VCCO + 0.55|70.00%|–0.55|2.10%|
|VCCO + 0.60|46.60%|–0.60|1.50%|
|VCCO + 0.65|21.20%|–0.65|1.10%|
|VCCO + 0.70|9.75%|–0.70|0.60%|
|VCCO + 0.75|4.55%|–0.75|0.45%|
|VCCO + 0.80|2.15%|–0.80|0.20%|
|VCCO + 0.85|1.00%|–0.85|0.10%|
|VCCO + 0.90|0.50%|–0.90|0.05%|
|VCCO + 0.95|0.25%|–0.95|0.05%|
## **Notes:**
1. A total of 200 mA per bank should not be exceeded.
_Table 5:_ **VIN Maximum Allowed AC Voltage Overshoot and Undershoot for HP I/O Banks[(1)(2)]**
|_Table 5:_ **VIN Maximu**|**m Allowed AC Voltage Over**|**shoot and Undershoot**|**for HP I/O Banks()()**|
|---|---|---|---|
|**AC Voltage Overshoot **|**% of UI at –40°C to 100°C **|**AC Voltage Undershoot **|**% of UI at –40°C to 100°C**|
|VCCO + 0.05|100%|–0.05|100%|
|VCCO + 0.10|100%|–0.10|100%|
|VCCO + 0.15|100%|–0.15|100%|
|VCCO + 0.20|100%|–0.20|100%|
|VCCO + 0.25|100%|–0.25|100%|
|VCCO + 0.30|100%|–0.30|100%|
|VCCO + 0.35|92.00%|–0.35|92.00%|
|VCCO + 0.40|70.00%|–0.40|40.00%|
|VCCO + 0.45|30.00%|–0.45|15.00%|
|VCCO + 0.50|15.00%|–0.50|10.00%|
|VCCO + 0.55|10.00%|–0.55|4.00%|
|VCCO + 0.60|8.00%|–0.60|0.00%|
|VCCO + 0.65|6.00%|–0.65|0.00%|
|VCCO + 0.70|4.00%|–0.70|0.00%|
|VCCO + 0.75|2.00%|–0.75|0.00%|
|VCCO + 0.80|2.00%|–0.80|0.00%|
|VCCO + 0.85|2.00%|–0.85|0.00%|
## **Notes:**
1. A total of 200 mA per bank should not be exceeded.
2. For UI smaller than 20 µs.
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 6:_ **Typical Quiescent Supply Current**
|**Symbol**|**Description**|**Device**|**Speed Grade and**<br>**VCCINT Operating Voltages**|**Speed Grade and**<br>**VCCINT Operating Voltages**|**Speed Grade and**<br>**VCCINT Operating Voltages**|**Speed Grade and**<br>**VCCINT Operating Voltages**|**Speed Grade and**<br>**VCCINT Operating Voltages**|**Units**|
|---|---|---|---|---|---|---|---|---|
||||**1.0V**|**0.95V**|||**0.90V**||
||||**-3**|**-2**|**-1**|**-1L**|**-1L**||
|ICCINTQ|Quiescent VCCINTsupply current|XCKU025|N/A|998|998|N/A|N/A|mA|
|||XCKU035|1097|998|998|998|907|mA|
|||XCKU040|1097|998|998|998|907|mA|
|||XCKU060|1590|1446|1446|1446|1315|mA|
|||XCKU085|3181|2893|2893|2893|2631|mA|
|||XCKU095|N/A|2100|2100|N/A|N/A|mA|
|||XCKU115|3181|2893|2893|2893|2631|mA|
|||XQKU040|N/A|998|998|N/A|N/A|mA|
|||XQKU060|N/A|1446|1446|N/A|N/A|mA|
|||XQKU095|N/A|2100|2100|N/A|N/A|mA|
|||XQKU115|N/A|2893|2893|N/A|N/A|mA|
|ICCINT_IOQ|Quiescent current for VCCINT_IO<br>supply|XCKU025|N/A|87|87|N/A|N/A|mA|
|||XCKU035|98|87|87|87|77|mA|
|||XCKU040|98|87|87|87|77|mA|
|||XCKU060|118|105|105|105|93|mA|
|||XCKU085|236|210|210|210|187|mA|
|||XCKU095|N/A|143|143|N/A|N/A|mA|
|||XCKU115|236|210|210|210|187|mA|
|||XQKU040|N/A|87|87|N/A|N/A|mA|
|||XQKU060|N/A|105|105|N/A|N/A|mA|
|||XQKU095|N/A|143|143|N/A|N/A|mA|
|||XQKU115|N/A|210|210|N/A|N/A|mA|
|ICCOQ|Quiescent VCCOsupply current|XCKU025|N/A|1|1|N/A|N/A|mA|
|||XCKU035|1|1|1|1|1|mA|
|||XCKU040|1|1|1|1|1|mA|
|||XCKU060|1|1|1|1|1|mA|
|||XCKU085|1|1|1|1|1|mA|
|||XCKU095|N/A|1|1|N/A|N/A|mA|
|||XCKU115|1|1|1|1|1|mA|
|||XQKU040|N/A|1|1|N/A|N/A|mA|
|||XQKU060|N/A|1|1|N/A|N/A|mA|
|||XQKU095|N/A|1|1|N/A|N/A|mA|
|||XQKU115|N/A|1|1|N/A|N/A|mA|
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 6:_ **Typical Quiescent Supply Current** _**(Cont’d)**_
|**Symbol**|**Description**|**Device**|**Speed Grade and**<br>**VCCINT Operating Voltages**|**Speed Grade and**<br>**VCCINT Operating Voltages**|**Speed Grade and**<br>**VCCINT Operating Voltages**|**Speed Grade and**<br>**VCCINT Operating Voltages**|**Speed Grade and**<br>**VCCINT Operating Voltages**|**Units**|
|---|---|---|---|---|---|---|---|---|
||||**1.0V**|**0.95V**|||**0.90V**||
||||**-3**|**-2**|**-1**|**-1L**|**-1L**||
|ICCAUXQ|Quiescent VCCAUXsupply current|XCKU025|N/A|145|145|N/A|N/A|mA|
|||XCKU035|145|145|145|145|145|mA|
|||XCKU040|145|145|145|145|145|mA|
|||XCKU060|188|188|188|188|188|mA|
|||XCKU085|376|376|376|376|376|mA|
|||XCKU095|N/A|273|273|N/A|N/A|mA|
|||XCKU115|376|376|376|376|376|mA|
|||XQKU040|N/A|145|145|N/A|N/A|mA|
|||XQKU060|N/A|188|188|N/A|N/A|mA|
|||XQKU095|N/A|273|273|N/A|N/A|mA|
|||XQKU115|N/A|376|376|N/A|N/A|mA|
|ICCAUX_IOQ|Quiescent VCCAUX_IOsupply current|XCKU025|N/A|66|66|N/A|N/A|mA|
|||XCKU035|66|66|66|66|66|mA|
|||XCKU040|66|66|66|66|66|mA|
|||XCKU060|83|83|83|83|83|mA|
|||XCKU085|165|165|165|165|165|mA|
|||XCKU095|N/A|124|124|N/A|N/A|mA|
|||XCKU115|165|165|165|165|165|mA|
|||XQKU040|N/A|66|66|N/A|N/A|mA|
|||XQKU060|N/A|83|83|N/A|N/A|mA|
|||XQKU095|N/A|124|124|N/A|N/A|mA|
|||XQKU115|N/A|165|165|N/A|N/A|mA|
|ICCBRAMQ|Quiescent VCCBRAMsupply current|XCKU025|N/A|39|39|N/A|N/A|mA|
|||XCKU035|42|39|39|39|39|mA|
|||XCKU040|42|39|39|39|39|mA|
|||XCKU060|76|69|69|69|69|mA|
|||XCKU085|153|139|139|139|139|mA|
|||XCKU095|N/A|111|111|N/A|N/A|mA|
|||XCKU115|153|139|139|139|139|mA|
|||XQKU040|N/A|39|39|N/A|N/A|mA|
|||XQKU060|N/A|69|69|N/A|N/A|mA|
|||XQKU095|N/A|111|111|N/A|N/A|mA|
|||XQKU115|N/A|139|139|N/A|N/A|mA|
## **Notes:**
1. Typical values are specified at nominal voltage, 85°C junction temperatures (Tj) with single-ended SelectIO™ resources. 2. Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and floating.
3. Use the Xilinx Power Estimator (XPE) spreadsheet tool (download at www.xilinx.com/power) to estimate static power consumption for conditions other than those specified.
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
## **Power-On/Off Power Supply Sequencing**
The recommended power-on sequence is VCCINT/VCCINT_IO, VCCBRAM, VCCAUX/VCCAUX_IO, and VCCO to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on. The recommended power-off sequence is the reverse of the power-on sequence. If VCCINT/VCCINT_IO and VCCBRAM have the same recommended voltage levels, they can be powered by the same supply and ramped simultaneously. VCCINT_IO must be connected to VCCINT. If VCCAUX/VCCAUX_IO and VCCO have the same recommended voltage levels, they can be powered by the same supply and ramped simultaneously. VCCAUX and VCCAUX_IO must be connected together. When the current minimums are met, the device powers on after the VCCINT/VCCINT_IO, VCCBRAM, VCCAUX/VCCAUX_IO, and VCCO supplies have all passed through their power-on reset threshold voltages. The device must not be configured until after VCCINT is applied.
VCCADC and VREF can be powered at any time and have no power-up sequencing recommendations.
The recommended power-on sequence to achieve minimum current draw for the GTH or GTY transceivers is VCCINT, VMGTAVCC, VMGTAVTT OR VMGTAVCC, VCCINT, VMGTAVTT. There is no recommended sequencing for VMGTVCCAUX. Both VMGTAVCC and VCCINT can be ramped simultaneously. The recommended power-off sequence is the reverse of the power-on sequence to achieve minimum current draw. If these recommended sequences are not met, current drawn from VMGTAVTT can be higher than specifications during power-up and power-down.
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
Table 7 shows the minimum current, in addition to ICCQ, that are required by Kintex UltraScale FPGAs for proper power-on and configuration. If the current minimums shown in Table 6 and Table 7 are met, the device powers on after all four supplies have passed through their power-on reset threshold voltages. The device must not be configured until after VCCINT is applied. Once initialized and configured, use the Xilinx Power Estimator (XPE) tools to estimate current drain on these supplies.
_Table 7:_ **Power-on Current by Device**
|**Device**|**ICCINTMIN + ICCINT_IOMIN**|**ICCO**|**ICCAUXMIN + ICCAUX_IOMIN**|**ICCBRAMMIN**|**Units**|
|---|---|---|---|---|---|
|XCKU025|ICCINTQ + ICCINT_IOQ + 2400|ICCO_0Q + 100|ICCAUXQ + ICCAUX_IOQ + 380|ICCBRAMQ + 50|mA|
|XCKU035|ICCINTQ + ICCINT_IOQ + 2400|ICCO_0Q + 100|ICCAUXQ + ICCAUX_IOQ + 380|ICCBRAMQ + 50|mA|
|XCKU040|ICCINTQ + ICCINT_IOQ + 2400|ICCO_0Q + 100|ICCAUXQ + ICCAUX_IOQ + 380|ICCBRAMQ + 50|mA|
|XCKU060|ICCINTQ + ICCINT_IOQ + 3284|ICCO_0Q + 137|ICCAUXQ + ICCAUX_IOQ + 520|ICCBRAMQ + 100|mA|
|XCKU085|ICCINTQ + ICCINT_IOQ + 6568|ICCO_0Q + 274|ICCAUXQ + ICCAUX_IOQ + 1040|ICCBRAMQ + 137|mA|
|XCKU095|ICCINTQ + ICCINT_IOQ + 3300|ICCO_0Q + 40|ICCAUXQ + ICCAUX_IOQ + 400|ICCBRAMQ + 150|mA|
|XCKU115|ICCINTQ + ICCINT_IOQ + 6568|ICCO_0Q + 274|ICCAUXQ + ICCAUX_IOQ + 1040|ICCBRAMQ + 137|mA|
|XQKU040|ICCINTQ + ICCINT_IOQ + 2400|ICCO_0Q + 100|ICCAUXQ + ICCAUX_IOQ + 380|ICCBRAMQ + 50|mA|
|XQKU060|ICCINTQ + ICCINT_IOQ + 3284|ICCO_0Q + 137|ICCAUXQ + ICCAUX_IOQ + 520|ICCBRAMQ + 100|mA|
|XQKU095|ICCINTQ + ICCINT_IOQ + 3300|ICCO_0Q + 40|ICCAUXQ + ICCAUX_IOQ + 400|ICCBRAMQ + 150|mA|
|XQKU115|ICCINTQ + ICCINT_IOQ + 6568|ICCO_0Q + 274|ICCAUXQ + ICCAUX_IOQ + 1040|ICCBRAMQ + 137|mA|
Table 8 shows the power supply ramp time.
_Table 8:_ **Power Supply Ramp Time**
|**Symbol**|**Description**|**Min**|**Max**|**Units**|
|---|---|---|---|---|
|TVCCINT|Ramp time from GND to 95% of VCCINT|0.2|40|ms|
|TVCCINT_IO|Ramp time from GND to 95% of VCCINT_IO|0.2|40|ms|
|TVCCO|Ramp time from GND to 95% of VCCO|0.2|40|ms|
|TVCCAUX|Ramp time from GND to 95% of VCCAUX|0.2|40|ms|
|TVCCBRAM|Ramp time from GND to 95% of VCCBRAM|0.2|40|ms|
|TMGTAVCC|Ramp time from GND to 95% of VMGTAVCC|0.2|40|ms|
|TMGTAVTT|Ramp time from GND to 95% of VMGTAVTT|0.2|40|ms|
|TMGTVCCAUX|Ramp time from GND to 95% of VMGTVCCAUX|0.2|40|ms|
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
## **DC Input and Output Levels**
Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the recommended operating conditions at the VOL and VOH test points. Only selected standards are tested. These are chosen to ensure that all standards meet their specifications. The selected standards are tested at a minimum VCCO with the respective VOL and VOH voltage levels shown. Other standards are sample tested.
_Table 9:_ **SelectIO DC Input and Output Levels For HR I/O Banks[(1)(2)]**
|**I/O**<br>**Standard**|**VIL**|**VIL**|**VIH**|**VIH**|**VOL**|**VOH**|**IOL**|**IOH**|
|---|---|---|---|---|---|---|---|---|
||**V, Min**|**V, Max**|**V, Min**|**V, Max**|**V, Max**|**V, Min**|**mA**|**mA**|
|HSTL_I|–0.300|VREF – 0.100|VREF + 0.100|VCCO + 0.300|0.400|VCCO – 0.400|8.0|–8.0|
|HSTL_I_18|–0.300|VREF – 0.100|VREF + 0.100|VCCO + 0.300|0.400|VCCO – 0.400|8.0|–8.0|
|HSTL_II|–0.300|VREF – 0.100|VREF + 0.100|VCCO + 0.300|0.400|VCCO – 0.400|16.0|–16.0|
|HSTL_II_18|–0.300|VREF – 0.100|VREF + 0.100|VCCO + 0.300|0.400|VCCO – 0.400|16.0|–16.0|
|HSUL_12|–0.300|VREF – 0.130|VREF + 0.130|VCCO + 0.300|20% VCCO|80% VCCO|0.1|–0.1|
|LVCMOS12|–0.300|35% VCCO|65% VCCO|VCCO + 0.300|0.400|VCCO – 0.400|Note 3|Note 3|
|LVCMOS15|–0.300|35% VCCO|65% VCCO|VCCO + 0.300|0.450|VCCO – 0.450|Note 4|Note 4|
|LVCMOS18|–0.300|35% VCCO|65% VCCO|VCCO + 0.300|0.450|VCCO – 0.450|Note 4|Note 4|
|LVCMOS25|–0.300|0.700|1.700|VCCO + 0.300|0.400|VCCO – 0.400|Note 4|Note 4|
|LVCMOS33|–0.300|0.800|2.000|3.400|0.400|VCCO – 0.400|Note 4|Note 4|
|LVTTL|–0.300|0.800|2.000|3.400|0.400|2.400|Note 4|Note 4|
|SSTL12|–0.300|VREF – 0.100|VREF + 0.100|VCCO + 0.300|VCCO/2 – 0.150|VCCO/2 + 0.150|14.25|–14.25|
|SSTL135|–0.300|VREF – 0.090|VREF + 0.090|VCCO + 0.300|VCCO/2 – 0.150|VCCO/2 + 0.150|13.0|–13.0|
|SSTL135_R|–0.300|VREF – 0.090|VREF + 0.090|VCCO + 0.300|VCCO/2 – 0.150|VCCO/2 + 0.150|8.9|–8.9|
|SSTL15|–0.300|VREF – 0.100|VREF + 0.100|VCCO + 0.300|VCCO/2 – 0.175|VCCO/2 + 0.175|13.0|–13.0|
|SSTL15_R|–0.300|VREF – 0.100|VREF + 0.100|VCCO + 0.300|VCCO/2 – 0.175|VCCO/2 + 0.175|8.9|–8.9|
|SSTL18_I|–0.300|VREF – 0.125|VREF + 0.125|VCCO + 0.300|VCCO/2 – 0.470|VCCO/2 + 0.470|8.0|–8.0|
|SSTL18_II|–0.300|VREF – 0.125|VREF + 0.125|VCCO + 0.300|VCCO/2 – 0.600|VCCO/2 + 0.600|13.4|–13.4|
## **Notes:**
1. Tested according to relevant specifications.
2. Standards specified using the default I/O standard configuration. For details, see the _UltraScale Architecture SelectIO Resources User Guide_ (UG571).
3. Supported drive strengths of 4, 8, or 12 mA in HR I/O banks.
4. Supported drive strengths of 4, 8, 12, or 16 mA in HR I/O banks.
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 10:_ **SelectIO DC Input and Output Levels for HP I/O Banks[(1)(2)(3)]**
|**I/O**<br>**Standard**|**VIL**|**VIL**|**VIH**|**VIH**|**VOL**|**VOH**|**IOL**|**IOH**|
|---|---|---|---|---|---|---|---|---|
||**V, Min**|**V, Max**|**V, Min**|**V, Max**|**V, Max**|**V, Min**|**mA**|**mA**|
|HSTL_I|–0.300|VREF – 0.100|VREF + 0.100|VCCO + 0.300|0.400|VCCO – 0.400|5.8|–5.8|
|HSTL_I_12|–0.300|VREF – 0.080|VREF + 0.080|VCCO + 0.300|25% VCCO|75% VCCO|4.1|–4.1|
|HSTL_I_18|–0.300|VREF – 0.100|VREF + 0.100|VCCO + 0.300|0.400|VCCO – 0.400|6.2|–6.2|
|HSUL_12|–0.300|VREF – 0.130|VREF + 0.130|VCCO + 0.300|20% VCCO|80% VCCO|0.1|–0.1|
|LVCMOS12|–0.300|35% VCCO|65% VCCO|VCCO + 0.300|0.400|VCCO – 0.400|Note 4|Note 4|
|LVCMOS15|–0.300|35% VCCO|65% VCCO|VCCO + 0.300|0.450|VCCO – 0.450|Note 5|Note 5|
|LVCMOS18|–0.300|35% VCCO|65% VCCO|VCCO + 0.300|0.450|VCCO – 0.450|Note 5|Note 5|
|LVDCI_15|–0.300|35% VCCO|65% VCCO|VCCO + 0.300|0.450|VCCO – 0.450|7.0|–7.0|
|LVDCI_18|–0.300|35% VCCO|65% VCCO|VCCO + 0.300|0.450|VCCO – 0.450|7.0|–7.0|
|SSTL12|–0.300|VREF – 0.100|VREF + 0.100|VCCO + 0.300|VCCO/2 – 0.150|VCCO/2 + 0.150|8.0|–8.0|
|SSTL135|–0.300|VREF – 0.090|VREF + 0.090|VCCO + 0.300|VCCO/2 – 0.150|VCCO/2 + 0.150|9.0|–9.0|
|SSTL15|–0.300|VREF – 0.100|VREF + 0.100|VCCO + 0.300|VCCO/2 – 0.175|VCCO/2 + 0.175|10.0|–10.0|
|SSTL18_I|–0.300|VREF – 0.125|VREF + 0.125|VCCO + 0.300|VCCO/2 – 0.470|VCCO/2 + 0.470|7.0|–7.0|
## **Notes:**
1. Tested according to relevant specifications.
2. Standards specified using the default I/O standard configuration. For details, see the _UltraScale Architecture SelectIO Resources User Guide_ (UG571).
3. POD10 and POD12 DC input and output levels are shown in Table 11, Table 16, and Table 17.
4. Supported drive strengths of 2, 4, 6, or 8 mA in HP I/O banks.
5. Supported drive strengths of 2, 4, 6, 8, or 12 mA in HP I/O banks.
_Table 11:_ **DC Input Levels for Single-ended POD10 and POD12 I/O Standards[(1)(2)]**
|**I/O**<br>**Standard**|**VIL**|**VIL**|**VIH**|**VIH**|
|---|---|---|---|---|
||**V, Min**|**V, Max**|**V, Min**|**V, Max**|
|POD10|–0.300|VREF – 0.068|VREF + 0.068|VCCO + 0.300|
|POD12|–0.300|VREF – 0.068|VREF + 0.068|VCCO + 0.300|
## **Notes:**
1. Tested according to relevant specifications.
2. Standards specified using the default I/O standard configuration. For details, see the _UltraScale Architecture SelectIO Resources User Guide_ (UG571).
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 12:_ **Differential SelectIO DC Input and Output Levels**
|**I/O**<br>**Standard**|**VICM(V)(1)**|**VICM(V)(1)**|**VICM(V)(1)**|**VID(V)(2)**|**VID(V)(2)**|**VID(V)(2)**|**VOCM(V)(3)**|**VOCM(V)(3)**|**VOCM(V)(3)**|**VOD(V)(4)**|**VOD(V)(4)**|**VOD(V)(4)**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
||**Min**|**Typ**|**Max**|**Min**|**Typ**|**Max**|**Min**|**Typ**|**Max**|**Min**|**Typ**|**Max**|
|BLVDS_25|0.300|1.200|1.425|0.100|–|–|–|1.250|–|Note 5|||
|MINI_LVDS_25|0.300|1.200|VCCAUX|0.200|0.400|0.600|1.000|1.200|1.485|0.300|0.450|0.600|
|SUB_LVDS|0.500|0.900|1.300|0.070|–|–|0.700|0.900|1.100|0.100|0.150|0.200|
|LVPECL|0.300|1.200|1.425|0.100|0.350|0.600|–|–|–|–|–|–|
|PPDS_25|0.200|0.900|VCCAUX|0.100|0.250|0.400|0.500|0.950|1.400|0.100|0.250|0.400|
|RSDS_25|0.300|0.900|1.500|0.100|0.350|0.600|1.000|1.200|1.485|0.100|0.350|0.600|
|SLVS_400_18|0.070|0.200|0.330|0.140|–|0.450|–|–|–|–|–|–|
|SLVS_400_25|0.070|0.200|0.330|0.140|–|0.450|–|–|–|–|–|–|
|TMDS_33|2.700|2.965|3.230|0.150|0.675|1.200|VCCO– 0.405|VCCO– 0.300|VCCO– 0.190|0.400|0.600|0.800|
## **Notes:**
1. VICM is the input common mode voltage.
2. VID is the input differential voltage (Q – Q).
3. VOCM is the output common mode voltage.
4. VOD is the output differential voltage (Q – Q).
5. VOD for BLVDS will vary significantly depending on topology and loading.
6. LVDS_25 is specified in Table 18.
7. LVDS is specified in Table 19.
_Table 13:_ **Complementary Differential SelectIO DC Input and Output Levels for HR I/O Banks**
|**I/O Standard**|**VICM(V)(1)**|**VICM(V)(1)**|**VICM(V)(1)**|**VID (V)(2)**|**VID (V)(2)**|**VOL(V)(3)**|**VOH(V)(4)**|**IOL**|**IOH**|
|---|---|---|---|---|---|---|---|---|---|
||**Min**|**Typ**|**Max**|**Min**|**Max**|**Max**|**Min**|**mA**|**mA**|
|DIFF_HSTL_I|0.300|0.750|1.125|0.100|–|0.400|VCCO – 0.400|8.0|–8.0|
|DIFF_HSTL_I_18|0.300|0.900|1.425|0.100|–|0.400|VCCO – 0.400|8.0|–8.0|
|DIFF_HSTL_II|0.300|0.750|1.125|0.100|–|0.400|VCCO – 0.400|16.0|–16.0|
|DIFF_HSTL_II_18|0.300|0.900|1.425|0.100|–|0.400|VCCO – 0.400|16.0|–16.0|
|DIFF_HSUL_12|0.300|0.600|0.850|0.100|–|20% VCCO|80% VCCO|0.1|–0.1|
|DIFF_SSTL12|0.300|0.600|0.850|0.100|–|(VCCO/2) – 0.150|(VCCO/2) + 0.150|14.25|–14.25|
|DIFF_SSTL135|0.300|0.675|1.000|0.100|–|(VCCO/2) – 0.150|(VCCO/2) + 0.150|13.0|–13.0|
|DIFF_SSTL135_R|0.300|0.675|1.000|0.100|–|(VCCO/2) – 0.150|(VCCO/2) + 0.150|8.9|–8.9|
|DIFF_SSTL15|0.300|0.750|1.125|0.100|–|(VCCO/2) – 0.175|(VCCO/2) + 0.175|13.0|–13.0|
|DIFF_SSTL15_R|0.300|0.750|1.125|0.100|–|(VCCO/2) – 0.175|(VCCO/2) + 0.175|8.9|–8.9|
|DIFF_SSTL18_I|0.300|0.900|1.425|0.100|–|(VCCO/2) – 0.470|(VCCO/2) + 0.470|8.0|–8.0|
|DIFF_SSTL18_II|0.300|0.900|1.425|0.100|–|(VCCO/2) – 0.600|(VCCO/2) + 0.600|13.4|–13.4|
## **Notes:**
1. VICM is the input common mode voltage.
2. VID is the input differential voltage.
3. VOL is the single-ended low-output voltage.
4. VOH is the single-ended high-output voltage.
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 14:_ **Complementary Differential SelectIO DC Input and Output Levels for HP I/O Banks[(1)]**
|**I/O Standard**|**VICM(V)(2)**|**VICM(V)(2)**|**VICM(V)(2)**|**VID (V)(3)**|**VID (V)(3)**|**VOL(V)(4)**|**VOH(V)(5)**|**IOL**|**IOH**|
|---|---|---|---|---|---|---|---|---|---|
||**Min**|**Typ**|**Max**|**Min**|**Max**|**Max**|**Min**|**mA**|**mA**|
|DIFF_HSTL_I|0.680|VCCO/2|(VCCO/2) + 0.150|0.100|–|0.400|VCCO – 0.400|5.8|–5.8|
|DIFF_HSTL_I_12|0.400 x VCCO|VCCO/2|0.600 x VCCO|0.100|–|0.250 x VCCO|0.750 x VCCO|4.1|–4.1|
|DIFF_HSTL_I_18|(VCCO/2) – 0.175|VCCO/2|(VCCO/2) + 0.175|0.100|–|0.400|VCCO – 0.400|6.2|–6.2|
|DIFF_HSUL_12|(VCCO/2) – 0.120|VCCO/2|(VCCO/2) + 0.120|0.100|–|20% VCCO|80% VCCO|0.1|–0.1|
|DIFF_SSTL12|(VCCO/2) – 0.150|VCCO/2|(VCCO/2) + 0.150|0.100|–|(VCCO/2) – 0.150|(VCCO/2) + 0.150|8.0|–8.0|
|DIFF_SSTL135|(VCCO/2) – 0.150|VCCO/2|(VCCO/2) + 0.150|0.100|–|(VCCO/2) – 0.150|(VCCO/2) + 0.150|9.0|–9.0|
|DIFF_SSTL15|(VCCO/2) – 0.175|VCCO/2|(VCCO/2) + 0.175|0.100|–|(VCCO/2) – 0.175|(VCCO/2) + 0.175|10.0|–10.0|
|DIFF_SSTL18_I|(VCCO/2) – 0.175|VCCO/2|(VCCO/2) + 0.175|0.100|–|(VCCO/2) – 0.470|(VCCO/2) + 0.470|7.0|–7.0|
## **Notes:**
1. DIFF_POD10 and DIFF_POD12 HP I/O bank specifications are shown in Table 15, Table 16, and Table 17.
2. VICM is the input common mode voltage.
3. VID is the input differential voltage.
4. VOL is the single-ended low-output voltage.
5. VOH is the single-ended high-output voltage.
_Table 15:_ **DC Input Levels for Differential POD10 and POD12 I/O Standards[(1)(2)]**
|**I/O Standard**|**VICM(V)**|**VICM(V)**|**VICM(V)**|**VID (V)**|**VID (V)**|
|---|---|---|---|---|---|
||**Min**|**Typ**|**Max**|**Min**|**Max**|
|DIFF_POD10|0.63|0.70|0.77|0.14|–|
|DIFF_POD12|0.76|0.84|0.92|0.16|–|
## **Notes:**
1. Tested according to relevant specifications.
2. Standards specified using the default I/O standard configuration. For details, see the _UltraScale Architecture SelectIO Resources User Guide_ (UG571).
_Table 16:_ **DC Output Levels for Single-ended and Differential POD10 and POD12 Standards[(1)(2)]**
|**Symbol**|**Description**|**VOUT**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|ROL|Pull-down resistance|VOM_DC(as described inTable 17)|36|40|44|Ω|
|ROH|Pull-up resistance|VOM_DC(as described inTable 17)|36|40|44|Ω|
## **Notes:**
1. Tested according to relevant specifications.
2. Standards specified using the default I/O standard configuration. For details, see the _UltraScale Architecture SelectIO Resources User Guide_ (UG571).
_Table 17:_ **Table 16 Definitions for DC Output Levels for POD Standards**
|**Symbol**|**Description**|**All Devices**|**Units**|
|---|---|---|---|
|VOM_DC|DC output Mid measurement level (for IV curve linearity)|0.8 x VCCO|V|
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
## **LVDS DC Specifications (LVDS_25)**
The LVDS_25 standard is available in the HR I/O banks. See the _UltraScale Architecture SelectIO Resources User Guide_ (UG571) for more information.
_Table 18:_ **LVDS_25 DC Specifications**
|**Symbol**|**DC Parameter**|**Conditions**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|VCCO|Supply voltage||2.375|2.500|2.625|V|
|VODIFF(1)|Differential Output Voltage:<br>(Q – Q<br>),Q = High<br>(Q<br>– Q), Q<br>= High|RT = 100Ωacross Q and Q<br>signals|247|350|600|mV|
|VOCM(1)|Output Common-Mode Voltage|RT = 100Ωacross Q and Q<br>signals|1.000|1.250|1.485|V|
|VIDIFF|Differential Input Voltage:<br>(Q – Q<br>),Q = High<br>(Q<br>– Q), Q<br>= High||100|350|600(2)|mV|
|VICM_DC(3)|Input Common-Mode Voltage (DC Coupling)||0.300|1.200|1.500|V|
|VICM_AC(4)|Input Common-Mode Voltage (AC Coupling)||0.600|–|1.100|V|
## **Notes:**
1. VOCM and VODIFF values are for LVDS_PRE_EMPHASIS = FALSE.
2. Maximum VIDIFF value is specified for the maximum VICM specification. With a lower VICM, a higher VDIFF is tolerated only when the recommended operating conditions and overshoot/undershoot VIN specifications are maintained.
3. Input common mode voltage for DC coupled configurations. EQUALIZATION = EQ_NONE (Default).
4. External input common mode voltage specification for AC coupled configurations. EQUALIZATION = EQ_LEVEL0, EQ_LEVEL1, EQ_LEVEL2, EQ_LEVEL3, EQ_LEVEL4.
## **LVDS DC Specifications (LVDS)**
The LVDS standard is available in the HP I/O banks. See the _UltraScale Architecture SelectIO Resources User Guide_ (UG571) for more information.
_Table 19:_ **LVDS DC Specifications**
|**Symbol**|**DC Parameter**|**Conditions**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|VCCO|Supply voltage||1.710|1.800|1.890|V|
|VODIFF(1)|Differential Output Voltage<br>(Q – Q<br>),Q = High<br>(Q<br>– Q), Q<br>= High|RT = 100Ωacross Q and Q<br>signals|247|350|600|mV|
|VOCM(1)|Output Common-Mode Voltage|RT = 100Ωacross Q and Q<br>signals|1.000|1.250|1.425|V|
|VIDIFF|Differential Input Voltage<br>(Q – Q<br>),Q = High<br>(Q<br>– Q), Q<br>= High||100|350|600(2)|mV|
|VICM_DC(3)|Input Common-Mode Voltage (DC Coupling)||0.300|1.200|1.425|V|
|VICM_AC(4)|Input Common-Mode Voltage (AC Coupling)||0.600|–|1.100|V|
## **Notes:**
1. VOCM and VODIFF values are for LVDS_PRE_EMPHASIS = FALSE.
2. Maximum VIDIFF value is specified for the maximum VICM specification. With a lower VICM, a higher VDIFF is tolerated only when the recommended operating conditions and overshoot/undershoot VIN specifications are maintained.
3. Input common mode voltage for DC coupled configurations. EQUALIZATION = EQ_NONE (Default).
4. External input common mode voltage specification for AC coupled configurations. EQUALIZATION = EQ_LEVEL0, EQ_LEVEL1, EQ_LEVEL2, EQ_LEVEL3, EQ_LEVEL4.
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
## **AC Switching Characteristics**
All values represented in this data sheet are based on the speed specifications in the Vivado® Design Suite as outlined in Table 20.
_Table 20:_ **Speed Specification Version By Device**
|**2016.4**|**Device**|
|---|---|
|1.23|XCKU025, XCKU035, XCKU040, XCKU060, XQKU040, XQKU060|
|1.24|XCKU085, XCKU095, XCKU115, XQKU095, XQKU115|
Switching characteristics are specified on a per-speed-grade basis and can be designated as Advance, Preliminary, or Production. Each designation is defined as follows:
## **Advance Product Specification**
These specifications are based on simulations only and are typically available soon after device design specifications are frozen. Although speed grades with this designation are considered relatively stable and conservative, some under-reporting might still occur.
## **Preliminary Product Specification**
These specifications are based on complete ES (engineering sample) silicon characterization. Devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon. The probability of under-reporting delays is greatly reduced as compared to Advance data.
## **Product Specification**
These specifications are released once enough production silicon of a particular device family member has been characterized to provide full correlation between specifications and devices over numerous production lots. There is no under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest speed grades transition to production before faster speed grades.
## **Testing of AC Switching Characteristics**
Internal timing parameters are derived from measuring internal test patterns. All AC switching characteristics are representative of worst-case supply voltage and junction temperature conditions.
For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer and back-annotate to the simulation net list. Unless otherwise noted, values apply to all Kintex UltraScale FPGAs.
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
## **Speed Grade Designations**
Since individual family members are produced at different times, the migration from one category to another depends completely on the status of the fabrication process for each device. Table 21 correlates the current status of the Kintex UltraScale FPGAs on a per speed grade basis.
_Table 21:_ **Speed Grade Designations by Device**
|_Table 21:_|**Speed Grade Designations by Device**|**Speed Grade Designations by Device**|**Speed Grade Designations by Device**|
|---|---|---|---|
|**Device**|**Speed Grade and VCCINT Operating Voltages**|||
||**Advance**|**Preliminary**|**Production**|
|XCKU025|||-2 (0.95V) and -1 (0.95V)|
|XCKU035|||-3 (1.0V), -2 (0.95V), -1 (0.95V), -1L (0.95V), and<br>-1L (0.90V)(1)|
|XCKU040|||-3 (1.0V), -2 (0.95V), -1 (0.95V), -1L (0.95V), and<br>-1L (0.90V)(1)|
|XCKU060|||-3 (1.0V), -2 (0.95V), -1 (0.95V), -1L (0.95V), and<br>-1L (0.90V)(1)|
|XCKU085|||-3 (1.0V), -2 (0.95V), -1 (0.95V), -1L (0.95V), and<br>-1L (0.90V)(1)|
|XCKU095|||-2 (0.95V) and -1 (0.95V)|
|XCKU115|||-3 (1.0V), -2 (0.95V), -1 (0.95V), -1L (0.95V), and<br>-1L (0.90V)(1)|
|XQKU040|||-2 (0.95V) and -1 (0.95V)|
|XQKU060|||-2 (0.95V) and -1 (0.95V)|
|XQKU095|||-2 (0.95V) and -1 (0.95V)|
|XQKU115|||-2 (0.95V) and -1 (0.95V)|
## **Notes:**
1. The lowest power -1L devices, where VCCINT = 0.90V, are listed in the Vivado Design Suite as -1LV.
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
## **Production Silicon and Software Status**
In some cases, a particular family member (and speed grade) is released to production before a speed specification is released with the correct label (Advance, Preliminary, Production). Any labeling discrepancies are corrected in subsequent speed specification releases.
Table 22 lists the production released Kintex UltraScale FPGAs, speed grade, and the minimum corresponding supported speed specification version and Vivado software revisions. The Vivado software and speed specifications listed are the minimum releases required for production. All subsequent releases of software and speed specifications are valid.
_Table 22:_ **Kintex UltraScale FPGAs Production Software and Speed Specification Release[(1)]**
|**Device**|**Speed Grade, Temperature Ranges, and VCCINT Operating Voltages**|**Speed Grade, Temperature Ranges, and VCCINT Operating Voltages**|**Speed Grade, Temperature Ranges, and VCCINT Operating Voltages**|**Speed Grade, Temperature Ranges, and VCCINT Operating Voltages**|**Speed Grade, Temperature Ranges, and VCCINT Operating Voltages**|**Speed Grade, Temperature Ranges, and VCCINT Operating Voltages**|
|---|---|---|---|---|---|---|
||**1.0V**|**0.95V**||||**0.90V**|
||**-3E**|**-2E, -2I**|**-1C, -1I**|**-1M**|**-1LI**|**-1LI(3)**|
|XCKU025(2)|N/A|Vivado Tools 2015.3 v1.23||N/A|N/A|N/A|
|XCKU035(2)|Vivado Tools 2015.2.1<br>v1.23 for FBVA676 and<br>FFVA1156 packages|Vivado Tools 2015.1 v1.23 for<br>FBVA676 and FFVA1156 packages||N/A|Vivado Tools 2015.3 v1.23||
||Vivado Tools 2015.3 v1.23 for FBVA900|||N/A|||
||Vivado Tools 2015.4 v1.23 for SFVA784|||N/A|Vivado Tools 2015.4 v1.23 for<br>SFVA784||
|XCKU040(2)|Vivado Tools 2015.2.1<br>v1.23 for FBVA676 and<br>FFVA1156 packages|Vivado Tools 2015.1 v1.23 for<br>FBVA676 and FFVA1156 packages||N/A|Vivado Tools 2015.3 v1.23||
||Vivado Tools 2015.3 v1.23 for FBVA900|||N/A|||
||Vivado Tools 2015.4 v1.23 for SFVA784|||N/A|Vivado Tools 2015.4 v1.23 for<br>SFVA784||
|XCKU060(2)|Vivado Tools 2015.4 v1.23|Vivado Tools 2015.2 v1.23||N/A|Vivado Tools<br>2015.3 v1.23|Vivado Tools<br>2015.4 v1.23|
|XCKU085(2)|Vivado Tools 2015.4 v1.24|Vivado Tools 2015.3 v1.24||N/A|Vivado Tools 2016.1 v1.24||
|XCKU095|N/A|Vivado Tools 2015.3 v1.24||N/A|N/A|N/A|
|XCKU115(2)|Vivado Tools 2015.4 v1.24|Vivado Tools 2015.2.1 v1.24||N/A|Vivado Tools 2016.1 v1.24||
|XQKU040|N/A|Vivado Tools 2016.4 v1.23|||N/A|N/A|
|XQKU060|N/A|Vivado Tools 2016.4 v1.23|||N/A|N/A|
|XQKU095|N/A|Vivado Tools 2016.4 v1.24|||N/A|N/A|
|XQKU115|N/A|Vivado Tools 2016.4 v1.24||N/A|N/A|N/A|
## **Notes:**
1. For designs developed using Vivado tools prior to 2016.4, see the design advisory answer record AR68169: _Design Advisory for Kintex UltraScale FPGAs and Virtex UltraScale FPGAs—New minimum production speed specification version (Speed File) required for all designs_ .
2. Designs with these devices that use the dedicated System Monitor I2C (I2C_SCL and I2C_SDA) or PCIe reset (PERSTN0 or PERSTN1) I/O where the bank 65 VCCO = 3.3V must use Vivado Design Suite 2015.4 or later.
3. The lowest power -1L devices, where VCCINT = 0.90V, are listed in the Vivado Design Suite as -1LV.
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
## **Performance Characteristics**
This section provides the performance characteristics of some common functions and designs implemented in Kintex UltraScale FPGAs. These values are subject to the same guidelines as the AC Switching Characteristics, page 17. In each table, the I/O bank type is either high performance (HP) or high range (HR).
_Table 23:_ **LVDS Component Mode Performance**
|**Description**|**I/O**<br>**Bank**<br>**Type**|**Speed Grade and VCCINT Operating Voltages**|**Speed Grade and VCCINT Operating Voltages**|**Speed Grade and VCCINT Operating Voltages**|**Speed Grade and VCCINT Operating Voltages**|**Speed Grade and VCCINT Operating Voltages**|**Speed Grade and VCCINT Operating Voltages**|**Speed Grade and VCCINT Operating Voltages**|**Speed Grade and VCCINT Operating Voltages**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|
|||**1.0V**||**0.95V**||||**0.90V**|||
|||**-3**||**-2**||**-1/-1L**||**-1L**|||
|||**Min**|**Max**|**Min**|**Max**|**Min**|**Max**|**Min**|**Max**||
|LVDS TX DDR (OSERDES 4:1, 8:1)|HP|0|1250|0|1250|0|1250|0|1250|Mb/s|
||HR|0|1250|0|1250|0|1000|0|1000|Mb/s|
|LVDS TX SDR (OSERDES 2:1, 4:1)|HP|0|625|0|625|0|625|0|625|Mb/s|
||HR|0|625|0|625|0|500|0|500|Mb/s|
|LVDS RX DDR (ISERDES 1:4, 1:8)(1)|HP|0|1250|0|1250|0|1250|0|1250|Mb/s|
||HR|0|1250|0|1250|0|1000|0|1000|Mb/s|
|LVDS RX SDR (ISERDES 1:2, 1:4)(1)|HP|0|625|0|625|0|625|0|625|Mb/s|
||HR|0|625|0|625|0|500|0|500|Mb/s|
## **Notes:**
1. LVDS receivers are typically bounded with certain applications where specific dynamic phase-alignment (DPA) or phase-tracking algorithms are used to achieve maximum performance.
_Table 24:_ **LVDS Native Mode Performance[(1)]**
|**Description**|**I/O**<br>**Bank**<br>**Type**|**Speed Grade and VCCINT Operating Voltages**|**Speed Grade and VCCINT Operating Voltages**|**Speed Grade and VCCINT Operating Voltages**|**Speed Grade and VCCINT Operating Voltages**|**Speed Grade and VCCINT Operating Voltages**|**Speed Grade and VCCINT Operating Voltages**|**Speed Grade and VCCINT Operating Voltages**|**Speed Grade and VCCINT Operating Voltages**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|
|||**1.0V**||**0.95V**||||**0.90V**|||
|||**-3**||**-2**||**-1/-1L**||**-1L**|||
|||**Min**|**Max**|**Min**|**Max**|**Min**|**Max**|**Min**|**Max**||
|LVDS TX DDR (TX_BITSLICE 4:1, 8:1)|HP|300|1600|300|1600|300|1400|300|1400|Mb/s|
||HR|300|1250|300|1250|300|1250|300|1250|Mb/s|
|LVDS TX SDR (TX_BITSLICE 2:1, 4:1)|HP|150|800|150|800|150|700|150|700|Mb/s|
||HR|150|625|150|625|150|625|150|625|Mb/s|
|LVDS RX DDR (RX_BITSLICE 1:4, 1:8)(2)|HP|300|1600|300|1600|300|1400|300|1400|Mb/s|
||HR|300|1250|300|1250|300|1250|300|1250|Mb/s|
|LVDS RX SDR (RX_BITSLICE 1:2, 1:4)(2)|HP|150|800|150|800|150|700|150|700|Mb/s|
||HR|150|625|150|625|150|625|150|625|Mb/s|
## **Notes:**
1. Native mode is supported through the High-Speed SelectIO Interface Wizard available with the Vivado Design Suite.
2. LVDS receivers are typically bounded with certain applications where specific dynamic phase-alignment (DPA) or phase-tracking algorithms are used to achieve maximum performance.
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 25:_ **LVDS Native-Mode 1000BASE-X Support[(1)]**
|**Description**|**I/O Bank Type**|**Speed Grade and VCCINT Operating Voltages**|**Speed Grade and VCCINT Operating Voltages**|**Speed Grade and VCCINT Operating Voltages**|**Speed Grade and VCCINT Operating Voltages**|
|---|---|---|---|---|---|
|||**1.0V**|**0.95V**||**0.90V**|
|||**-3**|**-2**|**-1/-1L**|**-1L**|
|1000BASE-X|HP|Yes|Yes|Yes|Yes|
## **Notes:**
1. 1000BASE-X support is based on the _IEEE Standard for CSMA/CD Access Method and Physical Layer Specifications_ (IEEE Std 802.3-2008).
Table 26 provides the maximum data rates for applicable memory standards using the Kintex UltraScale FPGAs memory PHY. Refer to Memory Interfaces for the complete list of memory interface standards supported and detailed specifications. The final performance of the memory interface is determined through a complete design implemented in the Vivado Design Suite, following guidelines in the _UltraScale Architecture PCB Design Guide_ (UG583), electrical analysis, and characterization of the system.
_Table 26:_ **Maximum Physical Interface (PHY) Rate for Memory Interfaces by I/O and Package**
|**Memory**<br>**Standard**|**I/O**<br>**Bank**<br>**Type**|**Package**|**DRAM Type**|**Speed Grade, Temperature Ranges,**<br>**and VCCINT Operating Voltages**|**Speed Grade, Temperature Ranges,**<br>**and VCCINT Operating Voltages**|**Speed Grade, Temperature Ranges,**<br>**and VCCINT Operating Voltages**|**Speed Grade, Temperature Ranges,**<br>**and VCCINT Operating Voltages**|**Speed Grade, Temperature Ranges,**<br>**and VCCINT Operating Voltages**|**Units**|
|---|---|---|---|---|---|---|---|---|---|
|||||**1.0V**|**0.95V**|||**0.90V**||
|||||**-3E**|**-2E**|**-2I**|**-1C/I**<br>**-1M**<br>**-1LI**|**-1LI**||
|DDR4|HP|All FF/RF packages<br>All FL packages<br>FBVA900|Single rank<br>component|2400|2400|2400|2133|2133|Mb/s|
||||1 rank DIMM(1)(2)|2133|2133|2133|1866|1866||
||||2 rank DIMM(1)(3)|1866|1866|1866|1600|1600||
||||4 rank DIMM(1)(4)|1333|1333|1333|N/A|N/A||
|||FBVA676<br>RBA676<br>SFVA784|Single rank<br>component|2133|2133|2133|1866|1866||
||||1 rank DIMM(1)(2)|1866|1866|1866|1600|1600||
||||2 rank DIMM(1)(3)|1600|1600|1600|1333|1333||
|DDR3|HP|All FF/RF packages<br>All FL packages<br>FBVA676<br>RBA676<br>FBVA900|Single rank<br>component|2133|2133|2133|1866|1866|Mb/s|
||||1 rank DIMM(1)(2)|1866|1866|1866|1600|1600||
||||2 rank DIMM(1)(3)|1600|1600|1600|1333|1333||
||||4 rank DIMM(1)(4)|1066|1066|1066|800|800||
|||SFVA784|Single rank<br>component|1866|1866|1866|1600|1600||
||||1 rank DIMM(1)(2)|1600|1600|1600|1333|1333||
||||2 rank DIMM(1)(3)|1333|1333|1333|1066|1066||
||||4 rank DIMM(1)(4)|800|800|800|606|606||
||HR|All|Single rank<br>component|1333(5)|||1066|1066||
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 26:_ **Maximum Physical Interface (PHY) Rate for Memory Interfaces by I/O and Package**
|**Memory**<br>**Standard**|**I/O**<br>**Bank**<br>**Type**|**Package**|**DRAM Type**|**Speed Grade, Temperature Ranges,**<br>**and VCCINT Operating Voltages**|**Speed Grade, Temperature Ranges,**<br>**and VCCINT Operating Voltages**|**Speed Grade, Temperature Ranges,**<br>**and VCCINT Operating Voltages**|**Speed Grade, Temperature Ranges,**<br>**and VCCINT Operating Voltages**|**Speed Grade, Temperature Ranges,**<br>**and VCCINT Operating Voltages**|**Units**|
|---|---|---|---|---|---|---|---|---|---|
|||||**1.0V**|**0.95V**|||**0.90V**||
|||||**-3E**|**-2E**|**-2I**|**-1C/I**<br>**-1M**<br>**-1LI**|**-1LI**||
|DDR3L|HP|All FF/RF packages<br>All FL packages<br>FBVA676<br>RBA676<br>FBVA900|Single rank<br>component|1866|1866|1866|1600|1600|Mb/s|
||||1 rank DIMM(1)(2)|1600|1600|1600|1333|1333||
||||2 rank DIMM(1)(3)|1333|1333|1333|1066|1066||
||||4 rank DIMM(1)(4)|800|800|800|606|606||
|||SFVA784|Single rank<br>component|1600|1600|1600|1600|1600||
||||1 rank DIMM(1)(2)|1333|1333|1333|1333|1333||
||||2 rank DIMM(1)(3)|1066|1066|1066|1066|1066||
||||4 rank DIMM(1)(4)|606|606|606|606|606||
||HR|All|Single rank<br>component|1066|1066|1066|800|800||
|QDR II+(6)|All|All|Single rank<br>component|633|600|600|550|550|MHz|
|QDRIV-XP|HP|All|Single rank<br>component|800|800|800|667|667||
|RLDRAM III|HP|All FF/RF packages<br>All FL packages<br>FBVA676<br>RBA676<br>FBVA900|Single rank<br>component|1066|1066|1066|933|933||
|||SFVA784||933|933|933|800|800||
|LPDDR3|HP|All|Single rank<br>component|1600|1600|1600|1600|1600|Mb/s|
||HR|All|Single rank<br>component|1066|1066|1066|1066|1066||
## **Notes:**
1. Dual in-line memory module (DIMM) includes RDIMM, SODIMM, UDIMM, and LRDIMM.
2. Includes: 1 rank 1 slot, DDP 2 rank, LRDIMM 2 or 4 rank 1 slot.
3. Includes: 2 rank 1 slot, 1 rank 2 slot, LRDIMM 2 rank 2 slot.
4. Includes: 2 rank 2 slot, 4 rank 1 slot.
5. Memory device must be rated at 1600 or above.
6. The QDRII+ performance specifications are for burst-length 4 (BL = 4) implementations.
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
## **IOB Pad Input, Output, and 3-State**
Table 27 (high-range IOB (HR)) and Table 28 (high-performance IOB (HP)) summarizes the values of standard-specific data input delay adjustments, output delays terminating at pads (based on standard) and 3-state delays.
- TINBUF_DELAY_PAD_I is the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The delay varies depending on the capability of the SelectIO input buffer.
- TOUTBUF_DELAY_O_PAD is the delay from the O pin to the IOB pad through the output buffer of an IOB pad. The delay varies depending on the capability of the SelectIO output buffer.
- TOUTBUF_DELAY_TD_PAD is the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is disabled. The delay varies depending on the SelectIO capability of the output buffer. In HP I/O banks, the internal DCI termination turn-on time is always faster than TOUTBUF_DELAY_TD_PAD when the DCITERMDISABLE pin is used. In HR I/O banks, the on-die termination turn-on time is always faster than TOUTBUF_DELAY_TD_PAD when the INTERMDISABLE pin is used.
_Table 27:_ **IOB High Range (HR) Switching Characteristics**
|**I/O Standards**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||**1.0V**|**0.95V**|||**0.9V **|**1.0V**|**0.95V**|||**0.9V **|**1.0V**|**0.95V**|||**0.9V**||
||**-3**|**-2**|**-1/**<br>**-1L**|**-1M**|**-1L**|**-3**|**-2**|**-1/**<br>**-1L**|**-1M**|**-1L**|**-3**|**-2**|**-1/**<br>**-1L**|**-1M**|**-1L**||
|BLVDS_25|0.46|0.58|0.64|0.64|0.64|1.37|1.37|1.62|1.62|1.62|1.39|1.40|1.66|1.66|1.66|ns|
|DIFF_HSTL_I_18_F|0.42|0.53|0.57|0.57|0.57|0.71|0.71|0.90|0.90|0.91|0.82|0.82|1.06|1.06|1.06|ns|
|DIFF_HSTL_I_18_S|0.42|0.53|0.57|0.57|0.57|0.83|0.83|1.02|1.02|1.03|0.93|0.94|1.16|1.16|1.16|ns|
|DIFF_HSTL_I_F|0.42|0.53|0.57|0.57|0.57|0.73|0.73|0.92|0.92|0.93|0.90|0.90|1.14|1.14|1.14|ns|
|DIFF_HSTL_I_S|0.42|0.53|0.57|0.57|0.57|0.77|0.77|0.96|0.96|0.96|0.95|0.98|1.23|1.23|1.23|ns|
|DIFF_HSTL_II_18_F|0.42|0.53|0.57|0.57|0.57|0.80|0.80|0.99|0.99|1.00|0.95|0.98|1.23|1.23|1.23|ns|
|DIFF_HSTL_II_18_S|0.42|0.53|0.57|0.57|0.57|0.83|0.83|1.03|1.03|1.03|1.01|1.03|1.28|1.28|1.28|ns|
|DIFF_HSTL_II_F|0.42|0.53|0.57|0.57|0.57|0.71|0.71|0.91|0.91|0.91|0.87|0.87|1.11|1.11|1.11|ns|
|DIFF_HSTL_II_S|0.42|0.53|0.57|0.57|0.57|0.80|0.80|0.99|0.99|0.99|0.95|0.96|1.20|1.20|1.20|ns|
|DIFF_HSUL_12_F|0.42|0.53|0.57|0.57|0.57|0.73|0.73|0.92|0.92|0.92|0.73|0.73|0.92|0.92|0.92|ns|
|DIFF_HSUL_12_S|0.42|0.53|0.57|0.57|0.57|0.82|0.82|1.01|1.01|1.02|0.82|0.82|1.01|1.01|1.02|ns|
|DIFF_SSTL12_F|0.42|0.53|0.57|0.57|0.57|0.70|0.70|0.89|0.89|0.89|0.81|0.81|1.02|1.02|1.02|ns|
|DIFF_SSTL12_S|0.42|0.53|0.57|0.57|0.57|1.04|1.04|1.26|1.26|1.26|1.04|1.04|1.26|1.26|1.26|ns|
|DIFF_SSTL135_F|0.42|0.53|0.57|0.57|0.57|0.70|0.70|0.88|0.88|0.88|0.86|0.87|1.09|1.09|1.09|ns|
|DIFF_SSTL135_S|0.42|0.53|0.57|0.57|0.57|0.77|0.77|0.96|0.96|0.96|0.93|0.94|1.18|1.18|1.18|ns|
|DIFF_SSTL135_R_F|0.42|0.53|0.57|0.57|0.57|0.72|0.72|0.91|0.91|0.91|0.83|0.84|1.06|1.06|1.06|ns|
|DIFF_SSTL135_R_S|0.42|0.53|0.57|0.57|0.57|0.80|0.80|1.00|1.00|1.00|0.93|0.93|1.17|1.17|1.17|ns|
|DIFF_SSTL15_F|0.42|0.53|0.57|0.57|0.57|0.66|0.66|0.85|0.85|0.85|0.81|0.82|1.05|1.05|1.05|ns|
|DIFF_SSTL15_S|0.42|0.53|0.57|0.57|0.57|0.78|0.78|0.98|0.98|0.98|0.96|0.96|1.20|1.20|1.21|ns|
|DIFF_SSTL15_R_F|0.42|0.53|0.57|0.57|0.57|0.73|0.73|0.92|0.92|0.92|0.86|0.86|1.09|1.09|1.09|ns|
|DIFF_SSTL15_R_S|0.42|0.53|0.57|0.57|0.57|0.81|0.81|1.01|1.01|1.02|0.93|0.94|1.18|1.18|1.18|ns|
|DIFF_SSTL18_I_F|0.42|0.53|0.57|0.57|0.57|0.74|0.74|0.94|0.94|0.94|0.92|0.93|1.18|1.18|1.19|ns|
|DIFF_SSTL18_I_S|0.42|0.53|0.57|0.57|0.57|0.86|0.86|1.05|1.05|1.06|0.86|0.86|1.05|1.05|1.06|ns|
|DIFF_SSTL18_II_F|0.42|0.53|0.57|0.57|0.57|0.71|0.71|0.90|0.90|0.90|0.87|0.88|1.11|1.11|1.12|ns|
|DIFF_SSTL18_II_S|0.42|0.53|0.57|0.57|0.57|0.83|0.83|1.03|1.03|1.03|0.99|1.04|1.29|1.29|1.30|ns|
DS892 (v1.14) February 2, 2017 **Product Specification**
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 27:_ **IOB High Range (HR) Switching Characteristics** _**(Cont’d)**_
|**I/O Standards**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||**1.0V**|**0.95V**|||**0.9V **|**1.0V**|**0.95V**|||**0.9V **|**1.0V**|**0.95V**|||**0.9V**||
||**-3**|**-2**|**-1/**<br>**-1L**|**-1M**|**-1L**|**-3**|**-2**|**-1/**<br>**-1L**|**-1M**|**-1L**|**-3**|**-2**|**-1/**<br>**-1L**|**-1M**|**-1L**||
|HSTL_I_18_F|0.52|0.55|0.59|0.59|0.59|0.73|0.73|0.93|0.93|0.93|0.84|0.84|1.08|1.08|1.08|ns|
|HSTL_I_18_S|0.52|0.55|0.59|0.59|0.59|0.85|0.85|1.05|1.05|1.05|0.95|0.96|1.18|1.18|1.18|ns|
|HSTL_I_F|0.52|0.55|0.59|0.59|0.59|0.75|0.75|0.94|0.94|0.95|0.92|0.92|1.16|1.16|1.17|ns|
|HSTL_I_S|0.52|0.55|0.59|0.59|0.59|0.79|0.79|0.98|0.98|0.99|0.97|1.00|1.25|1.25|1.25|ns|
|HSTL_II_18_F|0.52|0.55|0.59|0.59|0.59|0.82|0.82|1.01|1.01|1.02|0.97|1.00|1.25|1.25|1.25|ns|
|HSTL_II_18_S|0.52|0.55|0.59|0.59|0.59|0.85|0.85|1.05|1.05|1.05|1.03|1.05|1.30|1.30|1.30|ns|
|HSTL_II_F|0.52|0.55|0.59|0.59|0.59|0.73|0.73|0.93|0.93|0.93|0.89|0.90|1.13|1.13|1.13|ns|
|HSTL_II_S|0.52|0.55|0.59|0.59|0.59|0.82|0.82|1.01|1.01|1.02|0.98|0.98|1.22|1.22|1.22|ns|
|HSUL_12_F|0.52|0.55|0.59|0.59|0.59|0.75|0.75|0.94|0.94|0.95|0.75|0.75|0.94|0.94|0.95|ns|
|HSUL_12_S|0.52|0.55|0.59|0.59|0.59|0.84|0.84|1.04|1.04|1.04|0.96|0.97|1.15|1.15|1.15|ns|
|LVCMOS12_F_12|0.76|0.95|0.95|0.95|0.95|0.95|0.95|1.16|1.16|1.16|0.95|0.95|1.16|1.16|1.16|ns|
|LVCMOS12_F_4|0.76|0.95|0.95|0.95|0.95|1.13|1.16|1.39|1.39|1.39|1.13|1.16|1.39|1.39|1.39|ns|
|LVCMOS12_F_8|0.76|0.95|0.95|0.95|0.95|0.97|0.97|1.19|1.19|1.19|0.97|0.97|1.19|1.19|1.19|ns|
|LVCMOS12_S_12|0.76|0.95|0.95|0.95|0.95|1.06|1.06|1.28|1.28|1.28|1.06|1.06|1.28|1.28|1.28|ns|
|LVCMOS12_S_4|0.76|0.95|0.95|0.95|0.95|1.27|1.36|1.60|1.60|1.60|1.27|1.36|1.60|1.60|1.60|ns|
|LVCMOS12_S_8|0.76|0.95|0.95|0.95|0.95|1.10|1.10|1.32|1.32|1.32|1.10|1.10|1.32|1.32|1.32|ns|
|LVCMOS15_F_12|0.68|0.82|0.87|0.87|0.88|0.96|0.96|1.18|1.18|1.18|0.96|0.96|1.18|1.18|1.18|ns|
|LVCMOS15_F_16|0.68|0.82|0.87|0.87|0.88|0.94|0.94|1.15|1.15|1.15|0.94|0.94|1.17|1.17|1.17|ns|
|LVCMOS15_F_4|0.68|0.82|0.87|0.87|0.88|1.15|1.15|1.38|1.38|1.39|1.15|1.15|1.38|1.38|1.39|ns|
|LVCMOS15_F_8|0.68|0.82|0.87|0.87|0.88|1.02|1.02|1.24|1.24|1.24|1.02|1.02|1.24|1.24|1.24|ns|
|LVCMOS15_S_12|0.68|0.82|0.87|0.87|0.88|1.07|1.07|1.29|1.29|1.30|1.07|1.07|1.29|1.29|1.30|ns|
|LVCMOS15_S_16|0.68|0.82|0.87|0.87|0.88|1.04|1.04|1.26|1.26|1.27|1.04|1.04|1.26|1.26|1.27|ns|
|LVCMOS15_S_4|0.68|0.82|0.87|0.87|0.88|1.28|1.29|1.53|1.53|1.54|1.28|1.29|1.53|1.53|1.54|ns|
|LVCMOS15_S_8|0.68|0.82|0.87|0.87|0.88|1.11|1.11|1.34|1.34|1.34|1.11|1.11|1.34|1.34|1.34|ns|
|LVCMOS18_F_12|0.64|0.76|0.79|0.79|0.80|1.04|1.04|1.25|1.25|1.26|1.04|1.04|1.25|1.25|1.26|ns|
|LVCMOS18_F_16|0.64|0.76|0.79|0.79|0.80|1.00|1.00|1.21|1.21|1.22|1.00|1.00|1.21|1.21|1.22|ns|
|LVCMOS18_F_4|0.64|0.76|0.79|0.79|0.80|1.17|1.17|1.41|1.41|1.41|1.17|1.17|1.41|1.41|1.41|ns|
|LVCMOS18_F_8|0.64|0.76|0.79|0.79|0.80|1.10|1.10|1.33|1.33|1.33|1.10|1.10|1.33|1.33|1.33|ns|
|LVCMOS18_S_12|0.64|0.76|0.79|0.79|0.80|1.11|1.11|1.34|1.34|1.35|1.11|1.11|1.34|1.34|1.35|ns|
|LVCMOS18_S_16|0.64|0.76|0.79|0.79|0.80|1.11|1.11|1.34|1.34|1.34|1.11|1.11|1.34|1.34|1.34|ns|
|LVCMOS18_S_4|0.64|0.76|0.79|0.79|0.80|1.32|1.32|1.58|1.58|1.58|1.32|1.32|1.58|1.58|1.58|ns|
|LVCMOS18_S_8|0.64|0.76|0.79|0.79|0.80|1.18|1.18|1.38|1.38|1.38|1.18|1.18|1.38|1.38|1.38|ns|
|LVCMOS25_F_12|0.83|0.85|0.90|0.90|0.91|1.54|1.54|1.81|1.81|1.81|1.54|1.54|1.81|1.81|1.81|ns|
|LVCMOS25_F_16|0.83|0.85|0.90|0.90|0.91|1.56|1.59|1.88|1.88|1.88|1.56|1.59|1.88|1.88|1.88|ns|
|LVCMOS25_F_4|0.83|0.85|0.90|0.90|0.91|2.24|2.24|2.56|2.56|2.56|2.24|2.24|2.56|2.56|2.56|ns|
|LVCMOS25_F_8|0.83|0.85|0.90|0.90|0.91|1.67|1.67|1.95|1.95|1.95|1.67|1.67|1.95|1.95|1.95|ns|
|LVCMOS25_S_12|0.83|0.85|0.90|0.90|0.91|2.05|2.14|2.47|2.47|2.47|2.05|2.14|2.47|2.47|2.47|ns|
|LVCMOS25_S_16|0.83|0.85|0.90|0.90|0.91|1.84|1.89|2.19|2.19|2.19|1.84|1.89|2.19|2.19|2.19|ns|
|LVCMOS25_S_4|0.83|0.85|0.90|0.90|0.91|3.23|3.27|3.68|3.68|3.68|3.23|3.27|3.68|3.68|3.68|ns|
|LVCMOS25_S_8|0.83|0.85|0.90|0.90|0.91|2.11|2.15|2.47|2.47|2.47|2.11|2.15|2.47|2.47|2.47|ns|
DS892 (v1.14) February 2, 2017 **Product Specification**
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 27:_ **IOB High Range (HR) Switching Characteristics** _**(Cont’d)**_
|**I/O Standards**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||**1.0V**|**0.95V**|||**0.9V **|**1.0V**|**0.95V**|||**0.9V **|**1.0V**|**0.95V**|||**0.9V**||
||**-3**|**-2**|**-1/**<br>**-1L**|**-1M**|**-1L**|**-3**|**-2**|**-1/**<br>**-1L**|**-1M**|**-1L**|**-3**|**-2**|**-1/**<br>**-1L**|**-1M**|**-1L**||
|LVCMOS33_F_12|0.96|0.97|1.03|1.03|1.03|1.98|1.98|2.24|2.24|2.24|1.98|1.98|2.24|2.24|2.24|ns|
|LVCMOS33_F_16|0.96|0.97|1.03|1.03|1.03|1.79|1.79|2.09|2.09|2.09|1.79|1.79|2.09|2.09|2.09|ns|
|LVCMOS33_F_4|0.96|0.97|1.03|1.03|1.03|2.34|2.34|2.63|2.63|2.63|2.34|2.34|2.63|2.63|2.63|ns|
|LVCMOS33_F_8|0.96|0.97|1.03|1.03|1.03|2.05|2.05|2.32|2.32|2.33|2.05|2.05|2.32|2.32|2.33|ns|
|LVCMOS33_S_12|0.96|0.97|1.03|1.03|1.03|2.13|2.13|2.48|2.48|2.48|2.13|2.13|2.48|2.48|2.48|ns|
|LVCMOS33_S_16|0.96|0.97|1.03|1.03|1.03|2.11|2.11|2.43|2.43|2.43|2.11|2.11|2.43|2.43|2.43|ns|
|LVCMOS33_S_4|0.96|0.97|1.03|1.03|1.03|3.23|3.23|3.67|3.67|3.67|3.23|3.23|3.67|3.67|3.67|ns|
|LVCMOS33_S_8|0.96|0.97|1.03|1.03|1.03|2.28|2.28|2.55|2.55|2.55|2.66|2.67|2.78|2.78|2.78|ns|
|LVDS_25|0.45|0.58|0.62|0.62|0.63|0.80|0.83|0.95|0.96|0.95|105.74|105.74|105.85|105.85|105.85|ns|
|LVPECL|0.43|0.57|0.62|0.62|0.63|N/A|N/A|N/A|N/A|N/A|N/A|N/A|N/A|N/A|N/A|ns|
|LVTTL_F_12|1.04|1.04|1.05|1.05|1.06|1.83|1.83|2.10|2.10|2.10|1.83|1.83|2.10|2.10|2.10|ns|
|LVTTL_F_16|1.04|1.04|1.05|1.05|1.06|1.79|1.79|2.06|2.06|2.06|1.79|1.79|2.06|2.06|2.06|ns|
|LVTTL_F_4|1.04|1.04|1.05|1.05|1.06|2.34|2.34|2.63|2.63|2.63|2.34|2.34|2.63|2.63|2.63|ns|
|LVTTL_F_8|1.04|1.04|1.05|1.05|1.06|1.97|1.97|2.22|2.22|2.23|1.97|1.97|2.22|2.22|2.23|ns|
|LVTTL_S_12|1.04|1.04|1.05|1.05|1.06|1.90|1.90|2.19|2.19|2.19|1.96|1.97|2.19|2.19|2.19|ns|
|LVTTL_S_16|1.04|1.04|1.05|1.05|1.06|2.07|2.07|2.40|2.40|2.40|2.07|2.07|2.40|2.40|2.40|ns|
|LVTTL_S_4|1.04|1.04|1.05|1.05|1.06|3.23|3.23|3.67|3.67|3.67|3.23|3.23|3.67|3.67|3.67|ns|
|LVTTL_S_8|1.04|1.04|1.05|1.05|1.06|2.22|2.22|2.47|2.47|2.47|2.22|2.37|2.50|2.50|2.51|ns|
|MINI_LVDS_25|0.45|0.58|0.62|0.62|0.63|0.80|0.83|0.95|0.96|0.95|105.74|105.74|105.85|105.85|105.85|ns|
|PPDS_25|0.45|0.58|0.62|0.62|0.63|0.80|0.83|0.95|0.96|0.95|105.74|105.74|105.85|105.85|105.85|ns|
|RSDS_25|0.45|0.58|0.62|0.62|0.63|0.80|0.83|0.95|0.96|0.95|105.74|105.74|105.85|105.85|105.85|ns|
|SLVS_400_25|0.45|0.58|0.62|0.62|0.63|N/A|N/A|N/A|N/A|N/A|N/A|N/A|N/A|N/A|N/A|ns|
|SSTL12_F|0.52|0.55|0.59|0.59|0.59|0.72|0.72|0.91|0.91|0.91|0.83|0.83|1.04|1.04|1.04|ns|
|SSTL12_S|0.52|0.55|0.59|0.59|0.59|0.78|0.78|0.97|0.97|0.98|0.88|0.88|1.11|1.11|1.11|ns|
|SSTL135_F|0.52|0.55|0.59|0.59|0.59|0.72|0.72|0.90|0.90|0.91|0.88|0.89|1.11|1.11|1.11|ns|
|SSTL135_S|0.52|0.55|0.59|0.59|0.59|0.77|0.77|0.97|0.97|0.97|0.94|0.94|1.18|1.18|1.18|ns|
|SSTL135_R_F|0.52|0.55|0.59|0.59|0.59|0.74|0.74|0.93|0.93|0.93|0.85|0.86|1.08|1.08|1.08|ns|
|SSTL135_R_S|0.52|0.55|0.59|0.59|0.59|0.82|0.82|1.02|1.02|1.03|0.95|0.96|1.19|1.19|1.19|ns|
|SSTL15_F|0.52|0.55|0.59|0.59|0.59|0.68|0.68|0.87|0.87|0.87|0.83|0.84|1.07|1.07|1.07|ns|
|SSTL15_S|0.52|0.55|0.59|0.59|0.59|0.80|0.80|1.00|1.00|1.01|0.98|0.99|1.23|1.23|1.23|ns|
|SSTL15_R_F|0.52|0.55|0.59|0.59|0.59|0.75|0.75|0.94|0.94|0.94|0.88|0.89|1.11|1.11|1.11|ns|
|SSTL15_R_S|0.52|0.55|0.59|0.59|0.59|0.83|0.83|1.04|1.04|1.04|0.95|0.96|1.20|1.20|1.21|ns|
|SSTL18_I_F|0.52|0.55|0.59|0.59|0.59|0.76|0.76|0.96|0.96|0.96|0.94|0.95|1.21|1.21|1.21|ns|
|SSTL18_I_S|0.52|0.55|0.59|0.59|0.59|0.88|0.88|1.08|1.08|1.08|0.88|0.88|1.08|1.08|1.08|ns|
|SSTL18_II_F|0.52|0.55|0.59|0.59|0.59|0.73|0.73|0.92|0.92|0.92|0.89|0.90|1.14|1.14|1.14|ns|
|SSTL18_II_S|0.52|0.55|0.59|0.59|0.59|0.85|0.85|1.05|1.05|1.05|1.01|1.06|1.32|1.32|1.32|ns|
|SUB_LVDS|0.45|0.58|0.62|0.62|0.63|0.80|0.83|0.95|0.96|0.95|105.74|105.74|105.85|105.85|105.85|ns|
|TMDS_33|0.57|0.65|0.73|0.73|0.74|0.80|0.83|0.95|0.96|0.95|105.74|105.74|105.85|105.85|105.85|ns|
DS892 (v1.14) February 2, 2017 **Product Specification**
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 28:_ **IOB High Performance (HP) Switching Characteristics**
|**I/O Standards**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||**1.0V**|**0.95V**|||**0.9V **|**1.0V**|**0.95V**|||**0.9V **|**1.0V**|**0.95V**|||**0.9V**||
||**-3**|**-2**|**-1/**<br>**-1L**|**-1M**|**-1L**|**-3**|**-2**|**-1/**<br>**-1L**|**-1M**|**-1L**|**-3**|**-2**|**-1/**<br>**-1L**|**-1M**|**-1L**||
|DIFF_HSTL_I_12_F|0.43|0.48|0.55|0.55|0.55|0.46|0.50|0.54|0.54|0.54|0.54|0.62|0.68|0.68|0.68|ns|
|DIFF_HSTL_I_12_M|0.43|0.48|0.55|0.55|0.55|0.50|0.55|0.60|0.60|0.60|0.60|0.68|0.76|0.76|0.76|ns|
|DIFF_HSTL_I_12_S|0.43|0.48|0.55|0.55|0.55|0.56|0.61|0.67|0.67|0.67|0.67|0.76|0.85|0.85|0.85|ns|
|DIFF_HSTL_I_18_F|0.43|0.48|0.55|0.55|0.55|0.45|0.49|0.53|0.53|0.53|0.53|0.61|0.68|0.68|0.68|ns|
|DIFF_HSTL_I_18_M|0.43|0.48|0.55|0.55|0.55|0.50|0.55|0.59|0.59|0.59|0.59|0.68|0.76|0.76|0.76|ns|
|DIFF_HSTL_I_18_S|0.43|0.48|0.55|0.55|0.55|0.56|0.62|0.67|0.67|0.67|0.67|0.77|0.86|0.86|0.86|ns|
|DIFF_HSTL_I_DCI_12_F|0.43|0.48|0.55|0.55|0.55|0.46|0.50|0.54|0.54|0.54|0.54|0.62|0.68|0.68|0.68|ns|
|DIFF_HSTL_I_DCI_12_M|0.43|0.48|0.55|0.55|0.55|0.50|0.55|0.60|0.60|0.60|0.60|0.68|0.76|0.76|0.76|ns|
|DIFF_HSTL_I_DCI_12_S|0.43|0.48|0.55|0.55|0.55|0.56|0.61|0.67|0.67|0.67|0.67|0.76|0.85|0.85|0.85|ns|
|DIFF_HSTL_I_DCI_18_F|0.43|0.48|0.55|0.55|0.55|0.45|0.49|0.53|0.53|0.53|0.53|0.61|0.68|0.68|0.68|ns|
|DIFF_HSTL_I_DCI_18_M|0.43|0.48|0.55|0.55|0.55|0.50|0.55|0.59|0.59|0.59|0.59|0.68|0.76|0.76|0.76|ns|
|DIFF_HSTL_I_DCI_18_S|0.43|0.48|0.55|0.55|0.55|0.56|0.62|0.67|0.67|0.67|0.67|0.77|0.86|0.86|0.86|ns|
|DIFF_HSTL_I_DCI_F|0.43|0.48|0.55|0.55|0.55|0.46|0.50|0.54|0.54|0.54|0.54|0.62|0.68|0.68|0.68|ns|
|DIFF_HSTL_I_DCI_M|0.43|0.48|0.55|0.55|0.55|0.50|0.55|0.60|0.60|0.60|0.60|0.68|0.76|0.76|0.76|ns|
|DIFF_HSTL_I_DCI_S|0.43|0.48|0.55|0.55|0.55|0.56|0.61|0.67|0.67|0.67|0.67|0.76|0.85|0.85|0.85|ns|
|DIFF_HSTL_I_F|0.43|0.48|0.55|0.55|0.55|0.46|0.50|0.54|0.54|0.54|0.54|0.62|0.68|0.68|0.68|ns|
|DIFF_HSTL_I_M|0.43|0.48|0.55|0.55|0.55|0.50|0.55|0.60|0.60|0.60|0.60|0.68|0.76|0.76|0.76|ns|
|DIFF_HSTL_I_S|0.43|0.48|0.55|0.55|0.55|0.56|0.61|0.67|0.67|0.67|0.67|0.76|0.85|0.85|0.85|ns|
|DIFF_HSUL_12_DCI_F|0.43|0.48|0.55|0.55|0.55|0.46|0.50|0.54|0.54|0.54|0.54|0.62|0.68|0.68|0.68|ns|
|DIFF_HSUL_12_DCI_M|0.43|0.48|0.55|0.55|0.55|0.50|0.55|0.60|0.60|0.60|0.60|0.68|0.76|0.76|0.76|ns|
|DIFF_HSUL_12_DCI_S|0.43|0.48|0.55|0.55|0.55|0.56|0.61|0.67|0.67|0.67|0.67|0.76|0.85|0.85|0.85|ns|
|DIFF_HSUL_12_F|0.43|0.48|0.55|0.55|0.55|0.46|0.50|0.54|0.54|0.54|0.54|0.62|0.68|0.68|0.68|ns|
|DIFF_HSUL_12_M|0.43|0.48|0.55|0.55|0.55|0.50|0.55|0.60|0.60|0.60|0.60|0.68|0.76|0.76|0.76|ns|
|DIFF_HSUL_12_S|0.43|0.48|0.55|0.55|0.55|0.56|0.61|0.67|0.67|0.67|0.67|0.76|0.85|0.85|0.85|ns|
|DIFF_POD10_DCI_F|0.43|0.48|0.55|0.55|0.55|0.46|0.50|0.55|0.55|0.55|0.58|0.65|0.73|0.73|0.73|ns|
|DIFF_POD10_DCI_M|0.43|0.48|0.55|0.55|0.55|0.52|0.58|0.63|0.63|0.63|0.62|0.71|0.79|0.79|0.79|ns|
|DIFF_POD10_DCI_S|0.43|0.48|0.55|0.55|0.55|0.61|0.68|0.74|0.74|0.74|0.69|0.79|0.88|0.88|0.88|ns|
|DIFF_POD10_F|0.43|0.48|0.55|0.55|0.55|0.46|0.50|0.55|0.55|0.55|0.58|0.65|0.73|0.73|0.73|ns|
|DIFF_POD10_M|0.43|0.48|0.55|0.55|0.55|0.52|0.58|0.63|0.63|0.63|0.62|0.71|0.79|0.79|0.79|ns|
|DIFF_POD10_S|0.43|0.48|0.55|0.55|0.55|0.61|0.68|0.74|0.74|0.74|0.69|0.79|0.88|0.88|0.88|ns|
|DIFF_POD12_DCI_F|0.43|0.48|0.55|0.55|0.55|0.46|0.50|0.55|0.55|0.55|0.58|0.65|0.73|0.73|0.73|ns|
|DIFF_POD12_DCI_M|0.43|0.48|0.55|0.55|0.55|0.52|0.58|0.63|0.63|0.63|0.62|0.71|0.79|0.79|0.79|ns|
|DIFF_POD12_DCI_S|0.43|0.48|0.55|0.55|0.55|0.61|0.68|0.74|0.74|0.74|0.69|0.79|0.88|0.88|0.88|ns|
|DIFF_POD12_F|0.43|0.48|0.55|0.55|0.55|0.46|0.50|0.55|0.55|0.55|0.58|0.65|0.73|0.73|0.73|ns|
|DIFF_POD12_M|0.43|0.48|0.55|0.55|0.55|0.52|0.58|0.63|0.63|0.63|0.62|0.71|0.79|0.79|0.79|ns|
|DIFF_POD12_S|0.43|0.48|0.55|0.55|0.55|0.61|0.68|0.74|0.74|0.74|0.69|0.79|0.88|0.88|0.88|ns|
|DIFF_SSTL12_DCI_F|0.43|0.48|0.55|0.55|0.55|0.46|0.50|0.54|0.54|0.54|0.54|0.62|0.68|0.68|0.68|ns|
|DIFF_SSTL12_DCI_M|0.43|0.48|0.55|0.55|0.55|0.50|0.55|0.60|0.60|0.60|0.60|0.68|0.76|0.76|0.76|ns|
|DIFF_SSTL12_DCI_S|0.43|0.48|0.55|0.55|0.55|0.56|0.61|0.67|0.67|0.67|0.67|0.76|0.85|0.85|0.85|ns|
|DIFF_SSTL12_F|0.43|0.48|0.55|0.55|0.55|0.46|0.50|0.54|0.54|0.54|0.54|0.62|0.68|0.68|0.68|ns|
DS892 (v1.14) February 2, 2017 **Product Specification**
www.xilinx.com
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26
**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 28:_ **IOB High Performance (HP) Switching Characteristics** _**(Cont’d)**_
|**I/O Standards**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||**1.0V**|**0.95V**|||**0.9V **|**1.0V**|**0.95V**|||**0.9V **|**1.0V**|**0.95V**|||**0.9V**||
||**-3**|**-2**|**-1/**<br>**-1L**|**-1M**|**-1L**|**-3**|**-2**|**-1/**<br>**-1L**|**-1M**|**-1L**|**-3**|**-2**|**-1/**<br>**-1L**|**-1M**|**-1L**||
|DIFF_SSTL12_M|0.43|0.48|0.55|0.55|0.55|0.50|0.55|0.60|0.60|0.60|0.60|0.68|0.76|0.76|0.76|ns|
|DIFF_SSTL12_S|0.43|0.48|0.55|0.55|0.55|0.56|0.61|0.67|0.67|0.67|0.67|0.76|0.85|0.85|0.85|ns|
|DIFF_SSTL135_DCI_F|0.43|0.48|0.55|0.55|0.55|0.46|0.50|0.54|0.54|0.54|0.54|0.62|0.69|0.69|0.69|ns|
|DIFF_SSTL135_DCI_M|0.43|0.48|0.55|0.55|0.55|0.50|0.55|0.60|0.60|0.60|0.60|0.68|0.76|0.76|0.76|ns|
|DIFF_SSTL135_DCI_S|0.43|0.48|0.55|0.55|0.55|0.56|0.61|0.67|0.67|0.67|0.67|0.76|0.85|0.85|0.85|ns|
|DIFF_SSTL135_F|0.43|0.48|0.55|0.55|0.55|0.46|0.50|0.54|0.54|0.54|0.54|0.62|0.69|0.69|0.69|ns|
|DIFF_SSTL135_M|0.43|0.48|0.55|0.55|0.55|0.50|0.55|0.60|0.60|0.60|0.60|0.68|0.76|0.76|0.76|ns|
|DIFF_SSTL135_S|0.43|0.48|0.55|0.55|0.55|0.56|0.61|0.67|0.67|0.67|0.67|0.76|0.85|0.85|0.85|ns|
|DIFF_SSTL15_DCI_F|0.43|0.48|0.55|0.55|0.55|0.46|0.50|0.54|0.54|0.54|0.54|0.62|0.68|0.68|0.68|ns|
|DIFF_SSTL15_DCI_M|0.43|0.48|0.55|0.55|0.55|0.50|0.55|0.60|0.60|0.60|0.60|0.68|0.76|0.76|0.76|ns|
|DIFF_SSTL15_DCI_S|0.43|0.48|0.55|0.55|0.55|0.56|0.61|0.67|0.67|0.67|0.67|0.76|0.85|0.85|0.85|ns|
|DIFF_SSTL15_F|0.43|0.48|0.55|0.55|0.55|0.46|0.50|0.54|0.54|0.54|0.54|0.62|0.68|0.68|0.68|ns|
|DIFF_SSTL15_M|0.43|0.48|0.55|0.55|0.55|0.50|0.55|0.60|0.60|0.60|0.60|0.68|0.76|0.76|0.76|ns|
|DIFF_SSTL15_S|0.43|0.48|0.55|0.55|0.55|0.56|0.61|0.67|0.67|0.67|0.67|0.76|0.85|0.85|0.85|ns|
|DIFF_SSTL18_I_DCI_F|0.43|0.48|0.55|0.55|0.55|0.45|0.49|0.53|0.53|0.53|0.53|0.61|0.68|0.68|0.68|ns|
|DIFF_SSTL18_I_DCI_M|0.43|0.48|0.55|0.55|0.55|0.50|0.55|0.59|0.59|0.59|0.59|0.68|0.76|0.76|0.76|ns|
|DIFF_SSTL18_I_DCI_S|0.43|0.48|0.55|0.55|0.55|0.56|0.62|0.67|0.67|0.67|0.67|0.77|0.86|0.86|0.86|ns|
|DIFF_SSTL18_I_F|0.43|0.48|0.55|0.55|0.55|0.45|0.49|0.53|0.53|0.53|0.53|0.61|0.68|0.68|0.68|ns|
|DIFF_SSTL18_I_M|0.43|0.48|0.55|0.55|0.55|0.50|0.55|0.59|0.59|0.59|0.59|0.68|0.76|0.76|0.76|ns|
|DIFF_SSTL18_I_S|0.43|0.48|0.55|0.55|0.55|0.56|0.62|0.67|0.67|0.67|0.67|0.77|0.86|0.86|0.86|ns|
|HSLVDCI_15_F|0.43|0.46|0.52|0.52|0.52|0.48|0.53|0.56|0.56|0.56|0.57|0.64|0.71|0.71|0.71|ns|
|HSLVDCI_15_M|0.43|0.46|0.52|0.52|0.52|0.53|0.57|0.62|0.62|0.62|0.62|0.71|0.79|0.79|0.79|ns|
|HSLVDCI_15_S|0.43|0.46|0.52|0.52|0.52|0.58|0.64|0.69|0.69|0.69|0.70|0.79|0.88|0.88|0.88|ns|
|HSLVDCI_18_F|0.43|0.46|0.52|0.52|0.52|0.48|0.53|0.57|0.57|0.57|0.57|0.65|0.71|0.71|0.71|ns|
|HSLVDCI_18_M|0.43|0.46|0.52|0.52|0.52|0.52|0.57|0.62|0.62|0.62|0.62|0.71|0.79|0.79|0.79|ns|
|HSLVDCI_18_S|0.43|0.46|0.52|0.52|0.52|0.58|0.64|0.69|0.69|0.69|0.70|0.80|0.90|0.90|0.90|ns|
|HSTL_I_12_F|0.43|0.46|0.52|0.52|0.52|0.48|0.52|0.56|0.56|0.56|0.56|0.63|0.70|0.70|0.70|ns|
|HSTL_I_12_M|0.43|0.46|0.52|0.52|0.52|0.52|0.57|0.61|0.61|0.61|0.61|0.70|0.78|0.78|0.78|ns|
|HSTL_I_12_S|0.43|0.46|0.52|0.52|0.52|0.57|0.63|0.68|0.68|0.68|0.69|0.78|0.87|0.87|0.87|ns|
|HSTL_I_18_F|0.43|0.46|0.52|0.52|0.52|0.47|0.51|0.55|0.55|0.55|0.55|0.63|0.70|0.70|0.70|ns|
|HSTL_I_18_M|0.43|0.46|0.52|0.52|0.52|0.52|0.57|0.61|0.61|0.61|0.61|0.70|0.78|0.78|0.78|ns|
|HSTL_I_18_S|0.43|0.46|0.52|0.52|0.52|0.58|0.63|0.69|0.69|0.69|0.69|0.78|0.88|0.88|0.88|ns|
|HSTL_I_DCI_12_F|0.43|0.46|0.52|0.52|0.52|0.48|0.52|0.56|0.56|0.56|0.56|0.63|0.70|0.70|0.70|ns|
|HSTL_I_DCI_12_M|0.43|0.46|0.52|0.52|0.52|0.52|0.57|0.61|0.61|0.61|0.61|0.70|0.78|0.78|0.78|ns|
|HSTL_I_DCI_12_S|0.43|0.46|0.52|0.52|0.52|0.57|0.63|0.68|0.68|0.68|0.69|0.78|0.87|0.87|0.87|ns|
|HSTL_I_DCI_18_F|0.43|0.46|0.52|0.52|0.52|0.47|0.51|0.55|0.55|0.55|0.55|0.63|0.70|0.70|0.70|ns|
|HSTL_I_DCI_18_M|0.43|0.46|0.52|0.52|0.52|0.52|0.57|0.61|0.61|0.61|0.61|0.70|0.78|0.78|0.78|ns|
|HSTL_I_DCI_18_S|0.43|0.46|0.52|0.52|0.52|0.58|0.63|0.69|0.69|0.69|0.69|0.78|0.88|0.88|0.88|ns|
|HSTL_I_DCI_F|0.43|0.46|0.52|0.52|0.52|0.47|0.52|0.56|0.56|0.56|0.56|0.63|0.70|0.70|0.70|ns|
|HSTL_I_DCI_M|0.43|0.46|0.52|0.52|0.52|0.52|0.57|0.61|0.61|0.61|0.61|0.70|0.78|0.78|0.78|ns|
DS892 (v1.14) February 2, 2017 **Product Specification**
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 28:_ **IOB High Performance (HP) Switching Characteristics** _**(Cont’d)**_
|**I/O Standards**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||**1.0V**|**0.95V**|||**0.9V **|**1.0V**|**0.95V**|||**0.9V **|**1.0V**|**0.95V**|||**0.9V**||
||**-3**|**-2**|**-1/**<br>**-1L**|**-1M**|**-1L**|**-3**|**-2**|**-1/**<br>**-1L**|**-1M**|**-1L**|**-3**|**-2**|**-1/**<br>**-1L**|**-1M**|**-1L**||
|HSTL_I_DCI_S|0.43|0.46|0.52|0.52|0.52|0.57|0.63|0.68|0.68|0.68|0.69|0.78|0.87|0.87|0.87|ns|
|HSTL_I_F|0.43|0.46|0.52|0.52|0.52|0.47|0.52|0.56|0.56|0.56|0.56|0.63|0.70|0.70|0.70|ns|
|HSTL_I_M|0.43|0.46|0.52|0.52|0.52|0.52|0.57|0.61|0.61|0.61|0.61|0.70|0.78|0.78|0.78|ns|
|HSTL_I_S|0.43|0.46|0.52|0.52|0.52|0.57|0.63|0.68|0.68|0.68|0.69|0.78|0.87|0.87|0.87|ns|
|HSUL_12_DCI_F|0.43|0.46|0.52|0.52|0.52|0.48|0.52|0.56|0.56|0.56|0.56|0.63|0.70|0.70|0.70|ns|
|HSUL_12_DCI_M|0.43|0.46|0.52|0.52|0.52|0.52|0.57|0.61|0.61|0.61|0.61|0.70|0.78|0.78|0.78|ns|
|HSUL_12_DCI_S|0.43|0.46|0.52|0.52|0.52|0.57|0.63|0.68|0.68|0.68|0.69|0.78|0.87|0.87|0.87|ns|
|HSUL_12_F|0.43|0.46|0.52|0.52|0.52|0.48|0.52|0.56|0.56|0.56|0.56|0.63|0.70|0.70|0.70|ns|
|HSUL_12_M|0.43|0.46|0.52|0.52|0.52|0.52|0.57|0.61|0.61|0.61|0.61|0.70|0.78|0.78|0.78|ns|
|HSUL_12_S|0.43|0.46|0.52|0.52|0.52|0.57|0.63|0.68|0.68|0.68|0.69|0.78|0.87|0.87|0.87|ns|
|LVCMOS12_F_2|0.56|0.66|0.74|0.76|0.74|0.67|0.73|0.79|0.79|0.79|0.67|0.73|0.79|0.79|0.79|ns|
|LVCMOS12_F_4|0.56|0.66|0.74|0.76|0.74|0.63|0.68|0.73|0.73|0.73|0.63|0.68|0.73|0.73|0.73|ns|
|LVCMOS12_F_6|0.56|0.66|0.74|0.76|0.74|0.59|0.64|0.69|0.69|0.69|0.59|0.65|0.72|0.72|0.72|ns|
|LVCMOS12_F_8|0.56|0.66|0.74|0.76|0.74|0.57|0.63|0.67|0.67|0.67|0.59|0.66|0.72|0.72|0.72|ns|
|LVCMOS12_M_2|0.56|0.66|0.74|0.76|0.74|0.72|0.79|0.85|0.85|0.85|0.72|0.79|0.85|0.85|0.85|ns|
|LVCMOS12_M_4|0.56|0.66|0.74|0.76|0.74|0.66|0.71|0.77|0.77|0.77|0.66|0.71|0.77|0.77|0.77|ns|
|LVCMOS12_M_6|0.56|0.66|0.74|0.76|0.74|0.62|0.67|0.72|0.72|0.72|0.62|0.69|0.75|0.75|0.75|ns|
|LVCMOS12_M_8|0.56|0.66|0.74|0.76|0.74|0.62|0.67|0.72|0.72|0.72|0.64|0.71|0.78|0.78|0.78|ns|
|LVCMOS12_S_2|0.56|0.66|0.74|0.76|0.74|0.77|0.89|0.96|0.96|0.96|0.77|0.89|0.96|0.96|0.96|ns|
|LVCMOS12_S_4|0.56|0.66|0.74|0.76|0.74|0.68|0.74|0.79|0.79|0.79|0.68|0.74|0.79|0.79|0.79|ns|
|LVCMOS12_S_6|0.56|0.66|0.74|0.76|0.74|0.66|0.72|0.78|0.78|0.78|0.66|0.72|0.79|0.79|0.79|ns|
|LVCMOS12_S_8|0.56|0.66|0.74|0.76|0.74|0.66|0.72|0.77|0.77|0.77|0.67|0.74|0.82|0.82|0.82|ns|
|LVCMOS15_F_12|0.45|0.52|0.58|0.60|0.58|0.61|0.66|0.71|0.71|0.71|0.66|0.73|0.81|0.81|0.81|ns|
|LVCMOS15_F_2|0.45|0.52|0.58|0.60|0.58|0.73|0.77|0.83|0.83|0.83|0.73|0.77|0.83|0.83|0.83|ns|
|LVCMOS15_F_4|0.45|0.52|0.58|0.60|0.58|0.69|0.73|0.78|0.78|0.78|0.69|0.73|0.78|0.78|0.78|ns|
|LVCMOS15_F_6|0.45|0.52|0.58|0.60|0.58|0.63|0.68|0.73|0.73|0.73|0.63|0.70|0.77|0.77|0.77|ns|
|LVCMOS15_F_8|0.45|0.52|0.58|0.60|0.58|0.61|0.66|0.72|0.72|0.72|0.63|0.71|0.78|0.78|0.78|ns|
|LVCMOS15_M_12|0.45|0.52|0.58|0.60|0.58|0.63|0.69|0.75|0.75|0.75|0.67|0.77|0.85|0.85|0.85|ns|
|LVCMOS15_M_2|0.45|0.52|0.58|0.60|0.58|0.77|0.80|0.86|0.86|0.86|0.77|0.80|0.86|0.86|0.86|ns|
|LVCMOS15_M_4|0.45|0.52|0.58|0.60|0.58|0.72|0.76|0.82|0.82|0.82|0.72|0.76|0.82|0.82|0.82|ns|
|LVCMOS15_M_6|0.45|0.52|0.58|0.60|0.58|0.67|0.72|0.78|0.78|0.78|0.67|0.74|0.82|0.82|0.82|ns|
|LVCMOS15_M_8|0.45|0.52|0.58|0.60|0.58|0.65|0.71|0.76|0.76|0.76|0.65|0.76|0.83|0.83|0.83|ns|
|LVCMOS15_S_12|0.45|0.52|0.58|0.60|0.58|0.65|0.70|0.75|0.75|0.75|0.67|0.75|0.83|0.83|0.83|ns|
|LVCMOS15_S_2|0.45|0.52|0.58|0.60|0.58|0.78|0.85|0.91|0.91|0.91|0.78|0.85|0.91|0.91|0.91|ns|
|LVCMOS15_S_4|0.45|0.52|0.58|0.60|0.58|0.74|0.78|0.84|0.84|0.84|0.74|0.78|0.84|0.84|0.84|ns|
|LVCMOS15_S_6|0.45|0.52|0.58|0.60|0.58|0.72|0.76|0.82|0.82|0.82|0.72|0.76|0.84|0.84|0.84|ns|
|LVCMOS15_S_8|0.45|0.52|0.58|0.60|0.58|0.68|0.73|0.79|0.79|0.79|0.68|0.75|0.83|0.83|0.83|ns|
|LVCMOS18_F_12|0.43|0.49|0.54|0.55|0.54|0.67|0.72|0.78|0.78|0.78|0.67|0.81|0.90|0.90|0.90|ns|
|LVCMOS18_F_2|0.43|0.49|0.54|0.55|0.54|0.94|1.07|1.15|1.15|1.15|0.94|1.07|1.15|1.15|1.15|ns|
|LVCMOS18_F_4|0.43|0.49|0.54|0.55|0.54|0.78|0.82|0.89|0.89|0.89|0.78|0.82|0.89|0.89|0.89|ns|
DS892 (v1.14) February 2, 2017 **Product Specification**
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28
**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 28:_ **IOB High Performance (HP) Switching Characteristics** _**(Cont’d)**_
|**I/O Standards**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||**1.0V**|**0.95V**|||**0.9V **|**1.0V**|**0.95V**|||**0.9V **|**1.0V**|**0.95V**|||**0.9V**||
||**-3**|**-2**|**-1/**<br>**-1L**|**-1M**|**-1L**|**-3**|**-2**|**-1/**<br>**-1L**|**-1M**|**-1L**|**-3**|**-2**|**-1/**<br>**-1L**|**-1M**|**-1L**||
|LVCMOS18_F_6|0.43|0.49|0.54|0.55|0.54|0.72|0.77|0.83|0.83|0.83|0.72|0.79|0.88|0.88|0.88|ns|
|LVCMOS18_F_8|0.43|0.49|0.54|0.55|0.54|0.70|0.75|0.81|0.81|0.81|0.72|0.81|0.89|0.89|0.89|ns|
|LVCMOS18_M_12|0.43|0.49|0.54|0.55|0.54|0.70|0.76|0.81|0.81|0.81|0.74|0.83|0.92|0.92|0.92|ns|
|LVCMOS18_M_2|0.43|0.49|0.54|0.55|0.54|0.99|1.10|1.19|1.19|1.19|0.99|1.10|1.19|1.19|1.19|ns|
|LVCMOS18_M_4|0.43|0.49|0.54|0.55|0.54|0.82|0.86|0.92|0.92|0.92|0.82|0.86|0.92|0.92|0.92|ns|
|LVCMOS18_M_6|0.43|0.49|0.54|0.55|0.54|0.75|0.80|0.87|0.87|0.87|0.75|0.81|0.90|0.90|0.90|ns|
|LVCMOS18_M_8|0.43|0.49|0.54|0.55|0.54|0.73|0.78|0.85|0.85|0.85|0.73|0.83|0.92|0.92|0.92|ns|
|LVCMOS18_S_12|0.43|0.49|0.54|0.55|0.54|0.74|0.78|0.84|0.84|0.84|0.76|0.83|0.92|0.92|0.92|ns|
|LVCMOS18_S_2|0.43|0.49|0.54|0.55|0.54|1.05|1.16|1.25|1.25|1.25|1.05|1.16|1.25|1.25|1.25|ns|
|LVCMOS18_S_4|0.43|0.49|0.54|0.55|0.54|0.83|0.86|0.93|0.93|0.93|0.83|0.86|0.93|0.93|0.93|ns|
|LVCMOS18_S_6|0.43|0.49|0.54|0.55|0.54|0.79|0.82|0.89|0.89|0.89|0.79|0.82|0.90|0.90|0.90|ns|
|LVCMOS18_S_8|0.43|0.49|0.54|0.55|0.54|0.75|0.80|0.86|0.86|0.86|0.75|0.82|0.90|0.90|0.90|ns|
|LVDCI_15_F|0.45|0.52|0.58|0.60|0.58|0.48|0.53|0.56|0.56|0.56|0.57|0.64|0.71|0.71|0.71|ns|
|LVDCI_15_M|0.45|0.52|0.58|0.60|0.58|0.53|0.57|0.62|0.62|0.62|0.62|0.71|0.79|0.79|0.79|ns|
|LVDCI_15_S|0.45|0.52|0.58|0.60|0.58|0.58|0.64|0.69|0.69|0.69|0.70|0.79|0.88|0.88|0.88|ns|
|LVDCI_18_F|0.43|0.49|0.54|0.55|0.54|0.48|0.53|0.57|0.57|0.57|0.57|0.65|0.71|0.71|0.71|ns|
|LVDCI_18_M|0.43|0.49|0.54|0.55|0.54|0.52|0.57|0.62|0.62|0.62|0.62|0.71|0.79|0.79|0.79|ns|
|LVDCI_18_S|0.43|0.49|0.54|0.55|0.54|0.58|0.64|0.69|0.69|0.69|0.70|0.80|0.90|0.90|0.90|ns|
|LVDS|0.42|0.46|0.51|0.51|0.51|0.57|0.67|0.72|0.72|0.72|890.24|890.26|890.28|890.28|890.28|ns|
|POD10_DCI_F|0.43|0.46|0.52|0.52|0.52|0.48|0.52|0.56|0.56|0.56|0.59|0.67|0.74|0.74|0.74|ns|
|POD10_DCI_M|0.43|0.46|0.52|0.52|0.52|0.54|0.60|0.65|0.65|0.65|0.64|0.73|0.81|0.81|0.81|ns|
|POD10_DCI_S|0.43|0.46|0.52|0.52|0.52|0.63|0.69|0.76|0.76|0.76|0.71|0.81|0.89|0.89|0.89|ns|
|POD10_F|0.43|0.46|0.52|0.52|0.52|0.48|0.52|0.56|0.56|0.56|0.59|0.67|0.74|0.74|0.74|ns|
|POD10_M|0.43|0.46|0.52|0.52|0.52|0.54|0.60|0.65|0.65|0.65|0.64|0.73|0.81|0.81|0.81|ns|
|POD10_S|0.43|0.46|0.52|0.52|0.52|0.63|0.69|0.76|0.76|0.76|0.71|0.81|0.89|0.89|0.89|ns|
|POD12_DCI_F|0.43|0.46|0.52|0.52|0.52|0.48|0.52|0.56|0.56|0.56|0.59|0.67|0.74|0.74|0.74|ns|
|POD12_DCI_M|0.43|0.46|0.52|0.52|0.52|0.54|0.60|0.65|0.65|0.65|0.64|0.73|0.81|0.81|0.81|ns|
|POD12_DCI_S|0.43|0.46|0.52|0.52|0.52|0.63|0.69|0.76|0.76|0.76|0.71|0.81|0.89|0.89|0.89|ns|
|POD12_F|0.43|0.46|0.52|0.52|0.52|0.48|0.52|0.56|0.56|0.56|0.59|0.67|0.74|0.74|0.74|ns|
|POD12_M|0.43|0.46|0.52|0.52|0.52|0.54|0.60|0.65|0.65|0.65|0.64|0.73|0.81|0.81|0.81|ns|
|POD12_S|0.43|0.46|0.52|0.52|0.52|0.63|0.69|0.76|0.76|0.76|0.71|0.81|0.89|0.89|0.89|ns|
|SLVS_400_18|0.42|0.46|0.51|0.51|0.51|N/A|N/A|N/A|N/A|N/A|N/A|N/A|N/A|N/A|N/A|ns|
|SSTL12_DCI_F|0.43|0.46|0.52|0.52|0.52|0.48|0.52|0.56|0.56|0.56|0.56|0.63|0.70|0.70|0.70|ns|
|SSTL12_DCI_M|0.43|0.46|0.52|0.52|0.52|0.52|0.57|0.61|0.61|0.61|0.61|0.70|0.78|0.78|0.78|ns|
|SSTL12_DCI_S|0.43|0.46|0.52|0.52|0.52|0.57|0.63|0.68|0.68|0.68|0.69|0.78|0.87|0.87|0.87|ns|
|SSTL12_F|0.43|0.46|0.52|0.52|0.52|0.48|0.52|0.56|0.56|0.56|0.56|0.63|0.70|0.70|0.70|ns|
|SSTL12_M|0.43|0.46|0.52|0.52|0.52|0.52|0.57|0.61|0.61|0.61|0.61|0.70|0.78|0.78|0.78|ns|
|SSTL12_S|0.43|0.46|0.52|0.52|0.52|0.57|0.63|0.68|0.68|0.68|0.69|0.78|0.87|0.87|0.87|ns|
|SSTL135_DCI_F|0.43|0.46|0.52|0.52|0.52|0.48|0.52|0.56|0.56|0.56|0.56|0.64|0.70|0.70|0.70|ns|
|SSTL135_DCI_M|0.43|0.46|0.52|0.52|0.52|0.52|0.57|0.61|0.61|0.61|0.61|0.70|0.78|0.78|0.78|ns|
DS892 (v1.14) February 2, 2017 **Product Specification**
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29
**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 28:_ **IOB High Performance (HP) Switching Characteristics** _**(Cont’d)**_
|**I/O Standards**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TINBUF_DELAY_PAD_I**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_O_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**TOUTBUF_DELAY_TD_PAD**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||**1.0V**|**0.95V**|||**0.9V **|**1.0V**|**0.95V**|||**0.9V **|**1.0V**|**0.95V**|||**0.9V**||
||**-3**|**-2**|**-1/**<br>**-1L**|**-1M**|**-1L**|**-3**|**-2**|**-1/**<br>**-1L**|**-1M**|**-1L**|**-3**|**-2**|**-1/**<br>**-1L**|**-1M**|**-1L**||
|SSTL135_DCI_S|0.43|0.46|0.52|0.52|0.52|0.57|0.63|0.68|0.68|0.68|0.69|0.78|0.87|0.87|0.87|ns|
|SSTL135_F|0.43|0.46|0.52|0.52|0.52|0.48|0.52|0.56|0.56|0.56|0.56|0.64|0.70|0.70|0.70|ns|
|SSTL135_M|0.43|0.46|0.52|0.52|0.52|0.52|0.57|0.61|0.61|0.61|0.61|0.70|0.78|0.78|0.78|ns|
|SSTL135_S|0.43|0.46|0.52|0.52|0.52|0.57|0.63|0.68|0.68|0.68|0.69|0.78|0.87|0.87|0.87|ns|
|SSTL15_DCI_F|0.43|0.46|0.52|0.52|0.52|0.47|0.52|0.56|0.56|0.56|0.56|0.63|0.70|0.70|0.70|ns|
|SSTL15_DCI_M|0.43|0.46|0.52|0.52|0.52|0.52|0.57|0.61|0.61|0.61|0.61|0.70|0.78|0.78|0.78|ns|
|SSTL15_DCI_S|0.43|0.46|0.52|0.52|0.52|0.57|0.63|0.68|0.68|0.68|0.69|0.78|0.87|0.87|0.87|ns|
|SSTL15_F|0.43|0.46|0.52|0.52|0.52|0.47|0.52|0.56|0.56|0.56|0.56|0.63|0.70|0.70|0.70|ns|
|SSTL15_M|0.43|0.46|0.52|0.52|0.52|0.52|0.57|0.61|0.61|0.61|0.61|0.70|0.78|0.78|0.78|ns|
|SSTL15_S|0.43|0.46|0.52|0.52|0.52|0.57|0.63|0.68|0.68|0.68|0.69|0.78|0.87|0.87|0.87|ns|
|SSTL18_I_DCI_F|0.43|0.46|0.52|0.52|0.52|0.47|0.51|0.55|0.55|0.55|0.55|0.63|0.70|0.70|0.70|ns|
|SSTL18_I_DCI_M|0.43|0.46|0.52|0.52|0.52|0.52|0.57|0.61|0.61|0.61|0.61|0.70|0.78|0.78|0.78|ns|
|SSTL18_I_DCI_S|0.43|0.46|0.52|0.52|0.52|0.58|0.63|0.69|0.69|0.69|0.69|0.78|0.88|0.88|0.88|ns|
|SSTL18_I_F|0.43|0.46|0.52|0.52|0.52|0.47|0.51|0.55|0.55|0.55|0.55|0.63|0.70|0.70|0.70|ns|
|SSTL18_I_M|0.43|0.46|0.52|0.52|0.52|0.52|0.57|0.61|0.61|0.61|0.61|0.70|0.78|0.78|0.78|ns|
|SSTL18_I_S|0.43|0.46|0.52|0.52|0.52|0.58|0.63|0.69|0.69|0.69|0.69|0.78|0.88|0.88|0.88|ns|
|SUB_LVDS|0.42|0.46|0.51|0.51|0.51|0.57|0.67|0.72|0.72|0.72|890.24|890.26|890.28|890.28|890.28|ns|
Table 29 specifies the values of TOUTBUF_DELAY_TE_PAD and TINBUF_DELAY_IBUFDIS_O. TOUTBUF_DELAY_TE_PAD is the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is enabled (i.e., a high impedance state). TINBUF_DELAY_IBUFDIS_O is the IOB delay from IBUFDISABLE to O output. In HP I/O banks, the internal DCI termination turn-off time is always faster than TOUTBUF_DELAY_TE_PAD when the DCITERMDISABLE pin is used. In HR I/O banks, the internal IN_TERM termination turn-off time is always faster than TOUTBUF_DELAY_TE_PAD when the INTERMDISABLE pin is used.
_Table 29:_ **IOB 3-state Output Switching Characteristics**
|**Symbol**|**Description**|**Speed Grade and VCCINT**<br>**Operating Voltages**|**Speed Grade and VCCINT**<br>**Operating Voltages**|**Speed Grade and VCCINT**<br>**Operating Voltages**|**Speed Grade and VCCINT**<br>**Operating Voltages**|**Units**|
|---|---|---|---|---|---|---|
|||**1.0V**|**0.95V**||**0.90V**||
|||**-3**|**-2**|**-1/-1L**|**-1L**||
|TOUTBUF_DELAY_TE_PAD(1)|T input to pad high-impedance for HR I/O banks|1.37|1.52|1.69|1.69|ns|
||T input to pad high-impedance for HP I/O banks|0.62|0.71|0.78|0.78|ns|
|TINBUF_DELAY_IBUFDIS_O|IBUF turn-on time from IBUFDISABLE to O output<br>for HR I/O banks|0.47|0.65|0.68|0.68|ns|
||IBUF turn-on time from IBUFDISABLE to O output<br>for HP I/O banks|1.06|1.21|1.49|1.49|ns|
## **Notes:**
1. The TOUTBUF_DELAY_TE_PAD values are applicable to single-ended I/O standards. For true differential standards, the values are larger. Use the Vivado timing report for the most accurate timing values for your configuration.
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## **I/O Standard Adjustment Measurement Methodology**
## _**Input Delay Measurements**_
Table 30 shows the test setup parameters used for measuring input delay.
_Table 30:_ **Input Delay Measurement Methodology**
|**Description**|**I/O Standard**<br>**Attribute**|**VL(1)(2)**|**VH(1)(2)**|**VMEAS**<br>**(1)(4)(6)**|**VREF**<br>**(1)(3)(5)**|
|---|---|---|---|---|---|
|LVCMOS, 1.2V|LVCMOS12|0.1|1.1|0.6|–|
|LVCMOS, LVDCI, HSLVDCI, 1.5V|LVCMOS15,<br>LVDCI_15,<br>HSLVDCI_15|0.1|1.4|0.75|–|
|LVCMOS, LVDCI, HSLVDCI, 1.8V|LVCMOS18,<br>LVDCI_18,<br>HSLVDCI_18|0.1|1.7|0.9|–|
|LVCMOS, 2.5V|LVCMOS25|0.1|2.4|1.25|–|
|LVCMOS, 3.3V|LVCMOS33|0.1|3.2|1.65|–|
|LVTTL, 3.3V|LVTTL|0.1|3.2|1.65|–|
|HSTL (high-speed transceiver logic),<br>Class I, 1.2V|HSTL_I_12|VREF – 0.5|VREF + 0.5|VREF|0.60|
|HSTL, Class I and II, 1.5V|HSTL_I, HSTL_II|VREF – 0.65|VREF + 0.65|VREF|0.75|
|HSTL, Class I and II, 1.8V|HSTL_I_18,<br>HSTL_II_18|VREF – 0.8|VREF + 0.8|VREF|0.90|
|HSUL (high-speed unterminated logic), 1.2V|HSUL_12|VREF – 0.5|VREF + 0.5|VREF|0.60|
|SSTL (stub series terminated logic), 1.2V|SSTL12|VREF – 0.5|VREF + 0.5|VREF|0.60|
|SSTL, 1.35V|SSTL135, SSTL135_R|VREF – 0.575|VREF + 0.575|VREF|0.675|
|SSTL, 1.5V|SSTL15, SSTL15_R|VREF – 0.65|VREF + 0.65|VREF|0.75|
|SSTL, Class I and II, 1.8V|SSTL18_I, SSTL18_II|VREF – 0.8|VREF + 0.8|VREF|0.90|
|POD10, 1.0V|POD10|VREF – 0.6|VREF + 0.6|VREF|0.70|
|POD12, 1.2V|POD12|VREF – 0.74|VREF + 0.74|VREF|0.84|
|DIFF_HSTL, Class I, 1.2V|DIFF_HSTL_I_12|0.6 – 0.125|0.6 + 0.125|0(6)|–|
|DIFF_HSTL, Class I and II,1.5V|DIFF_HSTL_I,<br>DIFF_HSTL_II|0.75 – 0.125|0.75 + 0.125|0(6)|–|
|DIFF_HSTL, Class I and II, 1.8V|DIFF_HSTL_I_18,<br>DIFF_HSTL_II_18|0.9 – 0.125|0.9 + 0.125|0(6)|–|
|DIFF_HSUL, 1.2V|DIFF_HSUL_12|0.6 – 0.125|0.6 + 0.125|0(6)|–|
|DIFF_SSTL, 1.2V|DIFF_SSTL12|0.6 – 0.125|0.6 + 0.125|0(6)|–|
|DIFF_SSTL135/DIFF_SSTL135_R, 1.35V|DIFF_SSTL135,<br>DIFF_SSTL135_R|0.675 –<br>0.125|0.675 +<br>0.125|0(6)|–|
|DIFF_SSTL15/DIFF_SSTL15_R, 1.5V|DIFF_SSTL15,<br>DIFF_SSTL15_R|0.75 – 0.125|0.75 + 0.125|0(6)|–|
|DIFF_SSTL18_I/DIFF_SSTL18_II, 1.8V|DIFF_SSTL18_I,<br>DIFF_SSTL18_II|0.9 – 0.125|0.9 + 0.125|0(6)|–|
|DIFF_POD10, 1.0V|DIFF_POD10|0.70 – 0.125|0.70 + 0.125|0(6)|–|
|DIFF_POD12, 1.2V|DIFF_POD12|0.84 – 0.125|0.84 + 0.125|0(6)|–|
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 30:_ **Input Delay Measurement Methodology** _**(Cont’d)**_
|**Description**|**I/O Standard**<br>**Attribute**|**VL(1)(2)**|**VH(1)(2)**|**VMEAS**<br>**(1)(4)(6)**|**VREF**<br>**(1)(3)(5)**|
|---|---|---|---|---|---|
|LVDS (low-voltage differential signaling),<br>1.8V|LVDS|0.9 – 0.125|0.9 + 0.125|0(6)|–|
|LVDS_25, 2.5V|LVDS_25|1.25 – 0.125|1.25 + 0.125|0(6)|–|
|SUB_LVDS, 1.8V|SUB_LVDS|0.9 – 0.125|0.9 + 0.125|0(6)|–|
|SLVS, 1.8V|SLVS_400_18|0.9 – 0.125|0.9 + 0.125|0(6)|–|
|SLVS, 2.5V|SLVS_400_25|1.25 – 0.125|1.25 + 0.125|0(6)|–|
|LVPECL, 2.5|LVPECL|1.25 – 0.125|1.25 + 0.125|0(6)|–|
|BLVDS_25, 2.5V|BLVDS_25|1.25 – 0.125|1.25 + 0.125|0(6)|–|
|MINI_LVDS_25, 2.5V|MINI_LVDS_25|1.25 – 0.125|1.25 + 0.125|0(6)|–|
|PPDS_25|PPDS_25|1.25 – 0.125|1.25 + 0.125|0(6)|–|
|RSDS_25|RSDS_25|1.25 – 0.125|1.25 + 0.125|0(6)|–|
|TMDS_33|TMDS_33|3 – 0.125|3 + 0.125|0(6)|–|
## **Notes:**
1. The input delay measurement methodology parameters for LVDCI are the same for LVCMOS standards of the same voltage. Input delay measurement methodology parameters for HSLVDCI are the same as for HSTL_II standards of the same voltage. Parameters for all other DCI standards are the same for the corresponding non-DCI standards.
2. Input waveform switches between VLand VH.
3. Measurements are made at typical, minimum, and maximum VREF values. Reported delays reflect worst case of these measurements. VREF values listed are typical.
4. Input voltage level from which measurement starts.
5. This is an input voltage reference that bears no relation to the VREF/VMEAS parameters found in IBIS models and/or noted in Figure 1.
6. The value given is the differential input voltage.
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
## _**Output Delay Measurements**_
Output delays are measured with short output traces. Standard termination was used for all testing. The propagation delay of the trace is characterized separately and subtracted from the final measurement, and is therefore not included in the generalized test setups shown in Figure 1 and Figure 2.
**==> picture [294 x 154] intentionally omitted <==**
**----- Start of picture text -----**<br>
VREF<br>FPGA Output RREF<br>VMEAS (voltage level when taking delay measurement)<br>CREF (probe capacitance)<br>DS892_01_120414<br>**----- End of picture text -----**<br>
_Figure 1:_ **Single-Ended Test Setup**
**==> picture [246 x 96] intentionally omitted <==**
**----- Start of picture text -----**<br>
FPGA Output<br>+<br>CREF RREF VMEAS<br>–<br>DS892_02_120414<br>**----- End of picture text -----**<br>
_Figure 2:_ **Differential Test Setup**
Parameters VREF, RREF, CREF, and VMEAS fully describe the test conditions for each I/O standard. The most accurate prediction of propagation delay in any given application can be obtained through IBIS simulation, using this method:
1. Simulate the output driver of choice into the generalized test setup using values from Table 31.
2. Record the time to VMEAS.
3. Simulate the output driver of choice into the actual PCB trace and load using the appropriate IBIS model or capacitance value to represent the load.
4. Record the time to VMEAS.
5. Compare the results of step 2 and step 4. The increase or decrease in delay yields the actual propagation delay of the PCB trace.
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 31:_ **Output Delay Measurement Methodology**
|**Description**|**I/O Standard Attribute**|**RREF**<br>**(**Ω**)**|**CREF(1)**<br>**(pF)**|**VMEAS**<br>**(V)**|**VREF**<br>**(V)**|
|---|---|---|---|---|---|
|LVCMOS, 1.2V|LVCMOS12|1M|0|0.6|0|
|LVCMOS 1.5V|LVCMOS15|1M|0|0.75|0|
|LVCMOS 1.8V|LVCMOS18|1M|0|0.9|0|
|LVCMOS, 2.5V|LVCMOS25|1M|0|1.25|0|
|LVCMOS, 3.3V|LVCMOS33|1M|0|1.65|0|
|LVTTL, 3.3V|LVTTL|1M|0|1.65|0|
|LVDCI/HSLVDCI, 1.5V|LVDCI_15, HSLVDCI_15|50|0|VREF|0.75|
|LVDCI/HSLVDCI, 1.8V|LVDCI_18, HSLVDCI_18|50|0|VREF|0.9|
|HSTL (high-speed transceiver logic), Class I, 1.2V|HSTL_I_12|50|0|VREF|0.6|
|HSTL, Class I, 1.5V|HSTL_I|50|0|VREF|0.75|
|HSTL, Class II, 1.5V|HSTL_II|25|0|VREF|0.75|
|HSTL, Class I, 1.8V|HSTL_I_18|50|0|VREF|0.9|
|HSTL, Class II, 1.8V|HSTL_II_18|25|0|VREF|0.9|
|HSUL (high-speed unterminated logic), 1.2V|HSUL_12|50|0|VREF|0.6|
|SSTL12, 1.2V|SSTL12|50|0|VREF|0.6|
|SSTL135/SSTL135_R, 1.35V|SSTL135, SSTL135_R|50|0|VREF|0.675|
|SSTL15/SSTL15_R, 1.5V|SSTL15, SSTL15_R|50|0|VREF|0.75|
|SSTL (stub series terminated logic),<br>Class I and Class II, 1.8V|SSTL18_I, SSTL18_II|50|0|VREF|0.9|
|POD10, 1.0V|POD10|50|0|VREF|1.0|
|POD12, 1.2V|POD12|50|0|VREF|1.2|
|DIFF_HSTL, Class I, 1.2V|DIFF_HSTL_I_12|50|0|VREF|0.6|
|DIFF_HSTL, Class I and II, 1.5V|DIFF_HSTL_I, DIFF_HSTL_II|50|0|VREF|0.75|
|DIFF_HSTL, Class I and II, 1.8V|DIFF_HSTL_I_18,<br>DIFF_HSTL_II_18|50|0|VREF|0.9|
|DIFF_HSUL_12, 1.2V|DIFF_HSUL_12|50|0|VREF|0.6|
|DIFF_SSTL12, 1.2V|DIFF_SSTL12|50|0|VREF|0.6|
|DIFF_SSTL135/DIFF_SSTL135_R, 1.35V|DIFF_SSTL135,<br>DIFF_SSTL135_R|50|0|VREF|0.675|
|DIFF_SSTL15/DIFF_SSTL15_R, 1.5V|DIFF_SSTL15,<br>DIFF_SSTL15_R|50|0|VREF|0.75|
|DIFF_SSTL18, Class I and II, 1.8V|DIFF_SSTL18_I,<br>DIFF_SSTL18_II|50|0|VREF|0.9|
|DIFF_POD10, 1.0V|DIFF_POD10|50|0|VREF|1.0|
|DIFF_POD12, 1.2V|DIFF_POD12|50|0|VREF|1.2|
|LVDS (low-voltage differential signaling), 1.8V|LVDS|100|0|0(2)|0|
|LVDS, 2.5V|LVDS_25|100|0|0(2)|0|
|BLVDS (Bus LVDS), 2.5V|BLVDS_25|100|0|0(2)|0|
|Mini LVDS, 2.5V|MINI_LVDS_25|100|0|0(2)|0|
|PPDS_25|PPDS_25|100|0|0(2)|0|
|RSDS_25|RSDS_25|100|0|0(2)|0|
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 31:_ **Output Delay Measurement Methodology** _**(Cont’d)**_
|**Description**|**I/O Standard Attribute**|**RREF**<br>**(**Ω**)**|**CREF(1)**<br>**(pF)**|**VMEAS**<br>**(V)**|**VREF**<br>**(V)**|
|---|---|---|---|---|---|
|SUB_LVDS|SUB_LVDS|100|0|0(2)|0|
|TMDS_33|TMDS_33|50|0|0(2)|3.3|
## **Notes:**
1. CREF is the capacitance of the probe, nominally 0 pF.
2. The value given is the differential output voltage.
## **Block RAM and FIFO Switching Characteristics**
_Table 32:_ **Block RAM and FIFO Switching Characteristics**
|**Symbol**|**Description**|**Speed Grade and VCCINT**<br>**Operating Voltages**|**Speed Grade and VCCINT**<br>**Operating Voltages**|**Speed Grade and VCCINT**<br>**Operating Voltages**|**Speed Grade and VCCINT**<br>**Operating Voltages**|**Units**|
|---|---|---|---|---|---|---|
|||**1.0V**|**0.95V**||**0.90V**||
|||**-3**|**-2**|**-1/-1L**|**-1L**||
|**Maximum Frequency**|||||||
|FMAX_WF_NC|Block RAM<br>(Write First and No Change modes)|660|585|525|525|MHz|
|FMAX_RF|Block RAM (Read First mode)|575|510|460|400|MHz|
|FMAX_FIFO|FIFO in all modes without ECC|660|585|525|525|MHz|
|FMAX_ECC|Block RAM and FIFO in ECC configuration<br>without PIPELINE|530|450|390|390|MHz|
||Block RAM and FIFO in ECC configuration<br>with PIPELINE and Block RAM in Write First<br>or No Change mode.|660|585|525|525|MHz|
||Block RAM in ECC configuration in<br>Read First mode with PIPELINE|575|510|460|400|MHz|
|FMAX_ADDREN_RDADDRCHANGE|Block RAM with address enable and read<br>address change compare turned on.|575|510|460|400|MHz|
|TPW_WF_NC(1)|Block RAM in WRITE_FIRST and<br>NO_CHANGE modes and FIFO.<br>Clock High/Low pulse width|758|855|952|952|ps, Min|
|TPW_RF(1)|Block RAM in READ_FIRST modes.<br>Clock High/Low pulse width|870|980|1087|1250|ps, Min|
|**Block RAM and FIFO Clock-to-Out Delays**|||||||
|TRCKO_DO|Clock CLK to DOUT output (without output<br>register)|1.13|1.44|1.64|1.64|ns,<br>Max|
|TRCKO_DO_REG|Clock CLK to DOUT output (with output<br>register)|0.37|0.44|0.49|0.49|ns,<br>Max|
## **Notes:**
1. The MMCM and PLL DUTY_CYCLE attribute should be set to 50% to meet the pulse width requirements at the higher frequencies.
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
## **Input/Output Delay Switching Characteristics**
_Table 33:_ **Input/Output Delay Switching Characteristics**
|**Symbol**|**Description**|**Speed Grade and VCCINT Operating Voltages**|**Speed Grade and VCCINT Operating Voltages**|**Speed Grade and VCCINT Operating Voltages**|**Speed Grade and VCCINT Operating Voltages**|**Units**|
|---|---|---|---|---|---|---|
|||**1.0V**|**0.95V**||**0.90V**||
|||**-3**|**-2**|**-1/-1L**|**-1L**||
|FREFCLK|REFCLK frequency for IDELAYCTRL<br>(component mode).|200 to 800||||MHz|
||REFCLK frequency for IDELAYCTRL<br>(native mode).(1)|200 to 2400|200 to 2400|200 to 2133|200 to 2133|MHz|
|TMINPER_CLK|Minimum period for IODELAY CLK.|2.740|2.740|3.160|3.160|ns|
|TMINPER_RST|Minimum reset pulse width.|52.00||||ns|
|TIDELAY_RESOLUTION/<br>TODELAY_RESOLUTION|IDELAY/ODELAY chain resolution.|2.5 to 15||||ps|
## **Notes:**
1. PLL settings could restrict the minimum allowable data rate. For example, when using a PLL with CLKOUTPHY_MODE = VCO_HALF, the minimum frequency is PLL_FVCOMIN/2.
## **DSP48 Slice Switching Characteristics**
_Table 34:_ **DSP48 Slice Switching Characteristics**
|**Symbol**|**Description**|**Speed Grade and VCCINT**<br>**Operating Voltages**|**Speed Grade and VCCINT**<br>**Operating Voltages**|**Speed Grade and VCCINT**<br>**Operating Voltages**|**Speed Grade and VCCINT**<br>**Operating Voltages**|**Units**|
|---|---|---|---|---|---|---|
|||**1.0V**|**0.95V**||**0.90V**||
|||**-3**|**-2**|**-1/-1L**|**-1L**||
|**Maximum Frequency**|||||||
|FMAX|With all registers used|741|661|594|594|MHz|
|FMAX_PATDET|With pattern detector|687|581|512|512|MHz|
|FMAX_MULT_NOMREG|Two register multiply without MREG|462|429|361|361|MHz|
|FMAX_MULT_NOMREG_PATDET|Two register multiply without MREG with<br>pattern detect|428|387|326|326|MHz|
|FMAX_PREADD_NOADREG|Without ADREG|468|429|358|358|MHz|
|FMAX_NOPIPELINEREG|Without pipeline registers (MREG, ADREG)|335|312|260|260|MHz|
|FMAX_NOPIPELINEREG_PATDET|Without pipeline registers (MREG, ADREG)<br>with pattern detect|316|286|238|238|MHz|
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
## **Clock Buffers and Networks**
_Table 35:_ **Clock Buffers Switching Characteristics**
|**Symbol**|**Description**|**Speed Grade and**<br>**VCCINT Operating Voltages**|**Speed Grade and**<br>**VCCINT Operating Voltages**|**Speed Grade and**<br>**VCCINT Operating Voltages**|**Speed Grade and**<br>**VCCINT Operating Voltages**|**Units**|
|---|---|---|---|---|---|---|
|||**1.0V**|**0.95V**||**0.90V**||
|||**-3**|**-2**|**-1/-1L**|**-1L**||
|**Global Clock Switching Characteristics (Including BUFGCTRL)**|||||||
|FMAX|Maximum frequency of a global clock tree (BUFG)|850|725|630|630|MHz|
|**Global Clock Buffer with Input Divide Capability (BUFGCE_DIV)**|||||||
|FMAX|Maximum frequency of a global clock buffer with input<br>divide capability (BUFGCE_DIV)|850|725|630|630|MHz|
|**Global Clock Buffer with Clock Enable (BUFGCE)**|||||||
|FMAX|Maximum frequency of a global clock buffer with clock<br>enable (BUFGCE)|850|725|630|630|MHz|
|**Leaf Clock Buffer with Clock Enable (BUFCE_LEAF)**|||||||
|FMAX|Maximum frequency of a leaf clock buffer with clock<br>enable (BUFCE_LEAF)|850|725|630|630|MHz|
|**GTH/GTY Clock Buffer with Clock Enable and Clock Input Divide Capability (BUFG_GT)**|||||||
|FMAX|Maximum frequency of a serial transceiver clock buffer<br>with clock enable and clock input divide capability|512|512|512|512|MHz|
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
## **MMCM Switching Characteristics**
_Table 36:_ **MMCM Specification**
|**Symbol**|**Description**|**Speed Grade and VCCINT**<br>**Operating Voltages**|**Speed Grade and VCCINT**<br>**Operating Voltages**|**Speed Grade and VCCINT**<br>**Operating Voltages**|**Speed Grade and VCCINT**<br>**Operating Voltages**|**Units**|
|---|---|---|---|---|---|---|
|||**1.0V**|**0.95V**||**0.90V**||
|||**-3**|**-2**|**-1/-1L**|**-1L**||
|MMCM_FINMAX|Maximum input clock frequency|1066|933|800|800|MHz|
|MMCM_FINMIN|Minimum input clock frequency|10|10|10|10|MHz|
|MMCM_FINJITTER|Maximum input clock period jitter|< 20% of clock input period or 1 ns Max|||||
|MMCM_FINDUTY|Input duty cycle range: 10–49 MHz|25–75||||%|
||Input duty cycle range: 50–199 MHz|30–70||||%|
||Input duty cycle range: 200–399 MHz|35–65||||%|
||Input duty cycle range: 400–499 MHz|40–60||||%|
||Input duty cycle range: >500 MHz|45–55||||%|
|MMCM_FMIN_PSCLK|Minimum dynamic phase shift clock frequency|0.01|0.01|0.01|0.01|MHz|
|MMCM_FMAX_PSCLK|Maximum dynamic phase shift clock frequency|550|500|450|450|MHz|
|MMCM_FVCOMIN|Minimum MMCM VCO frequency|600|600|600|600|MHz|
|MMCM_FVCOMAX|Maximum MMCM VCO frequency|1600|1440|1200|1200|MHz|
|MMCM_FBANDWIDTH|Low MMCM bandwidth at typical(1)|1.00|1.00|1.00|1.00|MHz|
||High MMCM bandwidth at typical(1)|4.00|4.00|4.00|4.00|MHz|
|MMCM_TSTATPHAOFFSET|Static phase offset of the MMCM outputs(2)|0.12|0.12|0.12|0.12|ns|
|MMCM_TOUTJITTER|MMCM output jitter|Note 3|||||
|MMCM_TOUTDUTY|MMCM output clock duty cycle precision(4)|0.165|0.20|0.20|0.20|ns|
|MMCM_TLOCKMAX|MMCM maximum lock time for MMCM_FPFDMIN<br>frequencies above 20 MHz|100|100|100|100|µs|
||MMCM maximum lock time for MMCM_FPFDMIN<br>frequencies from 10 MHz to 20 MHz|200|200|200|200|µs|
|MMCM_FOUTMAX|MMCM maximum output frequency|850|725|630|630|MHz|
|MMCM_FOUTMIN|MMCM minimum output frequency(4)(5)|4.69|4.69|4.69|4.69|MHz|
|MMCM_TEXTFDVAR|External clock feedback variation|< 20% of clock input period or 1 ns Max|||||
|MMCM_RSTMINPULSE|Minimum reset pulse width|5.00|5.00|5.00|5.00|ns|
|MMCM_FPFDMAX|Maximum frequency at the phase frequency<br>detector|550|500|450|450|MHz|
|MMCM_FPFDMIN|Minimum frequency at the phase frequency<br>detector|10|10|10|10|MHz|
|MMCM_TFBDELAY|Maximum delay in the feedback path|5 ns Max or one clock cycle|||||
|MMCM_FDRPCLK_MAX|Maximum DRP clock frequency|200|200|200|200|MHz|
## **Notes:**
1. The MMCM does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies.
2. The static offset is measured between any MMCM outputs with identical phase.
3. Values for this parameter are available in the Clocking Wizard.
4. Includes global clock buffer.
5. Calculated as FVCO/128 assuming output duty cycle is 50%.
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## **PLL Switching Characteristics**
_Table 37:_ **PLL Specification[(1)]**
|**Symbol**|**Description**|**Speed Grade and VCCINT**<br>**Operating Voltages**|**Speed Grade and VCCINT**<br>**Operating Voltages**|**Speed Grade and VCCINT**<br>**Operating Voltages**|**Speed Grade and VCCINT**<br>**Operating Voltages**|**Units**|
|---|---|---|---|---|---|---|
|||**1.0V**|**0.95V**||**0.90V**||
|||**-3**|**-2**|**-1/-1L**|**-1L**||
|PLL_FINMAX|Maximum input clock frequency|1066|933|800|800|MHz|
|PLL_FINMIN|Minimum input clock frequency|70|70|70|70|MHz|
|PLL_FINJITTER|Maximum input clock period jitter|< 20% of clock input period or 1 ns Max|||||
|PLL_FINDUTY|Input duty cycle range: 70–399 MHz|35–65||||%|
||Input duty cycle range: 400–499 MHz|40–60||||%|
||Input duty cycle range: >500 MHz|45–55||||%|
|PLL_FVCOMIN|Minimum PLL VCO frequency|600|600|600|600|MHz|
|PLL_FVCOMAX|Maximum PLL VCO frequency|1335|1335|1200|1200|MHz|
|PLL_TSTATPHAOFFSET|Static phase offset of the PLL outputs(2)|0.12|0.12|0.12|0.12|ns|
|PLL_TOUTJITTER|PLL output jitter|Note 3|||||
|PLL_TOUTDUTY|PLL CLKOUT0/CLKOUT0B/CLKOUT1/CLKOUT1B<br>duty-cycle precision(4)|0.165|0.20|0.20|0.20|ns|
|PLL_TLOCKMAX|PLL maximum lock time|100||||µs|
|PLL_FOUTMAX|PLL maximum output frequency at<br>CLKOUT0/CLKOUT0B/CLKOUT1/CLKOUT1B|850|725|630|630|MHz|
||PLL maximum output frequency at CLKOUTPHY|2670|2670|2400|2400|MHz|
|PLL_FOUTMIN|PLL minimum output frequency at<br>CLKOUT0/CLKOUT0B/CLKOUT1/CLKOUT1B(5)|4.69|4.69|4.69|4.69|MHz|
||PLL minimum output frequency at CLKOUTPHY|2 x VCO mode: 1200<br>1 x VCO mode: 600<br>0.5 x VCO mode: 300||||MHz|
|PLL_RSTMINPULSE|Minimum reset pulse width|5.00|5.00|5.00|5.00|ns|
|PLL_FPFDMAX|Maximum frequency at the phase frequency<br>detector|667.5|667.5|600|600|MHz|
|PLL_FPFDMIN|Minimum frequency at the phase frequency<br>detector|70|70|70|70|MHz|
|PLL_FBANDWIDTH|PLL bandwidth at typical|15|15|15|15|MHz|
|PLL_FDRPCLK_MAX|Maximum DRP clock frequency|200|200|200|200|MHz|
## **Notes:**
1. The PLL does not filter typical spread-spectrum input clocks because they are usually far below the loop filter frequencies.
2. The static offset is measured between any PLL outputs with identical phase.
3. Values for this parameter are available in the Clocking Wizard.
4. Includes global clock buffer.
5. Calculated as FVCO/128 assuming output duty cycle is 50%.
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## **Device Pin-to-Pin Output Parameter Guidelines**
The pin-to-pin numbers in Table 38 through Table 41 are based on the clock root placement in the center of the device. The actual pin-to-pin values will vary if the root placement selected is different. Consult the Vivado Design Suite timing report for the actual pin-to-pin values.
_Table 38:_ **Global Clock Input to Output Delay Without MMCM/PLL (Near Clock Region)**
|**Symbol**|**Description**|**Device**|**Speed Grade and VCCINT**<br>**Operating Voltages**|**Speed Grade and VCCINT**<br>**Operating Voltages**|**Speed Grade and VCCINT**<br>**Operating Voltages**|**Speed Grade and VCCINT**<br>**Operating Voltages**|**Speed Grade and VCCINT**<br>**Operating Voltages**|**Units**|
|---|---|---|---|---|---|---|---|---|
||||**1.0V**|**0.95V**|||**0.90V**||
||||**-3**|**-2**|**-1**|**-1L**|**-1L**||
|**SSTL15 Global Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate,****_without_**<br>**MMCM/PLL.**|||||||||
|TICKOF|Global clock input and output flip-flop_without_<br>MMCM/PLL (near clock region)|XCKU025|N/A|6.07|7.00|N/A|N/A|ns|
|||XCKU035|5.40|6.21|7.05|7.05|7.44|ns|
|||XCKU040|5.40|6.21|7.05|7.05|7.44|ns|
|||XCKU060|5.19|5.99|6.93|6.93|7.19|ns|
|||XCKU085|5.20|6.08|7.08|7.08|7.19|ns|
|||XCKU095|N/A|6.09|7.13|N/A|N/A|ns|
|||XCKU115|5.20|6.08|7.08|7.08|7.19|ns|
|||XQKU040|N/A|6.21|7.17|N/A|N/A|ns|
|||XQKU060|N/A|5.99|6.93|N/A|N/A|ns|
|||XQKU095|N/A|6.09|7.13|N/A|N/A|ns|
|||XQKU115|N/A|6.08|7.08|N/A|N/A|ns|
## **Notes:**
1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible I/O and CLB flip-flops are clocked by the global clock net in a single SLR.
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 39:_ **Global Clock Input to Output Delay Without MMCM/PLL (Far Clock Region)**
|**Symbol**|**Description**|**Device**|**Speed Grade and VCCINT**<br>**Operating Voltages**|**Speed Grade and VCCINT**<br>**Operating Voltages**|**Speed Grade and VCCINT**<br>**Operating Voltages**|**Speed Grade and VCCINT**<br>**Operating Voltages**|**Speed Grade and VCCINT**<br>**Operating Voltages**|**Units**|
|---|---|---|---|---|---|---|---|---|
||||**1.0V**|**0.95V**|||**0.90V**||
||||**-3**|**-2**|**-1**|**-1L**|**-1L**||
|**SSTL15 Global Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate,****_without_**<br>**MMCM/PLL.**|||||||||
|TICKOF_FAR|Global clock input and output flip-flop_without_<br>MMCM/PLL (far clock region)|XCKU025|N/A|6.40|7.37|N/A|N/A|ns|
|||XCKU035|5.84|6.73|7.64|7.64|8.09|ns|
|||XCKU040|5.84|6.73|7.64|7.64|8.09|ns|
|||XCKU060|5.94|6.84|7.91|7.91|8.22|ns|
|||XCKU085|5.95|6.98|8.12|8.12|8.21|ns|
|||XCKU095|N/A|6.67|7.69|N/A|N/A|ns|
|||XCKU115|5.95|6.98|8.12|8.12|8.21|ns|
|||XQKU040|N/A|6.73|7.75|N/A|N/A|ns|
|||XQKU060|N/A|6.84|7.91|N/A|N/A|ns|
|||XQKU095|N/A|6.67|7.69|N/A|N/A|ns|
|||XQKU115|N/A|6.98|8.12|N/A|N/A|ns|
## **Notes:**
1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible I/O and CLB flip-flops are clocked by the global clock net in a single SLR.
_Table 40:_ **Global Clock Input to Output Delay With MMCM**
|**Symbol**|**Description**|**Device**|**Speed Grade and VCCINT**<br>**Operating Voltages**|**Speed Grade and VCCINT**<br>**Operating Voltages**|**Speed Grade and VCCINT**<br>**Operating Voltages**|**Speed Grade and VCCINT**<br>**Operating Voltages**|**Speed Grade and VCCINT**<br>**Operating Voltages**|**Units**|
|---|---|---|---|---|---|---|---|---|
||||**1.0V**|**0.95V**|||**0.90V**||
||||**-3**|**-2**|**-1**|**-1L**|**-1L**||
|**SSTL15 Global Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with MMCM.**|||||||||
|TICKOFMMCMCC|Global clock input and output flip-flop_with_<br>MMCM|XCKU025|N/A|1.80|1.88|N/A|N/A|ns|
|||XCKU035|2.13|2.45|2.78|2.78|3.72|ns|
|||XCKU040|2.13|2.45|2.78|2.78|3.72|ns|
|||XCKU060|1.58|1.92|2.05|2.05|2.41|ns|
|||XCKU085|1.58|1.95|2.12|2.12|2.41|ns|
|||XCKU095|N/A|1.59|1.85|N/A|N/A|ns|
|||XCKU115|1.58|1.95|2.12|2.12|2.41|ns|
|||XQKU040|N/A|1.81|1.91|N/A|N/A|ns|
|||XQKU060|N/A|1.92|2.05|N/A|N/A|ns|
|||XQKU095|N/A|1.59|1.85|N/A|N/A|ns|
|||XQKU115|N/A|1.95|2.12|N/A|N/A|ns|
## **Notes:**
1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible I/O and CLB flip-flops are clocked by the global clock net in a single SLR.
2. MMCM output jitter is already included in the timing calculation.
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_Table 41:_ **Global Clock Input to Output Delay With PLL**
|**Symbol**|**Description**|**Device**|**Speed Grade and VCCINT**<br>**Operating Voltages**|**Speed Grade and VCCINT**<br>**Operating Voltages**|**Speed Grade and VCCINT**<br>**Operating Voltages**|**Speed Grade and VCCINT**<br>**Operating Voltages**|**Speed Grade and VCCINT**<br>**Operating Voltages**|**Units**|
|---|---|---|---|---|---|---|---|---|
||||**1.0V**|**0.95V**|||**0.90V**||
||||**-3**|**-2**|**-1**|**-1L**|**-1L**||
|**SSTL15 Global Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with PLL.**|||||||||
|TICKOF_PLL_CC|Global clock input and output flip-flop_with_<br>PLL|XCKU025|N/A|5.39|6.11|N/A|N/A|ns|
|||XCKU035|4.25|4.46|5.08|5.08|5.46|ns|
|||XCKU040|4.25|4.46|5.08|5.08|5.46|ns|
|||XCKU060|5.13|5.83|6.66|6.66|6.95|ns|
|||XCKU085|5.14|5.96|6.85|6.85|6.96|ns|
|||XCKU095|N/A|5.70|6.49|N/A|N/A|ns|
|||XCKU115|5.14|5.96|6.85|6.85|6.96|ns|
|||XQKU040|N/A|5.72|6.50|N/A|N/A|ns|
|||XQKU060|N/A|5.83|6.66|N/A|N/A|ns|
|||XQKU095|N/A|5.70|6.49|N/A|N/A|ns|
|||XQKU115|N/A|5.96|6.85|N/A|N/A|ns|
## **Notes:**
1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible I/O and CLB flip-flops are clocked by the global clock net in a single SLR.
2. PLL output jitter is already included in the timing calculation.
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
## **Device Pin-to-Pin Input Parameter Guidelines**
The pin-to-pin numbers in Table 42 through Table 43 are based on the clock root placement in the center of the device. The actual pin-to-pin values will vary if the root placement selected is different. Consult the Vivado Design Suite timing report for the actual pin-to-pin values.
_Table 42:_ **Global Clock Input Setup and Hold With MMCM**
|**Symbol**|**Description**|**Description**|**Device**|**Speed Grade, VCCINT Operating Voltage,**<br>**and Temperature Range**|**Speed Grade, VCCINT Operating Voltage,**<br>**and Temperature Range**|**Speed Grade, VCCINT Operating Voltage,**<br>**and Temperature Range**|**Speed Grade, VCCINT Operating Voltage,**<br>**and Temperature Range**|**Speed Grade, VCCINT Operating Voltage,**<br>**and Temperature Range**|**Speed Grade, VCCINT Operating Voltage,**<br>**and Temperature Range**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|
|||||**1.0V**|**0.95V**||||**0.90V**||
|||||**-3E**|**-2E/I **|**-1C/I**|**-1M**|**-1LI**|**-1LI**||
|**Input Setup and Hold Time Relative to Global Clock Input Signal using SSTL15 Standard.(1)(2)(3)**|||||||||||
|TPSMMCMCC_KU025|Global clock input and<br>input flip-flop (or latch)<br>with MMCM|Setup|XCKU025|N/A|2.16|2.51|N/A|N/A|N/A|ns|
|TPHMMCMCC_KU025||Hold||N/A|–0.48|–0.48|N/A|N/A|N/A|ns|
|TPSMMCMCC_KU035||Setup|XCKU035|1.70|1.72|1.74|N/A|1.74|2.07|ns|
|TPHMMCMCC_KU035||Hold||–0.23|–0.23|–0.23|N/A|–0.23|–0.13|ns|
|TPSMMCMCC_KU040||Setup|XCKU040|1.70|1.72|1.74|N/A|1.74|2.07|ns|
|TPHMMCMCC_KU040||Hold||–0.23|–0.23|–0.23|N/A|–0.23|–0.13|ns|
|TPSMMCMCC_KU060||Setup|XCKU060|2.21|2.23|2.51|N/A|2.51|2.55|ns|
|TPHMMCMCC_KU060||Hold||–0.47|–0.47|–0.47|N/A|–0.47|–0.15|ns|
|TPSMMCMCC_KU085||Setup|XCKU085|2.21|2.23|2.51|N/A|2.51|2.55|ns|
|TPHMMCMCC_KU085||Hold||–0.37|–0.37|–0.37|N/A|–0.37|–0.15|ns|
|TPSMMCMCC_KU095||Setup|XCKU095|N/A|2.25|2.55|N/A|N/A|N/A|ns|
|TPHMMCMCC_KU095||Hold||N/A|–0.47|–0.47|N/A|N/A|N/A|ns|
|TPSMMCMCC_KU115||Setup|XCKU115|2.21|2.23|2.51|N/A|2.51|2.55|ns|
|TPHMMCMCC_KU115||Hold||–0.37|–0.37|–0.37|N/A|–0.37|–0.15|ns|
|TPSMMCMCC_KU040||Setup|XQKU040|N/A|2.23|2.58|2.60|N/A|N/A|ns|
|TPHMMCMCC_KU040||Hold||N/A|–0.45|–0.45|–0.45|N/A|N/A|ns|
|TPSMMCMCC_KU060||Setup|XQKU060|N/A|2.23|2.51|2.52|N/A|N/A|ns|
|TPHMMCMCC_KU060||Hold||N/A|–0.47|–0.47|–0.47|N/A|N/A|ns|
|TPSMMCMCC_KU095||Setup|XQKU095|N/A|2.25|2.55|2.56|N/A|N/A|ns|
|TPHMMCMCC_KU095||Hold||N/A|–0.47|–0.47|–0.47|N/A|N/A|ns|
|TPSMMCMCC_KU115||Setup|XQKU115|N/A|2.23|2.51|N/A|N/A|N/A|ns|
|TPHMMCMCC_KU115||Hold||N/A|–0.37|–0.37|N/A|N/A|N/A|ns|
## **Notes:**
1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global clock input signal using the slowest process, slowest temperature, and slowest voltage. Hold time is measured relative to the global clock input signal using the fastest process, fastest temperature, and fastest voltage.
2. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible I/O and CLB flip-flops are clocked by the global clock net in a single SLR.
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
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_Table 43:_ **Global Clock Input Setup and Hold With PLL**
|**Symbol**|**Description**|**Description**|**Device**|**Speed Grade, VCCINT Operating Voltage,**<br>**and Temperature Range**|**Speed Grade, VCCINT Operating Voltage,**<br>**and Temperature Range**|**Speed Grade, VCCINT Operating Voltage,**<br>**and Temperature Range**|**Speed Grade, VCCINT Operating Voltage,**<br>**and Temperature Range**|**Speed Grade, VCCINT Operating Voltage,**<br>**and Temperature Range**|**Speed Grade, VCCINT Operating Voltage,**<br>**and Temperature Range**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|
|||||**1.0V**|**0.95V**||||**0.90V**||
|||||**-3**|**-2**|**-1**|**-1M**|**-1L**|**-1L**||
|**Input Setup and Hold Time Relative to Global Clock Input Signal using SSTL15 Standard.(1)(2)(3)**|||||||||||
|TPSPLLCC_KU025|Global clock input and<br>input flip-flop (or latch)<br>with PLL|Setup|XCKU025|N/A|–0.48|–0.48|N/A|N/A|N/A|ns|
|TPHPLLCC_KU025||Hold||N/A|2.42|2.70|N/A|N/A|N/A|ns|
|TPSPLLCC_KU035||Setup|XCKU035|0.00|0.00|0.00|N/A|0.00|0.00|ns|
|TPHPLLCC_KU035||Hold||1.36|1.59|1.79|N/A|1.79|1.79|ns|
|TPSPLLCC_KU040||Setup|XCKU040|0.00|0.00|0.00|N/A|0.00|0.00|ns|
|TPHPLLCC_KU040||Hold||1.36|1.59|1.79|N/A|1.79|1.79|ns|
|TPSPLLCC_KU060||Setup|XCKU060|–0.70|–0.70|–0.70|N/A|–0.70|–0.78|ns|
|TPHPLLCC_KU060||Hold||2.18|2.41|2.75|N/A|2.75|2.98|ns|
|TPSPLLCC_KU085||Setup|XCKU085|–0.66|–0.66|–0.66|N/A|–0.66|–0.78|ns|
|TPHPLLCC_KU085||Hold||2.18|2.46|2.83|N/A|2.83|2.98|ns|
|TPSPLLCC_KU095||Setup|XCKU095|N/A|–0.94|–0.94|N/A|N/A|N/A|ns|
|TPHPLLCC_KU095||Hold||N/A|2.36|2.71|N/A|N/A|N/A|ns|
|TPSPLLCC_KU115||Setup|XCKU115|–0.66|–0.66|–0.66|N/A|–0.66|–0.78|ns|
|TPHPLLCC_KU115||Hold||2.18|2.46|2.83|N/A|2.83|2.98|ns|
|TPSPLLCC_KU040||Setup|XQKU040|N/A|–0.67|–0.67|–0.67|N/A|N/A|ns|
|TPHPLLCC_KU040||Hold||N/A|2.48|2.83|2.84|N/A|N/A|ns|
|TPSPLLCC_KU060||Setup|XQKU060|N/A|–0.70|–0.70|–0.70|N/A|N/A|ns|
|TPHPLLCC_KU060||Hold||N/A|2.41|2.75|2.75|N/A|N/A|ns|
|TPSPLLCC_KU095||Setup|XQKU095|N/A|–0.94|–0.94|–0.94|N/A|N/A|ns|
|TPHPLLCC_KU095||Hold||N/A|2.36|2.71|2.71|N/A|N/A|ns|
|TPSPLLCC_KU115||Setup|XQKU115|N/A|–0.66|–0.66|N/A|N/A|N/A|ns|
|TPHPLLCC_KU115||Hold||N/A|2.46|2.83|N/A|N/A|N/A|ns|
## **Notes:**
1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global clock input signal using the slowest process, slowest temperature, and slowest voltage. Hold time is measured relative to the global clock input signal using the fastest process, fastest temperature, and fastest voltage.
2. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible I/O and CLB flip-flops are clocked by the global clock net in a single SLR.
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 44:_ **Sampling Window**
|_Table 44:_ **Sampling Window**||||||||
|---|---|---|---|---|---|---|---|
|**Description**|**Speed Grade and VCCINT Operating Voltages**||||||**Units**|
||**1.0V**||**0.95V**|||**0.90V**||
||**-3**|**-2E**|**-2I**|**-1**|**-1L**|**-1L**||
|TSAMP_BUFG(1)|510|560|610|610|610|610|ps|
|TSAMP_NATIVE_DPA|100|100|100|125|125|150|ps|
|TSAMP_NATIVE_BISC|60|60|60|85|85|110|ps|
## **Notes:**
1. This parameter indicates the total sampling error of the Kintex UltraScale FPGAs DDR input registers, measured across voltage, temperature, and process. The characterization methodology uses the MMCM to capture the DDR input registers’ edges of operation. These measurements include: CLK0 MMCM jitter, MMCM accuracy (phase offset), and MMCM phase shift resolution. These measurements do not include package or clock tree skew.
## **Package Parameter Guidelines**
The parameters in this section provide the necessary values for calculating timing budgets for clock transmitter and receiver data-valid windows.
_Table 45:_ **Package Skew**
|**Symbol**|**Description**|**Device**|**Package**|**Value**|**Units**|
|---|---|---|---|---|---|
|PKGSKEW|Package Skew|XCKU025|FFVA1156|162|ps|
|||XCKU035|FBVA676|173|ps|
||||SFVA784|134|ps|
||||FBVA900|184|ps|
||||FFVA1156|168|ps|
|||XCKU040|FBVA676|173|ps|
||||SFVA784|134|ps|
||||FBVA900|184|ps|
||||FFVA1156|168|ps|
|||XCKU060|FFVA1156|168|ps|
||||FFVA1517|169|ps|
|||XCKU085|FLVA1517|217|ps|
||||FLVB1760|175|ps|
||||FLVF1924|143|ps|
|||XCKU095|FFVA1156|162|ps|
||||FFVC1517|181|ps|
||||FFVB1760|128|ps|
||||FFVB2104|191|ps|
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 45:_ **Package Skew** _**(Cont’d)**_
|**Symbol**|**Description**|**Device**|**Package**|**Value**|**Units**|
|---|---|---|---|---|---|
|PKGSKEW<br>(_cont’d)_|Package Skew|XCKU115|FLVA1517|217|ps|
||||FLVD1517|143|ps|
||||FLVB1760|177|ps|
||||FLVD1924|172|ps|
||||FLVF1924|143|ps|
||||FLVA2104|184|ps|
||||FLVB2104|198|ps|
|||XQKU040|RBA676|178|ps|
||||RFA1156|164|ps|
|||XQKU060|RFA1156|170|ps|
|||XQKU095|RFA1156|163|ps|
|||XQKU115|RLD1517|147|ps|
||||RLF1924|146|ps|
## **Notes:**
1. These values represent the worst-case skew between any two SelectIO resources in the package: shortest delay to longest delay from die pad to ball.
2. Package delay information is available for these device/package combinations. This information can be used to deskew the package.
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
## **GTH Transceiver Specifications**
## **GTH Transceiver DC Input and Output Levels**
Table 46 summarizes the DC specifications of the GTH transceivers in Kintex UltraScale FPGAs. Consult the _UltraScale Architecture GTH Transceiver User Guide_ (UG576) for further details.
_Table 46:_ **GTH Transceiver DC Specifications**
|**Symbol**|**DC Parameter**|**Conditions**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|DVPPIN|Differential peak-to-peak input<br>voltage (external AC coupled)|>10.3125 Gb/s|150|–|1250|mV|
|||6.6 Gb/s to 10.3125 Gb/s|150|–|1250|mV|
|||≤6.6 Gb/s|150|–|2000|mV|
|VIN|Single-ended input voltage.<br>Voltage measured at the pin<br>referenced to GND.|DC coupled<br>VMGTAVTT = 1.2V|–400|–|VMGTAVTT|mV|
|VCMIN|Common mode input voltage|DC coupled<br>VMGTAVTT = 1.2V|–|2/3 VMGTAVTT|–|mV|
|DVPPOUT|Differential peak-to-peak output<br>voltage(1)|Transmitter output swing<br>is set to1100|800|–|–|mV|
|VCMOUTDC|Common mode output voltage:<br>DC coupled (equation based)|When remote RX is<br>terminated to GND|VMGTAVTT/2 – DVPPOUT/4|||mV|
|||When remote RX<br>termination is floating|VMGTAVTT– DVPPOUT/2|||mV|
|||When remote RX is<br>terminated to VRX_TERM(2)|VMGTAVTT<br>DVPPOUT<br>4<br>----------------------**-**<br>–<br>VMGTAVTT<br>VRX_TERM<br>–<br>2<br>--------------------------------------------------------<br><br><br><br><br>–|||mV|
|VCMOUTAC|Common mode output voltage: AC coupled (equation based)||VMGTAVTT– DVPPOUT/2|||mV|
|RIN|Differential input resistance||–|100|–|Ω|
|ROUT|Differential output resistance||–|100|–|Ω|
|TOSKEW|Transmitter output pair (TXP and TXN) intra-pair skew<br>(All packages)||–|–|10|ps|
|CEXT|Recommended external AC coupling capacitor(3)||–|100|–|nF|
## **Notes:**
1. The output swing and pre-emphasis levels are programmable using the attributes discussed in the _UltraScale Architecture GTH Transceiver User Guide_ (UG576), and can result in values lower than reported in this table.
2. VRX_TERM is the remote RX termination voltage.
3. Other values can be used as appropriate to conform to specific protocols and standards.
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
**==> picture [526 x 75] intentionally omitted <==**
**----- Start of picture text -----**<br>
+V P<br>Single-Ended<br>Peak-to-Peak<br>N Voltage<br>0<br>ds892_03_120414<br>**----- End of picture text -----**<br>
_Figure 3:_ **Single-Ended Peak-to-Peak Voltage**
**==> picture [508 x 113] intentionally omitted <==**
**----- Start of picture text -----**<br>
+V<br>Differential<br>0 Peak-to-Peak<br>Voltage<br>–V P–N<br>Differential peak-to-peak voltage = (Single-ended peak-to-peak voltage) x 2 ds892_04_120414<br>**----- End of picture text -----**<br>
_Figure 4:_ **Differential Peak-to-Peak Voltage**
Table 47 and Table 48 summarize the DC specifications of the GTH transceivers input and output clocks in Kintex UltraScale FPGAs. Consult the _UltraScale Architecture GTH Transceiver User Guide_ (UG576) for further details.
_Table 47:_ **GTH Transceiver Clock DC Input Level Specification**
|**Symbol**|**DC Parameter**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|
|VIDIFF|Differential peak-to-peak input voltage|250|–|2000|mV|
|RIN|Differential input resistance|–|100|–|Ω|
|CEXT|Required external AC coupling capacitor|–|10|–|nF|
_Table 48:_ **GTH Transceiver Clock Output Level Specification**
|**Symbol**|**Description**|**Conditions**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|VOL|Output low voltage for P and N|RT = 100Ωacross P and N signals|–|400|–|mV|
|VOH|Output high voltage for P and N|RT = 100Ωacross P and N signals|–|760|–|mV|
|VDDOUT|Differential output voltage<br>(P–N), P = High<br>(N–P), N = High|RT = 100Ωacross P and N signals|–|±360|–|mV|
|VCMOUT|Common mode voltage|RT = 100Ωacross P and N signals|–|580|–|mV|
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
## **GTH Transceiver Switching Characteristics**
Consult the _UltraScale Architecture GTH Transceiver User Guide_ (UG576) for further information.
_Table 49:_ **GTH Transceiver Performance**
|**Symbol**|**Description**|**Output**<br>**Divider**|**Speed Grade, Temperature Ranges,**<br>**and VCCINT Operating Voltages**|**Speed Grade, Temperature Ranges,**<br>**and VCCINT Operating Voltages**|**Speed Grade, Temperature Ranges,**<br>**and VCCINT Operating Voltages**|**Speed Grade, Temperature Ranges,**<br>**and VCCINT Operating Voltages**|**Speed Grade, Temperature Ranges,**<br>**and VCCINT Operating Voltages**|**Speed Grade, Temperature Ranges,**<br>**and VCCINT Operating Voltages**|**Speed Grade, Temperature Ranges,**<br>**and VCCINT Operating Voltages**|**Speed Grade, Temperature Ranges,**<br>**and VCCINT Operating Voltages**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|
||||**1.0V**||**0.95V**||||**0.90V**|||
||||**-3E**||**-2E, -2I**||**-1C, -1I, -1M,**<br>**-1LI**||**-1LI**|||
|Package Type|||FF/FL|FB/SF|FF/FL<br>RF|FB/SF<br>RB|All Packages||All Packages|||
|FGTHMAX|GTH maximum line rate||16.375|12.5|16.375|12.5|12.5||12.5(1)||Gb/s|
|FGTHMIN|GTH minimum line rate||0.5|0.5|0.5|0.5|0.5||0.5||Gb/s|
||||Min|Max|Min|Max|Min|Max|Min|Max||
|FGTHCRANGE|CPLL line rate<br>range(2)|1|4.0|12.5|4.0|12.5|4.0|8.5|4.0|8.5|Gb/s|
|||2|2.0|6.25|2.0|6.25|2.0|4.25|2.0|4.25|Gb/s|
|||4|1.0|3.125|1.0|3.125|1.0|2.125|1.0|2.125|Gb/s|
|||8|0.5|1.5625|0.5|1.5625|0.5|1.0625|0.5|1.0625|Gb/s|
|||16|N/A||||||||Gb/s|
||||Min|Max|Min|Max|Min|Max|Min|Max||
|FGTHQRANGE1|QPLL0 line rate<br>range(3)|1|9.8|16.375|9.8|16.375|9.8|12.5|9.8|12.5|Gb/s|
|||2|4.9|8.1875|4.9|8.1875|4.9|8.1875|4.9|8.1875|Gb/s|
|||4|2.45|4.0938|2.45|4.0938|2.45|4.0938|2.45|4.0938|Gb/s|
|||8|1.225|2.0469|1.225|2.0469|1.225|2.0469|1.225|2.0469|Gb/s|
|||16|0.6125|1.0234|0.6125|1.0234|0.6125|1.0234|0.6125|1.0234|Gb/s|
||||Min|Max|Min|Max|Min|Max|Min|Max||
|FGTHQRANGE2|QPLL1 line rate<br>range(4)|1|8.0|13.0|8.0|13.0|8.0|12.5|8.0|12.5|Gb/s|
|||2|4.0|6.5|4.0|6.5|4.0|6.5|4.0|6.5|Gb/s|
|||4|2.0|3.25|2.0|3.25|2.0|3.25|2.0|3.25|Gb/s|
|||8|1.0|1.625|1.0|1.625|1.0|1.625|1.0|1.625|Gb/s|
|||16|0.5|0.8125|0.5|0.8125|0.5|0.8125|0.5|0.8125|Gb/s|
||||Min|Max|Min|Max|Min|Max|Min|Max||
|FCPLLRANGE|CPLL frequency|range|2.0|6.25|2.0|6.25|2.0|4.25|2.0|4.25|GHz|
|FQPLL0RANGE|QPLL0 frequency range||9.8|16.375|9.8|16.375|9.8|16.375|9.8|16.375|GHz|
|FQPLL1RANGE|QPLL1 frequency range||8.0|13.0|8.0|13.0|8.0|13.0|8.0|13.0|GHz|
## **Notes:**
1. Designs must use Vivado Design Suite v2015.4.1 or later to achieve 12.5 Gb/s.
2. The values listed are the rounded results of the calculated equation (2 x CPLL_Frequency)/Output_Divider.
3. The values listed are the rounded results of the calculated equation (QPLL0_Frequency)/Output_Divider.
4. The values listed are the rounded results of the calculated equation (QPLL1_Frequency)/Output_Divider.
_Table 50:_ **GTH Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics**
|**Symbol**|**Description**|**All Devices**|**All Devices**|**All Devices**|**Units**|
|---|---|---|---|---|---|
|FGTHDRPCLK|GTHDRPCLK maximum frequency|250|||MHz|
|||||||
|DS892 (v1.14) February 2, 2017<br>www.xilinx.com|||Sd Fdbk|||
||||en eeac|||
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 51:_ **GTH Transceiver Reference Clock Switching Characteristics**
|**Symbol**|**Description**|**Conditions**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|FGCLK|Reference clock frequency range||60|–|820|MHz|
|TRCLK|Reference clock rise time|20% – 80%|–|200|–|ps|
|TFCLK|Reference clock fall time|80% – 20%|–|200|–|ps|
|TDCREF|Reference clock duty cycle|Transceiver PLL only|40|50|60|%|
**==> picture [328 x 86] intentionally omitted <==**
**----- Start of picture text -----**<br>
TRCLK<br>80%<br>20%<br>TFCLK<br>**----- End of picture text -----**<br>
**==> picture [43 x 5] intentionally omitted <==**
**----- Start of picture text -----**<br>
ds892_05_120414<br>**----- End of picture text -----**<br>
_Figure 5:_ **Reference Clock Timing Parameters**
_Table 52:_ **GTH Transceiver Reference Clock Oscillator Selection Phase Noise Mask**
|**Symbol**|**Description**|**Offset**<br>**Frequency**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|QPLLREFCLKMASK(1)(2)|QPLL0/QPLL1 reference clock select<br>phase noise mask at<br>REFCLK frequency = 312.5 MHz.|10 kHz|–|–|–105|dBc/Hz|
|||100 kHz|–|–|–124||
|||1 MHz|–|–|–130||
|CPLLREFCLKMASK(1)(2)|CPLL reference clock select phase noise<br>mask at REFCLK frequency = 312.5 MHz.|10 kHz|–|–|–105|dBc/Hz|
|||100 kHz|–|–|–124||
|||1 MHz|–|–|–130||
|||50 MHz|–|–|–140||
## **Notes:**
1. For reference clock frequencies other than 312.5 MHz, adjust the phase-noise mask values by 20 x Log(N/312.5) where N is the new reference clock frequency in MHz.
2. This reference clock phase-noise mask is superseded by any reference clock phase-noise mask that is specified in a supported protocol, e.g., PCIe.
_Table 53:_ **GTH Transceiver PLL/Lock Time Adaptation**
|**Symbol**|**Description**|**Conditions**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|TLOCK|Initial PLL lock||–|–|1|ms|
|TDLOCK|Clock recovery phase acquisition and<br>adaptation time for decision<br>feedback equalizer (DFE).|After the PLL is locked to<br>the reference clock, this is<br>the time it takes to lock<br>the clock data recovery<br>(CDR) to the data present<br>at the input.|–|50,000|37 x 106|UI|
||Clock recovery phase acquisition and<br>adaptation time for low-power mode<br>(LPM) when the DFE is disabled.||–|50,000|2.3 x 106|UI|
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 54:_ **GTH Transceiver User Clock Switching Characteristics[(1)]**
|**Symbol**|**Description**|**Data Width Conditions**<br>**(Bit)**|**Data Width Conditions**<br>**(Bit)**|**Speed Grade, Temperature Ranges,**<br>**and VCCINT Operating Voltages**|**Speed Grade, Temperature Ranges,**<br>**and VCCINT Operating Voltages**|**Speed Grade, Temperature Ranges,**<br>**and VCCINT Operating Voltages**|**Speed Grade, Temperature Ranges,**<br>**and VCCINT Operating Voltages**|**Units**|
|---|---|---|---|---|---|---|---|---|
|||||**1.0V**|**0.95V**||**0.90V**||
|||**Internal**<br>**Logic**|**Interconnect**<br>**Logic**|<br>**-3E**|**-2E, -2I**|**-1C, -1I,**<br>**-1M, -1LI**|**-1LI**||
|FTXOUTPMA|TXOUTCLK maximum frequency sourced<br>from OUTCLKPMA|||511.719|511.719|390.625|390.625|MHz|
|FRXOUTPMA|RXOUTCLK maximum frequency sourced<br>from OUTCLKPMA|||511.719|511.719|390.625|390.625|MHz|
|FTXOUTPROGDIV|TXOUTCLK maximum frequency sourced<br>from TXPROGDIVCLK|||511.719|511.719|511.719|511.719|MHz|
|FRXOUTPROGDIV|RXOUTCLK maximum frequency sourced<br>from RXPROGDIVCLK|||511.719|511.719|511.719|511.719|MHz|
|FTXIN|TXUSRCLK<br>maximum<br>frequency|16|16, 32|511.719|511.719|390.625|390.625|MHz|
|||32|32, 64|511.719|511.719|390.625|390.625|MHz|
|||20|20, 40|409.375|409.375|312.500|312.500|MHz|
|||40|40, 80|409.375|409.375|312.500|312.500|MHz|
|FRXIN|RXUSRCLK<br>maximum<br>frequency|16|16, 32|511.719|511.719|390.625|390.625|MHz|
|||32|32, 64|511.719|511.719|390.625|390.625|MHz|
|||20|20, 40|409.375|409.375|312.500|312.500|MHz|
|||40|40, 80|409.375|409.375|312.500|312.500|MHz|
|FTXIN2|TXUSRCLK2<br>maximum<br>frequency|16|16|511.719|511.719|390.625|390.625|MHz|
|||16, 32|32|511.719|511.719|390.625|390.625|MHz|
|||32|64|255.860|255.860|195.313|195.313|MHz|
|||20|20|409.375|409.375|312.500|312.500|MHz|
|||20, 40|40|409.375|409.375|312.500|312.500|MHz|
|||40|80|204.688|204.688|156.250|156.250|MHz|
|FRXIN2|RXUSRCLK2<br>maximum<br>frequency|16|16|511.719|511.719|390.625|390.625|MHz|
|||16, 32|32|511.719|511.719|390.625|390.625|MHz|
|||32|64|255.860|255.860|195.313|195.313|MHz|
|||20|20|409.375|409.375|312.500|312.500|MHz|
|||20, 40|40|409.375|409.375|312.500|312.500|MHz|
|||40|80|204.688|204.688|156.250|156.250|MHz|
## **Notes:**
1. Clocking must be implemented as described in _UltraScale Architecture GTH Transceiver User Guide_ (UG576).
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 55:_ **GTH Transceiver Transmitter Switching Characteristics**
|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|FGTHTX|Serial data rate range||0.500|–|FGTHMAX|Gb/s|
|TRTX|TX rise time|20%–80%|–|40|–|ps|
|TFTX|TX fall time|80%–20%|–|40|–|ps|
|TLLSKEW|TX lane-to-lane skew(1)||–|–|500|ps|
|VTXOOBVDPP|Electrical idle amplitude||–|–|15|mV|
|TTXOOBTRANSITION|Electrical idle transition time||–|–|140|ns|
|TJ16.3_QPLL|Total jitter(2)(4)|16.3 Gb/s|–|–|0.28|UI|
|DJ16.3_QPLL|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ15_QPLL|Total jitter(2)(4)|15.0 Gb/s|–|–|0.28|UI|
|DJ15_QPLL|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ14.1_QPLL|Total jitter(2)(4)|14.1 Gb/s|–|–|0.28|UI|
|DJ14.1_QPLL|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ14.025_QPLL|Total jitter(2)(4)|14.025 Gb/s|–|–|0.28|UI|
|DJ14.025_QPLL|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ13.1_QPLL|Total jitter(2)(4)|13.1 Gb/s|–|–|0.28|UI|
|DJ13.1_QPLL|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ12.5_QPLL|Total jitter(2)(4)|12.5 Gb/s|–|–|0.28|UI|
|DJ12.5_QPLL|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ12.5_CPLL|Total jitter(3)(4)|12.5 Gb/s|–|–|0.33|UI|
|DJ12.5_CPLL|Deterministic jitter(3)(4)||–|–|0.17|UI|
|TJ11.3_QPLL|Total jitter(2)(4)|11.3 Gb/s|–|–|0.28|UI|
|DJ11.3_QPLL|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ10.3_QPLL|Total jitter(2)(4)|10.3 Gb/s|–|–|0.28|UI|
|DJ10.3_QPLL|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ10.3_CPLL|Total jitter(3)(4)|10.3 Gb/s|–|–|0.33|UI|
|DJ10.3_CPLL|Deterministic jitter(3)(4)||–|–|0.17|UI|
|TJ9.8_QPLL|Total jitter(2)(4)|9.8 Gb/s|–|–|0.28|UI|
|DJ9.8_QPLL|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ9.8_CPLL|Total jitter(3)(4)|9.8 Gb/s|–|–|0.28|UI|
|DJ9.8_CPLL|Deterministic jitter(3)(4)||–|–|0.17|UI|
|TJ8.0_CPLL|Total jitter(3)(4)|8.0 Gb/s|–|–|0.32|UI|
|DJ8.0_CPLL|Deterministic jitter(3)(4)||–|–|0.17|UI|
|TJ6.6_CPLL|Total jitter(3)(4)|6.6 Gb/s|–|–|0.30|UI|
|DJ6.6_CPLL|Deterministic jitter(3)(4)||–|–|0.15|UI|
|TJ5.0|Total jitter(3)(4)|5.0 Gb/s|–|–|0.30|UI|
|DJ5.0|Deterministic jitter(3)(4)||–|–|0.15|UI|
|TJ4.25|Total jitter(3)(4)|4.25 Gb/s|–|–|0.30|UI|
|DJ4.25|Deterministic jitter(3)(4)||–|–|0.15|UI|
|TJ4.0L|Total jitter(3)(4)|4.0 Gb/s(5)|–|–|0.32|UI|
|DJ4.0L|Deterministic jitter(3)(4)||–|–|0.16|UI|
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 55:_ **GTH Transceiver Transmitter Switching Characteristics** _**(Cont’d)**_
|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|TJ3.2|Total jitter(3)(4)|3.2 Gb/s(6)|–|–|0.20|UI|
|DJ3.2|Deterministic jitter(3)(4)||–|–|0.10|UI|
|TJ2.5|Total jitter(3)(4)|2.5 Gb/s(7)|–|–|0.20|UI|
|DJ2.5|Deterministic jitter(3)(4)||–|–|0.10|UI|
|TJ1.25|Total jitter(3)(4)|1.25 Gb/s(8)|–|–|0.15|UI|
|DJ1.25|Deterministic jitter(3)(4)||–|–|0.06|UI|
|TJ500|Total jitter(3)(4)|500 Mb/s(9)|–|–|0.10|UI|
|DJ500|Deterministic jitter(3)(4)||–|–|0.03|UI|
## **Notes:**
1. Using same REFCLK input with TX phase alignment enabled for up to four fully populated GTH Quads at maximum line rate.
2. Using QPLL_FBDIV = 40, 40-bit internal data width. These values are NOT intended for protocol specific compliance determinations.
3. Using CPLL_FBDIV = 2, 40-bit internal data width. These values are NOT intended for protocol specific compliance determinations.
4. All jitter values are based on a bit-error ratio of 10[-12] .
5. CPLL frequency at 2.0 GHz and TXOUT_DIV = 1
6. CPLL frequency at 3.2 GHz and TXOUT_DIV = 2.
7. CPLL frequency at 2.5 GHz and TXOUT_DIV = 2.
8. CPLL frequency at 2.5 GHz and TXOUT_DIV = 4.
9. CPLL frequency at 2.0 GHz and TXOUT_DIV = 4.
_Table 56:_ **GTH Transceiver Receiver Switching Characteristics**
|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|FGTHRX|Serial data rate||0.500|–|FGTHMAX|Gb/s|
|TRXELECIDLE|Time for RXELECIDLE to respond to loss or restoration of<br>data||–|10|–|ns|
|RXOOBVDPP|OOB detect threshold peak-to-peak||60|–|150|mV|
|RXSST|Receiver spread-spectrum tracking(1)|Modulated at 33 kHz|–5000|–|0|ppm|
|RXRL|Run length (CID)||–|–|256|UI|
|RXPPMTOL|Data/REFCLK PPM offset tolerance|Bit rates ≤6.6 Gb/s|–1250|–|1250|ppm|
|||Bit rates > 6.6 Gb/s<br>and≤8.0 Gb/s|–700|–|700|ppm|
|||Bit rates > 8.0 Gb/s|–200|–|200|ppm|
|**SJ Jitter Tolerance(2)**|||||||
|JT_SJ16.3|Sinusoidal jitter (QPLL)(3)|16.3 Gb/s|0.30|–|–|UI|
|JT_SJ15|Sinusoidal jitter (QPLL)(3)|15.0 Gb/s|0.30|–|–|UI|
|JT_SJ14.1|Sinusoidal jitter (QPLL)(3)|14.1 Gb/s|0.30|–|–|UI|
|JT_SJ13.1|Sinusoidal jitter (QPLL)(3)|13.1 Gb/s|0.30|–|–|UI|
|JT_SJ12.5|Sinusoidal jitter (QPLL)(3)|12.5 Gb/s|0.30|–|–|UI|
|JT_SJ11.3|Sinusoidal jitter (QPLL)(3)|11.3 Gb/s|0.30|–|–|UI|
|JT_SJ10.3_QPLL|Sinusoidal jitter (QPLL)(3)|10.3 Gb/s|0.30|–|–|UI|
|JT_SJ10.3_CPLL|Sinusoidal jitter (CPLL)(3)|10.3 Gb/s|0.30|–|–|UI|
|JT_SJ9.8|Sinusoidal jitter (QPLL)(3)|9.8 Gb/s|0.30|–|–|UI|
|JT_SJ8.0_QPLL|Sinusoidal jitter (QPLL)(3)|8.0 Gb/s|0.44|–|–|UI|
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_Table 56:_ **GTH Transceiver Receiver Switching Characteristics** _**(Cont’d)**_
|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|JT_SJ8.0_CPLL|Sinusoidal jitter (CPLL)(3)|8.0 Gb/s|0.42|–|–|UI|
|JT_SJ6.6_CPLL|Sinusoidal jitter (CPLL)(3)|6.6 Gb/s|0.44|–|–|UI|
|JT_SJ5.0|Sinusoidal jitter (CPLL)(3)|5.0 Gb/s|0.44|–|–|UI|
|JT_SJ4.25|Sinusoidal jitter (CPLL)(3)|4.25 Gb/s|0.44|–|–|UI|
|JT_SJ4.0L|Sinusoidal jitter (CPLL)(3)|4.0 Gb/s(4)|0.45|–|–|UI|
|JT_SJ3.75|Sinusoidal jitter (CPLL)(3)|3.75 Gb/s|0.44|–|–|UI|
|JT_SJ3.2|Sinusoidal jitter (CPLL)(3)|3.2 Gb/s(5)|0.45|–|–|UI|
|JT_SJ2.5|Sinusoidal jitter (CPLL)(3)|2.5 Gb/s(6)|0.50|–|–|UI|
|JT_SJ1.25|Sinusoidal jitter (CPLL)(3)|1.25 Gb/s(7)|0.50|–|–|UI|
|JT_SJ500|Sinusoidal jitter (CPLL)(3)|500 Mb/s|0.40|–|–|UI|
|**SJ Jitter Tolerance with Stressed Eye(2)**|||||||
|JT_TJSE3.2|Total jitter with stressed eye(8)|3.2 Gb/s|0.70|–|–|UI|
|JT_TJSE6.6||6.6 Gb/s|0.70|–|–|UI|
|JT_SJSE3.2|Sinusoidal jitter with stressed eye(8)|3.2 Gb/s|0.10|–|–|UI|
|JT_SJSE6.6||6.6 Gb/s|0.10|–|–|UI|
## **Notes:**
1. Using RXOUT_DIV = 1, 2, and 4.
2. All jitter values are based on a bit error ratio of 10[–12] .
3. The frequency of the injected sinusoidal jitter is 10 MHz.
4. CPLL frequency at 2.0 GHz and RXOUT_DIV = 1
5. CPLL frequency at 3.2 GHz and RXOUT_DIV = 2.
6. CPLL frequency at 2.5 GHz and RXOUT_DIV = 2.
7. CPLL frequency at 2.5 GHz and RXOUT_DIV = 4.
8. Composite jitter with RX equalizer enabled. DFE disabled.
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
## **GTH Transceiver Electrical Compliance**
The _UltraScale Architecture GTH Transceiver User Guide_ (UG576) contains recommended use modes that ensure compliance for the protocols listed in Table 57. The transceiver wizard provides the recommended settings for those use cases and for protocol specific characteristics.
_Table 57:_ **GTH Transceiver Protocol List**
|**Protocol**|**Specification**|**Serial Rate (Gb/s)**|**Electrical**<br>**Compliance**|
|---|---|---|---|
|CAUI-10|IEEE 802.3-2012|10.3125|Compliant|
|nPPI|IEEE 802.3-2012|10.3125|Compliant|
|10GBASE-KR|IEEE 802.3-2012|10.3125|Compliant|
|SFP+|SFF-8431 (SR and LR)|9.95328–11.10|Compliant|
|XFP|INF-8077i, revision 4.5|10.3125|Compliant|
|RXAUI|CEI-6G-SR|6.25|Compliant|
|5.0G Ethernet|IEEE 802.3bx (PAR)|5.0|Compliant|
|QSGMII|QSGMII v1.2 (Cisco Systems, ENG-46158)|5.0|Compliant|
|XAUI|IEEE 802.3-2012|3.125|Compliant|
|2.5G Ethernet|IEEE 802.3bx (PAR)|2.5|Compliant|
|1000BASE-X|IEEE 802.3-2012|1.25|Compliant|
|OTU2|ITU G.8251|10.709225|Compliant|
|OTU4 (OTL4.10)|OIF-CEI-11G-SR|11.180997|Compliant|
|OC-3/12/48/192|GR-253-CORE|0.1555–9.956|Compliant|
|Interlaken|OIF-CEI-6G, OIF-CEI-11G-SR|4.25–12.5|Compliant|
|PCIe Gen1, 2, 3|PCI Express Base 3.0|2.5, 5.0, and 8.0|Compliant|
|UHD-SDI(1)|SMPTE ST-2081 6G, SMPTE St-2082 12G|6 and 12|Compliant|
|SDI(1)|SMPTE 424M-2006|0.27—2.97|Compliant|
|Hybrid Memory Cube (HMC)|HMC-15G-SR|12.5 and 15.0|Compliant|
|CPRI|CPRI_v_6_1_2014-07-01|0.6144–12.165|Compliant|
|HDMI(2)|HDMI 2.0|All|Compliant|
|Passive Optical Network (PON)|10G-EPON, 1G-EPON, NG-PON2, XG-PON,<br>and 2.5G-PON|0.155–10.3125|Compliant|
|JESD204a/b|OIF-CEI-6G, OIF-CEI-11G|3.125–12.5|Compliant|
|Serial RapidIO|RapidIO Specification 3.1|1.25–10.3125|Compliant|
|DisplayPort (Source Only)|DP 1.2B CTS|1.62–5.4|Compliant|
|Fibre Channel|FC-PI-4|1.0625–14.025|Compliant|
|SATA Gen1, 2, 3|Serial ATA Revision 3.0 Specification|1.5, 3.0, and 6.0|Compliant|
|SAS Gen1, 2, 3|T10/BSR INCITS 519|3.0, 6.0, and 12.0|Compliant|
|SFI-5|OIF-SFI5-01.0|0.625–12.5|Compliant|
## **Notes:**
1. SDI protocols require external circuitry to achieve compliance.
2. HDMI protocols require external circuitry to achieve compliance.
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
## **GTH Transceiver Protocol Jitter Characteristics**
For Table 58 through Table 63, the _UltraScale Architecture GTH Transceiver User Guide_ (UG576) contains recommended settings for optimal usage of protocol specific characteristics.
_Table 58:_ **Gigabit Ethernet Protocol Characteristics (GTH Transceivers)**
|**Description**|**Line Rate (Mb/s)**|**Min**|**Max**|**Units**|
|---|---|---|---|---|
|**Gigabit Ethernet Transmitter Jitter Generation**|||||
|Total transmitter jitter (T_TJ)|1250|–|0.24|UI|
|**Gigabit Ethernet Receiver High Frequency Jitter Tolerance**|||||
|Total receiver jitter tolerance|1250|0.749|–|UI|
_Table 59:_ **XAUI Protocol Characteristics (GTH Transceivers)**
|**Description**|**Line Rate (Mb/s)**|**Min**|**Max**|**Units**|
|---|---|---|---|---|
|**XAUI Transmitter Jitter Generation**|||||
|Total transmitter jitter (T_TJ)|3125|–|0.35|UI|
|**XAUI Receiver High Frequency Jitter Tolerance**|||||
|Total receiver jitter tolerance|3125|0.65|–|UI|
_Table 60:_ **PCI Express Protocol Characteristics (GTH Transceivers)[(1)]**
|**Standard**|**Description**|**Condition**|**Line Rate (Mb/s)**|**Min**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|**PCI Express Transmitter Jitter Generation**|||||||
|PCI Express Gen 1|Total transmitter jitter||2500|–|0.25|UI|
|PCI Express Gen 2|Total transmitter jitter||5000|–|0.25|UI|
|PCI Express Gen 3(2)|Total transmitter jitter uncorrelated||8000|–|31.25|ps|
||Deterministic transmitter jitter uncorrelated|||–|12|ps|
|**PCI Express Receiver High Frequency Jitter Tolerance**|||||||
|PCI Express Gen 1|Total receiver jitter tolerance||2500|0.65|–|UI|
|PCI Express Gen 2(2)|Receiver inherent timing error||5000|0.40|–|UI|
||Receiver inherent deterministic timing error|||0.30|–|UI|
|PCI Express Gen 3(2)|Receiver sinusoidal<br>jitter tolerance|0.03 MHz–1.0 MHz|8000|1.00|–|UI|
|||1.0 MHz–10 MHz||Note 3|–|UI|
|||10 MHz–100 MHz||0.10|–|UI|
## **Notes:**
1. Tested per card electromechanical (CEM) methodology.
2. Using common REFCLK.
3. Between 1 MHz and 10 MHz the minimum sinusoidal jitter roll-off with a slope of 20 dB/decade.
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_Table 61:_ **CEI-6G and CEI-11G Protocol Characteristics (GTH Transceivers)**
|**Description**|**Line Rate (Mb/s)**|**Interface**|**Min**|**Max**|**Units**|
|---|---|---|---|---|---|
|**CEI-6G Transmitter Jitter Generation**||||||
|Total transmitter jitter(1)|4976–6375|CEI-6G-SR|–|0.3|UI|
|||CEI-6G-LR|–|0.3|UI|
|**CEI-6G Receiver High Frequency Jitter Tolerance**||||||
|Total receiver jitter tolerance(1)|4976–6375|CEI-6G-SR|0.6|–|UI|
|||CEI-6G-LR|0.95|–|UI|
|**CEI-11G Transmitter Jitter Generation**||||||
|Total transmitter jitter(2)|9950–11100|CEI-11G-SR|–|0.3|UI|
|||CEI-11G-LR/MR|–|0.3|UI|
|**CEI-11G Receiver High Frequency Jitter Tolerance**||||||
|Total receiver jitter tolerance(2)|9950–11100|CEI-11G-SR|0.65|–|UI|
|||CEI-11G-MR|0.65|–|UI|
|||CEI-11G-LR|0.825|–|UI|
## **Notes:**
1. Tested at most commonly used line rate of 6250 Mb/s using 390.625 MHz reference clock.
2. Tested at line rate of 9950 Mb/s using 155.46875 MHz reference clock and 11100 Mb/s using 173.4375 MHz reference clock.
_Table 62:_ **SFP+ Protocol Characteristics (GTH Transceivers)**
|**Description**|**Line Rate (Mb/s)**|**Min**|**Max**|**Units**|
|---|---|---|---|---|
|**SFP+ Transmitter Jitter Generation**|||||
|Total transmitter jitter|9830.40(1)|–|0.28|UI|
||9953.00||||
||10312.50||||
||10518.75||||
||11100.00||||
|**SFP+ Receiver Frequency Jitter Tolerance**|||||
|Total receiver jitter tolerance|9830.40(1)|0.7|–|UI|
||9953.00||||
||10312.50||||
||10518.75||||
||11100.00||||
## **Notes:**
1. Line rated used for CPRI over SFP+ applications.
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_Table 63:_ **CPRI Protocol Characteristics (GTH Transceivers)**
|**Description**|**Line Rate (Mb/s)**|**Min**|**Max**|**Units**|
|---|---|---|---|---|
|**CPRI Transmitter Jitter Generation**|||||
|Total transmitter jitter|614.4|–|0.35|UI|
||1228.8|–|0.35|UI|
||2457.6|–|0.35|UI|
||3072.0|–|0.35|UI|
||4915.2|–|0.3|UI|
||6144.0|–|0.3|UI|
||9830.4|–|Note 1|UI|
|**CPRI Receiver Frequency Jitter Tolerance**|||||
|Total receiver jitter tolerance|614.4|0.65|–|UI|
||1228.8|0.65|–|UI|
||2457.6|0.65|–|UI|
||3072.0|0.65|–|UI|
||4915.2|0.95|–|UI|
||6144.0|0.95|–|UI|
||9830.4|Note 1|–|UI|
## **Notes:**
1. Tested per SFP+ specification, see Table 62.
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
## **GTY Transceiver Specifications (XCKU095 and XQKU095)**
## **GTY Transceiver DC Input and Output Levels (XCKU095 and XQKU095)**
Table 64 summarizes the DC specifications of the GTY transceivers in the XCKU095 and XQKU095 devices (only). Consult www.xilinx.com/products/technology/high-speed-serial for further details.
_Table 64:_ **GTY Transceiver DC Specifications**
|**Symbol**|**DC Parameter**|**Conditions**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|DVPPIN|Differential peak-to-peak input<br>voltage (external AC coupled)|>10.3125 Gb/s|150|–|1250|mV|
|||6.6 Gb/s to 10.3125 Gb/s|150|–|1250|mV|
|||≤6.6 Gb/s|150|–|2000|mV|
|VIN|Single-ended input voltage.<br>Voltage measured at the pin<br>referenced to GND.|DC coupled<br>VMGTAVTT = 1.2V|–400|–|VMGTAVTT|mV|
|VCMIN|Common mode input voltage|DC coupled<br>VMGTAVTT = 1.2V|–|2/3 VMGTAVTT|–|mV|
|DVPPOUT|Differential peak-to-peak output<br>voltage(1)|Transmitter output swing<br>is set to`0x1F`|800|–|–|mV|
|VCMOUTDC|Common mode output voltage:<br>DC coupled (equation based)|When remote RX is<br>terminated to GND|VMGTAVTT/2 – DVPPOUT/4|||mV|
|||When remote RX<br>termination is floating|VMGTAVTT– DVPPOUT/2|||mV|
|||When remote RX is<br>terminated to VRX_TERM(2)|VMGTAVTT<br>DVPPOUT<br>4<br>----------------------**-**<br>–<br>VMGTAVTT<br>VRX_TERM<br>–<br>2<br>--------------------------------------------------------<br><br><br><br><br>–|||mV|
|VCMOUTAC|Common mode output voltage:<br>AC coupled|Equation based|VMGTAVTT– DVPPOUT/2|||mV|
|RIN|Differential input resistance||–|100|–|Ω|
|ROUT|Differential output resistance||–|100|–|Ω|
|TOSKEW|Transmitter output pair (TXP and|TXN) intra-pair skew|–|–|5|ps|
|CEXT|Recommended external AC coupling capacitor(3)||–|100|–|nF|
## **Notes:**
1. The output swing and pre-emphasis levels are programmable using the GTY transceiver attributes and can result in values lower than reported in this table.
2. VRX_TERM is the remote RX termination voltage.
3. Other values can be used as appropriate to conform to specific protocols and standards.
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**==> picture [526 x 75] intentionally omitted <==**
**----- Start of picture text -----**<br>
+V P<br>Single-Ended<br>Peak-to-Peak<br>N Voltage<br>0<br>ds892_03_120414<br>**----- End of picture text -----**<br>
_Figure 6:_ **Single-Ended Peak-to-Peak Voltage**
**==> picture [508 x 113] intentionally omitted <==**
**----- Start of picture text -----**<br>
+V<br>Differential<br>0 Peak-to-Peak<br>Voltage<br>–V P–N<br>Differential peak-to-peak voltage = (Single-ended peak-to-peak voltage) x 2 ds892_04_120414<br>**----- End of picture text -----**<br>
_Figure 7:_ **Differential Peak-to-Peak Voltage**
Table 65 summarizes the DC specifications of the clock input of the GTY transceivers in the XCKU095 and XQKU095 devices (only). Consult www.xilinx.com/products/technology/high-speed-serial for further details.
_Table 65:_ **GTY Transceiver Clock DC Input Level Specification**
|**Symbol**|**DC Parameter**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|
|VIDIFF|Differential peak-to-peak input voltage|250|–|2000|mV|
|RIN|Differential input resistance|–|100|–|Ω|
|CEXT|Required external AC coupling capacitor|–|10|–|nF|
_Table 66:_ **GTY Transceiver Clock Output Level Specification**
|**Symbol**|**Description**|**Conditions**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|VOL|Output Low voltage for P and N|RT = 100Ωacross P and N signals|–|400|–|mV|
|VOH|Output High voltage for P and N|RT = 100Ωacross P and N signals|–|760|–|mV|
|VDDOUT|Differential output voltage<br>(P–N), P = High<br>(N–P), N = High|RT = 100Ωacross P and N signals|–|±360|–|mV|
|VCMOUT|Common mode voltage|RT = 100Ωacross P and N signals|–|580|–|mV|
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
## **GTY Transceiver Switching Characteristics for the XCKU095 and XQKU095**
Consult www.xilinx.com/products/technology/high-speed-serial for further information.
_Table 67:_ **GTY Transceiver Performance**
|**Symbol**|**Description**|**Output**<br>**Divider**|<br>**Speed Grades and Temperature Range**|<br>**Speed Grades and Temperature Range**|<br>**Speed Grades and Temperature Range**|<br>**Speed Grades and Temperature Range**|**Units**|
|---|---|---|---|---|---|---|---|
||||**-2E, -2I**||**-1C, -1I, -1M**|||
|FGTYMAX|GTY maximum line rate||16.375||12.5||Gb/s|
|FGTYMIN|GTY minimum line rate||0.5||0.5||Gb/s|
||||Min|Max|Min|Max||
|FGTYCRANGE|CPLL line rate range(1)|1|4.0|12.5|4.0|8.5|Gb/s|
|||2|2.0|6.25|2.0|4.25|Gb/s|
|||4|1.0|3.125|1.0|2.125|Gb/s|
|||8|0.5|1.5625|0.5|1.0625|Gb/s|
||||Min|Max|Min|Max||
|FGTYQRANGE1|QPLL0 line rate range|1(2)|9.8|16.375|9.8|12.5|Gb/s|
|||2(2)|4.9|8.1875|4.9|8.1875|Gb/s|
|||4(2)|2.45|4.09375|2.45|4.09375|Gb/s|
|||8(2)|1.225|2.04688|1.225|2.04688|Gb/s|
|||16(2)|0.6125|1.02344|0.6125|1.02344|Gb/s|
||||Min|Max|Min|Max||
|FGTYQRANGE2|QPLL1 line rate range|1(3)|8.0|13.0|8.0|12.5|Gb/s|
|||2(3)|4.0|6.5|4.0|6.5|Gb/s|
|||4(3)|2.0|3.25|2.0|3.25|Gb/s|
|||8(3)|1.0|1.625|1.0|1.625|Gb/s|
|||16(3)|0.5|0.8125|0.5|0.8125|Gb/s|
||||Min|Max|Min|Max||
|FCPLLRANGE|CPLL frequency range||2.0|6.25|2.0|4.25|GHz|
|FQPLL0RANGE|QPLL0 frequency range||9.8|16.375|9.8|16.375|GHz|
|FQPLL1RANGE|QPLL1 frequency range||8.0|13.0|8.0|13.0|GHz|
## **Notes:**
1. The values listed are the rounded results of the calculated equation (2 x CPLL_Frequency)/Output_Divider.
2. The values listed are rounded results from calculated equation (QPLL0_Frequency)/Output_Divider.
3. The values listed are rounded results from calculated equation (QPLL1_Frequency)/Output_Divider.
_Table 68:_ **GTY Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics**
|**Symbol**|**Description**|**XCKU095 and XQKU095**|**Units**|
|---|---|---|---|
|FGTYDRPCLK|GTYDRPCLK maximum frequency|250|MHz|
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_Table 69:_ **GTY Transceiver Reference Clock Switching Characteristics**
|**Symbol**|**Description**|**Conditions**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|FGCLK|Reference clock frequency range||60|–|820|MHz|
|TRCLK|Reference clock rise time|20% – 80%|–|200|–|ps|
|TFCLK|Reference clock fall time|80% – 20%|–|200|–|ps|
|TDCREF|Reference clock duty cycle|Transceiver PLL only|40|50|60|%|
**==> picture [328 x 86] intentionally omitted <==**
**----- Start of picture text -----**<br>
TRCLK<br>80%<br>20%<br>TFCLK<br>**----- End of picture text -----**<br>
**==> picture [43 x 5] intentionally omitted <==**
**----- Start of picture text -----**<br>
ds892_05_120414<br>**----- End of picture text -----**<br>
_Figure 8:_ **Reference Clock Timing Parameters**
_Table 70:_ **GTY Transceiver Reference Clock Oscillator Selection Phase Noise Mask[(1)]**
|**Symbol**|**Description**|**Offset**<br>**Frequency**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|QPLLREFCLKMASK|QPLL0/QPLL1 reference clock select<br>phase noise mask at<br>REFCLK frequency = 156.25 MHz.|10 kHz|–|–|–112|dBc/Hz|
|||100 kHz|–|–|–128||
|||1 MHz|–|–|–145||
||QPLL0/QPLL1 reference clock select<br>phase noise mask at<br>REFCLK frequency = 312.5 MHz.|10 kHz|–|–|–103|dBc/Hz|
|||100 kHz|–|–|–123||
|||1 MHz|–|–|–143||
||QPLL0/QPLL1 reference clock select<br>phase noise mask at<br>REFCLK frequency =625 MHz.|10 kHz|–|–|–98|dBc/Hz|
|||100 kHz|–|–|–117||
|||1 MHz|–|–|–140||
|CPLLREFCLKMASK|CPLL reference clock select phase noise<br>mask at REFCLK<br>frequency = 156.25 MHz.|10 kHz|–|–|–112|dBc/Hz|
|||100 kHz|–|–|–128||
|||1 MHz|–|–|–145||
|||50 MHz|–|–|–145||
||CPLL reference clock select phase noise<br>mask at REFCLK frequency = 312.5 MHz.|10 kHz|–|–|–103|dBc/Hz|
|||100 kHz|–|–|–123||
|||1 MHz|–|–|–143||
|||50 MHz|–|–|–145||
||CPLL reference clock select phase noise<br>mask at REFCLK frequency = 625 MHz.|10 kHz|–|–|–98|dBc/Hz|
|||100 kHz|–|–|–117||
|||1 MHz|–|–|–140||
|||50 MHz|–|–|–144||
## **Notes:**
1. For reference clock frequencies not in this table, use the phase-noise mask for the nearest reference clock frequency.
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_Table 71:_ **GTY Transceiver PLL/Lock Time Adaptation**
|**Symbol**|**Description**|**Conditions**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|TLOCK|Initial PLL lock||–|–|1|ms|
|TDLOCK|Clock recovery phase acquisition and<br>adaptation time for decision<br>feedback equalizer (DFE).|After the PLL is locked to<br>the reference clock, this is<br>the time it takes to lock<br>the clock data recovery<br>(CDR) to the data present<br>at the input.|–|50,000|37 x 106|UI|
||Clock recovery phase acquisition and<br>adaptation time for low-power mode<br>(LPM) when the DFE is disabled.||–|50,000|2.3 x 106|UI|
_Table 72:_ **GTY Transceiver User Clock Switching Characteristics[(1)]**
|**Symbol**|**Description**|**Data Width Conditions (Bit)**|**Data Width Conditions (Bit)**|**Speed Grades and**<br>**Temperature Ranges**|**Speed Grades and**<br>**Temperature Ranges**|**Units**|
|---|---|---|---|---|---|---|
|||**Internal**<br>**Logic**|**Interconnect Logic**|**-2E, -2I**|**-1C, -1I, -1M**||
|FTXOUTPMA|TXOUTCLK maximum|frequency sourced from OUTCLKPMA||511.719|390.625|MHz|
|FRXOUTPMA|RXOUTCLK maximum|frequency sourced from OUTCLKPMA||511.719|390.625|MHz|
|FTXOUTPROGDIV|TXOUTCLK maximum|frequency sourced from TXPROGDIVCLK||511.719|511.719|MHz|
|FRXOUTPROGDIV|RXOUTCLK maximum|frequency sourced from RXPROGDIVCLK||511.719|511.719|MHz|
|FTXIN|TXUSRCLK maximum<br>frequency|16|16, 32|511.719|390.625|MHz|
|||32|32, 64|511.719|390.625|MHz|
|||20|20, 40|409.375|312.500|MHz|
|||40|40, 80|409.375|312.500|MHz|
|FRXIN|RXUSRCLK maximum<br>frequency|16|16, 32|511.719|390.625|MHz|
|||<br>32|32, 64|511.719|390.625|MHz|
|||20|20, 40|409.375|312.500|MHz|
|||40|40, 80|409.375|312.500|MHz|
|FTXIN2|TXUSRCLK2<br>maximum frequency|16|16|511.719|390.625|MHz|
|||20|20|409.375|312.500|MHz|
|||16, 32|32|511.719|390.625|MHz|
|||20, 40|40|409.375|312.500|MHz|
|||32|64|255.860|195.313|MHz|
|||40|80|204.688|156.250|MHz|
|FRXIN2|RXUSRCLK2<br>maximum frequency|16|16|511.719|390.625|MHz|
|||20|20|409.375|312.500|MHz|
|||16, 32|32|511.719|390.625|MHz|
|||20, 40|40|409.375|312.500|MHz|
|||32|64|255.860|195.313|MHz|
|||40|80|204.688|156.250|MHz|
## **Notes:**
1. Clocking must be implemented as described in the _UltraScale Architecture GTY Transceiver User Guide_ (UG578).
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_Table 73:_ **GTY Transceiver Transmitter Switching Characteristics**
|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|FGTYTX|Serial data rate range||0.500|–|FGTYMAX|Gb/s|
|TRTX|TX rise time|20%–80%|–|40|–|ps|
|TFTX|TX fall time|80%–20%|–|40|–|ps|
|TLLSKEW|TX lane-to-lane skew(1)||–|–|500|ps|
|VTXOOBVDPP|Electrical idle amplitude||–|–|15|mV|
|TTXOOBTRANSITION|Electrical idle transition time||–|–|140|ns|
|TJ16.375_QPLL|Total jitter(2)(4)|16.375 Gb/s|–|–|0.28|UI|
|DJ16.375_QPLL|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ15.0_QPLL|Total jitter(2)(4)|15.0 Gb/s|–|–|0.28|UI|
|DJ15.0_QPLL|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ14.1_QPLL|Total jitter(2)(4)|14.1 Gb/s|–|–|0.28|UI|
|DJ14.1_QPLL|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ14.025_QPLL|Total jitter(2)(4)|14.025 Gb/s|–|–|0.28|UI|
|DJ14.025_QPLL|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ13.1_QPLL|Total jitter(2)(4)|13.1 Gb/s|–|–|0.28|UI|
|DJ13.1_QPLL|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ12.5_QPLL|Total jitter(2)(4)|12.5 Gb/s|–|–|0.28|UI|
|DJ12.5_QPLL|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ12.5_CPLL|Total jitter(2)(4)|12.5 Gb/s|–|–|0.33|UI|
|DJ12.5_CPLL|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ11.3_QPLL|Total jitter(2)(4)|11.3 Gb/s|–|–|0.28|UI|
|DJ11.3_QPLL|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ10.3125_QPLL|Total jitter(2)(4)|10.3125 Gb/s|–|–|0.28|UI|
|DJ10.3125_QPLL|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ10.3125_CPLL|Total jitter(3)(4)|10.3125 Gb/s|–|–|0.33|UI|
|DJ10.3125_CPLL|Deterministic jitter(3)(4)||–|–|0.17|UI|
|TJ9.953_QPLL|Total jitter(2)(4)|9.953 Gb/s|–|–|0.28|UI|
|DJ9.953_QPLL|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ9.8_QPLL|Total jitter(2)(4)|9.8 Gb/s|–|–|0.28|UI|
|DJ9.8_QPLL|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ8.0_QPLL|Total jitter(2)(4)|8.0 Gb/s|–|–|0.28|UI|
|DJ8.0_QPLL|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ8.0_CPLL|Total jitter(3)(4)|8.0 Gb/s|–|–|0.32|UI|
|DJ8.0_CPLL|Deterministic jitter(3)(4)||–|–|0.17|UI|
|TJ6.6_CPLL|Total jitter(3)(4)|6.6 Gb/s|–|–|0.30|UI|
|DJ6.6_CPLL|Deterministic jitter(3)(4)||–|–|0.15|UI|
|TJ5.0|Total jitter(3)(4)|5.0 Gb/s|–|–|0.30|UI|
|DJ5.0|Deterministic jitter(3)(4)||–|–|0.15|UI|
|TJ4.25|Total jitter(3)(4)|4.25 Gb/s|–|–|0.30|UI|
|DJ4.25|Deterministic jitter(3)(4)||–|–|0.15|UI|
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_Table 73:_ **GTY Transceiver Transmitter Switching Characteristics** _**(Cont’d)**_
|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|TJ4.00L|Total jitter(3)(4)|4.00 Gb/s|–|–|0.32|UI|
|DJ4.00L|Deterministic jitter(3)(4)||–|–|0.16|UI|
|TJ3.75|Total jitter(3)(4)|3.75 Gb/s|–|–|0.20|UI|
|DJ3.75|Deterministic jitter(3)(4)||–|–|0.10|UI|
|TJ3.20|Total jitter(3)(4)|3.20 Gb/s(5)|–|–|0.20|UI|
|DJ3.20|Deterministic jitter(3)(4)||–|–|0.10|UI|
|TJ2.5|Total jitter(3)(4)|2.5 Gb/s(6)|–|–|0.20|UI|
|DJ2.5|Deterministic jitter(3)(4)||–|–|0.10|UI|
|TJ1.25|Total jitter(3)(4)|1.25 Gb/s(7)|–|–|0.15|UI|
|DJ1.25|Deterministic jitter(3)(4)||–|–|0.05|UI|
|TJ500|Total jitter(3)(4)|500 Mb/s|–|–|0.10|UI|
|DJ500|Deterministic jitter(3)(4)||–|–|0.05|UI|
## **Notes:**
1. Using same REFCLK input with TX phase alignment enabled for up to four fully-populated GTY Quads at maximum line rate.
2. Using QPLL_FBDIV = 40, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations.
3. Using CPLL_FBDIV = 2, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations.
4. All jitter values are based on a bit-error ratio of 10[-12] .
5. CPLL frequency at 3.2 GHz and TXOUT_DIV = 2.
6. CPLL frequency at 2.5 GHz and TXOUT_DIV = 2.
7. CPLL frequency at 2.5 GHz and TXOUT_DIV = 4.
_Table 74:_ **GTY Transceiver Receiver Switching Characteristics**
|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|FGTYRX|Serial data rate||0.500|–|FGTYMAX|Gb/s|
|TRXELECIDLE|Time for RXELECIDLE to respond to loss or restoration of<br>data||–|10|–|ns|
|RXOOBVDPP|OOB detect threshold peak-to-peak||60|–|150|mV|
|RXSST|Receiver spread-spectrum tracking(1)|Modulated at 33 kHz|–5000|–|0|ppm|
|RXRL|Run length (CID)||–|–|256|UI|
|RXPPMTOL|Data/REFCLK PPM offset tolerance|Bit rates ≤6.6 Gb/s|–1250|–|1250|ppm|
|||Bit rates > 6.6 Gb/s<br>and≤8.0 Gb/s|–700|–|700|ppm|
|||Bit rates > 8.0 Gb/s|–200|–|200|ppm|
|**SJ Jitter Tolerance(2)**|||||||
|JT_SJ16.375|Sinusoidal jitter (CPLL)(3)|16.375 Gb/s|–|–|0.30|UI|
|JT_SJ15.0|Sinusoidal jitter (CPLL)(3)|15.0 Gb/s|–|–|0.30|UI|
|JT_SJ14.1|Sinusoidal jitter (CPLL)(3)|14.1 Gb/s|–|–|0.30|UI|
|JT_SJ13.1|Sinusoidal jitter (CPLL)(3)|13.1 Gb/s|–|–|0.30|UI|
|JT_SJ12.5_QPLL|Sinusoidal jitter (CPLL)(3)|12.5 Gb/s|–|–|0.30|UI|
|JT_SJ12.5_CPLL|Sinusoidal jitter (CPLL)(3)|12.5 Gb/s|–|–|0.30|UI|
|JT_SJ11.3|Sinusoidal jitter (CPLL)(3)|11.3 Gb/s|–|–|0.30|UI|
|JT_SJ10.32_QPLL|Sinusoidal jitter (CPLL)(3)|10.32 Gb/s|–|–|0.30|UI|
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_Table 74:_ **GTY Transceiver Receiver Switching Characteristics** _**(Cont’d)**_
|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|JT_SJ10.32_CPLL|Sinusoidal jitter (CPLL)(3)|10.32 Gb/s|–|–|0.30|UI|
|JT_SJ9.8|Sinusoidal jitter (CPLL)(3)|9.8 Gb/s|–|–|0.30|UI|
|JT_SJ8.0_QPLL|Sinusoidal jitter (CPLL)(3)|8.0 Gb/s|–|–|0.44|UI|
|JT_SJ8.0_CPLL|Sinusoidal jitter (CPLL)(3)|8.0 Gb/s|–|–|0.42|UI|
|JT_SJ6.6_CPLL|Sinusoidal jitter (CPLL)(3)|6.6 Gb/s|–|–|0.44|UI|
|JT_SJ5.0|Sinusoidal jitter (CPLL)(3)|5.0 Gb/s|–|–|0.44|UI|
|JT_SJ4.25|Sinusoidal jitter (CPLL)(3)|4.25 Gb/s|–|–|0.44|UI|
|JT_SJ4.00L|Sinusoidal jitter (CPLL)(3)|4.0 Gb/s|–|–|0.45|UI|
|JT_SJ3.75|Sinusoidal jitter (CPLL)(3)|3.75 Gb/s|–|–|0.45|UI|
|JT_SJ3.20|Sinusoidal jitter (CPLL)(3)|3.2 Gb/s(4)|–|–|0.45|UI|
|JT_SJ2.5|Sinusoidal jitter (CPLL)(3)|2.5 Gb/s(5)|–|–|0.50|UI|
|JT_SJ1.25|Sinusoidal jitter (CPLL)(3)|1.25 Gb/s(6)|–|–|0.50|UI|
|JT_SJ500|Sinusoidal jitter (CPLL)(3)|500 Mb/s|–|–|0.50|UI|
|**SJ Jitter Tolerance with Stressed Eye(2)**|||||||
|JT_TJSE3.2|Total jitter with stressed eye(7)|3.2 Gb/s|–|–|0.7|UI|
|JT_TJSE6.6||6.6 Gb/s|–|–|0.7|UI|
|JT_SJSE3.2|Sinusoidal jitter with stressed eye(7)|3.2 Gb/s||–|0.7|UI|
|JT_SJSE6.6||6.6 Gb/s||–|0.7|UI|
## **Notes:**
1. Using RXOUT_DIV = 1, 2, and 4.
2. All jitter values are based on a bit error ratio of 10[–12] .
3. The frequency of the injected sinusoidal jitter is 80 MHz.
4. CPLL frequency at 3.2 GHz and RXOUT_DIV = 2.
5. CPLL frequency at 2.5 GHz and RXOUT_DIV = 2.
6. CPLL frequency at 2.5 GHz and RXOUT_DIV = 4.
7. Composite jitter with RX equalizer enabled. DFE disabled.
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
## **GTY Transceiver Electrical Compliance for the XCKU095 and XQKU095**
The _UltraScale Architecture GTY Transceiver User Guide_ (UG578) contains recommended use modes that ensure compliance for the protocols listed in Table 75. The transceiver wizard provides the recommended settings for those use cases and for protocol specific characteristics.
_Table 75:_ **GTY Transceiver Protocol List**
|**Protocol**|**Specification**|**Serial Rate**<br>**(Gb/s)**|**Electrical**<br>**Compliance**|
|---|---|---|---|
|Interlaken|OIF-CEI-6G, OIF-CEI-11GSR|4.25–12.5|Compliant|
|CAUI-10|IEEE 802.3-2012|10.3125|Compliant|
|nPPI|IEEE 802.3-2012|10.3125|Compliant|
|10GBASE-KR|IEEE 802.3-2012|10.3125|Compliant|
|SFP+|SFF-8431 (SR and LR)|9.95328–11.10|Compliant|
|XFP|INF-8077i, Revision 4.5|10.3125|Compliant|
|RXAUI|CEI-6G-SR|6.25|Compliant|
|XAUI|IEEE 802.3-2012|3.125|Compliant|
|1000BASE-X|IEEE 802.3-2012|1.25|Compliant|
|OTU2|ITU G.8251|10.709225|Compliant|
|OTU4 (OTL4.10)|OIF-CEI-11G-SR|11.180997|Compliant|
|OC-3/12/48/192|GR-253-CORE|0.1555–9.956|Compliant|
|PCIe Gen1, 2, 3|PCI Express Base 3.0|2.5, 5.0, and 8.0|Compliant|
|SDI|SMPTE 424M-2006|0.27–2.97|Compliant|
|Hybrid Memory Cube (HMC)|HMC-15G-SR|12.5 and 15.0|Compliant|
|CPRI|CPRI_v_6_1_2014-07-01|0.6144–12.165|Compliant|
|Passive Optical Network (PON)|10G-EPON, 1G-EPON, NG-PON2, XG-PON, and<br>2.5G-PON|0.155–10.3125|Compliant|
|JESD204a/b|OIF-CEI-6G, OIF-CEI-11G|3.125–12.5|Compliant|
|Serial RapidIO|RapidIO Specification 3.1|1.25–10.3125|Compliant|
|DisplayPort (Source Only)|DP 1.2B CTS|1.62–5.4|Compliant|
|Fibre Channel|FC-PI-4|1.0625–14.025|Compliant|
|SATA Gen1, 2, 3|Serial ATA Revision 3.0 Specification|1.5, 3.0, and 6.0|Compliant|
|SAS Gen1, 2, 3|T10/BSR INCITS 519|3.0, 6.0, and 12.0|Compliant|
|SFI-5|OIF-SFI5-01.0|0.625 - 12.5|Compliant|
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## **GTY Transceiver Protocol Jitter Characteristics (XCKU095 and XQKU095)**
For Table 76 through Table 80, the _UltraScale Architecture GTY Transceiver User Guide_ (UG578) contains recommended settings for optimal usage of protocol specific characteristics.
_Table 76:_ **Gigabit Ethernet Protocol Characteristics (GTY Transceivers)**
|**Description**|**Line Rate (Mb/s)**|**Min**|**Max**|**Units**|
|---|---|---|---|---|
|**Gigabit Ethernet Transmitter Jitter Generation**|||||
|Total transmitter jitter (T_TJ)|1250|–|0.24|UI|
|**Gigabit Ethernet Receiver High Frequency Jitter Tolerance**|||||
|Total receiver jitter tolerance|1250|0.749|–|UI|
_Table 77:_ **XAUI Protocol Characteristics (GTY Transceivers)**
|**Description**|**Line Rate (Mb/s)**|**Min**|**Max**|**Units**|
|---|---|---|---|---|
|**XAUI Transmitter Jitter Generation**|||||
|Total transmitter jitter (T_TJ)|3125|–|0.35|UI|
|**XAUI Receiver High Frequency Jitter Tolerance**|||||
|Total receiver jitter tolerance|3125|0.65|–|UI|
_Table 78:_ **CEI-6G and CEI-11G Protocol Characteristics (GTY Transceivers)**
|**Description**|**Line Rate (Mb/s)**|**Interface**|**Min**|**Max**|**Units**|
|---|---|---|---|---|---|
|**CEI-6G Transmitter Jitter Generation**||||||
|Total transmitter jitter(1)|4976–6375|CEI-6G-SR|–|0.3|UI|
|||CEI-6G-LR|–|0.3|UI|
|**CEI-6G Receiver High Frequency Jitter Tolerance**||||||
|Total receiver jitter tolerance(1)|4976–6375|CEI-6G-SR|0.6|–|UI|
|||CEI-6G-LR|0.95|–|UI|
|**CEI-11G Transmitter Jitter Generation**||||||
|Total transmitter jitter(2)|9950–11100|CEI-11G-SR|–|0.3|UI|
|||CEI-11G-LR/MR|–|0.3|UI|
|**CEI-11G Receiver High Frequency Jitter Tolerance**||||||
|Total receiver jitter tolerance(2)|9950–11100|CEI-11G-SR|0.65|–|UI|
|||CEI-11G-MR|0.65|–|UI|
|||CEI-11G-LR|0.825|–|UI|
## **Notes:**
1. Tested at most commonly used line rate of 6250 Mb/s using 390.625 MHz reference clock.
2. Tested at line rate of 9950 Mb/s using 155.46875 MHz reference clock and 11100 Mb/s using 173.4375 MHz reference clock.
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 79:_ **SFP+ Protocol Characteristics (GTY Transceivers)**
|**Description**|**Line Rate (Mb/s)**|**Min**|**Max**|**Units**|
|---|---|---|---|---|
|**SFP+ Transmitter Jitter Generation**|||||
|Total transmitter jitter|9830.40(1)|–|0.28|UI|
||9953.00||||
||10312.50||||
||10518.75||||
||11100.00||||
|**SFP+ Receiver Frequency Jitter Tolerance**|||||
|Total receiver jitter tolerance|9830.40(1)|0.7|–|UI|
||9953.00||||
||10312.50||||
||10518.75||||
||11100.00||||
## **Notes:**
1. Line rated used for CPRI over SFP+ applications.
_Table 80:_ **CPRI Protocol Characteristics (GTY Transceivers)**
|**Description**|**Line Rate (Mb/s)**|**Min**|**Max**|**Units**|
|---|---|---|---|---|
|**CPRI Transmitter Jitter Generation**|||||
|Total transmitter jitter|614.4|–|0.35|UI|
||1228.8|–|0.35|UI|
||2457.6|–|0.35|UI|
||3072.0|–|0.35|UI|
||4915.2|–|0.3|UI|
||6144.0|–|0.3|UI|
||9830.4|–|Note 1|UI|
|**CPRI Receiver Frequency Jitter Tolerance**|||||
|Total receiver jitter tolerance|614.4|0.65|–|UI|
||1228.8|0.65|–|UI|
||2457.6|0.65|–|UI|
||3072.0|0.65|–|UI|
||4915.2|0.95|–|UI|
||6144.0|0.95|–|UI|
||9830.4|Note 1|–|UI|
## **Notes:**
1. Tested per SFP+ specification, see Table 79.
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
## **Integrated Interface Block for Interlaken for the XCKU095 and XQKU095**
More information and documentation on solutions using the integrated interface block for Interlaken can be found at UltraScale Interlaken.
_Table 81:_ **Maximum Performance for Interlaken Designs**
|**Symbol**|**Description**|**Speed Grades and**<br>**VCCINT Operating Voltage**|**Speed Grades and**<br>**VCCINT Operating Voltage**|**Speed Grades and**<br>**VCCINT Operating Voltage**|**Speed Grades and**<br>**VCCINT Operating Voltage**|**Units**|
|---|---|---|---|---|---|---|
|||**0.95V**|||||
|||**-2**||**-1**|||
|FRX_SERDES_CLK|Receive serializer/ deserializer clock|195.32||195.32||MHz|
|FTX_SERDES_CLK|Transmit serializer/ deserializer clock|195.32||195.32||MHz|
|FDRP_CLK|Dynamic reconfiguration port clock|250.00||250.00||MHz|
|||Min|Max|Min|Max||
|FCORE_CLK|Interlaken core clock|300.00|322.27|300.00|322.27|MHz|
|FLBUS_CLK|Interlaken local bus clock|300.00|322.27|300.00|322.27|MHz|
## **Integrated Interface Block for 100G Ethernet MAC and PCS for the XCKU095 and XQKU095**
More information and documentation on solutions using the integrated 100 Gb/s Ethernet block can be found at UltraScale Integrated 100G Ethernet MAC/PCS.
_Table 82:_ **Maximum Performance for 100G Ethernet Designs**
|**Symbol**|**Description**|**Speed Grades and**<br>**VCCINT Operating Voltage**|**Speed Grades and**<br>**VCCINT Operating Voltage**|**Units**|
|---|---|---|---|---|
|||**0.95V**|||
|||**-2**|**-1**||
|FTX_CLK|Transmit clock|322.27|322.27|MHz|
|FRX_CLK|Receive clock|322.27|322.27|MHz|
|FRX_SERDES_CLK|Receive serializer/deserializer clock|322.27|322.27|MHz|
|FDRP_CLK|Dynamic reconfiguration port clock|250.00|250.00|MHz|
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
## **Integrated Interface Block for PCI Express Designs**
More information and documentation on solutions for PCI Express designs can be found at PCI Express.
_Table 83:_ **Maximum Performance for PCI Express Designs**
|**Symbol**|**Description**|**Speed Grades and VCCINT Operating Voltages**|**Speed Grades and VCCINT Operating Voltages**|**Speed Grades and VCCINT Operating Voltages**|**Speed Grades and VCCINT Operating Voltages**|**Speed Grades and VCCINT Operating Voltages**|**Units**|
|---|---|---|---|---|---|---|---|
|||**1.0V**|**0.95V**|||**0.90V**||
|||**-3**|**-2**|**-1**|**-1L**|**-1L**||
|FPIPECLK|Pipe clock maximum frequency|250.00|250.00|250.00|250.00|250.00|MHz|
|FCORECLK|Core clock maximum frequency|500.00|500.00|500.00(1)|250.00|250.00|MHz|
|FUSERCLK|User clock maximum frequency|250.00|250.00|250.00|250.00|250.00|MHz|
|FDRPCLK|DRP clock maximum frequency|250.00|250.00|250.00|250.00|250.00|MHz|
## **Notes:**
1. PCI Express x8 Gen 3 operation is supported in -2 and -3 speed grades. Refer to the _UltraScale Architecture Gen3 Integrated Block for PCI Express v4.0 User Guide_ (PG156) for information regarding x8 Gen 3 operation in the -1 speed grade.
## **System Monitor Specifications**
_Table 84:_ **SYSMON Specifications**
|**Parameter**|**Symbol**|**Comments/Conditions**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|VCCADC = 1.8V ±3%, VREFP = 1.25V, VREFN = 0V, ADCCLK = 5.2 MHz, Tj = –40°C to 100°C, typical values at Tj = 40°C|||||||
|**ADC Accuracy(1)**|||||||
|Resolution|||10|–|–|Bits|
|Integral nonlinearity(2)|INL||–|–|±2|LSBs|
|Differential nonlinearity|DNL|No missing codes, guaranteed<br>monotonic|–|–|±1|LSBs|
|Offset error||Offset calibration enabled|–|–|±2|LSBs|
|Gain error|||–|–|±0.4|%|
|Sample rate|||–|–|0.2|MS/s|
|RMS code noise||External 1.25V reference|–|–|1|LSBs|
|||On-chip reference|–|1|–|LSBs|
|**ADC Accuracy at Extended Temperatures**|||||||
|Resolution||Tj = –55°C to 125°C|10|–|–|Bits|
|Integral nonlinearity|INL|Tj = –55°C to 125°C|–|–|±2|LSBs|
|Differential nonlinearity|DNL|No missing codes, guaranteed<br>monotonic<br>Tj = –55°C to 125°C|–|–|±1||
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_Table 84:_ **SYSMON Specifications** _**(Cont’d)**_
|**Parameter**|**Symbol**|**Comments/Conditions**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|**Analog Inputs(2)**|||||||
|ADC input ranges||Unipolar operation|0|–|1|V|
|||Bipolar operation|–0.5|–|+0.5|V|
|||Unipolar common mode range (FS input)|0|–|+0.5|V|
|||Bipolar common mode range (FS input)|+0.5|–|+0.6|V|
|Maximum external channel input<br>ranges||Adjacent channels set within these<br>ranges should not corrupt<br>measurements on adjacent channels|–0.1|–|VCCADC|V|
|**On-Chip Sensor Accuracy**|||||||
|Temperature sensor error(1)||Tj = –40°C to 100°C (with external REF)|–|–|±4|°C|
|||Tj = –55°C to 125°C (with external REF)|–|–|±4.5|°C|
|||Tj = –40°C to 100°C (with internal REF)|–|–|±5|°C|
|||Tj = –55°C to 125°C (with internal REF)|–|–|±6.5|°C|
|Supply sensor error(3)||Tj = –40°C to 100°C (with external REF)|–|–|±1|%|
|||Tj = –55°C to 125°C (with external REF)|–|–|±2|%|
|||Tj = –40°C to 100°C (with internal REF)|–|–|±1.5|%|
|||Tj = –55°C to 125°C (with internal REF)|–|–|±2.5|%|
|**Conversion Rate(4)**|||||||
|Conversion time—continuous|tCONV|Number of ADCCLK cycles|26|–|32|Cycles|
|Conversion time—event|tCONV|Number of ADCCLK cycles|–|–|21|Cycles|
|DRP clock frequency|DCLK|DRP clock frequency|8|–|250|MHz|
|ADC clock frequency|ADCCLK|Derived from DCLK|1|–|5.2|MHz|
|DCLK duty cycle|||40|–|60|%|
|**SYSMON Reference(5)**|||||||
|External reference|VREFP|Externally supplied reference voltage|1.20|1.25|1.30|V|
|On-chip reference||Ground VREFPpin to AGND,<br>-2 and -3 speed grade<br>Tj = –40°C to 100°C|1.2375|1.25|1.2625|V|
|||Ground VREFPpin to AGND,<br>-1 and -1L speed grade<br>Tj = –40°C to 100°C|1.23125|1.25|1.26875|V|
|||Ground VREFPpin to AGND,<br>Tj = –55°C to 125°C|1.225|1.25|1.275|V|
## **Notes:**
1. ADC offset errors are removed by enabling the ADC automatic offset calibration feature. The values are specified for when this feature is enabled.
2. See the _Analog Input_ section in the _UltraScale Architecture System Monitor User Guide_ (UG580).
3. Supply sensor offset and gain errors are removed by enabling the automatic offset and gain calibration feature. The values are specified for when this feature is enabled.
4. See the _Adjusting the Acquisition Settling Time_ section in the _UltraScale Architecture System Monitor User Guide_ (UG580).
5. Any variation in the reference voltage from the nominal VREFP = 1.25V and VREFN = 0V will result in a deviation from the ideal transfer function. This also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). However, for external ratiometric type applications allowing reference to vary by ±4% is permitted.
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
## **I2C Interfaces**
_Table 85:_ **I2C Fast Mode Interface Switching Characteristics[(1)]**
|**Symbol**|**Description**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|
|TDCFCLK|SCL duty cycle|–|50|–|%|
|TFCKO|SDAO clock-to-out delay|–|–|900|ns|
|TFDCK|SDAI setup time|100|–|–|ns|
|FFCLK|SCL clock frequency|–|–|400|kHz|
## **Notes:**
1. Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads.
**==> picture [206 x 73] intentionally omitted <==**
**----- Start of picture text -----**<br>
SCL<br>TFDCK<br>SDAI<br>TFCKO<br>SDAO<br>**----- End of picture text -----**<br>
**==> picture [44 x 5] intentionally omitted <==**
**----- Start of picture text -----**<br>
DS892_06_120414<br>**----- End of picture text -----**<br>
_Figure 9:_ **I2C Fast Mode Interface Timing Diagram**
_Table 86:_ **I2C Standard Mode Interface Switching Characteristics[(1)]**
|**Symbol**|**Description**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|
|TDCSCLK|SCL duty cycle|–|50|–|%|
|TSCKO|SDAO clock-to-out delay|–|–|3450|ns|
|TSDCK|SDAI setup time|250|–|–|ns|
|FSCLK|SCL clock frequency|–|–|100|kHz|
## **Notes:**
1. Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads.
**==> picture [206 x 73] intentionally omitted <==**
**----- Start of picture text -----**<br>
SCL<br>TSDCK<br>SDAI<br>TSCKO<br>SDAO<br>**----- End of picture text -----**<br>
**==> picture [44 x 5] intentionally omitted <==**
**----- Start of picture text -----**<br>
DS892_07_120414<br>**----- End of picture text -----**<br>
_Figure 10:_ **I2C Standard Mode Interface Timing Diagram**
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## **Configuration Switching Characteristics**
_Table 87:_ **Configuration Switching Characteristics**
|**Symbol**|**Description**|**Description**|**Speed Grades and**<br>**VCCINT Operating Voltages**|**Speed Grades and**<br>**VCCINT Operating Voltages**|**Speed Grades and**<br>**VCCINT Operating Voltages**|**Speed Grades and**<br>**VCCINT Operating Voltages**|**Speed Grades and**<br>**VCCINT Operating Voltages**|**Units**|
|---|---|---|---|---|---|---|---|---|
||||**1.0V**|**0.95V**|||**0.90V**||
||||**-3**|**-2**|**-1**|**-1L**|**-1L**||
|**Power-up Timing Characteristics**|||||||||
|TPL|Program latency||7.5|7.5|7.5|7.5|7.5|ms, Max|
|TPOR|Power-on reset<br>(40 ms ramp rate time)||57|57|57|57|57|ms, Max|
||||0|0|0|0|0|ms, Min|
||Power-on reset with POR override<br>(2 ms ramp rate time)||15|15|15|15|15|ms, Max|
||||5|5|5|5|5|ms, Min|
|TPROGRAM|Program pulse width||250|250|250|250|250|ns, Min|
|**CCLK Output (Master Mode)**|||||||||
|TICCK|Master CCLK output delay from INIT_B||150|150|150|150|150|ns, Min|
|TMCCKL(1)|Master CCLK clock Low time duty cycle||40/60|40/60|40/60|40/60|40/60|%, Min/Max|
|TMCCKH|Master CCLK clock High time duty cycle||40/60|40/60|40/60|40/60|40/60|%, Min/Max|
|FMCCK|Master CCLK frequency|SPI x2/x4/x8<br>BPI x8/x16|150|150|150|150|150|MHz, Max|
|||SPI x1 and serial<br>SLR-based devices|125|125|125|125|125|MHz, Max|
|||SPI x1 and serial<br>all other devices|150|150|150|150|150|MHz, Max|
|||SelectMAP|125|125|125|125|125|MHz, Max|
|FMCCK_START|Master CCLK frequency at start of<br>configuration||3|3|3|3|3|MHz, Typ|
|FMCCKTOL|Frequency tolerance, master mode with<br>respect to nominal CCLK||±35|±35|±35|±35|±35|%, Max|
|**CCLK Input (Slave Modes)**|||||||||
|TSCCKL|Slave CCLK clock minimum Low time||2.5|2.5|2.5|2.5|2.5|ns, Min|
|TSCCKH|Slave CCLK clock minimum High time||2.5|2.5|2.5|2.5|2.5|ns, Min|
|FSCCK|Slave CCLK frequency|Serial SLR-based|125|125|125|125|125|MHz, Max|
|||Serial<br>All other devices|150|150|150|150|150|MHz, Max|
|||SelectMAP|125|125|125|125|125|MHz, Max|
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_Table 87:_ **Configuration Switching Characteristics** _**(Cont’d)**_
|**Symbol**|**Description**|**Description**|**Speed Grades and**<br>**VCCINT Operating Voltages**|**Speed Grades and**<br>**VCCINT Operating Voltages**|**Speed Grades and**<br>**VCCINT Operating Voltages**|**Speed Grades and**<br>**VCCINT Operating Voltages**|**Speed Grades and**<br>**VCCINT Operating Voltages**|**Units**|
|---|---|---|---|---|---|---|---|---|
||||**1.0V**|**0.95V**|||**0.90V**||
||||**-3**|**-2**|**-1**|**-1L**|**-1L**||
|**EMCCLK Input (Master Mode)**|||||||||
|TEMCCKL|External master CCLK Low time||2.5|2.5|2.5|2.5|2.5|ns, Min|
|TEMCCKH|External master CCLK High time||2.5|2.5|2.5|2.5|2.5|ns, Min|
|FEMCCK|External master CCLK<br>frequency|SPI x2/x4/x8<br>BPI x8/x16|150|150|150|150|150|MHz, Max|
|||SPI x1, Serial<br>SLR-based|125|125|125|125|125|MHz, Max|
|||SPI x1, Serial<br>All other devices|150|150|150|150|150|MHz, Max|
|||SelectMAP|125|125|125|125|125|MHz, Max|
|**Internal Configuration Access Port**|||||||||
|FICAPCK|Internal configuration<br>access port (ICAPE3)|Master SLR ICAP<br>accessing the<br>entire device|125|125|125|125|125|MHz, Max|
|||SLR ICAP<br>accessing the<br>local SLR|200|200|200|200|200|MHz, Max|
|||All other devices|200|200|200|200|200|MHz, Max|
|**Master/Slave Serial Mode Programming Switching**|||||||||
|TDCCK/TCCKD|DINsetup/hold||3.0/0|3.0/0|3.0/0|3.0/0|3.0/0|ns, Min|
|TCCO|DOUTclock to out||8|8|8|8|8|ns, Max|
|**SelectMAP Mode Programming Switching**|||||||||
|TSMDCCK/TSMCCKD|D[31:00] setup/hold||3.5/0|3.5/0|3.5/0|3.5/0|3.5/0|ns, Min|
|TSMCSCCK/TSMCCKCS|CSI_B setup/hold||4.0/0|4.0/0|4.0/0|4.0/0|4.0/0|ns, Min|
|TSMWCCK/TSMCCKW|RDWR_B setup/hold||10.0/0|10.0/0|10.0/0|10.0/0|10.0/0|ns, Min|
|TSMCKCSO|CSO_B clock to out<br>(330Ωpull-up resistor required)||7|7|7|7|7|ns, Max|
|TSMCO|D[31:00] clock to out in readback||8|8|8|8|8|ns, Max|
|FRBCCK|Readback frequency|SLR-based|125|125|125|125|125|MHz, Max|
|||All other devices|125|125|125|125|125|MHz, Max|
|**Boundary-Scan Port Timing Specifications**|||||||||
|TTAPTCK/TTCKTAP|TMS and TDI setup/hold|SLR-based|7.0/<br>2.0|7.0/<br>2.0|7.0/<br>2.0|7.0/<br>2.0|7.0/<br>2.0|ns, Min|
|||All other devices|3.0/<br>2.0|3.0/<br>2.0|3.0/<br>2.0|3.0/<br>2.0|3.0/<br>2.0|ns, Min|
|TTCKTDO|TCK falling edge to TDO<br>output|SLR-based|10|10|10|10|10|ns, Max|
|||All other devices|7|7|7|7|7|ns, Max|
|FTCK|TCK frequency|SLR-based|20|20|20|20|20|MHz, Max|
|||XCKU095|50|50|50|50|50|MHz, Max|
|||All other devices|66|66|66|66|66|MHz, Max|
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_Table 87:_ **Configuration Switching Characteristics** _**(Cont’d)**_
|**Symbol**|**Description**|**Speed Grades and**<br>**VCCINT Operating Voltages**|**Speed Grades and**<br>**VCCINT Operating Voltages**|**Speed Grades and**<br>**VCCINT Operating Voltages**|**Speed Grades and**<br>**VCCINT Operating Voltages**|**Speed Grades and**<br>**VCCINT Operating Voltages**|**Units**|
|---|---|---|---|---|---|---|---|
|||**1.0V**|**0.95V**|||**0.90V**||
|||**-3**|**-2**|**-1**|**-1L**|**-1L**||
|**BPI Master Flash Mode Programming Switching**||||||||
|TBPICCO|A[28:00], RS[1:0], FCS_B, FOE_B, FWE_B,<br>ADV_B clock to out|10|10|10|10|10|ns, Max|
|TBPIDCC/TBPICCD|D[15:00] setup/hold|3.5/0|3.5/0|3.5/0|3.5/0|3.5/0|ns, Min|
|**SPI Master Flash Mode Programming Switching**||||||||
|TSPIDCC/TSPICCD|D[03:00] setup/hold|3.0/0|3.0/0|3.0/0|3.0/0|3.0/0|ns, Min|
|TSPIDCC/TSPICCD|D[07:04] setup/hold|3.5/0|3.5/0|3.5/0|3.5/0|3.5/0|ns, Min|
|TSPICCM|MOSI clock to out|8.0|8.0|8.0|8.0|8.0|ns, Max|
|TSPICCFC|FCS_B clock to out|8.0|8.0|8.0|8.0|8.0|ns, Max|
|**DNA Port Switching**||||||||
|FDNACK|DNA port frequency|200|200|200|200|200|MHz, Max|
|**STARTUPE3 Ports**||||||||
|TUSRCCLKO|STARTUPE3 USRCCLKO input port to CCLK<br>pin output delay|1.00/<br>6.00|1.00/<br>6.70|1.00/<br>7.50|1.00/<br>7.50|1.00/<br>7.50|ns, Min/Max|
|TDO|DO[3:0] ports to D03-D00 pins output delay|1.00/<br>6.70|1.00/<br>7.70|1.00/<br>8.40|1.00/<br>8.40|1.00/<br>8.40|ns, Min/Max|
|TDTS|DTS[3:0] ports to D03-D00 pins 3-state<br>delays|1.00/<br>7.30|1.00/<br>8.30|1.00/<br>9.00|1.00/<br>9.00|1.00/<br>9.00|ns, Min/Max|
|TFCSBO|FCSBO port to FCS_B pin output delay|1.00/<br>6.90|1.00/<br>8.00|1.00/<br>8.60|1.00/<br>8.60|1.00/<br>8.60|ns, Min/Max|
|TFCSBTS|FCSBTS port to FCS_B pin 3-state delay|1.00/<br>6.90|1.00/<br>8.00|1.00/<br>8.60|1.00/<br>8.60|1.00/<br>8.60|ns, Min/Max|
|TUSRDONEO|USRDONEO port to DONE pin output delay|1.00/<br>8.50|1.00/<br>9.60|1.00/<br>10.40|1.00/<br>10.40|1.00/<br>10.40|ns, Min/Max|
|TUSRDONETS|USRDONETS port to DONE pin 3-state delay|1.00/<br>8.50|1.00/<br>9.60|1.00/<br>10.40|1.00/<br>10.40|1.00/<br>10.40|ns, Min/Max|
|TDI|D03-D00 pins to DI[3:0] ports input delay|0.5/<br>2.6|0.5/<br>3.1|0.5/<br>3.5|0.5/<br>3.5|0.5/<br>3.5|ns, Min/Max|
|FCFGMCLK|STARTUPE3 CFGMCLK output frequency|50|50|50|50|50|MHz, Typ|
|FCFGMCLKTOL|STARTUPE3 CFGMCLK output frequency<br>tolerance|±15|±15|±15|±15|±15|%, Max|
|**Startup Timing**||||||||
|TDCI_MATCH|Specifies a stall in the startup cycle until the<br>digitally controlled impedance (DCI) match<br>signals are asserted.|4|4|4|4|4|ms, Max|
## **Notes:**
1. When the CCLK is sourced from the EMCCLK pin with a divide-by-one setting, the external EMCCLK must meet this duty-cycle requirement.
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
## **eFUSE Programming Conditions**
_Table 88:_ **eFUSE Programming Conditions[(1)]**
|**Symbol**|**Description**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|
|IFS|VCCAUXsupply current|–|–|115|mA|
|Tj|Temperature range|–40|–|125|°C|
## **Notes:**
1. Do not program eFUSE during device configuration (e.g., during configuration, during configuration readback, or when readback CRC is active).
## **Revision History**
The following table shows the revision history for this document.
|**Date**|**Version**|**Description of Revisions**|
|---|---|---|
|02/02/2017|1.14|UpdatedTable 21andTable 22to production release for the following devices/speed/<br>temperature grades in the XQ Kintex UltraScale family in Vivado Design Suite 2016.4.<br>XQKU040: -1M, -2I, -2E, -1I (0.95V) devices<br>XQKU060: -1M, -2I, -2E, -1I (0.95V) devices<br>XQKU095: -1M, -2I, -2E, -1I (0.95V) devices<br>XQKU115: -2I, -2E, -1I (0.95V) devices<br>UpdatedTable 24with clarifications to the SDR minimums. UpdatedMMCM_FDRPCLK_MAX<br>inTable 36andPLL_FDRPCLK_MAXinTable 37.|
|12/22/2016|1.13|The Vivado Design Suite version is updated to the latest version listed inTable 20(either<br>v1.23 or v1.24). Per the_Kintex UltraScale and Virtex UltraScale FPGA Speed Specification_<br>_Changes_ (XCN16031<br>),Table 22changes the minimum speed specification versions for<br>designing with devices listed in this data sheet per the design advisory answer record<br>AR68169<br>: _Design Advisory for Kintex UltraScale FPGAs and Virtex UltraScale FPGAs—New_<br>_minimum production speed specification version (Speed File) required for all designs_.<br>Added the XQ devices to applicable tables includingTable 20,Table 21, andTable 22.<br>Clarified the maximum IDCandTSOLinTable 1. UpdatedILinTable 3to include<br>XQ devices. Added HP and HR minimum values toTable 23andTable 24. Added<br>TMINPER_CLKandNote 1toTable 33. AddedMMCM_FDRPCLK_MAXtoTable 36and<br>PLL_FDRPCLK_MAXtoTable 37. In theTable 49package type row, added SF for -3 and -2<br>speed specifications. This information is already reflected in the_UltraScale Architecture_<br>_and Product Overview_ (DS890<br>). AddedTable 66. Updated theAutomotive Applications<br>Disclaimer.|
|04/01/2016|1.12|UpdatedTable 20,Table 21, andTable 22to production release in Vivado Design Suite<br>2016.1 of the following devices/speed/temperature grades. With these changes, the XC<br>Kintex UltraScale family is production released.<br>XCKU085: -1L (0.95V) and -1L (0.90V) devices<br>XCKU115: -1L (0.95V) and -1L (0.90V) devices<br>InTable 26, added LPDDR3, updated the package fields, increased the DDR4 and DDR3L<br>memory PHY rates in the FBVA676/ SFVA784 packages, added LRDIMMs to the notes, and<br>removed Note 7. In addition, the QDRIV-XP is only for HP I/O banks. Updated VMEASfor<br>LVCMOS and LVTTL inTable 30. InTable 32, added theBlock RAM and FIFO Clock-to-Out<br>Delayssection. AddedTable 70.|
|12/16/2015|1.11|Updated thePower-On/Off Power Supply Sequencingsection. UpdatedTable 20to speed<br>specification 2015.4.1. Increased theFGTHMAXfor -1LI (0.90V) inTable 49and added<br>Note 1. Updated the -1LI (0.90V) column inTable 54.|
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
|**Date**|**Version**|**Description of Revisions**|
|---|---|---|
|11/24/2015|1.10.1|UpdatedTable 20,Table 21, andTable 22to production release of the following<br>devices/speed grades.<br>XCKU060: -3E and -1L (0.90V) devices<br>XCKU085: -3E devices<br>XCKU115: -3E devices<br>XCKU035: all speed grades in the SFVA784 package<br>XCKU040: all speed grades in the SFVA784 package<br>AddedNote 2toTable 22.<br>UpdatedTable 38throughTable 43with speed specifications for Vivado Design Suite<br>2015.4.<br>InTable 45, added the value for package skew on the XCKU095 FFVA1156.|
|10/12/2015|1.9|Updated data inTable 6(XCKU025, XCKU085, and XCKU095) andTable 7(XCKU095).<br>Updated the description inPower-On/Off Power Supply Sequencing.<br>UpdatedTable 21andTable 22to production release of the following devices/speed<br>grades.<br>XCKU025: -1C/-1I and -2E/-2I devices<br>XCKU035: -1LI (0.95V) and -1LI (0.90V)<br>XCKU040: -1LI (0.95V) and -1LI (0.90V)<br>XCKU060: -1LI (0.95V)<br>XCKU085: -1C/-1I and -2E/-2I devices<br>XCKU095: -1C/-1I and -2E/-2I devices<br>UpdatedTable 20,Table 21,Table 22,Table 32,Table 33,Table 34,Table 38through<br>Table 43, andTable 87with speed specifications for Vivado Design Suite 2015.3.<br>UpdatedTable 45with package skew data.<br>Added protocols toTable 57. UpdatedVCMOUTDCinTable 64. Added data toTable 73and<br>Table 74.<br>AddedStartup TimingtoTable 87.|
|09/22/2015|1.8|Added GTY tables to support the XCKU095. Added the XCKU025 device.<br>InTable 2, revised the -1L (0.90V)VCCINTand VCCINT_IOfor a recommended ±20mV<br>power supply operating range. Updated description ofICCADC.<br>UpdatedTable 21andTable 22to production release of the -1 and -2 speed grade<br>XCKU115 devices and production release of the -3 speed grade for the XCKU035 and<br>XCKU040 devices.<br>UpdatedTable 20,Table 21,Table 22,Table 32,Table 34,Table 38throughTable 43, and<br>Table 87with speed specifications for Vivado Design Suite 2015.2.1.<br>UpdatedTable 26with more delineated values including adding package variations.<br>InTable 45added the XCKU095 FFVA1156 package and updated skew values.<br>Updated protocols inTable 57.<br>Revised the values inTable 81and removed Note 1. UpdatedTable 84:Sample rate.<br>InTable 87, added further delineation between devices (SLR-based, XCKU095, and all<br>other devices), added values by speed grade, and updated -1L specifications.|
|08/03/2015|1.7|Updated and added device information inTable 7. InTable 18andTable 19updated<br>Note 2,Note 3, andNote 4.<br>UpdatedTable 21andTable 22to production release of the -1 and -2 speed grade<br>XCKU060 devices.<br>UpdatedTable 20,Table 21,Table 22,Table 32,Table 34,Table 38throughTable 43, and<br>Table 87with speed specifications for Vivado Design Suite 2015.2 v1.17.<br>AddedTable 52:GTH Transceiver Reference Clock Oscillator Selection Phase Noise Mask.<br>Added theGTH Transceiver Electrical Compliancesection.<br>RevisedFCORECLKandNote 1inTable 83. Updated theSTARTUPE3 Portsdescriptions in<br>Table 87. UpdatedNote 1inTable 88.|
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
|**Date**|**Version**|**Description of Revisions**|
|---|---|---|
|05/12/2015|1.6|The minimum software requirements changed for KU040 requiring Vivado Design Suite<br>2015.1 v1.15 per the design advisory answer record AR64347<br>: _Design Advisory for_<br>_UltraScale Speed Specification - 2015.1 Production Speed Specification Changes_. This<br>includes revisions toTable 20,Table 21,Table 22,Table 27,Table 28, andTable 38to<br>Table 43. Also, inTable 29, revised the HR I/O values for TOUTBUF_DELAY_TE_PADand added<br>Note 1.<br>UpdatedTable 21andTable 22to production release of the XCKU035 devices in the<br>FBVA676 and FFVA1156 packages. AddedNote 2toTable 3. Clarifying edits toTable 30<br>andTable 31. Added Note 1 toTable 81. Updated theOn-Chip Sensor Accuracyin<br>Table 84. InTable 87, added more specifications to theSTARTUPE3 Portssection.|
|02/24/2015|1.5|InTable 1, addedIDCandIRMSand updates to theGTH and GTY TransceiversIDCIN/OUT<br>section including addingNote 9.<br>Added many specifications and recommended values toTable 3. Updated specifications in<br>Table 4,Table 5, andTable 6. AddedTable 7. Revised the VOCMmaximum for<br>MINI_LVDS_25andRSDS_25inTable 12. Revised the VICMspecifications inTable 14.<br>Removed rows fromTable 16andTable 17. Removed VOHand VOLrows, revised the VOCM<br>maximum, and revised VICMinTable 18. Removed VOHand VOLrows and revised VICMin<br>Table 19.<br>Updated the following tables specifically addressing FBVA900 design specifications;<br>Table 21,Table 22,Table 45, andTable 49. Removed Table 27.<br>UpdatedTable 20,Table 21,Table 22,Table 27, andTable 28with speed specifications for<br>Vivado Design Suite 2014.4.1.<br>Completely revised thePerformance Characteristicssection including addingTable 23,<br>Table 24, andTable 25, updatingTable 26(including Note 7), and removing Table 27:<br>_Maximum Physical Interface (PHY) Rate for Memory Interfaces (FBV Packages)_. Added<br>the section:I/O Standard Adjustment Measurement Methodology. RevisedFREFCLKin<br>Table 33. RevisedMMCM_TLOCKMAXinTable 36. Revised the FINMAXinTable 36and<br>Table 37. UpdatedTable 44. Updated devices listed, packages listed, and package skew<br>inTable 45. UpdatedVCMOUTDCandDVPPOUTinTable 46. AddedTable 48.Table 49. Added<br>new values and descriptions to bothTable 55andTable 56. Updated the FDRP_CLKin<br>Table 81,Table 82, andTable 83. Added toFCORE_CLKandFUSERCLK Table 81. Updated<br>On-chip reference andNote 5inTable 84. Updated theFEMCCK,FSCCK,FMCCK,TPOR, and<br>TUSRCCLKOspecifications inTable 87.|
|11/14/2014|1.4|UpdatedNote 2andNote 3inTable 1andNote 3,Note 4, andNote 6inTable 2. Updated<br>Note 3inTable 6. Revised thePower-On/Off Power Supply Sequencingsection. Updated<br>the descriptions inTable 8. Removed Note 1 from bothTable 26and Table 27. Revised<br>DDR3 specification for FBVA900 package -2I speed grade in Table 27. UpdatedTable 20,<br>Table 27, andTable 28with speed specifications for Vivado Design Suite 2014.3. Updated<br>the descriptions inTable 37. Added a discussion on the data in the device pin-to-pin<br>parameter tables onpage 40andpage 43. Revised the values forFLBUS_CLKinTable 81.<br>UpdatedNote 5inTable 84. InTable 87, added more speed specifications, updatedTPL,<br>FMCCKTOL, andFRBCCK, added the_STARTUPE3 Ports_section, and addedNote 1.|
|07/10/2014|1.3|Updated LVDCI_15 information inTable 10. Revised the SLVS_400 values inTable 12.<br>UpdatedTable 20and all the tables relevant to the latest speed specification Vivado<br>2014.2 v1.08.<br>Removed RLDRAM II fromTable 26and Table 27. Also added FBV Package to Table 27.<br>Removed TDELAY_RST_RDYfromTable 33. RevisedMMCM_FINDUTYinTable 36and<br>PLL_FINDUTYinTable 37. Updated theVINdescription inTable 46. UpdatedFigure 3and<br>Figure 4. UpdatedNote 1inTable 55. Added two new sections for theIntegrated Interface<br>Block for Interlaken for the XCKU095 and XQKU095and theIntegrated Interface Block<br>for 100G Ethernet MAC and PCS for the XCKU095 and XQKU095.|
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**Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics**
|**Date**|**Version**|**Description of Revisions**|
|---|---|---|
|05/16/2014|1.2|UpdatedNote 2, added IOLand IOHspecifications, and addedNote 3andNote 4toTable 9<br>andTable 10. InTable 12, revised the MINI_LVDS_25 and RSDS_25 maximum value for<br>VOCMand added SLVS_400 specifications. InTable 13andTable 14, Added the IOLand<br>IOHspecifications. Removed the POD standards fromTable 10andTable 14.<br>Updated theAC Switching Characteristicssection andTable 20based upon the Vivado<br>Design Suite 2014.1 v1.06 speed specifications. Updated TPW_WF_NCinTable 32. Revised<br>MMCM_TFBDELAYinTable 36, and addedPLL_FBANDWIDTHtoTable 37. Updated format and<br>notes inTable 42andTable 43.<br>Revised notes inTable 49. Updated value forFGTHDRPCLKinTable 50. Updated the 0.90V<br>values for FTXOUTPROGDIVand FRXOUTPROGDIVinTable 54, and the corresponding FMAXin<br>Table 35. InTable 84, updatedOn-Chip Sensor Accuracysection, removedGain error<br>conditions, updatedNote 1, and addedNote 3.<br>InTable 87, revisedTPORspecifications and updatedFMCCK,FSCCK,FICAPCK,FRBCCK,<br>TTAPTCK/TTCKTAP,TTCKTDO, andFTCK.|
|04/09/2014|1.1|AddedIDCandIRMStoTable 1.<br>InTable 3, updated the programmable input termination resistance sections (R), added<br>Note 5andNote 6, and added theInternal VREFandDifferential termination<br>specifications.<br>InTable 8, updatedNote 3.<br>Revised theLVCMOS15VOH/VOLspecifications inTable 9andTable 10. InTable 12,<br>removed support for SUB_LVDS_25 and revised the VOCMvalues. Instead SUB_LVDS will<br>be supported in both HR and HP I/O banks. Replaced SUB_LVDS_25 inTable 27with<br>SUB_LVDS.<br>InTable 26, split the -2 speed specifications by temperature range and updated the DDR3<br>and RLDRAM III specifications. In Table 27, updated the -1 and -3 speed grade maximum<br>specifications for DDR4. Updated the speed specifications inTable 27andTable 28.<br>Removed Table 24: CLB Switching Characteristics which contained FTOG(the toggle<br>frequency). RevisedTable 32including adding TPW_WF_NC, TPW_RF, andNote 1. Updated<br>Table 33especially FREFCLK, TMINPER_RST, and the IDELAY/ODELAY chain resolution.<br>Replaced all the tables in theClock Buffers and Networkssection withTable 35. Updated<br>the MMCM_FPFDMAXinTable 36. Updated the PLL_FPFDMAXand the PLL_TOUTDUTYin<br>Table 37.<br>Changed theDVPPOUTvalue to minimum inTable 46. Updated the typical CEXTvalue in<br>Table 47. InTable 49, increased the FGTHQRANGE1maximum for the 16 output dividers in<br>the -1 speed grade, and addedNote 2andNote 3. InTable 54, updated four rows of<br>TXOUTCLK/RXOUTCLK information and removed Note 2, Note 3, and Note 4. Revised the<br>TLLSKEWvalue and units inTable 55. Updated the notes inTable 60.<br>InTable 84, revised theINLmaximum andADC Accuracy at Extended Temperaturesand<br>updated some of theOn-Chip Sensor Accuracymaximum values.<br>RevisedFMCCKand updated the ramp rate forTPORinTable 87.|
|12/10/2013|1.0|Initial Xilinx release.|
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