XC7VX690T-3FFG1158E

FPGA, Virtex-7, MMCM, PLL, 350 I/O's, 741 MHz, 693120 Cells, 970 mV to 1.03 V, FCBGA-1158, NCNR

⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
Manufacturer: AMD
Product type: FPGAs
No. of Logic Blocks:108300; No. of Macrocells:693120; FPGA Family:Virtex-7; Logic Case Style:FCBGA; No. of Pins:1158Pins; No. of Speed Grades:3; Total RAM Bits:52920Kbit; No. of I/O's
MSL: -
SVHC: No SVHC (15-Jan-2018)
FPGA Type: -
FPGA Family: Virtex-7
IC Mounting: Surface Mount
No. of Pins: 1158Pins
Speed Grade: 3
No. of I/O's: 350I/O's
Product Range: Virtex-7 XC7VX690T
Qualification: -
Total RAM Bits: 52920Kbit
No.of User I/Os: 350I/O's
Clock Management: MMCM, PLL
Logic Case Style: FCBGA
IC Case / Package: FCBGA
No. of Macrocells: 693120Macrocells
I/O Supply Voltage: 3.3V
No. of Logic Cells: 693120Logic Cells
Process Technology: 28nm (HKMG)
No. of Logic Blocks: 693120
No. of Speed Grades: 3
Core Supply Voltage Max: 1.03V
Core Supply Voltage Min: 970mV
Operating Frequency Max: 741MHz
Operating Temperature Max: 100°C
Operating Temperature Min: 0°C
Delivery and price
Units per pack	1
Price	13475.28 €
Current stock	10+
Lead time	30 days
Datasheet
**==> picture [143 x 46] intentionally omitted <==**

DS183 (v1.28) March 13, 2019 

## **Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

**Product Specification** 

## **Introduction** 

Virtex®-7 T and XT FPGAs are available in -3, -2, -1, and -2L speed grades, with -3 having the highest performance. The -2L devices operate at VCCINT = 1.0V and are screened for lower maximum static power. The speed specification of a -2L device is the same as the -2 speed grade. The -2G speed grade is available in devices utilizing Stacked Silicon Interconnect (SSI) technology. The -2G speed grade supports 12.5 Gb/s GTX or 13.1 Gb/s GTH transceivers as well as the standard -2 speed grade specifications. 

Virtex-7 T and XT FPGA DC and AC characteristics are specified in commercial, extended, industrial, and military temperature ranges. Except for the operating temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -1M speed grade military 

device are the same as for a -1C speed grade commercial device). However, only selected speed grades and/or devices are available in each temperature range. 

All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters included are common to popular designs and typical applications. 

Available device and package combinations can be found in: 

- _7 Series FPGAs Overview_ (DS180) 

- _Defense-Grade 7 Series FPGAs Overview_ (DS185) 

This Virtex-7 T and XT FPGA data sheet, part of an overall set of documentation on the 7 series FPGAs, is available on the Xilinx website at www.xilinx.com/7. 

## **DC Characteristics** 

_Table  1:_ **Absolute Maximum Ratings[(1)]** 

|**Symbol**|**Description**|**Min**|**Max**|**Units**|
|---|---|---|---|---|
|**FPGA Logic**|||||
|VCCINT|Internal supply voltage|–0.5|1.1|V|
|VCCAUX|Auxiliary supply voltage|–0.5|2.0|V|
|VCCBRAM|Supply voltage for the block RAM memories|–0.5|1.1|V|
|VCCO|Output drivers supply voltage for 3.3V HR I/O banks|–0.5|3.6|V|
||Output drivers supply voltage for 1.8V HP I/O banks|–0.5|2.0|V|
|VCCAUX_IO|Auxiliary supply voltage|–0.5|2.06|V|
|VREF|Input reference voltage|–0.5|2.0|V|
|VIN(2)(3)(4)|I/O input voltage for 3.3V HR I/O banks|–0.40|VCCO+ 0.55|V|
||I/O input voltage for 1.8V HP I/O banks|–0.55|VCCO+ 0.55|V|
||I/O input voltage (when VCCO= 3.3V) for VREFand differential I/O standards except<br>TMDS_33(5)|–0.40|2.625|V|
|VCCBATT|Key memory battery backup supply|–0.5|2.0|V|
|**GTX and GTH Transceivers**|||||
|VMGTAVCC|Analog supply voltage for the GTX/GTH transmitter and receiver circuits|–0.5|1.1|V|
|VMGTAVTT|Analog supply voltage for the GTX/GTH transmitter and receiver termination circuits|–0.5|1.32|V|
|VMGTVCCAUX|Auxiliary analog Quad PLL (QPLL) voltage supply for the GTX/GTH transceivers|–0.5|1.935|V|
|VMGTREFCLK|GTX/GTH transceiver reference clock absolute input voltage|–0.5|1.32|V|



© 2011–2017 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Kintex, Artix, Zynq, Spartan, ISE, Vivado and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. 

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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  1:_ **Absolute Maximum Ratings[(1)]** _**(Cont’d)**_ 

|**Symbol**|**Description**|**Min**|**Max**|**Units**|
|---|---|---|---|---|
|VMGTAVTTRCAL|Analog supply voltage for the resistor calibration circuit of the GTX/GTH transceiver<br>column|–0.5|1.32|V|
|VIN|Receiver (RXP/RXN) and Transmitter (TXP/TXN) absolute input voltage|–0.5|1.26|V|
|IDCIN-FLOAT|DC input current for receiver input pins DC coupled RX termination = floating|–|14|mA|
|IDCIN-MGTAVTT|DC input current for receiver input pins DC coupled RX termination = VMGTAVTT|–|12|mA|
|IDCIN-GND|DC input current for receiver input pins DC coupled RX termination = GND|–|6.5|mA|
|IDCOUT-FLOAT|DC output current for transmitter pins DC coupled RX termination = floating|–|14|mA|
|IDCOUT-MGTAVTT|DC output current for transmitter pins DC coupled RX termination = VMGTAVTT|–|12|mA|
|**XADC**|||||
|VCCADC|XADC supply relative to GNDADC|–0.5|2.0|V|
|VREFP|XADC reference input relative to GNDADC|–0.5|2.0|V|
|**Temperature**|||||
|TSTG|Storage temperature (ambient)|–65|150|°C|
|TSOL|Maximum soldering temperature for Pb/Sn component bodies(6)|–|+220|°C|
||Maximum soldering temperature for Pb-free component bodies(6)|–|+260|°C|
|Tj|Maximum junction temperature(6)|–|+125|°C|



## **Notes:** 

1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability. 

2. The lower absolute voltage specification always applies. 

3. For I/O operation, refer to the _7 Series FPGAs SelectIO Resources User Guide_ (UG471). 

4. The maximum limit applies to DC signals. For maximum undershoot and overshoot AC specifications, see Table 4 and Table 5. 

5. See Table 10 for TMDS_33 specifications. 

6. For soldering guidelines and thermal considerations, see the _7 Series FPGA Packaging and Pinout Specification_ (UG475). 

_Table  2:_ **Recommended Operating Conditions[(1)(2)]** 

|**Symbol**|**Description**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|
|**FPGA Logic**||||||
|VCCINT(3)|Internal supply voltage|0.97|1.00|1.03|V|
||Internal supply voltage for -1C devices with voltage identification (VID) bit<br>programmed to run at 0.9V typical(4).|0.87|0.90|0.93|V|
|VCCBRAM(3)|Block RAM supply voltage|0.97|1.00|1.03|V|
||Block RAM supply voltage for -1C devices with voltage identification (VID)<br>bit programmed to run at 0.9V typical(4).|0.87|0.90|1.03|V|
|VCCAUX|Auxiliary supply voltage|1.71|1.80|1.89|V|
|VCCO(5)(6)|Supply voltage for 3.3V HR I/O banks|1.14|–|3.465|V|
||Supply voltage for 1.8V HP I/O banks|1.14|–|1.89|V|
|VCCAUX_IO(7)|Auxiliary supply voltage when set to 1.8V|1.71|1.80|1.89|V|
||Auxiliary supply voltage when set to 2.0V|1.94|2.00|2.06|V|
|VIN(8)|I/O input voltage|–0.20|–|VCCO+ 0.2|V|
||I/O input voltage (when VCCO= 3.3V) for VREFand differential I/O<br>standards except TMDS_33(9)|–0.20|–|2.625|V|
|IIN(10)|Maximum current through any pin in a powered or unpowered bank when<br>forward biasing the clamp diode.|–|–|10|mA|



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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  2:_ **Recommended Operating Conditions[(1)(2)]** _**(Cont’d)**_ 

|**Symbol**|**Description**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|
|VCCBATT(11)|Battery voltage|1.0|–|1.89|V|
|**GTX and GTH Transceivers**||||||
|VMGTAVCC(12)|Analog supply voltage for the GTX/GTH transceiver QPLL frequency range<br>≤10.3125 GHz(13)(14)|0.97|1.0|1.08|V|
||Analog supply voltage for the GTX/GTH transceiver QPLL frequency range<br>> 10.3125 GHz|1.02|1.05|1.08|V|
|VMGTAVTT(12)|Analog supply voltage for the GTX/GTH transmitter and receiver<br>termination circuits|1.17|1.2|1.23|V|
|VMGTVCCAUX(12)|Auxiliary analog Quad PLL (QPLL) voltage supply for the transceivers|1.75|1.80|1.85|V|
|VMGTAVTTRCAL(12)|Analog supply voltage for the resistor calibration circuit of the GTX/GTH<br>transceiver column|1.17|1.2|1.23|V|
|**XADC**||||||
|VCCADC|XADC supply relative to GNDADC|1.71|1.80|1.89|V|
|VREFP|Externally supplied reference voltage|1.20|1.25|1.30|V|
|**Temperature**||||||
|Tj|Junction temperature operating range for commercial (C) temperature<br>devices|0|–|85|°C|
||Junction temperature operating range for extended (E) temperature<br>devices|0|–|100|°C|
||Junction temperature operating range for industrial (I) temperature devices|–40|–|100|°C|
||Junction temperature operating range for military (M) temperature devices|–55|–|125|°C|



## **Notes:** 

1. All voltages are relative to ground. 

2. For the design of the power distribution system, consult the _7 Series FPGAs PCB Design and Pin Planning Guide_ (UG483). 

3. VCCINT and VCCBRAM should be connected to the same supply. 

4. For more information on the VID bit see the _Lowering Power using the Voltage Identification Bit_ application note (XAPP555). 

5. Configuration data is retained even if VCCO drops to 0V. 

6. Includes VCCO of 1.2V, 1.35V, 1.5V, 1.8V, 2.5V (HR I/O only), 3.3V (HR I/O only) at ±5%. 

7. For more information, refer to the VCCAUX_IO section of _7 Series FPGAs SelectIO Resources User Guide_ (UG471). 

8. The lower absolute voltage specification always applies. 

9. See Table 10 for TMDS_33 specifications. 

10. A total of 200 mA per bank should not be exceeded. 

11. VCCBATT is required only when using bitstream encryption. If battery is not used, connect VCCBATT to either ground or VCCAUX. 

12. Each voltage listed requires the filter circuit described in the _7 Series FPGAs GTX/GTH Transceiver User Guide_ (UG476). 

13. For data rates ≤ 10.3125 Gb/s, VMGTAVCC should be 1.0V ±3% for lower power consumption. 

14. For lower power consumption, VMGTAVCC should be 1.0V ±3% over the entire CPLL frequency range. 

_Table  3:_ **DC Characteristics Over Recommended Operating Conditions** 

|**Symbol**|**Description**|**Min**|**Typ(1)**|**Max**|**Units**|
|---|---|---|---|---|---|
|VDRINT|Data retention VCCINTvoltage (below which configuration data might be lost)|0.75|–|–|V|
|VDRI|Data retention VCCAUXvoltage (below which configuration data might be lost)|1.5|–|–|V|
|IREF|VREFleakage current per pin|–|–|15|µA|
|IL|Input or output leakage current per pin (sample-tested)|–|–|15|µA|
|CIN(2)|Die input capacitance at the pad|–|–|8|pF|



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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  3:_ **DC Characteristics Over Recommended Operating Conditions** _**(Cont’d)**_ 

|**Symbol**|**Description**|**Min**|**Typ(1)**|**Max**|**Units**|
|---|---|---|---|---|---|
|IRPU|Pad pull-up (when selected) @ VIN= 0V, VCCO= 3.3V|90|–|330|µA|
||Pad pull-up (when selected) @ VIN= 0V, VCCO= 2.5V|68|–|250|µA|
||Pad pull-up (when selected) @ VIN= 0V, VCCO= 1.8V|34|–|220|µA|
||Pad pull-up (when selected) @ VIN= 0V, VCCO= 1.5V|23|–|150|µA|
||Pad pull-up (when selected) @ VIN= 0V, VCCO= 1.2V|12|–|120|µA|
|IRPD|Pad pull-down (when selected) @ VIN= 3.3V|68|–|330|µA|
||Pad pull-down (when selected) @ VIN= 1.8V|45|–|180|µA|
|ICCADC|Analog supply current, analog circuits in powered up state|–|–|25|mA|
|IBATT(3)|Battery supply current|–|–|150|nA|
|RIN_TERM(4)|Thevenin equivalent resistance of programmable input termination to VCCO/2<br>(UNTUNED_SPLIT_40)|28|40|55|Ω|
||Thevenin equivalent resistance of programmable input termination to VCCO/2<br>(UNTUNED_SPLIT_50)|35|50|65|Ω|
||Thevenin equivalent resistance of programmable input termination to VCCO/2<br>(UNTUNED_SPLIT_60)|44|60|83|Ω|
|n|Temperature diode ideality factor|–|1.010|–|–|
|r|Temperature diode series resistance|–|2|–|Ω|



## **Notes:** 

1. Typical values are specified at nominal voltage, 25°C. 

2. This measurement represents the die capacitance at the pad, not including the package. 

3. Maximum value specified for worst-case process at 25°C. For the XC7VX1140T and XC7V2000T devices, multiply the value by the number of super-logic regions (SLRs) in the device. 

4. Termination resistance to a VCCO/2 level. 

_Table  4:_ **VIN Maximum Allowed AC Voltage Overshoot and Undershoot for 3.3V HR I/O Banks[(1)(2)]** 

|_ae  :_ **INaxmum owe**|**oage versoo an**|**nersoo or .**|**ans**|
|---|---|---|---|
|**AC Voltage Overshoot**|**% of UI @–55°C to 125°C**|**AC Voltage Undershoot**|**% of UI @–55°C to 125°C**|
|VCCO+ 0.55|100|–0.40|100|
|||–0.45|61.7|
|||–0.50|25.8|
|||–0.55|11.0|
|VCCO+ 0.60|46.6|–0.60|4.77|
|VCCO+ 0.65|21.2|–0.65|2.10|
|VCCO+ 0.70|9.75|–0.70|0.94|
|VCCO+ 0.75|4.55|–0.75|0.43|
|VCCO+ 0.80|2.15|–0.80|0.20|
|VCCO+ 0.85|1.02|–0.85|0.09|
|VCCO+ 0.90|0.49|–0.90|0.04|
|VCCO+ 0.95|0.24|–0.95|0.02|



## **Notes:** 

1. A total of 200 mA per bank should not be exceeded. 

2. The peak voltage of the overshoot or undershoot, and the duration above VCCO + 0.20V or below GND – 0.20V, must not exceed the values in this table. 

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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  5:_ **VIN Maximum Allowed AC Voltage Overshoot and Undershoot for 1.8V HP I/O Banks[(1)(2)]** 

|_ae  :_ **IN axmum owe**|**oage versoo an**|**nersoo or .**|**ans**|
|---|---|---|---|
|**AC Voltage Overshoot**|**% of UI @–55°C to 125°C**|**AC Voltage Undershoot**|**% of UI @–55°C to 125°C**|
|VCCO+ 0.55|100|–0.55|100|
|VCCO+ 0.60|50.0(3)|–0.60|50.0(3)|
|VCCO+ 0.65|50.0(3)|–0.65|50.0(3)|
|VCCO+ 0.70|47.0|–0.70|50.0(3)|
|VCCO+ 0.75|21.2|–0.75|50.0(3)|
|VCCO+ 0.80|9.71|–0.80|50.0(3)|
|VCCO+ 0.85|4.51|–0.85|28.4|
|VCCO+ 0.90|2.12|–0.90|12.7|
|VCCO+ 0.95|1.01|–0.95|5.79|



## **Notes:** 

1. A total of 200 mA per bank should not be exceeded. 

2. The peak voltage of the overshoot or undershoot, and the duration above VCCO + 0.20V or below GND – 0.20V, must not exceed the values in this table. 

3. For UI lasting less than 20 µs. 

_Table  6:_ **Typical Quiescent Supply Current** 

|**Symbol**|**Description**|**Device**|**Speed Grade**<br>**-3**<br>**-2G**<br>**-2**<br>**-2L**<br>**-1**<br>**-1M**|**Speed Grade**<br>**-3**<br>**-2G**<br>**-2**<br>**-2L**<br>**-1**<br>**-1M**|**Speed Grade**<br>**-3**<br>**-2G**<br>**-2**<br>**-2L**<br>**-1**<br>**-1M**|**Speed Grade**<br>**-3**<br>**-2G**<br>**-2**<br>**-2L**<br>**-1**<br>**-1M**|**Speed Grade**<br>**-3**<br>**-2G**<br>**-2**<br>**-2L**<br>**-1**<br>**-1M**|**Speed Grade**<br>**-3**<br>**-2G**<br>**-2**<br>**-2L**<br>**-1**<br>**-1M**|**Units**|
|---|---|---|---|---|---|---|---|---|---|
|||||**-2G**|**-2**|**-2L**|**-1**|**-1M**||
|ICCINTQ|Quiescent VCCINTsupply current|XC7V585T|1483|1483|1483|1483|1483|N/A|mA|
|||XC7V2000T|N/A|3756|3756|3756|3756|N/A|mA|
|||XC7VX330T|1012|1012|1012|1012|1012|N/A|mA|
|||XC7VX415T|1324|1324|1324|1324|1324|N/A|mA|
|||XC7VX485T|1578|1578|1578|1578|1578|N/A|mA|
|||XC7VX550T|2214|2214|2214|2214|2214|N/A|mA|
|||XC7VX690T|2214|2214|2214|2214|2214|N/A|mA|
|||XC7VX980T|N/A|2580|2580|2580|2580|N/A|mA|
|||XC7VX1140T|N/A|3448|3448|3448|3448|N/A|mA|
|||XQ7V585T|N/A|N/A|1483|1483|1483|1483|mA|
|||XQ7VX330T|N/A|N/A|1012|1012|1012|1012|mA|
|||XQ7VX485T|N/A|N/A|1578|1578|1578|1578|mA|
|||XQ7VX690T|N/A|N/A|2214|N/A|2214|N/A|mA|
|||XQ7VX980T|N/A|N/A|N/A|2580|2580|N/A|mA|



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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  6:_ **Typical Quiescent Supply Current** _**(Cont’d)**_ 

|**Symbol**|**Description**|**Device**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|---|---|---|
||||**-3**|**-2G**|**-2**|**-2L**|**-1**|**-1M**||
|ICCOQ|Quiescent VCCOsupply current|XC7V585T|1|1|1|1|1|N/A|mA|
|||XC7V2000T|N/A|1|1|1|1|N/A|mA|
|||XC7VX330T|1|1|1|1|1|N/A|mA|
|||XC7VX415T|1|1|1|1|1|N/A|mA|
|||XC7VX485T|1|1|1|1|1|N/A|mA|
|||XC7VX550T|1|1|1|1|1|N/A|mA|
|||XC7VX690T|1|1|1|1|1|N/A|mA|
|||XC7VX980T|N/A|1|1|1|1|N/A|mA|
|||XC7VX1140T|N/A|1|1|1|1|N/A|mA|
|||XQ7V585T|N/A|N/A|1|1|1|1|mA|
|||XQ7VX330T|N/A|N/A|1|1|1|1|mA|
|||XQ7VX485T|N/A|N/A|1|1|1|1|mA|
|||XQ7VX690T|N/A|N/A|1|N/A|1|N/A|mA|
|||XQ7VX980T|N/A|N/A|N/A|1|1|N/A|mA|
|ICCAUXQ|Quiescent VCCAUXsupply current|XC7V585T|114|114|114|114|114|N/A|mA|
|||XC7V2000T|N/A|315|315|315|315|N/A|mA|
|||XC7VX330T|73|73|73|73|73|N/A|mA|
|||XC7VX415T|88|88|88|88|88|N/A|mA|
|||XC7VX485T|104|104|104|104|104|N/A|mA|
|||XC7VX550T|147|147|147|147|147|N/A|mA|
|||XC7VX690T|147|147|147|147|147|N/A|mA|
|||XC7VX980T|N/A|183|183|183|183|N/A|mA|
|||XC7VX1140T|N/A|250|250|250|250|N/A|mA|
|||XQ7V585T|N/A|N/A|114|114|114|114|mA|
|||XQ7VX330T|N/A|N/A|73|73|73|73|mA|
|||XQ7VX485T|N/A|N/A|104|104|104|104|mA|
|||XQ7VX690T|N/A|N/A|147|N/A|147|N/A|mA|
|||XQ7VX980T|N/A|N/A|N/A|183|183|N/A|mA|



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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  6:_ **Typical Quiescent Supply Current** _**(Cont’d)**_ 

|**Symbol**|**Description**|**Device**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|---|---|---|
||||**-3**|**-2G**|**-2**|**-2L**|**-1**|**-1M**||
|ICCAUX_IOQ|Quiescent VCCAUX_IOsupply current|XC7V585T|2|2|2|2|2|N/A|mA|
|||XC7V2000T|N/A|2|2|2|2|N/A|mA|
|||XC7VX330T|2|2|2|2|2|N/A|mA|
|||XC7VX415T|2|2|2|2|2|N/A|mA|
|||XC7VX485T|2|2|2|2|2|N/A|mA|
|||XC7VX550T|2|2|2|2|2|N/A|mA|
|||XC7VX690T|2|2|2|2|2|N/A|mA|
|||XC7VX980T|N/A|2|2|2|2|N/A|mA|
|||XC7VX1140T|N/A|2|2|2|2|N/A|mA|
|||XQ7V585T|N/A|N/A|2|2|2|2|mA|
|||XQ7VX330T|N/A|N/A|2|2|2|2|mA|
|||XQ7VX485T|N/A|N/A|2|2|2|2|mA|
|||XQ7VX690T|N/A|N/A|2|N/A|2|N/A|mA|
|||XQ7VX980T|N/A|N/A|N/A|2|2|N/A|mA|
|ICCBRAMQ|Quiescent VCCBRAMsupply current|XC7V585T|34|34|34|34|34|N/A|mA|
|||XC7V2000T|N/A|56|56|56|56|N/A|mA|
|||XC7VX330T|32|32|32|32|32|N/A|mA|
|||XC7VX415T|38|38|38|38|38|N/A|mA|
|||XC7VX485T|44|44|44|44|44|N/A|mA|
|||XC7VX550T|63|63|63|63|63|N/A|mA|
|||XC7VX690T|63|63|63|63|63|N/A|mA|
|||XC7VX980T|N/A|65|65|65|65|N/A|mA|
|||XC7VX1140T|N/A|81|81|81|81|N/A|mA|
|||XQ7V585T|N/A|N/A|34|34|34|34|mA|
|||XQ7VX330T|N/A|N/A|32|32|32|32|mA|
|||XQ7VX485T|N/A|N/A|44|44|44|44|mA|
|||XQ7VX690T|N/A|N/A|63|N/A|63|N/A|mA|
|||XQ7VX980T|N/A|N/A|N/A|65|65|N/A|mA|



## **Notes:** 

1. Typical values are specified at nominal voltage, 85°C junction temperatures (Tj) with single-ended SelectIO resources. 

2. Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and floating. 

3. Use the Xilinx Power Estimator (XPE) spreadsheet tool (download at http://www.xilinx.com/power) to estimate static power consumption for conditions other than those specified. 

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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

## **Power-On/Off Power Supply Sequencing** 

The recommended power-on sequence is VCCINT, VCCBRAM, VCCAUX, VCCAUX_IO, and VCCO to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on. The recommended power-off sequence is the reverse of the power-on sequence. If VCCINT and VCCBRAM have the same recommended voltage levels then both can be powered by the same supply and ramped simultaneously. If VCCAUX, VCCAUX_IO, and VCCO have the same recommended voltage levels then they can be powered by the same supply and ramped simultaneously. 

For VCCO voltages of 3.3V in HR I/O banks and configuration bank 0: 

- The voltage difference between VCCO and VCCAUX must not exceed 2.625V for longer than TVCCO2VCCAUX for each power-on/off cycle to maintain device reliability levels. 

- The TVCCO2VCCAUX time can be allocated in any percentage between the power-on and power-off ramps. 

The recommended power-on sequence to achieve minimum current draw for the GTX/GTH transceivers is VCCINT, VMGTAVCC, VMGTAVTT OR VMGTAVCC, VCCINT, VMGTAVTT. There is no recommended sequencing for VMGTVCCAUX. Both VMGTAVCC and VCCINT can be ramped simultaneously. The recommended power-off sequence is the reverse of the power-on sequence to achieve minimum current draw. 

If these recommended sequences are not met, current drawn from VMGTAVTT can be higher than specifications during powerup and power-down. 

- When VMGTAVTT is powered before VMGTAVCC and VMGTAVTT – VMGTAVCC > 150 mV and VMGTAVCC < 0.7V, the VMGTAVTT current draw can increase by 460 mA per transceiver during VMGTAVCC ramp up. The duration of the current draw can be up to 0.3 x TMGTAVCC (ramp time from GND to 90% of VMGTAVCC). The reverse is true for power-down. 

- When VMGTAVTT is powered before VCCINT and VMGTAVTT – VCCINT > 150 mV and VCCINT < 0.7V, the VMGTAVTT current draw can increase by 50 mA per transceiver during VCCINT ramp up. The duration of the current draw can be up to 0.3 x TVCCINT (ramp time from GND to 90% of VCCINT). The reverse is true for power-down. 

There is no recommended sequence for supplies not shown. 

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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

Table 7 shows the minimum current, in addition to ICCQ, that is required by Virtex-7 T and XT devices for proper power-on and configuration. If the current minimums shown in Table 6 and Table 7 are met, the device powers on after all five supplies have passed through their power-on reset threshold voltages. The FPGA must not be configured until after VCCINT is applied. 

Once initialized and configured, use the Xilinx Power tools to estimate current drain on these supplies. 

_Table  7:_ **Power-On Current for Virtex-7 T and XT Devices** 

|**Device**|**ICCINTMIN**|**ICCAUXMIN**|**ICCOMIN**|**ICCAUX_IO**|**ICCBRAM**|**Units**|
|---|---|---|---|---|---|---|
|XC7V585T|ICCINTQ+ 2700|ICCAUXQ+ 40|ICCOQ+ 60 mA per bank|ICCOAUXIOQ+ 40 mA per bank|ICCBRAMQ+ 108|mA|
|XC7V2000T|ICCINTQ+ 4000|ICCAUXQ+ 80|ICCOQ+ 60 mA per bank|ICCOAUXIOQ+ 40 mA per bank|ICCBRAMQ+ 176|mA|
|XC7VX330T|ICCINTQ+ 1000|ICCAUXQ+ 65|ICCOQ+ 40 mA per bank|ICCOAUXIOQ+ 40 mA per bank|ICCBRAMQ+ 95|mA|
|XC7VX415T|ICCINTQ+ 1200|ICCAUXQ+ 75|ICCOQ+ 40 mA per bank|ICCOAUXIOQ+ 40 mA per bank|ICCBRAMQ+ 115|mA|
|XC7VX485T|ICCINTQ+ 1200|ICCAUXQ+ 80|ICCOQ+ 40 mA per bank|ICCOAUXIOQ+ 40 mA per bank|ICCBRAMQ+ 140|mA|
|XC7VX550T|ICCINTQ+ 3300|ICCAUXQ+ 143|ICCOQ+ 40 mA per bank|ICCOAUXIOQ+ 57 mA per bank|ICCBRAMQ+ 200|mA|
|XC7VX690T|ICCINTQ+ 3300|ICCAUXQ+ 143|ICCOQ+ 40 mA per bank|ICCOAUXIOQ+ 57 mA per bank|ICCBRAMQ+ 200|mA|
|XC7VX980T|ICCINTQ+ 6500|ICCAUXQ+ 202|ICCOQ+ 40 mA per bank|ICCOAUXIOQ+ 60 mA per bank|ICCBRAMQ+ 204|mA|
|XC7VX1140T|ICCINTQ+ 8000|ICCAUXQ+ 235|ICCOQ+ 40 mA per bank|ICCOAUXIOQ+ 63 mA per bank|ICCBRAMQ+ 256|mA|
|XQ7V585T|ICCINTQ+ 2700|ICCAUXQ+ 40|ICCOQ+ 60 mA per bank|ICCOAUXIOQ+ 40 mA per bank|ICCBRAMQ+ 108|mA|
|XQ7VX330T|ICCINTQ+ 1000|ICCAUXQ+ 65|ICCOQ+ 40 mA per bank|ICCOAUXIOQ+ 40 mA per bank|ICCBRAMQ+ 95|mA|
|XQ7VX485T|ICCINTQ+ 1200|ICCAUXQ+ 80|ICCOQ+ 40 mA per bank|ICCOAUXIOQ+ 40 mA per bank|ICCBRAMQ+ 140|mA|
|XQ7VX690T|ICCINTQ+ 3300|ICCAUXQ+ 143|ICCOQ+ 40 mA per bank|ICCOAUXIOQ+ 57 mA per bank|ICCBRAMQ+ 200|mA|
|XQ7VX980T|ICCINTQ+ 6500|ICCAUXQ+ 202|ICCOQ+ 40 mA per bank|ICCOAUXIOQ+ 60 mA per bank|ICCBRAMQ+ 204|mA|



_Table  8:_ **Power Supply Ramp Time** 

|**Symbol**|**Description**|**Conditions**|**Min**|**Max**|**Units**|
|---|---|---|---|---|---|
|TVCCINT|Ramp time from GND to 90% of VCCINT||0.2|50|ms|
|TVCCO|Ramp time from GND to 90% of VCCO||0.2|50|ms|
|TVCCAUX|Ramp time from GND to 90% of VCCAUX||0.2|50|ms|
|TVCCAUX_IO|Ramp time from GND to 90% of VCCAUX_IO||0.2|50|ms|
|TVCCBRAM|Ramp time from GND to 90% of VCCBRAM||0.2|50|ms|
|TVCCO2VCCAUX|Allowed time per power cycle for VCCO– VCCAUX >2.625V|TJ= 125°C(1)|–|300|ms|
|||TJ= 100°C(1)|–|500||
|||TJ= 85°C(1)|–|800||
|TMGTAVCC|Ramp time from GND to 90% of VMGTAVCC||0.2|50|ms|
|TMGTAVTT|Ramp time from GND to 90% of VMGTAVTT||0.2|50|ms|
|TMGTVCCAUX|Ramp time from GND to 90% of VMGTVCCAUX||0.2|50|ms|



## **Notes:** 

1. Based on 240,000 power cycles with nominal VCCO of 3.3V or 36,500 power cycles with a worst case VCCO of 3.465V. 

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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

## **DC Input and Output Levels** 

Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the recommended operating conditions at the VOL and VOH test points. Only selected standards are tested. These are chosen to ensure that all standards meet their specifications. The selected standards are tested at a minimum VCCO with the respective VOL and VOH voltage levels shown. Other standards are sample tested. 

_Table  9:_ **SelectIO DC Input and Output Levels[(1)(2)]** 

|**I/O Standard**|**VIL**|**VIL**|**VIH**|**VIH**|**VOL**|**VOH**|**IOL**|**IOH**|
|---|---|---|---|---|---|---|---|---|
||**V, Min**|**V, Max**|**V, Min**|**V, Max**|**V, Max**|**V, Min**|**mA**|**mA**|
|HSTL_I|–0.300|VREF– 0.100|VREF+ 0.100|VCCO+ 0.300|0.400|VCCO– 0.400|8|–8|
|HSTL_I_12|–0.300|VREF– 0.080|VREF+ 0.080|VCCO+ 0.300|25% VCCO|75% VCCO|6.3|–6.3|
|HSTL_I_18|–0.300|VREF– 0.100|VREF+ 0.100|VCCO+ 0.300|0.400|VCCO– 0.400|8|–8|
|HSTL_II|–0.300|VREF– 0.100|VREF+ 0.100|VCCO+ 0.300|0.400|VCCO– 0.400|16|–16|
|HSTL_II_18|–0.300|VREF– 0.100|VREF+ 0.100|VCCO+ 0.300|0.400|VCCO– 0.400|16|–16|
|HSUL_12|–0.300|VREF– 0.130|VREF+ 0.130|VCCO+ 0.300|20% VCCO|80% VCCO|0.1|–0.1|
|LVCMOS12|–0.300|35% VCCO|65% VCCO|VCCO+ 0.300|0.400|VCCO– 0.400|Note 3|Note 3|
|LVCMOS15,<br>LVDCI_15|–0.300|35% VCCO|65% VCCO|VCCO+ 0.300|25% VCCO|75% VCCO|Note 4|Note 4|
|LVCMOS18,<br>LVDCI_18|–0.300|35% VCCO|65% VCCO|VCCO+ 0.300|0.450|VCCO– 0.450|Note 5|Note 5|
|LVCMOS25|–0.300|0.700|1.700|VCCO+ 0.300|0.400|VCCO– 0.400|Note 6|Note 6|
|LVCMOS33|–0.300|0.800|2.000|3.450|0.400|VCCO– 0.400|Note 6|Note 6|
|LVTTL|–0.300|0.800|2.000|3.450|0.400|2.400|Note 7|Note 7|
|MOBILE_DDR|–0.300|20% VCCO|80% VCCO|VCCO+ 0.300|10% VCCO|90% VCCO|0.1|–0.1|
|PCI33_3|–0.400|30% VCCO|50% VCCO|VCCO+ 0.500|10% VCCO|90% VCCO|1.5|–0.5|
|SSTL12|–0.300|VREF– 0.100|VREF+ 0.100|VCCO+ 0.300|VCCO/2 – 0.150|VCCO/2 + 0.150|14.25|–14.25|
|SSTL135|–0.300|VREF– 0.090|VREF+ 0.090|VCCO+ 0.300|VCCO/2 – 0.150|VCCO/2 + 0.150|13.0|–13.0|
|SSTL135_R|–0.300|VREF– 0.090|VREF+ 0.090|VCCO+ 0.300|VCCO/2 – 0.150|VCCO/2 + 0.150|8.9|–8.9|
|SSTL15|–0.300|VREF– 0.100|VREF+ 0.100|VCCO+ 0.300|VCCO/2 – 0.175|VCCO/2 + 0.175|13.0|–13.0|
|SSTL15_R|–0.300|VREF– 0.100|VREF+ 0.100|VCCO+ 0.300|VCCO/2 – 0.175|VCCO/2 + 0.175|8.9|–8.9|
|SSTL18_I|–0.300|VREF– 0.125|VREF+ 0.125|VCCO+ 0.300|VCCO/2 – 0.470|VCCO/2 + 0.470|8|–8|
|SSTL18_II|–0.300|VREF– 0.125|VREF+ 0.125|VCCO+ 0.300|VCCO/2 – 0.600|VCCO/2 + 0.600|13.4|–13.4|



## **Notes:** 

1. Tested according to relevant specifications. 

2. 3.3V and 2.5V standards are only supported in 3.3V I/O banks. 

3. Supported drive strengths of 2, 4, 6, or 8 mA in HP I/O banks and 4, 8, or 12 mA in HR I/O banks. 

4. Supported drive strengths of 2, 4, 6, 8, 12, or 16 mA in HP I/O banks and 4, 8, 12, or 16 mA in HR I/O banks. 

5. Supported drive strengths of 2, 4, 6, 8, 12, or 16 mA in HP I/O banks and 4, 8, 12, 16, or 24 mA in HR I/O banks. 

6. Supported drive strengths of 4, 8, 12, or 16 mA 

7. Supported drive strengths of 4, 8, 12, 16, or 24 mA 

8. For detailed interface specific DC voltage levels, see the _7 Series FPGAs SelectIO Resources User Guide_ (UG471). 

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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  10:_ **Differential SelectIO DC Input and Output Levels** 

|**I/O Standard**|**VICM(1)**|**VICM(1)**|**VICM(1)**|**VID(2)**|**VID(2)**|**VID(2)**|**VOCM(3)**|**VOCM(3)**|**VOCM(3)**|**VOD(4)**|**VOD(4)**|**VOD(4)**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
||**V, Min **|**V, Typ**|**V, Max**|**V, Min **|**V, Typ **|**V, Max**|**V, Min**|**V, Typ**|**V, Max**|**V, Min **|**V, Typ **|**V, Max**|
|BLVDS_25|0.300|1.200|1.425|0.100|–|–|–|1.250|–|Note 5|||
|MINI_LVDS_25|0.300|1.200|VCCAUX|0.200|0.400|0.600|1.000|1.200|1.400|0.300|0.450|0.600|
|PPDS_25|0.200|0.900|VCCAUX|0.100|0.250|0.400|0.500|0.950|1.400|0.100|0.250|0.400|
|RSDS_25|0.300|0.900|1.500|0.100|0.350|0.600|1.000|1.200|1.400|0.100|0.350|0.600|
|TMDS_33|2.700|2.965|3.230|0.150|0.675|1.200|VCCO–0.405|VCCO–0.300|VCCO–0.190|0.400|0.600|0.800|



## **Notes:** 

1. VICM is the input common mode voltage. 

2. VID is the input differential voltage (Q – Q). 

3. VOCM is the output common mode voltage. 

4. VOD is the output differential voltage (Q – Q). 

5. VOD for BLVDS will vary significantly depending on topology and loading. 

6. LVDS_25 is specified in Table 12. 

7. LVDS is specified in Table 13. 

_Table  11:_ **Complementary Differential SelectIO DC Input and Output Levels** 

|**I/O Standard**|**VICM(1)**|**VICM(1)**|**VICM(1)**|**VID(2)**|**VID(2)**|**VOL(3)**|**VOH(4)**|**IOL**|**IOH**|
|---|---|---|---|---|---|---|---|---|---|
||**V, Min**|**V, Typ**|**V, Max**|**V, Min**|**V, Max**|**V, Max**|**V, Min**|**mA, Max**|**mA, Min**|
|DIFF_HSTL_I|0.300|0.750|1.125|0.100|–|0.400|VCCO–0.400|8.00|–8.00|
|DIFF_HSTL_I_18|0.300|0.900|1.425|0.100|–|0.400|VCCO–0.400|8.00|–8.00|
|DIFF_HSTL_II|0.300|0.750|1.125|0.100|–|0.400|VCCO–0.400|16.00|–16.00|
|DIFF_HSTL_II_18|0.300|0.900|1.425|0.100|–|0.400|VCCO–0.400|16.00|–16.00|
|DIFF_HSUL_12|0.300|0.600|0.850|0.100|–|20% VCCO|80% VCCO|0.100|–0.100|
|DIFF_MOBILE_DDR|0.300|0.900|1.425|0.100|–|10% VCCO|90% VCCO|0.100|–0.100|
|DIFF_SSTL12|0.300|0.600|0.850|0.100|–|(VCCO/2) – 0.150|(VCCO/2) + 0.150|14.25|–14.25|
|DIFF_SSTL135|0.300|0.675|1.000|0.100|–|(VCCO/2) – 0.150|(VCCO/2) + 0.150|13.0|–13.0|
|DIFF_SSTL135_R|0.300|0.675|1.000|0.100|–|(VCCO/2) – 0.150|(VCCO/2) + 0.150|8.9|–8.9|
|DIFF_SSTL15|0.300|0.750|1.125|0.100|–|(VCCO/2) – 0.175|(VCCO/2) + 0.175|13.0|–13.0|
|DIFF_SSTL15_R|0.300|0.750|1.125|0.100|–|(VCCO/2) – 0.175|(VCCO/2) + 0.175|8.9|–8.9|
|DIFF_SSTL18_I|0.300|0.900|1.425|0.100|–|(VCCO/2) – 0.470|(VCCO/2) + 0.470|8.00|–8.00|
|DIFF_SSTL18_II|0.300|0.900|1.425|0.100|–|(VCCO/2) – 0.600|(VCCO/2) + 0.600|13.4|–13.4|



## **Notes:** 

1. VICM is the input common mode voltage. 

2. VID is the input differential voltage (Q – Q). 

3. VOL is the single-ended low-output voltage. 

4. VOH is the single-ended high-output voltage. 

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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

## **LVDS DC Specifications (LVDS_25)** 

The LVDS standard is available in the HR I/O banks. 

_Table  12:_ **LVDS_25 DC Specifications[(1)]** 

|**Symbol**|**DC Parameter**|**Conditions**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|VCCO|Supply voltage||2.375|2.500|2.625|V|
|VOH|Output High voltage for Q and Q|RT= 100Ωacross Q and Q<br>signals|–|–|1.675|V|
|VOL|Output Low voltage for Q and Q|RT= 100Ωacross Q and Q<br>signals|0.700|–|–|V|
|VODIFF|Differential output voltage<br>(Q– Q<br>),Q= High<br>(Q<br>– Q), Q<br>= High|RT= 100Ωacross Q and Q<br>signals|247|350|600|mV|
|VOCM|Output common-mode voltage|RT= 100Ωacross Q and Q<br>signals|1.000|1.250|1.425|V|
|VIDIFF|Differential input voltage<br>(Q– Q<br>),Q= High<br>(Q<br>– Q), Q<br>= High||100|350|600|mV|
|VICM|Input common-mode voltage||0.300|1.200|1.500|V|



## **Notes:** 

1. Differential inputs for LVDS_25 can be placed in banks with VCCO levels that are different from the required level for outputs. Consult the _7 Series FPGAs SelectIO Resources User Guide_ (UG471) for more information. 

## **LVDS DC Specifications (LVDS)** 

The LVDS standard is available in the HP I/O banks. 

_Table  13:_ **LVDS DC Specifications** 

|**Symbol**|**DC Parameter**|**Conditions**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|VCCO|Supply voltage||1.710|1.800|1.890|V|
|VOH|Output High voltage for Q and Q|RT= 100Ωacross Q and Q<br>signals|–|–|1.675|V|
|VOL|Output Low voltage for Q and Q|RT= 100Ωacross Q and Q<br>signals|0.825|–|–|V|
|VODIFF|Differential output voltage<br>(Q– Q<br>),Q= High<br>(Q<br>– Q), Q<br>= High|RT= 100Ωacross Q and Q<br>signals|247|350|600|mV|
|VOCM|Output common-mode voltage|RT= 100Ωacross Q and Q<br>signals|1.000|1.250|1.425|V|
|VIDIFF|Differential input voltage<br>(Q– Q<br>),Q= High<br>(Q<br>– Q), Q<br>= High|Common-mode input voltage = 1.25V|100|350|600|mV|
|VICM|Input common-mode voltage|Differential input voltage = ±350 mV|0.300|1.200|1.425|V|



## **Notes:** 

1. Differential inputs for LVDS can be placed in banks with VCCO levels that are different from the required level for outputs. Consult the _7 Series FPGAs SelectIO Resources User Guide_ (UG471) for more information. 

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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

## **AC Switching Characteristics** 

All values represented in this data sheet are based on the speed specifications in the ISE® Design Suite 14.7 and Vivado® Design Suite 2013.4 as outlined in Table 14. 

_Table  14:_ **Virtex-7 T and XT FPGA Speed Specification Version By Device** 

|**Version In:**|**Version In:**|**Typical VCCINT**|**Device**|
|---|---|---|---|
|**ISE 14.7**|**Vivado 2013.4**|**(Table 2)**||
|1.05|1.06|1.0V|XQ7V585T, XQ7VX485T|
|1.06|1.07|1.0V|XQ7VX330T, XQ7VX690T, XQ7VX980T|
|1.10|1.11|1.0V|XC7V585T, XC7VX485T|
|N/A|1.10|1.0V|XC7V2000T|
|1.10|1.11|1.0V|XC7VX330T, XC7VX415T, XC7VX550T, XC7VX690T, XC7VX980T|
|N/A|1.11|1.0V|XC7VX1140T|



Switching characteristics are specified on a per-speed-grade basis and can be designated as Advance, Preliminary, or Production. Each designation is defined as follows: 

## _**Advance Product Specification**_ 

These specifications are based on simulations only and are typically available soon after device design specifications are frozen. Although speed grades with this designation are considered relatively stable and conservative, some under-reporting might still occur. 

## _**Preliminary Product Specification**_ 

These specifications are based on complete ES (engineering sample) silicon characterization. Devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon. The probability of under-reporting delays is greatly reduced as compared to Advance data. 

## _**Production Product Specification**_ 

These specifications are released once enough production silicon of a particular device family member has been characterized to provide full correlation between specifications and devices over numerous production lots. There is no under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest speed grades transition to Production before faster speed grades. 

## **Testing of AC Switching Characteristics** 

Internal timing parameters are derived from measuring internal test patterns. All AC switching characteristics are representative of worst-case supply voltage and junction temperature conditions. 

For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer and back-annotate to the simulation net list. Unless otherwise noted, values apply to all Virtex-7 T and XT FPGAs. 

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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

## **Speed Grade Designations** 

Since individual family members are produced at different times, the migration from one category to another depends completely on the status of the fabrication process for each device. Table 15 correlates the current status of each Virtex-7 T and XT device on a per speed grade basis. 

_Table  15:_ **Virtex-7 T and XT Device Speed Grade Designations** 

|**Device**|**Speed Grade Designations**|**Speed Grade Designations**|**Speed Grade Designations**|
|---|---|---|---|
||**Advance**|**Preliminary**|**Production**|
|XC7V585T|||-3, -2, -2L, -1|
|XC7V2000T|||-2, -2L, -2G, -1|
|XC7VX330T|||-3, -2, -2L, -1|
|XC7VX415T|||-3, -2, -2L, -1|
|XC7VX485T|||-3, -2, -2L, -1|
|XC7VX550T|||-3, -2, -2L, -1|
|XC7VX690T|||-3, -2, -2L, -1|
|XC7VX980T|||-2, -2L, -1|
|XC7VX1140T|||-2, -2L, -2G, -1|
|XQ7V585T|||-2, -2L, -1I, -1M|
|XQ7VX330T|||-2, -2L, -1I, -1M|
|XQ7VX485T|||-2I, -2L, -1I, -1M|
|XQ7VX690T|||-2I, -1I|
|XQ7VX980T|||-2L, -1I|



## **Production Silicon and Software Status** 

In some cases, a particular family member (and speed grade) is released to production before a speed specification is released with the correct label (Advance, Preliminary, Production). Any labeling discrepancies are corrected in subsequent speed specification releases. 

Table 16 lists the production released Virtex-7 T and XT device, speed grade, and the minimum corresponding supported speed specification version and software revisions. The software and speed specifications listed are the minimum releases required for production. All subsequent releases of software and speed specifications are valid. 

_Table  16:_ **Virtex-7 T and XT Device Production Software and Speed Specification Release** 

|**Device**||**Speed Grade Designations**|**Speed Grade Designations**|**Speed Grade Designations**|**Speed Grade Designations**||
|---|---|---|---|---|---|---|
||**-3**|**-2G**|**-2**|**-2L**|**-1**|**-1M**|
|XC7V585T|Vivado tools 2012.4 v1.08<br>or ISE tools 14.2 v1.06|N/A|Vivado tools 2012.4 v1.08 or ISE tools 14.2 v1.06|||N/A|
|XC7V2000T|N/A|Vivado tools 2012.4 v1.07||||N/A|
|XC7VX330T|Vivado tools 2013.1 v1.08<br>or ISE tools 14.5 v1.08|N/A|Vivado tools 2013.1 v1.08 or ISE tools 14.5 v1.08|||N/A|
|XC7VX415T||N/A||||N/A|
|XC7VX485T|Vivado tools 2012.4 v1.08<br>or ISE tools 14.2 v1.06|N/A|Vivado tools 2012.4 v1.08 or ISE tools 14.2 v1.06|||N/A|
|XC7VX550T|Vivado tools 2013.1 v1.08<br>or ISE tools 14.5 v1.08|N/A|Vivado tools 2013.1 v1.08 or ISE tools 14.5 v1.08|||N/A|
|XC7VX690T|Vivado tools 2013.1 v1.08<br>or ISE tools 14.5 v1.08|N/A|Vivado tools 2013.1 v1.08 or ISE tools 14.5 v1.08|||N/A|
|XC7VX980T|N/A|N/A|Vivado tools 2013.1 v1.08 or ISE tools 14.5 v1.08|||N/A|



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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  16:_ **Virtex-7 T and XT Device Production Software and Speed Specification Release** _**(Cont’d)**_ 

|**Device**|**Speed Grade Designations**|**Speed Grade Designations**|**Speed Grade Designations**|**Speed Grade Designations**|**Speed Grade Designations**|**Speed Grade Designations**|
|---|---|---|---|---|---|---|
||**-3**|**-2G**|**-2**|**-2L**|**-1**|**-1M**|
|XC7VX1140T|N/A|Vivado tools 2013.1 v1.08||||N/A|
|XQ7V585T|N/A|N/A|Vivado tools 2013.1 v1.04 or ISE tools 14.5 v1.04||||
|XQ7VX330T|N/A|N/A|Vivado tools 2013.1 v1.04 or ISE tools 14.5 v1.04|||Vivado tools<br>2013.2 v1.05 or<br>ISE tools 14.6<br>v1.05|
|XQ7VX485T|N/A|N/A|Vivado tools 2013.1 v1.04 or ISE tools 14.5 v1.04||||
|XQ7VX690T|N/A|N/A|Vivado tools<br>2013.1 v1.04 or<br>ISE tools 14.5<br>v1.04|N/A|Vivado tools<br>2013.1 v1.04 or<br>ISE tools 14.5<br>v1.04|N/A|
|XQ7VX980T|N/A|N/A|N/A|Vivado tools 2013.1 v1.04 or<br>ISE tools 14.5 v1.04||N/A|



## **Performance Characteristics** 

This section provides the performance characteristics of some common functions and designs implemented in Virtex-7 T and XT devices. The numbers reported here are worst-case values; they have all been fully characterized. These values are subject to the same guidelines as the AC Switching Characteristics, page 13. In each table, the I/O bank type is either High Performance (HP) or High Range (HR). 

_Table  17:_ **Networking Applications Interface Performances** 

|_Table  17:_ **Networking Applications Interface Performances**||||||
|---|---|---|---|---|---|
|**Description**|**I/O Bank Type**|**Speed Grade**|||**Units**|
|||**-3**|**-2/-2L/-2G**|**-1/-1M**||
|SDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 8)|HR|710|710|625|Mb/s|
||HP|710|710|625|Mb/s|
|DDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 14)|HR|1250|1250|950|Mb/s|
||HP|1600|1400|1250|Mb/s|
|SDR LVDS receiver (SFI-4.1)(1)|HR|710|710|625|Mb/s|
||HP|710|710|625|Mb/s|
|DDR LVDS receiver (SPI-4.2)(1)|HR|1250|1250|950|Mb/s|
||HP|1600|1400|1250|Mb/s|



## **Notes:** 

1. LVDS receivers are typically bounded with certain applications where specific dynamic phase-alignment (DPA) algorithms dominate deterministic performance. 

Table 18 provides the maximum data rates for applicable memory standards using the Virtex-7 T and XT FPGAs memory PHY. The final performance of the memory interface is determined through a complete design implemented in the Vivado or ISE Design Suite, following guidelines in the _Zynq-7000 AP SoC and 7 Series Devices Memory Interface Solutions User Guide_ (UG586), electrical analysis, and characterization of the system. 

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_Table  18:_ **Maximum Physical Interface (PHY) Rate for Memory Interfaces IP available with the Memory Interface Generator[(1)(2)]** 

|**Generator(1)(2)**||||||||
|---|---|---|---|---|---|---|---|
|**Memory Standard**|**I/O Bank Type**|**VCCAUX_IO**|**Speed Grade**||||**Units**|
||||**-3**|**-2/-2L/-2G**|**-1**|**-1M**||
|**4:1 Memory Controllers**||||||||
|DDR3|HP|2.0V|1866(3)|1866(3)|1600|1066|Mb/s|
||HP|1.8V|1600|1333|1066|800||
||HR|N/A|1066|1066|800|800||
|DDR3L|HP|2.0V|1600|1600|1333|1066|Mb/s|
||HP|1.8V|1333|1066|800|800||
||HR|N/A|800|800|667|N/A||
|DDR2|HP|2.0V|800|800|800|667|Mb/s|
||HP|1.8V||||||
||HR|N/A||||533||
|RLDRAM III|HP|2.0V|800|667|667|550|MHz|
||HP|1.8V|550|500|450|400||
||HR|N/A|N/A|||||
|**2:1 Memory Controllers**||||||||
|DDR3|HP|2.0V|1066|1066|800|667|Mb/s|
||HP|1.8V||||||
||HR|N/A||||||
|DDR3L|HP|2.0V|1066|1066|800|667|Mb/s|
||HP|1.8V||||||
||HR|N/A|800|800|667|N/A||
|DDR2|HP|2.0V|800|800|800|667|Mb/s|
||HP|1.8V||||||
||HR|N/A||||533||
|QDR II+(4)|HP|2.0V|550|500|450|300|MHz|
||HP|1.8V||||||
||HR|N/A|500|450|400|300||
|RLDRAM II|HP|2.0V|533|500|450|400|MHz|
||HP|1.8V||||||
||HR|N/A||||||
|LPDDR2|HP|2.0V|667|667|667|533|Mb/s|
||HP|1.8V||||||
||HR|N/A||||||



## **Notes:** 

1. VREF tracking is required. For more information, see the _Zynq-7000 AP SoC and 7 Series Devices Memory Interface Solutions User Guide_ (UG586). 

2. When using the internal VREF, the maximum data rate is 800 Mb/s (400 MHz). 

3. For designs using 1866 Mb/s components, contact Xilinx Technical Support. 

4. The maximum QDRII+ performance specifications are for burst-length 4 (BL = 4) implementations. Burst length 2 (BL = 2) implementations are limited to 333 MHz for all speed grades and I/O bank types. 

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## **IOB Pad Input/Output/3-State** 

Table 19 (3.3V high-range IOB (HR)) and Table 20 (1.8V high-performance IOB (HP)) summarizes the values of standardspecific data input delay adjustments, output delays terminating at pads (based on standard) and 3-state delays. 

- TIOPI is described as the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The delay varies depending on the capability of the SelectIO input buffer. 

- TIOOP is described as the delay from the O pin to the IOB pad through the output buffer of an IOB pad. The delay varies depending on the capability of the SelectIO output buffer. 

- TIOTP is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is disabled. The delay varies depending on the SelectIO capability of the output buffer. In HP I/O banks, the internal DCI termination turn-on time is always faster than TIOTP when the DCITERMDISABLE pin is used. In HR I/O banks, the IN_TERM termination turn-on time is always faster than TIOTP when the INTERMDISABLE pin is used. 

_Table  19:_ **3.3V IOB High Range (HR) Switching Characteristics** 

|**I/O Standard**|**TIOPI**|**TIOPI**|**TIOPI**|**TIOPI**|**TIOOP**|**TIOOP**|**TIOOP**|**TIOOP**|**TIOTP**|**TIOTP**|**TIOTP**|**TIOTP**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||**Speed Grade**||||**Speed Grade**||||**Speed Grade**|||||
||**-3**|**-2/-2L/-2G**|**-1**|**-1M**|**-3**|**-2/-2L/-2G**|**-1**|**-1M**|**-3**|**-2/-2L/-2G**|**-1**|**-1M**||
|LVTTL_S4|1.31|1.42|1.64|1.64|3.77|3.90|4.00|4.00|3.52|3.67|3.86|3.86|ns|
|LVTTL_S8|1.31|1.42|1.64|1.64|3.50|3.64|3.73|3.73|3.26|3.40|3.60|3.60|ns|
|LVTTL_S12|1.31|1.42|1.64|1.64|3.49|3.62|3.72|3.72|3.24|3.39|3.58|3.58|ns|
|LVTTL_S16|1.31|1.42|1.64|1.64|3.03|3.17|3.26|3.26|2.79|2.93|3.13|3.13|ns|
|LVTTL_S24|1.31|1.42|1.64|1.64|3.25|3.39|3.48|3.48|3.01|3.15|3.35|3.35|ns|
|LVTTL_F4|1.31|1.42|1.64|1.64|3.22|3.36|3.45|3.45|2.98|3.12|3.32|3.32|ns|
|LVTTL_F8|1.31|1.42|1.64|1.64|2.71|2.84|2.93|2.93|2.46|2.61|2.80|2.80|ns|
|LVTTL_F12|1.31|1.42|1.64|1.64|2.69|2.82|2.92|2.92|2.44|2.59|2.79|2.79|ns|
|LVTTL_F16|1.31|1.42|1.64|1.64|2.57|2.85|3.15|3.15|2.33|2.61|3.02|3.02|ns|
|LVTTL_F24|1.31|1.42|1.64|1.64|2.41|2.64|2.89|3.04|2.16|2.41|2.76|2.91|ns|
|LVDS_25|0.64|0.68|0.80|0.87|1.36|1.47|1.55|1.55|1.11|1.24|1.41|1.41|ns|
|MINI_LVDS_25|0.68|0.70|0.79|0.87|1.36|1.47|1.55|1.55|1.11|1.24|1.41|1.41|ns|
|BLVDS_25|0.65|0.69|0.80|0.85|1.83|2.02|2.20|2.57|1.59|1.79|2.07|2.44|ns|
|RSDS_25 (point to point)|0.63|0.68|0.79|0.87|1.36|1.48|1.55|1.55|1.11|1.24|1.41|1.41|ns|
|PPDS_25|0.65|0.69|0.80|0.87|1.36|1.49|1.58|1.58|1.11|1.25|1.45|1.45|ns|
|TMDS_33|0.72|0.76|0.86|0.90|1.43|1.54|1.60|1.60|1.18|1.31|1.47|1.47|ns|
|PCI33_3|1.28|1.41|1.65|1.65|2.71|3.08|3.52|3.52|2.46|2.84|3.39|3.39|ns|
|HSUL_12_S|0.63|0.64|0.71|0.85|1.77|1.90|2.00|2.00|1.52|1.67|1.86|1.86|ns|
|HSUL_12_F|0.63|0.64|0.71|0.85|1.26|1.40|1.50|1.50|1.01|1.16|1.37|1.37|ns|
|DIFF_HSUL_12_S|0.58|0.61|0.70|0.84|1.55|1.68|1.78|1.78|1.30|1.45|1.65|1.65|ns|
|DIFF_HSUL_12_F|0.58|0.61|0.70|0.84|1.16|1.28|1.35|1.35|0.92|1.04|1.21|1.21|ns|
|MOBILE_DDR_S|0.64|0.66|0.74|0.74|2.58|2.91|3.31|3.31|2.33|2.68|3.17|3.17|ns|
|MOBILE_DDR_F|0.64|0.66|0.74|0.74|1.91|2.13|2.36|2.36|1.66|1.89|2.23|2.23|ns|
|DIFF_MOBILE_DDR_S|0.63|0.66|0.75|0.75|2.51|2.84|3.24|3.24|2.26|2.61|3.10|3.10|ns|
|DIFF_MOBILE_DDR_F|0.63|0.66|0.75|0.75|1.89|2.11|2.34|2.34|1.64|1.88|2.21|2.21|ns|
|HSTL_I_S|0.61|0.64|0.73|0.84|1.55|1.69|1.80|1.80|1.30|1.46|1.67|1.67|ns|
|HSTL_II_S|0.61|0.64|0.73|0.84|1.21|1.34|1.43|1.61|0.96|1.11|1.30|1.47|ns|
|HSTL_I_18_S|0.64|0.67|0.76|0.85|1.28|1.39|1.45|1.45|1.04|1.16|1.31|1.32|ns|
|HSTL_II_18_S|0.64|0.67|0.76|0.85|1.18|1.31|1.40|1.57|0.93|1.08|1.27|1.44|ns|



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_Table  19:_ **3.3V IOB High Range (HR) Switching Characteristics** _**(Cont’d)**_ 

|**I/O Standard**|**TIOPI**|**TIOPI**|**TIOPI**|**TIOPI**|**TIOOP**|**TIOOP**|**TIOOP**|**TIOOP**|**TIOTP**|**TIOTP**|**TIOTP**|**TIOTP**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||**Speed Grade**||||**Speed Grade**||||**Speed Grade**|||||
||**-3**|**-2/-2L/-2G**|**-1**|**-1M**|**-3**|**-2/-2L/-2G**|**-1**|**-1M**|**-3**|**-2/-2L/-2G**|**-1**|**-1M**||
|DIFF_HSTL_I_S|0.63|0.67|0.77|0.84|1.42|1.54|1.61|1.78|1.17|1.31|1.48|1.65|ns|
|DIFF_HSTL_II_S|0.63|0.67|0.77|0.84|1.15|1.24|1.27|1.61|0.91|1.01|1.14|1.47|ns|
|DIFF_HSTL_I_18_S|0.65|0.69|0.78|0.84|1.27|1.38|1.43|1.45|1.03|1.14|1.30|1.32|ns|
|DIFF_HSTL_II_18_S|0.65|0.69|0.78|0.85|1.14|1.23|1.26|1.57|0.90|1.00|1.13|1.44|ns|
|HSTL_I_F|0.61|0.64|0.73|0.84|1.10|1.19|1.23|1.31|0.85|0.96|1.10|1.18|ns|
|HSTL_II_F|0.61|0.64|0.73|0.84|1.05|1.18|1.28|1.31|0.80|0.95|1.15|1.18|ns|
|HSTL_I_18_F|0.64|0.67|0.76|0.85|1.05|1.18|1.28|1.36|0.80|0.95|1.15|1.22|ns|
|HSTL_II_18_F|0.64|0.67|0.76|0.85|1.03|1.14|1.23|1.32|0.78|0.90|1.10|1.19|ns|
|DIFF_HSTL_I_F|0.63|0.67|0.77|0.84|1.09|1.18|1.22|1.31|0.84|0.95|1.09|1.18|ns|
|DIFF_HSTL_II_F|0.63|0.67|0.77|0.84|1.02|1.11|1.14|1.31|0.77|0.88|1.01|1.18|ns|
|DIFF_HSTL_I_18_F|0.65|0.69|0.78|0.84|1.08|1.17|1.21|1.36|0.83|0.94|1.07|1.22|ns|
|DIFF_HSTL_II_18_F|0.65|0.69|0.78|0.85|1.01|1.10|1.13|1.32|0.76|0.87|1.00|1.19|ns|
|LVCMOS33_S4|1.31|1.40|1.60|1.60|3.77|3.90|4.00|4.00|3.52|3.67|3.86|3.86|ns|
|LVCMOS33_S8|1.31|1.40|1.60|1.60|3.49|3.62|3.72|3.72|3.24|3.39|3.58|3.58|ns|
|LVCMOS33_S12|1.31|1.40|1.60|1.60|3.05|3.18|3.28|3.28|2.80|2.95|3.15|3.15|ns|
|LVCMOS33_S16|1.31|1.40|1.60|1.60|3.06|3.43|3.88|3.88|2.81|3.20|3.75|3.75|ns|
|LVCMOS33_F4|1.31|1.40|1.60|1.60|3.22|3.36|3.45|3.45|2.98|3.12|3.32|3.32|ns|
|LVCMOS33_F8|1.31|1.40|1.60|1.60|2.71|2.84|2.93|2.93|2.46|2.61|2.80|2.80|ns|
|LVCMOS33_F12|1.31|1.40|1.60|1.60|2.57|2.85|3.15|3.15|2.33|2.61|3.02|3.02|ns|
|LVCMOS33_F16|1.31|1.40|1.60|1.60|2.44|2.69|2.96|2.96|2.19|2.45|2.82|2.82|ns|
|LVCMOS25_S4|1.08|1.16|1.32|1.35|3.08|3.22|3.31|3.31|2.84|2.98|3.18|3.18|ns|
|LVCMOS25_S8|1.08|1.16|1.32|1.35|2.85|2.98|3.07|3.08|2.60|2.75|2.94|2.94|ns|
|LVCMOS25_S12|1.08|1.16|1.32|1.35|2.44|2.57|2.67|2.67|2.19|2.34|2.54|2.54|ns|
|LVCMOS25_S16|1.08|1.16|1.32|1.35|2.79|2.92|3.01|3.01|2.54|2.68|2.88|2.88|ns|
|LVCMOS25_F4|1.08|1.16|1.32|1.35|2.71|2.84|2.93|2.93|2.46|2.61|2.80|2.80|ns|
|LVCMOS25_F8|1.08|1.16|1.32|1.35|2.14|2.28|2.37|2.37|1.90|2.04|2.24|2.24|ns|
|LVCMOS25_F12|1.08|1.16|1.32|1.35|2.15|2.29|2.52|2.52|1.91|2.05|2.38|2.38|ns|
|LVCMOS25_F16|1.08|1.16|1.32|1.35|1.92|2.17|2.45|2.45|1.67|1.94|2.32|2.32|ns|
|LVCMOS18_S4|0.64|0.66|0.74|0.95|1.55|1.68|1.78|1.78|1.30|1.45|1.65|1.65|ns|
|LVCMOS18_S8|0.64|0.66|0.74|0.95|2.14|2.28|2.37|2.37|1.90|2.04|2.24|2.24|ns|
|LVCMOS18_S12|0.64|0.66|0.74|0.95|2.14|2.28|2.37|2.37|1.90|2.04|2.24|2.24|ns|
|LVCMOS18_S16|0.64|0.66|0.74|0.95|1.49|1.62|1.72|1.72|1.24|1.39|1.58|1.58|ns|
|LVCMOS18_S24|0.64|0.66|0.74|0.95|1.74|1.92|2.08|2.22|1.50|1.69|1.95|2.08|ns|
|LVCMOS18_F4|0.64|0.66|0.74|0.95|1.38|1.51|1.61|1.64|1.13|1.28|1.47|1.50|ns|
|LVCMOS18_F8|0.64|0.66|0.74|0.95|1.64|1.78|1.87|1.87|1.40|1.54|1.74|1.74|ns|
|LVCMOS18_F12|0.64|0.66|0.74|0.95|1.64|1.78|1.87|1.87|1.40|1.54|1.74|1.74|ns|
|LVCMOS18_F16|0.64|0.66|0.74|0.95|1.52|1.68|1.81|1.81|1.28|1.45|1.68|1.68|ns|
|LVCMOS18_F24|0.64|0.66|0.74|0.95|1.34|1.46|1.55|2.09|1.09|1.23|1.42|1.96|ns|
|LVCMOS15_S4|0.66|0.69|0.81|0.93|1.86|2.00|2.09|2.09|1.62|1.76|1.96|1.96|ns|
|LVCMOS15_S8|0.66|0.69|0.81|0.93|2.05|2.18|2.28|2.28|1.80|1.95|2.14|2.15|ns|



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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  19:_ **3.3V IOB High Range (HR) Switching Characteristics** _**(Cont’d)**_ 

|**I/O Standard**|**TIOPI**|**TIOPI**|**TIOPI**|**TIOPI**|**TIOOP**|**TIOOP**|**TIOOP**|**TIOOP**|**TIOTP**|**TIOTP**|**TIOTP**|**TIOTP**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||**Speed Grade**||||**Speed Grade**||||**Speed Grade**|||||
||**-3**|**-2/-2L/-2G**|**-1**|**-1M**|**-3**|**-2/-2L/-2G**|**-1**|**-1M**|**-3**|**-2/-2L/-2G**|**-1**|**-1M**||
|LVCMOS15_S12|0.66|0.69|0.81|0.93|1.83|2.03|2.23|2.23|1.59|1.80|2.10|2.10|ns|
|LVCMOS15_S16|0.66|0.69|0.81|0.93|1.76|1.95|2.13|2.13|1.52|1.72|1.99|1.99|ns|
|LVCMOS15_F4|0.66|0.69|0.81|0.93|1.63|1.76|1.86|1.86|1.38|1.53|1.72|1.72|ns|
|LVCMOS15_F8|0.66|0.69|0.81|0.93|1.79|1.99|2.18|2.18|1.55|1.76|2.05|2.05|ns|
|LVCMOS15_F12|0.66|0.69|0.81|0.93|1.40|1.54|1.65|1.65|1.15|1.31|1.52|1.52|ns|
|LVCMOS15_F16|0.66|0.69|0.81|0.93|1.37|1.51|1.61|1.89|1.13|1.27|1.48|1.75|ns|
|LVCMOS12_S4|0.88|0.91|1.00|1.17|2.53|2.67|2.76|2.76|2.29|2.43|2.63|2.63|ns|
|LVCMOS12_S8|0.88|0.91|1.00|1.17|2.05|2.18|2.28|2.28|1.80|1.95|2.14|2.15|ns|
|LVCMOS12_S12|0.88|0.91|1.00|1.17|1.75|1.89|1.98|1.98|1.51|1.65|1.85|1.85|ns|
|LVCMOS12_F4|0.88|0.91|1.00|1.17|1.94|2.07|2.17|2.17|1.69|1.84|2.04|2.04|ns|
|LVCMOS12_F8|0.88|0.91|1.00|1.17|1.50|1.64|1.73|1.73|1.26|1.40|1.60|1.60|ns|
|LVCMOS12_F12|0.88|0.91|1.00|1.17|1.54|1.71|1.87|1.87|1.29|1.48|1.74|1.74|ns|
|SSTL135_S|0.61|0.64|0.73|0.85|1.27|1.40|1.50|1.53|1.02|1.17|1.36|1.40|ns|
|SSTL15_S|0.61|0.64|0.73|0.73|1.24|1.37|1.47|1.53|0.99|1.14|1.33|1.40|ns|
|SSTL18_I_S|0.64|0.67|0.76|0.84|1.59|1.74|1.85|1.85|1.34|1.50|1.72|1.72|ns|
|SSTL18_II_S|0.64|0.67|0.76|0.85|1.27|1.40|1.50|1.50|1.02|1.17|1.36|1.36|ns|
|DIFF_SSTL135_S|0.59|0.61|0.73|0.85|1.27|1.40|1.50|1.53|1.02|1.17|1.36|1.40|ns|
|DIFF_SSTL15_S|0.63|0.67|0.77|0.85|1.24|1.37|1.47|1.53|0.99|1.14|1.33|1.40|ns|
|DIFF_SSTL18_I_S|0.65|0.69|0.78|0.85|1.50|1.63|1.72|1.82|1.26|1.40|1.59|1.69|ns|
|DIFF_SSTL18_II_S|0.65|0.69|0.78|0.85|1.13|1.22|1.25|1.50|0.88|0.99|1.12|1.36|ns|
|SSTL135_F|0.61|0.64|0.73|0.85|1.04|1.17|1.26|1.31|0.79|0.93|1.13|1.18|ns|
|SSTL15_F|0.61|0.64|0.73|0.73|1.04|1.17|1.26|1.26|0.79|0.93|1.13|1.13|ns|
|SSTL18_I_F|0.64|0.67|0.76|0.84|1.12|1.22|1.26|1.34|0.88|0.99|1.13|1.21|ns|
|SSTL18_II_F|0.64|0.67|0.76|0.85|1.05|1.18|1.28|1.32|0.80|0.95|1.15|1.19|ns|
|DIFF_SSTL135_F|0.59|0.61|0.73|0.85|1.04|1.17|1.26|1.31|0.79|0.93|1.13|1.18|ns|
|DIFF_SSTL15_F|0.63|0.67|0.77|0.85|1.04|1.17|1.26|1.26|0.79|0.93|1.13|1.13|ns|
|DIFF_SSTL18_I_F|0.65|0.69|0.78|0.85|1.10|1.19|1.23|1.34|0.85|0.96|1.10|1.21|ns|
|DIFF_SSTL18_II_F|0.65|0.69|0.78|0.85|1.02|1.10|1.14|1.32|0.77|0.87|1.00|1.19|ns|



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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  20:_ **1.8V IOB High Performance (HP) Switching Characteristics** 

|**I/O Standard**|**TIOPI**|**TIOPI**|**TIOPI**|**TIOPI**|**TIOOP**|**TIOOP**|**TIOOP**|**TIOOP**|**TIOTP**|**TIOTP**|**TIOTP**|**TIOTP**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||**Speed Grade**||||**Speed Grade**||||**Speed Grade**|||||
||**-3**|**-2/-2L/-2G**|**-1**|**-1M**|**-3**|**-2/-2L/-2G**|**-1**|**-1M**|**-3**|**-2/-2L/-2G**|**-1**|**-1M**||
|LVDS|0.75|0.79|0.92|0.96|1.05|1.17|1.24|1.26|0.88|1.01|1.08|1.10|ns|
|HSUL_12_S|0.69|0.72|0.82|0.98|1.65|1.84|2.05|2.05|1.48|1.68|1.89|1.89|ns|
|HSUL_12_F|0.69|0.72|0.82|0.98|1.39|1.54|1.68|1.68|1.22|1.38|1.52|1.52|ns|
|DIFF_HSUL_12_S|0.69|0.72|0.82|0.98|1.65|1.84|2.05|2.05|1.48|1.68|1.89|1.89|ns|
|DIFF_HSUL_12_F|0.69|0.72|0.82|0.98|1.39|1.54|1.68|1.68|1.22|1.38|1.52|1.52|ns|
|DIFF_HSUL_12_DCI_S|0.69|0.72|0.82|0.82|1.78|1.91|2.05|2.05|1.61|1.76|1.89|1.89|ns|
|DIFF_HSUL_12_DCI_F|0.69|0.72|0.82|0.82|1.56|1.67|1.76|1.76|1.39|1.51|1.60|1.60|ns|
|HSTL_I_S|0.68|0.72|0.82|0.90|1.15|1.28|1.38|1.38|0.98|1.12|1.22|1.22|ns|
|HSTL_II_S|0.68|0.72|0.82|0.90|1.05|1.17|1.26|1.27|0.88|1.01|1.10|1.11|ns|
|HSTL_I_18_S|0.70|0.72|0.82|0.95|1.12|1.24|1.34|1.34|0.95|1.08|1.18|1.18|ns|
|HSTL_II_18_S|0.70|0.72|0.82|0.90|1.06|1.18|1.26|1.27|0.89|1.02|1.10|1.11|ns|
|HSTL_I_12_S|0.68|0.72|0.82|0.96|1.14|1.27|1.37|1.37|0.97|1.11|1.21|1.21|ns|
|HSTL_I_DCI_S|0.68|0.72|0.82|0.90|1.11|1.23|1.33|1.33|0.94|1.07|1.17|1.17|ns|
|HSTL_II_DCI_S|0.68|0.72|0.82|0.85|1.05|1.17|1.26|1.26|0.88|1.01|1.10|1.10|ns|
|HSTL_II_T_DCI_S|0.70|0.72|0.82|0.82|1.15|1.28|1.38|1.38|0.98|1.12|1.22|1.22|ns|
|HSTL_I_DCI_18_S|0.70|0.72|0.82|0.90|1.11|1.23|1.33|1.33|0.94|1.07|1.17|1.17|ns|
|HSTL_II_DCI_18_S|0.70|0.72|0.82|0.82|1.05|1.16|1.24|1.24|0.88|1.00|1.08|1.08|ns|
|HSTL_II _T_DCI_18_S|0.70|0.72|0.82|0.84|1.11|1.23|1.33|1.34|0.94|1.07|1.17|1.18|ns|
|DIFF_HSTL_I_S|0.75|0.79|0.92|1.02|1.15|1.28|1.38|1.38|0.98|1.12|1.22|1.22|ns|
|DIFF_HSTL_II_S|0.75|0.79|0.92|1.02|1.05|1.17|1.26|1.32|0.88|1.01|1.10|1.16|ns|
|DIFF_HSTL_I_DCI_S|0.75|0.79|0.92|0.92|1.15|1.28|1.38|1.38|0.98|1.12|1.22|1.22|ns|
|DIFF_HSTL_II_DCI_S|0.75|0.79|0.92|0.92|1.05|1.17|1.26|1.26|0.88|1.01|1.10|1.10|ns|
|DIFF_HSTL_I_18_S|0.75|0.79|0.92|0.98|1.12|1.24|1.34|1.34|0.95|1.08|1.18|1.18|ns|
|DIFF_HSTL_II_18_S|0.75|0.79|0.92|0.99|1.06|1.18|1.26|1.32|0.89|1.02|1.10|1.16|ns|
|DIFF_HSTL_I_DCI_18_S|0.75|0.79|0.92|0.92|1.11|1.23|1.33|1.33|0.94|1.07|1.17|1.17|ns|
|DIFF_HSTL_II_DCI_18_S|0.75|0.79|0.92|0.93|1.05|1.16|1.24|1.26|0.88|1.00|1.08|1.10|ns|
|DIFF_HSTL_II _T_DCI_18_S|0.75|0.79|0.92|0.92|1.11|1.23|1.33|1.33|0.94|1.07|1.17|1.17|ns|
|HSTL_I_F|0.68|0.72|0.82|0.90|1.02|1.14|1.22|1.22|0.85|0.98|1.06|1.06|ns|
|HSTL_II_F|0.68|0.72|0.82|0.90|0.97|1.08|1.15|1.15|0.80|0.92|0.99|0.99|ns|
|HSTL_I_18_F|0.70|0.72|0.82|0.95|1.04|1.16|1.24|1.24|0.87|1.00|1.08|1.08|ns|
|HSTL_II_18_F|0.70|0.72|0.82|0.90|0.98|1.09|1.16|1.20|0.81|0.94|1.00|1.03|ns|
|HSTL_I_12_F|0.68|0.72|0.82|0.96|1.02|1.13|1.21|1.21|0.85|0.97|1.05|1.05|ns|
|HSTL_I_DCI_F|0.68|0.72|0.82|0.90|1.04|1.16|1.24|1.24|0.87|1.00|1.08|1.08|ns|
|HSTL_II_DCI_F|0.68|0.72|0.82|0.85|0.97|1.08|1.15|1.15|0.80|0.92|0.99|0.99|ns|
|HSTL_II_T_DCI_F|0.70|0.72|0.82|0.82|1.02|1.14|1.22|1.22|0.85|0.98|1.06|1.06|ns|
|HSTL_I_DCI_18_F|0.70|0.72|0.82|0.90|1.04|1.16|1.24|1.24|0.87|1.00|1.08|1.08|ns|
|HSTL_II_DCI_18_F|0.70|0.72|0.82|0.82|0.98|1.09|1.16|1.16|0.81|0.93|1.00|1.00|ns|
|HSTL_II _T_DCI_18_F|0.70|0.72|0.82|0.84|1.04|1.16|1.24|1.24|0.87|1.00|1.08|1.08|ns|
|DIFF_HSTL_I_F|0.75|0.79|0.92|1.02|1.02|1.14|1.22|1.22|0.85|0.98|1.06|1.06|ns|



DS183 (v1.28) March 13, 2019 **Product Specification** 

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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  20:_ **1.8V IOB High Performance (HP) Switching Characteristics** _**(Cont’d)**_ 

|**I/O Standard**|**TIOPI**|**TIOPI**|**TIOPI**|**TIOPI**|**TIOOP**|**TIOOP**|**TIOOP**|**TIOOP**|**TIOTP**|**TIOTP**|**TIOTP**|**TIOTP**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||**Speed Grade**||||**Speed Grade**||||**Speed Grade**|||||
||**-3**|**-2/-2L/-2G**|**-1**|**-1M**|**-3**|**-2/-2L/-2G**|**-1**|**-1M**|**-3**|**-2/-2L/-2G**|**-1**|**-1M**||
|DIFF_HSTL_II_F|0.75|0.79|0.92|1.02|0.97|1.08|1.15|1.20|0.80|0.92|0.99|1.03|ns|
|DIFF_HSTL_I_DCI_F|0.75|0.79|0.92|0.92|1.02|1.14|1.22|1.22|0.85|0.98|1.06|1.06|ns|
|DIFF_HSTL_II_DCI_F|0.75|0.79|0.92|0.92|0.97|1.08|1.15|1.15|0.80|0.92|0.99|0.99|ns|
|DIFF_HSTL_I_18_F|0.75|0.79|0.92|0.98|1.04|1.16|1.24|1.24|0.87|1.00|1.08|1.08|ns|
|DIFF_HSTL_II_18_F|0.75|0.79|0.92|0.99|0.98|1.09|1.16|1.24|0.81|0.94|1.00|1.08|ns|
|DIFF_HSTL_I_DCI_18_F|0.75|0.79|0.92|0.92|1.04|1.16|1.24|1.24|0.87|1.00|1.08|1.08|ns|
|DIFF_HSTL_II_DCI_18_F|0.75|0.79|0.92|0.93|0.98|1.09|1.16|1.18|0.81|0.93|1.00|1.02|ns|
|DIFF_HSTL_II _T_DCI_18_F|0.75|0.79|0.92|0.92|1.04|1.16|1.24|1.24|0.87|1.00|1.08|1.08|ns|
|LVCMOS18_S2|0.47|0.50|0.60|0.90|3.95|4.28|4.85|4.85|3.78|4.13|4.69|4.69|ns|
|LVCMOS18_S4|0.47|0.50|0.60|0.90|2.67|2.98|3.43|3.43|2.50|2.82|3.27|3.27|ns|
|LVCMOS18_S6|0.47|0.50|0.60|0.90|2.14|2.38|2.72|2.72|1.97|2.22|2.56|2.56|ns|
|LVCMOS18_S8|0.47|0.50|0.60|0.90|1.98|2.21|2.52|2.52|1.81|2.05|2.36|2.36|ns|
|LVCMOS18_S12|0.47|0.50|0.60|0.90|1.70|1.91|2.17|2.17|1.53|1.75|2.01|2.01|ns|
|LVCMOS18_S16|0.47|0.50|0.60|0.90|1.57|1.75|1.97|1.97|1.40|1.59|1.81|1.81|ns|
|LVCMOS18_F2|0.47|0.50|0.60|0.90|3.50|3.87|4.48|4.48|3.33|3.71|4.32|4.32|ns|
|LVCMOS18_F4|0.47|0.50|0.60|0.90|2.23|2.50|2.87|2.87|2.06|2.34|2.71|2.71|ns|
|LVCMOS18_F6|0.47|0.50|0.60|0.90|1.80|2.00|2.26|2.26|1.63|1.84|2.09|2.09|ns|
|LVCMOS18_F8|0.47|0.50|0.60|0.90|1.46|1.72|2.04|2.04|1.29|1.56|1.88|1.88|ns|
|LVCMOS18_F12|0.47|0.50|0.60|0.90|1.26|1.40|1.53|1.53|1.09|1.24|1.37|1.37|ns|
|LVCMOS18_F16|0.47|0.50|0.60|0.90|1.19|1.33|1.44|1.66|1.02|1.17|1.28|1.50|ns|
|LVCMOS15_S2|0.59|0.62|0.73|0.88|3.55|3.89|4.45|4.45|3.38|3.73|4.29|4.29|ns|
|LVCMOS15_S4|0.59|0.62|0.73|0.88|2.45|2.70|3.06|3.06|2.28|2.54|2.90|2.90|ns|
|LVCMOS15_S6|0.59|0.62|0.73|0.88|2.24|2.51|2.88|2.88|2.07|2.35|2.72|2.72|ns|
|LVCMOS15_S8|0.59|0.62|0.73|0.88|1.91|2.16|2.49|2.49|1.74|2.00|2.32|2.32|ns|
|LVCMOS15_S12|0.59|0.62|0.73|0.88|1.77|1.98|2.23|2.23|1.60|1.82|2.07|2.07|ns|
|LVCMOS15_S16|0.59|0.62|0.73|0.88|1.62|1.81|2.02|2.02|1.45|1.65|1.86|1.86|ns|
|LVCMOS15_F2|0.59|0.62|0.73|0.88|3.38|3.69|4.18|4.18|3.21|3.53|4.02|4.02|ns|
|LVCMOS15_F4|0.59|0.62|0.73|0.88|2.04|2.21|2.44|2.44|1.87|2.06|2.27|2.27|ns|
|LVCMOS15_F6|0.59|0.62|0.73|0.88|1.47|1.74|2.09|2.09|1.30|1.58|1.93|1.93|ns|
|LVCMOS15_F8|0.59|0.62|0.73|0.88|1.31|1.46|1.61|1.61|1.14|1.30|1.45|1.45|ns|
|LVCMOS15_F12|0.59|0.62|0.73|0.88|1.21|1.34|1.45|1.45|1.04|1.18|1.29|1.29|ns|
|LVCMOS15_F16|0.59|0.62|0.73|0.88|1.18|1.31|1.41|1.68|1.01|1.15|1.25|1.52|ns|
|LVCMOS12_S2|0.64|0.67|0.78|1.04|3.38|3.80|4.48|4.48|3.21|3.64|4.31|4.31|ns|
|LVCMOS12_S4|0.64|0.67|0.78|1.04|2.62|2.94|3.43|3.43|2.45|2.78|3.27|3.27|ns|
|LVCMOS12_S6|0.64|0.67|0.78|1.04|2.05|2.33|2.72|2.72|1.88|2.17|2.56|2.56|ns|
|LVCMOS12_S8|0.64|0.67|0.78|1.04|1.94|2.18|2.51|2.51|1.77|2.02|2.34|2.34|ns|
|LVCMOS12_F2|0.64|0.67|0.78|1.04|2.84|3.15|3.62|3.62|2.67|2.99|3.46|3.46|ns|
|LVCMOS12_F4|0.64|0.67|0.78|1.04|1.97|2.18|2.44|2.44|1.80|2.02|2.28|2.28|ns|
|LVCMOS12_F6|0.64|0.67|0.78|1.04|1.33|1.51|1.70|1.70|1.16|1.35|1.54|1.54|ns|
|LVCMOS12_F8|0.64|0.67|0.78|1.04|1.27|1.42|1.55|1.55|1.10|1.26|1.39|1.39|ns|



DS183 (v1.28) March 13, 2019 **Product Specification** 

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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  20:_ **1.8V IOB High Performance (HP) Switching Characteristics** _**(Cont’d)**_ 

|**I/O Standard**|**TIOPI**|**TIOPI**|**TIOPI**|**TIOPI**|**TIOOP**|**TIOOP**|**TIOOP**|**TIOOP**|**TIOTP**|**TIOTP**|**TIOTP**|**TIOTP**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||**Speed Grade**||||**Speed Grade**||||**Speed Grade**|||||
||**-3**|**-2/-2L/-2G**|**-1**|**-1M**|**-3**|**-2/-2L/-2G**|**-1**|**-1M**|**-3**|**-2/-2L/-2G**|**-1**|**-1M**||
|LVDCI_18|0.47|0.50|0.60|0.87|1.99|2.15|2.35|2.35|1.82|1.99|2.19|2.19|ns|
|LVDCI_15|0.59|0.62|0.73|0.92|1.98|2.23|2.58|2.58|1.81|2.07|2.41|2.41|ns|
|LVDCI_DV2_18|0.47|0.50|0.60|0.88|1.99|2.15|2.34|2.34|1.82|1.99|2.18|2.18|ns|
|LVDCI_DV2_15|0.59|0.62|0.73|0.88|1.98|2.23|2.58|2.58|1.81|2.07|2.41|2.41|ns|
|HSLVDCI_18|0.68|0.72|0.82|0.90|1.99|2.15|2.35|2.35|1.82|1.99|2.19|2.19|ns|
|HSLVDCI_15|0.68|0.72|0.82|0.93|1.98|2.23|2.58|2.58|1.81|2.07|2.41|2.41|ns|
|SSTL18_I_S|0.68|0.72|0.82|0.95|1.02|1.15|1.24|1.24|0.85|0.99|1.08|1.08|ns|
|SSTL18_II_S|0.68|0.72|0.82|1.01|1.17|1.29|1.37|1.38|1.00|1.13|1.21|1.22|ns|
|SSTL18_I_DCI_S|0.68|0.72|0.82|0.87|0.92|1.06|1.17|1.18|0.75|0.90|1.01|1.02|ns|
|SSTL18_II_DCI_S|0.68|0.72|0.82|0.82|0.88|0.98|1.08|1.12|0.71|0.83|0.92|0.96|ns|
|SSTL18_II_T_DCI_S|0.68|0.72|0.82|0.98|0.92|1.06|1.17|1.18|0.75|0.90|1.01|1.02|ns|
|SSTL15_S|0.68|0.72|0.82|0.82|0.94|1.06|1.15|1.16|0.77|0.91|0.99|1.00|ns|
|SSTL15_DCI_S|0.68|0.72|0.82|0.90|0.94|1.06|1.15|1.16|0.77|0.90|0.99|1.00|ns|
|SSTL15_T_DCI_S|0.68|0.72|0.82|0.87|0.94|1.06|1.15|1.15|0.77|0.90|0.99|0.99|ns|
|SSTL135_S|0.69|0.72|0.82|0.93|0.97|1.10|1.19|1.20|0.80|0.94|1.03|1.03|ns|
|SSTL135_DCI_S|0.69|0.72|0.82|0.85|0.97|1.09|1.19|1.20|0.80|0.93|1.03|1.03|ns|
|SSTL135_T_DCI_S|0.69|0.72|0.82|0.93|0.97|1.09|1.19|1.20|0.80|0.93|1.03|1.03|ns|
|SSTL12_S|0.69|0.72|0.82|1.02|0.96|1.09|1.18|1.18|0.79|0.93|1.02|1.02|ns|
|SSTL12_DCI_S|0.69|0.72|0.82|0.90|1.03|1.17|1.27|1.27|0.86|1.01|1.11|1.11|ns|
|SSTL12_T_DCI_S|0.69|0.72|0.82|0.88|1.03|1.17|1.27|1.27|0.86|1.01|1.11|1.11|ns|
|DIFF_SSTL18_I_S|0.75|0.79|0.92|0.99|1.02|1.15|1.24|1.29|0.85|0.99|1.08|1.13|ns|
|DIFF_SSTL18_II_S|0.75|0.79|0.92|0.93|1.17|1.29|1.37|1.40|1.00|1.13|1.21|1.24|ns|
|DIFF_SSTL18_I_DCI_S|0.75|0.79|0.92|0.92|0.92|1.06|1.17|1.24|0.75|0.90|1.01|1.08|ns|
|DIFF_SSTL18_II_DCI_S|0.75|0.79|0.92|0.96|0.88|0.98|1.08|1.18|0.71|0.83|0.92|1.02|ns|
|DIFF_SSTL18_II_T_DCI_S|0.75|0.79|0.92|0.92|0.92|1.06|1.17|1.24|0.75|0.90|1.01|1.08|ns|
|DIFF_SSTL15_S|0.68|0.72|0.82|0.99|0.94|1.06|1.15|1.16|0.77|0.91|0.99|1.00|ns|
|DIFF_SSTL15_DCI_S|0.68|0.72|0.82|0.96|0.94|1.06|1.15|1.16|0.77|0.90|0.99|1.00|ns|
|DIFF_SSTL15_T_DCI_S|0.68|0.72|0.82|0.88|0.94|1.06|1.15|1.23|0.77|0.90|0.99|1.07|ns|
|DIFF_SSTL135_S|0.69|0.72|0.82|1.09|0.97|1.10|1.19|1.20|0.80|0.94|1.03|1.03|ns|
|DIFF_SSTL135_DCI_S|0.69|0.72|0.82|0.90|0.97|1.09|1.19|1.20|0.80|0.93|1.03|1.03|ns|
|DIFF_SSTL135_T_DCI_S|0.69|0.72|0.82|0.84|0.97|1.09|1.19|1.27|0.80|0.93|1.03|1.11|ns|
|DIFF_SSTL12_S|0.69|0.72|0.82|0.96|0.96|1.09|1.18|1.18|0.79|0.93|1.02|1.02|ns|
|DIFF_SSTL12_DCI_S|0.69|0.72|0.82|0.87|1.03|1.17|1.27|1.27|0.86|1.01|1.11|1.11|ns|
|DIFF_SSTL12_T_DCI_S|0.69|0.72|0.82|0.96|1.03|1.17|1.27|1.27|0.86|1.01|1.11|1.11|ns|
|SSTL18_I_F|0.68|0.72|0.82|0.95|0.94|1.06|1.15|1.15|0.77|0.91|0.99|0.99|ns|
|SSTL18_II_F|0.68|0.72|0.82|1.01|0.97|1.09|1.16|1.21|0.80|0.93|1.00|1.05|ns|
|SSTL18_I_DCI_F|0.68|0.72|0.82|0.87|0.89|1.02|1.10|1.15|0.72|0.86|0.94|0.99|ns|
|SSTL18_II_DCI_F|0.68|0.72|0.82|0.82|0.89|1.02|1.10|1.10|0.72|0.86|0.94|0.94|ns|
|SSTL18_II_T_DCI_F|0.68|0.72|0.82|0.98|0.89|1.02|1.10|1.15|0.72|0.86|0.94|0.99|ns|
|SSTL15_F|0.68|0.72|0.82|0.82|0.89|1.01|1.09|1.09|0.72|0.85|0.93|0.93|ns|



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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  20:_ **1.8V IOB High Performance (HP) Switching Characteristics** _**(Cont’d)**_ 

|**I/O Standard**|**TIOPI**|**TIOPI**|**TIOPI**|**TIOPI**|**TIOOP**|**TIOOP**|**TIOOP**|**TIOOP**|**TIOTP**|**TIOTP**|**TIOTP**|**TIOTP**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||**Speed Grade**||||**Speed Grade**||||**Speed Grade**|||||
||**-3**|**-2/-2L/-2G**|**-1**|**-1M**|**-3**|**-2/-2L/-2G**|**-1**|**-1M**|**-3**|**-2/-2L/-2G**|**-1**|**-1M**||
|SSTL15_DCI_F|0.68|0.72|0.82|0.90|0.89|1.01|1.09|1.12|0.72|0.85|0.93|0.96|ns|
|SSTL15_T_DCI_F|0.68|0.72|0.82|0.87|0.89|1.01|1.09|1.12|0.72|0.85|0.93|0.96|ns|
|SSTL135_F|0.69|0.72|0.82|0.93|0.88|1.00|1.08|1.12|0.71|0.85|0.92|0.96|ns|
|SSTL135_DCI_F|0.69|0.72|0.82|0.85|0.89|1.00|1.08|1.12|0.72|0.85|0.92|0.96|ns|
|SSTL135_T_DCI_F|0.69|0.72|0.82|0.93|0.89|1.00|1.08|1.12|0.72|0.85|0.92|0.96|ns|
|SSTL12_F|0.69|0.72|0.82|1.02|0.88|1.00|1.08|1.12|0.71|0.84|0.92|0.96|ns|
|SSTL12_DCI_F|0.69|0.72|0.82|0.90|0.91|1.03|1.11|1.11|0.74|0.88|0.95|0.95|ns|
|SSTL12_T_DCI_F|0.69|0.72|0.82|0.88|0.91|1.03|1.11|1.12|0.74|0.88|0.95|0.96|ns|
|DIFF_SSTL18_I_F|0.75|0.79|0.92|0.99|0.94|1.06|1.15|1.23|0.77|0.91|0.99|1.07|ns|
|DIFF_SSTL18_II_F|0.75|0.79|0.92|0.93|0.97|1.09|1.16|1.24|0.80|0.93|1.00|1.08|ns|
|DIFF_SSTL18_I_DCI_F|0.75|0.79|0.92|0.92|0.89|1.02|1.10|1.23|0.72|0.86|0.94|1.07|ns|
|DIFF_SSTL18_II_DCI_F|0.75|0.79|0.92|0.96|0.89|1.02|1.10|1.16|0.72|0.86|0.94|1.00|ns|
|DIFF_SSTL18_II_T_DCI_F|0.75|0.79|0.92|0.92|0.89|1.02|1.10|1.24|0.72|0.86|0.94|1.08|ns|
|DIFF_SSTL15_F|0.68|0.72|0.82|0.99|0.89|1.01|1.09|1.09|0.72|0.85|0.93|0.93|ns|
|DIFF_SSTL15_DCI_F|0.68|0.72|0.82|0.96|0.89|1.01|1.09|1.12|0.72|0.85|0.93|0.96|ns|
|DIFF_SSTL15_T_DCI_F|0.68|0.72|0.82|0.88|0.89|1.01|1.09|1.20|0.72|0.85|0.93|1.03|ns|
|DIFF_SSTL135_F|0.69|0.72|0.82|1.09|0.88|1.00|1.08|1.12|0.71|0.85|0.92|0.96|ns|
|DIFF_SSTL135_DCI_F|0.69|0.72|0.82|0.90|0.89|1.00|1.08|1.12|0.72|0.85|0.92|0.96|ns|
|DIFF_SSTL135_T_DCI_F|0.69|0.72|0.82|0.84|0.89|1.00|1.08|1.20|0.72|0.85|0.92|1.03|ns|
|DIFF_SSTL12_F|0.69|0.72|0.82|0.96|0.88|1.00|1.08|1.12|0.71|0.84|0.92|0.96|ns|
|DIFF_SSTL12_DCI_F|0.69|0.72|0.82|0.87|0.91|1.03|1.11|1.11|0.74|0.88|0.95|0.95|ns|
|DIFF_SSTL12_T_DCI_F|0.69|0.72|0.82|0.96|0.91|1.03|1.11|1.18|0.74|0.88|0.95|1.02|ns|



Table 21 specifies the values of TIOTPHZ and TIOIBUFDISABLE. TIOTPHZ is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is enabled (i.e., a high impedance state). TIOIBUFDISABLE is described as the IOB delay from IBUFDISABLE to O output. In HP I/O banks, the internal DCI termination turn-off time is always faster than TIOTPHZ when the DCITERMDISABLE pin is used. In HR I/O banks, the internal IN_TERM termination turn-off time is always faster than TIOTPHZ when the INTERMDISABLE pin is used. 

_Table  21:_ **IOB 3-state Output Switching Characteristics** 

|**Symbol**|**Description**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|
|||**-3**|**-2/-2L/-2G**|**-1**|**-1M**||
|TIOTPHZ|T input to pad high-impedance|0.76|0.86|0.99|0.99|ns|
|TIOIBUFDISABLE_HR|IBUF turn-on time from IBUFDISABLE to O output for<br>HR I/O banks|1.72|1.89|2.14|2.14|ns|
|TIOIBUFDISABLE_HP|IBUF turn-on time from IBUFDISABLE to O output for<br>HP I/O banks|1.31|1.46|1.76|1.76|ns|



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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

## **I/O Standard Adjustment Measurement Methodology** 

## **Input Delay Measurements** 

Table 22 shows the test setup parameters used for measuring input delay. 

_Table  22:_ **Input Delay Measurement Methodology** 

|**Description**|**I/O Standard Attribute**|**VL(1)(2)**|**VH(1)(2)**|**VMEAS**<br>**(1)(4)(6)**|**VREF**<br>**(1)(3)(5)**|
|---|---|---|---|---|---|
|LVCMOS, 1.2V|LVCMOS12|0.1|1.1|0.6|–|
|LVCMOS, 1.5V|LVCMOS15|0.1|1.4|0.75|–|
|LVCMOS, 1.8V|LVCMOS18|0.1|1.7|0.9|–|
|LVCMOS, 2.5V|LVCMOS25|0.1|2.4|1.25|–|
|LVCMOS, 3.3V|LVCMOS33|0.1|3.2|1.65|–|
|LVTTL, 3.3V|LVTTL|0.1|3.2|1.65|–|
|MOBILE_DDR, 1.8V|MOBILE_DDR|0.1|1.7|0.9|–|
|PCI33, 3.3V|PCI33_3|0.1|3.2|1.65|–|
|HSTL (High-Speed Transceiver Logic), Class I, 1.2V|HSTL_I_12|VREF– 0.5|VREF+ 0.5|VREF|0.60|
|HSTL, Class I & II, 1.5V|HSTL_I, HSTL_II|VREF– 0.65|VREF+ 0.65|VREF|0.75|
|HSTL, Class I & II, 1.8V|HSTL_I_18, HSTL_II_18|VREF– 0.8|VREF+ 0.8|VREF|0.90|
|HSUL (High-Speed Unterminated Logic), 1.2V|HSUL_12|VREF– 0.5|VREF+ 0.5|VREF|0.60|
|SSTL (Stub Terminated Transceiver Logic), 1.2V|SSTL12|VREF– 0.5|VREF+ 0.5|VREF|0.60|
|SSTL, 1.35V|SSTL135, SSTL135_R|VREF– 0.575|VREF+ 0.575|VREF|0.675|
|SSTL, 1.5V|SSTL15, SSTL15_R|VREF– 0.65|VREF+ 0.65|VREF|0.75|
|SSTL, Class I & II, 1.8V|SSTL18_I, SSTL18_II|VREF– 0.8|VREF+ 0.8|VREF|0.90|
|DIFF_MOBILE_DDR, 1.8V|DIFF_MOBILE_DDR|0.9 – 0.125|0.9 + 0.125|0(6)|–|
|DIFF_HSTL, Class I, 1.2V|DIFF_HSTL_I_12|0.6 – 0.125|0.6 + 0.125|0(6)|–|
|DIFF_HSTL, Class I & II,1.5V|DIFF_HSTL_I,<br>DIFF_HSTL_II|0.75 – 0.125|0.75 + 0.125|0(6)|–|
|DIFF_HSTL, Class I & II, 1.8V|DIFF_HSTL_I_18,<br>DIFF_HSTL_II_18|0.9 – 0.125|0.9 + 0.125|0(6)|–|
|DIFF_HSUL, 1.2V|DIFF_HSUL_12|0.6 – 0.125|0.6 + 0.125|0(6)|–|
|DIFF_SSTL, 1.2V|DIFF_SSTL12|0.6 – 0.125|0.6 + 0.125|0(6)|–|
|DIFF_SSTL135/DIFF_SSTL135_R, 1.35V|DIFF_SSTL135,<br>DIFF_SSTL135_R|0.675 – 0.125|0.675 + 0.125|0(6)|–|
|DIFF_SSTL15/DIFF_SSTL15_R, 1.5V|DIFF_SSTL15,<br>DIFF_SSTL15_R|0.75 – 0.125|0.75 + 0.125|0(6)|–|
|DIFF_SSTL18_I/DIFF_SSTL18_II, 1.8V|DIFF_SSTL18_I,<br>DIFF_SSTL18_II|0.9 – 0.125|0.9 + 0.125|0(6)|–|
|LVDS (Low-Voltage Differential Signaling), 1.8V|LVDS|0.9 – 0.125|0.9 + 0.125|0(6)|–|
|LVDS_25, 2.5V|LVDS_25|1.2 – 0.125|1.2 + 0.125|0(6)|–|
|BLVDS_25, 2.5V|BLVDS_25|1.25 – 0.125|1.25 + 0.125|0(6)|–|
|MINI_LVDS_25, 2.5V|MINI_LVDS_25|1.25 – 0.125|1.25 + 0.125|0(6)|–|
|PPDS_25|PPDS_25|1.25 – 0.125|1.25 + 0.125|0(6)|–|
|RSDS_25|RSDS_25|1.25 – 0.125|1.25 + 0.125|0(6)|–|



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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  22:_ **Input Delay Measurement Methodology** _**(Cont’d)**_ 

|**Description**|**I/O Standard Attribute**|**VL(1)(2)**|**VH(1)(2)**|**VMEAS**<br>**(1)(4)(6)**|**VREF**<br>**(1)(3)(5)**|
|---|---|---|---|---|---|
|TMDS_33|TMDS_33|3 – 0.125|3 + 0.125|0(6)|–|



## **Notes:** 

1. The input delay measurement methodology parameters for LVDCI are the same for LVCMOS standards of the same voltage. Input delay measurement methodology parameters for HSLVDCI are the same as for HSTL_II standards of the same voltage. Parameters for all other DCI standards are the same for the corresponding non-DCI standards. 

2. Input waveform switches between VLand VH. 

3. Measurements are made at typical, minimum, and maximum VREF values. Reported delays reflect worst case of these measurements. VREF values listed are typical. 

4. Input voltage level from which measurement starts. 

5. This is an input voltage reference that bears no relation to the VREF / VMEAS parameters found in IBIS models and/or noted in Figure 1. 

6. The value given is the differential input voltage. 

## **Output Delay Measurements** 

Output delays are measured with short output traces. Standard termination was used for all testing. The propagation delay of the trace is characterized separately and subtracted from the final measurement, and is therefore not included in the generalized test setups shown in Figure 1 and Figure 2. 

**==> picture [223 x 289] intentionally omitted <==**

**----- Start of picture text -----**<br>
VREF<br>FPGA Output RREF<br>VMEAS<br>(Voltage Level When Taking<br>Delay Measurement)<br>CREF<br>(Probe Capacitance)<br>DS183_06_010716<br>Figure 1: Single-Ended Test Setup<br>FPGA Output<br>+<br>CREF RREF VMEAS<br>–<br>DS183_07_010716<br>**----- End of picture text -----**<br>


_Figure 2:_ **Differential Test Setup** 

Parameters VREF, RREF, CREF, and VMEAS fully describe the test conditions for each I/O standard. The most accurate prediction of propagation delay in any given application can be obtained through IBIS simulation, using this method: 

1. Simulate the output driver of choice into the generalized test setup using values from Table 23. 

2. Record the time to VMEAS. 

3. Simulate the output driver of choice into the actual PCB trace and load using the appropriate IBIS model or capacitance value to represent the load. 

4. Record the time to VMEAS. 

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5. Compare the results of step 2 and step 4. The increase or decrease in delay yields the actual propagation delay of the PCB trace. 

_Table  23:_ **Output Delay Measurement Methodology** 

|**Description**|**I/O Standard Attribute**|**RREF**<br>**(**Ω**)**|**CREF**(1)<br>**(pF)**|**VMEAS**<br>**(V)**|**VREF**<br>**(V)**|
|---|---|---|---|---|---|
|LVCMOS, 1.2V|LVCMOS12|1M|0|0.6|0|
|LVCMOS/LVDCI/HSLVDCI, 1.5V|LVCMOS15, LVDCI_15, HSLVDCI_15|1M|0|0.75|0|
|LVCMOS/LVDCI/HSLVDCI, 1.8V|LVCMOS18, LVDCI_15, HSLVDCI_18|1M|0|0.9|0|
|LVCMOS, 2.5V|LVCMOS25|1M|0|1.25|0|
|LVCMOS, 3.3V|LVCMOS33|1M|0|1.65|0|
|LVTTL, 3.3V|LVTTL|1M|0|1.65|0|
|PCI33, 3.3V|PCI33_3|25|10|1.65|0|
|HSTL (High-Speed Transceiver Logic), Class I, 1.2V|HSTL_I_12|50|0|VREF|0.6|
|HSTL, Class I, 1.5V|HSTL_I|50|0|VREF|0.75|
|HSTL, Class II, 1.5V|HSTL_II|25|0|VREF|0.75|
|HSTL, Class I, 1.8V|HSTL_I_18|50|0|VREF|0.9|
|HSTL, Class II, 1.8V|HSTL_II_18|25|0|VREF|0.9|
|HSUL (High-Speed Unterminated Logic), 1.2V|HSUL_12|50|0|VREF|0.6|
|SSTL12, 1.2V|SSTL12|50|0|VREF|0.6|
|SSTL135/SSTL135_R, 1.35V|SSTL135, SSTL135_R|50|0|VREF|0.675|
|SSTL15/SSTL15_R, 1.5V|SSTL15, SSTL15_R|50|0|VREF|0.75|
|SSTL (Stub Series Terminated Logic),<br>Class I & Class II, 1.8V|SSTL18_I, SSTL18_II|50|0|VREF|0.9|
|DIFF_MOBILE_DDR, 1.8V|DIFF_MOBILE_DDR|50|0|VREF|0.9|
|DIFF_HSTL, Class I, 1.2V|DIFF_HSTL_I_12|50|0|VREF|0.6|
|DIFF_HSTL, Class I & II, 1.5V|DIFF_HSTL_I, DIFF_HSTL_II|50|0|VREF|0.75|
|DIFF_HSTL, Class I & II, 1.8V|DIFF_HSTL_I_18, DIFF_HSTL_II_18|50|0|VREF|0.9|
|DIFF_HSUL_12, 1.2V|DIFF_HSUL_12|50|0|VREF|0.6|
|DIFF_SSTL12, 1.2V|DIFF_SSTL12|50|0|VREF|0.6|
|DIFF_SSTL135/DIFF_SSTL135_R, 1.35V|DIFF_SSTL135, DIFF_SSTL135_R|50|0|VREF|0.675|
|DIFF_SSTL15/DIFF_SSTL15_R, 1.5V|DIFF_SSTL15, DIFF_SSTL15_R|50|0|VREF|0.75|
|DIFF_SSTL18, Class I & II, 1.8V|DIFF_SSTL18_I, DIFF_SSTL18_II|50|0|VREF|0.9|
|LVDS (Low-Voltage Differential Signaling), 1.8V|LVDS|100|0|0(2)|0|
|LVDS, 2.5V|LVDS_25|100|0|0(2)|0|
|BLVDS (Bus LVDS), 2.5V|BLVDS_25|100|0|0(2)|0|
|Mini LVDS, 2.5V|MINI_LVDS_25|100|0|0(2)|0|
|PPDS_25|PPDS_25|100|0|0(2)|0|
|RSDS_25|RSDS_25|100|0|0(2)|0|
|TMDS_33|TMDS_33|50|0|0(2)|3.3|



## **Notes:** 

1. CREF is the capacitance of the probe, nominally 0 pF. 

2. The value given is the differential output voltage. 

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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

## **Input/Output Logic Switching Characteristics** 

## _Table  24:_ **ILOGIC Switching Characteristics** 

|**Symbol**|**Description**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|
|||**-3**|**-2/-2L/-2G**|**-1**|**-1M**||
|**Setup/Hold**|||||||
|TICE1CK/TICKCE1|CE1 pin setup/hold with respect to CLK|0.42/0.00|0.48/0.00|0.67/0.00|0.67/0.00|ns|
|TISRCK/TICKSR|SR pin setup/hold with respect to CLK|0.53/0.01|0.61/0.01|0.99/0.01|0.99/0.01|ns|
|TIDOCKE2/TIOCKDE2|D pin setup/hold with respect to CLK without delay<br>(HP I/O banks only)|0.01/0.27|0.01/0.29|0.01/0.34|0.01/0.34|ns|
|TIDOCKDE2/TIOCKDDE2|DDLY pin setup/hold with respect to CLK<br>(using IDELAY) (HP I/O banks only)|0.01/0.27|0.02/0.29|0.02/0.34|0.02/0.34|ns|
|TIDOCKE3/TIOCKDE3|D pin setup/hold with respect to CLK without delay<br>(HR I/O banks only)|0.01/0.27|0.01/0.29|0.01/0.34|0.01/0.34|ns|
|TIDOCKDE3/TIOCKDDE3|DDLY pin setup/hold with respect to CLK<br>(using IDELAY) (HR I/O banks only)|0.01/0.27|0.02/0.29|0.02/0.34|0.02/0.34|ns|
|**Combinatorial**|||||||
|TIDIE2|D pin to O pin propagation delay, no delay<br>(HP I/O banks only)|0.09|0.10|0.12|0.12|ns|
|TIDIDE2|DDLY pin to O pin propagation delay (using IDELAY)<br>(HP I/O banks only)|0.10|0.11|0.13|0.13|ns|
|TIDIE3|D pin to O pin propagation delay, no delay<br>(HR I/O banks only)|0.09|0.10|0.12|0.12|ns|
|TIDIDE3|DDLY pin to O pin propagation delay (using IDELAY)<br>(HR I/O banks only)|0.10|0.11|0.13|0.13|ns|
|**Sequential Delays**|||||||
|TIDLOE2|D pin to Q1 pin using flip-flop as a latch without delay<br>(HP I/O banks only)|0.36|0.39|0.45|0.45|ns|
|TIDLODE2|DDLY pin to Q1 pin using flip-flop as a latch<br>(using IDELAY) (HP I/O banks only)|0.36|0.39|0.45|0.45|ns|
|TIDLOE3|D pin to Q1 pin using flip-flop as a latch without delay<br>(HR I/O banks only)|0.36|0.39|0.45|0.45|ns|
|TIDLODE3|DDLY pin to Q1 pin using flip-flop as a latch<br>(using IDELAY) (HR I/O banks only)|0.36|0.39|0.45|0.45|ns|
|TICKQ|CLK to Q outputs|0.47|0.50|0.58|0.58|ns|
|TRQ_ILOGICE2|SR pin to OQ/TQ out (HP I/O banks only)|0.84|0.94|1.16|1.16|ns|
|TGSRQ_ILOGICE2|Global set/reset to Q outputs (HP I/O banks only)|7.60|7.60|10.51|10.51|ns|
|TRQ_ILOGICE3|SR pin to OQ/TQ out (HR I/O banks only)|0.84|0.94|1.16|1.16|ns|
|TGSRQ_ILOGICE3|Global set/reset to Q outputs (HR I/O banks only)|7.60|7.60|10.51|10.51|ns|
|**Set/Reset**|||||||
|TRPW_ILOGICE2|Minimum pulse width, SR inputs (HP I/O banks only)|0.54|0.63|0.63|0.63|ns, Min|
|TRPW_ILOGICE3|Minimum pulse width, SR inputs (HR I/O banks only)|0.54|0.63|0.63|0.63|ns, Min|



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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

## _Table  25:_ **OLOGIC Switching Characteristics** 

|**Symbol**|**Description**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|
|||**-3**|**-2/-2L/-2G**|**-1**|**-1M**||
|**Setup/Hold**|||||||
|TODCK/TOCKD|D1/D2 pins setup/hold with respect to CLK|0.45/–0.13|0.50/–0.13|0.58/–0.13|0.58/–0.13|ns|
|TOOCECK/TOCKOCE|OCE pin setup/hold with respect to CLK|0.28/0.03|0.29/0.03|0.45/0.03|0.45/0.03|ns|
|TOSRCK/TOCKSR|SR pin setup/hold with respect to CLK|0.32/0.18|0.38/0.18|0.70/0.18|0.70/0.18|ns|
|TOTCK/TOCKT|T1/T2 pins setup/hold with respect to CLK|0.49/–0.16|0.56/–0.16|0.68/–0.16|0.68/–0.13|ns|
|TOTCECK/TOCKTCE|TCE pin setup/hold with respect to CLK|0.28/0.01|0.30/0.01|0.45/0.01|0.45/0.06|ns|
|**Combinatorial**|||||||
|TODQ|D1 to OQ out or T1 to TQ out|0.73|0.81|0.97|0.97|ns|
|**Sequential Delays**|||||||
|TOCKQ|CLK to OQ/TQ out|0.41|0.43|0.49|0.49|ns|
|TRQ_OLOGICE2|SR pin to OQ/TQ out (HP I/O banks only)|0.63|0.70|0.83|0.83|ns|
|TGSRQ_OLOGICE2|Global set/reset to Q outputs (HP I/O banks only)|7.60|7.60|10.51|10.51|ns|
|TRQ_OLOGICE3|SR pin to OQ/TQ out (HR I/O banks only)|0.63|0.70|0.83|0.83|ns|
|TGSRQ_OLOGICE3|Global set/reset to Q outputs (HR I/O banks only)|7.60|7.60|10.51|10.51|ns|
|**Set/Reset**|||||||
|TRPW_OLOGICE2|Minimum pulse width, SR inputs<br>(HP I/O banks only)|0.54|0.54|0.63|0.63|ns, Min|
|TRPW_OLOGICE3|Minimum pulse width, SR inputs<br>(HR I/O banks only)|0.54|0.54|0.63|0.63|ns, Min|



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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

## **Input Serializer/Deserializer Switching Characteristics** 

_Table  26:_ **ISERDES Switching Characteristics** 

|**Symbol**|**Description**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|
|||**-3**|**-2/-2L/-2G**|**-1**|**-1M**||
|**Setup/Hold for Control Lines**|||||||
|TISCCK_BITSLIP/<br>TISCKC_BITSLIP|BITSLIP pin setup/hold with respect to CLKDIV|0.01/0.12|0.02/0.13|0.02/0.15|0.02/0.15|ns|
|TISCCK_CE/ TISCKC_CE(2)|CE pin setup/hold with respect to CLK<br>(for CE1)|0.39/–0.02|0.44/–0.02|0.63/–0.02|0.63/–0.02|ns|
|TISCCK_CE2/<br>TISCKC_CE2(2)|CE pin setup/hold with respect to CLKDIV<br>(for CE2)|–0.12/0.29|–0.12/0.31|–0.12/0.35|–0.12/0.35|ns|
|**Setup/Hold for Data Lines**|||||||
|TISDCK_D/TISCKD_D|D pin setup/hold with respect to CLK|–0.02/0.11|–0.02/0.12|–0.02/0.15|–0.02/0.15|ns|
|TISDCK_DDLY/TISCKD_DDLY|DDLY pin setup/hold with respect to CLK<br>(using IDELAY)(1)|–0.02/0.11|–0.02/0.12|–0.02/0.15|–0.02/0.15|ns|
|TISDCK_D_DDR/<br>TISCKD_D_DDR|D pin setup/hold with respect to CLK at DDR<br>mode|–0.02/0.11|–0.02/0.12|–0.02/0.15|–0.02/0.15|ns|
|TISDCK_DDLY_DDR/<br>TISCKD_DDLY_DDR|D pin setup/hold with respect to CLK at DDR<br>mode (using IDELAY)(1)|0.11/0.11|0.12/0.12|0.15/0.15|0.15/0.15|ns|
|**Sequential Delays**|||||||
|TISCKO_Q|CLKDIV to out at Q pin|0.46|0.47|0.58|0.58|ns|
|**Propagation Delays**|||||||
|TISDO_DO|D input to DO output pin|0.09|0.10|0.12|0.12|ns|



## **Notes:** 

1. Recorded at 0 tap value. 

2. TISCCK_CE2 and TISCKC_CE2 are reported as TISCCK_CE/TISCKC_CE in the timing report. 

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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

## **Output Serializer/Deserializer Switching Characteristics** 

_Table  27:_ **OSERDES Switching Characteristics** 

|**Symbol**|**Description**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|
|||**-3**|**-2/-2L/-2G**|**-1**|**-1M**||
|**Setup/Hold**|||||||
|TOSDCK_D/TOSCKD_D|D input setup/hold with respect to CLKDIV|0.37/0.02|0.40/0.02|0.55/0.02|0.55/0.02|ns|
|TOSDCK_T/TOSCKD_T(1)|T input setup/hold with respect to CLK|0.49/–0.15|0.56/–0.15|0.68/–0.15|0.68/–0.15|ns|
|TOSDCK_T2/TOSCKD_T2(1)|T input setup/hold with respect to CLKDIV|0.27/–0.15|0.30/–0.15|0.34/–0.15|0.34/–0.15|ns|
|TOSCCK_OCE/TOSCKC_OCE|OCE input setup/hold with respect to CLK|0.28/0.03|0.29/0.03|0.45/0.03|0.45/0.03|ns|
|TOSCCK_S|SR (Reset) input setup with respect to<br>CLKDIV|0.41|0.46|0.75|0.75|ns|
|TOSCCK_TCE/TOSCKC_TCE|TCE input setup/hold with respect to CLK|0.28/0.01|0.30/0.01|0.45/0.01|0.45/0.01|ns|
|**Sequential Delays**|||||||
|TOSCKO_OQ|Clock to out from CLK to OQ|0.35|0.37|0.42|0.42|ns|
|TOSCKO_TQ|Clock to out from CLK to TQ|0.41|0.43|0.49|0.49|ns|
|**Combinatorial**|||||||
|TOSDO_TTQ|T input to TQ Out|0.73|0.81|0.97|0.97|ns|



## **Notes:** 

1. TOSDCK_T2 and TOSCKD_T2 are reported as TOSDCK_T/TOSCKD_T in the timing report. 

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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

## **Input/Output Delay Switching Characteristics** 

_Table  28:_ **Input/Output Delay Switching Characteristics** 

|**Symbol**|**Description**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|
|||**-3**|**-2/-2L/-2G**|**-1**|**-1M**||
|**IDELAYCTRL**|||||||
|TDLYCCO_RDY|Reset to ready for IDELAYCTRL|3.22|3.22|3.22|3.22|µs|
|FIDELAYCTRL_REF|Attribute REFCLK frequency = 200.0(1)|200|200|200|200|MHz|
||Attribute REFCLK frequency = 300.0(1)|300|300|N/A|N/A|MHz|
||Attribute REFCLK frequency = 400.0(1)|400|400|N/A|N/A|MHz|
|IDELAYCTRL_REF_PRECISION|REFCLK precision|±10|±10|±10|±10|MHz|
|TIDELAYCTRL_RPW|Minimum reset pulse width|52.00|52.00|52.00|52.00|ns|
|**IDELAY/ODELAY**|||||||
|TIDELAYRESOLUTION|IDELAY/ODELAY chain delay resolution|1/(32 x 2 x FREF)||||µs|
|TIDELAYPAT_JITand<br>TODELAYPAT_JIT|Pattern dependent period jitter in delay<br>chain for clock pattern.(2)|0|0|0|0|ps<br>per tap|
||Pattern dependent period jitter in delay<br>chain for random data pattern (PRBS<br>23)(3)|±5|±5|±5|±5|ps<br>per tap|
||Pattern dependent period jitter in delay<br>chain for random data pattern (PRBS<br>23)(4)|±9|±9|±9|±9|ps<br>per tap|
|TIDELAY_CLK_MAX/<br>TODELAY_CLK_MAX|Maximum frequency of CLK input to<br>IDELAY/ODELAY|800|800|710|710|MHz|
|TIDCCK_CE/ TIDCKC_CE|CE pin setup/hold with respect to C for<br>IDELAY|0.11/0.10|0.14/0.12|0.18/0.14|0.18/0.14|ns|
|TODCCK_CE/ TODCKC_CE|CE pin setup/hold with respect to C for<br>ODELAY|0.14/0.03|0.16/0.04|0.19/0.05|0.19/0.05|ns|
|TIDCCK_INC/ TIDCKC_INC|INC pin setup/hold with respect to C for<br>IDELAY|0.10/0.14|0.12/0.16|0.14/0.20|0.14/0.20|ns|
|TODCCK_INC/ TODCKC_INC|INC pin setup/hold with respect to C for<br>ODELAY|0.10/0.07|0.12/0.08|0.13/0.09|0.13/0.09|ns|
|TIDCCK_RST/ TIDCKC_RST|RST pin setup/hold with respect to C for<br>IDELAY|0.13/0.08|0.14/0.10|0.16/0.12|0.16/0.12|ns|
|TODCCK_RST/ TODCKC_RST|RST pin setup/hold with respect to C for<br>ODELAY|0.16/0.04|0.19/0.06|0.24/0.08|0.24/0.08|ns|
|TIDDO_IDATAIN|Propagation delay through IDELAY|Note 5|Note 5|Note 5|Note 5|ps|
|TODDO_ODATAIN|Propagation delay through ODELAY|Note 5|Note 5|Note 5|Note 5|ps|



## **Notes:** 

1. Average tap delay at 200 MHz = 78 ps, at 300 MHz = 52 ps, and at 400 MHz = 39 ps. 

2. When HIGH_PERFORMANCE mode is set to TRUE or FALSE. 

3. When HIGH_PERFORMANCE mode is set to TRUE. 

4. When HIGH_PERFORMANCE mode is set to FALSE. 

5. Delay depends on IDELAY/ODELAY tap setting. See the timing report for actual values. 

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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  29:_ **IO_FIFO Switching Characteristics** 

|**Symbol**|**Description**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|
|||**-3**|**-2/-2L/-2G**|**-1**|**-1M**||
|**IO_FIFO Clock to Out Delays**|||||||
|TOFFCKO_DO|RDCLK to Q outputs|0.51|0.56|0.63|0.63|ns|
|TCKO_FLAGS|Clock to IO_FIFO flags|0.59|0.62|0.81|0.81|ns|
|**Setup/Hold**|||||||
|TCCK_D/TCKC_D|D inputs to WRCLK|0.43/–0.01|0.47/–0.01|0.53/–0.01|0.53/0.09|ns|
|TIFFCCK_WREN/TIFFCKC_WREN|WREN to WRCLK|0.39/–0.01|0.43/–0.01|0.50/–0.01|0.50/–0.01|ns|
|TOFFCCK_RDEN/TOFFCKC_RDEN|RDEN to RDCLK|0.49/0.01|0.53/0.02|0.61/0.02|0.61/0.02|ns|
|**Minimum Pulse Width**|||||||
|TPWH_IO_FIFO|RESET, RDCLK, WRCLK|0.81|0.92|1.08|1.08|ns|
|TPWL_IO_FIFO|RESET, RDCLK, WRCLK|0.81|0.92|1.08|1.08|ns|
|**Maximum Frequency**|||||||
|FMAX|RDCLK and WRCLK|533.05|470.37|400.00|400.00|MHz|



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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

## **CLB Switching Characteristics** 

_Table  30:_ **CLB Switching Characteristics** 

|**Symbol**|**Description**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|
|||**-3**|**-2/-2L/-2G**|**-1**|**-1M**||
|**Combinatorial Delays**|||||||
|TILO|An – Dn LUT address to A|0.05|0.05|0.06|0.06|ns, Max|
|TILO_2|An – Dn LUT address to AMUX/CMUX|0.15|0.16|0.19|0.19|ns, Max|
|TILO_3|An – Dn LUT address to BMUX_A|0.24|0.25|0.30|0.30|ns, Max|
|TITO|An – Dn inputs to A – D Q outputs|0.58|0.61|0.74|0.74|ns, Max|
|TAXA|AX inputs to AMUX output|0.38|0.40|0.49|0.49|ns, Max|
|TAXB|AX inputs to BMUX output|0.40|0.42|0.52|0.52|ns, Max|
|TAXC|AX inputs to CMUX output|0.39|0.41|0.50|0.50|ns, Max|
|TAXD|AX inputs to DMUX output|0.43|0.44|0.52|0.52|ns, Max|
|TBXB|BX inputs to BMUX output|0.31|0.33|0.40|0.40|ns, Max|
|TBXD|BX inputs to DMUX output|0.38|0.39|0.47|0.47|ns, Max|
|TCXC|CX inputs to CMUX output|0.27|0.28|0.34|0.34|ns, Max|
|TCXD|CX inputs to DMUX output|0.33|0.34|0.41|0.41|ns, Max|
|TDXD|DX inputs to DMUX output|0.32|0.33|0.40|0.40|ns, Max|
|**Sequential Delays**|||||||
|TCKO|Clock to AQ – DQ outputs|0.26|0.27|0.32|0.32|ns, Max|
|TSHCKO|Clock to AMUX – DMUX outputs|0.32|0.32|0.39|0.39|ns, Max|
|**Setup and Hold Times**|**of CLB Flip-Flops Before/After Clock CLK**||||||
|TAS/TAH|AN– DNinput to CLK on A – D flip-flops|0.01/0.12|0.02/0.13|0.03/0.18|0.03/0.24|ns, Min|
|TDICK/TCKDI|AX– DXinput to CLK on A – D flip-flops|0.04/0.14|0.04/0.14|0.05/0.20|0.05/0.26|ns, Min|
||AX– DXinput through MUXs and/or carry logic<br>to CLK on A – D flip-flops|0.36/0.10|0.37/0.11|0.46/0.16|0.46/0.22|ns, Min|
|TCECK_CLB/TCKCE_CLB|CE input to CLK on A – D flip-flops|0.19/0.05|0.20/0.05|0.25/0.05|0.25/0.11|ns, Min|
|TSRCK/TCKSR|SR input to CLK on A – D flip-flops|0.30/0.05|0.31/0.07|0.37/0.09|0.37/0.22|ns, Min|
|**Set/Reset**|||||||
|TSRMIN|SR input minimum pulse width|0.52|0.78|1.04|1.04|ns, Min|
|TRQ|Delay from SR input to AQ – DQ flip-flops|0.38|0.38|0.46|0.46|ns, Max|
|TCEO|Delay from CE input to AQ – DQ flip-flops|0.34|0.35|0.43|0.43|ns, Max|
|FTOG|Toggle frequency (for export control)|1818|1818|1818|1818|MHz|



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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

## **CLB Distributed RAM Switching Characteristics (SLICEM Only)** 

_Table  31:_ **CLB Distributed RAM Switching Characteristics** 

|**Symbol**|**Description**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|
|||**-3**|**-2/-2L/-2G**|**-1**|**-1M**||
|**Sequential Delays**|||||||
|TSHCKO(1)|Clock to A – B outputs|0.68|0.70|0.85|0.85|ns, Max|
|TSHCKO_1|Clock to AMUX – BMUX outputs|0.91|0.95|1.15|1.15|ns, Max|
|**Setup and Hold Times Before/After Clock CLK**|||||||
|TDS_LRAM/TDH_LRAM|A – D inputs to CLK|0.45/0.23|0.45/0.24|0.54/0.27|0.54/0.28|ns, Min|
|TAS_LRAM/TAH_LRAM|Address An inputs to clock|0.13/0.50|0.14/0.50|0.17/0.58|0.17/0.61|ns, Min|
||Address An inputs through MUXs and/or<br>carry logic to clock|0.40/0.16|0.42/0.17|0.52/0.23|0.52/0.29|ns, Min|
|TWS_LRAM/TWH_LRAM|WE input to clock|0.29/0.09|0.30/0.09|0.36/0.09|0.36/0.11|ns, Min|
|TCECK_LRAM/TCKCE_LRAM|CE input to CLK|0.29/0.09|0.30/0.09|0.37/0.09|0.37/0.11|ns, Min|
|**Clock CLK**|||||||
|TMPW|Minimum pulse width|0.68|0.77|0.91|0.91|ns, Min|
|TMCP|Minimum clock period|1.35|1.54|1.82|1.82|ns, Min|



## **Notes:** 

1. TSHCKO also represents the CLK to XMUX output. Refer to the timing report for the CLK to XMUX path. 

## **CLB Shift Register Switching Characteristics (SLICEM Only)** 

_Table  32:_ **CLB Shift Register Switching Characteristics** 

|**Symbol**|**Description**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|
|||**-3**|**-2/-2L/-2G**|**-1**|**-1M**||
|**Sequential Delays**|||||||
|TREG|Clock to A – D outputs|0.96|0.98|1.20|1.20|ns, Max|
|TREG_MUX|Clock to AMUX – DMUX output|1.19|1.23|1.50|1.50|ns, Max|
|TREG_M31|Clock to DMUX output via M31 output|0.89|0.91|1.10|1.10|ns, Max|
|**Setup and Hold Times Before/After Clock CLK**|||||||
|TWS_SHFREG/TWH_SHFREG|WE input|0.26/0.09|0.27/0.09|0.33/0.09|0.33/0.11|ns, Min|
|TCECK_SHFREG/TCKCE_SHFREG|CE input to CLK|0.27/0.09|0.28/0.09|0.33/0.09|0.33/0.11|ns, Min|
|TDS_SHFREG/TDH_SHFREG|A – D inputs to CLK|0.28/0.26|0.28/0.26|0.33/0.30|0.33/0.36|ns, Min|
|**Clock CLK**|||||||
|TMPW_SHFREG|Minimum pulse width|0.55|0.65|0.78|0.78|ns, Min|



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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

## **Block RAM and FIFO Switching Characteristics** 

_Table  33:_ **Block RAM and FIFO Switching Characteristics** 

|**Symbol**|**Description**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|
|||**-3**|**-2/-2L/-2G**|**-1**|**-1M**||
|**Block RAM and FIFO Clock-to-Out Delays**|||||||
|TRCKO_DOand<br>TRCKO_DO_REG(1)|Clock CLK to DOUT output (without output<br>register)(2)(3)|1.57|1.80|2.08|2.08|ns, Max|
||Clock CLK to DOUT output (with output<br>register)(4)(5)|0.54|0.63|0.75|0.75|ns, Max|
|TRCKO_DO_ECCand<br>TRCKO_DO_ECC_REG|Clock CLK to DOUT output with ECC<br>(without output register)(2)(3)|2.35|2.58|3.26|3.26|ns, Max|
||Clock CLK to DOUT output with ECC (with<br>output register)(4)(5)|0.62|0.69|0.80|0.80|ns, Max|
|TRCKO_DO_CASCOUTand<br>TRCKO_DO_CASCOUT_REG|Clock CLK to DOUT output with Cascade<br>(without output register)(2)|2.21|2.45|2.80|2.80|ns, Max|
||Clock CLK to DOUT output with Cascade<br>(with output register)(4)|0.98|1.08|1.24|1.24|ns, Max|
|TRCKO_FLAGS|Clock CLK to FIFO flags outputs(6)|0.65|0.74|0.89|0.89|ns, Max|
|TRCKO_POINTERS|Clock CLK to FIFO pointers outputs(7)|0.79|0.87|0.98|0.98|ns, Max|
|TRCKO_PARITY_ECC|Clock CLK to ECCPARITY in ECC encode<br>only mode|0.66|0.72|0.80|0.80|ns, Max|
|TRCKO_SDBIT_ECCand<br>TRCKO_SDBIT_ECC_REG|Clock CLK to BITERR (without output<br>register)|2.17|2.38|3.01|3.01|ns, Max|
||Clock CLK to BITERR (with output register)|0.57|0.65|0.76|0.76|ns, Max|
|TRCKO_RDADDR_ECCand<br>TRCKO_RDADDR_ECC_REG|Clock CLK to RDADDR output with ECC<br>(without output register)|0.64|0.74|0.90|0.90|ns, Max|
||Clock CLK to RDADDR output with ECC<br>(with output register)|0.71|0.79|0.92|0.92|ns, Max|
|**Setup and Hold Times Before/After Clock CLK**|||||||
|TRCCK_ADDRA/TRCKC_ADDRA|ADDR inputs(8)|0.38/0.27|0.42/0.28|0.48/0.31|0.48/0.38|ns, Min|
|TRDCK_DI_WF_NC/<br>TRCKD_DI_WF_NC|Data input setup/hold time when block RAM<br>is configured in WRITE_FIRST or<br>NO_CHANGE mode(9)|0.49/0.51|0.55/0.53|0.63/0.57|0.63/0.57|ns, Min|
|TRDCK_DI_RF/TRCKD_DI_RF|Data input setup/hold time when block RAM<br>is configured in READ_FIRST mode(9)|0.17/0.25|0.19/0.29|0.21/0.35|0.21/0.35|ns, Min|
|TRDCK_DI_ECC/TRCKD_DI_ECC|DIN inputs with block RAM ECC in standard<br>mode(9)|0.42/0.37|0.47/0.39|0.53/0.43|0.53/0.58|ns, Min|
|TRDCK_DI_ECCW/TRCKD_DI_ECCW|DIN inputs with block RAM ECC encode<br>only(9)|0.79/0.37|0.87/0.39|0.99/0.43|0.99/0.58|ns, Min|
|TRDCK_DI_ECC_FIFO/<br>TRCKD_DI_ECC_FIFO|DIN inputs with FIFO ECC in standard<br>mode(9)|0.89/0.47|0.98/0.50|1.12/0.54|1.12/0.69|ns, Min|
|TRCCK_INJECTBITERR/<br>TRCKC_INJECTBITERR|Inject single/double bit error in ECC mode|0.49/0.30|0.55/0.31|0.63/0.34|0.63/0.43|ns, Min|
|TRCCK_EN/TRCKC_EN|Block RAM Enable (EN) input|0.30/0.17|0.33/0.18|0.38/0.20|0.38/0.32|ns, Min|
|TRCCK_REGCE/TRCKC_REGCE|CE input of output register|0.21/0.13|0.25/0.13|0.31/0.14|0.31/0.19|ns, Min|
|TRCCK_RSTREG/TRCKC_RSTREG|Synchronous RSTREG input|0.25/0.06|0.27/0.06|0.29/0.06|0.29/0.14|ns, Min|
|TRCCK_RSTRAM/TRCKC_RSTRAM|Synchronous RSTRAM input|0.27/0.35|0.29/0.37|0.31/0.39|0.31/0.39|ns, Min|
|TRCCK_WEA/TRCKC_WEA|Write Enable (WE) input (Block RAM only)|0.38/0.15|0.41/0.16|0.46/0.17|0.46/0.29|ns, Min|



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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  33:_ **Block RAM and FIFO Switching Characteristics** _**(Cont’d)**_ 

|**Symbol**|**Description**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|
|||**-3**|**-2/-2L/-2G**|**-1**|**-1M**||
|TRCCK_WREN/TRCKC_WREN|WREN FIFO inputs|0.39/0.25|0.39/0.30|0.40/0.37|0.40/0.49|ns, Min|
|TRCCK_RDEN/TRCKC_RDEN|RDEN FIFO inputs|0.36/0.26|0.36/0.30|0.37/0.37|0.37/0.49|ns, Min|
|**Reset Delays**|||||||
|TRCO_FLAGS|Reset RST to FIFO flags/pointers(10)|0.76|0.83|0.93|0.93|ns, Max|
|TRREC_RST/TRREM_RST|FIFO reset recovery and removal timing(11)|1.59/–0.68|1.76/–0.68|2.01/–0.68|2.01/–0.68|ns, Max|
|**Maximum Frequency**|||||||
|FMAX_BRAM_WF_NC|Block RAM<br>(Write first and No change modes)<br>When not in SDP RF mode|601.32|543.77|458.09|458.09|MHz|
|FMAX_BRAM_RF_PERFORMANCE|Block RAM<br>(Read first, Performance mode)<br>When in SDP RF mode but no address<br>overlap between port A and port B|601.32|543.77|458.09|458.09|MHz|
|FMAX_BRAM_RF_DELAYED_WRITE|Block RAM<br>(Read first, Delayed_write mode)<br>When in SDP RF mode and there is<br>possibility of overlap between port A and<br>port B addresses|528.26|477.33|400.80|400.80|MHz|
|FMAX_CAS_WF_NC|Block RAM Cascade<br>(Write first, No change mode)<br>When cascade but not in RF mode|551.27|493.83|408.00|408.00|MHz|
|FMAX_CAS_RF_PERFORMANCE|Block RAM Cascade<br>(Read first, Performance mode)<br>When in cascade with RF mode and no<br>possibility of address overlap/one port is<br>disabled|551.27|493.83|408.00|408.00|MHz|
|FMAX_CAS_RF_DELAYED_WRITE|When in cascade RF mode and there is a<br>possibility of address overlap between port<br>A and port B|478.24|427.35|350.88|350.88|MHz|
|FMAX_FIFO|FIFO in all modes without ECC|601.32|543.77|458.09|458.09|MHz|
|FMAX_ECC|Block RAM and FIFO in ECC configuration|484.26|430.85|351.12|351.12|MHz|



## **Notes:** 

1. The timing report shows all of these parameters as TRCKO_DO. 

2. TRCKO_DOR includes TRCKO_DOW, TRCKO_DOPR, and TRCKO_DOPW as well as the B port equivalent timing parameters. 

3. These parameters also apply to synchronous FIFO with DO_REG = 0. 

4. TRCKO_DO includes TRCKO_DOP as well as the B port equivalent timing parameters. 

5. These parameters also apply to multirate (asynchronous) and synchronous FIFO with DO_REG = 1. 

6. TRCKO_FLAGS includes the following parameters: TRCKO_AEMPTY, TRCKO_AFULL, TRCKO_EMPTY, TRCKO_FULL, TRCKO_RDERR, TRCKO_WRERR. 

7. TRCKO_POINTERS includes both TRCKO_RDCOUNT and TRCKO_WRCOUNT. 

8. The ADDR setup and hold must be met when EN is asserted (even when WE is deasserted). Otherwise, block RAM data corruption is possible. 

9. These parameters include both A and B inputs as well as the parity inputs of A and B. 

10. TRCO_FLAGS includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT. 

11. RDEN and WREN must be held Low prior to and during reset. The FIFO reset must be asserted for at least five positive clock edges of the slowest clock (WRCLK or RDCLK). 

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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

## **DSP48E1 Switching Characteristics** 

_Table  34:_ **DSP48E1 Switching Characteristics** 

|**Symbol**|**Description**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|
|||**-3**|**-2/-2L/-2G**|**-1**|**-1M**||
|**Setup and Hold Times of Data/Control Pins to the Input Register Clock**|||||||
|TDSPDCK_A_AREG/TDSPCKD_A_AREG|A input to A register CLK|0.24/0.12|0.27/0.14|0.31/0.16|0.33/0.18|ns|
|TDSPDCK_B_BREG/TDSPCKD_B_BREG|B input to B register CLK|0.28/0.13|0.32/0.14|0.39/0.15|0.41/0.18|ns|
|TDSPDCK_C_CREG/TDSPCKD_C_CREG|C input to C register CLK|0.15/0.15|0.17/0.17|0.20/0.20|0.20/0.22|ns|
|TDSPDCK_D_DREG/TDSPCKD_D_DREG|D input to D register CLK|0.21/0.19|0.27/0.22|0.35/0.26|0.35/0.27|ns|
|TDSPDCK_ACIN_AREG/TDSPCKD_ACIN_AREG|ACIN input to A register CLK|0.21/0.12|0.24/0.14|0.27/0.16|0.30/0.16|ns|
|TDSPDCK_BCIN_BREG/TDSPCKD_BCIN_BREG|BCIN input to B register CLK|0.22/0.13|0.25/0.14|0.30/0.15|0.32/0.15|ns|
|**Setup and Hold Times of Data Pins to the Pipeline Register Clock**|||||||
|TDSPDCK_{A, B}_MREG_MULT/<br>TDSPCKD_{A, B}_MREG_MULT|{A, B} input to M register CLK<br>using multiplier|2.04/–0.01|2.34/–0.01|2.79/–0.01|2.79/–0.01|ns|
|TDSPDCK_{A, D}_ADREG/<br>TDSPCKD_{A, D}_ADREG|{A, D} input to AD register CLK|1.09/–0.02|1.25/–0.02|1.49/–0.02|1.49/–0.02|ns|
|**Setup and Hold Times of Data/Control Pins to the Output Register Clock**|||||||
|TDSPDCK_{A, B}_PREG_MULT/<br>TDSPCKD_{A, B} _PREG_MULT|{A, B,} input to P register CLK<br>using multiplier|3.41/–0.24|3.90/–0.24|4.64/–0.24|4.64/–0.24|ns|
|TDSPDCK_D_PREG_MULT/<br>TDSPCKD_D_PREG_MULT|D input to P register CLK using<br>multiplier|3.33/–0.62|3.81/–0.62|4.53/–0.62|4.53/–0.62|ns|
|TDSPDCK_{A, B} _PREG/<br>TDSPCKD_{A, B} _PREG|A or B input to P register CLK not<br>using multiplier|1.47/–0.24|1.68/–0.24|2.00/–0.24|2.00/–0.24|ns|
|TDSPDCK_C_PREG/<br>TDSPCKD_C_PREG|C input to P register CLK not<br>using multiplier|1.30/–0.22|1.49/–0.22|1.78/–0.22|1.78/–0.22|ns|
|TDSPDCK_PCIN_PREG/<br>TDSPCKD_PCIN_PREG|PCIN input to P register CLK|1.12/–0.13|1.28/–0.13|1.52/–0.13|1.52/–0.13|ns|
|**Setup and Hold Times of the CE Pins**|||||||
|TDSPDCK_{CEA;CEB}_{AREG;BREG}/<br>TDSPCKD_{CEA;CEB}_{AREG;BREG}|{CEA; CEB} input to {A; B}<br>register CLK|0.30/0.05|0.36/0.06|0.44/0.09|0.44/0.09|ns|
|TDSPDCK_CEC_CREG/TDSPCKD_CEC_CREG|CEC input to C register CLK|0.24/0.08|0.29/0.09|0.36/0.11|0.36/0.11|ns|
|TDSPDCK_CED_DREG/TDSPCKD_CED_DREG|CED input to D register CLK|0.31/–0.02|0.36/–0.02|0.44/–0.02|0.44/0.02|ns|
|TDSPDCK_CEM_MREG/TDSPCKD_CEM_MREG|CEM input to M register CLK|0.26/0.15|0.29/0.17|0.33/0.20|0.33/0.20|ns|
|TDSPDCK_CEP_PREG/ TDSPCKD_CEP_PREG|CEP input to P register CLK|0.31/0.01|0.36/0.01|0.45/0.01|0.45/0.01|ns|
|**Setup and Hold Times of the RST Pins**|||||||
|TDSPDCK_{RSTA; RSTB}_{AREG; BREG}/<br>TDSPCKD_{RSTA; RSTB}_{AREG; BREG}|{RSTA, RSTB} input to {A, B}<br>register CLK|0.34/0.10|0.39/0.11|0.47/0.13|0.47/0.14|ns|
|TDSPDCK_RSTC_CREG/TDSPCKD_RSTC_CREG|RSTC input to C register CLK|0.06/0.22|0.07/0.24|0.08/0.26|0.08/0.26|ns|
|TDSPDCK_RSTD_DREG/TDSPCKD_RSTD_DREG|RSTD input to D register CLK|0.37/0.06|0.42/0.06|0.50/0.07|0.50/0.07|ns|
|TDSPDCK_RSTM_MREG/TDSPCKD_RSTM_MREG|RSTM input to M register CLK|0.18/0.18|0.20/0.21|0.23/0.24|0.23/0.24|ns|
|TDSPDCK_RSTP_PREG/TDSPCKD_RSTP_PREG|RSTP input to P register CLK|0.24/0.01|0.26/0.01|0.30/0.01|0.30/0.11|ns|
|**Combinatorial Delays from Input Pins to Output Pins**|||||||
|TDSPDO_A_CARRYOUT_MULT|A input to CARRYOUT output<br>using multiplier|3.21|3.69|4.39|4.39|ns|
|TDSPDO_D_P_MULT|D input to P output using<br>multiplier|3.15|3.61|4.30|4.30|ns|



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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  34:_ **DSP48E1 Switching Characteristics** _**(Cont’d)**_ 

|**Symbol**|**Description**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|
|||**-3**|**-2/-2L/-2G**|**-1**|**-1M**||
|TDSPDO_A_P|A input to P output not using<br>multiplier|1.30|1.48|1.76|1.76|ns|
|TDSPDO_C_P|C input to P output|1.13|1.30|1.55|1.55|ns|
|**Combinatorial Delays from Input Pins to Cascading Output Pins**|||||||
|TDSPDO_{A; B}_{ACOUT; BCOUT}|{A, B} input to {ACOUT, BCOUT}<br>output|0.47|0.53|0.63|0.63|ns|
|TDSPDO_{A, B}_CARRYCASCOUT_MULT|{A, B} input to CARRYCASCOUT<br>output using multiplier|3.44|3.94|4.69|4.69|ns|
|TDSPDO_D_CARRYCASCOUT_MULT|D input to CARRYCASCOUT<br>output using multiplier|3.36|3.85|4.58|4.58|ns|
|TDSPDO_{A, B}_CARRYCASCOUT|{A, B} input to CARRYCASCOUT<br>output not using multiplier|1.50|1.72|2.04|2.04|ns|
|TDSPDO_C_CARRYCASCOUT|C input to CARRYCASCOUT<br>output|1.34|1.53|1.83|1.83|ns|
|**Combinatorial Delays from Cascading Input Pins to All Output Pins**|||||||
|TDSPDO_ACIN_P_MULT|ACIN input to P output using<br>multiplier|3.09|3.55|4.24|4.24|ns|
|TDSPDO_ACIN_P|ACIN input to P output not using<br>multiplier|1.16|1.33|1.59|1.59|ns|
|TDSPDO_ACIN_ACOUT|ACIN input to ACOUT output|0.32|0.37|0.45|0.45|ns|
|TDSPDO_ACIN_CARRYCASCOUT_MULT|ACIN input to CARRYCASCOUT<br>output using multiplier|3.30|3.79|4.52|4.52|ns|
|TDSPDO_ACIN_CARRYCASCOUT|ACIN input to CARRYCASCOUT<br>output not using multiplier|1.37|1.57|1.87|1.87|ns|
|TDSPDO_PCIN_P|PCIN input to P output|0.94|1.08|1.29|1.29|ns|
|TDSPDO_PCIN_CARRYCASCOUT|PCIN input to CARRYCASCOUT<br>output|1.15|1.32|1.57|1.57|ns|
|**Clock to Outs from Output Register Clock to Output Pins**|||||||
|TDSPCKO_P_PREG|CLK PREG to P output|0.33|0.35|0.39|0.39|ns|
|TDSPCKO_CARRYCASCOUT_PREG|CLK PREG to<br>CARRYCASCOUT output|0.44|0.50|0.59|0.59|ns|
|**Clock to Outs from Pipeline Register Clock to Output Pins**|||||||
|TDSPCKO_P_MREG|CLK MREG to P output|1.42|1.64|1.96|1.96|ns|
|TDSPCKO_CARRYCASCOUT_MREG|CLK MREG to<br>CARRYCASCOUT output|1.63|1.87|2.24|2.24|ns|
|TDSPCKO_P_ADREG_MULT|CLK ADREG to P output using<br>multiplier|2.30|2.63|3.13|3.13|ns|
|TDSPCKO_CARRYCASCOUT_ADREG_MULT|CLK ADREG to<br>CARRYCASCOUT output using<br>multiplier|2.51|2.87|3.41|3.41|ns|



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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  34:_ **DSP48E1 Switching Characteristics** _**(Cont’d)**_ 

|**Symbol**|**Description**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|
|||**-3**|**-2/-2L/-2G**|**-1**|**-1M**||
|**Clock to Outs from Input Register Clock to Output Pins**|||||||
|TDSPCKO_P_AREG_MULT|CLK AREG to P output using<br>multiplier|3.34|3.83|4.55|4.55|ns|
|TDSPCKO_P_BREG|CLK BREG to P output not using<br>multiplier|1.39|1.59|1.88|1.88|ns|
|TDSPCKO_P_CREG|CLK CREG to P output not using<br>multiplier|1.43|1.64|1.95|1.95|ns|
|TDSPCKO_P_DREG_MULT|CLK DREG to P output using<br>multiplier|3.32|3.80|4.51|4.51|ns|
|**Clock to Outs from Input Register Clock to Cascading Output Pins**|||||||
|TDSPCKO_{ACOUT; BCOUT}_{AREG; BREG}|CLK (ACOUT, BCOUT) to {A,B}<br>register output|0.55|0.62|0.74|0.74|ns|
|TDSPCKO_CARRYCASCOUT_{AREG, BREG}_MULT|CLK (AREG, BREG) to<br>CARRYCASCOUT output using<br>multiplier|3.55|4.06|4.84|4.84|ns|
|TDSPCKO_CARRYCASCOUT_ BREG|CLK (BREG) to<br>CARRYCASCOUT output not<br>using multiplier|1.60|1.82|2.16|2.16|ns|
|TDSPCKO_CARRYCASCOUT_ DREG_MULT|CLK (DREG) to<br>CARRYCASCOUT output using<br>multiplier|3.52|4.03|4.79|4.79|ns|
|TDSPCKO_CARRYCASCOUT_ CREG|CLK (CREG) to<br>CARRYCASCOUT output|1.64|1.88|2.23|2.23|ns|
|**Maximum Frequency**|||||||
|FMAX|With all registers used|741.84|650.20|547.95|547.95|MHz|
|FMAX_PATDET|With pattern detector|627.35|549.75|463.61|463.61|MHz|
|FMAX_MULT_NOMREG|Two register multiply without<br>MREG|412.20|360.75|303.77|303.77|MHz|
|FMAX_MULT_NOMREG_PATDET|Two register multiply without<br>MREG with pattern detect|374.25|327.65|276.01|276.01|MHz|
|FMAX_PREADD_MULT_NOADREG|Without ADREG|468.82|408.66|342.70|342.70|MHz|
|FMAX_PREADD_MULT_NOADREG_PATDET|Without ADREG with pattern<br>detect|468.82|408.66|342.70|342.70|MHz|
|FMAX_NOPIPELINEREG|Without pipeline registers<br>(MREG, ADREG)|306.84|267.81|225.02|225.02|MHz|
|FMAX_NOPIPELINEREG_PATDET|Without pipeline registers<br>(MREG, ADREG) with pattern<br>detect|285.23|249.13|209.38|209.38|MHz|



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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

## **Clock Buffers and Networks** 

_Table  35:_ **Global Clock Switching Characteristics (Including BUFGCTRL)** 

|**Symbol**|**Description**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|
|||**-3**|**-2/-2L/-2G**|**-1**|**-1M**||
|TBCCCK_CE/TBCCKC_CE(1)|CE pins setup/hold|0.12/0.30|0.14/0.38|0.26/0.38|0.26/0.92|ns|
|TBCCCK_S/TBCCKC_S(1)|S pins setup/hold|0.12/0.30|0.14/0.38|0.26/0.38|0.26/0.92|ns|
|TBCCKO_O(2)|BUFGCTRL delay from I0/I1 to O|0.08|0.10|0.12|0.12|ns|
|**Maximum Frequency**|||||||
|FMAX_BUFG|Global clock tree (BUFG)|741.00|710.00|625.00|625.00|MHz|



## **Notes:** 

1. TBCCCK_CE and TBCCKC_CE must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These parameters do not apply to the BUFGMUX primitive that assures glitch-free operation. The other global clock setup and hold times are optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching between clocks. 

2. TBGCKO_O (BUFG delay from I0 to O) values are the same as TBCCKO_O values. 

_Table  36:_ **Input/Output Clock Switching Characteristics (BUFIO)** 

|**Symbol**|**Description**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|
|||**-3**|**-2/-2L/-2G**|**-1**|**-1M**||
|TBIOCKO_O|Clock to out delay from I to O|1.04|1.14|1.32|1.32|ns|
|**Maximum Frequency**|||||||
|FMAX_BUFIO|I/O clock tree (BUFIO)|800.00|800.00|710.00|710.00|MHz|



_Table  37:_ **Regional Clock Buffer Switching Characteristics (BUFR)** 

|**Symbol**|**Description**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|
|||**-3**|**-2/-2L/-2G**|**-1**|**-1M**||
|TBRCKO_O|Clock to out delay from I to O|0.60|0.65|0.77|0.77|ns|
|TBRCKO_O_BYP|Clock to out delay from I to O with Divide Bypass<br>attribute set|0.30|0.32|0.38|0.38|ns|
|TBRDO_O|Propagation delay from CLR to O|0.71|0.75|0.96|0.96|ns|
|**Maximum Frequency**|||||||
|FMAX_BUFR(1)|Regional clock tree (BUFR)|600.00|540.00|450.00|450.00|MHz|



## **Notes:** 

1. The maximum input frequency to the BUFR and BUFMR is the BUFIO FMAX frequency. 

## _Table  38:_ **Horizontal Clock Buffer Switching Characteristics (BUFH)** 

|**Symbol**|**Description**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|
|||**-3**|**-2/-2L/-2G**|**-1**|**-1M**||
|TBHCKO_O|BUFH delay from I to O|0.10|0.11|0.13|0.13|ns|
|TBHCCK_CE/TBHCKC_CE|CE pin setup and hold|0.20/0.16|0.23/0.20|0.38/0.21|0.38/0.79|ns|
|**Maximum Frequency**|||||||
|FMAX_BUFH|Horizontal clock buffer (BUFH)|741.00|710.00|625.00|625.00|MHz|



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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  39:_ **Duty Cycle Distortion and Clock Tree Skew** 

|**Symbol**|**Description**|**Device**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|---|---|---|
||||**-3**|**-2G**|**-2**|**-2L**|**-1**|**-1M**||
|TDCD_CLK|Global clock tree duty cycle distortion(1)|All|0.20|0.20|0.20|0.20|0.20|0.20|ns|
|TCKSKEW|Global clock tree skew(2)|XC7V585T|0.75|N/A|0.91|0.91|0.98|N/A|ns|
|||XC7V2000T|N/A|0.39|0.39|0.39|0.39|N/A|ns|
|||XC7VX330T|0.60|N/A|0.74|0.74|0.79|N/A|ns|
|||XC7VX415T|0.76|N/A|0.84|0.84|0.91|N/A|ns|
|||XC7VX485T|0.60|N/A|0.74|0.74|0.79|N/A|ns|
|||XC7VX550T|0.73|N/A|0.88|0.88|0.96|N/A|ns|
|||XC7VX690T|0.73|N/A|0.88|0.88|0.96|N/A|ns|
|||XC7VX980T|N/A|N/A|0.91|0.91|0.98|N/A|ns|
|||XC7VX1140T|N/A|0.39|0.39|0.39|0.39|N/A|ns|
|||XQ7V585T|N/A|N/A|0.91|0.91|0.98|0.98|ns|
|||XQ7VX330T|N/A|N/A|0.74|0.74|0.79|0.79|ns|
|||XQ7VX485T|N/A|N/A|0.74|0.74|0.79|0.79|ns|
|||XQ7VX690T|N/A|N/A|0.88|N/A|0.96|N/A|ns|
|||XQ7VX980T|N/A|N/A|N/A|0.91|0.98|N/A|ns|
|TDCD_BUFIO|I/O clock tree duty cycle distortion|All|0.12|0.12|0.12|0.12|0.12|0.12|ns|
|TBUFIOSKEW|I/O clock tree skew across one clock region|All|0.02|0.02|0.02|0.02|0.02|0.02|ns|
|TDCD_BUFR|Regional clock tree duty cycle distortion|All|0.15|0.15|0.15|0.15|0.15|0.15|ns|



## **Notes:** 

1. These parameters represent the worst-case duty cycle distortion observable at the I/O flip-flops. For all I/O standards, IBIS can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical rise/fall times. 

2. The TCKSKEW value represents the worst-case clock-tree skew observable between sequential I/O elements in a single SLR. Significantly less clock-tree skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx Timing Analyzer tools to evaluate clock skew specific to your application. 

## **MMCM Switching Characteristics** 

_Table  40:_ **MMCM Specification** 

|**Symbol**|**Description**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|
|||**-3**|**-2/-2L/-2G**|**-1**|**-1M**||
|MMCM_FINMAX|Maximum input clock frequency|1066.00|933.00|800.00|800.00|MHz|
|MMCM_FINMIN|Minimum input clock frequency|10|10|10|10|MHz|
|MMCM_FINJITTER|Maximum input clock period jitter|< 20% of clock input period or 1 ns Max|||||
|MMCM_FINDUTY|Allowable input duty cycle: 10—49 MHz|25|25|25|25|%|
||Allowable input duty cycle: 50—199 MHz|30|30|30|30|%|
||Allowable input duty cycle: 200—399 MHz|35|35|35|35|%|
||Allowable input duty cycle: 400—499 MHz|40|40|40|40|%|
||Allowable input duty cycle: >500 MHz|45|45|45|45|%|
|MMCM_FMIN_PSCLK|Minimum dynamic phase shift clock frequency|0.01|0.01|0.01|0.01|MHz|
|MMCM_FMAX_PSCLK|Maximum dynamic phase shift clock frequency|550.00|500.00|450.00|450.00|MHz|
|MMCM_FVCOMIN|Minimum MMCM VCO frequency|600.00|600.00|600.00|600.00|MHz|
|MMCM_FVCOMAX|Maximum MMCM VCO frequency|1600.00|1440.00|1200.00|1200.00|MHz|



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_Table  40:_ **MMCM Specification** _**(Cont’d)**_ 

|**Symbol**|**Description**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|
|||**-3**|**-2/-2L/-2G**|**-1**|**-1M**||
|MMCM_FBANDWIDTH|Low MMCM bandwidth at typical(1)|1.00|1.00|1.00|1.00|MHz|
||High MMCM bandwidth at typical(1)|4.00|4.00|4.00|4.00|MHz|
|MMCM_TSTATPHAOFFSET|Static phase offset of the MMCM outputs(2)|0.12|0.12|0.12|0.12|ns|
|MMCM_TOUTJITTER|MMCM output jitter|Note 3|||||
|MMCM_TOUTDUTY|MMCM output clock duty cycle precision(4)|0.20|0.20|0.20|0.20|ns|
|MMCM_TLOCKMAX|MMCM maximum Lock Time|100|100|100|100|µs|
|MMCM_FOUTMAX|MMCM maximum output frequency|1066.00|933.00|800.00|800.00|MHz|
|MMCM_FOUTMIN|MMCM minimum output frequency(5)(6)|4.69|4.69|4.69|4.69|MHz|
|MMCM_TEXTFDVAR|External clock feedback variation|< 20% of clock input period or 1 ns Max|||||
|MMCM_RSTMINPULSE|Minimum reset pulse width|5.00|5.00|5.00|5.00|ns|
|MMCM_FPFDMAX|Maximum frequency at the phase frequency<br>detector|550.00|500.00|450.00|450.00|MHz|
|MMCM_FPFDMIN|Minimum frequency at the phase frequency<br>detector|10.00|10.00|10.00|10.00|MHz|
|MMCM_TFBDELAY|Maximum delay in the feedback path|3 ns Max or one CLKIN cycle|||||
|**MMCM Switching Characteristics Setup and Hold**|||||||
|TMMCMDCK_PSEN/<br>TMMCMCKD_PSEN|Setup and hold of phase-shift enable|1.04/0.00|1.04/0.00|1.04/0.00|1.04/0.00|ns|
|TMMCMDCK_PSINCDEC/<br>TMMCMCKD_PSINCDEC|Setup and hold of phase-shift<br>increment/decrement|1.04/0.00|1.04/0.00|1.04/0.00|1.04/0.00|ns|
|TMMCMCKO_PSDONE|Phase shift clock-to-out of PSDONE|0.59|0.68|0.81|0.81|ns|
|**Dynamic Reconfiguration Port (DRP) for MMCM Before and After DCLK**|||||||
|TMMCMDCK_DADDR/<br>TMMCMCKD_DADDR|DADDR setup/hold|1.25/0.15|1.40/0.15|1.63/0.15|1.63/0.15|ns, Min|
|TMMCMDCK_DI/<br>TMMCMCKD_DI|DI setup/hold|1.25/0.15|1.40/0.15|1.63/0.15|1.63/0.15|ns, Min|
|TMMCMDCK_DEN/<br>TMMCMCKD_DEN|DEN setup/hold|1.76/0.00|1.97/0.00|2.29/0.00|2.29/0.00|ns, Min|
|TMMCMDCK_DWE/<br>TMMCMCKD_DWE|DWE setup/hold|1.25/0.15|1.40/0.15|1.63/0.15|1.63/0.15|ns, Min|
|TMMCMCKO_DRDY|CLK to out of DRDY|0.65|0.72|0.99|0.99|ns, Max|
|FDCK|DCLK frequency|200.00|200.00|200.00|200.00|MHz, Max|



## **Notes:** 

1. The MMCM does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies. 

2. The static offset is measured between any MMCM outputs with identical phase. 

3. Values for this parameter are available in the Clocking Wizard. See http://www.xilinx.com/products/intellectual-property/clocking_wizard.htm. 

4. Includes global clock buffer. 

5. Calculated as FVCO/128 assuming output duty cycle is 50%. 

6. When CLKOUT4_CASCADE = TRUE, MMCM_FOUTMIN is 0.036 MHz. 

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## **PLL Switching Characteristics** 

_Table  41:_ **PLL Specification** 

|**Symbol**|**Description**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|
|||**-3**|**-2/-2L/-2G**|**-1**|**-1M**||
|PLL_FINMAX|Maximum input clock frequency|1066.00|933.00|800.00|800.00|MHz|
|PLL_FINMIN|Minimum input clock frequency|19.00|19.00|19.00|19.00|MHz|
|PLL_FINJITTER|Maximum input clock period jitter|< 20% of clock input period or 1 ns Max|||||
|PLL_FINDUTY|Allowable input duty cycle: 19—49 MHz|25|25|25|25|%|
||Allowable input duty cycle: 50—199 MHz|30|30|30|30|%|
||Allowable input duty cycle: 200—399 MHz|35|35|35|35|%|
||Allowable input duty cycle: 400—499 MHz|40|40|40|40|%|
||Allowable input duty cycle: >500 MHz|45|45|45|45|%|
|PLL_FVCOMIN|Minimum PLL VCO frequency|800.00|800.00|800.00|800.00|MHz|
|PLL_FVCOMAX|Maximum PLL VCO frequency|2133.00|1866.00|1600.00|1600.00|MHz|
|PLL_FBANDWIDTH|Low PLL bandwidth at typical(1)|1.00|1.00|1.00|1.00|MHz|
||High PLL bandwidth at typical(1)|4.00|4.00|4.00|4.00|MHz|
|PLL_TSTATPHAOFFSET|Static phase offset of the PLL outputs(2)|0.12|0.12|0.12|0.12|ns|
|PLL_TOUTJITTER|PLL output jitter|Note 3|||||
|PLL_TOUTDUTY|PLL output clock duty cycle precision(4)|0.20|0.20|0.20|0.20|ns|
|PLL_TLOCKMAX|PLL maximum lock time|100|100|100|100|µs|
|PLL_FOUTMAX|PLL maximum output frequency|1066.00|933.00|800.00|800.00|MHz|
|PLL_FOUTMIN|PLL minimum output frequency(5)|6.25|6.25|6.25|6.25|MHz|
|PLL_TEXTFDVAR|External clock feedback variation|< 20% of clock input period or 1 ns Max|||||
|PLL_RSTMINPULSE|Minimum reset pulse width|5.00|5.00|5.00|5.00|ns|
|PLL_FPFDMAX|Maximum frequency at the phase frequency detector|550.00|500.00|450.00|450.00|MHz|
|PLL_FPFDMIN|Minimum frequency at the phase frequency detector|19.00|19.00|19.00|19.00|MHz|
|PLL_TFBDELAY|Maximum delay in the feedback path|3 ns Max or one CLKIN cycle|||||
|**Dynamic Reconfiguration Port (DRP) for PLL Before and After DCLK**|||||||
|TPLLDCK_DADDR/<br>TPLLCKD_DADDR|DADDR setup/hold|1.25/0.15|1.40/0.15|1.63/0.15|1.63/0.15|ns, Min|
|TPLLDCK_DI/<br>TPLLCKD_DI|DI setup/hold|1.25/0.15|1.40/0.15|1.63/0.15|1.63/0.15|ns, Min|
|TPLLDCK_DEN/<br>TPLLCKD_DEN|DEN setup/hold|1.76/0.00|1.97/0.00|2.29/0.00|2.29/0.00|ns, Min|
|TPLLDCK_DWE/<br>TPLLCKD_DWE|DWE setup/hold|1.25/0.15|1.40/0.15|1.63/0.15|1.63/0.15|ns, Min|
|TPLLCKO_DRDY|CLK to out of DRDY|0.65|0.72|0.99|0.99|ns, Max|
|FDCK|DCLK frequency|200.00|200.00|200.00|200.00|MHz, Max|



## **Notes:** 

1. The PLL does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies. 

2. The static offset is measured between any PLL outputs with identical phase. 

3. Values for this parameter are available in the Clocking Wizard. See http://www.xilinx.com/products/intellectual-property/clocking_wizard.htm. 

4. Includes global clock buffer. 

5. Calculated as FVCO/128 assuming output duty cycle is 50%. 

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## **Device Pin-to-Pin Output Parameter Guidelines** 

_Table  42:_ **Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Near Clock Region)[(1)]** 

|**Symbol**|**Description**|**Device**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|---|---|---|
||||**-3**|**-2G**|**-2**|**-2L**|**-1**|**-1M**||
|SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate,_without_MMCM/PLL.||||||||||
|TICKOF|Clock-capable clock input and OUTFF<br>at pins/banks closest to the BUFGs<br>_without_MMCM/PLL (near clock<br>region)(2)|XC7V585T|5.63|N/A|6.20|6.20|6.97|N/A|ns|
|||XC7V2000T|N/A|5.66|5.66|5.66|6.35|N/A|ns|
|||XC7VX330T|5.41|N/A|5.97|5.97|6.71|N/A|ns|
|||XC7VX415T|5.46|N/A|5.96|5.96|6.70|N/A|ns|
|||XC7VX485T|5.29|N/A|5.84|5.84|6.57|N/A|ns|
|||XC7VX550T|5.45|N/A|6.02|6.02|6.76|N/A|ns|
|||XC7VX690T|5.46|N/A|6.02|6.02|6.76|N/A|ns|
|||XC7VX980T|N/A|N/A|6.12|6.12|6.87|N/A|ns|
|||XC7VX1140T|N/A|5.59|5.59|5.59|6.28|N/A|ns|
|||XQ7V585T|N/A|N/A|6.20|6.20|6.97|6.97|ns|
|||XQ7VX330T|N/A|N/A|5.97|5.97|6.71|6.71|ns|
|||XQ7VX485T|N/A|N/A|5.84|5.84|6.57|6.57|ns|
|||XQ7VX690T|N/A|N/A|6.02|N/A|6.76|N/A|ns|
|||XQ7VX980T|N/A|N/A|N/A|6.12|6.87|N/A|ns|



## **Notes:** 

1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net in a single SLR. 

2. Refer to the Die Level Bank Numbering Overview section of _7 Series FPGA Packaging and Pinout Specification_ (UG475). 

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_Table  43:_ **Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Far Clock Region)[(1)]** 

|**Symbol**|**Description**|**Device**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|---|---|---|
||||**-3**|**-2G**|**-2**|**-2L**|**-1**|**-1M**||
|SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate,_without_MMCM/PLL.||||||||||
|TICKOFFAR|Clock-capable clock input and<br>OUTFF at pins/banks farthest<br>from the BUFGs_without_<br>MMCM/PLL (far clock region)(2)|XC7V585T|6.81|N/A|7.53|7.53|8.44|N/A|ns|
|||XC7V2000T|N/A|6.00|6.00|6.00|6.73|N/A|ns|
|||XC7VX330T|6.31|N/A|6.97|6.97|7.83|N/A|ns|
|||XC7VX415T|6.36|N/A|6.90|6.90|7.69|N/A|ns|
|||XC7VX485T|6.20|N/A|6.86|6.86|7.69|N/A|ns|
|||XC7VX550T|6.66|N/A|7.37|7.37|8.27|N/A|ns|
|||XC7VX690T|6.69|N/A|7.37|7.37|8.27|N/A|ns|
|||XC7VX980T|N/A|N/A|7.47|7.47|8.37|N/A|ns|
|||XC7VX1140T|N/A|5.93|5.93|5.93|6.65|N/A|ns|
|||XQ7V585T|N/A|N/A|7.53|7.53|8.44|8.44|ns|
|||XQ7VX330T|N/A|N/A|6.97|6.97|7.83|7.83|ns|
|||XQ7VX485T|N/A|N/A|6.86|6.86|7.69|7.69|ns|
|||XQ7VX690T|N/A|N/A|7.37|N/A|8.27|N/A|ns|
|||XQ7VX980T|N/A|N/A|N/A|7.47|8.37|N/A|ns|



## **Notes:** 

1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net in a single SLR. 

2. Refer to the Die Level Bank Numbering Overview section of _7 Series FPGA Packaging and Pinout Specification_ (UG475). 

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_Table  44:_ **Clock-Capable Clock Input to Output Delay With MMCM** 

|**Symbol**|**Description**|**Device**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|---|---|---|
||||**-3**|**-2G**|**-2**|**-2L**|**-1**|**-1M**||
|SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate,_with_MMCM.||||||||||
|TICKOFMMCMCC|Clock-capable clock input and<br>OUTFF_with_MMCM|XC7V585T|1.07|N/A|1.07|1.07|1.07|N/A|ns|
|||XC7V2000T|N/A|0.82|0.82|0.82|0.82|N/A|ns|
|||XC7VX330T|1.01|N/A|1.01|1.01|1.01|N/A|ns|
|||XC7VX415T|1.07|N/A|1.07|1.07|1.07|N/A|ns|
|||XC7VX485T|0.91|N/A|0.91|0.91|0.91|N/A|ns|
|||XC7VX550T|0.97|N/A|0.97|0.97|0.97|N/A|ns|
|||XC7VX690T|1.07|N/A|1.07|1.07|1.07|N/A|ns|
|||XC7VX980T|N/A|N/A|0.96|0.96|0.96|N/A|ns|
|||XC7VX1140T|N/A|0.82|0.82|0.82|0.82|N/A|ns|
|||XQ7V585T|N/A|N/A|1.07|1.07|1.07|1.07|ns|
|||XQ7VX330T|N/A|N/A|1.01|1.01|1.01|1.01|ns|
|||XQ7VX485T|N/A|N/A|0.91|0.91|0.91|0.91|ns|
|||XQ7VX690T|N/A|N/A|1.07|N/A|1.07|N/A|ns|
|||XQ7VX980T|N/A|N/A|N/A|0.96|0.96|N/A|ns|



## **Notes:** 

1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net in a single SLR. 

2. MMCM output jitter is already included in the timing calculation. 

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_Table  45:_ **Clock-Capable Clock Input to Output Delay With PLL** 

|**Symbol**|**Description**|**Device**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|---|---|---|
||||**-3**|**-2G**|**-2**|**-2L**|**-1**|**-1M**||
|SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate,_with_PLL.||||||||||
|TICKOFPLLCC|Clock-capable clock input<br>and OUTFF_with_PLL|XC7V585T|0.96|N/A|0.96|0.96|0.96|N/A|ns|
|||XC7V2000T|N/A|0.71|0.71|0.71|0.71|N/A|ns|
|||XC7VX330T|0.90|N/A|0.90|0.90|0.90|N/A|ns|
|||XC7VX415T|0.96|N/A|0.96|0.96|0.96|N/A|ns|
|||XC7VX485T|0.80|N/A|0.80|0.80|0.80|N/A|ns|
|||XC7VX550T|0.86|N/A|0.86|0.86|0.86|N/A|ns|
|||XC7VX690T|0.96|N/A|0.96|0.96|0.96|N/A|ns|
|||XC7VX980T|N/A|N/A|0.85|0.85|0.85|N/A|ns|
|||XC7VX1140T|N/A|0.71|0.71|0.71|0.71|N/A|ns|
|||XQ7V585T|N/A|N/A|0.96|0.96|0.96|0.96|ns|
|||XQ7VX330T|N/A|N/A|0.90|0.90|0.90|0.90|ns|
|||XQ7VX485T|N/A|N/A|0.80|0.80|0.80|0.80|ns|
|||XQ7VX690T|N/A|N/A|0.96|N/A|0.96|N/A|ns|
|||XQ7VX980T|N/A|N/A|N/A|0.85|0.85|N/A|ns|



## **Notes:** 

1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net in a single SLR. 

2. PLL output jitter is already included in the timing calculation. 

_Table  46:_ **Pin-to-Pin, Clock-to-Out using BUFIO** 

|**Symbol**|**Description**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|
|||**-3**|**-2/-2L/-2G**|**-1**|**-1M**||
|SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate,_with_BUFIO.|||||||
|TICKOFCS|Clock-to-out of I/O clock for HR I/O banks|4.93|5.52|6.20|6.20|ns|
||Clock-to-out of I/O clock for HP I/O banks|4.85|5.44|6.11|6.11|ns|



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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

## **Device Pin-to-Pin Input Parameter Guidelines** 

_Table  47:_ **Global Clock Input Setup and Hold Without MMCM/PLL with ZHOLD_DELAY on HR I/O Banks (only)** 

|**Symbol**|**Description**|**Device**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|---|---|---|
||||**-3**|**-2G**|**-2**|**-2L**|**-1**|**-1M**||
|Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15 Standard.(1)||||||||||
|TPSFD/TPHFD|Full delay (legacy<br>delay or default delay)<br>Global clock Input and<br>IFF(2)without<br>MMCM/PLL with<br>ZHOLD_DELAY on HR<br>I/O banks|XC7V585T|3.12/–0.37|N/A|3.19/–0.37|3.19/–0.37|3.42/–0.37|N/A|ns|
|||XC7V2000T|N/A|N/A|N/A|N/A|N/A|N/A|ns|
|||XC7VX330T|2.90/–0.31|N/A|2.96/–0.31|2.96/–0.31|3.16/–0.31|N/A|ns|
|||<br>XC7VX415T|N/A|N/A|N/A|N/A|N/A|N/A|ns|
|||XC7VX485T|N/A|N/A|N/A|N/A|N/A|N/A|ns|
|||XC7VX550T|N/A|N/A|N/A|N/A|N/A|N/A|ns|
|||XC7VX690T|N/A|N/A|N/A|N/A|N/A|N/A|ns|
|||XC7VX980T|N/A|N/A|N/A|N/A|N/A|N/A|ns|
|||XC7VX1140T|N/A|N/A|N/A|N/A|N/A|N/A|ns|
|||XQ7V585T|N/A|N/A|3.19/–0.37|3.19/–0.37|3.42/–0.37|3.42/–0.37|ns|
|||XQ7VX330T|N/A|N/A|2.96/–0.31|2.96/–0.31|3.16/–0.31|3.16/–0.31|ns|
|||XQ7VX485T|N/A|N/A|N/A|N/A|N/A|N/A|ns|
|||XQ7VX690T|N/A|N/A|N/A|N/A|N/A|N/A|ns|
|||XQ7VX980T|N/A|N/A|N/A|N/A|N/A|N/A|ns|



## **Notes:** 

1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage. 

2. IFF = Input Flip-Flop or Latch 

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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  48:_ **Clock-Capable Clock Input Setup and Hold With MMCM** 

|**Symbol**|**Description**|**Device**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|---|---|---|
||||**-3**|**-2G**|**-2**|**-2L**|**-1**|**-1M**||
|Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15 Standard.(1)(2)||||||||||
|TPSMMCMCC/<br>TPHMMCMCC|No delay<br>clock-capable<br>clock input and<br>IFF(3)with MMCM|XC7V585T|2.71/–0.10|N/A|3.00/–0.10|3.00/–0.10|3.33/–0.10|N/A|ns|
|||XC7V2000T|N/A|2.60/–0.24|2.60/–0.24|2.60/–0.24|2.87/–0.24|N/A|ns|
|||XC7VX330T|2.58/–0.15|N/A|2.87/–0.15|2.87/–0.15|3.18/–0.15|N/A|ns|
|||XC7VX415T|2.73/0.01|N/A|3.03/0.01|3.03/0.01|3.36/0.01|N/A|ns|
|||XC7VX485T|2.58/–0.15|N/A|2.87/–0.15|2.87/–0.15|3.18/–0.15|N/A|ns|
|||XC7VX550T|2.72/–0.09|N/A|3.01/–0.09|3.01/–0.09|3.34/–0.09|N/A|ns|
|||XC7VX690T|2.72/0.01|N/A|3.01/0.01|3.01/0.01|3.34/0.01|N/A|ns|
|||XC7VX980T|N/A|N/A|3.00/–0.10|3.00/–0.10|3.33/–0.10|N/A|ns|
|||XC7VX1140T|N/A|2.61/–0.24|2.61/–0.24|2.61/–0.24|2.88/–0.24|N/A|ns|
|||XQ7V585T|N/A|N/A|3.00/–0.10|3.00/–0.10|3.33/–0.10|3.33/–0.10|ns|
|||XQ7VX330T|N/A|N/A|2.87/–0.15|2.87/–0.15|3.18/–0.15|3.18/–0.15|ns|
|||XQ7VX485T|N/A|N/A|2.87/–0.15|2.87/–0.15|3.18/–0.15|3.18/–0.15|ns|
|||XQ7VX690T|N/A|N/A|3.01/0.01|N/A|3.34/0.01|N/A|ns|
|||XQ7VX980T|N/A|N/A|N/A|3.00/–0.10|3.33/–0.10|N/A|ns|



## **Notes:** 

1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage. 

2. Listed below are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net in a single SLR. 

3. IFF = Input Flip-Flop or Latch 

4. Use IBIS to determine any duty-cycle distortion incurred using various standards. 

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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  49:_ **Clock-Capable Clock Input Setup and Hold With PLL** 

|**Symbol**|**Description**|**Device**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|---|---|---|
||||**-3**|**-2G**|**-2**|**-2L**|**-1**|**-1M**||
|Input Setup and Hold Time Relative to Clock-Capable Clock Input Signal for SSTL15 Standard.(1)(2)||||||||||
|TPSPLLCC/<br>TPHPLLCC|No delay clock-capable<br>clock input and IFF(3)<br>with PLL|<br>XC7V585T|3.07/–0.21|N/A|3.40/–0.21|3.40/–0.21|3.72/–0.21|N/A|ns|
|||XC7V2000T|N/A|2.99/–0.35|2.99/–0.35|2.99/–0.35|3.27/–0.35|N/A|ns|
|||XC7VX330T|2.94/–0.26|N/A|3.26/–0.26|3.26/–0.26|3.57/–0.26|N/A|ns|
|||XC7VX415T|3.09/–0.10|N/A|3.42/–0.10|3.42/–0.10|3.75/–0.10|N/A|ns|
|||XC7VX485T|2.95/–0.26|N/A|3.26/–0.26|3.26/–0.26|3.58/–0.26|N/A|ns|
|||XC7VX550T|3.08/–0.20|N/A|3.40/–0.20|3.40/–0.20|3.74/–0.20|N/A|ns|
|||XC7VX690T|3.08/–0.10|N/A|3.40/–0.10|3.40/–0.10|3.74/–0.10|N/A|ns|
|||XC7VX980T|N/A|N/A|3.39/–0.21|3.39/–0.21|3.72/–0.21|N/A|ns|
|||XC7VX1140T|N/A|3.00/–0.35|3.00/–0.35|3.00/–0.35|3.27/–0.35|N/A|ns|
|||XQ7V585T|N/A|N/A|3.40/–0.21|3.40/–0.21|3.72/–0.21|3.72/–0.21|ns|
|||XQ7VX330T|N/A|N/A|3.26/–0.26|3.26/–0.26|3.57/–0.26|3.57/–0.26|ns|
|||XQ7VX485T|N/A|N/A|3.26/–0.26|3.26/–0.26|3.58/–0.26|3.58/–0.26|ns|
|||XQ7VX690T|N/A|N/A|3.40/–0.10|N/A|3.74/–0.10|N/A|ns|
|||XQ7VX980T|N/A|N/A|N/A|3.39/–0.21|3.72/–0.21|N/A|ns|



## **Notes:** 

1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage. 

2. Listed below are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net in a single SLR. 

3. IFF = Input Flip-Flop or Latch 

4. Use IBIS to determine any duty-cycle distortion incurred using various standards. 

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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  50:_ **Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO** 

|**Symbol**|**Description**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|
|||**-3**|**-2/-2L/-2G**|**-1**|**-1M**||
|Input Setup and Hold Time Relative to a Forwarded Clock Input Pin Using BUFIO for SSTL15 Standard.|||||||
|TPSCS/TPHCS|Setup/hold of I/O clock for HR I/O banks|–0.36/1.36|–0.36/1.50|–0.36/1.70|–0.36/1.70|ns|
||Setup/hold of I/O clock for HP I/O banks|–0.34/1.39|–0.34/1.53|–0.34/1.73|–0.34/1.73|ns|



## _Table  51:_ **Sample Window** 

|**Symbol**|**Description**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|
|||**-3**|**-2/-2L/-2G**|**-1**|**-1M**||
|TSAMP|Sampling error at receiver pins(1)|0.51|0.56|0.61|0.61|ns|
|TSAMP_BUFIO|Sampling error at receiver pins using BUFIO(2)|0.30|0.35|0.40|0.40|ns|



## **Notes:** 

1. This parameter indicates the total sampling error of the Virtex-7 T and XT FPGAs DDR input registers, measured across voltage, temperature, and process. The characterization methodology uses the MMCM to capture the DDR input registers’ edges of operation. These measurements include: 

   - CLK0 MMCM jitter 

   - MMCM accuracy (phase offset) 

   - MMCM phase shift resolution 

   - These measurements do not include package or clock tree skew. 

2. This parameter indicates the total sampling error of the Virtex-7 T and XT FPGAs DDR input registers, measured across voltage, temperature, and process. The characterization methodology uses the BUFIO clock network and IDELAY to capture the DDR input registers’ edges of operation. These measurements do not include package or clock tree skew. 

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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

## **Additional Package Parameter Guidelines** 

The parameters in this section provide the necessary values for calculating timing budgets for Virtex-7 T and XT FPGA clock transmitter and receiver data-valid windows. 

_Table  52:_ **Package Skew** 

|**Symbol**|**Description**|**Device**|**Package**|**Value**|**Units**|
|---|---|---|---|---|---|
|TPKGSKEW|Package Skew(1)|XC7V585T|FFG1157|232|ps|
||||FFG1761|255|ps|
|||XC7V2000T|FHG1761|308|ps|
||||FLG1925|266|ps|
|||XC7VX330T|FFG1157|170|ps|
||||FFG1761|270|ps|
|||XC7VX415T|FFG1157|203|ps|
||||FFG1158|237|ps|
||||FFG1927|183|ps|
|||XC7VX485T|FFG1157|191|ps|
||||FFG1158|209|ps|
||||FFG1761|274|ps|
||||FFG1927|209|ps|
||||FFG1930|304|ps|
|||XC7VX550T|FFG1158|217|ps|
||||FFG1927|254|ps|
|||XC7VX690T|FFG1157|239|ps|
||||FFG1158|217|ps|
||||FFG1761|284|ps|
||||FFG1926|238|ps|
||||FFG1927|254|ps|
||||FFG1930|287|ps|
|||XC7VX980T|FFG1926|242|ps|
||||FFG1928|199|ps|
||||FFG1930|243|ps|
|||XC7VX1140T|FLG1926|271|ps|
||||FLG1928|216|ps|
||||FLG1930|279|ps|
|||XQ7V585T|RF1157|232|ps|
||||RF1761|255|ps|
|||XQ7VX330T|RF1157|170|ps|
||||RF1761|270|ps|
|||XQ7VX485T|RF1761|274|ps|
||||RF1930|304|ps|



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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  52:_ **Package Skew** _**(Cont’d)**_ 

|**Symbol**|**Description**|**Device**|**Package**|**Value**|**Units**|
|---|---|---|---|---|---|
|TPKGSKEW|Package Skew(1)|XQ7VX690T|RF1157|239|ps|
||||RF1158|217|ps|
||||RF1761|284|ps|
||||RF1930|287|ps|
|||XQ7VX980T|RF1930|287|ps|



## **Notes:** 

1. These values represent the worst-case skew between any two SelectIO resources in the package: shortest delay to longest delay from die pad to ball. 

2. Package delay information is available for these device/package combinations. This information can be used to deskew the package. 

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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

## **GTX Transceiver Specifications** 

## **GTX Transceiver DC Input and Output Levels** 

Table 53 summarizes the DC specifications of the GTX transceivers in Virtex-7 T and XT FPGAs. Consult the _7 Series FPGAs GTX/GTH Transceiver User Guide_ (UG476) for further details. 

_Table  53:_ **GTX Transceiver DC Specifications** 

|**Symbol**|**DC Parameter**|**Conditions**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|DVPPOUT|Differential peak-to-peak output<br>voltage(1)|Transmitter output swing is set to<br>maximum setting|1000|–|–|mV|
|VCMOUTDC|DC common mode output<br>voltage.|Equation based|VMGTAVTT– DVPPOUT/4|||mV|
|ROUT|Differential output resistance||–|100|–|Ω|
|TOSKEW|Transmitter output pair (TXP and TXN) intra-pair skew||–|2|12|ps|
|DVPPIN|Differential peak-to-peak input<br>voltage (external AC coupled)|>10.3125 Gb/s|150|–|1250|mV|
|||6.6 Gb/s to 10.3125 Gb/s|150|–|1250|mV|
|||≤6.6 Gb/s|150|–|2000|mV|
|VIN|Single-ended input voltage(2)|DC coupled<br>VMGTAVTT= 1.2V|–200|–|VMGTAVTT|mV|
|VCMIN|Common mode input voltage|DC coupled<br>VMGTAVTT= 1.2V|–|2/3 VMGTAVTT|–|mV|
|RIN|Differential input resistance||–|100|–|Ω|
|CEXT|Recommended external AC coupling capacitor(3)||–|100|–|nF|



## **Notes:** 

1. The output swing and preemphasis levels are programmable using the attributes discussed in the _7 Series FPGAs GTX/GTH Transceiver User Guide_ (UG476), and can result in values lower than reported in this table. 

2. Voltage measured at the pin referenced to ground. 

3. Other values can be used as appropriate to conform to specific protocols and standards. 

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+V P<br>Single-Ended<br>Peak-to-Peak<br>N Voltage<br>0<br>ds183_01_062414<br>**----- End of picture text -----**<br>


_Figure 3:_ **Single-Ended Peak-to-Peak Voltage** 

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**----- Start of picture text -----**<br>
+V<br>Differential<br>0  Peak-to-Peak<br>Voltage<br>–V  P–N<br>DS183_02_062414<br>**----- End of picture text -----**<br>


_Figure 4:_ **Differential Peak-to-Peak Voltage** 

_**Note:**_ In Figure 4, differential peak-to-peak voltage = single-ended peak-to-peak voltage x 2. 

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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

Table 54 summarizes the DC specifications of the clock input of the GTX transceiver. Consult the _7 Series FPGAs GTX/GTH Transceiver User Guide_ (UG476) for further details. 

_Table  54:_ **GTX Transceiver Clock DC Input Level Specification** 

|_Table  54:_ **GTX**|**Transceiver Clock DC Input Level Specification**|||||
|---|---|---|---|---|---|
|**Symbol**|**DC Parameter**|**Min**|**Typ**|**Max**|**Units**|
|VIDIFF|Differential peak-to-peak input voltage|250|–|2000|mV|
|RIN|Differential input resistance|–|100|–|Ω|
|CEXT|Required external AC coupling capacitor|–|100|–|nF|



## **GTX Transceiver Switching Characteristics** 

Consult the _7 Series FPGAs GTX/GTH Transceiver User Guide_ (UG476) for further information. 

_Table  55:_ **GTX Transceiver Performance** 

|**Symbol**|**Description**|**Output Divider**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|
||||**-3/-2G**|**-2/-2L**|**-1/-1M(1)**||
|FGTXMAX(2)|Maximum GTX transceiver data rate||12.5|10.3125|8.0|Gb/s|
|FGTXMIN(2)|Minimum GTX transceiver data rate||0.500|0.500|0.500|Gb/s|
|FGTXCRANGE|CPLL line rate range|1|3.2–6.6|||Gb/s|
|||2|1.6–3.3|||Gb/s|
|||4|0.8–1.65|||Gb/s|
|||8|0.5–0.825|||Gb/s|
|||16|N/A|||Gb/s|
|FGTXQRANGE1|QPLL line rate range 1|1|5.93–8.0|5.93–8.0|5.93–8.0|Gb/s|
|||2|2.965–4.0|2.965–4.0|2.965–4.0|Gb/s|
|||4|1.4825–2.0|1.4825–2.0|1.4825–2.0|Gb/s|
|||8|0.74125–1.0|0.74125–1.0|0.74125–1.0|Gb/s|
|||16|N/A|N/A|N/A|Gb/s|
|FGTXQRANGE2|QPLL line rate range 2(3)|1|9.8–12.5|9.8–10.3125|N/A|Gb/s|
|||2|4.9–6.25|4.9–5.15625|N/A|Gb/s|
|||4|2.45–3.125|2.45–2.578125|N/A|Gb/s|
|||8|1.225–1.5625|1.225–1.2890625|N/A|Gb/s|
|||16|0.6125–0.78125|0.6125–0.64453125|N/A|Gb/s|
|FGCPLLRANGE|GTX transceiver CPLL frequency range||1.6–3.3|1.6–3.3|1.6–3.3|GHz|
|FGQPLLRANGE1|GTX transceiver QPLL frequency range 1||5.93–8.0|5.93–8.0|5.93–8.0|GHz|
|FGQPLLRANGE2|GTX transceiver QPLL frequency range 2||9.8–12.5|9.8–10.3125|N/A|GHz|



## **Notes:** 

1. The -1 speed grade requires a 4-byte internal data width for operation above 5.0 Gb/s. A -1 speed grade with VCCINT = 0.9V, as described in the _Lowering Power using the Voltage Identification Bit_ application note (XAPP555), requires a 4-byte internal data width for operation above 3.8 Gb/s. 

2. Data rates between 8.0 Gb/s and 9.8 Gb/s are not available. 

3. For QPLL line rate range 2, the maximum line rate with the divider N set to 66 is 10.3125Gb/s. 

_Table  56:_ **GTX Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics** 

|**Symbol**|**Description**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|
|||**-3/-2G**|**-2/-2L**|**-1/-1M**||
|FGTXDRPCLK|GTXDRPCLK maximum frequency|175.01|175.01|156.25|MHz|



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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  57:_ **GTX Transceiver Reference Clock Switching Characteristics** 

|_Table  57:_|**GTX Transceiver Reference Clock**|**Switching Characteristics**|||||
|---|---|---|---|---|---|---|
|**Symbol**|**Description**|**Conditions**|**All Speed Grades**|||**Units**|
||||**Min**|**Typ**|**Max**||
|FGCLK|Reference clock frequency range|-3 speed grade|60|–|700|MHz|
|||All other speed grades|60|–|670|MHz|
|TRCLK|Reference clock rise time|20% – 80%|–|200|–|ps|
|TFCLK|Reference clock fall time|80% – 20%|–|200|–|ps|
|TDCREF|Reference clock duty cycle|Transceiver PLL only|40|50|60|%|



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T RCLK<br>80%<br>20%<br>T FCLK<br>**----- End of picture text -----**<br>


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ds183_03_021611<br>**----- End of picture text -----**<br>


_Figure 5:_ **Reference Clock Timing Parameters** 

_Table  58:_ **GTX Transceiver PLL/Lock Time Adaptation** 

|**Symbol**|**Description**|**Conditions**|**All Speed Grades**|**All Speed Grades**|**All Speed Grades**|**Units**|
|---|---|---|---|---|---|---|
||||**Min**|**Typ**|**Max**||
|TLOCK|Initial PLL lock||–|–|1|ms|
|TDLOCK|Clock recovery phase acquisition and<br>adaptation time for decision feedback<br>equalizer (DFE).|After the PLL is locked to the<br>reference clock, this is the time it<br>takes to lock the clock data<br>recovery (CDR) to the data<br>present at the input.|–|50,000|37 x106|UI|
||Clock recovery phase acquisition and<br>adaptation time for low-power mode<br>(LPM) when the DFE is disabled.||–|50,000|2.3 x106|UI|



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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  59:_ **GTX Transceiver User Clock Switching Characteristics[(1)(2)]** 

|**Symbol**|**Description**|**Data Width Conditions**|**Data Width Conditions**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|---|
|||**Internal Logic**|**Interconnect Logic**|**-3/-2G(3)**|**-2/-2L(3)**|**-1/-1M(4)**||
|FTXOUT|TXOUTCLK maximum frequency|||412.500|412.500|312.500|MHz|
|FRXOUT|RXOUTCLK maximum frequency|||412.500|412.500|312.500|MHz|
|FTXIN|TXUSRCLK maximum frequency|16-bit|16-bit and 32-bit|412.500|412.500|312.500|MHz|
|||32-bit|32-bit|390.625|322.266|250.000|MHz|
|FRXIN|RXUSRCLK maximum frequency|16-bit|16-bit and 32-bit|412.500|412.500|312.500|MHz|
|||32-bit|32-bit|390.625|322.266|250.000|MHz|
|FTXIN2|TXUSRCLK2 maximum frequency|16-bit|16-bit|412.500|412.500|312.500|MHz|
|||16-bit and 32-bit|32-bit|390.625|322.266|250.000|MHz|
|||32-bit|64-bit|195.313|161.133|125.000|MHz|
|FRXIN2|RXUSRCLK2 maximum frequency|16-bit|16-bit|412.500|412.500|312.500|MHz|
|||16-bit and 32-bit|32-bit|390.625|322.266|250.000|MHz|
|||32-bit|64-bit|195.313|161.133|125.000|MHz|



## **Notes:** 

1. Clocking must be implemented as described in the _7 Series FPGAs GTX/GTH Transceiver User Guide_ (UG476). 

2. These frequencies are not supported for all possible transceiver configurations. 

3. For speed grades -3, -2, -2L, and -2G, a 16-bit datapath can only be used for speeds less than 6.6 Gb/s. 

4. For speed grade -1, a 16-bit datapath can only be used for speeds less than 5.0 Gb/s. For speed grade -1C with VCCINT = 0.9V, as described in the _Lowering Power using the Voltage Identification Bit_ application note (XAPP555), a 16-bit datapath can only be used for speeds less than 3.8 Gb/s. 

_Table  60:_ **GTX Transceiver Transmitter Switching Characteristics** 

|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|FGTXTX|Serial data rate range||0.500|–|FGTXMAX|Gb/s|
|TRTX|TX rise time|20%–80%|–|40|–|ps|
|TFTX|TX fall time|80%–20%|–|40|–|ps|
|TLLSKEW|TX lane-to-lane skew(1)||–|–|500|ps|
|VTXOOBVDPP|Electrical idle amplitude||–|–|15|mV|
|TTXOOBTRANSITION|Electrical idle transition time||–|–|140|ns|
|TJ12.5|Total jitter(2)(4)|12.5 Gb/s|–|–|0.28|UI|
|DJ12.5|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ11.18|Total jitter(2)(4)|11.18 Gb/s|–|–|0.28|UI|
|DJ11.18|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ10.3125|Total jitter(2)(4)|10.3125 Gb/s|–|–|0.28|UI|
|DJ10.3125|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ9.953|Total jitter(2)(4)|9.953 Gb/s|–|–|0.28|UI|
|DJ9.953|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ9.8|Total jitter(2)(4)|9.8 Gb/s|–|–|0.28|UI|
|DJ9.8|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ8.0|Total jitter(2)(4)|8.0 Gb/s|–|–|0.30|UI|
|DJ8.0|Deterministic jitter(2)(4)||–|–|0.15|UI|
|TJ6.6_QPLL|Total jitter(2)(4)|6.6 Gb/s|–|–|0.28|UI|
|DJ6.6_QPLL|Deterministic jitter(2)(4)||–|–|0.17|UI|



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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  60:_ **GTX Transceiver Transmitter Switching Characteristics** _**(Cont’d)**_ 

|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|TJ6.6_CPLL|Total jitter(3)(4)|6.6 Gb/s|–|–|0.30|UI|
|DJ6.6_CPLL|Deterministic jitter(3)(4)||–|–|0.15|UI|
|TJ5.0|Total jitter(3)(4)|5.0 Gb/s|–|–|0.30|UI|
|DJ5.0|Deterministic jitter(3)(4)||–|–|0.15|UI|
|TJ4.25|Total jitter(3)(4)|4.25 Gb/s|–|–|0.30|UI|
|DJ4.25|Deterministic jitter(3)(4)||–|–|0.15|UI|
|TJ3.75|Total jitter(3)(4)|3.75 Gb/s|–|–|0.30|UI|
|DJ3.75|Deterministic jitter(3)(4)||–|–|0.15|UI|
|TJ3.20|Total jitter(3)(4)|3.20 Gb/s(5)|–|–|0.20|UI|
|DJ3.20|Deterministic jitter(3)(4)||–|–|0.10|UI|
|TJ3.20L|Total jitter(3)(4)|3.20 Gb/s(6)|–|–|0.32|UI|
|DJ3.20L|Deterministic jitter(3)(4)||–|–|0.16|UI|
|TJ2.5|Total jitter(3)(4)|2.5 Gb/s(7)|–|–|0.20|UI|
|DJ2.5|Deterministic jitter(3)(4)||–|–|0.08|UI|
|TJ1.25|Total jitter(3)(4)|1.25 Gb/s(8)|–|–|0.15|UI|
|DJ1.25|Deterministic jitter(3)(4)||–|–|0.06|UI|
|TJ500|Total jitter(3)(4)|500 Mb/s|–|–|0.10|UI|
|DJ500|Deterministic jitter(3)(4)||–|–|0.03|UI|



## **Notes:** 

1. Using same REFCLK input with TX phase alignment enabled for up to 12 consecutive transmitters (three fully populated GTX Quads). 

2. Using QPLL_FBDIV = 40, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations. 

3. Using CPLL_FBDIV = 2, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations. 

4. All jitter values are based on a bit-error ratio of 1e[-12] . 

5. CPLL frequency at 3.2 GHz and TXOUT_DIV = 2. 

6. CPLL frequency at 1.6 GHz and TXOUT_DIV = 1. 

7. CPLL frequency at 2.5 GHz and TXOUT_DIV = 2. 

8. CPLL frequency at 2.5 GHz and TXOUT_DIV = 4. 

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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  61:_ **GTX Transceiver Receiver Switching Characteristics** 

|**Symbol**|**Description**|**Description**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|FGTXRX|Serial data rate||0.500|–|FGTXMAX|Gb/s|
|TRXELECIDLE|Time for RXELECIDLE to respond to loss or restoration of data||–|10|–|ns|
|RXOOBVDPP|OOB detect threshold peak-to-peak||60|–|150|mV|
|RXSST|Receiver spread-spectrum<br>tracking(1)|Modulated @ 33 kHz|–5000|–|0|ppm|
|RXRL|Run length (CID)||–|–|512|UI|
|RXPPMTOL|Data/REFCLK PPM offset<br>tolerance|Bit rates≤6.6 Gb/s|–1250|–|1250|ppm|
|||Bit rates>6.6 Gb/s and<br>≤8.0 Gb/s|–700|–|700|ppm|
|||Bit rates>8.0 Gb/s|–200|–|200|ppm|
|**SJ Jitter Tolerance(2)**|||||||
|JT_SJ12.5|Sinusoidal jitter (QPLL)(3)|12.5 Gb/s|0.3|–|–|UI|
|JT_SJ11.18|Sinusoidal jitter (QPLL)(3)|11.18 Gb/s|0.3|–|–|UI|
|JT_SJ10.32|Sinusoidal jitter (QPLL)(3)|10.32 Gb/s|0.3|–|–|UI|
|JT_SJ9.95|Sinusoidal jitter (QPLL)(3)|9.95 Gb/s|0.3|–|–|UI|
|JT_SJ9.8|Sinusoidal jitter (QPLL)(3)|9.8 Gb/s|0.3|–|–|UI|
|JT_SJ8.0|Sinusoidal jitter (QPLL)(3)|8.0 Gb/s|0.44|–|–|UI|
|JT_SJ6.6_QPLL|Sinusoidal jitter (QPLL)(3)|6.6 Gb/s|0.48|–|–|UI|
|JT_SJ6.6_CPLL|Sinusoidal jitter (CPLL)(3)|6.6 Gb/s|0.44|–|–|UI|
|JT_SJ5.0|Sinusoidal jitter (CPLL)(3)|5.0 Gb/s|0.44|–|–|UI|
|JT_SJ4.25|Sinusoidal jitter (CPLL)(3)|4.25 Gb/s|0.44|–|–|UI|
|JT_SJ3.75|Sinusoidal jitter (CPLL)(3)|3.75 Gb/s|0.44|–|–|UI|
|JT_SJ3.2|Sinusoidal jitter (CPLL)(3)|3.2 Gb/s(4)|0.45|–|–|UI|
|JT_SJ3.2L|Sinusoidal jitter (CPLL)(3)|3.2 Gb/s(5)|0.45|–|–|UI|
|JT_SJ2.5|Sinusoidal jitter (CPLL)(3)|2.5 Gb/s(6)|0.5|–|–|UI|
|JT_SJ1.25|Sinusoidal jitter (CPLL)(3)|1.25 Gb/s(7)|0.5|–|–|UI|
|JT_SJ500|Sinusoidal jitter (CPLL)(3)|500 Mb/s|0.4|–|–|UI|
|**SJ Jitter Tolerance with Stressed Eye(2)**|||||||
|JT_TJSE3.2|Total jitter with stressed eye(8)|3.2 Gb/s|0.70|–|–|UI|
|JT_TJSE6.6||6.6 Gb/s|0.70|–|–|UI|
|JT_SJSE3.2|Sinusoidal jitter with stressed<br>eye(8)|3.2 Gb/s|0.1|–|–|UI|
|JT_SJSE6.6||6.6 Gb/s|0.1|–|–|UI|



## **Notes:** 

1. Using RXOUT_DIV = 1, 2, and 4. 

2. All jitter values are based on a bit error ratio of 1e[–12] . 

3. The frequency of the injected sinusoidal jitter is 80 MHz. 

4. CPLL frequency at 3.2 GHz and RXOUT_DIV = 2. 

5. CPLL frequency at 1.6 GHz and RXOUT_DIV = 1. 

6. CPLL frequency at 2.5 GHz and RXOUT_DIV = 2. 

7. CPLL frequency at 2.5 GHz and RXOUT_DIV = 4. 

8. Composite jitter with RX in LPM or DFE mode. 

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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

## **GTX Transceiver Protocol Jitter Characteristics** 

For Table 62 through Table 67, the _7 Series FPGAs GTX/GTH Transceiver User Guide_ (UG476) contains recommended settings for optimal usage of protocol specific characteristics. 

_Table  62:_ **Gigabit Ethernet Protocol Characteristics (GTX Transceivers)** 

|**Description**|**Line Rate (Mb/s)**|**Min**|**Max**|**Units**|
|---|---|---|---|---|
|**Gigabit Ethernet Transmitter Jitter Generation**|||||
|Total transmitter jitter (T_TJ)|1250|–|0.24|UI|
|**Gigabit Ethernet Receiver High Frequency Jitter Tolerance**|||||
|Total receiver jitter tolerance|1250|0.749|–|UI|



## _Table  63:_ **XAUI Protocol Characteristics (GTX Transceivers)** 

|**Description**|**Line Rate (Mb/s)**|**Min**|**Max**|**Units**|
|---|---|---|---|---|
|**XAUI Transmitter Jitter Generation**|||||
|Total transmitter jitter (T_TJ)|3125|–|0.35|UI|
|**XAUI Receiver High Frequency Jitter Tolerance**|||||
|Total receiver jitter tolerance|3125|0.65|–|UI|



_Table  64:_ **PCI Express Protocol Characteristics (GTX Transceivers)[(1)]** 

|**Standard**|**Description**|**Description**|**Line Rate (Mb/s)**|**Min**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|**PCI Express Transmitter Jitter Generation**|||||||
|PCI Express Gen 1|Total transmitter jitter||2500|–|0.25|UI|
|PCI Express Gen 2|Total transmitter jitter||5000|–|0.25|UI|
|PCI Express Gen 3|Total transmitter jitter uncorrelated||8000|–|31.25|ps|
||Deterministic transmitter jitter uncorrelated|||–|12|ps|
|**PCI Express Receiver High Frequency Jitter Tolerance**|||||||
|PCI Express Gen 1|Total receiver jitter tolerance||2500|0.65|–|UI|
|PCI Express Gen 2(2)|Receiver inherent timing error||5000|0.40|–|UI|
||Receiver inherent deterministic timing error|||0.30|–|UI|
|PCI Express Gen 3|Receiver sinusoidal jitter<br>tolerance|0.03 MHz–1.0 MHz|8000|1.00|–|UI|
|||1.0 MHz–10 MHz||Note 3|–|UI|
|||10 MHz–100 MHz||0.10|–|UI|



## **Notes:** 

1. Tested per card electromechanical (CEM) methodology. 

2. Using common REFCLK. 

3. Between 1 MHz and 10 MHz the minimum sinusoidal jitter roll-off with a slope of 20dB/decade. 

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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  65:_ **CEI-6G and CEI-11G Protocol Characteristics (GTX Transceivers)** 

|**Description**|**Line Rate (Mb/s)**|**Interface**|**Min**|**Max**|**Units**|
|---|---|---|---|---|---|
|**CEI-6G Transmitter Jitter Generation**||||||
|Total transmitter jitter(1)|4976–6375|CEI-6G-SR|–|0.3|UI|
|||CEI-6G-LR|–|0.3|UI|
|**CEI-6G Receiver High Frequency Jitter Tolerance**||||||
|Total receiver jitter tolerance(1)|4976–6375|CEI-6G-SR|0.6|–|UI|
|||CEI-6G-LR|0.95|–|UI|
|**CEI-11G Transmitter Jitter Generation**||||||
|Total transmitter jitter(2)|9950–11100|CEI-11G-SR|–|0.3|UI|
|||CEI-11G-LR/MR|–|0.3|UI|
|**CEI-11G Receiver High Frequency Jitter Tolerance**||||||
|Total receiver jitter tolerance(2)|9950–11100|CEI-11G-SR|0.65|–|UI|
|||CEI-11G-MR|0.65|–|UI|
|||CEI-11G-LR|0.825|–|UI|



## **Notes:** 

1. Tested at most commonly used line rate of 6250 Mb/s using 390.625 MHz reference clock. 

2. Tested at line rate of 9950 Mb/s using 155.46875 MHz reference clock and 11100 Mb/s using 173.4375 MHz reference clock. 

_Table  66:_ **SFP+ Protocol Characteristics (GTX Transceivers)** 

|**Description**|**Line Rate (Mb/s)**|**Min**|**Max**|**Units**|
|---|---|---|---|---|
|**SFP+ Transmitter Jitter Generation**|||||
|Total transmitter jitter|9830.40(1)|–|0.28|UI|
||9953.00||||
||10312.50||||
||10518.75||||
||11100.00||||
|**SFP+ Receiver Frequency Jitter Tolerance**|||||
|Total receiver jitter tolerance|9830.40(1)|0.7|–|UI|
||9953.00||||
||10312.50||||
||10518.75||||
||11100.00||||



## **Notes:** 

1. Line rated used for CPRI over SFP+ applications. 

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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  67:_ **CPRI Protocol Characteristics (GTX Transceivers)** 

|**Description**|**Line Rate (Mb/s)**|**Min**|**Max**|**Units**|
|---|---|---|---|---|
|**CPRI Transmitter Jitter Generation**|||||
|Total transmitter jitter|614.4|–|0.35|UI|
||1228.8|–|0.35|UI|
||2457.6|–|0.35|UI|
||3072.0|–|0.35|UI|
||4915.2|–|0.3|UI|
||6144.0|–|0.3|UI|
||9830.4|–|Note 1|UI|
|**CPRI Receiver Frequency Jitter Tolerance**|||||
|Total receiver jitter tolerance|614.4|0.65|–|UI|
||1228.8|0.65|–|UI|
||2457.6|0.65|–|UI|
||3072.0|0.65|–|UI|
||4915.2|0.95|–|UI|
||6144.0|0.95|–|UI|
||9830.4|Note 1|–|UI|



## **Notes:** 

1. Tested per SFP+ specification, see Table 66. 

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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

## **GTH Transceiver Specifications** 

## **GTH Transceiver DC Input and Output Levels** 

Table 68 summarizes the DC specifications of the GTH transceivers in Virtex-7 T and XT FPGAs. Consult the _7 Series FPGAs GTX/GTH Transceiver User Guide_ (UG476) for further details. 

_Table  68:_ **GTH Transceiver DC Specifications** 

|**Symbol**|**DC Parameter**|**Conditions**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|DVPPIN|Differential peak-to-peak input<br>voltage (external AC coupled)|>10.3125 Gb/s|150|–|1250|mV|
|||6.6 Gb/s to 10.3125 Gb/s|150|–|1250|mV|
|||≤6.6 Gb/s|150|–|2000|mV|
|VIN|Single-ended input voltage(1)|DC coupled<br>VMGTAVTT= 1.2V|–400|–|VMGTAVTT|mV|
|VCMIN|Common mode input voltage|DC coupled<br>VMGTAVTT= 1.2V|–|2/3 VMGTAVTT|–|mV|
|DVPPOUT|Differential peak-to-peak output<br>voltage(2)|Transmitter output swing is set to<br>1010|800|–|–|mV|
|VCMOUTDC|Common mode output voltage:<br>DC coupled|Equation based|VMGTAVTT– DVPPOUT/4|||mV|
|VCMOUTAC|Common mode output voltage:<br>AC coupled|Equation based|VMGTAVTT– DVPPOUT/2|||mV|
|RIN|Differential input resistance||–|100|–|Ω|
|ROUT|Differential output resistance||–|100|–|Ω|
|TOSKEW|Transmitter output pair (TXP and TXN) intra-pair skew||–|–|10|ps|
|CEXT|Recommended external AC coupling capacitor(3)||–|100|–|nF|



## **Notes:** 

1. Voltage measured at the pin referenced to ground. 

2. The output swing and preemphasis levels are programmable using the attributes discussed in the _7 Series FPGAs GTX/GTH Transceiver User Guide_ (UG476), and can result in values lower than reported in this table. 

3. Other values can be used as appropriate to conform to specific protocols and standards. 

**==> picture [529 x 73] intentionally omitted <==**

**----- Start of picture text -----**<br>
+V P<br>Single-Ended<br>Peak-to-Peak<br>N Voltage<br>0<br>ds183_01_062414<br>**----- End of picture text -----**<br>


_Figure 6:_ **Single-Ended Peak-to-Peak Voltage** 

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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

**==> picture [515 x 108] intentionally omitted <==**

**----- Start of picture text -----**<br>
+V<br>Differential<br>0  Peak-to-Peak<br>Voltage<br>–V  P–N<br>DS183_02_062414<br>**----- End of picture text -----**<br>


_Figure 7:_ **Differential Peak-to-Peak Voltage** 

_**Note:**_ In Figure 7, differential peak-to-peak voltage = single-ended peak-to-peak voltage x 2. 

Table 69 summarizes the DC specifications of the clock input of the GTH transceiver. Consult the _7 Series FPGAs GTX/GTH Transceiver User Guide_ (UG476) for further details. 

_Table  69:_ **GTH Transceiver Clock DC Input Level Specification** 

|_Table  69:_ **GTH**|**Transceiver Clock DC Input Level Specification**|||||
|---|---|---|---|---|---|
|**Symbol**|**DC Parameter**|**Min**|**Typ**|**Max**|**Units**|
|VIDIFF|Differential peak-to-peak input voltage|350|–|2000|mV|
|RIN|Differential input resistance|–|100|–|Ω|
|CEXT|Required external AC coupling capacitor|–|100|–|nF|



## **GTH Transceiver Switching Characteristics** 

Consult the _7 Series FPGAs GTX/GTH Transceiver User Guide_ (UG476) for further information. 

_Table  70:_ **GTH Transceiver Performance** 

|**Symbol**|**Description**|**Output Divider**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|
||||**-3E/-2GE**|**-2(C/I)/-2LE**|**-1(C/I/M)(1)**||
|FGTHMAX|Maximum GTH transceiver data rate||13.1|11.3|8.5|Gb/s|
|FGTHMIN|Minimum GTH transceiver data rate||0.500|0.500|0.500|Gb/s|
|FGTHCRANGE|CPLL line rate range|1|3.2–10.3125||3.2–8.0|Gb/s|
|||2|1.6–5.16||1.6–4.0|Gb/s|
|||4|0.8–2.58||0.8–2.0|Gb/s|
|||8|0.5–1.29||0.5–1.0|Gb/s|
|||16|N/A|||Gb/s|
|FGTHQRANGE1|QPLL line rate range 1|1|8.0–11.85|8.0–11.3|8.0–8.5|Gb/s|
|||2|4.0–5.925|4.0–5.925|4.0–4.25|Gb/s|
|||4|2.0–2.9625|2.0–2.9625|2.0–2.125|Gb/s|
|||8|1.0–1.48125|1.0–1.48125|1.0–1.0625|Gb/s|
|||16|0.5–0.740625|0.5–0.740625|0.5–0.53125|Gb/s|
|FGTHQRANGE2|QPLL line rate range 2|1|11.85–13.1|N/A||Gb/s|
|||2|5.925–6.55|5.925–6.25|N/A|Gb/s|
|||4|2.9625–3.275|2.9625–3.125|N/A|Gb/s|
|||8|1.48125–1.63|1.48125–1.5625|N/A|Gb/s|
|||16|0.740625–0.81875|0.740625–0.78125|N/A|Gb/s|
|FGCPLLRANGE|GTH transceiver CPLL frequency range||1.6–5.16||1.6–4.0|GHz|



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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  70:_ **GTH Transceiver Performance** _**(Cont’d)**_ 

|**Symbol**|**Description**|**Output Divider**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|
||||**-3E/-2GE**|**-2(C/I)/-2LE**|**-1(C/I/M)(1)**||
|FGQPLLRANGE1|GTH transceiver QPLL frequency range 1||8.0–11.85|8.0–11.85|8.0–8.5|GHz|
|FGQPLLRANGE2|GTH transceiver QPLL frequency range 2||11.85–13.1|11.85–12.5|N/A|GHz|



## **Notes:** 

1. The -1 speed grade requires a 4-byte internal data width for operation above 5.0 Gb/s. A -1 speed grade with VCCINT = 0.9V, as described in the _Lowering Power using the Voltage Identification Bit_ application note (XAPP555), requires a 4-byte internal data width for operation above 3.8 Gb/s. 

## _Table  71:_ **GTH Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics** 

|**Symbol**|**Description**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|
|||**-3/-2G**|**-2L**|**-2**|**-1/-1M**||
|FGTHDRPCLK|GTHDRPCLK maximum frequency|175.01|175.01|175.01|156.25|MHz|



_Table  72:_ **GTH Transceiver Reference Clock Switching Characteristics** 

|**Symbol**|**Description**|**Conditions**|**All Speed Grades**|**All Speed Grades**|**All Speed Grades**|**Units**|
|---|---|---|---|---|---|---|
||||**Min**|**Typ**|**Max**||
|FGCLK|Reference clock frequency range||60|–|820|MHz|
|TRCLK|Reference clock rise time|20% – 80%|–|200|–|ps|
|TFCLK|Reference clock fall time|80% – 20%|–|200|–|ps|
|TDCREF|Reference clock duty cycle|Transceiver PLL only|40|50|60|%|



**==> picture [329 x 86] intentionally omitted <==**

**----- Start of picture text -----**<br>
T RCLK<br>80%<br>20%<br>T FCLK<br>**----- End of picture text -----**<br>


**==> picture [42 x 5] intentionally omitted <==**

**----- Start of picture text -----**<br>
ds183_03_021611<br>**----- End of picture text -----**<br>


_Figure 8:_ **Reference Clock Timing Parameters** 

_Table  73:_ **GTH Transceiver PLL/Lock Time Adaptation** 

|**Symbol**|**Description**|**Conditions**|**All Speed Grades**|**All Speed Grades**|**All Speed Grades**|**Units**|
|---|---|---|---|---|---|---|
||||**Min**|**Typ**|**Max**||
|TLOCK|Initial PLL lock||–|–|1|ms|
|TDLOCK|Clock recovery phase acquisition and<br>adaptation time for decision feedback<br>equalizer (DFE).|After the PLL is locked to the<br>reference clock, this is the time it<br>takes to lock the clock data<br>recovery (CDR) to the data<br>present at the input.|–|50,000|37 x106|UI|
||Clock recovery phase acquisition and<br>adaptation time for low-power mode<br>(LPM) when the DFE is disabled.||–|50,000|2.3 x106|UI|



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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  74:_ **GTH Transceiver User Clock Switching Characteristics[(1)]** 

|**Symbol**|**Description**|**Data Width Conditions**|**Data Width Conditions**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|---|
|||**Internal Logic**|**Interconnect Logic**|**-3E/-2GE(2)**|**-2(C/I)/-2LE(2)**|**-1(C/I/M)(3)**||
|FTXOUT|TXOUTCLK maximum frequency|||412.500|412.500|312.500|MHz|
|FRXOUT|RXOUTCLK maximum frequency|||412.500|412.500|312.500|MHz|
|FTXIN|TXUSRCLK<br>maximum frequency|16-bit|16-bit and 32-bit|412.500|412.500|312.500|MHz|
|||32-bit|32-bit|409.375|353.125|265.625|MHz|
|FRXIN|RXUSRCLK<br>maximum frequency|16-bit|16-bit and 32-bit|412.500|412.500|312.500|MHz|
|||32-bit|32-bit|409.375|353.125|265.625|MHz|
|FTXIN2|TXUSRCLK2<br>maximum frequency|16-bit|16-bit|412.500|412.500|312.500|MHz|
|||16-bit and 32-bit|32-bit|409.375|353.125|265.625|MHz|
|||32-bit|64-bit|204.688|176.563|132.813|MHz|
|FRXIN2|RXUSRCLK2<br>maximum frequency|16-bit|16-bit|412.500|412.500|312.500|MHz|
|||16-bit and 32-bit|32-bit|409.375|353.125|265.625|MHz|
|||32-bit|64-bit|204.688|176.563|132.813|MHz|



## **Notes:** 

1. Clocking must be implemented as described in the _7 Series FPGAs GTX/GTH Transceiver User Guide_ (UG476). 

2. For speed grades -3E, -2GE, -2C, -2I, and -2LE, a 16-bit datapath can only be used for line rates less than 6.6 Gb/s. 

3. For speed grade -1 with VCCINT = 0.9V, as described in the _Lowering Power using the Voltage Identification Bit_ application note (XAPP555), a 16-bit datapath can only be used for line rates less than 3.8 Gb/s. For speed grade -1 with VCCINT = 1.0V, a 16-bit datapath can only be used for line rates less than 5.0 Gb/s. 

_Table  75:_ **GTH Transceiver Transmitter Switching Characteristics** 

|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|FGTHTX|Serial data rate range||0.500|–|FGTHMAX|Gb/s|
|TRTX|TX rise time|20%–80%|–|40|–|ps|
|TFTX|TX fall time|80%–20%|–|40|–|ps|
|TLLSKEW|TX lane-to-lane skew(1)||–|–|500|ps|
|VTXOOBVDPP|Electrical idle amplitude||–|–|15|mV|
|TTXOOBTRANSITION|Electrical idle transition time||–|–|140|ns|
|TJ13.1|Total jitter(2)(4)|13.1 Gb/s|–|–|0.3|UI|
|DJ13.1|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ12.5|Total jitter(2)(4)|12.5 Gb/s|–|–|0.28|UI|
|DJ12.5|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ11.3|Total jitter(2)(4)|11.3 Gb/s|–|–|0.28|UI|
|DJ11.3|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ10.3125_QPLL|Total jitter(2)(4)|10.3125 Gb/s|–|–|0.28|UI|
|DJ10.3125_QPLL|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ10.3125_CPLL|Total jitter(3)(4)|10.3125 Gb/s|–|–|0.33|UI|
|DJ10.3125_CPLL|Deterministic jitter(3)(4)||–|–|0.17|UI|
|TJ9.953|Total jitter(2)(4)|9.953 Gb/s|–|–|0.28|UI|
|DJ9.953|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ9.8|Total jitter(2)(4)|9.8 Gb/s|–|–|0.28|UI|
|DJ9.8|Deterministic jitter(2)(4)||–|–|0.17|UI|



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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  75:_ **GTH Transceiver Transmitter Switching Characteristics** _**(Cont’d)**_ 

|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|TJ8.0_QPLL|Total jitter(2)(4)|8.0 Gb/s|–|–|0.28|UI|
|DJ8.0_QPLL|Deterministic jitter(2)(4)||–|–|0.17|UI|
|TJ8.0_CPLL|Total jitter(3)(4)|8.0 Gb/s|–|–|0.32|UI|
|DJ8.0_CPLL|Deterministic jitter(3)(4)||–|–|0.17|UI|
|TJ6.6_CPLL|Total jitter(3)(4)|6.6 Gb/s|–|–|0.30|UI|
|DJ6.6_CPLL|Deterministic jitter(3)(4)||–|–|0.15|UI|
|TJ5.0|Total jitter(3)(4)|5.0 Gb/s|–|–|0.30|UI|
|DJ5.0|Deterministic jitter(3)(4)||–|–|0.15|UI|
|TJ4.25|Total jitter(3)(4)|4.25 Gb/s|–|–|0.30|UI|
|DJ4.25|Deterministic jitter(3)(4)||–|–|0.15|UI|
|TJ3.75|Total jitter(3)(4)|3.75 Gb/s|–|–|0.30|UI|
|DJ3.75|Deterministic jitter(3)(4)||–|–|0.15|UI|
|TJ3.20|Total jitter(3)(4)|3.20 Gb/s(5)|–|–|0.2|UI|
|DJ3.20|Deterministic jitter(3)(4)||–|–|0.1|UI|
|TJ3.20L|Total jitter(3)(4)|3.20 Gb/s(6)|–|–|0.32|UI|
|DJ3.20L|Deterministic jitter(3)(4)||–|–|0.16|UI|
|TJ2.5|Total jitter(3)(4)|2.5 Gb/s(7)|–|–|0.20|UI|
|DJ2.5|Deterministic jitter(3)(4)||–|–|0.08|UI|
|TJ1.25|Total jitter(3)(4)|1.25 Gb/s(8)|–|–|0.15|UI|
|DJ1.25|Deterministic jitter(3)(4)||–|–|0.06|UI|
|TJ500|Total jitter(3)(4)|500 Mb/s|–|–|0.1|UI|
|DJ500|Deterministic jitter(3)(4)||–|–|0.03|UI|



## **Notes:** 

1. Using same REFCLK input with TX phase alignment enabled for up to 12 consecutive transmitters (three fully populated GTH Quads). 

2. Using QPLL_FBDIV = 40, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations. 

3. Using CPLL_FBDIV = 2, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations. 4. All jitter values are based on a bit-error ratio of 1e[-12] . 

5. CPLL frequency at 3.2 GHz and TXOUT_DIV = 2. 

6. CPLL frequency at 1.6 GHz and TXOUT_DIV = 1. 

7. CPLL frequency at 2.5 GHz and TXOUT_DIV = 2. 

8. CPLL frequency at 2.5 GHz and TXOUT_DIV = 4. 

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_Table  76:_ **GTH Transceiver Receiver Switching Characteristics** 

|**Symbol**|**Description**|**Description**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|FGTHRX|Serial data rate||0.500|–|FGTHMAX|Gb/s|
|TRXELECIDLE|Time for RXELECIDLE to respond to loss or restoration of data||–|10|–|ns|
|RXOOBVDPP|OOB detect threshold peak-to-peak||60|–|150|mV|
|RXSST|Receiver spread-spectrum<br>tracking(1)|Modulated @ 33 kHz|–5000|–|0|ppm|
|RXRL|Run length (CID)||–|–|512|UI|
|RXPPMTOL|Data/REFCLK PPM offset<br>tolerance|Bit rates≤6.6 Gb/s|–1250|–|1250|ppm|
|||Bit rates>6.6 Gb/s and<br>≤8.0 Gb/s|–700|–|700|ppm|
|||Bit rates>8.0 Gb/s|–200|–|200|ppm|
|**SJ Jitter Tolerance(2)**|||||||
|JT_SJ13.1|Sinusoidal jitter (QPLL)(3)|13.1 Gb/s|0.3|–|–|UI|
|JT_SJ12.5|Sinusoidal jitter (QPLL)(3)|12.5 Gb/s|0.3|–|–|UI|
|JT_SJ11.3|Sinusoidal jitter (QPLL)(3)|11.3 Gb/s|0.3|–|–|UI|
|JT_SJ10.32_QPLL|Sinusoidal jitter (QPLL)(3)|10.32 Gb/s|0.3|–|–|UI|
|JT_SJ10.32_CPLL|Sinusoidal jitter (CPLL)(3)|10.32 Gb/s|0.3|–|–|UI|
|JT_SJ9.8|Sinusoidal jitter (QPLL)(3)|9.8 Gb/s|0.3|–|–|UI|
|JT_SJ8.0_QPLL|Sinusoidal jitter (QPLL)(3)|8.0 Gb/s|0.44|–|–|UI|
|JT_SJ8.0_CPLL|Sinusoidal jitter (CPLL)(3)|8.0 Gb/s|0.42|–|–|UI|
|JT_SJ6.6_CPLL|Sinusoidal jitter (CPLL)(3)|6.6 Gb/s|0.44|–|–|UI|
|JT_SJ5.0|Sinusoidal jitter (CPLL)(3)|5.0 Gb/s|0.44|–|–|UI|
|JT_SJ4.25|Sinusoidal jitter (CPLL)(3)|4.25 Gb/s|0.44|–|–|UI|
|JT_SJ3.75|Sinusoidal jitter (CPLL)(3)|3.75 Gb/s|0.44|–|–|UI|
|JT_SJ3.2|Sinusoidal jitter (CPLL)(3)|3.2 Gb/s(4)|0.45|–|–|UI|
|JT_SJ3.2L|Sinusoidal jitter (CPLL)(3)|3.2 Gb/s(5)|0.45|–|–|UI|
|JT_SJ2.5|Sinusoidal jitter (CPLL)(3)|2.5 Gb/s(6)|0.5|–|–|UI|
|JT_SJ1.25|Sinusoidal jitter (CPLL)(3)|1.25 Gb/s(7)|0.5|–|–|UI|
|JT_SJ500|Sinusoidal jitter (CPLL)(3)|500 Mb/s|0.4|–|–|UI|
|**SJ Jitter Tolerance with Stressed Eye(2)**|||||||
|JT_TJSE3.2|Total jitter with stressed eye(8)|3.2 Gb/s|0.70|–|–|UI|
|JT_TJSE6.6||6.6 Gb/s|0.70|–|–|UI|
|JT_SJSE3.2|Sinusoidal jitter with stressed<br>eye(8)|3.2 Gb/s|0.1|–|–|UI|
|JT_SJSE6.6||6.6 Gb/s|0.1|–|–|UI|



## **Notes:** 

1. Using RXOUT_DIV = 1, 2, and 4. 

2. All jitter values are based on a bit error ratio of 1e[–12] . 

3. The frequency of the injected sinusoidal jitter is 80 MHz. 

4. CPLL frequency at 3.2 GHz and RXOUT_DIV = 2. 

5. CPLL frequency at 1.6 GHz and RXOUT_DIV = 1. 

6. CPLL frequency at 2.5 GHz and RXOUT_DIV = 2. 

7. CPLL frequency at 2.5 GHz and RXOUT_DIV = 4. 

8. Composite jitter with RX in LPM or DFE mode. 

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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

## **GTH Transceiver Protocol Jitter Characteristics** 

For Table 77 through Table 82, the _7 Series FPGAs GTX/GTH Transceiver User Guide_ (UG476)contains recommended settings for optimal usage of protocol specific characteristics. 

_Table  77:_ **Gigabit Ethernet Protocol Characteristics (GTH Transceivers)** 

|**Description**|**Line Rate (Mb/s)**|**Min**|**Max**|**Units**|
|---|---|---|---|---|
|**Gigabit Ethernet Transmitter Jitter Generation**|||||
|Total transmitter jitter (T_TJ)|1250|–|0.24|UI|
|**Gigabit Ethernet Receiver High Frequency Jitter Tolerance**|||||
|Total receiver jitter tolerance|1250|0.749|–|UI|



## _Table  78:_ **XAUI Protocol Characteristics (GTH Transceivers)** 

|**Description**|**Line Rate (Mb/s)**|**Min**|**Max**|**Units**|
|---|---|---|---|---|
|**XAUI Transmitter Jitter Generation**|||||
|Total transmitter jitter (T_TJ)|3125|–|0.35|UI|
|**XAUI Receiver High Frequency Jitter Tolerance**|||||
|Total receiver jitter tolerance|3125|0.65|–|UI|



_Table  79:_ **PCI Express Protocol Characteristics (GTH Transceivers)[(1)]** 

|**Standard**|**Description**|**Description**|**Line Rate (Mb/s)**|**Min**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|**PCI Express Transmitter Jitter Generation**|||||||
|PCI Express Gen 1|Total transmitter jitter||2500|–|0.25|UI|
|PCI Express Gen 2|Total transmitter jitter||5000|–|0.25|UI|
|PCI Express Gen 3|Total transmitter jitter uncorrelated||8000|–|31.25|ps|
||Deterministic transmitter jitter uncorrelated|||–|12|ps|
|**PCI Express Receiver High Frequency Jitter Tolerance**|||||||
|PCI Express Gen 1|Total receiver jitter tolerance||2500|0.65|–|UI|
|PCI Express Gen 2|Receiver inherent timing error||5000|0.40|–|UI|
||Receiver inherent deterministic timing error|||0.30|–|UI|
|PCI Express Gen 3|Receiver sinusoidal jitter<br>tolerance|0.03 MHz–1.0 MHz|8000|1.00|–|UI|
|||1.0 MHz–10 MHz||Note 3|–|UI|
|||10 MHz–100 MHz||0.10|–|UI|



## **Notes:** 

1. Tested per card electromechanical (CEM) methodology. 

2. Using common REFCLK. 

3. Between 1 MHz and 10 MHz the minimum sinusoidal jitter roll-off with a slope of 20dB/decade. 

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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  80:_ **CEI-6G and CEI-11G Protocol Characteristics (GTH Transceivers)** 

|**Description**|**Line Rate (Mb/s)**|**Interface**|**Min**|**Max**|**Units**|
|---|---|---|---|---|---|
|**CEI-6G Transmitter Jitter Generation**||||||
|Total transmitter jitter(1)|4976–6375|CEI-6G-SR|–|0.3|UI|
|||CEI-6G-LR|–|0.3|UI|
|**CEI-6G Receiver High Frequency Jitter Tolerance**||||||
|Total receiver jitter tolerance(1)|4976–6375|CEI-6G-SR|0.6|–|UI|
|||CEI-6G-LR|0.95|–|UI|
|**CEI-11G Transmitter Jitter Generation**||||||
|Total transmitter jitter(2)|9950–11100|CEI-11G-SR|–|0.3|UI|
|||CEI-11G-LR/MR|–|0.3|UI|
|**CEI-11G Receiver High Frequency Jitter Tolerance**||||||
|Total receiver jitter tolerance(2)|9950–11100|CEI-11G-SR|0.65|–|UI|
|||CEI-11G-MR|0.65|–|UI|
|||CEI-11G-LR|0.825|–|UI|



## **Notes:** 

1. Tested at most commonly used line rate of 6250 Mb/s using 390.625 MHz reference clock. 

2. Tested at line rate of 9950 Mb/s using 155.46875 MHz reference clock and 11100 Mb/s using 173.4375 MHz reference clock. 

_Table  81:_ **SFP+ Protocol Characteristics (GTH Transceivers)** 

|**Description**|**Line Rate (Mb/s)**|**Min**|**Max**|**Units**|
|---|---|---|---|---|
|**SFP+ Transmitter Jitter Generation**|||||
|Total transmitter jitter|9830.40(1)|–|0.28|UI|
||9953.00||||
||10312.50||||
||10518.75||||
||11100.00||||
|**SFP+ Receiver Frequency Jitter Tolerance**|||||
|Total receiver jitter tolerance|9830.40(1)|0.7|–|UI|
||9953.00||||
||10312.50||||
||10518.75||||
||11100.00||||



## **Notes:** 

1. Line rated used for CPRI over SFP+ applications. 

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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  82:_ **CPRI Protocol Characteristics (GTH Transceivers)** 

|**Description**|**Line Rate (Mb/s)**|**Min**|**Max**|**Units**|
|---|---|---|---|---|
|**CPRI Transmitter Jitter Generation**|||||
|Total transmitter jitter|614.4|–|0.35|UI|
||1228.8|–|0.35|UI|
||2457.6|–|0.35|UI|
||3072.0|–|0.35|UI|
||4915.2|–|0.3|UI|
||6144.0|–|0.3|UI|
||9830.4|–|Note 1|UI|
|**CPRI Receiver Frequency Jitter Tolerance**|||||
|Total receiver jitter tolerance|614.4|0.65|–|UI|
||1228.8|0.65|–|UI|
||2457.6|0.65|–|UI|
||3072.0|0.65|–|UI|
||4915.2|0.95|–|UI|
||6144.0|0.95|–|UI|
||9830.4|Note 1|–|UI|



## **Notes:** 

1. Tested per SFP+ specification, see Table 81. 

## **Integrated Interface Block for PCI Express Designs Switching Characteristics** 

More information and documentation on solutions for PCI Express designs can be found at: http://www.xilinx.com/technology/protocols/pciexpress.htm 

_Table  83:_ **Maximum Performance for PCI Express Designs** 

|**Symbol**|**Description**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|
|||**-3**|**-2/-2L/-2G**|**-1/1M**||
|FPIPECLK|Pipe clock maximum frequency|250.00|250.00|250.00|MHz|
|FUSERCLK|User clock maximum frequency|500.00(1)|500.00(1)|250.00|MHz|
|FUSERCLK2|User clock 2 maximum frequency|250.00|250.00|250.00|MHz|
|FDRPCLK|DRP clock maximum frequency|250.00|250.00|250.00|MHz|



## **Notes:** 

1. PCI Express x8 Gen 2 operation is only supported in -2 and -3 speed grades for devices that have GTX transceivers. Refer to _7 Series FPGAs Integrated Block for PCI Express Product Guide_ (PG054) for specific supported core configurations. 

2. PCI Express Gen 3 operation is only supported in -2 and -3 speed grades for devices that have GTH transceivers. Refer to _Virtex-7 FPGA Gen3 Integrated Block for PCI Express v3.0_ (PG023) for specific supported core configurations. 

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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

## **XADC Specifications** 

## _Table  84:_ **XADC Specifications** 

|**Parameter**|**Symbol**|**Comments/Conditions**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|VCCADC= 1.8V ± 5%, VREFP= 1.25V, VREFN||= 0V, ADCCLK = 26 MHz, Tj= –40°C to 100°C, Typical values at Tj=+40°C|||||
|**ADC Accuracy(1)**|||||||
|Resolution|||12|–|–|Bits|
|Integral Nonlinearity(2)|INL||–|–|±3|LSBs|
|Differential Nonlinearity|DNL|No missing codes, guaranteed monotonic|–|–|±1|LSBs|
|Offset Error||Offset calibration enabled|–|–|±6|LSBs|
|Gain Error||Gain calibration disabled|–|–|±0.5|%|
|Offset Matching||Offset calibration enabled|–|–|4|LSBs|
|Gain Matching||Gain calibration disabled|–|–|0.3|%|
|Sample Rate|||–|–|1|MS/s|
|Signal to Noise Ratio(2)|SNR|FSAMPLE= 500KS/s, FIN= 20 kHz|60|–|–|dB|
|RMS Code Noise||External 1.25V reference|–|–|2|LSBs|
|||On-chip reference|–|3|–|LSBs|
|Total Harmonic Distortion(2)|THD|FSAMPLE= 500KS/s, FIN= 20 kHz|–|70|–|dB|
|**ADC Accuracy at Extended Temperatures**|||||||
|Resolution||Tj= –55°C to 125°C|10|–|–|Bits|
|Integral Nonlinearity(2)|INL|Tj= –55°C to 125°C|–|–|±1|LSB<br>(at 10 bits)|
|Differential Nonlinearity|DNL|No missing codes, guaranteed monotonic,<br>Tj= –55°C to 125°C|–|–|±1||
|**Analog Inputs**(3)|||||||
|ADC Input Ranges||Unipolar operation|0|–|1|V|
|||Bipolar operation|–0.5|–|+0.5|V|
|||Unipolar common mode range (FS input)|0|–|+0.5|V|
|||Bipolar common mode range (FS input)|+0.5|–|+0.6|V|
|Maximum External Channel Input Ranges||Adjacent channels set within these ranges<br>should not corrupt measurements on adjacent<br>channels|–0.1|–|VCCADC|V|
|Auxiliary Channel Full<br>Resolution Bandwidth|FRBW||250|–|–|kHz|
|**On-Chip Sensors**|||||||
|Temperature Sensor Error||Tj= –40°C to 100°C.|–|–|±4|°C|
|||Tj= –55°C to +125°C|–|–|±6|°C|
|Supply Sensor Error||Measurement range of VCCAUX1.8V ±5%<br>Tj= –40°C to +100°C|–|–|±1|%|
|||Measurement range of VCCAUX1.8V ±5%<br>Tj= –55°C to +125°C|–|–|±2|%|
|**Conversion Rate**(4)|||||||
|Conversion Time - Continuous|tCONV|Number of ADCCLK cycles|26|–|32|Cycles|
|Conversion Time - Event|tCONV|Number of CLK cycles|–|–|21|Cycles|
|DRP Clock Frequency|DCLK|DRP clock frequency|8|–|250|MHz|
|ADC Clock Frequency|ADCCLK|Derived from DCLK|1|–|26|MHz|



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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  84:_ **XADC Specifications** _**(Cont’d)**_ 

|**Parameter**|**Symbol**|**Comments/Conditions**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|DCLK Duty Cycle|||40|–|60|%|
|**XADC Reference**(5)|||||||
|External Reference|VREFP|Externally supplied reference voltage|1.20|1.25|1.30|V|
|On-Chip Reference||Ground VREFPpin to AGND,<br>Tj= –40°C to 100°C|1.2375|1.25|1.2625|V|



## **Notes:** 

1. Offset and gain errors are removed by enabling the XADC automatic gain calibration feature. The values are specified for when this feature is enabled. 

2. Only specified for the bitstream option XADCEnhancedLinearity = ON. 

3. For a detailed description, see the ADC chapter in the _7 Series FPGAs and Zynq-7000 AP SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter_ (UG480). 

4. For a detailed description, see the Timing chapter in the _7 Series FPGAs and Zynq-7000 AP SoC XADC Dual 12-Bit 1 MSPS Analog-toDigital Converter_ (UG480). 

5. Any variation in the reference voltage from the nominal VREFP = 1.25V and VREFN = 0V will result in a deviation from the ideal transfer function. This also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). However, for external ratiometric type applications allowing reference to vary by ±4% is permitted. On-chip reference variation is ±1%. 

## **Configuration Switching Characteristics** 

## _Table  85:_ **Configuration Switching Characteristics** 

|**Symbol**|**Description**|**Virtex-7 T and XT**<br>**Devices**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|
||||**-3**|**-2/-2L/-2G**|**-1/-1M**||
|**Power-up Timing Characteristics**|||||||
|TPL(1)|Program latency||5|5|5|ms, Max|
|TPOR(1)|Power-on reset (50ms ramp rate time)||10/50|10/50|10/50|ms, Min/Max|
||Power-on reset (1ms ramp rate time)||10/35|10/35|10/35|ms, Min/Max|
|TPROGRAM|Program pulse width||250|250|250|ns, Min|
|**CCLK Output (Master Mode)**|||||||
|TICCK|Master CCLK output delay||150|150|150|ns, Min|
|TMCCKL|Master CCLK clock Low time duty cycle||40/60|40/60|40/60|%, Min/Max|
|TMCCKH|Master CCLK clock High time duty cycle||40/60|40/60|40/60|%, Min/Max|
|FMCCK|Master CCLK frequency||100|100|100|MHz, Max|
||Master CCLK frequency for AES encrypted x16||50|50|50|MHz, Max|
|FMCCK_START|Master CCLK frequency at start of configuration||3|3|3|MHz, Typ|
|FMCCKTOL|Frequency tolerance, master mode with respect to nominal<br>CCLK.||±50|±50|±50|%, Max|
|**CCLK Input (Slave Modes)**|||||||
|TSCCKL|Slave CCLK clock minimum Low time||2.5|2.5|2.5|ns, Min|
|TSCCKH|Slave CCLK clock minimum High time||2.5|2.5|2.5|ns, Min|
|FSCCK|Slave CCLK frequency||100|100|100|MHz, Max|
|**EMCCLK Input (Master Mode)**|||||||
|TEMCCKL|External master CCLK Low time||2.5|2.5|2.5|ns, Min|
|TEMCCKH|External master CCLK High time||2.5|2.5|2.5|ns, Min|
|FEMCCK|External master CCLK frequency||100|100|100|MHz, Max|



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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  85:_ **Configuration Switching Characteristics** _**(Cont’d)**_ 

|**Symbol**|**Description**|**Virtex-7 T and XT**<br>**Devices**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|
||||**-3**|**-2/-2L/-2G**|**-1/-1M**||
|**Internal Configuration Access Port**|||||||
|FICAPCK|Internal configuration access port<br>(ICAPE2)|Master SLR ICAP<br>accessing the entire<br>device|70.00|70.00|70.00|MHz, Max|
|||SLR ICAP accessing<br>the local SLR|100.00|100.00|100.00|MHz, Max|
|||All other devices|100.00|100.00|100.00|MHz, Max|
|**Master/Slave Serial Mode Programming Switching**|||||||
|TDCCK/TCCKD|DIN setup/hold||4.0/0.0|4.0/0.0|4.0/0.0|ns, Min|
|TCCO|DOUT clock to out||8.0|8.0|8.0|ns, Max|
|**SelectMAP Mode Programming Switching**|||||||
|TSMDCCK/TSMCCKD|D[31:00] setup/hold||4.0/0.0|4.0/0.0|4.0/0.0|ns, Min|
|TSMCSCCK/TSMCCKCS|CSI_B setup/hold||4.0/0.0|4.0/0.0|4.0/0.0|ns, Min|
|TSMWCCK/TSMCCKW|RDWR_B setup/hold||10.0/0.0|10.0/0.0|10.0/0.0|ns, Min|
|TSMCKCSO|CSO_B clock to out (330Ωpull-up resistor required)||7.0|7.0|7.0|ns, Max|
|TSMCO|D[31:00] clock to out in readback||8.0|8.0|8.0|ns, Max|
|FRBCCK|Readback frequency|SLR-based|N/A|70|70|MHz, Max|
|||All other devices|100|100|100|MHz, Max|
|**Boundary-Scan Port Timing Specifications**|||||||
|TTAPTCK/TTCKTAP|TMS and TDI setup/hold|SLR-based|N/A|9.0/2.0|9.0/2.0|ns, Min|
|||All other devices|3.0/2.0|3.0/2.0|3.0/2.0|ns, Min|
|TTCKTDO|TCK falling edge to TDO output|SLR-based|N/A|17|17|ns, Max|
|||All other devices|7.0|7.0|7.0|ns, Max|
|FTCK|TCK frequency|SLR-based|N/A|20|20|MHz, Max|
|||All other devices|66|66|66|MHz, Max|
|**BPI Flash Master Mode Programming Switching**|||||||
|TBPICCO(2)|A[28:00], RS[1:0], FCS_B, FOE_B, FWE_B, ADV_B clock to out||8.5|8.5|8.5|ns, Max|
|TBPIDCC/TBPICCD|D[15:00] setup/hold||4.0/0.0|4.0/0.0|4.0/0.0|ns, Min|
|**SPI Flash Master Mode Programming Switching**|||||||
|TSPIDCC/TSPICCD|D[03:00] setup/hold||3.0/0.0|3.0/0.0|3.0/0.0|ns, Min|
|TSPICCM|MOSI clock to out||8.0|8.0|8.0|ns, Max|
|TSPICCFC|FCS_B clock to out||8.0|8.0|8.0|ns, Max|
|**STARTUPE2 Ports**|||||||
|TUSRCCLKO|STARTUPE2 USRCCLKO input to CCLK output||0.50/6.00|0.50/6.70|0.50/7.50|ns, Min/Max|
|FCFGMCLK|STARTUPE2 CFGMCLK output frequency||65.00|65.00|65.00|MHz, Typ|
|FCFGMCLKTOL|STARTUPE2 CFGMCLK output frequency tolerance||±50|±50|±50|%, Max|
|**Device DNA Access Port**|||||||
|FDNACK|DNA access port (DNA_PORT)||100.00|100.00|100.00|MHz, Max|



## **Notes:** 

1. To support longer delays in configuration, use the design solutions described in the _7 Series FPGA Configuration User Guide_ (UG470). 

2. Only during configuration, the last edge is determined by a weak pull-up/pull-down resistor in the I/O. 

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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

## **eFUSE Programming Conditions** 

Table 86 lists the programming conditions specifically for eFUSE. For more information, see the _7 Series FPGA Configuration User Guide_ (UG470). 

_Table  86:_ **eFUSE Programming Conditions[(1)]** 

|_Table  86:_ **eFUSE**|**Programming Conditions(1)**|||||
|---|---|---|---|---|---|
|**Symbol**|**Description**|**Min**|**Typ**|**Max**|**Units**|
|IFS|VCCAUXsupply current|–|–|115|mA|
|t j|Temperature range|15|–|125|°C|



## **Notes:** 

1. The FPGA must not be configured during eFUSE programming. 

## **Revision History** 

The following table shows the revision history for this document. 

|**Date**|**Version**|**Description**|
|---|---|---|
|03/01/2011|1.0|Initial Xilinx release.|
|10/05/2011|1.1|Removed the XC7V285T, XC7V450T, and XC7V855T devices from the entire data sheet. Added the<br>XC7VX330T, XC7VX415T, XC7VX550T, XC7VX690T, XC7VX980T, and XC7VX1140T devices to the<br>entire data sheet.<br>Replaced -1L with -2L throughout this data sheet. Added the extended temperature range discussion<br>topage 1. Updated Min/Max values and removed Note 5 fromTable 2. ClarifiedPower-On/Off Power<br>Supply Sequencingpower sequencing discussion including adding TVCCO2VCCAUXtoTable 8. Added<br>ICCAUX_IOand ICCBRAMtoTable 6andTable 7. Updated VICMinTable 12andTable 13. Added Note 1<br>to Table 12. UpdatedTable 86including addingNote 1. Added Table 13. Revised the reference clock<br>maximum frequency (FGCLK) inTable 57. AddedTable 59. AddedGTH Transceiver Specifications<br>section. Removed erroneous instances of HSTL_III fromTable 20. Removed the_I/O Standard_<br>_Adjustment Measurement Methodology_section. Use IBIS for more accurate information and<br>measurements. Updated TIDELAYPAT_JITinTable 28. Added TAS/TAHtoTable 30. Added<br>TRDCK_DI_WF_NC/TRCKD_DI_WF_NCand TRDCK_DI_RF/TRCKD_DI_RFtoTable 33. Completely updated<br>the specifications inTable 85. Updated MMCM_FINDUTYand added FINJITTER, TOUTJITTER, and<br>TEXTFDVARandNote 3toTable 40. Updated theAC Switching Characteristicssection. Updated the<br>Table 52package list. Updated theNotice of Disclaimer.|
|11/07/2011|1.2|Added -2G speed grade, where appropriate, throughout document.<br>Revised the VOCMspecification inTable 12. Updated theAC Switching Characteristicsbased upon the<br>ISE 13.3 v1.02 speed specification throughout document includingTable 19andTable 20. Added<br>MMCM to the symbol names of a few specifications inTable 40and PLL to the symbol names in<br>Table 41. InTable 42throughTable 49, updated the pin-to-pin description with the SSTL15 standard.<br>Updated units inTable 51.|
|02/13/2012|1.3|Updated summary description onpage 1. InTable 2, revised VCCOfor the 3.3V HR I/O banks and<br>updated Tj. Added typical numbers toTable 3. Updated the notes inTable 6. Added MGTAVCC,<br>MGTAVTT, and MGTVCCAUX power supply ramp times toTable 8. RearrangedTable 9, added<br>Mobile_DDR, HSTL_I_18, HSTL_II_18, HSUL_12, SSTL135_R, SSTL15_R, and SSTL12 and<br>removed DIFF_SSTL135, DIFF_SSTL18_I, DIFF_SSTL18_II, DIFF_HSTL_I, and DIFF_HSTL_II.<br>AddedTable 10andTable 11. Revised the specifications inTable 12andTable 13. Updated the<br>eFUSE Programming Conditionssection and removed the endurance table. Added theIO_FIFO<br>Switching Characteristicstable. Revised ICCADCand updatedNote 1inTable 84. Revised DDR LVDS<br>transmitter data width inTable 17. Updated theAC Switching Characteristicsbased upon the ISE 13.4<br>v1.03 speed specification throughout document. Removed notes fromTable 30as they are no longer<br>applicable. Updated specifications inTable 85. UpdatedNote 1inTable 39.<br>In theGTX Transceiver Specificationssection: Revised VIN, and added IDCINand IDCOUTtoTable 53.<br>Updated and added notes toTable 55. InTable 57, revised FGCLK, removed TPHASE, and added<br>TDLOCK. Revised specifications and addedNote 2toTable 59. AddedTable 60andTable 61along with<br>GTX Transceiver Protocol Jitter CharacteristicsinTable 62throughTable 67.|



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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

|**Date**|**Version**|**Description**|
|---|---|---|
|05/23/2012|1.4|Reorganized entire data sheet including addingTable 46andTable 50.<br>Updated TSOLinTable 1. Updated IBATTand added RIN_TERMtoTable 3. Added values toTable 6and<br>Table 7. UpdatedPower-On/Off Power Supply Sequencingsection with regards to GTX/GTH<br>transceivers. Updated many parameters inTable 9, including SSTL135 and SSTL135_R. Removed<br>VOXcolumn and added DIFF_HSUL_12 toTable 11. Updated VOLinTable 12. UpdatedTable 17and<br>removed notes 2 and 3. UpdatedTable 18.<br>Updated theAC Switching Characteristicssection based upon the ISE 14.1 v1.04 for the -3, -2, -2L<br>(1.0V), -1, and v1.05 for the -2L (0.9V) speed specifications throughout the document.<br>InTable 33, updatedReset Delayssection includingNote 10andNote 11. Added data for TLOCKand<br>TDLOCKinTable 57. Updated many of the XADC specifications inTable 84and addedNote 2. Updated<br>and moved_Dynamic Reconfiguration Port (DRP) for MMCM Before and After DCLK_section from<br>Table 85toTable 40andTable 41.|
|08/03/2012|1.5|Updated the descriptions, changed VINandNote 2and addedNote 4inTable 1. InTable 2, changed<br>descriptions and notes, removed Note 7, changed GTX transceiver parameters and values and added<br>Note 13andNote 14. Updated parameters inTable 3. AddedTable 4andTable 5. Updated the values<br>for inTable 7. Updated LVCMOS12 and the SSTLs inTable 9. Updated many of the specifications in<br>Table 10andTable 11.<br>Updated theAC Switching Characteristicssection, based uponTable 14, for the ISE 14.2 speed<br>specifications throughout the document with appropriate changes toTable 15andTable 16including<br>production release of the XC7VX485T in the -2 and -1 speed designations.<br>Added notes and specifications toTable 18. Updated theIOB Pad Input/Output/3-Statediscussion and<br>changedTable 21by adding TIOIBUFDISABLE.<br>Removed many of the combinatorial delay specifications and TCINCK/TCKCINfromTable 30.<br>RearrangedTable 53including moving some parameters toTable 1. AddedTable 58. Updated<br>Table 59. InTable 61, updated SJ Jitter Tolerance with Stressed Eye section,page 57andNote 8.<br>AddedNote 1,Note 2, andNote 2toTable 64. AddedNote 1andNote 2toTable 65, and line rate<br>ranges. UpdatedTable 66including addingNote 1. UpdatedTable 67including addingNote 1.<br>InTable 84updatedNote 1and added Note 4. InTable 85, updated TPORand FEMCCK.|
|09/20/2012|1.6|Removed the XC7V1500T device from data sheet. InTable 2, revised VCCINTand VCCBRAMand added<br>Note 3. Updated some of the values inTable 7. RevisedTable 15andTable 16to include production<br>release of the XC7V585T in the -2 and -1 speed designations. Added values for the XC7V585T in<br>Table 52. UpdatedNote 2inTable 60.|
|09/26/2012|1.7|RevisedTable 15andTable 16to include production release of the XC7VX485T in the -3 speed<br>designation.|
|10/19/2012|1.8|RevisedTable 15andTable 16to include production release of the XC7VX485T in the -2L (1.0V)<br>speed designation.<br>Removed -2L (0.9V) speed specifications from data sheet, this change includes edits to VCCINTand<br>VCCBRAMinTable 2, editingNote 1and removing Note 2 inTable 55. Also inTable 55, updated the<br>FGTXMAX, FGTXQRANGE1, and FGQPLLRANGE1specification for -1 speed grade from 6.6 Gb/s to<br>8.0 Gb/s. EditedNote 4inTable 59andNote 3inTable 74.|
|12/12/2012|1.9|Updated theAC Switching Characteristicssection, based uponTable 14, for the ISE 14.3 speed<br>specifications throughout the document. RevisedTable 15andTable 16to include production release<br>of the XC7V585T in the -3 and -2L(1.0V) speed designations. Updated the notes inTable 52.<br>UpdatedGTH Transceiver Specificationsincluding removal of GTH Transceiver DC Characteristics<br>section (use the XPE (download athttp://www.xilinx.com/power<br>). UpdatedTable 70and added<br>Table 73,Table 75, andTable 76. Removed Note 4 fromTable 84.|
|12/24/2012|1.10|Updated theAC Switching Characteristicssection, based uponTable 14, for the ISE 14.4 and<br>Vivado 2012.4 speed specifications throughout the document. Revised the XC7V2000T in the -1 and<br>-2 speed designationsTable 15to preliminary.<br>Added theGTH Transceiver Protocol Jitter Characteristicssection. Updated TTCKTDOand added<br>Internal Configuration Access Portsection toTable 85.|
|01/31/2013|1.11|AddedNote 2toTable 2. RevisedTable 15andTable 16to include production release of the<br>XC7V2000T in the -1 and -2 speed specifications. UpdatedNote 1inTable 37. Updated the notes in<br>Table 39,Table 42throughTable 45,Table 48, andTable 49. InTable 68, updated DVPPIN. InTable 69,<br>updated VIDIFF. Removed TLOCKand TPHASEfromTable 72. Updated TDLOCKinTable 73.|



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**Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics** 

|**Date**|**Version**|**Description**|
|---|---|---|
|03/07/2013|1.12|Updated theAC Switching Characteristicssection, based uponTable 14, for the ISE 14.5 and<br>Vivado 2013.1 speed specifications throughout the document. RevisedTable 15andTable 16to<br>include production release of the XC7VX690T.<br>Revised DVPPOUTinTable 68. Updated values inTable 69andTable 76. Removed Note 1 from<br>Table 70. Updated MMCM_FPFDMAXinTable 40and PLL_FPFDMAXinTable 41. Added skew values to<br>Table 52.|
|03/27/2013|1.13|InTable 7, added values for the XC7VX330T and XC7VX415T devices. RevisedTable 15andTable 16<br>to include production release of the XC7VX330T and XC7VX415T. InTable 18, updated the table title,<br>LPDDR2 values, and removed Note 3. Removed Note 2:_For QPLL line rate, the maximum line rate with the_<br>_divider N set to 66 is 10.3125 Gb/s_fromTable 70.|
|04/17/2013|1.14|Updated theAC Switching Characteristicssection with production release changes toTable 15and<br>Table 16for XC7VX550T for all speed specifications.<br>InTable 1, revised VIN(I/O input voltage) to match values inTable 4andTable 5, and combinedNote 4<br>with old Note 5 and then added newNote 5. Revised VINdescription and addedNote 9inTable 2.<br>Updated first 3 rows inTable 4andTable 5. Updated values and added new values toTable 7. Also<br>revised PCI33_3 voltage minimum inTable 10to match values inTable 1,Table 4, andTable 5. Added<br>Note 1toTable 12andTable 13. Throughout the data sheet (Table 31,Table 32, andTable 47)<br>removed the obvious note “A Zero “0” Hold Time listing indicates no hold time or a negative hold time.”<br>Updated and clarified USRCLK data inTable 59andTable 74.|
|05/07/2013|1.15|RevisedTable 15andTable 16for the production release of the XC7V2000T and XC7VX980T devices.|
|05/15/2013|1.16|RevisedTable 15andTable 16for the production release of the XC7VX1140T devices.|
|09/04/2013|1.17|InTable 1, updated IDCINand IDCOUTsection for cases when floating, at VMGTAVTT, or GND. Removed<br>notes fromTable 7. Updated FMAX_PREADD_MULT_NOADREG_PATDETfor -1 speed grade inTable 34. In<br>Table 59andTable 74, updated number of bits in Internal Logic column for FTXIN2and FRXIN2from 64<br>to 32. UpdatedNote 8and description of FGTXRXinTable 61. Updated FGTHQRANGE1, FGTHQRANGE2,<br>FGQPLLRANGE1, and FGQPLLRANGE2inTable 70. Updated clock names andNote 2andNote 3in<br>Table 74. Removed TJ6.6_QPLLand DJ6.6_QPLLfromTable 75. Updated description of FGTHRX,<br>removed JT_SJ6.6_QPLL, and updatedNote 8inTable 76. Replaced BitGen with bitstream inNote 2of<br>Table 84. Updated FRBCCK, TTAPTCK/TTCKTAP, TTCKTDO, and FTCKinTable 85.|
|11/26/2013|1.18|Added Virtex-7Q defense-grade devices throughout. Added -1M speed grade throughout. Added<br>reference to_7 Series FPGAs Overview_and_Defense-Grade 7 Series FPGAs Overview_inIntroduction.<br>InTable 2, added junction temperature operating range for military (M) devices and updatedNote 6. In<br>Table 3, removed commercial (C), industrial (I), and extended (E) from descriptions of RIN_TERM.<br>Updated temperature ranges inTable 4andTable 5. Added TJ= 125°C to Conditions column for<br>TVCCO2VCCAUXinTable 8. Updated to ISE Design Suite 14.7 and Vivado Design Suite 2013.3 inAC<br>Switching Characteristics. Added 1.05 and 1.06 rows toTable 14. Added -1M speed grade toTable 70<br>andTable 74. Added TUSRCCLKOand FDNACKtoTable 85.|
|03/04/2014|1.19|InTable 2, removed 1.0V fromNote 6and addedNote 7. AddedNote 2toTable 4. AddedNote 2and<br>updatedNote 3inTable 5. Updated to Vivado Design Suite 2013.4 inAC Switching Characteristics.<br>RevisedTable 15andTable 16for the production release of the XQ7VX690T devices. Added<br>HSUL_12_F, DIFF_HSUL_12_F, MOBILE_DDR_S, MOBILE_DDR_F, DIFF_MOBILE_DDR_S, and<br>DIFF_MOBILE_DDR_F standards to and updated values inTable 19. Added HSUL_12_F,<br>DIFF_HSUL_12_F, DIFF_HSUL_12_DCI_S, and DIFF_HSUL_12_DCI_F standards to and updated<br>values inTable 20. Removed notes fromTable 19andTable 20. Removed introductory paragraph of<br>Device Pin-to-Pin Output Parameter GuidelinesandDevice Pin-to-Pin Input Parameter Guidelines.<br>Enhanced precision of FGTHDRPCLKnumbers inTable 71. AddedNote 1toTable 83. Updated display<br>format of “ADC Accuracy at Extended Temperatures” section inTable 84. Updated FICAPCKinTable 85.|
|04/11/2014|1.20|RevisedTable 15andTable 16for the production release of the XQ7VX485T devices. UpdatedNote 1<br>inTable 83.|
|07/01/2014|1.21|InTable 4andTable 5, updatedNote 2per the customer noticeXCN14014<br>: _7 Series FPGA and_<br>_Zynq-7000 AP SoC I/O Undershoot Voltage Data Sheet Update_. InPower-On/Off Power Supply<br>Sequencing, added sentence about there being no recommended sequence for supplies not shown.<br>InTable 15, moved all XQ7V585T, XQ7VX330T, and XQ7VX980T speed grades from Preliminary to<br>Production. InTable 16, added production software for -2, -2L, -1, and -1M speed grades of XQ7V585T<br>and XQ7VX330T, and -2L and -1M speed grades of XQ7VX980T. AddedNote 3toTable 18. In<br>Table 28, added attribute REFCLK frequency of 400 MHz to FIDELAYCTRL_REFand average tap delay<br>at 400 MHz toNote 1. Updated description of TICKOFinTable 42and addedNote 2. Updated<br>description of TICKOFFARinTable 43and addedNote 2. InTable 52, updated TPKGSKEWfor<br>XQ7VX980T to 287 ps. InTable 53, moved DVPPOUTvalue of 1000 mV from Max to Min column,<br>updated VINDC parameter description, and addedNote 2.|



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|**Date**|**Version**|**Description**|
|---|---|---|
|07/01/2014|1.21<br>_(Cont’d)_|Added “peak-to-peak” to labels inFigure 3andFigure 4. Added note afterFigure 4. InTable 68,<br>updated VINDC parameter description, moved DVPPOUTvalue of 800 mV from Max to Min column, and<br>addedNote 1. Added “peak-to-peak” to labels inFigure 6andFigure 7. Added note afterFigure 7. In<br>Table 83, updatedNote 1and addedNote 2. InTable 85, replaced USRCCLK Output with<br>STARTUPE2 Ports and added FCFGMCLKand FCFGMCLKTOL.|
|03/06/2015|1.22|UpdatedNote 3inTable 6. InTable 12, changed maximum VICMvalue from 1.425V to 1.500V.<br>Removed minimum sample rate specification fromTable 84.|
|06/23/2015|1.23|Added FFV1157, FFV1158, FFV1761, FFV1927, and RF1158 packages toTable 52.|
|09/24/2015|1.24|Added introductory paragraph beforeTable 18. UpdatedNote 3inTable 18. Removed note about<br>PCI-SIG 3.0 certification and compliance test boards fromTable 64andTable 79. Updated FICAPCK<br>description from ICAPE3 to ICAPE2 inTable 85.|
|02/02/2016|1.25|AddedI/O Standard Adjustment Measurement Methodology.|
|03/28/2016|1.26|Updated VMEASfor LVCMOS33, LVTTL, and PCI33_3 inTable 22.|
|04/06/2017|1.27|InTable 28, changed TIDELAYRESOLUTIONunits from ps to µs. Removed FFV1157, FFV1158, FFV1761,<br>and FFV1927 packages fromTable 52per the customer noticeXCN16022<br>: _Cross-ship of Lead-free_<br>_Bump and Substrates in Lead-free (FFG/FBG/SBG) Packages_.|
|03/13/2019|1.28|UpdatedNote 3inTable 3.|



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XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III) USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN SUCH APPLICATIONS. 

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