XC7S50-1FTGB196I

FPGA, Spartan-7, 8150 Blocks, 52160 Macrocells, 2700Kbit, 950mV to 1.05V Supply, FCBGA-196, NCNR

⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
Manufacturer: AMD
Product type: FPGAs
No. of Logic Blocks:8150; No. of Macrocells:52160; FPGA Family:Spartan-7; Logic Case Style:FCBGA; No. of Pins:196Pins; No. of Speed Grades:1; Total RAM Bits:2700Kbit; No. of I/O's:100
MSL: MSL 3 - 168 hours
SVHC: No SVHC (15-Jan-2018)
FPGA Type: -
FPGA Family: Spartan-7
IC Mounting: Surface Mount
No. of Pins: 196Pins
Speed Grade: 1
No. of I/O's: 100I/O's
Product Range: Spartan-7 XC7S50
Qualification: -
Total RAM Bits: 2700Kbit
No.of User I/Os: 100I/O's
Clock Management: MMCM, PLL
Logic Case Style: FCBGA
IC Case / Package: FCBGA
No. of Macrocells: 52160Macrocells
I/O Supply Voltage: 3.3V
No. of Logic Cells: 52160Logic Cells
Process Technology: 28nm (HKMG)
No. of Logic Blocks: 52160
No. of Speed Grades: 1
Core Supply Voltage Max: 1.05V
Core Supply Voltage Min: 950mV
Operating Frequency Max: 464MHz
Operating Temperature Max: 100°C
Operating Temperature Min: -40°C
Delivery and price
Units per pack	1
Price	48.22 €
Current stock	10+
Lead time	30 days
Datasheet
DS189 (v1.6) June 18, 2018 

**==> picture [174 x 34] intentionally omitted <==**

## **Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics** 

**Preliminary Product Specification** 

## **Introduction** 

Spartan®-7 FPGAs are available in -2, -1, and -1L speed grades, with -2 having the highest performance. The Spartan-7 FPGAs predominantly operate at a 1.0V core voltage. The -1L devices are screened for lower maximum static power and can operate at lower core voltages for lower dynamic power than the -1 devices. The -1L devices operate only at VCCINT = VCCBRAM = 0.95V and have the same speed specifications as the -1 speed grade. 

Spartan-7 FPGA DC and AC characteristics are specified in commercial (C), industrial (I), and expanded (Q) temperature ranges. Except the operating temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -1Q expanded speed grade device are the same as for a -1C commercial speed grade device). However, only selected speed grades and/or devices are available in each temperature range. For example, the -1L speed grade is only available in the industrial (I) temperature range, and the -1Q speed grade is only available in XA Spartan-7 FPGAs. 

All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters included are common to popular designs and typical applications. 

Available device and package combinations can be found in: 

- _7 Series FPGAs Overview_ (DS180) [Ref 1] 

- _XA Spartan-7 Automotive FPGA Data Sheet: Overview_ (DS171) [Ref 2] 

This Spartan-7 FPGA data sheet, part of an overall set of documentation on the 7 series FPGAs, is available on the Xilinx website at www.xilinx.com/documentation. 

## **DC Characteristics** 

_Table  1:_ **Absolute Maximum Ratings[(1)]** 

|**Symbol**|**Description**|**Min**|**Max**|**Units**|
|---|---|---|---|---|
|**FPGA Logic**|||||
|VCCINT|Internal supply voltage.|–0.5|1.1|V|
|VCCAUX|Auxiliary supply voltage.|–0.5|2.0|V|
|VCCBRAM|Supply voltage for the block RAM memories.|–0.5|1.1|V|
|VCCO|Output drivers supply voltage for HR I/O banks.|–0.5|3.6|V|
|VREF|Input reference voltage.|–0.5|2.0|V|



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**Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  1:_ **Absolute Maximum Ratings[(1)]** _**(Cont’d)**_ 

|**Symbol**|**Description**|**Min**|**Max**|**Units**|
|---|---|---|---|---|
|VIN(2)(3)(4)|I/O input voltage.|–0.4|VCCO + 0.55|V|
||I/O input voltage (when VCCO = 3.3V) for VREFand differential I/O<br>standards except TMDS_33.(5)|–0.4|2.625|V|
|VCCBATT|Key memory battery backup supply.|–0.5|2.0|V|
|**XADC**|||||
|VCCADC|XADC supply relative to GNDADC.|–0.5|2.0|V|
|VREFP|XADC reference input relative to GNDADC.|–0.5|2.0|V|
|**Temperature**|||||
|TSTG|Storage temperature (ambient).|–65|150|°C|
|TSOL|Maximum soldering temperature for Pb/Sn component bodies.(6)|–|+220|°C|
||Maximum soldering temperature for Pb-free component bodies.(6)|–|+260|°C|
|Tj|Maximum junction temperature.(6)|–|+125|°C|



## **Notes:** 

1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability. 

2. The lower absolute voltage specification always applies. 

3. For I/O operation, refer to the _7 Series FPGAs SelectIO Resources User Guide_ (UG471) [Ref 3]. 

4. The maximum limit applies to DC signals. For maximum undershoot and overshoot AC specifications, see Table 4. 

5. See Table 9 for TMDS_33 specifications. 

6. For soldering guidelines and thermal considerations, see the _7 Series FPGA Packaging and Pinout Specification_ (UG475) [Ref 4]. 

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**Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  2:_ **Recommended Operating Conditions[(1)(2)]** 

|**Symbol**|**Description**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|
|**FPGA Logic**||||||
|VCCINT(3)|For -2 and -1 (1.0V) devices: internal supply voltage.|0.95|1.00|1.05|V|
||For -1L (0.95V) devices: internal supply voltage.|0.92|0.95|0.98|V|
|VCCAUX|Auxiliary supply voltage.|1.71|1.80|1.89|V|
|VCCBRAM(3)|For -2 and -1 (1.0V) devices: block RAM supply voltage.|0.95|1.00|1.05|V|
||For -1L (0.95V) devices: block RAM supply voltage.|0.92|0.95|0.98|V|
|VCCO(4)(5)|Supply voltage for HR I/O banks.|1.14|–|3.465|V|
|VIN(6)|I/O input voltage.|–0.20|–|VCCO + 0.20|V|
||I/O input voltage (when VCCO = 3.3V) for VREFand<br>differential I/O standards except TMDS_33.(7)|–0.20|–|2.625|V|
|IIN(8)|Maximum current through any pin in a powered or unpowered<br>bank when forward biasing the clamp diode.|–|–|10|mA|
|VCCBATT(9)|Battery voltage.|1.0|–|1.89|V|
|**XADC**||||||
|VCCADC|XADC supply relative to GNDADC.|1.71|1.80|1.89|V|
|VREFP|Externally supplied reference voltage.|1.20|1.25|1.30|V|
|**Temperature**||||||
|Tj|Junction temperature operating range for commercial (C)<br>temperature devices.|0|–|85|°C|
||Junction temperature operating range for industrial (I)<br>temperature devices.|–40|–|100|°C|
||Junction temperature operating range for expanded (Q)<br>temperature devices.|–40|–|125|°C|



## **Notes:** 

1. All voltages are relative to ground. 

2. For the design of the power distribution system consult the _7 Series FPGAs PCB Design Guide_ (UG483) [Ref 5]. 

3. If VCCINT and VCCBRAM are operating at the same voltage, VCCINT and VCCBRAM should be connected to the same supply. 

4. Configuration data is retained even if VCCO drops to 0V. 

5. Includes VCCO of 1.2V, 1.35V, 1.5V, 1.8V, 2.5V, and 3.3V at ±5%. 

6. The lower absolute voltage specification always applies. 

7. See Table 9 for TMDS_33 specifications. 

8. A total of 200 mA per bank should not be exceeded. 

9. VCCBATT is required only when using bitstream encryption. If battery is not used, connect VCCBATT to either ground or VCCAUX. 

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**Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  3:_ **DC Characteristics Over Recommended Operating Conditions** 

|**Symbol**|**Description**|**Min**|**Typ(1)**|**Max**|**Units**|
|---|---|---|---|---|---|
|VDRINT|Data retention VCCINTvoltage (below which configuration<br>data might be lost).|0.75|–|–|V|
|VDRI|Data retention VCCAUXvoltage (below which configuration<br>data might be lost).|1.5|–|–|V|
|IREF|VREFleakage current per pin.|–|–|15|µA|
|IL|Input or output leakage current per pin (sample-tested).|–|–|15|µA|
|CIN(2)|Die input capacitance at the pad.|–|–|8|pF|
|IRPU|Pad pull-up (when selected) at VIN = 0V, VCCO = 3.3V.|90|–|330|µA|
||Pad pull-up (when selected) at VIN = 0V, VCCO = 2.5V.|68|–|250|µA|
||Pad pull-up (when selected) at VIN = 0V, VCCO = 1.8V.|34|–|220|µA|
||Pad pull-up (when selected) at VIN = 0V, VCCO = 1.5V.|23|–|150|µA|
||Pad pull-up (when selected) at VIN = 0V, VCCO = 1.2V.|12|–|120|µA|
|IRPD|Pad pull-down (when selected) at VIN = 3.3V.|68|–|330|µA|
|ICCADC|Analog supply current, analog circuits in powered up state.|–|–|25|mA|
|IBATT(3)|Battery supply current.|–|–|150|nA|
|RIN_TERM(4)|Thevenin equivalent resistance of programmable input<br>termination to VCCO/2 (UNTUNED_SPLIT_40).|28|40|55|Ω|
||Thevenin equivalent resistance of programmable input<br>termination to VCCO/2 (UNTUNED_SPLIT_50).|35|50|65|Ω|
||Thevenin equivalent resistance of programmable input<br>termination to VCCO/2 (UNTUNED_SPLIT_60).|44|60|83|Ω|
|n|Temperature diode ideality factor.|–|1.010|–|–|
|r|Temperature diode series resistance.|–|2|–|Ω|



## **Notes:** 

1. Typical values are specified at nominal voltage, 25°C. 

2. This measurement represents the die capacitance at the pad, not including the package. 

3. Maximum value specified for worst case process at 25°C. 

4. Termination resistance to a VCCO/2 level. 

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**Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  4:_ **VIN Maximum Allowed AC Voltage Overshoot and Undershoot for HR I/O Banks[(1)(2)]** 

|_Table  4:_ **VIN Maximum All**|**owed AC Voltage Overshoot a**|**d Undershoot for HR I/O Bank**|**s**|
|---|---|---|---|
|**AC Voltage Overshoot**|**% of UI at –40°C to 125°C**|**AC Voltage Undershoot**|**% of UI at –40°C to 125°C**|
|VCCO + 0.55|100|–0.40|100|
|||–0.45|61.7|
|||–0.50|25.8|
|||–0.55|11.0|
|VCCO + 0.60|46.6|–0.60|4.77|
|VCCO + 0.65|21.2|–0.65|2.10|
|VCCO + 0.70|9.75|–0.70|0.94|
|VCCO + 0.75|4.55|–0.75|0.43|
|VCCO + 0.80|2.15|–0.80|0.20|
|VCCO + 0.85|1.02|–0.85|0.09|
|VCCO + 0.90|0.49|–0.90|0.04|
|VCCO + 0.95|0.24|–0.95|0.02|



## **Notes:** 

1. A total of 200 mA per bank should not be exceeded. 

2. The peak voltage of the overshoot or undershoot, and the duration above VCCO + 0.20V or below GND – 0.20V, must not exceed the values in this table. 

_Table  5:_ **Typical Quiescent Supply Current[(1)(2)(3)]** 

|**Symbol**|**Description**|**Device**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|---|---|---|
||||**1.0V**|||||**0.95V**||
||||**-2C**|**-2I**|**-1C**|**-1I**|**-1Q**|**-1LI**||
|ICCINTQ|Quiescent VCCINTsupply current.|XC7S6|36|36|36|36|36|32|mA|
|||XC7S15|36|36|36|36|36|32|mA|
|||XC7S25|48|48|48|48|48|43|mA|
|||XC7S50|95|95|95|95|95|59|mA|
|||XC7S75|148|148|148|148|148|134|mA|
|||XC7S100|148|148|148|148|148|134|mA|
|||XA7S6|N/A|36|N/A|36|36|N/A|mA|
|||XA7S15|N/A|36|N/A|36|36|N/A|mA|
|||XA7S25|N/A|48|N/A|48|48|N/A|mA|
|||XA7S50|N/A|95|N/A|95|95|N/A|mA|
|||XA7S75|N/A|148|N/A|148|148|N/A|mA|
|||XA7S100|N/A|148|N/A|148|148|N/A|mA|



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**Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  5:_ **Typical Quiescent Supply Current[(1)(2)(3)]** _**(Cont’d)**_ 

|**Symbol**|**Description**|**Device**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|---|---|---|
||||**1.0V**|||||**0.95V**||
||||**-2C**|**-2I**|**-1C**|**-1I**|**-1Q**|**-1LI**||
|ICCOQ|Quiescent VCCOsupply current.|XC7S6|1|1|1|1|1|1|mA|
|||XC7S15|1|1|1|1|1|1|mA|
|||XC7S25|1|1|1|1|1|1|mA|
|||XC7S50|1|1|1|1|1|1|mA|
|||XC7S75|4|4|4|4|4|4|mA|
|||XC7S100|4|4|4|4|4|4|mA|
|||XA7S6|N/A|1|N/A|1|1|N/A|mA|
|||XA7S15|N/A|1|N/A|1|1|N/A|mA|
|||XA7S25|N/A|1|N/A|1|1|N/A|mA|
|||XA7S50|N/A|1|N/A|1|1|N/A|mA|
|||XA7S75|N/A|4|N/A|4|4|N/A|mA|
|||XA7S100|N/A|4|N/A|4|4|N/A|mA|
|ICCAUXQ|Quiescent VCCAUXsupply current.|XC7S6|10|10|10|10|10|10|mA|
|||XC7S15|10|10|10|10|10|10|mA|
|||XC7S25|13|13|13|13|13|13|mA|
|||XC7S50|22|22|22|22|22|20|mA|
|||XC7S75|43|43|43|43|43|43|mA|
|||XC7S100|43|43|43|43|43|43|mA|
|||XA7S6|N/A|10|N/A|10|10|N/A|mA|
|||XA7S15|N/A|10|N/A|10|10|N/A|mA|
|||XA7S25|N/A|13|N/A|13|13|N/A|mA|
|||XA7S50|N/A|22|N/A|22|22|N/A|mA|
|||XA7S75|N/A|43|N/A|43|43|N/A|mA|
|||XA7S100|N/A|43|N/A|43|43|N/A|mA|



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**Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  5:_ **Typical Quiescent Supply Current[(1)(2)(3)]** _**(Cont’d)**_ 

|**Symbol**|**Description**|**Device**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|---|---|---|
||||**1.0V**|||||**0.95V**||
||||**-2C**|**-2I**|**-1C**|**-1I**|**-1Q**|**-1LI**||
|ICCBRAMQ|Quiescent VCCBRAMsupply current.|XC7S6|1|1|1|1|1|1|mA|
|||XC7S15|1|1|1|1|1|1|mA|
|||XC7S25|1|1|1|1|1|1|mA|
|||XC7S50|2|2|2|2|2|1|mA|
|||XC7S75|9|9|9|9|9|8|mA|
|||XC7S100|9|9|9|9|9|8|mA|
|||XA7S6|N/A|1|N/A|1|1|N/A|mA|
|||XA7S15|N/A|1|N/A|1|1|N/A|mA|
|||XA7S25|N/A|1|N/A|1|1|N/A|mA|
|||XA7S50|N/A|2|N/A|2|2|N/A|mA|
|||XA7S75|N/A|9|N/A|9|9|N/A|mA|
|||XA7S100|N/A|9|N/A|9|9|N/A|mA|



## **Notes:** 

1. Typical values are specified at nominal voltage, 85°C junction temperature (Tj) with single-ended SelectIO™ resources. 

2. Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and floating. 

3. Use the _Xilinx Power Estimator_ spreadsheet tool [Ref 6] to estimate static power consumption for conditions other than those specified. 

## **Power-On/Off Power Supply Sequencing** 

The recommended power-on sequence is VCCINT, VCCBRAM, VCCAUX, and VCCO to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on. The recommended power-off sequence is the reverse of the power-on sequence. If VCCINT and VCCBRAM have the same recommended voltage levels then both can be powered by the same supply and ramped simultaneously. If VCCAUX and VCCO have the same recommended voltage levels then both can be powered by the same supply and ramped simultaneously. 

For VCCO voltages of 3.3V in HR I/O banks and configuration bank 0 the following conditions apply. 

- The voltage difference between VCCO and VCCAUX must not exceed 2.625V for longer than TVCCO2VCCAUX for each power-on/off cycle to maintain device reliability levels. 

- The TVCCO2VCCAUX time can be allocated in any percentage between the power-on and power-off ramps. 

There is no recommended sequence for supplies not discussed in this section. 

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**Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics** 

Table 6 shows the minimum current, in addition to ICCQ maximum, that is required by Spartan-7 devices for proper power-on and configuration. If the current minimums shown in Table 6 are met, the device powers on after all four supplies have passed through their power-on reset threshold voltages. The FPGA must not be configured until after VCCINT is applied. Once initialized and configured, use the _Xilinx Power Estimator_ spreadsheet tool [Ref 6] to estimate current drain on these supplies. 

_Table  6:_ **Power-On Current** 

|**Device**|**ICCINTMIN**|**ICCAUXMIN**|**ICCOMIN**|**ICCBRAMMIN**|**Units**|
|---|---|---|---|---|---|
|XC7S6|ICCINTQ+ 120|ICCAUXQ+ 40|ICCOQ+ 40 mA per bank|ICCBRAMQ+ 60|mA|
|XC7S15|ICCINTQ+ 120|ICCAUXQ+ 40|ICCOQ+ 40 mA per bank|ICCBRAMQ+ 60|mA|
|XC7S25|ICCINTQ+ 120|ICCAUXQ+ 40|ICCOQ+ 40 mA per bank|ICCBRAMQ+ 60|mA|
|XC7S50|ICCINTQ+ 120|ICCAUXQ+ 40|ICCOQ+ 40 mA per bank|ICCBRAMQ+ 60|mA|
|XC7S75|ICCINTQ+ 300|ICCAUXQ+ 140|ICCOQ+ 40 mA per bank|ICCBRAMQ+ 60|mA|
|XC7S100|ICCINTQ+ 300|ICCAUXQ+ 140|ICCOQ+ 40 mA per bank|ICCBRAMQ+ 60|mA|
|XA7S6|ICCINTQ+ 120|ICCAUXQ+ 40|ICCOQ+ 40 mA per bank|ICCBRAMQ+ 60|mA|
|XA7S15|ICCINTQ+ 120|ICCAUXQ+ 40|ICCOQ+ 40 mA per bank|ICCBRAMQ+ 60|mA|
|XA7S25|ICCINTQ+ 120|ICCAUXQ+ 40|ICCOQ+ 40 mA per bank|ICCBRAMQ+ 60|mA|
|XA7S50|ICCINTQ+ 120|ICCAUXQ+ 40|ICCOQ+ 40 mA per bank|ICCBRAMQ+ 60|mA|
|XA7S75|ICCINTQ+ 300|ICCAUXQ+ 140|ICCOQ+ 40 mA per bank|ICCBRAMQ+ 60|mA|
|XA7S100|ICCINTQ+ 300|ICCAUXQ+ 140|ICCOQ+ 40 mA per bank|ICCBRAMQ+ 60|mA|



_Table  7:_ **Power Supply Ramp Time** 

|**Symbol**|**Description**|**Conditions**|**Min**|**Max**|**Units**|
|---|---|---|---|---|---|
|TVCCINT|Ramp time from GND to 90% of VCCINT.||0.2|50|ms|
|TVCCO|Ramp time from GND to 90% of VCCO.||0.2|50|ms|
|TVCCAUX|Ramp time from GND to 90% of VCCAUX.||0.2|50|ms|
|TVCCBRAM|Ramp time from GND to 90% of VCCBRAM.||0.2|50|ms|
|TVCCO2VCCAUX|Allowed time per power cycle for VCCO – VCCAUX > 2.625V.|TJ = 125°C(1)|–|300|ms|
|||TJ = 100°C(1)|–|500|ms|
|||TJ = 85°C(1)|–|800|ms|



## **Notes:** 

1. Based on 240,000 power cycles with a nominal VCCO of 3.3V or 36,500 power cycles with a worst case VCCO of 3.465V. 

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**Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics** 

## **DC Input and Output Levels** 

Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the recommended operating conditions at the VOL and VOH test points. Only selected standards are tested. These are chosen to ensure that all standards meet their specifications. The selected standards are tested at a minimum VCCO with the respective VOL and VOH voltage levels shown. Other standards are sample tested. 

_Table  8:_ **SelectIO DC Input and Output Levels[(1)(2)(3)]** 

|**I/O Standard**|**VIL**|**VIL**|**VIH**|**VIH**|**VOL**|**VOH**|**IOL**|**IOH**|
|---|---|---|---|---|---|---|---|---|
||**V, Min**|**V, Max**|**V, Min**|**V, Max**|**V, Max**|**V, Min**|**mA, Max **|**mA, Min**|
|HSTL_I|–0.300|VREF – 0.100|VREF + 0.100|VCCO + 0.300|0.400|VCCO – 0.400|8.00|–8.00|
|HSTL_I_18|–0.300|VREF – 0.100|VREF + 0.100|VCCO + 0.300|0.400|VCCO – 0.400|8.00|–8.00|
|HSTL_II|–0.300|VREF – 0.100|VREF + 0.100|VCCO + 0.300|0.400|VCCO – 0.400|16.00|–16.00|
|HSTL_II_18|–0.300|VREF – 0.100|VREF + 0.100|VCCO + 0.300|0.400|VCCO – 0.400|16.00|–16.00|
|HSUL_12|–0.300|VREF – 0.130|VREF + 0.130|VCCO + 0.300|20% VCCO|80% VCCO|0.10|–0.10|
|LVCMOS12|–0.300|35% VCCO|65% VCCO|VCCO + 0.300|0.400|VCCO – 0.400|Note 4|Note 4|
|LVCMOS15|–0.300|35% VCCO|65% VCCO|VCCO + 0.300|25% VCCO|75% VCCO|Note 5|Note 5|
|LVCMOS18|–0.300|35% VCCO|65% VCCO|VCCO + 0.300|0.450|VCCO – 0.450|Note 6|Note 6|
|LVCMOS25|–0.300|0.7|1.700|VCCO + 0.300|0.400|VCCO – 0.400|Note 5|Note 5|
|LVCMOS33|–0.300|0.8|2.000|3.450|0.400|VCCO – 0.400|Note 5|Note 5|
|LVTTL|–0.300|0.8|2.000|3.450|0.400|2.400|Note 6|Note 6|
|MOBILE_DDR|–0.300|20% VCCO|80% VCCO|VCCO + 0.300|10% VCCO|90% VCCO|0.10|–0.10|
|PCI33_3|–0.400|30% VCCO|50% VCCO|VCCO + 0.500|10% VCCO|90% VCCO|1.50|–0.50|
|SSTL135|–0.300|VREF – 0.090|VREF + 0.090|VCCO + 0.300|VCCO/2 – 0.150|VCCO/2 + 0.150|13.00|–13.00|
|SSTL135_R|–0.300|VREF – 0.090|VREF + 0.090|VCCO + 0.300|VCCO/2 – 0.150|VCCO/2 + 0.150|8.90|–8.90|
|SSTL15|–0.300|VREF – 0.100|VREF + 0.100|VCCO + 0.300|VCCO/2 – 0.175|VCCO/2 + 0.175|13.00|–13.00|
|SSTL15_R|–0.300|VREF – 0.100|VREF + 0.100|VCCO + 0.300|VCCO/2 – 0.175|VCCO/2 + 0.175|8.90|–8.90|
|SSTL18_I|–0.300|VREF – 0.125|VREF + 0.125|VCCO + 0.300|VCCO/2 – 0.470|VCCO/2 + 0.470|8.00|–8.00|
|SSTL18_II|–0.300|VREF – 0.125|VREF + 0.125|VCCO + 0.300|VCCO/2 – 0.600|VCCO/2 + 0.600|13.40|–13.40|



## **Notes:** 

1. Tested according to relevant specifications. 

2. 3.3V and 2.5V standards are only supported in HR I/O banks. 

3. For detailed interface specific DC voltage levels, see the _7 Series FPGAs SelectIO Resources User Guide_ (UG471) [Ref 3]. 4. Supported drive strengths of 4, 8, or 12 mA in HR I/O banks. 5. Supported drive strengths of 4, 8, 12, or 16 mA in HR I/O banks. 

6. Supported drive strengths of 4, 8, 12, 16, or 24 mA in HR I/O banks. 

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**Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  9:_ **Differential SelectIO DC Input and Output Levels** 

|**I/O Standard**|**VICM(1)**|**VICM(1)**|**VICM(1)**|**VID(2)**|**VID(2)**|**VID(2)**|**VOCM(3)**|**VOCM(3)**|**VOCM(3)**|**VOD(4)**|**VOD(4)**|**VOD(4)**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
||**V,**<br>**Min**|**V,**<br>**Typ**|**V,**<br>**Max**|**V,**<br>**Min**|**V,**<br>**Typ**|**V,**<br>**Max**|**V,**<br>**Min**|**V,**<br>**Typ**|**V,**<br>**Max**|**V,**<br>**Min**|**V,**<br>**Typ**|**V,**<br>**Max**|
|BLVDS_25|0.300|1.200|1.425|0.100|–|–|–|1.250|–|Note 5|||
|MINI_LVDS_25|0.300|1.200|VCCAUX|0.200|0.400|0.600|1.000|1.200|1.400|0.300|0.450|0.600|
|PPDS_25|0.200|0.900|VCCAUX|0.100|0.250|0.400|0.500|0.950|1.400|0.100|0.250|0.400|
|RSDS_25|0.300|0.900|1.500|0.100|0.350|0.600|1.000|1.200|1.400|0.100|0.350|0.600|
|TMDS_33|2.700|2.965|3.230|0.150|0.675|1.200|VCCO – 0.405|VCCO – 0.300|VCCO – 0.190|0.400|0.600|0.800|



## **Notes:** 

1. VICM is the input common mode voltage. 

2. VID is the input differential voltage (Q – Q). 

3. VOCM is the output common mode voltage. 

4. VOD is the output differential voltage (Q – Q). 

5. VOD for BLVDS will vary significantly depending on topology and loading. 

_Table  10:_ **Complementary Differential SelectIO DC Input and Output Levels** 

|**I/O Standard**|**VICM(1)**|**VICM(1)**|**VICM(1)**|**VID(2)**|**VID(2)**|**VOL(3)**|**VOH(4)**|**IOL**|**IOH**|
|---|---|---|---|---|---|---|---|---|---|
||**V, Min**|**V, Typ **|**V, Max **|**V, Min **|**V, Max**|**V, Max**|**V, Min**|**mA, Max **|**mA, Min**|
|DIFF_HSTL_I|0.300|0.750|1.125|0.100|–|0.400|VCCO – 0.400|8.00|–8.00|
|DIFF_HSTL_I_18|0.300|0.900|1.425|0.100|–|0.400|VCCO – 0.400|8.00|–8.00|
|DIFF_HSTL_II|0.300|0.750|1.125|0.100|–|0.400|VCCO – 0.400|16.00|–16.00|
|DIFF_HSTL_II_18|0.300|0.900|1.425|0.100|–|0.400|VCCO – 0.400|16.00|–16.00|
|DIFF_HSUL_12|0.300|0.600|0.850|0.100|–|20% VCCO|80% VCCO|0.100|–0.100|
|DIFF_MOBILE_DDR|0.300|0.900|1.425|0.100|–|10% VCCO|90% VCCO|0.100|–0.100|
|DIFF_SSTL135|0.300|0.675|1.000|0.100|–|(VCCO/2) – 0.150|(VCCO/2) + 0.150|13.0|–13.0|
|DIFF_SSTL135_R|0.300|0.675|1.000|0.100|–|(VCCO/2) – 0.150|(VCCO/2) + 0.150|8.9|–8.9|
|DIFF_SSTL15|0.300|0.750|1.125|0.100|–|(VCCO/2) – 0.175|(VCCO/2) + 0.175|13.0|–13.0|
|DIFF_SSTL15_R|0.300|0.750|1.125|0.100|–|(VCCO/2) – 0.175|(VCCO/2) + 0.175|8.9|–8.9|
|DIFF_SSTL18_I|0.300|0.900|1.425|0.100|–|(VCCO/2) – 0.470|(VCCO/2) + 0.470|8.00|–8.00|
|DIFF_SSTL18_II|0.300|0.900|1.425|0.100|–|(VCCO/2) – 0.600|(VCCO/2) + 0.600|13.4|–13.4|



## **Notes:** 

1. VICM is the input common mode voltage. 

2. VID is the input differential voltage (Q – Q). 

3. VOL is the single-ended low-output voltage. 

4. VOH is the single-ended high-output voltage. 

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**Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics** 

## **LVDS DC Specifications (LVDS_25)** 

_Table  11:_ **LVDS_25 DC Specifications[(1)]** 

|**Symbol**|**DC Parameter**|**Conditions**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|VCCO|Supply voltage.||2.375|2.500|2.625|V|
|VOH|Output High voltage for Q and Q<br>.|RT = 100Ωacross Q and Q<br>signals.|–|–|1.675|V|
|VOL|Output Low voltage for Q and Q<br>.|RT = 100Ωacross Q and Q<br>signals.|0.700|–|–|V|
|VODIFF|Differential output voltage:<br>(Q – Q<br>), Q = High<br>(Q<br>– Q), Q<br>= High|RT = 100Ωacross Q and Q<br>signals.|247|350|600|mV|
|VOCM|Output common-mode voltage.|RT= 100Ωacross Q and Q<br>signals.|1.000|1.250|1.425|V|
|VIDIFF|Differential input voltage:<br>(Q – Q<br>), Q = High<br>(Q<br>– Q), Q<br>= High||100|350|600|mV|
|VICM|Input common-mode voltage.||0.300|1.200|1.500|V|



## **Notes:** 

1. Differential inputs for LVDS_25 can be placed in banks with VCCO levels that are different from the required level for outputs. Consult the _7 Series FPGAs SelectIO Resources User Guide_ (UG471) [Ref 3] for more information. 

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**Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics** 

## **AC Switching Characteristics** 

All values represented in this data sheet are based on the speed specifications from the Vivado® Design Suite as outlined in Table 12. 

_Table  12:_ **Speed Specification Version By Device** 

|**2018.2**|**Device**|
|---|---|
|1.22|XC7S6, XC7S15, XC7S25, XC7S50, XC7S75, XC7S100|
|1.15|XA7S6, XA7S15, XA7S25, XA7S50, XA7S75, XA7S100|



Switching characteristics are specified on a per-speed-grade basis and can be designated as Advance, Preliminary, or Production. Each designation is defined as follows. 

## **Advance Product Specification** 

These specifications are based on simulations only and are typically available soon after device design specifications are frozen. Although speed grades with this designation are considered relatively stable and conservative, some under-reporting might still occur. 

## **Preliminary Product Specification** 

These specifications are based on complete ES (engineering sample) silicon characterization. Devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon. The probability of under-reporting delays is greatly reduced as compared to Advance data. 

## **Production Product Specification** 

These specifications are released once enough production silicon of a particular device family member has been characterized to provide full correlation between specifications and devices over numerous production lots. There is no under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest speed grades transition to Production before faster speed grades. 

## **Testing of AC Switching Characteristics** 

Internal timing parameters are derived from measuring internal test patterns. All AC switching characteristics are representative of worst-case supply voltage and junction temperature conditions. 

For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer and back-annotate to the simulation net list. Unless otherwise noted, values apply to all Spartan-7 FPGAs. 

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**Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics** 

## **Speed Grade Designations** 

Since individual family members are produced at different times, the migration from one category to another depends completely on the status of the fabrication process for each device. Table 13 correlates the current status of each Spartan-7 device on a per speed grade basis. 

_Table  13:_ **Spartan-7 Device Speed Grade Designations** 

|**Device**|**Speed Grade, Temperature Range, and VCCINT Operating Voltage**|**Speed Grade, Temperature Range, and VCCINT Operating Voltage**|**Speed Grade, Temperature Range, and VCCINT Operating Voltage**|
|---|---|---|---|
||**Advance**|**Preliminary**|**Production**|
|XC7S6||-1Q (1.0V)|-2C (1.0V), -2I (1.0V), -1C (1.0V),<br>-1I (1.0V), and -1LI (0.95V)(1)|
|XC7S15||-1Q (1.0V)|-2C (1.0V), -2I (1.0V), -1C (1.0V),<br>-1I (1.0V), and -1LI (0.95V)(1)|
|XC7S25|||-2C (1.0V), -2I (1.0V), -1C (1.0V),<br>-1I (1.0V), -1Q (1.0V), and -1LI (0.95V)(1)|
|XC7S50|||-2C (1.0V), -2I (1.0V), -1C (1.0V),<br>-1I (1.0V), -1Q (1.0V), and -1LI (0.95V)(1)|
|XC7S75||-1Q (1.0V)|-2C (1.0V), -2I (1.0V), -1C (1.0V),<br>-1I (1.0V), and -1LI (0.95V)(1)|
|XC7S100||-1Q (1.0V)|-2C (1.0V), -2I (1.0V), -1C (1.0V),<br>-1I (1.0V), and -1LI (0.95V)(1)|
|XA7S6||-2I (1.0V), -1I (1.0V), -1Q (1.0V)||
|XA7S15||-2I (1.0V), -1I (1.0V), -1Q (1.0V)||
|XA7S25|||-2I (1.0V), -1I (1.0V), -1Q (1.0V)|
|XA7S50|||-2I (1.0V), -1I (1.0V), -1Q (1.0V)|
|XA7S75||-2I (1.0V), -1I (1.0V), -1Q (1.0V)||
|XA7S100||-2I (1.0V), -1I (1.0V), -1Q (1.0V)||



## **Notes:** 

1. The lowest power -1LI devices, where VCCINT = 0.95V, are listed in the Vivado Design Suite as -1IL. 

## **Production Silicon and Software Status** 

In some cases, a particular family member (and speed grade) is released to production before a speed specification is released with the correct label (Advance, Preliminary, Production). Any labeling discrepancies are corrected in subsequent speed specification releases. 

Table 14 lists the production released Spartan-7 device, speed grade, and the minimum corresponding supported speed specification version and software revisions. The software and speed specifications listed are the minimum releases required for production. All subsequent releases of software and speed specifications are valid. 

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**Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  14:_ **Spartan-7 Device Production Software and Speed Specification Release** 

|**Device**|**VCCINT Operating Voltage, Speed Grade, and Temperature Range**|**VCCINT Operating Voltage, Speed Grade, and Temperature Range**|**VCCINT Operating Voltage, Speed Grade, and Temperature Range**|**VCCINT Operating Voltage, Speed Grade, and Temperature Range**|**VCCINT Operating Voltage, Speed Grade, and Temperature Range**|**VCCINT Operating Voltage, Speed Grade, and Temperature Range**|
|---|---|---|---|---|---|---|
||**1.0V**|||||**0.95V**|
||**-2C**|**-2I**|**-1C**|**-1I**|**-1Q**|**-1LI**|
|XC7S6|Vivado tools 2018.2 v1.22|||||Vivado tools<br>2018.2 v1.22|
|XC7S15|Vivado tools 2018.2 v1.22|||||Vivado tools<br>2018.2 v1.22|
|XC7S25|Vivado tools 2017.4 v1.20||||Vivado tools<br>2018.1 v1.21|Vivado tools<br>2017.4 v1.20|
|XC7S50|Vivado tools 2017.2 v1.17||||Vivado tools<br>2017.3 v1.19|Vivado tools<br>2017.2 v1.17|
|XC7S75|Vivado tools 2018.1 v1.21|||||Vivado tools<br>2018.1 v1.21|
|XC7S100|Vivado tools 2018.1 v1.21|||||Vivado tools<br>2018.1 v1.21|
|XA7S6|N/A||N/A|||N/A|
|XA7S15|N/A||N/A|||N/A|
|XA7S25|N/A|Vivado tools<br>2018.1 v1.15|N/A|Vivado tools 2018.1 v1.15||N/A|
|XA7S50|N/A|Vivado tools<br>2017.3 v1.12|N/A|Vivado tools 2017.3 v1.12||N/A|
|XA7S75|N/A||N/A|||N/A|
|XA7S100|N/A||N/A|||N/A|



## **Performance Characteristics** 

This section provides the performance characteristics of some common functions and designs implemented in Spartan-7 FPGAs. These values are subject to the same guidelines as the AC Switching Characteristics, page 12. 

_Table  15:_ **Networking Applications Interface Performances** 

|_Table  15:_ **Networking Applications Interface Performances**|||||
|---|---|---|---|---|
|**Description**|**VCCINT Operating Voltage, Speed**<br>**Grade, and Temperature Range**|||**Units**|
||**1.0V**||**0.95V**||
||**-2C/-2I**|**-1C/-1I/-1Q**|**-1LI**||
|SDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 8)|680|600|600|Mb/s|
|DDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 14)|1250|950|950|Mb/s|
|SDR LVDS receiver(1)|680|600|600|Mb/s|
|DDR LVDS receiver(1)|1250|950|950|Mb/s|



## **Notes:** 

1. LVDS receivers are typically bounded with certain applications where specific dynamic phase-alignment (DPA) algorithms dominate deterministic performance. 

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_Table  16:_ **Maximum Physical Interface (PHY) Rate for Memory Interface IP available with the Memory Interface Generator[(1)]** 

|**Memory Standard**|**VCCINT Operating Voltage, Speed Grade,**<br>**and Temperature Range**|**VCCINT Operating Voltage, Speed Grade,**<br>**and Temperature Range**|**VCCINT Operating Voltage, Speed Grade,**<br>**and Temperature Range**|**Units**|
|---|---|---|---|---|
||**1.0V**||**0.95V**||
||**-2C/-2I**|**-1C/-1I/-1Q**|**-1LI**||
|**4:1 Memory Controllers**|||||
|DDR3|800(2)|667|667|Mb/s|
|DDR3L|800(2)|667|667|Mb/s|
|DDR2|800(2)|667|667|Mb/s|
|**2:1 Memory Controllers**|||||
|DDR3|800(2)|667|667|Mb/s|
|DDR3L|800(2)|667|667|Mb/s|
|DDR2|800(2)|667|667|Mb/s|
|LPDDR2|667|533|533|Mb/s|



## **Notes:** 

1. VREF tracking is required. For more information, see the _Zynq-7000 AP SoC and 7 Series FPGAs Memory Interface Solutions User Guide_ (UG586) [Ref 7]. 

2. The maximum PHY rate is 667 Mb/s in the FTGB196 package. 

## **IOB Pad Input/Output/3-State** 

Table 17 summarizes the values of standard-specific data input delay adjustments, output delays terminating at pads (based on standard) and 3-state delays. 

- TIOPI is described as the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The delay varies depending on the capability of the SelectIO input buffer. 

- TIOOP is described as the delay from the O pin to the IOB pad through the output buffer of an IOB pad. The delay varies depending on the capability of the SelectIO output buffer. 

- TIOTP is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is disabled. The delay varies depending on the SelectIO capability of the output buffer. In HR I/O banks, the IN_TERM termination turn-on time is always faster than TIOTP when the INTERMDISABLE pin is used. 

_Table  17:_ **IOB High Range (HR) Switching Characteristics** 

|**I/O Standard**|**TIOPI**|**TIOPI**|**TIOPI**|**TIOOP**|**TIOOP**|**TIOOP**|**TIOTP**|**TIOTP**|**TIOTP**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|
||**VCCINT Operating Voltage and Speed Grade**||||||||||
||**1.0V**||**0.95V**|**1.0V**||**0.95V**|**1.0V**||**0.95V**||
||**-2**|**-1**|**-1L**|**-2**|**-1**|**-1L**|**-2**|**-1**|**-1L**||
|LVTTL_S4|1.34|1.41|1.41|3.93|4.18|4.18|3.96|4.20|4.20|ns|
|LVTTL_S8|1.34|1.41|1.41|3.66|3.92|3.92|3.69|3.93|3.93|ns|
|LVTTL_S12|1.34|1.41|1.41|3.65|3.90|3.90|3.68|3.91|3.91|ns|
|LVTTL_S16|1.34|1.41|1.41|3.19|3.45|3.45|3.22|3.46|3.46|ns|
|LVTTL_S24|1.34|1.41|1.41|3.41|3.67|3.67|3.44|3.68|3.68|ns|



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**Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  17:_ **IOB High Range (HR) Switching Characteristics** _**(Cont’d)**_ 

|**I/O Standard**|**TIOPI**|**TIOPI**|**TIOPI**|**TIOOP**|**TIOOP**|**TIOOP**|**TIOTP**|**TIOTP**|**TIOTP**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|
||**VCCINT Operating Voltage and Speed Grade**||||||||||
||**1.0V**||**0.95V**|**1.0V**||**0.95V**|**1.0V**||**0.95V**||
||**-2**|**-1**|**-1L**|**-2**|**-1**|**-1L**|**-2**|**-1**|**-1L**||
|LVTTL_F4|1.34|1.41|1.41|3.38|3.64|3.64|3.41|3.65|3.65|ns|
|LVTTL_F8|1.34|1.41|1.41|2.87|3.12|3.12|2.90|3.13|3.13|ns|
|LVTTL_F12|1.34|1.41|1.41|2.85|3.10|3.10|2.88|3.12|3.12|ns|
|LVTTL_F16|1.34|1.41|1.41|2.68|2.93|2.93|2.71|2.95|2.95|ns|
|LVTTL_F24|1.34|1.41|1.41|2.65|2.90|2.90|2.68|2.91|2.91|ns|
|LVDS_25|0.81|0.88|0.88|1.41|1.67|1.67|1.44|1.68|1.68|ns|
|MINI_LVDS_25|0.81|0.88|0.88|1.40|1.65|1.65|1.43|1.66|1.66|ns|
|BLVDS_25|0.81|0.88|0.88|1.96|2.21|2.21|1.99|2.23|2.23|ns|
|RSDS_25 (point to point)|0.81|0.88|0.88|1.40|1.65|1.65|1.43|1.66|1.66|ns|
|PPDS_25|0.81|0.88|0.88|1.41|1.67|1.67|1.44|1.68|1.68|ns|
|TMDS_33|0.81|0.88|0.88|1.54|1.79|1.79|1.57|1.80|1.80|ns|
|PCI33_3|1.32|1.39|1.39|3.22|3.48|3.48|3.25|3.49|3.49|ns|
|HSUL_12_S|0.75|0.82|0.82|1.93|2.18|2.18|1.96|2.20|2.20|ns|
|HSUL_12_F|0.75|0.82|0.82|1.41|1.67|1.67|1.44|1.68|1.68|ns|
|DIFF_HSUL_12_S|0.76|0.83|0.83|1.93|2.18|2.18|1.96|2.20|2.20|ns|
|DIFF_HSUL_12_F|0.76|0.83|0.83|1.41|1.67|1.67|1.44|1.68|1.68|ns|
|MOBILE_DDR_S|0.84|0.91|0.91|1.80|2.06|2.06|1.83|2.07|2.07|ns|
|MOBILE_DDR_F|0.84|0.91|0.91|1.51|1.76|1.76|1.54|1.77|1.77|ns|
|DIFF_MOBILE_DDR_S|0.78|0.85|0.85|1.82|2.07|2.07|1.85|2.09|2.09|ns|
|DIFF_MOBILE_DDR_F|0.78|0.85|0.85|1.57|1.82|1.82|1.60|1.84|1.84|ns|
|HSTL_I_S|0.75|0.82|0.82|1.74|1.99|1.99|1.77|2.01|2.01|ns|
|HSTL_II_S|0.73|0.80|0.80|1.54|1.79|1.79|1.57|1.80|1.80|ns|
|HSTL_I_18_S|0.75|0.82|0.82|1.41|1.67|1.67|1.44|1.68|1.68|ns|
|HSTL_II_18_S|0.75|0.81|0.81|1.54|1.79|1.79|1.57|1.80|1.80|ns|
|DIFF_HSTL_I_S|0.76|0.83|0.83|1.71|1.96|1.96|1.74|1.98|1.98|ns|
|DIFF_HSTL_II_S|0.76|0.83|0.83|1.63|1.88|1.88|1.66|1.90|1.90|ns|
|DIFF_HSTL_I_18_S|0.79|0.86|0.86|1.51|1.76|1.76|1.54|1.77|1.77|ns|
|DIFF_HSTL_II_18_S|0.78|0.85|0.85|1.58|1.84|1.84|1.61|1.85|1.85|ns|
|HSTL_I_F|0.75|0.82|0.82|1.22|1.48|1.48|1.25|1.49|1.49|ns|
|HSTL_II_F|0.73|0.80|0.80|1.24|1.49|1.49|1.27|1.51|1.51|ns|
|HSTL_I_18_F|0.75|0.82|0.82|1.26|1.51|1.51|1.29|1.52|1.52|ns|
|HSTL_II_18_F|0.75|0.81|0.81|1.24|1.49|1.49|1.27|1.51|1.51|ns|
|DIFF_HSTL_I_F|0.76|0.83|0.83|1.30|1.56|1.56|1.33|1.57|1.57|ns|
|DIFF_HSTL_II_F|0.76|0.83|0.83|1.33|1.59|1.59|1.36|1.60|1.60|ns|
|DIFF_HSTL_I_18_F|0.79|0.86|0.86|1.33|1.59|1.59|1.36|1.60|1.60|ns|
|DIFF_HSTL_II_18_F|0.78|0.85|0.85|1.33|1.59|1.59|1.36|1.60|1.60|ns|



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_Table  17:_ **IOB High Range (HR) Switching Characteristics** _**(Cont’d)**_ 

|**I/O Standard**|**TIOPI**|**TIOPI**|**TIOPI**|**TIOOP**|**TIOOP**|**TIOOP**|**TIOTP**|**TIOTP**|**TIOTP**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|
||**VCCINT Operating Voltage and Speed Grade**||||||||||
||**1.0V**||**0.95V**|**1.0V**||**0.95V**|**1.0V**||**0.95V**||
||**-2**|**-1**|**-1L**|**-2**|**-1**|**-1L**|**-2**|**-1**|**-1L**||
|LVCMOS33_S4|1.34|1.41|1.41|3.93|4.18|4.18|3.96|4.20|4.20|ns|
|LVCMOS33_S8|1.34|1.41|1.41|3.65|3.90|3.90|3.68|3.91|3.91|ns|
|LVCMOS33_S12|1.34|1.41|1.41|3.21|3.46|3.46|3.24|3.48|3.48|ns|
|LVCMOS33_S16|1.34|1.41|1.41|3.52|3.77|3.77|3.55|3.79|3.79|ns|
|LVCMOS33_F4|1.34|1.41|1.41|3.38|3.64|3.64|3.41|3.65|3.65|ns|
|LVCMOS33_F8|1.34|1.41|1.41|2.87|3.12|3.12|2.90|3.13|3.13|ns|
|LVCMOS33_F12|1.34|1.41|1.41|2.68|2.93|2.93|2.71|2.95|2.95|ns|
|LVCMOS33_F16|1.34|1.41|1.41|2.68|2.93|2.93|2.71|2.95|2.95|ns|
|LVCMOS25_S4|1.20|1.27|1.27|3.26|3.51|3.51|3.29|3.52|3.52|ns|
|LVCMOS25_S8|1.20|1.27|1.27|3.01|3.26|3.26|3.04|3.27|3.27|ns|
|LVCMOS25_S12|1.20|1.27|1.27|2.60|2.85|2.85|2.63|2.87|2.87|ns|
|LVCMOS25_S16|1.20|1.27|1.27|2.94|3.20|3.20|2.97|3.21|3.21|ns|
|LVCMOS25_F4|1.20|1.27|1.27|2.87|3.12|3.12|2.90|3.13|3.13|ns|
|LVCMOS25_F8|1.20|1.27|1.27|2.30|2.56|2.56|2.33|2.57|2.57|ns|
|LVCMOS25_F12|1.20|1.27|1.27|2.29|2.54|2.54|2.32|2.55|2.55|ns|
|LVCMOS25_F16|1.20|1.27|1.27|2.13|2.39|2.39|2.16|2.40|2.40|ns|
|LVCMOS18_S4|0.83|0.89|0.89|1.74|1.99|1.99|1.77|2.01|2.01|ns|
|LVCMOS18_S8|0.83|0.89|0.89|2.30|2.56|2.56|2.33|2.57|2.57|ns|
|LVCMOS18_S12|0.83|0.89|0.89|2.30|2.56|2.56|2.33|2.57|2.57|ns|
|LVCMOS18_S16|0.83|0.89|0.89|1.65|1.90|1.90|1.68|1.91|1.91|ns|
|LVCMOS18_S24|0.83|0.89|0.89|1.72|1.98|1.98|1.75|1.99|1.99|ns|
|LVCMOS18_F4|0.83|0.89|0.89|1.57|1.82|1.82|1.60|1.84|1.84|ns|
|LVCMOS18_F8|0.83|0.89|0.89|1.80|2.06|2.06|1.83|2.07|2.07|ns|
|LVCMOS18_F12|0.83|0.89|0.89|1.80|2.06|2.06|1.83|2.07|2.07|ns|
|LVCMOS18_F16|0.83|0.89|0.89|1.52|1.77|1.77|1.55|1.79|1.79|ns|
|LVCMOS18_F24|0.83|0.89|0.89|1.46|1.71|1.71|1.49|1.73|1.73|ns|
|LVCMOS15_S4|0.86|0.93|0.93|2.18|2.43|2.43|2.21|2.45|2.45|ns|
|LVCMOS15_S8|0.86|0.93|0.93|2.21|2.46|2.46|2.24|2.48|2.48|ns|
|LVCMOS15_S12|0.86|0.93|0.93|1.71|1.96|1.96|1.74|1.98|1.98|ns|
|LVCMOS15_S16|0.86|0.93|0.93|1.71|1.96|1.96|1.74|1.98|1.98|ns|
|LVCMOS15_F4|0.86|0.93|0.93|1.97|2.23|2.23|2.00|2.24|2.24|ns|
|LVCMOS15_F8|0.86|0.93|0.93|1.72|1.98|1.98|1.75|1.99|1.99|ns|
|LVCMOS15_F12|0.86|0.93|0.93|1.47|1.73|1.73|1.50|1.74|1.74|ns|
|LVCMOS15_F16|0.86|0.93|0.93|1.46|1.71|1.71|1.49|1.73|1.73|ns|
|LVCMOS12_S4|0.95|1.02|1.02|2.69|2.95|2.95|2.72|2.96|2.96|ns|
|LVCMOS12_S8|0.95|1.02|1.02|2.21|2.46|2.46|2.24|2.48|2.48|ns|



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**Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  17:_ **IOB High Range (HR) Switching Characteristics** _**(Cont’d)**_ 

|**I/O Standard**|**TIOPI**|**TIOPI**|**TIOPI**|**TIOOP**|**TIOOP**|**TIOOP**|**TIOTP**|**TIOTP**|**TIOTP**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|
||**VCCINT Operating Voltage and Speed Grade**||||||||||
||**1.0V**||**0.95V**|**1.0V**||**0.95V**|**1.0V**||**0.95V**||
||**-2**|**-1**|**-1L**|**-2**|**-1**|**-1L**|**-2**|**-1**|**-1L**||
|LVCMOS12_S12|0.95|1.02|1.02|1.91|2.17|2.17|1.94|2.18|2.18|ns|
|LVCMOS12_F4|0.95|1.02|1.02|2.10|2.35|2.35|2.13|2.37|2.37|ns|
|LVCMOS12_F8|0.95|1.02|1.02|1.66|1.92|1.92|1.69|1.93|1.93|ns|
|LVCMOS12_F12|0.95|1.02|1.02|1.51|1.76|1.76|1.54|1.77|1.77|ns|
|SSTL135_S|0.75|0.82|0.82|1.47|1.73|1.73|1.50|1.74|1.74|ns|
|SSTL15_S|0.68|0.75|0.75|1.43|1.68|1.68|1.46|1.69|1.69|ns|
|SSTL18_I_S|0.75|0.82|0.82|1.79|2.04|2.04|1.82|2.06|2.06|ns|
|SSTL18_II_S|0.75|0.82|0.82|1.43|1.68|1.68|1.46|1.70|1.70|ns|
|DIFF_SSTL135_S|0.76|0.83|0.83|1.47|1.73|1.73|1.50|1.74|1.74|ns|
|DIFF_SSTL15_S|0.76|0.83|0.83|1.43|1.68|1.68|1.46|1.69|1.69|ns|
|DIFF_SSTL18_I_S|0.79|0.86|0.86|1.80|2.06|2.06|1.83|2.07|2.07|ns|
|DIFF_SSTL18_II_S|0.79|0.86|0.86|1.51|1.76|1.76|1.54|1.77|1.77|ns|
|SSTL135_F|0.75|0.82|0.82|1.24|1.49|1.49|1.27|1.51|1.51|ns|
|SSTL15_F|0.68|0.75|0.75|1.19|1.45|1.45|1.22|1.46|1.46|ns|
|SSTL18_I_F|0.75|0.82|0.82|1.24|1.49|1.49|1.27|1.51|1.51|ns|
|SSTL18_II_F|0.75|0.82|0.82|1.24|1.49|1.49|1.27|1.51|1.51|ns|
|DIFF_SSTL135_F|0.76|0.83|0.83|1.24|1.49|1.49|1.27|1.51|1.51|ns|
|DIFF_SSTL15_F|0.76|0.83|0.83|1.19|1.45|1.45|1.22|1.46|1.46|ns|
|DIFF_SSTL18_I_F|0.79|0.86|0.86|1.35|1.60|1.60|1.38|1.62|1.62|ns|
|DIFF_SSTL18_II_F|0.79|0.86|0.86|1.33|1.59|1.59|1.36|1.60|1.60|ns|



Table 18 specifies the values of TIOTPHZ and TIOIBUFDISABLE. TIOTPHZ is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is enabled (i.e., a high impedance state). TIOIBUFDISABLE is described as the IOB delay from IBUFDISABLE to O output. In HR I/O banks, the internal IN_TERM termination turn-off time is always faster than TIOTPHZ when the INTERMDISABLE pin is used. 

_Table  18:_ **IOB 3-state Output Switching Characteristics** 

|**Symbol**|**Description**|**VCCINT Operating Voltage and**<br>**Speed Grade**|**VCCINT Operating Voltage and**<br>**Speed Grade**|**VCCINT Operating Voltage and**<br>**Speed Grade**|**Units**|
|---|---|---|---|---|---|
|||**1.0V**||**0.95V**||
|||**-2**|**-1**|**-1L**||
|TIOTPHZ|T input to pad high-impedance.|2.19|2.37|2.37|ns|
|TIOIBUFDISABLE|IBUF turn-on time from IBUFDISABLE to O output.|2.30|2.60|2.60|ns|



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**Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics** 

## **I/O Standard Adjustment Measurement Methodology** 

## _**Input Delay Measurements**_ 

Table 19 shows the test setup parameters used for measuring input delay. 

_Table  19:_ **Input Delay Measurement Methodology** 

|**Description**|**I/O Standard Attribute**|**VL(1)**|**VH(1)**|**VMEAS(3)(5)**|**VREF(2)(4)**|
|---|---|---|---|---|---|
|LVCMOS, 1.2V|LVCMOS12|0.1|1.1|0.6|–|
|LVCMOS, 1.5V|LVCMOS15|0.1|1.4|0.75|–|
|LVCMOS, 1.8V|LVCMOS18|0.1|1.7|0.9|–|
|LVCMOS, 2.5V|LVCMOS25|0.1|2.4|1.25|–|
|LVCMOS, 3.3V|LVCMOS33|0.1|3.2|1.65|–|
|LVTTL, 3.3V|LVTTL|0.1|3.2|1.65|–|
|MOBILE_DDR, 1.8V|MOBILE_DDR|0.1|1.7|0.9|–|
|PCI33, 3.3V|PCI33_3|0.1|3.2|1.65|–|
|HSTL (high-speed transceiver<br>logic), Class I, 1.2V|HSTL_I_12|VREF – 0.5|VREF + 0.5|VREF|0.60|
|HSTL, Class I & II, 1.5V|HSTL_I, HSTL_II|VREF – 0.65|VREF + 0.65|VREF|0.75|
|HSTL, Class I & II, 1.8V|HSTL_I_18,<br>HSTL_II_18|VREF – 0.8|VREF + 0.8|VREF|0.90|
|HSUL (high-speed<br>unterminated logic), 1.2V|HSUL_12|VREF – 0.5|VREF + 0.5|VREF|0.60|
|SSTL (stub-terminated<br>transceiver logic), 1.2V|SSTL12|VREF – 0.5|VREF + 0.5|VREF|0.60|
|SSTL, 1.35V|SSTL135, SSTL135_R|VREF – 0.575|VREF + 0.575|VREF|0.675|
|SSTL, 1.5V|SSTL15, SSTL15_R|VREF – 0.65|VREF + 0.65|VREF|0.75|
|SSTL, Class I & II, 1.8V|SSTL18_I, SSTL18_II|VREF – 0.8|VREF + 0.8|VREF|0.90|
|DIFF_MOBILE_DDR, 1.8V|DIFF_MOBILE_DDR|0.9 – 0.125|0.9 + 0.125|0(5)|–|
|DIFF_HSTL, Class I, 1.2V|DIFF_HSTL_I_12|0.6 – 0.125|0.6 + 0.125|0(5)|–|
|DIFF_HSTL, Class I & II,1.5V|DIFF_HSTL_I,<br>DIFF_HSTL_II|0.75 – 0.125|0.75 + 0.125|0(5)|–|
|DIFF_HSTL, Class I & II, 1.8V|DIFF_HSTL_I_18,<br>DIFF_HSTL_II_18|0.9 – 0.125|0.9 + 0.125|0(5)|–|
|DIFF_HSUL, 1.2V|DIFF_HSUL_12|0.6 – 0.125|0.6 + 0.125|0(5)|–|
|DIFF_SSTL135/<br>DIFF_SSTL135_R, 1.35V|DIFF_SSTL135,<br>DIFF_SSTL135_R|0.675 – 0.125|0.675 + 0.125|0(5)|–|
|DIFF_SSTL15/<br>DIFF_SSTL15_R, 1.5V|DIFF_SSTL15,<br>DIFF_SSTL15_R|0.75 – 0.125|0.75 + 0.125|0(5)|–|
|DIFF_SSTL18_I/<br>DIFF_SSTL18_II, 1.8V|DIFF_SSTL18_I,<br>DIFF_SSTL18_II|0.9 – 0.125|0.9 + 0.125|0(5)|–|
|LVDS_25, 2.5V|LVDS_25|1.2 – 0.125|1.2 + 0.125|0(5)|–|
|BLVDS_25, 2.5V|BLVDS_25|1.25 – 0.125|1.25 + 0.125|0(5)|–|
|MINI_LVDS_25, 2.5V|MINI_LVDS_25|1.25 – 0.125|1.25 + 0.125|0(5)|–|



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**Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  19:_ **Input Delay Measurement Methodology** _**(Cont’d)**_ 

|**Description**|**I/O Standard Attribute**|**VL(1)**|**VH(1)**|**VMEAS(3)(5)**|**VREF(2)(4)**|
|---|---|---|---|---|---|
|PPDS_25|PPDS_25|1.25 – 0.125|1.25 + 0.125|0(5)|–|
|RSDS_25|RSDS_25|1.25 – 0.125|1.25 + 0.125|0(5)|–|
|TMDS_33|TMDS_33|3 – 0.125|3 + 0.125|0(5)|–|



## **Notes:** 

1. Input waveform switches between VL and VH. 

2. Measurements are made at typical, minimum, and maximum VREF values. Reported delays reflect worst case of these measurements. VREF values listed are typical. 

3. Input voltage level from which measurement starts. 

4. This is an input voltage reference that bears no relation to the VREF / VMEAS parameters found in IBIS models and/or noted in Figure 1. 

5. The value given is the differential input voltage. 

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**Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics** 

## _**Output Delay Measurements**_ 

Output delays are measured with short output traces. Standard termination was used for all testing. The propagation delay of the trace is characterized separately and subtracted from the final measurement, and is therefore not included in the generalized test setups shown in Figure 1 and Figure 2. 

**==> picture [362 x 191] intentionally omitted <==**

**----- Start of picture text -----**<br>
VREF<br>Output RREF<br>VMEAS (voltage level when taking delay measurement)<br>CREF (probe capacitance)<br>X16654-092616<br>**----- End of picture text -----**<br>


_Figure 1:_ **Single-ended Test Setup** 

**==> picture [278 x 112] intentionally omitted <==**

**----- Start of picture text -----**<br>
Output<br>+<br>CREF RREF VMEAS<br>–<br>X16640-092616<br>**----- End of picture text -----**<br>


_Figure 2:_ **Differential Test Setup** 

Parameters VREF, RREF, CREF, and VMEAS fully describe the test conditions for each I/O standard. The most accurate prediction of propagation delay in any given application can be obtained through IBIS simulation, using this method: 

1. Simulate the output driver of choice into the generalized test setup using values from Table 20. 

2. Record the time to VMEAS. 

3. Simulate the output driver of choice into the actual PCB trace and load using the appropriate IBIS model or capacitance value to represent the load. 

4. Record the time to VMEAS. 

5. Compare the results of step 2 and step 4. The increase or decrease in delay yields the actual propagation delay of the PCB trace. 

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**Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  20:_ **Output Delay Measurement Methodology** 

|_Table  20:_ **Output Delay Measurement Methodology**||||||
|---|---|---|---|---|---|
|**Description**|**I/O Standard Attribute**|**RREF**<br>**(**Ω**)**|**CREF(1)**<br>**(pF)**|**VMEAS**<br>**(V)**|**VREF**<br>**(V)**|
|LVCMOS, 1.2V|LVCMOS12|1M|0|0.6|0|
|LVCMOS, 1.5V|LVCMOS15|1M|0|0.75|0|
|LVCMOS, 1.8V|LVCMOS18|1M|0|0.9|0|
|LVCMOS, 2.5V|LVCMOS25|1M|0|1.25|0|
|LVCMOS, 3.3V|LVCMOS33|1M|0|1.65|0|
|LVTTL, 3.3V|LVTTL|1M|0|1.65|0|
|PCI33, 3.3V|PCI33_3|25|10|1.65|0|
|HSTL (high-speed transceiver logic), Class I, 1.2V|HSTL_I_12|50|0|VREF|0.6|
|HSTL, Class I, 1.5V|HSTL_I|50|0|VREF|0.75|
|HSTL, Class II, 1.5V|HSTL_II|25|0|VREF|0.75|
|HSTL, Class I, 1.8V|HSTL_I_18|50|0|VREF|0.9|
|HSTL, Class II, 1.8V|HSTL_II_18|25|0|VREF|0.9|
|HSUL (high-speed unterminated logic), 1.2V|HSUL_12|50|0|VREF|0.6|
|SSTL12, 1.2V|SSTL12|50|0|VREF|0.6|
|SSTL135/SSTL135_R, 1.35V|SSTL135, SSTL135_R|50|0|VREF|0.675|
|SSTL15/SSTL15_R, 1.5V|SSTL15, SSTL15_R|50|0|VREF|0.75|
|SSTL (stub-series terminated logic),<br>Class I & Class II, 1.8V|SSTL18_I, SSTL18_II|50|0|VREF|0.9|
|DIFF_MOBILE_DDR, 1.8V|DIFF_MOBILE_DDR|50|0|VREF|0.9|
|DIFF_HSTL, Class I, 1.2V|DIFF_HSTL_I_12|50|0|VREF|0.6|
|DIFF_HSTL, Class I & II, 1.5V|DIFF_HSTL_I, DIFF_HSTL_II|50|0|VREF|0.75|
|DIFF_HSTL, Class I & II, 1.8V|DIFF_HSTL_I_18,<br>DIFF_HSTL_II_18|50|0|VREF|0.9|
|DIFF_HSUL_12, 1.2V|DIFF_HSUL_12|50|0|VREF|0.6|
|DIFF_SSTL135/DIFF_SSTL135_R, 1.35V|DIFF_SSTL135,<br>DIFF_SSTL135_R|50|0|VREF|0.675|
|DIFF_SSTL15/DIFF_SSTL15_R, 1.5V|DIFF_SSTL15, DIFF_SSTL15_R|50|0|VREF|0.75|
|DIFF_SSTL18, Class I & II, 1.8V|DIFF_SSTL18_I,<br>DIFF_SSTL18_II|50|0|VREF|0.9|
|LVDS, 2.5V|LVDS_25|100|0|0(2)|0|
|BLVDS (Bus LVDS), 2.5V|BLVDS_25|100|0|0(2)|0|
|Mini LVDS, 2.5V|MINI_LVDS_25|100|0|0(2)|0|
|PPDS_25|PPDS_25|100|0|0(2)|0|
|RSDS_25|RSDS_25|100|0|0(2)|0|
|TMDS_33|TMDS_33|50|0|0(2)|3.3|



## **Notes:** 

1. CREF is the capacitance of the probe, nominally 0 pF. 

2. The value given is the differential output voltage. 

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**Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics** 

## **Input/Output Logic Switching Characteristics** 

_Table  21:_ **ILOGIC Switching Characteristics** 

|**Symbol**|**Description**|**VCCINT Operating Voltage and**<br>**Speed Grade**|**VCCINT Operating Voltage and**<br>**Speed Grade**|**VCCINT Operating Voltage and**<br>**Speed Grade**|**Units**|
|---|---|---|---|---|---|
|||**1.0V**||**0.95V**||
|||**-2**|**-1**|**-1L**||
|**Setup/Hold**||||||
|TICE1CK/TICKCE1|CE1 pin setup/hold with respect to CLK.|0.54/0.02|0.76/0.02|0.76/0.02|ns|
|TISRCK/TICKSR|SR pin setup/hold with respect to CLK.|0.70/0.01|1.13/0.01|1.13/0.01|ns|
|TIDOCK/TIOCKD|D pin setup/hold with respect to CLK without<br>delay.|0.01/0.29|0.01/0.33|0.01/0.33|ns|
|TIDOCKD/TIOCKDD|DDLY pin setup/hold with respect to CLK (using<br>IDELAY).|0.02/0.29|0.02/0.33|0.02/0.33|ns|
|**Combinatorial**||||||
|TIDI|D pin to O pin propagation delay, no delay.|0.11|0.13|0.13|ns|
|TIDID|DDLY pin to O pin propagation delay (using<br>IDELAY).|0.12|0.14|0.14|ns|
|**Sequential Delays**||||||
|TIDLO|D pin to Q1 pin using flip-flop as a latch without<br>delay.|0.44|0.51|0.51|ns|
|TIDLOD|DDLY pin to Q1 pin using flip-flop as a latch (using<br>IDELAY).|<br>0.44|0.51|0.51|ns|
|TICKQ|CLK to Q outputs.|0.57|0.66|0.66|ns|
|TRQ_ILOGIC|SR pin to OQ/TQ out.|1.08|1.32|1.32|ns|
|TGSRQ_ILOGIC|Global set/reset to Q outputs.|7.60|10.51|10.51|ns|
|**Set/Reset**||||||
|TRPW_ILOGIC|Minimum pulse width, SR inputs.|0.72|0.72|0.72|ns, Min|



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**Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics** 

## _Table  22:_ **OLOGIC Switching Characteristics** 

|**Symbol**|**Description**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**Units**|
|---|---|---|---|---|---|
|||**1.0V**||**0.95V**||
|||**-2**|**-1**|**-1L**||
|**Setup/Hold**||||||
|TODCK/TOCKD|D1/D2 pins setup/hold with respect to CLK.|0.71/–0.11|0.84/–0.11|0.84/–0.11|ns|
|TOOCECK/TOCKOCE|OCE pin setup/hold with respect to CLK.|0.34/0.58|0.51/0.58|0.51/0.58|ns|
|TOSRCK/TOCKSR|SR pin setup/hold with respect to CLK.|0.44/0.21|0.80/0.21|0.80/0.21|ns|
|TOTCK/TOCKT|T1/T2 pins setup/hold with respect to CLK.|0.73/–0.14|0.89/–0.14|0.89/–0.14|ns|
|TOTCECK/TOCKTCE|TCE pin setup/hold with respect to CLK.|0.34/0.01|0.51/0.01|0.51/0.01|ns|
|**Combinatorial**||||||
|TODQ|D1 to OQ out or T1 to TQ out.|0.96|1.16|1.16|ns|
|**Sequential Delays**||||||
|TOCKQ|CLK to OQ/TQ out.|0.49|0.56|0.56|ns|
|TRQ_OLOGIC|SR pin to OQ/TQ out.|0.80|0.95|0.95|ns|
|TGSRQ_OLOGIC|Global set/reset to Q outputs.|7.60|10.51|10.51|ns|
|**Set/Reset**||||||
|TRPW_OLOGIC|Minimum pulse width, SR inputs.|0.74|0.74|0.74|ns, Min|



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**Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics** 

## **Input Serializer/Deserializer Switching Characteristics** 

_Table  23:_ **ISERDES Switching Characteristics** 

|**Symbol**|**Description**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**Units**|
|---|---|---|---|---|---|
|||**1.0V**||**0.95V**||
|||**-2**|**-1**|**-1L**||
|**Setup/Hold for Control Lines**||||||
|TISCCK_BITSLIP/<br>TISCKC_BITSLIP|BITSLIP pin setup/hold with respect to<br>CLKDIV.|0.02/0.15|0.02/0.17|0.02/0.17|ns|
|TISCCK_CE/<br>TISCKC_CE|CE pin setup/hold with respect to CLK<br>(for CE1).|0.50/–0.01|0.72/–0.01|0.72/–0.01|ns|
|TISCCK_CE2/<br>TISCKC_CE2|CE pin setup/hold with respect to CLKDIV<br>(for CE2).|–0.10/0.36|–0.10/0.40|–0.10/0.40|ns|
|**Setup/Hold for Data Lines**||||||
|TISDCK_D/<br>TISCKD_D|D pin setup/hold with respect to CLK.|–0.02/0.14|–0.02/0.17|–0.02/0.17|ns|
|TISDCK_DDLY/<br>TISCKD_DDLY|DDLY pin setup/hold with respect to CLK<br>(using IDELAY).(1)|–0.02/0.14|–0.02/0.17|–0.02/0.17|ns|
|TISDCK_D_DDR/<br>TISCKD_D_DDR|D pin setup/hold with respect to CLK at<br>DDR mode.|–0.02/0.14|–0.02/0.17|–0.02/0.17|ns|
|TISDCK_DDLY_DDR/<br>TISCKD_DDLY_DDR|D pin setup/hold with respect to CLK at<br>DDR mode (using IDELAY).(1)|0.14/0.14|0.17/0.17|0.17/0.17|ns|
|**Sequential Delays**||||||
|TISCKO_Q|CLKDIV to out at Q pin.|0.54|0.66|0.66|ns|
|**Propagation Delays**||||||
|TISDO_DO|D input to DO output pin.|0.11|0.13|0.13|ns|



## **Notes:** 

1. Recorded at 0 tap value. 

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**Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics** 

## **Output Serializer/Deserializer Switching Characteristics** 

_Table  24:_ **OSERDES Switching Characteristics** 

|**Symbol**|**Description**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**Units**|
|---|---|---|---|---|---|
|||**1.0V**||**0.95V**||
|||**-2**|**-1**|**-1L**||
|**Setup/Hold**||||||
|TOSDCK_D/<br>TOSCKD_D|D input setup/hold with respect to CLKDIV.|0.45/0.03|0.63/0.03|0.63/0.03|ns|
|TOSDCK_T/<br>TOSCKD_T|T input setup/hold with respect to CLK.|0.73/–0.13|0.88/–0.13|0.88/–0.13|ns|
|TOSDCK_T2/<br>TOSCKD_T2|T input setup/hold with respect to CLKDIV.|0.34/–0.13|0.39/–0.13|0.39/–0.13|ns|
|TOSCCK_OCE/<br>TOSCKC_OCE|OCE input setup/hold with respect to CLK.|0.34/0.58|0.51/0.58|0.51/0.58|ns|
|TOSCCK_S|SR (reset) input setup with respect to CLKDIV.|0.52|0.85|0.85|ns|
|TOSCCK_TCE/<br>TOSCKC_TCE|TCE input setup/hold with respect to CLK.|0.34/0.01|0.51/0.01|0.51/0.01|ns|
|**Sequential Delays**||||||
|TOSCKO_OQ|Clock to out from CLK to OQ.|0.42|0.48|0.48|ns|
|TOSCKO_TQ|Clock to out from CLK to TQ.|0.49|0.56|0.56|ns|
|**Combinatorial**||||||
|TOSDO_TTQ|T input to TQ out.|0.92|1.11|1.11|ns|



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**Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics** 

## **Input/Output Delay Switching Characteristics** 

_Table  25:_ **Input/Output Delay Switching Characteristics** 

|**Symbol**|**Description**|**VCCINT Operating Voltage and**<br>**Speed Grade**|**VCCINT Operating Voltage and**<br>**Speed Grade**|**VCCINT Operating Voltage and**<br>**Speed Grade**|**Units**|
|---|---|---|---|---|---|
|||**1.0V**||**0.95V**||
|||**-2**|**-1**|**-1L**||
|**IDELAYCTRL**||||||
|TDLYCCO_RDY|Reset to ready for IDELAYCTRL.|3.67|3.67|3.67|µs|
|FIDELAYCTRL_REF|Attribute REFCLK frequency = 200.00.(1)|200.00|200.00|200.00|MHz|
||Attribute REFCLK frequency = 300.00.(1)|300.00|300.00|300.00|MHz|
||Attribute REFCLK frequency = 400.00.(1)|400.00|N/A|N/A|MHz|
|IDELAYCTRL_REF_<br>PRECISION|REFCLK precision|±10|±10|±10|MHz|
|TIDELAYCTRL_RPW|Minimum reset pulse width.|59.28|59.28|59.28|ns|
|**IDELAY**||||||
|TIDELAYRESOLUTION|IDELAY chain delay resolution.|1/(32 x 2 x FREF)|||µs|
|TIDELAYPAT_JIT|Pattern dependent period jitter in delay chain for<br>clock pattern.(2)|0|0|0|ps<br>per tap|
||Pattern dependent period jitter in delay chain for<br>random data pattern (PRBS 23).(3)|±5|±5|±5|ps<br>per tap|
||Pattern dependent period jitter in delay chain for<br>random data pattern (PRBS 23).(4)|±9|±9|±9|ps<br>per tap|
|TIDELAY_CLK_MAX|Maximum frequency of CLK input to IDELAY.|680.00|600.00|600.00|MHz|
|TIDCCK_CE/<br>TIDCKC_CE|CE pin setup/hold with respect to C for IDELAY.|0.16/0.13|0.21/0.16|0.21/0.16|ns|
|TIDCCK_INC/<br>TIDCKC_INC|INC pin setup/hold with respect to C for IDELAY.|0.14/0.18|0.16/0.22|0.16/0.22|ns|
|TIDCCK_RST/<br>TIDCKC_RST|RST pin setup/hold with respect to C for IDELAY.|0.16/0.11|0.18/0.14|0.18/0.14|ns|
|TIDDO_IDATAIN|Propagation delay through IDELAY.|Note 5|Note 5|Note 5|ps|



## **Notes:** 

1. Average tap delay at 200 MHz = 78 ps, at 300 MHz = 52 ps, and at 400 MHz = 39 ps. 

2. When HIGH_PERFORMANCE mode is set to TRUE or FALSE. 

3. When HIGH_PERFORMANCE mode is set to TRUE. 

4. When HIGH_PERFORMANCE mode is set to FALSE. 

5. Delay depends on IDELAY tap setting. See the timing report for actual values. 

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**Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  26:_ **IO_FIFO Switching Characteristics** 

|**Symbol**|**Description**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**Units**|
|---|---|---|---|---|---|
|||**1.0V**||**0.95V**||
|||**-2**|**-1**|**-1L**||
|**IO_FIFO Clock to Out Delays**||||||
|TOFFCKO_DO|RDCLK to Q outputs.|0.60|0.68|0.68|ns|
|TCKO_FLAGS|Clock to IO_FIFO flags.|0.61|0.77|0.77|ns|
|**Setup/Hold**||||||
|TCCK_D/TCKC_D|D inputs to WRCLK.|0.51/0.02|0.58/0.02|0.58/0.02|ns|
|TIFFCCK_WREN/<br>TIFFCKC_WREN|WREN to WRCLK.|0.47/–0.01|0.53/–0.01|0.53/–0.01|ns|
|TOFFCCK_RDEN/<br>TOFFCKC_RDEN|RDEN to RDCLK.|0.58/0.02|0.66/0.02|0.66/0.02|ns|
|**Minimum Pulse Width**||||||
|TPWH_IO_FIFO|RESET, RDCLK, WRCLK.|2.15|2.15|2.15|ns|
|TPWL_IO_FIFO|RESET, RDCLK, WRCLK.|2.15|2.15|2.15|ns|
|Maximum Frequency||||||
|FMAX|RDCLK and WRCLK.|200.00|200.00|200.00|MHz|



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**Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics** 

## **CLB Switching Characteristics** 

_Table  27:_ **CLB Switching Characteristics** 

|**Symbol**|**Description**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**Units**|
|---|---|---|---|---|---|
|||**1.0V**||**0.95V**||
|||**-2**|**-1**|**-1L**||
|**Combinatorial Delays**||||||
|TILO|An – Dn LUT address to A.|0.11|0.13|0.13|ns, Max|
|TILO_2|An – Dn LUT address to AMUX/CMUX.|0.30|0.36|0.36|ns, Max|
|TILO_3|An – Dn LUT address to BMUX_A.|0.46|0.55|0.55|ns, Max|
|TITO|An – Dn inputs to A – D Q outputs.|1.05|1.27|1.27|ns, Max|
|TAXA|AX inputs to AMUX output.|0.69|0.84|0.84|ns, Max|
|TAXB|AX inputs to BMUX output.|0.66|0.83|0.83|ns, Max|
|TAXC|AX inputs to CMUX output.|0.68|0.82|0.82|ns, Max|
|TAXD|AX inputs to DMUX output.|0.75|0.90|0.90|ns, Max|
|TBXB|BX inputs to BMUX output.|0.57|0.69|0.69|ns, Max|
|TBXD|BX inputs to DMUX output.|0.69|0.82|0.82|ns, Max|
|TCXC|CX inputs to CMUX output.|0.48|0.58|0.58|ns, Max|
|TCXD|CX inputs to DMUX output.|0.59|0.71|0.71|ns, Max|
|TDXD|DX inputs to DMUX output.|0.58|0.70|0.70|ns, Max|
|**Sequential Delays**||||||
|TCKO|Clock to AQ – DQ outputs.|0.44|0.53|0.53|ns, Max|
|TSHCKO|Clock to AMUX – DMUX outputs.|0.53|0.66|0.66|ns, Max|
|**Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK**||||||
|TAS/TAH|AN – DN input to CLK on A – D flip-flops.|0.09/0.14|0.11/0.18|0.11/0.18|ns, Min|
|TDICK/TCKDI|AX – DX input to CLK on A – D flip-flops.|0.07/0.21|0.09/0.26|0.09/0.26|ns, Min|
||AX – DX input through MUXs and/or carry logic to<br>CLK on A – D flip-flops.|0.66/0.09|0.81/0.11|0.81/0.11|ns, Min|
|TCECK_CLB/<br>TCKCE_CLB|CE input to CLK on A – D flip-flops.|0.17/0.00|0.21/0.01|0.21/0.01|ns, Min|
|TSRCK/TCKSR|SR input to CLK on A – D flip-flops.|0.43/0.04|0.53/0.05|0.53/0.05|ns, Min|
|**Set/Reset**||||||
|TSRMIN|SR input minimum pulse width.|0.78|1.04|1.04|ns, Min|
|TRQ|Delay from SR input to AQ – DQ flip-flops.|0.59|0.71|0.71|ns, Max|
|TCEO|Delay from CE input to AQ – DQ flip-flops.|0.58|0.70|0.70|ns, Max|
|FTOG|Toggle frequency (for export control).|1286|1098|1098|MHz|



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**Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics** 

## **CLB Distributed RAM Switching Characteristics (SLICEM Only)** 

_Table  28:_ **CLB Distributed RAM Switching Characteristics** 

|**Symbol**|**Description**|**VCCINT Operating Voltage and**<br>**Speed Grade**|**VCCINT Operating Voltage and**<br>**Speed Grade**|**VCCINT Operating Voltage and**<br>**Speed Grade**|**Units**|
|---|---|---|---|---|---|
|||**1.0V**||**0.95V**||
|||**-2**|**-1**|**-1L**||
|**Sequential Delays**||||||
|TSHCKO|Clock to A – B outputs.|1.09|1.32|1.32|ns, Max|
|TSHCKO_1|Clock to AMUX – BMUX outputs.|1.53|1.86|1.86|ns, Max|
|**Setup and Hold Times Before/After Clock CLK**||||||
|TDS_LRAM/TDH_LRAM|A – D inputs to CLK.|0.60/0.30|0.72/0.35|0.72/0.35|ns, Min|
|TAS_LRAM/TAH_LRAM|Address An inputs to clock.|0.30/0.60|0.37/0.70|0.37/0.70|ns, Min|
||Address An inputs through MUXs and/or<br>carry logic to clock.|0.77/0.21|0.94/0.26|0.94/0.26|ns, Min|
|TWS_LRAM/TWH_LRAM|WE input to clock.|0.43/0.12|0.53/0.17|0.53/0.17|ns, Min|
|TCECK_LRAM/TCKCE_LRAM|CE input to CLK.|0.44/0.11|0.53/0.17|0.53/0.17|ns, Min|
|**Clock CLK**||||||
|TMPW_LRAM|Minimum pulse width.|1.13|1.25|1.25|ns, Min|
|TMCP|Minimum clock period.|2.26|2.50|2.50|ns, Min|



## **Notes:** 

1. TSHCKO also represents the CLK to XMUX output. Refer to the timing report for the CLK to XMUX path. 

## **CLB Shift Register Switching Characteristics (SLICEM Only)** 

_Table  29:_ **CLB Shift Register Switching Characteristics** 

|**Symbol**|**Description**|**VCCINT Operating Voltage and**<br>**Speed Grade**|**VCCINT Operating Voltage and**<br>**Speed Grade**|**VCCINT Operating Voltage and**<br>**Speed Grade**|**Units**|
|---|---|---|---|---|---|
|||**1.0V**||**0.95V**||
|||**-2**|**-1**|**-1L**||
|**Sequential Delays**||||||
|TREG|Clock to A – D outputs.|1.33|1.61|1.61|ns, Max|
|TREG_MUX|Clock to AMUX – DMUX output.|1.77|2.15|2.15|ns, Max|
|TREG_M31|Clock to DMUX output via M31 output.|1.23|1.46|1.46|ns, Max|
|**Setup and Hold Times Before/After Clock CLK**||||||
|TWS_SHFREG/ TWH_SHFREG|WE input.|0.41/0.12|0.51/0.17|0.51/0.17|ns, Min|
|TCECK_SHFREG/<br>TCKCE_SHFREG|CE input to CLK.|0.42/0.11|0.52/0.17|0.52/0.17|ns, Min|
|TDS_SHFREG/ TDH_SHFREG|A – D inputs to CLK.|0.37/0.37|0.44/0.43|0.44/0.43|ns, Min|
|**Clock CLK**||||||
|TMPW_SHFREG|Minimum pulse width.|0.86|0.98|0.98|ns, Min|



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## **Block RAM and FIFO Switching Characteristics** 

_Table  30:_ **Block RAM and FIFO Switching Characteristics** 

|**Symbol**|**Description**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**Units**|
|---|---|---|---|---|---|
|||**1.0V**||**0.95V**||
|||**-2**|**-1**|**-1L**||
|**Block RAM and FIFO Clock-to-Out Delays**||||||
|TRCKO_DO and<br>TRCKO_DO_REG|Clock CLK to DOUT output (without<br>output register).(1)(2)|2.13|2.46|2.46|ns, Max|
||Clock CLK to DOUT output (with output<br>register).(3)(4)|0.74|0.89|0.89|ns, Max|
|TRCKO_DO_ECC and<br>TRCKO_DO_ECC_REG|Clock CLK to DOUT output with ECC<br>(without output register).(1)(2)|3.04|3.84|3.84|ns, Max|
||Clock CLK to DOUT output with ECC<br>(with output register).(3)(4)|0.81|0.94|0.94|ns, Max|
|TRCKO_DO_CASCOUT and<br>TRCKO_DO_CASCOUT_REG|<br>Clock CLK to DOUT output with cascade<br>(without output register).(1)|2.88|3.30|3.30|ns, Max|
||Clock CLK to DOUT output with cascade<br>(with output register).(3)|1.28|1.46|1.46|ns, Max|
|TRCKO_FLAGS|Clock CLK to FIFO flags outputs.(5)|0.87|1.05|1.05|ns, Max|
|TRCKO_POINTERS|Clock CLK to FIFO pointers outputs.(6)|1.02|1.15|1.15|ns, Max|
|TRCKO_PARITY_ECC|Clock CLK to ECCPARITY in ECC encode<br>only mode.|0.85|0.94|0.94|ns, Max|
|TRCKO_SDBIT_ECCand<br>TRCKO_SDBIT_ECC_REG|Clock CLK to BITERR (without output<br>register).|2.81|3.55|3.55|ns, Max|
||Clock CLK to BITERR (with output<br>register).|0.76|0.89|0.89|ns, Max|
|TRCKO_RDADDR_ECCand<br>TRCKO_RDADDR_ECC_REG|Clock CLK to RDADDR output with ECC<br>(without output register).|0.88|1.07|1.07|ns, Max|
||Clock CLK to RDADDR output with ECC<br>(with output register).|0.93|1.08|1.08|ns, Max|
|**Setup and Hold Times Before/After Clock CLK**||||||
|TRCCK_ADDRA/<br>TRCKC_ADDRA|ADDR inputs.(7)|0.49/0.33|0.57/0.36|0.57/0.36|ns, Min|
|TRDCK_DI_WF_NC/<br>TRCKD_DI_WF_NC|Data input setup/hold time when block<br>RAM is configured in WRITE_FIRST or<br>NO_CHANGE mode.(8)|0.65/0.63|0.74/0.67|0.74/0.67|ns, Min|
|TRDCK_DI_RF/<br>TRCKD_DI_RF|Data input setup/hold time when block<br>RAM is configured in READ_FIRST<br>mode.(8)|0.22/0.34|0.25/0.41|0.25/0.41|ns, Min|
|TRDCK_DI_ECC/<br>TRCKD_DI_ECC|DIN inputs with block RAM ECC in<br>standard mode.(8)|0.55/0.46|0.63/0.50|0.63/0.50|ns, Min|
|TRDCK_DI_ECCW/<br>TRCKD_DI_ECCW|DIN inputs with block RAM ECC encode<br>only.(8)|1.02/0.46|1.17/0.50|1.17/0.50|ns, Min|



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**Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  30:_ **Block RAM and FIFO Switching Characteristics** _**(Cont’d)**_ 

|**Symbol**|**Description**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**Units**|
|---|---|---|---|---|---|
|||**1.0V**||**0.95V**||
|||**-2**|**-1**|**-1L**||
|TRDCK_DI_ECC_FIFO/<br>TRCKD_DI_ECC_FIFO|DIN inputs with FIFO ECC in standard<br>mode.(8)|1.15/0.59|1.32/0.64|1.32/0.64|ns, Min|
|TRCCK_INJECTBITERR/<br>TRCKC_INJECTBITERR|Inject single/double bit error in ECC<br>mode.|0.64/0.37|0.74/0.40|0.74/0.40|ns, Min|
|TRCCK_EN/TRCKC_EN|Block RAM enable (EN) input.|0.39/0.21|0.45/0.23|0.45/0.23|ns, Min|
|TRCCK_REGCE/<br>TRCKC_REGCE|CE input of output register.|0.29/0.15|0.36/0.16|0.36/0.16|ns, Min|
|TRCCK_RSTREG/<br>TRCKC_RSTREG|Synchronous RSTREG input.|0.32/0.07|0.35/0.07|0.35/0.07|ns, Min|
|TRCCK_RSTRAM/<br>TRCKC_RSTRAM|Synchronous RSTRAM input.|0.34/0.43|0.36/0.46|0.36/0.46|ns, Min|
|TRCCK_WEA/TRCKC_WEA|Write enable (WE) input (block RAM<br>only).|0.48/0.19|0.54/0.20|0.54/0.20|ns, Min|
|TRCCK_WREN/<br>TRCKC_WREN|WREN FIFO inputs.|0.46/0.35|0.47/0.43|0.47/0.43|ns, Min|
|TRCCK_RDEN/<br>TRCKC_RDEN|RDEN FIFO inputs.|0.43/0.35|0.43/0.43|0.43/0.43|ns, Min|
|**Reset Delays**||||||
|TRCO_FLAGS|Reset RST to FIFO flags/pointers.(9)|0.98|1.10|1.10|ns, Max|
|TRREC_RST/TRREM_RST|FIFO reset recovery and removal<br>timing.(10)|2.07/–0.81|2.37/–0.81|2.37/–0.81|ns, Max|
|**Maximum Frequency**||||||
|FMAX_BRAM_WF_NC|Block RAM (write first and no change<br>modes) when not in SDP RF mode.|460.83|388.20|388.20|MHz|
|FMAX_BRAM_RF_<br>PERFORMANCE|Block RAM (read first, performance<br>mode) when in SDP RF mode but no<br>address overlap between port A and<br>port B.|460.83|388.20|388.20|MHz|
|FMAX_BRAM_RF_<br>DELAYED_WRITE|Block RAM (read first, delayed write<br>mode) when in SDP RF mode and there<br>is possibility of overlap between port A<br>and port B addresses.|404.53|339.67|339.67|MHz|
|FMAX_CAS_WF_NC|Block RAM cascade (write first, no<br>change mode) when cascade but not in<br>RF mode.|418.59|345.78|345.78|MHz|
|FMAX_CAS_RF_<br>PERFORMANCE|Block RAM cascade (read first,<br>performance mode) when in cascade<br>with RF mode and no possibility of<br>address overlap/one port is disabled.|418.59|345.78|345.78|MHz|



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**Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  30:_ **Block RAM and FIFO Switching Characteristics** _**(Cont’d)**_ 

|**Symbol**|**Description**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**Units**|
|---|---|---|---|---|---|
|||**1.0V**||**0.95V**||
|||**-2**|**-1**|**-1L**||
|FMAX_CAS_RF_<br>DELAYED_WRITE|When in cascade RF mode and there is a<br>possibility of address overlap between<br>port A and port B.|362.19|297.35|297.35|MHz|
|FMAX_FIFO|FIFO in all modes without ECC.|460.83|388.20|388.20|MHz|
|FMAX_ECC|Block RAM and FIFO in ECC<br>configuration.|365.10|297.53|297.53|MHz|



## **Notes:** 

1. TRCKO_DOR includes TRCKO_DOW, TRCKO_DOPR, and TRCKO_DOPW as well as the B port equivalent timing parameters. 

2. These parameters also apply to synchronous FIFO with DO_REG = 0. 

3. TRCKO_DO includes TRCKO_DOP as well as the B port equivalent timing parameters. 

4. These parameters also apply to multi-rate (asynchronous) and synchronous FIFO with DO_REG = 1. 

5. TRCKO_FLAGS includes the following parameters: TRCKO_AEMPTY, TRCKO_AFULL, TRCKO_EMPTY, TRCKO_FULL, TRCKO_RDERR, TRCKO_WRERR. 

6. T includes both T and T . RCKO_POINTERS RCKO_RDCOUNT RCKO_WRCOUNT 

7. The ADDR setup and hold must be met when EN is asserted (even when WE is deasserted). Otherwise, block RAM data corruption is possible. 

8. These parameters include both A and B inputs as well as the parity inputs of A and B. 

9. TRCO_FLAGS includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT. 

10. RDEN and WREN must be held Low prior to and during reset. The FIFO reset must be asserted for at least five positive clock edges of the slowest clock (WRCLK or RDCLK). 

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**Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics** 

## **DSP48E1 Switching Characteristics** 

_Table  31:_ **DSP48E1 Switching Characteristics** 

|**Symbol**|**Description**|**VCCINT Operating**<br>**Voltage and Speed**<br>**Grade**|**VCCINT Operating**<br>**Voltage and Speed**<br>**Grade**|**VCCINT Operating**<br>**Voltage and Speed**<br>**Grade**|**Units**|
|---|---|---|---|---|---|
|||**1.0V**||**0.95V**||
|||**-2**|**-1**|**-1L**||
|**Setup and Hold Times of Data/Control Pins to the Input Register Clock**||||||
|TDSPDCK_A_AREG/<br>TDSPCKD_A_AREG|A input to A register CLK.|0.30/<br>0.13|0.37/<br>0.14|0.37/<br>0.14|ns|
|TDSPDCK_B_BREG/<br>TDSPCKD_B_BREG|B input to B register CLK.|0.38/<br>0.16|0.45/<br>0.18|0.45/<br>0.18|ns|
|TDSPDCK_C_CREG/<br>TDSPCKD_C_CREG|C input to C register CLK.|0.20/<br>0.19|0.24/<br>0.21|0.24/<br>0.21|ns|
|TDSPDCK_D_DREG/<br>TDSPCKD_D_DREG|D input to D register CLK.|0.32/<br>0.27|0.42/<br>0.27|0.42/<br>0.27|ns|
|TDSPDCK_ACIN_AREG/<br>TDSPCKD_ACIN_AREG|ACIN input to A register CLK.|0.27/<br>0.13|0.32/<br>0.14|0.32/<br>0.14|ns|
|TDSPDCK_BCIN_BREG/<br>TDSPCKD_BCIN_BREG|BCIN input to B register CLK.|0.29/<br>0.16|0.36/<br>0.18|0.36/<br>0.18|ns|
|**Setup and Hold Times of Data Pins to the Pipeline Register Clock**||||||
|TDSPDCK_{A, B}_MREG_MULT/<br>TDSPCKD_{A, B}_MREG_MULT|{A, B} input to M register CLK using<br>multiplier.|2.76/<br>–0.01|3.29/<br>–0.01|3.29/<br>–0.01|ns|
|TDSPDCK_{A, D}_ADREG/<br>TDSPCKD_{A, D}_ADREG|{A, D} input to AD register CLK.|1.48/<br>–0.02|1.76/<br>–0.02|1.76/<br>–0.02|ns|
|**Setup and Hold Times of Data/Control Pins to the Output Register Clock**||||||
|TDSPDCK_{A, B}_PREG_MULT/<br>TDSPCKD_{A, B}_PREG_MULT|{A, B} input to P register CLK using<br>multiplier.|4.60/<br>–0.28|5.48/<br>–0.28|5.48/<br>–0.28|ns|
|TDSPDCK_D_PREG_MULT/<br>TDSPCKD_D_PREG_MULT|D input to P register CLK using multiplier.|4.50/<br>–0.73|5.35/<br>–0.73|5.35/<br>–0.73|ns|
|TDSPDCK_{A, B} _PREG/<br>TDSPCKD_{A, B}_PREG|A or B input to P register CLK not using<br>multiplier.|1.98/<br>–0.28|2.35/<br>–0.28|2.35/<br>–0.28|ns|
|TDSPDCK_C_PREG/<br>TDSPCKD_C_PREG|C input to P register CLK not using multiplier.|1.76/<br>–0.26|2.10/<br>–0.26|2.10/<br>–0.26|ns|
|TDSPDCK_PCIN_PREG/<br>TDSPCKD_PCIN_PREG|PCIN input to P register CLK.|1.51/<br>–0.15|1.80/<br>–0.15|1.80/<br>–0.15|ns|
|**Setup and Hold Times of the CE Pins**||||||
|TDSPDCK_{CEA;CEB}_{AREG;BREG}/<br>TDSPCKD_{CEA;CEB}_{AREG;BREG}|{CEA; CEB} input to {A; B} register CLK.|0.42/<br>0.08|0.52/<br>0.11|0.52/<br>0.11|ns|
|TDSPDCK_CEC_CREG/<br>TDSPCKD_CEC_CREG|CEC input to C register CLK.|0.34/<br>0.11|0.42/<br>0.13|0.42/<br>0.13|ns|
|TDSPDCK_CED_DREG/<br>TDSPCKD_CED_DREG|CED input to D register CLK.|0.43/<br>–0.03|0.52/<br>–0.03|0.52/<br>–0.03|ns|



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**Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  31:_ **DSP48E1 Switching Characteristics** _**(Cont’d)**_ 

|**Symbol**|**Description**|**VCCINT Operating**<br>**Voltage and Speed**<br>**Grade**|**VCCINT Operating**<br>**Voltage and Speed**<br>**Grade**|**VCCINT Operating**<br>**Voltage and Speed**<br>**Grade**|**Units**|
|---|---|---|---|---|---|
|||**1.0V**||**0.95V**||
|||**-2**|**-1**|**-1L**||
|TDSPDCK_CEM_MREG/<br>TDSPCKD_CEM_MREG|CEM input to M register CLK.|0.21/<br>0.20|0.27/<br>0.23|0.27/<br>0.23|ns|
|TDSPDCK_CEP_PREG/<br>TDSPCKD_CEP_PREG|CEP input to P register CLK.|0.43/<br>0.01|0.53/<br>0.01|0.53/<br>0.01|ns|
|**Setup and Hold Times of the RST Pins**||||||
|TDSPDCK_{RSTA; RSTB}_{AREG; BREG}/<br>TDSPCKD_{RSTA; RSTB}_{AREG; BREG}|{RSTA, RSTB} input to {A, B} register CLK.|0.46/<br>0.13|0.55/<br>0.15|0.55/<br>0.15|ns|
|TDSPDCK_RSTC_CREG/<br>TDSPCKD_RSTC_CREG|RSTC input to C register CLK.|0.08/<br>0.11|0.09/<br>0.12|0.09/<br>0.12|ns|
|TDSPDCK_RSTD_DREG/<br>TDSPCKD_RSTD_DREG|RSTD input to D register CLK|0.50/<br>0.08|0.59/<br>0.09|0.59/<br>0.09|ns|
|TDSPDCK_RSTM_MREG/<br>TDSPCKD_RSTM_MREG|RSTM input to M register CLK|0.23/<br>0.24|0.27/<br>0.28|0.27/<br>0.28|ns|
|TDSPDCK_RSTP_PREG/<br>TDSPCKD_RSTP_PREG|RSTP input to P register CLK|0.30/<br>0.01|0.35/<br>0.01|0.35/<br>0.01|ns|
|**Combinatorial Delays from Input Pins to Output Pins**||||||
|TDSPDO_A_CARRYOUT_MULT|A input to CARRYOUT output using multiplier.|4.35|5.18|5.18|ns|
|TDSPDO_D_P_MULT|D input to P output using multiplier.|4.26|5.07|5.07|ns|
|TDSPDO_B_P|B input to P output not using multiplier.|1.75|2.08|2.08|ns|
|TDSPDO_C_P|C input to P output.|1.53|1.82|1.82|ns|
|**Combinatorial Delays from Input Pins to Cascading Output Pins**||||||
|TDSPDO_{A; B}_{ACOUT; BCOUT}|{A, B} input to {ACOUT, BCOUT} output.|0.63|0.74|0.74|ns|
|TDSPDO_{A, B}_CARRYCASCOUT_MULT|{A, B} input to CARRYCASCOUT output using<br>multiplier.|4.65|5.54|5.54|ns|
|TDSPDO_D_CARRYCASCOUT_MULT|D input to CARRYCASCOUT output using<br>multiplier.|4.54|5.40|5.40|ns|
|TDSPDO_{A, B}_CARRYCASCOUT|{A, B} input to CARRYCASCOUT output not<br>using multiplier.|2.03|2.41|2.41|ns|
|TDSPDO_C_CARRYCASCOUT|C input to CARRYCASCOUT output.|1.81|2.15|2.15|ns|
|**Combinatorial Delays from Cascading Input Pins to All Output Pins**||||||
|TDSPDO_ACIN_P_MULT|ACIN input to P output using multiplier.|4.19|5.00|5.00|ns|
|TDSPDO_ACIN_P|ACIN input to P output not using multiplier.|1.57|1.88|1.88|ns|
|TDSPDO_ACIN_ACOUT|ACIN input to ACOUT output.|0.44|0.53|0.53|ns|
|TDSPDO_ACIN_CARRYCASCOUT_MULT|ACIN input to CARRYCASCOUT output using<br>multiplier.|4.47|5.33|5.33|ns|
|TDSPDO_ACIN_CARRYCASCOUT|ACIN input to CARRYCASCOUT output not<br>using multiplier.|1.85|2.21|2.21|ns|
|TDSPDO_PCIN_P|PCIN input to P output.|1.28|1.52|1.52|ns|



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**Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  31:_ **DSP48E1 Switching Characteristics** _**(Cont’d)**_ 

|**Symbol**|**Description**|**VCCINT Operating**<br>**Voltage and Speed**<br>**Grade**|**VCCINT Operating**<br>**Voltage and Speed**<br>**Grade**|**VCCINT Operating**<br>**Voltage and Speed**<br>**Grade**|**Units**|
|---|---|---|---|---|---|
|||**1.0V**||**0.95V**||
|||**-2**|**-1**|**-1L**||
|TDSPDO_PCIN_CARRYCASCOUT|PCIN input to CARRYCASCOUT output.|1.56|1.85|1.85|ns|
|**Clock to Outs from Output Register Clock to Output Pins**||||||
|TDSPCKO_P_PREG|CLK PREG to P output.|0.37|0.44|0.44|ns|
|TDSPCKO_CARRYCASCOUT_PREG|CLK PREG to CARRYCASCOUT output.|0.59|0.69|0.69|ns|
|**Clock to Outs from Pipeline Register Clock to Output Pins**||||||
|TDSPCKO_P_MREG|CLK MREG to P output.|1.93|2.31|2.31|ns|
|TDSPCKO_CARRYCASCOUT_MREG|CLK MREG to CARRYCASCOUT output.|2.21|2.64|2.64|ns|
|TDSPCKO_P_ADREG_MULT|CLK ADREG to P output using multiplier.|3.10|3.69|3.69|ns|
|TDSPCKO_CARRYCASCOUT_ADREG_MULT|CLK ADREG to CARRYCASCOUT output using<br>multiplier.|3.38|4.02|4.02|ns|
|**Clock to Outs from Input Register Clock to Output Pins**||||||
|TDSPCKO_P_AREG_MULT|CLK AREG to P output using multiplier.|4.51|5.37|5.37|ns|
|TDSPCKO_P_BREG|CLK BREG to P output not using multiplier.|1.87|2.22|2.22|ns|
|TDSPCKO_P_CREG|CLK CREG to P output not using multiplier.|1.93|2.30|2.30|ns|
|TDSPCKO_P_DREG_MULT|CLK DREG to P output using multiplier.|4.48|5.32|5.32|ns|
|**Clock to Outs from Input Register Clock to Cascading Output Pins**||||||
|TDSPCKO_{ACOUT; BCOUT}_<br>{AREG; BREG}|CLK (ACOUT, BCOUT) to {A,B} register<br>output.|0.73|0.87|0.87|ns|
|TDSPCKO_CARRYCASCOUT_<br>{AREG, BREG}_MULT|CLK (AREG, BREG) to CARRYCASCOUT<br>output using multiplier.|4.79|5.70|5.70|ns|
|TDSPCKO_CARRYCASCOUT_ BREG|CLK BREG to CARRYCASCOUT output not<br>using multiplier.|2.15|2.55|2.55|ns|
|TDSPCKO_CARRYCASCOUT_ DREG_MULT|CLK DREG to CARRYCASCOUT output using<br>multiplier.|4.76|5.65|5.65|ns|
|TDSPCKO_CARRYCASCOUT_ CREG|CLK CREG to CARRYCASCOUT output.|2.21|2.63|2.63|ns|
|**Maximum Frequency**||||||
|FMAX|With all registers used.|550.66|464.25|464.25|MHz|
|FMAX_PATDET|With pattern detector.|465.77|392.93|392.93|MHz|
|FMAX_MULT_NOMREG|Two register multiply without MREG.|305.62|257.47|257.47|MHz|
|FMAX_MULT_NOMREG_PATDET|Two register multiply without MREG with<br>pattern detect.|277.62|233.92|233.92|MHz|
|FMAX_PREADD_MULT_NOADREG|Without ADREG.|346.26|290.44|290.44|MHz|
|FMAX_PREADD_MULT_NOADREG_PATDET|Without ADREG with pattern detect.|346.26|290.44|290.44|MHz|
|FMAX_NOPIPELINEREG|Without pipeline registers (MREG, ADREG).|227.01|190.69|190.69|MHz|
|FMAX_NOPIPELINEREG_PATDET|Without pipeline registers (MREG, ADREG)<br>with pattern detect.|211.15|177.43|177.43|MHz|



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**Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics** 

## **Clock Buffers and Networks** 

_Table  32:_ **Global Clock Switching Characteristics (Including BUFGCTRL)** 

|**Symbol**|**Description**|**VCCINT Operating Voltage and**<br>**Speed Grade**|**VCCINT Operating Voltage and**<br>**Speed Grade**|**VCCINT Operating Voltage and**<br>**Speed Grade**|**Units**|
|---|---|---|---|---|---|
|||**1.0V**||**0.95V**||
|||**-2**|**-1**|**-1L**||
|TBCCCK_CE/TBCCKC_CE(1)|CE pins setup/hold.|0.13/0.40|0.16/0.41|0.16/0.41|ns|
|TBCCCK_S/ TBCCKC_S(1)|S pins setup/hold.|0.13/0.40|0.16/0.41|0.16/0.41|ns|
|TBCCKO_O(2)|BUFGCTRL delay from I0/I1 to O.|0.09|0.10|0.10|ns|
|**Maximum Frequency**||||||
|FMAX_BUFG|Global clock tree (BUFG).|628.00|464.00|464.00|MHz|



## **Notes:** 

1. TBCCCK_CE and TBCCKC_CE must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These parameters do not apply to the BUFGMUX primitive that assures glitch-free operation. The other global clock setup and hold times are optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching between clocks. 

2. TBGCKO_O (BUFG delay from I0 to O) values are the same as TBCCKO_O values. 

_Table  33:_ **Input/Output Clock Switching Characteristics (BUFIO)** 

|**Symbol**|**Description**|**VCCINT Operating Voltage and**<br>**Speed Grade**|**VCCINT Operating Voltage and**<br>**Speed Grade**|**VCCINT Operating Voltage and**<br>**Speed Grade**|**Units**|
|---|---|---|---|---|---|
|||**1.0V**||**0.95V**||
|||**-2**|**-1**|**-1L**||
|TBIOCKO_O|Clock to out delay from I to O.|1.26|1.54|1.54|ns|
|**Maximum Frequency**||||||
|FMAX_BUFIO|I/O clock tree (BUFIO).|680.00|600.00|600.00|MHz|



_Table  34:_ **Regional Clock Buffer Switching Characteristics (BUFR)** 

|**Symbol**|**Description**|**VCCINT Operating Voltage and**<br>**Speed Grade**|**VCCINT Operating Voltage and**<br>**Speed Grade**|**VCCINT Operating Voltage and**<br>**Speed Grade**|**Units**|
|---|---|---|---|---|---|
|||**1.0V**||**0.95V**||
|||**-2**|**-1**|**-1L**||
|TBRCKO_O|Clock to out delay from I to O.|0.76|0.99|0.99|ns|
|TBRCKO_O_BYP|Clock to out delay from I to O with Divide Bypass<br>attribute set.|0.39|0.52|0.52|ns|
|TBRDO_O|Propagation delay from CLR to O.|0.85|1.09|1.09|ns|
|**Maximum Frequency**||||||
|FMAX_BUFR(1)|Regional clock tree (BUFR).|375.00|315.00|315.00|MHz|



## **Notes:** 

1. The maximum input frequency to the BUFR is the BUFIO FMAX frequency. 

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**Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  35:_ **Horizontal Clock Buffer Switching Characteristics (BUFH)** 

|**Symbol**|**Description**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**Units**|
|---|---|---|---|---|---|
|||**1.0V**||**0.95V**||
|||**-2**|**-1**|**-1L**||
|TBHCKO_O|BUFH delay from I to O.|0.11|0.13|0.13|ns|
|TBHCCK_CE/ TBHCKC_CE|CE pin setup and hold.|0.22/0.15|0.28/0.21|0.28/0.21|ns|
|**Maximum Frequency**||||||
|FMAX_BUFH|Horizontal clock buffer (BUFH).|628.00|464.00|464.00|MHz|



_Table  36:_ **Duty Cycle Distortion and Clock-Tree Skew** 

|**Symbol**|**Description**|**Device**|**VCCINT Operating Voltage and**<br>**Speed Grade**|**VCCINT Operating Voltage and**<br>**Speed Grade**|**VCCINT Operating Voltage and**<br>**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|
||||**1.0V**||**0.95V**||
||||**-2**|**-1**|**-1L**||
|TDCD_CLK|Global clock tree duty-cycle distortion.(1)|All|0.20|0.20|0.20|ns|
|TCKSKEW|Global clock tree skew.(2)|XC7S6|0.05|0.06|0.06|ns|
|||XC7S15|0.05|0.06|0.06|ns|
|||XC7S25|0.26|0.26|0.26|ns|
|||XC7S50|0.26|0.26|0.26|ns|
|||XC7S75|0.33|0.36|0.36|ns|
|||XC7S100|0.33|0.36|0.36|ns|
|||XA7S6|0.05|0.06|N/A|ns|
|||XA7S15|0.05|0.06|N/A|ns|
|||XA7S25|0.26|0.26|N/A|ns|
|||XA7S50|0.26|0.26|N/A|ns|
|||XA7S75|0.33|0.36|N/A|ns|
|||XA7S100|0.33|0.36|N/A|ns|
|TDCD_BUFIO|I/O clock tree duty cycle distortion.|All|0.14|0.14|0.14|ns|
|TBUFIOSKEW|I/O clock tree skew across one clock region.|All|0.03|0.03|0.03|ns|
|TDCD_BUFR|Regional clock tree duty cycle distortion.|All|0.18|0.18|0.18|ns|



## **Notes:** 

1. These parameters represent the worst-case duty cycle distortion observable at the I/O flip flops. For all I/O standards, IBIS can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical rise/fall times. 

2. The TCKSKEW value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx timing analysis tools to evaluate clock skew specific to your application. 

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**Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics** 

## **MMCM Switching Characteristics** 

_Table  37:_ **MMCM Specification** 

|**Symbol**|**Description**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**Units**|
|---|---|---|---|---|---|
|||**1.0V**||**0.95V**||
|||**-2**|**-1**|**-1L**||
|MMCM_FINMAX|Maximum input clock frequency.|800.00|800.00|800.00|MHz|
|MMCM_FINMIN|Minimum input clock frequency.|10.00|10.00|10.00|MHz|
|MMCM_FINJITTER|Maximum input clock period jitter.|< 20% of clock input period or 1 ns Max||||
|MMCM_FINDUTY|Allowable input duty cycle: 10—49 MHz.|25|25|25|%|
||Allowable input duty cycle: 50—199<br>MHz.|30|30|30|%|
||Allowable input duty cycle: 200—399<br>MHz.|35|35|35|%|
||Allowable input duty cycle: 400—499<br>MHz.|40|40|40|%|
||Allowable input duty cycle: > 500 MHz.|45|45|45|%|
|MMCM_FMIN_PSCLK|Minimum dynamic phase-shift clock<br>frequency.|0.01|0.01|0.01|MHz|
|MMCM_FMAX_PSCLK|Maximum dynamic phase-shift clock<br>frequency.|500.00|450.00|450.00|MHz|
|MMCM_FVCOMIN|Minimum MMCM VCO frequency.|600.00|600.00|600.00|MHz|
|MMCM_FVCOMAX|Maximum MMCM VCO frequency.|1440.00|1200.00|1200.00|MHz|
|MMCM_FBANDWIDTH|Low MMCM bandwidth at typical.(1)|1.00|1.00|1.00|MHz|
||High MMCM bandwidth at typical.(1)|4.00|4.00|4.00|MHz|
|MMCM_TSTATPHAOFFSET|Static phase offset of the MMCM<br>outputs.(2)|0.12|0.12|0.12|ns|
|MMCM_TOUTJITTER|MMCM output jitter.|Note 3||||
|MMCM_TOUTDUTY|MMCM output clock duty-cycle<br>precision.(4)|0.20|0.20|0.20|ns|
|MMCM_TLOCKMAX|MMCM maximum lock time.|100.00|100.00|100.00|µs|
|MMCM_FOUTMAX|MMCM maximum output frequency.|800.00|800.00|800.00|MHz|
|MMCM_FOUTMIN|MMCM minimum output frequency.(5)(6)|4.69|4.69|4.69|MHz|
|MMCM_TEXTFDVAR|External clock feedback variation.|< 20% of clock input period or 1 ns Max||||
|MMCM_RSTMINPULSE|Minimum reset pulse width.|5.00|5.00|5.00|ns|
|MMCM_FPFDMAX|Maximum frequency at the phase<br>frequency detector.|500.00|450.00|450.00|MHz|
|MMCM_FPFDMIN|Minimum frequency at the phase<br>frequency detector.|10.00|10.00|10.00|MHz|
|MMCM_TFBDELAY|Maximum delay in the feedback path.|3 ns Max or one CLKIN cycle||||
|**MMCM Switching Characteristics Setup and Hold**||||||
|TMMCMDCK_PSEN/<br>TMMCMCKD_PSEN|Setup and hold of phase-shift enable.|1.04/0.00|1.04/0.00|1.04/0.00|ns|



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**Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics** 

## _Table  37:_ **MMCM Specification** _**(Cont’d)**_ 

|**Symbol**|**Description**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**Units**|
|---|---|---|---|---|---|
|||**1.0V**||**0.95V**||
|||**-2**|**-1**|**-1L**||
|TMMCMDCK_PSINCDEC/<br>TMMCMCKD_PSINCDEC|Setup and hold of phase-shift<br>increment/decrement.|1.04/0.00|1.04/0.00|1.04/0.00|ns|
|TMMCMCKO_PSDONE|Phase shift clock-to-out of PSDONE.|0.68|0.81|0.81|ns|
|**Dynamic Reconfiguration Port (DRP) for MMCM Before and After DCLK**||||||
|TMMCMDCK_DADDR/<br>TMMCMCKD_DADDR|DADDR setup/hold.|1.40/0.15|1.63/0.15|1.63/0.15|ns, Min|
|TMMCMDCK_DI/<br>TMMCMCKD_DI|DI setup/hold.|1.40/0.15|1.63/0.15|1.63/0.15|ns, Min|
|TMMCMDCK_DEN/<br>TMMCMCKD_DEN|DEN setup/hold.|1.97/0.00|2.29/0.00|2.29/0.00|ns, Min|
|TMMCMDCK_DWE/<br>TMMCMCKD_DWE|DWE setup/hold.|1.40/0.15|1.63/0.15|1.63/0.15|ns, Min|
|TMMCMCKO_DRDY|CLK to out of DRDY.|0.72|0.99|0.99|ns, Max|
|FDCK|DCLK frequency.|200.00|200.00|200.00|MHz, Max|



## **Notes:** 

1. The MMCM does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies. 

2. The static offset is measured between any MMCM outputs with identical phase. 

3. Values for this parameter are available in the _Clocking Wizard_ [Ref 8]. 

4. Includes global clock buffer. 

5. Calculated as FVCO/128 assuming output duty cycle is 50%. 

6. When CLKOUT4_CASCADE = TRUE, MMCM_FOUTMIN is 0.036 MHz. 

## **PLL Switching Characteristics** 

_Table  38:_ **PLL Specification** 

|**Symbol**|**Description**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**Units**|
|---|---|---|---|---|---|
|||**1.0V**||**0.95V**||
|||**-2**|**-1**|**-1L**||
|PLL_FINMAX|Maximum input clock frequency.|800.00|800.00|800.00|MHz|
|PLL_FINMIN|Minimum input clock frequency.|19.00|19.00|19.00|MHz|
|PLL_FINJITTER|Maximum input clock period jitter.|< 20% of clock input period or 1 ns Max||||
|PLL_FINDUTY|Allowable input duty cycle: 19—49 MHz.|25|25|25|%|
||Allowable input duty cycle: 50—199 MHz.|30|30|30|%|
||Allowable input duty cycle: 200—399 MHz.|35|35|35|%|
||Allowable input duty cycle: 400—499 MHz.|40|40|40|%|
||Allowable input duty cycle: >500 MHz.|45|45|45|%|
|PLL_FVCOMIN|Minimum PLL VCO frequency.|800.00|800.00|800.00|MHz|
|PLL_FVCOMAX|Maximum PLL VCO frequency.|1866.00|1600.00|1600.00|MHz|



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## _Table  38:_ **PLL Specification** 

|**Symbol**|**Description**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**Units**|
|---|---|---|---|---|---|
|||**1.0V**||**0.95V**||
|||**-2**|**-1**|**-1L**||
|PLL_FBANDWIDTH|Low PLL bandwidth at typical.|1.00|1.00|1.00|MHz|
||High PLL bandwidth at typical.(1)|4.00|4.00|4.00|MHz|
|PLL_TSTATPHAOFFSET|Static phase offset of the PLL outputs.(2)|0.12|0.12|0.12|ns|
|PLL_TOUTJITTER|PLL output jitter.|Note 3||||
|PLL_TOUTDUTY|PLL output clock duty-cycle precision.(4)|0.20|0.20|0.20|ns|
|PLL_TLOCKMAX|PLL maximum lock time.|100.00|100.00|100.00|µs|
|PLL_FOUTMAX|PLL maximum output frequency.|800.00|800.00|800.00|MHz|
|PLL_FOUTMIN|PLL minimum output frequency.(5)|6.25|6.25|6.25|MHz|
|PLL_TEXTFDVAR|External clock feedback variation.|< 20% of clock input period or 1 ns Max||||
|PLL_RSTMINPULSE|Minimum reset pulse width.|5.00|5.00|5.00|ns|
|PLL_FPFDMAX|Maximum frequency at the phase<br>frequency detector.|500.00|450.00|450.00|MHz|
|PLL_FPFDMIN|Minimum frequency at the phase frequency<br>detector.|19.00|19.00|19.00|MHz|
|PLL_TFBDELAY|Maximum delay in the feedback path.|3 ns Max or one CLKIN cycle||||
|**Dynamic Reconfiguration Port (DRP) for PLL Before and After DCLK**||||||
|TPLLDCK_DADDR/<br>TPLLCKD_DADDR|Setup and hold of D address.|1.40/0.15|1.63/0.15|1.63/0.15|ns, Min|
|TPLLDCK_DI/<br>TPLLCKD_DI|Setup and hold of D input.|1.40/0.15|1.63/0.15|1.63/0.15|ns, Min|
|TPLLDCK_DEN/<br>TPLLCKD_DEN|Setup and hold of D enable.|1.97/0.00|2.29/0.00|2.29/0.00|ns, Min|
|TPLLDCK_DWE/<br>TPLLCKD_DWE|Setup and hold of D write enable.|1.40/0.15|1.63/0.15|1.63/0.15|ns, Min|
|TPLLCKO_DRDY|CLK to out of DRDY.|0.72|0.99|0.99|ns, Max|
|FDCK|DCLK frequency.|200.00|200.00|200.00|MHz, Max|



## **Notes:** 

1. The PLL does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies. 

2. The static offset is measured between any PLL outputs with identical phase. 

3. Values for this parameter are available in the _Clocking Wizard_ [Ref 8]. 4. Includes global clock buffer. 

5. Calculated as FVCO/128 assuming output duty cycle is 50%. 

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**Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics** 

## **Device Pin-to-Pin Output Parameter Guidelines** 

_Table  39:_ **Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Near Clock Region)[(1)]** 

|**Symbol**|**Description**|**Device**|**VCCINT Operating Voltage and**<br>**Speed Grade**|**VCCINT Operating Voltage and**<br>**Speed Grade**|**VCCINT Operating Voltage and**<br>**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|
||||**1.0V**||**0.95V**||
||||**-2**|**-1**|**-1L**||
|**SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate,****_without_ MMCM/PLL.**|||||||
|TICKOF|Clock-capable clock input and OUTFF at<br>pins/banks closest to the BUFGs_without_<br>MMCM/PLL (near clock region).(2)|XC7S6|5.55|6.50|6.50|ns|
|||XC7S15|5.55|6.50|6.50|ns|
|||XC7S25|5.55|6.44|6.44|ns|
|||XC7S50|5.71|6.62|6.62|ns|
|||XC7S75|5.73|6.71|6.71|ns|
|||XC7S100|5.73|6.71|6.71|ns|
|||XA7S6|5.55|6.50|N/A|ns|
|||XA7S15|5.55|6.50|N/A|ns|
|||XA7S25|5.55|6.44|N/A|ns|
|||XA7S50|5.71|6.62|N/A|ns|
|||XA7S75|5.73|6.71|N/A|ns|
|||XA7S100|5.73|6.71|N/A|ns|



## **Notes:** 

1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 

2. Refer to the _Die Level Bank Numbering Overview_ section of the _7 Series FPGA Packaging and Pinout Specification_ (UG475) [Ref 4]. 

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**Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  40:_ **Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Far Clock Region)[(1)]** 

|**Symbol**|**Description**|**Device**|**VCCINT Operating Voltage and**<br>**Speed Grade**|**VCCINT Operating Voltage and**<br>**Speed Grade**|**VCCINT Operating Voltage and**<br>**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|
||||**1.0V**||**0.95V**||
||||**-2**|**-1**|**-1L**||
|**SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate,****_without_ MMCM/PLL.**|||||||
|TICKOFFAR|Clock-capable clock input and OUTFF at<br>pins/banks farthest from the BUFGs_without_<br>MMCM/PLL (far clock region).(2)|XC7S6|5.55|6.50|6.50|ns|
|||XC7S15|5.55|6.50|6.50|ns|
|||XC7S25|5.55|6.44|6.44|ns|
|||XC7S50|5.71|6.62|6.62|ns|
|||XC7S75|6.01|7.02|7.02|ns|
|||XC7S100|6.01|7.02|7.02|ns|
|||XA7S6|5.55|6.50|N/A|ns|
|||XA7S15|5.55|6.50|N/A|ns|
|||XA7S25|5.55|6.44|N/A|ns|
|||XA7S50|5.71|6.62|N/A|ns|
|||XA7S75|6.01|7.02|N/A|ns|
|||XA7S100|6.01|7.02|N/A|ns|



## **Notes:** 

1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 

2. Refer to the _Die Level Bank Numbering Overview_ section of the _7 Series FPGA Packaging and Pinout Specification_ (UG475) [Ref 4]. 

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**Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  41:_ **Clock-Capable Clock Input to Output Delay With MMCM[(1)]** 

|**Symbol**|**Description**|**Device**|**VCCINT Operating Voltage and**<br>**Speed Grade**|**VCCINT Operating Voltage and**<br>**Speed Grade**|**VCCINT Operating Voltage and**<br>**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|
||||**1.0V**||**0.95V**||
||||**-2**|**-1**|**-1L**||
|**SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate,****_with_ MMCM.**|||||||
|TICKOFMMCMCC|Clock-capable clock input and OUTFF_with_<br>MMCM.(2)|XC7S6|1.03|1.03|1.03|ns|
|||XC7S15|1.03|1.03|1.03|ns|
|||XC7S25|1.00|1.00|1.00|ns|
|||XC7S50|1.00|1.00|1.00|ns|
|||XC7S75|1.00|1.00|1.00|ns|
|||XC7S100|1.00|1.00|1.00|ns|
|||XA7S6|1.03|1.03|N/A|ns|
|||XA7S15|1.03|1.03|N/A|ns|
|||XA7S25|1.00|1.00|N/A|ns|
|||XA7S50|1.00|1.00|N/A|ns|
|||XA7S75|1.00|1.00|N/A|ns|
|||XA7S100|1.00|1.00|N/A|ns|



## **Notes:** 

1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 

2. MMCM output jitter is already included in the timing calculation. 

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**Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  42:_ **Clock-Capable Clock Input to Output Delay With PLL[(1)]** 

|**Symbol**|**Description**|**Device**|**VCCINT Operating Voltage and**<br>**Speed Grade**|**VCCINT Operating Voltage and**<br>**Speed Grade**|**VCCINT Operating Voltage and**<br>**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|
||||**1.0V**||**0.95V**||
||||**-2**|**-1**|**-1L**||
|**SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate,****_with_ PLL.**|||||||
|TICKOFPLLCC|Clock-capable clock input and OUTFF_with_<br>PLL.(2)|XC7S6|0.85|0.85|0.85|ns|
|||XC7S15|0.85|0.85|0.85|ns|
|||XC7S25|0.83|0.83|0.83|ns|
|||XC7S50|0.83|0.83|0.83|ns|
|||XC7S75|0.83|0.83|0.83|ns|
|||XC7S100|0.83|0.83|0.83|ns|
|||XA7S6|0.85|0.85|N/A|ns|
|||XA7S15|0.85|0.85|N/A|ns|
|||XA7S25|0.83|0.83|N/A|ns|
|||XA7S50|0.83|0.83|N/A|ns|
|||XA7S75|0.83|0.83|N/A|ns|
|||XA7S100|0.83|0.83|N/A|ns|



## **Notes:** 

1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 

2. PLL output jitter is already included in the timing calculation. 

_Table  43:_ **Pin-to-Pin, Clock-to-Out using BUFIO** 

|**Symbol**|**Description**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**Units**|
|---|---|---|---|---|---|
|||**1.0V**||**0.95V**||
|||**-2**|**-1**|**-1L**||
|**SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with BUFIO.**||||||
|TICKOFCS|Clock to out of I/O clock.|5.61|6.64|6.64|ns|



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**Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics** 

## **Device Pin-to-Pin Input Parameter Guidelines** 

All devices are 100% functionally tested. Values are expressed in nanoseconds unless otherwise noted. 

_Table  44:_ **Global Clock Input Setup and Hold Without MMCM/PLL with ZHOLD_DELAY on HR I/O Banks** 

|**Symbol**|**Description**|**Device**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**Units**|
|---|---|---|---|---|---|---|
||||**1.0V**||**0.95V**||
||||**-2**|**-1**|**-1L**||
|**Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15 Standard.(1)**|||||||
|TPSFD/<br>TPHFD|Full delay (legacy delay or default<br>delay) global clock input and IFF(2)<br>without MMCM/PLL with ZHOLD_DELAY<br>on HR I/O banks.|XC7S6|2.76/–0.40|3.17/–0.40|3.17/–0.40|ns|
|||XC7S15|2.76/–0.40|3.17/–0.40|3.17/–0.40|ns|
|||XC7S25|2.67/–0.37|3.12/–0.37|3.12/–0.37|ns|
|||XC7S50|2.66/–0.28|3.11/–0.28|3.11/–0.28|ns|
|||XC7S75|2.91/–0.33|3.36/–0.33|3.36/–0.33|ns|
|||XC7S100|2.91/–0.33|3.36/–0.33|3.36/–0.33|ns|
|||XA7S6|2.76/–0.40|3.17/–0.40|N/A|ns|
|||XA7S15|2.76/–0.40|3.17/–0.40|N/A|ns|
|||XA7S25|2.67/–0.37|3.12/–0.37|N/A|ns|
|||XA7S50|2.66/–0.28|3.11/–0.28|N/A|ns|
|||XA7S75|2.91/–0.33|3.36/–0.33|N/A|ns|
|||XA7S100|2.91/–0.33|3.36/–0.33|N/A|ns|



## **Notes:** 

1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage. 

2. IFF = Input flip-flop or latch. 

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_Table  45:_ **Clock-Capable Clock Input Setup and Hold With MMCM** 

|**Symbol**|**Description**|**Device**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**Units**|
|---|---|---|---|---|---|---|
||||**1.0V**||**0.95V**||
||||**-2**|**-1**|**-1L**||
|**Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15 Standard.(1)(2)**|||||||
|TPSMMCMCC/<br>TPHMMCMCC|No delay clock-capable clock input and<br>IFF(3)with MMCM.|XC7S6|2.73/–0.59|3.27/–0.59|3.27/–0.59|ns|
|||XC7S15|2.73/–0.59|3.27/–0.59|3.27/–0.59|ns|
|||XC7S25|2.69/–0.61|3.21/–0.61|3.21/–0.61|ns|
|||XC7S50|2.81/–0.62|3.35/–0.62|3.35/–0.62|ns|
|||XC7S75|2.81/–0.62|3.36/–0.62|3.36/–0.62|ns|
|||XC7S100|2.81/–0.62|3.36/–0.62|3.36/–0.62|ns|
|||XA7S6|2.73/–0.59|3.27/–0.59|N/A|ns|
|||XA7S15|2.73/–0.59|3.27/–0.59|N/A|ns|
|||XA7S25|2.69/–0.61|3.21/–0.61|N/A|ns|
|||XA7S50|2.81/–0.62|3.35/–0.62|N/A|ns|
|||XA7S75|2.81/–0.62|3.36/–0.62|N/A|ns|
|||XA7S100|2.81/–0.62|3.36/–0.62|N/A|ns|



## **Notes:** 

1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage. 

2. Use IBIS to determine any duty-cycle distortion incurred using various standards. 

3. IFF = Input flip-flop or latch. 

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_Table  46:_ **Clock-Capable Clock Input Setup and Hold With PLL** 

|**Symbol**|**Description**|**Device**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**Units**|
|---|---|---|---|---|---|---|
||||**1.0V**||**0.95V**||
||||**-2**|**-1**|**-1L**||
|**Input Setup and Hold Time Relative to Clock-Capable Clock Input Signal for SSTL15 Standard.(1)(2)**|||||||
|TPSPLLCC/<br>TPHPLLCC|No delay clock-capable clock input and<br>IFF(3)with PLL.|XC7S6|3.07/–0.17|3.69/–0.17|3.69/–0.17|ns|
|||XC7S15|3.07/–0.17|3.69/–0.17|3.69/–0.17|ns|
|||XC7S25|3.04/–0.19|3.64/–0.19|3.64/–0.19|ns|
|||XC7S50|3.15/–0.19|3.77/–0.19|3.77/–0.19|ns|
|||XC7S75|3.15/–0.19|3.78/–0.19|3.78/–0.19|ns|
|||XC7S100|3.15/–0.19|3.78/–0.19|3.78/–0.19|ns|
|||XA7S6|3.07/–0.17|3.69/–0.17|N/A|ns|
|||XA7S15|3.07/–0.17|3.69/–0.17|N/A|ns|
|||XA7S25|3.04/–0.19|3.64/–0.19|N/A|ns|
|||XA7S50|3.15/–0.19|3.77/–0.19|N/A|ns|
|||XA7S75|3.15/–0.19|3.78/–0.19|N/A|ns|
|||XA7S100|3.15/–0.19|3.78/–0.19|N/A|ns|



## **Notes:** 

1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage. 

2. Use IBIS to determine any duty-cycle distortion incurred using various standards. 

3. IFF = Input flip-flop or latch. 

_Table  47:_ **Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO** 

|**Symbol**|**Description**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**Units**|
|---|---|---|---|---|---|
|||**1.0V**||**0.95V**||
|||**-2**|**-1**|**-1L**||
|**Input Setup and Hold Time Relative to a Forwarded Clock Input Pin Using BUFIO for SSTL15 Standard.**||||||
|TPSCS/TPHCS|Setup and hold of I/O clock.|–0.38/1.46|–0.38/1.73|–0.38/1.76|ns|



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**Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics** 

## _Table  48:_ **Sample Window** 

|**Symbol**|**Description**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**Units**|
|---|---|---|---|---|---|
|||**1.0V**||**0.95V**||
|||**-2**|**-1**|**-1L**||
|TSAMP|Sampling error at receiver pins.(1)|0.64|0.70|0.70|ns|
|TSAMP_BUFIO|Sampling error at receiver pins using BUFIO.(2)|0.40|0.46|0.46|ns|



## **Notes:** 

1. This parameter indicates the total sampling error of the Spartan-7 FPGAs DDR input registers, measured across voltage, temperature, and process. The characterization methodology uses the MMCM to capture the DDR input registers’ edges of operation. These measurements include: 

   - CLK0 MMCM jitter 

   - MMCM accuracy (phase offset) 

   - MMCM phase shift resolution 

These measurements do not include package or clock tree skew. 

2. This parameter indicates the total sampling error of the Spartan-7 FPGAs DDR input registers, measured across voltage, temperature, and process. The characterization methodology uses the BUFIO clock network and IDELAY to capture the DDR input registers’ edges of operation. These measurements do not include package or clock tree skew. 

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**Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics** 

## **Additional Package Parameter Guidelines** 

The parameters in this section provide the necessary values for calculating timing budgets for Spartan-7 FPGA clock transmitter and receiver data-valid windows. 

_Table  49:_ **Package Skew[(1)]** 

|**Symbol**|**Description**|**Device**|**Package**|**Value**|**Units**|
|---|---|---|---|---|---|
|TPKGSKEW|Package skew.(2)|XC7S6|CPGA196|44|ps|
||||CSGA225|83|ps|
||||FTGB196|65|ps|
|||XC7S15|CPGA196|44|ps|
||||CSGA225|83|ps|
||||FTGB196|65|ps|
|||XC7S25|CSGA225|93|ps|
||||CSGA324|62|ps|
||||FTGB196|83|ps|
|||XC7S50|CSGA324|80|ps|
||||FGGA484|110|ps|
||||FTGB196|103|ps|
|||XC7S75|FGGA484|117|ps|
||||FGGA676|110|ps|
|||XC7S100|FGGA484|117|ps|
||||FGGA676|110|ps|
|||XA7S6|CPGA196|44|ps|
||||CSGA225|83|ps|
||||FTGB196|65|ps|
|||XA7S15|CPGA196|44|ps|
||||CSGA225|83|ps|
||||FTGB196|65|ps|
|||XA7S25|CSGA225|93|ps|
||||CSGA324|62|ps|
||||FTGB196|83|ps|
|||XA7S50|CSGA324|80|ps|
||||FGGA484|110|ps|
||||FTGB196|103|ps|
|||XA7S75|FGGA484|117|ps|
||||FGGA676|110|ps|
|||XC7S100|FGGA484|117|ps|
||||FGGA676|110|ps|



## **Notes:** 

1. Package delay information is available for these device/package combinations. This information can be used to deskew the package. 

2. These values represent the worst-case skew between any two SelectIO resources in the package: shortest delay to longest delay from die pad to ball. 

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**Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics** 

## **XADC Specifications** 

The _7 Series FPGAs Overview_ (DS180) [Ref 1] and _XA Spartan-7 Automotive FPGA Data Sheet: Overview_ (DS171) [Ref 2] list the devices that contain a 7 series XADC dual 12-Bit 1 MSPS analog-to-digital converter. 

_Table  50:_ **XADC Specifications** 

|**Parameter**|**Symbol**|**Comments/Conditions**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|VCCADC = 1.8V ± 5%, VREFP = 1.25V, VREFN= 0V, ADCCLK = 26 MHz, –55°C ≤Tj ≤125°C.<br>Typical values at Tj = +40°C.|||||||
|**ADC Accuracy(1)**|||||||
|Resolution|||12|–|–|Bits|
|Integral nonlinearity(2)|INL|–40°C≤Tj ≤100°C|–|–|±2|LSBs|
|||–55°C≤Tj< –40°C; 100°C < Tj ≤125°C|–|–|±3|LSBs|
|Differential nonlinearity|DNL|No missing codes, guaranteed monotonic.|–|–|±1|LSBs|
|Offset error|Unipolar|–40°C≤Tj ≤100°C|–|–|±8|LSBs|
|||–55°C≤Tj< –40°C; 100°C < Tj ≤125°C|–|–|±12|LSBs|
||Bipolar|–55°C≤Tj ≤125°C|–|–|±4|LSBs|
|Gain error|||–|–|±0.5|%|
|Offset matching|||–|–|4|LSBs|
|Gain matching|||–|–|0.3|%|
|Sample rate|||–|–|1|MS/s|
|Signal to noise ratio(2)|SNR|FSAMPLE= 500 KS/s, FIN= 20 kHz|60|–|–|dB|
|RMS code noise||External 1.25V reference.|–|–|2|LSBs|
|||On-chip reference.|–|3|–|LSBs|
|Total harmonic distortion(2)|THD|FSAMPLE= 500 KS/s, FIN= 20 kHz|70|–|–|dB|
|**Analog Inputs(3)**|||||||
|ADC input ranges||Unipolar operation.|0|–|1|V|
|||Bipolar operation.|–0.5|–|+0.5|V|
|||Unipolar common mode range (FS input).|0|–|+0.5|V|
|||Bipolar common mode range (FS input).|+0.5|–|+0.6|V|
|Maximum external channel<br>ranges|input|Adjacent analog channels set within these<br>ranges should not corrupt measurements<br>on adjacent channels.|–0.1|–|VCCADC|V|
|Full-resolution bandwidth|FRBW|Auxiliary channel full resolution<br>bandwidth.|250|–|–|kHz|
|**On-chip Sensors**|||||||
|Temperature sensor error||–40°C≤Tj ≤100°C|–|–|±4|°C|
|||–55°C≤Tj< –40°C; 100°C < Tj ≤125°C|–|–|±6|°C|
|Supply sensor error||–40°C≤Tj ≤100°C|–|–|±1|%|
|||–55°C≤Tj< –40°C; 100°C < Tj ≤125°C|–|–|±2|%|



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**Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  50:_ **XADC Specifications** _**(Cont’d)**_ 

|**Parameter**|**Symbol**|**Comments/Conditions**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|**Conversion Rate(4)**|||||||
|Conversion time:<br>continuous|tCONV|Number of ADCCLK cycles.|26|–|32|Cycles|
|Conversion time: event|tCONV|Number of CLK cycles.|–|–|21|Cycles|
|DRP clock frequency|DCLK|DRP clock frequency.|8|–|250|MHz|
|ADC clock frequency|ADCCLK|Derived from DCLK.|1|–|26|MHz|
|DCLK duty cycle|||40|–|60|%|
|**XADC Reference(5)**|||||||
|External reference|VREFP|Externally supplied reference voltage.|1.20|1.25|1.30|V|
|On-chip reference||Ground VREFPpin to AGND,<br>–40°C≤Tj ≤100°C|1.2375|1.25|1.2625|V|
|||Ground VREFP pin to AGND,<br>–55°C≤Tj< –40°C; 100°C < Tj ≤125°C|1.225|1.25|1.275|V|



## **Notes:** 

1. Offset and gain errors are removed by enabling the XADC automatic gain calibration feature. The values are specified for when this feature is enabled. 

2. Only specified for bitstream option XADCEnhancedLinearity = ON. 

3. For a detailed description, see the _ADC_ chapter in the _7 Series FPGAs and Zynq-7000 AP SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide_ (UG480) [Ref 9]. 

4. For a detailed description, see the _Timing_ chapter in the _7 Series FPGAs and Zynq-7000 AP SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide_ (UG480) [Ref 9]. 

5. Any variation in the reference voltage from the nominal VREFP = 1.25V and VREFN = 0V will result in a deviation from the ideal transfer function. This also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). However, for external ratiometric type applications allowing reference to vary by ±4% is permitted. 

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**Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics** 

## **Configuration Switching Characteristics** 

_Table  51:_ **Configuration Switching Characteristics** 

|**Symbol**|**Description**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**Units**|
|---|---|---|---|---|---|
|||**1.0V**||**0.95V**||
|||**-2**|**-1**|**-1L**||
|**Power-up Timing Characteristics**||||||
|TPL(1)|Program latency.|5.00|5.00|5.00|ms, Max|
|TPOR(2)|Power-on reset<br>(50 ms ramp rate time).|10/50|10/50|10/50|ms,<br>Min/Max|
||Power-on reset<br>(1 ms ramp rate time).|10/35|10/35|10/35|ms,<br>Min/Max|
|TPROGRAM|Program pulse width.|250.00|250.00|250.00|ns, Min|
|**CCLK Output**|**(Master Mode)**|||||
|TICCK|Master CCLK output delay.|150.00|150.00|150.00|ns, Min|
|TMCCKL|Master CCLK clock Low time duty cycle.|40/60|40/60|40/60|%, Min/Max|
|TMCCKH|Master CCLK clock High time duty cycle.|40/60|40/60|40/60|%, Min/Max|
|FMCCK|Master CCLK frequency.|100.00|100.00|100.00|MHz, Max|
||Master CCLK frequency for AES encrypted x16.(2)|50.00|50.00|50.00|MHz, Max|
|FMCCK_START|Master CCLK frequency at start of configuration.|3.00|3.00|3.00|MHz, Typ|
|FMCCKTOL|Frequency tolerance, master mode with respect to<br>nominal CCLK.|±50|±50|±50|%, Max|
|**CCLK Input (Slave Modes)**||||||
|TSCCKL|Slave CCLK clock minimum Low time.|2.50|2.50|2.50|ns, Min|
|TSCCKH|Slave CCLK clock minimum High time.|2.50|2.50|2.50|ns, Min|
|FSCCK|Slave CCLK frequency.|100.00|100.00|100.00|MHz, Max|
|**EMCCLK Input (Master Mode)**||||||
|TEMCCKL|External master CCLK Low time.|2.50|2.50|2.50|ns, Min|
|TEMCCKH|External master CCLK High time.|2.50|2.50|2.50|ns, Min|
|FEMCCK|External master CCLK frequency.|100.00|100.00|100.00|MHz, Max|
|**Internal Configuration Access Port**||||||
|FICAPCK|Internal configuration access port (ICAPE2) clock<br>frequency.|100.00|100.00|100.00|MHz, Max|
|**Master/Slave Serial Mode Programming Switching**||||||
|TDCCK/<br>TCCKD|DINsetup/hold.|4.00/0.00|4.00/0.00|4.00/0.00|ns, Min|
|TCCO|DOUTclock to out.|8.00|8.00|8.00|ns, Max|
|**SelectMAP Mode Programming Switching**||||||
|TSMDCCK/<br>TSMCCKD|D[31:00] setup/hold.|4.00/0.00|4.00/0.00|4.00/0.00|ns, Min|



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**Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics** 

_Table  51:_ **Configuration Switching Characteristics** _**(Cont’d)**_ 

|**Symbol**|**Description**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**VCCINT Operating Voltage and Speed**<br>**Grade**|**Units**|
|---|---|---|---|---|---|
|||**1.0V**||**0.95V**||
|||**-2**|**-1**|**-1L**||
|TSMCSCCK/<br>TSMCCKCS|CSI_B setup/hold.|4.00/0.00|4.00/0.00|4.00/0.00|ns, Min|
|TSMWCCK/<br>TSMCCKW|RDWR_B setup/hold.|10.00/0.00|10.00/0.00|10.00/0.00|ns, Min|
|TSMCKCSO|CSO_B clock to out (330Ωpull-up resistor<br>required).|7.00|7.00|7.00|ns, Max|
|TSMCO|D[31:00] clock to out in readback.|8.00|8.00|8.00|ns, Max|
|FRBCCK|Readback frequency.|100.00|100.00|100.00|MHz, Max|
|**Boundary-Scan Port Timing Specifications**||||||
|TTAPTCK/<br>TTCKTAP|TMS and TDI setup/hold.|3.00/2.00|3.00/2.00|3.00/2.00|ns, Min|
|TTCKTDO|TCK falling edge to TDO output.|7.00|7.00|7.00|ns, Max|
|FTCK|TCK frequency.|66.00|66.00|66.00|MHz, Max|
|**SPI Flash Master Mode Programming Switching**||||||
|TSPIDCC/<br>TSPICCD|D[03:00] setup/hold.|3.00/0.00|3.00/0.00|3.00/0.00|ns, Min|
|TSPICCM|MOSI clock to out.|8.00|8.00|8.00|ns, Max|
|TSPICCFC|FCS_B clock to out.|8.00|8.00|8.00|ns, Max|
|**STARTUPE2 Ports**||||||
|TUSRCCLKO|STARTUPE2 USRCCLKO input to CCLK output.|0.50/6.70|0.50/7.50|0.50/7.50|ns, Min/Max|
|FCFGMCLK|STARTUPE2 CFGMCLK output frequency.|65.00|65.00|65.00|MHz, Typ|
|FCFGMCLKTOL|STARTUPE2 CFGMCLK output frequency tolerance.|±50|±50|±50|%, Max|
|**Device DNA Access Port**||||||
|FDNACK|DNA access port (DNA_PORT).|100.00|100.00|100.00|MHz, Max|



## **Notes:** 

1. To support longer delays in configuration, use the design solutions described in the _7 Series FPGA Configuration User Guide_ (UG470) [Ref 10]. 

2. See the _7 Series FPGAs Overview_ (DS180) [Ref 1] and _XA Spartan-7 Automotive FPGA Data Sheet: Overview_ (DS171) [Ref 2] for a list of devices that support bitstream encryption. 

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**Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics** 

## **eFUSE Programming Conditions** 

Table 52 lists the programming conditions specifically for eFUSE. For more information, see the _7 Series FPGA Configuration User Guide_ (UG470) [Ref 10]. 

_Table  52:_ **eFUSE Programming Conditions[(1)]** 

|**Symbol**|**Description**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|
|IFS|VCCAUXsupply current|–|–|115|mA|
|Tj|Temperature range|15|–|125|°C|



## **Notes:** 

1. The FPGA must not be configured during eFUSE programming. 

## **References** 

1. _7 Series FPGAs Overview_ (DS180) 

2. _XA Spartan-7 Automotive FPGA Data Sheet: Overview_ (DS171) 

3. _7 Series FPGAs SelectIO Resources User Guide_ (UG471) 

4. _7 Series FPGA Packaging and Pinout Specification_ (UG475) 

5. _7 Series FPGAs PCB Design Guide_ (UG483) 

6. _Xilinx Power Estimator_ spreadsheet tool (XPE) 

7. _Zynq-7000 AP SoC and 7 Series FPGAs Memory Interface Solutions User Guide_ (UG586) 

8. See the Clocking Wizard in Vivado software. 

9. _7 Series FPGAs and Zynq-7000 AP SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide_ (UG480) 

10. _7 Series FPGA Configuration User Guide_ (UG470) 

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## **Revision History** 

The following table shows the revision history for this document: 

|**Date**|**Version**|**Description of Revisions**|
|---|---|---|
|06/18/2018|1.6|InTable 12, updated Vivado tools version to 2018.2. InTable 13, moved all speed<br>grades except -1Q (1.0V) for XC7S6 and XC7S15 to Production. InTable 14, added<br>Vivado tools version for XC7S6 and XC7S15.|
|04/04/2018|1.5|Added XA7S6, XA7S15, XA7S25, XA7S75, and XA7S100 devices throughout. In<br>Table 5, updated typical quiescent supply current values for XC7S25 and XC7S50<br>devices, and added values for XC7S6, XC7S15, XC7S75, and XC7S100 devices. In<br>Table 6, updated table title and ICCINTMINand ICCAUXMINfor XC7S75 and XC7S100<br>devices. InTable 13, moved all speed grades for XC7S6 and XC7S15 to Preliminary,<br>moved -1LI (0.95V) speed grade for XC7S25 to Production, and moved all speed<br>grades except -1Q (1.0V) for XC7S75 and XC7S100 from Preliminary to Production.<br>InTable 14, added Vivado tools version for XC7S25, XC7S75, and XC7S100. In<br>Table 36,Table 39,Table 40,Table 41,Table 42,Table 44,Table 45, andTable 46,<br>changed parameter value for XA7S50 to N/A. InTable 49, added package skew<br>values for XC7S6 and XC7S15 devices.|
|12/22/2017|1.4|InTable 12, updated Vivado tools version to 2017.4. InTable 13, moved all speed<br>grades for XC7S75 and XC7S100 from Advance to Preliminary and all speed grades<br>except -1LI (0.95V) for XC7S25 from Advance to Production. InTable 14, added<br>Vivado tools version for XC7S25. AddedNote 2toTable 16. InTable 49, added<br>package skew values for XC7S25 device in CSGA324 package and XC7S75 and<br>XC7S100 devices in FGGA676 package.|
|11/20/2017|1.3|Added XA7S50 device throughout. Updated description of offered temperature<br>ranges in second paragraph ofIntroduction. Added row for junction temperature (Tj)<br>at expanded (Q) temperature toTable 2. Added -1Q (1.0V) speed grade toTable 5,<br>andTable 13toTable 16. InTable 12, updated Vivado tools version to 2017.3. In<br>Table 49, added package skew values for XC7S25, XC7S50, XC7S75, and XC7S100<br>devices in CSGA225, FTGB196, and FGGA484 packages. Added_XA Spartan-7_<br>_Automotive FPGA Data Sheet: Overview_(DS171) toReferences.|
|06/20/2017|1.2|Updated paragraph beforeTable 6. InTable 12, updated Vivado tools version to<br>2017.2. InTable 13, moved all speed grades for XC7S50 from Preliminary to<br>Production and updatedNote 1. InTable 14, added Vivado tools version for XC7S50.<br>InTable 49, added package skew value for XC7S50 device in FGGA484 package.|
|04/07/2017|1.1|Added 1.35V toNote 5inTable 2. InTable 12, updated Vivado tools version to<br>2016.4. InTable 13, moved all speed grades for XC7S50 from Advance to<br>Preliminary. Removed SFI-4.1 and SPI-4.2 from descriptions of SDR LVDS receiver<br>and DDR LVDS receiver, respectively, inTable 15. InTable 25, changed<br>TIDELAYRESOLUTIONunits from ps to µs. Removed BUFMR fromNote 1inTable 34. In<br>Table 49, replaced TQGA144 with FTGB196 for XC7S6, XC7S15, and XC7S25<br>devices, added FTGB196 package for XC7S50 device, and added package skew value<br>for XC7S50 device in CSGA324 package.|
|09/27/2016|1.0|Initial Xilinx release.|



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## **Please Read: Important Legal Notices** 

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© Copyright 2016–2018 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. 

## **Automotive Applications Disclaimer** 

AUTOMOTIVE PRODUCTS (IDENTIFIED AS "XA" IN THE PART NUMBER) ARE NOT WARRANTED FOR USE IN THE DEPLOYMENT OF AIRBAGS OR FOR USE IN APPLICATIONS THAT AFFECT CONTROL OF A VEHICLE (“SAFETY APPLICATION”) UNLESS THERE IS A SAFETY CONCEPT OR REDUNDANCY FEATURE CONSISTENT WITH THE ISO 26262 AUTOMOTIVE SAFETY STANDARD (“SAFETY DESIGN”). CUSTOMER SHALL, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE PRODUCTS, THOROUGHLY TEST SUCH SYSTEMS FOR SAFETY PURPOSES. USE OF PRODUCTS IN A SAFETY APPLICATION WITHOUT A SAFETY DESIGN IS FULLY AT THE RISK OF CUSTOMER, SUBJECT ONLY TO APPLICABLE LAWS AND REGULATIONS GOVERNING LIMITATIONS ON PRODUCT LIABILITY. 

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