XC7A100T-1CSG324I
FPGA, Artix-7, MMCM, PLL, 210 I/O's, 464 MHz, 101440 Cells, 950 mV to 1.05 V, CSBGA-324, NCNR
⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
- Manufacturer: AMD
- Product type: FPGAs
- No. of Logic Blocks:15850; No. of Macrocells:101440; FPGA Family:Artix-7; Logic Case Style:CSBGA; No. of Pins:324Pins; No. of Speed Grades:1; Total RAM Bits:4860Kbit; No. of I/O's:210I/
- MSL: -
- SVHC: No SVHC (15-Jan-2018)
- FPGA Type: SRAM based FPGA
- FPGA Family: Artix-7
- IC Mounting: Surface Mount
- No. of Pins: 324Pins
- Speed Grade: 1
- No. of I/O's: 210I/O's
- Product Range: Artix-7 XC7A100T
- Qualification: -
- Total RAM Bits: 4860Kbit
- No.of User I/Os: 210I/O's
- Clock Management: MMCM, PLL
- Logic Case Style: CSBGA
- IC Case / Package: CSBGA
- No. of Macrocells: 101440Macrocells
- I/O Supply Voltage: 3.3V
- No. of Logic Cells: 101440Logic Cells
- Process Technology: 28nm (HKMG)
- No. of Logic Blocks: 101440
- No. of Speed Grades: 1
- Core Supply Voltage Max: 1.05V
- Core Supply Voltage Min: 950mV
- Operating Frequency Max: 464MHz
- Operating Temperature Max: 100°C
- Operating Temperature Min: -40°C
| Delivery and price | |
|---|---|
| Units per pack | 1 |
| Price | 121.37 € |
| Current stock | 10+ |
| Lead time | 30 days |
**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
DS181 (v1.27.1) July 3, 2024
## **Product Specification**
## **Introduction**
AMD Artix™ 7 FPGAs are available in -3, -2, -1, -1LI, and -2L speed grades, with -3 having the highest performance. The Artix 7 FPGAs predominantly operate at a 1.0V core voltage. The -1LI and -2L devices are screened for lower maximum static power and can operate at lower core voltages for lower dynamic power than the -1 and -2 devices, respectively. The -1LI devices operate only at VCCINT = VCCBRAM = 0.95V and have the same speed specifications as the -1 speed grade. The -2L devices can operate at either of two VCCINT voltages, 0.9V and 1.0V and are screened for lower maximum static power. When operated at VCCINT = 1.0V, the speed specification of a -2L device is the same as the -2 speed grade. When operated at VCCINT = 0.9V, the -2L static and dynamic power is reduced.
Artix 7 FPGA DC and AC characteristics are specified in commercial, extended, industrial, expanded (-1Q), and military (-1M) temperature ranges. Except the operating temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -1M
speed grade military device are the same as for a -1C speed grade commercial device). However, only selected speed grades and/or devices are available in each temperature range. For example, -1M is only available in the defense-grade Artix 7Q family and -1Q is only available in XA Artix 7 FPGAs.
All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters included are common to popular designs and typical applications.
Available device and package combinations can be found in:
- _7 Series FPGAs Overview_ (DS180)
- _Defense-Grade 7 Series FPGAs Overview_ (DS185)
- _XA Artix 7 FPGAs Overview_ (DS197)
This Artix 7 FPGA data sheet, part of an overall set of documentation on the 7 series FPGAs, is available on the Xilinx website at https://docs.amd.com.
## **DC Characteristics**
_Table 1:_ **Absolute Maximum Ratings[(1)]**
|**Symbol**<br>~~Pee~~|**Description**<br>~~Pee~~|**Min**<br>~~Pee~~|**Max**<br>~~Pee~~|**Units**<br>~~Pee~~|
|---|---|---|---|---|
|**FPGA Logic**<br>~~ee~~|||||
|VCCINT<br>~~ee~~|Internal supply voltage|–0.5|1.1|V|
|VCCAUX<br>~~ee~~<br>~~a~~<br>~~ee~~|Auxiliary supply voltage|–0.5|2.0|V|
|VCCBRAM<br>~~ee~~<br>~~ee~~|Supply voltage for the block RAM memories|–0.5|1.1|V|
|VCCO<br>~~ee~~<br>~~ee~~|Output drivers supply voltage for HR I/O banks|–0.5|3.6|V|
|VREF<br>~~ee~~<br>~~aa~~|Input reference voltage<br>~~a~~|–0.5<br>~~ee~~|2.0<br>~~ee~~|V<br>~~ee~~|
|VIN(2)(3)(4)<br>~~a a~~<br>~~a ee~~<br>~~San~~|I/O input voltage<br>~~a~~<br>~~ee~~|–0.4<br>~~ee~~<br>~~ee~~|VCCO+ 0.55<br>~~ee~~<br>~~ee~~|V<br>~~ee~~<br>~~ee~~|
||I/O input voltage (when VCCO= 3.3V) for VREFand differential I/O standards<br>except TMDS_33(5)<br>~~a~~<br>~~ee~~<br>~~San~~|–0.4<br>~~ee~~<br>~~ee~~<br>~~San~~|2.625<br>~~ee~~<br>~~ee~~<br>~~San~~|V<br>~~ee~~<br>~~ee~~<br>~~San~~|
|VCCBATT<br>~~a ee~~<br>~~San~~|Key memory battery backup supply<br>~~ee~~<br>~~San~~|–0.5<br>~~ee~~<br>~~ee ~~<br>~~San~~|2.0<br>~~ee~~<br> ~~ee~~<br>~~San~~|V<br>~~ee~~<br>~~ee~~<br>~~San~~|
|**GTP Transceiver**<br>~~San~~<br>~~eenn~~|||||
|VMGTAVCC<br>~~San~~<br>~~ee~~<br>~~ee~~|Analog supply voltage for the GTP transmitter and receiver circuits<br>~~San~~<br>~~nn~~|–0.5<br>~~San~~<br>~~nn~~|1.1<br>~~San~~<br>~~nn~~|V<br>~~San~~<br>~~nn~~|
|VMGTAVTT<br>~~ee~~<br>~~ee~~|Analog supply voltage for the GTP transmitter and receiver termination circuits<br>~~nn~~|–0.5<br>~~nn~~|1.32<br>~~nn~~|V<br>~~nn~~|
|VMGTREFCLK<br>~~ee~~<br>~~a~~|Reference clock absolute input voltage|–0.5|1.32|V|
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DS181 (v1.27.1) July 3, 2024 **Product Specification**
1
**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 1:_ **Absolute Maximum Ratings[(1)]** _**(Cont’d)**_
|**Symbol**<br>~~a~~|**Description**|**Min**|**Max**|**Units**|
|---|---|---|---|---|
|VIN<br>~~a~~|Receiver (RXP/RXN) and Transmitter (TXP/TXN) absolute input voltage<br>|–0.5<br>|1.26<br>|V<br>|
|IDCIN-FLOAT<br>~~aOO~~|DC input current for receiver input pins DC coupled RX termination = floating<br>~~OO~~|–<br>~~OO~~|14<br>~~OO~~|mA<br>~~OO~~|
|IDCIN-MGTAVTT<br>~~OO~~<br>~~a~~|DC input current for receiver input pins DC coupled RX termination = VMGTAVTT<br>~~OO~~<br>~~D~~|–<br>~~OO~~<br>~~D~~|12<br>~~OO~~<br>~~D~~|mA<br>~~OO~~<br>~~D~~|
|IDCIN-GND<br>~~OO~~|DC input current for receiver input pins DC coupled RX termination = GND<br>~~OO~~|–<br>~~OO~~|6.5<br>~~OO~~|mA<br>~~OO~~|
|IDCOUT-FLOAT<br>~~OO~~<br>~~eG~~|DC output current for transmitter pins DC coupled RX termination = floating<br>~~OO~~<br>~~eG~~|–<br>~~OO~~<br>~~eG~~|14<br>~~OO~~<br>~~eG~~|mA<br>~~OO~~<br>~~eG~~|
|IDCOUT-MGTAVTT<br>~~eG~~<br>~~DO~~|DC output current for transmitter pins DC coupled RX termination = VMGTAVTT<br>~~eG~~<br>~~DO~~|–<br>~~eG~~<br>~~DO~~|12<br>~~eG~~<br>~~DO~~|mA<br>~~eG~~<br>~~DO~~|
|**XADC**<br>~~pe~~<br>~~ee~~|||||
|VCCADC<br>~~pe~~<br>~~ee~~|XADC supply relative to GNDADC<br>~~pe~~|–0.5<br>~~pe~~|2.0<br>~~pe~~|V<br>~~pe~~|
|VREFP<br>~~ee~~<br>~~a~~|XADC reference input relative to GNDADC<br>~~D~~|–0.5<br>~~D~~|2.0<br>~~D~~|V<br>~~D~~|
|**Temperature**<br>~~a D~~<br>~~|~~|||||
|TSTG<br>~~|~~<br>~~a~~|Storage temperature (ambient)<br>~~|~~<br>~~a~~|–65<br>~~|~~<br>~~a~~|150<br>~~|~~<br>~~a~~|°C<br>~~|~~<br>~~a~~|
|TSOL<br>~~a~~<br>~~|~~<br>~~Re~~|Maximum soldering temperature for Pb/Sn component bodies(6)<br>~~a~~<br>~~|~~|–<br>~~a~~<br>~~|~~|+220<br>~~a~~<br>~~|~~|°C<br>~~a~~<br>~~|~~|
||Maximum soldering temperature for Pb-free component bodies(6)<br>~~|~~<br>~~De~~<br>|–<br>~~|~~<br>~~De~~<br>|+260<br>~~|~~<br>~~De~~<br>|°C<br>~~|~~<br>~~De~~<br>|
|Tj<br>~~Re~~|Maximum junction temperature(6)<br>~~De~~<br>~~D~~|–<br>~~De~~<br>~~D~~|+125<br>~~De~~<br>~~D~~|°C<br>~~De~~<br>~~D~~|
2. The lower absolute voltage specification always applies.
3. For I/O operation, refer to _7 Series FPGAs SelectIO Resources User Guide_ (UG471).
4. The maximum limit applies to DC signals. For maximum undershoot and overshoot AC specifications, see Table 4.
5. See Table 9 for TMDS_33 specifications.
6. For soldering guidelines and thermal considerations, see _7 Series FPGA Packaging and Pinout Specification_ (UG475).
_Table 2:_ **Recommended Operating Conditions[(1)(2)]**
|**Symbol**<br>~~a~~|**Description**<br>~~a~~|**Min**<br>~~a~~|**Typ**<br>~~a~~|**Max**<br>~~a~~|**Units**<br>~~a~~|
|---|---|---|---|---|---|
|**FPGA Logic**<br>~~pe~~||||||
|VCCINT(3)<br>~~pe~~|For -3, -2, -2LE (1.0V), -1, -1Q, -1M devices: internal supply voltage<br>~~pe~~<br>~~ee~~|0.95<br>~~pe~~<br>~~ee~~|1.00<br>~~pe~~<br>~~ee~~|1.05<br>~~pe~~<br>~~ee~~|V<br>~~pe~~<br>~~ee~~|
||For -1LI (0.95V) devices: internal supply voltage<br>~~ee~~<br>~~GO~~|0.92<br>~~ee~~<br>~~GO~~|0.95<br>~~ee~~<br>~~GO~~|0.98<br>~~ee~~<br>~~GO~~|V<br>~~ee~~<br>~~GO~~|
||For -2LE (0.9V) devices: internal supply voltage<br>~~GO~~<br>~~GO~~|0.87<br>~~GO~~<br>~~GO~~|0.90<br>~~GO~~<br>~~GO~~|0.93<br>~~GO~~<br>~~GO~~|V<br>~~GO~~<br>~~GO~~|
|VCCAUX<br>~~GG~~<br>~~EEE~~|Auxiliary supply voltage<br>~~GO~~<br>~~GG~~<br>~~EEE~~|1.71<br>~~GO~~<br>~~GG~~<br>~~ee~~|1.80<br>~~GO~~<br>~~GG~~<br>~~ee~~|1.89<br>~~GO~~<br>~~GG~~<br>~~ee~~|V<br>~~GO~~<br>~~GG~~<br>~~ee~~|
|VCCBRAM(3)<br>~~GG~~<br>~~EEE~~|For -3, -2, -2LE (1.0V), -2LE (0.9V), -1, -1Q, -1M devices: block RAM supply<br>voltage<br>~~GG~~<br>~~EEE~~|0.95<br>~~GG~~<br>~~ee~~|1.00<br>~~GG~~<br>~~ee~~|1.05<br>~~GG~~<br>~~ee~~|V<br>~~GG~~<br>~~ee~~|
||For -1LI (0.95V) devices: block RAM supply voltage<br>~~EEE~~|0.92<br>~~ee~~|0.95<br>~~ee~~|0.98<br>~~ee~~|V<br>~~ee~~|
|VCCO(4)(5)<br>~~EEE~~<br>~~OO~~<br>~~ee~~|Supply voltage for HR I/O banks<br>~~EEE~~<br>~~OO~~<br>~~ee~~|1.14<br>~~ee~~<br>~~OO~~|–<br>~~ee~~<br>~~OO~~|3.465<br>~~ee~~<br>~~OO~~|V<br>~~ee~~<br>~~OO~~|
|VIN(6)<br>~~OO~~<br>~~ee~~|I/O input voltage<br>~~OO~~<br>~~ee~~|–0.20<br>~~OO~~|–<br>~~OO~~|VCCO+ 0.20<br>~~OO~~|V<br>~~OO~~|
||I/O input voltage (when VCCO= 3.3V) for VREFand differential I/O standards<br>except TMDS_33(7)<br>~~ee~~|–0.20|–|2.625|V|
|IIN(8)<br>~~ee ~~|Maximum current through any pin in a powered or unpowered bank when<br>forward biasing the clamp diode.<br> ~~ee~~|–|–|10|mA|
|VCCBATT(9)<br>~~a FO~~|Battery voltage<br>~~FO~~|1.0<br>~~FO~~|–<br>~~FO~~|1.89<br>~~FO~~|V<br>~~FO~~|
|**GTP Transceiver**<br>~~a FO~~<br>~~CT~~||||||
|VMGTAVCC(10)<br>~~CT~~<br>~~a~~|Analog supply voltage for the GTP transmitter and receiver circuits<br>~~CT~~<br>~~Ge~~|0.97<br>~~CT~~<br>~~Ge~~|1.0<br>~~CT~~<br>~~Ge~~|1.03<br>~~CT~~<br>~~Ge~~|V<br>~~CT~~<br>~~Ge~~|
|VMGTAVTT(10)<br>~~a ~~<br>~~a~~|Analog supply voltage for the GTP transmitter and receiver termination circuits<br> ~~Ge~~<br>~~DO~~|1.17<br>~~Ge~~<br>~~DO~~|1.2<br>~~Ge~~<br>~~DO~~|1.23<br>~~Ge~~<br>~~DO~~|V<br>~~Ge~~<br>~~DO~~|
DS181 (v1.27.1) July 3, 2024 **Product Specification**
Send Feedback
2
**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 2:_ **Recommended Operating Conditions[(1)(2)]** _**(Cont’d)**_
|**Symbol**<br>~~a~~|**Description**<br>|**Min**<br>|**Typ**<br>|**Max**<br>|**Units**<br>|
|---|---|---|---|---|---|
|**XADC**<br>||||||
|VCCADC<br>~~DO~~|XADC supply relative to GNDADC<br>~~DO~~|1.71<br>~~DO~~|1.80<br>~~DO~~|1.89<br>~~DO~~|V<br>~~DO~~|
|VREFP<br>~~Ca~~|Externally supplied reference voltage<br>~~Ca~~|1.20<br>~~Ca~~|1.25<br>~~Ca~~|1.30<br>~~Ca~~|V<br>~~Ca~~|
|**Temperature**<br>~~Ca~~<br>~~|~~||||||
|Tj<br>~~|~~|Junction temperature operating range for commercial (C) temperature devices<br>~~|~~<br>~~ee~~|0<br>~~|~~<br>~~ee~~|–<br>~~|~~<br>~~ee~~|85<br>~~|~~<br>~~ee~~|°C<br>~~|~~<br>~~ee~~|
||Junction temperature operating range for extended (E) temperature devices<br>~~a~~|0<br>~~a~~|–<br>~~a~~|100<br>~~a~~|°C<br>~~a~~|
||Junction temperature operating range for industrial (I) temperature devices<br>~~a~~<br>~~GO~~|–40<br>~~a~~<br>~~GO~~|–<br>~~a~~<br>~~GO~~|100<br>~~a~~<br>~~GO~~|°C<br>~~a~~<br>~~GO~~|
||Junction temperature operating range for expanded (Q) temperature devices<br>~~GO~~<br>~~a~~|–40<br>~~GO~~<br>~~a~~|–<br>~~GO~~<br>~~a~~|125<br>~~GO~~<br>~~a~~|°C<br>~~GO~~<br>~~a~~|
||Junction temperature operating range for military (M) temperature devices<br>~~a~~|–55<br>~~a~~|–<br>~~a~~|125<br>~~a~~|°C<br>~~a~~|
## **Notes:**
1. All voltages are relative to ground.
2. For the design of the power distribution system consult _7 Series FPGAs PCB Design and Pin Planning Guide_ (UG483).
3. If VCCINT and VCCBRAM are operating at the same voltage, VCCINT and VCCBRAM should be connected to the same supply.
4. Configuration data is retained even if VCCO drops to 0V.
5. Includes VCCO of 1.2V, 1.35V, 1.5V, 1.8V, 2.5V, and 3.3V at ±5%.
6. The lower absolute voltage specification always applies.
7. See Table 9 for TMDS_33 specifications.
8. A total of 200 mA per bank should not be exceeded.
9. VCCBATT is required only when using bitstream encryption. If battery is not used, connect VCCBATT to either ground or VCCAUX.
10. Each voltage listed requires the filter circuit described in _7 Series FPGAs GTP Transceiver User Guide_ (UG482).
_Table 3:_ **DC Characteristics Over Recommended Operating Conditions**
|**Symbol**<br>~~a~~|**Description**<br>~~a~~|**Min**<br>~~a~~|**Typ(1)**<br>~~a~~|**Max**<br>~~a~~|**Units**<br>~~a~~|
|---|---|---|---|---|---|
|VDRINT<br>~~a~~|Data retention VCCINTvoltage (below which configuration data might be lost)<br>~~a~~|0.75<br>~~a~~|–<br>~~a~~|–<br>~~a~~|V<br>~~a~~|
|VDRI<br>~~a~~<br>~~a~~|Data retention VCCAUXvoltage (below which configuration data might be lost)<br>~~a~~<br>~~a~~|1.5<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|V<br>~~a~~<br>~~a~~|
|IREF<br>~~a~~<br>~~a~~|VREFleakage current per pin<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|15<br>~~a~~<br>~~a~~|µA<br>~~a~~<br>~~a~~|
|IL<br>~~a~~|Input or output leakage current per pin (sample-tested)<br>~~a~~|–<br>~~a~~|–<br>~~a~~|15<br>~~a~~|µA<br>~~a~~|
|CIN(2)<br>~~a~~<br>~~a~~<br>~~**a**~~|Die input capacitance at the pad<br>~~a~~<br>~~a~~<br>~~**a**~~|–<br>~~a~~<br>~~a~~<br>|–<br>~~a~~<br>~~a~~<br>|8<br>~~a~~<br>~~a~~<br>|pF<br>~~a~~<br>~~a~~<br>|
|IRPU<br>~~a~~<br>~~**a**~~|Pad pull-up (when selected) @ VIN= 0V, VCCO= 3.3V<br>~~a~~<br>~~**a**~~|90<br>~~a~~<br>|–<br>~~a~~<br>|330<br>~~a~~<br>|µA<br>~~a~~<br>|
||Pad pull-up (when selected) @ VIN= 0V, VCCO= 2.5V<br>~~**a**~~|68<br>|–<br>|250<br>|µA<br>|
||Pad pull-up (when selected) @ VIN= 0V, VCCO= 1.8V<br>~~a~~|34<br>~~a~~|–<br>~~a~~|220<br>~~a~~|µA<br>~~a~~|
||Pad pull-up (when selected) @ VIN= 0V, VCCO= 1.5V<br>~~a~~<br>~~a~~|23<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|150<br>~~a~~<br>~~a~~|µA<br>~~a~~<br>~~a~~|
||Pad pull-up (when selected) @ VIN= 0V, VCCO= 1.2V<br>~~a~~<br>~~a~~|12<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|120<br>~~a~~<br>~~a~~|µA<br>~~a~~<br>~~a~~|
|IRPD<br>~~a~~|Pad pull-down (when selected) @ VIN= 3.3V<br>~~a~~|68<br>~~a~~|–<br>~~a~~|330<br>~~a~~|µA<br>~~a~~|
|ICCADC<br>~~a~~<br>~~a~~|Analog supply current, analog circuits in powered up state|–|–|25|mA|
|IBATT(3)<br>~~a~~<br>~~a~~|Battery supply current|–|–|150|nA|
|RIN_TERM(4)<br>~~a~~|Thevenin equivalent resistance of programmable input termination to VCCO/2<br>(UNTUNED_SPLIT_40)|28|40|55||
||Thevenin equivalent resistance of programmable input termination to VCCO/2<br>(UNTUNED_SPLIT_50)|35|50|65||
||Thevenin equivalent resistance of programmable input termination to VCCO/2<br>(UNTUNED_SPLIT_60)|44|60|83||
DS181 (v1.27.1) July 3, 2024 **Product Specification**
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**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 3:_ **DC Characteristics Over Recommended Operating Conditions** _**(Cont’d)**_
|**Symbol**|**Description**|**Min**|**Typ(1)**|**Max**|**Units**|
|---|---|---|---|---|---|
|n|Temperature diode ideality factor|–|1.010|–|–|
|r|Temperature diode series resistance|–|2|–||
## **Notes:**
1. Typical values are specified at nominal voltage, 25°C.
2. This measurement represents the die capacitance at the pad, not including the package.
3. Maximum value specified for worst case process at 25°C.
4. Termination resistance to a VCCO/2 level.
_Table 4:_ **VIN Maximum Allowed AC Voltage Overshoot and Undershoot for HR I/O Banks[(1)(2)]**
|_Table 4:_ **VIN Maximum Allowed AC Voltage Overshoot and Undershoot for HR I/O BanksIN Maximum Allowed AC Voltage Overshoot and Undershoot for HR I/O Banks Maximum Allowed AC Voltage Overshoot and Undershoot for HR I/O Banks**|**VIN Maximum Allowed AC Voltage Overshoot and Undershoot for HR I/O BanksIN Maximum Allowed AC Voltage Overshoot and Undershoot for HR I/O Banks Maximum Allowed AC Voltage Overshoot and Undershoot for HR I/O Banks**|**VIN Maximum Allowed AC Voltage Overshoot and Undershoot for HR I/O BanksIN Maximum Allowed AC Voltage Overshoot and Undershoot for HR I/O Banks Maximum Allowed AC Voltage Overshoot and Undershoot for HR I/O Banks**|**VIN Maximum Allowed AC Voltage Overshoot and Undershoot for HR I/O BanksIN Maximum Allowed AC Voltage Overshoot and Undershoot for HR I/O Banks Maximum Allowed AC Voltage Overshoot and Undershoot for HR I/O Banks[(1)(2)]**|
|---|---|---|---|
|**AC Voltage Overshoot**<br>~~|~~|**% of UI @–55°C to 125°C**<br>~~|~~|**AC Voltage Undershoot**<br>~~|~~|**% of UI @–55°C to 125°C**<br>~~|~~|
|VCCO+ 0.55|100|–0.40<br>~~ee~~|100<br>~~ee~~|
|||–0.45<br>~~ee~~<br>~~ee~~|61.7<br>~~ee~~<br>~~ee~~|
|||–0.50<br>~~ee~~<br>~~ee~~|25.8<br>~~ee~~<br>~~ee~~|
|||–0.55<br>~~ee~~<br>~~ee~~|11.0<br>~~ee~~<br>~~ee~~|
|VCCO+ 0.60<br>~~|~~|46.6<br>~~|~~|–0.60<br>~~|~~|4.77<br>~~|~~|
|VCCO+ 0.65<br>~~|~~|21.2<br>~~|~~<br>~~|~~|–0.65<br>~~|~~<br>~~|~~|2.10<br>~~|~~|
|VCCO+ 0.70<br>~~ee~~|9.75<br>~~ee~~<br>~~|~~|–0.70<br>~~ee~~<br>~~|~~|0.94<br>~~ee~~|
|VCCO+ 0.75<br>~~|~~|4.55<br>~~|~~<br>~~|~~|–0.75<br>~~|~~<br>~~|~~|0.43<br>~~|~~|
|VCCO+ 0.80<br>~~|~~|2.15<br>~~|~~<br>~~|~~|–0.80<br>~~|~~<br>~~|~~|0.20<br>~~|~~|
|VCCO+ 0.85<br>~~ee~~|1.02<br>~~ee~~<br>~~|~~|–0.85<br>~~ee~~<br>~~|~~|0.09<br>~~ee~~|
|VCCO+ 0.90<br>~~|~~|0.49<br>~~|~~<br>~~|~~|–0.90<br>~~|~~<br>~~|~~|0.04<br>~~|~~|
|VCCO+ 0.95<br>~~|~~<br>~~ee~~|0.24<br>~~|~~<br>~~ee~~|–0.95<br>~~|~~<br>~~ee~~|0.02<br>~~|~~<br>~~ee~~|
## **Notes:**
1. A total of 200 mA per bank should not be exceeded.
2. The peak voltage of the overshoot or undershoot, and the duration above VCCO + 0.20V or below GND – 0.20V, must not exceed the values in this table.
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DS181 (v1.27.1) July 3, 2024 **Product Specification**
4
**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 5:_ **Typical Quiescent Supply Current**
|**Symbol**|**Description**|**Device**<br>~~A~~|**Speed Grade**<br>~~Pp~~|**Speed Grade**<br>~~Pp~~|**Speed Grade**<br>~~Pp~~|**Speed Grade**<br>~~Pp~~|**Speed Grade**<br>~~Pp~~|**Speed Grade**<br>~~Pp~~|**Units**<br>~~Pp~~<br>~~ee~~<br>~~ee~~|
|---|---|---|---|---|---|---|---|---|---|
||||**1.0V**<br>~~Pp~~||||**0.95V**<br>~~Pp~~|**0.9V**<br>~~Pp~~<br>~~ee~~||
||||**-3**<br>~~a~~|**-2**<br>~~ee~~|**-2LE**<br>~~ee~~|**-1**<br>~~ee~~|**-1LI**<br>~~ee~~|**-2LE**<br>~~ee~~<br>~~ee~~||
|ICCINTQ|Quiescent VCCINTsupply current|XC7A12T<br>~~A~~|48|48|48|48|43|38<br>~~ee~~|mA<br>~~ee~~|
|||XC7A15T<br>~~Aa~~|95|95|95|95|58|66<br>~~ee~~|mA<br>~~ee~~|
|||XC7A25T<br>~~a~~<br>~~a~~|48|48|48|48|43|38|mA|
|||XC7A35T<br>~~a~~<br>~~a~~<br>~~ee~~|95<br>~~ee~~<br>~~ee~~|95<br>~~ee~~<br>~~ee~~|95<br>~~ee~~|95<br>~~ee~~|58|66|mA|
|||XC7A50T<br>~~ee~~|95<br>~~ee~~|95<br>~~ee~~|95<br>~~ee~~|95<br>~~ee~~|58|66|mA|
|||XC7A75T<br>~~ee~~<br>~~a~~|155<br>~~ee~~|155<br>~~ee~~|155<br>~~ee~~|155<br>~~ee~~|96|108|mA|
|||XC7A100T<br>~~a~~<br>~~a~~<br>~~ee~~|155<br>~~ee~~<br>~~ee~~|155<br>~~ee~~<br>~~ee~~|155<br>~~ee~~|155<br>~~ee~~|96|108|mA|
|||XC7A200T<br>~~ee~~|328<br>~~ee~~|328<br>~~ee~~|328<br>~~ee~~|328<br>~~ee~~|203|232|mA|
|||XA7A12T<br>~~ee~~<br>~~a~~|N/A<br>~~ee~~|48<br>~~ee~~|N/A<br>~~ee~~|48<br>~~ee~~|N/A|N/A|mA|
|||XA7A15T<br>~~a~~<br>~~a~~<br>~~ee~~|N/A<br>~~ee~~<br>~~ee~~|95<br>~~ee~~<br>~~ee~~|N/A<br>~~ee~~|95<br>~~ee~~|N/A|N/A|mA|
|||XA7A25T<br>~~ee~~|N/A<br>~~ee~~|48<br>~~ee~~|N/A<br>~~ee~~|48<br>~~ee~~|N/A|N/A|mA|
|||XA7A35T<br>~~ee~~<br>~~a~~|N/A<br>~~ee~~|95<br>~~ee~~|N/A<br>~~ee~~|95<br>~~ee~~|N/A|N/A|mA|
|||XA7A50T<br>~~a~~<br>~~a~~<br>~~ee~~|N/A<br>~~ee~~<br>~~ee~~|95<br>~~ee~~<br>~~ee~~|N/A<br>~~ee~~|95<br>~~ee~~|N/A|N/A|mA|
|||XA7A75T<br>~~a~~<br>~~ee~~|N/A<br>~~ee~~<br>~~ee~~|155<br>~~ee~~<br>~~ee~~|N/A<br>~~ee~~|155<br>~~ee~~|N/A|N/A|mA|
|||XA7A100T<br>~~ee~~<br>~~a~~|N/A<br>~~ee~~|155<br>~~ee~~|N/A<br>~~ee~~|155<br>~~ee~~|N/A|N/A|mA|
|||XQ7A50T<br>~~a~~<br>~~a~~<br>~~ee~~|N/A<br>~~ee~~<br>~~ee~~|95<br>~~ee~~<br>~~ee~~|N/A<br>~~ee~~|95<br>~~ee~~|58|N/A|mA|
|||XQ7A100T<br>~~ee~~|N/A<br>~~ee~~|155<br>~~ee~~|N/A<br>~~ee~~|155<br>~~ee~~|96|N/A|mA|
|||XQ7A200T<br>~~ee~~<br>~~a~~|N/A<br>~~ee~~|328<br>~~ee~~|N/A<br>~~ee~~|328<br>~~ee~~|203|N/A|mA|
|ICCOQ|Quiescent VCCOsupply current<br>~~PR~~|XC7A12T<br>~~a~~<br>~~a~~<br>~~ee~~|1<br>~~ee~~<br>~~ee~~|1<br>~~ee~~<br>~~ee~~|1<br>~~ee~~|1<br>~~ee~~|1|1|mA|
|||XC7A15T<br>~~ee~~|1<br>~~ee~~|1<br>~~ee~~|1<br>~~ee~~|1<br>~~ee~~|1|1|mA|
|||XC7A25T<br>~~ee~~<br>~~a~~|1<br>~~ee~~|1<br>~~ee~~|1<br>~~ee~~|1<br>~~ee~~|1|1|mA|
|||XC7A35T<br>~~a~~<br>~~a~~<br>~~ee~~|1<br>~~ee~~<br>~~ee~~|1<br>~~ee~~<br>~~ee~~|1<br>~~ee~~|1<br>~~ee~~|1|1|mA|
|||XC7A50T<br>~~ee~~|1<br>~~ee~~|1<br>~~ee~~|1<br>~~ee~~|1<br>~~ee~~|1|1|mA|
|||XC7A75T<br>~~ee~~<br>~~a~~|4<br>~~ee~~|4<br>~~ee~~|4<br>~~ee~~|4<br>~~ee~~|4|4|mA|
|||XC7A100T<br>~~a~~<br>~~a~~<br>~~ee~~|4<br>~~ee~~<br>~~ee~~|4<br>~~ee~~<br>~~ee~~|4<br>~~ee~~|4<br>~~ee~~|4|4|mA|
|||XC7A200T<br>~~ee~~|5<br>~~ee~~|5<br>~~ee~~|5<br>~~ee~~|5<br>~~ee~~|5|5|mA|
|||XA7A12T<br>~~ee~~<br>~~a~~|N/A<br>~~ee~~|1<br>~~ee~~|N/A<br>~~ee~~|1<br>~~ee~~|N/A|N/A|mA|
|||XA7A15T<br>~~a~~<br>~~a~~<br>~~ee~~|N/A<br>~~ee~~<br>~~ee~~|1<br>~~ee~~<br>~~ee~~|N/A<br>~~ee~~|1<br>~~ee~~|N/A|N/A|mA|
|||XA7A25T<br>~~ee~~|N/A<br>~~ee~~|1<br>~~ee~~|N/A<br>~~ee~~|1<br>~~ee~~|N/A|N/A|mA|
|||XA7A35T<br>~~ee~~<br>~~a~~|N/A<br>~~ee~~|1<br>~~ee~~|N/A<br>~~ee~~|1<br>~~ee~~|N/A|N/A|mA|
|||XA7A50T<br>~~a~~<br>~~a~~<br>~~ee~~|N/A<br>~~ee~~<br>~~ee~~|1<br>~~ee~~<br>~~ee~~|N/A<br>~~ee~~|1<br>~~ee~~|N/A|N/A|mA|
|||XA7A75T<br>~~ee~~|N/A<br>~~ee~~|4<br>~~ee~~|N/A<br>~~ee~~|4<br>~~ee~~|N/A|N/A|mA|
|||XA7A100T<br>~~ee~~<br>~~a~~<br>~~PR~~|N/A<br>~~ee~~<br>|4<br>~~ee~~|N/A<br>~~ee~~|4<br>~~ee~~|N/A|N/A|mA|
|||XQ7A50T<br>~~a~~<br>~~PRee~~|N/A<br>~~ee~~|1<br>~~ee~~|N/A<br>~~ee~~|1<br>~~ee~~|1|N/A|mA|
|||XQ7A100T<br>~~PRee~~|N/A<br>~~ee~~|4<br>~~ee~~|N/A<br>~~ee~~|4<br>~~ee~~|4|N/A|mA|
|||XQ7A200T<br>~~ee~~<br>~~ee~~|N/A<br>~~ee~~<br>~~ee~~|5<br>~~ee~~<br>~~ee~~|N/A<br>~~ee~~<br>~~ee~~|5<br>~~ee~~<br>~~ee~~|5<br>~~ee~~|N/A<br>~~ee~~|mA<br>~~ee~~|
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~~AMDT~~ **Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 5:_ **Typical Quiescent Supply Current** _**(Cont’d)**_
|**Symbol**<br>~~=~~|**Description**<br>~~=~~|**Device**<br>~~=~~|**Speed Grade**<br>~~pe~~<br>~~=~~|**Speed Grade**<br>~~pe~~<br>~~=~~|**Speed Grade**<br>~~pe~~<br>~~=~~|**Speed Grade**<br>~~pe~~<br>~~=~~|**Speed Grade**<br>~~pe~~<br>~~=~~|**Speed Grade**<br>~~pe~~<br>~~=~~|**Units**<br>~~pe~~<br>~~=~~<br>~~ee~~|
|---|---|---|---|---|---|---|---|---|---|
||||**1.0V**<br>~~=~~||||**0.95V**<br>~~=~~|**0.9V**<br>~~=~~||
||||**-3**<br>~~=~~<br>~~a~~|**-2**<br>~~=~~<br>~~ee~~|**-2LE**<br>~~=~~<br>~~ee~~|**-1**<br>~~=~~<br>~~ee~~|**-1LI**<br>~~=~~<br>~~ee~~|**-2LE**<br>~~=~~<br>~~ee~~||
|ICCAUXQ|Quiescent VCCAUXsupply current|XC7A12T<br>~~a~~|13|13|13|13|13|13|mA|
|||XC7A15T<br>~~a~~<br>~~a~~|22|22|22|22|19|22|mA|
|||XC7A25T<br>~~a~~<br>~~a~~<br>~~ee~~|13<br>~~ee~~<br>~~ee~~|13<br>~~ee~~<br>~~ee~~|13<br>~~ee~~|13<br>~~ee~~|13|13|mA|
|||XC7A35T<br>~~ee~~|22<br>~~ee~~|22<br>~~ee~~|22<br>~~ee~~|22<br>~~ee~~|19|22|mA|
|||XC7A50T<br>~~ee~~<br>~~a~~|22<br>~~ee~~|22<br>~~ee~~|22<br>~~ee~~|22<br>~~ee~~|19|22|mA|
|||XC7A75T<br>~~a~~<br>~~a~~<br>~~ee~~|36<br>~~ee~~<br>~~ee~~|36<br>~~ee~~<br>~~ee~~|36<br>~~ee~~|36<br>~~ee~~|32|36|mA|
|||XC7A100T<br>~~ee~~|36<br>~~ee~~|36<br>~~ee~~|36<br>~~ee~~|36<br>~~ee~~|32|36|mA|
|||XC7A200T<br>~~ee~~<br>~~a~~|73<br>~~ee~~|73<br>~~ee~~|73<br>~~ee~~|73<br>~~ee~~|65|73|mA|
|||XA7A12T<br>~~a~~<br>~~a~~<br>~~ee~~|N/A<br>~~ee~~<br>~~ee~~|13<br>~~ee~~<br>~~ee~~|N/A<br>~~ee~~|13<br>~~ee~~|N/A|N/A|mA|
|||XA7A15T<br>~~ee~~|N/A<br>~~ee~~|22<br>~~ee~~|N/A<br>~~ee~~|22<br>~~ee~~|N/A|N/A|mA|
|||XA7A25T<br>~~ee~~<br>~~a~~|N/A<br>~~ee~~|13<br>~~ee~~|N/A<br>~~ee~~|13<br>~~ee~~|N/A|N/A|mA|
|||XA7A35T<br>~~a~~<br>~~a~~<br>~~ee~~|N/A<br>~~ee~~<br>~~ee~~|22<br>~~ee~~<br>~~ee~~|N/A<br>~~ee~~|22<br>~~ee~~|N/A|N/A|mA|
|||XA7A50T<br>~~a~~<br>~~ee~~|N/A<br>~~ee~~<br>~~ee~~|22<br>~~ee~~<br>~~ee~~|N/A<br>~~ee~~|22<br>~~ee~~|N/A|N/A|mA|
|||XA7A75T<br>~~ee~~<br>~~a~~|N/A<br>~~ee~~|36<br>~~ee~~|N/A<br>~~ee~~|36<br>~~ee~~|N/A|N/A|mA|
|||XA7A100T<br>~~a~~<br>~~a~~<br>~~ee~~|N/A<br>~~ee~~<br>~~ee~~|36<br>~~ee~~<br>~~ee~~|N/A<br>~~ee~~|36<br>~~ee~~|N/A|N/A|mA|
|||XQ7A50T<br>~~ee~~|N/A<br>~~ee~~|22<br>~~ee~~|N/A<br>~~ee~~|22<br>~~ee~~|19|N/A|mA|
|||XQ7A100T<br>~~ee~~<br>~~a~~|N/A<br>~~ee~~|36<br>~~ee~~|N/A<br>~~ee~~|36<br>~~ee~~|32|N/A|mA|
|||XQ7A200T<br>~~a~~<br>~~a~~|N/A<br>~~ee~~|73<br>~~ee~~|N/A|73|65|N/A|mA|
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~~AMDT~~ **Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 5:_ **Typical Quiescent Supply Current** _**(Cont’d)**_
|**Symbol**<br>~~=~~|**Description**<br>~~=~~|**Device**<br>~~=~~|**Speed Grade**<br>~~pe~~<br>~~=~~|**Speed Grade**<br>~~pe~~<br>~~=~~|**Speed Grade**<br>~~pe~~<br>~~=~~|**Speed Grade**<br>~~pe~~<br>~~=~~|**Speed Grade**<br>~~pe~~<br>~~=~~|**Speed Grade**<br>~~pe~~<br>~~=~~|**Units**<br>~~pe~~<br>~~=~~<br>~~ee~~|
|---|---|---|---|---|---|---|---|---|---|
||||**1.0V**<br>~~=~~||||**0.95V**<br>~~=~~|**0.9V**<br>~~=~~||
||||**-3**<br>~~=~~<br>~~a~~|**-2**<br>~~=~~<br>~~ee~~|**-2LE**<br>~~=~~<br>~~ee~~|**-1**<br>~~=~~<br>~~ee~~|**-1LI**<br>~~=~~<br>~~ee~~|**-2LE**<br>~~=~~<br>~~ee~~||
|ICCBRAMQ|Quiescent VCCBRAMsupply current|XC7A12T<br>~~a~~|1|1|1|1|1|1|mA|
|||XC7A15T<br>~~a~~<br>~~a~~|2|2|2|2|1|2|mA|
|||XC7A25T<br>~~a~~<br>~~a~~<br>~~ee~~|1<br>~~ee~~<br>~~ee~~|1<br>~~ee~~<br>~~ee~~|1<br>~~ee~~|1<br>~~ee~~|1|1|mA|
|||XC7A35T<br>~~ee~~|2<br>~~ee~~|2<br>~~ee~~|2<br>~~ee~~|2<br>~~ee~~|1|2|mA|
|||XC7A50T<br>~~ee~~<br>~~a~~|2<br>~~ee~~|2<br>~~ee~~|2<br>~~ee~~|2<br>~~ee~~|1|2|mA|
|||XC7A75T<br>~~a~~<br>~~a~~<br>~~ee~~|4<br>~~ee~~<br>~~ee~~|4<br>~~ee~~<br>~~ee~~|4<br>~~ee~~|4<br>~~ee~~|2|4|mA|
|||XC7A100T<br>~~ee~~|4<br>~~ee~~|4<br>~~ee~~|4<br>~~ee~~|4<br>~~ee~~|2|4|mA|
|||XC7A200T<br>~~ee~~<br>~~a~~|11<br>~~ee~~|11<br>~~ee~~|11<br>~~ee~~|11<br>~~ee~~|6|11|mA|
|||XA7A12T<br>~~a~~<br>~~a~~<br>~~ee~~|N/A<br>~~ee~~<br>~~ee~~|1<br>~~ee~~<br>~~ee~~|N/A<br>~~ee~~|1<br>~~ee~~|N/A|N/A|mA|
|||XA7A15T<br>~~ee~~|N/A<br>~~ee~~|2<br>~~ee~~|N/A<br>~~ee~~|2<br>~~ee~~|N/A|N/A|mA|
|||XA7A25T<br>~~ee~~<br>~~a~~|N/A<br>~~ee~~|1<br>~~ee~~|N/A<br>~~ee~~|1<br>~~ee~~|N/A|N/A|mA|
|||XA7A35T<br>~~a~~<br>~~a~~<br>~~ee~~|N/A<br>~~ee~~<br>~~ee~~|2<br>~~ee~~<br>~~ee~~|N/A<br>~~ee~~|2<br>~~ee~~|N/A|N/A|mA|
|||XA7A50T<br>~~a~~<br>~~ee~~|N/A<br>~~ee~~<br>~~ee~~|2<br>~~ee~~<br>~~ee~~|N/A<br>~~ee~~|2<br>~~ee~~|N/A|N/A|mA|
|||XA7A75T<br>~~ee~~<br>~~a~~|N/A<br>~~ee~~|4<br>~~ee~~|N/A<br>~~ee~~|4<br>~~ee~~|N/A|N/A|mA|
|||XA7A100T<br>~~a~~<br>~~a~~<br>~~ee~~|N/A<br>~~ee~~<br>~~ee~~|4<br>~~ee~~<br>~~ee~~|N/A<br>~~ee~~|4<br>~~ee~~|N/A|N/A|mA|
|||XQ7A50T<br>~~ee~~|N/A<br>~~ee~~|2<br>~~ee~~|N/A<br>~~ee~~|2<br>~~ee~~|1|N/A|mA|
|||XQ7A100T<br>~~ee~~<br>~~a~~|N/A<br>~~ee~~|4<br>~~ee~~|N/A<br>~~ee~~|4<br>~~ee~~|2|N/A|mA|
|||XQ7A200T<br>~~a~~<br>~~a~~|N/A<br>~~ee~~|11<br>~~ee~~|N/A|11|6|N/A|mA|
## **Notes:**
1. Typical values are specified at nominal voltage, 85°C junction temperature (Tj) with single-ended SelectIO resources.
2. Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and floating.
3. Use the Xilinx Power Estimator (XPE) spreadsheet tool (download at http://www.xilinx.com/power) to estimate static power consumption for conditions other than those specified.
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**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
## **Power-On/Off Power Supply Sequencing**
The recommended power-on sequence is VCCINT, VCCBRAM, VCCAUX, and VCCO to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on. The recommended power-off sequence is the reverse of the power-on sequence. If VCCINT and VCCBRAM have the same recommended voltage levels then both can be powered by the same supply and ramped simultaneously. If VCCAUX and VCCO have the same recommended voltage levels then both can be powered by the same supply and ramped simultaneously.
For VCCO voltages of 3.3V in HR I/O banks and configuration bank 0:
- The voltage difference between VCCO and VCCAUX must not exceed 2.625V for longer than TVCCO2VCCAUX for each power-on/off cycle to maintain device reliability levels.
- The TVCCO2VCCAUX time can be allocated in any percentage between the power-on and power-off ramps.
The recommended power-on sequence to achieve minimum current draw for the GTP transceivers is VCCINT, VMGTAVCC, VMGTAVTT OR VMGTAVCC, VCCINT, VMGTAVTT. Both VMGTAVCC and VCCINT can be ramped simultaneously. The recommended power-off sequence is the reverse of the power-on sequence to achieve minimum current draw.
If these recommended sequences are not met, current drawn from VMGTAVTT can be higher than specifications during powerup and power-down.
- When VMGTAVTT is powered before VMGTAVCC and VMGTAVTT – VMGTAVCC > 150 mV and VMGTAVCC < 0.7V, the VMGTAVTT current draw can increase by 460 mA per transceiver during VMGTAVCC ramp up. The duration of the current draw can be up to 0.3 x TMGTAVCC (ramp time from GND to 90% of VMGTAVCC). The reverse is true for power-down.
- When VMGTAVTT is powered before VCCINT and VMGTAVTT – VCCINT > 150 mV and VCCINT < 0.7V, the VMGTAVTT current draw can increase by 50 mA per transceiver during VCCINT ramp up. The duration of the current draw can be up to 0.3 x TVCCINT (ramp time from GND to 90% of VCCINT). The reverse is true for power-down.
There is no recommended sequence for supplies not shown.
Table 6 shows the minimum current, in addition to ICCQ, that is required by Artix 7 devices for proper power-on and configuration. If the current minimums shown in Table 5 and Table 6 are met, the device powers on after all four supplies have passed through their power-on reset threshold voltages. The FPGA must not be configured until after VCCINT is applied.
Once initialized and configured, use the Xilinx Power Estimator (XPE) tool (download at http://www.xilinx.com/power) to estimate current drain on these supplies.
_Table 6:_ **Power-On Current for Artix 7 Devices**
|**Device**<br>~~eG~~|**ICCINTMIN**<br>~~eG~~|**ICCAUXMIN**<br>~~eG~~|**ICCOMIN**<br>~~eG~~|**ICCBRAMMIN**<br>~~eG~~|**Units**<br>~~eG~~|
|---|---|---|---|---|---|
|XC7A12T<br>~~a~~<br>~~Re~~|ICCINTQ+ 120|ICCAUXQ+ 40|ICCOQ+ 40 mA per bank|ICCBRAMQ+ 60|mA|
|XC7A15T<br>~~a~~<br>~~Re~~|ICCINTQ+ 120|ICCAUXQ+ 40|ICCOQ+ 40 mA per bank|ICCBRAMQ+ 60|mA|
|XC7A25T<br>~~Re~~<br>~~eG~~<br>~~Re~~|ICCINTQ+ 120<br>~~eG~~|ICCAUXQ+ 40<br>~~GG~~|ICCOQ+ 40 mA per bank<br>~~GG~~|ICCBRAMQ+ 60|mA|
|XC7A35T<br>~~eG~~<br>~~Re~~<br>~~Re~~|ICCINTQ+ 120<br>~~eG~~|ICCAUXQ+ 40<br>~~GG~~|ICCOQ+ 40 mA per bank<br>~~GG~~|ICCBRAMQ+ 60|mA|
|XC7A50T<br>~~Re~~<br>~~Re~~|ICCINTQ+ 120|ICCAUXQ+ 40|ICCOQ+ 40 mA per bank|ICCBRAMQ+ 60|mA|
|XC7A75T<br>~~Re~~<br>~~eG~~<br>~~Re~~|ICCINTQ+ 170<br>~~eG~~|ICCAUXQ+ 40<br>~~GG~~|ICCOQ+ 40 mA per bank<br>~~GG~~|ICCBRAMQ+ 60|mA|
|XC7A100T<br>~~eG~~<br>~~Re~~<br>~~Re~~|ICCINTQ+ 170<br>~~eG~~|ICCAUXQ+ 40<br>~~GG~~|ICCOQ+ 40 mA per bank<br>~~GG~~|ICCBRAMQ+ 60|mA|
|XC7A200T<br>~~Re~~<br>~~Re~~|ICCINTQ+ 340|ICCAUXQ+ 50|ICCOQ+ 40 mA per bank|ICCBRAMQ+ 80|mA|
|XA7A12T<br>~~Re~~<br>~~eG~~<br>~~Re~~|ICCINTQ+ 120<br>~~eG~~|ICCAUXQ+ 40<br>~~GG~~|ICCOQ+ 40 mA per bank<br>~~GG~~|ICCBRAMQ+ 60|mA|
|XA7A15T<br>~~eG~~<br>~~Re~~<br>~~Re~~|ICCINTQ+ 120<br>~~eG~~|ICCAUXQ+ 40<br>~~GG~~|ICCOQ+ 40 mA per bank<br>~~GG~~|ICCBRAMQ+ 60|mA|
|XA7A25T<br>~~Re~~<br>~~Re~~|ICCINTQ+ 120|ICCAUXQ+ 40|ICCOQ+ 40 mA per bank|ICCBRAMQ+ 60|mA|
|XA7A35T<br>~~Re~~<br>~~eG~~|ICCINTQ+ 120<br>~~eG~~|ICCAUXQ+ 40<br>~~GG~~|ICCOQ+ 40 mA per bank<br>~~GG~~|ICCBRAMQ+ 60|mA|
|XA7A50T<br>~~eG~~<br>~~eG~~<br>~~Re~~|ICCINTQ+ 120<br>~~eG~~<br>~~eG~~|ICCAUXQ+ 40<br>~~GG~~<br>~~eG~~|ICCOQ+ 40 mA per bank<br>~~GG~~<br>~~eG~~|ICCBRAMQ+ 60<br>~~eG~~|mA<br>~~eG~~|
|XA7A75T<br>~~Re~~|ICCINTQ+ 170|ICCAUXQ+ 40|ICCOQ+ 40 mA per bank|ICCBRAMQ+ 60|mA|
|XA7A100T<br>~~Re~~<br>~~eG~~|ICCINTQ+ 170<br>~~eG~~|ICCAUXQ+ 40<br>~~GG~~|ICCOQ+ 40 mA per bank<br>~~GG~~|ICCBRAMQ+ 60|mA|
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**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 6:_ **Power-On Current for Artix 7 Devices** _**(Cont’d)**_
|~~es~~||||||
|---|---|---|---|---|---|
|**Symbol**<br>~~es~~|**Description**|**Conditions**|**Min**|**Max**|**Units**|
|TVCCINT<br>~~es~~<br>~~a~~|Ramp time from GND to 90% of VCCINT||0.2|50|ms|
|TVCCO<br>~~a~~<br>~~a~~<br>~~es~~|Ramp time from GND to 90% of VCCO||0.2|50|ms|
|TVCCAUX<br>~~a~~<br>~~es~~|Ramp time from GND to 90% of VCCAUX||0.2|50|ms|
|TVCCBRAM<br>~~es~~<br>~~A~~|Ramp time from GND to 90% of VCCBRAM<br>~~ee~~||0.2<br>~~ee~~<br>|50<br>~~eee~~<br>|ms|
|TVCCO2VCCAUX<br>~~A~~|Allowed time per power cycle for VCCO– VCCAUX 2.625V|TJ= 125°C(1)<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~<br>|300<br>~~ee~~<br>~~eee~~<br>|ms|
|||TJ= 100°C(1)<br>~~ee~~<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|500<br>~~ee~~<br>~~eee~~<br>~~ee~~<br>||
|||TJ= 85°C(1)<br>~~ee ~~<br>~~ee~~|–<br>~~ee ~~<br> ~~ee~~<br>~~ee~~|800<br> ~~eee~~<br>~~ee~~<br>~~ee~~||
|TMGTAVCC<br>~~a~~<br>~~es~~|Ramp time from GND to 90% of VMGTAVCC<br> <br>~~ee ~~||0.2<br> ~~ee~~<br> ~~ee~~|50<br>~~ee~~<br>~~ee~~|ms|
|TMGTAVTT<br>~~a~~<br>~~es~~|Ramp time from GND to 90% of VMGTAVTT||0.2|50|ms|
_Table 7:_ **Power Supply Ramp Time**
## **Notes:**
1. Based on 240,000 power cycles with nominal VCCO of 3.3V or 36,500 power cycles with worst case VCCO of 3.465V.
## **DC Input and Output Levels**
Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the recommended operating conditions at the VOL and VOH test points. Only selected standards are tested. These are chosen to ensure that all standards meet their specifications. The selected standards are tested at a minimum VCCO with the respective VOL and VOH voltage levels shown. Other standards are sample tested.
_Table 8:_ **SelectIO DC Input and Output Levels[(1)(2)]**
|**I/O Standard**<br>~~ee~~|**VIL**<br>~~ee~~|**VIL**<br>~~ee~~|**VIH**<br>~~ee~~|**VIH**<br>~~ee~~|**VOL**|**VOH**|**IOL**|**IOH**|
|---|---|---|---|---|---|---|---|---|
||**V, Min**<br>~~ee~~|**V, Max**<br>~~ee~~|**V, Min**<br>~~ee~~|**V, Max**<br>~~ee~~|**V, Max**|**V, Min**|**mA, Max **|**mA, Min**|
|HSTL_I<br>~~GG~~<br>~~ee~~|–0.300<br>~~GG~~<br>~~ee~~|VREF– 0.100<br>~~GG~~<br>~~GG~~|VREF+ 0.100<br>~~GG~~<br>~~GG~~|VCCO+ 0.300<br>~~GCG~~<br>~~GG~~|0.400<br>~~GCG~~|VCCO– 0.400<br>~~GCG~~|8.00<br>~~GCG~~|–8.00|
|HSTL_I_18<br>~~GG~~<br>~~ee~~<br>~~po~~|–0.300<br>~~GG~~<br>~~ee~~|VREF– 0.100<br>~~GG~~<br>~~GG~~|VREF+ 0.100<br>~~GG ~~<br>~~GG~~|VCCO+ 0.300<br> ~~GCG~~<br>~~GG~~|0.400<br>~~GCG~~|VCCO– 0.400<br>~~GCG~~|8.00<br>~~GCG~~|–8.00|
|HSTL_II<br>~~ee~~<br>~~po~~<br>~~Re~~|–0.300<br>~~ee ~~<br>~~ee~~|VREF– 0.100<br> ~~GG~~<br>~~ee~~|VREF+ 0.100<br>~~GG~~<br>~~Ge~~|VCCO+ 0.300<br>~~GG~~<br>~~CG~~|0.400<br>~~CG~~|VCCO– 0.400<br>~~CG~~|16.00<br>~~CG~~|–16.00<br>~~CG~~|
|HSTL_II_18<br>~~po~~<br>~~Re~~<br>~~ee~~|–0.300<br>~~ee~~<br>~~ee~~|VREF– 0.100<br>~~ee~~<br>~~Ge~~|VREF+ 0.100<br>~~Ge~~<br>~~GG~~|VCCO+ 0.300<br>~~CG~~<br>~~GG~~|0.400<br>~~CG~~|VCCO– 0.400<br>~~CG~~|16.00<br>~~CG~~|–16.00<br>~~CG~~|
|HSUL_12<br>~~Re ~~<br>~~ee~~<br>~~po~~|–0.300<br> ~~ee~~<br>~~ee~~|VREF– 0.130<br>~~ee~~<br>~~Ge~~|VREF+ 0.130<br>~~Ge ~~<br>~~GG~~|VCCO+ 0.300<br> ~~CG~~<br>~~GG~~|20% VCCO<br>~~CG~~|80% VCCO<br>~~CG~~|0.10<br>~~CG~~|–0.10<br>~~CG~~|
|LVCMOS12<br>~~ee~~<br>~~po~~<br>~~ee~~|–0.300<br>~~ee ~~<br>~~Ge~~|35% VCCO<br> ~~Ge ~~<br>~~Ge~~|65% VCCO<br> ~~GG~~<br>~~GC~~|VCCO+ 0.300<br>~~GG~~<br>~~GC~~|0.400<br>~~eG~~|VCCO– 0.400<br>~~eG~~|Note 3|Note 3|
|LVCMOS15<br>~~po~~<br>~~ee~~<br>~~po~~|–0.300<br>~~Ge~~|35% VCCO<br>~~Ge~~|65% VCCO<br>~~GC~~<br>~~GS~~|VCCO+ 0.300<br>~~GC~~<br>~~GS~~|25% VCCO<br>~~eG~~|75% VCCO<br>~~eG~~|Note 4|Note 4|
|LVCMOS18<br>~~ee ~~<br>~~Ge~~<br>~~po~~|–0.300<br> ~~Ge~~<br>~~Ge~~|35% VCCO<br>~~Ge ~~<br>~~Ge~~|65% VCCO<br> ~~GC~~<br>~~Ge~~<br>~~GS~~|VCCO+ 0.300<br>~~GC~~<br>~~Ge~~<br>~~GS~~|0.450<br>~~eG~~<br>~~Ge~~|VCCO– 0.450<br>~~eG~~<br>~~Ge~~|Note 5<br>~~Ge~~|Note 5<br>~~Ge~~|
|LVCMOS25<br>~~Ge~~<br>~~po~~<br>~~Re~~|–0.300<br>~~Ge~~<br>~~ee~~|0.7<br>~~Ge~~<br>~~ee~~|1.700<br>~~Ge~~<br>~~GS~~<br>~~Ge~~|VCCO+ 0.300<br>~~Ge~~<br>~~GS~~<br>~~CG~~|0.400<br>~~Ge~~<br>~~CG~~|VCCO– 0.400<br>~~Ge~~<br>~~CG~~|Note 4<br>~~Ge~~<br>~~CG~~|Note 4<br>~~Ge~~<br>~~CG~~|
|LVCMOS33<br>~~po~~<br>~~Re~~<br>~~ee~~|–0.300<br>~~ee~~<br>~~ee~~|0.8<br>~~ee~~<br>~~Ge~~|2.000<br>~~GS~~<br>~~Ge~~<br>~~GG~~|3.450<br>~~GS~~<br>~~CG~~<br>~~GG~~|0.400<br>~~CG~~|VCCO– 0.400<br>~~CG~~|Note 4<br>~~CG~~|Note 4<br>~~CG~~|
|LVTTL<br>~~Re ~~<br>~~ee~~<br>~~po~~|–0.300<br> ~~ee~~<br>~~ee~~|0.8<br>~~ee~~<br>~~Ge~~|2.000<br>~~Ge ~~<br>~~GG~~|3.450<br> ~~CG~~<br>~~GG~~|0.400<br>~~CG~~|2.400<br>~~CG~~|Note 5<br>~~CG~~|Note 5<br>~~CG~~|
|MOBILE_DDR<br>~~ee~~<br>~~po~~<br>~~Re~~|–0.300<br>~~ee ~~<br>~~ee~~|20% VCCO<br> ~~Ge ~~<br>~~ee~~|80% VCCO<br> ~~GG~~<br>~~Ge~~|VCCO+ 0.300<br>~~GG~~<br>~~CG~~|10% VCCO<br>~~CG~~|90% VCCO<br>~~CG~~|0.10<br>~~CG~~|–0.10<br>~~CG~~|
|PCI33_3<br>~~po~~<br>~~Re~~<br>~~ee~~|–0.400<br>~~ee~~<br>~~ee~~|30% VCCO<br>~~ee~~<br>~~Ge~~|50% VCCO<br>~~Ge~~<br>~~GG~~|VCCO+ 0.500<br>~~CG~~<br>~~GG~~|10% VCCO<br>~~CG~~|90% VCCO<br>~~CG~~|1.50<br>~~CG~~|–0.50<br>~~CG~~|
|SSTL135<br>~~Re ~~<br>~~ee~~<br>~~pO~~|–0.300<br> ~~ee~~<br>~~ee~~|VREF– 0.090<br>~~ee~~<br>~~Ge~~|VREF+ 0.090<br>~~Ge ~~<br>~~GG~~|VCCO+ 0.300 <br> ~~CG~~<br>~~GG~~|VCCO/2 – 0.150 <br>~~CG~~|VCCO/2 + 0.150<br>~~CG~~|13.00<br>~~CG~~|–13.00<br>~~CG~~|
|SSTL135_R<br>~~ee~~<br>~~pO~~|–0.300<br>~~ee ~~|VREF– 0.090<br> ~~Ge ~~|VREF+ 0.090<br> ~~GG~~|VCCO+ 0.300 <br>~~GG~~|VCCO/2 – 0.150|VCCO/2 + 0.150|8.90|–8.90|
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DS181 (v1.27.1) July 3, 2024 **Product Specification**
9
**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
|**I/O Standard**<br>~~ee~~|**VIL**<br>~~ee~~|**VIL**<br>~~ee~~|**VIH**<br>~~ee~~<br>~~ee~~|**VIH**<br>~~ee~~<br>~~ee~~|**VOL**<br>~~ee~~<br>~~ee~~|**VOH**<br>~~ee~~<br>~~eee~~|**IOL**<br>~~ee~~<br>~~eee~~|**IOH**<br>~~ee~~<br>~~eee~~|
|---|---|---|---|---|---|---|---|---|
||**V, Min**<br>~~ee~~<br>~~Ge~~|**V, Max**<br>~~ee~~<br>~~Ge~~|**V, Min**<br>~~ee~~<br>~~Ge~~|**V, Max**<br>~~ee~~<br>~~ee~~<br>~~Ge~~|**V, Max**<br>~~ee~~<br>~~ee~~<br>~~Ge~~|**V, Min**<br>~~ee~~<br>~~eee~~<br>~~Ge~~|**mA, Max **<br>~~ee~~<br>~~eee~~<br>~~Ge~~|**mA, Min**<br>~~ee~~<br>~~eee~~<br>~~Ge~~|
|SSTL15<br>~~GC~~|–0.300<br>~~GC~~|VREF– 0.100<br>~~GC~~|VREF+ 0.100<br>~~GC~~|VCCO+ 0.300 <br>~~ee ~~<br>~~GC~~|VCCO/2 – 0.175 <br> ~~ee ~~<br>~~GC~~|VCCO/2 + 0.175<br> ~~eee~~<br>~~GC~~|13.00<br>~~eee~~<br>~~GC~~|–13.00<br>~~eee~~<br>~~GC~~|
|SSTL15_R<br>~~po~~<br>~~Pe~~|–0.300<br>~~po~~<br>~~Ge~~|VREF– 0.100<br>~~po~~<br>~~Ge~~|VREF+ 0.100<br>~~po~~<br>~~GG~~|VCCO+ 0.300 <br>~~po~~<br>~~GG~~|VCCO/2 – 0.175 <br>~~po~~<br>~~GG~~|VCCO/2 + 0.175<br>~~po~~<br>~~GG~~|8.90<br>~~po~~<br>~~GG~~|–8.90<br>~~po~~<br>~~GG~~|
|SSTL18_I<br>~~po~~<br>~~Pe~~<br>~~po~~|–0.300<br>~~po~~<br>~~Ge~~|VREF– 0.125<br>~~po~~<br>~~Ge~~|VREF+ 0.125<br>~~po~~<br>~~GG~~|VCCO+ 0.300 <br>~~po~~<br>~~GG~~|VCCO/2 – 0.470 <br>~~po~~<br>~~GG~~|VCCO/2 + 0.470<br>~~po~~<br>~~GG~~|8.00<br>~~po~~<br>~~GG~~|–8.00<br>~~po~~<br>~~GG~~|
|SSTL18_II<br>~~Pe ~~<br>~~po~~|–0.300<br> ~~Ge~~|VREF– 0.125<br>~~Ge ~~|VREF+ 0.125<br> ~~GG~~|VCCO+ 0.300 <br>~~GG~~|VCCO/2 – 0.600 <br>~~GG~~|VCCO/2 + 0.600<br>~~GG~~|13.40<br>~~GG~~|–13.40<br>~~GG~~|
## **Notes:**
1. Tested according to relevant specifications.
2. 3.3V and 2.5V standards are only supported in HR I/O banks.
3. Supported drive strengths of 4, 8, or 12 mA in HR I/O banks.
4. Supported drive strengths of 4, 8, 12, or 16 mA in HR I/O banks.
5. Supported drive strengths of 4, 8, 12, 16, or 24 mA in HR I/O banks.
6. For detailed interface specific DC voltage levels, see _7 Series FPGAs SelectIO Resources User Guide_ (UG471).
_Table 9:_ **Differential SelectIO DC Input and Output Levels**
|**I/O Standard**<br>~~a ~~<br>~~I~~|**VICM(1)**<br>~~ee~~<br>~~erees~~|**VICM(1)**<br>~~ee~~<br>~~erees~~|**VICM(1)**<br>~~ee~~<br>~~erees~~|**VID(2)**<br>~~eG~~<br>~~eeee~~|**VID(2)**<br>~~eG~~<br>~~eeee~~|**VID(2)**<br>~~eG~~<br>~~eeee~~|**VOCM(3)**<br>~~eG~~<br>~~eseeeee~~|**VOCM(3)**<br>~~eG~~<br>~~eseeeee~~|**VOCM(3)**<br>~~eG~~<br>~~eseeeee~~|**VOD(4)**<br>~~eG~~<br>~~eee~~|**VOD(4)**<br>~~eG~~<br>~~eee~~|**VOD(4)**<br>~~eG~~<br>~~eee~~|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
||**V, Min **<br>~~ee~~<br> ~~ere~~|**V, Typ**<br>~~ee~~<br>~~ere~~|**V, Max**<br>~~ee~~<br>~~es~~|**V, Min **<br>~~eG~~<br>~~ee~~|**V, Typ **<br>~~eG~~<br>~~ee~~|**V, Max**<br>~~eG~~<br>~~ee~~|**V, Min**<br>~~eG~~<br>~~es~~|**V, Typ**<br>~~eG~~<br>~~ee~~|**V, Max**<br>~~eG~~<br>~~eee~~|**V, Min **<br>~~eG~~<br>~~eee~~|**V, Typ **<br>~~eG~~<br>~~eee~~|**V, Max**<br>~~eG~~<br>~~eee~~|
|BLVDS_25<br> <br>~~I~~|0.300<br> ~~ere~~<br>~~eG~~|1.200<br>~~ere~~<br>~~eG~~|1.425<br>~~es~~<br>~~eG~~|0.100<br>~~ee~~<br>~~eG~~|–<br>~~ee~~<br>~~GG~~|–<br>~~ee~~<br>~~GG~~|–<br>~~es~~|1.250<br>~~ee~~|–<br>~~eee~~|Note 5<br>~~eee~~|||
|MINI_LVDS_25 <br> <br>~~I~~<br>~~Re~~<br>~~PR~~|0.300<br> ~~ere~~<br>~~eG~~<br>~~Re~~<br>~~ee~~|1.200<br>~~ere ~~<br>~~eG~~<br>~~eG~~<br>~~ee~~|VCCAUX<br> ~~es ~~<br>~~eG~~<br>~~eG~~<br>~~ee~~|0.200<br> ~~ee ~~<br>~~eG ~~<br>~~eG~~<br>~~GG~~|0.400<br> ~~ee~~<br> ~~GG~~<br>~~GG~~<br>~~GG~~|0.600<br>~~ee ~~<br>~~GG~~<br>~~GG~~<br>~~Ge~~|1.000<br> ~~es ~~<br>~~GG~~<br>~~Ge~~|1.200<br> ~~ee ~~|1.400<br> ~~eee~~|0.300<br>~~eee~~|0.450<br>~~eee~~|0.600<br>~~eee~~|
|PPDS_25<br>~~PR~~<br>~~po~~|0.200<br>~~ee~~<br>~~CT~~|0.900<br>~~ee~~<br>~~CT~~|VCCAUX<br>~~ee~~|0.100<br>~~GG~~|0.250<br>~~GG~~|0.400<br>~~Ge~~|0.500<br>~~Ge~~|0.950|1.400|0.100|0.250|0.400|
|RSDS_25<br>~~PR~~<br>~~po~~|0.300<br>~~ee ~~<br>~~CT~~|0.900<br> ~~ee~~<br>~~CT~~|1.500<br>~~ee~~|0.100<br>~~GG~~|0.350<br>~~GG ~~|0.600<br> ~~Ge~~|1.000<br>~~Ge~~|1.200|1.400|0.100|0.350|0.600|
|TMDS_33<br>~~po~~<br>~~a~~|2.700<br>~~CT~~<br>~~ee~~|2.965<br>~~CT~~<br>~~ee~~|3.230<br>~~eG~~|0.150<br>~~eG ~~|0.675<br> ~~GG~~|1.200<br>~~GG~~|VCCO–0.405|VCCO–0.300|VCCO–0.190|0.400|0.600|0.800|
## **Notes:**
1. VICM is the input common mode voltage.
2. VID is the input differential voltage (Q – Q).
3. VOCM is the output common mode voltage.
4. VOD is the output differential voltage (Q – Q).
5. VOD for BLVDS will vary significantly depending on topology and loading.
_Table 10:_ **Complementary Differential SelectIO DC Input and Output Levels**
|**I/O Standard**<br>~~eee~~<br>~~po~~|**VICM(1)**<br>~~eee~~<br>~~a~~|**VICM(1)**<br>~~eee~~<br>~~a~~|**VICM(1)**<br>~~eee~~<br>~~a~~|**VID(2)**<br>~~eee~~|**VID(2)**<br>~~eee~~|**VOL(3)**<br>~~eee~~|**VOH(4)**<br>~~eee~~<br>~~ee~~|**IOL**<br>~~eee~~|**IOH**<br>~~eee~~|
|---|---|---|---|---|---|---|---|---|---|
||**V, Min **<br>~~eee~~<br>~~a~~|**V,Typ **<br>~~eee~~|**V, Max **<br>~~eee~~|**V,Min **<br>~~eee~~|**V, Max**<br>~~eee~~|**V, Max**<br>~~eee~~|**V, Min**<br>~~eee~~<br>~~ee~~|**mA, Max**<br>~~eee~~|**mA, Min**<br>~~eee~~|
|DIFF_HSTL_I<br>~~po~~<br>~~po~~|0.300<br>~~a~~|0.750|1.125|0.100|–|0.400|VCCO–0.400<br>~~ee~~|8.00|–8.00|
|DIFF_HSTL_I_18<br>~~po~~<br>~~po~~<br>~~po~~|0.300<br>~~a~~|0.900|1.425|0.100|–|0.400|VCCO–0.400<br>~~ee~~|8.00|–8.00|
|DIFF_HSTL_II<br>~~po~~<br>~~po~~<br>~~po~~|0.300|0.750|1.125|0.100|–|0.400|VCCO–0.400|16.00|–16.00|
|DIFF_HSTL_II_18<br>~~po~~<br>~~po~~<br>~~po~~|0.300|0.900|1.425|0.100|–|0.400|VCCO–0.400|16.00|–16.00|
|DIFF_HSUL_12<br>~~po~~<br>~~po~~<br>~~po~~|0.300|0.600|0.850|0.100|–|20% VCCO|80% VCCO|0.100|–0.100|
|DIFF_MOBILE_DDR<br>~~po~~<br>~~po~~<br>~~po~~|0.300|0.900|1.425|0.100|–|10% VCCO|90% VCCO|0.100|–0.100|
|DIFF_SSTL135<br>~~po~~<br>~~po~~<br>~~po~~|0.300|0.675|1.000|0.100|–|(VCCO/2) – 0.150|(VCCO/2) + 0.150|13.0|–13.0|
|DIFF_SSTL135_R<br>~~po~~<br>~~po~~<br>~~po~~|0.300|0.675|1.000|0.100|–|(VCCO/2) – 0.150|(VCCO/2) + 0.150|8.9|–8.9|
|DIFF_SSTL15<br>~~po~~<br>~~po~~<br>~~po~~|0.300|0.750|1.125|0.100|–|(VCCO/2) – 0.175|(VCCO/2) + 0.175|13.0|–13.0|
|DIFF_SSTL15_R<br>~~po~~<br>~~po~~<br>~~po~~|0.300|0.750|1.125|0.100|–|(VCCO/2) – 0.175|(VCCO/2) + 0.175|8.9|–8.9|
|DIFF_SSTL18_I<br>~~po~~<br>~~po~~|0.300|0.900|1.425|0.100|–|(VCCO/2) – 0.470|(VCCO/2) + 0.470|8.00|–8.00|
DS181 (v1.27.1) July 3, 2024 **Product Specification**
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10
**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 10:_ **Complementary Differential SelectIO DC Input and Output Levels** _**(Cont’d)**_
|**I/O Standard**|**VICM(1)**|**VICM(1)**|**VICM(1)**|**VID(2)**|**VID(2)**|**VOL(3)**|**VOH(4)**|**IOL**|**IOH**|
|---|---|---|---|---|---|---|---|---|---|
||**V, Min **|**V,Typ **|**V, Max **|**V,Min **|**V, Max**|**V, Max**|**V, Min**|**mA, Max**|**mA, Min**|
|DIFF_SSTL18_II|0.300|0.900|1.425|0.100|–|(VCCO/2) – 0.600|(VCCO/2) + 0.600|13.4|–13.4|
## **Notes:**
1. VICM is the input common mode voltage.
2. VID is the input differential voltage (Q – Q).
3. VOL is the single-ended low-output voltage.
4. VOH is the single-ended high-output voltage.
## **LVDS DC Specifications (LVDS_25)**
_Table 11:_ **LVDS_25 DC Specifications[(1)]**
|**Symbol**<br>~~a~~|**DC Parameter**|**Conditions**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|VCCO<br>~~a~~<br>~~a~~|Supply Voltage<br>~~CG~~||2.375<br>~~CG~~|2.500<br>~~CG~~|2.625<br>~~CG~~|V<br>~~CG~~|
|VOH<br>~~a~~<br>~~a~~|Output High Voltage for Q and Q<br>~~CG~~<br>~~GG~~|RT= 100across Q and Q<br>signals<br>~~CG~~<br>~~GG~~|–<br>~~CG~~<br>~~GG~~|–<br>~~CG~~<br>~~GG~~|1.675<br>~~CG~~<br>~~GG~~|V<br>~~CG~~<br>~~GG~~|
|VOL<br>~~a ~~<br>~~a~~|Output Low Voltage for Q and Q<br> ~~GG~~<br>|RT= 100across Q and Q<br>signals<br>~~GG~~<br>|0.700<br>~~GG~~<br>|–<br>~~GG~~<br>|–<br>~~GG~~<br>|V<br>~~GG~~<br>|
|VODIFF<br>~~aG~~|Differential Output Voltage:<br>(Q– Q<br>),Q= High<br>(Q<br>– Q), Q<br>= High<br>~~G~~|RT= 100across Q and Q<br>signals<br>~~GG~~|247<br>~~G~~|350<br>~~G~~|600<br>~~G~~|mV<br>~~G~~|
|VOCM<br>~~G~~|Output Common-Mode Voltage<br>~~G~~|RT= 100across Q and Q<br>signals<br>~~GG~~|1.000<br>~~G~~|1.250<br>~~G~~|1.425<br>~~G~~|V<br>~~G~~|
|VIDIFF<br>~~G~~<br>~~a~~|Differential Input Voltage:<br>(Q– Q<br>),Q= High<br>(Q<br>– Q), Q<br>= High<br>~~GG~~||100<br>~~G~~|350<br>~~G~~|600<br>~~G~~|mV<br>~~G~~|
|VICM<br>~~a~~<br>~~a~~|Input Common-Mode Voltage||0.300|1.200|1.500|V|
## **Notes:**
1. Differential inputs for LVDS_25 can be placed in banks with VCCO levels that are different from the required level for outputs. Consult the _7 Series FPGAs SelectIO Resources User Guide_ (UG471) for more information.
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DS181 (v1.27.1) July 3, 2024 **Product Specification**
11
**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
## **AC Switching Characteristics**
All values represented in this data sheet are based on the speed specifications from the ISE™ Design Suite and Vivado™Design Suite as outlined in Table 12.
_Table 12:_ **Artix 7 FPGA Speed Specification Version By Device**
|**Version In:**|**Version In:**|**Typical VCCINT**|**Device**|
|---|---|---|---|
|**ISE 14.7**|**Vivado 2018.2**|**(Table 2)**||
|N/A|1.22|1.0V|XC7A12T, XC7A15T, XC7A25T, XC7A35T, XC7A50T, XC7A75T|
|N/A|1.22|0.95V|XC7A12T, XC7A15T, XC7A25T, XC7A35T, XC7A50T, XC7A75T, XC7A100T,<br>XC7A200T|
|N/A|1.14|0.9V|XC7A12T, XC7A15T, XC7A25T, XC7A35T, XC7A50T, XC7A75T|
|1.10|1.22|1.0V|XC7A100T, XC7A200T|
|1.07|1.14|0.9V|XC7A100T, XC7A200T|
|N/A|1.15|1.0V|XA7A12T, XA7A15T, XA725T, XA7A35T, XA7A50T, XA7A75T|
|1.07|1.15|1.0V|XA7A100T|
|1.06|1.11|1.0V|XQ7A100T, XQ7A200T|
|N/A|1.11|1.0V|XQ7A50T|
Switching characteristics are specified on a per-speed-grade basis and can be designated as Advance, Preliminary, or Production. Each designation is defined as follows:
## _**Advance Product Specification**_
These specifications are based on simulations only and are typically available soon after device design specifications are frozen. Although speed grades with this designation are considered relatively stable and conservative, some under-reporting might still occur.
## _**Preliminary Product Specification**_
These specifications are based on complete ES (engineering sample) silicon characterization. Devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon. The probability of under-reporting delays is greatly reduced as compared to Advance data.
## _**Production Product Specification**_
These specifications are released once enough production silicon of a particular device family member has been characterized to provide full correlation between specifications and devices over numerous production lots. There is no under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest speed grades transition to Production before faster speed grades.
## **Testing of AC Switching Characteristics**
Internal timing parameters are derived from measuring internal test patterns. All AC switching characteristics are representative of worst-case supply voltage and junction temperature conditions.
For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer and back-annotate to the simulation net list. Unless otherwise noted, values apply to all Artix 7 FPGAs.
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**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
## **Speed Grade Designations**
Since individual family members are produced at different times, the migration from one category to another depends completely on the status of the fabrication process for each device. Table 13 correlates the current status of each Artix 7 device on a per speed grade basis.
_Table 13:_ **Artix 7 Device Speed Grade Designations**
|**Device**<br>~~TT,~~|**Speed Grade Designations**<br>~~pt~~<br>~~TT,~~|**Speed Grade Designations**<br>~~pt~~<br>~~TT,~~|**Speed Grade Designations**<br>~~pt~~<br>~~TT,~~|
|---|---|---|---|
||**Advance**<br>~~pt~~<br>~~TT,~~|**Preliminary**<br>~~pt~~<br>~~TT,~~|**Production**<br>~~pt~~<br>~~TT,~~|
|XC7A12T<br>~~TT,~~<br>~~a~~|~~TT,~~<br>|~~TT,~~<br>|-3, -2, -2LE (1.0V), -1, -1LI (0.95V), and -2LE (0.9V)<br>~~TT,~~<br>|
|XC7A15T<br>~~GG~~|~~GG~~|~~GG~~|-3, -2, -2LE (1.0V), -1, -1LI (0.95V), and -2LE (0.9V)<br>~~GG~~|
|XC7A25T<br>~~GG~~<br>~~GG~~|~~GG~~<br>~~GG~~|~~GG~~<br>~~GG~~|-3, -2, -2LE (1.0V), -1, -1LI (0.95V), and -2LE (0.9V)<br>~~GG~~<br>~~GG~~|
|XC7A35T<br>~~GG~~<br>~~GG~~|~~GG~~<br>~~GG~~|~~GG~~<br>~~GG~~|-3, -2, -2LE (1.0V), -1, -1LI (0.95V), and -2LE (0.9V)<br>~~GG~~<br>~~GG~~|
|XC7A50T<br>~~GG~~|~~GG~~|~~GG~~|-3, -2, -2LE (1.0V), -1, -1LI (0.95V), and -2LE (0.9V)<br>~~GG~~|
|XC7A75T<br>~~GG~~<br>~~GG~~|~~GG~~<br>~~GG~~|~~GG~~<br>~~GG~~|-3, -2, -2LE (1.0V), -1, -1LI (0.95V), and -2LE (0.9V)<br>~~GG~~<br>~~GG~~|
|XC7A100T<br>~~GG~~<br>~~GG~~|~~GG~~<br>~~GG~~|~~GG~~<br>~~GG~~|-3, -2, -2LE (1.0V), -1, -1LI (0.95V), and -2LE (0.9V)<br>~~GG~~<br>~~GG~~|
|XC7A200T<br>~~GG~~|~~GG~~|~~GG~~|-3, -2, -2LE (1.0V), -1, -1LI (0.95V), and -2LE (0.9V)<br>~~GG~~|
|XA7A12T<br>~~GG~~<br>~~GG~~|~~GG~~<br>~~GG~~|~~GG~~<br>~~GG~~|-2I, -1I, and -1Q<br>~~GG~~<br>~~GG~~|
|XA7A15T<br>~~GG~~<br>~~GG~~|~~GG~~<br>~~GG~~|~~GG~~<br>~~GG~~|-2I, -1I, and -1Q<br>~~GG~~<br>~~GG~~|
|XA7A25T<br>~~GG~~|~~GG~~|~~GG~~|-2I, -1I, and -1Q<br>~~GG~~|
|XA7A35T<br>~~GG~~<br>~~GG~~|~~GG~~<br>~~GG~~|~~GG~~<br>~~GG~~|-2I, -1I, and -1Q<br>~~GG~~<br>~~GG~~|
|XA7A50T<br>~~GG~~<br>~~GG~~|~~GG~~<br>~~GG~~|~~GG~~<br>~~GG~~|-2I, -1I, and -1Q<br>~~GG~~<br>~~GG~~|
|XA7A75T<br>~~GG~~|~~GG~~|~~GG~~|-2I, -1I, and -1Q<br>~~GG~~|
|XA7A100T<br>~~GG~~<br>~~GG~~|~~GG~~<br>~~GG~~|~~GG~~<br>~~GG~~|-2I, -1I, and -1Q<br>~~GG~~<br>~~GG~~|
|XQ7A50T<br>~~GG~~<br>~~GG~~|~~GG~~<br>~~GG~~|~~GG~~<br>~~GG~~|-2I, -1I, -1LI (0.95V), and -1M<br>~~GG~~<br>~~GG~~|
|XQ7A100T<br>~~GG~~|~~GG~~|~~GG~~|-2I, -1I, -1LI (0.95V), and -1M<br>~~GG~~|
|XQ7A200T<br>~~GG~~<br>~~DD~~|~~GG~~<br>~~DD~~|~~GG~~<br>~~DD~~|-2I, -1I, -1LI (0.95V), and -1M<br>~~GG~~<br>~~DD~~|
## **Production Silicon and Software Status**
In some cases, a particular family member (and speed grade) is released to production before a speed specification is released with the correct label (Advance, Preliminary, Production). Any labeling discrepancies are corrected in subsequent speed specification releases.
Table 14 lists the production released Artix 7 device, speed grade, and the minimum corresponding supported speed specification version and software revisions. The software and speed specifications listed are the minimum releases required for production. All subsequent releases of software and speed specifications are valid.
_Table 14:_ **Artix 7 Device Production Software and Speed Specification Release**
|**Device**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|
|---|---|---|---|---|---|---|---|---|
||**1.0V**||||||**0.95V**|**0.9V**|
||**-3**|**-2**|**-2LE**|**-1**|**-1Q**|**-1M**|**-1LI**|**-2LE**|
|XC7A12T|Vivado tools<br>2018.2 v1.22|Vivado tools 2017.4 v1.20|||N/A|N/A|Vivado tools<br>2017.4 v1.20|Vivado tools<br>2018.1 v1.14|
|XC7A15T|Vivado tools 2014.4 v1.14||||N/A|N/A|Vivado tools<br>2014.4 v1.14|Vivado tools<br>2014.4 v1.10|
|XC7A25T|Vivado tools<br>2018.2 v1.22|Vivado tools 2017.4 v1.20|||N/A|N/A|Vivado tools<br>2017.4 v1.20|Vivado tools<br>2018.1 v1.14|
|XC7A35T|Vivado tools 2013.4 v1.11||||N/A|N/A|Vivado tools<br>2014.4 v1.14|Vivado tools<br>2013.4 v1.08|
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**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
|**Device**<br><br>~~or~~|**Speed Grade**<br>~~Pe~~<br>~~or~~|**Speed Grade**<br>~~Pe~~<br>~~or~~|**Speed Grade**<br>~~Pe~~<br>~~or~~|**Speed Grade**<br>~~Pe~~<br>~~or~~|**Speed Grade**<br>~~Pe~~<br>~~or~~|**Speed Grade**<br>~~Pe~~<br>~~or~~|**Speed Grade**<br>~~Pe~~<br>~~or~~|**Speed Grade**<br>~~Pe~~<br>~~or~~|
|---|---|---|---|---|---|---|---|---|
||**1.0V**<br>~~or~~<br>~~Rs~~||||||**0.95V**<br>~~or~~|**0.9V**<br>~~or~~|
||**-3**<br>~~or~~<br>~~Rs~~|**-2**<br>~~or~~|**-2LE**<br>~~or~~|**-1**<br>~~or~~|**-1Q**<br>~~or~~|**-1M**<br>~~or~~|**-1LI**<br>~~or~~|**-2LE**<br>~~or~~|
|XC7A50T<br>~~or~~|Vivado tools 2013.4 v1.11<br>~~or~~<br>~~Rs~~||||N/A<br>~~or~~|N/A<br>~~or~~|Vivado tools<br>2014.4 v1.14<br>~~or~~|Vivado tools<br>2013.4 v1.08<br>~~or~~|
|XC7A75T|Vivado tools 2013.3 v1.10||||N/A|N/A|Vivado tools<br>2014.4 v1.14|Vivado tools<br>2013.3 v1.07|
|XC7A100T|ISE tools 14.4 or Vivado tools 2012.4 with the<br>14.4/2012.4 device pack v1.07||||N/A|N/A|Vivado tools<br>2014.4 v1.14|ISE tools 14.5<br>or Vivado<br>tools 2013.1<br>v1.05|
|XC7A200T|ISE tools 14.4 or Vivado tools 2012.4 with the<br>14.4/2012.4 device pack v1.07||||N/A|N/A|Vivado tools<br>2014.4 v1.14||
|XA7A12T|N/A|Vivado tools<br>2018.1 v1.15|N/A|Vivado tools 2018.1 v1.15||N/A|N/A|N/A|
|XA7A15T|N/A|Vivado tools<br>2014.4 v1.14|N/A|Vivado tools 2014.4 v1.14||N/A|N/A|N/A|
|XA7A25T|N/A|Vivado tools<br>2018.1 v1.15|N/A|Vivado tools 2018.1 v1.15||N/A|N/A|N/A|
|XA7A35T|N/A|Vivado tools<br>2014.1 v1.09|N/A|Vivado tools 2014.1 v1.09||N/A|N/A|N/A|
|XA7A50T|N/A|Vivado tools<br>2014.1 v1.09|N/A|Vivado tools 2014.1 v1.09||N/A|N/A|N/A|
|XA7A75T|N/A|Vivado tools<br>2014.1 v1.09|N/A|Vivado tools 2014.1 v1.09||N/A|N/A|N/A|
|XA7A100T|N/A|ISE tools 14.5<br>or Vivado tools<br>2013.1 v1.05|N/A|ISE tools 14.5<br>or Vivado tools<br>2013.1 v1.05|ISE tools 14.6<br>or Vivado tools<br>2013.2 v1.06|N/A|N/A|N/A|
|XQ7A50T|N/A|Vivado tools<br>2014.2 v1.08|N/A|Vivado tools<br>2014.2 v1.08|N/A|Vivado tools<br>2014.2 v1.08|Vivado tools<br>2015.4 v1.11|N/A|
|XQ7A100T|N/A|ISE tools 14.5<br>or Vivado tools<br>2013.1 v1.04|N/A|ISE tools 14.5<br>or Vivado tools<br>2013.1 v1.04|N/A|ISE tools 14.6<br>or Vivado tools<br>2013.2 v1.05|Vivado tools<br>2015.4 v1.11|N/A|
|XQ7A200T|N/A|ISE tools 14.5<br>or Vivado tools<br>2013.1 v1.04|N/A|ISE tools 14.5<br>or Vivado tools<br>2013.1 v1.04|N/A|ISE tools 14.6<br>or Vivado tools<br>2013.2 v1.05|Vivado tools<br>2015.4 v1.11|N/A|
_Table 14:_ **Artix 7 Device Production Software and Speed Specification Release** _**(Cont’d)**_
## **Selecting the Correct Speed Grade and Voltage in the Vivado Tools**
It is important to select the correct device speed grade and voltage in the Vivado tools for the device that you are selecting.
To select the 1.0V speed specifications in the Vivado tools, select the **Artix 7** , **XA Artix 7** , or **Defense Grade Artix 7Q** sub-family, and then select the part name that is the device name followed by the package name followed by the speed grade. For example, select the **xc7a100tfgg676-3** part name for the XC7A100T device in the FGG676 package and -3 (1.0V) speed grade or select the **xc7a100tfgg676-2L** part name for the XC7A100T device in the FGG676 package and -2LE (1.0V) speed grade.
To select the -1LI (0.95V) speed specifications in the Vivado tools, select the **Artix 7** sub-family and then select the part name that is the device name followed by an “i” followed by the package name followed by the speed grade. For example, select the **xc7a100tifgg676-1L** part name for the XC7A100T device in the FGG676 package and -1LI (0.95V) speed grade. The -1LI (0.95V) speed specifications are not supported in the ISE tools.
To select the -2LE (0.9V) speed specifications in the Vivado tools, select the **Artix 7 Low Voltage** sub-family and then select the part name that is the device name followed by an “l” followed by the package name followed by the speed grade. For example, select the **xc7a100tlfgg676-2L** part name for the XC7A100T device in the FGG676 package and -2LE (0.9V) speed grade.
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**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
A similar part naming convention applies to the speed specifications selection in the ISE tools for supported devices. See Table 14 for the subset of 7 series FPGAs supported in the ISE tools.
## **Performance Characteristics**
This section provides the performance characteristics of some common functions and designs implemented in Artix 7 devices. The numbers reported here are worst-case values; they have all been fully characterized. These values are subject to the same guidelines as the AC Switching Characteristics, page 12.
_Table 15:_ **Networking Applications Interface Performances**
|_Table 15:_ **Networking Applications Interface Performances**|||||||
|---|---|---|---|---|---|---|
|**Description**|**Speed Grade**|||||**Units**|
||**1.0V**|||**0.95V**|**0.9V**||
||**-3**|**-2/-2LE**|**-1**|**-1LI**|**-2LE**||
|SDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 8)|680|680|600|600|600|Mb/s|
|DDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 14)|1250|1250|950|950|950|Mb/s|
|SDR LVDS receiver (SFI-4.1)(1)|680|680|600|600|600|Mb/s|
|DDR LVDS receiver (SPI-4.2)(1)|1250|1250|950|950|950|Mb/s|
## **Notes:**
1. LVDS receivers are typically bounded with certain applications where specific dynamic phase-alignment (DPA) algorithms dominate deterministic performance.
_Table 16:_ **Maximum Physical Interface (PHY) Rate for Memory Interfaces IP available with the Memory Interface**
|**Generator(1)(2)**||||||||
|---|---|---|---|---|---|---|---|
|**Memory Standard**<br>~~ee~~|**Speed Grade**<br>~~ee~~||||||**Units**<br>~~ee~~|
||**1.0V**<br>~~ee~~||||**0.95V**<br>~~ee~~|**0.9V**<br>~~ee~~||
||**-3**<br>~~ee~~|**-2/-2LE**<br>~~ee~~|**-1**<br>~~ee~~|**-1Q/-1M**<br>~~ee~~|**-1LI**<br>~~ee~~|**-2LE**<br>~~ee~~||
|**4:1 Memory Controllers**<br>~~pT~~<br>~~CO~~||||||||
|DDR3<br>~~pT~~<br>~~GG~~|1066(3)<br>~~pT~~<br>~~GG~~|800<br>~~pT~~<br>~~GG~~|800<br>~~pT~~<br>~~GG~~|667<br>~~pT~~<br>~~GG~~|800<br>~~pT~~<br>~~GG~~<br>~~CO~~|800<br>~~pT~~<br>~~GG~~<br>~~CO~~|Mb/s<br>~~pT~~<br>~~GG~~|
|DDR3L<br>~~pe~~|800<br>~~pe~~|800<br>~~pe~~|667<br>~~pe~~|N/A<br>~~pe~~<br>~~GG~~|667<br>~~CO~~<br>~~pe~~<br>~~GG~~|667<br>~~CO~~<br>~~pe~~|Mb/s<br>~~pe~~|
|DDR2<br>~~pe~~<br>~~DG~~|800<br>~~pe~~<br>~~DG~~|800<br>~~pe~~<br>~~DG~~|667<br>~~pe~~<br>~~DG~~|533<br>~~pe~~<br>~~DG~~<br>~~GG~~|667<br>~~pe~~<br>~~DG~~<br>~~GG~~|667<br>~~pe~~<br>~~DG~~|Mb/s<br>~~pe~~<br>~~DG~~|
|**2:1 Memory Controllers**<br>~~DG~~<br>~~GG~~||||||||
|DDR3<br>~~pf~~|800<br>~~pf~~|700<br>~~pf~~|620<br>~~pf~~|620<br>~~pf~~<br>~~GO~~|620<br>~~pf~~<br>~~GO~~|620<br>~~pf~~|Mb/s<br>~~pf~~|
|DDR3L<br>~~pf~~<br>~~GG~~|800<br>~~pf~~<br>~~GG~~|700<br>~~pf~~<br>~~GG~~|620<br>~~pf~~<br>~~GG~~|N/A<br>~~pf~~<br>~~GG~~<br>~~GO~~|620<br>~~pf~~<br>~~GG~~<br>~~GO~~<br>~~CO~~|620<br>~~pf~~<br>~~GG~~<br>~~CO~~|Mb/s<br>~~pf~~<br>~~GG~~|
|DDR2<br>~~GG~~<br>~~GG~~|800<br>~~GG~~<br>~~GG~~|700<br>~~GG~~<br>~~GG~~|620<br>~~GG~~<br>~~GG~~|533<br>~~GG~~<br>~~GO~~<br>~~GG~~|620<br>~~GG~~<br>~~GO~~<br>~~GG~~<br>~~CO~~|620<br>~~GG~~<br>~~GG~~<br>~~CO~~|Mb/s<br>~~GG~~<br>~~GG~~|
|LPDDR2<br>~~po~~|667<br>~~po~~|667<br>~~po~~|533<br>~~po~~|400<br>~~po~~|533<br>~~CO~~<br>~~po~~|533<br>~~CO~~<br>~~po~~|Mb/s<br>~~po~~|
## **Notes:**
1. VREF tracking is required. For more information, see _7 Series FPGAs Memory Interface Solutions User Guide_ (UG586).
2. When using the internal VREF, the maximum data rate is 800 Mb/s (400 MHz).
3. The maximum PHY rate is 800 Mb/s in the CPG238 package.
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~~BMD~~ **Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
## **IOB Pad Input/Output/3-State**
Table 17 summarizes the values of standard-specific data input delay adjustments, output delays terminating at pads (based on standard) and 3-state delays.
- TIOPI is described as the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The delay varies depending on the capability of the SelectIO input buffer.
- TIOOP is described as the delay from the O pin to the IOB pad through the output buffer of an IOB pad. The delay varies depending on the capability of the SelectIO output buffer.
- TIOTP is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is disabled. The delay varies depending on the SelectIO capability of the output buffer. In HR I/O banks, the IN_TERM termination turn-on time is always faster than TIOTP when the INTERMDISABLE pin is used.
_Table 17:_ **IOB High Range (HR) Switching Characteristics**
|**I/O Standard**<br>~~ee=~~<br>~~a~~|**TIOPI**<br>~~ee~~<br>~~ee=~~|**TIOPI**<br>~~ee~~<br>~~ee=~~|**TIOPI**<br>~~ee~~<br>~~ee=~~|**TIOPI**<br>~~ee~~<br>~~ee=~~|**TIOPI**<br>~~ee~~<br>~~ee=~~|**TIOPI**<br>~~ee~~<br>~~ee=~~|**TIOOP**<br>~~ee~~<br>~~=~~|**TIOOP**<br>~~ee~~<br>~~=~~|**TIOOP**<br>~~ee~~<br>~~=~~|**TIOOP**<br>~~ee~~<br>~~=~~|**TIOOP**<br>~~ee~~<br>~~=~~|**TIOOP**<br>~~ee~~<br>~~=~~|**TIOTP**<br>~~ee~~<br>~~=~~|**TIOTP**<br>~~ee~~<br>~~=~~|**TIOTP**<br>~~ee~~<br>~~=~~|**TIOTP**<br>~~ee~~<br>~~=~~|**TIOTP**<br>~~ee~~<br>~~=~~|**TIOTP**<br>~~ee~~<br>~~=~~|**Units**<br>~~=~~|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||**Speed Grade**<br>~~ee=~~||||||**Speed Grade**<br>~~=~~||||||**Speed Grade**<br>~~=~~|||||||
||**1.0V**<br>~~ee=~~<br>~~pTTTEP~~||||**0.95V **<br>~~ee=~~<br>~~EP~~|**0.9V**<br>~~=~~<br>~~EP~~|**1.0V**<br>~~=~~<br>~~ETET~~||||**0.95V **<br>~~=~~<br>~~ET~~|**0.9V**<br>~~=~~|**1.0V**<br>~~=~~||||**0.95V **<br>~~=~~|**0.9V**<br>~~=~~||
||**-3**<br>~~=~~<br>~~pT~~|**-2/**<br>**-2LE**<br>~~=~~<br>~~pTTT~~|**-1**<br>~~=~~<br>~~TT~~|**-1Q/**<br>**-1M**<br>~~=~~<br>~~TTEP~~|**-1LI**<br>~~=~~<br>~~EP~~|**-2LE**<br>~~=~~<br>~~EP~~|**-3**<br>~~=~~<br>~~ET~~|**-2/**<br>**-2LE**<br>~~=~~<br>~~ET~~|**-1**<br>~~=~~<br>~~ETET~~|**-1Q/**<br>**-1M**<br>~~=~~<br>~~ET~~|**-1LI**<br>~~=~~<br>~~ET~~|**-2LE**<br>~~=~~|**-3**<br>~~=~~|**-2/**<br>**-2LE**<br>~~=~~|**-1**<br>~~=~~|**-1Q/**<br>**-1M**<br>~~=~~|**-1LI**<br>~~=~~|**-2LE**<br>~~=~~||
|LVTTL_S4<br>~~a~~<br>~~Se~~|1.26<br>~~pT~~|1.34<br>~~pTTT~~|1.41<br>~~TT~~|1.53<br>~~TTEP~~|1.41<br>~~EP~~|1.58<br>~~EP~~|3.80<br>~~ET~~|3.93<br>~~ET~~|4.18<br>~~ETET~~|4.18<br>~~ET~~|4.18<br>~~ET~~|4.41|3.82|3.96|4.20|4.20|4.20|4.05|ns|
|LVTTL_S8<br>~~a~~<br>~~Se~~<br>~~Se~~|1.26<br>~~pT~~|1.34<br>~~pT TT~~|1.41<br>~~TT~~<br>~~OO~~|1.53<br>~~TT EP~~<br>~~OO~~|1.41<br>~~EP~~<br>~~OO~~|1.58<br>~~EP ~~<br>~~OO~~|3.54<br> ~~ET~~<br>~~OO~~|3.66<br>~~ET~~|3.92<br>~~ET ET~~|3.92<br>~~ET~~|3.92<br>~~ET~~|4.15|3.56|3.69|3.93|3.93|3.93|3.78|ns|
|LVTTL_S12<br>~~Se~~<br>~~Se~~<br>~~Se~~|1.26|1.34|1.41<br>~~OO~~|1.53<br>~~OO~~|1.41<br>~~OO~~|1.58<br>~~OO~~|3.52<br>~~OO~~|3.65|3.90|3.90|3.90|4.13|3.54|3.68|3.91|3.91|3.91|3.77|ns|
|LVTTL_S16<br>~~Se~~<br>~~Se~~<br>~~Se~~|1.26|1.34|1.41<br>~~OO~~|1.53<br>~~OO~~|1.41<br>~~OO~~|1.58<br>~~OO~~|3.07<br>~~OO~~|3.19|3.45|3.45|3.45|3.68|3.09|3.22|3.46|3.46|3.46|3.31|ns|
|LVTTL_S24<br>~~Se~~<br>~~Se~~<br>~~Se~~|1.26|1.34|1.41|1.53|1.41|1.58|3.29|3.41|3.67|3.67|3.67|3.90|3.31|3.44|3.68|3.68|3.68|3.53|ns|
|LVTTL_F4<br>~~Se~~<br>~~Se~~<br>~~Se~~|1.26|1.34|1.41|1.53|1.41|1.58|3.26|3.38|3.64|3.64|3.64|3.86|3.28|3.41|3.65|3.65|3.65|3.50|ns|
|LVTTL_F8<br>~~Se~~<br>~~Se~~<br>~~Se~~|1.26|1.34|1.41|1.53|1.41|1.58|2.74|2.87|3.12|3.12|3.12|3.35|2.76|2.90|3.13|3.13|3.13|2.99|ns|
|LVTTL_F12<br>~~Se~~<br>~~Se~~<br>~~Se~~|1.26|1.34|1.41|1.53|1.41|1.58|2.73|2.85|3.10|3.10|3.10|3.33|2.74|2.88|3.12|3.12|3.12|2.97|ns|
|LVTTL_F16<br>~~Se~~<br>~~Se~~<br>~~Se~~|1.26|1.34|1.41|1.53|1.41|1.58|2.56|2.68|2.93|2.93|2.93|3.16|2.57|2.71|2.95|2.95|2.95|2.80|ns|
|LVTTL_F24<br>~~Se~~<br>~~Se~~<br>~~**S**e~~|1.26|1.34|1.41|1.53|1.41|1.58|2.52|2.65|2.90|3.23|2.90|3.22|2.54|2.68|2.91|3.24|2.91|2.86|ns|
|LVDS_25<br>~~Se~~<br>~~**S**e~~|0.73|0.81|0.88|0.89|0.88|0.90|1.29|1.41|1.67|1.67|1.67|1.86|1.31|1.44|1.68|1.68|1.68|1.50|ns|
|MINI_LVDS_25<br>~~**S**e~~<br>~~Se~~|0.73|0.81|0.88|0.89|0.88|0.90|1.27|1.40|1.65<br>~~G~~|1.65<br>~~G~~|1.65<br>~~G~~|1.88<br>~~G~~|1.29<br>~~G~~|1.43<br>~~G~~|1.66<br>~~G~~|1.66<br>~~G~~|1.66<br>~~G~~|1.52<br>~~G~~|ns<br>~~G~~|
|BLVDS_25<br>~~Se~~<br>~~—~~<br>~~|~~|0.73<br>~~ttt?~~|0.81<br>~~ttt?~~|0.88<br>~~ttt?~~|0.88<br>~~ttt?~~|0.88<br>~~ttt?ety~~|0.90<br>~~ety~~|1.84<br>~~ety~~|1.96<br>~~etytt~~|2.21<br>~~G~~<br>~~tt~~|2.76<br>~~G~~<br>~~ttyt~~|2.21<br>~~G~~<br>~~ytey~~|2.44<br>~~G~~<br>~~ey~~|1.85<br>~~G~~<br>~~ey~~|1.99<br>~~G~~<br>~~ty~~|2.23<br>~~G~~<br>~~ty~~|2.77<br>~~G~~<br>~~ty~~|2.23<br>~~G~~<br>~~ty~~|2.08<br>~~G~~|ns<br>~~G~~|
|RSDS_25 (point<br>to point)<br>~~Se~~<br>~~—~~<br>~~|~~<br>~~Se~~|0.73<br>~~ttt?~~|0.81<br>~~ttt?~~|0.88<br>~~ttt?~~|0.89<br>~~ttt?~~|0.88<br>~~ttt?ety~~|0.90<br>~~ety~~|1.27<br>~~ety~~|1.40<br>~~etytt~~|1.65<br>~~tt~~|1.65<br>~~ttyt~~|1.65<br>~~ytey~~|1.88<br>~~ey~~|1.29<br>~~ey~~|1.43<br>~~ty~~|1.66<br>~~ty~~|1.66<br>~~ty~~|1.66<br>~~ty~~|1.52|ns|
|PPDS_25<br>~~—~~<br>~~| ~~<br>~~Se~~<br>~~Se~~|0.73<br> ~~ttt?~~|0.81<br>~~ttt?~~|0.88<br>~~ttt?~~<br>~~OO~~|0.89<br>~~ttt?~~<br>~~OO~~|0.88<br>~~ttt? ety~~<br>~~OO~~|0.90<br>~~ety~~<br>~~OO~~|1.29<br>~~ety~~<br>~~OO~~|1.41<br>~~ety tt~~|1.67<br>~~tt~~|1.67<br>~~tt yt~~|1.67<br>~~yt ey~~|1.88<br>~~ey~~|1.31<br>~~ey ~~|1.44<br> ~~ty~~|1.68<br>~~ty~~|1.68<br>~~ty~~|1.68<br>~~ty~~|1.52|ns|
|TMDS_33<br>~~Se~~<br>~~Se~~<br>~~Se~~|0.73|0.81|0.88<br>~~OO~~|0.92<br>~~OO~~|0.88<br>~~OO~~|0.90<br>~~OO~~|1.41<br>~~OO~~|1.54|1.79|1.79|1.79|1.99|1.43|1.57|1.80|1.80|1.80|1.63|ns|
|PCI33_3<br>~~Se~~<br>~~Se~~<br>~~Se~~|1.24|1.32|1.39<br>~~OO~~|1.52<br>~~OO~~|1.39<br>~~OO~~|1.57<br>~~OO~~|3.10<br>~~OO~~|3.22|3.48|3.48|3.48|3.71|3.12|3.25|3.49|3.49|3.49|3.34|ns|
|HSUL_12_S<br>~~Se~~<br>~~Se~~<br>~~Se~~|0.67|0.75|0.82|0.88|0.82|0.87|1.81|1.93|2.18|2.18|2.18|2.41|1.82|1.96|2.20|2.20|2.20|2.05|ns|
|HSUL_12_F<br>~~Se~~<br>~~Se~~<br>~~—~~<br>~~|~~|0.67<br>~~ttt?~~|0.75<br>~~ttt?~~|0.82<br>~~ttt?~~|0.88<br>~~ttt?~~|0.82<br>~~ttt?ety~~|0.87<br>~~ety~~|1.29<br>~~ety~~|1.41<br>~~etytt~~|1.67<br>~~tt~~|1.67<br>~~ttyt~~|1.67<br>~~ytey~~|1.90<br>~~ey~~|1.31<br>~~ey~~|1.44<br>~~ty~~|1.68<br>~~ty~~|1.68<br>~~ty~~|1.68<br>~~ty~~|1.53|ns|
|DIFF_HSUL_<br>12_S<br>~~Se~~<br>~~—~~<br>~~|~~<br>~~—~~<br>~~|~~|0.68<br>~~ttt?~~<br>~~ttt?~~|0.76<br>~~ttt?~~<br>~~ttt?~~|0.83<br>~~ttt?~~<br>~~ttt?~~|0.86<br>~~ttt?~~<br>~~ttt?~~|0.83<br>~~ttt?ety~~<br>~~ttt?ety~~|0.88<br>~~ety~~<br>~~ety~~|1.81<br>~~ety~~<br>~~ety~~|1.93<br>~~etytt~~<br>~~etytt~~|2.18<br>~~tt~~<br>~~tt~~|2.18<br>~~ttyt~~<br>~~ttyt~~|2.18<br>~~ytey~~<br>~~ytey~~|2.21<br>~~ey~~<br>~~ey~~|1.82<br>~~ey~~<br>~~ey~~|1.96<br>~~ty~~<br>~~ty~~|2.20<br>~~ty~~<br>~~ty~~|2.20<br>~~ty~~<br>~~ty~~|2.20<br>~~ty~~<br>~~ty~~|1.84|ns|
|DIFF_HSUL_<br>12_F<br>~~—~~<br>~~| ~~<br>~~—~~<br>~~|~~<br>~~—~~<br>~~|~~|0.68<br> ~~ttt?~~<br>~~ttt?~~<br>~~ttt?~~|0.76<br>~~ttt?~~<br>~~ttt?~~<br>~~ttt?~~|0.83<br>~~ttt?~~<br>~~ttt?~~<br>~~ttt?~~|0.86<br>~~ttt?~~<br>~~ttt?~~<br>~~ttt?~~|0.83<br>~~ttt? ety~~<br>~~ttt?ety~~<br>~~ttt?ety~~|0.88<br>~~ety~~<br>~~ety~~<br>~~ety~~|1.29<br>~~ety~~<br>~~ety~~<br>~~ety~~|1.41<br>~~ety tt~~<br>~~etytt~~<br>~~etytt~~|1.67<br>~~tt~~<br>~~tt~~<br>~~tt~~|1.67<br>~~tt yt~~<br>~~ttyt~~<br>~~ttyt~~|1.67<br>~~yt ey~~<br>~~ytey~~<br>~~ytey~~|1.79<br>~~ey~~<br>~~ey~~<br>~~ey~~|1.31<br>~~ey ~~<br>~~ey~~<br>~~ey~~|1.44<br> ~~ty~~<br>~~ty~~<br>~~ty~~|1.68<br>~~ty~~<br>~~ty~~<br>~~ty~~|1.68<br>~~ty~~<br>~~ty~~<br>~~ty~~|1.68<br>~~ty~~<br>~~ty~~<br>~~ty~~|1.42|ns|
|MOBILE_<br>DDR_S<br>~~—~~<br>~~| ~~<br>~~—~~<br>~~|~~<br>~~—~~<br>~~|~~|0.76<br> ~~ttt?~~<br>~~ttt?~~<br>~~ttt?~~|0.84<br>~~ttt?~~<br>~~ttt?~~<br>~~ttt?~~|0.91<br>~~ttt?~~<br>~~ttt?~~<br>~~ttt?~~|0.91<br>~~ttt?~~<br>~~ttt?~~<br>~~ttt?~~|0.91<br>~~ttt? ety~~<br>~~ttt?ety~~<br>~~ttt?ety~~|0.96<br>~~ety~~<br>~~ety~~<br>~~ety~~|1.68<br>~~ety~~<br>~~ety~~<br>~~ety~~|1.80<br>~~ety tt~~<br>~~etytt~~<br>~~etytt~~|2.06<br>~~tt~~<br>~~tt~~<br>~~tt~~|2.06<br>~~tt yt~~<br>~~ttyt~~<br>~~ttyt~~|2.06<br>~~yt ey~~<br>~~ytey~~<br>~~ytey~~|2.24<br>~~ey~~<br>~~ey~~<br>~~ey~~|1.70<br>~~ey ~~<br>~~ey~~<br>~~ey~~|1.83<br> ~~ty~~<br>~~ty~~<br>~~ty~~|2.07<br>~~ty~~<br>~~ty~~<br>~~ty~~|2.07<br>~~ty~~<br>~~ty~~<br>~~ty~~|2.07<br>~~ty~~<br>~~ty~~<br>~~ty~~|1.88|ns|
|MOBILE_<br>DDR_F<br>~~—~~<br>~~| ~~<br>~~—~~<br>~~|~~<br>~~—~~<br>~~|~~|0.76<br> ~~ttt?~~<br>~~ttt?~~<br>~~ttt?~~|0.84<br>~~ttt?~~<br>~~ttt?~~<br>~~ttt?~~|0.91<br>~~ttt?~~<br>~~ttt?~~<br>~~ttt?~~|0.91<br>~~ttt?~~<br>~~ttt?~~<br>~~ttt?~~|0.91<br>~~ttt? ety~~<br>~~ttt?ety~~<br>~~ttt?ety~~|0.96<br>~~ety~~<br>~~ety~~<br>~~ety~~|1.38<br>~~ety~~<br>~~ety~~<br>~~ety~~|1.51<br>~~ety tt~~<br>~~etytt~~<br>~~etytt~~|1.76<br>~~tt~~<br>~~tt~~<br>~~tt~~|1.76<br>~~tt yt~~<br>~~ttyt~~<br>~~ttyt~~|1.76<br>~~yt ey~~<br>~~ytey~~<br>~~ytey~~|1.97<br>~~ey~~<br>~~ey~~<br>~~ey~~|1.40<br>~~ey ~~<br>~~ey~~<br>~~ey~~|1.54<br> ~~ty~~<br>~~ty~~<br>~~ty~~|1.77<br>~~ty~~<br>~~ty~~<br>~~ty~~|1.77<br>~~ty~~<br>~~ty~~<br>~~ty~~|1.77<br>~~ty~~<br>~~ty~~<br>~~ty~~|1.61|ns|
|DIFF_MOBILE_<br>DDR_S<br>~~—~~<br>~~| ~~<br>~~—~~<br>~~|~~<br>~~—~~<br>~~tL~~|0.70<br> ~~ttt?~~<br>~~ttt?~~<br>~~tL ttt?~~|0.78<br>~~ttt?~~<br>~~ttt?~~<br>~~ttt?~~|0.85<br>~~ttt?~~<br>~~ttt?~~<br>~~ttt?~~|0.85<br>~~ttt?~~<br>~~ttt?~~<br>~~ttt?~~|0.85<br>~~ttt? ety~~<br>~~ttt?ety~~<br>~~ttt?ete~~|0.87<br>~~ety~~<br>~~ety~~<br>~~ete~~|1.70<br>~~ety~~<br>~~ety~~<br>~~ete~~|1.82<br>~~ety tt~~<br>~~etytt~~<br>~~etett~~|2.07<br>~~tt~~<br>~~tt~~<br>~~tt~~|2.07<br>~~tt yt~~<br>~~ttyt~~<br>~~ttty~~|2.07<br>~~yt ey~~<br>~~ytey~~<br>~~tyey~~|2.24<br>~~ey~~<br>~~ey~~<br>~~ey~~|1.71<br>~~ey ~~<br>~~ey~~<br>~~eyte~~|1.85<br> ~~ty~~<br>~~ty~~<br>~~te et~~|2.09<br>~~ty~~<br>~~ty~~<br>~~et~~|2.09<br>~~ty~~<br>~~ty~~<br>~~et~~|2.09<br>~~ty~~<br>~~ty~~<br>~~yt~~|1.88<br>~~yt~~|ns|
|DIFF_MOBILE_<br>DDR_F<br>~~—~~<br>~~| ~~<br>~~—~~<br>~~tL~~|0.70<br> ~~ttt?~~<br>~~tL ttt?~~|0.78<br>~~ttt?~~<br>~~ttt?~~|0.85<br>~~ttt?~~<br>~~ttt?~~|0.85<br>~~ttt?~~<br>~~ttt?~~|0.85<br>~~ttt? ety~~<br>~~ttt?ete~~|0.87<br>~~ety~~<br>~~ete~~|1.45<br>~~ety~~<br>~~ete~~|1.57<br>~~ety tt~~<br>~~etett~~|1.82<br>~~tt~~<br>~~tt~~|1.82<br>~~tt yt~~<br>~~ttty~~|1.82<br>~~yt ey~~<br>~~tyey~~|2.00<br>~~ey~~<br>~~ey~~|1.46<br>~~ey ~~<br>~~eyte~~|1.60<br> ~~ty~~<br>~~te et~~|1.84<br>~~ty~~<br>~~et~~|1.84<br>~~ty~~<br>~~et~~|1.84<br>~~ty~~<br>~~yt~~|1.64<br>~~yt~~|ns|
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DS181 (v1.27.1) July 3, 2024 **Product Specification**
16
**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 17:_ **IOB High Range (HR) Switching Characteristics** _**(Cont’d)**_
|**I/O Standard**<br> <br>~~ee=~~<br>~~a~~|**TIOPI**<br> ~~ee~~<br>~~ee=~~|**TIOPI**<br> ~~ee~~<br>~~ee=~~|**TIOPI**<br> ~~ee~~<br>~~ee=~~|**TIOPI**<br> ~~ee~~<br>~~ee=~~|**TIOPI**<br> ~~ee~~<br>~~ee=~~|**TIOPI**<br> ~~ee~~<br>~~ee=~~|**TIOOP**<br>~~ee~~<br>~~=~~|**TIOOP**<br>~~ee~~<br>~~=~~|**TIOOP**<br>~~ee~~<br>~~=~~|**TIOOP**<br>~~ee~~<br>~~=~~|**TIOOP**<br>~~ee~~<br>~~=~~|**TIOOP**<br>~~ee~~<br>~~=~~|**TIOTP**<br>~~ee~~<br>~~=~~|**TIOTP**<br>~~ee~~<br>~~=~~|**TIOTP**<br>~~ee~~<br>~~=~~|**TIOTP**<br>~~ee~~<br>~~=~~|**TIOTP**<br>~~ee~~<br>~~=~~|**TIOTP**<br>~~ee~~<br>~~=~~|**Units**<br>~~=~~|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||**Speed Grade**<br>~~ee=~~||||||**Speed Grade**<br>~~=~~||||||**Speed Grade**<br>~~=~~|||||||
||**1.0V**<br>~~ee=~~<br>~~pTTTEP~~||||**0.95V **<br>~~ee=~~<br>~~EP~~|**0.9V**<br>~~=~~<br>~~EP~~|**1.0V**<br>~~=~~<br>~~ETTT~~||||**0.95V **<br>~~=~~<br>~~TT~~|**0.9V**<br>~~=~~|**1.0V**<br>~~=~~||||**0.95V **<br>~~=~~|**0.9V**<br>~~=~~||
||**-3**<br>~~=~~<br>~~pT~~|**-2/**<br>**-2LE**<br>~~=~~<br>~~pTTT~~|**-1**<br>~~=~~<br>~~TT~~|**-1Q/**<br>**-1M**<br>~~=~~<br>~~TTEP~~|**-1LI**<br>~~=~~<br>~~EP~~|**-2LE**<br>~~=~~<br>~~EP~~|**-3**<br>~~=~~<br>~~ET~~|**-2/**<br>**-2LE**<br>~~=~~<br>~~ET~~|**-1**<br>~~=~~<br>~~ETTT~~|**-1Q/**<br>**-1M**<br>~~=~~<br>~~TT~~|**-1LI**<br>~~=~~<br>~~TT~~|**-2LE**<br>~~=~~|**-3**<br>~~=~~|**-2/**<br>**-2LE**<br>~~=~~|**-1**<br>~~=~~|**-1Q/**<br>**-1M**<br>~~=~~|**-1LI**<br>~~=~~|**-2LE**<br>~~=~~||
|HSTL_I_S<br>~~a~~|0.67<br>~~pT~~|0.75<br>~~pTTT~~|0.82<br>~~TT~~|0.86<br>~~TTEP~~|0.82<br>~~EP~~|0.87<br>~~EP~~|1.62<br>~~ET~~|1.74<br>~~ET~~|1.99<br>~~ETTT~~|1.99<br>~~TT~~|1.99<br>~~TT~~|2.19|1.63|1.77|2.01|2.01|2.01|1.83|ns|
|HSTL_II_S<br>~~a~~<br>~~Se~~<br>~~Se~~|0.65<br>~~pT~~<br>~~Se~~|0.73<br>~~pT TT~~|0.80<br>~~TT~~<br>~~OG~~|0.86<br>~~TT EP~~<br>~~OG~~|0.80<br>~~EP~~<br>~~OG~~|0.85<br>~~EP ~~<br>~~OG~~|1.41<br> ~~ET~~|1.54<br>~~ET~~|1.79<br>~~ET TT~~|1.79<br>~~TT~~|1.79<br>~~TT~~|1.99|1.43|1.57|1.80|1.81|1.80|1.63|ns|
|HSTL_I_18_S<br>~~Se~~<br>~~Se~~<br>~~**S**e~~|0.67<br>~~Se~~|0.75|0.82<br>~~OG~~|0.88<br>~~OG~~|0.82<br>~~OG~~|0.87<br>~~OG~~|1.29|1.41|1.67|1.67|1.67|1.86|1.31|1.44|1.68|1.68|1.68|1.50|ns|
|HSTL_II_18_S<br>~~Se~~<br>~~**S**e~~|0.66|0.75|0.81|0.88|0.81|0.87|1.41|1.54|1.79|1.79|1.79|1.97|1.43|1.57|1.80|1.80|1.80|1.61|ns|
|DIFF_HSTL_I_S<br>~~**S**e~~<br>~~—~~<br>~~ttt~~|0.68<br>~~ttt~~|0.76<br>~~ttt~~|0.83<br>~~ttttT?~~|0.86<br>~~tT?~~|0.83<br>~~tT?ety~~|0.85<br>~~ety~~|1.59<br>~~ety~~|1.71<br>~~etytt~~|1.96<br>~~G~~<br>~~tt~~|1.96<br>~~G~~<br>~~ttyt~~|1.96<br>~~G~~<br>~~yttT~~|2.13<br>~~G~~<br>~~tT~~|1.60<br>~~G~~|1.74<br>~~G~~<br>~~ty~~|1.98<br>~~G~~<br>~~ty~~|1.98<br>~~G~~<br>~~ty~~|1.98<br>~~G~~<br>~~ty~~|1.77<br>~~G~~<br>~~ty~~|ns<br>~~G~~|
|DIFF_HSTL_<br>II_S<br>~~—~~<br>~~ttt~~<br>~~—~~<br>~~ttt~~|0.68<br>~~ttt~~<br>~~ttt~~|0.76<br>~~ttt~~<br>~~ttt~~|0.83<br>~~ttttT?~~<br>~~ttttT?~~|0.86<br>~~tT?~~<br>~~tT?~~|0.83<br>~~tT?ety~~<br>~~tT?ety~~|0.85<br>~~ety~~<br>~~ety~~|1.51<br>~~ety~~<br>~~ety~~|1.63<br>~~etytt~~<br>~~etytt~~|1.88<br>~~G~~<br>~~tt~~<br>~~tt~~|1.88<br>~~G~~<br>~~ttyt~~<br>~~ttyt~~|1.88<br>~~G~~<br>~~yttT~~<br>~~yttT~~|2.07<br>~~G~~<br>~~tT~~<br>~~tT~~|1.52<br>~~G~~|1.66<br>~~G~~<br>~~ty~~<br>~~ty~~|1.90<br>~~G~~<br>~~ty~~<br>~~ty~~|1.90<br>~~G~~<br>~~ty~~<br>~~ty~~|1.90<br>~~G~~<br>~~ty~~<br>~~ty~~|1.70<br>~~G~~<br>~~ty~~<br>~~ty~~|ns<br>~~G~~|
|DIFF_HSTL_<br>I_18_S<br>~~—~~<br>~~ttt~~<br>~~—~~<br>~~ttt~~<br>~~—~~<br>~~ttt~~|0.71<br>~~ttt~~<br>~~ttt~~<br>~~ttt~~|0.79<br>~~ttt~~<br>~~ttt~~<br>~~ttt~~|0.86<br>~~ttt tT?~~<br>~~ttttT?~~<br>~~ttttT?~~|0.86<br>~~tT?~~<br>~~tT?~~<br>~~tT?~~|0.86<br>~~tT? ety~~<br>~~tT?ety~~<br>~~tT?ety~~|0.87<br>~~ety~~<br>~~ety~~<br>~~ety~~|1.38<br>~~ety~~<br>~~ety~~<br>~~ety~~|1.51<br>~~ety tt~~<br>~~etytt~~<br>~~etytt~~|1.76<br>~~tt~~<br>~~tt~~<br>~~tt~~|1.76<br>~~tt yt~~<br>~~ttyt~~<br>~~ttyt~~|1.76<br>~~yt tT~~<br>~~yttT~~<br>~~yttT~~|1.96<br>~~tT~~<br>~~tT~~<br>~~tT~~|1.40|1.54<br>~~ty~~<br>~~ty~~<br>~~ty~~|1.77<br>~~ty~~<br>~~ty~~<br>~~ty~~|1.77<br>~~ty~~<br>~~ty~~<br>~~ty~~|1.77<br>~~ty~~<br>~~ty~~<br>~~ty~~|1.59<br>~~ty~~<br>~~ty~~<br>~~ty~~|ns|
|DIFF_HSTL_<br>II_18_S<br>~~—~~<br>~~ttt~~<br>~~—~~<br>~~ttt~~<br>~~Se~~|0.70<br>~~ttt~~<br>~~ttt~~|0.78<br>~~ttt~~<br>~~ttt~~|0.85<br>~~ttt tT?~~<br>~~ttttT?~~|0.88<br>~~tT?~~<br>~~tT?~~|0.85<br>~~tT? ety~~<br>~~tT?ety~~|0.87<br>~~ety~~<br>~~ety~~|1.46<br>~~ety~~<br>~~ety~~|1.58<br>~~ety tt~~<br>~~etytt~~|1.84<br>~~tt~~<br>~~tt~~|1.84<br>~~tt yt~~<br>~~ttyt~~|1.84<br>~~yt tT~~<br>~~yttT~~|2.00<br>~~tT~~<br>~~tT~~|1.48|1.61<br>~~ty~~<br>~~ty~~|1.85<br>~~ty~~<br>~~ty~~|1.85<br>~~ty~~<br>~~ty~~|1.85<br>~~ty~~<br>~~ty~~|1.64<br>~~ty~~<br>~~ty~~|ns|
|HSTL_I_F<br>~~—~~<br>~~ttt~~<br>~~Se~~<br>~~Se~~|0.67<br>~~ttt~~|0.75<br>~~ttt~~|0.82<br>~~ttt tT?~~|0.86<br>~~tT?~~|0.82<br>~~tT? ety~~|0.87<br>~~ety~~|1.10<br>~~ety~~|1.22<br>~~ety tt~~|1.48<br>~~tt~~|1.49<br>~~tt yt~~|1.48<br>~~yt tT~~|1.69<br>~~tT~~|1.12|1.25<br>~~ty~~|1.49<br>~~ty~~|1.51<br>~~ty~~|1.49<br>~~ty~~|1.33<br>~~ty~~|ns|
|HSTL_II_F<br>~~Se~~<br>~~Se~~<br>~~Se~~|0.65|0.73|0.80<br>~~OO~~|0.86<br>~~OO~~|0.80<br>~~OO~~|0.85<br>~~OO~~|1.12<br>~~OO~~|1.24|1.49|1.49|1.49|1.71|1.13|1.27|1.51|1.51|1.51|1.34|ns|
|HSTL_I_18_F<br>~~Se~~<br>~~Se~~<br>~~Se~~|0.67|0.75|0.82<br>~~OO~~|0.88<br>~~OO~~|0.82<br>~~OO~~|0.87<br>~~OO~~|1.13<br>~~OO~~|1.26|1.51|1.54|1.51|1.72|1.15|1.29|1.52|1.56|1.52|1.36|ns|
|HSTL_II_18_F<br>~~Se~~<br>~~Se~~<br>~~Se~~|0.66|0.75|0.81<br>~~OO~~|0.88<br>~~OO~~|0.81<br>~~OO~~|0.87<br>~~OO~~|1.12<br>~~OO~~|1.24|1.49|1.51|1.49|1.71|1.13|1.27|1.51|1.52|1.51|1.34|ns|
|DIFF_HSTL_I_F<br>~~Se~~<br>~~Se~~<br>~~—tt~~|0.68<br>~~tt~~|0.76<br>~~tttty~~|0.83<br>~~tty~~|0.86<br>~~tty~~|0.83<br>~~ttyeee~~|0.85<br>~~eee~~|1.18<br>~~eee~~|1.30<br>~~eeety~~|1.56<br>~~ty~~|1.56<br>~~tyyt~~|1.56<br>~~ytey~~|1.77<br>~~ey~~|1.20<br>~~ey~~|1.33<br>~~ey~~|1.57<br>~~ey~~|1.57<br>~~eyyy~~|1.57<br>~~yy~~|1.41|ns|
|DIFF_HSTL_<br>II_F<br>~~Se~~<br>~~—tt~~<br>~~—tt~~|0.68<br>~~tt~~<br>~~tt~~|0.76<br>~~tttty~~<br>~~tttty~~|0.83<br>~~tty~~<br>~~tty~~|0.86<br>~~tty~~<br>~~tty~~|0.83<br>~~ttyeee~~<br>~~ttyeee~~|0.85<br>~~eee~~<br>~~eee~~|1.21<br>~~eee~~<br>~~eee~~|1.33<br>~~eeety~~<br>~~eeety~~|1.59<br>~~ty~~<br>~~ty~~|1.59<br>~~tyyt~~<br>~~tyyt~~|1.59<br>~~ytey~~<br>~~ytey~~|1.77<br>~~ey~~<br>~~ey~~|1.23<br>~~ey~~<br>~~ey~~|1.36<br>~~ey~~<br>~~ey~~|1.60<br>~~ey~~<br>~~ey~~|1.60<br>~~eyyy~~<br>~~eyyy~~|1.60<br>~~yy~~<br>~~yy~~|1.41|ns|
|DIFF_HSTL_<br>I_18_F<br>~~— tt~~<br>~~—tt~~<br>~~—tt~~|0.71<br>~~tt~~<br>~~tt~~<br>~~tt~~|0.79<br>~~tt tty~~<br>~~tttty~~<br>~~tt tty~~|0.86<br>~~tty~~<br>~~tty~~<br>~~tty~~|0.86<br>~~tty~~<br>~~tty~~<br>~~tty~~|0.86<br>~~tty eee~~<br>~~ttyeee~~<br>~~ttyeee~~|0.87<br>~~eee~~<br>~~eee~~<br>~~eee~~|1.21<br>~~eee~~<br>~~eee~~<br>~~eee~~|1.33<br>~~eee ty~~<br>~~eeety~~<br>~~eeety~~|1.59<br>~~ty~~<br>~~ty~~<br>~~ty~~|1.59<br>~~ty yt~~<br>~~tyyt~~<br>~~tyyt~~|1.59<br>~~yt ey~~<br>~~ytey~~<br>~~ytey~~|1.77<br>~~ey~~<br>~~ey~~<br>~~ey~~|1.23<br>~~ey~~<br>~~ey~~<br>~~ey~~|1.36<br>~~ey~~<br>~~ey~~<br>~~ey~~|1.60<br>~~ey~~<br>~~ey~~<br>~~ey~~|1.60<br>~~ey yy~~<br>~~eyyy~~<br>~~eyyy~~|1.60<br>~~yy~~<br>~~yy~~<br>~~yy~~|1.41|ns|
|DIFF_HSTL_<br>II_18_F<br>~~— tt~~<br>~~—tt~~<br>~~Se~~|0.70<br>~~tt~~<br>~~tt~~|0.78<br>~~tt tty~~<br>~~tt tty~~|0.85<br>~~tty~~<br>~~tty~~|0.88<br>~~tty~~<br>~~tty~~|0.85<br>~~tty eee~~<br>~~ttyeee~~|0.87<br>~~eee~~<br>~~eee~~|1.21<br>~~eee~~<br>~~eee~~|1.33<br>~~eee ty~~<br>~~eeety~~|1.59<br>~~ty~~<br>~~ty~~|1.59<br>~~ty yt~~<br>~~tyyt~~|1.59<br>~~yt ey~~<br>~~ytey~~|1.77<br>~~ey~~<br>~~ey~~|1.23<br>~~ey~~<br>~~ey~~|1.36<br>~~ey~~<br>~~ey~~|1.60<br>~~ey~~<br>~~ey~~|1.60<br>~~ey yy~~<br>~~eyyy~~|1.60<br>~~yy~~<br>~~yy~~|1.41|ns|
|LVCMOS33_S4<br>~~— tt~~<br>~~Se~~<br>~~Se~~|1.26<br>~~tt~~|1.34<br>~~tt tty~~|1.41<br>~~tty~~|1.52<br>~~tty~~|1.41<br>~~tty eee~~|1.62<br>~~eee~~|3.80<br>~~eee~~|3.93<br>~~eee ty~~|4.18<br>~~ty~~|4.18<br>~~ty yt~~|4.18<br>~~yt ey~~|4.41<br>~~ey~~|3.82<br>~~ey~~|3.96<br>~~ey~~|4.20<br>~~ey~~|4.20<br>~~ey yy~~|4.20<br>~~yy~~|4.05|ns|
|LVCMOS33_S8<br>~~Se~~<br>~~Se~~<br>~~Se~~|1.26|1.34|1.41|1.52|1.41|1.62|3.52|3.65|3.90|3.90|3.90|4.13|3.54|3.68|3.91|3.91|3.91|3.77|ns|
|LVCMOS33_S12 <br>~~Se~~<br>~~Se~~<br>~~Se~~|1.26<br>~~A~~|1.34|1.41|1.52|1.41|1.62|3.09|3.21|3.46|3.46|3.46|3.69|3.10|3.24|3.48|3.48|3.48|3.33|ns|
|LVCMOS33_S16 <br>~~Se~~<br>~~Se~~<br>~~Se~~|1.26<br>~~A~~<br>|1.34|1.41|1.52|1.41|1.62|3.40|3.52|3.77|3.78|3.77|4.00|3.42|3.55|3.79|3.79|3.79|3.64|ns|
|LVCMOS33_F4<br>~~Se~~<br>~~Se~~~~**S**e~~|1.26<br>~~A~~<br>~~e~~|1.34|1.41|1.52|1.41|1.62|3.26|3.38|3.64|3.64|3.64|3.86|3.28|3.41|3.65|3.65|3.65|3.50|ns|
|LVCMOS33_F8<br>~~Se~~~~**S**e~~|1.26<br>~~e~~|1.34|1.41|1.52|1.41|1.62|2.74|2.87|3.12|3.12|3.12|3.35|2.76|2.90|3.13|3.13|3.13|2.99|ns|
|LVCMOS33_F12 <br>~~**S**e~~<br>~~Se~~|1.26<br>~~e~~|1.34|1.41|1.52|1.41|1.62|2.56|2.68|2.93<br>~~O~~|2.93<br>~~O~~|2.93<br>~~O~~|3.16<br>~~O~~|2.57<br>~~O~~|2.71<br>~~O~~|2.95<br>~~O~~|2.95<br>~~O~~|2.95<br>~~O~~|2.80<br>~~O~~|ns<br>~~O~~|
|LVCMOS33_F16 <br>~~Se~~<br>~~Se~~|1.26|1.34|1.41|1.52|1.41|1.62|2.56|2.68|2.93<br>~~O~~|3.06<br>~~O~~|2.93<br>~~O~~|3.16<br>~~O~~|2.57<br>~~O~~|2.71<br>~~O~~|2.95<br>~~O~~|3.07<br>~~O~~|2.95<br>~~O~~|2.80<br>~~O~~|ns<br>~~O~~|
|LVCMOS25_S4<br>~~Se~~<br>~~Se~~<br>~~Se~~|1.12|1.20|1.27<br>~~OO~~|1.38<br>~~OO~~|1.27<br>~~OO~~|1.43<br>~~OO~~|3.13<br>~~OO~~|3.26|3.51|3.51|3.51|3.72|3.15|3.29|3.52|3.52|3.52|3.36|ns|
|LVCMOS25_S8<br>~~Se~~<br>~~Se~~<br>~~Se~~|1.12|1.20|1.27<br>~~OO~~|1.38<br>~~OO~~|1.27<br>~~OO~~|1.43<br>~~OO~~|2.88<br>~~OO~~|3.01|3.26|3.26|3.26|3.49|2.90|3.04|3.27|3.27|3.27|3.13|ns|
|LVCMOS25_S12 <br>~~Se~~<br>~~Se~~<br>~~Se~~|1.12|1.20|1.27<br>~~OO~~|1.38<br>~~OO~~|1.27<br>~~OO~~|1.43<br>~~OO~~|2.48<br>~~OO~~|2.60|2.85|2.85|2.85|3.08|2.49|2.63|2.87|2.87|2.87|2.72|ns|
|LVCMOS25_S16 <br>~~Se~~<br>~~Se~~<br>~~Se~~|1.12|1.20|1.27|1.38|1.27|1.43|2.82|2.94|3.20|3.20|3.20|3.43|2.84|2.97|3.21|3.21|3.21|3.06|ns|
|LVCMOS25_F4<br>~~Se~~<br>~~Se~~<br>~~Se~~|1.12|1.20|1.27|1.38|1.27|1.43|2.74|2.87|3.12|3.12|3.12|3.35|2.76|2.90|3.13|3.13|3.13|2.99|ns|
|LVCMOS25_F8<br>~~Se~~<br>~~Se~~<br>~~Se~~|1.12|1.20|1.27<br>~~OO~~|1.38<br>~~OO~~|1.27<br>~~OO~~|1.43<br>~~OO~~|2.18<br>~~OO~~|2.30|2.56|2.56|2.56|2.79|2.20|2.33|2.57|2.57|2.57|2.42|ns|
|LVCMOS25_F12 <br>~~Se~~<br>~~Se~~<br>~~Se~~|1.12|1.20|1.27<br>~~OO~~|1.38<br>~~OO~~|1.27<br>~~OO~~|1.43<br>~~OO~~|2.16<br>~~OO~~|2.29|2.54|2.54|2.54|2.77|2.18|2.32|2.55|2.56|2.55|2.41|ns|
|LVCMOS25_F16 <br>~~Se~~<br>~~Se~~<br>~~Se~~|1.12|1.20|1.27<br>~~OO~~|1.38<br>~~OO~~|1.27<br>~~OO~~|1.43<br>~~OO~~|2.01<br>~~OO~~|2.13|2.39|2.63|2.39|2.61|2.03|2.16|2.40|2.65|2.40|2.25|ns|
|LVCMOS18_S4<br>~~Se~~<br>~~Se~~<br>~~Se~~|0.74|0.83|0.89|0.97|0.89|0.94|1.62|1.74|1.99|1.99|1.99|2.19|1.63|1.77|2.01|2.01|2.01|1.83|ns|
|LVCMOS18_S8<br>~~Se~~<br>~~Se~~|0.74|0.83|0.89|0.97|0.89|0.94|2.18|2.30|2.56|2.56|2.56|2.79|2.20|2.33|2.57|2.57|2.57|2.42|ns|
|LVCMOS18_S12 <br>~~Se~~<br>~~a~~|0.74|0.83|0.89|0.97|0.89|0.94|2.18|2.30|2.56|2.56|2.56|2.79|2.20|2.33|2.57|2.57|2.57|2.42|ns|
DS181 (v1.27.1) July 3, 2024 **Product Specification**
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17
**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 17:_ **IOB High Range (HR) Switching Characteristics** _**(Cont’d)**_
|**I/O Standard**<br> <br>~~ee=~~<br>~~a~~|**TIOPI**<br> ~~ee~~<br>~~ee=~~|**TIOPI**<br> ~~ee~~<br>~~ee=~~|**TIOPI**<br> ~~ee~~<br>~~ee=~~|**TIOPI**<br> ~~ee~~<br>~~ee=~~|**TIOPI**<br> ~~ee~~<br>~~ee=~~|**TIOPI**<br> ~~ee~~<br>~~ee=~~|**TIOOP**<br>~~ee~~<br>~~=~~|**TIOOP**<br>~~ee~~<br>~~=~~|**TIOOP**<br>~~ee~~<br>~~=~~|**TIOOP**<br>~~ee~~<br>~~=~~|**TIOOP**<br>~~ee~~<br>~~=~~|**TIOOP**<br>~~ee~~<br>~~=~~|**TIOTP**<br>~~ee~~<br>~~=~~|**TIOTP**<br>~~ee~~<br>~~=~~|**TIOTP**<br>~~ee~~<br>~~=~~|**TIOTP**<br>~~ee~~<br>~~=~~|**TIOTP**<br>~~ee~~<br>~~=~~|**TIOTP**<br>~~ee~~<br>~~=~~|**Units**<br>~~=~~|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||**Speed Grade**<br>~~ee=~~||||||**Speed Grade**<br>~~=~~||||||**Speed Grade**<br>~~=~~|||||||
||**1.0V**<br>~~ee=~~<br>~~pTTTEP~~||||**0.95V **<br>~~ee=~~<br>~~EP~~|**0.9V**<br>~~=~~<br>~~EP~~|**1.0V**<br>~~=~~<br>~~ETTT~~||||**0.95V **<br>~~=~~<br>~~TT~~|**0.9V**<br>~~=~~|**1.0V**<br>~~=~~||||**0.95V **<br>~~=~~|**0.9V**<br>~~=~~||
||**-3**<br>~~=~~<br>~~pT~~|**-2/**<br>**-2LE**<br>~~=~~<br>~~pTTT~~|**-1**<br>~~=~~<br>~~TT~~|**-1Q/**<br>**-1M**<br>~~=~~<br>~~TTEP~~|**-1LI**<br>~~=~~<br>~~EP~~|**-2LE**<br>~~=~~<br>~~EP~~|**-3**<br>~~=~~<br>~~ET~~|**-2/**<br>**-2LE**<br>~~=~~<br>~~ET~~|**-1**<br>~~=~~<br>~~ETTT~~|**-1Q/**<br>**-1M**<br>~~=~~<br>~~TT~~|**-1LI**<br>~~=~~<br>~~TT~~|**-2LE**<br>~~=~~|**-3**<br>~~=~~|**-2/**<br>**-2LE**<br>~~=~~|**-1**<br>~~=~~|**-1Q/**<br>**-1M**<br>~~=~~|**-1LI**<br>~~=~~|**-2LE**<br>~~=~~||
|LVCMOS18_S16 <br>~~a~~|0.74<br>~~pT~~|0.83<br>~~pTTT~~|0.89<br>~~TT~~|0.97<br>~~TTEP~~|0.89<br>~~EP~~|0.94<br>~~EP~~|1.52<br>~~ET~~|1.65<br>~~ET~~|1.90<br>~~ETTT~~|1.90<br>~~TT~~|1.90<br>~~TT~~|2.13|1.54|1.68|1.91|1.91|1.91|1.77|ns|
|LVCMOS18_S24 <br>~~a~~<br>~~Se~~<br>~~Se~~|0.74<br>~~pT~~<br>~~Se~~|0.83<br>~~pT TT~~|0.89<br>~~TT~~<br>~~OG~~|0.97<br>~~TT EP~~<br>~~OG~~|0.89<br>~~EP~~<br>~~OG~~|0.94<br>~~EP ~~<br>~~OG~~|1.60<br> ~~ET~~|1.72<br>~~ET~~|1.98<br>~~ET TT~~|2.40<br>~~TT~~|1.98<br>~~TT~~|2.21|1.62|1.75|1.99|2.41|1.99|1.84|ns|
|LVCMOS18_F4<br>~~Se~~<br>~~Se~~<br>~~**S**e~~|0.74<br>~~Se~~|0.83|0.89<br>~~OG~~|0.97<br>~~OG~~|0.89<br>~~OG~~|0.94<br>~~OG~~|1.45|1.57|1.82|1.82|1.82|2.05|1.46|1.60|1.84|1.84|1.84|1.69|ns|
|LVCMOS18_F8<br>~~Se~~<br>~~**S**e~~|0.74|0.83|0.89|0.97|0.89|0.94|1.68|1.80|2.06|2.06|2.06|2.29|1.70|1.83|2.07|2.07|2.07|1.92|ns|
|LVCMOS18_F12 <br>~~**S**e~~<br>~~Se~~|0.74|0.83|0.89|0.97|0.89|0.94|1.68|1.80|2.06<br>~~G~~|2.06<br>~~G~~|2.06<br>~~G~~|2.29<br>~~G~~|1.70<br>~~G~~|1.83<br>~~G~~|2.07<br>~~G~~|2.07<br>~~G~~|2.07<br>~~G~~|1.92<br>~~G~~|ns<br>~~G~~|
|LVCMOS18_F16 <br>~~Se~~<br>~~Se~~|0.74|0.83|0.89|0.97|0.89|0.94|1.40|1.52|1.77<br>~~G~~|1.78<br>~~G~~|1.77<br>~~G~~|2.00<br>~~G~~|1.42<br>~~G~~|1.55<br>~~G~~|1.79<br>~~G~~|1.79<br>~~G~~|1.79<br>~~G~~|1.64<br>~~G~~|ns<br>~~G~~|
|LVCMOS18_F24 <br>~~Se~~<br>~~Se~~<br>~~Se~~|0.74|0.83|0.89<br>~~OO~~|0.97<br>~~OO~~|0.89<br>~~OO~~|0.94<br>~~OO~~|1.34<br>~~OO~~|1.46|1.71|2.28|1.71|1.94|1.35|1.49|1.73|2.29|1.73|1.58|ns|
|LVCMOS15_S4<br>~~Se~~<br>~~Se~~<br>~~Se~~|0.77|0.86|0.93<br>~~OO~~|0.96<br>~~OO~~|0.93<br>~~OO~~|0.98<br>~~OO~~|2.05<br>~~OO~~|2.18|2.43|2.43|2.43|2.50|2.07|2.21|2.45|2.45|2.45|2.14|ns|
|LVCMOS15_S8<br>~~Se~~<br>~~Se~~<br>~~Se~~|0.77|0.86|0.93<br>~~OO~~|0.96<br>~~OO~~|0.93<br>~~OO~~|0.98<br>~~OO~~|2.09<br>~~OO~~|2.21|2.46|2.46|2.46|2.69|2.10|2.24|2.48|2.48|2.48|2.33|ns|
|LVCMOS15_S12 <br>~~Se~~<br>~~Se~~<br>~~Se~~|0.77|0.86|0.93|0.96|0.93|0.98|1.59|1.71|1.96|1.96|1.96|2.19|1.60|1.74|1.98|1.98|1.98|1.83|ns|
|LVCMOS15_S16 <br>~~Se~~<br>~~Se~~<br>~~Se~~|0.77|0.86|0.93|0.96|0.93|0.98|1.59|1.71|1.96|1.96|1.96|2.19|1.60|1.74|1.98|1.98|1.98|1.83|ns|
|LVCMOS15_F4<br>~~Se~~<br>~~Se~~<br>~~Se~~|0.77|0.86|0.93|0.96|0.93|0.98|1.85|1.97|2.23|2.23|2.23|2.27|1.87|2.00|2.24|2.24|2.24|1.91|ns|
|LVCMOS15_F8<br>~~Se~~<br>~~Se~~<br>~~Se~~|0.77|0.86|0.93|0.96|0.93|0.98|1.60|1.72|1.98|1.98|1.98|2.21|1.62|1.75|1.99|1.99|1.99|1.84|ns|
|LVCMOS15_F12 <br>~~Se~~<br>~~Se~~<br>~~Se~~|0.77|0.86|0.93|0.96|0.93|0.98|1.35|1.47|1.73|1.73|1.73|1.96|1.37|1.50|1.74|1.74|1.74|1.59|ns|
|LVCMOS15_F16 <br>~~Se~~<br>~~Se~~<br>~~**S**e~~|0.77|0.86|0.93|0.96|0.93|0.98|1.34|1.46|1.71|2.07|1.71|1.94|1.35|1.49|1.73|2.09|1.73|1.58|ns|
|LVCMOS12_S4<br>~~Se~~<br>~~**S**e~~|0.87|0.95|1.02|1.19|1.02|1.08|2.57|2.69|2.95|2.95|2.95|3.18|2.59|2.72|2.96|2.96|2.96|2.81|ns|
|LVCMOS12_S8<br>~~**S**e~~<br>~~Se~~|0.87|0.95|1.02|1.19|1.02|1.08|2.09|2.21|2.46<br>~~G~~|2.46<br>~~G~~|2.46<br>~~G~~|2.69<br>~~G~~|2.10<br>~~G~~|2.24<br>~~G~~|2.48<br>~~G~~|2.48<br>~~G~~|2.48<br>~~G~~|2.33<br>~~G~~|ns<br>~~G~~|
|LVCMOS12_S12 <br>~~Se~~<br>~~Se~~|0.87|0.95|1.02|1.19|1.02|1.08|1.79|1.91|2.17<br>~~G~~|2.17<br>~~G~~|2.17<br>~~G~~|2.40<br>~~G~~|1.81<br>~~G~~|1.94<br>~~G~~|2.18<br>~~G~~|2.18<br>~~G~~|2.18<br>~~G~~|2.03<br>~~G~~|ns<br>~~G~~|
|LVCMOS12_F4<br>~~Se~~<br>~~Se~~<br>~~Se~~|0.87|0.95|1.02<br>~~OO~~|1.19<br>~~OO~~|1.02<br>~~OO~~|1.08<br>~~OO~~|1.98<br>~~OO~~|2.10|2.35|2.35|2.35|2.58|1.99|2.13|2.37|2.37|2.37|2.22|ns|
|LVCMOS12_F8<br>~~Se~~<br>~~Se~~<br>~~Se~~|0.87|0.95|1.02<br>~~OO~~|1.19<br>~~OO~~|1.02<br>~~OO~~|1.08<br>~~OO~~|1.54<br>~~OO~~|1.66|1.92|1.92|1.92|2.15|1.56|1.69|1.93|1.93|1.93|1.78|ns|
|LVCMOS12_F12 <br>~~Se~~<br>~~Se~~<br>~~Se~~|0.87|0.95|1.02<br>~~OO~~|1.19<br>~~OO~~|1.02<br>~~OO~~|1.08<br>~~OO~~|1.38<br>~~OO~~|1.51|1.76|1.76|1.76|1.97|1.40|1.54|1.77|1.77|1.77|1.61|ns|
|SSTL135_S<br>~~Se~~<br>~~Se~~<br>~~Se~~|0.67|0.75|0.82|0.88|0.82|0.87|1.35|1.47|1.73|1.73|1.73|1.93|1.37|1.50|1.74|1.74|1.74|1.56|ns|
|SSTL15_S<br>~~Se~~<br>~~Se~~<br>~~Se~~|0.60|0.68|0.75|0.75|0.75|0.80|1.30|1.43|1.68|1.71|1.68|1.88|1.32|1.46|1.69|1.73|1.69|1.52|ns|
|SSTL18_I_S<br>~~Se~~<br>~~Se~~<br>~~Se~~|0.67|0.75|0.82|0.86|0.82|0.87|1.67|1.79|2.04|2.04|2.04|2.24|1.68|1.82|2.06|2.06|2.06|1.88|ns|
|SSTL18_II_S<br>~~Se~~<br>~~Se~~<br>~~—~~<br>~~|~~|0.67<br>~~ttt?~~|0.75<br>~~ttt?~~|0.82<br>~~ttt?~~|0.88<br>~~ttt?~~|0.82<br>~~ttt?ety~~|0.85<br>~~ety~~|1.31<br>~~ety~~|1.43<br>~~etytt~~|1.68<br>~~tt~~|1.68<br>~~ttyt~~|1.68<br>~~ytey~~|1.91<br>~~ey~~|1.32<br>~~ey~~|1.46<br>~~ty~~|1.70<br>~~ty~~|1.70<br>~~ty~~|1.70<br>~~ty~~|1.55|ns|
|DIFF_SSTL135_<br>S<br>~~Se~~<br>~~—~~<br>~~|~~<br>~~—~~<br>~~|~~|0.68<br>~~ttt?~~<br>~~ttt?~~|0.76<br>~~ttt?~~<br>~~ttt?~~|0.83<br>~~ttt?~~<br>~~ttt?~~|0.88<br>~~ttt?~~<br>~~ttt?~~|0.83<br>~~ttt?ety~~<br>~~ttt?ety~~|0.87<br>~~ety~~<br>~~ety~~|1.35<br>~~ety~~<br>~~ety~~|1.47<br>~~etytt~~<br>~~etytt~~|1.73<br>~~tt~~<br>~~tt~~|1.73<br>~~ttyt~~<br>~~ttyt~~|1.73<br>~~ytey~~<br>~~ytey~~|1.93<br>~~ey~~<br>~~ey~~|1.37<br>~~ey~~<br>~~ey~~|1.50<br>~~ty~~<br>~~ty~~|1.74<br>~~ty~~<br>~~ty~~|1.74<br>~~ty~~<br>~~ty~~|1.74<br>~~ty~~<br>~~ty~~|1.56|ns|
|DIFF_SSTL15_<br>S<br>~~—~~<br>~~| ~~<br>~~—~~<br>~~|~~<br>~~—~~<br>~~|~~|0.68<br> ~~ttt?~~<br>~~ttt?~~<br>~~ttt?~~|0.76<br>~~ttt?~~<br>~~ttt?~~<br>~~ttt?~~|0.83<br>~~ttt?~~<br>~~ttt?~~<br>~~ttt?~~|0.88<br>~~ttt?~~<br>~~ttt?~~<br>~~ttt?~~|0.83<br>~~ttt? ety~~<br>~~ttt?ety~~<br>~~ttt?ety~~|0.87<br>~~ety~~<br>~~ety~~<br>~~ety~~|1.30<br>~~ety~~<br>~~ety~~<br>~~ety~~|1.43<br>~~ety tt~~<br>~~etytt~~<br>~~etytt~~|1.68<br>~~tt~~<br>~~tt~~<br>~~tt~~|1.71<br>~~tt yt~~<br>~~ttyt~~<br>~~ttyt~~|1.68<br>~~yt ey~~<br>~~ytey~~<br>~~ytey~~|1.88<br>~~ey~~<br>~~ey~~<br>~~ey~~|1.32<br>~~ey ~~<br>~~ey~~<br>~~ey~~|1.46<br> ~~ty~~<br>~~ty~~<br>~~ty~~|1.69<br>~~ty~~<br>~~ty~~<br>~~ty~~|1.73<br>~~ty~~<br>~~ty~~<br>~~ty~~|1.69<br>~~ty~~<br>~~ty~~<br>~~ty~~|1.52|ns|
|DIFF_SSTL18<br>_I_S<br>~~—~~<br>~~| ~~<br>~~—~~<br>~~|~~<br>~~ttt~~|0.71<br> ~~ttt?~~<br>~~ttt?~~<br>~~ttt~~|0.79<br>~~ttt?~~<br>~~ttt?~~<br>~~ttt~~|0.86<br>~~ttt?~~<br>~~ttt?~~<br>~~tttte~~|0.88<br>~~ttt?~~<br>~~ttt?~~<br>~~te~~|0.86<br>~~ttt? ety~~<br>~~ttt?ety~~<br>~~teete~~|0.87<br>~~ety~~<br>~~ety~~<br>~~ete~~|1.68<br>~~ety~~<br>~~ety~~<br>~~ete~~|1.80<br>~~ety tt~~<br>~~etytt~~<br>~~etett~~|2.06<br>~~tt~~<br>~~tt~~<br>~~tt~~|2.06<br>~~tt yt~~<br>~~ttyt~~<br>~~ttty~~|2.06<br>~~yt ey~~<br>~~ytey~~<br>~~tyey~~|2.24<br>~~ey~~<br>~~ey~~<br>~~ey~~|1.70<br>~~ey ~~<br>~~ey~~<br>~~eyee~~|1.83<br> ~~ty~~<br>~~ty~~<br>~~ee~~|2.07<br>~~ty~~<br>~~ty~~<br>~~ee~~|2.07<br>~~ty~~<br>~~ty~~|2.07<br>~~ty~~<br>~~ty~~<br>~~tt~~|1.88<br>~~tt~~|ns|
|DIFF_SSTL18<br>_II_S<br>~~—~~<br>~~| ~~<br>~~ttt~~|0.71<br> ~~ttt?~~<br>~~ttt~~|0.79<br>~~ttt?~~<br>~~ttt~~|0.86<br>~~ttt?~~<br>~~tttte~~|0.88<br>~~ttt?~~<br>~~te~~|0.86<br>~~ttt? ety~~<br>~~teete~~|0.87<br>~~ety~~<br>~~ete~~|1.38<br>~~ety~~<br>~~ete~~|1.51<br>~~ety tt~~<br>~~etett~~|1.76<br>~~tt~~<br>~~tt~~|1.76<br>~~tt yt~~<br>~~ttty~~|1.76<br>~~yt ey~~<br>~~tyey~~|1.94<br>~~ey~~<br>~~ey~~|1.40<br>~~ey ~~<br>~~eyee~~|1.54<br> ~~ty~~<br>~~ee~~|1.77<br>~~ty~~<br>~~ee~~|1.77<br>~~ty~~|1.77<br>~~ty~~<br>~~tt~~|1.58<br>~~tt~~|ns|
DS181 (v1.27.1) July 3, 2024 **Product Specification**
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18
**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 17:_ **IOB High Range (HR) Switching Characteristics** _**(Cont’d)**_
|**I/O Standard**<br>~~eS~~|**TIOPI**<br>~~ee~~<br>~~eS~~|**TIOPI**<br>~~ee~~<br>~~eS~~|**TIOPI**<br>~~ee~~<br>~~eS~~|**TIOPI**<br>~~ee~~<br>~~eS~~|**TIOPI**<br>~~ee~~<br>~~eS~~|**TIOPI**<br>~~ee~~<br>~~eS~~|**TIOOP**<br>~~ee~~<br>~~eS~~|**TIOOP**<br>~~ee~~<br>~~eS~~|**TIOOP**<br>~~ee~~<br>~~eS~~|**TIOOP**<br>~~ee~~<br>~~eS~~|**TIOOP**<br>~~ee~~<br>~~eS~~|**TIOOP**<br>~~ee~~<br>~~eS~~|**TIOTP**<br>~~ee~~<br>~~eS~~|**TIOTP**<br>~~ee~~<br>~~eS~~|**TIOTP**<br>~~ee~~<br>~~eS~~|**TIOTP**<br>~~ee~~<br>~~eS~~|**TIOTP**<br>~~ee~~<br>~~eS~~|**TIOTP**<br>~~ee~~<br>~~eS~~|**Units**<br>~~eS~~|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||**Speed Grade**<br>~~a~~<br>~~eS~~||||||**Speed Grade**<br>~~a~~<br>~~eS~~||||||**Speed Grade**<br>~~a~~<br>~~eS~~|||||||
||**1.0V**<br>~~a~~<br>~~a~~<br>~~eS~~||||**0.95V **<br>~~a~~<br>~~a~~<br>~~eS~~|**0.9V**<br>~~a~~<br>~~a~~<br>~~eS~~|**1.0V**<br>~~a~~<br>~~a~~<br>~~eS~~||||**0.95V **<br>~~a~~<br>~~a~~<br>~~eS~~|**0.9V**<br>~~a~~<br>~~a~~<br>~~eS~~|**1.0V**<br>~~a~~<br>~~a~~<br>~~eS~~||||**0.95V **<br>~~a~~<br>~~a~~<br>~~eS~~|**0.9V**<br>~~a~~<br>~~a~~<br>~~eS~~||
||**-3**<br>~~a~~<br>~~eS~~|**-2/**<br>**-2LE**<br>~~a~~<br>~~eS~~|**-1**<br>~~a~~<br>~~eS~~|**-1Q/**<br>**-1M**<br>~~a~~<br>~~eS~~|**-1LI**<br>~~a~~<br>~~eS~~|**-2LE**<br>~~a~~<br>~~eS~~|**-3**<br>~~a~~<br>~~eS~~|**-2/**<br>**-2LE**<br>~~a~~<br>~~eS~~|**-1**<br>~~a~~<br>~~eS~~|**-1Q/**<br>**-1M**<br>~~a~~<br>~~eS~~|**-1LI**<br>~~a~~<br>~~eS~~|**-2LE**<br>~~a~~<br>~~eS~~|**-3**<br>~~a~~<br>~~eS~~|**-2/**<br>**-2LE**<br>~~a~~<br>~~eS~~|**-1**<br>~~a~~<br>~~eS~~|**-1Q/**<br>**-1M**<br>~~a~~<br>~~eS~~|**-1LI**<br>~~a~~<br>~~eS~~|**-2LE**<br>~~a~~<br>~~eS~~||
|SSTL135_F<br>~~a~~|0.67|0.75|0.82|0.88|0.82|0.87|1.12|1.24|1.49|1.49|1.49|1.71|1.13|1.27|1.51|1.51|1.51|1.34|ns|
|SSTL15_F<br>~~a~~<br>~~Se~~|0.60<br>~~Se~~|0.68|0.75|0.75|0.75|0.80|1.07|1.19|1.45|1.45|1.45|1.68|1.09|1.22|1.46|1.46|1.46|1.31|ns|
|SSTL18_I_F<br>~~Se~~<br>~~a~~<br>~~Se OG~~|0.67<br>~~Se~~<br>~~OG~~|0.75<br>~~OG~~|0.82<br>~~OG~~|0.86<br>~~OG~~|0.82<br>~~OG~~|0.87<br>~~OG~~|1.12<br>~~OG~~|1.24<br>~~OG~~|1.49<br>~~OG~~|1.53<br>~~OG~~|1.49<br>~~OG~~|1.72<br>~~OG~~|1.13<br>~~OG~~|1.27<br>~~OG~~|1.51<br>~~OG~~|1.54<br>~~OG~~|1.51<br>~~OG~~|1.36<br>~~OG~~|ns<br>~~OG~~|
|SSTL18_II_F<br>~~Se OG~~<br>~~ee~~|0.67<br>~~OG~~<br>|0.75<br>~~OG~~<br>~~ee~~|0.82<br>~~OG~~<br>~~ee~~|0.88<br>~~OG~~<br>~~ee~~|0.82<br>~~OG~~<br>~~eee~~|0.85<br>~~OG~~<br>~~eee~~|1.12<br>~~OG~~<br>~~eee~~|1.24<br>~~OG~~<br>~~eee~~|1.49<br>~~OG~~<br>~~eee~~|1.51<br>~~OG~~<br>~~eee~~|1.49<br>~~OG~~<br>~~eee~~|1.71<br>~~OG~~<br>~~eee~~|1.13<br>~~OG~~<br>~~eee~~|1.27<br>~~OG~~<br>~~eee~~|1.51<br>~~OG~~<br>~~eee~~|1.52<br>~~OG~~<br>~~eee~~|1.51<br>~~OG~~<br>~~eee~~|1.34<br>~~OG~~<br>~~eee~~|ns<br>~~OG~~<br>~~eee~~|
|DIFF_SSTL135<br>_F<br>~~Se OG~~<br>~~ee~~|0.68<br>~~OG~~<br>|0.76<br>~~OG~~<br>~~ee~~|0.83<br>~~OG~~<br>~~ee~~|0.88<br>~~OG~~<br>~~ee~~|0.83<br>~~OG~~<br>~~eee~~|0.87<br>~~OG~~<br>~~eee~~|1.12<br>~~OG~~<br>~~eee~~|1.24<br>~~OG~~<br>~~eee~~|1.49<br>~~OG~~<br>~~eee~~|1.49<br>~~OG~~<br>~~eee~~|1.49<br>~~OG~~<br>~~eee~~|1.71<br>~~OG~~<br>~~eee~~|1.13<br>~~OG~~<br>~~eee~~|1.27<br>~~OG~~<br>~~eee~~|1.51<br>~~OG~~<br>~~eee~~|1.51<br>~~OG~~<br>~~eee~~|1.51<br>~~OG~~<br>~~eee~~|1.34<br>~~OG~~<br>~~eee~~|ns<br>~~OG~~<br>~~eee~~|
|DIFF_SSTL15_F <br>~~ee ~~<br>~~a~~<br>~~ee~~|0.68<br> <br>~~eee~~|0.76<br> ~~ee~~<br>~~eee~~|0.83<br>~~ee~~<br>~~eee~~|0.88<br>~~ee~~<br>~~eee~~|0.83<br>~~eee~~<br>~~eee~~|0.87<br>~~eee~~<br>~~eee~~|1.07<br>~~eee~~<br>~~eee~~|1.19<br>~~eee~~<br>~~eee~~|1.45<br>~~eee~~<br>~~eee~~|1.45<br>~~eee~~<br>~~eee~~|1.45<br>~~eee~~<br>~~eee~~|1.68<br>~~eee~~<br>~~eee~~|1.09<br>~~eee~~<br>~~eee~~|1.22<br>~~eee~~<br>~~eee~~|1.46<br>~~eee~~<br>~~eee~~|1.46<br>~~eee~~<br>~~eee~~|1.46<br>~~eee~~<br>~~eee~~|1.31<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
|DIFF_SSTL18_I<br>_F<br>~~a~~<br>~~ee~~<br>~~ee~~|0.71<br>~~eee~~<br>|0.79<br>~~eee~~<br>~~ee~~|0.86<br>~~eee~~<br>~~ee~~|0.88<br>~~eee~~<br>~~ee~~|0.86<br>~~eee~~<br>~~eee~~|0.87<br>~~eee~~<br>~~eee~~|1.23<br>~~eee~~<br>~~eee~~|1.35<br>~~eee~~<br>~~eee~~|1.60<br>~~eee~~<br>~~eee~~|1.60<br>~~eee~~<br>~~eee~~|1.60<br>~~eee~~<br>~~eee~~|1.80<br>~~eee~~<br>~~eee~~|1.24<br>~~eee~~<br>~~eee~~|1.38<br>~~eee~~<br>~~eee~~|1.62<br>~~eee~~<br>~~eee~~|1.62<br>~~eee~~<br>~~eee~~|1.62<br>~~eee~~<br>~~eee~~|1.44<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
|DIFF_SSTL18_II<br>_F<br>~~ee~~<br>~~ee~~|0.71<br>~~eee~~<br>|0.79<br>~~eee~~<br>~~ee~~|0.86<br>~~eee~~<br>~~ee~~|0.88<br>~~eee~~<br>~~ee~~|0.86<br>~~eee~~<br>~~eee~~|0.87<br>~~eee~~<br>~~eee~~|1.21<br>~~eee~~<br>~~eee~~|1.33<br>~~eee~~<br>~~eee~~|1.59<br>~~eee~~<br>~~eee~~|1.59<br>~~eee~~<br>~~eee~~|1.59<br>~~eee~~<br>~~eee~~|1.79<br>~~eee~~<br>~~eee~~|1.23<br>~~eee~~<br>~~eee~~|1.36<br>~~eee~~<br>~~eee~~|1.60<br>~~eee~~<br>~~eee~~|1.60<br>~~eee~~<br>~~eee~~|1.60<br>~~eee~~<br>~~eee~~|1.42<br>~~eee~~<br>~~eee~~|ns<br>~~eee~~<br>~~eee~~|
Table 18 specifies the values of TIOTPHZ and TIOIBUFDISABLE. TIOTPHZ is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is enabled (i.e., a high impedance state). TIOIBUFDISABLE is described as the IOB delay from IBUFDISABLE to O output. In HR I/O banks, the internal IN_TERM termination turn-off time is always faster than TIOTPHZ when the INTERMDISABLE pin is used.
_Table 18:_ **IOB 3-state Output Switching Characteristics**
|**Symbol**|**Description**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|---|---|
|||**1.0V**||||**0.95V**|**0.9V**||
|||**-3**|**-2/-2LE**|**-1**|**-1Q/-1M**|**-1LI**|**-2LE**||
|TIOTPHZ|T input to pad high-impedance|2.06|2.19|2.37|2.37|2.37|2.03|ns|
|TIOIBUFDISABLE|IBUF turn-on time from IBUFDISABLE to O<br>output|2.11|2.30|2.60|2.60|2.60|2.17|ns|
## **I/O Standard Adjustment Measurement Methodology**
## **Input Delay Measurements**
Table 19 shows the test setup parameters used for measuring input delay.
_Table 19:_ **Input Delay Measurement Methodology**
||~~ee~~|~~ee~~|~~ee~~|||
|---|---|---|---|---|---|
|**Description**<br>~~es~~|**I/O Standard Attribute**<br>~~es~~<br>~~ee~~|**VL(1)**<br>~~es~~<br>~~ee~~|**VH(1)**<br>~~es~~<br>~~ee~~|**VMEAS**<br>**(3)(5)**<br>~~es~~|**VREF**<br>**(2)(4)**<br>~~es~~|
|LVCMOS, 1.2V<br>~~a~~|LVCMOS12<br>~~ee ~~<br>~~a~~|0.1<br> ~~ee ~~<br>~~a~~|1.1<br> ~~ee~~<br>~~a~~|0.6<br>~~a~~|–<br>~~a~~|
|LVCMOS, 1.5V<br>~~a~~|LVCMOS15<br>~~a~~|0.1<br>~~a~~|1.4<br>~~a~~|0.75<br>~~a~~|–<br>~~a~~|
|LVCMOS, 1.8V<br>~~a~~<br>~~a~~|LVCMOS18<br>~~a~~<br>~~a~~|0.1<br>~~a~~<br>~~a~~|1.7<br>~~a~~<br>~~a~~|0.9<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|
|LVCMOS, 2.5V<br>~~a~~<br>~~a~~|LVCMOS25<br>~~a~~<br>~~a~~|0.1<br>~~a~~<br>~~a~~|2.4<br>~~a~~<br>~~a~~|1.25<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|
|LVCMOS, 3.3V<br>~~a~~|LVCMOS33<br>~~a~~|0.1<br>~~a~~|3.2<br>~~a~~|1.65<br>~~a~~|–<br>~~a~~|
|LVTTL, 3.3V<br>~~a~~<br>~~a~~|LVTTL<br>~~a~~<br>~~a~~|0.1<br>~~a~~<br>~~a~~|3.2<br>~~a~~<br>~~a~~|1.65<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|
|MOBILE_DDR, 1.8V<br>~~a~~<br>~~a~~|MOBILE_DDR<br>~~a~~<br>~~a~~|0.1<br>~~a~~<br>~~a~~|1.7<br>~~a~~<br>~~a~~|0.9<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|
|PCI33, 3.3V<br>~~a~~|PCI33_3<br>~~a~~|0.1<br>~~a~~|3.2<br>~~a~~|1.65<br>~~a~~|–<br>~~a~~|
|HSTL (High-Speed Transceiver Logic), Class I, 1.2V<br>~~a~~<br>~~a~~|HSTL_I_12<br>~~a~~<br>~~a~~|VREF– 0.5<br>~~a~~<br>~~a~~|VREF+ 0.5<br>~~a~~<br>~~a~~|VREF<br>~~a~~<br>~~a~~|0.60<br>~~a~~<br>~~a~~|
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DS181 (v1.27.1) July 3, 2024 **Product Specification**
19
**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 19:_ **Input Delay Measurement Methodology** _**(Cont’d)**_
|**Description**<br>|**I/O Standard Attribute**<br>|**VL(1)**<br>|**VH(1)**<br>|**VMEAS**<br>**(3)(5)**<br>|**VREF**<br>**(2)(4)**<br>|
|---|---|---|---|---|---|
|HSTL, Class I & II, 1.5V<br>~~a~~|HSTL_I, HSTL_II<br>~~a~~|VREF– 0.65<br>~~a~~|VREF+ 0.65<br>~~a~~|VREF<br>~~a~~|0.75<br>~~a~~|
|HSTL, Class I & II, 1.8V<br>~~a~~|HSTL_I_18, HSTL_II_18<br>~~a~~|VREF– 0.8<br>~~a~~|VREF+ 0.8<br>~~a~~|VREF<br>~~a~~|0.90<br>~~a~~|
|HSUL (High-Speed Unterminated Logic), 1.2V<br>~~a~~<br>~~a~~|HSUL_12<br>~~a~~<br>~~a~~|VREF– 0.5<br>~~a~~<br>~~a~~|VREF+ 0.5<br>~~a~~<br>~~a~~|VREF<br>~~a~~<br>~~a~~|0.60<br>~~a~~<br>~~a~~|
|SSTL (Stub Terminated Transceiver Logic), 1.2V<br>~~a~~<br>~~a~~|SSTL12<br>~~a~~<br>~~a~~|VREF– 0.5<br>~~a~~<br>~~a~~|VREF+ 0.5<br>~~a~~<br>~~a~~|VREF<br>~~a~~<br>~~a~~|0.60<br>~~a~~<br>~~a~~|
|SSTL, 1.35V<br>~~a~~|SSTL135, SSTL135_R<br>~~a~~|VREF– 0.575<br>~~a~~|VREF+ 0.575<br>~~a~~|VREF<br>~~a~~|0.675<br>~~a~~|
|SSTL, 1.5V<br>~~a~~<br>~~a~~|SSTL15, SSTL15_R<br>~~a~~<br>~~a~~|VREF– 0.65<br>~~a~~<br>~~a~~|VREF+ 0.65<br>~~a~~<br>~~a~~|VREF<br>~~a~~<br>~~a~~|0.75<br>~~a~~<br>~~a~~|
|SSTL, Class I & II, 1.8V<br>~~a~~<br>~~a~~|SSTL18_I, SSTL18_II<br>~~a~~<br>~~a~~|VREF– 0.8<br>~~a~~<br>~~a~~|VREF+ 0.8<br>~~a~~<br>~~a~~|VREF<br>~~a~~<br>~~a~~|0.90<br>~~a~~<br>~~a~~|
|DIFF_MOBILE_DDR, 1.8V<br>~~a~~|DIFF_MOBILE_DDR<br>~~a~~|0.9 – 0.125<br>~~a~~|0.9 + 0.125<br>~~a~~|0(5)<br>~~a~~|–<br>~~a~~|
|DIFF_HSTL, Class I, 1.2V<br>~~a~~|DIFF_HSTL_I_12<br>~~a~~|0.6 – 0.125<br>~~a~~|0.6 + 0.125<br>~~a~~|0(5)<br>~~a~~|–<br>~~a~~|
|DIFF_HSTL, Class I & II,1.5V<br>~~ee~~|DIFF_HSTL_I,<br>DIFF_HSTL_II<br>~~ee~~|0.75 – 0.125<br>~~ee~~|0.75 + 0.125<br>~~ee~~|0(5)<br>~~ee~~|–<br>~~ee~~|
|DIFF_HSTL, Class I & II, 1.8V<br>~~ee~~|DIFF_HSTL_I_18,<br>DIFF_HSTL_II_18<br>~~ee~~|0.9 – 0.125<br>~~ee~~|0.9 + 0.125<br>~~ee~~|0(5)<br>~~ee~~|–<br>~~ee~~|
|DIFF_HSUL, 1.2V|DIFF_HSUL_12|0.6 – 0.125|0.6 + 0.125|0(5)|–|
|DIFF_SSTL135/DIFF_SSTL135_R, 1.35V<br>~~a~~|DIFF_SSTL135,<br>DIFF_SSTL135_R<br>~~a~~|0.675 – 0.125<br>~~a~~|0.675 + 0.125<br>~~a~~|0(5)<br>~~a~~|–<br>~~a~~|
|DIFF_SSTL15/DIFF_SSTL15_R, 1.5V<br>~~a~~|DIFF_SSTL15,<br>DIFF_SSTL15_R<br>~~a~~|0.75 – 0.125<br>~~a~~|0.75 + 0.125<br>~~a~~|0(5)<br>~~a~~|–<br>~~a~~|
|DIFF_SSTL18_I/DIFF_SSTL18_II, 1.8V|DIFF_SSTL18_I,<br>DIFF_SSTL18_II|0.9 – 0.125|0.9 + 0.125|0(5)|–|
|LVDS_25, 2.5V<br>~~a~~|LVDS_25<br>~~a~~|1.2 – 0.125<br>~~a~~|1.2 + 0.125<br>~~a~~|0(5)<br>~~a~~|–<br>~~a~~|
|BLVDS_25, 2.5V<br>~~a~~<br>~~a~~|BLVDS_25<br>~~a~~<br>~~a~~|1.25 – 0.125<br>~~a~~<br>~~a~~|1.25 + 0.125<br>~~a~~<br>~~a~~|0(5)<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|
|MINI_LVDS_25, 2.5V<br>~~a~~|MINI_LVDS_25<br>~~a~~|1.25 – 0.125<br>~~a~~|1.25 + 0.125<br>~~a~~|0(5)<br>~~a~~|–<br>~~a~~|
|PPDS_25<br>~~a~~<br>~~a~~|PPDS_25<br>~~a~~<br>~~a~~|1.25 – 0.125<br>~~a~~<br>~~a~~|1.25 + 0.125<br>~~a~~<br>~~a~~|0(5)<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|
|RSDS_25<br>~~a~~<br>~~a~~|RSDS_25<br>~~a~~<br>~~a~~|1.25 – 0.125<br>~~a~~<br>~~a~~|1.25 + 0.125<br>~~a~~<br>~~a~~|0(5)<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|
|TMDS_33<br>~~a~~|TMDS_33<br>~~a~~|3 – 0.125<br>~~a~~|3 + 0.125<br>~~a~~|0(5)<br>~~a~~|–<br>~~a~~|
## **Notes:**
1. Input waveform switches between VLand VH.
2. Measurements are made at typical, minimum, and maximum VREF values. Reported delays reflect worst case of these measurements. VREF values listed are typical.
3. Input voltage level from which measurement starts.
4. This is an input voltage reference that bears no relation to the VREF / VMEAS parameters found in IBIS models and/or noted in Figure 1.
5. The value given is the differential input voltage.
DS181 (v1.27.1) July 3, 2024 **Product Specification**
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20
**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
## **Output Delay Measurements**
Output delays are measured with short output traces. Standard termination was used for all testing. The propagation delay of the trace is characterized separately and subtracted from the final measurement, and is therefore not included in the generalized test setups shown in Figure 1 and Figure 2.
**==> picture [203 x 153] intentionally omitted <==**
**----- Start of picture text -----**<br>
VREF<br>FPGA Output RREF<br>VMEAS<br>(Voltage Level When Taking<br>Delay Measurement)<br>CREF<br>(Probe Capacitance)<br>L<br>DS181_04_090514<br>**----- End of picture text -----**<br>
_Figure 1:_ **Single-Ended Test Setup**
**==> picture [217 x 95] intentionally omitted <==**
**----- Start of picture text -----**<br>
FPGA Output<br>+<br>CREF RREF VMEAS<br>–<br>DS181_05_090514<br>**----- End of picture text -----**<br>
_Figure 2:_ **Differential Test Setup**
Parameters VREF, RREF, CREF, and VMEAS fully describe the test conditions for each I/O standard. The most accurate prediction of propagation delay in any given application can be obtained through IBIS simulation, using this method:
1. Simulate the output driver of choice into the generalized test setup using values from Table 20.
2. Record the time to VMEAS.
3. Simulate the output driver of choice into the actual PCB trace and load using the appropriate IBIS model or capacitance value to represent the load.
4. Record the time to VMEAS.
5. Compare the results of step 2 and step 4. The increase or decrease in delay yields the actual propagation delay of the PCB trace.
_Table 20:_ **Output Delay Measurement Methodology**
|**Description**<br>~~ee~~|**I/O Standard Attribute**<br>~~ee~~|**RREF**<br>**(****)**<br>~~ee~~|**CREF(1)**<br>**(pF)**<br>~~ee~~|**VMEAS**<br>**(V)**<br>~~ee~~|**VREF**<br>**(V)**<br>~~ee~~|
|---|---|---|---|---|---|
|LVCMOS, 1.2V<br>~~SS~~|LVCMOS12<br>~~SS~~|1M<br>~~SS~~|0<br>~~SS~~|0.6<br>~~SS~~|0<br>~~SS~~|
|LVCMOS, 1.5V<br>~~SS~~<br>~~a~~|LVCMOS15<br>~~SS~~<br>~~a~~|1M<br>~~SS~~<br>~~a~~|0<br>~~SS~~<br>~~a~~|0.75<br>~~SS~~<br>~~a~~|0<br>~~SS~~<br>~~a~~|
|LVCMOS, 1.8V<br>~~a~~|LVCMOS18<br>~~a~~|1M<br>~~a~~|0<br>~~a~~|0.9<br>~~a~~|0<br>~~a~~|
|LVCMOS, 2.5V<br>~~a~~<br>~~ee~~|LVCMOS25<br>~~a~~<br>~~ee~~|1M<br>~~a~~<br>~~ee~~|0<br>~~a~~<br>~~ee~~|1.25<br>~~a~~<br>~~ee~~|0<br>~~a~~<br>~~ee~~|
|LVCMOS, 3.3V<br>~~ee~~<br>~~a~~|LVCMOS33<br>~~ee~~<br>~~a~~|1M<br>~~ee~~<br>~~a~~|0<br>~~ee~~<br>~~a~~|1.65<br>~~ee~~<br>~~a~~|0<br>~~ee~~<br>~~a~~|
|LVTTL, 3.3V<br>~~a~~<br>~~ee~~|LVTTL<br>~~a~~|1M<br>~~a~~|0<br>~~a~~|1.65<br>~~a~~|0<br>~~a~~|
|PCI33, 3.3V<br>~~a~~<br>~~ee~~|PCI33_3<br>~~a~~|25<br>~~a~~|10<br>~~a~~|1.65<br>~~a~~|0<br>~~a~~|
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DS181 (v1.27.1) July 3, 2024 **Product Specification**
21
**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 20:_ **Output Delay Measurement Methodology** _**(Cont’d)**_
|**Description**<br>|**I/O Standard Attribute**<br>|**RREF**<br>**(****)**<br>|**CREF(1)**<br>**(pF)**<br>|**VMEAS**<br>**(V)**<br>|**VREF**<br>**(V)**<br>|
|---|---|---|---|---|---|
|HSTL (High-Speed Transceiver Logic), Class I, 1.2V<br>~~a~~|HSTL_I_12<br>~~a~~|50<br>~~a~~|0<br>~~a~~|VREF<br>~~a~~|0.6<br>~~a~~|
|HSTL, Class I, 1.5V<br>~~a~~<br>~~a~~|HSTL_I<br>~~a~~<br>~~a~~|50<br>~~a~~<br>~~a~~|0<br>~~a~~<br>~~a~~|VREF<br>~~a~~<br>~~a~~|0.75<br>~~a~~<br>~~a~~|
|HSTL, Class II, 1.5V<br>~~ee~~|HSTL_II<br>~~ee~~|25<br>~~ee~~|0<br>~~ee~~|VREF<br>~~ee~~|0.75<br>~~ee~~|
|HSTL, Class I, 1.8V<br>~~ee~~<br>~~OO~~|HSTL_I_18<br>~~ee~~<br>~~OO~~|50<br>~~ee~~<br>~~OO~~|0<br>~~ee~~<br>~~OO~~|VREF<br>~~ee~~<br>~~OO~~|0.9<br>~~ee~~<br>~~OO~~|
|HSTL, Class II, 1.8V<br>~~OO~~<br>~~a~~|HSTL_II_18<br>~~OO~~|25<br>~~OO~~|0<br>~~OO~~|VREF<br>~~OO~~|0.9<br>~~OO~~|
|HSUL (High-Speed Unterminated Logic), 1.2V<br>~~ee~~|HSUL_12<br>~~ee~~|50<br>~~ee~~|0<br>~~ee~~|VREF<br>~~ee~~|0.6<br>~~ee~~|
|SSTL12, 1.2V<br>~~ee~~<br>~~OO~~|SSTL12<br>~~ee~~<br>~~OO~~|50<br>~~ee~~<br>~~OO~~|0<br>~~ee~~<br>~~OO~~|VREF<br>~~ee~~<br>~~OO~~|0.6<br>~~ee~~<br>~~OO~~|
|SSTL135/SSTL135_R, 1.35V<br>~~OO~~<br>~~a~~|SSTL135, SSTL135_R<br>~~OO~~|50<br>~~OO~~|0<br>~~OO~~|VREF<br>~~OO~~|0.675<br>~~OO~~|
|SSTL15/SSTL15_R, 1.5V<br>~~ee~~|SSTL15, SSTL15_R<br>~~ee~~|50<br>~~ee~~|0<br>~~ee~~|VREF<br>~~ee~~|0.75<br>~~ee~~|
|SSTL (Stub Series Terminated Logic),<br>Class I & Class II, 1.8V<br>~~ee~~|SSTL18_I, SSTL18_II<br>~~ee~~|50<br>~~ee~~|0<br>~~ee~~|VREF<br>~~ee~~|0.9<br>~~ee~~|
|DIFF_MOBILE_DDR, 1.8V<br>~~ee~~|DIFF_MOBILE_DDR<br>~~ee~~|50<br>~~ee~~|0<br>~~ee~~|VREF<br>~~ee~~|0.9<br>~~ee~~|
|DIFF_HSTL, Class I, 1.2V<br>~~ee~~<br>~~OO~~|DIFF_HSTL_I_12<br>~~ee~~<br>~~OO~~|50<br>~~ee~~<br>~~OO~~|0<br>~~ee~~<br>~~OO~~|VREF<br>~~ee~~<br>~~OO~~|0.6<br>~~ee~~<br>~~OO~~|
|DIFF_HSTL, Class I & II, 1.5V<br>~~OO~~<br>~~a~~|DIFF_HSTL_I, DIFF_HSTL_II<br>~~OO~~|50<br>~~OO~~|0<br>~~OO~~|VREF<br>~~OO~~|0.75<br>~~OO~~|
|DIFF_HSTL, Class I & II, 1.8V<br>~~a~~<br>~~ee~~|DIFF_HSTL_I_18, DIFF_HSTL_II_18<br>~~ee~~|50<br>~~ee~~|0<br>~~ee~~|VREF<br>~~ee~~|0.9<br>~~ee~~|
|DIFF_HSUL_12, 1.2V<br>~~ee~~<br>~~OO~~|DIFF_HSUL_12<br>~~ee~~<br>~~OO~~|50<br>~~ee~~<br>~~OO~~|0<br>~~ee~~<br>~~OO~~|VREF<br>~~ee~~<br>~~OO~~|0.6<br>~~ee~~<br>~~OO~~|
|DIFF_SSTL135/DIFF_SSTL135_R, 1.35V<br>~~OO~~<br>~~a~~|DIFF_SSTL135, DIFF_SSTL135_R<br>~~OO~~|50<br>~~OO~~|0<br>~~OO~~|VREF<br>~~OO~~|0.675<br>~~OO~~|
|DIFF_SSTL15/DIFF_SSTL15_R, 1.5V<br>~~a~~<br>~~ee~~|DIFF_SSTL15, DIFF_SSTL15_R<br>~~ee~~|50<br>~~ee~~|0<br>~~ee~~|VREF<br>~~ee~~|0.75<br>~~ee~~|
|DIFF_SSTL18, Class I & II, 1.8V<br>~~ee~~<br>~~OO~~|DIFF_SSTL18_I, DIFF_SSTL18_II<br>~~ee~~<br>~~OO~~|50<br>~~ee~~<br>~~OO~~|0<br>~~ee~~<br>~~OO~~|VREF<br>~~ee~~<br>~~OO~~|0.9<br>~~ee~~<br>~~OO~~|
|LVDS, 2.5V<br>~~OO~~<br>~~a~~|LVDS_25<br>~~OO~~|100<br>~~OO~~|0<br>~~OO~~|0(2)<br>~~OO~~|0<br>~~OO~~|
|BLVDS (Bus LVDS), 2.5V<br>~~a~~<br>~~ee~~|BLVDS_25<br>~~ee~~|100<br>~~ee~~|0<br>~~ee~~|0(2)<br>~~ee~~|0<br>~~ee~~|
|Mini LVDS, 2.5V<br>~~ee~~<br>~~OO~~|MINI_LVDS_25<br>~~ee~~<br>~~OO~~|100<br>~~ee~~<br>~~OO~~|0<br>~~ee~~<br>~~OO~~|0(2)<br>~~ee~~<br>~~OO~~|0<br>~~ee~~<br>~~OO~~|
|PPDS_25<br>~~OO~~<br>~~a~~|PPDS_25<br>~~OO~~|100<br>~~OO~~|0<br>~~OO~~|0(2)<br>~~OO~~|0<br>~~OO~~|
|RSDS_25<br>~~ee~~|RSDS_25<br>~~ee~~|100<br>~~ee~~|0<br>~~ee~~|0(2)<br>~~ee~~|0<br>~~ee~~|
|TMDS_33<br>~~ee~~<br>~~CF~~|TMDS_33<br>~~ee~~<br>~~CF~~|50<br>~~ee~~<br>~~CF~~|0<br>~~ee~~<br>~~CF~~|0(2)<br>~~ee~~<br>~~CF~~|3.3<br>~~ee~~<br>~~CF~~|
## **Notes:**
1. CREF is the capacitance of the probe, nominally 0 pF.
2. The value given is the differential output voltage.
DS181 (v1.27.1) July 3, 2024 **Product Specification**
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**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
## **Input/Output Logic Switching Characteristics**
_Table 21:_ **ILOGIC Switching Characteristics**
|**Symbol**<br>~~a~~|**Description**<br>~~a~~|**Speed Grade**<br>~~Oo~~<br>|**Speed Grade**<br>~~Oo~~<br>|**Speed Grade**<br>~~Oo~~<br>|**Speed Grade**<br>~~Oo~~<br>|**Speed Grade**<br>~~Oo~~<br>|**Speed Grade**<br>~~Oo~~<br>|**Units**|
|---|---|---|---|---|---|---|---|---|
|||**1.0V**<br>~~Oo~~<br>||||**0.95V**<br>~~Oo~~|**0.9V**<br>~~Oo~~||
|||**-3**<br>~~Oo~~<br>~~a~~|**-2/-2LE**<br>~~Oo~~|**-1**<br>~~Oo~~|**-1Q/-1M**<br>~~Oo~~|**-1LI**<br>~~Oo~~|**-2LE**<br>~~Oo~~||
|**Setup/Hold**<br>~~TT~~|||||||||
|TICE1CK/<br>TICKCE1<br>~~TT~~|CE1 pin setup/hold with respect to<br>CLK<br>~~TT~~|0.48/0.02<br>~~TT~~|0.54/0.02<br>~~TT~~|0.76/0.02<br>~~TT~~|0.76/0.02<br>~~TT~~|0.76/0.02<br>~~TT~~|0.50/–0.07<br>~~TT~~|ns<br>~~TT~~|
|TISRCK/<br>TICKSR|SR pin setup/hold with respect to<br>CLK|0.60/0.01|0.70/0.01|1.13/0.01|1.13/0.01|1.13/0.01|0.88/–0.35|ns|
|TIDOCK/<br>TIOCKD|D pin setup/hold with respect to CLK<br>without Delay|0.01/0.27|0.01/0.29|0.01/0.33|0.01/0.33|0.01/0.33|0.01/0.33|ns|
|TIDOCKD/<br>TIOCKDD|DDLY pin setup/hold with respect to<br>CLK (using IDELAY)|0.02/0.27|0.02/0.29|0.02/0.33|0.02/0.33|0.02/0.33|0.01/0.33|ns|
|**Combinatorial**|||||||||
|TIDI|D pin to O pin propagation delay, no<br>Delay|0.11|0.11|0.13|0.13|0.13|0.14|ns|
|TIDID|DDLY pin to O pin propagation delay<br>(using IDELAY)|0.11|0.12|0.14|0.14|0.14|0.15|ns|
|**Sequential Delays**|||||||||
|TIDLO|D pin to Q1 pin using flip-flop as a<br>latch without Delay|0.41|0.44|0.51|0.51|0.51|0.54|ns|
|TIDLOD|DDLY pin to Q1 pin using flip-flop as<br>a latch (using IDELAY)|0.41|0.44|0.51|0.51|0.51|0.55|ns|
|TICKQ|CLK to Q outputs|0.53|0.57|0.66|0.66<br>~~ee~~|0.66<br>~~ee~~|0.71|ns|
|TRQ_<br>ILOGIC<br>~~a~~|SR pin to OQ/TQ out<br>~~ee~~|0.96<br>~~ee~~|1.08<br>~~ee~~|1.32<br>~~ee~~|1.32<br>~~ee~~<br>~~ee~~|1.32<br>~~ee~~<br>~~ee~~|1.32<br>~~ee~~|ns<br>~~ee~~|
|TGSRQ_<br>ILOGIC<br>~~a~~|Global set/reset to Q outputs<br>~~ee~~|7.60<br>~~ee~~|7.60<br>~~ee~~|10.51<br>~~ee~~|10.51<br>~~ee~~<br>~~ee~~|10.51<br>~~ee~~<br>~~ee~~|11.39<br>~~ee~~|ns<br>~~ee~~|
|**Set/Reset**|||||||||
|TRPW_<br>ILOGIC|Minimum pulse width, SR inputs|0.61|0.72|0.72|0.72|0.72|0.72|ns, Min|
DS181 (v1.27.1) July 3, 2024 **Product Specification**
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**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
## _Table 22:_ **OLOGIC Switching Characteristics** _**(Cont’d)**_
|**Symbol**<br>**Description**<br>**Speed Grade**<br>**Units**<br>**1.0V**<br>**0.95V**<br>**0.9V**<br>**-3**<br>**-2/-2LE**<br>**-1**<br>**-1Q/-1M**<br>**-1LI**<br>**-2LE**<br>~~pT~~<br>~~|~~<br>~~a ee~~|
|---|
|**Combinatorial**<br>~~pC~~|
|TODQ<br>D1 to OQ out or T1 to TQ out<br>0.83<br>0.96<br>1.16<br>1.16<br>1.16<br>1.36<br>ns<br>~~ee~~<br>~~GG~~|
|**Sequential Delays**<br>~~pC~~|
|TOCKQ<br>CLK to OQ/TQ out<br>0.47<br>0.49<br>0.56<br>0.56<br>0.56<br>0.63<br>ns<br>TRQ_OLOGIC<br>SR pin to OQ/TQ out<br>0.72<br>0.80<br>0.95<br>0.95<br>0.95<br>1.12<br>ns<br>TGSRQ_OLOGIC<br>Global set/reset to Q outputs<br>7.60<br>7.60<br>10.51<br>10.51<br>10.51<br>11.39<br>ns<br>**Set/Reset**<br>TRPW_OLOGIC<br>Minimum pulse width, SR inputs<br>0.64<br>0.74<br>0.74<br>0.74<br>0.74<br>0.74<br>ns,<br>~~aGG~~<br>~~a~~<br>~~Ge GO~~<br>~~a a~~<br>~~GD~~<br>~~pC~~|
|Min|
|**Input Serializer/Deserializer Switching Characteristics**|
|_Table 23:_ **ISERDES Switching Characteristics**|
|**Symbol**<br>**Description**<br>**Speed Grade**<br>**Units**<br>**1.0V**<br>**0.95V**<br>**0.9V**<br>**-3**<br>**-2/-2LE**<br>**-1**<br>**-1Q/-1M**<br>**-1LI**<br>**-2LE**<br>~~pt~~<br>~~Bf~~<br>~~er~~<br>~~a~~|
|**Setup/Hold for Control Lines**<br>~~PC~~|
|TISCCK_BITSLIP/<br>BITSLIP pin setup/hold with<br>0.01/0.14<br>0.02/0.15<br>0.02/0.17<br>0.02/0.17<br>0.02/0.17<br>0.02/0.21<br>ns|
|TISCKC_BITSLIP<br>respect to CLKDIV|
|TISCCK_CE/<br>TISCKC_CE(2)<br>CE pin setup/hold with respect to<br>CLK (for CE1)<br>0.45/–0.01 0.50/–0.01 0.72/–0.01 0.72/–0.01 0.72/–0.01 0.45/–0.11<br>ns|
|TISCCK_CE2/<br>TISCKC_CE2(2)<br>CE pin setup/hold with respect to<br>CLKDIV (for CE2)<br>–0.10/0.33 –0.10/0.36 –0.10/0.40 –0.10/0.40 –0.10/0.40 –0.17/0.40<br>ns|
|**Setup/Hold for Data Lines**<br>~~pC~~|
|TISDCK_D/<br>D pin setup/hold with respect to<br>–0.02/0.12 –0.02/0.14 –0.02/0.17 –0.02/0.17 –0.02/0.17 –0.04/0.19<br>ns|
|TISCKD_D<br>CLK|
|TISDCK_DDLY/<br>TISCKD_DDLY<br>DDLY pin setup/hold with respect<br>to CLK (using IDELAY)(1)<br>–0.02/0.12 –0.02/0.14 –0.02/0.17 –0.02/0.17 –0.02/0.17 –0.03/0.19<br>ns|
|TISDCK_D_DDR/<br>D pin setup/hold with respect to<br>–0.02/0.12 –0.02/0.14 –0.02/0.17 –0.02/0.17 –0.02/0.17 –0.04/0.19<br>ns|
|TISCKD_D_DDR<br>CLK at DDR mode|
|TISDCK_DDLY_DDR/<br>DDLY pin setup/hold with respect<br>0.12/0.12<br>0.14/0.14<br>0.17/0.17<br>0.17/0.17<br>0.17/0.17<br>0.19/0.19<br>ns|
|TISCKD_DDLY_DDR<br>to CLK at DDR mode (using<br>IDELAY)(1)|
|**Sequential Delays**<br>~~pn~~|
|TISCKO_Q<br>CLKDIV to out at Q pin<br>0.53<br>0.54<br>0.66<br>0.66<br>0.66<br>0.67<br>ns<br>~~IGG~~|
|**Propagation Delays**<br>~~pC~~|
|TISDO_DO<br>D input to DO output pin<br>0.11<br>0.11<br>0.13<br>0.13<br>0.13<br>0.14<br>ns<br>~~DG~~|
|**Notes:**|
1. Recorded at 0 tap value.
2. TISCCK_CE2 and TISCKC_CE2 are reported as TISCCK_CE/TISCKC_CE in the timing report.
DS181 (v1.27.1) July 3, 2024 **Product Specification**
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**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
## **Output Serializer/Deserializer Switching Characteristics**
_Table 24:_ **OSERDES Switching Characteristics**
|**Symbol**<br>~~Bf~~|**Description**<br>~~Bf~~|**Speed Grade**<br>~~pT~~|**Speed Grade**<br>~~pT~~|**Speed Grade**<br>~~pT~~|**Speed Grade**<br>~~pT~~|**Speed Grade**<br>~~pT~~|**Speed Grade**<br>~~pT~~|**Units**|
|---|---|---|---|---|---|---|---|---|
|||**1.0V**<br>~~pT~~||||**0.95V**<br>~~pT~~|**0.9V**<br>~~pT~~||
|||**-3**<br>~~pT~~<br>~~a~~|**-2/-2LE**<br>~~pT~~|**-1**<br>~~pT~~|**-1Q/-1M**<br>~~pT~~|**-1LI**<br>~~pT~~|**-2LE**<br>~~pT~~||
|**Setup/Hold**<br>~~pT~~<br>~~Bf~~<br>~~pT~~|||||||||
|TOSDCK_D/<br>TOSCKD_D<br>~~pT~~|D input setup/hold with respect to<br>CLKDIV<br>~~pT~~|0.42/0.03<br>~~pT~~|0.45/0.03<br>~~pT~~|0.63/0.03<br>~~pT~~|0.63/0.08<br>~~pT~~|0.63/0.03<br>~~pT~~|0.44/–0.02<br>~~pT~~|ns<br>~~pT~~|
|TOSDCK_T/<br>TOSCKD_T(1)|T input setup/hold with respect to<br>CLK|0.69/–0.13|0.73/–0.13|0.88/–0.13|0.88/–0.13|0.88/–0.13|0.66/–0.25|ns|
|TOSDCK_T2/<br>TOSCKD_T2(1)|T input setup/hold with respect to<br>CLKDIV|0.31/–0.13|0.34/–0.13|0.39/–0.13|0.39/–0.13|0.39/–0.13|0.46/–0.25|ns|
|TOSCCK_OCE/<br>TOSCKC_OCE|OCE input setup/hold with respect<br>to CLK|0.32/0.58|0.34/0.58|0.51/0.58|0.51/0.58|0.51/0.58|0.28/–0.04|ns|
|TOSCCK_S|SR (reset) input setup with respect<br>to CLKDIV|0.47|0.52|0.85|0.85|0.85|0.70|ns|
|TOSCCK_TCE/<br>TOSCKC_TCE|TCE input setup/hold with respect<br>to CLK|0.32/0.01|0.34/0.01|0.51/0.01|0.51/0.10|0.51/0.01|0.24/0.00|ns|
|**Sequential Delays**<br>~~pC~~<br>~~GO~~<br>~~ee~~|||||||||
|TOSCKO_OQ<br>~~eG~~<br>~~ee~~|Clock to out from CLK to OQ<br>~~eG~~<br>|0.40<br>~~eG~~<br>|0.42<br>~~eG~~<br>|0.48<br>~~eG~~<br>~~GO~~<br>|0.48<br>~~eG~~<br>~~GO~~<br><br>~~DO~~|0.48<br>~~eG~~<br>~~GO~~<br>|0.54<br>~~eG~~<br>|ns<br>~~eG~~<br>|
|TOSCKO_TQ<br>~~eG~~<br>~~ee~~|Clock to out from CLK to TQ<br>~~eG~~<br>~~Ge~~|0.47<br>~~eG~~<br>~~Ge~~|0.49<br>~~eG~~<br>~~Ge~~|0.56<br>~~eG~~<br>~~GO~~<br>~~Ge~~|0.56<br>~~eG~~<br>~~GO~~<br>~~Ge~~<br>~~DO~~|0.56<br>~~eG~~<br>~~GO~~<br>~~Ge~~|0.63<br>~~eG~~<br>~~Ge~~|ns<br>~~eG~~<br>~~Ge~~|
|**Combinatorial**<br>~~GO~~<br>~~eeGe~~<br>~~DO~~<br>~~pC~~<br>~~CO~~|||||||||
|TOSDO_TTQ<br>~~eG~~|T input to TQ Out<br>~~eG~~|0.83<br>~~eG~~|0.92<br>~~eG~~|1.11<br>~~eG~~<br>~~CO~~|1.11<br>~~eG~~<br>~~CO~~|1.11<br>~~eG~~|1.18<br>~~eG~~|ns<br>~~eG~~|
1. TOSDCK_T2 and TOSCKD_T2 are reported as TOSDCK_T/TOSCKD_T in the timing report.
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**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
## **Input/Output Delay Switching Characteristics**
## _Table 25:_ **Input/Output Delay Switching Characteristics**
|**Symbol**|**Description**<br>~~a~~|**Speed Grade**<br>~~a~~|**Speed Grade**<br>~~a~~|**Speed Grade**<br>~~a~~|**Speed Grade**<br>~~a~~|**Speed Grade**<br>~~a~~|**Speed Grade**<br>~~a~~|**Units**|
|---|---|---|---|---|---|---|---|---|
|||**1.0V**<br>~~a~~||||**0.95V**|**0.9V**||
|||**-3**<br>~~a~~|**-2/-2LE**|**-1**|**-1Q/-1M**|**-1LI**|**-2LE**||
|**IDELAYCTRL**<br>~~TT~~|||||||||
|TDLYCCO_RDY<br>~~TT~~<br>~~>~~|Reset to ready for IDELAYCTRL<br>~~TT~~<br>~~>~~|3.67<br>~~TT~~<br>~~FF~~|3.67<br>~~TT~~<br>~~FF~~|3.67<br>~~TT~~|3.67<br>~~TT~~|3.67<br>~~TT~~|3.67<br>~~TT~~|µs<br>~~TT~~|
|FIDELAYCTRL_REF|Attribute REFCLK<br>frequency = 200.00(1)|200.00|200.00|200.00|200.00|200.00|200.00|MHz|
||Attribute REFCLK<br>frequency = 300.00(1)|300.00|300.00|300.00|300.00|300.00|300.00|MHz|
||Attribute REFCLK<br>frequency = 400.00(1)|400.00|400.00|N/A|N/A|N/A|N/A|MHz|
|IDELAYCTRL_REF_<br>PRECISION<br>~~a~~|REFCLK precision|±10|±10|±10|±10|±10|±10|MHz|
|TIDELAYCTRL_RPW<br>~~a~~<br>~~OO~~|Minimum Reset pulse width<br>~~OO~~|59.28|59.28|59.28|59.28|59.28|59.28|ns|
|**IDELAY**<br>~~a~~<br>~~OO~~|||||||||
|TIDELAYRESOLUTION<br>~~OO~~<br>~~a~~|IDELAY chain delay resolution<br>~~OO~~<br>~~a~~|1/(32 x 2 x FREF)<br>~~a~~||||||µs<br>~~a~~|
|TIDELAYPAT_JIT|Pattern dependent period jitter in<br>delay chain for clock pattern.(2)|0|0|0|0|0|0|ps<br>per tap|
||Pattern dependent period jitter in<br>delay chain for random data<br>pattern (PRBS 23)(3)|±5|±5|±5|±5|±5|±5|ps<br>per tap|
||Pattern dependent period jitter in<br>delay chain for random data<br>pattern (PRBS 23)(4)|±9|±9|±9|±9|±9|±9|ps<br>per tap|
|TIDELAY_CLK_MAX|Maximum frequency of CLK input<br>to IDELAY|680.00|680.00|600.00|600.00|600.00|520.00|MHz|
|TIDCCK_CE/<br>TIDCKC_CE|CE pin setup/hold with respect to<br>C for IDELAY|0.12/0.11|0.16/0.13|0.21/0.16|0.21/0.16|0.21/0.16|0.14/0.16|ns|
|TIDCCK_INC/<br>TIDCKC_INC|INC pin setup/hold with respect to<br>C for IDELAY|0.12/0.16|0.14/0.18|0.16/0.22|0.16/0.23|0.16/0.22|0.10/0.23|ns|
|TIDCCK_RST/<br>TIDCKC_RST|RST pin setup/hold with respect<br>to C for IDELAY|0.15/0.09|0.16/0.11|0.18/0.14|0.18/0.14|0.18/0.14|0.22/0.19|ns|
|TIDDO_IDATAIN|Propagation delay through<br>IDELAY|Note 5|Note 5|Note 5|Note 5|Note 5|Note 5|ps|
## **Notes:**
1. Average Tap Delay at 200 MHz = 78 ps, at 300 MHz = 52 ps, and at 400 MHz = 39 ps.
2. When HIGH_PERFORMANCE mode is set to TRUE or FALSE.
3. When HIGH_PERFORMANCE mode is set to TRUE.
4. When HIGH_PERFORMANCE mode is set to FALSE.
5. Delay depends on IDELAY tap setting. See the timing report for actual values.
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DS181 (v1.27.1) July 3, 2024 **Product Specification**
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**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 26:_ **IO_FIFO Switching Characteristics**
|**Symbol**<br>~~Pf~~|**Description**<br>~~Pf~~|**Speed Grade**<br>~~OO~~|**Speed Grade**<br>~~OO~~|**Speed Grade**<br>~~OO~~|**Speed Grade**<br>~~OO~~|**Speed Grade**<br>~~OO~~|**Speed Grade**<br>~~OO~~|**Units**<br>~~OO~~|
|---|---|---|---|---|---|---|---|---|
|||**1.0V**<br>~~OO~~||||**0.95V**<br>~~OO~~|**0.9V**<br>~~OO~~||
|||**-3**<br>~~OO~~<br>~~a~~|**-2/-2LE**<br>~~OO~~|**-1**<br>~~OO~~|**-1Q/-1M**<br>~~OO~~|**-1LI**<br>~~OO~~|**-2LE**<br>~~OO~~||
|**IO_FIFO Clock to Out Delays**<br>~~OO~~<br>~~Pf~~<br>~~TT~~|||||||||
|TOFFCKO_DO<br>~~TT~~<br>~~a~~|RDCLK to Q outputs<br>~~TT~~|0.55<br>~~TT~~|0.60<br>~~TT~~|0.68<br>~~TT~~|0.68<br>~~TT~~|0.68<br>~~TT~~|0.81<br>~~TT~~|ns<br>~~TT~~|
|TCKO_FLAGS<br>~~a~~<br>~~a CC~~|Clock to IO_FIFO flags<br>~~CC~~|0.55<br>~~CC~~|0.61<br>~~CC~~|0.77<br>~~CC~~|0.77<br>~~CC~~|0.77<br>~~CC~~|0.79<br>~~CC~~|ns<br>~~CC~~|
|**Setup/Hold**<br>~~a CC~~|||||||||
|TCCK_D/TCKC_D<br>~~a~~|D inputs to WRCLK<br>~~ee~~|0.47/0.02<br>~~ee~~|0.51/0.02<br>~~ee~~|0.58/0.02<br>~~ee~~|0.58/0.18<br>~~ee~~|0.58/0.02<br>~~ee~~|0.76/0.09<br>~~ee~~|ns<br>~~ee~~|
|TIFFCCK_WREN/<br>TIFFCKC_WREN<br>~~a~~|WREN to WRCLK<br>~~ee~~|0.42/–0.01<br>~~ee~~|0.47/–0.01<br>~~ee~~|0.53/–0.01<br>~~ee~~|0.53/–0.01<br>~~ee~~|0.53/–0.01<br>~~ee~~|0.70/–0.05<br>~~ee~~|ns<br>~~ee~~|
|TOFFCCK_RDEN/<br>TOFFCKC_RDEN<br>~~a~~|RDEN to RDCLK<br>~~ee~~|0.53/0.02<br>~~ee~~|0.58/0.02<br>~~ee~~|0.66/0.02<br>~~ee~~|0.66/0.02<br>~~ee~~|0.66/0.02<br>~~ee~~|0.79/–0.02<br>~~ee~~|ns<br>~~ee~~|
|**Minimum Pulse Width**|||||||||
|TPWH_IO_FIFO<br>~~a~~|RESET, RDCLK, WRCLK|1.62|2.15|2.15|2.15|2.15|2.15|ns|
|TPWL_IO_FIFO<br>~~a~~<br>~~a~~|RESET, RDCLK, WRCLK|1.62|2.15|2.15|2.15|2.15|2.15|ns|
|**Maximum Frequency**<br>~~a~~|||||||||
|FMAX<br>~~a~~|RDCLK and WRCLK|266.67|200.00|200.00|200.00|200.00|200.00|MHz|
DS181 (v1.27.1) July 3, 2024 **Product Specification**
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**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
## **CLB Switching Characteristics**
_Table 27:_ **CLB Switching Characteristics**
|**Symbol**<br>~~se~~|**Description**<br>~~Oo~~<br>~~se~~|**Speed Grade**<br>~~Oo~~<br>~~se~~|**Speed Grade**<br>~~Oo~~<br>~~se~~|**Speed Grade**<br>~~Oo~~<br>~~se~~|**Speed Grade**<br>~~Oo~~<br>~~se~~|**Speed Grade**<br>~~Oo~~<br>~~se~~|**Speed Grade**<br>~~Oo~~<br>~~se~~|**Units**|
|---|---|---|---|---|---|---|---|---|
|||**1.0V**<br>~~Oo~~<br>~~se~~||||**0.95V**<br>~~se~~|**0.9V**<br>~~se~~||
|||**-3**<br>~~se~~<br>~~a~~|**-2/-2LE**<br>~~se~~<br>~~a~~|**-1**<br>~~se~~<br>~~a~~|**-1Q/-1M**<br>~~se~~<br>~~a~~|**-1LI**<br>~~se~~<br>~~a~~|**-2LE**<br>~~se~~<br>~~a~~||
|**Combinatorial Delays**<br>~~TO~~|||||||||
|TILO<br>~~TO~~<br>~~**a**~~|An – Dn LUT address to A<br>~~TO~~<br>~~ee~~|0.10<br>~~TO~~<br>~~ee~~|0.11<br>~~TO~~<br>~~ee~~|0.13<br>~~TO~~<br>~~ee~~|0.13<br>~~TO~~|0.13<br>~~TO~~<br>~~ee~~|0.15<br>~~TO~~<br>~~ee~~|ns, Max<br>~~TO~~<br>~~ee~~|
|TILO_2<br>~~**a**~~|An – Dn LUT address to<br>AMUX/CMUX<br>~~ee~~|0.27<br>~~ee~~|0.30<br>~~ee~~|0.36<br>~~ee~~|0.36|0.36<br>~~ee~~|0.41<br>~~ee~~|ns, Max<br>~~ee~~|
|TILO_3<br>~~**a**~~|An – Dn LUT address to BMUX_A<br>~~ee ~~|0.42<br> ~~ee~~|0.46<br>~~ee ~~|0.55<br> ~~ee~~|0.55|0.55<br>~~ee~~|0.65<br>~~ee~~|ns, Max<br>~~ee~~|
|TITO<br>~~a~~|An – Dn inputs to A – D Q outputs<br>~~a~~|0.94<br>~~a~~|1.05<br>~~a~~|1.27<br>~~a~~|1.27<br>~~a~~|1.27<br>~~a~~|1.51<br>~~a~~|ns, Max<br>~~a~~|
|TAXA<br>~~a~~<br>~~a~~|AX inputs to AMUX output<br>~~a~~<br>~~a~~<br>~~a~~|0.62<br>~~a~~<br>~~a~~|0.69<br>~~a~~<br>~~a~~|0.84<br>~~a~~<br>~~a~~|0.84<br>~~a~~<br>~~a~~|0.84<br>~~a~~<br>~~a~~|1.01<br>~~a~~<br>~~a~~|ns, Max<br>~~a~~<br>~~a~~|
|TAXB<br>~~a~~<br>~~a~~|AX inputs to BMUX output<br>~~a~~<br>~~a~~<br>~~a~~|0.58<br>~~a~~<br>~~a~~|0.66<br>~~a~~<br>~~a~~|0.83<br>~~a~~<br>~~a~~|0.83<br>~~a~~<br>~~a~~|0.83<br>~~a~~<br>~~a~~|0.98<br>~~a~~<br>~~a~~|ns, Max<br>~~a~~<br>~~a~~|
|TAXC<br>~~a~~|AX inputs to CMUX output<br>~~a~~|0.60<br>~~a~~|0.68<br>~~a~~|0.82<br>~~a~~|0.82<br>~~a~~|0.82<br>~~a~~|0.98<br>~~a~~|ns, Max<br>~~a~~|
|TAXD<br>~~a~~<br>~~a~~|AX inputs to DMUX output<br>~~a~~<br>~~a~~<br>~~a~~|0.68<br>~~a~~<br>~~a~~|0.75<br>~~a~~<br>~~a~~|0.90<br>~~a~~<br>~~a~~|0.90<br>~~a~~<br>~~a~~|0.90<br>~~a~~<br>~~a~~|1.08<br>~~a~~<br>~~a~~|ns, Max<br>~~a~~<br>~~a~~|
|TBXB<br>~~a~~<br>~~a~~|BX inputs to BMUX output<br>~~a~~<br>~~a~~|0.51<br>~~a~~|0.57<br>~~a~~|0.69<br>~~a~~|0.69<br>~~a~~|0.69<br>~~a~~|0.82<br>~~a~~|ns, Max<br>~~a~~|
|TBXD<br>~~a~~|BX inputs to DMUX output<br>~~a~~|0.62|0.69|0.82|0.82|0.82|0.99|ns, Max|
|TCXC<br>~~a ~~<br>~~eC~~|CX inputs to CMUX output<br> ~~a~~<br>~~eC~~|0.42<br>~~eC~~|0.48<br>~~eC~~|0.58<br>~~eC~~|0.58<br>~~eC~~|0.58<br>~~eC~~|0.69<br>~~eC~~|ns, Max<br>~~eC~~|
|TCXD<br>~~eC~~<br>~~a~~|CX inputs to DMUX output<br>~~eC~~<br>~~a~~|0.53<br>~~eC~~<br>~~a~~|0.59<br>~~eC~~<br>~~a~~|0.71<br>~~eC~~<br>~~a~~|0.71<br>~~eC~~<br>~~a~~|0.71<br>~~eC~~<br>~~a~~|0.86<br>~~eC~~<br>~~a~~|ns, Max<br>~~eC~~<br>~~a~~|
|TDXD<br>~~a~~|DX inputs to DMUX output<br>~~a~~|0.52<br>~~a~~|0.58<br>~~a~~|0.70<br>~~a~~|0.70<br>~~a~~|0.70<br>~~a~~|0.84<br>~~a~~|ns, Max<br>~~a~~|
|**Sequential Delays**<br>~~a~~|||||||||
|TCKO<br>~~a~~|Clock to AQ – DQ outputs<br>~~a~~|0.40<br>~~a~~|0.44<br>~~a~~|0.53<br>~~a~~|0.53<br>~~a~~|0.53<br>~~a~~|0.62<br>~~a~~|ns, Max<br>~~a~~|
|TSHCKO<br>~~a~~|Clock to AMUX – DMUX outputs<br>~~a~~|0.47<br>~~a~~|0.53<br>~~a~~|0.66<br>~~a~~|0.66<br>~~a~~|0.66<br>~~a~~|0.73<br>~~a~~|ns, Max<br>~~a~~|
|**Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK**<br>~~a~~|||||||||
|TAS/TAH|AN– DNinput to CLK on A – D<br>flip-flops|0.07/0.12|0.09/0.14|0.11/0.18|0.11/0.28|0.11/0.18|0.11/0.22|ns, Min|
|TDICK/<br>TCKDI|AX– DXinput to CLK on A – D<br>flip-flops|0.06/0.19|0.07/0.21|0.09/0.26|0.09/0.35|0.09/0.26|0.09/0.33|ns, Min|
||AX– DXinput through MUXs and/or<br>carry logic to CLK on A – D<br>flip-flops|0.59/0.08|0.66/0.09|0.81/0.11|0.81/0.20|0.81/0.11|0.97/0.15|ns, Min|
|TCECK_CLB/<br>TCKCE_CLB|CE input to CLK on A – D flip-flops|0.15/0.00|0.17/0.00|0.21/0.01|0.21/0.13|0.21/0.01|0.34/–0.01|ns, Min|
|TSRCK/<br>TCKSR|SR input to CLK on A – D flip-flops|0.38/0.03|0.43/0.04|0.53/0.05|0.53/0.18|0.53/0.05|0.62/0.19|ns, Min|
|**Set/Reset**<br>~~a~~|||||||||
|TSRMIN<br>~~a~~<br>~~a~~|SR input minimum pulse width<br>~~a~~<br>~~a~~|0.52<br>~~a~~<br>~~a~~|0.78<br>~~a~~<br>~~a~~|1.04<br>~~a~~<br>~~a~~|1.04<br>~~a~~<br>~~a~~|1.04<br>~~a~~<br>~~a~~|0.95<br>~~a~~<br>~~a~~|ns, Min<br>~~a~~<br>~~a~~|
|TRQ<br>~~a~~|Delay from SR input to AQ – DQ<br>flip-flops<br>~~a~~|0.53<br>~~a~~|0.59<br>~~a~~|0.71<br>~~a~~|0.71<br>~~a~~|0.71<br>~~a~~|0.83<br>~~a~~|ns, Max<br>~~a~~|
|TCEO|Delay from CE input to AQ – DQ<br>flip-flops|0.52|0.58|0.70|0.70|0.70|0.83|ns, Max|
|FTOG|Toggle frequency (for export<br>control)|1412|1286|1098|1098|1098|1098|MHz|
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**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
## **CLB Distributed RAM Switching Characteristics (SLICEM Only)**
_Table 28:_ **CLB Distributed RAM Switching Characteristics**
|**Symbol**<br>~~Bf~~|**Description**<br>~~Bf~~<br>~~a~~|**Speed Grade**<br>~~a~~|**Speed Grade**<br>~~a~~|**Speed Grade**<br>~~a~~|**Speed Grade**<br>~~a~~|**Speed Grade**<br>~~a~~|**Speed Grade**<br>~~a~~|**Units**|
|---|---|---|---|---|---|---|---|---|
|||**1.0V**<br>~~a~~||||**0.95V**|**0.9V**||
|||**-3**<br>~~a~~|**-2/-2LE**|**-1**|**-1Q/-1M**|**-1LI**|**-2LE**||
|**Sequential Delays**<br>~~TT~~|||||||||
|TSHCKO<br>~~TT~~<br>~~a~~|Clock to A – B outputs<br>~~TT~~|0.98<br>~~TT~~|1.09<br>~~TT~~|1.32<br>~~TT~~|1.32<br>~~TT~~|1.32<br>~~TT~~|1.54<br>~~TT~~|ns, Max<br>~~TT~~|
|TSHCKO_1<br>~~a~~<br>~~OO~~|Clock to AMUX – BMUX outputs<br>|1.37<br>|1.53<br>|1.86<br>|1.86<br>|1.86<br>|2.18<br>|ns, Max<br>|
|**Setup and Hold Times Before/After Clock CLK**<br>~~a~~<br>~~OO~~|||||||||
|TDS_LRAM/<br>TDH_LRAM<br>~~OO~~|A – D inputs to CLK<br>|0.54/0.28<br>|0.60/0.30<br>|0.72/0.35<br>|0.72/0.37<br>|0.72/0.35<br>|0.96/0.40<br>|ns, Min<br>|
|TAS_LRAM/<br>TAH_LRAM<br>~~eer~~|Address An inputs to clock<br>~~eer~~|0.27/0.55<br>~~eer~~|0.30/0.60<br>~~eer~~|0.37/0.70<br>~~eer~~|0.37/0.71<br>~~eer~~|0.37/0.70<br>~~eer~~|0.43/0.71<br>~~eer~~|ns, Min<br>~~eer~~|
||Address An inputs through MUXs<br>and/or carry logic to clock<br>~~eer~~|0.69/0.18<br>~~eer~~|0.77/0.21<br>~~eer~~|0.94/0.26<br>~~eer~~|0.94/0.35<br>~~eer~~|0.94/0.26<br>~~eer~~|1.11/0.31<br>~~eer~~|ns, Min<br>~~eer~~|
|TWS_LRAM/<br>TWH_LRAM<br>~~eer~~|WE input to clock<br>~~eer~~|0.38/0.10<br>~~eer~~|0.43/0.12<br>~~eer~~|0.53/0.17<br>~~eer~~|0.53/0.17<br>~~eer~~|0.53/0.17<br>~~eer~~|0.62/0.13<br>~~eer~~|ns, Min<br>~~eer~~|
|TCECK_LRAM/<br>TCKCE_LRAM|CE input to CLK|0.39/0.10|0.44/0.11|0.53/0.17|0.53/0.17|0.53/0.17|0.63/0.12|ns, Min|
|**Clock CLK**|||||||||
|TMPW_LRAM<br>~~a~~|Minimum pulse width<br>~~a~~|1.05<br>~~a~~|1.13<br>~~a~~|1.25<br>~~a~~|1.25<br>~~a~~|1.25<br>~~a~~|1.61<br>~~a~~|ns, Min<br>~~a~~|
|TMCP<br>~~a~~<br>~~a~~|Minimum clock period<br>~~a~~<br>~~a~~|2.10<br>~~a~~<br>~~a~~|2.26<br>~~a~~<br>~~a~~|2.50<br>~~a~~<br>~~a~~|2.50<br>~~a~~<br>~~a~~|2.50<br>~~a~~<br>~~a~~|3.21<br>~~a~~<br>~~a~~|ns, Min<br>~~a~~<br>~~a~~|
## **Notes:**
1. TSHCKO also represents the CLK to XMUX output. Refer to the timing report for the CLK to XMUX path.
## **CLB Shift Register Switching Characteristics (SLICEM Only)**
_Table 29:_ **CLB Shift Register Switching Characteristics**
|**Symbol**<br>~~Bf~~|**Description**<br>~~Bf ~~|**Speed Grade**<br>~~OO~~<br>~~Ee~~|**Speed Grade**<br>~~OO~~<br>~~Ee~~|**Speed Grade**<br>~~OO~~<br>~~Ee~~|**Speed Grade**<br>~~OO~~<br>~~Ee~~|**Speed Grade**<br>~~OO~~<br>~~Ee~~|**Speed Grade**<br>~~OO~~<br>~~Ee~~|**Units**<br>~~OO~~|
|---|---|---|---|---|---|---|---|---|
|||**1.0V**<br>~~OO~~<br>~~Ee~~||||**0.95V**<br>~~OO~~<br>~~Ee~~|**0.9V**<br>~~OO~~<br>~~Ee~~||
|||**-3**<br>~~OO~~<br> ~~Ee~~<br>~~a~~|**-2/-2LE**<br>~~OO~~<br>~~Ee~~|**-1**<br>~~OO~~<br>~~Ee~~|**-1Q/-1M**<br>~~OO~~<br>~~Ee~~|**-1LI**<br>~~OO~~<br>~~Ee~~|**-2LE**<br>~~OO~~<br>~~Ee~~||
|**Sequential Delays**<br>~~OO~~<br>~~Bf ~~<br>~~TT~~|||||||||
|TREG<br>~~TT~~<br>~~a OC~~|Clock to A – D outputs<br>~~TT~~<br>~~OC~~|1.19<br>~~TT~~<br>~~OC~~|1.33<br>~~TT~~<br>~~OC~~|1.61<br>~~TT~~<br>~~OC~~|1.61<br>~~TT~~<br>~~OC~~|1.61<br>~~TT~~<br>~~OC~~|1.89<br>~~TT~~<br>~~OC~~|ns, Max<br>~~TT~~<br>~~OC~~|
|TREG_MUX<br>~~a OC~~<br>~~a eC~~|Clock to AMUX – DMUX output<br>~~OC~~<br>~~eC~~|1.58<br>~~OC~~<br>~~eC~~|1.77<br>~~OC~~<br>~~eC~~|2.15<br>~~OC~~<br>~~eC~~|2.15<br>~~OC~~<br>~~eC~~|2.15<br>~~OC~~<br>~~eC~~|2.53<br>~~OC~~<br>~~eC~~|ns, Max<br>~~OC~~<br>~~eC~~|
|TREG_M31<br>~~a eC~~<br>~~rs~~|Clock to DMUX output via M31<br>output<br>~~eC~~<br>~~rs~~|1.12<br>~~eC~~<br>~~rs~~|1.23<br>~~eC~~<br>~~rs~~|1.46<br>~~eC~~<br>~~rs~~|1.46<br>~~eC~~<br>~~rs~~|1.46<br>~~eC~~<br>~~rs~~|1.68<br>~~eC~~<br>~~rs~~|ns, Max<br>~~eC~~<br>~~rs~~|
|**Setup and Hold Times Before/After Clock CLK**<br>~~rs~~|||||||||
|TWS_SHFREG/<br>TWH_SHFREG<br>~~rs~~|WE input<br>~~rs~~|0.37/0.10<br>~~rs~~|0.41/0.12<br>~~rs~~|0.51/0.17<br>~~rs~~|0.51/0.17<br>~~rs~~|0.51/0.17<br>~~rs~~|0.59/0.13<br>~~rs~~|ns, Min<br>~~rs~~|
|TCECK_SHFREG/<br>TCKCE_SHFREG|CE input to CLK|0.37/0.10|0.42/0.11|0.52/0.17|0.52/0.17|0.52/0.17|0.60/0.12|ns, Min|
|TDS_SHFREG/<br>TDH_SHFREG|A – D inputs to CLK|0.33/0.34|0.37/0.37|0.44/0.43|0.44/0.44|0.44/0.43|0.54/0.55|ns, Min|
|**Clock CLK**|||||||||
|TMPW_SHFREG<br>~~a~~|Minimum pulse width|0.77|0.86|0.98|0.98|0.98|1.22|ns, Min|
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**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
## **Block RAM and FIFO Switching Characteristics**
_Table 30:_ **Block RAM and FIFO Switching Characteristics**
|**Symbol**<br>~~pf~~|**Description**<br>~~pf ~~|**Speed Grade**<br>~~pt~~<br>|**Speed Grade**<br>~~pt~~<br>|**Speed Grade**<br>~~pt~~<br>|**Speed Grade**<br>~~pt~~<br>|**Speed Grade**<br>~~pt~~<br>|**Speed Grade**<br>~~pt~~<br>|**Units**<br>~~pt~~<br>~~a~~|
|---|---|---|---|---|---|---|---|---|
|||**1.0V**<br>~~pt~~<br>||||**0.95V**<br>~~pt~~<br>|**0.9V**<br>~~pt~~<br>||
|||**-3**<br>~~pt~~<br> ~~a~~|**-2/-2LE**<br>~~pt~~<br>~~a~~|**-1**<br>~~pt~~<br>~~a~~|**-1Q/-1M**<br>~~pt~~<br>~~a~~|**-1LI**<br>~~pt~~<br>~~a~~|**-2LE**<br>~~pt~~<br>~~a~~||
|**Block RAM and FIFO Clock-to-Out Delays**<br>~~|~~|||||||||
|TRCKO_DOand<br>TRCKO_DO_REG(1)<br>~~|~~|Clock CLK to DOUT<br>output (without output<br>register)(2)(3)<br>~~|~~|1.85<br>~~|~~|2.13<br>~~|~~|2.46<br>~~|~~|2.46<br>~~|~~|2.46<br>~~|~~|2.87<br>~~|~~|ns, Max<br>~~|~~|
||Clock CLK to DOUT<br>output (with output<br>register)(4)(5)|0.64|0.74|0.89|0.89|0.89|1.02|ns, Max|
|TRCKO_DO_ECCand<br>TRCKO_DO_ECC_REG|Clock CLK to DOUT<br>output with ECC (without<br>output register)(2)(3)|2.77|3.04|3.84|3.84|3.84|5.30|ns, Max|
||Clock CLK to DOUT<br>output with ECC (with<br>output register)(4)(5)|0.73|0.81|0.94|0.94|0.94|1.11|ns, Max|
|TRCKO_DO_CASCOUTand<br>TRCKO_DO_CASCOUT_REG|Clock CLK to DOUT<br>output with cascade<br>(without output register)(2)|2.61|2.88|3.30|3.30|3.30|3.76|ns, Max|
||Clock CLK to DOUT<br>output with cascade (with<br>output register)(4)|1.16|1.28|1.46|1.46|1.46|1.56|ns, Max|
|TRCKO_FLAGS|Clock CLK to FIFO flags<br>outputs(6)|0.76|0.87|1.05|1.05|1.05|1.14|ns, Max|
|TRCKO_POINTERS|Clock CLK to FIFO<br>pointers outputs(7)|0.94|1.02|1.15|1.15|1.15|1.30|ns, Max|
|TRCKO_PARITY_ECC|Clock CLK to ECCPARITY<br>in ECC encode only mode|0.78|0.85|0.94|0.94|0.94|1.10|ns, Max|
|TRCKO_SDBIT_ECCand<br>TRCKO_SDBIT_ECC_REG|Clock CLK to BITERR<br>(without output register)|2.56|2.81|3.55|3.55|3.55|4.90|ns, Max|
||Clock CLK to BITERR<br>(with output register)|0.68|0.76|0.89|0.89|0.89|1.05|ns, Max|
|TRCKO_RDADDR_ECCand<br>TRCKO_RDADDR_ECC_REG|Clock CLK to RDADDR<br>output with ECC (without<br>output register)|0.75|0.88|1.07|1.07|1.07|1.15|ns, Max|
||Clock CLK to RDADDR<br>output with ECC (with<br>output register)|0.84|0.93|1.08|1.08|1.08|1.29|ns, Max|
|**Setup and Hold Times Before/After Clock CLK**<br>~~|~~|||||||||
|TRCCK_ADDRA/<br>TRCKC_ADDRA<br>~~|~~|ADDR inputs(8)<br>~~|~~|0.45/0.31<br>~~|~~|0.49/0.33<br>~~|~~|0.57/0.36<br>~~|~~|0.57/0.52<br>~~|~~|0.57/0.36<br>~~|~~|0.77/0.45<br>~~|~~|ns, Min<br>~~|~~|
|TRDCK_DI_WF_NC/<br>TRCKD_DI_WF_NC|Data input setup/hold time<br>when block RAM is<br>configured in<br>WRITE_FIRST or<br>NO_CHANGE mode(9)|0.58/0.60|0.65/0.63|0.74/0.67|0.74/0.67|0.74/0.67|0.92/0.76|ns, Min|
|TRDCK_DI_RF/<br>TRCKD_DI_RF|Data input setup/hold time<br>when block RAM is<br>configured in<br>READ_FIRST mode(9)|0.20/0.29|0.22/0.34|0.25/0.41|0.25/0.50|0.25/0.41|0.29/0.38|ns, Min|
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**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 30:_ **Block RAM and FIFO Switching Characteristics** _**(Cont’d)**_
|**Symbol**<br>~~pf~~<br>~~a~~|**Description**<br>~~pf~~<br>~~a~~|**Speed Grade**<br>~~OO~~|**Speed Grade**<br>~~OO~~|**Speed Grade**<br>~~OO~~|**Speed Grade**<br>~~OO~~|**Speed Grade**<br>~~OO~~|**Speed Grade**<br>~~OO~~|**Units**<br>~~OO~~|
|---|---|---|---|---|---|---|---|---|
|||**1.0V**<br>~~OO~~||||**0.95V**<br>~~OO~~|**0.9V**<br>~~OO~~||
|||**-3**<br>~~OO~~<br>~~ee~~|**-2/-2LE**<br>~~OO~~<br>~~ee~~|**-1**<br>~~OO~~<br>~~ee~~|**-1Q/-1M**<br>~~OO~~<br>~~ee~~|**-1LI**<br>~~OO~~|**-2LE**<br>~~OO~~||
|TRDCK_DI_ECC/<br>TRCKD_DI_ECC<br>~~a~~|DIN inputs with block RAM<br>ECC in standard mode(9)<br>~~a~~|0.50/0.43<br>~~ee~~|0.55/0.46<br>~~ee~~|0.63/0.50<br>~~ee~~|0.63/0.50<br>~~ee~~|0.63/0.50|0.78/0.54|ns, Min|
|TRDCK_DI_ECCW/<br>TRCKD_DI_ECCW<br>~~a~~|DIN inputs with block RAM<br>ECC encode only(9)<br>~~a~~|0.93/0.43<br>~~ee ~~|1.02/0.46<br> ~~ee~~|1.17/0.50<br>~~ee ~~|1.17/0.50<br> ~~ee~~|1.17/0.50|1.38/0.48|ns, Min|
|TRDCK_DI_ECC_FIFO/<br>TRCKD_DI_ECC_FIFO|DIN inputs with FIFO ECC<br>in standard mode(9)|1.04/0.56|1.15/0.59|1.32/0.64|1.32/0.64|1.32/0.64|1.55/0.77|ns, Min|
|TRCCK_INJECTBITERR/<br>TRCKC_INJECTBITERR|Inject single/double bit<br>error in ECC mode|0.58/0.35|0.64/0.37|0.74/0.40|0.74/0.52|0.74/0.40|0.92/0.48|ns, Min|
|TRCCK_EN/TRCKC_EN|Block RAM enable (EN)<br>input|0.35/0.20|0.39/0.21|0.45/0.23|0.45/0.41|0.45/0.23|0.57/0.26|ns, Min|
|TRCCK_REGCE/<br>TRCKC_REGCE|CE input of output register|0.24/0.15|0.29/0.15|0.36/0.16|0.36/0.39|0.36/0.16|0.40/0.19|ns, Min|
|TRCCK_RSTREG/<br>TRCKC_RSTREG|Synchronous RSTREG<br>input|0.29/0.07|0.32/0.07|0.35/0.07|0.35/0.17|0.35/0.07|0.41/0.07|ns, Min|
|TRCCK_RSTRAM/<br>TRCKC_RSTRAM|Synchronous RSTRAM<br>input|0.32/0.42|0.34/0.43|0.36/0.46|0.36/0.57|0.36/0.46|0.40/0.47|ns, Min|
|TRCCK_WEA/<br>TRCKC_WEA|Write enable (WE) input<br>(block RAM only)|0.44/0.18|0.48/0.19|0.54/0.20|0.54/0.42|0.54/0.20|0.64/0.23|ns, Min|
|TRCCK_WREN/<br>TRCKC_WREN|WREN FIFO inputs|0.46/0.30|0.46/0.35|0.47/0.43|0.47/0.43|0.47/0.43|0.77/0.44|ns, Min|
|TRCCK_RDEN/<br>TRCKC_RDEN<br>~~CO~~|RDEN FIFO inputs<br>|0.42/0.30<br>|0.43/0.35<br>|0.43/0.43<br>|0.43/0.62<br>|0.43/0.43<br>|0.71/0.50<br>|ns, Min<br>|
|**Reset Delays**<br>~~CO~~|||||||||
|TRCO_FLAGS<br>~~CO~~|Reset RST to FIFO<br>flags/pointers(10)<br>|0.90<br>|0.98<br>|1.10<br>|1.10<br>|1.10<br>|1.25<br>|ns, Max<br>|
|TRREC_RST/<br>TRREM_RST<br>|FIFO reset recovery and<br>removal timing(11)<br>|1.87/–0.81 <br>|2.07/–0.81 <br>|2.37/–0.81 <br>|2.37/–0.58 <br>|2.37/–0.81 <br>|2.44/–0.71 <br>|ns, Max<br>|
|**Maximum Frequency**<br>~~OO~~|||||||||
|FMAX_BRAM_WF_NC<br>~~OO~~|Block RAM (write first and<br>no change modes) when<br>not in SDP RF mode<br>~~OO~~|509.68<br>~~OO~~|460.83<br>~~OO~~|388.20<br>~~OO~~|388.20<br>~~OO~~|388.20<br>~~OO~~|315.66<br>~~OO~~|MHz<br>~~OO~~|
|FMAX_BRAM_RF_<br>PERFORMANCE|Block RAM (read first,<br>performance mode) when<br>in SDP RF mode but no<br>address overlap between<br>port A and port B|509.68|460.83|388.20|388.20|388.20|315.66|MHz|
|FMAX_BRAM_RF_<br>DELAYED_WRITE|Block RAM (read first,<br>delayed write mode) when<br>in SDP RF mode and<br>there is possibility of<br>overlap between port A<br>and port B addresses|447.63|404.53|339.67|339.67|339.67|268.96|MHz|
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**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 30:_ **Block RAM and FIFO Switching Characteristics** _**(Cont’d)**_
|**Symbol**<br>~~pf~~|**Description**<br>~~pf~~|**Speed Grade**<br>~~|~~|**Speed Grade**<br>~~|~~|**Speed Grade**<br>~~|~~|**Speed Grade**<br>~~|~~|**Speed Grade**<br>~~|~~|**Speed Grade**<br>~~|~~|**Units**<br>~~|~~|
|---|---|---|---|---|---|---|---|---|
|||**1.0V**<br>~~|~~||||**0.95V**<br>~~|~~|**0.9V**<br>~~|~~||
|||**-3**<br>~~|~~|**-2/-2LE**<br>~~|~~|**-1**<br>~~|~~|**-1Q/-1M**<br>~~|~~|**-1LI**<br>~~|~~|**-2LE**<br>~~|~~||
|FMAX_CAS_WF_NC|Block RAM cascade (write<br>first, no change mode)<br>when cascade but not in<br>RF mode|467.07|418.59|345.78|345.78|345.78|273.30|MHz|
|FMAX_CAS_RF_<br>PERFORMANCE|Block RAM cascade (read<br>first, performance mode)<br>when in cascade with RF<br>mode and no possibility of<br>address overlap/one port<br>is disabled|467.07|418.59|345.78|345.78|345.78|273.30|MHz|
|FMAX_CAS_RF_<br>DELAYED_WRITE|When in cascade RF<br>mode and there is a<br>possibility of address<br>overlap between port A<br>and port B|405.35|362.19|297.35|297.35|297.35|226.60|MHz|
|FMAX_FIFO|FIFO in all modes without<br>ECC|509.68|460.83|388.20|388.20|388.20|315.66|MHz|
|FMAX_ECC|Block RAM and FIFO in<br>ECC configuration|410.34|365.10|297.53|297.53|297.53|215.38|MHz|
## **Notes:**
1. The timing report shows all of these parameters as TRCKO_DO.
2. TRCKO_DOR includes TRCKO_DOW, TRCKO_DOPR, and TRCKO_DOPW as well as the B port equivalent timing parameters.
3. These parameters also apply to synchronous FIFO with DO_REG = 0.
4. TRCKO_DO includes TRCKO_DOP as well as the B port equivalent timing parameters.
5. These parameters also apply to multirate (asynchronous) and synchronous FIFO with DO_REG = 1.
6. TRCKO_FLAGS includes the following parameters: TRCKO_AEMPTY, TRCKO_AFULL, TRCKO_EMPTY, TRCKO_FULL, TRCKO_RDERR, TRCKO_WRERR.
7. TRCKO_POINTERS includes both TRCKO_RDCOUNT and TRCKO_WRCOUNT.
8. The ADDR setup and hold must be met when EN is asserted (even when WE is deasserted). Otherwise, block RAM data corruption is possible.
9. These parameters include both A and B inputs as well as the parity inputs of A and B.
10. TRCO_FLAGS includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT.
11. RDEN and WREN must be held Low prior to and during reset. The FIFO reset must be asserted for at least five positive clock edges of the slowest clock (WRCLK or RDCLK).
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**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
## **DSP48E1 Switching Characteristics**
## _Table 31:_ **DSP48E1 Switching Characteristics**
|**Symbol**|**Description**|**Speed Grade**<br>~~po~~|**Speed Grade**<br>~~po~~|**Speed Grade**<br>~~po~~|**Speed Grade**<br>~~po~~|**Speed Grade**<br>~~po~~|**Speed Grade**<br>~~po~~|**Units**|
|---|---|---|---|---|---|---|---|---|
|||**1.0V**<br>~~po~~<br>~~ee~~||||**0.95V**<br>~~po~~|**0.9V**<br>~~po~~||
|||**-3**<br>~~ee~~|**-2/-2LE**<br>~~ee~~|**-1**<br>~~ee~~|**-1Q/-1M**<br>~~ee~~<br>~~ee~~|**-1LI**<br>~~ee~~|**-2LE**<br>~~ee~~||
|**Setup and Hold Times of Data/Control Pins to the Input Register Clock**<br>~~ee~~<br>~~pT~~|||||||||
|TDSPDCK_A_AREG/<br>TDSPCKD_A_AREG<br>~~pT~~|A input to A register CLK<br>~~pT~~|0.26/<br>0.12<br>~~pT~~|0.30/<br>0.13<br>~~pT~~|0.37/<br>0.14<br>~~pT~~|0.37/<br>0.28<br>~~pT~~|0.37/<br>0.14<br>~~pT~~|0.45/<br>0.14<br>~~pT~~|ns<br>~~pT~~|
|TDSPDCK_B_BREG/<br>TDSPCKD_B_BREG|B input to B register CLK|0.33/<br>0.15|0.38/<br>0.16|0.45/<br>0.18|0.45/<br>0.25|0.45/<br>0.18|0.60/<br>0.19|ns|
|TDSPDCK_C_CREG/<br>TDSPCKD_C_CREG|C input to C register CLK|0.17/<br>0.17|0.20/<br>0.19|0.24/<br>0.21|0.24/<br>0.26|0.24/<br>0.21|0.34/<br>0.29|ns|
|TDSPDCK_D_DREG/<br>TDSPCKD_D_DREG|D input to D register CLK|0.25/<br>0.25|0.32/<br>0.27|0.42/<br>0.27|0.42/<br>0.42|0.42/<br>0.27|0.54/<br>0.23|ns|
|TDSPDCK_ACIN_AREG/<br>TDSPCKD_ACIN_AREG|ACIN input to A register CLK|0.23/<br>0.12|0.27/<br>0.13|0.32/<br>0.14|0.32/<br>0.17|0.32/<br>0.14|0.36/<br>0.14|ns|
|TDSPDCK_BCIN_BREG/<br>TDSPCKD_BCIN_BREG|BCIN input to B register CLK|0.25/<br>0.15|0.29/<br>0.16|0.36/<br>0.18|0.36/<br>0.18|0.36/<br>0.18|0.41/<br>0.19|ns|
|**Setup and Hold Times of Data Pins to the Pipeline Register Clock**|||||||||
|TDSPDCK_{A, B}_MREG_MULT/<br>TDSPCKD_{A, B}_MREG_MULT|{A, B} input to M register CLK<br>using multiplier|2.40/<br>–0.01|2.76/<br>–0.01|3.29/<br>–0.01|3.29/<br>–0.01|3.29/<br>–0.01|4.31/<br>–0.07|ns|
|TDSPDCK_{A, D}_ADREG/<br>TDSPCKD_{A, D}_ADREG|{A, D} input to AD register CLK|1.29/<br>–0.02|1.48/<br>–0.02|1.76/<br>–0.02|1.76/<br>–0.02|1.76/<br>–0.02|2.29/<br>–0.27|ns|
|**Setup and Hold Times of Data/Control Pins to the Output Register Clock**<br>~~pe~~|||||||||
|TDSPDCK_{A, B}_PREG_MULT/<br>TDSPCKD_{A, B} _PREG_MULT<br>~~pe~~|{A, B} input to P register CLK<br>using multiplier<br>~~pe~~|4.02/<br>–0.28<br>~~pe~~|4.60/<br>–0.28<br>~~pe~~|5.48/<br>–0.28<br>~~pe~~|5.48/<br>–0.28<br>~~pe~~|5.48/<br>–0.28<br>~~pe~~|6.95/<br>–0.48<br>~~pe~~|ns<br>~~pe~~|
|TDSPDCK_D_PREG_MULT/<br>TDSPCKD_D_PREG_MULT|D input to P register CLK using<br>multiplier|3.93/<br>–0.73|4.50/<br>–0.73|5.35/<br>–0.73|5.35/<br>–0.73|5.35/<br>–0.73|6.73/<br>–1.68|ns|
|TDSPDCK_{A, B} _PREG/<br>TDSPCKD_{A, B} _PREG|A or B input to P register CLK<br>not using multiplier|1.73/<br>–0.28|1.98/<br>–0.28|2.35/<br>–0.28|2.35/<br>–0.28|2.35/<br>–0.28|2.80/<br>–0.48|ns|
|TDSPDCK_C_PREG/<br>TDSPCKD_C_PREG|C input to P register CLK not<br>using multiplier|1.54/<br>–0.26|1.76/<br>–0.26|2.10/<br>–0.26|2.10/<br>–0.26|2.10/<br>–0.26|2.54/<br>–0.45|ns|
|TDSPDCK_PCIN_PREG/<br>TDSPCKD_PCIN_PREG|PCIN input to P register CLK|1.32/<br>–0.15|1.51/<br>–0.15|1.80/<br>–0.15|1.80/<br>–0.15|1.80/<br>–0.15|2.13/<br>–0.25|ns|
|**Setup and Hold Times of the CE Pins**|||||||||
|TDSPDCK_{CEA;CEB}_{AREG;BREG}/<br>TDSPCKD_{CEA;CEB}_{AREG;BREG}|{CEA; CEB} input to {A; B}<br>register CLK|0.35/<br>0.06|0.42/<br>0.08|0.52/<br>0.11|0.52/<br>0.11|0.52/<br>0.11|0.64/<br>0.11|ns|
|TDSPDCK_CEC_CREG/<br>TDSPCKD_CEC_CREG|CEC input to C register CLK|0.28/<br>0.10|0.34/<br>0.11|0.42/<br>0.13|0.42/<br>0.13|0.42/<br>0.13|0.49/<br>0.16|ns|
|TDSPDCK_CED_DREG/<br>TDSPCKD_CED_DREG|CED input to D register CLK|0.36/<br>–0.03|0.43/<br>–0.03|0.52/<br>–0.03|0.52/<br>–0.03|0.52/<br>–0.03|0.68/<br>0.14|ns|
|TDSPDCK_CEM_MREG/<br>TDSPCKD_CEM_MREG|CEM input to M register CLK|0.17/<br>0.18|0.21/<br>0.20|0.27/<br>0.23|0.27/<br>0.23|0.27/<br>0.23|0.45/<br>0.29|ns|
|TDSPDCK_CEP_PREG/<br>TDSPCKD_CEP_PREG|CEP input to P register CLK|0.36/<br>0.01|0.43/<br>0.01|0.53/<br>0.01|0.53/<br>0.01|0.53/<br>0.01|0.63/<br>0.00|ns|
DS181 (v1.27.1) July 3, 2024 **Product Specification**
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33
**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 31:_ **DSP48E1 Switching Characteristics** _**(Cont’d)**_
|**Symbol**|**Description**|**Speed Grade**<br>~~—~~|**Speed Grade**<br>~~—~~|**Speed Grade**<br>~~—~~|**Speed Grade**<br>~~—~~|**Speed Grade**<br>~~—~~|**Speed Grade**<br>~~—~~|**Units**|
|---|---|---|---|---|---|---|---|---|
|||**1.0V**||||**0.95V**|**0.9V**||
|||**-3**<br>~~a~~|**-2/-2LE**<br>~~a~~|**-1**<br>~~a~~|**-1Q/-1M**<br>~~a~~|**-1LI**<br>~~a~~|**-2LE**<br>~~a~~||
|**Setup and Hold Times of the RST Pins**<br>~~TO~~|||||||||
|TDSPDCK_{RSTA; RSTB}_{AREG; BREG}/<br>TDSPCKD_{RSTA; RSTB}_{AREG; BREG}<br>~~TO~~|{RSTA, RSTB} input to {A, B}<br>register CLK<br>~~TO~~|0.41/<br>0.11<br>~~TO~~|0.46/<br>0.13<br>~~TO~~|0.55/<br>0.15<br>~~TO~~|0.55/<br>0.24<br>~~TO~~|0.55/<br>0.15<br>~~TO~~|0.63/<br>0.40<br>~~TO~~|ns<br>~~TO~~|
|TDSPDCK_RSTC_CREG/<br>TDSPCKD_RSTC_CREG|RSTC input to C register CLK|0.07/<br>0.10|0.08/<br>0.11|0.09/<br>0.12|0.09/<br>0.25|0.09/<br>0.12|0.13/<br>0.11|ns|
|TDSPDCK_RSTD_DREG/<br>TDSPCKD_RSTD_DREG|RSTD input to D register CLK|0.44/<br>0.07|0.50/<br>0.08|0.59/<br>0.09|0.59/<br>0.09|0.59/<br>0.09|0.67/<br>0.08|ns|
|TDSPDCK_RSTM_MREG/<br>TDSPCKD_RSTM_MREG|RSTM input to M register CLK|0.21/<br>0.22|0.23/<br>0.24|0.27/<br>0.28|0.27/<br>0.28|0.27/<br>0.28|0.28/<br>0.35|ns|
|TDSPDCK_RSTP_PREG/<br>TDSPCKD_RSTP_PREG|RSTP input to P register CLK|0.27/<br>0.01|0.30/<br>0.01|0.35/<br>0.01|0.35/<br>0.03|0.35/<br>0.01|0.43/<br>0.00|ns|
|**Combinatorial Delays from Input Pins to Output Pins**|||||||||
|TDSPDO_A_CARRYOUT_MULT|A input to CARRYOUT output<br>using multiplier|3.79|4.35|5.18|5.18|5.18|6.61|ns|
|TDSPDO_D_P_MULT|D input to P output using<br>multiplier|3.72|4.26|5.07|5.07|5.07|6.41|ns|
|TDSPDO_B_P|B input to P output not using<br>multiplier|1.53|1.75|2.08|2.08|2.08|2.48|ns|
|TDSPDO_C_P<br>~~a~~|C input to P output|1.33|1.53|1.82|1.82|1.82|2.22|ns|
|**Combinatorial Delays from Input Pins to Cascading Output Pins**<br>~~a~~|||||||||
|TDSPDO_{A; B}_{ACOUT; BCOUT}|{A, B} input to {ACOUT, BCOUT}<br>output|0.55|0.63|0.74|0.74|0.74|0.87|ns|
|TDSPDO_{A, B}_CARRYCASCOUT_MULT|{A, B} input to<br>CARRYCASCOUT output using<br>multiplier|4.06|4.65|5.54|5.54|5.54|7.03|ns|
|TDSPDO_D_CARRYCASCOUT_MULT|D input to CARRYCASCOUT<br>output using multiplier|3.97|4.54|5.40|5.40|5.40|6.81|ns|
|TDSPDO_{A, B}_CARRYCASCOUT|{A, B} input to<br>CARRYCASCOUT output not<br>using multiplier|1.77|2.03|2.41|2.41|2.41|2.88|ns|
|TDSPDO_C_CARRYCASCOUT|C input to CARRYCASCOUT<br>output|1.58|1.81|2.15|2.15|2.15|2.62|ns|
|**Combinatorial Delays from Cascading Input Pins to All Output Pins**|||||||||
|TDSPDO_ACIN_P_MULT|ACIN input to P output using<br>multiplier|3.65|4.19|5.00|5.00|5.00|6.40|ns|
|TDSPDO_ACIN_P|ACIN input to P output not using<br>multiplier|1.37|1.57|1.88|1.88|1.88|2.44|ns|
|TDSPDO_ACIN_ACOUT|ACIN input to ACOUT output|0.38|0.44|0.53|0.53|0.53|0.63|ns|
|TDSPDO_ACIN_CARRYCASCOUT_MULT<br>~~a~~|ACIN input to<br>CARRYCASCOUT output using<br>multiplier<br>~~ee~~|3.90<br>~~ee~~|4.47<br>~~ee~~|5.33<br>~~ee~~|5.33<br>~~ee~~|5.33<br>~~ee~~|6.79<br>~~ee~~|ns<br>~~ee~~|
|TDSPDO_ACIN_CARRYCASCOUT<br>~~a ~~|ACIN input to<br>CARRYCASCOUT output not<br>using multiplier<br> ~~ee~~|1.61<br>~~ee~~|1.85<br>~~ee~~|2.21<br>~~ee~~|2.21<br>~~ee~~|2.21<br>~~ee~~|2.84<br>~~ee~~|ns<br>~~ee~~|
|TDSPDO_PCIN_P|PCIN input to P output|1.11<br>~~ee~~|1.28<br>~~ee~~|1.52<br>~~ee~~|1.52|1.52|1.82|ns|
|TDSPDO_PCIN_CARRYCASCOUT<br>~~ee~~|PCIN input to<br>CARRYCASCOUT output<br>~~ee~~|1.36<br>~~ee~~<br>~~ee~~|1.56<br>~~ee~~<br>~~ee~~|1.85<br>~~ee~~<br>~~ee~~|1.85<br>~~ee~~|1.85<br>~~ee~~|2.21<br>~~ee~~|ns<br>~~ee~~|
34
**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
## _Table 31:_ **DSP48E1 Switching Characteristics** _**(Cont’d)**_
|**Symbol**|**Description**|**Speed Grade**<br>~~—~~|**Speed Grade**<br>~~—~~|**Speed Grade**<br>~~—~~|**Speed Grade**<br>~~—~~|**Speed Grade**<br>~~—~~|**Speed Grade**<br>~~—~~|**Units**|
|---|---|---|---|---|---|---|---|---|
|||**1.0V**||||**0.95V**|**0.9V**||
|||**-3**<br>~~a~~|**-2/-2LE**<br>~~a~~|**-1**<br>~~a~~|**-1Q/-1M**<br>~~a~~|**-1LI**<br>~~a~~|**-2LE**<br>~~a~~||
|**Clock to Outs from Output Register Clock to Output Pins**<br>~~TO~~|||||||||
|TDSPCKO_P_PREG<br>~~TO~~|CLK PREG to P output<br>~~TO~~|0.33<br>~~TO~~|0.37<br>~~TO~~|0.44<br>~~TO~~|0.44<br>~~TO~~|0.44<br>~~TO~~|0.54<br>~~TO~~|ns<br>~~TO~~|
|TDSPCKO_CARRYCASCOUT_PREG<br>~~ee~~|CLK PREG to<br>CARRYCASCOUT output<br>~~ee~~|0.52<br>~~ee~~|0.59<br>~~ee~~|0.69<br>~~ee~~|0.69<br>~~ee~~|0.69<br>~~ee~~|0.84<br>~~ee~~|ns<br>~~ee~~|
|**Clock to Outs from Pipeline Register Clock to Output Pins**<br>~~ee~~|||||||||
|TDSPCKO_P_MREG|CLK MREG to P output|1.68|1.93|2.31|2.31|2.31|2.73|ns|
|TDSPCKO_CARRYCASCOUT_MREG<br>~~a~~|CLK MREG to<br>CARRYCASCOUT output<br>~~ee~~|1.92<br>~~ee~~|2.21<br>~~ee~~|2.64<br>~~ee~~|2.64<br>~~ee~~|2.64<br>~~ee~~|3.12<br>~~ee~~|ns<br>~~ee~~|
|TDSPCKO_P_ADREG_MULT<br>~~a ~~|CLK ADREG to P output using<br>multiplier<br> ~~ee~~|2.72<br>~~ee~~|3.10<br>~~ee~~|3.69<br>~~ee~~|3.69<br>~~ee~~|3.69<br>~~ee~~|4.60<br>~~ee~~|ns<br>~~ee~~|
|TDSPCKO_CARRYCASCOUT_ADREG_<br>MULT|CLK ADREG to<br>CARRYCASCOUT output using<br>multiplier|2.96|3.38|4.02|4.02|4.02|4.99|ns|
|**Clock to Outs from Input Register Clock to Output Pins**|||||||||
|TDSPCKO_P_AREG_MULT|CLK AREG to P output using<br>multiplier|3.94|4.51|5.37|5.37|5.37|6.84|ns|
|TDSPCKO_P_BREG|CLK BREG to P output not using<br>multiplier|1.64|1.87|2.22|2.22|2.22|2.65|ns|
|TDSPCKO_P_CREG|CLK CREG to P output not<br>using multiplier|1.69|1.93|2.30|2.30|2.30|2.81|ns|
|TDSPCKO_P_DREG_MULT|CLK DREG to P output using<br>multiplier|3.91|4.48|5.32|5.32|5.32|6.77|ns|
|**Clock to Outs from Input Register Clock to Cascading Output Pins**|||||||||
|TDSPCKO_{ACOUT; BCOUT}_{AREG;<br>BREG}|CLK (ACOUT, BCOUT) to {A,B}<br>register output|0.64|0.73|0.87|0.87|0.87|1.02|ns|
|TDSPCKO_CARRYCASCOUT_{AREG,<br>BREG}_MULT|CLK (AREG, BREG) to<br>CARRYCASCOUT output using<br>multiplier|4.19|4.79|5.70|5.70|5.70|7.24|ns|
|TDSPCKO_CARRYCASCOUT_ BREG|CLK BREG to<br>CARRYCASCOUT output not<br>using multiplier|1.88|2.15|2.55|2.55|2.55|3.04|ns|
|TDSPCKO_CARRYCASCOUT_<br>DREG_MULT|CLK DREG to<br>CARRYCASCOUT output using<br>multiplier|4.16|4.76|5.65|5.65|5.65|7.17|ns|
|TDSPCKO_CARRYCASCOUT_ CREG|CLK CREG to<br>CARRYCASCOUT output|1.94|2.21|2.63|2.63|2.63|3.20|ns|
|**Maximum Frequency**|||||||||
|FMAX<br>~~a~~|With all registers used<br>|628.93<br>|550.66<br>|464.25<br>|464.25<br>|464.25 <br>|363.77<br>|MHz<br>|
|FMAX_PATDET<br>~~a~~|With pattern detector<br>|531.63<br>|465.77<br>|392.93<br>|392.93<br>|392.93 <br>|310.08<br>|MHz<br>|
|FMAX_MULT_NOMREG<br>~~ee~~|Two register multiply without<br>MREG<br>~~ee~~|349.28<br>~~ee~~|305.62<br>~~ee~~|257.47<br>~~ee~~|257.47<br>~~ee~~|257.47 <br>~~ee~~|210.44<br>~~ee~~|MHz<br>~~ee~~|
|FMAX_MULT_NOMREG_PATDET<br>~~ee~~|Two register multiply without<br>MREG with pattern detect<br>~~ee~~|317.26<br>~~ee~~|277.62<br>~~ee~~|233.92<br>~~ee~~|233.92<br>~~ee~~|233.92 <br>~~ee~~|191.28<br>~~ee~~|MHz<br>~~ee~~|
|FMAX_PREADD_MULT_NOADREG|Without ADREG|397.30|346.26|290.44|290.44|290.44|223.26|MHz|
|FMAX_PREADD_MULT_NOADREG_<br>PATDET<br>~~ee~~|Without ADREG with pattern<br>detect<br>~~ee~~|397.30<br>~~ee~~|346.26<br>~~ee~~|290.44<br>~~ee~~|290.44<br>~~ee~~|290.44 <br>~~ee~~|223.26<br>~~ee~~|MHz<br>~~ee~~|
DS181 (v1.27.1) July 3, 2024 **Product Specification**
Send Feedback
35
**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 31:_ **DSP48E1 Switching Characteristics** _**(Cont’d)**_
|**Symbol**|**Description**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|---|---|
|||**1.0V**||||**0.95V**|**0.9V**||
|||**-3**|**-2/-2LE**|**-1**|**-1Q/-1M**|**-1LI**|**-2LE**||
|FMAX_NOPIPELINEREG|Without pipeline registers<br>(MREG, ADREG)|260.01|227.01|190.69|190.69|190.69|150.13|MHz|
|FMAX_NOPIPELINEREG_PATDET|Without pipeline registers<br>(MREG, ADREG) with pattern<br>detect|241.72|211.15|177.43|177.43|177.43|140.10|MHz|
## **Clock Buffers and Networks**
_Table 32:_ **Global Clock Switching Characteristics (Including BUFGCTRL)**
|**Symbol**|**Description**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|---|---|
|||**1.0V**||||**0.95V**|**0.9V**||
|||**-3**|**-2/-2LE**|**-1**|**-1Q/-1M**|**-1LI**|**-2LE**||
|TBCCCK_CE/<br>TBCCKC_CE(1)|CE pins setup/hold|0.12/0.39|0.13/0.40|0.16/0.41|0.16/0.83|0.16/0.41|0.31/0.67|ns|
|TBCCCK_S/<br>TBCCKC_S(1)|S pins setup/hold|0.12/0.39|0.13/0.40|0.16/0.41|0.16/0.83|0.16/0.41|0.31/0.67|ns|
|TBCCKO_O(2)|BUFGCTRL delay from I0/I1 to O|0.08|0.09|0.10|0.10|0.10|0.14|ns|
|**Maximum Frequency**|||||||||
|FMAX_BUFG|Global clock tree (BUFG)|628.00|628.00|464.00|464.00|464.00|394.00|MHz|
## **Notes:**
1. TBCCCK_CE and TBCCKC_CE must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These parameters do not apply to the BUFGMUX primitive that assures glitch-free operation. The other global clock setup and hold times are optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching between clocks.
2. TBGCKO_O (BUFG delay from I0 to O) values are the same as TBCCKO_O values.
_Table 33:_ **Input/Output Clock Switching Characteristics (BUFIO)**
**Speed Grade Symbol Description 1.0V 0.95V 0.9V Units -3 -2/-2LE -1 -1Q/-1M -1LI -2LE** TBIOCKO_O Clock to out delay from I to O 1.11 1.26 1.54 1.54 1.54 1.56 ns **Maximum Frequency** ~~aS~~ FMAX_BUFIO I/O clock tree (BUFIO) 680.00 680.00 600.00 600.00 600.00 600.00 MHz _Table 34:_ **Regional Clock Buffer Switching Characteristics (BUFR) Speed Grade Symbol Description 1.0V 0.95V 0.9V Units -3 -2/-2LE -1 -1Q/-1M -1LI -2LE** TBRCKO_O Clock to out delay from I to O 0.64 0.76 0.99 0.99 0.99 1.24 ns Clock to out delay from I to O with 0.34 0.39 0.52 0.52 0.52 0.72 ns T BRCKO_O_BYP Divide Bypass attribute set ~~==~~ TBRDO_O Propagation delay from CLR to O 0.81 0.85 1.09 1.09 1.09 0.96 ns DS181 (v1.27.1) July 3, 2024 Send Feedback **Product Specification** 36
**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 34:_ **Regional Clock Buffer Switching Characteristics (BUFR)** _**(Cont’d)**_
|**Symbol**|**Description**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|---|---|
|||**1.0V**||||**0.95V**|**0.9V**||
|||**-3**|**-2/-2LE**|**-1**|**-1Q/-1M**|**-1LI**|**-2LE**||
|**Maximum Frequency**|||||||||
|FMAX_BUFR(1)|Regional clock tree (BUFR)|420.00|375.00|315.00|315.00|315.00|315.00|MHz|
## **Notes:**
1. The maximum input frequency to the BUFR and BUFMR is the BUFIO FMAX frequency.
_Table 35:_ **Horizontal Clock Buffer Switching Characteristics (BUFH)**
|**Symbol**|**Description**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|---|---|
|||**1.0V**||||**0.95V**|**0.9V**||
|||**-3**|**-2/-2LE**|**-1**|**-1Q/-1M**|**-1LI**|**-2LE**||
|TBHCKO_O|BUFH delay from I to O|0.10|0.11|0.13|0.13|0.13|0.16|ns|
|TBHCCK_CE/<br>TBHCKC_CE|CE pin setup and hold|0.19/0.13|0.22/0.15|0.28/0.21|0.28/0.42|0.28/0.21|0.35/0.25|ns|
|**Maximum Frequency**|||||||||
|FMAX_BUFH|Horizontal clock buffer (BUFH)|628.00|628.00|464.00|464.00|464.00|394.00|MHz|
_Table 36:_ **Duty Cycle Distortion and Clock-Tree Skew**
|**Symbol**<br>~~a~~|**Description**<br>|**Device**<br>~~Se~~<br>|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**<br>|
|---|---|---|---|---|---|---|---|---|---|
||||**1.0V**<br>~~Se~~<br>||||**0.95V**<br>|**0.9V**<br>||
||||**-3**<br>~~Se~~<br>|**-2/-2LE**<br>|**-1**<br>|**-1Q/-1M**<br>|**-1LI**<br>|**-2LE**<br>||
|TDCD_CLK<br>~~a~~|Global clock tree duty-cycle<br>distortion(1)<br>~~ee~~|All<br>~~Se~~<br>~~ee~~|0.20<br>~~Se~~<br>~~ee~~|0.20<br>~~ee~~|0.20<br>~~ee~~|N/A<br>~~ee~~|0.20<br>~~ee~~|0.25<br>~~ee~~|ns<br>~~ee~~|
|TCKSKEW<br>~~a~~<br>~~a~~|Global clock tree skew(2)<br>~~ee~~<br>~~Se~~<br>~~Se~~<br>~~Se~~<br>~~Se~~<br>~~Se~~<br>~~a~~|XC7A12T<br>~~Se~~<br>~~ee~~<br>~~i~~<br>~~es~~|0.26<br>~~Se~~<br>~~ee~~|0.26<br>~~ee~~|0.26<br>~~ee~~|N/A<br>~~ee~~|0.26<br>~~ee~~|0.33<br>~~ee~~|ns<br>~~ee~~|
|||XC7A15T<br>~~i~~<br>~~es~~<br>~~Se~~|0.26<br>|0.26<br>|0.26<br>|N/A<br>|0.26<br>|0.33<br>|ns<br>|
|||XC7A25T<br>~~es~~<br>~~Se~~|0.26<br>|0.26<br>|0.26<br>|N/A<br>|0.26<br>|0.33<br>|ns<br>|
|||XC7A35T<br>~~Sea~~<br>~~es~~|0.26<br>~~a~~|0.26<br>~~a~~|0.26<br>~~a~~|N/A<br>~~a~~|0.26<br>~~a~~|0.33<br>~~a~~|ns<br>~~a~~|
|||XC7A50T<br>~~a~~<br>~~es~~<br>~~Se~~|0.26<br>~~a~~<br>|0.26<br>~~a~~<br>|0.26<br>~~a~~<br>|N/A<br>~~a~~<br>|0.26<br>~~a~~<br>|0.33<br>~~a~~<br>|ns<br>~~a~~<br>|
|||XC7A75T<br>~~es~~<br>~~Se~~|0.27<br>|0.33<br>|0.36<br>|N/A<br>|0.36<br>|0.48<br>|ns<br>|
|||XC7A100T<br>~~Sea~~<br>~~es~~|0.27<br>~~a~~|0.33<br>~~a~~|0.36<br>~~a~~|N/A<br>~~a~~|0.36<br>~~a~~|0.48<br>~~a~~|ns<br>~~a~~|
|||XC7A200T<br>~~a~~<br>~~es~~<br>~~Se~~|0.40<br>~~a~~<br>|0.48<br>~~a~~<br>|0.54<br>~~a~~<br>|N/A<br>~~a~~<br>|0.54<br>~~a~~<br>|0.69<br>~~a~~<br>|ns<br>~~a~~<br>|
|||XA7A12T<br>~~es~~<br>~~Se~~|N/A<br>|0.26<br>|0.26<br>|0.26<br>|N/A<br>|N/A<br>|ns<br>|
|||XA7A15T<br>~~Sea~~<br>~~es~~|N/A<br>~~a~~|0.26<br>~~a~~|0.26<br>~~a~~|0.26<br>~~a~~|N/A<br>~~a~~|N/A<br>~~a~~|ns<br>~~a~~|
|||XA7A25T<br>~~a~~<br>~~es~~<br>~~Se~~|N/A<br>~~a~~<br>|0.26<br>~~a~~<br>|0.26<br>~~a~~<br>|0.26<br>~~a~~<br>|N/A<br>~~a~~<br>|N/A<br>~~a~~<br>|ns<br>~~a~~<br>|
|||XA7A35T<br>~~es~~<br>~~Se~~|N/A<br>|0.26<br>|0.26<br>|0.26<br>|N/A<br>|N/A<br>|ns<br>|
|||XA7A50T<br>~~Sea~~<br>~~es~~|N/A<br>~~a~~|0.26<br>~~a~~|0.26<br>~~a~~|0.26<br>~~a~~|N/A<br>~~a~~|N/A<br>~~a~~|ns<br>~~a~~|
|||XA7A75T<br>~~a~~<br>~~es~~<br>~~Se~~|N/A<br>~~a~~<br>|0.33<br>~~a~~<br>|0.36<br>~~a~~<br>|0.36<br>~~a~~<br>|N/A<br>~~a~~<br>|N/A<br>~~a~~<br>|ns<br>~~a~~<br>|
|||XA7A100T<br>~~es~~<br>~~Se~~|N/A<br>|0.33<br>|0.36<br>|0.36<br>|N/A<br>|N/A<br>|ns<br>|
|||XQ7A50T<br>~~Sea~~<br>~~es~~|N/A<br>~~a~~<br>|0.26<br>~~a~~<br>|0.26<br>~~a~~<br>|0.26<br>~~a~~<br>|0.26<br>~~a~~<br>|N/A<br>~~a~~<br>|ns<br>~~a~~<br>|
|||XQ7A100T<br>~~a~~<br>~~es~~|N/A<br>~~a~~<br>|0.33<br>~~a~~<br><br>~~a~~|0.36<br>~~a~~<br><br>~~a~~|0.36<br>~~a~~<br>|0.36<br>~~a~~<br>|N/A<br>~~a~~<br>|ns<br>~~a~~<br>|
|||XQ7A200T<br>~~esa~~|N/A<br>~~a~~|0.48<br>~~a~~<br>~~a~~|0.54<br>~~a~~<br>~~a~~|0.54<br>~~a~~|0.54<br>~~a~~|N/A<br>~~a~~|ns<br>~~a~~|
|TDCD_BUFIO<br>~~a~~|I/O clock tree duty cycle distortion <br>~~a~~|All<br>~~a~~|0.14<br>~~a~~|0.14<br>~~a~~<br>~~a~~|0.14<br>~~a~~<br>~~a~~|0.14<br>~~a~~|0.14<br>~~a~~|0.14<br>~~a~~|ns<br>~~a~~|
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DS181 (v1.27.1) July 3, 2024 **Product Specification**
37
**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 36:_ **Duty Cycle Distortion and Clock-Tree Skew** _**(Cont’d)**_
|**Symbol**|**Description**|**Device**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|---|---|---|
||||**1.0V**||||**0.95V**|**0.9V**||
||||**-3**|**-2/-2LE**|**-1**|**-1Q/-1M**|**-1LI**|**-2LE**||
|TBUFIOSKEW|I/O clock tree skew across one<br>clock region|All|0.03|0.03|0.03|0.03|0.03|0.03|ns|
|TDCD_BUFR|Regional clock tree duty cycle<br>distortion|All|0.18|0.18|0.18|0.18|0.18|0.18|ns|
## **Notes:**
1. These parameters represent the worst-case duty cycle distortion observable at the I/O flip flops. For all I/O standards, IBIS can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical rise/fall times.
2. The TCKSKEW value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx Timing Analyzer tools to evaluate clock skew specific to your application.
## **MMCM Switching Characteristics**
_Table 37:_ **MMCM Specification**
|**Symbol**<br>~~ee~~|**Description**<br>~~ee~~|**Speed Grade**<br>~~re~~<br>~~ee~~|**Speed Grade**<br>~~re~~<br>~~ee~~|**Speed Grade**<br>~~re~~<br>~~ee~~|**Speed Grade**<br>~~re~~<br>~~ee~~|**Speed Grade**<br>~~re~~<br>~~ee~~|**Units**<br>~~ee~~|
|---|---|---|---|---|---|---|---|
|||**1.0V**<br>~~re~~<br>~~ee~~|||**0.95V**<br>~~re~~<br>~~ee~~|**0.9V**<br>~~re~~<br>~~ee~~||
|||**-3**<br>~~ee~~<br>~~a~~|**-2/-2LE**<br>~~ee~~<br>~~a~~|**-1**<br>~~ee~~<br>~~a~~|**-1LI**<br>~~ee~~<br>~~a~~|**-2LE**<br>~~ee~~<br>~~a~~||
|MMCM_FINMAX<br>~~a~~|Maximum input clock frequency<br>~~a~~<br>~~a~~|800.00<br>~~a~~|800.00|800.00|800.00|800.00|MHz|
|MMCM_FINMIN<br>~~a~~<br>~~ee ee~~|Minimum input clock frequency<br>~~a~~<br>~~ee~~|10.00<br>~~ee~~|10.00<br>~~ee~~|10.00<br>~~ee~~|10.00<br>~~ee~~|10.00<br>~~ee~~|MHz<br>~~ee~~|
|MMCM_FINJITTER<br>~~a~~<br>~~ee ee~~|Maximum input clock period jitter<br>~~a~~<br>~~ee~~|< 20% of clock input period or 1 ns Max<br>~~ee~~<br>~~eeee~~||||||
|MMCM_FINDUTY<br>~~ee ee~~<br>~~a~~|Allowable input duty cycle:<br>10—49 MHz<br>~~ee~~|25<br>~~ee~~<br>~~ee~~<br>~~ee~~|25<br>~~ee~~<br>~~ee~~<br>~~ee~~|25<br>~~ee~~<br>~~ee~~<br>~~ee~~|25<br>~~ee~~|25<br>~~ee~~|%<br>~~ee~~|
||Allowable input duty cycle:<br>50—199 MHz<br>~~ee~~<br>~~ee~~|30<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|30<br>~~ee~~<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|30<br>~~ee~~<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|30<br>~~ee~~<br>~~ee~~|30<br>~~ee~~<br>~~ee~~<br>~~ee~~|%<br>~~ee~~<br>~~ee~~<br>~~ee~~|
||Allowable input duty cycle:<br>200—399 MHz<br>~~ee~~|35<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|35<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|35<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|35<br>~~ee~~|35<br>~~ee~~<br>~~ee~~|%<br>~~ee~~<br>~~ee~~|
||Allowable input duty cycle:<br>400—499 MHz<br>~~ee~~<br>~~ee~~|40<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|40<br>~~ee~~<br>~~ee ~~<br>~~ee~~<br>~~ee~~|40<br>~~ee~~<br> ~~ee~~<br>~~ee~~<br>~~ee~~|40<br>~~ee~~<br>~~ee~~|40<br>~~ee~~<br>~~ee~~<br>~~ee~~|%<br>~~ee~~<br>~~ee~~<br>~~ee~~|
||Allowable input duty cycle: > 500 MHz<br>~~ee~~<br>~~eC~~<br>~~es~~|45<br>~~ee~~<br>~~ee~~<br>~~eC~~|45<br>~~ee~~<br>~~ee~~<br>~~eC~~|45<br>~~ee~~<br>~~ee~~<br>~~eC~~|45<br>~~ee~~<br>~~eC~~|45<br>~~ee~~<br>~~eC~~|%<br>~~ee~~<br>~~eC~~|
|MMCM_FMIN_PSCLK<br>~~a~~|Minimum dynamic phase-shift clock<br>frequency<br>~~eC~~<br>~~es~~|0.01<br>~~eC~~|0.01<br>~~eC~~|0.01<br>~~eC~~|0.01<br>~~eC~~|0.01<br>~~eC~~|MHz<br>~~eC~~|
|MMCM_FMAX_PSCLK<br>~~a~~<br>~~aa~~|Maximum dynamic phase-shift clock<br>frequency<br>~~es~~<br>~~aa~~|550.00<br>~~aa~~|500.00|450.00|450.00|450.00|MHz|
|MMCM_FVCOMIN<br>~~a~~|Minimum MMCM VCO frequency<br>~~a~~|600.00|600.00|600.00|600.00|600.00|MHz|
|MMCM_FVCOMAX<br>~~a~~<br>~~SS~~<br>~~ee~~|Maximum MMCM VCO frequency<br>~~a~~<br>~~SS~~<br>~~ee eee~~|1600.00<br>~~SS~~<br>~~eee~~|1440.00<br>~~SS~~<br>~~eee~~|1200.00<br>~~SS~~<br>~~eee~~|1200.00<br>~~SS~~<br>~~eee~~|1200.00<br>~~SS~~<br>~~eee~~|MHz<br>~~SS~~<br>~~eee~~|
|MMCM_FBANDWIDTH<br>~~SS~~<br>~~ee~~|Low MMCM bandwidth at typical(1)<br>~~SS~~<br>~~ee eee~~|1.00<br>~~SS~~<br>~~eee~~|1.00<br>~~SS~~<br>~~eee~~|1.00<br>~~SS~~<br>~~eee~~|1.00<br>~~SS~~<br>~~eee~~|1.00<br>~~SS~~<br>~~eee~~|MHz<br>~~SS~~<br>~~eee~~|
||High MMCM bandwidth at typical(1)<br>~~ee eee~~|4.00<br>~~eee~~|4.00<br>~~eee~~|4.00<br>~~eee~~|4.00<br>~~eee~~|4.00<br>~~eee~~|MHz<br>~~eee~~|
|MMCM_TSTATPHAOFFSET <br>~~ee~~<br>~~a~~|Static phase offset of the MMCM<br>outputs(2)<br>~~ee eee~~<br>~~ee~~|0.12<br>~~eee~~<br>~~ee~~|0.12<br>~~eee~~<br>~~ee~~|0.12<br>~~eee~~<br>~~ee~~|0.12<br>~~eee~~<br>~~ee~~|0.12<br>~~eee~~<br>~~ee~~|ns<br>~~eee~~<br>~~ee~~|
|MMCM_TOUTJITTER<br>~~a~~|MMCM output jitter|Note 3||||||
|MMCM_TOUTDUTY<br>~~a~~<br>~~a~~|MMCM output clock duty-cycle<br>precision(4)|0.20|0.20|0.20|0.20|0.25|ns|
|MMCM_TLOCKMAX<br>~~a~~|MMCM maximum lock time|100.00|100.00|100.00|100.00|100.00|µs|
|MMCM_FOUTMAX<br>~~a~~<br>~~a~~|MMCM maximum output frequency|800.00|800.00|800.00|800.00|800.00|MHz|
|MMCM_FOUTMIN<br>~~a~~<br>~~a~~|MMCM minimum output frequency(5)(6)|4.69|4.69|4.69|4.69|4.69|MHz|
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DS181 (v1.27.1) July 3, 2024 **Product Specification**
38
**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 37:_ **MMCM Specification** _**(Cont’d)**_
|**Symbol**<br>~~|~~|**Description**<br>~~|~~|**Speed Grade**<br>~~po~~<br>|**Speed Grade**<br>~~po~~<br>|**Speed Grade**<br>~~po~~<br>|**Speed Grade**<br>~~po~~<br>|**Speed Grade**<br>~~po~~<br>|**Units**|
|---|---|---|---|---|---|---|---|
|||**1.0V**<br>~~po~~<br>|||**0.95V**<br>~~po~~<br>|**0.9V**<br>~~po~~<br>||
|||**-3**<br>~~po~~<br>~~ee~~|**-2/-2LE**<br>~~po~~<br>~~ee~~|**-1**<br>~~po~~<br>~~ee~~|**-1LI**<br>~~po~~<br>~~ee~~|**-2LE**<br>~~po~~<br>~~ee~~||
|MMCM_TEXTFDVAR<br>~~a~~|External clock feedback variation|< 20% of clock input period or 1 ns Max||||||
|MMCM_RSTMINPULSE<br>~~a~~<br>~~Ge~~|Minimum reset pulse width<br>~~Ge~~|5.00<br>~~GG~~|5.00<br>~~GG~~|5.00<br>~~GG~~|5.00<br>~~GG~~|5.00|ns|
|MMCM_FPFDMAX<br>~~Ge~~|Maximum frequency at the phase<br>frequency detector<br>~~Ge~~|550.00<br>~~GG~~|500.00<br>~~GG~~|450.00<br>~~GG~~|450.00<br>~~GG~~|450.00|MHz|
|MMCM_FPFDMIN|Minimum frequency at the phase<br>frequency detector|10.00|10.00|10.00|10.00|10.00|MHz|
|MMCM_TFBDELAY<br>~~De~~|Maximum delay in the feedback path<br>~~De~~|3 ns Max or one CLKIN cycle<br>~~De~~||||||
|**MMCM Switching Characteristics Setup and Hold**<br>~~De~~<br>~~pn~~||||||||
|TMMCMDCK_PSEN/<br>TMMCMCKD_PSEN<br>~~pn~~|Setup and hold of phase-shift enable<br>~~pn~~|1.04/0.00<br>~~pn~~|1.04/0.00<br>~~pn~~|1.04/0.00<br>~~pn~~|1.04/0.00<br>~~pn~~|1.04/0.00<br>~~pn~~|ns<br>~~pn~~|
|TMMCMDCK_PSINCDEC/<br>TMMCMCKD_PSINCDEC|Setup and hold of phase-shift<br>increment/decrement|1.04/0.00|1.04/0.00|1.04/0.00|1.04/0.00|1.04/0.00|ns|
|TMMCMCKO_PSDONE<br>~~De~~|Phase shift clock-to-out of PSDONE<br>~~De~~|0.59<br>~~FG~~|0.68<br>~~FG~~|0.81<br>~~FG~~|0.81<br>~~FG~~|0.78|ns|
|**Dynamic Reconfiguration Port (DRP) for MMCM Before and After DCLK**<br>~~De~~<br>~~FG~~<br>~~pn~~||||||||
|TMMCMDCK_DADDR/<br>TMMCMCKD_DADDR|DADDR setup/hold|1.25/0.15|1.40/0.15|1.63/0.15|1.63/0.15|1.43/0.00|ns, Min|
|TMMCMDCK_DI/<br>TMMCMCKD_DI|DI setup/hold|1.25/0.15|1.40/0.15|1.63/0.15|1.63/0.15|1.43/0.00|ns, Min|
|TMMCMDCK_DEN/<br>TMMCMCKD_DEN|DEN setup/hold|1.76/0.00|1.97/0.00|2.29/0.00|2.29/0.00|2.40/0.00|ns, Min|
|TMMCMDCK_DWE/<br>TMMCMCKD_DWE<br>~~De~~|DWE setup/hold<br>~~De~~|1.25/0.15<br>~~GG~~|1.40/0.15<br>~~GG~~|1.63/0.15<br>~~GG~~|1.63/0.15<br>~~CO~~|1.43/0.00<br>~~CO~~|ns, Min|
|TMMCMCKO_DRDY<br>~~Ge~~<br>~~De~~|CLK to out of DRDY<br>~~Ge~~<br>~~De~~|0.65<br>~~Ge~~<br>~~GG~~|0.72<br>~~Ge~~<br>~~GG~~|0.99<br>~~Ge~~<br>~~GG~~|0.99<br>~~Ge~~<br>~~CO~~|0.99<br>~~Ge~~<br>~~CO~~|ns, Max<br>~~Ge~~|
|FDCK<br>~~De~~|DCLK frequency<br>~~De~~|200.00<br>~~GG~~<br>~~FG~~|200.00<br>~~GG~~<br>~~FG~~|200.00<br>~~GG~~<br>~~FG~~|200.00<br>~~CO~~<br>~~FG~~|100.00<br>~~CO~~|MHz, Max|
## **Notes:**
1. The MMCM does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies.
2. The static offset is measured between any MMCM outputs with identical phase.
3. Values for this parameter are available in the Clocking Wizard. See http://www.xilinx.com/products/intellectual-property/clocking_wizard.html.
4. Includes global clock buffer.
5. Calculated as FVCO/128 assuming output duty cycle is 50%.
6. When CLKOUT4_CASCADE = TRUE, MMCM_FOUTMIN is 0.036 MHz.
DS181 (v1.27.1) July 3, 2024 **Product Specification**
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39
**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
## **PLL Switching Characteristics**
## _Table 38:_ **PLL Specification**
|**Symbol**|**Description**|**Speed Grade**<br>~~pO~~|**Speed Grade**<br>~~pO~~|**Speed Grade**<br>~~pO~~|**Speed Grade**<br>~~pO~~|**Speed Grade**<br>~~pO~~|**Units**<br>~~ee~~|
|---|---|---|---|---|---|---|---|
|||**1.0V**<br>~~pO~~<br>~~esee~~<br>~~ee~~|||**0.95V**<br>~~pO~~<br>~~ee~~|**0.9V**<br>~~pO~~<br>~~ee~~||
|||**-3**<br>~~es~~|**-2/-2LE**<br>~~ee~~|**-1**<br>~~ee~~|**-1LI**<br>~~ee~~|**-2LE**<br>~~ee~~||
|PLL_FINMAX<br>~~GG~~|Maximum input clock frequency<br>~~GG~~|800.00<br>~~es ~~<br>~~GG~~|800.00<br> ~~ee~~<br>~~GG~~<br>~~GO~~|800.00<br>~~ee~~<br>~~GG~~<br>~~GO~~|800.00<br>~~ee ~~<br>~~GG~~|800.00<br> ~~ee~~<br>~~GG~~|MHz<br>~~ee~~<br>~~GG~~|
|PLL_FINMIN<br>~~GG~~<br>~~CG~~|Minimum input clock frequency<br>~~GG~~<br>~~CG~~|19.00<br>~~GG~~<br>~~CG~~|19.00<br>~~GG~~<br>~~CG~~<br>~~GO~~|19.00<br>~~GG~~<br>~~CG~~<br>~~GO~~|19.00<br>~~GG~~<br>~~CG~~|19.00<br>~~GG~~<br>~~CG~~|MHz<br>~~GG~~<br>~~CG~~|
|PLL_FINJITTER<br>~~Ce~~|Maximum input clock period jitter<br>~~Ce~~|< 20% of clock input period or 1 ns Max<br>~~GO~~<br>~~Ce~~||||||
|PLL_FINDUTY<br>~~Ce~~<br>~~a~~|Allowable input duty cycle: 19—49 MHz<br>~~Ce~~<br>~~a~~|25<br>~~Ce~~|25<br>~~Ce~~|25<br>~~Ce~~|25<br>~~Ce~~|25<br>~~Ce~~|%<br>~~Ce~~|
||Allowable input duty cycle: 50—199 MHz<br>~~a~~<br>~~GG~~|30<br>~~GG~~|30<br>~~GG~~|30<br>~~GG~~|30<br>~~GG~~|30<br>~~GG~~|%<br>~~GG~~|
||Allowable input duty cycle: 200—399 MHz<br>~~GC~~|35<br>~~GC~~|35<br>~~GC~~|35<br>~~GC~~|35<br>~~GC~~|35<br>~~GC~~|%<br>~~GC~~|
||Allowable input duty cycle: 400—499 MHz<br>~~GC~~<br>~~a~~|40<br>~~GC~~|40<br>~~GC~~|40<br>~~GC~~|40<br>~~GC~~|40<br>~~GC~~|%<br>~~GC~~|
||Allowable input duty cycle: >500 MHz<br>~~a~~<br>~~GG~~|45<br>~~GG~~<br>~~GG~~|45<br>~~GG~~<br>~~GG~~|45<br>~~GG~~|45<br>~~GG~~|45<br>~~GG~~|%<br>~~GG~~|
|PLL_FVCOMIN<br>~~Ge~~<br>~~a~~|Minimum PLL VCO frequency<br>~~Ge~~|800.00<br>~~Ge~~<br>~~GG~~|800.00<br>~~Ge~~<br>~~GG~~|800.00<br>~~Ge~~|800.00<br>~~Ge~~|800.00<br>~~Ge~~|MHz<br>~~Ge~~|
|PLL_FVCOMAX<br>~~Ge~~<br>~~a~~|Maximum PLL VCO frequency<br>~~Ge~~<br>~~GO~~|2133.00<br>~~Ge~~<br>~~GG~~<br>~~GO~~|1866.00<br>~~Ge~~<br>~~GG~~<br>~~GO~~|1600.00<br>~~Ge~~|1600.00<br>~~Ge~~|1600.00<br>~~Ge~~|MHz<br>~~Ge~~|
|PLL_FBANDWIDTH<br>~~a~~<br>~~pyr~~<br>~~ee~~|Low PLL bandwidth at typical(1)<br>~~GO~~<br>~~pyr~~|1.00<br>~~GG~~<br>~~GO~~<br>~~pyr~~|1.00<br>~~GG~~<br>~~GO~~<br>~~pyr~~|1.00<br>~~pyr~~|1.00<br>~~pyr~~|1.00<br>~~pyr~~|MHz<br>~~pyr~~|
||High PLL bandwidth at typical(1)<br>~~pyr~~<br>~~GG~~|4.00<br>~~pyr~~<br>~~GG~~|4.00<br>~~pyr~~<br>~~GG~~|4.00<br>~~pyr~~<br>~~GG~~|4.00<br>~~pyr~~<br>~~GG~~|4.00<br>~~pyr~~<br>~~GG~~|MHz<br>~~pyr~~<br>~~GG~~|
|PLL_TSTATPHAOFFSET<br>~~pyr~~<br>~~ee~~|Static phase offset of the PLL outputs(2)<br>~~pyr~~<br>~~GG~~|0.12<br>~~pyr~~<br>~~GG~~|0.12<br>~~pyr~~<br>~~GG~~<br>~~D~~|0.12<br>~~pyr~~<br>~~GG~~|0.12<br>~~pyr~~<br>~~GG~~|0.12<br>~~pyr~~<br>~~GG~~|ns<br>~~pyr~~<br>~~GG~~|
|PLL_TOUTJITTER<br>~~ee~~<br>~~GG~~<br>~~a~~|PLL output jitter<br>~~GG~~<br>~~GG~~|Note 3<br>~~GG~~<br>~~D~~<br>~~GG~~<br>~~GG~~||||||
|PLL_TOUTDUTY<br>~~Ge~~<br>~~a~~|PLL output clock duty-cycle precision(4)<br>~~Ge~~|0.20<br>~~Ge~~<br>~~GG~~|0.20<br>~~Ge~~<br>~~GG~~|0.20<br>~~Ge~~|0.20<br>~~Ge~~|0.25<br>~~Ge~~|ns<br>~~Ge~~|
|PLL_TLOCKMAX<br>~~Ge~~<br>~~a~~|PLL maximum lock time<br>~~Ge~~<br>~~GO~~|100.00<br>~~Ge~~<br>~~GG~~<br>~~GO~~<br>~~GG~~|100.00<br>~~Ge~~<br>~~GG~~<br>~~GO~~<br>~~GG~~|100.00<br>~~Ge~~<br>~~GG~~|100.00<br>~~Ge~~|100.00<br>~~Ge~~|µs<br>~~Ge~~|
|PLL_FOUTMAX<br>~~a~~<br>~~Ce~~<br>~~a~~|PLL maximum output frequency<br>~~GO~~<br>~~Ce~~<br>|800.00<br>~~GG~~<br>~~GO~~<br>~~Ce~~<br>~~GG~~<br>~~GG~~<br>|800.00<br>~~GG~~<br>~~GO~~<br>~~Ce~~<br>~~GG~~<br>~~GG~~<br>|800.00<br>~~Ce~~<br>~~GG~~<br>~~GG~~<br>|800.00<br>~~Ce~~<br>|800.00<br>~~Ce~~<br>|MHz<br>~~Ce~~<br>|
|PLL_FOUTMIN<br>~~Ge~~<br>~~a~~|PLL minimum output frequency(5)<br>~~Ge~~<br>|6.25<br>~~GG~~<br>~~Ge~~<br>~~GG~~<br>|6.25<br>~~GG~~<br>~~Ge~~<br>~~GG~~<br>|6.25<br>~~GG~~<br>~~Ge~~<br>~~GG~~<br>|6.25<br>~~Ge~~<br>|6.25<br>~~Ge~~<br>|MHz<br>~~Ge~~<br>|
|PLL_TEXTFDVAR<br>~~Ge~~<br>~~a~~|External clock feedback variation<br>~~Ge~~<br>|< 20% of clock input period or 1 ns Max<br>~~Ge~~<br>~~GG~~<br>||||||
|PLL_RSTMINPULSE<br>~~aGG~~|Minimum reset pulse width<br>~~GG~~|5.00<br>~~GG~~<br>~~GG~~|5.00<br>~~GG~~<br>~~GG~~|5.00<br>~~GG~~<br>~~GG~~|5.00<br>~~GG~~|5.00<br>~~GG~~|ns<br>~~GG~~|
|PLL_FPFDMAX|Maximum frequency at the phase<br>frequency detector|550.00|500.00|450.00|450.00|450.00|MHz|
|PLL_FPFDMIN|Minimum frequency at the phase<br>frequency detector|19.00|19.00|19.00|19.00|19.00|MHz|
|PLL_TFBDELAY<br>~~a~~|Maximum delay in the feedback path<br>|3 ns Max or one CLKIN cycle<br>||||||
|**Dynamic Reconfiguration Port (DRP) for PLL Before and After DCLK**<br>~~ape~~||||||||
|TPLLDCK_DADDR/<br>TPLLCKD_DADDR<br>~~pe~~|Setup and hold of D address<br>~~pe~~|1.25/0.15<br>~~pe~~|1.40/0.15<br>~~pe~~|1.63/0.15<br>~~pe~~|1.63/0.15<br>~~pe~~|1.43/0.00<br>~~pe~~|ns, Min<br>~~pe~~|
|TPLLDCK_DI/<br>TPLLCKD_DI|Setup and hold of D input|1.25/0.15|1.40/0.15|1.63/0.15|1.63/0.15|1.43/0.00|ns, Min|
|TPLLDCK_DEN/<br>TPLLCKD_DEN|Setup and hold of D enable|1.76/0.00|1.97/0.00|2.29/0.00|2.29/0.00|2.40/0.00|ns, Min|
|TPLLDCK_DWE/<br>TPLLCKD_DWE|Setup and hold of D write enable|1.25/0.15<br>~~GO~~|1.40/0.15<br>~~GO~~|1.63/0.15<br>~~GO~~|1.63/0.15|1.43/0.00|ns, Min|
|TPLLCKO_DRDY<br>~~Ce~~|CLK to out of DRDY<br>~~Ce~~|0.65<br>~~Ce~~<br>~~GO~~|0.72<br>~~Ce~~<br>~~GO~~|0.99<br>~~Ce~~<br>~~GO~~|0.99<br>~~Ce~~|0.99<br>~~Ce~~|ns, Max<br>~~Ce~~|
DS181 (v1.27.1) July 3, 2024 **Product Specification**
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40
**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 38:_ **PLL Specification** _**(Cont’d)**_
|**Symbol**|**Description**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|---|
|||**1.0V**|||**0.95V**|**0.9V**||
|||**-3**|**-2/-2LE**|**-1**|**-1LI**|**-2LE**||
|FDCK|DCLK frequency|200.00|200.00|200.00|200.00|100.00|MHz, Max|
## **Notes:**
1. The PLL does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies.
2. The static offset is measured between any PLL outputs with identical phase.
3. Values for this parameter are available in the Clocking Wizard. See http://www.xilinx.com/products/intellectual-property/clocking_wizard.html.
4. Includes global clock buffer.
5. Calculated as FVCO/128 assuming output duty cycle is 50%.
## **Device Pin-to-Pin Output Parameter Guidelines**
_Table 39:_ **Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Near Clock Region)[(1)]**
|**Symbol**|**Description**|**Device**|**Speed Grade**<br>~~pO~~|**Speed Grade**<br>~~pO~~|**Speed Grade**<br>~~pO~~|**Speed Grade**<br>~~pO~~|**Speed Grade**<br>~~pO~~|**Speed Grade**<br>~~pO~~|**Units**|
|---|---|---|---|---|---|---|---|---|---|
||||**1.0V**<br>~~pO~~||||**0.95V**<br>~~pO~~|**0.9V**<br>~~pO~~||
||||**-3**<br>~~ee~~|**-2/-2LE**<br>~~ee~~|**-1**<br>~~ee ~~|**-1M/-1Q**<br> ~~ee~~|**-1LI**<br>~~ee~~|**-2LE**||
|SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate,_without_MMCM/PLL.<br>~~pC~~||||||||||
|TICKOF<br>~~pC~~|Clock-capable clock input and OUTFF at<br>pins/banks closest to the BUFGs_without_<br>MMCM/PLL (near clock region)(2)<br>~~pC~~<br>~~po~~<br>~~po~~|XC7A12T<br>~~pC~~<br>~~ee~~|4.97<br>~~pC~~<br>~~ee~~|5.55<br>~~pC~~<br>~~ee~~|6.44<br>~~pC~~<br>~~ee~~|N/A<br>~~pC~~<br>~~ee~~|6.44<br>~~pC~~<br>~~ee~~|7.38<br>~~pC~~<br>~~ee~~|ns<br>~~pC~~<br>~~ee~~|
|||XC7A15T<br>~~ee~~<br>~~es~~|5.10<br>~~ee~~<br>|5.70<br>~~ee~~<br>|6.61<br>~~ee~~<br>|N/A<br>~~ee~~<br>|6.61<br>~~ee~~<br>|7.56<br>~~ee~~<br>|ns<br>~~ee~~<br>|
|||XC7A25T<br>~~ee~~<br>~~es~~|4.97<br>~~ee~~<br>|5.55<br>~~ee~~<br>|6.44<br>~~ee~~<br>|N/A<br>~~ee~~<br>|6.44<br>~~ee~~<br>|7.38<br>~~ee~~<br>|ns<br>~~ee~~<br>|
|||XC7A35T<br>~~eses~~|5.10<br>~~es~~|5.70<br>~~es~~|6.61<br>~~es~~|N/A<br>~~es~~|6.61<br>~~es~~|7.56<br>~~es~~|ns<br>~~es~~|
|||XC7A50T<br>~~ee~~<br>~~es~~|5.10<br>~~ee~~<br>|5.70<br>~~ee~~<br>|6.61<br>~~ee~~<br>|N/A<br>~~ee~~<br>|6.61<br>~~ee~~<br>|7.56<br>~~ee~~<br>|ns<br>~~ee~~<br>|
|||XC7A75T<br>~~ee~~<br>~~es~~|5.14<br>~~ee~~<br>|5.74<br>~~ee~~<br>|6.72<br>~~ee~~<br>|N/A<br>~~ee~~<br>|6.72<br>~~ee~~<br>|7.62<br>~~ee~~<br>|ns<br>~~ee~~<br>|
|||XC7A100T<br>~~eses~~|5.14<br>~~es~~|5.74<br>~~es~~|6.72<br>~~es~~|N/A<br>~~es~~|6.72<br>~~es~~|7.62<br>~~es~~|ns<br>~~es~~|
|||XC7A200T<br>~~ee~~<br>~~es~~|5.47<br>~~ee~~<br>|6.11<br>~~ee~~<br>|7.16<br>~~ee~~<br>|N/A<br>~~ee~~<br>|7.16<br>~~ee~~<br>|8.08<br>~~ee~~<br>|ns<br>~~ee~~<br>|
|||XA7A12T<br>~~ee~~<br>~~es~~|N/A<br>~~ee~~<br>|5.55<br>~~ee~~<br>|6.44<br>~~ee~~<br>|6.44<br>~~ee~~<br>|N/A<br>~~ee~~<br>|N/A<br>~~ee~~<br>|ns<br>~~ee~~<br>|
|||XA7A15T<br>~~eses~~|N/A<br>~~es~~|5.70<br>~~es~~|6.61<br>~~es~~|6.61<br>~~es~~|N/A<br>~~es~~|N/A<br>~~es~~|ns<br>~~es~~|
|||XA7A25T<br>~~ee~~|N/A<br>~~ee~~|5.55<br>~~ee~~|6.44<br>~~ee~~|6.44<br>~~ee~~|N/A<br>~~ee~~|N/A<br>~~ee~~|ns<br>~~ee~~|
|||XA7A35T<br>~~ee~~<br>~~se~~|N/A<br>~~ee~~<br>~~se~~|5.70<br>~~ee~~<br>~~se~~|6.61<br>~~ee~~<br>~~se~~|6.61<br>~~ee~~<br>~~se~~|N/A<br>~~ee~~<br>~~se~~|N/A<br>~~ee~~<br>~~se~~|ns<br>~~ee~~<br>~~se~~|
|||XA7A50T<br>~~se~~<br>~~es~~|N/A<br>~~se~~<br>~~es~~|5.70<br>~~se~~<br>~~es~~|6.61<br>~~se~~<br>~~es~~|6.61<br>~~se~~<br>~~es~~|N/A<br>~~se~~<br>~~es~~|N/A<br>~~se~~<br>~~es~~|ns<br>~~se~~<br>~~es~~|
|||XA7A75T<br>~~ee~~<br>~~po~~|N/A<br>~~ee~~|5.74<br>~~ee~~|6.72<br>~~ee~~|6.72<br>~~ee~~|N/A<br>~~ee~~|N/A<br>~~ee~~|ns<br>~~ee~~|
|||XA7A100T<br>~~ee~~<br>~~po~~|N/A<br>~~ee~~|5.74<br>~~ee~~|6.72<br>~~ee~~|6.72<br>~~ee~~|N/A<br>~~ee~~|N/A<br>~~ee~~|ns<br>~~ee~~|
|||XQ7A50T<br>~~po~~<br>~~a~~|N/A<br>|5.70<br>|6.61<br>|6.61<br>|6.61<br>|N/A<br>|ns<br>|
|||XQ7A100T<br>~~ee~~<br>~~po~~|N/A<br>~~ee~~|5.74<br>~~ee~~|6.72<br>~~ee~~|6.72<br>~~ee~~|6.72<br>~~ee~~|N/A<br>~~ee~~|ns<br>~~ee~~|
|||XQ7A200T<br>~~ee~~<br>~~po~~|N/A<br>~~ee~~|6.11<br>~~ee~~|7.16<br>~~ee~~|7.16<br>~~ee~~|7.16<br>~~ee~~|N/A<br>~~ee~~|ns<br>~~ee~~|
## **Notes:**
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Refer to the Die Level Bank Numbering Overview section of _7 Series FPGA Packaging and Pinout Specification_ (UG475).
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41
**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 40:_ **Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Far Clock Region)[(1)]**
|**Symbol**|**Description**|**Device**|**Speed Grade**<br>~~pO~~|**Speed Grade**<br>~~pO~~|**Speed Grade**<br>~~pO~~|**Speed Grade**<br>~~pO~~|**Speed Grade**<br>~~pO~~|**Speed Grade**<br>~~pO~~|**Units**<br>~~ee~~|
|---|---|---|---|---|---|---|---|---|---|
||||**1.0V**<br>~~pO~~<br>~~eeee~~||||**0.95V**<br>~~pO~~<br>~~ee~~|**0.9V**<br>~~pO~~<br>~~ee~~<br>~~ee~~||
||||**-3**<br>~~ee~~|**-2/-2LE**<br>~~ee~~|**-1**<br>~~ee~~|**-1M/-1Q**<br>~~ee~~|**-1LI**<br>~~ee~~|**-2LE**<br>~~ee~~<br>~~ee~~||
|SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate,_without_MMCM/PLL.<br>~~eeee~~<br>~~ee~~||||||||||
|TICKOFFAR|Clock-capable clock input and OUTFF<br>at pins/banks farthest from the BUFGs<br>_without_MMCM/PLL (far clock region)(2)|XC7A12T<br>~~se~~|4.97<br>~~se~~|5.55<br>~~se~~|6.44<br>~~se~~|N/A<br>~~se~~|6.44<br>~~se~~|7.38<br>~~se~~|ns<br>~~se~~|
|||XC7A15T<br>~~se~~<br>~~es~~|5.10<br>~~se~~<br>~~es~~|5.70<br>~~se~~<br>~~es~~|6.61<br>~~se~~<br>~~es~~|N/A<br>~~se~~<br>~~es~~|6.61<br>~~se~~<br>~~es~~|7.57<br>~~se~~<br>~~es~~|ns<br>~~se~~<br>~~es~~|
|||XC7A25T<br>~~es~~<br>~~ee~~|4.97<br>~~es~~<br>~~ee~~|5.55<br>~~es~~<br>~~ee~~|6.44<br>~~es~~<br>~~ee~~|N/A<br>~~es~~<br>~~ee~~|6.44<br>~~es~~<br>~~ee~~|7.38<br>~~es~~<br>~~ee~~|ns<br>~~es~~<br>~~ee~~|
|||XC7A35T<br>~~a~~|5.10<br>|5.70<br>|6.61<br>|N/A<br>|6.61<br>|7.57<br>|ns<br>|
|||XC7A50T<br>~~aes~~|5.10<br>~~es~~|5.70<br>~~es~~|6.61<br>~~es~~|N/A<br>~~es~~|6.61<br>~~es~~|7.57<br>~~es~~|ns<br>~~es~~|
|||XC7A75T<br>~~es~~<br>~~ee~~|5.38<br>~~es~~<br>~~ee~~|6.01<br>~~es~~<br>~~ee~~|7.02<br>~~es~~<br>~~ee~~|N/A<br>~~es~~<br>~~ee~~|7.02<br>~~es~~<br>~~ee~~|7.94<br>~~es~~<br>~~ee~~|ns<br>~~es~~<br>~~ee~~|
|||XC7A100T<br>~~a~~|5.38<br>|6.01<br>|7.02<br>|N/A<br>|7.02<br>|7.94<br>|ns<br>|
|||XC7A200T<br>~~aes~~|6.17<br>~~es~~|6.89<br>~~es~~|8.05<br>~~es~~|N/A<br>~~es~~|8.05<br>~~es~~|9.03<br>~~es~~|ns<br>~~es~~|
|||XA7A12T<br>~~es~~<br>~~ee~~|N/A<br>~~es~~<br>~~ee~~|5.55<br>~~es~~<br>~~ee~~|6.44<br>~~es~~<br>~~ee~~|6.44<br>~~es~~<br>~~ee~~|N/A<br>~~es~~<br>~~ee~~|N/A<br>~~es~~<br>~~ee~~|ns<br>~~es~~<br>~~ee~~|
|||XA7A15T<br>~~a~~|N/A<br>|5.70<br>|6.61<br>|6.61<br>|N/A<br>|N/A<br>|ns<br>|
|||XA7A25T<br>~~aes~~|N/A<br>~~es~~|5.55<br>~~es~~|6.44<br>~~es~~|6.44<br>~~es~~|N/A<br>~~es~~|N/A<br>~~es~~|ns<br>~~es~~|
|||XA7A35T<br>~~es~~<br>~~ee~~|N/A<br>~~es~~<br>~~ee~~|5.70<br>~~es~~<br>~~ee~~|6.61<br>~~es~~<br>~~ee~~|6.61<br>~~es~~<br>~~ee~~|N/A<br>~~es~~<br>~~ee~~|N/A<br>~~es~~<br>~~ee~~|ns<br>~~es~~<br>~~ee~~|
|||XA7A50T<br>~~a~~|N/A<br>|5.70<br>|6.61<br>|6.61<br>|N/A<br>|N/A<br>|ns<br>|
|||XA7A75T<br>~~aes~~|N/A<br>~~es~~|6.01<br>~~es~~|7.02<br>~~es~~|7.02<br>~~es~~|N/A<br>~~es~~|N/A<br>~~es~~|ns<br>~~es~~|
|||XA7A100T<br>~~es~~<br>~~ee~~|N/A<br>~~es~~<br>~~ee~~|6.01<br>~~es~~<br>~~ee~~|7.02<br>~~es~~<br>~~ee~~|7.02<br>~~es~~<br>~~ee~~|N/A<br>~~es~~<br>~~ee~~|N/A<br>~~es~~<br>~~ee~~|ns<br>~~es~~<br>~~ee~~|
|||XQ7A50T<br>~~a~~|N/A<br>|5.70<br>|6.61<br>|6.61<br>|6.61<br>|N/A<br>|ns<br>|
|||XQ7A100T<br>~~aes~~|N/A<br>~~es~~|6.01<br>~~es~~|7.02<br>~~es~~|7.02<br>~~es~~|7.02<br>~~es~~|N/A<br>~~es~~|ns<br>~~es~~|
|||XQ7A200T<br>~~es~~<br>~~se~~|N/A<br>~~es~~<br>~~se~~|6.89<br>~~es~~<br>~~se~~|8.05<br>~~es~~<br>~~se~~|8.05<br>~~es~~<br>~~se~~|8.05<br>~~es~~<br>~~se~~|N/A<br>~~es~~<br>~~se~~|ns<br>~~es~~<br>~~se~~|
## **Notes:**
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Refer to the Die Level Bank Numbering Overview section of _7 Series FPGA Packaging and Pinout Specification_ (UG475).
DS181 (v1.27.1) July 3, 2024 **Product Specification**
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**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 41:_ **Clock-Capable Clock Input to Output Delay With MMCM**
|**Symbol**<br>~~a~~|**Description**<br>~~a~~|**Device**<br>~~a~~|**Speed Grade**<br>~~Pp~~<br>~~a~~|**Speed Grade**<br>~~Pp~~<br>~~a~~|**Speed Grade**<br>~~Pp~~<br>~~a~~|**Speed Grade**<br>~~Pp~~<br>~~a~~|**Speed Grade**<br>~~Pp~~<br>~~a~~|**Speed Grade**<br>~~Pp~~<br>~~a~~|**Units**|
|---|---|---|---|---|---|---|---|---|---|
||||**1.0V**<br>~~Pp~~<br>~~a~~<br>~~eeee~~<br>~~ee~~||||**0.95V**<br>~~Pp~~<br>~~a~~<br>~~ee~~|**0.9V**<br>~~Pp~~<br>~~a~~<br>~~ee~~||
||||**-3**<br>~~a~~<br>~~ee~~|**-2/-2LE**<br>~~a~~<br>~~ee~~|**-1**<br>~~a~~<br>~~ee~~|**-1M/-1Q**<br>~~a~~<br>~~ee~~|**-1LI**<br>~~a~~<br>~~ee~~|**-2LE**<br>~~a~~<br>~~ee~~||
|SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate,_with_MMCM.<br>~~ee ee~~<br>~~ee~~<br>~~ee~~<br>~~pe~~<br>~~es~~||||||||||
|TICKOFMMCMCC<br>~~pe~~|Clock-capable clock input and<br>OUTFF_with_MMCM<br>~~pe~~<br>~~—~~<br>~~—~~<br>~~—~~<br>~~—~~<br>~~—~~<br>~~—~~|XC7A12T<br>~~pe~~<br>~~es~~<br>~~—~~<br>~~|~~|1.00<br>~~pe~~<br>~~|~~|1.00<br>~~pe~~<br>~~|~~|1.00<br>~~pe~~|N/A<br>~~pe~~|1.00<br>~~pe~~|1.78<br>~~pe~~|ns<br>~~pe~~|
|||XC7A15T<br>~~es~~<br>~~—~~<br>~~|~~|1.00<br>~~|~~|1.00<br>~~|~~|1.00|N/A|1.00|1.78|ns|
|||XC7A25T<br>~~—~~<br>~~|~~<br>~~ee~~|1.00<br>~~|~~<br>~~ee~~|1.00<br>~~|~~<br>~~ee~~|1.00<br>~~ee~~|N/A<br>~~ee~~|1.00<br>~~ee~~|1.78<br>~~ee~~|ns<br>~~ee~~|
|||XC7A35T<br>~~a~~<br>~~—~~<br>~~|~~|1.00<br>~~|~~|1.00|1.00|N/A|1.00|1.78|ns|
|||XC7A50T<br>~~a~~<br>~~—~~<br>~~|~~|1.00<br>~~|~~|1.00|1.00|N/A|1.00|1.78|ns|
|||XC7A75T<br>~~—~~<br>~~|~~<br>~~ee~~|1.00<br>~~|~~<br>~~ee~~|1.00<br>~~ee~~|1.00<br>~~ee~~|N/A<br>~~ee~~|1.00<br>~~ee~~|1.79<br>~~ee~~|ns<br>~~ee~~|
|||XC7A100T<br>~~a~~<br>~~—~~<br>~~|~~|1.00<br>~~|~~|1.00|1.00|N/A|1.00|1.79|ns|
|||XC7A200T<br>~~a~~<br>~~—~~<br>~~|~~|1.01<br>~~|~~|1.02|1.04|N/A|1.04|1.84|ns|
|||XA7A12T<br>~~—~~<br>~~|~~<br>~~ee~~|N/A<br>~~|~~<br>~~ee~~|1.00<br>~~ee~~|1.00<br>~~ee~~|1.00<br>~~ee~~|N/A<br>~~ee~~|N/A<br>~~ee~~|ns<br>~~ee~~|
|||XA7A15T<br>~~a~~<br>~~—~~<br>~~|~~|N/A<br>~~|~~|1.00|1.00|1.00|N/A|N/A|ns|
|||XA7A25T<br>~~a~~<br>~~—~~<br>~~|~~|N/A<br>~~|~~|1.00|1.00|1.00|N/A|N/A|ns|
|||XA7A35T<br>~~—~~<br>~~|~~<br>~~ee~~|N/A<br>~~|~~<br>~~ee~~|1.00<br>~~ee~~|1.00<br>~~ee~~|1.00<br>~~ee~~|N/A<br>~~ee~~|N/A<br>~~ee~~|ns<br>~~ee~~|
|||XA7A50T<br>~~ee~~<br>~~a~~<br>~~—~~<br>~~|~~|N/A<br>~~ee~~<br>~~|~~|1.00<br>~~ee~~|1.00<br>~~ee~~|1.00<br>~~ee~~|N/A<br>~~ee~~|N/A<br>~~ee~~|ns<br>~~ee~~|
|||XA7A75T<br>~~a~~<br>~~—~~<br>~~|~~|N/A<br>~~|~~|1.00|1.00|1.00|N/A|N/A|ns|
|||XA7A100T<br>~~—~~<br>~~|~~<br>~~ee~~|N/A<br>~~|~~<br>~~ee~~|1.00<br>~~ee~~|1.00<br>~~ee~~|1.00<br>~~ee~~|N/A<br>~~ee~~|N/A<br>~~ee~~|ns<br>~~ee~~|
|||XQ7A50T<br>~~a~~<br>~~—~~<br>~~|~~|N/A<br>~~|~~|1.00|1.00|1.00|1.00|N/A|ns|
|||XQ7A100T<br>~~a~~<br>~~—~~<br>~~|~~<br>~~es~~|N/A<br>~~|~~|1.00|1.00|1.00|1.00|N/A|ns|
|||XQ7A200T<br>~~—~~<br>~~|~~<br>~~es~~|N/A<br>~~|~~|1.02|1.04|1.04|1.04|N/A|ns|
## **Notes:**
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. MMCM output jitter is already included in the timing calculation.
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**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 42:_ **Clock-Capable Clock Input to Output Delay With PLL**
|**Symbol**|**Description**|**Device**|**Speed Grade**<br>~~pO~~|**Speed Grade**<br>~~pO~~|**Speed Grade**<br>~~pO~~|**Speed Grade**<br>~~pO~~|**Speed Grade**<br>~~pO~~|**Speed Grade**<br>~~pO~~|**Units**|
|---|---|---|---|---|---|---|---|---|---|
||||**1.0V**<br>~~pO~~<br>~~eeee~~||||**0.95V**<br>~~pO~~<br>~~ee~~|**0.9V**<br>~~pO~~<br>~~ee~~||
||||**-3**<br>~~ee~~|**-2/-2LE**<br>~~ee~~|**-1**<br>~~ee~~|**-1M/-1Q**<br>~~ee~~|**-1LI**<br>~~ee~~|**-2LE**<br>~~ee~~||
|SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate,_with_PLL.<br>~~eeee~~<br>~~PC~~||||||||||
|TICKOFPLLCC<br>~~PC~~|Clock-capable clock input and<br>OUTFF_with_PLL<br>~~PC~~|XC7A12T<br>~~PC~~<br>~~a~~|0.83<br>~~PC~~<br>|0.83<br>~~PC~~<br>|0.83<br>~~PC~~<br>|N/A<br>~~PC~~<br>|0.83<br>~~PC~~<br>|1.38<br>~~PC~~<br>|ns<br>~~PC~~<br>|
|||XC7A15T<br>~~aes~~|0.82<br>~~es~~|0.82<br>~~es~~|0.82<br>~~es~~|N/A<br>~~es~~|0.82<br>~~es~~|1.39<br>~~es~~|ns<br>~~es~~|
|||XC7A25T<br>~~es~~<br>~~se~~|0.83<br>~~es~~<br>~~se~~|0.83<br>~~es~~<br>~~se~~|0.83<br>~~es~~<br>~~se~~|N/A<br>~~es~~<br>~~se~~|0.83<br>~~es~~<br>~~se~~|1.38<br>~~es~~<br>~~se~~|ns<br>~~es~~<br>~~se~~|
|||XC7A35T<br>~~a~~<br>~~Rs~~|0.82<br>~~ee~~|0.82<br>~~ee~~|0.82<br>~~ee~~|N/A<br>~~ee~~|0.82<br>~~ee~~|1.39<br>~~ee~~|ns<br>~~ee~~|
|||XC7A50T<br>~~a~~<br>~~Rs~~|0.82<br>~~ee~~|0.82<br>~~ee~~|0.82<br>~~ee~~|N/A<br>~~ee~~|0.82<br>~~ee~~|1.39<br>~~ee~~|ns<br>~~ee~~|
|||XC7A75T<br>~~Rs~~<br>~~se~~|0.82<br>~~ee~~<br>~~se~~|0.82<br>~~ee~~<br>~~se~~|0.82<br>~~ee~~<br>~~se~~|N/A<br>~~ee~~<br>~~se~~|0.82<br>~~ee~~<br>~~se~~|1.40<br>~~ee~~<br>~~se~~|ns<br>~~ee~~<br>~~se~~|
|||XC7A100T<br>~~a~~<br>~~Rs~~|0.82<br>~~ee~~|0.82<br>~~ee~~|0.82<br>~~ee~~|N/A<br>~~ee~~|0.82<br>~~ee~~|1.40<br>~~ee~~|ns<br>~~ee~~|
|||XC7A200T<br>~~a~~<br>~~Rs~~|0.81<br>~~ee~~|0.81<br>~~ee~~|0.81<br>~~ee~~|N/A<br>~~ee~~|0.81<br>~~ee~~|1.45<br>~~ee~~|ns<br>~~ee~~|
|||XA7A12T<br>~~Rs~~<br>~~se~~|N/A<br>~~ee~~<br>~~se~~|0.83<br>~~ee~~<br>~~se~~|0.83<br>~~ee~~<br>~~se~~|0.83<br>~~ee~~<br>~~se~~|N/A<br>~~ee~~<br>~~se~~|N/A<br>~~ee~~<br>~~se~~|ns<br>~~ee~~<br>~~se~~|
|||XA7A15T<br>~~a~~<br>~~Rs~~|N/A<br>~~ee~~|0.82<br>~~ee~~|0.82<br>~~ee~~|0.82<br>~~ee~~|N/A<br>~~ee~~|N/A<br>~~ee~~|ns<br>~~ee~~|
|||XA7A25T<br>~~a~~<br>~~Rs~~|N/A<br>~~ee~~|0.83<br>~~ee~~|0.83<br>~~ee~~|0.83<br>~~ee~~|N/A<br>~~ee~~|N/A<br>~~ee~~|ns<br>~~ee~~|
|||XA7A35T<br>~~Rs~~<br>~~se~~|N/A<br>~~ee~~<br>~~se~~|0.82<br>~~ee~~<br>~~se~~|0.82<br>~~ee~~<br>~~se~~|0.82<br>~~ee~~<br>~~se~~|N/A<br>~~ee~~<br>~~se~~|N/A<br>~~ee~~<br>~~se~~|ns<br>~~ee~~<br>~~se~~|
|||XA7A50T<br>~~se~~<br>~~a~~<br>~~Rs~~|N/A<br>~~se~~<br>~~ee~~|0.82<br>~~se~~<br>~~ee~~|0.82<br>~~se~~<br>~~ee~~|0.82<br>~~se~~<br>~~ee~~|N/A<br>~~se~~<br>~~ee~~|N/A<br>~~se~~<br>~~ee~~|ns<br>~~se~~<br>~~ee~~|
|||XA7A75T<br>~~a~~<br>~~Rs~~|N/A<br>~~ee~~|0.82<br>~~ee~~|0.82<br>~~ee~~|0.82<br>~~ee~~|N/A<br>~~ee~~|N/A<br>~~ee~~|ns<br>~~ee~~|
|||XA7A100T<br>~~Rs~~<br>~~se~~|N/A<br>~~ee~~<br>~~se~~|0.82<br>~~ee~~<br>~~se~~|0.82<br>~~ee~~<br>~~se~~|0.82<br>~~ee~~<br>~~se~~|N/A<br>~~ee~~<br>~~se~~|N/A<br>~~ee~~<br>~~se~~|ns<br>~~ee~~<br>~~se~~|
|||XQ7A50T<br>~~a~~<br>~~Rs~~|N/A<br>~~ee~~|0.82<br>~~ee~~|0.82<br>~~ee~~|0.82<br>~~ee~~|0.82<br>~~ee~~|N/A<br>~~ee~~|ns<br>~~ee~~|
|||XQ7A100T<br>~~a~~<br>~~Rs~~|N/A<br>~~ee~~|0.82<br>~~ee~~|0.82<br>~~ee~~|0.82<br>~~ee~~|0.82<br>~~ee~~|N/A<br>~~ee~~|ns<br>~~ee~~|
|||XQ7A200T<br>~~Rs~~<br>~~se~~|N/A<br>~~ee~~<br>~~se~~|0.81<br>~~ee~~<br>~~se~~|0.81<br>~~ee~~<br>~~se~~|0.81<br>~~ee~~<br>~~se~~|0.81<br>~~ee~~<br>~~se~~|N/A<br>~~ee~~<br>~~se~~|ns<br>~~ee~~<br>~~se~~|
## **Notes:**
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. PLL output jitter is already included in the timing calculation.
_Table 43:_ **Pin-to-Pin, Clock-to-Out using BUFIO**
|**Symbol**|**Description**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|---|---|
|||**1.0V**||||**0.95V**|**0.9V**||
|||**-3**|**-2/-2LE**|**-1**|**-1M/-1Q**|**-1LI**|**-2LE**||
|SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with BUFIO.|||||||||
|TICKOFCS|Clock to out of I/O clock|5.01|5.61|6.64|6.64|6.64|7.32|ns|
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DS181 (v1.27.1) July 3, 2024 **Product Specification**
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**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
## **Device Pin-to-Pin Input Parameter Guidelines**
All devices are 100% functionally tested. Values are expressed in nanoseconds unless otherwise noted.
_Table 44:_ **Global Clock Input Setup and Hold Without MMCM/PLL with ZHOLD_DELAY on HR I/O Banks**
|**Symbol**|**Description**|**Device**|**Speed Grade**<br>~~pT~~|**Speed Grade**<br>~~pT~~|**Speed Grade**<br>~~pT~~|**Speed Grade**<br>~~pT~~|**Speed Grade**<br>~~pT~~|**Speed Grade**<br>~~pT~~|**Units**|
|---|---|---|---|---|---|---|---|---|---|
||||**1.0V**<br>~~pT~~||||**0.95V**<br>~~pT~~|**0.9V**<br>~~pT~~||
||||**-3**<br>~~a ee~~|**-2/-2LE**<br>~~ee~~|**-1**<br>~~ee~~|**-1M/-1Q**<br>~~ee~~|**-1LI**<br>~~ee~~|**-2LE**<br>~~ee~~||
|Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15 Standard.(1)<br>~~pC~~||||||||||
|TPSFD/<br>TPHFD<br>~~pC~~|Full delay (legacy delay<br>or default delay)<br>global clock input and<br>IFF(2)without<br>MMCM/PLL with<br>ZHOLD_DELAY on HR<br>I/O banks<br>~~pC~~<br>~~po~~<br>~~po~~<br>~~po~~<br>~~po~~<br>~~po~~<br>~~po~~<br>~~po~~|XC7A12T<br>~~pC~~<br>~~Gs~~<br>~~po~~|2.49/–0.37<br>~~pC~~<br>~~Gs~~<br>|2.67/–0.37<br>~~pC~~<br>~~eG~~<br>|3.12/–0.37<br>~~pC~~<br>~~eG~~<br>|N/A<br>~~pC~~<br>~~eG~~<br>|3.12/–0.37<br>~~pC~~<br>|5.13/–0.54<br>~~pC~~<br>|ns<br>~~pC~~<br>|
|||XC7A15T<br>~~Gs~~<br>~~po~~|2.47/–0.29<br>~~Gs~~<br>|2.65/–0.29<br>~~eG~~<br>|3.10/–0.29<br>~~eG~~<br>|N/A<br>~~eG~~<br>|3.10/–0.29<br>|5.10/–0.44<br>|ns<br>|
|||XC7A25T<br>~~pose~~|2.49/–0.37<br>~~se~~|2.67/–0.37<br>~~se~~|3.12/–0.37<br>~~se~~|N/A<br>~~se~~|3.12/–0.37<br>~~se~~|5.13/–0.54<br>~~se~~|ns<br>~~se~~|
|||XC7A35T<br>~~se~~<br>~~BG~~<br>~~po~~|2.47/–0.29<br>~~se~~<br>~~BG~~<br>|2.65/–0.29<br>~~se~~<br>~~BG~~<br>|3.10/–0.29<br>~~se~~<br>~~BG~~<br>|N/A<br>~~se~~<br>~~BG~~<br>|3.10/–0.29<br>~~se~~<br>~~BG~~<br>|5.10/–0.44<br>~~se~~<br>~~BG~~<br>|ns<br>~~se~~<br>~~BG~~<br>|
|||XC7A50T<br>~~BG~~<br>~~po~~|2.47/–0.29<br>~~BG~~<br>|2.65/–0.29<br>~~BG~~<br><br>~~se~~|3.10/–0.29<br>~~BG~~<br><br>~~se~~|N/A<br>~~BG~~<br>|3.10/–0.29<br>~~BG~~<br>|5.10/–0.44<br>~~BG~~<br>|ns<br>~~BG~~<br>|
|||XC7A75T<br>~~pose~~|2.69/–0.34<br>~~se~~|2.89/–0.34<br>~~se~~<br>~~se~~|3.34/–0.34<br>~~se~~<br>~~se~~|N/A<br>~~se~~|3.34/–0.34<br>~~se~~|5.66/–0.51<br>~~se~~|ns<br>~~se~~|
|||XC7A100T<br>~~se~~<br>~~GG~~<br>~~po~~|2.69/–0.34<br>~~se~~<br>~~GG~~<br>|2.89/–0.34<br>~~se~~<br>~~se~~<br>~~GG~~<br>|3.34/–0.34<br>~~se~~<br>~~se~~<br>~~GG~~<br>|N/A<br>~~se~~<br>~~GG~~<br>|3.34/–0.34<br>~~se~~<br>~~GG~~<br>|5.66/–0.51<br>~~se~~<br>~~GG~~<br>|ns<br>~~se~~<br>~~GG~~<br>|
|||XC7A200T<br>~~GG~~<br>~~po~~|3.03/–0.36<br>~~GG~~<br>|3.27/–0.36<br>~~GG~~<br><br>~~se~~|3.79/–0.36<br>~~GG~~<br><br>~~se~~|N/A<br>~~GG~~<br>|3.79/–0.36<br>~~GG~~<br>|6.66/–0.55<br>~~GG~~<br>|ns<br>~~GG~~<br>|
|||XA7A12T<br>~~pose~~<br>~~po~~|N/A<br>~~se~~<br>|2.67/–0.37<br>~~se~~<br>~~se~~<br>|3.12/–0.37<br>~~se~~<br>~~se~~<br>~~Ge~~<br>|3.12/–0.37<br>~~se~~<br>|N/A<br>~~se~~<br>|N/A<br>~~se~~<br>|ns<br>~~se~~<br>|
|||XA7A15T<br>~~se~~<br>~~Ge~~<br>~~po~~|N/A<br>~~se~~<br>~~Ge~~<br>|2.65/–0.29<br>~~se~~<br>~~se~~<br>~~Ge~~<br>|3.10/–0.29<br>~~se~~<br>~~se~~<br>~~Ge~~<br>~~Ge~~<br>|3.10/–0.29<br>~~se~~<br>~~Ge~~<br>|N/A<br>~~se~~<br>~~Ge~~<br>|N/A<br>~~se~~<br>~~Ge~~<br>|ns<br>~~se~~<br>~~Ge~~<br>|
|||XA7A25T<br>~~Ge~~<br>~~po~~|N/A<br>~~Ge~~<br>|2.67/–0.37<br>~~Ge~~<br><br>~~se~~|3.12/–0.37<br>~~Ge~~<br>~~Ge~~<br><br>~~se~~|3.12/–0.37<br>~~Ge~~<br>|N/A<br>~~Ge~~<br>|N/A<br>~~Ge~~<br>|ns<br>~~Ge~~<br>|
|||XA7A35T<br>~~pose~~<br>~~po~~|N/A<br>~~se~~<br>|2.65/–0.29<br>~~se~~<br>~~se~~<br>|3.10/–0.29<br>~~Ge~~<br>~~se~~<br>~~se~~<br>~~Ge~~<br>|3.10/–0.29<br>~~se~~<br>|N/A<br>~~se~~<br>|N/A<br>~~se~~<br>|ns<br>~~se~~<br>|
|||XA7A50T<br>~~se~~<br>~~Ge~~<br>~~po~~|N/A<br>~~se~~<br>~~Ge~~<br>|2.65/–0.29<br>~~se~~<br>~~se~~<br>~~Ge~~<br>|3.10/–0.29<br>~~se~~<br>~~se~~<br>~~Ge~~<br>~~Ge~~<br>|3.10/–0.29<br>~~se~~<br>~~Ge~~<br>|N/A<br>~~se~~<br>~~Ge~~<br>|N/A<br>~~se~~<br>~~Ge~~<br>|ns<br>~~se~~<br>~~Ge~~<br>|
|||XA7A75T<br>~~Ge~~<br>~~po~~|N/A<br>~~Ge~~<br>|2.89/–0.34<br>~~Ge~~<br><br>~~se~~|3.34/–0.34<br>~~Ge~~<br>~~Ge~~<br><br>~~se~~|3.34/–0.34<br>~~Ge~~<br>|N/A<br>~~Ge~~<br>|N/A<br>~~Ge~~<br>|ns<br>~~Ge~~<br>|
|||XA7A100T<br>~~pose~~<br>~~po~~|N/A<br>~~se~~|2.89/–0.34<br>~~se~~<br>~~se~~|3.34/–0.34<br>~~Ge~~<br>~~se~~<br>~~se~~<br>~~Ge~~|3.34/–0.34<br>~~se~~|N/A<br>~~se~~|N/A<br>~~se~~|ns<br>~~se~~|
|||XQ7A50T<br>~~se~~<br>~~Ge~~<br>~~po~~|N/A<br>~~se~~<br>~~Ge~~|2.65/–0.29<br>~~se~~<br>~~se~~<br>~~Ge~~|3.10/–0.29<br>~~se~~<br>~~se~~<br>~~Ge~~<br>~~Ge~~|3.10/–0.29<br>~~se~~<br>~~Ge~~|3.10/–0.29<br>~~se~~<br>~~Ge~~|N/A<br>~~se~~<br>~~Ge~~|ns<br>~~se~~<br>~~Ge~~|
|||XQ7A100T<br>~~Ge~~<br>~~po~~<br>~~po~~|N/A<br>~~Ge~~|2.89/–0.34<br>~~Ge~~|3.34/–0.34<br>~~Ge~~<br>~~Ge~~|3.34/–0.34<br>~~Ge~~|3.34/–0.34<br>~~Ge~~|N/A<br>~~Ge~~|ns<br>~~Ge~~|
|||XQ7A200T<br>~~po~~<br>~~po~~|N/A|3.27/–0.36|3.79/–0.36<br>~~Ge~~|3.79/–0.36|3.79/–0.36|N/A|ns|
## **Notes:**
1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage.
2. IFF = Input flip-flop or latch.
DS181 (v1.27.1) July 3, 2024 **Product Specification**
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**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 45:_ **Clock-Capable Clock Input Setup and Hold With MMCM**
|**Symbol**<br>~~So~~|**Description**<br>~~So~~|**Device**|**Speed Grade**<br>~~pd~~|**Speed Grade**<br>~~pd~~|**Speed Grade**<br>~~pd~~|**Speed Grade**<br>~~pd~~|**Speed Grade**<br>~~pd~~|**Speed Grade**<br>~~pd~~|**Units**|
|---|---|---|---|---|---|---|---|---|---|
||||**1.0V**<br>~~pd~~<br>~~a~~<br>~~eeee~~||||**0.95V**<br>~~pd~~<br>~~ee~~|**0.9V**<br>~~pd~~<br>~~ee~~||
||||**-3**<br>~~pd~~<br>~~a~~|**-2/-2LE**<br>~~pd~~<br>~~ee~~|**-1**<br>~~pd~~<br>~~ee~~|**-1M/-1Q**<br>~~pd~~<br>~~ee~~|**-1LI**<br>~~pd~~<br>~~ee~~|**-2LE**<br>~~pd~~<br>~~ee~~||
|Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15 Standard.(1)<br>~~a~~<br>~~eeee~~<br>~~|~~||||||||||
|TPSMMCMCC/<br>TPHMMCMCC<br>~~|~~|No delay clock-<br>capable clock input<br>and IFF(2)with<br>MMCM<br>~~|~~<br>~~RR~~<br>~~po~~<br>~~po~~<br>~~po~~<br>~~po~~<br>~~po~~|XC7A12T<br>~~|~~<br>~~ee~~<br>~~RR~~|2.37/–0.61 <br>~~|~~<br>~~ee~~<br>|2.69/–0.61 <br>~~|~~<br>~~ee~~<br>|3.21/–0.61<br>~~|~~<br>~~ee~~<br>|N/A<br>~~|~~<br>~~ee~~<br>|3.21/–0.61 <br>~~|~~<br>~~ee~~<br>|2.00/–0.47<br>~~|~~<br>~~ee~~<br>|ns<br>~~|~~<br>~~ee~~<br>|
|||XC7A15T<br>~~ee~~<br>~~RR~~|2.46/–0.62 <br>~~ee~~<br>|2.80/–0.62 <br>~~ee~~<br>|3.35/–0.62<br>~~ee~~<br>|N/A<br>~~ee~~<br>|3.35/–0.62 <br>~~ee~~<br>|2.14/–0.48<br>~~ee~~<br>|ns<br>~~ee~~<br>|
|||XC7A25T<br>~~RRee~~<br>~~po~~|2.37/–0.61 <br>~~ee~~<br>~~po~~|2.69/–0.61 <br>~~ee~~|3.21/–0.61<br>~~ee~~|N/A<br>~~ee~~|3.21/–0.61 <br>~~ee~~|2.00/–0.47<br>~~ee~~|ns<br>~~ee~~|
|||XC7A35T<br>~~po~~|2.46/–0.62 <br>~~po~~|2.80/–0.62|3.35/–0.62|N/A|3.35/–0.62|2.14/–0.48|ns|
|||XC7A50T<br>~~po~~<br>~~ee~~|2.46/–0.62 <br>~~po~~<br>~~ee~~|2.80/–0.62 <br>~~ee~~|3.35/–0.62<br>~~ee~~|N/A<br>~~ee~~|3.35/–0.62 <br>~~ee~~|2.14/–0.48<br>~~ee~~|ns<br>~~ee~~|
|||XC7A75T<br>~~ee~~<br>~~ee~~<br>~~po~~|2.47/–0.62 <br>~~ee~~<br>~~ee~~<br>~~po~~|2.81/–0.62 <br>~~ee~~<br>~~ee~~|3.36/–0.62<br>~~ee~~<br>~~ee~~|N/A<br>~~ee~~<br>~~ee~~|3.36/–0.62 <br>~~ee~~<br>~~ee~~|2.15/–0.48<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
|||XC7A100T<br>~~po~~|2.47/–0.62 <br>~~po~~|2.81/–0.62|3.36/–0.62|N/A|3.36/–0.62|2.15/–0.48|ns|
|||XC7A200T<br>~~po~~<br>~~ee~~|2.59/–0.63 <br>~~po~~<br>~~ee~~|2.95/–0.63 <br>~~ee~~|3.52/–0.63<br>~~ee~~|N/A<br>~~ee~~|3.52/–0.63 <br>~~ee~~|2.32/–0.51<br>~~ee~~|ns<br>~~ee~~|
|||XA7A12T<br>~~ee~~<br>~~ee~~<br>~~po~~|N/A<br>~~ee~~<br>~~ee~~<br>~~po~~|2.69/–0.61 <br>~~ee~~<br>~~ee~~|3.21/–0.61 <br>~~ee~~<br>~~ee~~|3.21/–0.61<br>~~ee~~<br>~~ee~~|N/A<br>~~ee~~<br>~~ee~~|N/A<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
|||XA7A15T<br>~~po~~|N/A<br>~~po~~|2.80/–0.62|3.35/–0.62|3.35/–0.62|N/A|N/A|ns|
|||XA7A25T<br>~~po~~<br>~~ee~~|N/A<br>~~po~~<br>~~ee~~|2.69/–0.61 <br>~~ee~~|3.21/–0.61 <br>~~ee~~|3.21/–0.61<br>~~ee~~|N/A<br>~~ee~~|N/A<br>~~ee~~|ns<br>~~ee~~|
|||XA7A35T<br>~~ee~~<br>~~ee~~<br>~~po~~|N/A<br>~~ee~~<br>~~ee~~<br>~~po~~|2.80/–0.62 <br>~~ee~~<br>~~ee~~|3.35/–0.62 <br>~~ee~~<br>~~ee~~|3.35/–0.62<br>~~ee~~<br>~~ee~~|N/A<br>~~ee~~<br>~~ee~~|N/A<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
|||XA7A50T<br>~~ee~~<br>~~po~~|N/A<br>~~ee~~<br>~~po~~|2.80/–0.62 <br>~~ee~~|3.35/–0.62 <br>~~ee~~|3.35/–0.62<br>~~ee~~|N/A<br>~~ee~~|N/A<br>~~ee~~|ns<br>~~ee~~|
|||XA7A75T<br>~~po~~<br>~~ee~~|N/A<br>~~po~~<br>~~ee~~|2.81/–0.62 <br>~~ee~~|3.36/–0.62 <br>~~ee~~|3.36/–0.62<br>~~ee~~|N/A<br>~~ee~~|N/A<br>~~ee~~|ns<br>~~ee~~|
|||XA7A100T<br>~~ee~~<br>~~ee~~<br>~~po~~|N/A<br>~~ee~~<br>~~ee~~<br>~~po~~|2.81/–0.62 <br>~~ee~~<br>~~ee~~|3.36/–0.62 <br>~~ee~~<br>~~ee~~|3.36/–0.62<br>~~ee~~<br>~~ee~~|N/A<br>~~ee~~<br>~~ee~~|N/A<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|
|||XQ7A50T<br>~~po~~|N/A<br>~~po~~|2.80/–0.62|3.35/–0.62|3.35/–0.62|3.35/–0.62|N/A|ns|
|||XQ7A100T<br>~~po~~<br>~~ee~~|N/A<br>~~po~~<br>~~ee~~|2.81/–0.62 <br>~~ee~~|3.36/–0.62 <br>~~ee~~|3.36/–0.62 <br>~~ee~~|3.36/–0.62<br>~~ee~~|N/A<br>~~ee~~|ns<br>~~ee~~|
|||XQ7A200T<br>~~ee~~<br>~~po~~|N/A<br>~~ee~~<br>~~po~~|2.95/–0.63 <br>~~ee~~<br>~~po~~|3.52/–0.63 <br>~~ee~~<br>~~po~~|3.52/–0.63 <br>~~ee~~<br>~~po~~|3.52/–0.63<br>~~ee~~<br>~~po~~|N/A<br>~~ee~~<br>~~po~~|ns<br>~~ee~~<br>~~po~~|
## **Notes:**
1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage.
2. IFF = Input flip-flop or latch
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
DS181 (v1.27.1) July 3, 2024 **Product Specification**
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46
**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 46:_ **Clock-Capable Clock Input Setup and Hold With PLL**
|**Symbol**|**Description**|**Device**<br>~~pe~~<br>~~a~~|**Speed Grade**<br>~~pe~~|**Speed Grade**<br>~~pe~~|**Speed Grade**<br>~~pe~~|**Speed Grade**<br>~~pe~~|**Speed Grade**<br>~~pe~~|**Speed Grade**<br>~~pe~~|**Units**|
|---|---|---|---|---|---|---|---|---|---|
||||**1.0V**<br>~~pe~~||||**0.95V**<br>~~pe~~|**0.9V**<br>~~pe~~||
||||**-3**<br>~~a ee~~|**-2/-2LE**<br>~~ee~~|**-1**<br>~~ee~~|**-1M/-1Q**<br>~~ee~~|**-1LI**<br>~~ee~~|**-2LE**<br>~~ee~~||
|Input Setup and Hold Time Relative to Clock-Capable Clock Input Signal for SSTL15 Standard.(1)<br>~~|~~||||||||||
|TPSPLLCC/<br>TPHPLLCC<br>~~|~~|No delay clock-capable<br>clock input and IFF(2)<br>with PLL<br>~~|~~|XC7A12T<br>~~|~~<br>~~se~~<br>~~esee~~|2.68/–0.19<br>~~|~~<br>~~se~~<br>~~ee~~|3.04/–0.19<br>~~|~~<br>~~se~~<br>~~ee~~|3.64/–0.19<br>~~|~~<br>~~se~~<br>~~ee~~|N/A<br>~~|~~<br>~~se~~<br>~~ee~~|3.64/–0.19<br>~~|~~<br>~~se~~<br>~~ee~~|2.32/–0.57<br>~~|~~<br>~~se~~<br>~~ee~~|ns<br>~~|~~<br>~~se~~<br>~~ee~~|
|||XC7A15T<br>~~se~~<br>~~esee~~|2.77/–0.20<br>~~se~~<br>~~ee~~|3.15/–0.20<br>~~se~~<br>~~ee~~|3.77/–0.20<br>~~se~~<br>~~ee~~|N/A<br>~~se~~<br>~~ee~~|3.77/–0.20<br>~~se~~<br>~~ee~~|2.46/–0.59<br>~~se~~<br>~~ee~~|ns<br>~~se~~<br>~~ee~~|
|||XC7A25T<br>~~esee~~<br>~~ss~~|2.68/–0.19<br>~~ee~~<br>~~ss~~|3.04/–0.19<br>~~ee~~<br>~~ss~~|3.64/–0.19<br>~~ee~~<br>~~ss~~|N/A<br>~~ee~~<br>~~ss~~|3.64/–0.19<br>~~ee~~<br>~~ss~~|2.32/–0.57<br>~~ee~~<br>~~ss~~|ns<br>~~ee~~<br>~~ss~~|
|||XC7A35T<br>~~ee~~<br>~~es~~|2.77/–0.20<br>~~ee~~<br>~~ee~~|3.15/–0.20<br>~~ee~~<br>~~ee~~|3.77/–0.20<br>~~ee~~|N/A<br>~~ee~~|3.77/–0.20<br>~~ee~~|2.46/–0.59<br>~~ee~~|ns<br>~~ee~~|
|||XC7A50T<br>~~ee~~<br>~~es~~|2.77/–0.20<br>~~ee~~<br>~~ee~~|3.15/–0.20<br>~~ee~~<br>~~ee~~|3.77/–0.20<br>~~ee~~|N/A<br>~~ee~~|3.77/–0.20<br>~~ee~~|2.46/–0.59<br>~~ee~~|ns<br>~~ee~~|
|||XC7A75T<br>~~es ~~<br>~~ss~~|2.78/–0.20<br> ~~ee~~<br>~~ss~~|3.15/–0.20<br>~~ee~~<br>~~ss~~|3.78/–0.20<br>~~ss~~|N/A<br>~~ss~~|3.78/–0.20<br>~~ss~~|2.47/–0.59<br>~~ss~~|ns<br>~~ss~~|
|||XC7A100T<br>~~ee~~<br>~~es~~|2.78/–0.20<br>~~ee~~<br>~~ee~~|3.15/–0.20<br>~~ee~~<br>~~ee~~|3.78/–0.20<br>~~ee~~|N/A<br>~~ee~~|3.78/–0.20<br>~~ee~~|2.47/–0.59<br>~~ee~~|ns<br>~~ee~~|
|||XC7A200T<br>~~ee~~<br>~~es~~|2.91/–0.21<br>~~ee~~<br>~~ee~~|3.29/–0.21<br>~~ee~~<br>~~ee~~|3.94/–0.21<br>~~ee~~|N/A<br>~~ee~~|3.94/–0.21<br>~~ee~~|2.64/–0.62<br>~~ee~~|ns<br>~~ee~~|
|||XA7A12T<br>~~es ~~<br>~~ss~~|N/A<br> ~~ee~~<br>~~ss~~|3.04/–0.19<br>~~ee~~<br>~~ss~~|3.64/–0.19<br>~~ss~~|3.64/–0.19<br>~~ss~~|N/A<br>~~ss~~|N/A<br>~~ss~~|ns<br>~~ss~~|
|||XA7A15T<br>~~ee~~<br>~~es~~|N/A<br>~~ee~~<br>~~ee~~|3.15/–0.20<br>~~ee~~<br>~~ee~~|3.77/–0.20<br>~~ee~~|3.77/–0.20<br>~~ee~~|N/A<br>~~ee~~|N/A<br>~~ee~~|ns<br>~~ee~~|
|||XA7A25T<br>~~ee~~<br>~~es~~|N/A<br>~~ee~~<br>~~ee~~|3.04/–0.19<br>~~ee~~<br>~~ee~~|3.64/–0.19<br>~~ee~~|3.64/–0.19<br>~~ee~~|N/A<br>~~ee~~|N/A<br>~~ee~~|ns<br>~~ee~~|
|||XA7A35T<br>~~es ~~<br>~~ss~~|N/A<br> ~~ee~~<br>~~ss~~|3.15/–0.20<br>~~ee~~<br>~~ss~~|3.77/–0.20<br>~~ss~~|3.77/–0.20<br>~~ss~~|N/A<br>~~ss~~|N/A<br>~~ss~~|ns<br>~~ss~~|
|||XA7A50T<br>~~ss~~<br>~~ee~~<br>~~es~~|N/A<br>~~ss~~<br>~~ee~~<br>~~ee~~|3.15/–0.20<br>~~ss~~<br>~~ee~~<br>~~ee~~|3.77/–0.20<br>~~ss~~<br>~~ee~~|3.77/–0.20<br>~~ss~~<br>~~ee~~|N/A<br>~~ss~~<br>~~ee~~|N/A<br>~~ss~~<br>~~ee~~|ns<br>~~ss~~<br>~~ee~~|
|||XA7A75T<br>~~ee~~<br>~~es~~|N/A<br>~~ee~~<br>~~ee~~|3.15/–0.20<br>~~ee~~<br>~~ee~~|3.78/–0.20<br>~~ee~~|3.78/–0.20<br>~~ee~~|N/A<br>~~ee~~|N/A<br>~~ee~~|ns<br>~~ee~~|
|||XA7A100T<br>~~es ~~<br>~~ss~~|N/A<br> ~~ee~~<br>~~ss~~|3.15/–0.20<br>~~ee~~<br>~~ss~~|3.78/–0.20<br>~~ss~~|3.78/–0.20<br>~~ss~~|N/A<br>~~ss~~|N/A<br>~~ss~~|ns<br>~~ss~~|
|||XQ7A50T<br>~~ee~~<br>~~es~~|N/A<br>~~ee~~<br>~~ee~~|3.15/–0.20<br>~~ee~~<br>~~ee~~|3.77/–0.20<br>~~ee~~|3.77/–0.20<br>~~ee~~|3.77/–0.20<br>~~ee~~|N/A<br>~~ee~~|ns<br>~~ee~~|
|||XQ7A100T<br>~~ee~~<br>~~es~~|N/A<br>~~ee~~<br>~~ee~~|3.15/–0.20<br>~~ee~~<br>~~ee~~|3.78/–0.20<br>~~ee~~|3.78/–0.20<br>~~ee~~|3.78/–0.20<br>~~ee~~|N/A<br>~~ee~~|ns<br>~~ee~~|
|||XQ7A200T<br>~~es ~~<br>~~ss~~|N/A<br> ~~ee~~<br>~~ss~~|3.29/–0.21<br>~~ee~~<br>~~ss~~|3.94/–0.21<br>~~ss~~|3.94/–0.21<br>~~ss~~|3.94/–0.21<br>~~ss~~|N/A<br>~~ss~~|ns<br>~~ss~~|
## **Notes:**
1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage.
2. IFF = Input flip-flop or latch
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
_Table 47:_ **Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO**
|**Symbol**|**Description**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|---|---|
|||**1.0V**||||**0.95V**|**0.9V**||
|||**-3**|**-2/-2LE**|**-1**|**-1M/-1Q**|**-1LI**|**-2LE**||
|Input Setup and Hold Time Relative to a Forwarded Clock Input Pin Using BUFIO for SSTL15 Standard.|||||||||
|TPSCS/TPHCS|Setup and hold of I/O clock|–0.38/1.31|–0.38/1.46|–0.38/1.76|–0.38/1.76|–0.38/1.76|–0.16/1.89|ns|
_Table 48:_ **Sample Window**
|**Symbol**|**Description**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|---|---|
|||**1.0V**||||**0.95V**|**0.9V**||
|||**-3**|**-2/-2LE**|**-1**|**-1M/-1Q**|**-1LI**|**-2LE**||
|TSAMP|Sampling error at receiver pins(1)|0.59|0.64|0.70|0.70|0.70|0.70|ns|
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DS181 (v1.27.1) July 3, 2024 **Product Specification**
47
**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 48:_ **Sample Window** _**(Cont’d)**_
|**Symbol**|**Description**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|---|---|
|||**1.0V**||||**0.95V**|**0.9V**||
|||**-3**|**-2/-2LE**|**-1**|**-1M/-1Q**|**-1LI**|**-2LE**||
|TSAMP_BUFIO|Sampling error at receiver pins using<br>BUFIO(2)|0.35|0.40|0.46|0.46|0.46|0.46|ns|
## **Notes:**
1. This parameter indicates the total sampling error of the Artix 7 FPGAs DDR input registers, measured across voltage, temperature, and process. The characterization methodology uses the MMCM to capture the DDR input registers’ edges of operation. These measurements include:
- CLK0 MMCM jitter
- MMCM accuracy (phase offset)
- MMCM phase shift resolution
- These measurements do not include package or clock tree skew.
2. This parameter indicates the total sampling error of the Artix 7 FPGAs DDR input registers, measured across voltage, temperature, and process. The characterization methodology uses the BUFIO clock network and IDELAY to capture the DDR input registers’ edges of operation. These measurements do not include package or clock tree skew.
## **Additional Package Parameter Guidelines**
The parameters in this section provide the necessary values for calculating timing budgets for Artix 7 FPGA clock transmitter and receiver data-valid windows.
_Table 49:_ **Package Skew**
|**Symbol**<br>~~GG~~|**Description**<br>~~GG~~|**Device**<br>~~GG~~|**Package**<br>~~GG~~|**Value**<br>~~GG~~|**Units**<br>~~GG~~|
|---|---|---|---|---|---|
|TPKGSKEW|Package skew(1)|XC7A12T|CPG238|55|ps|
||||CSG325|76|ps<br>~~—~~|
|||XC7A15T<br>~~a~~|CPG236<br>~~es~~|48<br>~~es~~|ps<br>~~—~~<br>~~es~~|
||||CSG324<br>~~es~~|104<br>~~es~~|ps<br>~~es~~|
||||CSG325<br>~~es~~<br>~~es~~|142<br>~~es~~<br>~~es~~|ps<br>~~es~~<br>~~es~~|
||||FTG256<br>~~es~~<br>~~es~~|98<br>~~es~~<br>~~es~~|ps<br>~~es~~<br>~~es~~|
||||FGG484<br>~~es~~<br>~~es~~<br>~~eee~~|97<br>~~es~~<br>~~es~~<br>~~eee~~|ps<br>~~es~~<br>~~es~~<br>~~eee~~|
|||XC7A25T<br>~~a~~|CPG238<br>~~es~~<br>~~eee~~|55<br>~~es~~<br>~~eee~~|ps<br>~~es~~<br>~~eee~~|
||||CSG325<br>~~eee~~|76<br>~~eee~~|ps<br>~~eee~~|
|||XC7A35T<br>~~a~~|CPG236<br>~~eee~~<br>~~es~~|48<br>~~eee~~<br>~~es~~<br>~~ee~~|ps<br>~~eee~~<br>~~es~~|
||||CSG324<br>~~ee~~|104<br>~~ee~~<br>~~ee~~|ps<br>~~ee~~|
||||CSG325<br>~~ee~~<br>~~ee~~|142<br>~~ee~~<br>~~ee~~<br>~~ee~~|ps<br>~~ee~~<br>~~ee~~|
||||FTG256<br>~~ee~~<br>~~es~~|98<br>~~ee~~<br>~~es~~|ps<br>~~ee~~<br>~~es~~|
||||FGG484<br>~~es~~<br>~~es~~|97<br>~~es~~<br>~~es~~|ps<br>~~es~~<br>~~es~~|
|||XC7A50T|CPG236<br>~~es~~<br>~~es~~|48<br>~~es~~<br>~~es~~|ps<br>~~es~~<br>~~es~~|
||||CSG324<br>~~es~~|104<br>~~es~~|ps<br>~~es~~|
||||CSG325<br>~~es~~<br>~~es~~|142<br>~~es~~<br>~~es~~|ps<br>~~es~~<br>~~es~~|
||||FTG256<br>~~es~~<br>~~es~~|98<br>~~es~~<br>~~es~~|ps<br>~~es~~<br>~~es~~|
||||FGG484<br>~~es~~<br>~~es~~|97<br>~~es~~<br>~~es~~|ps<br>~~es~~<br>~~es~~|
|||XC7A75T|CSG324<br>~~es~~<br>~~es~~|113<br>~~es~~<br>~~es~~|ps<br>~~es~~<br>~~es~~|
||||FTG256<br>~~es~~<br>~~es~~|120<br>~~es~~<br>~~es~~|ps<br>~~es~~<br>~~es~~|
||||FGG484<br>~~es~~<br>~~es~~|144<br>~~es~~<br>~~es~~|ps<br>~~es~~<br>~~es~~|
||||FGG676<br>~~es~~|153<br>~~es~~|ps<br>~~es~~|
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DS181 (v1.27.1) July 3, 2024 **Product Specification**
48
**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 49:_ **Package Skew** _**(Cont’d)**_
|**Symbol**<br>~~GG~~|**Description**<br>~~GG~~|**Device**<br>~~GG~~|**Package**<br>~~GG~~|**Value**<br>~~GG~~|**Units**<br>~~GG~~|
|---|---|---|---|---|---|
|TPKGSKEW|Package skew(1)|XC7A100T|CSG324<br>~~ee~~|113<br>~~ee~~|ps<br>~~ee~~|
||||FTG256<br>~~ee~~<br>~~ee~~|120<br>~~ee~~<br>~~ee~~|ps<br>~~ee~~<br>~~ee~~|
||||FGG484<br>~~ee~~<br>~~es~~|144<br>~~ee~~<br>~~es~~|ps<br>~~ee~~<br>~~es~~|
||||FGG676<br>~~es~~<br>~~es~~|153<br>~~es~~<br>~~es~~|ps<br>~~es~~<br>~~es~~|
|||XC7A200T<br>~~—_————————E~~|SBG484<br>~~es~~<br>~~es~~|111<br>~~es~~<br>~~es~~|ps<br>~~es~~<br>~~es~~|
||||FBG484<br>~~es~~|109<br>~~es~~|ps<br>~~es~~|
||||FBG676<br>~~es~~<br>~~es~~|121<br>~~es~~<br>~~es~~<br>~~ee~~|ps<br>~~es~~<br>~~es~~|
||||FFG1156<br>~~ee~~<br>~~—_————————E~~|151<br>~~ee~~<br>~~ee~~<br>~~—_————————E~~|ps<br>~~ee~~<br>~~—_————————E~~|
|||XA7A12T<br>~~—_————————E~~|CSG325<br>~~ee~~<br>~~—_————————E~~|76<br>~~ee~~<br>~~ee~~<br>~~—_————————E~~|ps<br>~~ee~~<br>~~—_————————E~~|
||||CPG238<br>~~—_————————E~~<br>~~es~~|55<br>~~—_————————E~~<br>~~es~~|ps<br>~~—_————————E~~<br>~~es~~|
|||XA7A15T<br>~~—_————————E~~<br>~~a~~|CPG236<br>~~—_————————E~~<br>~~es~~<br>~~es~~|48<br>~~—_————————E~~<br>~~es~~<br>~~es~~|ps<br>~~—_————————E~~<br>~~es~~<br>~~es~~|
||||CSG324<br>~~es~~<br>~~es~~|104<br>~~es~~<br>~~es~~|ps<br>~~es~~<br>~~es~~|
||||CSG325<br>~~es~~<br>~~es~~|142<br>~~es~~<br>~~ee~~|ps<br>~~es~~<br>~~ee~~|
|||XA7A25T<br>~~a~~|CSG325<br>~~es~~<br>~~es~~|76<br>~~es~~<br>~~ee~~|ps<br>~~es~~<br>~~ee~~|
||||CPG238<br>~~es~~<br>~~es~~|55<br>~~ee~~<br>~~es~~|ps<br>~~ee~~<br>~~es~~|
|||XA7A35T<br>~~a~~|CPG236<br>~~es ~~<br>~~es~~<br>~~es~~|48<br> ~~ee ~~<br>~~es~~<br>~~es~~|ps<br> ~~ee~~<br>~~es~~<br>~~es~~|
||||CSG324<br>~~es~~<br>~~es~~|104<br>~~es~~<br>~~es~~|ps<br>~~es~~<br>~~es~~|
||||CSG325<br>~~es~~|142<br>~~es~~|ps<br>~~es~~|
|||XA7A50T|CPG236<br>~~es~~<br>~~es~~|48<br>~~es~~<br>~~es~~<br>~~ee~~|ps<br>~~es~~<br>~~es~~|
||||CSG324<br>~~ee~~|104<br>~~ee~~<br>~~ee~~|ps<br>~~ee~~|
||||CSG325<br>~~ee~~<br>~~es~~|142<br>~~ee~~<br>~~ee~~<br>~~es~~|ps<br>~~ee~~<br>~~es~~|
|||XA7A75T<br>~~a~~|CSG324<br>~~es~~<br>~~es~~|113<br>~~es~~<br>~~es~~|ps<br>~~es~~<br>~~es~~|
||||FGG484<br>~~es~~|144<br>~~es~~|ps<br>~~es~~|
|||XA7A100T<br>~~a~~<br>~~ee~~<br>~~—————EE~~|CSG324<br>~~es~~<br>~~ee~~|113<br>~~es~~<br>~~ee~~|ps<br>~~es~~<br>~~ee~~|
||||FGG484<br>~~ee~~<br>~~es~~<br>~~————EE~~|144<br>~~ee~~<br>~~es~~<br>~~————EE~~|ps<br>~~ee~~<br>~~es~~<br>~~————EE~~|
|||XQ7A50T<br>~~ee~~<br>~~—————EE~~|CS325<br>~~ee~~<br>~~es~~<br>~~————EE~~|142<br>~~ee~~<br>~~es~~<br>~~————EE~~|ps<br>~~ee~~<br>~~es~~<br>~~————EE~~|
||||FG484<br>~~————EE~~<br>~~es~~|97<br>~~————EE~~<br>~~es~~|ps<br>~~————EE~~<br>~~es~~|
|||XQ7A100T<br>~~—————EE~~<br>~~a~~|CS324<br>~~————EE~~<br>~~es~~<br>~~a~~|113<br>~~————EE~~<br>~~es~~<br>~~a~~|ps<br>~~————EE~~<br>~~es~~<br>~~a~~|
||||FG484<br>~~a~~<br>~~ee~~<br>~~es~~|144<br>~~a~~<br>~~ee~~<br>~~ee~~|ps<br>~~a~~<br>~~ee~~<br>~~ee~~|
|||XQ7A200T<br>~~a~~|RS484<br>~~a~~<br>~~ee~~<br>~~es~~|111<br>~~a~~<br>~~ee~~<br>~~ee~~|ps<br>~~a~~<br>~~ee~~<br>~~ee~~|
||||RB484<br>~~es~~<br>~~es~~|109<br>~~ee~~<br>~~es~~|ps<br>~~ee~~<br>~~es~~|
||||RB676<br>~~es~~|121<br>~~es~~|ps<br>~~es~~|
## **Notes:**
1. These values represent the worst-case skew between any two SelectIO resources in the package: shortest delay to longest delay from die pad to ball.
2. Package delay information is available for these device/package combinations. This information can be used to deskew the package.
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**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
## **GTP Transceiver Specifications**
## **GTP Transceiver DC Input and Output Levels**
Table 50 summarizes the DC output specifications of the GTP transceivers in Artix 7 FPGAs. Consult _7 Series FPGAs GTP Transceiver User Guide_ (UG482) for further details.
_Table 50:_ **GTP Transceiver DC Specifications**
|**Symbol**<br>~~a~~|**DC Parameter**<br>~~a~~|**Conditions**<br>~~a~~|**Min**<br>~~a~~|**Typ**<br>~~a~~|**Max**<br>~~a~~|**Units**<br>~~a~~|
|---|---|---|---|---|---|---|
|DVPPOUT<br>~~a~~<br>~~SS~~|Differential peak-to-peak output<br>voltage(1)<br>~~a~~<br>~~SS~~|Transmitter output swing is set to<br>maximum setting<br>~~a~~|1000<br>~~a~~|–<br>~~a~~|–<br>~~a~~|mV<br>~~a~~|
|VCMOUTDC<br>~~SS~~|DC common mode output<br>voltage<br>~~SS~~|Equation based|VMGTAVTT– DVPPOUT/4|||mV|
|ROUT<br>~~SS~~|Differential output resistance<br>~~SS~~||–|100|–||
|VCMOUTAC<br>~~SS~~|Common mode output voltage: AC coupled<br>~~SS~~||1/2 VMGTAVTT|||mV|
|TOSKEW<br>~~SS~~|Transmitter output pair (TXP and TXN) intra-pair skew<br>(FF, FB, SB packages)||–|–|10|ps|
||Transmitter output pair (TXP and TXN) intra-pair skew<br>(FG, FT, CS, CP packages)<br>~~SS~~<br>~~ee~~||–<br>~~ee~~|–<br>~~ee~~|12<br>~~ee~~|ps|
|DVPPIN<br>~~SS~~|Differential peak-to-peak input<br>voltage<br>~~SS~~|External AC coupled<br>~~ee~~|150<br>~~ee~~|–<br>~~ee~~|2000<br>~~ee~~|mV|
|VIN<br>~~SS~~|Single-ended input voltage(2)<br>~~SS~~|DC coupled VMGTAVTT= 1.2V<br>~~ee~~|–200<br>~~ee~~|–<br>~~ee~~|VMGTAVTT<br>~~ee~~|mV|
|VCMIN<br>~~SS~~|Common mode input voltage<br>~~SS~~|DC coupled VMGTAVTT= 1.2V<br>~~ee~~|–<br>~~ee ~~|2/3 VMGTAVTT<br> ~~ee~~|–<br>~~ee~~|mV|
|RIN|Differential input resistance||–|100|–||
|CEXT|Recommended external AC coupling capacitor(3)||–|100|–|nF|
## **Notes:**
1. The output swing and preemphasis levels are programmable using the attributes discussed in _7 Series FPGAs GTP Transceiver User Guide_ (UG482) and can result in values lower than reported in this table.
2. Voltage measured at the pin referenced to ground.
3. Other values can be used as appropriate to conform to specific protocols and standards.
**==> picture [529 x 212] intentionally omitted <==**
**----- Start of picture text -----**<br>
+V P<br>Single-Ended<br>Peak-to-Peak<br>N Voltage<br>_X_X_X<br>0 _ XX _X ds181_01_062014<br>Figure 3: Single-Ended Peak-to-Peak Voltage<br>+V<br>Differential<br>0 Peak-to-Peak<br>Voltage<br>|<br>–V | P–N .<br>ds181_02_062014<br>**----- End of picture text -----**<br>
_Figure 4:_ **Differential Peak-to-Peak Voltage**
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**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
## _**Note:**_ In Figure 4, differential peak-to-peak voltage = single-ended peak-to-peak voltage x 2.
Table 51 summarizes the DC specifications of the clock input of the GTP transceiver. Consult _7 Series FPGAs GTP Transceiver User Guide_ (UG482) for further details.
|**Symbol**<br>~~——~~|**DC Parameter**<br>~~—————~~|**Min**<br>~~===~~|**Typ**<br>~~===~~|**Max**<br>~~===~~|**Units**<br>~~===~~|
|---|---|---|---|---|---|
|VIDIFF<br>~~——~~|Differential peak-to-peak input voltage<br>~~—————~~|350<br>~~===~~|–<br>~~===~~|2000<br>~~===~~|mV<br>~~===~~|
|RIN<br>~~——~~|Differential input resistance<br>~~—————~~|–<br>~~===~~|100<br>~~===~~|–<br>~~===~~|<br>~~===~~|
|CEXT<br>~~——~~|Required external AC coupling capacitor<br>~~—————~~|–<br>~~===~~|100<br>~~===~~|–<br>~~===~~|nF<br>~~===~~|
## **GTP Transceiver Switching Characteristics**
Consult _7 Series FPGAs GTP Transceiver User Guide_ (UG482) for further information.
_Table 52:_ **GTP Transceiver Performance**
|**Symbol**|**Description**|**Output**<br>**Divider**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|
||||**-3 (1.0V)**||**-2 (1.0V)**<br>**-2LE (1.0V)**||**-1 (1.0V)**<br>**-1LI (0.95V)**<br>**-1Q (1.0V)**<br>**-1M (1.0V)**||**-2LE (0.9V)**|||
||||**Package Type**|||||||||
||||**FF**<br>**FB**<br>**SB**|**FG**<br>**FT**<br>**CS**<br>**CP**|**FF**<br>**FB**<br>**SB**<br>**RB**<br>**RS**|**FG**<br>**FT**<br>**CS**<br>**CP**|**FF**<br>**FB**<br>**SB**<br>**RB**<br>**RS**|**FG**<br>**FT**<br>**CS**<br>**CP**|**FF**<br>**FB**<br>**SB**|**FG**<br>**FT**<br>**CS**<br>**CP**||
|FGTPMAX|Maximum GTP transceiver data rate||6.6|6.25|6.6|6.25|3.75|3.75|3.75|3.75|Gb/s|
|FGTPMIN|Minimum GTP transceiver data rate||0.500|0.500|0.500|0.500|0.500|0.500|0.500|0.500|Gb/s|
|FGTPRANGE|PLL line rate range|1|3.2–6.6||3.2–6.6||3.2–3.75||3.2–3.75||Gb/s|
|||2|1.6–3.3||1.6–3.3||1.6–3.2||1.6–3.2||Gb/s|
|||4|0.8–1.65||0.8–1.65||0.8–1.6||0.8–1.6||Gb/s|
|||8|0.5–0.825||0.5–0.825||0.5–0.8||0.5–0.8||Gb/s|
|FGTPPLLRANGE|GTP transceiver PLL frequency<br>range||1.6–3.3||1.6–3.3||1.6–3.3<br>~~-—s~~||1.6–3.3<br>~~-—s~~||GHz<br>~~-—s~~|
|_Table 53:_ **GTP Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics**<br>**Symbol**<br>**Description**<br>**Speed Grade**<br>**Units**<br>**1.0V**<br>**0.95V**<br>**0.9V**<br>**-3**<br>**-2/-2LE**<br>**-1**<br>**-1LI**<br>**-2LE**<br>FGTPDRPCLK<br>GTPDRPCLK maximum frequency<br>175<br>175<br>156<br>156<br>125<br>MHz<br>_Table 54:_ **GTP Transceiver Reference Clock Switching Characteristics**<br>~~a~~<br>~~-—s~~|
|---|
|**Symbol**<br>**Description**<br>**Conditions**<br>**All Speed Grades**<br>**Units**<br>**Min**<br>**Typ**<br>**Max**<br>FGCLK<br>Reference clock frequency range<br>60<br>–<br>660<br>MHz<br>TRCLK<br>Reference clock rise time<br>20% – 80%<br>–<br>200<br>–<br>ps<br>TFCLK<br>Reference clock fall time<br>80% – 20%<br>–<br>200<br>–<br>ps<br>TDCREF<br>Reference clock duty cycle<br>Transceiver PLL only<br>40<br>–<br>60<br>%<br>~~ee~~|
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**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
|ds181_03_062811<br>80%<br>20%<br>TFCLK<br>TRCLK<br>~~|~~<br>—<br>\<br>A<br>ee<br>~~|~~|<br>|<br>|<br>|<br>~~Qf~~<br>~—--4--\------f----<br>-<br>\----<br>—~~!~~|||
|---|---|---|
|_Figure 5:_ **Reference Clock Timing Parameters**|||
|_Table 55:_ **GTP Transceiver PLL/Lock Time Adaptation**|||
|**Symbol**<br>**Description**<br>**Conditions**<br>**All Speed Grades**<br>**Min**<br>**Typ**<br>**Max**||**Units**|
|TLOCK<br>Initial PLL lock<br>–<br>–<br>1||ms|
|After the PLL is locked to the|||
|TDLOCK<br>Clock recovery phase acquisition and<br>adaptation time.<br>reference clock, this is the time it<br>takes to lock the clock data<br>recovery (CDR) to the data<br>–<br>50,000<br>2.3 x106||UI|
|present at the input.|||
|_Table 56:_ **GTP Transceiver User Clock Switching Characteristics(1)**|||
|**Symbol**<br>**Description**<br>**Conditions**<br>**Speed Grade**<br>**Units**<br>**1.0V**<br>**0.95V**<br>**0.9V**<br>**-3**<br>**-2/-2LE**<br>**-1**<br>**-1LI**<br>**-2LE**<br>FTXOUT<br>TXOUTCLK maximum frequency<br>412.500<br>412.500<br>234.375<br>234.375<br>234.375<br>MHz<br>FRXOUT<br>RXOUTCLK maximum frequency<br>412.500<br>412.500<br>234.375<br>234.375<br>234.375<br>MHz<br>FTXIN<br>TXUSRCLK maximum frequency<br>16-bit data path<br>412.500<br>412.500<br>234.375<br>234.375<br>234.375<br>MHz<br>FRXIN<br>RXUSRCLK maximum frequency<br>16-bit data path<br>412.500<br>412.500<br>234.375<br>234.375<br>234.375<br>MHz<br>FTXIN2<br>TXUSRCLK2 maximum frequency<br>16-bit data path<br>412.500<br>412.500<br>234.375<br>234.375<br>234.375<br>MHz<br>FRXIN2<br>RXUSRCLK2 maximum frequency<br>16-bit data path<br>412.500<br>412.500<br>234.375<br>234.375<br>234.375<br>MHz<br>~~Po~~<br>~~PtPp~~<br>~~a~~<br>~~aes~~<br>~~e~~~~**s**~~<br>~~a DGs~~<br>~~a~~<br>~~eses rs~~<br>~~PRss~~<br>~~eo~~|||
## **Notes:**
1. Clocking must be implemented as described in _7 Series FPGAs GTP Transceiver User Guide_ (UG482).
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**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
AMD7Z1 **Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics** _Table 57:_ **GTP Transceiver Transmitter Switching Characteristics** ~~a~~ **Symbol Description Condition Min Typ Max Units**
_Table 57:_ **GTP Transceiver Transmitter Switching Characteristics**
|**Symbol**<br>~~a~~|**Description**<br>~~a~~|**Condition**<br>~~a~~|**Min**<br>~~a~~|**Typ**<br>~~a~~|**Max**<br>~~a~~|**Units**<br>~~a~~|
|---|---|---|---|---|---|---|
|FGTPTX<br>~~a~~|Serial data rate range<br>~~a~~||0.500<br>~~a~~|–<br>~~a~~|FGTPMAX<br>~~a~~|Gb/s<br>~~a~~|
|TRTX<br>~~a~~<br>~~Ge~~|TX rise time<br>~~a~~<br>~~Ge~~|20%–80%<br>~~a~~<br>~~GG~~|–<br>~~a~~<br>~~GG~~|50<br>~~a~~<br>~~GG~~|–<br>~~a~~<br>~~GG~~|ps<br>~~a~~|
|TFTX<br>~~eG~~|TX fall time<br>~~eG~~|80%–20%<br>~~eG~~|–<br>~~eG~~|50<br>~~eG~~|–<br>~~eG~~|ps<br>~~eG~~|
|TLLSKEW<br>~~eG~~<br>~~Ge~~|TX lane-to-lane skew(1)<br>~~eG~~<br>~~Ge~~||–<br>~~eG~~<br>~~Ge~~|–<br>~~eG~~<br>~~Ge~~|500<br>~~eG~~<br>~~Ge~~|ps<br>~~eG~~<br>~~Ge~~|
|VTXOOBVDPP<br>~~GC~~|Electrical idle amplitude<br>~~GC~~||–<br>~~GC~~|–<br>~~GC~~|20<br>~~GC~~|mV<br>~~GC~~|
|TTXOOBTRANSITION<br>~~GC~~<br>~~GG~~<br>~~ee ee~~|Electrical idle transition time<br>~~GC~~<br>~~GG~~<br>~~ee~~<br>~~er~~||–<br>~~GC~~<br>~~GG~~<br>~~er~~|–<br>~~GC~~<br>~~GG~~|140<br>~~GC~~<br>~~GG~~<br>~~ee~~|ns<br>~~GC~~<br>~~GG~~<br>~~ee~~|
|TJ6.6<br>~~GG~~<br>~~ee ee~~<br>~~ee~~|Total Jitter(2)(3)<br>~~GG~~<br>~~ee~~|6.6 Gb/s<br>~~GG~~<br>~~er~~|–<br>~~GG~~<br>~~er~~<br>~~ee~~|–<br>~~GG~~<br>~~ee~~|0.30<br>~~GG~~<br>~~ee~~<br>~~ee~~|UI<br>~~GG~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|DJ6.6<br>~~ee ee~~<br>~~ee~~|Deterministic Jitter(2)(3)<br>~~ee~~||–<br>~~er~~<br>~~ee~~|–<br>~~ee~~|0.15<br>~~ee~~<br>~~ee~~|UI<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|TJ5.0<br>~~ee ee~~<br>~~ee~~<br>~~or~~<br>~~ee~~|Total Jitter(2)(3)<br>~~ee~~<br>~~or~~|5.0 Gb/s<br>~~er~~<br>~~or~~|–<br>~~er~~<br>~~ee~~<br>~~or~~<br>~~ee~~|–<br>~~ee~~<br>~~or~~<br>~~ee~~|0.30<br>~~ee~~<br>~~ee~~<br>~~or~~<br>~~ee~~|UI<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~or~~<br>~~ee~~<br>~~ee~~|
|DJ5.0<br>~~or~~<br>~~ee~~|Deterministic Jitter(2)(3)<br>~~or~~||–<br>~~or~~<br>~~ee~~|–<br>~~or~~<br>~~ee~~|0.15<br>~~or~~<br>~~ee~~|UI<br>~~or~~<br>~~ee~~<br>~~ee~~|
|TJ4.25<br>~~or~~<br>~~ee~~<br>~~or~~<br>~~ee~~<br>~~**ee**~~|Total Jitter(2)(3)<br>~~or~~<br>~~or~~<br>|4.25 Gb/s<br>~~or~~<br>~~or~~<br>~~er~~|–<br>~~or~~<br>~~ee~~<br>~~or~~<br>~~ee~~|–<br>~~or~~<br>~~ee~~<br>~~or~~<br>~~ee~~|0.30<br>~~or~~<br>~~ee~~<br>~~or~~<br>~~ee~~|UI<br>~~or~~<br>~~ee~~<br>~~ee~~<br>~~or~~<br>~~eeee~~|
|DJ4.25<br>~~or~~<br>~~ee~~<br>~~**ee** ee~~|Deterministic Jitter(2)(3)<br>~~or~~<br>~~ee~~||–<br>~~or~~<br>~~ee~~<br>~~r~~|–<br>~~or~~<br>~~ee~~|0.15<br>~~or~~<br>~~ee~~<br>~~ee~~|UI<br>~~or~~<br>~~eeee~~<br>~~ee~~|
|TJ3.75<br>~~or~~<br>~~ee~~<br>~~**ee** ee~~|Total Jitter(2)(3)<br>~~or~~<br>~~ee~~|3.75 Gb/s<br>~~or~~<br>~~er~~|–<br>~~or~~<br>~~ee~~<br>~~r~~|–<br>~~or~~<br>~~ee~~|0.30<br>~~or~~<br>~~ee~~<br>~~ee~~|UI<br>~~or~~<br>~~eeee~~<br>~~ee~~<br>~~ee~~|
|DJ3.75<br>~~**ee** ee~~|Deterministic Jitter(2)(3)<br>~~ee~~||–<br><br>~~r~~<br>~~ee~~|–<br><br>~~ee~~|0.15<br><br>~~ee~~<br>~~ee~~|UI<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|TJ3.2<br>~~**ee** ee~~<br>~~or~~<br>~~ee~~|Total Jitter(2)(3)<br>~~ee~~<br>~~or~~|3.20 Gb/s(4)<br>~~er~~<br>~~or~~|–<br><br>~~r~~<br>~~ee~~<br>~~or~~<br>~~ee~~|–<br><br>~~ee~~<br>~~or~~<br>~~ee~~|0.2<br><br>~~ee~~<br>~~ee~~<br>~~or~~<br>~~ee~~|UI<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~or~~<br>~~ee~~<br>~~ee~~|
|DJ3.2<br>~~or~~<br>~~ee~~|Deterministic Jitter(2)(3)<br>~~or~~||–<br>~~or~~<br>~~ee~~|–<br>~~or~~<br>~~ee~~|0.1<br>~~or~~<br>~~ee~~|UI<br>~~or~~<br>~~ee~~<br>~~ee~~|
|TJ3.2L<br>~~or~~<br>~~ee~~<br>~~or~~<br>~~ee~~<br>~~**ee**~~|Total Jitter(2)(3)<br>~~or~~<br>~~or~~<br>|3.20 Gb/s(5)<br>~~or~~<br>~~or~~<br>~~er~~|–<br>~~or~~<br>~~ee~~<br>~~or~~<br>~~ee~~|–<br>~~or~~<br>~~ee~~<br>~~or~~<br>~~ee~~|0.32<br>~~or~~<br>~~ee~~<br>~~or~~<br>~~ee~~|UI<br>~~or~~<br>~~ee~~<br>~~ee~~<br>~~or~~<br>~~eeee~~|
|DJ3.2L<br>~~or~~<br>~~ee~~<br>~~**ee** ee~~|Deterministic Jitter(2)(3)<br>~~or~~<br>~~ee~~||–<br>~~or~~<br>~~ee~~<br>~~r~~|–<br>~~or~~<br>~~ee~~|0.16<br>~~or~~<br>~~ee~~<br>~~ee~~|UI<br>~~or~~<br>~~eeee~~<br>~~ee~~|
|TJ2.5<br>~~or~~<br>~~ee~~<br>~~**ee** ee~~|Total Jitter(2)(3)<br>~~or~~<br>~~ee~~|2.5 Gb/s(6)<br>~~or~~<br>~~er~~|–<br>~~or~~<br>~~ee~~<br>~~r~~|–<br>~~or~~<br>~~ee~~|0.20<br>~~or~~<br>~~ee~~<br>~~ee~~|UI<br>~~or~~<br>~~eeee~~<br>~~ee~~<br>~~ee~~|
|DJ2.5<br>~~**ee** ee~~|Deterministic Jitter(2)(3)<br>~~ee~~||–<br><br>~~r~~<br>~~ee~~|–<br><br>~~ee~~|0.08<br><br>~~ee~~<br>~~ee~~|UI<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|TJ1.25<br>~~**ee** ee~~<br>~~or~~<br>~~ee~~|Total Jitter(2)(3)<br>~~ee~~<br>~~or~~|1.25 Gb/s(7)<br>~~er~~<br>~~or~~<br>~~A~~|–<br><br>~~r~~<br>~~ee~~<br>~~or~~<br>~~ee~~|–<br><br>~~ee~~<br>~~or~~<br>~~ee~~|0.15<br><br>~~ee~~<br>~~ee~~<br>~~or~~<br>~~ee~~|UI<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~or~~<br>~~ee~~<br>~~ee~~|
|DJ1.25<br>~~or~~<br>~~ee~~<br>~~ee~~|Deterministic Jitter(2)(3)<br>~~or~~||–<br>~~or~~<br>~~ee~~<br>~~ee~~|–<br>~~or~~<br>~~ee~~<br>~~ee~~|0.06<br>~~or~~<br>~~ee~~<br>~~ee~~|UI<br>~~or~~<br>~~ee~~<br>~~ee~~|
|TJ500<br>~~or~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|Total Jitter(2)(3)<br>~~or~~<br>~~ee~~|500 Mb/s<br>~~or~~<br>~~ee~~<br>~~A~~|–<br>~~or~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|–<br>~~or~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.1<br>~~or~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|UI<br>~~or~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|DJ500<br>~~ee~~<br>~~ee~~|Deterministic Jitter(2)(3)<br>~~ee~~||–<br>~~ee~~<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.03<br>~~ee~~<br>~~ee~~<br>~~ee~~|UI<br>~~ee~~<br>~~ee~~|
2. Using PLL[0/1]_FBDIV = 2, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations. 3. All jitter values are based on a bit-error ratio of 1e[-12] .
4. PLL frequency at 3.2 GHz and TXOUT_DIV = 2.
5. PLL frequency at 1.6 GHz and TXOUT_DIV = 1.
6. PLL frequency at 2.5 GHz and TXOUT_DIV = 2.
7. PLL frequency at 2.5 GHz and TXOUT_DIV = 4.
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**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 58:_ **GTP Transceiver Receiver Switching Characteristics**
|**Symbol**<br>~~a~~|**Description**|**Description**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|FGTPRX<br>~~a~~|Serial data rate|RX oversampler not enabled|0.500|–|FGTPMAX|Gb/s|
|TRXELECIDLE<br>~~a~~|Time for RXELECIDLE to respond to loss or restoration of data||–|10|–|ns|
|RXOOBVDPP<br>~~a~~|OOB detect threshold peak-to-peak||60|–|150|mV|
|RXSST<br>~~a ee~~|Receiver spread-spectrum<br>tracking(1)<br>~~ee~~|Modulated @ 33 kHz<br>~~ee~~|–5000<br>~~ee~~|–<br>~~ee~~|5000<br>~~ee~~|ppm<br>~~ee~~|
|RXRL<br>~~a ee~~<br>~~a~~|Run length (CID)<br>~~ee~~|~~ee~~|–<br>~~ee~~|–<br>~~ee~~|512<br>~~ee~~|UI<br>~~ee~~|
|RXPPMTOL<br>~~a~~<br>~~a~~|Data/REFCLK PPM offset tolerance||–1250|–|1250|ppm|
|**SJ Jitter Tolerance(2)**<br>~~ee~~|||||||
|JT_SJ6.6<br>~~ee~~|Sinusoidal Jitter(3)<br>|6.6 Gb/s<br>|0.44<br>|–<br>|–<br>|UI<br>|
|JT_SJ5.0<br>~~eea~~|Sinusoidal Jitter(3)<br>~~a~~|5.0 Gb/s<br>~~a~~|0.44<br>~~a~~|–<br>~~a~~|–<br>~~a~~|UI<br>~~a~~|
|JT_SJ4.25<br>~~a~~<br>~~a~~|Sinusoidal Jitter(3)<br>~~a~~<br>~~a~~|4.25 Gb/s<br>~~a~~<br>~~a~~|0.44<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|UI<br>~~a~~<br>~~a~~|
|JT_SJ3.75<br>~~a~~<br>~~a~~|Sinusoidal Jitter(3)<br>~~a~~<br>~~a~~|3.75 Gb/s<br>~~a~~<br>~~a~~|0.44<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|UI<br>~~a~~<br>~~a~~|
|JT_SJ3.2<br>~~a~~<br>~~a~~|Sinusoidal Jitter(3)<br>~~a~~<br>~~a~~|3.2 Gb/s(4)<br>~~a~~<br>~~a~~<br>~~a~~|0.45<br>~~a~~<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~<br>~~a~~|UI<br>~~a~~<br>~~a~~<br>~~a~~|
|JT_SJ3.2L<br>~~a~~<br>~~a~~|Sinusoidal Jitter(3)<br>~~a~~<br>~~a~~|3.2 Gb/s(5)<br>~~a~~<br>~~a~~<br>~~a~~|0.45<br>~~a~~<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~<br>~~a~~|UI<br>~~a~~<br>~~a~~<br>~~a~~|
|JT_SJ2.5<br>~~a~~<br>~~a~~|Sinusoidal Jitter(3)<br>~~a~~<br>~~a~~|2.5 Gb/s(6)<br>~~a~~<br>~~a~~<br>~~a~~|0.5<br>~~a~~<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~<br>~~a~~|UI<br>~~a~~<br>~~a~~<br>~~a~~|
|JT_SJ1.25<br>~~a~~<br>~~a~~|Sinusoidal Jitter(3)<br>~~a~~<br>~~a~~|1.25 Gb/s(7)<br>~~a~~<br>~~a~~|0.5<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|UI<br>~~a~~<br>~~a~~|
|JT_SJ500<br>~~a~~<br>~~a~~|Sinusoidal Jitter(3)<br>~~a~~<br>~~a~~<br>~~a~~|500 Mb/s<br>~~a~~<br>~~a~~<br>~~a~~|0.4<br>~~a~~<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~<br>~~a~~|UI<br>~~a~~<br>~~a~~<br>~~a~~|
|**SJ Jitter Tolerance with Stressed Eye(2)**<br>~~a~~<br>~~a~~|||||||
|JT_TJSE3.2<br>~~a~~<br>~~a~~|Total Jitter with Stressed Eye(8)<br>~~a~~|3.2 Gb/s<br>~~a~~<br>~~i~~|0.70<br>~~a~~|–<br>~~a~~|–<br>~~a~~|UI<br>~~a~~|
|JT_TJSE6.6<br>~~a~~<br>~~a~~||6.6 Gb/s<br>~~a~~<br>~~i~~|0.70<br>~~a~~|–<br>~~a~~|–<br>~~a~~|UI<br>~~a~~|
|JT_SJSE3.2<br>~~a~~<br>~~a~~<br>~~**a**~~|Sinusoidal Jitter with Stressed<br>Eye(8)<br>~~a~~<br>~~a~~|3.2 Gb/s<br>~~a~~<br>~~i~~<br>~~**a**~~|0.1<br>~~a~~|–<br>~~a~~|–<br>~~a~~|UI<br>~~a~~|
|JT_SJSE6.6<br>~~**a**~~||6.6 Gb/s<br>~~**a**~~|0.1|–|–|UI|
## **Notes:**
1. Using RXOUT_DIV = 1, 2, and 4.
2. All jitter values are based on a bit error ratio of 1e[–12] .
3. The frequency of the injected sinusoidal jitter is 10 MHz.
4. PLL frequency at 3.2 GHz and RXOUT_DIV = 2.
5. PLL frequency at 1.6 GHz and RXOUT_DIV = 1.
6. PLL frequency at 2.5 GHz and RXOUT_DIV = 2.
7. PLL frequency at 2.5 GHz and RXOUT_DIV = 4.
8. Composite jitter.
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**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
## **GTP Transceiver Protocol Jitter Characteristics**
For Table 59 through Table 63, the _7 Series FPGAs GTP Transceiver User Guide_ (UG482) contains recommended settings for optimal usage of protocol specific characteristics.
|For Table 59 through Table 63, theTable 59 through Table 63, thethrough Table 63, theTable 63, the, the(UG482) contains recommended settings forUG482) contains recommended settings for<br>) contains recommended settings forcontains recommended settings for<br>optimal usage of protocol specific characteristics.|) contains recommended settings forcontains recommended settings for|
|---|---|
|_Table 59:_ **Gigabit Ethernet Protocol Characteristics**||
|**Description**<br>**Line Rate (Mb/s)**<br>**Min**<br>**Max**<br>**Units**<br>**Gigabit Ethernet Transmitter Jitter Generation**<br>Total transmitter jitter (T_TJ)<br>1250<br>–<br>0.24<br>UI<br>**Gigabit Ethernet Receiver High Frequency Jitter Tolerance**<br>Total receiver jitter tolerance<br>1250<br>0.749<br>–<br>UI<br>~~—SS=~~||
|_Table 60:_ **XAUI Protocol Characteristics**||
|**Description**<br>**Line Rate (Mb/s)**<br>**Min**<br>**Max**<br>**Units**<br>**XAUI Transmitter Jitter Generation**<br>Total transmitter jitter (T_TJ)<br>3125<br>–<br>0.35<br>UI<br>**XAUI Receiver High Frequency Jitter Tolerance**<br>Total receiver jitter tolerance<br>3125<br>0.65<br>–<br>UI<br>~~————~~||
|_Table 61:_ **PCI Express Protocol Characteristics(1)**||
|**Standard**<br>**Description**<br>**Line Rate (Mb/s)**<br>**Min**<br>**Max**<br>**Units**<br>**PCI Express Transmitter Jitter Generation**<br>PCI Express Gen 1<br>Total transmitter jitter<br>2500<br>–<br>0.25<br>UI<br>PCI Express Gen 2<br>Total transmitter jitter<br>5000<br>–<br>0.25<br>UI<br>**PCI Express Receiver High Frequency Jitter Tolerance**<br>PCI Express Gen 1<br>Total receiver jitter tolerance<br>2500<br>0.65<br>–<br>UI<br>PCI Express Gen 2(2)<br>Receiver inherent timing error<br>5000<br>0.40<br>–<br>UI<br>Receiver inherent deterministic timing error<br>0.30<br>–<br>UI<br>~~OO~~||
|**Notes:**||
|1.<br>Tested per card electromechanical (CEM) methodology.||
|2.<br>Using common REFCLK.||||||
|---|---|---|---|---|---|
|_Table 62:_ **CEI-6G Protocol Characteristics**||||||
|**Description**<br>**Line Rate (Mb/s)**<br>**Interface**<br>**Min**<br>**Max**<br>**Units**<br>**CEI-6G Transmitter Jitter Generation**<br>Total transmitter jitter(1)<br>4976–6375<br>CEI-6G-SR<br>–<br>0.3<br>UI<br>**CEI-6G Receiver High Frequency Jitter Tolerance**<br>Total receiver jitter tolerance(1)<br>4976–6375<br>CEI-6G-SR<br>0.6<br>–<br>UI<br>~~SSS~~||||||
|**Notes:**||||||
|1.<br>Tested at most commonly used line rate of 6250 Mb/s using 390.625 MHz reference clock.|Tested at most commonly used line rate of 6250 Mb/s using 390.625 MHz reference clock.|||||
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**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 63:_ **CPRI Protocol Characteristics**
|_Table 63:_ **CPRI Protocol Characteristics**|~~G~~||||
|---|---|---|---|---|
|**Description**<br>~~a~~|**Line Rate (Mb/s)**<br>~~a~~<br>~~G~~|**Min**<br>~~a~~|**Max**<br>~~a~~|**Units**<br>~~a~~|
|**CPRI Transmitter Jitter Generation**<br>~~G~~<br>~~pe~~|||||
|Total transmitter jitter<br>~~pe~~|614.4<br>~~e~~<br>~~ee~~|–<br>~~e~~<br>~~ee~~|0.35<br>~~e~~<br>~~ee~~|UI<br>~~e~~<br>~~ee~~|
||1228.8<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~|0.35<br>~~ee~~<br>~~ee~~|UI<br>~~ee~~<br>~~ee~~|
||2457.6<br>~~ee~~|–<br>~~ee~~|0.35<br>~~ee~~|UI<br>~~ee~~|
||3072.0<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~|0.35<br>~~ee~~<br>~~ee~~|UI<br>~~ee~~<br>~~ee~~|
||4915.2<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~|0.3<br>~~ee~~<br>~~ee~~|UI<br>~~ee~~<br>~~ee~~|
||6144.0<br>~~ee~~<br>~~po~~|–<br>~~ee~~<br>~~po~~|0.3<br>~~ee~~<br>~~po~~|UI<br>~~ee~~<br>~~po~~|
|**CPRI Receiver Frequency Jitter Tolerance**<br>~~po~~|||||
|Total receiver jitter tolerance|614.4<br>~~ee~~|0.65<br>~~ee~~|–<br>~~ee~~|UI<br>~~ee~~|
||1228.8<br>~~ee~~|0.65<br>~~ee~~|–<br>~~ee~~|UI<br>~~ee~~|
||2457.6<br>~~ee~~<br>~~es~~|0.65<br>~~ee~~<br>~~es~~|–<br>~~ee~~<br>~~es~~|UI<br>~~ee~~<br>~~es~~|
||3072.0<br>~~es~~<br>~~ee~~|0.65<br>~~es~~<br>~~ee~~|–<br>~~es~~<br>~~ee~~|UI<br>~~es~~<br>~~ee~~|
||4915.2(1)<br>~~ee~~|0.60<br>~~ee~~|–<br>~~ee~~|UI<br>~~ee~~|
||6144.0(1)<br>~~ee~~<br>~~es~~|0.60<br>~~ee~~<br>~~es~~|–<br>~~ee~~<br>~~es~~|UI<br>~~ee~~<br>~~es~~|
## **Notes:**
1. Tested to CEI-6G-SR.
## **Integrated Interface Block for PCI Express Designs Switching Characteristics**
More information and documentation on solutions for PCI Express designs can be found at: - www.xilinx.com/products/technology/pci express.html
_Table 64:_ **Maximum Performance for PCI Express Designs**
|**Symbol**|**Description**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|---|
|||**1.0V**|||**0.95V**|**0.9V**||
|||**-3**|**-2/-2LE**|**-1**|**-1LI**|**-2LE**||
|FPIPECLK|Pipe clock maximum frequency|250.00|250.00|250.00|250.00|250.00|MHz|
|FUSERCLK|User clock maximum frequency|250.00|250.00|250.00|250.00|250.00|MHz|
|FUSERCLK2|User clock 2 maximum frequency|250.00|250.00|250.00|250.00|250.00|MHz|
|FDRPCLK|DRP clock maximum frequency|250.00|250.00|250.00|250.00|250.00|MHz|
## **Notes:**
1. Refer to PG054, _7 Series FPGAs Integrated Block for PCI Express Product Guide_ for specific supported core configurations.
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**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
## AMD7Z1 **Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics XADC Specifications** _Table 65:_ **XADC Specifications Parameter Symbol Comments/Conditions Min Typ Max Units** ~~GG~~
## **XADC Specifications**
## _Table 65:_ **XADC Specifications**
|**Parameter**<br>~~GG~~|**Symbol**<br>~~GG~~|**Comments/Conditions**<br>~~GG~~|**Min**<br>~~GG~~|**Typ**<br>~~GG~~|**Max**<br>~~GG~~|**Units**<br>~~GG~~|
|---|---|---|---|---|---|---|
|VCCADC= 1.8V ± 5%, VREFP= 1.25V, VREFN= 0V, ADCCLK = 26 MHz, –55°CTj125°C, Typical values at Tj=+40°C<br>~~pT~~|||||||
|**ADC Accuracy(1)**<br>~~pT~~<br>~~pn~~|||||||
|Resolution<br>~~pn~~<br>~~eG~~|||12<br>~~pn~~<br>~~eG~~|–<br>~~pn~~<br>~~eG~~|–<br>~~pn~~<br>~~eG~~|Bits<br>~~pn~~<br>~~eG~~|
|Integral Nonlinearity(2)<br>~~+~~|INL<br>~~+~~|–40°CTj100°C<br>~~+~~|–<br>~~+~~|–<br>~~+~~|±2<br>~~+~~|LSBs<br>~~—~~|
|||–55°CTj< –40°C; 100°C < Tj125°C<br>~~+~~<br>~~ee~~|–<br>~~+~~<br>~~ee~~|–<br>~~+~~<br>~~ee~~|±3<br>~~+~~<br>~~ee~~|LSBs<br>~~—~~<br>~~ee~~|
|Differential Nonlinearity<br>~~+~~<br>~~GG~~|DNL<br>~~+~~<br>~~GG~~|No missing codes, guaranteed monotonic<br>~~+~~<br>~~ee~~<br>~~GG~~|–<br>~~+~~<br>~~ee~~<br>~~GG~~<br>~~ee~~|–<br>~~+~~<br>~~ee~~<br>~~GG~~<br>~~ee~~|±1<br>~~+ ~~<br>~~ee~~<br>~~GG~~<br>~~ee~~|LSBs<br> ~~—~~<br>~~ee~~<br>~~GG~~<br>~~ee~~|
|Offset Error|Unipolar<br>~~ee~~|–40°CTj100°C<br>~~ee~~|–<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~|±8<br>~~ee~~<br>~~ee~~|LSBs<br>~~ee~~<br>~~ee~~|
|||–55°CTj< –40°C; 100°C < Tj125°C<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~<br>~~ee~~|±12<br>~~ee~~<br>~~ee~~<br>~~ee~~|LSBs<br>~~ee~~<br>~~ee~~<br>~~ee~~|
||Bipolar<br>~~ee~~<br>~~Ge~~|–55°CTj125°C<br>~~ee~~<br>~~ee~~<br>~~Ge~~|–<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~Ge~~|–<br>~~ee~~<br>~~ee ~~<br>~~ee~~<br>~~Ge~~|±4<br>~~ee~~<br> ~~ee~~<br>~~ee~~<br>~~Ge~~|LSBs<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~Ge~~|
|Gain Error<br>~~Ge~~<br>~~a~~|||–<br>~~Ge~~<br>~~a~~|–<br>~~Ge~~<br>~~a~~|±0.5<br>~~Ge~~<br>~~a~~|%<br>~~Ge~~<br>~~a~~|
|Offset Matching<br>~~a~~<br>~~a~~|||–<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|4<br>~~a~~<br>~~a~~|LSBs<br>~~a~~<br>~~a~~|
|Gain Matching<br>~~a~~<br>~~a~~|||–<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|0.3<br>~~a~~<br>~~a~~|%<br>~~a~~<br>~~a~~|
|Sample Rate<br>~~a~~<br>~~a~~|||–<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|1<br>~~a~~<br>~~a~~|MS/s<br>~~a~~<br>~~a~~|
|Signal to Noise Ratio(2)<br>~~a~~<br>~~DO~~|SNR<br>~~a~~<br>~~DO~~|FSAMPLE= 500KS/s, FIN= 20 kHz<br>~~a~~<br>~~DO~~|60<br>~~a~~<br>~~DO~~|–<br>~~a~~<br>~~DO~~|–<br>~~a~~<br>~~DO~~|dB<br>~~a~~<br>~~DO~~|
|RMS Code Noise<br>~~DO~~<br>~~ry~~||External 1.25V reference<br>~~DO~~<br>~~ry~~|–<br>~~DO~~<br>~~ry~~|–<br>~~DO~~<br>~~ry~~|2<br>~~DO~~<br>~~ry~~|LSBs<br>~~DO~~<br>~~ry~~|
|||On-chip reference<br>~~ry~~<br>~~ee~~|–<br>~~ry~~<br>~~ee~~|3<br>~~ry~~<br>~~ee~~|–<br>~~ry~~<br>~~ee~~|LSBs<br>~~ry~~<br>~~ee~~|
|Total Harmonic Distortion(2)<br>~~ry~~<br>~~DO~~|THD<br>~~ry~~<br>~~DO~~|FSAMPLE= 500KS/s, FIN= 20 kHz<br>~~ry~~<br>~~ee~~<br>~~DO~~|70<br>~~ry~~<br>~~ee~~<br>~~DO~~|–<br>~~ry~~<br>~~ee~~<br>~~DO~~|–<br>~~ry~~<br>~~ee~~<br>~~DO~~|dB<br>~~ry~~<br>~~ee~~<br>~~DO~~|
|**Analog Inputs**(3)<br>~~DO~~<br>~~pe~~|||||||
|ADC Input Ranges<br>~~pe~~<br>~~a~~||Unipolar operation<br>~~pe~~<br>~~ee~~|0<br>~~pe~~<br>~~ee~~|–<br>~~pe~~<br>~~ee~~|1<br>~~pe~~<br>~~ee~~|V<br>~~pe~~<br>~~ee~~|
|||Bipolar operation<br>~~ee~~<br>~~ee~~|–0.5<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~|+0.5<br>~~ee~~<br>~~ee~~|V<br>~~ee~~<br>~~ee~~|
|||Unipolar common mode range (FS input)<br>~~ee~~<br>~~ee~~|0<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~|+0.5<br>~~ee~~<br>~~ee~~|V<br>~~ee~~<br>~~ee~~|
|||Bipolar common mode range (FS input)<br>~~ee~~|+0.5<br>~~ee~~|–<br>~~ee~~|+0.6|V|
|Maximum External Channel Input Ranges<br>~~a~~||Adjacent analog channels set within these<br>ranges should not corrupt measurements on<br>adjacent channels<br>~~ee~~|–0.1<br>~~ee~~|–<br>~~ee~~|VCCADC|V|
|Auxiliary Channel Full<br>Resolution Bandwidth<br>~~a~~|FRBW|~~ee ~~|250<br> ~~ee~~|–<br>~~ee~~|–|kHz|
|**On-Chip Sensors**<br>~~|~~<br>~~pe~~<br>~~———ry———y——~~|||||||
|Temperature Sensor Error<br>~~|~~<br>~~pe~~<br>~~ee~~||–40°CTj100°C<br>~~|~~<br>~~———ry———y——~~|–<br>~~|~~<br>~~———ry———y——~~|–<br>~~|~~<br>~~———ry———y——~~|±4<br>~~|~~<br>~~———ry———y——~~|°C<br>~~|~~<br>~~———ry———y——~~|
|||–55°CTj< –40°C; 100°C < Tj125°C<br>~~———ry———y——~~<br>~~ee~~<br>~~ee~~<br>~~————~~|–<br>~~———ry———y——~~<br>~~ee~~<br>~~———— EE~~|–<br>~~———ry———y——~~<br>~~ee~~<br>~~EE~~|±6<br>~~———ry———y——~~<br>~~ee~~<br>~~EE~~|°C<br>~~———ry———y——~~<br>~~ee~~<br>~~EE~~|
|Supply Sensor Error<br>~~pe~~<br>~~ee~~||–40°CTj100°C<br>~~———ry———y——~~<br>~~ee~~<br>~~————~~|–<br>~~———ry———y——~~<br>~~———— EE~~|–<br>~~———ry———y——~~<br>~~EE~~|±1<br>~~———ry———y——~~<br>~~EE~~|%<br>~~———ry———y——~~<br>~~EE~~|
|||–55°CTj< –40°C; 100°C < Tj125°C<br>~~ee~~<br>~~————~~<br>~~a~~|–<br>~~———— EE~~<br>~~a~~|–<br>~~EE~~<br>~~a~~|±2<br>~~EE~~<br>~~a~~|%<br>~~EE~~<br>~~a~~|
|**Conversion Rate**(4)<br>~~ee~~<br>~~———— EE~~<br>~~a~~<br>~~pT~~|||||||
|Conversion Time - Continuous<br>~~eG~~|tCONV<br>~~eG~~|Number of ADCCLK cycles<br>~~Ge~~|26<br>~~Ge~~|–<br>~~Ge~~|32|Cycles|
|Conversion Time - Event<br>~~eG~~<br>~~Ge~~|tCONV<br>~~eG~~<br>~~Ge~~|Number of CLK cycles<br>~~Ge~~<br>~~CO~~|–<br>~~Ge~~<br>~~CO~~|–<br>~~Ge~~<br>~~CO~~|21<br>~~CO~~|Cycles|
|DRP Clock Frequency<br>~~Ge~~<br>~~GG~~|DCLK<br>~~Ge~~<br>~~GG~~|DRP clock frequency<br>~~CO~~<br>~~GG~~|8<br>~~CO~~<br>~~GG~~|–<br>~~CO~~<br>~~GG~~|250<br>~~CO~~<br>~~GG~~|MHz<br>~~GG~~|
|ADC Clock Frequency<br>~~GO~~|ADCCLK<br>~~GO~~|Derived from DCLK<br>~~GO~~|1<br>~~GO~~|–<br>~~GO~~|26<br>~~GO~~|MHz<br>~~GO~~|
|DCLK Duty Cycle<br>~~GO~~<br>~~a~~|||40<br>~~GO~~<br>~~a~~|–<br>~~GO~~<br>~~a~~|60<br>~~GO~~<br>~~a~~|%<br>~~GO~~<br>~~a~~|
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**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 65:_ **XADC Specifications** _**(Cont’d)**_
|**Parameter**|**Symbol**|**Comments/Conditions**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|**XADC Reference**(5)|||||||
|External Reference|VREFP|Externally supplied reference voltage|1.20|1.25|1.30|V|
|On-Chip Reference||Ground VREFPpin to AGND,<br>–40°CTj100°C|1.2375|1.25|1.2625|V|
|||Ground VREFPpin to AGND,<br>–55°CTj< –40°C; 100°C < Tj125°C|1.225|1.25|1.275|V|
## **Notes:**
1. Offset and gain errors are removed by enabling the XADC automatic gain calibration feature. The values are specified for when this feature is enabled.
2. Only specified for bitstream option XADCEnhancedLinearity = ON.
3. See the ADC chapter in the _7 Series FPGAs and Zynq 7000 SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter_ (UG480) for a detailed description.
4. See the Timing chapter in the _7 Series FPGAs and Zynq 7000 SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter_ (UG480) for a detailed description.
5. Any variation in the reference voltage from the nominal VREFP = 1.25V and VREFN = 0V will result in a deviation from the ideal transfer function. This also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). However, for external ratiometric type applications allowing reference to vary by ±4% is permitted.
## **Configuration Switching Characteristics**
_Table 66:_ **Configuration Switching Characteristics**
|**Symbol**<br>~~eo~~|**Description**<br>~~eo~~|**Speed Grade**<br>~~pt~~<br>~~eo~~|**Speed Grade**<br>~~pt~~<br>~~eo~~|**Speed Grade**<br>~~pt~~<br>~~eo~~|**Speed Grade**<br>~~pt~~<br>~~eo~~|**Speed Grade**<br>~~pt~~<br>~~eo~~|**Units**<br>~~pt~~<br>~~eo~~<br>~~ee~~|
|---|---|---|---|---|---|---|---|
|||**1.0V**<br>~~pt~~<br>~~eo~~<br>~~esee~~<br>~~ee~~|||**0.95V**<br>~~pt~~<br>~~eo~~<br>~~ee~~|**0.9V**<br>~~pt~~<br>~~eo~~<br>~~ee~~||
|||**-3**<br>~~eo~~<br>~~es~~|**-2/-2LE**<br>~~eo~~<br>~~ee~~|**-1**<br>~~eo~~<br>~~ee~~|**-1LI**<br>~~eo~~<br>~~ee~~|**-2LE**<br>~~eo~~<br>~~ee~~||
|**Power-up Timing Characteristics**<br>~~es ee~~<br>~~ee~~<br>~~ee~~<br>~~—————~~||||||||
|TPL(1)<br>~~—————~~<br>~~Se~~|Program latency<br>~~—————~~<br>~~Se~~|5.00<br>~~—————~~|5.00<br>~~—————~~|5.00<br>~~—————~~|5.00<br>~~—————~~|5.00<br>~~—————~~|ms, Max<br>~~—————~~|
|TPOR(1)<br>~~—————~~<br>~~Se~~|Power-on reset (50 ms ramp rate time)<br>~~—————~~<br>~~Se~~|10/50<br>~~—————~~|10/50<br>~~—————~~|10/50<br>~~—————~~|10/50<br>~~—————~~|10/50<br>~~—————~~|ms, Min/Max<br>~~—————~~|
||Power-on reset (1 ms ramp rate time)<br>~~—————~~<br>~~Se~~|10/35<br>~~—————~~|10/35<br>~~—————~~|10/35<br>~~—————~~|10/35<br>~~—————~~|10/35<br>~~—————~~|ms, Min/Max<br>~~—————~~|
|TPROGRAM<br>~~Se~~<br>~~Ge~~|Program pulse width<br>~~Se~~<br>~~Ge~~|250.00<br>~~Ge~~|250.00<br>~~Ge~~|250.00<br>~~Ge~~|250.00<br>~~Ge~~|250.00<br>~~Ge~~|ns, Min<br>~~Ge~~|
|**CCLK Output (Master Mode)**<br>~~Ge~~||||||||
|TICCK<br>~~FG~~|Master CCLK output delay<br>~~FG~~|150.00<br>~~FG~~|150.00<br>~~FG~~|150.00<br>~~FG~~|150.00<br>~~FG~~|150.00<br>~~FG~~|ns, Min<br>~~FG~~|
|TMCCKL<br>~~FG~~<br>~~GG~~|Master CCLK clock Low time duty cycle<br>~~FG~~<br>~~GG~~|40/60<br>~~FG~~<br>~~GG~~|40/60<br>~~FG~~<br>~~GG~~|40/60<br>~~FG~~<br>~~GG~~|40/60<br>~~FG~~<br>~~GG~~|40/60<br>~~FG~~<br>~~GG~~|%, Min/Max<br>~~FG~~<br>~~GG~~|
|TMCCKH<br>~~GG~~<br>~~ee~~<br>~~eens~~|Master CCLK clock High time duty cycle<br>~~GG~~<br>~~ee~~<br>~~eens~~|40/60<br>~~GG~~<br>~~ee~~<br>~~eee~~|40/60<br>~~GG~~<br>~~ee~~<br>~~eee~~|40/60<br>~~GG~~<br>~~ee~~<br>~~eee~~|40/60<br>~~GG~~<br>~~ee~~<br>~~ee~~|40/60<br>~~GG~~<br>~~ee~~<br>~~ee~~|%, Min/Max<br>~~GG~~<br>~~ee~~<br>~~ee~~|
|FMCCK<br>~~ee~~<br>~~eens~~|Master CCLK frequency<br>~~ee~~<br>~~eens~~|100.00<br>~~ee~~<br>~~eee~~|100.00<br>~~ee~~<br>~~eee~~|100.00<br>~~ee~~<br>~~eee~~|100.00<br>~~ee~~<br>~~ee~~|70.00<br>~~ee~~<br>~~ee~~|MHz, Max<br>~~ee~~<br>~~ee~~|
||Master CCLK frequency for AES encrypted x16<br>~~ee~~<br>~~eens~~|50.00<br>~~ee~~<br>~~eee~~|50.00<br>~~ee~~<br>~~eee~~|50.00<br>~~ee~~<br>~~eee~~|50.00<br>~~ee~~<br>~~ee~~|35.00<br>~~ee~~<br>~~ee~~|MHz, Max<br>~~ee~~<br>~~ee~~|
|FMCCK_START<br>~~eens~~<br>~~eG~~|Master CCLK frequency at start of configuration<br>~~eens ~~<br>~~eG~~|3.00<br> ~~eee ~~<br>~~eG~~|3.00<br> ~~eee ~~<br>~~eG~~|3.00<br> ~~eee ~~<br>~~eG~~|3.00<br> ~~ee ~~<br>~~eG~~|3.00<br> ~~ee ~~<br>~~eG~~|MHz, Typ<br> ~~ee~~<br>~~eG~~|
|FMCCKTOL<br>~~eG~~<br>~~a~~|Frequency tolerance, master mode with respect<br>to nominal CCLK<br>~~eG~~<br>|±50<br>~~eG~~<br>|±50<br>~~eG~~<br>|±50<br>~~eG~~<br>|±50<br>~~eG~~<br>|±50<br>~~eG~~<br>|%, Max<br>~~eG~~<br>|
|**CCLK Input (Slave Modes)**<br>~~a~~||||||||
|TSCCKL<br>~~GG~~|Slave CCLK clock minimum Low time<br>~~GG~~|2.50<br>~~GG~~|2.50<br>~~GG~~|2.50<br>~~GG~~<br>~~CO~~|2.50<br>~~GG~~<br>~~CO~~|2.50<br>~~GG~~<br>~~CO~~|ns, Min<br>~~GG~~|
|TSCCKH<br>~~GG~~<br>~~eG~~|Slave CCLK clock minimum High time<br>~~GG~~<br>~~eG~~|2.50<br>~~GG~~<br>~~eG~~|2.50<br>~~GG~~<br>~~eG~~|2.50<br>~~GG~~<br>~~eG~~<br>~~CO~~|2.50<br>~~GG~~<br>~~eG~~<br>~~CO~~|2.50<br>~~GG~~<br>~~eG~~<br>~~CO~~|ns, Min<br>~~GG~~<br>~~eG~~|
|FSCCK<br>~~eG~~<br>~~a~~|Slave CCLK frequency<br>~~eG~~<br>~~a~~|100.00<br>~~eG~~<br>~~a~~|100.00<br>~~eG~~<br>~~a~~|100.00<br>~~eG~~<br>~~CO~~<br>~~a~~|100.00<br>~~eG~~<br>~~CO~~<br>~~a~~|70.00<br>~~eG~~<br>~~CO~~<br>~~a~~|MHz, Max<br>~~eG~~<br>~~a~~|
|**EMCCLK Input (Master Mode)**<br>~~a~~<br>~~Rs~~||||||||
|TEMCCKL<br>~~Rs~~|External master CCLK Low time<br>|2.50<br>|2.50<br>|2.50<br>|2.50<br>|2.50<br>|ns, Min<br>|
|TEMCCKH<br>~~RsCG~~|External master CCLK High time<br>~~CG~~|2.50<br>~~CG~~|2.50<br>~~CG~~|2.50<br>~~CG~~|2.50<br>~~CG~~|2.50<br>~~CG~~|ns, Min<br>~~CG~~|
|FEMCCK<br>~~CG~~|External master CCLK frequency<br>~~CG~~|100.00<br>~~CG~~|100.00<br>~~CG~~|100.00<br>~~CG~~|100.00<br>~~CG~~|70.00<br>~~CG~~|MHz, Max<br>~~CG~~|
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**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 66:_ **Configuration Switching Characteristics** _**(Cont’d)**_
|**Symbol**|**Description**|**Speed Grade**<br>~~OO~~|**Speed Grade**<br>~~OO~~|**Speed Grade**<br>~~OO~~|**Speed Grade**<br>~~OO~~|**Speed Grade**<br>~~OO~~|**Units**|
|---|---|---|---|---|---|---|---|
|||**1.0V**<br>~~a~~|||**0.95V**|**0.9V**||
|||**-3**<br>~~a~~|**-2/-2LE**<br>~~a~~|**-1**<br>~~a~~<br>~~a~~|**-1LI**<br>~~a~~|**-2LE**<br>~~a~~||
|**Internal Configuration Access Port**<br>~~a~~<br>~~TO~~||||||||
|FICAPCK<br>~~TO~~<br>~~OO~~|Internal configuration access port (ICAPE2)<br>clock frequency<br>~~TO~~<br>|100.00<br>~~TO~~<br>|100.00<br>~~TO~~<br>|100.00<br>~~TO~~<br>|100.00<br>~~TO~~<br>|70.00<br>~~TO~~<br>|MHz, Max<br>~~TO~~<br>|
|**Master/Slave Serial Mode Programming Switching**<br>~~OO~~||||||||
|TDCCK/<br>TCCKD<br>~~OO~~|DIN setup/hold<br>|4.00/0.00<br>|4.00/0.00<br>|4.00/0.00<br>|4.00/0.00<br>|5.00/0.00<br>|ns, Min<br>|
|TCCO<br>~~a~~|DOUT clock to out<br>~~a~~|8.00<br>~~a~~|8.00<br>~~a~~|8.00<br>~~a~~|8.00<br>~~a~~|9.00<br>~~a~~|ns, Max<br>~~a~~|
|**SelectMAP Mode Programming Switching**<br>~~a~~||||||||
|TSMDCCK/<br>TSMCCKD|D[31:00] setup/hold|4.00/0.00|4.00/0.00|4.00/0.00|4.00/0.00|4.50/0.00|ns, Min|
|TSMCSCCK/<br>TSMCCKCS|CSI_B setup/hold|4.00/0.00|4.00/0.00|4.00/0.00|4.00/0.00|5.00/0.00|ns, Min|
|TSMWCCK/<br>TSMCCKW|RDWR_B setup/hold|10.00/0.00|10.00/0.00|10.00/0.00|10.00/0.00|12.00/0.00|ns, Min|
|TSMCKCSO|CSO_B clock to out (330pull-up resistor<br>required)|7.00|7.00|7.00|7.00|8.00|ns, Max|
|TSMCO<br>~~a~~|D[31:00] clock to out in readback<br>~~a~~|8.00<br>~~a~~<br>~~A~~|8.00<br>~~a~~|8.00<br>~~a~~|8.00<br>~~a~~|10.00<br>~~a~~|ns, Max<br>~~a~~|
|FRBCCK<br>~~a~~<br>~~a~~|Readback frequency<br>~~a~~<br>~~a~~|100.00<br>~~a~~<br>~~a~~<br>~~A~~|100.00<br>~~a~~<br>~~a~~|100.00<br>~~a~~<br>~~a~~|100.00<br>~~a~~<br>~~a~~|70.00<br>~~a~~<br>~~a~~|MHz, Max<br>~~a~~<br>~~a~~|
|**Boundary-Scan Port Timing Specifications**<br>~~a~~<br>~~A~~<br>~~OO~~||||||||
|TTAPTCK/<br>TTCKTAP|TMS and TDI setup/hold|3.00/2.00|3.00/2.00|3.00/2.00|3.00/2.00|3.00/2.00|ns, Min|
|TTCKTDO<br>~~a~~|TCK falling edge to TDO output|7.00|7.00|7.00|7.00|8.50|ns, Max|
|FTCK<br>~~a~~<br>~~OO~~|TCK frequency|66.00|66.00|66.00|66.00|50.00|MHz, Max|
|**BPI Flash Master Mode Programming Switching**<br>~~a~~<br>~~OO~~||||||||
|TBPICCO(2)<br>~~OO~~|A[28:00], RS[1:0], FCS_B, FOE_B, FWE_B,<br>ADV_B clock to out|8.50|8.50|8.50|8.50|10.00|ns, Max|
|TBPIDCC/<br>TBPICCD<br>~~OO~~|D[15:00] setup/hold<br>|4.00/0.00<br>|4.00/0.00<br>|4.00/0.00<br>|4.00/0.00<br>|4.50/0.00<br>|ns, Min<br>|
|**SPI Flash Master Mode Programming Switching**<br>~~OO~~||||||||
|TSPIDCC/<br>TSPICCD<br>~~OO~~|D[03:00] setup/hold<br>|3.00/0.00<br>|3.00/0.00<br>|3.00/0.00<br>|3.00/0.00<br>|3.00/0.00<br>|ns, Min<br>|
|TSPICCM<br>~~ee~~|MOSI clock to out<br>~~ee~~|8.00<br>~~ee~~|8.00<br>~~ee~~|8.00<br>~~ee~~|8.00<br>~~ee~~|9.00<br>~~ee~~|ns, Max<br>~~ee~~|
|TSPICCFC<br>~~ee~~<br>~~a~~|FCS_B clock to out<br>~~ee~~<br>~~a~~|8.00<br>~~ee~~<br>~~a~~|8.00<br>~~ee~~<br>~~a~~|8.00<br>~~ee~~<br>~~a~~|8.00<br>~~ee~~<br>~~a~~|9.00<br>~~ee~~<br>~~a~~|ns, Max<br>~~ee~~<br>~~a~~|
|**STARTUPE2 Ports**||||||||
|TUSRCCLKO|STARTUPE2 USRCCLKO input to CCLK output|0.50/6.00|0.50/6.70|0.50/7.50|0.50/7.50|0.50/7.50|ns,<br>Min/Max|
|FCFGMCLK|STARTUPE2 CFGMCLK output frequency<br>~~ee~~|65.00<br>~~ee~~|65.00<br>~~ee~~|65.00<br>~~ee~~|65.00<br>~~ee~~|65.00<br>~~ee~~|MHz, Typ<br>~~ee~~|
|FCFGMCLKTOL <br>~~a~~|STARTUPE2 CFGMCLK output frequency<br>tolerance<br>~~a~~<br>~~ee~~|±50<br>~~a~~<br>~~ee~~|±50<br>~~a~~<br>~~ee~~|±50<br>~~a~~<br>~~ee~~|±50<br>~~a~~<br>~~ee~~|±50<br>~~a~~<br>~~ee~~|%, Max<br>~~a~~<br>~~ee~~|
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**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
_Table 66:_ **Configuration Switching Characteristics** _**(Cont’d)**_
|**Symbol**|**Description**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|---|
|||**1.0V**|||**0.95V**|**0.9V**||
|||**-3**|**-2/-2LE**|**-1**|**-1LI**|**-2LE**||
|**Device DNA Access Port**||||||||
|FDNACK|DNA access port (DNA_PORT)|100.00|100.00|100.00|100.00|70.00|MHz, Max|
## **Notes:**
1. To support longer delays in configuration, use the design solutions described in _7 Series FPGA Configuration User Guide_ (UG470).
2. Only during configuration, the last edge is determined by a weak pull-up/pull-down resistor in the I/O.
## **eFUSE Programming Conditions**
Table 67 lists the programming conditions specifically for eFUSE. For more information, see _7 Series FPGA Configuration User Guide_ (UG470).
_Table 67:_ **eFUSE Programming Conditions[(1)]**
|_Table 67:_ **eFUSE Programming Conditions**|**eFUSE Programming Conditions[(1)]**|||||
|---|---|---|---|---|---|
|**Symbol**|**Description**|**Min**|**Typ**|**Max**|**Units**|
|IFS|VCCAUXsupply current|–|–|115|mA|
|Tj|Temperature range|15|–|125|°C|
## **Notes:**
1. The FPGA must not be configured during eFUSE programming.
## **Revision History**
The following table shows the revision history for this document:
|**Date**|**Version**|**Description**|
|---|---|---|
|09/26/2011|1.0|Initial Xilinx release.|
|11/07/2011|1.1|Revised the VOCMspecification inTable 11. Updated theAC Switching Characteristicsbased upon the<br>ISE 13.3 software v1.02 speed specification throughout document includingTable 13andTable 14.<br>Added MMCM_TFBDELAYwhile adding MMCM_ to the symbol names of a few specifications in<br>Table 37and PLL to the symbol names inTable 38. InTable 39throughTable 46, updated the pin-to-<br>pin description with the SSTL15 standard. Updated units in Table 46.|
|02/13/2012|1.2|Updated the Artix 7 family of devices listed throughout the entire data sheet. Updated theAC Switching<br>Characteristicsbased upon the ISE 13.4 software v1.03 for the -3, -2, and -1 speed grades and v1.00<br>for the -2L speed grade.<br>Updated summary description onpage 1. InTable 2, revised VCCOfor the 3.3V HR I/O banks and<br>updated Tj. Updated the notes inTable 5. Added MGTAVCC and MGTAVTT power supply ramp times<br>toTable 7. RearrangedTable 8, added Mobile_DDR, HSTL_I_18, HSTL_II_18, HSUL_12,<br>SSTL135_R, SSTL15_R, and SSTL12 and removed DIFF_SSTL135, DIFF_SSTL18_I,<br>DIFF_SSTL18_II, DIFF_HSTL_I, and DIFF_HSTL_II. AddedTable 9andTable 10. Revised the<br>specifications inTable 11. Revised VINinTable 50. Updated theeFUSE Programming Conditions<br>section and removed the endurance table. Added the table. Revised FTXINand FRXINinTable 56.<br>Revised ICCADCand updatedNote 1inTable 65. Revised DDR LVDS transmitter data width in<br>Table 15. Removed notes fromTable 27as they are no longer applicable. Updated specifications in<br>Table 66. UpdatedNote 1inTable 36.|
DS181 (v1.27.1) July 3, 2024 **Product Specification**
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**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
|**Date**|**Version**|**Description**|
|---|---|---|
|06/01/2012|1.3|Reorganized entire data sheet including addingTable 43andTable 47.<br>Updated TSOLinTable 1. Updated IBATTand added RIN_TERMtoTable 3. UpdatedPower-On/Off Power<br>Supply Sequencingsection with regards to GTP transceivers. InTable 8, updated many parameters<br>including SSTL135 and SSTL135_R. Removed VOXcolumn and added DIFF_HSUL_12 toTable 10.<br>Updated VOLinTable 11. UpdatedTable 15and removed notes 2 and 3. UpdatedTable 16.<br>Updated theAC Switching Characteristicsbased upon the ISE 14.1 software v1.03 for the -3, -2, -2L<br>(1.0V), -1, and v1.01 for the -2L (0.9V) speed specifications throughout the document.<br>InTable 30, updatedReset Delayssection includingNote 10andNote 11. InTable 56, replaced<br>FTXOUTwith FGLK. Updated many of the XADC specifications inTable 65and addedNote 2. Updated<br>and moved_Dynamic Reconfiguration Port (DRP) for MMCM Before and After DCLK_section from<br>Table 66toTable 37andTable 38.|
|09/20/2012|1.4|InTable 1, updated the descriptions, changed VINandNote 2, and addedNote 4. InTable 2, changed<br>descriptions and notes. Updated parameters inTable 3. AddedTable 4. Revised thePower-On/Off<br>Power Supply Sequencingsection. Updated standards and specifications inTable 8,Table 9, and<br>Table 10. Removed the XC7A350T device from data sheet.<br>Updated theAC Switching Characteristicssection to the ISE 14.2 speed specifications throughout the<br>document. Updated theIOB Pad Input/Output/3-Statediscussion and changedTable 18by adding<br>TIOIBUFDISABLE. Removed many of the combinatorial delay specifications and TCINCK/TCKCINfrom<br>Table 27.Changed FPFDMAXconditions inTable 37andTable 38. Updated theGTP Transceiver<br>Specificationssection, moved the GTP Transceiver DC characteristics section to the overallDC<br>Characteristicssection, and added theGTP Transceiver Protocol Jitter Characteristicssection. In<br>Table 65, updatedNote 1. InTable 66, updated TPOR.|
|02/01/2013|1.5|Updated theAC Switching Characteristicsbased upon the 14.4/2012.4 device pack for ISE 14.4 and<br>Vivado 2012.4, both at v1.07 for the -3, -2, -2L (1.0V), -1 speed specifications, and v1.05 for the -2L<br>(0.9V) speed specifications throughout the document. Production changes toTable 13andTable 14<br>for -3, -2, -2L (1.0V), -1 speed specifications.<br>Revised IDCINand IDCOUTand added Note 5 inTable 1. AddedNote 2toTable 2. UpdatedTable 5.<br>Added minimum current specifications toTable 6. Removed SSTL12 and HSTL_I_12 fromTable 8.<br>Removed DIFF_SSTL12 fromTable 10. UpdatedTable 13. Added a 2:1 memory controller section to<br>Table 16. UpdatedNote 1inTable 34. RevisedTable 36. UpdatedNote 1andNote 2inTable 49.<br>Updated DVPPINinTable 50. Updated VIDIFFinTable 51. Removed TLOCKand TPHASEand revised<br>FGCLKinTable 54. Updated TDLOCKinTable 55. UpdatedTable 56. InTable 57, updated TRTX, TFTX,<br>VTXOOBVDPP, and revisedNote 1throughNote 7. InTable 58, updated RXSSTand RXPPMTOLand<br>revisedNote 4throughNote 7. InTable 63, revised and addedNote 1.<br>Revised the maximum external channel input ranges inTable 65. InTable 66, revised FMCCKand<br>added theInternal Configuration Access Portsection.|
|04/17/2013|1.6|Updated theAC Switching Characteristicsbased upon v1.07 of the ISE 14.5 and Vivado 2013.1 for the<br>-3, -2, -2L (1.0V), and -1 speed specifications, and v1.05 for the -2L (0.9V) speed specifications.<br>Production changes toTable 13andTable 14for -2L (0.9V) speed specifications.<br>InTable 1, revised VIN(I/O input voltage) to match values inTable 4and combinedNote 4with old Note<br>5 and then added newNote 5. Revised VINdescription, removed Note 10, and addedNote 7inTable 2.<br>Updated first 3 rows inTable 4. Also revised PCI33_3 voltage minimum inTable 8to match values in<br>Table 1andTable 4. AddedNote 1toTable 11. Removed Note 1 fromTable 14. UpdatedTable 16title.<br>Throughout the data sheet (Table 28,Table 29, andTable 44) removed the obvious note “A Zero “0”<br>Hold Time listing indicates no hold time or a negative hold time.”|
|09/04/2013|1.7|Added new Artix 7 devices (XC7A35T, XC7A50T, and XC7A75T) throughout. InTable 1, updated IDCIN<br>and IDCOUTfor cases when floating, at VMGTAVTT, or GND. Added back Note 1 toTable 14. Added CPG<br>package toTable 50andTable 52.|
|11/27/2013|1.8|Added automotive and expanded temperature range Artix 7 devices throughout. Added -1M and -1Q<br>speed grades throughout. Added reference to_7 Series FPGAs Overview_,_Defense-Grade 7 Series_<br>_FPGAs Overview_, and_XA Artix 7 FPGAs Overview_inIntroduction. InTable 2, added junction<br>temperature operating ranges for expanded (Q) and military (M) devices, and addedNote 3. InTable 3,<br>removed commercial (C), industrial (I), and extended (E) from descriptions of RIN_TERM. Updated<br>temperature ranges inTable 4. Removed notes fromTable 6. Added TJ= 125°C to Conditions column<br>for TVCCO2VCCAUXinTable 7. InAC Switching Characteristics, updated first paragraph, added<br>Table 12, and added -1Q/-1M speed grades to other tables in this section. InTable 52, added RB and<br>RS packages, and updated FGTPMAX. InTable 65, updated ADC Accuracy, On-Chip Sensors, XADC<br>Reference sections and notes. Added TUSRCCLKOand FDNACKtoTable 66.|
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**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
|**Date**|**Version**|**Description**|
|---|---|---|
|01/07/2014|1.9|InTable 13, promoted all XC7A75T speed grades from Advance to Production and all XQ7A50T speed<br>grades from Preliminary to Advance. InTable 14, inserted “Vivado tools 2013.3” for the production<br>XC7A75T speed grades.|
|01/23/2014|1.10|Updated theAC Switching Characteristicsbased upon ISE 14.7 and Vivado 2013.4. UpdatedNote 5<br>inTable 2. Removed pad pull-down @ VIN= 1.8V for IRPDinTable 3. AddedNote 2toTable 4.<br>Removed XQ7A50T fromTable 12,Table 13, andTable 14. InTable 13, changed speed grades for XA<br>Artix 7 FPGAs and defense-grade Artix 7Q family from -2 to -2I and -1 to -1I, and moved all speed<br>grades of XA7A100T, and -1I and -2I speed grades of XQ7A100T from Preliminary to Production. In<br>Table 14, updated production software for XA7A100T and XQ7A100T. AddedHSUL_12_F,<br>DIFF_HSUL_12_F,MOBILE_DDR_S, MOBILE_DDR_F, DIFF_MOBILE_DDR_S, and<br>DIFF_MOBILE_DDR_F toTable 17. Removed introductory text inDevice Pin-to-Pin Output Parameter<br>Guidelines.|
|03/04/2014|1.11|UpdatedNote 2inTable 4. InTable 13, moved XQ7A100T -1M speed grade from Preliminary to<br>Production. InTable 14, added production software for XQ7A100T -1M speed grade.|
|03/28/2014|1.12|InTable 5, added ICCINTQ, ICCOQ, ICCAUXQ, and ICCBRAMQvalues for XC7A35T, XC7A50T, XA7A35T,<br>XA7A50T, and XQ7A50T devices. InTable 6, added power-on current values for XC7A35T, XC7A50T,<br>XA7A35T, XA7A50T, and XQ7A50T devices. InTable 12, added row for XC7A35T, XC7A50T, and<br>XC7A75T devices. InTable 13, moved all speed grades of XC7A35T and XC7A50T devices from<br>Advance to Production, and added XQ7A50T. InTable 14, added XQ7A50T and production software<br>for XC7A35T and XC7A50T -3, -2, -2L (1.0V), -1, and -2L (0.9V) speed grades. For FIDELAYCTRL_REF<br>inTable 25, updated REFCLK frequency of 300 MHz, added REFCLK frequency of 400 MHz, and<br>updatedNote 1. InTable 36, added TCKSKEWdata for XC7A35T and XC7A50T devices. InTable 39,<br>updated TICKOFdata for -1 and -2L (0.9V) speed grades of XC7A35T and XC7A50T devices. In<br>Table 40, updated TICKOFFARdata for -1 and -2L (0.9V) speed grades of XC7A35T and XC7A50T<br>devices. InTable 41, added TICKOFMMCMCCdata for -2L (0.9V) speed grade of XC7A35T and<br>XC7A50T devices. InTable 42, added TICKOFPLLCCdata for -2L (0.9V) speed grade of XC7A35T and<br>XC7A50T devices. InTable 44, updated TPSFD/TPHFDdata for -2/-2L, -1, and -2L (0.9V) speed grades<br>of XC7A35T and XC7A50T devices. InTable 45, updated TPSMMCMCC/TPHMMCMCCdata for -1 and -2L<br>(0.9V) speed grades of XC7A35T and XC7A50T devices. InTable 46, updated TPSPLLCC/TPHPLLCC<br>data for -1 and -2L (0.9V) speed grades of XC7A35T and XC7A50T devices. InTable 49, added<br>package skew values for XC7A35T, XC7A50T, XA7A35T, XA7A50T, and XQ7A50T devices.|
|05/13/2014|1.13|InAC Switching Characteristics, updated to Vivado 2014.1. InTable 12, updated Vivado 2014.1<br>version numbers and consolidated rows. InTable 13, moved all XA7A75T speed grades from Advance<br>to Preliminary and all XQ7A200T speed grades from Preliminary to Production. InTable 14, added<br>production software for XQ7A200T -2, -1, and -1M speed grades. Added timing data for XA7A35T,<br>XA7A50T, XA7A75T, and XQ7A50T devices toTable 39,Table 40,Table 41,Table 42,Table 44,<br>Table 45, andTable 46.|
|07/01/2014|1.14|UpdatedNote 2inTable 4per the customer notice XCN14014<br>: _7 Series FPGA and Zynq-7000 AP SoC_<br>_I/O Undershoot Voltage Data Sheet Update_. InPower-On/Off Power Supply Sequencing, added<br>sentence about there being no recommended sequence for supplies not shown. InAC Switching<br>Characteristics, updated to Vivado 2014.2. InTable 12, added row for XQ7A50T. InTable 13, moved<br>all XQ7A50T speed grades from Advance to Production. InTable 14, added production software for<br>XQ7A50T -2, -1, and -1M speed grades. InTable 36, added TCKSKEWvalues for XA7A35T, XA7A50T,<br>and XQ7A50T. Updated description of TICKOFinTable 39and addedNote 2. Updated description of<br>TICKOFFARinTable 40and addedNote 2. InTable 50, moved DVPPOUTvalue of 1000 mV from Max to<br>Min column, updated VINDC parameter description, and addedNote 2. Added “peak-to-peak” to labels<br>inFigure 3andFigure 4. Added note afterFigure 4. AddedNote 1toTable 64. InTable 66, replaced<br>USRCCLK Output with STARTUPE2 Ports and added FCFGMCLKand FCFGMCLKTOL.|
|09/23/2014|1.15|Removed 3.3V as descriptor of HR I/O banks throughout. UpdatedNote 3inTable 5. InTable 13,<br>moved all XA7A35T and XA7A50T speed grades from Advance to Production, and all XA7A75T speed<br>grades from Preliminary to Production. InTable 14, added production software for XA7A35T, XA7A50T,<br>and XA7A75T -2, -1, and -1Q speed grades, and removed Note 2. AddedI/O Standard Adjustment<br>Measurement Methodology.|
|10/09/2014|1.16|Added XC7A15T and XA7A15T devices. Added -1LI speed grade throughout. UpdatedIntroduction.<br>Added -1LI (0.95V) to description of VCCINTand VCCBRAMinTable 2. UpdatedNote 1and added<br>Note 2toTable 14.|
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**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
|**Date**|**Version**|**Description**|
|---|---|---|
|11/19/2014|1.17|Replaced -2L speed grade with -2LE throughout. Updated descriptions of VCCINTand VCCBRAMin<br>Table 2. Updated theAC Switching Characteristicsbased upon Vivado 2014.4. InTable 12, updated<br>Vivado software version and added a row for VCCINT= 0.95V. InTable 13, moved all speed grades for<br>all devices from Advance to Production. InTable 14, added Vivado 2014.4 software version to -1LI<br>(0.95V) speed grade column for commercial devices and applicable speed grades for XC7A15T and<br>XA7A15T devices, and removed table notes. AddedSelecting the Correct Speed Grade and Voltage<br>in the Vivado Tools. InTable 16, moved LPDDR2 row to end of 2:1 Memory Controllers section.<br>Updated speed grade heading row inTable 52.|
|03/18/2015|1.18|InTable 11, changed maximum VICMvalue from 1.425V to 1.500V. Removed LVDS 1.8V standard from<br>Table 19andTable 20. Removed minimum sample rate specification fromTable 65.|
|09/24/2015|1.19|Updated first paragraph inIntroduction. Assigned quiescent supply currents to -1LI speed grade<br>Artix-7Q devices inTable 5. InTable 14, changed -1LI speed grade Artix-7Q device cells from N/A to<br>blank and addedNote 1. Removed DIFF_SSTL12 standard fromTable 19andTable 20. Changed -1LI<br>speed grade Artix-7Q device cells from N/A to blank inTable 36,Table 39,Table 40,Table 41,Table 42,<br>Table 44,Table 45, andTable 46. Added SBV484, FBV484, FBV676, and FFV1156 packages to<br>Table 49. Removed Pb-free G suffix from packages inTable 50andTable 52.|
|11/24/2015|1.20|InAC Switching Characteristics, updated to Vivado 2015.4. InTable 13, added -1LI (0.95V) speed<br>grade to Production column for XQ7A50T, XQ7A100T, and XQ7A200T. InTable 14, removed table note<br>and added Vivado 2015.4 software version to -1LI (0.95V) speed grade column for XQ7A50T,<br>XQ7A100T, and XQ7A200T. InTable 36, added TCKSKEWfor XQ7A50T, XQ7A100T, and XQ7A200T<br>at -1LI (0.95V) speed grade. Updated device pin-to-pin output parameter tables (Table 39toTable 42)<br>and input parameter tables (Table 44toTable 46) for XQ7A50T, XQ7A100T, and XQ7A200T at -1LI<br>(0.95V) speed grade.|
|09/27/2016|1.21|Added XC7A12T and XC7A25T devices. Updated theAC Switching Characteristicsbased upon<br>Vivado 2016.3. InTable 19, updated VMEASvalues for LVCMOS 3.3V, LVTTL 3.3V, and PCI33 3.3V,<br>and removed note 1. Removed LVDCI_15, HSLVDCI_15, LVDCI_15, and HSLVDCI_18 I/O standards<br>fromTable 20.|
|04/13/2017|1.22|Added 1.35V toNote 5inTable 2. Updated theAC Switching Characteristicsbased upon Vivado<br>2016.4. InTable 13, added -2LE (0.9V) speed grade to Advance column for XC7A12T and XC7A25T.<br>InTable 25, changed TIDELAYRESOLUTIONunits from ps to µs. InTable 36, updated TCKSKEWfor<br>XC7A12T and XC7A25T devices at -2LE (0.9V) speed grade. Updated device pin-to-pin output<br>parameter tables (Table 39toTable 42) and input parameter tables (Table 44toTable 46) for XC7A12T<br>and XC7A25T devices at -2LE (0.9V) speed grade. Removed SBV484, FBV484, FBV676, and<br>FFV1156 packages fromTable 49per the customer notice XCN16022<br>: _Cross-ship of Lead-free Bump_<br>_and Substrates in Lead-free (FFG/FBG/SBG) Packages_.|
|12/21/2017|1.23|Updated theAC Switching Characteristicsbased upon Vivado 2017.4. For XC7A12T and XC7A25T in<br>Table 13, moved -3 and -2LE (0.9V) speed grades to Preliminary column and -2, -1, and -1LI (0.95V)<br>speed grades to Production column. InTable 14, added Vivado 2017.4 software version to -2, -2LE, -1,<br>and -1LI (0.95V) speed grade columns for XC7A12T and XC7A25T. InTable 44, updated TPSFD/ TPHFD<br>for XC7A12T and XC7A25T at -3, -2/-2LE, -1 and -1LI (0.95V) speed grades. InTable 46, updated<br>TPSPLLCCfor XC7A12T and XC7A25T at -1 and -1LI (0.95V) speed grades. InTable 49, added<br>package skew values for XC7A12T and XC7A25T.|
|04/04/2018|1.24|Added XA7A12T and XA7A25T devices. Updated theAC Switching Characteristicsbased upon<br>Vivado 2018.1. InTable 13, for XC7A12T and XC7A25T moved -2LE (0.9V) speed grade to Production<br>column and added XA7A12T and XA7A25T with -2I, -1I, and -1Q speed grades in Production column.<br>AddedNote 3toTable 16.|
|06/18/2018|1.25|Updated theAC Switching Characteristicsbased upon Vivado 2018.2. InTable 13, for XC7A12T and<br>XC7A25T moved -3 speed grade to Production. InTable 14, added Vivado 2018.2 software version to<br>-3 speed grade for XC7A12T and XC7A25T and removed note.|
|03/23/2021<br>~~a~~|1.26|Replaced D with DDLY in description of TISDCK_DDLY_DDR/TISCKD_DDLY_DDRinTable 23.|
|02/10/2022<br>~~a~~<br>~~a~~|1.27|Added -2LE (1.0V) speed grade for XC7A12T and XC7A25T devices toTable 13.|
|07/03/2024<br>~~a~~<br>~~a ~~|1.27.1<br> ~~a~~|Editorial updates only. No technical content updates.|
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**Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics**
## **Notice of Disclaimer**
The information presented in this document is for informational purposes only and may contain technical inaccuracies, omissions, and typographical errors. The information contained herein is subject to change and may be rendered inaccurate for many reasons, including but not limited to product and roadmap changes, component and motherboard version changes, new model and/or product releases, product differences between differing manufacturers, software changes, BIOS flashes, firmware upgrades, or the like. Any computer system has risks of security vulnerabilities that cannot be completely prevented or mitigated. AMD assumes no obligation to update or otherwise correct or revise this information. However, AMD reserves the right to revise this information and to make changes from time to time to the content hereof without obligation of AMD to notify any person of such revisions or changes. THIS INFORMATION IS PROVIDED “AS IS.” AMD MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE CONTENTS HEREOF AND ASSUMES NO RESPONSIBILITY FOR ANY INACCURACIES, ERRORS, OR OMISSIONS THAT MAY APPEAR IN THIS INFORMATION. AMD SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, OR FITNESS FOR ANY PARTICULAR PURPOSE. IN NO EVENT WILL AMD BE LIABLE TO ANY PERSON FOR ANY RELIANCE, DIRECT, INDIRECT, SPECIAL, OR OTHER CONSEQUENTIAL DAMAGES ARISING FROM THE USE OF ANY INFORMATION CONTAINED HEREIN, EVEN IF AMD IS EXPRESSLY ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
## **AUTOMOTIVE APPLICATIONS DISCLAIMER**
AUTOMOTIVE PRODUCTS (IDENTIFIED AS "XA" IN THE PART NUMBER) ARE NOT WARRANTED FOR USE IN THE DEPLOYMENT OF AIRBAGS OR FOR USE IN APPLICATIONS THAT AFFECT CONTROL OF A VEHICLE (“SAFETY APPLICATION”) UNLESS THERE IS A SAFETY CONCEPT OR REDUNDANCY FEATURE CONSISTENT WITH THE ISO 26262 AUTOMOTIVE SAFETY STANDARD (“SAFETY DESIGN”). CUSTOMER SHALL, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE PRODUCTS, THOROUGHLY TEST SUCH SYSTEMS FOR SAFETY PURPOSES. USE OF PRODUCTS IN A SAFETY APPLICATION WITHOUT A SAFETY DESIGN IS FULLY AT THE RISK OF CUSTOMER, SUBJECT ONLY TO APPLICABLE LAWS AND REGULATIONS GOVERNING LIMITATIONS ON PRODUCT LIABILITY.
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Updated at June 5, 2026
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