XC3S200AN-4FTG256C

FPGA, Spartan-3AN, DLL, 195 I/O's, 250 MHz, 4032 Cells, 1.14 V to 1.26 V, FCBGA-256, NCNR

⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
Manufacturer: AMD
Product type: FPGAs
No. of Logic Blocks:4032; No. of Macrocells:4032; FPGA Family:Spartan-3AN; Logic Case Style:FCBGA; No. of Pins:256Pins; No. of Speed Grades:4; Total RAM Bits:288Kbit; No. of I/O's:1
MSL: -
SVHC: No SVHC (15-Jan-2018)
FPGA Type: Flash based FPGA
FPGA Family: Spartan-3AN
IC Mounting: Surface Mount
No. of Pins: 256Pins
Speed Grade: 4
No. of I/O's: 195I/O's
Product Range: Spartan-3AN XC3S200AN
Qualification: -
Total RAM Bits: 288Kbit
No.of User I/Os: 195I/O's
Clock Management: DLL
Logic Case Style: FCBGA
IC Case / Package: FCBGA
No. of Macrocells: 4032Macrocells
I/O Supply Voltage: 3.6V
No. of Logic Cells: 4032Logic Cells
Process Technology: -
No. of Logic Blocks: 4032
No. of Speed Grades: 4
Core Supply Voltage Max: 1.26V
Core Supply Voltage Min: 1.14V
Operating Frequency Max: 250MHz
Operating Temperature Max: 85°C
Operating Temperature Min: 0°C
Delivery and price
Units per pack	1
Price	41.46 €
Current stock	10+
Lead time	30 days
Datasheet
DS557 June 12, 2014 

**Product Specification** 

**==> picture [143 x 46] intentionally omitted <==**

## **Spartan-3AN FPGA Family Data Sheet** 

## **Module 1: Introduction and Ordering Information DS557 (v4.2) June 12, 2014** 

- Introduction 

- Features 

- Architectural Overview 

- Configuration Overview 

- In-system Flash Memory Overview 

- General I/O Capabilities 

- Supported Packages and Package Marking 

- Ordering Information 

## **Module 2: Functional Description** 

## **DS557 (v4.2) June 12, 2014** 

The functionality of the Spartan®-3AN FPGA family is described in the following documents: 

- UG331 **:** _Spartan-3 Generation FPGA User Guide_ 

   - Clocking Resources 

   - Digital Clock Managers (DCMs) 

   - Block RAM 

   - Configurable Logic Blocks (CLBs) 

      - Distributed RAM 

      - SRL16 Shift Registers 

      - Carry and Arithmetic Logic 

   - I/O Resources 

   - Embedded Multiplier Blocks 

   - Programmable Interconnect 

   - ISE® Design Tools and IP Cores 

   - Embedded Processing and Control Solutions 

   - Pin Types and Package Overview 

   - Package Drawings 

   - Powering FPGAs 

   - Power Management 

- UG332: _Spartan-3 Generation Configuration User Guide_ 

   - Configuration Overview 

   - Configuration Pins and Behavior 

   - Bitstream Sizes 

   - Detailed Descriptions by Mode 

## **Module 3: DC and Switching Characteristics DS557 (v4.2) June 12, 2014** 

- DC Electrical Characteristics 

   - Absolute Maximum Ratings 

   - Supply Voltage Specifications 

   - Recommended Operating Conditions 

- Switching Characteristics 

   - I/O Timing 

   - Configurable Logic Block (CLB) Timing 

   - • Multiplier Timing 

   - Block RAM Timing 

   - Digital Clock Manager (DCM) Timing 

   - • Suspend Mode Timing 

   - Device DNA Timing 

   - Configuration and JTAG Timing 

## **Module 4: Pinout Descriptions** 

## **DS557 (v4.2) June 12, 2014** 

- Pin Descriptions 

- Package Overview 

- Pinout Tables 

- Footprint Diagrams 

_Table  1:_ **Production Status of Spartan-3AN FPGAs** 

|**Spartan-3AN FPGA**|**Status**|
|---|---|
|XC3S50AN|Production|
|XC3S200AN|Production|
|XC3S400AN|Production|
|XC3S700AN|Production|
|XC3S1400AN|Production|



Additional information on the Spartan-3AN family can be found at: 

http://www.xilinx.com/support/index.html/content/xilinx/en/s upportNav/silicon_devices/fpga/spartan-3an.html. 

      - Self-contained In-System Flash mode 

      - Master Serial Mode using Platform Flash PROM 

      - Master SPI Mode using Commodity Serial Flash 

      - Master BPI Mode using Commodity Parallel Flash 

      - Slave Parallel (SelectMAP) using a Processor 

      - Slave Serial using a Processor 

      - JTAG Mode 

   - ISE iMPACT Programming Examples 

   - MultiBoot Reconfiguration 

   - Design Authentication using Device DNA 

- UG333: _Spartan-3AN In-System Flash User Guide_ 

- UG334: _Spartan-3AN Starter Kit User Guide_ 

© Copyright 2007–2014 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners. 

DS557 June 12, 2014 **Product Specification** 

www.xilinx.com 

1 

**==> picture [143 x 46] intentionally omitted <==**

DS557 (v4.2) June 12, 2014 

## **Spartan-3AN FPGA Family: Introduction and Ordering Information** 

**Product Specification** 

## **Introduction** 

The Spartan®-3AN FPGA family combines the best attributes of a leading edge, low cost FPGA with nonvolatile technology across a broad range of densities. The family combines all the features of the Spartan-3A FPGA family plus leading technology in-system Flash memory for configuration and nonvolatile data storage. The Spartan-3AN FPGAs are part of the Extended Spartan-3A family, which also includes the Spartan-3A FPGAs and the higher density Spartan-3A DSP FPGAs. The Spartan-3AN FPGA family is excellent for space-constrained applications such as blade servers, medical devices, automotive infotainment, telematics, GPS, and other small consumer products. Combining FPGA and Flash technology minimizes chip count, PCB traces and overall size while increasing system reliability. 

The Spartan-3AN FPGA internal configuration interface is completely self-contained, increasing design security. The family maintains full support for external configuration. The Spartan-3AN FPGA is the world’s first nonvolatile FPGA with MultiBoot, supporting two or more configuration files in one device, allowing alternative configurations for field upgrades, test modes, or multiple system configurations. 

## **Features** 

- The new standard for low cost nonvolatile FPGA solutions 

- Eliminates traditional nonvolatile FPGA limitations with the advanced 90 nm Spartan-3A device feature set 

   - Memory, multipliers, DCMs, SelectIO, hot swap, power management, etc. 

- Integrated robust configuration memory 

   - Saves board space 

   - Improves ease-of-use 

   - Simplifies design 

   - Reduces support issues 

- Plentiful amounts of nonvolatile memory available to the user 

   - Up to 11+ Mb available 

   - MultiBoot support 

   - Embedded processing and code shadowing 

   - Scratchpad memory 

- Robust 100K Flash memory program/erase cycles 

- 20 years Flash memory data retention 

- Security features provide bitstream anti-cloning protection 

   - Buried configuration interface 

   - Unique Device DNA serial number in each device for design Authentication to prevent unauthorized copying 

   - • Flash memory sector protection and lockdown 

- Configuration watchdog timer automatically recovers from configuration errors 

- Suspend mode reduces system power consumption 

   - Retains all design state and FPGA configuration data 

   - Fast response time, typically less than 100 μs 

- Full hot-swap compliance 

- Multi-voltage, multi-standard SelectIO™ interface pins 

   - Up to 502 I/O pins or 227 differential signal pairs 

   - LVCMOS, LVTTL, HSTL, and SSTL single-ended signal standards 

   - 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling 

   - Up to 24 mA output drive 

   - 3.3V ±10% compatibility and hot swap compliance 

   - 622+ Mb/s data transfer rate per I/O 

   - DDR/DDR2 SDRAM support up to 400 Mb/s 

   - LVDS, RSDS, mini-LVDS, PPDS, and HSTL/SSTL differential I/O 

- Abundant, flexible logic resources 

   - Densities up to 25,344 logic cells 

   - Optional shift register or distributed RAM support 

   - Enhanced 18 x 18 multipliers with optional pipeline 

- Hierarchical SelectRAM™ memory architecture 

   - Up to 576 Kbits of dedicated block RAM 

   - Up to 176 Kbits of efficient distributed RAM 

- Up to eight Digital Clock Managers (DCMs) 

- Eight global clocks and eight additional clocks per each half of device, plus abundant low-skew routing 

- Complete Xilinx® ISE® and WebPACK™ software development system support 

- MicroBlaze™ and PicoBlaze  embedded processor cores 

- Fully compliant 32-/64-bit 33 MHz PCI™ technology support 

- Low-cost QFP and BGA Pb-free (RoHS) packaging options 

   - Pin-compatible with the same packages in the Spartan-3A FPGA family 

## _Table  2:_ **Summary of Spartan-3AN FPGA Attributes** 

|**Device**|**System**<br>**Gates**|<br>**Equivalent**<br>**Logic Cells **|**CLBs**|**Slices**|**Distributed**<br>**RAM Bits**(1)|**Block RAM**<br>**Bits**(1)|<br>**Dedicated**<br>**Multipliers **|**DCMs**|**Maximum**<br>**User I/O**|**Max Differential**<br>**I/O Pairs**|<br>**Bitstream**<br>**Size**(1)|<br>**In-System**<br>**Flash Bits**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|XC3S50AN|50K|1,584|176|704|11K|54K|3|2|108|50|427K|1M(2)|
|XC3S200AN|200K|4,032|448|1,792|28K|288K|16|4|195|90|1,168K|4M|
|XC3S400AN|400K|8,064|896|3,584|56K|360K|20|4|311|142|1,842K|4M|
|XC3S700AN|700K|13,248|1,472|5,888|92K|360K|20|8|372|165|2,669K|8M|
|XC3S1400AN|1400K|25,344|2,816|11,264|176K|576K|32|8|502|227|4,644K|16M|



## **Notes:** 

1. By convention, one Kb is equivalent to 1,024 bits and one Mb is equivalent to 1,024 Kb. 

2. Maximum supported by Xilinx tools. See the customer notice XCN14003: _Flash Wafer Fabrication Change and Gold (Au) To Copper (Cu) Transition for Spartan-3AN FPGA Devices_ . 

© Copyright 2007–2014 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners. 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

2 

**Spartan-3AN FPGA Family: Introduction and Ordering Information** 

## **Architectural Overview** 

The Spartan-3AN FPGA architecture is compatible with that of the Spartan-3A FPGA. The architecture consists of five fundamental programmable functional elements: 

- **Configurable Logic Blocks (CLBs)** contain flexible Look-Up Tables (LUTs) that implement logic plus storage elements used as flip-flops or latches. 

- **Input/Output Blocks (IOBs)** control the flow of data between the I/O pins and the internal logic of the device. IOBs support bidirectional data flow plus 3-state operation. They support a variety of signal standards, including several high-performance differential standards. Double Data-Rate (DDR) registers are included. 

- **Block RAM** provides data storage in the form of 18-Kbit dual-port blocks. 

- **Multiplier Blocks** accept two 18-bit binary numbers as inputs and calculate the product. 

- **Digital Clock Manager (DCM) Blocks** provide self-calibrating, fully digital solutions for distributing, delaying, multiplying, dividing, and phase-shifting clock signals. 

These elements are organized as shown in Figure 1. A dual ring of staggered IOBs surrounds a regular array of CLBs. Each device has two columns of block RAM except for the XC3S50AN, which has one column. Each RAM column consists of several 18-Kbit RAM blocks. Each block RAM is associated with a dedicated multiplier. The DCMs are positioned in the center with two at the top and two at the bottom of the device. The XC3S50AN has DCMs only at the top, while the XC3S700AN and XC3S1400AN add two DCMs in the middle of the two columns of block RAM and multipliers. 

The Spartan-3AN FPGA features a rich network of traces that interconnect all five functional elements, transmitting signals among them. Each functional element has an associated switch matrix that permits multiple connections to the routing. 

**==> picture [444 x 337] intentionally omitted <==**

**----- Start of picture text -----**<br>
IOBs<br>CLB<br>DCM<br>I OBs<br>DCM<br>CLBs<br>DCM<br>IOBs<br>DS557-1_01_122006<br>Multiplier<br>Block RAM<br>IOBs IOBs<br>Block RAM / Multiplier<br>**----- End of picture text -----**<br>


## **Notes:** 

1. The XC3S700AN and XC3S1400AN have two additional DCMs on both the left and right sides as indicated by the dashed lines. The XC3S50AN has only two DCMs at the top and only one Block RAM/Multiplier column. 

_Figure 1:_ **Spartan-3AN Family Architecture** 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

3 

**Spartan-3AN FPGA Family: Introduction and Ordering Information** 

## Spartan-3AN FPGA 

**==> picture [313 x 90] intentionally omitted <==**

**----- Start of picture text -----**<br>
‘0’ M2 VCCAUX 3.3V<br>Configure<br>from internal  ‘1’ M1 INIT_B<br>flash memory Indicates when<br>‘1’ M0 DONE configuration is<br>finished<br>DS557-1_06_082810<br>**----- End of picture text -----**<br>


_Figure 2:_ **Spartan-3AN FPGA Configuration Interface from Internal SPI Flash Memory** 

## **Configuration** 

Spartan-3AN FPGAs are programmed by loading configuration data into robust, reprogrammable, static CMOS configuration latches (CCLs) that collectively control all functional elements and routing resources. The FPGA’s configuration data is stored on-chip in nonvolatile Flash memory, or externally in a PROM or some other nonvolatile medium, either on or off the board. After applying power, the configuration data is written to the FPGA using any of seven different modes: 

- Configure from internal SPI Flash memory (Figure 2) 

   - Completely self-contained 

   - Reduced board space 

   - Easy-to-use configuration interface 

- Master Serial from a Xilinx Platform Flash PROM 

- Serial Peripheral Interface (SPI) from an external industry-standard SPI serial Flash 

- Byte Peripheral Interface (BPI) Up from an industry-standard x8 or x8/x16 parallel NOR Flash 

- Slave Serial, typically downloaded from a processor 

- Slave Parallel, typically downloaded from a processor 

- Boundary-Scan (JTAG), typically downloaded from a processor or system tester 

The MultiBoot feature stores multiple configuration files in the on-chip Flash, providing extended life with field upgrades. MultiBoot also supports multiple system solutions with a single board to minimize inventory and simplify the addition of new features, even in the field. Flexibility is maintained to do additional MultiBoot configurations via the external configuration method. 

The Spartan-3AN device authentication protocol prevents cloning. Design cloning, unauthorized overbuilding, and complete reverse engineering have driven device security requirements to higher and higher levels. Authentication moves the security from bitstream protection to the next generation of design-level security protecting both the design and embedded microcode. The authentication algorithm is entirely user defined, implemented using FPGA logic. Every product, generation, or design can have a different algorithm and functionality to enhance security. 

## **In-System Flash Memory** 

Each Spartan-3AN FPGA contains abundant integrated SPI serial Flash memory, shown in Table 3, used primarily to store the FPGA’s configuration bitstream. However, the Flash memory array is large enough to store at least two MultiBoot FPGA configuration bitstreams or nonvolatile data required by the FPGA application, such as code-shadowed MicroBlaze processor applications. 

_Table  3:_ **Spartan-3AN Device In-System Flash Memory** 

|**Part Number**|**Total Flash**<br>**Memory**<br>**(Bits)**|**FPGA**<br>**Bitstream**<br>**(Bits)**|**Additional**<br>**Flash**<br>**Memory**<br>**(Bits)**(1)|
|---|---|---|---|
|XC3S50AN|1,081,344(2)|437,312|642,048|
|XC3S200AN|4,325,376|1,196,128|3,127,872|
|XC3S400AN|4,325,376|1,886,560|2,437,248|
|XC3S700AN|8,650,752|2,732,640|5,917,824|
|XC3S1400AN|17,301,504|4,755,296|12,545,280|



## **Notes:** 

1. Aligned to next available page location. 

2. Maximum supported by Xilinx tools. 

After configuration, the FPGA design has full access to the in-system Flash memory via an internal SPI interface; the control logic is implemented with FPGA logic. Additionally, the FPGA application itself can store nonvolatile data or provide live, in-system Flash updates. 

The Spartan-3AN device in-system Flash memory supports leading-edge serial Flash features. 

- Small page size (264 or 528 bytes) simplifies nonvolatile data storage 

- Randomly accessible, byte addressable 

- Up to 66 MHz serial data transfers 

- SRAM page buffers 

   - Read Flash data while programming another Flash page 

   - EEPROM-like byte write functionality 

   - Two buffers in most devices, one in XC3S50AN 

- Page, Block, and Sector Erase 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

4 

**Spartan-3AN FPGA Family: Introduction and Ordering Information** 

- Sector-based data protection and security features 

   - Sector Protect: Write- and erase-protect a sector (changeable) 

   - Sector Lockdown: Sector data is unchangeable (permanent) 

- 128-byte Security Register 

   - Separate from FPGA’s unique Device DNA identifier 

   - 64-byte factory-programmed identifier unique to the in-system Flash memory 

   - 64-byte one-time programmable, user-programmable field 

- 100,000 Program/Erase cycles 

- 20-year data retention 

- Comprehensive programming support 

   - In-system prototype programming via JTAG using Xilinx Platform Cable USB and iMPACT software 

   - Product programming support using BPM Microsystems programmers with appropriate programming adapter 

   - Design examples demonstrating in-system programming from a Spartan-3AN FPGA application 

## **I/O Capabilities** 

The Spartan-3AN FPGA SelectIO interface supports many popular single-ended and differential standards. Table 4 shows the number of user I/Os as well as the number of differential I/O pairs available for each device/package combination. Some of the user I/Os are unidirectional, input-only pins as indicated in Table 4. 

Spartan-3AN FPGAs support the following single-ended standards: 

- 3.3V low-voltage TTL (LVTTL) 

- Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V, 1.5V, or 1.2V 

- 3.3V PCI at 33 MHz or 66 MHz 

- HSTL I, II, and III at 1.5V and 1.8V, commonly used in memory applications 

- SSTL I and II at 1.8V, 2.5V, and 3.3V, commonly used for memory applications 

Spartan-3AN FPGAs support the following differential standards: 

- LVDS, mini-LVDS, RSDS, and PPDS I/O at 2.5V or 3.3V 

- Bus LVDS I/O at 2.5V 

- TMDS I/O at 3.3V 

- Differential HSTL and SSTL I/O 

- LVPECL inputs at 2.5V or 3.3V 

_Table  4:_ **Available User I/Os and Differential (Diff) I/O Pairs** 

|**Package**(1)<br>**Body Size (mm)**|**TQ144**<br>**TQG144**|**TQ144**<br>**TQG144**|**FT256**<br>**FTG256**|**FT256**<br>**FTG256**|**FG400**<br>**FGG400**|**FG400**<br>**FGG400**|**FG484**<br>**FGG484**|**FG484**<br>**FGG484**|**FG676**<br>**FGG676**|**FG676**<br>**FGG676**|
|---|---|---|---|---|---|---|---|---|---|---|
||**20 x 20**(2)||**17 x 17**||**21 x 21**||**23 x 23**||**27 x 27**||
|**Device**(3)|**User**|**Diff**|**User**|**Diff**|**User**|**Diff**|**User**|**Diff**|**User**|**Diff**|
|XC3S50AN|**108**(4)<br>_(7)_|**50**<br>_(24)_|**144**(5)<br>_(32)_|**64**(5)<br>_(32)_|–|–|–|–|–|–|
|XC3S200AN|–|–|**195**<br>_(35)_|**90**<br>_(50)_|–|–|–|–|–|–|
|XC3S400AN|–|–|**195**<br>_(35)_|**90**<br>_(50)_|**311**<br>_(63)_|**142**<br>_(78)_|–|–|–|–|
|XC3S700AN|–|–|–|–|–|–|**372**<br>_(84)_|**165**<br>_(93)_|–|–|
|XC3S1400AN|–|–|–|–|–|–|**375**(5)<br>_(87)_|**165**(5)<br>_(93)_|**502**<br>_(94)_|**227**<br>_(131)_|



## **Notes:** 

1. See Pb and Pb-Free Packaging, page 7 for details on Pb and Pb-free packaging options. 

2. The footprint for the TQ(G)144 (22 mm x 22 mm) package is larger than the package body. 

3. Each Spartan-3AN FPGA has a pin-compatible Spartan-3A FPGA equivalent, although Spartan-3A FPGAs do not have internal SPI flash and offer more part/package combinations. 

4. The number shown in **bold** indicates the maximum number of I/O and input-only pins. The number shown in ( _italics_ ) indicates the number of input-only pins. The differential (Diff) input-only pin count includes both differential pairs on input-only pins and differential pairs on I/O pins within I/O banks that are restricted to differential inputs. 

5. Xilinx has issued a discontinuation notice for these highlighted devices/packages. For more information see XCN13016: _Product Discontinuation Notice For Selected Spartan-3AN FPGA Products_ . 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

5 

**Spartan-3AN FPGA Family: Introduction and Ordering Information** 

## **Package Marking** 

Figure 3 provides a top marking example for Spartan-3AN FPGAs in the quad-flat packages. Figure 4 shows the top marking for Spartan-3AN FPGAs in BGA packages. The markings for the BGA packages are nearly identical to those for the quad-flat packages, except that the marking is rotated with respect to the ball A1 indicator. 

The “5C” and “4I” Speed Grade/Temperature Range part combinations may be dual marked as “5C/4I”. Devices with the dual mark can be used as either -5C or -4I devices. Devices with a single mark are only guaranteed for the marked speed grade and temperature range. 

**==> picture [308 x 148] intentionally omitted <==**

**----- Start of picture text -----**<br>
Mask Revision Code<br>Fabrication Code<br>R<br>SPARTAN R Process Technology<br>Device Type XC3S50ANTM<br>Package TQG144 AGQ0725 Date Code<br>D1234567A<br>Speed Grade 4C Lot Code<br>Temperature Range<br>Pin P1 DS557-1_02_080107<br>**----- End of picture text -----**<br>


_Figure 3:_ **Spartan-3AN FPGA QFP Package Marking Example** 

**==> picture [290 x 112] intentionally omitted <==**

**----- Start of picture text -----**<br>
Mask Revision Code<br>BGA Ball A1 R<br>SPARTAN R Fabrication CodeProcess Code<br>Device Type XC3S200ANTM<br>Package FTG256 AGQ0725 Date Code<br>D1234567A<br>4C Lot Code<br>Speed Grade<br>Temperature Range<br>DS557-1_03_080107<br>**----- End of picture text -----**<br>


_Figure 4:_ **Spartan-3AN FPGA BGA Package Marking Example** 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

6 

**Spartan-3AN FPGA Family: Introduction and Ordering Information** 

## **Pb and Pb-Free Packaging** 

Spartan-3AN FPGAs are available in both leaded (Pb) and Pb-free packaging options (see Table 5). The Pb-free packages are available for all devices and include a ‘G’ character in the ordering code. Leaded (non-Pb-free) packages are available for selected devices. The ordering code for the leaded devices does not have an extra ‘G’. Leaded and Pb-free devices have the same pin-out. 

_Table  5:_ **Pb and Pb-Free Package Options** 

|**Pins**|**Pins**|**Pins**|**144**|**144**|**256**|**256**|**400**|**400**|**484**|**484**|**676**|**676**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Type**|||**TQFP**||**FTBGA**||**FBGA**||**FBGA**||**FBGA**||
|**Material**|||**Pb-Free**|**Pb**|**Pb-Free**|**Pb**|**Pb-Free**|**Pb**|**Pb-Free**|**Pb**|**Pb-Free**|**Pb**|
|**Device**|**Speed**|**Range**|**TQG144**|**TQ144**|**FTG256**|**FT256**|**FGG400**|**FG400**|**FGG484**|**FG484**|**FGG676**|**FG676**|
|XC3S50AN|-4|C, I|✔|SCD4100(1)|Note 3|Note 3|||||||
||-5|C|✔|Note 2|Note 3|Note 3|||||||
|XC3S200AN|-4|C, I|||✔|✔|||||||
||-5|C|||✔|✔|||||||
|XC3S400AN|-4|C, I|||✔|✔|✔|✔|||||
||-5|C|||✔|✔|✔|Note 2|||||
|XC3S700AN|-4|C, I|||||||✔|✔|||
||-5|C|||||||✔|Note 2|||
|XC3S1400AN|-4|C, I|||||||Note 3|Note 3|✔|✔|
||-5|C|||||||Note 3|Note 3|✔|Note 2|



## **Notes:** 

1. To order a Pb package for the XC3S50AN -4 option, append SCD4100 to the part number (XC3S50AN-4TQ144C4100). 

2. For Pb packaging for these options, contact your Xilinx sales representative. 

3. Xilinx has issued a discontinuation notice for these highlighted devices/packages. For more information see XCN13016: _Product Discontinuation Notice For Selected Spartan-3AN FPGA Products_ . 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

7 

**Spartan-3AN FPGA Family: Introduction and Ordering Information** 

## **Ordering Information** 

**Example: XC3S50AN -4 TQG144 C** Device Type Temperature Range: C = Commercial (TJ = 0[o] C to 85[o] C) Speed Grade I = Industrial (TJ = -40[o] C to 100[o] C) Package Type/Number of Pins 

DS557-1_05_101109 

_Figure 5:_ **Device Numbering Format** 

|**Device**|**Speed Grade**|**Speed Grade**|**Package Type / Number of Pins**|**Package Type / Number of Pins**|**Temperature Range (TJ)**|**Temperature Range (TJ)**|
|---|---|---|---|---|---|---|
|XC3S50AN|-4|Standard Performance|TQ144/<br>TQG144|144-pin Thin Quad Flat Pack (TQFP)|C|Commercial (0°C to 85°C)|
|XC3S200AN|-5|High Performance(1)|FT256/<br>FTG256|256-ball Fine-Pitch Thin Ball Grid Array (FTBGA)|I|Industrial (–40°C to 100°C)|
|XC3S400AN|||FG400/<br>FGG400|400-ball Fine-Pitch Ball Grid Array (FBGA)|||
|XC3S700AN|||FG484/<br>FGG484|484-ball Fine-Pitch Ball Grid Array (FBGA)|||
|XC3S1400AN|||FG676/<br>FGG676|676-ball Fine-Pitch Ball Grid Array (FBGA)|||



## **Notes:** 

1. The -5 speed grade is exclusively available in the Commercial temperature range. 

2. See Table 4 and Table 5 for available package combinations. 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

8 

**Spartan-3AN FPGA Family: Introduction and Ordering Information** 

## **Revision History** 

The following table shows the revision history for this document. 

|**Date**|**Version**|**Revision**|
|---|---|---|
|02/26/2007|1.0|Initial release.|
|08/16/2007|2.0|Updated for Production release of initial device.|
|09/12/2007|2.0.1|Noted that only dual-mark devices are guaranteed for both -4I and -5C.|
|12/12/2007|3.0|Updated to Production status with Production release of final family member, XC3S50AN. Noted that<br>non-Pb-free packages may be available for selected devices.|
|06/02/2008|3.1|Minor updates.|
|11/19/2009|3.2|Updated document throughout to reflect availability of Pb package options. Added references to the<br>Extended Spartan-3A family. Removed table note 2 fromTable 2. InTable 4, added Pb packages,<br>added table note 4, and updated table note 2. AddedTable 5.|
|12/02/2010|4.0|UpdatedNotice of Disclaimer.|
|04/01/2011|4.1|InTable 2, revised the Maximum Differential I/O Pairs and Maximum User I/O values for the<br>XC3S50AN. InTable 4, added packages to the XC3S50AN, XC3S400AN, and XC3S1400AN. Updated<br>Pb and Pb-Free Packagingsection andTable 5to include the new device/package combinations for<br>the XC3S50AN, XC3S400AN, and XC3S1400AN.|
|06/11/2014|4.2|InTable 2, revised the XC3S50AN values inMaximum User I/OandMax Differential I/O Pairscolumns,<br>and addedNote 2to theIn-System Flash Bitscolumn. InTable 3, added the sameNote 2. Descriptions<br>of these changes and further links to the product changes are outlined in the customer notice<br>XCN14003<br>: _Flash Wafer Fabrication Change and Gold (Au) To Copper (Cu) Transition for Spartan-3AN_<br>_FPGA Devices_.<br>Xilinx has issued a discontinuation notice for the XC3S50AN in the FT(G)256 package and the<br>XC3S1400AN in the FG(G)484 package. SeeXCN13016<br>: _Product Discontinuation Notice For_<br>_Selected Spartan-3AN FPGA Products_. This customer notice is highlighted inTable 4andTable 5.<br>UpdatedNotice of Disclaimer.|



## **Notice of Disclaimer** 

The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of Xilinx’s limited warranty, please refer to Xilinx’s Terms of Sale which can be viewed at www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in such critical applications, please refer to Xilinx’s Terms of Sale which can be viewed at www.xilinx.com/legal.htm#tos. 

## **AUTOMOTIVE APPLICATIONS DISCLAIMER** 

XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III) USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN SUCH APPLICATIONS. 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

9 

DS557 (v4.2) June 12, 2014 

**Product Specification** 

**==> picture [143 x 46] intentionally omitted <==**

## **Spartan-3AN FPGA Family: Functional Description** 

## **Spartan-3AN FPGA Design Documentation** 

The functionality of the Spartan®-3AN FPGA family is described in the following documents. The topics covered in each guide are listed below: 

- **DS706: Extended Spartan-3A Family Overview** 

- **UG331: Spartan-3 Generation FPGA User Guide** 

   - Clocking Resources 

   - Digital Clock Managers (DCMs) 

   - Block RAM 

   - Configurable Logic Blocks (CLBs) 

- 

## **UG333: Spartan-3AN FPGA In-System Flash User Guide** 

      - For FPGA applications that write to or read from the In-System Flash memory after configuration 

      - SPI_ACCESS interface 

      - In-System Flash memory architecture 

      - Read, program, and erase commands 

      - Status registers 

      - Sector Protection and Sector Lockdown features 

   - Distributed RAM 

   - SRL16 Shift Registers 

   - Carry and Arithmetic Logic 

- I/O Resources 

- Embedded Multiplier Blocks 

- Programmable Interconnect 

- ISE[®] Design Tools 

- IP Cores 

- Security Register with Unique Identifier 

Create a Xilinx user account and sign up to receive automatic e-mail notification whenever this data sheet or the associated user guides are updated. 

   - **Sign Up for Alerts on Xilinx.com** https://secure.xilinx.com/webreg/register.do?group=my profile&languageID=1 

- Embedded Processing and Control Solutions 

- Pin Types and Package Overview 

- Package Drawings 

- Powering FPGAs 

- Power Management 

## **• UG332: Spartan-3 Generation Configuration User Guide** 

- Configuration Overview 

## **Spartan-3AN FPGA Starter Kit** 

For specific hardware examples, please see the Spartan-3AN FPGA Starter Kit board web page, which has links to various design examples and the user guide. 

      - **Spartan-3AN FPGA Starter Kit Board Page** http://www.xilinx.com/s3anstarter 

      - **UG334: Spartan-3AN FPGA Starter Kit User Guide** 

   - Configuration Pins and Behavior 

   - Bitstream Sizes 

- Detailed Descriptions by Mode 

   - Master Serial Mode using Xilinx® Platform Flash 

   - Master SPI Mode using SPI Serial Flash PROM 

   - Internal Master SPI Mode 

   - Master BPI Mode using Parallel NOR Flash 

   - Slave Parallel (SelectMAP) using a Processor 

   - Slave Serial using a Processor 

   - JTAG Mode 

- ISE iMPACT Programming Examples 

- MultiBoot Reconfiguration 

- Design Authentication using Device DNA 

© Copyright 2007–2014 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners. 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

10 

**Spartan-3AN FPGA Family: Functional Description** 

## **Related Product Families** 

The Spartan-3AN FPGA family is generally compatible with the Spartan-3A FPGA family. 

- **DS529: Spartan-3A FPGA Family Data Sheet** 

## **Revision History** 

The following table shows the revision history for this document. 

|**Date**|**Version**|**Revision**|
|---|---|---|
|02/26/2007|1.0|Initial release.|
|08/16/2007|2.0|Updated for Production release of initial device.|
|09/12/2007|2.0.1|Minor updates to text.|
|09/24/2007|2.1|Added note that In-System Flash commands were not supported by simulation until ISE 10.1 software.|
|12/12/2007|3.0|Updated to Production status with Production release of final family member, XC3S50AN. Noted that<br>SPI_ACCESS simulation is supported in ISE 10.1 software. Updated links.|
|06/02/2008|3.1|Minor updates.|
|11/19/2009|3.2|In theSpartan-3AN FPGA Design Documentationsection, added link to DS706<br>, _Extended Spartan-3A_<br>_Family Overview_and removed references to older software versions.|
|12/02/2010|4.0|Updated link to sign up for Alerts and updatedNotice of Disclaimer.|
|04/01/2011|4.1|Added the FT(G)256 package selection for the XC3S50AN and XC3S400AN devices and the<br>FG(G)484 package selection for the XC3S1400AN device throughout this data sheet.|
|06/11/2014|4.2|Xilinx has issued a discontinuation notice for the XC3S50AN in the FT(G)256 package and the<br>XC3S1400AN in the FG(G)484 package. SeeXCN13016<br>: _Product Discontinuation Notice For_<br>_Selected Spartan-3AN FPGA Products_. UpdatedNotice of Disclaimer.|



## **Notice of Disclaimer** 

The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of Xilinx’s limited warranty, please refer to Xilinx’s Terms of Sale which can be viewed at www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in such critical applications, please refer to Xilinx’s Terms of Sale which can be viewed at www.xilinx.com/legal.htm#tos. 

## **AUTOMOTIVE APPLICATIONS DISCLAIMER** 

XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III) USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN SUCH APPLICATIONS. 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

11 

**Product Specification** 

**==> picture [143 x 46] intentionally omitted <==**

## **Spartan-3AN FPGA Family: DC and Switching Characteristics** 

DS557 (v4.2) June 12, 2014 

## **DC Electrical Characteristics** 

In this section, specifications can be designated as Advance, Preliminary, or Production. These terms are defined as follows: 

**Advance:** Initial estimates are based on simulation, early characterization, and/or extrapolation from the characteristics of other families. Values are subject to change. Use as estimates, not for production. 

**Preliminary:** Based on characterization. Further changes are not expected. 

**Production:** These specifications are approved once the silicon has been characterized over numerous production lots. Parameter values are considered stable with no future changes expected. 

All parameter limits are representative of worst-case supply voltage and junction temperature conditions. **Unless otherwise noted, the published parameter values apply to all Spartan** ® **-3AN devices. AC and DC characteristics are specified using the same numbers for both commercial and industrial grades.** 

## **Absolute Maximum Ratings** 

Stresses beyond those listed under Table 6: Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions beyond those listed under the Recommended Operating Conditions is not implied. Exposure to absolute maximum conditions for extended periods of time adversely affects device reliability. 

_Table  6:_ **Absolute Maximum Ratings** 

|**Symbol**|**Description**|**Conditions**|**Min**|**Max**|**Units**|
|---|---|---|---|---|---|
|VCCINT|Internal supply voltage||–0.5|1.32|V|
|VCCAUX|Auxiliary supply voltage||–0.5|3.75|V|
|VCCO|Output driver supply voltage||–0.5|3.75|V|
|VREF|Input reference voltage||–0.5|VCCO+ 0.5|V|
|VIN|Voltage applied to all User I/O pins and<br>dual-purpose pins|Driver in a high-impedance state|–0.95|4.6|V|
||Voltage applied to all Dedicated pins||–0.5|4.6|V|
|IIK|Input clamp current per I/O pin|–0.5V < VIN< (VCCO+ 0.5V)(1)|–|±100|mA|
|VESD|Electrostatic Discharge Voltage|Human body model|–|±2000|V|
|||Charged device model|–|±500|V|
|||Machine model|–|±200|V|
|TJ|Junction temperature||–|125|°C|
|TSTG|Storage temperature||–65|150|°C|



## **Notes:** 

1. Upper clamp applies only when using PCI IOSTANDARDs. 

1. For soldering guidelines, see UG112: Device Package User Guide and XAPP427: Implementation and Solder Reflow Guidelines for Pb-Free Packages. 

> © Copyright 2007–2014 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners. 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

12 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

## **Power Supply Specifications** 

_Table  7:_ **Supply Voltage Thresholds for Power-On Reset** 

|**Symbol**|**Description**|**Min**|**Max**|**Units**|
|---|---|---|---|---|
|VCCINTT|Threshold for the VCCINTsupply|0.4|1.0|V|
|VCCAUXT|Threshold for the VCCAUXsupply|1.0|2.0|V|
|VCCO2T|Threshold for the VCCOBank 2 supply|1.0|2.0|V|



## **Notes:** 

1. When configuring from the In-System Flash, VCCAUX must be in the recommended operating range; on power-up make sure VCCAUX reaches at least 3.0V before INIT_B goes High to indicate the start of configuration. VCCINT, VCCAUX, and VCCO supplies to the FPGA can be applied in any order if this requirement is met. However, an external configuration source might have specific requirements. Check the data sheet for the attached configuration source. Apply VCCINT last for lowest overall power consumption (see the chapter called “Powering Spartan-3 Generation FPGAs” in UG331 for more information). 

2. To ensure successful power-on, VCCINT, VCCO Bank 2, and VCCAUX supplies must rise through their respective threshold-voltage ranges with no dips at any point. 

_Table  8:_ **Supply Voltage Ramp Rate** 

|**Symbol**|**Description**|**Min**|**Max**|**Units**|
|---|---|---|---|---|
|VCCINTR|Ramp rate from GND to valid VCCINTsupply level|0.2|100|ms|
|VCCAUXR|Ramp rate from GND to valid VCCAUXsupply level|0.2|100|ms|
|VCCO2R|Ramp rate from GND to valid VCCOBank 2 supply level|0.2|100|ms|



## **Notes:** 

1. When configuring from the In-System Flash, VCCAUX must be in the recommended operating range; on power-up make sure VCCAUX reaches at least 3.0V before INIT_B goes High to indicate the start of configuration. VCCINT, VCCAUX, and VCCO supplies to the FPGA can be applied in any order if this requirement is met. However, an external configuration source might have specific requirements. Check the data sheet for the attached configuration source. Apply VCCINT last for lowest overall power consumption (see the chapter called “Powering Spartan-3 Generation FPGAs” in UG331 for more information). 

2. To ensure successful power-on, VCCINT, VCCO Bank 2, and VCCAUX supplies must rise through their respective threshold-voltage ranges with no dips at any point. 

_Table  9:_ **Supply Voltage Levels Necessary for Preserving CMOS Configuration Latch (CCL) Contents and RAM Data** 

|**Symbol**|**Description**|**Min**|**Units**|
|---|---|---|---|
|VDRINT|VCCINTlevel required to retain CMOS Configuration Latch (CCL) and RAM data|1.0|V|
|VDRAUX|VCCAUXlevel required to retain CMOS Configuration Latch (CCL) and RAM data|2.0|V|



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

13 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

## **General Recommended Operating Conditions** 

_Table  10:_ **General Recommended Operating Conditions** 

|**Symbol**|**Description**|**Description**||**Min**|**Nominal**|**Max**|**Units**|
|---|---|---|---|---|---|---|---|
|TJ|Junction temperature|Commercial||0|–|85|°C|
|||Industrial||–40|–|100|°C|
|VCCINT|Internal supply voltage|||1.14|1.20|1.26|V|
|VCCO(1)|Output driver supply voltage|||1.10|–|3.60|V|
|VCCAUX|Auxiliary supply voltage|VCCAUX= 3.3V||3.00|3.30|3.60|V|
|VIN(2)|Input voltage|PCI IOSTANDARD||–0.5|–|VCCO+ 0.5|V|
|||All other<br>IOSTANDARDs|IP or IO_#|–0.5|–|4.10|V|
||||IO_Lxxy_#(3)|–0.5|–|4.10|V|
|TIN|Input signal transition time(4)|||–|–|500|ns|



## **Notes:** 

1. This VCCO range spans the lowest and highest operating voltages for all supported I/O standards. Table 13 lists the recommended VCCO range specific to each of the single-ended I/O standards, and Table 15 lists that specific to the differential standards. 

2. See XAPP459, _Eliminating I/O Coupling Effects when Interfacing Large-Swing Single-Ended Signals to User I/O Pins on Spartan-3 Families_ . 

3. For single-ended signals that are placed on a differential-capable I/O, VIN of –0.2V to –0.5V is supported but can cause increased leakage between the two pins. See _Parasitic Leakage_ in UG331, _Spartan-3 Generation FPGA User Guide_ . 

4. Measured between 10% and 90% VCCO. Follow Signal Integrity recommendations. 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

14 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

## **General DC Characteristics for I/O Pins** 

_Table  11:_ **General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins** 

|**Symbol**|**Description**|**Test Conditions**|**Test Conditions**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|---|
|IL(2)|Leakage current at User I/O,<br>Input-only, Dual-Purpose, and<br>Dedicated pins, FPGA powered|Driver is in a high-impedance state,<br>VIN= 0V or VCCOmax, sample-tested||–10|–|+10|µA|
|IHS|Leakage current on pins during<br>hot socketing, FPGA unpowered|All pins except INIT_B, PROG_B, DONE, and JTAG<br>pins when PUDC_B = 1.||–10|–|+10|µA|
|||INIT_B, PROG_B, DONE, and JTAG pins or other<br>pins when PUDC_B = 0.||Add IHS+ IRPU|||µA|
|IRPU(3)|Current through pull-up resistor<br>at User I/O, Dual-Purpose,<br>Input-only, and Dedicated pins.<br>Dedicated pins are powered by<br>VCCAUX.(4)|VIN= GND|VCCOor VCCAUX=<br>3.0V to 3.6V|–151|–315|–710|µA|
||||VCCO= 2.3V to 2.7V|–82|–182|–437|µA|
||||VCCO= 1.7V to 1.9V|–36|–88|–226|µA|
||||VCCO= 1.4V to 1.6V|–22|–56|–148|µA|
||||VCCO= 1.14V to 1.26V|–11|–31|–83|µA|
|RPU(3)|Equivalent pull-up resistor value<br>at User I/O, Dual-Purpose,<br>Input-only, and Dedicated pins<br>(based on IRPUper Note3)|VIN= GND|VCCO= 3.0V to 3.6V|5.1|11.4|23.9|kΩ|
||||VCCO= 2.3V to 2.7V|6.2|14.8|33.1|kΩ|
||||VCCO= 1.7V to 1.9V|8.4|21.6|52.6|kΩ|
||||VCCO= 1.4V to 1.6V|10.8|28.4|74.0|kΩ|
||||VCCO= 1.14V to 1.26V|15.3|41.1|119.4|kΩ|
|IRPD(3)|Current through pull-down<br>resistor at User I/O,<br>Dual-Purpose, Input-only, and<br>Dedicated pins|VIN= VCCO|VCCAUX= 3.0V to 3.6V|167|346|659|µA|
|RPD(3)|Equivalent pull-down resistor<br>value at User I/O, Dual-Purpose,<br>Input-only, and Dedicated pins<br>(based on IRPDper Note3)|VCCAUX= 3.0V to 3.6V|VIN= 3.0V to 3.6V|5.5|10.4|20.8|kΩ|
||||VIN= 2.3V to 2.7V|4.1|7.8|15.7|kΩ|
||||VIN= 1.7V to 1.9V|3.0|5.7|11.1|kΩ|
||||VIN= 1.4V to 1.6V|2.7|5.1|9.6|kΩ|
||||VIN= 1.14V to 1.26V|2.4|4.5|8.1|kΩ|
|IREF|VREFcurrent per pin|All VCCOlevels||–10|–|+10|µA|
|CIN|Input capacitance|–||–|–|10|pF|
|RDT|Resistance of optional differential<br>termination circuit within a<br>differential I/O pair. Not available<br>on Input-only pairs.|VCCO= 3.3V±10%|LVDS_33,<br>MINI_LVDS_33,<br>RSDS_33|90|100|115|Ω|
|||VCCO= 2.5V±10%|LVDS_25,<br>MINI_LVDS_25,<br>RSDS_25|90|110|–|Ω|



## **Notes:** 

1. The numbers in this table are based on the conditions set forth in Table 10. 

2. For single-ended signals that are placed on a differential-capable I/O, VIN of –0.2V to –0.5V is supported but can cause increased leakage between the two pins. See _Parasitic Leakage_ in UG331, _Spartan-3 Generation FPGA User Guide_ . 

3. This parameter is based on characterization. The pull-up resistance RPU = VCCO / IRPU. The pull-down resistance RPD = VIN / IRPD. 

4. VCCAUX must be 3.3V on Spartan-3AN FPGAs. VCCAUX for Spartan-3A FPGAs can be either 3.3V or 2.5V. 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

15 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

## **Quiescent Current Requirements** 

_Table  12:_ **Spartan-3AN FPGA Quiescent Supply Current Characteristics** 

|**Symbol**|**Description**|**Device**|**Typical**(2)|**Commercial**<br>**Maximum**(2)|**Industrial**<br>**Maximum**(2)|**Units**|
|---|---|---|---|---|---|---|
|ICCINTQ|Quiescent VCCINTsupply current|XC3S50AN|2|20|30|mA|
|||XC3S200AN|7|50|70|mA|
|||XC3S400AN|10|85|125|mA|
|||XC3S700AN|13|120|185|mA|
|||XC3S1400AN|24|220|310|mA|
|ICCOQ|Quiescent VCCOsupply current|XC3S50AN|0.2|2|3|mA|
|||XC3S200AN|0.2|2|3|mA|
|||XC3S400AN|0.3|3|4|mA|
|||XC3S700AN|0.3|3|4|mA|
|||XC3S1400AN|0.3|3|4|mA|
|ICCAUXQ|Quiescent VCCAUXsupply current|XC3S50AN|3.1|8.1|10.1|mA|
|||XC3S200AN|5.1|12.1|15.1|mA|
|||XC3S400AN|5.1|18.1|24.1|mA|
|||XC3S700AN|6.1|28.1|34.1|mA|
|||XC3S1400AN|10.1|50.1|58.1|mA|



## **Notes:** 

1. The numbers in this table are based on the conditions set forth in Table 10. 

2. Quiescent supply current is measured with all I/O drivers in a high-impedance state and with all pull-up/pull-down resistors at the I/O pads disabled. The internal SPI Flash is deselected (CSB = High); the internal SPI Flash current is consumed on the VCCAUX supply rail. Typical values are characterized using typical devices at room temperature (TJ of 25°C at VCCINT = 1.2V, VCCO = 3.3V, and VCCAUX = 3.3V). The maximum limits are tested for each device at the respective maximum specified junction temperature and at maximum voltage limits with VCCINT = 1.26V, VCCO = 3.6V, and VCCAUX = 3.6V. The FPGA is programmed with a “blank” configuration data file (that is, a design with no functional elements instantiated). For conditions other than those described above (for example, a design including functional elements), measured quiescent current levels will be different than the values in the table. 

3. There are two recommended ways to estimate the total power consumption (quiescent plus dynamic) for a specific design: 

   - The Spartan-3AN FPGA Xilinx Power Estimator provides quick, approximate, typical estimates, and does not require a netlist of the design. 

   - • Xilinx Power Analyzer uses a netlist as input to provide maximum estimates as well as more accurate typical estimates. For more information on power for the In-System Flash memory, see the Power Management chapter of UG333. 

4. The maximum numbers in this table indicate the minimum current each power rail requires in order for the FPGA to power-on successfully. 5. For information on the power-saving Suspend mode, see XAPP480: _Using Suspend Mode in Spartan-3 Generation FPGAs_ . Suspend mode typically saves 40% total power consumption compared to quiescent current. 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

16 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

## **Single-Ended I/O Standards** 

_Table  13:_ **Recommended Operating Conditions for User I/Os Using Single-Ended Standards** 

|**IOSTANDARD**<br>**Attribute**|**VCCO for Drivers**(2)|**VCCO for Drivers**(2)|**VCCO for Drivers**(2)|**VREF**|**VREF**|**VREF**|**VIL**|**VIH**(3)|
|---|---|---|---|---|---|---|---|---|
||**Min (V)**|**Nom (V)**|**Max (V)**|**Min (V)**|**Nom (V)**|**Max (V)**|**Max (V)**|**Min (V)**|
|LVTTL|3.0|3.3|3.6|VREFis not used for<br>these I/O standards|||0.8|2.0|
|LVCMOS33(4)|3.0|3.3|3.6||||0.8|2.0|
|LVCMOS25(4)(5)|2.3|2.5|2.7||||0.7|1.7|
|LVCMOS18|1.65|1.8|1.95||||0.4|0.8|
|LVCMOS15|1.4|1.5|1.6||||0.4|0.8|
|LVCMOS12|1.1|1.2|1.3||||0.4|0.7|
|PCI33_3(6)|3.0|3.3|3.6||||0.3•VCCO|0.5•VCCO|
|PCI66_3(6)|3.0|3.3|3.6||||0.3•VCCO|0.5•VCCO|
|HSTL_I|1.4|1.5|1.6|0.68|0.75|0.9|VREF– 0.1|VREF+ 0.1|
|HSTL_III|1.4|1.5|1.6|–|0.9|–|VREF– 0.1|VREF+ 0.1|
|HSTL_I_18|1.7|1.8|1.9|0.8|0.9|1.1|VREF– 0.1|VREF+ 0.1|
|HSTL_II_18|1.7|1.8|1.9|–|0.9|–|VREF– 0.1|VREF+ 0.1|
|HSTL_III_18|1.7|1.8|1.9|–|1.1|–|VREF– 0.1|VREF+ 0.1|
|SSTL18_I|1.7|1.8|1.9|0.833|0.900|0.969|VREF– 0.125|VREF+ 0.125|
|SSTL18_II|1.7|1.8|1.9|0.833|0.900|0.969|VREF– 0.125|VREF+ 0.125|
|SSTL2_I|2.3|2.5|2.7|1.13|1.25|1.38|VREF– 0.150|VREF+ 0.150|
|SSTL2_II|2.3|2.5|2.7|1.13|1.25|1.38|VREF– 0.150|VREF+ 0.150|
|SSTL3_I|3.0|3.3|3.6|1.3|1.5|1.7|VREF– 0.2|VREF+ 0.2|
|SSTL3_II|3.0|3.3|3.6|1.3|1.5|1.7|VREF– 0.2|VREF+ 0.2|



## **Notes:** 

1. Descriptions of the symbols used in this table are as follows: VCCO – the supply voltage for output drivers 

   - VREF – the reference voltage for setting the input switching threshold 

   - VIL – the input voltage that indicates a Low logic level 

   - VIH – the input voltage that indicates a High logic level 

2. In general, the VCCO rails supply only output drivers, not input circuits. The exceptions are for LVCMOS25 inputs and for PCI™ I/O standards. 

3. For device operation, the maximum signal voltage (VIH max) can be as high as VIN max. See Table 6. 

4. There is approximately 100 mV of hysteresis on inputs using LVCMOS33 and LVCMOS25 I/O standards. 

5. All Dedicated pins (PROG_B, DONE, SUSPEND, TCK, TDI, TDO, and TMS) draw power from the VCCAUX rail and use the LVCMOS33 standard. The Dual-Purpose configuration pins use the LVCMOS standard before the User mode. When using these pins as part of a standard 2.5V configuration interface, apply 2.5V to the VCCO lines of Banks 0, 1, and 2 at power-on as well as throughout configuration. 

6. For information on PCI IP solutions, see www.xilinx.com/pci. The PCI IOSTANDARD is not supported on input-only pins. The PCIX IOSTANDARD is available and has equivalent characteristics but no PCI-X IP is supported. 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

17 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

## _Table  14:_ **DC Characteristics of User I/Os Using Single-Ended Standards** 

|**IOSTANDARD**<br>**Attribute**|**IOSTANDARD**<br>**Attribute**|**Test**<br>**Conditions**|**Test**<br>**Conditions**|**Logic Level**<br>**Characteristics**|**Logic Level**<br>**Characteristics**|
|---|---|---|---|---|---|
|||**IOL**<br>**(mA)**|**IOH**<br>**(mA)**|**VOL**<br>**Max (V)**|**VOH**<br>**Min (V)**|
|LVTTL(3)|2|2|–2|0.4|2.4|
||4|4|–4|||
||6|6|–6|||
||8|8|–8|||
||12|12|–12|||
||16|16|–16|||
||24|24|–24|||
|LVCMOS33(3)|2|2|–2|0.4|VCCO –0.4|
||4|4|–4|||
||6|6|–6|||
||8|8|–8|||
||12|12|–12|||
||16|16|–16|||
||24(5)|24|–24|||
|LVCMOS25(3)|2|2|–2|0.4|VCCO –0.4|
||4|4|–4|||
||6|6|–6|||
||8|8|–8|||
||12|12|–12|||
||16(5)|16|–16|||
||24(5)|24|–24|||
|LVCMOS18(3)|2|2|–2|0.4|VCCO –0.4|
||4|4|–4|||
||6|6|–6|||
||8|8|–8|||
||12(5)|12|–12|||
||16(5)|16|–16|||
|LVCMOS15(3)|2|2|–2|0.4|VCCO –0.4|
||4|4|–4|||
||6|6|–6|||
||8(5)|8|–8|||
||12(5)|12|–12|||
|LVCMOS12(3)|2|2|–2|0.4|VCCO –0.4|
||4(5)|4|–4|||
||6(5)|6|–6|||
|PCI33_3(4)||1.5|–0.5|10% VCCO|90% VCCO|
|PCI66_3(4)||1.5|–0.5|10% VCCO|90% VCCO|



_Table  14:_ **DC Characteristics of User I/Os Using Single-Ended Standards** _**(Cont’d)**_ 

|**IOSTANDARD**<br>**Attribute**|**Test**<br>**Conditions**|**Test**<br>**Conditions**|**Logic Level**<br>**Characteristics**|**Logic Level**<br>**Characteristics**|
|---|---|---|---|---|
||**IOL**<br>**(mA)**|**IOH**<br>**(mA)**|**VOL**<br>**Max (V)**|**VOH**<br>**Min (V)**|
|HSTL_I(5)|8|–8|0.4|VCCO- 0.4|
|HSTL_III(5)|24|–8|0.4|VCCO- 0.4|
|HSTL_I_18|8|–8|0.4|VCCO- 0.4|
|HSTL_II_18(5)|16|–16|0.4|VCCO- 0.4|
|HSTL_III_18|24|–8|0.4|VCCO- 0.4|
|SSTL18_I|6.7|–6.7|VTT– 0.475|VTT+ 0.475|
|SSTL18_II(5)|13.4|–13.4|VTT– 0.603|VTT+ 0.603|
|SSTL2_I|8.1|–8.1|VTT– 0.61|VTT+ 0.61|
|SSTL2_II(5)|16.2|–16.2|VTT– 0.81|VTT+ 0.81|
|SSTL3_I|8|–8|VTT– 0.6|VTT+ 0.6|
|SSTL3_II|16|–16|VTT– 0.8|VTT+ 0.8|



## **Notes:** 

1. The numbers in this table are based on the conditions set forth in Table 10 and Table 13. 

2. Descriptions of the symbols used in this table are as follows: IOL – the output current condition under which VOL is tested IOH – the output current condition under which VOH is tested VOL – the output voltage that indicates a Low logic level VOH – the output voltage that indicates a High logic level VCCO – the supply voltage for output drivers 

   - VTT – the voltage applied to a resistor termination 

3. For the LVCMOS and LVTTL standards: the same VOL and VOH limits apply for the Fast, Slow and QUIETIO slew attributes. 

4. Tested according to the relevant PCI specifications. For information on PCI IP solutions, see www.xilinx.com/products/ design_resources/conn_central/protocols/pci_pcix.htm. The PCIX IOSTANDARD is available and has equivalent characteristics but no PCI-X IP is supported. 

5. These higher-drive output standards are supported only on FPGA banks 1 and 3. Inputs are unrestricted. See the chapter “Using I/O Resources” in UG331. 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

18 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

## **Differential I/O Standards Differential Input Pairs** 

**==> picture [317 x 173] intentionally omitted <==**

**----- Start of picture text -----**<br>
V<br>INP<br>P Differential<br>Internal N I/O Pair Pins<br>V<br>Logic INN<br>V<br>INN<br>V 50% VID<br>INP<br>V<br>ICM<br>GND level<br>V<br>INP + VINN<br>VICM = Input common mode voltage =<br>2<br>V V<br>ID = Differential input voltage = INP - VINN DS529-3_10_012907<br>**----- End of picture text -----**<br>


_Figure 6:_ **Differential Input Voltages** 

_Table  15:_ **Recommended Operating Conditions for User I/Os Using Differential Signal Standards** 

|**IOSTANDARD Attribute**|**VCCO for Drivers**(1)|**VCCO for Drivers**(1)|**VCCO for Drivers**(1)|**VID**|**VID**|**VID**|**VICM**(2)|**VICM**(2)|**VICM**(2)|
|---|---|---|---|---|---|---|---|---|---|
||**Min (V)**|**Nom (V)**|**Max (V)**|**Min (mV)**|**Nom (mV)**|**Max (mV)**|**Min (V)**|**Nom (V)**|**Max (V)**|
|LVDS_25(3)|2.25|2.5|2.75|100|350|600|0.3|1.25|2.35|
|LVDS_33(3)|3.0|3.3|3.6|100|350|600|0.3|1.25|2.35|
|BLVDS_25(4)|2.25|2.5|2.75|100|300|–|0.3|1.3|2.35|
|MINI_LVDS_25(3)|2.25|2.5|2.75|200|–|600|0.3|1.2|1.95|
|MINI_LVDS_33(3)|3.0|3.3|3.6|200|–|600|0.3|1.2|1.95|
|LVPECL_25(5)|Inputs Only|||100|800|1000|0.3|1.2|1.95|
|LVPECL_33(5)|Inputs Only|||100|800|1000|0.3|1.2|2.8(6)|
|RSDS_25(3)|2.25|2.5|2.75|100|200|–|0.3|1.2|1.5|
|RSDS_33(3)|3.0|3.3|3.6|100|200|–|0.3|1.2|1.5|
|TMDS_33(3,4,7)|3.14|3.3|3.47|150|–|1200|2.7|–|3.23|
|PPDS_25(3)|2.25|2.5|2.75|100|–|400|0.2|–|2.3|
|PPDS_33(3)|3.0|3.3|3.6|100|–|400|0.2|–|2.3|
|DIFF_HSTL_I_18(8)|1.7|1.8|1.9|100|–|–|0.8|–|1.1|
|DIFF_HSTL_II_18(8,9)|1.7|1.8|1.9|100|–|–|0.8|–|1.1|
|DIFF_HSTL_III_18(8)|1.7|1.8|1.9|100|–|–|0.8|–|1.1|
|DIFF_HSTL_I(8)|1.4|1.5|1.6|100|–|–|0.68||0.9|
|DIFF_HSTL_III(8)|1.4|1.5|1.6|100|–|–|–|0.9|–|
|DIFF_SSTL18_I(8)|1.7|1.8|1.9|100|–|–|0.7|–|1.1|
|DIFF_SSTL18_II(8,9)|1.7|1.8|1.9|100|–|–|0.7|–|1.1|
|DIFF_SSTL2_I(8)|2.3|2.5|2.7|100|–|–|1.0|–|1.5|
|DIFF_SSTL2_II(8,9)|2.3|2.5|2.7|100|–|–|1.0|–|1.5|
|DIFF_SSTL3_I(8)|3.0|3.3|3.6|100|–|–|1.1|–|1.9|



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

19 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

_Table  15:_ **Recommended Operating Conditions for User I/Os Using Differential Signal Standards** _**(Cont’d)**_ 

|**IOSTANDARD Attribute**|**VCCO for Drivers**(1)|**VCCO for Drivers**(1)|**VCCO for Drivers**(1)|**VID**|**VID**|**VID**|**VICM**(2)|**VICM**(2)|**VICM**(2)|
|---|---|---|---|---|---|---|---|---|---|
||**Min (V)**|**Nom (V)**|**Max (V)**|**Min (mV)**|**Nom (mV)**|**Max (mV)**|**Min (V)**|**Nom (V)**|**Max (V)**|
|DIFF_SSTL3_II(8)|3.0|3.3|3.6|100|–|–|1.1|–|1.9|



## **Notes:** 

1. The VCCO rails supply only differential output drivers, not input circuits. 

2. VICM must be less than VCCAUX. 

3. These true differential output standards are supported only on FPGA banks 0 and 2. Inputs are unrestricted. See the “Using I/O Resources” chapter in UG331. 

4. See External Termination Requirements for Differential I/O, page 22. 

5. LVPECL is supported on inputs only, not outputs. Requires VCCAUX = 3.3V ± 10%. 

6. LVPECL_33 maximum VICM = VCCAUX – (VID / 2) 

7. Requires VCCAUX = 3.3V ± 10% for inputs. (VCCAUX – 300 mV) ≤ VICM ≤ (VCCAUX – 37 mV) 

8. VREF inputs are used for the DIFF_SSTL and DIFF_HSTL standards. The VREF settings are the same as for the single-ended versions in Table 13. Other differential standards do not use VREF. 

9. These higher-drive output standards are supported only on FPGA banks 1 and 3. Inputs are unrestricted. See the “Using I/O Resources” chapter in UG331. 

## **Differential Output Pairs** 

**==> picture [302 x 215] intentionally omitted <==**

**----- Start of picture text -----**<br>
V<br>OUTP<br>P Differential<br>Internal N I/O Pair Pins<br>V<br>Logic OUTN<br>V<br>V OH<br>OUTN<br>V 50% VOD<br>OUTP<br>V<br>V OL<br>OCM<br>GND level<br>VOUTP + VOUTN<br>VOCM = Output common mode voltage =<br>2<br>VOD = Output differential voltage = VOUTP - VOUTN<br>VOH = Output voltage indicating a High logic level<br>VOL [= Output voltage indicating a Low logic level] DS529-3_11_082810<br>**----- End of picture text -----**<br>


_Figure 7:_ **Differential Output Voltages** 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

20 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

_Table  16:_ **DC Characteristics of User I/Os Using Differential Signal Standards** 

|**IOSTANDARD Attribute**|**VOD**|**VOD**|**VOD**|**VOCM**|**VOCM**|**VOCM**|**VOH**|**VOL**|
|---|---|---|---|---|---|---|---|---|
||**Min (mV)**|**Typ (mV)**|**Max (mV)**|**Min (V)**|**Typ (V)**|**Max (V)**|**Min (V)**|**Max (V)**|
|LVDS_25|247|350|454|1.125|–|1.375|–|–|
|LVDS_33|247|350|454|1.125|–|1.375|–|–|
|BLVDS_25|240|350|460|–|1.30|–|–|–|
|MINI_LVDS_25|300|–|600|1.0|–|1.4|–|–|
|MINI_LVDS_33|300|–|600|1.0|–|1.4|–|–|
|RSDS_25|100|–|400|1.0|–|1.4|–|–|
|RSDS_33|100|–|400|1.0|–|1.4|–|–|
|TMDS_33|400|–|800|VCCO– 0.405|–|VCCO– 0.190|–|–|
|PPDS_25|100|–|400|0.5|0.8|1.4|–|–|
|PPDS_33|100|–|400|0.5|0.8|1.4|–|–|
|DIFF_HSTL_I_18|–|–|–|–|–|–|VCCO– 0.4|0.4|
|DIFF_HSTL_II_18|–|–|–|–|–|–|VCCO– 0.4|0.4|
|DIFF_HSTL_III_18|–|–|–|–|–|–|VCCO– 0.4|0.4|
|DIFF_HSTL_I|–|–|–|–|–|–|VCCO– 0.4|0.4|
|DIFF_HSTL_III|–|–|–|–|–|–|VCCO– 0.4|0.4|
|DIFF_SSTL18_I|–|–|–|–|–|–|VTT+ 0.475|VTT– 0.475|
|DIFF_SSTL18_II|–|–|–|–|–|–|VTT+ 0.475|VTT– 0.475|
|DIFF_SSTL2_I|–|–|–|–|–|–|VTT+ 0.61|VTT– 0.61|
|DIFF_SSTL2_II|–|–|–|–|–|–|VTT+ 0.81|VTT– 0.81|
|DIFF_SSTL3_I|–|–|–|–|–|–|VTT+ 0.6|VTT– 0.6|
|DIFF_SSTL3_II|–|–|–|–|–|–|VTT+ 0.8|VTT– 0.8|



## **Notes:** 

1. The numbers in this table are based on the conditions set forth in Table 10 and Table 15. 

2. See External Termination Requirements for Differential I/O, page 22. 

3. Output voltage measurements for all differential standards are made with a termination resistor (RT) of 100Ω across the N and P pins of the differential signal pair. 

4. At any given time, no more than two of the following differential output standards can be assigned to an I/O bank: LVDS_25, RSDS_25, MINI_LVDS_25, PPDS_25 when VCCO=2.5V, or LVDS_33, RSDS_33, MINI_LVDS_33, TMDS_33, PPDS_33 when VCCO = 3.3V 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

21 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

## **External Termination Requirements for Differential I/O** 

## _**LVDS, RSDS, MINI_LVDS, and PPDS I/O Standards**_ 

**==> picture [399 x 208] intentionally omitted <==**

**----- Start of picture text -----**<br>
Bank 0 and 2 Any Bank<br>Bank 0 Bank 0<br> 1/4th of Bourns No VCCO Restrictions<br>Part Number LVDS_33, LVDS_25,<br>Bank 2 Z0 = 50Ω CAT16-PT4F4 Bank 2 MINI_LVDS_33,<br>MINI_LVDS_25,<br>VCCO = 3.3V VCCO = 2.5V RSDS_33, RSDS_25,<br>PPDS_33, PPDS_25<br>LVDS_33,  LVDS_25,<br>MINI_LVDS_33, MINI_LVDS_25, Z0 = 50Ω 100Ω<br>RSDS_33,  RSDS_25,<br>PPDS_33  PPDS_25<br>DIFF_TERM=No<br>a) Input-only Differential Pairs or Pairs not Using DIFF_TERM=Yes Constraint<br>VCCO = 3.3V VCCO = 2.5V<br>Z0 = 50Ω<br>LVDS_33,  LVDS_25,<br>VCCO = 3.3V VCCO = 2.5V MINI_LVDS_33, MINI_LVDS_25,<br>RSDS_33,  RSDS_25,<br>LVDS_33,  LVDS_25,  PPDS_33  PPDS_25<br>MINI_LVDS_33,RSDS_33,  MINI_LVDS_25,RSDS_25,  Z0 = 50Ω RDT<br>PPDS_33  PPDS_25<br>DIFF_TERM=Yes<br>b) Differential Pairs Using DIFF_TERM=Yes Constraint DS529-3_09_080307<br>Bank 3 Bank 1<br>**----- End of picture text -----**<br>


_Figure 8:_ **External Input Termination for LVDS, RSDS, MINI_LVDS, and PPDS I/O Standards** 

## _**BLVDS_25 I/O Standard**_ 

**==> picture [323 x 126] intentionally omitted <==**

**----- Start of picture text -----**<br>
Any Bank Any Bank<br>Bank 0 Bank 0<br> 1/4th of Bourns  1/4th of Bourns<br>Part Number Part Number<br>Bank 2 CAT16-LV4F12 CAT16-PT4F4 Bank 2<br>VCCO = 2.5V 165Ω Z0 = 50Ω No VCCO Requirement<br>BLVDS_25 140Ω Z0 = 50Ω 100Ω BLVDS_25<br>165Ω<br>DS529-3_07_080307<br>Bank 3 Bank 1 Bank 3 Bank 1<br>**----- End of picture text -----**<br>


_Figure 9:_ **External Output and Input Termination Resistors for BLVDS_25 I/O Standard** 

## _**TMDS_33 I/O Standard**_ 

**==> picture [220 x 119] intentionally omitted <==**

**----- Start of picture text -----**<br>
Bank 0 and 2 Any Bank<br>Bank 0 Bank 0<br>3.3V<br>Bank 2 50Ω 50Ω Bank 2<br>VCCO = 3.3V VCCAUX = 3.3V<br>TMDS_33 TMDS_33<br>DVI/HDMI cable DS529-3_08_020107<br>Bank 3 Bank 1<br>**----- End of picture text -----**<br>


_Figure 10:_ **External Input Resistors Required for TMDS_33 I/O Standard** 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

22 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

## **Device DNA Read Endurance** 

_Table  17:_ **Device DNA Identifier Memory Characteristics** 

|**Symbol**|**Description**|**Minimum**|**Units**|
|---|---|---|---|
|DNA_CYCLES|Number of READ operations or JTAG ISC_DNA read operations. Unaffected by<br>HOLD or SHIFT operations|30,000,000|Read<br>cycles|



## **In-System Flash Memory Data Retention, Program/Write Endurance** 

_Table  18:_ **In-System Flash (ISF) Memory Characteristics** 

|**Symbol**|**Description**|**Minimum**(1)|**Units**|
|---|---|---|---|
|ISF_RETENTION|Data retention|20|Years|
|ISF_ACTIVE|Time that the ISF memory is selected and active. SPI_ACCESS design primitive<br>pins CSB = Low, CLK toggling|2|Years|
|ISF_PAGE_CYCLES|Number of program/erase cycles, per ISF memory page|100,000|Cycles|
|ISF_PAGE_REWRITE|Number of cumulative random (non-sequential) page erase/program operations<br>within a sector before pages must be rewritten|10,000|Cycles|
|ISF_SPR_CYCLES|Number of program/erase cycles for Sector Protection Register|10,000|Cycles|
|ISF_SEC_CYCLES|Number of program cycles for Sector Lockdown Register per sector,<br>user-programmable field in Security Register, and Power-of-2 Page Size|1|Cycle|



## **Notes:** 

1. Minimum value at which functionality is still guaranteed. Do not exceed these values. 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

23 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

## **Switching Characteristics** 

All Spartan-3AN FPGAs ship in two speed grades: -4 and the higher performance -5. Switching characteristics in this document are designated as Preview, Advance, Preliminary, or Production, as shown in Table 19. Each category is defined as follows: 

**Preview** : These specifications are based on estimates only and should not be used for timing analysis. 

**Advance** : These specifications are based on simulations only and are typically available soon after establishing FPGA specifications. Although speed grades with this designation are considered relatively stable and conservative, some under-reporting might still occur. 

**Preliminary** : These specifications are based on complete early silicon characterization. Devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon. The probability of under-reporting preliminary delays is greatly reduced compared to Advance data. 

**Production** : These specifications are approved once enough production silicon of a particular device family member has been characterized to provide full correlation between speed files and devices over numerous production lots. There is no under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest speed grades transition to Production before faster speed grades. 

## **Software Version Requirements** 

Production-quality systems must use FPGA designs compiled using a speed file designated as PRODUCTION status. FPGA designs using a less mature speed file designation should only be used during system prototyping or pre-production qualification. FPGA designs with speed files designated as Preview, Advance, or Preliminary should not be used in a production-quality system. 

Whenever a speed file designation changes, as a device matures toward Production status, rerun the latest Xilinx® ISE® software on the FPGA design to ensure that the FPGA design incorporates the latest timing information and software updates. 

In some cases, a particular family member (and speed grade) is released to Production at a different time than when the speed file is released with the Production label. Any labeling discrepancies are corrected in subsequent speed file releases. See Table 19 for devices that can be considered to have the Production label. 

All parameter limits are representative of worst-case supply voltage and junction temperature conditions. **Unless otherwise noted, the published parameter values apply to all Spartan-3AN devices. AC and DC characteristics are specified using the same numbers for both commercial and industrial grades.** 

Create a Xilinx user account and sign up to receive automatic e-mail notification whenever this data sheet or the associated user guides are updated. 

## • Sign Up for Alerts 

= https://secure.xilinx.com/webreg/register.do?group myprofi le&languageID=1 

Timing parameters and their representative values are selected for inclusion either because they are important as general design requirements or they indicate fundamental device performance characteristics. The Spartan-3AN speed files (v1.41), part of the Xilinx Development Software, are the original source for many but not all of the values. The speed grade designations for these files are shown in Table 19. For more complete, more precise, and worst-case data, use the values reported by the Xilinx static timing analyzer (TRACE in the Xilinx development software) and back-annotated to the simulation netlist. 

_Table  19:_ **Spartan-3AN Family v1.41 Speed Grade Designations** 

|**Device**|**Preview**|**Advance**|**Preliminary**|**Production**|
|---|---|---|---|---|
|XC3S50AN||||-4,-5|
|XC3S200AN||||-4,-5|
|XC3S400AN||||-4,-5|
|XC3S700AN||||-4,-5|
|XC3S1400AN||||-4,-5|



Table 20 provides the recent history of the Spartan-3AN speed files. 

_Table  20:_ **Spartan-3AN Speed File Version History** 

|**Version**|**ISE**<br>**Release**|**Description**|
|---|---|---|
|1.41|ISE 10.1.03|Updated for Spartan-3A family. No<br>change to data for Spartan-3AN family.|
|1.40|ISE 10.1.02|Updated for Spartan-3A family. No<br>change to data for Spartan-3AN family.|
|1.39|ISE 10.1|Updated for Spartan-3A family. No<br>change to data for Spartan-3AN family.|
|1.38|ISE 9.2.03i|Updated to Production. No change to<br>data.|
|1.37|ISE 9.2.01i|Updated pin-to-pin setup and hold<br>times, TMDS output adjustment,<br>multiplier setup/hold times, and block<br>RAM clock width.|
|1.36|ISE 9.2i|Added -5 speed grade, updated to<br>Advance.|
|1.34|ISE 9.1.03i|Updated pin-to-pin timing.|
|1.32|ISE 9.1.01i|Preview speed files for -4 speed grade.|



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

24 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

## **I/O Timing** 

## **Pin-to-Pin Clock-to-Output Times** 

_Table  21:_ **Pin-to-Pin Clock-to-Output Times for the IOB Output Path** 

|**Symbol**|**Description**|**Conditions**|**Device**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|
|||||**-5**|**-4**||
|||||**Max**|**Max**||
|**Clock-to-Output Times**|||||||
|TICKOFDCM|When reading from the Output<br>Flip-Flop (OFF), the time from the<br>active transition on the Global<br>Clock pin to data appearing at the<br>Output pin. The DCM is in use.|LVCMOS25(2), 12 mA<br>output drive, Fast slew<br>rate, with DCM(3)|XC3S50AN|3.18|3.42|ns|
||||XC3S200AN|3.21|3.27|ns|
||||XC3S400AN|2.97|3.33|ns|
||||XC3S700AN|3.39|3.50|ns|
||||XC3S1400AN|3.51|3.99|ns|
|TICKOF|When reading from OFF, the time<br>from the active transition on the<br>Global Clock pin to data appearing<br>at the Output pin. The DCM is not<br>in use.|LVCMOS25(2), 12 mA<br>output drive, Fast slew<br>rate, without DCM|XC3S50AN|4.59|5.02|ns|
||||XC3S200AN|4.88|5.24|ns|
||||XC3S400AN|4.68|5.12|ns|
||||XC3S700AN|4.97|5.34|ns|
||||XC3S1400AN|5.06|5.69|ns|



## **Notes:** 

1. The numbers in this table are tested using the methodology presented in Table 30 and are based on the operating conditions set forth in Table 10 and Table 13. 

2. This clock-to-output time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or a standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. If the former is true, _add_ the appropriate Input adjustment from Table 26. If the latter is true, _add_ the appropriate Output adjustment from Table 29. 

3. DCM output jitter is included in all measurements. 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

25 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

## **Pin-to-Pin Setup and Hold Times** 

_Table  22:_ **Pin-to-Pin Setup and Hold Times for the IOB Input Path (System Synchronous)** 

|**Symbol**|**Description**|**Conditions**|**Device**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|
|||||**-5**|**-4**||
|||||**Min**|**Min**||
|**Setup Times**|||||||
|TPSDCM|When writing to the Input<br>Flip-Flop (IFF), the time from the<br>setup of data at the Input pin to<br>the active transition at a Global<br>Clock pin. The DCM is in use. No<br>Input Delay is programmed.|LVCMOS25(2),<br>IFD_DELAY_VALUE = 0,<br>with DCM(4)|XC3S50AN|2.45|2.68|ns|
||||XC3S200AN|2.59|2.84|ns|
||||XC3S400AN|2.38|2.68|ns|
||||XC3S700AN|2.38|2.57|ns|
||||XC3S1400AN|1.91|2.17|ns|
|TPSFD|When writing to IFF, the time from<br>the setup of data at the Input pin<br>to an active transition at the<br>Global Clock pin. The DCM is not<br>in use. The Input Delay is<br>programmed.|LVCMOS25(2),<br>IFD_DELAY_VALUE = 5,<br>without DCM|XC3S50AN|2.55|2.76|ns|
||||XC3S200AN|2.32|2.76|ns|
||||XC3S400AN|2.21|2.60|ns|
||||XC3S700AN|2.28|2.63|ns|
||||XC3S1400AN|2.33|2.41|ns|
|**Hold Times**|||||||
|TPHDCM|When writing to IFF, the time from<br>the active transition at the Global<br>Clock pin to the point when data<br>must be held at the Input pin. The<br>DCM is in use. No Input Delay is<br>programmed.|LVCMOS25(3),<br>IFD_DELAY_VALUE = 0,<br>with DCM(4)|XC3S50AN|–0.36|–0.36|ns|
||||XC3S200AN|–0.52|–0.52|ns|
||||XC3S400AN|–0.33|–0.29|ns|
||||XC3S700AN|–0.17|–0.12|ns|
||||XC3S1400AN|–0.07|0.00|ns|
|TPHFD|When writing to IFF, the time from<br>the active transition at the Global<br>Clock pin to the point when data<br>must be held at the Input pin. The<br>DCM is not in use. The Input<br>Delay is programmed.|LVCMOS25(3),<br>IFD_DELAY_VALUE = 5,<br>without DCM|XC3S50AN|–0.63|–0.58|ns|
||||XC3S200AN|–0.56|–0.56|ns|
||||XC3S400AN|–0.42|–0.42|ns|
||||XC3S700AN|–0.80|–0.75|ns|
||||XC3S1400AN|–0.69|–0.69|ns|



## **Notes:** 

1. The numbers in this table are tested using the methodology presented in Table 30 and are based on the operating conditions set forth in Table 10 and Table 13. 

2. This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data Input. If this is true of the Global Clock Input, subtract the appropriate adjustment from Table 26. If this is true of the data Input, add the appropriate Input adjustment from the same table. 

3. This hold time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data Input. If this is true of the Global Clock Input, add the appropriate Input adjustment from Table 26. If this is true of the data Input, subtract the appropriate Input adjustment from the same table. When the hold time is negative, it is possible to change the data before the clock’s active edge. 

4. DCM output jitter is included in all measurements. 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

26 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

## **Input Setup and Hold Times** 

_Table  23:_ **Setup and Hold Times for the IOB Input Path** 

|**Symbol**|**Description**|**Conditions**|**IFD_**<br>**DELAY_**<br>**VALUE**|**Device**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|---|
||||||**-5**|**-4**||
||||||**Min**|**Min**||
|**Setup Times**||||||||
|TIOPICK|Time from the setup of data at the<br>Input pin to the active transition at the<br>ICLK input of the Input Flip-Flop (IFF).<br>No Input Delay is programmed.|LVCMOS25(2)|0|XC3S50AN|1.56|1.58|ns|
|||||XC3S200AN|1.71|1.81|ns|
|||||XC3S400AN|1.30|1.51|ns|
|||||XC3S700AN|1.34|1.51|ns|
|||||XC3S1400AN|1.36|1.74|ns|
|TIOPICKD|Time from the setup of data at the<br>Input pin to the active transition at the<br>ICLK input of the Input Flip-Flop (IFF).<br>The Input Delay is programmed.|LVCMOS25(2)|1|XC3S50AN|2.16|2.18|ns|
||||2||3.10|3.12|ns|
||||3||3.51|3.76|ns|
||||4||4.04|4.32|ns|
||||5||3.88|4.24|ns|
||||6||4.72|5.09|ns|
||||7||5.47|5.94|ns|
||||8||5.97|6.52|ns|
||||1|XC3S200AN|2.05|2.20|ns|
||||2||2.72|2.93|ns|
||||3||3.38|3.78|ns|
||||4||3.88|4.37|ns|
||||5||3.69|4.20|ns|
||||6||4.56|5.23|ns|
||||7||5.34|6.11|ns|
||||8||5.85|6.71|ns|
||||1|XC3S400AN|1.79|2.02|ns|
||||2||2.43|2.67|ns|
||||3||3.02|3.43|ns|
||||4||3.49|3.96|ns|
||||5||3.41|3.95|ns|
||||6||4.20|4.81|ns|
||||7||4.96|5.66|ns|
||||8||5.44|6.19|ns|



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

27 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

_Table  23:_ **Setup and Hold Times for the IOB Input Path** _**(Cont’d)**_ 

|**Symbol**|**Description**|**Conditions**|**IFD_**<br>**DELAY_**<br>**VALUE**|**Device**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|---|
||||||**-5**|**-4**||
||||||**Min**|**Min**||
|TIOPICKD|Time from the setup of data at the<br>Input pin to the active transition at the<br>ICLK input of the Input Flip-Flop (IFF).<br>The Input Delay is programmed.|LVCMOS25(2)|1|XC3S700AN|1.82|1.95|ns|
||||2||2.62|2.83|ns|
||||3||3.32|3.72|ns|
||||4||3.83|4.31|ns|
||||5||3.69|4.14|ns|
||||6||4.60|5.19|ns|
||||7||5.39|6.10|ns|
||||8||5.92|6.73|ns|
||||1|XC3S1400AN|1.79|2.17|ns|
||||2||2.55|2.92|ns|
||||3||3.38|3.76|ns|
||||4||3.75|4.32|ns|
||||5||3.81|4.19|ns|
||||6||4.39|5.09|ns|
||||7||5.16|5.98|ns|
||||8||5.69|6.57|ns|
|**Hold Times**||||||||
|TIOICKP|Time from the active transition at the<br>ICLK input of the Input Flip-Flop (IFF)<br>to the point where data must be held<br>at the Input pin. No Input Delay is<br>programmed.|LVCMOS25(3)|0|XC3S50AN|–0.66|–0.64|ns|
|||||XC3S200AN|–0.85|–0.65|ns|
|||||XC3S400AN|–0.42|–0.42|ns|
|||||XC3S700AN|–0.81|–0.67|ns|
|||||XC3S1400AN|–0.71|–0.71|ns|
|TIOICKPD|Time from the active transition at the<br>ICLK input of the Input Flip-Flop (IFF)<br>to the point where data must be held<br>at the Input pin. The Input Delay is<br>programmed.|LVCMOS25(3)|1|XC3S50AN|–0.88|–0.88|ns|
||||2||–1.33|–1.33|ns|
||||3||–2.05|–2.05|ns|
||||4||–2.43|–2.43|ns|
||||5||–2.34|–2.34|ns|
||||6||–2.81|–2.81|ns|
||||7||–3.03|–3.03|ns|
||||8||–3.83|–3.57|ns|
||||1|XC3S200AN|–1.51|–1.51|ns|
||||2||–2.09|–2.09|ns|
||||3||–2.40|–2.40|ns|
||||4||–2.68|–2.68|ns|
||||5||–2.56|–2.56|ns|
||||6||–2.99|–2.99|ns|
||||7||–3.29|–3.29|ns|
||||8||–3.61|–3.61|ns|



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

28 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

_Table  23:_ **Setup and Hold Times for the IOB Input Path** _**(Cont’d)**_ 

|**Symbol**|**Description**|**Conditions**|**IFD_**<br>**DELAY_**<br>**VALUE**|**Device**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|---|
||||||**-5**|**-4**||
||||||**Min**|**Min**||
|TIOICKPD|Time from the active transition at the<br>ICLK input of the Input Flip-Flop (IFF)<br>to the point where data must be held<br>at the Input pin. The Input Delay is<br>programmed.|LVCMOS25(3)|1|XC3S400AN|–1.12|–1.12|ns|
||||2||–1.70|–1.70|ns|
||||3||–2.08|–2.08|ns|
||||4||–2.38|–2.38|ns|
||||5||–2.23|–2.23|ns|
||||6||–2.69|–2.69|ns|
||||7||–3.08|–3.08|ns|
||||8||–3.35|–3.35|ns|
||||1|XC3S700AN|–1.67|–1.67|ns|
||||2||–2.27|–2.27|ns|
||||3||–2.59|–2.59|ns|
||||4||–2.92|–2.92|ns|
||||5||–2.89|–2.89|ns|
||||6||–3.22|–3.22|ns|
||||7||–3.52|–3.52|ns|
||||8||–3.81|–3.81|ns|
||||1|XC3S1400AN|–1.60|–1.60|ns|
||||2||–2.06|–2.06|ns|
||||3||–2.46|–2.46|ns|
||||4||–2.86|–2.86|ns|
||||5||–2.88|–2.88|ns|
||||6||–3.24|–3.24|ns|
||||7||–3.55|–3.55|ns|
||||8||–3.89|–3.89|ns|
|**Set/Reset Pulse Width**||||||||
|TRPW_IOB|Minimum pulse width to SR control<br>input on IOB|–|–|All|1.33|1.61|ns|



## **Notes:** 

1. The numbers in this table are tested using the methodology presented in Table 30 and are based on the operating conditions set forth in Table 10 and Table 13. 

2. This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, add the appropriate Input adjustment from Table 26. 

3. These hold times require adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, subtract the appropriate Input adjustment from Table 26. When the hold time is negative, it is possible to change the data before the clock’s active edge. 

_Table  24:_ **Sample Window (Source Synchronous)** 

|**Symbol**|**Description**|**Maximum**|**Units**|
|---|---|---|---|
|TSAMP|Setup and hold capture<br>window of an IOB flip-flop.|The input capture sample window value is highly specific to a particular application, device,<br>package, I/O standard, I/O placement, DCM usage, and clock buffer.|ps|



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

29 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

## **Input Propagation Times** 

_Table  25:_ **Propagation Times for the IOB Input Path** 

|**Symbol**|**Description**|**Conditions**|**DELAY_VALUE**|**Device**|**Speed**<br>**Grade**|**Speed**<br>**Grade**|**Units**|
|---|---|---|---|---|---|---|---|
||||||**-5**|**-4**||
||||||**Max**|**Max**||
|**Propagation Times**||||||||
|TIOPI|The time it takes for data to travel<br>from the Input pin to the I output<br>with no input delay programmed|LVCMOS25(2)|IBUF_DELAY_VALUE=0|XC3S50AN|1.04|1.12|ns|
|||||XC3S200AN|0.87|0.87|ns|
|||||XC3S400AN|0.65|0.72|ns|
|||||XC3S700AN|0.92|0.92|ns|
|||||XC3S1400AN|0.96|1.21|ns|
|TIOPID|The time it takes for data to travel<br>from the Input pin to the I output<br>with the input delay programmed|LVCMOS25(2)|1|XC3S50AN|1.79|2.07|ns|
||||2||2.13|2.46|ns|
||||3||2.36|2.71|ns|
||||4||2.88|3.21|ns|
||||5||3.11|3.46|ns|
||||6||3.45|3.84|ns|
||||7||3.75|4.19|ns|
||||8||4.00|4.47|ns|
||||9||3.61|4.11|ns|
||||10||3.95|4.50|ns|
||||11||4.18|4.67|ns|
||||12||4.75|5.20|ns|
||||13||4.98|5.44|ns|
||||14||5.31|5.95|ns|
||||15||5.62|6.28|ns|
||||16||5.86|6.57|ns|
||||1|XC3S200AN|1.57|1.65|ns|
||||2||1.87|1.97|ns|
||||3||2.16|2.33|ns|
||||4||2.68|2.96|ns|
||||5||2.87|3.19|ns|
||||6||3.20|3.60|ns|
||||7||3.57|4.02|ns|
||||8||3.79|4.26|ns|
||||9||3.42|3.86|ns|
||||10||3.79|4.25|ns|
||||11||4.02|4.55|ns|
||||12||4.62|5.24|ns|
||||13||4.86|5.53|ns|
||||14||5.18|5.94|ns|



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

30 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

_Table  25:_ **Propagation Times for the IOB Input Path** _**(Cont’d)**_ 

|**Symbol**|**Description**|**Conditions**|**DELAY_VALUE**|**Device**|**Speed**<br>**Grade**|**Speed**<br>**Grade**|**Units**|
|---|---|---|---|---|---|---|---|
||||||**-5**|**-4**||
||||||**Max**|**Max**||
|TIOPID|The time it takes for data to travel<br>from the Input pin to the I output<br>with the input delay programmed|LVCMOS25(2)|15|XC3S200AN|5.43|6.24|ns|
||||16||5.75|6.59|ns|
||||1|XC3S400AN|1.32|1.43|ns|
||||2||1.67|1.83|ns|
||||3||1.90|2.07|ns|
||||4||2.33|2.52|ns|
||||5||2.60|2.91|ns|
||||6||2.94|3.20|ns|
||||7||3.23|3.51|ns|
||||8||3.50|3.85|ns|
||||9||3.18|3.55|ns|
||||10||3.53|3.95|ns|
||||11||3.76|4.20|ns|
||||12||4.26|4.67|ns|
||||13||4.51|4.97|ns|
||||14||4.85|5.32|ns|
||||15||5.14|5.64|ns|
||||16||5.40|5.95|ns|
||||1|XC3S700AN|1.84|1.87|ns|
||||2||2.20|2.27|ns|
||||3||2.46|2.60|ns|
||||4||2.93|3.15|ns|
||||5||3.21|3.45|ns|
||||6||3.54|3.80|ns|
||||7||3.86|4.16|ns|
||||8||4.13|4.48|ns|
||||9||3.82|4.19|ns|
||||10||4.17|4.58|ns|
||||11||4.43|4.89|ns|
||||12||4.95|5.49|ns|
||||13||5.22|5.83|ns|
||||14||5.57|6.21|ns|
||||15||5.89|6.55|ns|
||||16||6.16|6.89|ns|
||||1|XC3S1400AN|1.95|2.18|ns|
||||2||2.29|2.59|ns|
||||3||2.54|2.84|ns|
||||4||2.96|3.30|ns|



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

31 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

_Table  25:_ **Propagation Times for the IOB Input Path** _**(Cont’d)**_ 

|**Symbol**|**Description**|**Conditions**|**DELAY_VALUE**|**Device**|**Speed**<br>**Grade**|**Speed**<br>**Grade**|**Units**|
|---|---|---|---|---|---|---|---|
||||||**-5**|**-4**||
||||||**Max**|**Max**||
|TIOPID|The time it takes for data to travel<br>from the Input pin to the I output<br>with the input delay programmed|LVCMOS25(2)|5|XC3S1400AN|3.17|3.52|ns|
||||6||3.52|3.92|ns|
||||7||3.82|4.18|ns|
||||8||4.10|4.57|ns|
||||9||3.84|4.31|ns|
||||10||4.20|4.79|ns|
||||11||4.46|5.06|ns|
||||12||4.87|5.51|ns|
||||13||5.07|5.73|ns|
||||14||5.43|6.08|ns|
||||15||5.73|6.33|ns|
||||16||6.01|6.77|ns|
|TIOPLI|The time it takes for data to travel<br>from the Input pin through the IFF<br>latch to the I output with no input<br>delay programmed|LVCMOS25(2)|IFD_DELAY_VALUE=0|XC3S50AN|1.70|1.81|ns|
|||||XC3S200AN|1.85|2.04|ns|
|||||XC3S400AN|1.44|1.74|ns|
|||||XC3S700AN|1.48|1.74|ns|
|||||XC3S1400AN|1.50|1.97|ns|



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

32 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

_Table  25:_ **Propagation Times for the IOB Input Path** _**(Cont’d)**_ 

|**Symbol**|**Description**|**Conditions**|**DELAY_VALUE**|**Device**|**Speed**<br>**Grade**|**Speed**<br>**Grade**|**Units**|
|---|---|---|---|---|---|---|---|
||||||**-5**|**-4**||
||||||**Max**|**Max**||
|TIOPLID|The time it takes for data to travel<br>from the Input pin through the IFF<br>latch to the I output with the input<br>delay programmed|LVCMOS25(2)|1|XC3S50AN|2.30|2.41|ns|
||||2||3.24|3.35|ns|
||||3||3.65|3.98|ns|
||||4||4.18|4.55|ns|
||||5||4.02|4.47|ns|
||||6||4.86|5.32|ns|
||||7||5.61|6.17|ns|
||||8||6.11|6.75|ns|
||||1|XC3S200AN|2.19|2.43|ns|
||||2||2.86|3.16|ns|
||||3||3.52|4.01|ns|
||||4||4.02|4.60|ns|
||||5||3.83|4.43|ns|
||||6||4.70|5.46|ns|
||||7||5.48|6.33|ns|
||||8||5.99|6.94|ns|
||||1|XC3S400AN|1.93|2.25|ns|
||||2||2.57|2.90|ns|
||||3||3.16|3.66|ns|
||||4||3.63|4.19|ns|
||||5||3.55|4.18|ns|
||||6||4.34|5.03|ns|
||||7||5.09|5.88|ns|
||||8||5.58|6.42|ns|
||||1|XC3S700AN|1.96|2.18|ns|
||||2||2.76|3.06|ns|
||||3||3.45|3.95|ns|
||||4||3.97|4.54|ns|
||||5||3.83|4.37|ns|
||||6||4.74|5.42|ns|
||||7||5.53|6.33|ns|
||||8||6.06|6.96|ns|



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

33 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

_Table  25:_ **Propagation Times for the IOB Input Path** _**(Cont’d)**_ 

|**Symbol**|**Description**|**Conditions**|**DELAY_VALUE**|**Device**|**Speed**<br>**Grade**|**Speed**<br>**Grade**|**Units**|
|---|---|---|---|---|---|---|---|
||||||**-5**|**-4**||
||||||**Max**|**Max**||
|TIOPLID|The time it takes for data to travel<br>from the Input pin through the IFF<br>latch to the I output with the input<br>delay programmed|LVCMOS25(2)|1|XC3S1400AN|1.93|2.40|ns|
||||2||2.69|3.15|ns|
||||3||3.52|3.99|ns|
||||4||3.89|4.55|ns|
||||5||3.95|4.42|ns|
||||6||4.53|5.32|ns|
||||7||5.30|6.21|ns|
||||8||5.83|6.80|ns|



## **Notes:** 

1. The numbers in this table are tested using the methodology presented in Table 30 and are based on the operating conditions set forth in Table 10 and Table 13. 

2. This propagation time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. When this is true, _add_ the appropriate Input adjustment from Table 26. 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

34 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

## **Input Timing Adjustments** 

_Table  26:_ **Input Timing Adjustments by IOSTANDARD** 

|**Convert Input Time from**<br>**LVCMOS25 to the**<br>**Following Signal Standard**<br>**(IOSTANDARD)**|**Add the**<br>**Adjustment Below**|**Add the**<br>**Adjustment Below**|**Units**|
|---|---|---|---|
||**Speed Grade**|||
||**-5**|**-4**||
|**Single-Ended Standards**||||
|LVTTL|0.62|0.62|ns|
|LVCMOS33|0.54|0.54|ns|
|LVCMOS25|0|0|ns|
|LVCMOS18|0.83|0.83|ns|
|LVCMOS15|0.60|0.60|ns|
|LVCMOS12|0.31|0.31|ns|
|PCI33_3|0.41|0.41|ns|
|PCI66_3|0.41|0.41|ns|
|HSTL_I|0.72|0.72|ns|
|HSTL_III|0.77|0.77|ns|
|HSTL_I_18|0.69|0.69|ns|
|HSTL_II_18|0.69|0.69|ns|
|HSTL_III_18|0.79|0.79|ns|
|SSTL18_I|0.71|0.71|ns|
|SSTL18_II|0.71|0.71|ns|
|SSTL2_I|0.68|0.68|ns|
|SSTL2_II|0.68|0.68|ns|
|SSTL3_I|0.78|0.78|ns|
|SSTL3_II|0.78|0.78|ns|



_Table  26:_ **Input Timing Adjustments by IOSTANDARD** 

|**Convert Input Time from**<br>**LVCMOS25 to the**<br>**Following Signal Standard**<br>**(IOSTANDARD)**|**Add the**<br>**Adjustment Below**|**Add the**<br>**Adjustment Below**|**Units**|
|---|---|---|---|
||**Speed Grade**|||
||**-5**|**-4**||
|**Differential Standards**||||
|LVDS_25|0.76|0.76|ns|
|LVDS_33|0.79|0.79|ns|
|BLVDS_25|0.79|0.79|ns|
|MINI_LVDS_25|0.78|0.78|ns|
|MINI_LVDS_33|0.79|0.79|ns|
|LVPECL_25|0.78|0.78|ns|
|LVPECL_33|0.79|0.79|ns|
|RSDS_25|0.79|0.79|ns|
|RSDS_33|0.77|0.77|ns|
|TMDS_33|0.79|0.79|ns|
|PPDS_25|0.79|0.79|ns|
|PPDS_33|0.79|0.79|ns|
|DIFF_HSTL_I_18|0.74|0.74|ns|
|DIFF_HSTL_II_18|0.72|0.72|ns|
|DIFF_HSTL_III_18|1.05|1.05|ns|
|DIFF_HSTL_I|0.72|0.72|ns|
|DIFF_HSTL_III|1.05|1.05|ns|
|DIFF_SSTL18_I|0.71|0.71|ns|
|DIFF_SSTL18_II|0.71|0.71|ns|
|DIFF_SSTL2_I|0.74|0.74|ns|
|DIFF_SSTL2_II|0.75|0.75|ns|
|DIFF_SSTL3_I|1.06|1.06|ns|
|DIFF_SSTL3_II|1.06|1.06|ns|



## **Notes:** 

1. The numbers in this table are tested using the methodology presented in Table 30 and are based on the operating conditions set forth in Table 10, Table 13, and Table 15. 

2. These adjustments are used to convert input path times originally specified for the LVCMOS25 standard to times that correspond to other signal standards. 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

35 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

## **Output Propagation Times** 

_Table  27:_ **Timing for the IOB Output Path** 

|**Symbol**|**Description**|**Conditions**|**Device**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|
|||||**-5**|**-4**||
|||||**Max**|**Max**||
|**Clock-to-Output Times**|||||||
|TIOCKP|When reading from the Output<br>Flip-Flop (OFF), the time from the<br>active transition at the OCLK input to<br>data appearing at the Output pin|LVCMOS25(2), 12 mA output<br>drive, Fast slew rate|All|2.87|3.13|ns|
|**Propagation Times**|||||||
|TIOOP|The time it takes for data to travel from<br>the IOB’s O input to the Output pin|LVCMOS25(2), 12 mA output<br>drive, Fast slew rate|All|2.78|2.91|ns|
|**Set/Reset Times**|||||||
|TIOSRP|Time from asserting the OFF’s SR<br>input to setting/resetting data at the<br>Output pin|LVCMOS25(2), 12 mA output<br>drive, Fast slew rate|All|3.63|3.89|ns|
|TIOGSRQ|Time from asserting the Global Set<br>Reset (GSR) input on the<br>STARTUP_SPARTAN3A primitive to<br>setting/resetting data at the Output pin|||8.62|9.65|ns|



## **Notes:** 

1. The numbers in this table are tested using the methodology presented in Table 30 and are based on the operating conditions set forth in Table 10 and Table 13. 

2. This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. When this is true, _add_ the appropriate Output adjustment from Table 29. 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

36 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

## **Three-State Output Propagation Times** 

_Table  28:_ **Timing for the IOB Three-State Path** 

|**Symbol**|**Description**|**Conditions**|**Device**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|
|||||**-5**|**-4**||
|||||**Max**|**Max**||
|**Synchronous Output Enable/Disable Times**|||||||
|TIOCKHZ|Time from the active transition at the OTCLK<br>input of the Three-state Flip-Flop (TFF) to when<br>the Output pin enters the high-impedance state|LVCMOS25, 12 mA<br>output drive, Fast slew<br>rate|All|0.63|0.76|ns|
|TIOCKON(2)|Time from the active transition at TFF’s OTCLK<br>input to when the Output pin drives valid data||All|2.80|3.06|ns|
|**Asynchronous Output Enable/Disable Times**|||||||
|TGTS|Time from asserting the Global Three State<br>(GTS) input on the STARTUP_SPARTAN3A<br>primitive to when the Output pin enters the<br>high-impedance state|LVCMOS25, 12 mA<br>output drive, Fast slew<br>rate|All|9.47|10.36|ns|
|**Set/Reset Times**|||||||
|TIOSRHZ|Time from asserting TFF’s SR input to when the<br>Output pin enters a high-impedance state|LVCMOS25, 12 mA<br>output drive, Fast slew<br>rate|All|1.61|1.86|ns|
|TIOSRON(2)|Time from asserting TFF’s SR input at TFF to<br>when the Output pin drives valid data||All|3.57|3.82|ns|



## **Notes:** 

1. The numbers in this table are tested using the methodology presented in Table 30 and are based on the operating conditions set forth in Table 10 and Table 13. 

2. This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. When this is true, _add_ the appropriate Output adjustment from Table 29. 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

37 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

## **Output Timing Adjustments** 

_Table  29:_ **Output Timing Adjustments for IOB** 

|**Convert Output Time from**<br>**LVCMOS25 with 12 mA Drive**<br>**and Fast Slew Rate to the**<br>**Following Signal Standard**<br>**(IOSTANDARD)**|**Convert Output Time from**<br>**LVCMOS25 with 12 mA Drive**<br>**and Fast Slew Rate to the**<br>**Following Signal Standard**<br>**(IOSTANDARD)**|**Convert Output Time from**<br>**LVCMOS25 with 12 mA Drive**<br>**and Fast Slew Rate to the**<br>**Following Signal Standard**<br>**(IOSTANDARD)**|**Add the**<br>**Adjustment Below**|**Add the**<br>**Adjustment Below**|**Units**|
|---|---|---|---|---|---|
||||**Speed Grade**|||
||||**-5**|**-4**||
|**Single-Ended**|**Standards**|||||
|LVTTL|Slow|2 mA|5.58|5.58|ns|
|||4 mA|3.16|3.16|ns|
|||6 mA|3.17|3.17|ns|
|||8 mA|2.09|2.09|ns|
|||12 mA|1.62|1.62|ns|
|||16 mA|1.24|1.24|ns|
|||24 mA|2.74(3)|2.74(3)|ns|
||Fast|2 mA|3.03|3.03|ns|
|||4 mA|1.71|1.71|ns|
|||6 mA|1.71|1.71|ns|
|||8 mA|0.53|0.53|ns|
|||12 mA|0.53|0.53|ns|
|||16 mA|0.59|0.59|ns|
|||24 mA|0.60|0.60|ns|
||QuietIO|2 mA|27.67|27.67|ns|
|||4 mA|27.67|27.67|ns|
|||6 mA|27.67|27.67|ns|
|||8 mA|16.71|16.71|ns|
|||12 mA|16.67|16.67|ns|
|||16 mA|16.22|16.22|ns|
|||24 mA|12.11|12.11|ns|



_Table  29:_ **Output Timing Adjustments for IOB** _**(Cont’d)**_ 

|**Convert Output Time from**<br>**LVCMOS25 with 12 mA Drive**<br>**and Fast Slew Rate to the**<br>**Following Signal Standard**<br>**(IOSTANDARD)**|**Convert Output Time from**<br>**LVCMOS25 with 12 mA Drive**<br>**and Fast Slew Rate to the**<br>**Following Signal Standard**<br>**(IOSTANDARD)**|**Convert Output Time from**<br>**LVCMOS25 with 12 mA Drive**<br>**and Fast Slew Rate to the**<br>**Following Signal Standard**<br>**(IOSTANDARD)**|**Add the**<br>**Adjustment Below**|**Add the**<br>**Adjustment Below**|**Units**|
|---|---|---|---|---|---|
||||**Speed Grade**|||
||||**-5**|**-4**||
|LVCMOS33|Slow|2 mA|5.58|5.58|ns|
|||4 mA|3.17|3.17|ns|
|||6 mA|3.17|3.17|ns|
|||8 mA|2.09|2.09|ns|
|||12 mA|1.24|1.24|ns|
|||16 mA|1.15|1.15|ns|
|||24 mA|2.55(3)|2.55(3)|ns|
||Fast|2 mA|3.02|3.02|ns|
|||4 mA|1.71|1.71|ns|
|||6 mA|1.72|1.72|ns|
|||8 mA|0.53|0.53|ns|
|||12 mA|0.59|0.59|ns|
|||16 mA|0.59|0.59|ns|
|||24 mA|0.51|0.51|ns|
||QuietIO|2 mA|27.67|27.67|ns|
|||4 mA|27.67|27.67|ns|
|||6 mA|27.67|27.67|ns|
|||8 mA|16.71|16.71|ns|
|||12 mA|16.29|16.29|ns|
|||16 mA|16.18|16.18|ns|
|||24 mA|12.11|12.11|ns|



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

38 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

_Table  29:_ **Output Timing Adjustments for IOB** _**(Cont’d)**_ 

|**Convert Output Time from**<br>**LVCMOS25 with 12 mA Drive**<br>**and Fast Slew Rate to the**<br>**Following Signal Standard**<br>**(IOSTANDARD)**|**Convert Output Time from**<br>**LVCMOS25 with 12 mA Drive**<br>**and Fast Slew Rate to the**<br>**Following Signal Standard**<br>**(IOSTANDARD)**|**Convert Output Time from**<br>**LVCMOS25 with 12 mA Drive**<br>**and Fast Slew Rate to the**<br>**Following Signal Standard**<br>**(IOSTANDARD)**|**Add the**<br>**Adjustment Below**|**Add the**<br>**Adjustment Below**|**Units**|
|---|---|---|---|---|---|
||||**Speed Grade**|||
||||**-5**|**-4**||
|LVCMOS25|Slow|2 mA|5.33|5.33|ns|
|||4 mA|2.81|2.81|ns|
|||6 mA|2.82|2.82|ns|
|||8 mA|1.14|1.14|ns|
|||12 mA|1.10|1.10|ns|
|||16 mA|0.83|0.83|ns|
|||24 mA|2.26(3)|2.26(3)|ns|
||Fast|2 mA|4.36|4.36|ns|
|||4 mA|1.76|1.76|ns|
|||6 mA|1.25|1.25|ns|
|||8 mA|0.38|0.38|ns|
|||12 mA|0|0|ns|
|||16 mA|0.01|0.01|ns|
|||24 mA|0.01|0.01|ns|
||QuietIO|2 mA|25.92|25.92|ns|
|||4 mA|25.92|25.92|ns|
|||6 mA|25.92|25.92|ns|
|||8 mA|15.57|15.57|ns|
|||12 mA|15.59|15.59|ns|
|||16 mA|14.27|14.27|ns|
|||24 mA|11.37|11.37|ns|



_Table  29:_ **Output Timing Adjustments for IOB** _**(Cont’d)**_ 

|**Convert Output Time from**<br>**LVCMOS25 with 12 mA Drive**<br>**and Fast Slew Rate to the**<br>**Following Signal Standard**<br>**(IOSTANDARD)**|**Convert Output Time from**<br>**LVCMOS25 with 12 mA Drive**<br>**and Fast Slew Rate to the**<br>**Following Signal Standard**<br>**(IOSTANDARD)**|**Convert Output Time from**<br>**LVCMOS25 with 12 mA Drive**<br>**and Fast Slew Rate to the**<br>**Following Signal Standard**<br>**(IOSTANDARD)**|**Add the**<br>**Adjustment Below**|**Add the**<br>**Adjustment Below**|**Units**|
|---|---|---|---|---|---|
||||**Speed Grade**|||
||||**-5**|**-4**||
|LVCMOS18|Slow|2 mA|4.48|4.48|ns|
|||4 mA|3.69|3.69|ns|
|||6 mA|2.91|2.91|ns|
|||8 mA|1.99|1.99|ns|
|||12 mA|1.57|1.57|ns|
|||16 mA|1.19|1.19|ns|
||Fast|2 mA|3.96|3.96|ns|
|||4 mA|2.57|2.57|ns|
|||6 mA|1.90|1.90|ns|
|||8 mA|1.06|1.06|ns|
|||12 mA|0.83|0.83|ns|
|||16 mA|0.63|0.63|ns|
||QuietIO|2 mA|24.97|24.97|ns|
|||4 mA|24.97|24.97|ns|
|||6 mA|24.08|24.08|ns|
|||8 mA|16.43|16.43|ns|
|||12 mA|14.52|14.52|ns|
|||16 mA|13.41|13.41|ns|
|LVCMOS15|Slow|2 mA|5.82|5.82|ns|
|||4 mA|3.97|3.97|ns|
|||6 mA|3.21|3.21|ns|
|||8 mA|2.53|2.53|ns|
|||12 mA|2.06|2.06|ns|
||Fast|2 mA|5.23|5.23|ns|
|||4 mA|3.05|3.05|ns|
|||6 mA|1.95|1.95|ns|
|||8 mA|1.60|1.60|ns|
|||12 mA|1.30|1.30|ns|
||QuietIO|2 mA|34.11|34.11|ns|
|||4 mA|25.66|25.66|ns|
|||6 mA|24.64|24.64|ns|
|||8 mA|22.06|22.06|ns|
|||12 mA|20.64|20.64|ns|



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

39 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

_Table  29:_ **Output Timing Adjustments for IOB** _**(Cont’d)**_ 

|**Convert Output Time from**<br>**LVCMOS25 with 12 mA Drive**<br>**and Fast Slew Rate to the**<br>**Following Signal Standard**<br>**(IOSTANDARD)**|**Convert Output Time from**<br>**LVCMOS25 with 12 mA Drive**<br>**and Fast Slew Rate to the**<br>**Following Signal Standard**<br>**(IOSTANDARD)**|**Convert Output Time from**<br>**LVCMOS25 with 12 mA Drive**<br>**and Fast Slew Rate to the**<br>**Following Signal Standard**<br>**(IOSTANDARD)**|**Add the**<br>**Adjustment Below**|**Add the**<br>**Adjustment Below**|**Units**|
|---|---|---|---|---|---|
||||**Speed Grade**|||
||||**-5**|**-4**||
|LVCMOS12|Slow|2 mA|7.14|7.14|ns|
|||4 mA|4.87|4.87|ns|
|||6 mA|5.67|5.67|ns|
||Fast|2 mA|6.77|6.77|ns|
|||4 mA|5.02|5.02|ns|
|||6 mA|4.09|4.09|ns|
||QuietIO|2 mA|50.76|50.76|ns|
|||4 mA|43.17|43.17|ns|
|||6 mA|37.31|37.31|ns|
|PCI33_3|||0.34|0.34|ns|
|PCI66_3|||0.34|0.34|ns|
|HSTL_I|||0.78|0.78|ns|
|HSTL_III|||1.16|1.16|ns|
|HSTL_I_18|||0.35|0.35|ns|
|HSTL_II_18|||0.30|0.30|ns|
|HSTL_III_18|||0.47|0.47|ns|
|SSTL18_I|||0.40|0.40|ns|
|SSTL18_II|||0.30|0.30|ns|
|SSTL2_I|||0|0|ns|
|SSTL2_II|||–0.05|–0.05|ns|
|SSTL3_I|||0|0|ns|
|SSTL3_II|||0.17|0.17|ns|



_Table  29:_ **Output Timing Adjustments for IOB** _**(Cont’d)**_ 

|**Convert Output Time from**<br>**LVCMOS25 with 12 mA Drive**<br>**and Fast Slew Rate to the**<br>**Following Signal Standard**<br>**(IOSTANDARD)**|**Add the**<br>**Adjustment Below**|**Add the**<br>**Adjustment Below**|**Units**|
|---|---|---|---|
||**Speed Grade**|||
||**-5**|**-4**||
|**Differential Standards**||||
|LVDS_25|1.16|1.16|ns|
|LVDS_33|0.46|0.46|ns|
|BLVDS_25|0.11|0.11|ns|
|MINI_LVDS_25|0.75|0.75|ns|
|MINI_LVDS_33|0.40|0.40|ns|
|LVPECL_25|Input Only|||
|LVPECL_33||||
|RSDS_25|1.42|1.42|ns|
|RSDS_33|0.58|0.58|ns|
|TMDS_33|0.46|0.46|ns|
|PPDS_25|1.07|1.07|ns|
|PPDS_33|0.63|0.63|ns|
|DIFF_HSTL_I_18|0.43|0.43|ns|
|DIFF_HSTL_II_18|0.41|0.41|ns|
|DIFF_HSTL_III_18|0.36|0.36|ns|
|DIFF_HSTL_I|1.01|1.01|ns|
|DIFF_HSTL_III|0.54|0.54|ns|
|DIFF_SSTL18_I|0.49|0.49|ns|
|DIFF_SSTL18_II|0.41|0.41|ns|
|DIFF_SSTL2_I|0.82|0.82|ns|
|DIFF_SSTL2_II|0.09|0.09|ns|
|DIFF_SSTL3_I|1.16|1.16|ns|
|DIFF_SSTL3_II|0.28|0.28|ns|



## **Notes:** 

1. The numbers in this table are tested using the methodology presented in Table 30 and are based on the operating conditions set forth in Table 10, Table 13, and Table 15. 

2. These adjustments are used to convert output- and three-state-path times originally specified for the LVCMOS25 standard with 12 mA drive and Fast slew rate to times that correspond to other signal standards. Do not adjust times that measure when outputs go into a high-impedance state. 

3. Note that 16 mA drive is faster than 24 mA drive for the Slow slew rate. 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

40 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

## **Timing Measurement Methodology** 

When measuring timing parameters at the programmable I/Os, different signal standards call for different test conditions. Table 30 lists the conditions to use for each standard. 

The method for measuring Input timing is as follows: A signal that swings between a Low logic level of VL and a High logic level of VH is applied to the Input under test. Some standards also require the application of a bias voltage to the VREF pins of a given bank to properly set the input-switching threshold. The measurement point of the Input signal (VM) is commonly located halfway between VL and VH. 

The Output test setup is shown in Figure 11. A termination voltage VT is applied to the termination resistor RT, the other end of which is connected to the Output. For each standard, RT and VT generally take on the standard values recommended for minimizing signal reflections. If the standard does not ordinarily use terminations (for example, 

LVCMOS, LVTTL), then RT is set to 1MΩ to indicate an open connection, and VT is set to zero. The same measurement point (VM) that was used at the Input is also used at the Output. 

**==> picture [167 x 111] intentionally omitted <==**

**----- Start of picture text -----**<br>
VT (VREF)<br>FPGA Output<br>RT (RREF)<br>VM (VMEAS)<br>CL (CREF)<br>DS312-3_04_102406<br>**----- End of picture text -----**<br>


## **Notes:** 

1. The names shown in parentheses are used in the IBIS file. 

_Figure 11:_ **Output Test Setup** 

_Table  30:_ **Test Methods for Timing Measurement at I/Os** 

|**Signal Standard**<br>**(IOSTANDARD)**|**Signal Standard**<br>**(IOSTANDARD)**|**Inputs**|**Inputs**|**Inputs**|**Outputs**(2)|**Outputs**(2)|**Inputs and**<br>**Outputs**|
|---|---|---|---|---|---|---|---|
|||**VREF (V)**|**VL (V)**|**VH (V)**|**RT (**Ω**)**|**VT (V)**|**VM (V)**|
|**Single-Ended**||||||||
|LVTTL||–|0|3.3|1M|0|1.4|
|LVCMOS33||–|0|3.3|1M|0|1.65|
|LVCMOS25||–|0|2.5|1M|0|1.25|
|LVCMOS18||–|0|1.8|1M|0|0.9|
|LVCMOS15||–|0|1.5|1M|0|0.75|
|LVCMOS12||–|0|1.2|1M|0|0.6|
|PCI33_3|Rising|–|Note3|Note3|25|0|0.94|
||Falling||||25|3.3|2.03|
|PCI66_3|Rising|–|Note3|Note3|25|0|0.94|
||Falling||||25|3.3|2.03|
|HSTL_I||0.75|VREF– 0.5|VREF+ 0.5|50|0.75|VREF|
|HSTL_III||0.9|VREF– 0.5|VREF+ 0.5|50|1.5|VREF|
|HSTL_I_18||0.9|VREF– 0.5|VREF+ 0.5|50|0.9|VREF|
|HSTL_II_18||0.9|VREF– 0.5|VREF+ 0.5|25|0.9|VREF|
|HSTL_III_18||1.1|VREF– 0.5|VREF+ 0.5|50|1.8|VREF|
|SSTL18_I||0.9|VREF– 0.5|VREF+ 0.5|50|0.9|VREF|
|SSTL18_II||0.9|VREF– 0.5|VREF+ 0.5|25|0.9|VREF|
|SSTL2_I||1.25|VREF– 0.75|VREF+ 0.75|50|1.25|VREF|
|SSTL2_II||1.25|VREF– 0.75|VREF+ 0.75|25|1.25|VREF|
|SSTL3_I||1.5|VREF– 0.75|VREF+ 0.75|50|1.5|VREF|
|SSTL3_II||1.5|VREF– 0.75|VREF+ 0.75|25|1.5|VREF|



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

41 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

_Table  30:_ **Test Methods for Timing Measurement at I/Os** _**(Cont’d)**_ 

|**Signal Standard**<br>**(IOSTANDARD)**|**Inputs**|**Inputs**|**Inputs**|**Outputs**(2)|**Outputs**(2)|**Inputs and**<br>**Outputs**|
|---|---|---|---|---|---|---|
||**VREF (V)**|**VL (V)**|**VH (V)**|**RT (**Ω**)**|**VT (V)**|**VM (V)**|
|**Differential**|||||||
|LVDS_25|–|VICM– 0.125|VICM+ 0.125|50|1.2|VICM|
|LVDS_33|–|VICM– 0.125|VICM+ 0.125|50|1.2|VICM|
|BLVDS_25|–|VICM– 0.125|VICM+ 0.125|1M|0|VICM|
|MINI_LVDS_25|–|VICM– 0.125|VICM+ 0.125|50|1.2|VICM|
|MINI_LVDS_33|–|VICM– 0.125|VICM+ 0.125|50|1.2|VICM|
|LVPECL_25|–|VICM– 0.3|VICM+ 0.3|N/A|N/A|VICM|
|LVPECL_33|–|VICM– 0.3|VICM+ 0.3|N/A|N/A|VICM|
|RSDS_25|–|VICM– 0.1|VICM+ 0.1|50|1.2|VICM|
|RSDS_33|–|VICM– 0.1|VICM+ 0.1|50|1.2|VICM|
|TMDS_33|–|VICM– 0.1|VICM+ 0.1|50|3.3|VICM|
|PPDS_25|–|VICM– 0.1|VICM+ 0.1|50|0.8|VICM|
|PPDS_33|–|VICM– 0.1|VICM+ 0.1|50|0.8|VICM|
|DIFF_HSTL_I|–|VICM– 0.5|VICM+ 0.5|50|0.75|VICM|
|DIFF_HSTL_III|–|VICM– 0.5|VICM+ 0.5|50|1.5|VICM|
|DIFF_HSTL_I_18|–|VICM– 0.5|VICM+ 0.5|50|0.9|VICM|
|DIFF_HSTL_II_18|–|VICM– 0.5|VICM+ 0.5|50|0.9|VICM|
|DIFF_HSTL_III_18|–|VICM– 0.5|VICM+ 0.5|50|1.8|VICM|
|DIFF_SSTL18_I|–|VICM– 0.5|VICM+ 0.5|50|0.9|VICM|
|DIFF_SSTL18_II|–|VICM– 0.5|VICM+ 0.5|50|0.9|VICM|
|DIFF_SSTL2_I|–|VICM– 0.5|VICM+ 0.5|50|1.25|VICM|
|DIFF_SSTL2_II|–|VICM– 0.5|VICM+ 0.5|50|1.25|VICM|
|DIFF_SSTL3_I|–|VICM– 0.5|VICM+ 0.5|50|1.5|VICM|
|DIFF_SSTL3_II|–|VICM– 0.5|VICM+ 0.5|50|1.5|VICM|



## **Notes:** 

1. Descriptions of the relevant symbols are as follows: VREF – The reference voltage for setting the input switching threshold VICM – The common mode input voltage 

   - VM – Voltage of measurement point on signal transition 

   - VL – Low-level test voltage at Input pin 

   - VH – High-level test voltage at Input pin 

   - RT – Effective termination resistance, which takes on a value of 1 MΩ when no parallel termination is required VT – Termination voltage 

2. The load capacitance (CL) at the Output pin is 0 pF for all signal standards. 

3. According to the PCI specification. For information on PCI IP solutions, see www.xilinx.com/products/design_resources/conn_central/protocols/pci_pcix.htm. The PCIX IOSTANDARD is available and has equivalent characteristics but no PCI-X IP is supported. 

The capacitive load (CL) is connected between the output and GND. _The Output timing for all standards, as published in the speed files and the data sheet, is always based on a CL value of zero._ High-impedance probes (less than 1 pF) are used for all measurements. Any delay that the test fixture might contribute to test measurements is subtracted from those measurements to produce the final timing numbers as published in the speed files and data sheet. 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

42 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

## **Using IBIS Models to Simulate Load Conditions in Application** 

IBIS models permit the most accurate prediction of timing delays for a given application. The parameters found in the IBIS model (VREF, RREF, and VMEAS) correspond directly with the parameters used in Table 30 (VT, RT, and VM). Do not confuse VREF (the termination voltage) from the IBIS model with VREF (the input-switching threshold) from the table. A fourth parameter, CREF, is always zero. The four parameters describe all relevant output test conditions. IBIS models are found in the Xilinx development software as well as at the following link: 

## www.xilinx.com/support/download/index.htm 

Delays for a given application are simulated according to its specific load conditions as follows: 

1. Simulate the desired signal standard with the output driver connected to the test setup shown in Figure 11. Use parameter values VT, RT, and VM from Table 30. CREF is zero. 

2. Record the time to VM. 

3. Simulate the same signal standard with the output driver connected to the PCB trace with load. Use the appropriate IBIS model (including VREF, RREF, CREF, and VMEAS values) or capacitive value to represent the load. 

4. Record the time to VMEAS. 

5. Compare the results of steps 2 and 4. Add (or subtract) the increase (or decrease) in delay to (or from) the appropriate Output standard adjustment (Table 29) to yield the worst-case delay of the PCB trace. 

## **Simultaneously Switching Output Guidelines** 

This section provides guidelines for the recommended maximum allowable number of Simultaneous Switching Outputs (SSOs). These guidelines describe the maximum number of user I/O pins of a given output signal standard that should simultaneously switch in the same direction, while maintaining a safe level of switching noise. Meeting these guidelines for the stated test conditions ensures that the FPGA operates free from the adverse effects of ground and power bounce. 

Ground or power bounce occurs when a large number of outputs simultaneously switch in the same direction. The output drive transistors all conduct current to a common voltage rail. Low-to-High transitions conduct to the VCCO rail; High-to-Low transitions conduct to the GND rail. The resulting cumulative current transient induces a voltage difference across the inductance that exists between the die pad and the power supply or ground return. The inductance is associated with bonding wires, the package lead frame, 

and any other signal routing inside the package. Other variables contribute to SSO noise levels, including stray inductance on the PCB as well as capacitive loading at receivers. Any SSO-induced voltage consequently affects internal switching noise margins and ultimately signal quality. 

Table 31 and Table 32 provide the essential SSO guidelines. For each device/package combination, Table 31 provides the number of equivalent VCCO/GND pairs. The equivalent number of pairs is based on characterization and may not match the physical number of pairs. For each output signal standard and drive strength, Table 32 recommends the maximum number of SSOs, switching in the same direction, allowed per VCCO/GND pair within an I/O bank. The guidelines in Table 32 are categorized by package style, slew rate, and output drive current. Furthermore, the number of SSOs is specified by I/O bank. Generally, the left and right I/O banks (Banks 1 and 3) support higher output drive current. 

Multiply the appropriate numbers from Table 31 and Table 32 to calculate the maximum number of SSOs allowed within an I/O bank. Exceeding these SSO guidelines might result in increased power or ground bounce, degraded signal integrity, or increased system jitter. 

SSOMAX/IO Bank = Table 31 x Table 32 

The recommended maximum SSO values assumes that the FPGA is soldered on the printed circuit board and that the board uses sound design practices. The SSO values do not apply for FPGAs mounted in sockets, due to the lead inductance introduced by the socket. 

The number of SSOs allowed for quad-flat packages (TQ) is lower than for ball grid array packages (FG) due to the larger lead inductance of the quad-flat packages. Ball grid array packages are recommended for applications with a large number of simultaneously switching outputs. 

_Table  31:_ **Equivalent VCCO/GND Pairs per Bank** 

|_Table  31:_ **Eq**|**uivalent VCCO/GND Pairs per Bank**|**uivalent VCCO/GND Pairs per Bank**|**uivalent VCCO/GND Pairs per Bank**|**uivalent VCCO/GND Pairs per Bank**|**uivalent VCCO/GND Pairs per Bank**|
|---|---|---|---|---|---|
|**Device**|**Package Style**|||||
||**TQG144 **|**FTG256 **|**FGG400 **|**FGG484 **|**FGG676**|
|XC3S50AN|2|3|–|–|–|
|XC3S200AN|–|4|–|–|–|
|XC3S400AN|–|4|5|–|–|
|XC3S700AN|–|–|–|5|–|
|XC3S1400AN|–|–|–|6|9|



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

43 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

_Table  32:_ **Recommended Number of Simultaneously Switching Outputs per VCCO-GND Pair** 

|**Switching Outputs per**|**Switching Outputs per**|**Switching Outputs per**|**VCCO-GND Pair**|**VCCO-GND Pair**|**VCCO-GND Pair**|**VCCO-GND Pair**|
|---|---|---|---|---|---|---|
|**Signal Standard**<br>**(IOSTANDARD)**|||**Package Type**||||
||||**TQG144**||**FTG256,**<br>**FGG400,**<br>**FGG484,**<br>**FGG676**||
||||**Top,**<br>**Bottom**<br>**Banks 0,2**|**Left,**<br>**Right**<br>**Banks 1,3**|**Top,**<br>**Bottom**<br>**Banks 0,2**|**Left,**<br>**Right**<br>**Banks 1,3**|
|**Single-Ended Standards**|||||||
|LVTTL|Slow|2|20|20|60|60|
|||4|10|10|41|41|
|||6|10|10|29|29|
|||8|6|6|22|22|
|||12|6|6|13|13|
|||16|5|5|11|11|
|||24|4|4|9|9|
||Fast|2|10|10|10|10|
|||4|6|6|6|6|
|||6|5|5|5|5|
|||8|3|3|3|3|
|||12|3|3|3|3|
|||16|3|3|3|3|
|||24|2|2|2|2|
||QuietIO|2|40|40|80|80|
|||4|24|24|48|48|
|||6|20|20|36|36|
|||8|16|16|27|27|
|||12|12|12|16|16|
|||16|9|9|13|13|
|||24|9|9|12|12|



_Table  32:_ **Recommended Number of Simultaneously Switching Outputs per VCCO-GND Pair** _**(Cont’d)**_ 

|**Switching Outputs**|**Switching Outputs**|**per**|**VCCO-GND Pair****_(Cont’d)_**|**VCCO-GND Pair****_(Cont’d)_**|**VCCO-GND Pair****_(Cont’d)_**|**VCCO-GND Pair****_(Cont’d)_**|
|---|---|---|---|---|---|---|
|**Signal Standard**<br>**(IOSTANDARD)**|||**Package Type**||||
||||**TQG144**||**FTG256,**<br>**FGG400,**<br>**FGG484,**<br>**FGG676**||
||||**Top,**<br>**Bottom**<br>**Banks 0,2**|**Left,**<br>**Right**<br>**Banks 1,3**|**Top,**<br>**Bottom**<br>**Banks 0,2**|**Left,**<br>**Right**<br>**Banks 1,3**|
|LVCMOS33|Slow|2|24|24|76|76|
|||4|14|14|46|46|
|||6|11|11|27|27|
|||8|10|10|20|20|
|||12|9|9|13|13|
|||16|8|8|10|10|
|||24|–|8|–|9|
||Fast|2|10|10|10|10|
|||4|8|8|8|8|
|||6|5|5|5|5|
|||8|4|4|4|4|
|||12|4|4|4|4|
|||16|2|2|2|2|
|||24|–|2|–|2|
||QuietIO|2|36|36|76|76|
|||4|32|32|46|46|
|||6|24|24|32|32|
|||8|16|16|26|26|
|||12|16|16|18|18|
|||16|12|12|14|14|
|||24|–|10|–|10|



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

44 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

_Table  32:_ **Recommended Number of Simultaneously Switching Outputs per VCCO-GND Pair** _**(Cont’d)**_ 

_Table  32:_ **Recommended Number of Simultaneously Switching Outputs per VCCO-GND Pair** _**(Cont’d)**_ 

|**Switching O**|**utputs**|**per**|**VCCO-G**|**ND Pair****_(Cont’d)_**|**ND Pair****_(Cont’d)_**|||**Switching O**|**utputs**|**per**|**VCCO-G**|**ND Pair****_(Cont’d)_**|**ND Pair****_(Cont’d)_**||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|||||**Package Type**||||||||**Package Type**|||
||||||**FTG256,**||||||||**FTG256,**||
|**Signal Standard**|||**TQG144**||**FGG400,**<br>**FGG484,**|||**Signal Standard**|||**TQG144**||**FGG400,**<br>**FGG484,**||
|**(IOSTANDARD)**|||||**FGG676**|||**(IOSTANDARD)**|||||**FGG676**||
||||**Top,**|**Left,**|**Top,**|**Left,**|||||**Top,**|**Left,**|**Top,**|**Left,**|
||||**Bottom**|**Right**|**Bottom**|**Right**|||||**Bottom**|**Right**|**Bottom**|**Right**|
||||**Banks 0,2**|**Banks 1,3**|**Banks 0,2**|**Banks 1,3**|||||**Banks 0,2**|**Banks 1,3**|**Banks 0,2**|**Banks 1,3**|
|LVCMOS25|Slow|2|16|16|76|76||LVCMOS18|Slow|2|13|13|64|64|
|||4|10|10|46|46||||4|8|8|34|34|
|||6|8|8|33|33||||6|8|8|22|22|
|||8|7|7|24|24||||8|7|7|18|18|
|||12|6|6|18|18||||12|–|5|–|13|
|||16|–|6|–|11||||16|–|5|–|10|
|||24|–|5|–|7|||Fast|2|13|13|18|18|
||Fast|2|12|12|18|18||||4|8|8|9|9|
|||4|10|10|14|14||||6|7|7|7|7|
|||6|8|8|6|6||||8|4|4|4|4|
|||8|6|6|6|6||||12|–|4|–|4|
|||12|3|3|3|3||||16|–|3|–|3|
|||16|–|3|–|3|||QuietIO|2|30|30|64|64|
|||24|–|2|–|2||||4|24|24|64|64|
||QuietIO|2|36|36|76|76||||6|20|20|48|48|
|||4|30|30|60|60||||8|16|16|36|36|
|||6|24|24|48|48||||12|–|12|–|36|
|||8|20|20|36|36||||16|–|12|–|24|
|||12|12|12|36|36||LVCMOS15|Slow|2|12|12|55|55|
|||16|–|12|–|36||||4|7|7|31|31|
|||24|–|8|–|8||||6|7|7|18|18|
|||||||||||8|–|6|–|15|
|||||||||||12|–|5|–|10|
||||||||||Fast|2|10|10|25|25|
|||||||||||4|7|7|10|10|
|||||||||||6|6|6|6|6|
|||||||||||8|–|4|–|4|
|||||||||||12|–|3|–|3|
||||||||||QuietIO|2|30|30|70|70|
|||||||||||4|21|21|40|40|
|||||||||||6|18|18|31|31|
|||||||||||8|–|12|–|31|
|||||||||||12|–|12|–|20|



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

45 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

_Table  32:_ **Recommended Number of Simultaneously Switching Outputs per VCCO-GND Pair** _**(Cont’d)**_ 

_Table  32:_ **Recommended Number of Simultaneously Switching Outputs per VCCO-GND Pair** _**(Cont’d)**_ 

|**Signal Standard**<br>**(IOSTANDARD)**|**Signal Standard**<br>**(IOSTANDARD)**||**Package Type**|**Package Type**|**Package Type**|**Package Type**|**Package Type**||**Signal Standard**<br>**(IOSTANDARD)**|**Package Type**|**Package Type**|**Package Type**|**Package Type**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||||**TQG144**|||**FTG256,**<br>**FGG400,**<br>**FGG484,**<br>**FGG676**||||**TQG144**||**FTG256,**<br>**FGG400,**<br>**FGG484,**<br>**FGG676**||
||||**Top,**<br>**Bottom**<br>**Banks 0,2**|**Left,**<br>**Right**<br>**Banks 1,3**||**Top,**<br>**Bottom**<br>**Banks 0,2**|**Left,**<br>**Right**<br>**Banks 1,3**|||**Top,**<br>**Bottom**<br>**Banks 0,2**|**Left,**<br>**Right**<br>**Banks 1,3**|**Top,**<br>**Bottom**<br>**Banks 0,2**|**Left,**<br>**Right**<br>**Banks 1,3**|
|LVCMOS12|Slow|2|17|17||40|40||PPDS_33|8|–|27|–|
|||4|–|13||–|25||DIFF_HSTL_I|–|5|–|10|
|||6|–|10||–|18||DIFF_HSTL_III|–|3|–|4|
||Fast|2|12|9||31|31||DIFF_HSTL_I_18|6|6|8|8|
|||4|–|9||–|13||DIFF_HSTL_II_18|–|2|–|2|
|||6|–|9||–|9||DIFF_HSTL_III_18|4|4|5|4|
||QuietIO|2|36|36||55|55||DIFF_SSTL18_I|3|6|3|7|
|||4|–|33||–|36||DIFF_SSTL18_II|–|4|–|4|
|||6|–|27||–|36||DIFF_SSTL2_I|5|5|9|9|
|PCI33_3|||9|9||16|16||DIFF_SSTL2_II|–|3|–|4|
|PCI66_3|||–|9||–|13||DIFF_SSTL3_I|3|4|4|5|
|HSTL_I|||–|11||–|20||DIFF_SSTL3_II|2|3|3|3|
|HSTL_III|||–|7||–|8||**Notes:**<br>1.<br>Not all I/O standards are supported on all I/O banks. The left and<br>right banks (I/O banks 1 and 3) support higher output drive<br>current than the top and bottom banks (I/O banks 0 and 2).<br>Similarly, true differential output standards, such as LVDS, RSDS,<br>PPDS, miniLVDS, and TMDS, are only supported in top or bottom<br>banks (I/O banks 0 and 2). Refer toUG331<br>: _Spartan-3_<br>_Generation FPGA User Guide_for additional information.<br>2.<br>The numbers in this table are recommendations that assume<br>sound board lay out practice. Test limits are the VIL/VIHvoltage<br>limits for the respective I/O standard.<br>3.<br>If more than one signal standard is assigned to the I/Os of a given<br>bank, refer toXAPP689<br>: _Managing Ground Bounce in Large_<br>_FPGAs_for information on how to perform weighted average SSO<br>calculations.|||||
|HSTL_I_18|||13|13||17|17|||||||
|HSTL_II_18|||–|5||–|5|||||||
|HSTL_III_18|||8|8||10|8|||||||
|SSTL18_I|||7|13||7|15|||||||
|SSTL18_II|||–|9||–|9|||||||
|SSTL2_I|||10|10||18|18|||||||
|SSTL2_II|||–||6|–|9|||||||
|SSTL3_I|||7||8|8|10|||||||
|SSTL3_II|||5||6|6|7|||||||
|**Differential Standards (Number of I/O**|||||**_Pairs_**<br>**or Channels)**|||||||||
|LVDS_25|||8||–|22|–|||||||
|LVDS_33|||8||–|27|–|||||||
|BLVDS_25|||1||1|4|4|||||||
|MINI_LVDS_25|||8||–|22|–|||||||
|MINI_LVDS_33|||8||–|27|–|||||||
|LVPECL_25|||||Input Only|||||||||
|LVPECL_33|||||Input Only|||||||||
|RSDS_25|||8||–|22|–|||||||
|RSDS_33|||8||–|27|–|||||||
|TMDS_33|||8||–|27|–|||||||
|PPDS_25|||8||–|22|–|||||||



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

46 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

## **Configurable Logic Block (CLB) Timing** 

## _Table  33:_ **CLB (SLICEM) Timing** 

|**Symbol**|**Description**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|
|||**-5**||**-4**|||
|||**Min**|**Max**|**Min**|**Max**||
|**Clock-to-Output Times**|||||||
|TCKO|When reading from the FFX (FFY) Flip-Flop, the time<br>from the active transition at the CLK input to data<br>appearing at the XQ (YQ) output|–|0.60|–|0.68|ns|
|**Setup Times**|||||||
|TAS|Time from the setup of data at the F or G input to the<br>active transition at the CLK input of the CLB|0.18|–|0.36|–|ns|
|TDICK|Time from the setup of data at the BX or BY input to<br>the active transition at the CLK input of the CLB|1.58|–|1.88|–|ns|
|**Hold Times**|||||||
|TAH|Time from the active transition at the CLK input to the<br>point where data is last held at the F or G input|0|–|0|–|ns|
|TCKDI|Time from the active transition at the CLK input to the<br>point where data is last held at the BX or BY input|0|–|0|–|ns|
|**Clock Timing**|||||||
|TCH|The High pulse width of the CLB’s CLK signal|0.63|–|0.75|–|ns|
|TCL|The Low pulse width of the CLK signal|0.63|–|0.75|–|ns|
|FTOG|Toggle frequency (for export control)|0|770|0|667|MHz|
|**Propagation Times**|||||||
|TILO|The time it takes for data to travel from the CLB’s F<br>(G) input to the X (Y) output|–|0.62|–|0.71|ns|
|**Set/Reset Pulse Width**|||||||
|TRPW_CLB|The minimum allowable pulse width, High or Low, to<br>the CLB’s SR input|1.33|–|1.61|–|ns|



## **Notes:** 

1. The numbers in this table are based on the operating conditions set forth in Table 10. 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

47 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

_Table  34:_ **CLB Distributed RAM Switching Characteristics** 

|**Symbol**|**Description**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|
|||**-5**||**-4**|||
|||**Min**|**Max**|**Min**|**Max**||
|**Clock-to-Output Times**|||||||
|TSHCKO|Time from the active edge at the CLK input to data appearing on<br>the distributed RAM output|–|1.69|–|2.01|ns|
|**Setup Times**|||||||
|TDS|Setup time of data at the BX or BY input before the active<br>transition at the CLK input of the distributed RAM|–0.07|–|–0.02|–|ns|
|TAS|Setup time of the F/G address inputs before the active transition<br>at the CLK input of the distributed RAM|0.18|–|0.36|–|ns|
|TWS|Setup time of the write enable input before the active transition at<br>the CLK input of the distributed RAM|0.30|–|0.59|–|ns|
|**Hold Times**|||||||
|TDH|Hold time of the BX and BY data inputs after the active transition<br>at the CLK input of the distributed RAM|0.13|–|0.13|–|ns|
|TAH,TWH|Hold time of the F/G address inputs or the write enable input after<br>the active transition at the CLK input of the distributed RAM|0.01|–|0.01|–|ns|
|**Clock Pulse Width**|||||||
|TWPH, TWPL|Minimum High or Low pulse width at CLK input|0.88|–|1.01|–|ns|
|**Notes:**|||||||



1. The numbers in this table are based on the operating conditions set forth in Table 10. 

_Table  35:_ **CLB Shift Register Switching Characteristics** 

|**Symbol**|**Description**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|
|||**-5**||**-4**|||
|||**Min**|**Max**|**Min**|**Max**||
|**Clock-to-Output Times**|||||||
|TREG|Time from the active edge at the CLK input to data appearing on<br>the shift register output|–|4.11|–|4.82|ns|
|**Setup Times**|||||||
|TSRLDS|Setup time of data at the BX or BY input before the active<br>transition at the CLK input of the shift register|0.13|–|0.18|–|ns|
|**Hold Times**|||||||
|TSRLDH|Hold time of the BX or BY data input after the active transition at<br>the CLK input of the shift register|0.16|–|0.16|–|ns|
|**Clock Pulse Width**|||||||
|TWPH, TWPL|Minimum High or Low pulse width at CLK input|0.90|–|1.01|–|ns|



## **Notes:** 

1. The numbers in this table are based on the operating conditions set forth in Table 10. 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

48 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

## **Clock Buffer/Multiplexer Switching Characteristics** 

_Table  36:_ **Clock Distribution Switching Characteristics** 

|_Table  36:_ **Clock Distribution Switching Characteristics**||||||
|---|---|---|---|---|---|
|**Description**|**Symbol**|**Minimum**|**Maximum**||**Units**|
||||**Speed Grade**|||
||||**-5**|**-4**||
|Global clock buffer (BUFG, BUFGMUX, BUFGCE) I input to<br>O-output delay|TGIO|–|0.22|0.23|ns|
|Global clock multiplexer (BUFGMUX) select S-input setup to I0 and<br>I1 inputs. Same as BUFGCE enable CE-input|TGSI|–|0.56|0.63|ns|
|Frequency of signals distributed on global buffers (all sides)|FBUFG|0|350|334|MHz|



## **Notes:** 

1. The numbers in this table are based on the operating conditions set forth in Table 10. 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

49 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

## **18 x 18 Embedded Multiplier Timing** 

_Table  37:_ **18 x 18 Embedded Multiplier Timing** 

|**Symbol**|**Description**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|
|||**-5**||**-4**|||
|||**Min**|**Max**|**Min**|**Max**||
|**Combinatorial Delay**|||||||
|TMULT|Combinational multiplier propagation delay from the A and B inputs<br>to the P outputs, assuming 18-bit inputs and a 36-bit product<br>(AREG, BREG, and PREG registers unused)|–|4.36|–|4.88|ns|
|**Clock-to-Output Times**|||||||
|TMSCKP_P|Clock-to-output delay from the active transition of the CLK input to<br>valid data appearing on the P outputs when using the PREG<br>register(2,3)|–|0.84|–|1.30|ns|
|TMSCKP_A<br>TMSCKP_B|Clock-to-output delay from the active transition of the CLK input to<br>valid data appearing on the P outputs when using either the AREG<br>or BREG register(2,4)|–|4.44|–|4.97|ns|
|**Setup Times**|||||||
|TMSDCK_P|Data setup time at the A or B input before the active transition at the<br>CLK when using only the PREG output register (AREG, BREG<br>registers unused)(3)|3.56|–|3.98|–|ns|
|TMSDCK_A|Data setup time at the A input before the active transition at the CLK<br>when using the AREG input register(4)|0.00|–|0.00|–|ns|
|TMSDCK_B|Data setup time at the B input before the active transition at the CLK<br>when using the BREG input register(4)|0.00|–|0.00|–|ns|
|**Hold Times**|||||||
|TMSCKD_P|Data hold time at the A or B input after the active transition at the<br>CLK when using only the PREG output register (AREG, BREG<br>registers unused)(3)|0.00|–|0.00|–|ns|
|TMSCKD_A|Data hold time at the A input after the active transition at the CLK<br>when using the AREG input register(4)|0.35|–|0.45|–|ns|
|TMSCKD_B|Data hold time at the B input after the active transition at the CLK<br>when using the BREG input register(4)|0.35|–|0.45|–|ns|
|**Clock Frequency**|||||||
|FMULT|Internal operating frequency for a two-stage 18x18 multiplier using<br>the AREG and BREG input registers and the PREG output<br>register(5)|0|280|0|250|MHz|



## **Notes:** 

1. The numbers in this table are based on the operating conditions set forth in Table 10. 

2. The PREG register is typically used in both single-stage and two-stage pipelined multiplier implementations. 

3. The PREG register is typically used when inferring a single-stage multiplier. 

4. Input registers AREG or BREG are typically used when inferring a two-stage multiplier. 

5. Combinational delay is less and pipelined performance is higher when multiplying input data with less than 18 bits. 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

50 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

## **Block RAM Timing** 

_Table  38:_ **Block RAM Timing** 

|**Symbol**|**Description**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|
|||**-5**||**-4**|||
|||**Min**|**Max**|**Min**|**Max**||
|**Clock-to-Output Times**|||||||
|TRCKO|When reading from block RAM, the delay from the active<br>transition at the CLK input to data appearing at the DOUT<br>output|–|2.06|–|2.49|ns|
|**Setup Times**|||||||
|TRCCK_ADDR|Setup time for the ADDR inputs before the active transition at<br>the CLK input of the block RAM|0.32|–|0.36|–|ns|
|TRDCK_DIB|Setup time for data at the DIN inputs before the active<br>transition at the CLK input of the block RAM|0.28|–|0.31|–|ns|
|TRCCK_ENB|Setup time for the EN input before the active transition at the<br>CLK input of the block RAM|0.69|–|0.77|–|ns|
|TRCCK_WEB|Setup time for the WE input before the active transition at the<br>CLK input of the block RAM|1.12|–|1.26|–|ns|
|**Hold Times**|||||||
|TRCKC_ADDR|Hold time on the ADDR inputs after the active transition at the<br>CLK input|0|–|0|–|ns|
|TRCKD_DIB|Hold time on the DIN inputs after the active transition at the<br>CLK input|0|–|0|–|ns|
|TRCKC_ENB|Hold time on the EN input after the active transition at the CLK<br>input|0|–|0|–|ns|
|TRCKC_WEB|Hold time on the WE input after the active transition at the CLK<br>input|0|–|0|–|ns|
|**Clock Timing**|||||||
|TBPWH|High pulse width of the CLK signal|1.56|–|1.79|–|ns|
|TBPWL|Low pulse width of the CLK signal|1.56|–|1.79|–|ns|
|**Clock Frequency**|||||||
|FBRAM|Block RAM clock frequency|0|320|0|280|MHz|



## **Notes:** 

1. The numbers in this table are based on the operating conditions set forth in Table 10. 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

51 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

## **Digital Clock Manager (DCM) Timing** 

For specification purposes, the DCM consists of three key components: the Delay-Locked Loop (DLL), the Digital Frequency Synthesizer (DFS), and the Phase Shifter (PS). 

Aspects of DLL operation play a role in all DCM applications. All such applications inevitably use the CLKIN and the CLKFB inputs connected to either the CLK0 or the CLK2X feedback, respectively. Thus, specifications in the DLL tables (Table 39 and Table 40) apply to any application that only employs the DLL component. When the DFS and/or the PS components are used together with the DLL, then the specifications listed in the DFS and PS tables (Table 41 through Table 44) supersede any corresponding ones in the DLL tables. DLL specifications that do not change with the addition of DFS or PS functions are presented in Table 39 and Table 40. 

Period jitter is the worst-case deviation from the ideal clock period over a collection of millions of samples. In a histogram of period jitter, the mean value is the clock period. 

Cycle-cycle jitter is the worst-case difference in clock period between adjacent clock cycles in the collection of clock periods sampled. In a histogram of cycle-cycle jitter, the mean value is zero. 

## **Spread Spectrum** 

DCMs accept typical spread spectrum clocks as long as they meet the input requirements. The DLL will track the frequency changes created by the spread spectrum clock to drive the global clocks to the FPGA logic. See XAPP469: _Spread-Spectrum Clocking Reception for Displays_ for details. 

Period jitter and cycle-cycle jitter are two of many different ways of specifying clock jitter. Both specifications describe statistical variation from a mean value. 

## **Delay-Locked Loop (DLL)** 

_Table  39:_ **Recommended Operating Conditions for the DLL** 

|**Symbol**|**Symbol**|**Description**|**Description**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|---|---|
|||||**-5**||**-4**|||
|||||**Min**|**Max**|**Min**|**Max**||
|**Input Frequency Ranges**|||||||||
|FCLKIN|CLKIN_FREQ_DLL|Frequency of the CLKIN clock input||5(2)|280(3)|5(2)|250(3)|MHz|
|**Input Pulse Requirements**|||||||||
|CLKIN_PULSE||CLKIN pulse width as a<br>percentage of the CLKIN<br>period|FCLKIN<<br> 150 MHz|40%|60%|40%|60%|%|
||||FCLKIN> 150 MHz|45%|55%|45%|55%|%|
|**Input Clock Jitter Tolerance and Delay Path Variation**(4)|||||||||
|CLKIN_CYC_JITT_DLL_LF||Cycle-to-cycle jitter at the<br>CLKIN input|FCLKIN<<br> 150 MHz|–|±300|–|±300|ps|
|CLKIN_CYC_JITT_DLL_HF|||FCLKIN> 150 MHz|–|±150|–|±150|ps|
|CLKIN_PER_JITT_DLL||Period jitter at the CLKIN input||–|±1|–|±1|ns|
|CLKFB_DELAY_VAR_EXT||Allowable variation of off-chip feedback delay<br>from the DCM output to the CLKFB input||–|±1|–|±1|ns|



## **Notes:** 

1. DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use. 

2. The DFS, when operating independently of the DLL, supports lower FCLKIN frequencies. See Table 41. 

3. The CLKIN_DIVIDE_BY_2 attribute can be used to increase the effective input frequency range up to FBUFG. When set to TRUE, CLKIN_DIVIDE_BY_2 divides the incoming clock frequency by two as it enters the DCM. 

4. CLKIN input jitter beyond these limits might cause the DCM to lose lock. 

5. The DCM specifications are guaranteed when both adjacent DCMs are locked. 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

52 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

_Table  40:_ **Switching Characteristics for the DLL** 

|**Symbol**|**Description**|**Description**|**Device**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|---|---|
|||||**-5**||**-4**|||
|||||**Min**|**Max**|**Min**|**Max**||
|**Output Frequency Ranges**|||||||||
|CLKOUT_FREQ_CLK0|Frequency for the CLK0 and CLK180 outputs||All|5|280|5|250|MHz|
|CLKOUT_FREQ_CLK90|Frequency for the CLK90 and CLK270 outputs|||5|200|5|200|MHz|
|CLKOUT_FREQ_2X|Frequency for the CLK2X and CLK2X180 outputs|||10|334|10|334|MHz|
|CLKOUT_FREQ_DV|Frequency for the CLKDV output|||0.3125|186|0.3125|166|MHz|
|**Output Clock Jitter**(2,3,4)|||||||||
|CLKOUT_PER_JITT_0|Period jitter at the CLK0 output||All|–|±100|–|±100|ps|
|CLKOUT_PER_JITT_90|Period jitter at the CLK90 output|||–|±150|–|±150|ps|
|CLKOUT_PER_JITT_180|Period jitter at the CLK180 output|||–|±150|–|±150|ps|
|CLKOUT_PER_JITT_270|Period jitter at the CLK270 output|||–|±150|–|±150|ps|
|CLKOUT_PER_JITT_2X|Period jitter at the CLK2X and CLK2X180 outputs|||–|±[0.5%<br>of<br>CLKIN<br>period<br>+ 100]|–|±[0.5%<br>of<br>CLKIN<br>period<br>+ 100]|ps|
|CLKOUT_PER_JITT_DV1|Period jitter at the CLKDV output when performing<br>integer division|||–|±150|–|±150|ps|
|CLKOUT_PER_JITT_DV2|Period jitter at the CLKDV output when performing<br>non-integer division|||–|±[0.5%<br>of<br>CLKIN<br>period<br>+ 100]|–|±[0.5%<br>of<br>CLKIN<br>period<br>+ 100]|ps|
|**Duty Cycle**(4)|||||||||
|CLKOUT_DUTY_CYCLE_DLL|Duty cycle variation for the CLK0, CLK90, CLK180,<br>CLK270, CLK2X, CLK2X180, and CLKDV outputs,<br>including the BUFGMUX and clock tree duty-cycle<br>distortion||All|–|±[1% of<br>CLKIN<br>period<br>+ 350]|–|±[1% of<br>CLKIN<br>period<br>+ 350]|ps|
|**Phase Alignment**(4)|||||||||
|CLKIN_CLKFB_PHASE|Phase offset between the CLKIN and CLKFB inputs||All|–|±150|–|±150|ps|
|CLKOUT_PHASE_DLL|Phase offset between DLL<br>outputs|CLK0 to CLK2X<br>(not CLK2X180)||–|±[1% of<br>CLKIN<br>period<br>+ 100]|–|±[1% of<br>CLKIN<br>period<br>+ 100]|ps|
|||All others||–|±[1% of<br>CLKIN<br>period<br>+ 150]|–|±[1% of<br>CLKIN<br>period<br>+ 150]|ps|
|**Lock Time**|||||||||
|LOCK_DLL(3)|When using the DLL alone:<br>The time from deassertion at<br>the DCM’s Reset input to the<br>rising transition at its LOCKED<br>output. When the DCM is<br>locked, the CLKIN and CLKFB<br>signals are in phase|5 MHz<<br> FCLKIN<<br>15 MHz|All|–|5|–|5|ms|
|||FCLKIN> 15 MHz||–|600|–|600|µs|



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

53 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

_Table  40:_ **Switching Characteristics for the DLL** _**(Cont’d)**_ 

|**Symbol**|**Description**|**Device**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|---|
||||**-5**||**-4**|||
||||**Min**|**Max**|**Min**|**Max**||
|**Delay Lines**||||||||
|DCM_DELAY_STEP(5)|Finest delay resolution, average over all taps|All|15|35|15|35|ps|



## **Notes:** 

1. The numbers in this table are based on the operating conditions set forth in Table 10 and Table 39. 

2. Indicates the maximum amount of output jitter that the DCM adds to the jitter on the CLKIN input. 

3. For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute. 

4. Some jitter and duty-cycle specifications include 1% of input clock period or 0.01 UI. For example, the data sheet specifies a maximum jitter of “±[1% of CLKIN period + 150]”. Assume the CLKIN frequency is 100 MHz. The equivalent CLKIN period is 10 ns and 1% of 10 ns is 0.1 ns or 100 ps. According to the data sheet, the maximum jitter is ±[100 ps + 150 ps] = ±250 ps. 

5. The typical delay step size is 23 ps. 

## **Digital Frequency Synthesizer (DFS)** 

_Table  41:_ **Recommended Operating Conditions for the DFS** 

|**Symbol**|**Symbol**|**Description**|**Description**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|---|---|
|||||**-5**||**-4**|||
|||||**Min**|**Max**|**Min**|**Max**||
|**Input Frequency Ranges**(2)|||||||||
|FCLKIN|CLKIN_FREQ_FX|Frequency for the CLKIN input||0.200|333(3)|0.200|333(3)|MHz|
|**Input Clock Jitter Tolerance**(4)|||||||||
|CLKIN_CYC_JITT_FX_LF||Cycle-to-cycle jitter at the<br>CLKIN input, based on CLKFX<br>output frequency|FCLKFX <<br> 150 MHz|–|±300|–|±300|ps|
|CLKIN_CYC_JITT_FX_HF|||FCLKFX> 150 MHz|–|±150|–|±150|ps|
|CLKIN_PER_JITT_FX||Period jitter at the CLKIN input||–|±1|–|±1|ns|



## **Notes:** 

1. DFS specifications apply when either of the DFS outputs (CLKFX or CLKFX180) are used. 

2. If both DFS and DLL outputs are used on the same DCM, follow the more restrictive CLKIN_FREQ_DLL specifications in Table 39. 

3. To support double the maximum effective FCLKIN limit, set the CLKIN_DIVIDE_BY_2 attribute to TRUE. This attribute divides the incoming clock frequency by two as it enters the DCM. 

4. CLKIN input jitter beyond these limits may cause the DCM to lose lock. 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

54 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

_Table  42:_ **Switching Characteristics for the DFS** 

|**Symbol**|**Description**|**Description**|**Device**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|---|---|
|||||**-5**||**-4**|||
|||||**Min**|**Max**|**Min**|**Max**||
|**Output Frequency Ranges**|||||||||
|CLKOUT_FREQ_FX|Frequency for the CLKFX and CLKFX180 outputs||All|5|350|5|320|MHz|
|**Output Clock Jitter(2)(3)**|||||||||
|CLKOUT_PER_JITT_FX|Period jitter at the CLKFX and<br>CLKFX180 outputs.|CLKIN<br>≤20 MHz|All|Typ|Max|Typ|Max||
|||||Use the Spartan-3A Jitter<br>Calculator:<br>www.xilinx.com/support/documenta<br>tion/data_sheets/s3a_jitter_calc.zip||||ps|
|||CLKIN<br>> 20 MHz||±[1% of<br>CLKFX<br>period<br>+ 100]|±[1% of<br>CLKFX<br>period<br>+ 200]|±[1% of<br>CLKFX<br>period<br>+ 100]|±[1% of<br>CLKFX<br>period<br>+ 200]|ps|
|**Duty Cycle(4)(5)**|||||||||
|CLKOUT_DUTY_CYCLE_FX|Duty cycle precision for the CLKFX and CLKFX180<br>outputs, including the BUFGMUX and clock tree<br>duty-cycle distortion||All|–|±[1% of<br>CLKFX<br>period<br>+ 350]|–|±[1% of<br>CLKFX<br>period<br>+ 350]|ps|
|**Phase Alignment**(5)|||||||||
|CLKOUT_PHASE_FX|Phase offset between the DFS CLKFX<br>output and the DLL CLK0 output when<br>both the DFS and DLL are used||All|–|±200|–|±200|ps|
|CLKOUT_PHASE_FX180|Phase offset between the DFS<br>CLKFX180 output and the DLL CLK0<br>output when both the DFS and DLL<br>are used||All|–|±[1% of<br>CLKFX<br>period<br>+ 200]|–|±[1% of<br>CLKFX<br>period<br>+ 200]|ps|
|**Lock Time**|||||||||
|LOCK_FX(2)|The time from deassertion at the<br>DCM’s Reset input to the rising<br>transition at its LOCKED output. The<br>DFS asserts LOCKED when the<br>CLKFX and CLKFX180 signals are<br>valid. If using both the DLL and the<br>DFS, use the longer locking time.|5 MHz<<br> FCLKIN<br><<br> 15 MHz|All|–|5|–|5|ms|
|||FCLKIN><br>15 MHz||–|450|–|450|µs|



## **Notes:** 

1. The numbers in this table are based on the operating conditions set forth in Table 10 and Table 41. 

2. For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute. 

3. Maximum output jitter is characterized within a reasonable noise environment (40 SSOs and 25% CLB switching) on an XC3S1400A FPGA. Output jitter strongly depends on the environment, including the number of SSOs, the output drive strength, CLB utilization, CLB switching activities, switching frequency, power supply and PCB design. The actual maximum output jitter depends on the system application. 

4. The CLKFX and CLKFX180 outputs always have an approximate 50% duty cycle. 

5. Some duty-cycle and alignment specifications include a percentage of the CLKFX output period. For example, the data sheet specifies a maximum CLKFX jitter of “±[1% of CLKFX period + 200]”. Assume the CLKFX output frequency is 100 MHz. The equivalent CLKFX period is 10 ns and 1% of 10 ns is 0.1 ns or 100 ps. According to the data sheet, the maximum jitter is ±[100 ps + 200 ps] = ±300 ps. 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

55 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

## **Phase Shifter (PS)** 

_Table  43:_ **Recommended Operating Conditions for the PS in Variable Phase Mode** 

|**Symbol**|**Description**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|
|||**-5**||**-4**|||
|||**Min**|**Max**|**Min**|**Max**||
|**Operating Frequency Ranges**|||||||
|PSCLK_FREQ (FPSCLK)|Frequency for the PSCLK input|1|167|1|167|MHz|
|**Input Pulse Requirements**|||||||
|PSCLK_PULSE|PSCLK pulse width as a percentage of the PSCLK period|40%|60%|40%|60%|%|



_Table  44:_ **Switching Characteristics for the PS in Variable Phase Mode** 

|**Symbol**|**Description**||**Phase Shift Amount**|**Units**|
|---|---|---|---|---|
|**Phase Shifting Range**|||||
|MAX_STEPS(2,3)|Maximum allowed number of<br>DCM_DELAY_STEP steps for a given<br>CLKIN clock period, where T = CLKIN<br>clock period in ns. If using<br>CLKIN_DIVIDE_BY_2 = TRUE, double<br>the clock effective clock period.|CLKIN < 60 MHz|±[INTEGER(10•(TCLKIN– 3 ns))]|steps|
|||CLKIN≥60 MHz|±[INTEGER(15•(TCLKIN– 3 ns))]||
|FINE_SHIFT_RANGE_MIN|Minimum guaranteed delay for variable phase shifting||±[MAX_STEPS•<br>DCM_DELAY_STEP_MIN]|ns|
|FINE_SHIFT_RANGE_MAX|Maximum guaranteed delay for variable phase shifting||±[MAX_STEPS•<br>DCM_DELAY_STEP_MAX]|ns|



## **Notes:** 

1. The numbers in this table are based on the operating conditions set forth in Table 10 and Table 43. 

2. The maximum variable phase shift range, MAX_STEPS, is only valid when the DCM is has no initial fixed phase shifting, that is, the PHASE_SHIFT attribute is set to 0. 

3. The DCM_DELAY_STEP values are provided at the bottom of Table 40. 

## **Miscellaneous DCM Timing** 

_Table  45:_ **Miscellaneous DCM Timing** 

|_Table  45:_ **Miscellaneous DCM**|**Timing**||||
|---|---|---|---|---|
|**Symbol**|**Description**|**Min**|**Max**|**Units**|
|DCM_RST_PW_MIN|Minimum duration of a RST pulse width|3|–|CLKIN<br>cycles|
|DCM_RST_PW_MAX(2)|Maximum duration of a RST pulse width|N/A|N/A|seconds|
|||N/A|N/A|seconds|
|DCM_CONFIG_LAG_TIME(3)|Maximum duration from VCCINTapplied to FPGA configuration<br>successfully completed (DONE pin goes High) and clocks<br>applied to DCM DLL|N/A|N/A|minutes|
|||N/A|N/A|minutes|



## **Notes:** 

1. This limit only applies to applications that use the DCM DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV). The DCM DFS outputs (CLKFX, CLKFX180) are unaffected. 

2. This specification is equivalent to the Virtex™-4 FPGA DCM_RESET specification. This specification does not apply for Spartan-3AN FPGAs. 

3. This specification is equivalent to the Virtex-4 FPGA TCONFIG specification. This specification does not apply for Spartan-3AN FPGAs. 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

56 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

## **DNA Port Timing** 

_Table  46:_ **DNA_PORT Interface Timing** 

|**Symbol**|**Description**|**Min**|**Max**|**Units**|
|---|---|---|---|---|
|TDNASSU|Setup time on SHIFT before the rising edge of CLK|1.0|–|ns|
|TDNASH|Hold time on SHIFT after the rising edge of CLK|0.5|–|ns|
|TDNADSU|Setup time on DIN before the rising edge of CLK|1.0|–|ns|
|TDNADH|Hold time on DIN after the rising edge of CLK|0.5|–|ns|
|TDNARSU|Setup time on READ before the rising edge of CLK|5.0|10,000|ns|
|TDNARH|Hold time on READ after the rising edge of CLK|0|–|ns|
|TDNADCKO|Clock-to-output delay on DOUT after rising edge of CLK|0.5|1.5|ns|
|TDNACLKF|CLK frequency|0|100|MHz|
|TDNACLKH|CLK High time|1.0|∞|ns|
|TDNACLKL|CLK Low time|1.0|∞|ns|



## **Notes:** 

1. The minimum READ pulse width is 5 ns, the maximum READ pulse width is 10 µs. 

## **Internal SPI Access Port Timing** 

_Table  47:_ **SPI_ACCESS Interface Timing** 

|**Symbol**|**Description**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Speed Grade**|**Units**|
|---|---|---|---|---|---|---|
|||**-5**||**-4**|||
|||**Min**|**Max**|**Min**|**Max**||
|TSPICCK_MOSI|Setup time on MOSI before the active edge of CLK|4.47|–|5.0|–|ns|
|TSPICKC_MOSI|Hold time on MOSI after the active edge of CLK|4.03|–|4.5|–|ns|
|TCSB|CSB High time|50|–|50|–|ns|
|TSPICCK_CSB|Setup time on CSB before the active edge of CLK|7.15|–|8.0|–|ns|
|TSPICCK_CSB|Hold time on CSB after the active edge of CLK|7.15|–|8.0|–|ns|
|TSPICKO_MISO|Clock-to-output delay on MISO after active edge of CLK|–|14.3|–|16.0|ns|
|FSPICLK|CLK frequency|–|50|–|50|MHz|
|FSPICAR1|CLK frequency for Continuous Array Read command|–|50|–|50|MHz|
|FSPICAR1|CLK frequency for Continuous Array Read command,<br>reduced initial latency|–|33|–|33|MHz|
|TSPICLKL|CLK High time|–|∞|–|∞|ns|
|TSPICLKH|CLK Low time|6.8|∞|6.8|∞|ns|



## **Notes:** 

1. For details on using SPI_ACCESS and the In-System Flash memory, see UG333 _Spartan-3AN FPGA In-System Flash User Guide_ . 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

57 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

## **In-System Flash (ISF) Memory Timing** 

_Table  48:_ **In-System Flash (ISF) Memory Operations** 

|**Symbol**|**Description**|**Device**|**Typical(1)**|**Max**|**Units**|
|---|---|---|---|---|---|
|TXFER|Page to Buffer transfer time|All|–|400|µs|
|TCOMP|Page to Buffer compare time|All|–|400|µs|
|TPP|Page Programming time|XC3S50AN<br>XC3S200AN<br>XC3S400AN|2|4|ms|
|||XC3S700AN<br>XC3S1400AN|3|6|ms|
|TPE|Page Erase time|XC3S50AN<br>XC3S200AN<br>XC3S400AN|13|32|ms|
|||XC3S700AN(2)<br>XC3S1400AN|15|35|ms|
|TPEP|Page Erase and Programming time|XC3S50AN<br>XC3S200AN<br>XC3S400AN<br>XC3S700AN(3)|14|35|ms|
|||XC3S1400AN|17|40|ms|
|TBE|Block Erase time|XC3S50AN|15|35|ms|
|||XC3S200AN<br>XC3S400AN|30|75|ms|
|||XC3S700AN<br>XC3S1400AN|45|100|ms|
|TSE|Sector Erase time|XC3S50AN|0.8|2.5|s|
|||XC3S200AN<br>XC3S400AN<br>XC3S700AN<br>XC3S1400AN|1.6|5|s|



## **Notes:** 

1. Typical values can vary with process and other conditions. 

2. XC3S700AN TPE maximum is 50 ms for Flash devices manufactured using the UMC process. For more information, see the Xilinx customer notice XCN14003: _Flash Wafer Fabrication Change and Gold (Au) To Copper (Cu) Transition for Spartan-3AN FPGA Devices_ . 

3. XC3S700AN TPEP maximum is 55 ms for Flash devices manufactured using the UMC process. For more information, see the Xilinx customer notice XCN14003: _Flash Wafer Fabrication Change and Gold (Au) To Copper (Cu) Transition for Spartan-3AN FPGA Devices_ . 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

58 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

## **Suspend Mode Timing** 

**==> picture [478 x 227] intentionally omitted <==**

**----- Start of picture text -----**<br>
Entering Suspend Mode Exiting Suspend Mode<br>sw_gwe_cycle<br>sw_gts_cycle<br>SUSPEND Input<br>t t<br>SUSPENDHIGH_AWAKE SUSPENDLOW_AWAKE<br>AWAKE Output<br>tSUSPEND_GWE tAWAKE_GWE<br>Flip-Flops, Block RAM,<br>Write Protected<br>Distributed RAM<br>t t<br>SUSPEND_GTS AWAKE_GTS<br>FPGA Outputs Defined by SUSPEND constraint<br>t t<br>SUSPEND_DISABLE SUSPEND_ENABLE<br>FPGA Inputs,<br>Blocked<br>Interconnect<br>DS610-3_08_061207<br>**----- End of picture text -----**<br>


_Figure 12:_ **Suspend Mode Timing** 

_Table  49:_ **Suspend Mode Timing Parameters** 

|**Symbol**|**Description**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|
|**Entering Suspend Mode**||||||
|TSUSPENDHIGH_AWAKE|Rising edge of SUSPEND pin to falling edge of AWAKE pin without glitch filter<br>(**_suspend_filter:No_**)|–|7|–|ns|
|TSUSPENDFILTER|Adjustment to SUSPEND pin rising edge parameters when glitch filter enabled<br>(**_suspend_filter:Yes_**)|+160|+300|+600|ns|
|TSUSPEND_GTS|Rising edge of SUSPEND pin until FPGA output pins drive their defined<br>SUSPEND constraint behavior|–|10|–|ns|
|TSUSPEND_GWE|Rising edge of SUSPEND pin to write-protect lock on all writable clocked<br>elements|–|< 5|–|ns|
|TSUSPEND_DISABLE|Rising edge of the SUSPEND pin to FPGA input pins and interconnect<br>disabled|–|340|–|ns|
|**Exiting Suspend Mode**||||||
|TSUSPENDLOW_AWAKE|Falling edge of the SUSPEND pin to rising edge of the AWAKE pin<br>Does not include DCM lock time|–|4 to 108|–|µs|
|TSUSPEND_ENABLE|Falling edge of the SUSPEND pin to FPGA input pins and interconnect<br>re-enabled|–|3.7 to 109|–|µs|
|TAWAKE_GWE1|Rising edge of the AWAKE pin until write-protect lock released on all writable<br>clocked elements, using**_sw_clk:InternalClock_**and**_sw_gwe_cycle:1_**|–|67|–|ns|
|TAWAKE_GWE512|Rising edge of the AWAKE pin until write-protect lock released on all writable<br>clocked elements, using**_sw_clk:InternalClock_**and**_sw_gwe_cycle:512_**|–|14|–|µs|
|TAWAKE_GTS1|Rising edge of the AWAKE pin until outputs return to the behavior described<br>in the FPGA application, using**_sw_clk:InternalClock_**and**_sw_gts_cycle:1_**|–|57|–|ns|
|TAWAKE_GTS512|Rising edge of the AWAKE pin until outputs return to the behavior described<br>in the FPGA application, using**_sw_clk:InternalClock_**and**_sw_gts_cycle:512_**|–|14|–|µs|



## **Notes:** 

1. These parameters based on characterization. 

2. For information on using the Spartan-3AN Suspend feature, see XAPP480: _Using Suspend Mode in Spartan-3 Generation FPGAs_ . 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

59 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

## **Configuration and JTAG Timing** 

## **General Configuration Power-On/Reconfigure Timing** 

**==> picture [462 x 184] intentionally omitted <==**

**----- Start of picture text -----**<br>
VCCINT 1.2V<br>(Supply) 1.0V<br>VCCAUX 3.3V<br>(Supply) 2.0V<br>VCCO Bank 2 2.5V<br>(Supply) 2.0V 3.3Vor<br>T<br>POR<br>PROG_B<br>(Input)<br>TPROG TPL<br>INIT_B<br>(Open-Drain)<br>T<br>ICCK<br>CCLK<br>(Output)<br>DS557-3_01_052908<br>**----- End of picture text -----**<br>


## **Notes:** 

1. When configuring from the In-System Flash, VCCAUX must be in the recommended operating range; on power-up make sure VCCAUX reaches at least 3.0V before INIT_B goes High to indicate the start of configuration. VCCINT, VCCAUX, and VCCO supplies to the FPGA can be applied in any order if this requirement is met. 

2. The Low-going pulse on PROG_B is optional after power-on but necessary for reconfiguration without a power cycle. 

3. The rising edge of INIT_B samples the voltage levels applied to the mode pins (M0 - M2). 

_Figure 13:_ **Waveforms for Power-On and the Beginning of Configuration** 

_Table  50:_ **Power-On Timing and the Beginning of Configuration** 

|**Symbol**|**Description**|**Device**|**All Speed Grades**|**All Speed Grades**|**Units**|
|---|---|---|---|---|---|
||||**Min**|**Max**||
|TPOR(2)|The time from the application of VCCINT, VCCAUX, and VCCO<br>Bank 2 supply voltage ramps (whichever occurs last) to the<br>rising transition of the INIT_B pin|All|–|18|ms|
|TPROG|The width of the low-going pulse on the PROG_B pin|All|0.5|–|µs|
|TPL(2)|The time from the rising edge of the PROG_B pin to the<br>rising transition on the INIT_B pin|XC3S50AN|–|0.5|ms|
|||XC3S200AN|–|0.5|ms|
|||XC3S400AN|–|1|ms|
|||XC3S700AN|–|2|ms|
|||XC3S1400AN|–|2|ms|
|TINIT|Minimum Low pulse width on INIT_B output|All|250|–|ns|
|TICCK(3)|The time from the rising edge of the INIT_B pin to the<br>generation of the configuration clock signal at the CCLK<br>output pin|All|0.5|4|µs|



## **Notes:** 

1. The numbers in this table are based on the operating conditions set forth in Table 10. This means power must be applied to all VCCINT, VCCO, and VCCAUX lines. 

2. Power-on reset and the clearing of configuration memory occurs during this period. 

3. This specification applies only to the Master Serial, SPI, and BPI modes. 

4. For details on configuration, see UG332 _Spartan-3 Generation Configuration User Guide_ . 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

60 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

## **Configuration Clock (CCLK) Characteristics** 

_Table  51:_ **Master Mode CCLK Output Period by** _**ConfigRate**_ **Option Setting** 

|**Symbol**|**Description**|**_ConfigRate_**<br>**Setting**(1)|**Temperature**<br>**Range**|**Minimum**|**Maximum**|**Units**|
|---|---|---|---|---|---|---|
|TCCLK1|CCLK clock period by<br>**_ConfigRate_**setting|1<br>_(power-on value)_|Commercial|1,254|2,500|ns|
||||Industrial|1,180||ns|
|TCCLK3||3|Commercial|413|833|ns|
||||Industrial|390||ns|
|TCCLK6||6<br>(_default_)|Commercial|207|417|ns|
||||Industrial|195||ns|
|TCCLK7||7|Commercial|178|357|ns|
||||Industrial|168||ns|
|TCCLK8||8|Commercial|156|313|ns|
||||Industrial|147||ns|
|TCCLK10||10|Commercial|123|250|ns|
||||Industrial|116||ns|
|TCCLK12||12|Commercial|103|208|ns|
||||Industrial|97||ns|
|TCCLK13||13|Commercial|93|192|ns|
||||Industrial|88||ns|
|TCCLK17||17|Commercial|72|147|ns|
||||Industrial|68||ns|
|TCCLK22||22|Commercial|54|114|ns|
||||Industrial|51||ns|
|TCCLK25||25|Commercial|47|100|ns|
||||Industrial|45||ns|
|TCCLK27||27|Commercial|44|93|ns|
||||Industrial|42||ns|
|TCCLK33||33|Commercial|36|76|ns|
||||Industrial|34||ns|
|TCCLK44||44|Commercial|26|57|ns|
||||Industrial|25||ns|
|TCCLK50||50|Commercial|22|50|ns|
||||Industrial|21||ns|
|TCCLK100||100|Commercial|11.2|25|ns|
||||Industrial|10.6||ns|



## **Notes:** 

1. Set the _**ConfigRate**_ option value when generating a configuration bitstream. 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

61 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

_Table  52:_ **Master Mode CCLK Output Frequency by** _**ConfigRate**_ **Option Setting** 

|**Symbol**|**Description**|**_ConfigRate_**<br>**Setting**|**Temperature**<br>**Range**|**Minimum**|**Maximum**|**Units**|
|---|---|---|---|---|---|---|
|FCCLK1|Equivalent CCLK clock frequency<br>by**_ConfigRate_**setting|1<br>_(power-on value)_|Commercial|0.400|0.797|MHz|
||||Industrial||0.847|MHz|
|FCCLK3||3|Commercial|1.20|2.42|MHz|
||||Industrial||2.57|MHz|
|FCCLK6||6<br>(_default_)|Commercial|2.40|4.83|MHz|
||||Industrial||5.13|MHz|
|FCCLK7||7|Commercial|2.80|5.61|MHz|
||||Industrial||5.96|MHz|
|FCCLK8||8|Commercial|3.20|6.41|MHz|
||||Industrial||6.81|MHz|
|FCCLK10||10|Commercial|4.00|8.12|MHz|
||||Industrial||8.63|MHz|
|FCCLK12||12|Commercial|4.80|9.70|MHz|
||||Industrial||10.31|MHz|
|FCCLK13||13|Commercial|5.20|10.69|MHz|
||||Industrial||11.37|MHz|
|FCCLK17||17|Commercial|6.80|13.74|MHz|
||||Industrial||14.61|MHz|
|FCCLK22||22|Commercial|8.80|18.44|MHz|
||||Industrial||19.61|MHz|
|FCCLK25||25|Commercial|10.00|20.90|MHz|
||||Industrial||22.23|MHz|
|FCCLK27||27|Commercial|10.80|22.39|MHz|
||||Industrial||23.81|MHz|
|FCCLK33||33|Commercial|13.20|27.48|MHz|
||||Industrial||29.23|MHz|
|FCCLK44||44|Commercial|17.60|37.60|MHz|
||||Industrial||40.00|MHz|
|FCCLK50||50|Commercial|20.00|44.80|MHz|
||||Industrial||47.66|MHz|
|FCCLK100||100|Commercial|40.00|88.68|MHz|
||||Industrial||94.34|MHz|



_Table  53:_ **Master Mode CCLK Output Minimum Low and High Time** 

|**Symbol**|**Description**|**Description**|**_ConfigRate_ Setting**|**_ConfigRate_ Setting**|**_ConfigRate_ Setting**|**_ConfigRate_ Setting**|**_ConfigRate_ Setting**|**_ConfigRate_ Setting**|**_ConfigRate_ Setting**|**_ConfigRate_ Setting**|**_ConfigRate_ Setting**|**_ConfigRate_ Setting**|**_ConfigRate_ Setting**|**_ConfigRate_ Setting**|**_ConfigRate_ Setting**|**_ConfigRate_ Setting**|**_ConfigRate_ Setting**|**_ConfigRate_ Setting**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||||**1**|**3**|**6**|**7**|**8**|**10**|**12**|**13**|**17**|**22**|**25**|**27**|**33**|**44**|**50**|**100**||
|TMCCL,<br>TMCCH|Master Mode<br>CCLK<br>Minimum<br>Low and High<br>Time|Commercial|595|196|98.3|84.5|74.1|58.4|48.9|44.1|34.2|25.6|22.3|20.9|17.1|12.3|10.4|5.3|ns|
|||Industrial|560|185|92.6|79.8|69.8|55.0|46.0|41.8|32.3|24.2|21.4|20.0|16.2|11.9|10.0|5.0|ns|



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

62 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

_Table  54:_ **Slave Mode CCLK Input Low and High Time** 

|**Symbol**|**Description**|**Description**|||**Min**|**Min**|**Max**|**Max**|**Units**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|
|TSCCL,<br>TSCCH|CCLK Low and High time||||5||∞||ns||
|**Master Serial and Slave Serial Mode Timing**<br>X-Ref Target - Figure 14<br>_Figure 14:_ **Waveforms for Master Serial and Slave Serial Configuration**<br>_Table  55:_ **Timing for the Master Serial and Slave Serial Configuration Modes**<br>DS312-3_05_103105<br>Bit 0<br>Bit 1<br>Bit n<br>Bit n+1<br>Bit n-64<br>Bit n-63<br>1/FCCSER<br>TSCCL<br>TDCC<br>TCCD<br>TSCCH<br>TCCO<br>**PROG_B**<br>(Input)<br>**DIN**<br>(Input)<br>**DOUT**<br>(Output)<br>(Open-Drain)<br>**INIT_B**<br>(Input/Output)<br>**CCLK**<br>TMCCL<br>TMCCH|||||||||||
||||||T<br>TMCCH||||||
||||T<br>TMCCL||||||||
||||Bit n<br>Bit n+1<br>Bit n-64<br>Bit n-63<br>1/FCCSER<br>SCCL<br>SCCH<br>TCCO||||||||
||||DS312-3_05_103105||||||||
|**Symbol**|**Description**|||**Slave/**<br>**Master**||**All Speed Grades**||||**Units**|
|||||||**Min**||**Max**|||
|**Clock-to-Output Times**|||||||||||
|TCCO|The time from the falling transition on the CCLK pin to data appearing at the<br>DOUT pin|||Both||1.5||10||ns|
|**Setup Times**|||||||||||
|TDCC|The time from the setup of data at the DIN pin to the rising transition at the<br>CCLK pin|||Both||7||–||ns|
|**Hold Times**|||||||||||
|TCCD|The time from the rising transition at the CCLK pin to the point when data is<br>last held at the DIN pin|||Master||0||–||ns|
|||||Slave||1.0|||||
|**Clock Timing**|||||||||||
|TCCH|High pulse width at the CCLK input pin|||Master||SeeTable 53|||||
|||||Slave||SeeTable 54|||||
|TCCL|Low pulse width at the CCLK input pin|||Master||SeeTable 53|||||
|||||Slave||SeeTable 54|||||
|FCCSER|Frequency of the clock signal at the<br>CCLK input pin(2)|No bitstream compression||Slave||0||100||MHz|
|||With bitstream compression||||0||100||MHz|



## **Notes:** 

1. The numbers in this table are based on the operating conditions set forth in Table 10. 

2. For serial configuration with a daisy-chain of multiple FPGAs, the maximum limit is 25 MHz. 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

63 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

## **Slave Parallel Mode Timing** 

**==> picture [538 x 253] intentionally omitted <==**

**----- Start of picture text -----**<br>
PROG_B<br>(Input)<br>INIT_B<br>(Open-Drain)<br>TSMCSCC TSMCCCS<br>CSI_B<br>(Input)<br>T<br>SMCCW T<br>SMWCC<br>RDWR_B<br>(Input)<br>TMCCH TMCCL<br>TSCCH TSCCL<br>CCLK<br>(Input)<br>TSMDCC TSMCCD 1/FCCPAR<br>D0 - D7<br>Byte 0 Byte 1 Byte n Byte n+1<br>(Inputs)<br>DS529-3_02_051607<br>**----- End of picture text -----**<br>


## **Notes:** 

1. It is possible to abort configuration by pulling CSI_B Low in a given CCLK cycle, then switching RDWR_B Low or High in any subsequent cycle for which CSI_B remains Low. The RDWR_B pin asynchronously controls the driver impedance of the D0–D7 bus. When RDWR_B switches High, be careful to avoid contention on the D0–D7 bus. 

2. To pause configuration, pause CCLK instead of de-asserting CSI_B. See UG332, Chapter 7, section “Non-Continuous SelectMAP Data Loading” for more details. 

_Figure 15:_ **Waveforms for Slave Parallel Configuration** 

_Table  56:_ **Timing for the Slave Parallel Configuration Mode** 

|**Symbol**|**Description**|**Description**|**All Speed Grades**|**All Speed Grades**|**Units**|
|---|---|---|---|---|---|
||||**Min**|**Max**||
|**Setup Times**||||||
|TSMDCC|The time from the setup of data at the D0-D7 pins to the rising transition at the CCLK pin||7|–|ns|
|TSMCSCC|Setup time on the CSI_B pin before the rising transition at the CCLK pin||7|–|ns|
|TSMCCW(2)|Setup time on the RDWR_B pin before the rising transition at the CCLK pin||15|–|ns|
|**Hold Times**||||||
|TSMCCD|The time from the rising transition at the CCLK pin to the point when data is last held at<br>the D0-D7 pins||1.0|–|ns|
|TSMCCCS|The time from the rising transition at the CCLK pin to the point when a logic level is last<br>held at the CSO_B pin||0|–|ns|
|TSMWCC|The time from the rising transition at the CCLK pin to the point when a logic level is last<br>held at the RDWR_B pin||0|–|ns|
|**Clock Timing**||||||
|TCCH|The High pulse width at the CCLK input pin||5|–|ns|
|TCCL|The Low pulse width at the CCLK input pin||5|–|ns|
|FCCPAR|Frequency of the clock signal<br>at the CCLK input pin|No bitstream compression|0|80|MHz|
|||With bitstream compression|0|80|MHz|



## **Notes:** 

1. The numbers in this table are based on the operating conditions set forth in Table 10. 

2. Some Xilinx documents refer to Parallel modes as SelectMAP modes. 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

64 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

## **External Serial Peripheral Interface (SPI) Configuration Timing** 

**==> picture [535 x 372] intentionally omitted <==**

**----- Start of picture text -----**<br>
PROG_B<br>(Input)<br>PUDC_B PUDC_B must be stable before INIT_B goes High and constant throughout the configuration process.<br>(Input)<br>VS[2:0] <1:1:1><br>(Input) Mode input pins M[2:0] and variant select input pins VS[2:0] are sampled when INIT_B<br>goes High.  After this point, input values do not matter until DONE goes High, at which<br>point these pins become user-I/O pins.<br>M[2:0] <0:0:1><br>(Input)<br>T T<br>MINIT INITM<br>INIT_B<br>(Open-Drain) New  ConfigRate  active<br>T T TMCCL n TCCLK n<br>TCCLK1 MCCL1 MCCH1 TCCLK1 TMCCH n<br>CCLK<br>TV<br>DIN<br>Data Data Data Data<br>(Input)<br>TCSS<br>TDCC<br>CSO_B TCCD<br>TCCO<br>Command Command<br>MOSI (msb) (msb-1)<br>TDSU TDH<br>Pin initially pulled High by internal pull-up resistor if PUDC_B input is Low.<br>Pin initially high-impedance (Hi-Z) if PUDC_B input is High. External pull-up resistor required on CSO_B.<br>**----- End of picture text -----**<br>


Shaded values indicate specifications on attached SPI Flash PROM. 

DS529-3_06_102506 

_Figure 16:_ **Waveforms for External Serial Peripheral Interface (SPI) Configuration** 

_Table  57:_ **Timing for External Serial Peripheral Interface (SPI) Configuration Mode** 

|**Symbol**|**Description**|**Minimum**|**Maximum**|**Units**|
|---|---|---|---|---|
|TCCLK1|Initial CCLK clock period|SeeTable 51|||
|TCCLK_n_|CCLK clock period after FPGA loads**_ConfigRate_**bitstream option setting|SeeTable 51|||
|TMINIT|Setup time on VS[2:0] variant-select pins and M[2:0] mode pins before the<br>rising edge of INIT_B|50|–|ns|
|TINITM|Hold time on VS[2:0] variant-select pins and M[2:0] mode pins after the<br>rising edge of INIT_B|0|–|ns|
|TCCO|MOSI output valid delay after CCLK falling clock edge|SeeTable 55|||
|TDCC|Setup time on the DIN data input before CCLK rising clock edge|SeeTable 55|||
|TCCD|Hold time on the DIN data input after CCLK rising clock edge|SeeTable 55|||



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

65 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

_Table  58:_ **Configuration Timing Requirements for Attached SPI Serial Flash** 

|**Symbol**|**Description**|**Requirement**|**Units**|
|---|---|---|---|
|TCCS|SPI serial Flash PROM chip-select time|_TCCS_<br>_TMCCL_1<br>_TCCO_<br>–<br>≤|ns|
|TDSU|SPI serial Flash PROM data input setup time|_TDSU_<br>_TMCCL_1<br>_TCCO_<br>–<br>≤|ns|
|TDH|SPI serial Flash PROM data input hold time|_TDH_<br>_TMCCH_1<br>≤|ns|
|TV|SPI serial Flash PROM data clock-to-output time|_TV_<br>_TMCCLn_<br>_TDCC_<br>–<br>≤|ns|
|fCor fR|Maximum SPI serial Flash PROM clock frequency (also depends on<br>specific read command used)|_fC_<br>1<br>_TCCLKn min_<br>(<br>)<br>---------------------------------<br>≥|MHz|



## **Notes:** 

1. These requirements are for successful FPGA configuration in SPI mode, where the FPGA generates the CCLK signal. The post-configuration timing can be different to support the specific needs of the application loaded into the FPGA. 

2. Subtract additional printed circuit board routing delay as required by the application. 

## **Byte Peripheral Interface (BPI) Configuration Timing** 

**==> picture [527 x 367] intentionally omitted <==**

**----- Start of picture text -----**<br>
PROG_B<br>(Input)<br>PUDC_B PUDC_B must be stable before INIT_B goes High and constant throughout the configuration process.<br>(Input)<br>Mode input pins M[2:0] are sampled when INIT_B goes High.  After this point,<br>M[2:0]<br><0:1:0> input values do not matter until DONE goes High, at which point the mode pins<br>(Input)<br>become user-I/O pins.<br>TMINIT TINITM<br>INIT_B<br>(Open-Drain)<br>Pin initially pulled High by internal pull-up resistor if PUDC_B input is Low.<br>Pin initially high-impedance (Hi-Z) if PUDC_B input is High.<br>LDC[2:0]<br>HDC<br>CSO_B New  ConfigRate  active<br>TINITADDR TCCLK1 TCCLK n<br>T<br>CCLK1<br>CCLK<br>TCCO<br>A[25:0] 000_0000 000_0001 Address Address Address<br>TAVQV TDCC TCCD<br>D[7:0] Byte 0 Byte 1 Data Data Data Data<br>(Input)<br>Shaded values indicate specifications on attached parallel NOR Flash PROM.<br>DS557-3_16_032009<br>**----- End of picture text -----**<br>


_Figure 17:_ **Waveforms for Byte-wide Peripheral Interface (BPI) Configuration** 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

66 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

_Table  59:_ **Timing for Byte-wide Peripheral Interface (BPI) Configuration Mode** 

|**Symbol**|**Description**|**Minimum**|**Maximum**|**Units**|
|---|---|---|---|---|
|TCCLK1|Initial CCLK clock period|SeeTable 51|||
|TCCLK_n_|CCLK clock period after FPGA loads ConfigRate setting|SeeTable 51|||
|TMINIT|Setup time on M[2:0] mode pins before the rising edge of INIT_B|50|–|ns|
|TINITM|Hold time on M[2:0] mode pins after the rising edge of INIT_B|0|–|ns|
|TINITADDR|Minimum period of initial A[25:0] address cycle; LDC[2:0] and HDC are asserted<br>and valid|5|5|TCCLK1<br>cycles|
|TCCO|Address A[25:0] outputs valid after CCLK falling edge|SeeTable 55|||
|TDCC|Setup time on D[7:0] data inputs before CCLK rising edge|See TSMDCCinTable 56|||
|TCCD|Hold time on D[7:0] data inputs after CCLK rising edge|0|–|ns|



_Table  60:_ **Configuration Timing Requirements for Attached Parallel NOR Flash** 

|**Symbol**|**Description**|**Requirement**|**Units**|
|---|---|---|---|
|TCE<br>(tELQV)|Parallel NOR Flash PROM chip-select time|_TCE_<br>_TINITADDR_<br>≤|ns|
|TOE<br>(tGLQV)|Parallel NOR Flash PROM output-enable time|_TOE_<br>_TINITADDR_<br>≤|ns|
|TACC<br>(tAVQV)|Parallel NOR Flash PROM read access time|_TACC_<br>0.5_TCCLKn min_<br>(<br>)<br>_TCCO_<br>_TDCC_<br>_PCB_<br>–<br>–<br>–<br>≤|ns|
|TBYTE<br>(tFLQV,tFHQV)|For x8/x16 PROMs only: BYTE# to output valid time(3)|_TBYTE_<br>_TINITADDR_<br>≤|ns|



## **Notes:** 

1. These requirements are for successful FPGA configuration in BPI mode, where the FPGA generates the CCLK signal. The post-configuration timing can be different to support the specific needs of the application loaded into the FPGA. 

2. Subtract additional printed circuit board routing delay as required by the application. 

3. The initial BYTE# timing can be extended using an external, appropriately sized pull-down resistor on the FPGA’s LDC2 pin. The resistor value also depends on whether the FPGA’s PUDC_B pin is High or Low. 

## **IEEE 1149.1/1532 JTAG Test Access Port Timing** 

**==> picture [468 x 192] intentionally omitted <==**

**----- Start of picture text -----**<br>
TCCH TCCL<br>TCK<br>(Input)<br>TTMSTCK TTCKTMS 1/FTCK<br>TMS<br>(Input)<br>TTDITCK TTCKTDI<br>TDI<br>(Input)<br>TTCKTDO<br>TDO<br>(Output)<br>DS557_13_083110<br>**----- End of picture text -----**<br>


_Figure 18:_ **JTAG Waveforms** 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

67 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

_Table  61:_ **Timing for the JTAG**[(2)] **Test Access Port** 

|_Table  61:_|**Timing for the JTAG**(2)**Test Access Port**|**Timing for the JTAG**(2)**Test Access Port**||||
|---|---|---|---|---|---|
|**Symbol**|**Description**||**All Speed**<br>**Grades**||**Units**|
||||**Min**|**Max**||
|**Clock-to-Output Times**||||||
|TTCKTDO|The time from the falling transition on the TCK pin to data appearing at the TDO pin||1.0|11.0|ns|
|**Setup Times**||||||
|TTDITCK|The time from the setup of data at the<br>TDI pin to the rising transition at the<br>TCK pin|All devices and functions except those shown below|7.0|–|ns|
|||Boundary-Scan commands (INTEST, EXTEST,<br>SAMPLE) on XC3S700AN and XC3S1400AN FPGAs|11.0|||
|TTMSTCK|The time from the setup of a logic level at the TMS pin to the rising transition at the TCK pin||7.0|–|ns|
|**Hold Times**||||||
|TTCKTDI|The time from the rising transition at<br>the TCK pin to the point when data is<br>last held at the TDI pin|All functions except those shown below|0|–|ns|
|||Configuration commands (CFG_IN, ISC_PROGRAM)|2.0|||
|TTCKTMS|The time from the rising transition at the TCK pin to the point when a logic level is last held at the<br>TMS pin||0|–|ns|
|**Clock Timing**||||||
|TCCH|The High pulse width at the TCK pin|All functions except ISC_DNA command|5|–|ns|
|TCCL|The Low pulse width at the TCK pin||5|–|ns|
|TCCHDNA|The High pulse width at the TCK pin|During ISC_DNA command|10|10,000|ns|
|TCCLDNA|The Low pulse width at the TCK pin||10|10,000|ns|
|FTCK|Frequency of the TCK signal|All operations on XC3S50AN, XC3S200AN, and<br>XC3S400AN FPGAs and for BYPASS or HIGHZ<br>instructions on all FPGAs|0|33|MHz|
|||All operations on XC3S700AN and XC3S1400AN<br>FPGAs, except for BYPASS or HIGHZ instructions||20||



## **Notes:** 

1. The numbers in this table are based on the operating conditions set forth in Table 10. 

2. For details on JTAG, see Chapter 9, “JTAG Configuration Mode and Boundary-Scan” in UG332 _Spartan-3 Generation Configuration User Guide_ . 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

68 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

## **Revision History** 

The following table shows the revision history for this document. 

|**Date**|**Version**|**Revision**|
|---|---|---|
|02/26/2007|1.0|Initial release.|
|08/16/2007|2.0|Updated for Production release of initial device (XC3S200AN). Timing specifications updated for v1.38<br>speed files. DC specifications updated with production values. Other changes throughout.|
|08/31/2007|2.0.1|Updated for Production release of XC3S1400AN. Improved tPEPfor XC3S700AN inTable 48.|
|09/12/2007|2.0.2|Updated for Production release of XC3S700AN.|
|09/24/2007|2.1|Updated for Production release of XC3S400AN. UpdatedSoftware Version Requirementsto note that<br>Production speed files are available as of Service Pack 3. Removed PCIX IOSTANDARD due to limited<br>PCIX interface support. Added note that SPI_ACCESS (In-System Flash) is not currently supported in<br>simulation.|
|12/12/2007|3.0|Updated to Production status with Production release of final family member, XC3S50AN. Noted that<br>SPI_ACCESS simulation is supported in ISE 10.1 software. Removed DNA_RETENTION limit of 10<br>years inTable 17since number of Read cycles is the only unique limit. Updated Setup, Hold, and<br>Propagation Times for the IOB Input Path to show values by device inTable 23andTable 25. Increased<br>SSO recommendation for SSTL18_II inTable 32. UpdatedFigure 17andTable 59to show BPI data<br>synchronous to CCLK rising edge. Updated links.|
|06/02/2008|3.1|Improved VCCAUXT and VCCO2T POR minimum inTable 7and updated VCCO POR levels inFigure 13.<br>Clarified power sequencing in Note1ofTable 7,Table 8, andFigure 13. Added VINto Recommended<br>Operating Conditions inTable 10and added reference to XAPP459<br>,“Eliminating I/O Coupling Effects<br>when Interfacing Large-Swing Single-Ended Signals to User I/O Pins.” Reduced typical ICCINTQand<br>ICCAUXQquiescent current values by 12%-58% inTable 12. Noted latest speed file v1.39 in ISE 10.1<br>software inTable 19. Added reference to Sample Window inTable 24. Changed Internal SPI interface<br>max frequency to 50 MHz and updated other Internal SPI timing parameters to match names and<br>values from speed file inTable 47. Restored Units column toTable 49. Updated CCLK output maximum<br>period inTable 51to match minimum frequency inTable 52. Added references to User Guides.|
|11/19/2009|3.2|Updated selected I/O standard DC characteristics. Changed typical quiescent current temperature<br>from ambient to junction. Removed references to older software versions. Updated column 3 header<br>ofTable 17andTable 18. Added table note toTable 18. Added TIOPIand TIOPIDpropagation times in<br>Table 25. Updated TIOCKHZand TIOCKONsynchronous output enable/disable times inTable 28.<br>Removed VREFrequirements for differential HSTL and differential SSTL inTable 30. Improved<br>DIFF_SSTL18_II SSO limits inTable 32. Updated table note 3 inTable 39. Removed references to old<br>software versions fromTable 47andTable 48. Added description of spread spectrum inSpread<br>Spectrumsection. Updated BPI configuration waveforms inFigure 17. Updated TACCequation in<br>Table 60.|
|12/02/2010|4.0|Added IIKtoTable 6. Updated VINinTable 10and added a footnote to ILinTable 11to note potential<br>leakage between pins of a differential pair. Added note 6 toTable 13. Corrected CLK High and Low<br>Time symbol inTable 46. Corrected symbols for TSUSPEND_GTSand TSUSPEND_GWEinTable 49.<br>Updated link to sign up for Alerts and updatedNotice of Disclaimer.|
|04/01/2011|4.1|InTable 31, added the equivalent pairs per bank for the XC3S50AN and XC3S400AN in the FT(G)256<br>package and the XC3S1400AN in the FG(G)484 package.|
|06/11/2014|4.2|Clarified and updated the maximum description inTable 24.<br>AddedNote 1,Note 2, andNote 3toTable 48. These changes are outlined in the customer notice<br>XCN14003<br>: _Flash Wafer Fabrication Change and Gold (Au) To Copper (Cu) Transition for Spartan-3AN_<br>_FPGA Devices_.<br>Xilinx has issued a discontinuation notice for the XC3S50AN in the FT(G)256 package and the<br>XC3S1400AN in the FG(G)484 package. SeeXCN13016<br>: _Product Discontinuation Notice For_<br>_Selected Spartan-3AN FPGA Products_. UpdatedNotice of Disclaimer.|



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

69 

**Spartan-3AN FPGA Family: DC and Switching Characteristics** 

## **Notice of Disclaimer** 

The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of Xilinx’s limited warranty, please refer to Xilinx’s Terms of Sale which can be viewed at www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in such critical applications, please refer to Xilinx’s Terms of Sale which can be viewed at www.xilinx.com/legal.htm#tos. 

## **AUTOMOTIVE APPLICATIONS DISCLAIMER** 

XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III) USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN SUCH APPLICATIONS. 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

70 

5 

**==> picture [143 x 46] intentionally omitted <==**

DS557 (v4.2) June 12, 2014 

## **Spartan-3AN FPGA Family: Pinout Descriptions** 

**Product Specification** 

## **Introduction** 

This section describes how the various pins on a Spartan®-3AN FPGA connect within the supported component packages, and provides device-specific thermal characteristics. For general information on the pin functions and the package characteristics, see the Packaging section of UG331: 

- **UG331: Spartan-3 Generation FPGA User Guide** http://www.xilinx.com/support/documentation/user_guides/ug331.pdf 

Spartan-3AN FPGAs are available in Pb-free, RoHS packages, indicated by a “G” in the middle of the package code. Leaded (Pb) packages are available for selected devices, with the same pinout and without the “G” in the ordering code (see Table 5, page 7). The Pb-free package code can be selected in the software for the Pb packages since the pinouts are identical. References to the Pb-free package code in this document apply also to the Pb package. 

## **Pin Types** 

Most pins on a Spartan-3AN FPGA are general-purpose, user-defined I/O pins. There are, however, up to 12 different functional types of pins on Spartan-3AN FPGA packages, as outlined in Table 62. In the package footprint drawings that follow, the individual pins are color-coded according to pin type as in the table. 

_Table  62:_ **Types of Pins on Spartan-3AN FPGAs** 

|**Type with**<br>**Color Code**|**Description**|**Pin Name(s) in**<br>**Type**(1)|
|---|---|---|
|I/O|Unrestricted, general-purpose user-I/O pin. Most pins can be paired together to form differential<br>I/Os.|IO_#<br>IO_Lxxy_#|
|INPUT|Unrestricted, general-purpose input-only pin. This pin does not have an output structure,<br>differential termination resistor, or PCI™ clamp diode.|IP_#<br>IP_Lxxy_#|
|DUAL|Dual-purpose pin used in some configuration modes during the configuration process and then<br>usually available as a user I/O after configuration. If the pin is not used during configuration, this<br>pin behaves as an I/O-type pin. See UG332<br>: _Spartan-3 Generation Configuration User Guide_for<br>additional information on these signals.|M[2:0]<br>PUDC_B<br>CCLK<br>MOSI/CSI_B<br>D[7:1]<br>D0/DIN<br>DOUT<br>CSO_B<br>RDWR_B<br>INIT_B<br>A[25:0]<br>VS[2:0]<br>LDC[2:0]<br>HDC|
|VREF|Dual-purpose pin that is either a user-I/O pin or Input-only pin, or, along with all other VREF pins<br>in the same bank, provides a reference voltage input for certain I/O standards. If used for a<br>reference voltage within a bank, all VREF pins within the bank must be connected.|IP/VREF_#<br>IP_Lxx_#/VREF_#<br>IO/VREF_#<br>IO_Lxx_#/VREF_#|
|CLK|Either a user-I/O pin or an input to a specific clock buffer driver. Most packages have 16 global<br>clock inputs that optionally clock the entire device. The exceptions are all devices in the TQG144<br>package and the XC3S50AN in the FTG256 package. The RHCLK inputs optionally clock the<br>right half of the device. The LHCLK inputs optionally clock the left half of the device. See the<br>Using Global Clock Resources chapter inUG331<br>: _Spartan-3 Generation FPGA User Guide_for<br>additional information on these signals.|IO_Lxx_#/GCLK[15:0],<br>IO_Lxx_#/LHCLK[7:0],<br>IO_Lxx_#/RHCLK[7:0]|



© Copyright 2007–2014 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners. 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

71 

**Spartan-3AN FPGA Family: Pinout Descriptions** 

_Table  62:_ **Types of Pins on Spartan-3AN FPGAs** _**(Cont’d)**_ 

|**Type with**<br>**Color Code**|**Description**|**Pin Name(s) in**<br>**Type**(1)|
|---|---|---|
|CONFIG|Dedicated configuration pin, two per device. Not available as a user-I/O pin. Every package has<br>two dedicated configuration pins. These pins are powered by VCCAUX. See UG332<br>: _Spartan-3_<br>_Generation Configuration User Guide_for additional information on the DONE and PROG_B<br>signals.|DONE, PROG_B|
|PWR<br>MGMT|Control and status pins for the power-saving Suspend mode. SUSPEND is a dedicated pin and<br>is powered by VCCAUX. AWAKE is a dual-purpose pin. Unless Suspend mode is enabled in the<br>application, AWAKE is available as a user-I/O pin.|SUSPEND, AWAKE|
|JTAG|Dedicated JTAG pin - 4 per device. Not available as a user-I/O pin. Every package has four<br>dedicated JTAG pins. These pins are powered by VCCAUX.|TDI, TMS, TCK, TDO|
|GND|Dedicated ground pin. The number of GND pins depends on the package used. All must be<br>connected.|GND|
|VCCAUX|Dedicated auxiliary power supply pin. The number of VCCAUX pins depends on the package<br>used. The In-System Flash memory is powered by VCCAUX. All must be connected to +3.3V.|VCCAUX|
|VCCINT|Dedicated internal core logic power supply pin. The number of VCCINT pins depends on the<br>package used. All must be connected to +1.2V.|VCCINT|
|VCCO|Along with all the other VCCO pins in the same bank, this pin supplies power to the output buffers<br>within the I/O bank and sets the input threshold voltage for some I/O standards. All must be<br>connected.|VCCO_#|
|N.C.|This package pin is not connected in this specific device/package combination.|N.C.|



## **Notes:** 

1. # = I/O bank number, an integer between 0 and 3. 

## **Package Pins by Type** 

Each package has three separate voltage supply inputs—VCCINT, VCCAUX, and VCCO—and a common ground return, GND. The numbers of pins dedicated to these functions vary by package, as shown in Table 63. 

_Table  63:_ **Power and Ground Supply Pins by Package** 

|**Package**|**VCCINT**|**VCCAUX**|**VCCO**|**GND**|
|---|---|---|---|---|
|TQG144|4|4|8|13|
|FTG256|6|4|16|28|
|FGG400|9|8|22|43|
|FGG484|15|10|24|53|
|FGG676|23|14|36|77|



A majority of package pins are user-defined I/O or input pins. However, the numbers and characteristics of these I/Os depend on the device type and the package in which it is available, as shown in Table 64. The table shows the maximum number of single-ended I/O pins available, assuming that all I/O-, INPUT-, DUAL-, VREF-, and CLK-type pins are used as general-purpose I/O. AWAKE is counted here as a dual-purpose I/O pin. Likewise, the table shows the maximum number of differential pin-pairs available on the package. Finally, the table shows how the total maximum user-I/Os are distributed by pin type, including the number of unconnected—N.C.—pins on the device. 

Not all I/O standards are supported on all I/O banks. The left and right banks (I/O banks 1 and 3) support higher output drive current than the top and bottom banks (I/O banks 0 and 2). Similarly, true differential output standards, such as LVDS, RSDS, PPDS, miniLVDS, and TMDS, are only supported in the top or bottom banks (I/O banks 0 and 2). Inputs are unrestricted. For more details, see the “Using I/O Resources” chapter in UG331. 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

72 

**Spartan-3AN FPGA Family: Pinout Descriptions** 

_Table  64:_ **Maximum User I/O by Package** 

|**Device**|**Package**|**Maximum**<br>**User I/Os**<br>**and**<br>**Input-Only**|**Maximum**<br>**Input-**<br>**Only**|**Maximum**<br>**Differential**<br>**Pairs**|**All Possible I/Os by Type**|**All Possible I/Os by Type**|**All Possible I/Os by Type**|**All Possible I/Os by Type**|**All Possible I/Os by Type**|**All Possible I/Os by Type**|
|---|---|---|---|---|---|---|---|---|---|---|
||||||**I/O**|**INPUT**|**DUAL**|**VREF** (1)|**CLK**|**N.C.**|
|XC3S50AN|TQG144|108|7|50|42|2|26|8|30|0|
||FTG256(2)|144|32|64|53|20|26|15|30|51|
|XC3S200AN|FTG256|195|35|90|69|21|52|21|32|0|
|XC3S400AN|FTG256|195|35|90|69|21|52|21|32|0|
||FGG400|311|63|142|155|46|52|26|32|0|
|XC3S700AN|FGG484|372|84|165|194|61|52|33|32|3|
|XC3S1400AN|FGG484(2)|375|87|165|195|62|52|34|32|0|
||FGG676|502|94|227|313|67|52|38|32|17|



## **Notes:** 

1. Some VREFs are on INPUT pins. See pinout tables for details. 

2. Xilinx has issued a discontinuation notice for these highlighted devices/packages. For more information see XCN13016: _Product Discontinuation Notice For Selected Spartan-3AN FPGA Products_ . 

Electronic versions of the package pinout tables and foot-prints are available for download from the Xilinx website at: 

http://www.xilinx.com/support/documentation/data_sheets/s3a_pin.zip 

Using a spreadsheet program, the data can be sorted and reformatted according to any specific needs. Similarly, the ASCII-text file is easily parsed by most scripting programs. 

## **Package Overview** 

Table 65 shows the five low-cost, space-saving production package styles for the Spartan-3AN family. 

_Table  65:_ **Spartan-3AN Family Package Options** 

|**Package**|**Leads**|**Type**|**Maximum I/Os**|**Lead Pitch**<br>**(mm)**|**Body Area**<br>**(mm)**|**Height**<br>**(mm)**|
|---|---|---|---|---|---|---|
|TQ144/TQG144|144|Thin Quad Flat Pack (TQFP)|108|0.5|20 x 20|1.60|
|FT256/FTG256|256|Fine-pitch Thin Ball Grid Array (FBGA)|195|1.0|17 x 17|1.55|
|FG400/FGG400|400|Fine-pitch Ball Grid Array (FBGA)|311|1.0|21 x 21|2.43|
|FG484/FGG484|484|Fine-pitch Ball Grid Array (FBGA)|375|1.0|23 x 23|2.60|
|FG676/FGG676|676|Fine-pitch Ball Grid Array (FBGA)|502|1.0|27 x 27|2.60|



## **Notes:** 

1. For mass, refer to the MDDS files (see Table 66). 

Each package style is available in an environmentally friendly lead-free (Pb-free) option. The Pb-free packages include an extra “G” in the package style name. For example, the standard “CS484” package becomes “CSG484” when ordered as the Pb-free option. Leaded (Pb) packages are available for selected devices, with the same pinout and without the “G” in the ordering code; See Table 5, page 7 for more information. The mechanical dimensions of the Pb and Pb-free packages are similar, as shown in the mechanical drawings provided in Table 66. 

For additional package information, see UG112: _Device Package User Guide_ . 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

73 

**Spartan-3AN FPGA Family: Pinout Descriptions** 

## **Mechanical Drawings** 

Detailed mechanical drawings for each package type are available from the Xilinx website at the specified location in Table 66. Material Declaration Data Sheets (MDDS) are also available on the Xilinx website for each package. 

_Table  66:_ **Xilinx Package Documentation** 

|**Package**|**Drawing**|**MDDS**|
|---|---|---|
|TQ144|Package Drawing|PK169_TQ144|
|TQG144||PK461_TQG144|
|FT256|Package Drawing|PK158_FT256|
|FTG256||PK<br>424_<br>FTG256|
|FG400|Package Drawing|PK182_FG400|
|FGG400||PK108_FGG400|
|FG484|Package Drawing|PK183_FG484|
|FGG484||PK110_FGG484|
|FG676|Package Drawing|PK155_FG676|
|FGG676||PK<br>394_<br>FGG676|



## **Package Thermal Characteristics** 

The power dissipated by an FPGA application has implications on package selection and system design. The power consumed by a Spartan-3AN FPGA is reported using either the Xilinx Power Estimator or the Xilinx Power Analyzer calculator integrated in the Xilinx® ISE® development software. Table 67 provides the thermal characteristics for the various Spartan-3AN FPGA packages. This information is also available using the Thermal Query tool at http://www.xilinx.com/cgi-bin/thermal/thermal.pl. 

The junction-to-case thermal resistance (θJC) indicates the difference between the temperature measured on the package body (case) and the junction temperature per watt of power consumption. The junction-to-board (θJB) value similarly reports the difference between the board and junction temperature. The junction-to-ambient (θJA) value reports the temperature difference between the ambient environment and the junction temperature. The θJA value is reported at different air velocities, measured in linear feet per minute (LFM). The “Still Air (0 LFM)” column shows the θJA value in a system without a fan. The thermal resistance drops with increasing air flow. 

_Table  67:_ **Spartan-3AN FPGA Package Thermal Characteristics** 

|**Device**|**Package**(1)|**Junction-to-Case**<br>**(**θ**JC)**|**Junction-to-Board**<br>**(**θ**JB)**|**Junction-to-Ambient (**θ**JA) **<br>**at Different Air Flows**|**Junction-to-Ambient (**θ**JA) **<br>**at Different Air Flows**|**Junction-to-Ambient (**θ**JA) **<br>**at Different Air Flows**|**Junction-to-Ambient (**θ**JA) **<br>**at Different Air Flows**|**Units**|
|---|---|---|---|---|---|---|---|---|
|||||**Still Air**<br>**(0 LFM)**|**250 LFM**|**500 LFM**|**750 LFM**||
|XC3S50AN|TQG144|13.4|32.8|38.9|32.8|32.5|31.7|°C/Watt|
||FTG256(3)|||||||°C/Watt|
|XC3S200AN|FTG256|7.4|23.3|29.0|23.8|23.0|22.3|°C/Watt|
|XC3S400AN|FTG256|5.9|13.6|25.9|21.7|20.2|19.3|°C/Watt|
||FGG400|6.2|12.9|22.5|16.7|15.6|15.0|°C/Watt|
|XC3S700AN|FGG484|5.3|11.5|19.4|15.0|13.9|13.4|°C/Watt|
|XC3S1400AN|FGG484(3)|||||||°C/Watt|
||FGG676|4.3|10.9|17.7|13.7|12.6|12.1|°C/Watt|



## **Notes:** 

1. Thermal characteristics are similar for leaded (non-Pb-free) packages. 

2. Use the Thermal Query tool at http://www.xilinx.com/cgi-bin/thermal/thermal.pl for specific device information. 

3. Xilinx has issued a discontinuation notice for these highlighted devices/packages. For more information see XCN13016: _Product Discontinuation Notice For Selected Spartan-3AN FPGA Products_ . 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

74 

**Spartan-3AN FPGA Family: Pinout Descriptions** 

## **TQG144: 144-lead Thin Quad Flat Package** 

The XC3S50AN is available in the 144-lead thin quad flat package, TQG144. 

Table 68 lists all the package pins. They are sorted by bank number and then by pin name. Pins that form a differential I/O pair appear together in the table. The table also shows the pin number for each pin and the pin type (as defined in Table 62). The XC3S50AN does not support the address output pins for the Byte-wide Peripheral Interface (BPI) configuration mode. 

An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at: www.xilinx.com/support/documentation/data_sheets/s3a_pin.zip. 

## **Pinout Table** 

_Table  68:_ **Spartan-3AN TQG144 Pinout** 

|**Bank**|**Pin Name**|**Pin**|**Type**|
|---|---|---|---|
|0|IO_0|P142|I/O|
|0|IO_L01N_0|P111|I/O|
|0|IO_L01P_0|P110|I/O|
|0|IO_L02N_0|P113|I/O|
|0|IO_L02P_0/VREF_0|P112|VREF|
|0|IO_L03N_0|P117|I/O|
|0|IO_L03P_0|P115|I/O|
|0|IO_L04N_0|P116|I/O|
|0|IO_L04P_0|P114|I/O|
|0|IO_L05N_0|P121|I/O|
|0|IO_L05P_0|P120|I/O|
|0|IO_L06N_0/GCLK5|P126|GCLK|
|0|IO_L06P_0/GCLK4|P124|GCLK|
|0|IO_L07N_0/GCLK7|P127|GCLK|
|0|IO_L07P_0/GCLK6|P125|GCLK|
|0|IO_L08N_0/GCLK9|P131|GCLK|
|0|IO_L08P_0/GCLK8|P129|GCLK|
|0|IO_L09N_0/GCLK11|P132|GCLK|
|0|IO_L09P_0/GCLK10|P130|GCLK|
|0|IO_L10N_0|P135|I/O|
|0|IO_L10P_0|P134|I/O|
|0|IO_L11N_0|P139|I/O|
|0|IO_L11P_0|P138|I/O|
|0|IO_L12N_0/PUDC_B|P143|DUAL|
|0|IO_L12P_0/VREF_0|P141|VREF|
|0|IP_0|P140|INPUT|
|0|IP_0/VREF_0|P123|VREF|
|0|VCCO_0|P119|VCCO|
|0|VCCO_0|P136|VCCO|
|1|IO_1|P79|I/O|
|1|IO_L01N_1/LDC2|P78|DUAL|
|1|IO_L01P_1/HDC|P76|DUAL|
|1|IO_L02N_1/LDC0|P77|DUAL|



_Table  68:_ **Spartan-3AN TQG144 Pinout** _**(Cont’d)**_ 

|**Bank**|**Pin Name**|**Pin**|**Type**|
|---|---|---|---|
|1|IO_L02P_1/LDC1|P75|DUAL|
|1|IO_L03N_1|P84|I/O|
|1|IO_L03P_1|P82|I/O|
|1|IO_L04N_1/RHCLK1|P85|RHCLK|
|1|IO_L04P_1/RHCLK0|P83|RHCLK|
|1|IO_L05N_1/TRDY1/RHCLK3|P88|RHCLK|
|1|IO_L05P_1/RHCLK2|P87|RHCLK|
|1|IO_L06N_1/RHCLK5|P92|RHCLK|
|1|IO_L06P_1/RHCLK4|P90|RHCLK|
|1|IO_L07N_1/RHCLK7|P93|RHCLK|
|1|IO_L07P_1/IRDY1/RHCLK6|P91|RHCLK|
|1|IO_L08N_1|P98|I/O|
|1|IO_L08P_1|P96|I/O|
|1|IO_L09N_1|P101|I/O|
|1|IO_L09P_1|P99|I/O|
|1|IO_L10N_1|P104|I/O|
|1|IO_L10P_1|P102|I/O|
|1|IO_L11N_1|P105|I/O|
|1|IO_L11P_1|P103|I/O|
|1|IP_1/VREF_1|P80|VREF|
|1|IP_1/VREF_1|P97|VREF|
|1|VCCO_1|P86|VCCO|
|1|VCCO_1|P95|VCCO|
|2|IO_2/MOSI/CSI_B|P62|DUAL|
|2|IO_L01N_2/M0|P38|DUAL|
|2|IO_L01P_2/M1|P37|DUAL|
|2|IO_L02N_2/CSO_B|P41|DUAL|
|2|IO_L02P_2/M2|P39|DUAL|
|2|IO_L03N_2/VS1|P44|DUAL|
|2|IO_L03P_2/RDWR_B|P42|DUAL|
|2|IO_L04N_2/VS0|P45|DUAL|
|2|IO_L04P_2/VS2|P43|DUAL|
|2|IO_L05N_2/D7|P48|DUAL|



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

75 

**Spartan-3AN FPGA Family: Pinout Descriptions** 

_Table  68:_ **Spartan-3AN TQG144 Pinout** _**(Cont’d)**_ 

|**Bank**|**Pin Name**|**Pin**|**Type**|
|---|---|---|---|
|2|IO_L05P_2|P46|I/O|
|2|IO_L06N_2/D6|P49|DUAL|
|2|IO_L06P_2|P47|I/O|
|2|IO_L07N_2/D4|P51|DUAL|
|2|IO_L07P_2/D5|P50|DUAL|
|2|IO_L08N_2/GCLK15|P55|GCLK|
|2|IO_L08P_2/GCLK14|P54|GCLK|
|2|IO_L09N_2/GCLK1|P59|GCLK|
|2|IO_L09P_2/GCLK0|P57|GCLK|
|2|IO_L10N_2/GCLK3|P60|GCLK|
|2|IO_L10P_2/GCLK2|P58|GCLK|
|2|IO_L11N_2/DOUT|P64|DUAL|
|2|IO_L11P_2/AWAKE|P63|PWR MGMT|
|2|IO_L12N_2/D3|P68|DUAL|
|2|IO_L12P_2/INIT_B|P67|DUAL|
|2|IO_L13N_2/D0/DIN/MISO|P71|DUAL|
|2|IO_L13P_2/D2|P69|DUAL|
|2|IO_L14N_2/CCLK|P72|DUAL|
|2|IO_L14P_2/D1|P70|DUAL|
|2|IP_2/VREF_2|P53|VREF|
|2|VCCO_2|P40|VCCO|
|2|VCCO_2|P61|VCCO|
|3|IO_L01N_3|P6|I/O|
|3|IO_L01P_3|P4|I/O|
|3|IO_L02N_3|P5|I/O|
|3|IO_L02P_3|P3|I/O|
|3|IO_L03N_3|P8|I/O|
|3|IO_L03P_3|P7|I/O|
|3|IO_L04N_3/VREF_3|P11|VREF|
|3|IO_L04P_3|P10|I/O|
|3|IO_L05N_3/LHCLK1|P13|LHCLK|
|3|IO_L05P_3/LHCLK0|P12|LHCLK|
|3|IO_L06N_3/IRDY2/LHCLK3|P16|LHCLK|
|3|IO_L06P_3/LHCLK2|P15|LHCLK|
|3|IO_L07N_3/LHCLK5|P20|LHCLK|
|3|IO_L07P_3/LHCLK4|P18|LHCLK|
|3|IO_L08N_3/LHCLK7|P21|LHCLK|
|3|IO_L08P_3/TRDY2/LHCLK6|P19|LHCLK|
|3|IO_L09N_3|P25|I/O|
|3|IO_L09P_3|P24|I/O|
|3|IO_L10N_3|P29|I/O|
|3|IO_L10P_3|P27|I/O|



_Table  68:_ **Spartan-3AN TQG144 Pinout** _**(Cont’d)**_ 

|**Bank**|**Pin Name**|**Pin**|**Type**|
|---|---|---|---|
|3|IO_L11N_3|P30|I/O|
|3|IO_L11P_3|P28|I/O|
|3|IO_L12N_3|P32|I/O|
|3|IO_L12P_3|P31|I/O|
|3|IP_L13N_3/VREF_3|P35|VREF|
|3|IP_L13P_3|P33|INPUT|
|3|VCCO_3|P14|VCCO|
|3|VCCO_3|P23|VCCO|
|GND|GND|P9|GND|
|GND|GND|P17|GND|
|GND|GND|P26|GND|
|GND|GND|P34|GND|
|GND|GND|P56|GND|
|GND|GND|P65|GND|
|GND|GND|P81|GND|
|GND|GND|P89|GND|
|GND|GND|P100|GND|
|GND|GND|P106|GND|
|GND|GND|P118|GND|
|GND|GND|P128|GND|
|GND|GND|P137|GND|
|VCCAUX|SUSPEND|P74|PWR MGMT|
|VCCAUX|DONE|P73|CONFIG|
|VCCAUX|PROG_B|P144|CONFIG|
|VCCAUX|TCK|P109|JTAG|
|VCCAUX|TDI|P2|JTAG|
|VCCAUX|TDO|P107|JTAG|
|VCCAUX|TMS|P1|JTAG|
|VCCAUX|VCCAUX|P36|VCCAUX|
|VCCAUX|VCCAUX|P66|VCCAUX|
|VCCAUX|VCCAUX|P108|VCCAUX|
|VCCAUX|VCCAUX|P133|VCCAUX|
|VCCINT|VCCINT|P22|VCCINT|
|VCCINT|VCCINT|P52|VCCINT|
|VCCINT|VCCINT|P94|VCCINT|
|VCCINT|VCCINT|P122|VCCINT|



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

76 

**Spartan-3AN FPGA Family: Pinout Descriptions** 

## **User I/Os by Bank** 

Table 69 indicates how the 108 available user-I/O pins are distributed between the four I/O banks on the TQG144 package. The AWAKE pin is counted as a dual-purpose I/O. 

_Table  69:_ **User I/Os Per Bank for the XC3S50AN in the TQG144 Package** 

|**Package**<br>**Edge**|**I/O Bank**|**Maximum I/Os**|**All Possible I/O Pins by Type**|**All Possible I/O Pins by Type**|**All Possible I/O Pins by Type**|**All Possible I/O Pins by Type**|**All Possible I/O Pins by Type**|
|---|---|---|---|---|---|---|---|
||||**I/O**|**INPUT**|**DUAL**|**VREF**|**CLK**|
|Top|0|27|14|1|1|3|8|
|Right|1|25|11|0|4|2|8|
|Bottom|2|30|2|0|21|1|6|
|Left|3|26|15|1|0|2|8|
|**Total**||**108**|**42**|**2**|**26**|**8**|**30**|



## **Footprint Migration Differences** 

The XC3S50AN FPGA is the only Spartan-3AN device offered in the TQG144 package. The XC3S50AN FPGA is pin compatible with the Spartan-3A XC3S50A FPGA in the TQ(G)144 package, although the Spartan-3A FPGA requires an external configuration source. 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

77 

**Spartan-3AN FPGA Family: Pinout Descriptions** 

## **TQG144 Footprint** 

_**Note:**_ Pin 1 indicator in top-left corner and logo orientation. 

**==> picture [484 x 485] intentionally omitted <==**

**----- Start of picture text -----**<br>
- a<br>TMS 1 108 VCCAUX<br>TDI 2 Bank 0 107 TDO<br>IO_L02P_3 a 3 106 GND<br>IO_L01P_3 4 X - 105 IO_L11N_1<br>IO_L02N_3 5 104 IO_L10N_1<br>IO_L01N_3 6 103 IO_L11P_1<br>IO_L03P_3 7 102 IO_L10P_1<br>IO_L03N_3 8 101 IO_L09N_1<br>GND 9 100 GND<br>IO_L04P_3 10 99 IO_L09P_1<br>IO_L04N_3/VREF_3 11 98 IO_L08N_1<br>IO_L05P_3/LHCLK0 12 97 IP_1/VREF_1<br>IO_L05N_3/LHCLK1 13 96 IO_L08P_1<br>VCCO_3 14 95 VCCO_1<br>IO_L06P_3/LHCLK2 15 94 VCCINT<br>IO_L06N_3/LHCLK3 16 93 IO_L07N_1/RHCLK7<br>GND 17 92 IO_L06N_1/RHCLK5<br>IO_L07P_3/LHCLK4 18 91 IO_L07P_1/RHCLK6<br>IO_L08P_3/LHCLK6 19 = 90 IO_L06P_1/RHCLK4<br>IO_L07N_3/LHCLK5 20 89 GND<br>IO_L08N_3/LHCLK7 21 88 IO_L05N_1/RHCLK3<br>=<br>VCCINT 22 87 IO_L05P_1/RHCLK2<br>VCCO_3 23 86 VCCO_1<br>IO_L09P_3 24 85 IO_L04N_1/RHCLK1<br>IO_L09N_3 25 84 IO_L03N_1<br>GND : 26 > |k 83 IO_L04P_1/RHCLK0<br>IO_L10P_3 27 82 IO_L03P_1<br>IO_L11P_3 28 81 GND<br>IO_L10N_3 29 80 IP_1/VREF_1<br>IO_L11N_3 30 79 IO_1<br>IO_L12P_3 31 78 IO_L01N_1/LDC2<br>IO_L12N_3 32 77 IO_L02N_1/LDC0<br>IP_L13P_3 33 76 IO_L01P_1/HDC<br>GND 34 75 IO_L02P_1/LDC1<br>IP_L13N_3/VREF_3 35 74 SUSPEND<br>VCCAUX 36 Bank 2 73 DONE<br>DS529-4_10_031207<br>PROG_B IO_L12N_0/PUDC_B IO_0 IO_L12P_0/VREF_0 IP_0 IO_L11N_0 IO_L11P_0 GND VCCO_0 IO_L10N_0 IO_L10P_0 VCCAUX IO_L09N_0/GCLK11 IO_L08N_0/GCLK9 IO_L09P_0/GCLK10 IO_L08P_0/GCLK8 GND IO_L07N_0/GCLK7 IO_L06N_0/GCLK5 IO_L07P_0/GCLK6 IO_L06P_0/GCLK4 IP_0/VREF_0 VCCINT IO_L05N_0 IO_L05P_0 VCCO_0 GND IO_L03N_0 IO_L04N_0 IO_L03P_0 IO_L04P_0 IO_L02N_0 IO_L02P_0/VREF_0 IO_L01N_0 IO_L01P_0 TCK<br>144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109<br>Bank 3<br>Bank 1<br>37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72<br>IO_L01P_2/M1 IO_L01N_2/M0 IO_L02P_2/M2 VCCO_2 IO_L02N_2/CSO_B IO_L03P_2/RDWR_B IO_L04P_2/VS2 IO_L03N_2/VS1 IO_L04N_2/VS0 IO_L05P_2 IO_L06P_2 IO_L05N_2/D7 IO_L06N_2/D6 IO_L07P_2/D5 IO_L07N_2/D4 VCCINT IP_2/VREF_2 IO_L08P_2/GCLK14 IO_L08N_2/GCLK15 GND IO_L09P_2/GCLK0 IO_L10P_2/GCLK2 IO_L09N_2/GCLK1 IO_L10N_2/GCLK3 VCCO_2 IO_2/MOSI/CSI_B IO_L11P_2/AWAKE IO_L11N_2/DOUT GND VCCAUX IO_L12P_2/INIT_B IO_L12N_2/D3 IO_L13P_2/D2 IO_L14P_2/D1 IO_L13N_2/D0/DIN/MISO IO_L14N_2/CCLK<br>**----- End of picture text -----**<br>


_Figure 19:_ **XC3S50AN FPGA in TQG144 Package Footprint (Top View)** 

**I/O:** Unrestricted, general-purpose **DUAL:** Configuration pins, then **VREF:** User I/O or input voltage 42 25 8 user I/O possible user I/O reference for bank **INPUT:** Unrestricted, **CLK:** User I/O, input, or global **VCCO:** Output voltage supply for 2 30 8 general-purpose input pin buffer input bank **CONFIG:** Dedicated configuration **JTAG:** Dedicated JTAG port pins **VCCINT:** Internal core supply 2 4 4 pins voltage (+1.2V) 0 **N.C.:** Not connected 13 **GND:** Ground 4 **VCCAUX:** Auxiliary supply voltage **SUSPEND:** Dedicated SUSPEND 2 and dual-purpose AWAKE Power Management pins 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

78 

**Spartan-3AN FPGA Family: Pinout Descriptions** 

## **FTG256: 256-Ball Fine-Pitch, Thin Ball Grid Array** 

Xilinx has issued a discontinuation notice for the XC3S50AN in the FT(G)256 package. See XCN13016: _Product Discontinuation Notice For Selected Spartan-3AN FPGA Products_ . 

The 256-ball fine-pitch, thin ball grid array package, FTG256, supports the XC3S200AN and XC3S400AN devices. Table 70 lists all the package pins for these devices including the discontinued XC3S50AN. They are sorted by bank number and then by the pin name of the largest device. Pins that form a differential I/O pair appear together in the table. The differential I/O pairs that have different assignments between the XC3S50AN and the XC3S200AN or XC3S400AN are highlighted in light blue in Table 70. See Footprint Migration Differences, page 87 for additional information. The table also shows the pin number for each pin and the pin type (as defined in Table 62). 

The footprints for the XC3S200AN and XC3S400AN in the FTG256 are identical. Figure 21 shows the common footprint for the XC3S200AN and XC3S400AN. The discontinued XC3S50AN footprint is compatible with the XC3S200AN and XC3S400AN, however, there are 51 unconnected balls (indicated as N.C. in Table 70). 

Table 73 summarizes the discontinued XC3S50AN FPGA footprint migration differences for the FTG256 package. 

The XC3S50AN does not support the address output pins for the byte-wide peripheral interface (BPI) configuration mode. 

An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at: www.xilinx.com/support/documentation/data_sheets/s3a_pin.zip. 

## **Pinout Table** 

_Table  70:_ **Spartan-3AN FTG256 Pinout (XC3S50AN (Discontinued), XC3S200AN, XC3S400AN)** 

|**Bank**|**XC3S50AN Pin Name (Discontinued)**|**XC3S200AN/XC3S400AN Pin Name**|**FTG256 Ball**|**Type**|
|---|---|---|---|---|
|0|IO_L01N_0|IO_L01N_0|C13|I/O|
|0|IO_L01P_0|IO_L01P_0|D13|I/O|
|0|IO_L02N_0|IO_L02N_0|B14|I/O|
|0|IO_L02P_0/VREF_0|IO_L02P_0/VREF_0|B15|VREF|
|0|IO_L03N_0|IO_L03N_0|D11|I/O|
|0|IO_L03P_0|IO_L03P_0|C12|I/O|
|0|IO_L04N_0|IO_L04N_0|A13|I/O|
|0|IO_L04P_0|IO_L04P_0|A14|I/O|
|0|N.C.|IO_L05N_0|A12|I/O|
|0|IP_0|IO_L05P_0|B12|I/O|
|0|N.C.|IO_L06N_0/VREF_0|E10|VREF|
|0|N.C.|IO_L06P_0|D10|I/O|
|0|IO_L07N_0|IO_L07N_0|A11|I/O|
|0|IO_L07P_0|IO_L07P_0|C11|I/O|
|0|IO_L08N_0|IO_L08N_0|A10|I/O|
|0|IO_L08P_0|IO_L08P_0|B10|I/O|
|0|IO_L09N_0/GCLK5|IO_L09N_0/GCLK5|D9|GCLK|
|0|IO_L09P_0/GCLK4|IO_L09P_0/GCLK4|C10|GCLK|
|0|IO_L10N_0/GCLK7|IO_L10N_0/GCLK7|A9|GCLK|
|0|IO_L10P_0/GCLK6|IO_L10P_0/GCLK6|C9|GCLK|
|0|IO_L11N_0/GCLK9|IO_L11N_0/GCLK9|D8|GCLK|
|0|IO_L11P_0/GCLK8|IO_L11P_0/GCLK8|C8|GCLK|
|0|IO_L12N_0/GCLK11|IO_L12N_0/GCLK11|B8|GCLK|
|0|IO_L12P_0/GCLK10|IO_L12P_0/GCLK10|A8|GCLK|



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

79 

**Spartan-3AN FPGA Family: Pinout Descriptions** 

_Table  70:_ **Spartan-3AN FTG256 Pinout (XC3S50AN (Discontinued), XC3S200AN, XC3S400AN)** _**(Cont’d)**_ 

|**Bank**|**XC3S50AN Pin Name (Discontinued)**|**XC3S200AN/XC3S400AN Pin Name**|**FTG256 Ball**|**Type**|
|---|---|---|---|---|
|0|N.C.|IO_L13N_0|C7|I/O|
|0|N.C.|IO_L13P_0|A7|I/O|
|0|N.C.|IO_L14N_0/VREF_0|E7|VREF|
|0|N.C.|IO_L14P_0|F8|I/O|
|0|IO_L15N_0|IO_L15N_0|B6|I/O|
|0|IO_L15P_0|IO_L15P_0|A6|I/O|
|0|IO_L16N_0|IO_L16N_0|C6|I/O|
|0|IO_L16P_0|IO_L16P_0|D7|I/O|
|0|IO_L17N_0|IO_L17N_0|C5|I/O|
|0|IO_L17P_0|IO_L17P_0|A5|I/O|
|0|IO_L18N_0|IO_L18N_0|B4|I/O|
|0|IO_L18P_0|IO_L18P_0|A4|I/O|
|0|IO_L19N_0|IO_L19N_0|B3|I/O|
|0|IO_L19P_0|IO_L19P_0|A3|I/O|
|0|IO_L20N_0/PUDC_B|IO_L20N_0/PUDC_B|D5|DUAL|
|0|IO_L20P_0/VREF_0|IO_L20P_0/VREF_0|C4|VREF|
|0|IP_0|IP_0|D6|INPUT|
|0|IP_0|IP_0|D12|INPUT|
|0|IP_0|IP_0|E6|INPUT|
|0|IP_0|IP_0|F7|INPUT|
|0|IP_0|IP_0|F9|INPUT|
|0|IP_0|IP_0|F10|INPUT|
|0|IP_0/VREF_0|IP_0/VREF_0|E9|VREF|
|0|VCCO_0|VCCO_0|B5|VCCO|
|0|VCCO_0|VCCO_0|B9|VCCO|
|0|VCCO_0|VCCO_0|B13|VCCO|
|0|VCCO_0|VCCO_0|E8|VCCO|
|1|IO_L01N_1/LDC2|IO_L01N_1/LDC2|N14|DUAL|
|1|IO_L01P_1/HDC|IO_L01P_1/HDC|N13|DUAL|
|1|IO_L02N_1/LDC0|IO_L02N_1/LDC0|P15|DUAL|
|1|IO_L02P_1/LDC1|IO_L02P_1/LDC1|R15|DUAL|
|1|IO_L03N_1|IO_L03N_1/A1|N16|DUAL|
|1|IO_L03P_1|IO_L03P_1/A0|P16|DUAL|
|1|N.C.|IO_L05N_1/VREF_1|M14|VREF|
|1|N.C.|IO_L05P_1|M13|I/O|
|1|N.C.|IO_L06N_1/A3|K13|DUAL|
|1|N.C.|IO_L06P_1/A2|L13|DUAL|
|1|N.C.|IO_L07N_1/A5|M16|DUAL|
|1|N.C.|IO_L07P_1/A4|M15|DUAL|
|1|N.C.|IO_L08N_1/A7|L16|DUAL|



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

80 

**Spartan-3AN FPGA Family: Pinout Descriptions** 

_Table  70:_ **Spartan-3AN FTG256 Pinout (XC3S50AN (Discontinued), XC3S200AN, XC3S400AN)** _**(Cont’d)**_ 

|**Bank**|**XC3S50AN Pin Name (Discontinued)**|**XC3S200AN/XC3S400AN Pin Name**|**FTG256 Ball**|**Type**|
|---|---|---|---|---|
|1|N.C.|IO_L08P_1/A6|L14|DUAL|
|1|IO_L10N_1|IO_L10N_1/A9|J13|DUAL|
|1|IO_L10P_1|IO_L10P_1/A8|J12|DUAL|
|1|IO_L11N_1/RHCLK1|IO_L11N_1/RHCLK1|K14|RHCLK|
|1|IO_L11P_1/RHCLK0|IO_L11P_1/RHCLK0|K15|RHCLK|
|1|IO_L12N_1/TRDY1/RHCLK3|IO_L12N_1/TRDY1/RHCLK3|J16|RHCLK|
|1|IO_L12P_1/RHCLK2|IO_L12P_1/RHCLK2|K16|RHCLK|
|1|IO_L14N_1/RHCLK5|IO_L14N_1/RHCLK5|H14|RHCLK|
|1|IO_L14P_1/RHCLK4|IO_L14P_1/RHCLK4|J14|RHCLK|
|1|IO_L15N_1/RHCLK7|IO_L15N_1/RHCLK7|H16|RHCLK|
|1|IO_L15P_1/IRDY1/RHCLK6|IO_L15P_1/IRDY1/RHCLK6|H15|RHCLK|
|1|N.C.|IO_L16N_1/A11|F16|DUAL|
|1|N.C.|IO_L16P_1/A10|G16|DUAL|
|1|N.C.|IO_L17N_1/A13|G14|DUAL|
|1|N.C.|IO_L17P_1/A12|H13|DUAL|
|1|N.C.|IO_L18N_1/A15|F15|DUAL|
|1|N.C.|IO_L18P_1/A14|E16|DUAL|
|1|N.C.|IO_L19N_1/A17|F14|DUAL|
|1|N.C.|IO_L19P_1/A16|G13|DUAL|
|1|IO_L20N_1|IO_L20N_1/A19|F13|DUAL|
|1|IO_L20P_1|IO_L20P_1/A18|E14|DUAL|
|1|IO_L22N_1|IO_L22N_1/A21|D15|DUAL|
|1|IO_L22P_1|IO_L22P_1/A20|D16|DUAL|
|1|IO_L23N_1|IO_L23N_1/A23|D14|DUAL|
|1|IO_L23P_1|IO_L23P_1/A22|E13|DUAL|
|1|IO_L24N_1|IO_L24N_1/A25|C15|DUAL|
|1|IO_L24P_1|IO_L24P_1/A24|C16|DUAL|
|1|IP_L04N_1/VREF_1|IP_L04N_1/VREF_1|K12|VREF|
|1|IP_L04P_1|IP_L04P_1|K11|INPUT|
|1|N.C.|IP_L09N_1|J11|INPUT|
|1|N.C.|IP_L09P_1/VREF_1|J10|VREF|
|1|IP_L13N_1|IP_L13N_1|H11|INPUT|
|1|IP_L13P_1|IP_L13P_1|H10|INPUT|
|1|IP_L21N_1|IP_L21N_1|G11|INPUT|
|1|IP_L21P_1/VREF_1|IP_L21P_1/VREF_1|G12|VREF|
|1|IP_L25N_1|IP_L25N_1|F11|INPUT|
|1|IP_L25P_1/VREF_1|IP_L25P_1/VREF_1|F12|VREF|
|1|VCCO_1|VCCO_1|E15|VCCO|
|1|VCCO_1|VCCO_1|H12|VCCO|
|1|VCCO_1|VCCO_1|J15|VCCO|



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

81 

**Spartan-3AN FPGA Family: Pinout Descriptions** 

_Table  70:_ **Spartan-3AN FTG256 Pinout (XC3S50AN (Discontinued), XC3S200AN, XC3S400AN)** _**(Cont’d)**_ 

|**Bank**|**XC3S50AN Pin Name (Discontinued)**|**XC3S200AN/XC3S400AN Pin Name**|**FTG256 Ball**|**Type**|
|---|---|---|---|---|
|1|VCCO_1|VCCO_1|N15|VCCO|
|2|IO_L01N_2/M0|IO_L01N_2/M0|P4|DUAL|
|2|IO_L01P_2/M1|IO_L01P_2/M1|N4|DUAL|
|2|IO_L02N_2/CSO_B|IO_L02N_2/CSO_B|T2|DUAL|
|2|IO_L02P_2/M2|IO_L02P_2/M2|R2|DUAL|
|2|IO_L04P_2/VS2|IO_L03N_2/VS2|T3|DUAL|
|2|IO_L03P_2/RDWR_B|IO_L03P_2/RDWR_B|R3|DUAL|
|2|IO_L04N_2/VS0|IO_L04N_2/VS0|P5|DUAL|
|2|IO_L03N_2/VS1|IO_L04P_2/VS1|N6|DUAL|
|2|IO_L06P_2|IO_L05N_2|R5|I/O|
|2|IO_L05P_2|IO_L05P_2|T4|I/O|
|2|IO_L06N_2/D6|IO_L06N_2/D6|T6|DUAL|
|2|IO_L05N_2/D7|IO_L06P_2/D7|T5|DUAL|
|2|N.C.|IO_L07N_2|P6|I/O|
|2|N.C.|IO_L07P_2|N7|I/O|
|2|IO_L08N_2/D4|IO_L08N_2/D4|N8|DUAL|
|2|IO_L08P_2/D5|IO_L08P_2/D5|P7|DUAL|
|2|N.C.|IO_L09N_2/GCLK13|T7|GCLK|
|2|N.C.|IO_L09P_2/GCLK12|R7|GCLK|
|2|IO_L10N_2/GCLK15|IO_L10N_2/GCLK15|T8|GCLK|
|2|IO_L10P_2/GCLK14|IO_L10P_2/GCLK14|P8|GCLK|
|2|IO_L11N_2/GCLK1|IO_L11N_2/GCLK1|P9|GCLK|
|2|IO_L11P_2/GCLK0|IO_L11P_2/GCLK0|N9|GCLK|
|2|IO_L12N_2/GCLK3|IO_L12N_2/GCLK3|T9|GCLK|
|2|IO_L12P_2/GCLK2|IO_L12P_2/GCLK2|R9|GCLK|
|2|N.C.|IO_L13N_2|M10|I/O|
|2|N.C.|IO_L13P_2|N10|I/O|
|2|IO_L14P_2/MOSI/CSI_B|IO_L14N_2/MOSI/CSI_B|P10|DUAL|
|2|IO_L14N_2|IO_L14P_2|T10|I/O|
|2|IO_L15N_2/DOUT|IO_L15N_2/DOUT|R11|DUAL|
|2|IO_L15P_2/AWAKE|IO_L15P_2/AWAKE|T11|PWR MGMT|
|2|IO_L16N_2|IO_L16N_2|N11|I/O|
|2|IO_L16P_2|IO_L16P_2|P11|I/O|
|2|IO_L17N_2/D3|IO_L17N_2/D3|P12|DUAL|
|2|IO_L17P_2/INIT_B|IO_L17P_2/INIT_B|T12|DUAL|
|2|IO_L20P_2/D1|IO_L18N_2/D1|R13|DUAL|
|2|IO_L18P_2/D2|IO_L18P_2/D2|T13|DUAL|
|2|N.C.|IO_L19N_2|P13|I/O|
|2|N.C.|IO_L19P_2|N12|I/O|
|2|IO_L20N_2/CCLK|IO_L20N_2/CCLK|R14|DUAL|



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

82 

**Spartan-3AN FPGA Family: Pinout Descriptions** 

_Table  70:_ **Spartan-3AN FTG256 Pinout (XC3S50AN (Discontinued), XC3S200AN, XC3S400AN)** _**(Cont’d)**_ 

|**Bank**|**XC3S50AN Pin Name (Discontinued)**|**XC3S200AN/XC3S400AN Pin Name**|**FTG256 Ball**|**Type**|
|---|---|---|---|---|
|2|IO_L18N_2/D0/DIN/MISO|IO_L20P_2/D0/DIN/MISO|T14|DUAL|
|2|IP_2|IP_2|L7|INPUT|
|2|IP_2|IP_2|L8|INPUT|
|2|IP_2/VREF_2|IP_2/VREF_2|L9|VREF|
|2|IP_2/VREF_2|IP_2/VREF_2|L10|VREF|
|2|IP_2/VREF_2|IP_2/VREF_2|M7|VREF|
|2|IP_2/VREF_2|IP_2/VREF_2|M8|VREF|
|2|IP_2/VREF_2|IP_2/VREF_2|M11|VREF|
|2|IP_2/VREF_2|IP_2/VREF_2|N5|VREF|
|2|VCCO_2|VCCO_2|M9|VCCO|
|2|VCCO_2|VCCO_2|R4|VCCO|
|2|VCCO_2|VCCO_2|R8|VCCO|
|2|VCCO_2|VCCO_2|R12|VCCO|
|3|IO_L01N_3|IO_L01N_3|C1|I/O|
|3|IO_L01P_3|IO_L01P_3|C2|I/O|
|3|IO_L02N_3|IO_L02N_3|D3|I/O|
|3|IO_L02P_3|IO_L02P_3|D4|I/O|
|3|IO_L03N_3|IO_L03N_3|E1|I/O|
|3|IO_L03P_3|IO_L03P_3|D1|I/O|
|3|N.C.|IO_L05N_3|E2|I/O|
|3|N.C.|IO_L05P_3|E3|I/O|
|3|N.C.|IO_L07N_3|G4|I/O|
|3|N.C.|IO_L07P_3|F3|I/O|
|3|IO_L08N_3/VREF_3|IO_L08N_3/VREF_3|G1|VREF|
|3|IO_L08P_3|IO_L08P_3|F1|I/O|
|3|N.C.|IO_L09N_3|H4|I/O|
|3|N.C.|IO_L09P_3|G3|I/O|
|3|N.C.|IO_L10N_3|H5|I/O|
|3|N.C.|IO_L10P_3|H6|I/O|
|3|IO_L11N_3/LHCLK1|IO_L11N_3/LHCLK1|H1|LHCLK|
|3|IO_L11P_3/LHCLK0|IO_L11P_3/LHCLK0|G2|LHCLK|
|3|IO_L12N_3/IRDY2/LHCLK3|IO_L12N_3/IRDY2/LHCLK3|J3|LHCLK|
|3|IO_L12P_3/LHCLK2|IO_L12P_3/LHCLK2|H3|LHCLK|
|3|IO_L14N_3/LHCLK5|IO_L14N_3/LHCLK5|J1|LHCLK|
|3|IO_L14P_3/LHCLK4|IO_L14P_3/LHCLK4|J2|LHCLK|
|3|IO_L15N_3/LHCLK7|IO_L15N_3/LHCLK7|K1|LHCLK|
|3|IO_L15P_3/TRDY2/LHCLK6|IO_L15P_3/TRDY2/LHCLK6|K3|LHCLK|
|3|N.C.|IO_L16N_3|L2|I/O|
|3|N.C.|IO_L16P_3/VREF_3|L1|VREF|
|3|N.C.|IO_L17N_3|J6|I/O|



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

83 

**Spartan-3AN FPGA Family: Pinout Descriptions** 

_Table  70:_ **Spartan-3AN FTG256 Pinout (XC3S50AN (Discontinued), XC3S200AN, XC3S400AN)** _**(Cont’d)**_ 

|**Bank**|**XC3S50AN Pin Name (Discontinued)**|**XC3S200AN/XC3S400AN Pin Name**|**FTG256 Ball**|**Type**|
|---|---|---|---|---|
|3|N.C.|IO_L17P_3|J4|I/O|
|3|N.C.|IO_L18N_3|L3|I/O|
|3|N.C.|IO_L18P_3|K4|I/O|
|3|N.C.|IO_L19N_3|L4|I/O|
|3|N.C.|IO_L19P_3|M3|I/O|
|3|IO_L20N_3|IO_L20N_3|N1|I/O|
|3|IO_L20P_3|IO_L20P_3|M1|I/O|
|3|IO_L22N_3|IO_L22N_3|P1|I/O|
|3|IO_L22P_3|IO_L22P_3|N2|I/O|
|3|IO_L23N_3|IO_L23N_3|P2|I/O|
|3|IO_L23P_3|IO_L23P_3|R1|I/O|
|3|IO_L24N_3|IO_L24N_3|M4|I/O|
|3|IO_L24P_3|IO_L24P_3|N3|I/O|
|3|IP_L04N_3/VREF_3|IP_L04N_3/VREF_3|F4|VREF|
|3|IP_L04P_3|IP_L04P_3|E4|INPUT|
|3|N.C.|IP_L06N_3/VREF_3|G5|VREF|
|3|N.C.|IP_L06P_3|G6|INPUT|
|3|IP_L13N_3|IP_L13N_3|J7|INPUT|
|3|IP_L13P_3|IP_L13P_3|H7|INPUT|
|3|IP_L21N_3|IP_L21N_3|K6|INPUT|
|3|IP_L21P_3|IP_L21P_3|K5|INPUT|
|3|IP_L25N_3/VREF_3|IP_L25N_3/VREF_3|L6|VREF|
|3|IP_L25P_3|IP_L25P_3|L5|INPUT|
|3|VCCO_3|VCCO_3|D2|VCCO|
|3|VCCO_3|VCCO_3|H2|VCCO|
|3|VCCO_3|VCCO_3|J5|VCCO|
|3|VCCO_3|VCCO_3|M2|VCCO|
|GND|GND|GND|A1|GND|
|GND|GND|GND|A16|GND|
|GND|GND|GND|B7|GND|
|GND|GND|GND|B11|GND|
|GND|GND|GND|C3|GND|
|GND|GND|GND|C14|GND|
|GND|GND|GND|E5|GND|
|GND|GND|GND|E12|GND|
|GND|GND|GND|F2|GND|
|GND|GND|GND|F6|GND|
|GND|GND|GND|G8|GND|
|GND|GND|GND|G10|GND|
|GND|GND|GND|G15|GND|



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

84 

**Spartan-3AN FPGA Family: Pinout Descriptions** 

_Table  70:_ **Spartan-3AN FTG256 Pinout (XC3S50AN (Discontinued), XC3S200AN, XC3S400AN)** _**(Cont’d)**_ 

|**Bank**|**XC3S50AN Pin Name (Discontinued)**|**XC3S200AN/XC3S400AN Pin Name**|**FTG256 Ball**|**Type**|
|---|---|---|---|---|
|GND|GND|GND|H9|GND|
|GND|GND|GND|J8|GND|
|GND|GND|GND|K2|GND|
|GND|GND|GND|K7|GND|
|GND|GND|GND|K9|GND|
|GND|GND|GND|L11|GND|
|GND|GND|GND|L15|GND|
|GND|GND|GND|M5|GND|
|GND|GND|GND|M12|GND|
|GND|GND|GND|P3|GND|
|GND|GND|GND|P14|GND|
|GND|GND|GND|R6|GND|
|GND|GND|GND|R10|GND|
|GND|GND|GND|T1|GND|
|GND|GND|GND|T16|GND|
|VCCAUX|SUSPEND|SUSPEND|R16|PWR MGMT|
|VCCAUX|DONE|DONE|T15|CONFIG|
|VCCAUX|PROG_B|PROG_B|A2|CONFIG|
|VCCAUX|TCK|TCK|A15|JTAG|
|VCCAUX|TDI|TDI|B1|JTAG|
|VCCAUX|TDO|TDO|B16|JTAG|
|VCCAUX|TMS|TMS|B2|JTAG|
|VCCAUX|VCCAUX|VCCAUX|E11|VCCAUX|
|VCCAUX|VCCAUX|VCCAUX|F5|VCCAUX|
|VCCAUX|VCCAUX|VCCAUX|L12|VCCAUX|
|VCCAUX|VCCAUX|VCCAUX|M6|VCCAUX|
|VCCINT|VCCINT|VCCINT|G7|VCCINT|
|VCCINT|VCCINT|VCCINT|G9|VCCINT|
|VCCINT|VCCINT|VCCINT|H8|VCCINT|
|VCCINT|VCCINT|VCCINT|J9|VCCINT|
|VCCINT|VCCINT|VCCINT|K8|VCCINT|
|VCCINT|VCCINT|VCCINT|K10|VCCINT|



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

85 

**Spartan-3AN FPGA Family: Pinout Descriptions** 

## **User I/Os by Bank** 

Table 71 and Table 72 indicate how the available user-I/O pins are distributed between the four I/O banks on the FTG256 package. The AWAKE pin is counted as a dual-purpose I/O. The XC3S50AN FPGA (which is discontinued in the FTG256 package) has 51 unconnected balls, labeled with an N.C. type. These pins are also indicated in Figure 20. 

_Table  71:_ **User I/Os Per Bank on XC3S50AN[(1)] in the FTG256 Package** 

|_Table  71:_**Use**|**r I/Os Per Ban**|**k on XC3S50A**|**N(1) in the FTG256 Package**|**N(1) in the FTG256 Package**|**N(1) in the FTG256 Package**|**N(1) in the FTG256 Package**|**N(1) in the FTG256 Package**|
|---|---|---|---|---|---|---|---|
|**Package**<br>**Edge**|**I/O Bank**|**Maximum I/Os**|**All Possible I/O Pins by Type**|||||
||||**I/O**|**INPUT**|**DUAL**|**VREF**|**CLK**|
|Top|0|40|21|7|1|3|8|
|Right|1|32|12|5|4|3|8|
|Bottom|2|40|5|2|21|6|6|
|Left|3|32|15|6|0|3|8|
|**Total**||**144**|**53**|**20**|**26**|**15**|**30**|



## **Notes:** 

1. Xilinx has issued a discontinuation notice for the XC3S50AN in the FT(G)256 package. See XCN13016: _Product Discontinuation Notice For Selected Spartan-3AN FPGA Products_ . 

_Table  72:_ **User I/Os Per Bank on XC3S200AN and XC3S400AN in the FTG256 Package** 

|**Package**<br>**Edge**|**I/O Bank**|**Maximum I/Os**|**All Possible I/O Pins by Type**|**All Possible I/O Pins by Type**|**All Possible I/O Pins by Type**|**All Possible I/O Pins by Type**|**All Possible I/O Pins by Type**|
|---|---|---|---|---|---|---|---|
||||**I/O**|**INPUT**|**DUAL**|**VREF**|**CLK**|
|Top|0|47|27|6|1|5|8|
|Right|1|50|1|6|30|5|8|
|Bottom|2|48|11|2|21|6|8|
|Left|3|50|30|7|0|5|8|
|**Total**||**195**|**69**|**21**|**52**|**21**|**32**|



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

86 

**Spartan-3AN FPGA Family: Pinout Descriptions** 

## **Footprint Migration Differences** 

## **Unconnected Balls on XC3S50AN (Discontinued in the FTG256 Package)** 

Table 73 summarizes any footprint and functionality differences between the XC3S50AN and the XC3S200AN or XC3S400AN devices for migration between these devices in the FTG256 package. The XC3S200AN and XC3S400AN have identical pinouts. The XC3S50AN pinout is compatible with the XC3S200AN and XC3S400AN, however, there are 51 unconnected balls and one functionally different ball. Generally, designs migrate upward from the XC3S50AN to either the XC3S200AN or XC3S400AN. If using differential I/O, see Table 74. If using the BPI configuration mode (parallel Flash), see Table 75. 

In Table 73, the arrow (→) indicates that this pin can unconditionally migrate from the device on the left to the device on the right. Migration in the other direction is possible depending on how the pin is configured for the device on the right. 

_Table  73:_ **FTG256 XC3S50AN[(1)] Footprint Migration/Differences** 

|**FTG256 Ball**|**Bank**|**XC3S50AN**|**Migration**|**XC3S200AN or XC3S400AN**|
|---|---|---|---|---|
|A7|0|N.C.|→|I/O|
|A12|0|N.C.|→|I/O|
|B12|0|INPUT|→|I/O|
|C7|0|N.C.|→|I/O|
|D10|0|N.C.|→|I/O|
|E2|3|N.C.|→|I/O|
|E3|3|N.C.|→|I/O|
|E7|0|N.C.|→|I/O/VREF|
|E10|0|N.C.|→|I/O/VREF|
|E16|1|N.C.|→|I/O|
|F3|3|N.C.|→|I/O|
|F8|0|N.C.|→|I/O|
|F14|1|N.C.|→|I/O|
|F15|1|N.C.|→|I/O|
|F16|1|N.C.|→|I/O|
|G3|3|N.C.|→|I/O|
|G4|3|N.C.|→|I/O|
|G5|3|N.C.|→|INPUT/VREF|
|G6|3|N.C.|→|INPUT|
|G13|1|N.C.|→|I/O|
|G14|1|N.C.|→|I/O|
|G16|1|N.C.|→|I/O|
|H4|3|N.C.|→|I/O|
|H5|3|N.C.|→|I/O|
|H6|3|N.C.|→|I/O|
|H13|1|N.C.|→|I/O|
|J4|3|N.C.|→|I/O|
|J6|3|N.C.|→|I/O|
|J10|1|N.C.|→|INPUT/VREF|
|J11|1|N.C.|→|INPUT|
|K4|3|N.C.|→|I/O|



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

87 

**Spartan-3AN FPGA Family: Pinout Descriptions** 

_Table  73:_ **FTG256 XC3S50AN[(1)] Footprint Migration/Differences** _**(Cont’d)**_ 

|**FTG256 Ball**|**Bank**|**XC3S50AN**|**Migration**|**XC3S200AN or XC3S400AN**|
|---|---|---|---|---|
|K13|1|N.C.|→|I/O|
|L1|3|N.C.|→|I/O/VREF|
|L2|3|N.C.|→|I/O|
|L3|3|N.C.|→|I/O|
|L4|3|N.C.|→|I/O|
|L13|1|N.C.|→|I/O|
|L14|1|N.C.|→|I/O|
|L16|1|N.C.|→|I/O|
|M3|3|N.C.|→|I/O|
|M10|2|N.C.|→|I/O|
|M13|1|N.C.|→|I/O|
|M14|1|N.C.|→|I/O/VREF|
|M15|1|N.C.|→|I/O|
|M16|1|N.C.|→|I/O|
|N7|2|N.C.|→|I/O|
|N10|2|N.C.|→|I/O|
|N12|2|N.C.|→|I/O|
|P6|2|N.C.|→|I/O|
|P13|2|N.C.|→|I/O|
|R7|2|N.C.|→|I/O|
|T7|2|N.C.|→|I/O|
|**Number of Differences:**|||52||



## **Notes:** 

1. Xilinx has issued a discontinuation notice for the XC3S50AN in the FT(G)256 package. See XCN13016: _Product Discontinuation Notice For Selected Spartan-3AN FPGA Products_ . 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

88 

**Spartan-3AN FPGA Family: Pinout Descriptions** 

## **XC3S50AN Differential I/O Alignment Differences** 

Also, some differential I/O pairs on the discontinued XC3S50AN FPGA are aligned differently than the corresponding pairs on the XC3S200AN or XC3S400AN FPGAs, as shown in Table 74. All the mismatched pairs are in I/O Bank 2. The N side of each pair is shaded. 

_Table  74:_ **Differential I/O Differences in FTG256** 

|**FTG256 Ball**|**Bank**|**XC3S50AN(1)**|**XC3S200AN or XC3S400AN**|
|---|---|---|---|
|T3|2|IO_L04P_2/VS2|IO_L03N_2/VS2|
|N6||IO_L03N_2/VS1|IO_L04P_2/VS1|
|R5||IO_L06P_2|IO_L05N_2|
|T5||IO_L05N_2/D7|IO_L06P_2/D7|
|P10||IO_L14P_2/MOSI/CSI_B|IO_L14N_2/MOSI/CSI_B|
|T10||IO_L14N_2|IO_L14P_2|
|R13||IO_L20P_2|IO_L18N_2|
|T14||IO_L18N_2|IO_L20P_2|



## **Notes:** 

1. Xilinx has issued a discontinuation notice for the XC3S50AN in the FT(G)256 package. See XCN13016: _Product Discontinuation Notice For Selected Spartan-3AN FPGA Products_ . 

## **XC3S50AN Does Not Have BPI Mode Address Outputs** 

The XC3S50AN FPGA does not generate the BPI-mode address pins during configuration. Table 75 summarizes these differences. 

_Table  75:_ **XC3S50AN BPI Functional Differences** 

|**FTG256 Ball**|**Bank**|**XC3S50AN(1)**|**XC3S200AN or XC3S400AN**|
|---|---|---|---|
|N16|1|IO_L03N_1|IO_L03N_1/A1|
|P16||IO_L03P_1|IO_L03P_1/A0|
|J13||IO_L10N_1|IO_L10N_1/A9|
|J12||IO_L10P_1|IO_L10P_1/A8|
|F13||IO_L20N_1|IO_L20N_1/A19|
|E14||IO_L20P_1|IO_L20P_1/A18|
|D15||IO_L22N_1|IO_L22N_1/A21|
|D16||IO_L22P_1|IO_L22P_1/A20|
|D14||IO_L23N_1|IO_L23N_1/A23|
|E13||IO_L23P_1|IO_L23P_1/A22|
|C15||IO_L24N_1|IO_L24N_1/A25|
|C16||IO_L24P_1|IO_L24P_1/A24|



## **Notes:** 

1. Xilinx has issued a discontinuation notice for the XC3S50AN in the FT(G)256 package. See XCN13016: _Product Discontinuation Notice For Selected Spartan-3AN FPGA Products_ . 

The Spartan-3AN FPGAs are pin compatible with the same density Spartan-3A FPGAs in the FT(G)256 package, although the Spartan-3A FPGAs require an external configuration source. 

## **FTG256 Footprint (XC3S50AN)** 

Xilinx has issued a discontinuation notice for the XC3S50AN in the FT(G)256 package. See XCN13016: _Product Discontinuation Notice For Selected Spartan-3AN FPGA Products_ . 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

89 

**Spartan-3AN FPGA Family: Pinout Descriptions** 

|**A**<br>**B**<br>**C**<br>**D**<br>**E**<br>**F**<br>**G**<br>**H**<br>**J**<br>**K**<br>**L**<br>**M**<br>**N**<br>**P**<br>**R**<br>**T**<br>**Bank 3**<br>**(High Output Drive)**<br>**(High Output Drive)**|**1**|**2**|**3**|**4**<br>**5**<br>**6**<br>**7**<br>**(Differential Outputs)**|**4**<br>**5**<br>**6**<br>**7**<br>**(Differential Outputs)**|**4**<br>**5**<br>**6**<br>**7**<br>**(Differential Outputs)**|**4**<br>**5**<br>**6**<br>**7**<br>**(Differential Outputs)**|**8**<br>**9**<br>**10**<br>**11**<br>**12**<br>**13**<br>**Bank 0**<br>**(Differential Outputs)**|**8**<br>**9**<br>**10**<br>**11**<br>**12**<br>**13**<br>**Bank 0**<br>**(Differential Outputs)**|**8**<br>**9**<br>**10**<br>**11**<br>**12**<br>**13**<br>**Bank 0**<br>**(Differential Outputs)**|**8**<br>**9**<br>**10**<br>**11**<br>**12**<br>**13**<br>**Bank 0**<br>**(Differential Outputs)**|**8**<br>**9**<br>**10**<br>**11**<br>**12**<br>**13**<br>**Bank 0**<br>**(Differential Outputs)**|**8**<br>**9**<br>**10**<br>**11**<br>**12**<br>**13**<br>**Bank 0**<br>**(Differential Outputs)**|**14**|**15**|S529-4_09_012009<br>**16**<br>**GND**<br>**TDO**<br>**I/O**<br>L24P_1<br>**I/O**<br>L22P_1<br>**N.C.**<br>**N.C.**<br>**N.C.**<br>**I/O**<br>L15N_1<br>RHCLK7<br>**I/O**<br>L12N_1<br>TRDY1<br>RHCLK3<br>**I/O**<br>L12P_1<br>RHCLK2<br>**N.C.**<br>**N.C.**<br>**I/O**<br>L03N_1<br>**I/O**<br>L03P_1<br>SUSPEND<br>**GND**<br>**Bank 1**<br>**(High Output Drive)**<br>**(High Output Drive)**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||**GND**|**PROG_B**|**I/O**<br>L19P_0|**I/O**<br>L18P_0|**I/O**<br>L17P_0|**I/O**<br>L15P_0|**N.C.**|**I/O**<br>L12P_0<br>GCLK10|**I/O**<br>L10N_0<br>GCLK7|**I/O**<br>L08N_0|**I/O**<br>L07N_0|**N.C.**|**I/O**<br>L04N_0|**I/O**<br>L04P_0|**TCK**|**GND**|
||**TDI**|**TMS**|**I/O**<br>L19N_0|**I/O**<br>L18N_0|VCCO_0|**I/O**<br>L15N_0|**GND**|**I/O**<br>L12N_0<br>GCLK11|VCCO_0|**I/O**<br>L08P_0|**GND**|**INPUT**|VCCO_0|**I/O**<br>L02N_0|**I/O**<br>L02P_0<br>VREF_0|**TDO**|
||**I/O**<br>L01N_3|**I/O**<br>L01P_3|**GND**|**I/O**<br>L20P_0<br>VREF_0|**I/O**<br>L17N_0|**I/O**<br>L16N_0|**N.C.**|**I/O**<br>L11P_0<br>GCLK8|**I/O**<br>L10P_0<br>GCLK6|**I/O**<br>L09P_0<br>GCLK4|**I/O**<br>L07P_0|**I/O**<br>L03P_0|**I/O**<br>L01N_0|**GND**|**I/O**<br>L24N_1|**I/O**<br>L24P_1|
||**I/O**<br>L03P_3|VCCO_3|**I/O**<br>L02N_3|**I/O**<br>L02P_3|**I/O**<br>L20N_0<br>PUDC_B|**INPUT**|**I/O**<br>L16P_0|**I/O**<br>L11N_0<br>GCLK9|**I/O**<br>L09N_0<br>GCLK5|**N.C.**|**I/O**<br>L03N_0|**INPUT**|**I/O**<br>L01P_0|**I/O**<br>L23N_1|**I/O**<br>L22N_1|**I/O**<br>L22P_1|
||**I/O**<br>L03N_3|**N.C.**|**N.C.**|**INPUT**<br>L04P_3|**GND**|**INPUT**|**N.C.**|VCCO_0|**INPUT**<br>VREF_0|**N.C.**|VCCAUX|**GND**|**I/O**<br>L23P_1|**I/O**<br>L20P_1|VCCO_1|**N.C.**|
||**I/O**<br>L08P_3|**GND**|**N.C.**|**INPUT**<br>L04N_3<br>VREF_3|VCCAUX|**GND**|**INPUT**|**N.C.**|**INPUT**|**INPUT**|**INPUT**<br>L25N_1|**INPUT**<br>L25P_1<br>VREF_1|**I/O**<br>L20N_1|**N.C.**|**N.C.**|**N.C.**|
||**I/O**<br>L08N_3<br>VREF_3|**I/O**<br>L11P_3<br>LHCLK0|**N.C.**|**N.C.**|**N.C.**|**N.C.**|**VCCINT**|**GND**|**VCCINT**|**GND**|**INPUT**<br>L21N_1|**INPUT**<br>L21P_1<br>VREF_1|**N.C.**|**N.C.**|**GND**|**N.C.**|
||**I/O**<br>L11N_3<br>LHCLK1|VCCO_3|**I/O**<br>L12P_3<br>LHCLK2|**N.C.**|**N.C.**|**N.C.**|**INPUT**<br>L13P_3|**VCCINT**|**GND**|**INPUT**<br>L13P_1|**INPUT**<br>L13N_1|VCCO_1|**N.C.**|**I/O**<br>L14N_1<br>RHCLK5|**I/O**<br>L15P_1<br>IRDY1<br>RHCLK6|**I/O**<br>L15N_1<br>RHCLK7|
||**I/O**<br>L14N_3<br>LHCLK5|**I/O**<br>L14P_3<br>LHCLK4|**I/O**<br>L12N_3<br>IRDY2<br>LHCLK3|**N.C.**|VCCO_3|**N.C.**|**INPUT**<br>L13N_3|**GND**|**VCCINT**|**N.C.**|**N.C.**|**I/O**<br>L10P_1|**I/O**<br>L10N_1|**I/O**<br>L14P_1<br>RHCLK4|VCCO_1|**I/O**<br>L12N_1<br>TRDY1<br>RHCLK3|
||**I/O**<br>L15N_3<br>LHCLK7|**GND**|**I/O**<br>L15P_3<br>TRDY2<br>LHCLK6|**N.C.**|**INPUT**<br>L21P_3|**INPUT**<br>L21N_3|**GND**|**VCCINT**|**GND**|**VCCINT**|**INPUT**<br>L04P_1|**INPUT**<br>L04N_1<br>VREF_1|**N.C.**|**I/O**<br>L11N_1<br>RHCLK1|**I/O**<br>L11P_1<br>RHCLK0|**I/O**<br>L12P_1<br>RHCLK2|
||**N.C.**|**N.C.**|**N.C.**|**N.C.**|**INPUT**<br>L25P_3|**INPUT**<br>L25N_3<br>VREF_3|**INPUT**|**INPUT**|**INPUT**<br>VREF_2|**INPUT**<br>VREF_2|**GND**|VCCAUX|**N.C.**|**N.C.**|**GND**|**N.C.**|
||**I/O**<br>L20P_3|VCCO_3|**N.C.**|**I/O**<br>L24N_3|**GND**|VCCAUX|**INPUT**<br>VREF_2|**INPUT**<br>VREF_2|VCCO_2|**N.C.**|**INPUT**<br>VREF_2|**GND**|**N.C.**|**N.C.**|**N.C.**|**N.C.**|
||**I/O**<br>L20N_3|**I/O**<br>L22P_3|**I/O**<br>L24P_3|**I/O**<br>L01P_2<br>M1|**INPUT**<br>VREF_2|**I/O**<br>L03N_2<br>VS1|**N.C.**|**I/O**<br>L08N_2<br>D4|**I/O**<br>L11P_2<br>GCLK0|**N.C.**|**I/O**<br>L16N_2|**N.C.**|**I/O**<br>L01P_1<br>HDC|**I/O**<br>L01N_1<br>LDC2|VCCO_1|**I/O**<br>L03N_1|
||**I/O**<br>L22N_3|**I/O**<br>L23N_3|**GND**|**I/O**<br>L01N_2<br>M0|**I/O**<br>L04N_2<br>VS0|**N.C.**|**I/O**<br>L08P_2<br>D5|**I/O**<br>L10P_2<br>GCLK14|**I/O**<br>L11N_2<br>GCLK1|**I/O**<br>L14P_2<br>MOSI<br>CSI_B|**I/O**<br>L16P_2|**I/O**<br>L17N_2<br>D3|**N.C.**|**GND**|**I/O**<br>L02N_1<br>LDC0|**I/O**<br>L03P_1|
||**I/O**<br>L23P_3|**I/O**<br>L02P_2<br>M2|**I/O**<br>L03P_2<br>RDWR_B|VCCO_2|**I/O**<br>L06P_2|**GND**|**N.C.**|VCCO_2|**I/O**<br>L12P_2<br>GCLK2|**GND**|**I/O**<br>L15N_2<br>DOUT|VCCO_2|**I/O**<br>L20P_2<br>D1|**I/O**<br>L20N_2<br>CCLK|**I/O**<br>L02P_1<br>LDC1|SUSPEND|
||**GND**|**I/O**<br>L02N_2<br>CSO_B|**I/O**<br>L04P_2<br>VS2|**I/O**<br>L05P_2|**I/O**<br>L05N_2<br>D7|**I/O**<br>L06N_2<br>D6|**N.C.**|**I/O**<br>L10N_2<br>GCLK15|**I/O**<br>L12N_2<br>GCLK3|**I/O**<br>L14N_2|**I/O**<br>L15P_2<br>AWAKE|**I/O**<br>L17P_2<br>INIT_B|**I/O**<br>L18P_2<br>D2|**I/O**<br>L18N_2<br>D0<br>DIN/MISO|**DONE**|**GND**|
||||**(Differential Outputs)**|||||**Bank 2**<br>**(Differential Outputs)**|||||||D||



_Figure 20:_ **XC3S50AN FTG256 Package Footprint (Top View)** 

**I/O:** Unrestricted, **DUAL:** Configuration pins, **VREF:** User I/O or input **SUSPEND:** Dedicated 53 25 15 2 general-purpose user I/O then possible user I/O voltage reference for bank SUSPEND and dual-purpose AWAKE **INPUT:** Unrestricted, **CLK:** User I/O, input, or **VCCO:** Output voltage Power Management pins 20 30 16 general-purpose input pin global buffer input supply for bank **CONFIG:** Dedicated **JTAG:** Dedicated JTAG **VCCINT:** Internal core 2 4 6 configuration pins port pins supply voltage (+1.2V) **N.C.:** Not connected **GND:** Ground **VCCAUX:** Auxiliary supply 51 28 4 (XC3S50AN only) voltage 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

90 

**Spartan-3AN FPGA Family: Pinout Descriptions** 

## **FTG256 Footprint (XC3S200AN, XC3S400AN)** 

|**A**<br>**B**<br>**C**<br>**D**<br>**E**<br>**F**<br>**G**<br>**H**<br>**J**<br>**K**<br>**L**<br>**M**<br>**N**<br>**P**<br>**R**<br>**T**<br>**Bank 3**|**1**|**2**|**3**|**4**|**5**|**6**|**7**|**8**<br>**9**<br>**10**<br>**Bank 0**|**8**<br>**9**<br>**10**<br>**Bank 0**|**8**<br>**9**<br>**10**<br>**Bank 0**|**11**|**12**|**13**|**14**|**15**|**16**<br>**GND**<br>**TDO**<br>**I/O**<br>L24P_1<br>A24<br>**I/O**<br>L22P_1<br>A20<br>**I/O**<br>L18P_1<br>A14<br>**I/O**<br>L16N_1<br>A11<br>**I/O**<br>L16P_1<br>A10<br>**I/O**<br>L15N_1<br>RHCLK7<br>**I/O**<br>L12N_1<br>TRDY1<br>RHCLK3<br>**I/O**<br>L12P_1<br>RHCLK2<br>**I/O**<br>L08N_1<br>A7<br>**I/O**<br>L07N_1<br>A5<br>**I/O**<br>L03N_1<br>A1<br>**I/O**<br>L03P_1<br>A0<br>SUSPEND<br>**GND**<br>**Bank 1**<br>529-4_06_012009|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||**GND**|**PROG_B**|**I/O**<br>L19P_0|**I/O**<br>L18P_0|**I/O**<br>L17P_0|**I/O**<br>L15P_0|**I/O**<br>L13P_0|**I/O**<br>L12P_0<br>GCLK10|**I/O**<br>L10N_0<br>GCLK7|**I/O**<br>L08N_0|**I/O**<br>L07N_0|**I/O**<br>L05N_0|**I/O**<br>L04N_0|**I/O**<br>L04P_0|**TCK**|**GND**|
||**TDI**|**TMS**|**I/O**<br>L19N_0|**I/O**<br>L18N_0|VCCO_0|**I/O**<br>L15N_0|**GND**|**I/O**<br>L12N_0<br>GCLK11|VCCO_0|**I/O**<br>L08P_0|**GND**|**I/O**<br>L05P_0|VCCO_0|**I/O**<br>L02N_0|**I/O**<br>L02P_0<br>VREF_0|**TDO**|
||**I/O**<br>L01N_3|**I/O**<br>L01P_3|**GND**|**I/O**<br>L20P_0<br>VREF_0|**I/O**<br>L17N_0|**I/O**<br>L16N_0|**I/O**<br>L13N_0|**I/O**<br>L11P_0<br>GCLK8|**I/O**<br>L10P_0<br>GCLK6|**I/O**<br>L09P_0<br>GCLK4|**I/O**<br>L07P_0|**I/O**<br>L03P_0|**I/O**<br>L01N_0|**GND**|**I/O**<br>L24N_1<br>A25|**I/O**<br>L24P_1<br>A24|
||**I/O**<br>L03P_3|VCCO_3|**I/O**<br>L02N_3|**I/O**<br>L02P_3|**I/O**<br>L20N_0<br>PUDC_B|**INPUT**|**I/O**<br>L16P_0|**I/O**<br>L11N_0<br>GCLK9|**I/O**<br>L09N_0<br>GCLK5|**I/O**<br>L06P_0|**I/O**<br>L03N_0|**INPUT**|**I/O**<br>L01P_0|**I/O**<br>L23N_1<br>A23|**I/O**<br>L22N_1<br>A21|**I/O**<br>L22P_1<br>A20|
||**I/O**<br>L03N_3|**I/O**<br>L05N_3|**I/O**<br>L05P_3|**INPUT**<br>L04P_3|**GND**|**INPUT**|**I/O**<br>L14N_0<br>VREF_0|VCCO_0|**INPUT**<br>VREF_0|**I/O**<br>L06N_0<br>VREF_0|VCCAUX|**GND**|**I/O**<br>L23P_1<br>A22|**I/O**<br>L20P_1<br>A18|VCCO_1|**I/O**<br>L18P_1<br>A14|
||**I/O**<br>L08P_3|**GND**|**I/O**<br>L07P_3|**INPUT**<br>L04N_3<br>VREF_3|VCCAUX|**GND**|**INPUT**|**I/O**<br>L14P_0|**INPUT**|**INPUT**|**INPUT**<br>L25N_1|**INPUT**<br>L25P_1<br>VREF_1|**I/O**<br>L20N_1<br>A19|**I/O**<br>L19N_1<br>A17|**I/O**<br>L18N_1<br>A15|**I/O**<br>L16N_1<br>A11|
||**I/O**<br>L08N_3<br>VREF_3|**I/O**<br>L11P_3<br>LHCLK0|**I/O**<br>L09P_3|**I/O**<br>L07N_3|**INPUT**<br>L06N_3<br>VREF_3|**INPUT**<br>L06P_3|**VCCINT**|**GND**|**VCCINT**|**GND**|**INPUT**<br>L21N_1|**INPUT**<br>L21P_1<br>VREF_1|**I/O**<br>L19P_1<br>A16|**I/O**<br>L17N_1<br>A13|**GND**|**I/O**<br>L16P_1<br>A10|
||**I/O**<br>L11N_3<br>LHCLK1|VCCO_3|**I/O**<br>L12P_3<br>LHCLK2|**I/O**<br>L09N_3|**I/O**<br>L10N_3|**I/O**<br>L10P_3|**INPUT**<br>L13P_3|**VCCINT**|**GND**|**INPUT**<br>L13P_1|**INPUT**<br>L13N_1|VCCO_1|**I/O**<br>L17P_1<br>A12|**I/O**<br>L14N_1<br>RHCLK5|**I/O**<br>L15P_1<br>IRDY1<br>RHCLK6|**I/O**<br>L15N_1<br>RHCLK7|
||**I/O**<br>L14N_3<br>LHCLK5|**I/O**<br>L14P_3<br>LHCLK4|**I/O**<br>L12N_3<br>IRDY2<br>LHCLK3|**I/O**<br>L17P_3|VCCO_3|**I/O**<br>L17N_3|**INPUT**<br>L13N_3|**GND**|**VCCINT**|**INPUT**<br>L09P_1<br>VREF_1|**INPUT**<br>L09N_1|**I/O**<br>L10P_1<br>A8|**I/O**<br>L10N_1<br>A9|**I/O**<br>L14P_1<br>RHCLK4|VCCO_1|**I/O**<br>L12N_1<br>TRDY1<br>RHCLK3|
||**I/O**<br>L15N_3<br>LHCLK7|**GND**|**I/O**<br>L15P_3<br>TRDY2<br>LHCLK6|**I/O**<br>L18P_3|**INPUT**<br>L21P_3|**INPUT**<br>L21N_3|**GND**|**VCCINT**|**GND**|**VCCINT**|**INPUT**<br>L04P_1|**INPUT**<br>L04N_1<br>VREF_1|**I/O**<br>L06N_1<br>A3|**I/O**<br>L11N_1<br>RHCLK1|**I/O**<br>L11P_1<br>RHCLK0|**I/O**<br>L12P_1<br>RHCLK2|
||**I/O**<br>L16P_3<br>VREF_3|**I/O**<br>L16N_3|**I/O**<br>L18N_3|**I/O**<br>L19N_3|**INPUT**<br>L25P_3|**INPUT**<br>L25N_3<br>VREF_3|**INPUT**|**INPUT**|**INPUT**<br>VREF_2|**INPUT**<br>VREF_2|**GND**|VCCAUX|**I/O**<br>L06P_1<br>A2|**I/O**<br>L08P_1<br>A6|**GND**|**I/O**<br>L08N_1<br>A7|
||**I/O**<br>L20P_3|VCCO_3|**I/O**<br>L19P_3|**I/O**<br>L24N_3|**GND**|VCCAUX|**INPUT**<br>VREF_2|**INPUT**<br>VREF_2|VCCO_2|**I/O**<br>L13N_2|**INPUT**<br>VREF_2|**GND**|**I/O**<br>L05P_1|**I/O**<br>L05N_1<br>VREF_1|**I/O**<br>L07P_1<br>A4|**I/O**<br>L07N_1<br>A5|
||**I/O**<br>L20N_3|**I/O**<br>L22P_3|**I/O**<br>L24P_3|**I/O**<br>L01P_2<br>M1|**INPUT**<br>VREF_2|**I/O**<br>L04P_2<br>VS1|**I/O**<br>L07P_2|**I/O**<br>L08N_2<br>D4|**I/O**<br>L11P_2<br>GCLK0|**I/O**<br>L13P_2|**I/O**<br>L16N_2|**I/O**<br>L19P_2|**I/O**<br>L01P_1<br>HDC|**I/O**<br>L01N_1<br>LDC2|VCCO_1|**I/O**<br>L03N_1<br>A1|
||**I/O**<br>L22N_3|**I/O**<br>L23N_3|**GND**|**I/O**<br>L01N_2<br>M0|**I/O**<br>L04N_2<br>VS0|**I/O**<br>L07N_2|**I/O**<br>L08P_2<br>D5|**I/O**<br>L10P_2<br>GCLK14|**I/O**<br>L11N_2<br>GCLK1|**I/O**<br>L14N_2<br>MOSI<br>CSI_B|**I/O**<br>L16P_2|**I/O**<br>L17N_2<br>D3|**I/O**<br>L19N_2|**GND**|**I/O**<br>L02N_1<br>LDC0|**I/O**<br>L03P_1<br>A0|
||**I/O**<br>L23P_3|**I/O**<br>L02P_2<br>M2|**I/O**<br>L03P_2<br>RDWR_B|VCCO_2|**I/O**<br>L05N_2|**GND**|**I/O**<br>L09P_2<br>GCLK12|VCCO_2|**I/O**<br>L12P_2<br>GCLK2|**GND**|**I/O**<br>L15N_2<br>DOUT|VCCO_2|**I/O**<br>L18N_2<br>D1|**I/O**<br>L20N_2<br>CCLK|**I/O**<br>L02P_1<br>LDC1|SUSPEND|
||**GND**|**I/O**<br>L02N_2<br>CSO_B|**I/O**<br>L03N_2<br>VS2|**I/O**<br>L05P_2|**I/O**<br>L06P_2<br>D7|**I/O**<br>L06N_2<br>D6|**I/O**<br>L09N_2<br>GCLK13|**I/O**<br>L10N_2<br>GCLK15|**I/O**<br>L12N_2<br>GCLK3|**I/O**<br>L14P_2|**I/O**<br>L15P_2<br>AWAKE|**I/O**<br>L17P_2<br>INIT_B|**I/O**<br>L18P_2<br>D2|**I/O**<br>L20P_2<br>D0<br>DIN/MISO|**DONE**|**GND**|
|||||||||**Bank 2**|||||||DS||



_Figure 21:_ **XC3S200AN and XC3S400AN FPGA in FTG256 Package Footprint (Top View)** 

**I/O:** Unrestricted, **DUAL:** Configuration pins, **VREF:** User I/O or input **SUSPEND:** Dedicated 69 51 21 2 general-purpose user I/O then possible user I/O voltage reference for bank SUSPEND and dual-purpose AWAKE **INPUT:** Unrestricted, **CLK:** User I/O, input, or **VCCO:** Output voltage 21 32 16 Power Management pins general-purpose input pin global buffer input supply for bank **CONFIG:** Dedicated **JTAG:** Dedicated JTAG **VCCINT:** Internal core 2 4 6 configuration pins port pins supply voltage (+1.2V) **N.C.:** Not connected **GND:** Ground **VCCAUX:** Auxiliary supply 0 28 4 voltage 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

91 

**Spartan-3AN FPGA Family: Pinout Descriptions** 

## **FGG400: 400-Ball Fine-Pitch Ball Grid Array** 

The 400-ball fine-pitch ball grid array, FGG400, supports the XC3S400AN FPGA as shown in Table 76 and Figure 22. 

Table 76 lists all the FGG400 package pins. They are sorted by bank number and then by pin name. Pins that form a differential I/O pair appear together in the table. The table also shows the pin number for each pin and the pin type (as defined in Table 62). 

An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at: www.xilinx.com/support/documentation/data_sheets/s3a_pin.zip. 

## **Pinout Table** 

_Table  76:_ **Spartan-3AN FGG400 Pinout** 

|**Bank**|**Pin Name**|**FGG400**<br>**Ball**|<br>**Type**|
|---|---|---|---|
|0|IO_L01N_0|A18|I/O|
|0|IO_L01P_0|B18|I/O|
|0|IO_L02N_0|C17|I/O|
|0|IO_L02P_0/VREF_0|D17|VREF|
|0|IO_L03N_0|E15|I/O|
|0|IO_L03P_0|D16|I/O|
|0|IO_L04N_0|A17|I/O|
|0|IO_L04P_0/VREF_0|B17|VREF|
|0|IO_L05N_0|A16|I/O|
|0|IO_L05P_0|C16|I/O|
|0|IO_L06N_0|C15|I/O|
|0|IO_L06P_0|D15|I/O|
|0|IO_L07N_0|A14|I/O|
|0|IO_L07P_0|C14|I/O|
|0|IO_L08N_0|A15|I/O|
|0|IO_L08P_0|B15|I/O|
|0|IO_L09N_0|F13|I/O|
|0|IO_L09P_0|E13|I/O|
|0|IO_L10N_0/VREF_0|C13|VREF|
|0|IO_L10P_0|D14|I/O|
|0|IO_L11N_0|C12|I/O|
|0|IO_L11P_0|B13|I/O|
|0|IO_L12N_0|F12|I/O|
|0|IO_L12P_0|D12|I/O|
|0|IO_L13N_0|A12|I/O|
|0|IO_L13P_0|B12|I/O|
|0|IO_L14N_0|C11|I/O|
|0|IO_L14P_0|B11|I/O|
|0|IO_L15N_0/GCLK5|E11|GCLK|
|0|IO_L15P_0/GCLK4|D11|GCLK|
|0|IO_L16N_0/GCLK7|C10|GCLK|



_Table  76:_ **Spartan-3AN FGG400 Pinout** _**(Cont’d)**_ 

|**Bank**|**Pin Name**|**FGG400**<br>**Ball**|<br>**Type**|
|---|---|---|---|
|0|IO_L16P_0/GCLK6|A10|GCLK|
|0|IO_L17N_0/GCLK9|E10|GCLK|
|0|IO_L17P_0/GCLK8|D10|GCLK|
|0|IO_L18N_0/GCLK11|A8|GCLK|
|0|IO_L18P_0/GCLK10|A9|GCLK|
|0|IO_L19N_0|C9|I/O|
|0|IO_L19P_0|B9|I/O|
|0|IO_L20N_0|C8|I/O|
|0|IO_L20P_0|B8|I/O|
|0|IO_L21N_0|D8|I/O|
|0|IO_L21P_0|C7|I/O|
|0|IO_L22N_0/VREF_0|F9|VREF|
|0|IO_L22P_0|E9|I/O|
|0|IO_L23N_0|F8|I/O|
|0|IO_L23P_0|E8|I/O|
|0|IO_L24N_0|A7|I/O|
|0|IO_L24P_0|B7|I/O|
|0|IO_L25N_0|C6|I/O|
|0|IO_L25P_0|A6|I/O|
|0|IO_L26N_0|B5|I/O|
|0|IO_L26P_0|A5|I/O|
|0|IO_L27N_0|F7|I/O|
|0|IO_L27P_0|E7|I/O|
|0|IO_L28N_0|D6|I/O|
|0|IO_L28P_0|C5|I/O|
|0|IO_L29N_0|C4|I/O|
|0|IO_L29P_0|A4|I/O|
|0|IO_L30N_0|B3|I/O|
|0|IO_L30P_0|A3|I/O|
|0|IO_L31N_0|F6|I/O|
|0|IO_L31P_0|E6|I/O|



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

92 

**Spartan-3AN FPGA Family: Pinout Descriptions** 

_Table  76:_ **Spartan-3AN FGG400 Pinout** _**(Cont’d)**_ 

|**Bank**|**Pin Name**|**FGG400**<br>**Ball**|<br>**Type**|
|---|---|---|---|
|0|IO_L32N_0/PUDC_B|B2|DUAL|
|0|IO_L32P_0/VREF_0|A2|VREF|
|0|IP_0|E14|INPUT|
|0|IP_0|F11|INPUT|
|0|IP_0|F14|INPUT|
|0|IP_0|G8|INPUT|
|0|IP_0|G9|INPUT|
|0|IP_0|G10|INPUT|
|0|IP_0|G12|INPUT|
|0|IP_0|G13|INPUT|
|0|IP_0|H9|INPUT|
|0|IP_0|H10|INPUT|
|0|IP_0|H11|INPUT|
|0|IP_0|H12|INPUT|
|0|IP_0/VREF_0|G11|VREF|
|0|VCCO_0|B4|VCCO|
|0|VCCO_0|B10|VCCO|
|0|VCCO_0|B16|VCCO|
|0|VCCO_0|D7|VCCO|
|0|VCCO_0|D13|VCCO|
|0|VCCO_0|F10|VCCO|
|1|IO_L01N_1/LDC2|V20|DUAL|
|1|IO_L01P_1/HDC|W20|DUAL|
|1|IO_L02N_1/LDC0|U18|DUAL|
|1|IO_L02P_1/LDC1|V19|DUAL|
|1|IO_L03N_1/A1|R16|DUAL|
|1|IO_L03P_1/A0|T17|DUAL|
|1|IO_L05N_1|T20|I/O|
|1|IO_L05P_1|T18|I/O|
|1|IO_L06N_1|U20|I/O|
|1|IO_L06P_1|U19|I/O|
|1|IO_L07N_1|P17|I/O|
|1|IO_L07P_1|P16|I/O|
|1|IO_L08N_1|R17|I/O|
|1|IO_L08P_1|R18|I/O|
|1|IO_L09N_1|R20|I/O|
|1|IO_L09P_1|R19|I/O|
|1|IO_L10N_1/VREF_1|P20|VREF|
|1|IO_L10P_1|P18|I/O|
|1|IO_L12N_1/A3|N17|DUAL|



_Table  76:_ **Spartan-3AN FGG400 Pinout** _**(Cont’d)**_ 

|**Bank**|**Pin Name**|**FGG400**<br>**Ball**|<br>**Type**|
|---|---|---|---|
|1|IO_L12P_1/A2|N15|DUAL|
|1|IO_L13N_1/A5|N19|DUAL|
|1|IO_L13P_1/A4|N18|DUAL|
|1|IO_L14N_1/A7|M18|DUAL|
|1|IO_L14P_1/A6|M17|DUAL|
|1|IO_L16N_1/A9|L16|DUAL|
|1|IO_L16P_1/A8|L15|DUAL|
|1|IO_L17N_1/RHCLK1|M20|RHCLK|
|1|IO_L17P_1/RHCLK0|M19|RHCLK|
|1|IO_L18N_1/TRDY1/RHCLK3|L18|RHCLK|
|1|IO_L18P_1/RHCLK2|L19|RHCLK|
|1|IO_L20N_1/RHCLK5|L17|RHCLK|
|1|IO_L20P_1/RHCLK4|K18|RHCLK|
|1|IO_L21N_1/RHCLK7|J20|RHCLK|
|1|IO_L21P_1/IRDY1/RHCLK6|K20|RHCLK|
|1|IO_L22N_1/A11|J18|DUAL|
|1|IO_L22P_1/A10|J19|DUAL|
|1|IO_L24N_1|K16|I/O|
|1|IO_L24P_1|J17|I/O|
|1|IO_L25N_1/A13|H18|DUAL|
|1|IO_L25P_1/A12|H19|DUAL|
|1|IO_L26N_1/A15|G20|DUAL|
|1|IO_L26P_1/A14|H20|DUAL|
|1|IO_L28N_1|H17|I/O|
|1|IO_L28P_1|G18|I/O|
|1|IO_L29N_1/A17|F19|DUAL|
|1|IO_L29P_1/A16|F20|DUAL|
|1|IO_L30N_1/A19|F18|DUAL|
|1|IO_L30P_1/A18|G17|DUAL|
|1|IO_L32N_1|E19|I/O|
|1|IO_L32P_1|E20|I/O|
|1|IO_L33N_1|F17|I/O|
|1|IO_L33P_1|E18|I/O|
|1|IO_L34N_1|D18|I/O|
|1|IO_L34P_1|D20|I/O|
|1|IO_L36N_1/A21|F16|DUAL|
|1|IO_L36P_1/A20|G16|DUAL|
|1|IO_L37N_1/A23|C19|DUAL|
|1|IO_L37P_1/A22|C20|DUAL|
|1|IO_L38N_1/A25|B19|DUAL|



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

93 

**Spartan-3AN FPGA Family: Pinout Descriptions** 

_Table  76:_ **Spartan-3AN FGG400 Pinout** _**(Cont’d)**_ 

|**Bank**|**Pin Name**|**FGG400**<br>**Ball**|<br>**Type**|
|---|---|---|---|
|1|IO_L38P_1/A24|B20|DUAL|
|1|IP_1/VREF_1|N14|VREF|
|1|IP_L04N_1/VREF_1|P15|VREF|
|1|IP_L04P_1|P14|INPUT|
|1|IP_L11N_1/VREF_1|M15|VREF|
|1|IP_L11P_1|M16|INPUT|
|1|IP_L15N_1|M13|INPUT|
|1|IP_L15P_1/VREF_1|M14|VREF|
|1|IP_L19N_1|L13|INPUT|
|1|IP_L19P_1|L14|INPUT|
|1|IP_L23N_1|K14|INPUT|
|1|IP_L23P_1/VREF_1|K15|VREF|
|1|IP_L27N_1|J15|INPUT|
|1|IP_L27P_1|J16|INPUT|
|1|IP_L31N_1|J13|INPUT|
|1|IP_L31P_1/VREF_1|J14|VREF|
|1|IP_L35N_1|H14|INPUT|
|1|IP_L35P_1|H15|INPUT|
|1|IP_L39N_1|G14|INPUT|
|1|IP_L39P_1/VREF_1|G15|VREF|
|1|VCCO_1|D19|VCCO|
|1|VCCO_1|H16|VCCO|
|1|VCCO_1|K19|VCCO|
|1|VCCO_1|N16|VCCO|
|1|VCCO_1|T19|VCCO|
|2|IO_L01N_2/M0|V4|DUAL|
|2|IO_L01P_2/M1|U4|DUAL|
|2|IO_L02N_2/CSO_B|Y2|DUAL|
|2|IO_L02P_2/M2|W3|DUAL|
|2|IO_L03N_2|W4|I/O|
|2|IO_L03P_2|Y3|I/O|
|2|IO_L04N_2|R7|I/O|
|2|IO_L04P_2|T6|I/O|
|2|IO_L05N_2|U5|I/O|
|2|IO_L05P_2|V5|I/O|
|2|IO_L06N_2|U6|I/O|
|2|IO_L06P_2|T7|I/O|
|2|IO_L07N_2/VS2|U7|DUAL|
|2|IO_L07P_2/RDWR_B|T8|DUAL|
|2|IO_L08N_2|Y5|I/O|



_Table  76:_ **Spartan-3AN FGG400 Pinout** _**(Cont’d)**_ 

|**Bank**|**Pin Name**|**FGG400**<br>**Ball**|<br>**Type**|
|---|---|---|---|
|2|IO_L08P_2|Y4|I/O|
|2|IO_L09N_2/VS0|W6|DUAL|
|2|IO_L09P_2/VS1|V6|DUAL|
|2|IO_L10N_2|Y7|I/O|
|2|IO_L10P_2|Y6|I/O|
|2|IO_L11N_2|U9|I/O|
|2|IO_L11P_2|T9|I/O|
|2|IO_L12N_2/D6|W8|DUAL|
|2|IO_L12P_2/D7|V7|DUAL|
|2|IO_L13N_2|V9|I/O|
|2|IO_L13P_2|V8|I/O|
|2|IO_L14N_2/D4|T10|DUAL|
|2|IO_L14P_2/D5|U10|DUAL|
|2|IO_L15N_2/GCLK13|Y9|GCLK|
|2|IO_L15P_2/GCLK12|W9|GCLK|
|2|IO_L16N_2/GCLK15|W10|GCLK|
|2|IO_L16P_2/GCLK14|V10|GCLK|
|2|IO_L17N_2/GCLK1|V11|GCLK|
|2|IO_L17P_2/GCLK0|Y11|GCLK|
|2|IO_L18N_2/GCLK3|V12|GCLK|
|2|IO_L18P_2/GCLK2|U11|GCLK|
|2|IO_L19N_2|R12|I/O|
|2|IO_L19P_2|T12|I/O|
|2|IO_L20N_2/MOSI/CSI_B|W12|DUAL|
|2|IO_L20P_2|Y12|I/O|
|2|IO_L21N_2|W13|I/O|
|2|IO_L21P_2|Y13|I/O|
|2|IO_L22N_2/DOUT|V13|DUAL|
|2|IO_L22P_2/AWAKE|U13|PWR MGMT|
|2|IO_L23N_2|R13|I/O|
|2|IO_L23P_2|T13|I/O|
|2|IO_L24N_2/D3|W14|DUAL|
|2|IO_L24P_2/INIT_B|Y14|DUAL|
|2|IO_L25N_2|T14|I/O|
|2|IO_L25P_2|V14|I/O|
|2|IO_L26N_2/D1|V15|DUAL|
|2|IO_L26P_2/D2|Y15|DUAL|
|2|IO_L27N_2|T15|I/O|
|2|IO_L27P_2|U15|I/O|
|2|IO_L28N_2|W16|I/O|



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

94 

**Spartan-3AN FPGA Family: Pinout Descriptions** 

_Table  76:_ **Spartan-3AN FGG400 Pinout** _**(Cont’d)**_ 

|**Bank**|**Pin Name**|**FGG400**<br>**Ball**|<br>**Type**|
|---|---|---|---|
|2|IO_L28P_2|Y16|I/O|
|2|IO_L29N_2|U16|I/O|
|2|IO_L29P_2|V16|I/O|
|2|IO_L30N_2|Y18|I/O|
|2|IO_L30P_2|Y17|I/O|
|2|IO_L31N_2|U17|I/O|
|2|IO_L31P_2|V17|I/O|
|2|IO_L32N_2/CCLK|Y19|DUAL|
|2|IO_L32P_2/D0/DIN/MISO|W18|DUAL|
|2|IP_2|P9|INPUT|
|2|IP_2|P12|INPUT|
|2|IP_2|P13|INPUT|
|2|IP_2|R8|INPUT|
|2|IP_2|R10|INPUT|
|2|IP_2|T11|INPUT|
|2|IP_2/VREF_2|N9|VREF|
|2|IP_2/VREF_2|N12|VREF|
|2|IP_2/VREF_2|P8|VREF|
|2|IP_2/VREF_2|P10|VREF|
|2|IP_2/VREF_2|P11|VREF|
|2|IP_2/VREF_2|R14|VREF|
|2|VCCO_2|R11|VCCO|
|2|VCCO_2|U8|VCCO|
|2|VCCO_2|U14|VCCO|
|2|VCCO_2|W5|VCCO|
|2|VCCO_2|W11|VCCO|
|2|VCCO_2|W17|VCCO|
|3|IO_L01N_3|D3|I/O|
|3|IO_L01P_3|D4|I/O|
|3|IO_L02N_3|C2|I/O|
|3|IO_L02P_3|B1|I/O|
|3|IO_L03N_3|D2|I/O|
|3|IO_L03P_3|C1|I/O|
|3|IO_L05N_3|E1|I/O|
|3|IO_L05P_3|D1|I/O|
|3|IO_L06N_3|G5|I/O|
|3|IO_L06P_3|F4|I/O|
|3|IO_L07N_3|J5|I/O|
|3|IO_L07P_3|J6|I/O|
|3|IO_L08N_3|H4|I/O|



_Table  76:_ **Spartan-3AN FGG400 Pinout** _**(Cont’d)**_ 

|**Bank**|**Pin Name**|**FGG400**<br>**Ball**|<br>**Type**|
|---|---|---|---|
|3|IO_L08P_3|H6|I/O|
|3|IO_L09N_3|G4|I/O|
|3|IO_L09P_3|F3|I/O|
|3|IO_L10N_3|F2|I/O|
|3|IO_L10P_3|E3|I/O|
|3|IO_L12N_3|H2|I/O|
|3|IO_L12P_3|G3|I/O|
|3|IO_L13N_3/VREF_3|G1|VREF|
|3|IO_L13P_3|F1|I/O|
|3|IO_L14N_3|H3|I/O|
|3|IO_L14P_3|J4|I/O|
|3|IO_L16N_3|J2|I/O|
|3|IO_L16P_3|J3|I/O|
|3|IO_L17N_3/LHCLK1|K2|LHCLK|
|3|IO_L17P_3/LHCLK0|J1|LHCLK|
|3|IO_L18N_3/IRDY2/LHCLK3|L3|LHCLK|
|3|IO_L18P_3/LHCLK2|K3|LHCLK|
|3|IO_L20N_3/LHCLK5|L5|LHCLK|
|3|IO_L20P_3/LHCLK4|K4|LHCLK|
|3|IO_L21N_3/LHCLK7|M1|LHCLK|
|3|IO_L21P_3/TRDY2/LHCLK6|L1|LHCLK|
|3|IO_L22N_3|M3|I/O|
|3|IO_L22P_3/VREF_3|M2|VREF|
|3|IO_L24N_3|M5|I/O|
|3|IO_L24P_3|M4|I/O|
|3|IO_L25N_3|N2|I/O|
|3|IO_L25P_3|N1|I/O|
|3|IO_L26N_3|N4|I/O|
|3|IO_L26P_3|N3|I/O|
|3|IO_L28N_3|R1|I/O|
|3|IO_L28P_3|P1|I/O|
|3|IO_L29N_3|P4|I/O|
|3|IO_L29P_3|P3|I/O|
|3|IO_L30N_3|R3|I/O|
|3|IO_L30P_3|R2|I/O|
|3|IO_L32N_3|T2|I/O|
|3|IO_L32P_3/VREF_3|T1|VREF|
|3|IO_L33N_3|R4|I/O|
|3|IO_L33P_3|T3|I/O|
|3|IO_L34N_3|U3|I/O|



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

95 

**Spartan-3AN FPGA Family: Pinout Descriptions** 

_Table  76:_ **Spartan-3AN FGG400 Pinout** _**(Cont’d)**_ 

|**Bank**|**Pin Name**|**FGG400**<br>**Ball**|<br>**Type**|
|---|---|---|---|
|3|IO_L34P_3|U1|I/O|
|3|IO_L36N_3|T4|I/O|
|3|IO_L36P_3|R5|I/O|
|3|IO_L37N_3|V2|I/O|
|3|IO_L37P_3|V1|I/O|
|3|IO_L38N_3|W2|I/O|
|3|IO_L38P_3|W1|I/O|
|3|IP_3|H7|INPUT|
|3|IP_L04N_3/VREF_3|G6|VREF|
|3|IP_L04P_3|G7|INPUT|
|3|IP_L11N_3/VREF_3|J7|VREF|
|3|IP_L11P_3|J8|INPUT|
|3|IP_L15N_3|K7|INPUT|
|3|IP_L15P_3|K8|INPUT|
|3|IP_L19N_3|K5|INPUT|
|3|IP_L19P_3|K6|INPUT|
|3|IP_L23N_3|L6|INPUT|
|3|IP_L23P_3|L7|INPUT|
|3|IP_L27N_3|M7|INPUT|
|3|IP_L27P_3|M8|INPUT|
|3|IP_L31N_3|N7|INPUT|
|3|IP_L31P_3|M6|INPUT|
|3|IP_L35N_3|N6|INPUT|
|3|IP_L35P_3|P5|INPUT|
|3|IP_L39N_3/VREF_3|P7|VREF|
|3|IP_L39P_3|P6|INPUT|
|3|VCCO_3|E2|VCCO|
|3|VCCO_3|H5|VCCO|
|3|VCCO_3|L2|VCCO|
|3|VCCO_3|N5|VCCO|
|3|VCCO_3|U2|VCCO|
|GND|GND|A1|GND|
|GND|GND|A11|GND|
|GND|GND|A20|GND|
|GND|GND|B6|GND|
|GND|GND|B14|GND|
|GND|GND|C3|GND|
|GND|GND|C18|GND|
|GND|GND|D9|GND|
|GND|GND|E5|GND|



_Table  76:_ **Spartan-3AN FGG400 Pinout** _**(Cont’d)**_ 

|**Bank**|**Pin Name**|**FGG400**<br>**Ball**|<br>**Type**|
|---|---|---|---|
|GND|GND|E12|GND|
|GND|GND|F15|GND|
|GND|GND|G2|GND|
|GND|GND|G19|GND|
|GND|GND|H8|GND|
|GND|GND|H13|GND|
|GND|GND|J9|GND|
|GND|GND|J11|GND|
|GND|GND|K1|GND|
|GND|GND|K10|GND|
|GND|GND|K12|GND|
|GND|GND|K17|GND|
|GND|GND|L4|GND|
|GND|GND|L9|GND|
|GND|GND|L11|GND|
|GND|GND|L20|GND|
|GND|GND|M10|GND|
|GND|GND|M12|GND|
|GND|GND|N8|GND|
|GND|GND|N11|GND|
|GND|GND|N13|GND|
|GND|GND|P2|GND|
|GND|GND|P19|GND|
|GND|GND|R6|GND|
|GND|GND|R9|GND|
|GND|GND|T16|GND|
|GND|GND|U12|GND|
|GND|GND|V3|GND|
|GND|GND|V18|GND|
|GND|GND|W7|GND|
|GND|GND|W15|GND|
|GND|GND|Y1|GND|
|GND|GND|Y10|GND|
|GND|GND|Y20|GND|
|VCCAUX|SUSPEND|R15|PWR MGMT|
|VCCAUX|DONE|W19|CONFIG|
|VCCAUX|PROG_B|D5|CONFIG|
|VCCAUX|TCK|A19|JTAG|
|VCCAUX|TDI|F5|JTAG|
|VCCAUX|TDO|E17|JTAG|



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

96 

**Spartan-3AN FPGA Family: Pinout Descriptions** 

_Table  76:_ **Spartan-3AN FGG400 Pinout** _**(Cont’d)**_ 

|**Bank**|**Pin Name**|**FGG400**<br>**Ball**|<br>**Type**|
|---|---|---|---|
|VCCAUX|TMS|E4|JTAG|
|VCCAUX|VCCAUX|A13|VCCAUX|
|VCCAUX|VCCAUX|E16|VCCAUX|
|VCCAUX|VCCAUX|H1|VCCAUX|
|VCCAUX|VCCAUX|K13|VCCAUX|
|VCCAUX|VCCAUX|L8|VCCAUX|
|VCCAUX|VCCAUX|N20|VCCAUX|
|VCCAUX|VCCAUX|T5|VCCAUX|
|VCCAUX|VCCAUX|Y8|VCCAUX|
|VCCINT|VCCINT|J10|VCCINT|
|VCCINT|VCCINT|J12|VCCINT|
|VCCINT|VCCINT|K9|VCCINT|
|VCCINT|VCCINT|K11|VCCINT|
|VCCINT|VCCINT|L10|VCCINT|
|VCCINT|VCCINT|L12|VCCINT|
|VCCINT|VCCINT|M9|VCCINT|
|VCCINT|VCCINT|M11|VCCINT|
|VCCINT|VCCINT|N10|VCCINT|



## **User I/Os by Bank** 

Table 77 indicates how the 311 available user-I/O pins are distributed between the four I/O banks on the FGG400 package. The AWAKE pin is counted as a dual-purpose I/O. 

_Table  77:_ **User I/Os Per Bank for the XC3S400AN in the FGG400 Package** 

|**Package**<br>**Edge**|**I/O Bank**|**Maximum I/Os**|**All Possible I/O Pins by Type**|**All Possible I/O Pins by Type**|**All Possible I/O Pins by Type**|**All Possible I/O Pins by Type**|**All Possible I/O Pins by Type**|
|---|---|---|---|---|---|---|---|
||||**I/O**|**INPUT**|**DUAL**|**VREF**|**CLK**|
|Top|0|77|50|12|1|6|8|
|Right|1|79|21|12|30|8|8|
|Bottom|2|76|35|6|21|6|8|
|Left|3|79|49|16|0|6|8|
|**Total**||**311**|**155**|**46**|**52**|**26**|**32**|



## **Footprint Migration Differences** 

The XC3S400AN is the only Spartan-3AN FPGA offered in the FGG400 package. 

The XC3S400AN FPGA is pin compatible with the Spartan-3A XC3S400A FPGA in the FG(G)400 package, although the Spartan-3A FPGA requires an external configuration source. 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

97 

**Spartan-3AN FPGA Family: Pinout Descriptions** 

## **FGG400 Footprint** 

## **Left Half of FGG400 Package (Top View)** 

**I/O:** Unrestricted, 155 general-purpose user I/O **INPUT:** Unrestricted, 46 general-purpose input pin 

**DUAL:** Configuration pins, 51 then possible user I/O **VREF:** User I/O or input 26 voltage reference for bank 

**CLK:** User I/O, input, or 32 clock buffer input 

**CONFIG:** Dedicated 2 configuration pins 

**JTAG:** Dedicated JTAG 4 port pins **SUSPEND:** Dedicated SUSPEND and 2 dual-purpose AWAKE Power Management pins **GND:** Ground 43 

**VCCO:** Output voltage 22 supply for bank **VCCINT:** Internal core 9 supply voltage (+1.2V) **VCCAUX:** Auxiliary supply 8 voltage 

**==> picture [101 x 37] intentionally omitted <==**

**==> picture [323 x 662] intentionally omitted <==**

**----- Start of picture text -----**<br>
Bank 0<br>1 2 3 4 5 6 7 8 9 10<br>I/O I/O I/O I/O<br>I/O I/O I/O I/O I/O<br>A GND L32P_0 L18N_0 L18P_0 L16P_0<br>L30P_0 L29P_0 L26P_0 L25P_0 L24N_0<br>VREF_0 GCLK11 GCLK10 GCLK6<br>I/O<br>I/O I/O I/O I/O I/O I/O<br>B L32N_0 VCCO_0 GND VCCO_0<br>L02P_3 L30N_0 L26N_0 L24P_0 L20P_0 L19P_0<br>PUDC_B<br>I/O<br>I/O I/O I/O I/O I/O I/O I/O I/O<br>C GND L16N_0<br>L03P_3 L02N_3 L29N_0 L28P_0 L25N_0 L21P_0 L20N_0 L19N_0<br>GCLK7<br>I/O<br>I/O I/O I/O I/O I/O I/O<br>D VCCO_0 GND L17P_0<br>L05P_3 L03N_3 L01N_3 L01P_3 L28N_0 L21N_0<br>GCLK8<br>I/O<br>I/O I/O I/O I/O I/O I/O<br>E VCCO_3 TMS GND L17N_0<br>L05N_3 L10P_3 L31P_0 L27P_0 L23P_0 L22P_0<br>GCLK9<br>I/O<br>I/O I/O I/O I/O I/O I/O I/O<br>F TDI L22N_0 VCCO_0<br>L13P_3 L10N_3 L09P_3 L06P_3 L31N_0 L27N_0 L23N_0<br>VREF_0<br>I/O INPUT<br>I/O I/O I/O INPUT<br>G L13N_3 GND L04N_3 INPUT INPUT INPUT<br>L12P_3 L09N_3 L06N_3 L04P_3<br>VREF_3 VREF_3<br>I/O I/O I/O I/O<br>H VCCAUX VCCO_3 INPUT GND INPUT INPUT<br>L12N_3 L14N_3 L08N_3 L08P_3<br>I/O INPUT<br>I/O I/O I/O I/O I/O INPUT<br>J L17P_3 L11N_3 GND VCCINT<br>L16N_3 L16P_3 L14P_3 L07N_3 L07P_3 L11P_3<br>LHCLK0 VREF_3<br>I/O I/O I/O<br>INPUT INPUT INPUT INPUT<br>K GND L17N_3 L18P_3 L20P_3 VCCINT GND<br>L19N_3 L19P_3 L15N_3 L15P_3<br>LHCLK1 LHCLK2 LHCLK4<br>I/O I/O I/O<br>L L21P_3TRDY2 VCCO_3 L18N_3IRDY2 GND L20N_3 INPUT L23N_3 INPUT L23P_3 VCCAUX GND VCCINT<br>LHCLK6 LHCLK3 LHCLK5<br>I/O I/O<br>I/O I/O I/O INPUT INPUT INPUT<br>M L21N_3 L22P_3 VCCINT GND<br>L22N_3 L24P_3 L24N_3 L31P_3 L27N_3 L27P_3<br>LHCLK7 VREF_3<br>I/O I/O I/O I/O INPUT INPUT INPUT<br>N L25P_3 L25N_3 L26P_3 L26N_3 VCCO_3 L35N_3 L31N_3 GND VREF_2 [VCCINT]<br>INPUT<br>I/O I/O I/O INPUT INPUT INPUT INPUT<br>P GND L39N_3 INPUT<br>L28P_3 L29P_3 L29N_3 L35P_3 L39P_3 VREF_2 VREF_2<br>VREF_3<br>I/O I/O I/O I/O I/O I/O<br>R GND INPUT GND INPUT<br>L28N_3 L30P_3 L30N_3 L33N_3 L36P_3 L04N_2<br>I/O I/O I/O<br>I/O I/O I/O I/O I/O I/O<br>T L32P_3 VCCAUX L07P_2 L14N_2<br>L32N_3 L33P_3 L36N_3 L04P_2 L06P_2 L11P_2<br>VREF_3 RDWR_B D4<br>I/O I/O I/O<br>I/O I/O I/O I/O I/O<br>U VCCO_3 L01P_2 L07N_2 VCCO_2 L14P_2<br>L34P_3 L34N_3 L05N_2 L06N_2 L11N_2<br>M1 VS2 D5<br>I/O I/O I/O I/O<br>I/O I/O I/O I/O I/O<br>V GND L01N_2 L09P_2 L12P_2 L16P_2<br>L37P_3 L37N_3 L05P_2 L13P_2 L13N_2<br>M0 VS1 D7 GCLK14<br>I/O I/O I/O I/O I/O<br>I/O I/O I/O<br>W L02P_2 VCCO_2 L09N_2 GND L12N_2 L15P_2 L16N_2<br>L38P_3 L38N_3 L03N_2<br>M2 VS0 D6 GCLK12 GCLK15<br>I/O I/O<br>I/O I/O I/O I/O I/O<br>Y GND L02N_2 VCCAUX L15N_2 GND<br>L03P_2 L08P_2 L08N_2 L10P_2 L10N_2<br>CSO_B GCLK13<br>Bank 2<br>DS529-4_03_011608<br>PROG_B<br>Bank 3<br>**----- End of picture text -----**<br>


_Figure 22:_ **FGG400 Package Footprint (Top View)** 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

98 

**Spartan-3AN FPGA Family: Pinout Descriptions** 

|**11**|**12**<br>**13**|**12**<br>**13**|**14**<br>**15**<br>**Bank 0**|**14**<br>**15**<br>**Bank 0**|**16**|**17**|**18**|**19**|**20**<br>**GND**<br>**A**<br>**I/O**<br>L38P_1<br>A24<br>**B**<br>**I/O**<br>L37P_1<br>A22<br>**C**<br>**I/O**<br>L34P_1<br>**D**<br>**I/O**<br>L32P_1<br>**E**<br>**I/O**<br>L29P_1<br>A16<br>**F**<br>**I/O**<br>L26N_1<br>A15<br>**G**<br>**I/O**<br>L26P_1<br>A14<br>**H**<br>**I/O**<br>L21N_1<br>RHCLK7<br>**J**<br>**I/O**<br>L21P_1<br>IRDY1<br>RHCLK6<br>**K**<br>**GND**<br>**L**<br>**I/O**<br>L17N_1<br>RHCLK1<br>**M**<br>VCCAUX **N**<br>**I/O**<br>L10N_1<br>VREF_1<br>**P**<br>**I/O**<br>L09N_1<br>**R**<br>**I/O**<br>L05N_1<br>**T**<br>**I/O**<br>L06N_1<br>**U**<br>**I/O**<br>L01N_1<br>LDC2<br>**V**<br>**I/O**<br>L01P_1<br>HDC<br>**W**<br>**GND**<br>**Y**<br>**Bank 1**|
|---|---|---|---|---|---|---|---|---|---|
|**GND**|**I/O**<br>L13N_0|VCCAUX|**I/O**<br>L07N_0|**I/O**<br>L08N_0|**I/O**<br>L05N_0|**I/O**<br>L04N_0|**I/O**<br>L01N_0|**TCK**|**GND**|
|**I/O**<br>L14P_0|**I/O**<br>L13P_0|**I/O**<br>L11P_0|**GND**|**I/O**<br>L08P_0|VCCO_0|**I/O**<br>L04P_0<br>VREF_0|**I/O**<br>L01P_0|**I/O**<br>L38N_1<br>A25|**I/O**<br>L38P_1<br>A24|
|**I/O**<br>L14N_0|**I/O**<br>L11N_0|**I/O**<br>L10N_0<br>VREF_0|**I/O**<br>L07P_0|**I/O**<br>L06N_0|**I/O**<br>L05P_0|**I/O**<br>L02N_0|**GND**|**I/O**<br>L37N_1<br>A23|**I/O**<br>L37P_1<br>A22|
|**I/O**<br>L15P_0<br>GCLK4|**I/O**<br>L12P_0|VCCO_0|**I/O**<br>L10P_0|**I/O**<br>L06P_0|**I/O**<br>L03P_0|**I/O**<br>L02P_0<br>VREF_0|**I/O**<br>L34N_1|VCCO_1|**I/O**<br>L34P_1|
|**I/O**<br>L15N_0<br>GCLK5|**GND**|**I/O**<br>L09P_0|**INPUT**|**I/O**<br>L03N_0|VCCAUX|**TDO**|**I/O**<br>L33P_1|**I/O**<br>L32N_1|**I/O**<br>L32P_1|
|**INPUT**|**I/O**<br>L12N_0|**I/O**<br>L09N_0|**INPUT**|**GND**|**I/O**<br>L36N_1<br>A21|**I/O**<br>L33N_1|**I/O**<br>L30N_1<br>A19|**I/O**<br>L29N_1<br>A17|**I/O**<br>L29P_1<br>A16|
|**INPUT**<br>VREF_0|**INPUT**|**INPUT**|**INPUT**<br>L39N_1|**INPUT**<br>L39P_1<br>VREF_1|**I/O**<br>L36P_1<br>A20|**I/O**<br>L30P_1<br>A18|**I/O**<br>L28P_1|**GND**|**I/O**<br>L26N_1<br>A15|
|**INPUT**|**INPUT**|**GND**|**INPUT**<br>L35N_1|**INPUT**<br>L35P_1|VCCO_1|**I/O**<br>L28N_1|**I/O**<br>L25N_1<br>A13|**I/O**<br>L25P_1<br>A12|**I/O**<br>L26P_1<br>A14|
|**GND**|**VCCINT**|**INPUT**<br>L31N_1|**INPUT**<br>L31P_1<br>VREF_1|**INPUT**<br>L27N_1|**INPUT**<br>L27P_1|**I/O**<br>L24P_1|**I/O**<br>L22N_1<br>A11|**I/O**<br>L22P_1<br>A10|**I/O**<br>L21N_1<br>RHCLK7|
|**VCCINT**|**GND**|VCCAUX|**INPUT**<br>L23N_1|**INPUT**<br>L23P_1<br>VREF_1|**I/O**<br>L24N_1|**GND**|**I/O**<br>L20P_1<br>RHCLK4|VCCO_1|**I/O**<br>L21P_1<br>IRDY1<br>RHCLK6|
|**GND**|**VCCINT**|**INPUT**<br>L19N_1|**INPUT**<br>L19P_1|**I/O**<br>L16P_1<br>A8|**I/O**<br>L16N_1<br>A9|**I/O**<br>L20N_1<br>RHCLK5|**I/O**<br>L18N_1<br>TRDY1<br>RHCLK3|**I/O**<br>L18P_1<br>RHCLK2|**GND**|
|**VCCINT**|**GND**|**INPUT**<br>L15N_1|**INPUT**<br>L15P_1<br>VREF_1|**INPUT**<br>L11N_1<br>VREF_1|**INPUT**<br>L11P_1|**I/O**<br>L14P_1<br>A6|**I/O**<br>L14N_1<br>A7|**I/O**<br>L17P_1<br>RHCLK0|**I/O**<br>L17N_1<br>RHCLK1|
|**GND**|**INPUT**<br>VREF_2|**GND**|**INPUT**<br>VREF_1|**I/O**<br>L12P_1<br>A2|VCCO_1|**I/O**<br>L12N_1<br>A3|**I/O**<br>L13P_1<br>A4|**I/O**<br>L13N_1<br>A5|VCCAUX|
|**INPUT**<br>VREF_2|**INPUT**|**INPUT**|**INPUT**<br>L04P_1|**INPUT**<br>L04N_1<br>VREF_1|**I/O**<br>L07P_1|**I/O**<br>L07N_1|**I/O**<br>L10P_1|**GND**|**I/O**<br>L10N_1<br>VREF_1|
|VCCO_2|**I/O**<br>L19N_2|**I/O**<br>L23N_2|**INPUT**<br>VREF_2|SUSPEND|**I/O**<br>L03N_1<br>A1|**I/O**<br>L08N_1|**I/O**<br>L08P_1|**I/O**<br>L09P_1|**I/O**<br>L09N_1|
|**INPUT**|**I/O**<br>L19P_2|**I/O**<br>L23P_2|**I/O**<br>L25N_2|**I/O**<br>L27N_2|**GND**|**I/O**<br>L03P_1<br>A0|**I/O**<br>L05P_1|VCCO_1|**I/O**<br>L05N_1|
|**I/O**<br>L18P_2<br>GCLK2|**GND**|**I/O**<br>L22P_2<br>AWAKE|VCCO_2|**I/O**<br>L27P_2|**I/O**<br>L29N_2|**I/O**<br>L31N_2|**I/O**<br>L02N_1<br>LDC0|**I/O**<br>L06P_1|**I/O**<br>L06N_1|
|**I/O**<br>L17N_2<br>GCLK1|**I/O**<br>L18N_2<br>GCLK3|**I/O**<br>L22N_2<br>DOUT|**I/O**<br>L25P_2|**I/O**<br>L26N_2<br>D1|**I/O**<br>L29P_2|**I/O**<br>L31P_2|**GND**|**I/O**<br>L02P_1<br>LDC1|**I/O**<br>L01N_1<br>LDC2|
|VCCO_2|**I/O**<br>L20N_2<br>MOSI<br>CSI_B|**I/O**<br>L21N_2|**I/O**<br>L24N_2<br>D3|**GND**|**I/O**<br>L28N_2|VCCO_2|**I/O**<br>L32P_2<br>D0<br>DIN/MISO|**DONE**|**I/O**<br>L01P_1<br>HDC|
|**I/O**<br>L17P_2<br>GCLK0|**I/O**<br>L20P_2|**I/O**<br>L21P_2|**I/O**<br>L24P_2<br>INIT_B|**I/O**<br>L26P_2<br>D2|**I/O**<br>L28P_2|**I/O**<br>L30P_2|**I/O**<br>L30N_2|**I/O**<br>L32N_2<br>CCLK|**GND**|
||||**Bank 2**|||||||



## **Right Half of FGG400 Package (Top View)** 

_Figure 22:_ **FGG400 Package Footprint (Top View)** 

DS557_4_22_030911 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

99 

**Spartan-3AN FPGA Family: Pinout Descriptions** 

## **FGG484: 484-Ball Fine-Pitch Ball Grid Array** 

Xilinx has issued a discontinuation notice for the XC3S1400AN in the FG(G)484 package. See XCN13016: _Product Discontinuation Notice For Selected Spartan-3AN FPGA Products_ . 

The 484-ball fine-pitch ball grid array, FGG484, supports the XC3S700AN and the discontinued XC3S1400AN FPGAs. There are three pinout differences, as described in Table 81. 

Table 78 lists all the FGG484 package pins. They are sorted by bank number and then by pin name. Pins that form a differential I/O pair appear together in the table. The table also shows the pin number for each pin and the pin type (as defined in Table 62). 

The shaded rows indicate pinout differences between the XC3S700AN and the XC3S1400AN FPGAs. The XC3S700AN has three unconnected balls, indicated as N.C. and with a black diamond (◆) in Table 78 and Figure 23. 

An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at: www.xilinx.com/support/documentation/data_sheets/s3a_pin.zip. 

## **Pinout Table** 

_Table  78:_ **Spartan-3AN FGG484 Pinout** 

|**Bank**|**Pin Name**|**FGG484**<br>**Ball**|**Type**|
|---|---|---|---|
|0|IO_L01N_0|D18|I/O|
|0|IO_L01P_0|E17|I/O|
|0|IO_L02N_0|C19|I/O|
|0|IO_L02P_0/VREF_0|D19|VREF|
|0|IO_L03N_0|A20|I/O|
|0|IO_L03P_0|B20|I/O|
|0|IO_L04N_0|F15|I/O|
|0|IO_L04P_0|E15|I/O|
|0|IO_L05N_0|A18|I/O|
|0|IO_L05P_0|C18|I/O|
|0|IO_L06N_0|A19|I/O|
|0|IO_L06P_0/VREF_0|B19|VREF|
|0|IO_L07N_0|C17|I/O|
|0|IO_L07P_0|D17|I/O|
|0|IO_L08N_0|C16|I/O|
|0|IO_L08P_0|D16|I/O|
|0|IO_L09N_0|E14|I/O|
|0|IO_L09P_0|C14|I/O|
|0|IO_L10N_0|A17|I/O|
|0|IO_L10P_0|B17|I/O|
|0|IO_L11N_0|C15|I/O|
|0|IO_L11P_0|D15|I/O|
|0|IO_L12N_0/VREF_0|A15|VREF|
|0|IO_L12P_0|A16|I/O|
|0|IO_L13N_0|A14|I/O|
|0|IO_L13P_0|B15|I/O|



_Table  78:_ **Spartan-3AN FGG484 Pinout** _**(Cont’d)**_ 

|**Bank**|**Pin Name**|**FGG484**<br>**Ball**|**Type**|
|---|---|---|---|
|0|IO_L14N_0|E13|I/O|
|0|IO_L14P_0|F13|I/O|
|0|IO_L15N_0|C13|I/O|
|0|IO_L15P_0|D13|I/O|
|0|IO_L16N_0|A13|I/O|
|0|IO_L16P_0|B13|I/O|
|0|IO_L17N_0/GCLK5|E12|GCLK|
|0|IO_L17P_0/GCLK4|C12|GCLK|
|0|IO_L18N_0/GCLK7|A11|GCLK|
|0|IO_L18P_0/GCLK6|A12|GCLK|
|0|IO_L19N_0/GCLK9|C11|GCLK|
|0|IO_L19P_0/GCLK8|B11|GCLK|
|0|IO_L20N_0/GCLK11|E11|GCLK|
|0|IO_L20P_0/GCLK10|D11|GCLK|
|0|IO_L21N_0|C10|I/O|
|0|IO_L21P_0|A10|I/O|
|0|IO_L22N_0|A8|I/O|
|0|IO_L22P_0|A9|I/O|
|0|IO_L23N_0|E10|I/O|
|0|IO_L23P_0|D10|I/O|
|0|IO_L24N_0/VREF_0|C9|VREF|
|0|IO_L24P_0|B9|I/O|
|0|IO_L25N_0|C8|I/O|
|0|IO_L25P_0|B8|I/O|
|0|IO_L26N_0|A6|I/O|
|0|IO_L26P_0|A7|I/O|
|0|IO_L27N_0|C7|I/O|



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

100 

**Spartan-3AN FPGA Family: Pinout Descriptions** 

_Table  78:_ **Spartan-3AN FGG484 Pinout** _**(Cont’d)**_ 

|**Bank**|**Pin Name**|**FGG484**<br>**Ball**|**Type**|
|---|---|---|---|
|0|IO_L27P_0|D7|I/O|
|0|IO_L28N_0|A5|I/O|
|0|IO_L28P_0|B6|I/O|
|0|IO_L29N_0|D6|I/O|
|0|IO_L29P_0|C6|I/O|
|0|IO_L30N_0|D8|I/O|
|0|IO_L30P_0|E9|I/O|
|0|IO_L31N_0|B4|I/O|
|0|IO_L31P_0|A4|I/O|
|0|IO_L32N_0|D5|I/O|
|0|IO_L32P_0|C5|I/O|
|0|IO_L33N_0|B3|I/O|
|0|IO_L33P_0|A3|I/O|
|0|IO_L34N_0|F8|I/O|
|0|IO_L34P_0|E7|I/O|
|0|IO_L35N_0|E6|I/O|
|0|IO_L35P_0|F7|I/O|
|0|IO_L36N_0/PUDC_B|A2|DUAL|
|0|IO_L36P_0/VREF_0|B2|VREF|
|0|IP_0|E16|INPUT|
|0|IP_0|E8|INPUT|
|0|IP_0|F10|INPUT|
|0|IP_0|F12|INPUT|
|0|IP_0|F16|INPUT|
|0|IP_0|G10|INPUT|
|0|IP_0|G11|INPUT|
|0|IP_0|G12|INPUT|
|0|IP_0|G13|INPUT|
|0|IP_0|G14|INPUT|
|0|IP_0|G15|INPUT|
|0|IP_0|G16|INPUT|
|0|IP_0|G7|INPUT|
|0|IP_0|G9|INPUT|
|0|IP_0|H10|INPUT|
|0|IP_0|H13|INPUT|
|0|IP_0|H14|INPUT|
|0|IP_0/VREF_0|G8|VREF|
|0|IP_0/VREF_0|H12|VREF|
|0|IP_0/VREF_0|H9|VREF|
|0|VCCO_0|B10|VCCO|



_Table  78:_ **Spartan-3AN FGG484 Pinout** _**(Cont’d)**_ 

|**Bank**|**Pin Name**|**FGG484**<br>**Ball**|**Type**|
|---|---|---|---|
|0|VCCO_0|B14|VCCO|
|0|VCCO_0|B18|VCCO|
|0|VCCO_0|B5|VCCO|
|0|VCCO_0|F14|VCCO|
|0|VCCO_0|F9|VCCO|
|1|IO_L01N_1/LDC2|Y21|DUAL|
|1|IO_L01P_1/HDC|AA22|DUAL|
|1|IO_L02N_1/LDC0|W20|DUAL|
|1|IO_L02P_1/LDC1|W19|DUAL|
|1|IO_L03N_1/A1|T18|DUAL|
|1|IO_L03P_1/A0|T17|DUAL|
|1|IO_L05N_1|W21|I/O|
|1|IO_L05P_1|Y22|I/O|
|1|IO_L06N_1|V20|I/O|
|1|IO_L06P_1|V19|I/O|
|1|IO_L07N_1|V22|I/O|
|1|IO_L07P_1|W22|I/O|
|1|IO_L09N_1|U21|I/O|
|1|IO_L09P_1|U22|I/O|
|1|IO_L10N_1|U19|I/O|
|1|IO_L10P_1|U20|I/O|
|1|IO_L11N_1|T22|I/O|
|1|IO_L11P_1|T20|I/O|
|1|IO_L13N_1|T19|I/O|
|1|IO_L13P_1|R20|I/O|
|1|IO_L14N_1|R22|I/O|
|1|IO_L14P_1|R21|I/O|
|1|IO_L15N_1/VREF_1|P22|VREF|
|1|IO_L15P_1|P20|I/O|
|1|IO_L17N_1/A3|P18|DUAL|
|1|IO_L17P_1/A2|R19|DUAL|
|1|IO_L18N_1/A5|N21|DUAL|
|1|IO_L18P_1/A4|N22|DUAL|
|1|IO_L19N_1/A7|N19|DUAL|
|1|IO_L19P_1/A6|N20|DUAL|
|1|IO_L20N_1/A9|N17|DUAL|
|1|IO_L20P_1/A8|N18|DUAL|
|1|IO_L21N_1/RHCLK1|L22|RHCLK|
|1|IO_L21P_1/RHCLK0|M22|RHCLK|
|1|IO_L22N_1/TRDY1/RHCLK3|L20|RHCLK|



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

101 

**Spartan-3AN FPGA Family: Pinout Descriptions** 

_Table  78:_ **Spartan-3AN FGG484 Pinout** _**(Cont’d)**_ 

_Table  78:_ **Spartan-3AN FGG484 Pinout** _**(Cont’d)**_ 

|**Bank**|**Pin Name**|**FGG484**<br>**Ball**|**Type**||**Bank**|**Pin Name**|**FGG484**<br>**Ball**|**Type**|
|---|---|---|---|---|---|---|---|---|
|1|IO_L22P_1/RHCLK2|L21|RHCLK||1|IP_L08P_1|P15|INPUT|
|1|IO_L24N_1/RHCLK5|M20|RHCLK||1|IP_L12N_1/VREF_1|R18|VREF|
|1|IO_L24P_1/RHCLK4|M18|RHCLK||1|IP_L12P_1|R17|INPUT|
|1|IO_L25N_1/RHCLK7|K19|RHCLK||1|IP_L16N_1/VREF_1|N16|VREF|
|1|IO_L25P_1/IRDY1/RHCLK6|K20|RHCLK||1|IP_L16P_1|N15|INPUT|
|1|IO_L26N_1/A11|J22|DUAL||1|IP_L23N_1|M16|INPUT|
|1|IO_L26P_1/A10|K22|DUAL||1|IP_L23P_1|M17|INPUT|
|1|IO_L28N_1|L19|I/O||1|IP_L27N_1|L16|INPUT|
|1|IO_L28P_1|L18|I/O||1|IP_L27P_1/VREF_1|M15|VREF|
|1|IO_L29N_1/A13|J20|DUAL||1|IP_L31N_1|K16|INPUT|
|1|IO_L29P_1/A12|J21|DUAL||1|IP_L31P_1|L15|INPUT|
|1|IO_L30N_1/A15|G22|DUAL||1|IP_L35N_1|K15|INPUT|
|1|IO_L30P_1/A14|H22|DUAL||1|IP_L35P_1/VREF_1|K14|VREF|
|1|IO_L32N_1|K18|I/O||1|IP_L39N_1|H18|INPUT|
|1|IO_L32P_1|K17|I/O||1|IP_L39P_1|H17|INPUT|
|1|IO_L33N_1/A17|H20|DUAL||1|IP_L43N_1/VREF_1|J15|VREF|
|1|IO_L33P_1/A16|H21|DUAL||1|IP_L43P_1|J16|INPUT|
|1|IO_L34N_1/A19|F21|DUAL||1|IP_L47N_1|H15|INPUT|
|1|IO_L34P_1/A18|F22|DUAL||1|IP_L47P_1/VREF_1|H16|VREF|
|1|IO_L36N_1|G20|I/O||1|VCCO_1|E21|VCCO|
|1|IO_L36P_1|G19|I/O||1|VCCO_1|J17|VCCO|
|1|IO_L37N_1|H19|I/O||1|VCCO_1|K21|VCCO|
|1|IO_L37P_1|J18|I/O||1|VCCO_1|P17|VCCO|
|1|IO_L38N_1|F20|I/O||1|VCCO_1|P21|VCCO|
|1|IO_L38P_1|E20|I/O||1|VCCO_1|V21|VCCO|
|1|IO_L40N_1|F18|I/O||2|IO_L01N_2/M0|W5|DUAL|
|1|IO_L40P_1|F19|I/O||2|IO_L01P_2/M1|V6|DUAL|
|1|IO_L41N_1|D22|I/O||2|IO_L02N_2/CSO_B|Y4|DUAL|
|1|IO_L41P_1|E22|I/O||2|IO_L02P_2/M2|W4|DUAL|
|1|IO_L42N_1|D20|I/O||2|IO_L03N_2|AA3|I/O|
|1|IO_L42P_1|D21|I/O||2|IO_L03P_2|AB2|I/O|
|1|IO_L44N_1/A21|C21|DUAL||2|IO_L04N_2|AA4|I/O|
|1|IO_L44P_1/A20|C22|DUAL||2|IO_L04P_2|AB3|I/O|
|1|IO_L45N_1/A23|B21|DUAL||2|IO_L05N_2|Y5|I/O|
|1|IO_L45P_1/A22|B22|DUAL||2|IO_L05P_2|W6|I/O|
|1|IO_L46N_1/A25|G17|DUAL||2|IO_L06N_2|AB5|I/O|
|1|IO_L46P_1/A24|G18|DUAL||2|IO_L06P_2|AB4|I/O|
|1|IP_L04N_1/VREF_1|R16|VREF||2|IO_L07N_2|Y6|I/O|
|1|IP_L04P_1|R15|INPUT||2|IO_L07P_2|W7|I/O|
|1|IP_L08N_1|P16|INPUT||2|IO_L08N_2|AB6|I/O|



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

102 

**Spartan-3AN FPGA Family: Pinout Descriptions** 

_Table  78:_ **Spartan-3AN FGG484 Pinout** _**(Cont’d)**_ 

|**Bank**|**Pin Name**|**FGG484**<br>**Ball**|**Type**|
|---|---|---|---|
|2|IO_L08P_2|AA6|I/O|
|2|IO_L09N_2/VS2|W9|DUAL|
|2|IO_L09P_2/RDWR_B|V9|DUAL|
|2|IO_L10N_2|AB7|I/O|
|2|IO_L10P_2|Y7|I/O|
|2|IO_L11N_2/VS0|Y8|DUAL|
|2|IO_L11P_2/VS1|W8|DUAL|
|2|IO_L12N_2|AB8|I/O|
|2|IO_L12P_2|AA8|I/O|
|2|IO_L13N_2|Y10|I/O|
|2|IO_L13P_2|V10|I/O|
|2|IO_L14N_2/D6|AB9|DUAL|
|2|IO_L14P_2/D7|Y9|DUAL|
|2|IO_L15N_2|AB10|I/O|
|2|IO_L15P_2|AA10|I/O|
|2|IO_L16N_2/D4|AB11|DUAL|
|2|IO_L16P_2/D5|Y11|DUAL|
|2|IO_L17N_2/GCLK13|V11|GCLK|
|2|IO_L17P_2/GCLK12|U11|GCLK|
|2|IO_L18N_2/GCLK15|Y12|GCLK|
|2|IO_L18P_2/GCLK14|W12|GCLK|
|2|IO_L19N_2/GCLK1|AB12|GCLK|
|2|IO_L19P_2/GCLK0|AA12|GCLK|
|2|IO_L20N_2/GCLK3|U12|GCLK|
|2|IO_L20P_2/GCLK2|V12|GCLK|
|2|IO_L21N_2|Y13|I/O|
|2|IO_L21P_2|AB13|I/O|
|2|IO_L22N_2/MOSI/CSI_B|AB14|DUAL|
|2|IO_L22P_2|AA14|I/O|
|2|IO_L23N_2|Y14|I/O|
|2|IO_L23P_2|W13|I/O|
|2|IO_L24N_2/DOUT|AA15|DUAL|
|2|IO_L24P_2/AWAKE|AB15|PWR MGMT|
|2|IO_L25N_2|Y15|I/O|
|2|IO_L25P_2|W15|I/O|
|2|IO_L26N_2/D3|U13|DUAL|
|2|IO_L26P_2/INIT_B|V13|DUAL|
|2|IO_L27N_2|Y16|I/O|
|2|IO_L27P_2|AB16|I/O|
|2|IO_L28N_2/D1|Y17|DUAL|



_Table  78:_ **Spartan-3AN FGG484 Pinout** _**(Cont’d)**_ 

|**Bank**|**Pin Name**|**FGG484**<br>**Ball**|**Type**|
|---|---|---|---|
|2|IO_L28P_2/D2|AA17|DUAL|
|2|IO_L29N_2|AB18|I/O|
|2|IO_L29P_2|AB17|I/O|
|2|IO_L30N_2|V15|I/O|
|2|IO_L30P_2|V14|I/O|
|2|IO_L31N_2|V16|I/O|
|2|IO_L31P_2|W16|I/O|
|2|IO_L32N_2|AA19|I/O|
|2|IO_L32P_2|AB19|I/O|
|2|IO_L33N_2|V17|I/O|
|2|IO_L33P_2|W18|I/O|
|2|IO_L34N_2|W17|I/O|
|2|IO_L34P_2|Y18|I/O|
|2|IO_L35N_2|AA21|I/O|
|2|IO_L35P_2|AB21|I/O|
|2|IO_L36N_2/CCLK|AA20|DUAL|
|2|IO_L36P_2/D0/DIN/MISO|AB20|DUAL|
|2|IP_2|P12|INPUT|
|2|IP_2|R10|INPUT|
|2|IP_2|R11|INPUT|
|2|IP_2|R9|INPUT|
|2|IP_2|T13|INPUT|
|2|IP_2|T14|INPUT|
|2|IP_2|T9|INPUT|
|2|IP_2|U10|INPUT|
|2|IP_2|U15|INPUT|
|2|XC3S1400AN: IP_2<br>XC3S700AN: N.C.◆|U16|INPUT|
|2|XC3S1400AN: IP_2<br>XC3S700AN: N.C.◆|U7|INPUT|
|2|IP_2|U8|INPUT|
|2|IP_2|V7|INPUT|
|2|IP_2/VREF_2|R12|VREF|
|2|IP_2/VREF_2|R13|VREF|
|2|IP_2/VREF_2|R14|VREF|
|2|IP_2/VREF_2|T10|VREF|
|2|IP_2/VREF_2|T11|VREF|
|2|IP_2/VREF_2|T15|VREF|
|2|IP_2/VREF_2|T16|VREF|
|2|IP_2/VREF_2|T7|VREF|



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

103 

**Spartan-3AN FPGA Family: Pinout Descriptions** 

_Table  78:_ **Spartan-3AN FGG484 Pinout** _**(Cont’d)**_ 

|**Bank**|**Pin Name**|**FGG484**<br>**Ball**|**Type**|
|---|---|---|---|
|2|XC3S1400AN: IP_2/VREF_2<br>XC3S700AN: N.C.◆|T8|VREF|
|2|IP_2/VREF_2|V8|VREF|
|2|VCCO_2|AA13|VCCO|
|2|VCCO_2|AA18|VCCO|
|2|VCCO_2|AA5|VCCO|
|2|VCCO_2|AA9|VCCO|
|2|VCCO_2|U14|VCCO|
|2|VCCO_2|U9|VCCO|
|3|IO_L01N_3|D2|I/O|
|3|IO_L01P_3|C1|I/O|
|3|IO_L02N_3|C2|I/O|
|3|IO_L02P_3|B1|I/O|
|3|IO_L03N_3|E4|I/O|
|3|IO_L03P_3|D3|I/O|
|3|IO_L05N_3|G5|I/O|
|3|IO_L05P_3|G6|I/O|
|3|IO_L06N_3|E1|I/O|
|3|IO_L06P_3|D1|I/O|
|3|IO_L07N_3|E3|I/O|
|3|IO_L07P_3|F4|I/O|
|3|IO_L08N_3|G4|I/O|
|3|IO_L08P_3|F3|I/O|
|3|IO_L09N_3|H6|I/O|
|3|IO_L09P_3|H5|I/O|
|3|IO_L10N_3|J5|I/O|
|3|IO_L10P_3|K6|I/O|
|3|IO_L12N_3|F1|I/O|
|3|IO_L12P_3|F2|I/O|
|3|IO_L13N_3|G1|I/O|
|3|IO_L13P_3|G3|I/O|
|3|IO_L14N_3|H3|I/O|
|3|IO_L14P_3|H4|I/O|
|3|IO_L16N_3|H1|I/O|
|3|IO_L16P_3|H2|I/O|
|3|IO_L17N_3/VREF_3|J1|VREF|
|3|IO_L17P_3|J3|I/O|
|3|IO_L18N_3|K4|I/O|
|3|IO_L18P_3|K5|I/O|
|3|IO_L20N_3|K2|I/O|



_Table  78:_ **Spartan-3AN FGG484 Pinout** _**(Cont’d)**_ 

|**Bank**|**Pin Name**|**FGG484**<br>**Ball**|**Type**|
|---|---|---|---|
|3|IO_L20P_3|K3|I/O|
|3|IO_L21N_3/LHCLK1|L3|LHCLK|
|3|IO_L21P_3/LHCLK0|L5|LHCLK|
|3|IO_L22N_3/IRDY2/LHCLK3|L1|LHCLK|
|3|IO_L22P_3/LHCLK2|K1|LHCLK|
|3|IO_L24N_3/LHCLK5|M2|LHCLK|
|3|IO_L24P_3/LHCLK4|M1|LHCLK|
|3|IO_L25N_3/LHCLK7|M4|LHCLK|
|3|IO_L25P_3/TRDY2/LHCLK6|M3|LHCLK|
|3|IO_L26N_3|N3|I/O|
|3|IO_L26P_3/VREF_3|N1|VREF|
|3|IO_L28N_3|P2|I/O|
|3|IO_L28P_3|P1|I/O|
|3|IO_L29N_3|P5|I/O|
|3|IO_L29P_3|P3|I/O|
|3|IO_L30N_3|N4|I/O|
|3|IO_L30P_3|M5|I/O|
|3|IO_L32N_3|R2|I/O|
|3|IO_L32P_3|R1|I/O|
|3|IO_L33N_3|R4|I/O|
|3|IO_L33P_3|R3|I/O|
|3|IO_L34N_3|T4|I/O|
|3|IO_L34P_3|R5|I/O|
|3|IO_L36N_3|T3|I/O|
|3|IO_L36P_3/VREF_3|T1|VREF|
|3|IO_L37N_3|U2|I/O|
|3|IO_L37P_3|U1|I/O|
|3|IO_L38N_3|V3|I/O|
|3|IO_L38P_3|V1|I/O|
|3|IO_L40N_3|U5|I/O|
|3|IO_L40P_3|T5|I/O|
|3|IO_L41N_3|U4|I/O|
|3|IO_L41P_3|U3|I/O|
|3|IO_L42N_3|W2|I/O|
|3|IO_L42P_3|W1|I/O|
|3|IO_L43N_3|W3|I/O|
|3|IO_L43P_3|V4|I/O|
|3|IO_L44N_3|Y2|I/O|
|3|IO_L44P_3|Y1|I/O|
|3|IO_L45N_3|AA2|I/O|



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

104 

**Spartan-3AN FPGA Family: Pinout Descriptions** 

_Table  78:_ **Spartan-3AN FGG484 Pinout** _**(Cont’d)**_ 

_Table  78:_ **Spartan-3AN FGG484 Pinout** _**(Cont’d)**_ 

|**Bank**|**Pin Name**|**FGG484**<br>**Ball**|**Type**||**Bank**|**Pin Name**|**FGG484**<br>**Ball**|**Type**|
|---|---|---|---|---|---|---|---|---|
|3|IO_L45P_3|AA1|I/O||GND|GND|C3|GND|
|3|IP_3/VREF_3|J8|VREF||GND|GND|D14|GND|
|3|IP_3/VREF_3|R6|VREF||GND|GND|D9|GND|
|3|IP_L04N_3/VREF_3|H7|VREF||GND|GND|F11|GND|
|3|IP_L04P_3|H8|INPUT||GND|GND|F17|GND|
|3|IP_L11N_3|K8|INPUT||GND|GND|F6|GND|
|3|IP_L11P_3|J7|INPUT||GND|GND|G2|GND|
|3|IP_L15N_3/VREF_3|L8|VREF||GND|GND|G21|GND|
|3|IP_L15P_3|K7|INPUT||GND|GND|J11|GND|
|3|IP_L19N_3|M8|INPUT||GND|GND|J13|GND|
|3|IP_L19P_3|L7|INPUT||GND|GND|J14|GND|
|3|IP_L23N_3|M6|INPUT||GND|GND|J19|GND|
|3|IP_L23P_3|M7|INPUT||GND|GND|J4|GND|
|3|IP_L27N_3|N9|INPUT||GND|GND|J9|GND|
|3|IP_L27P_3|N8|INPUT||GND|GND|K10|GND|
|3|IP_L31N_3|N5|INPUT||GND|GND|K12|GND|
|3|IP_L31P_3|N6|INPUT||GND|GND|L11|GND|
|3|IP_L35N_3|P8|INPUT||GND|GND|L13|GND|
|3|IP_L35P_3|N7|INPUT||GND|GND|L17|GND|
|3|IP_L39N_3|R8|INPUT||GND|GND|L2|GND|
|3|IP_L39P_3|P7|INPUT||GND|GND|L6|GND|
|3|IP_L46N_3/VREF_3|T6|VREF||GND|GND|L9|GND|
|3|IP_L46P_3|R7|INPUT||GND|GND|M10|GND|
|3|VCCO_3|E2|VCCO||GND|GND|M12|GND|
|3|VCCO_3|J2|VCCO||GND|GND|M14|GND|
|3|VCCO_3|J6|VCCO||GND|GND|M21|GND|
|3|VCCO_3|N2|VCCO||GND|GND|N11|GND|
|3|VCCO_3|P6|VCCO||GND|GND|N13|GND|
|3|VCCO_3|V2|VCCO||GND|GND|P10|GND|
|GND|GND|A1|GND||GND|GND|P14|GND|
|GND|GND|A22|GND||GND|GND|P19|GND|
|GND|GND|AA11|GND||GND|GND|P4|GND|
|GND|GND|AA16|GND||GND|GND|P9|GND|
|GND|GND|AA7|GND||GND|GND|T12|GND|
|GND|GND|AB1|GND||GND|GND|T2|GND|
|GND|GND|AB22|GND||GND|GND|T21|GND|
|GND|GND|B12|GND||GND|GND|U17|GND|
|GND|GND|B16|GND||GND|GND|U6|GND|
|GND|GND|B7|GND||GND|GND|W10|GND|
|GND|GND|C20|GND||GND|GND|W14|GND|



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

105 

**Spartan-3AN FPGA Family: Pinout Descriptions** 

_Table  78:_ **Spartan-3AN FGG484 Pinout** _**(Cont’d)**_ 

|**Bank**|**Pin Name**|**FGG484**<br>**Ball**|**Type**|
|---|---|---|---|
|GND|GND|Y20|GND|
|GND|GND|Y3|GND|
|VCCAUX|SUSPEND|U18|PWR MGMT|
|VCCAUX|DONE|Y19|CONFIG|
|VCCAUX|PROG_B|C4|CONFIG|
|VCCAUX|TCK|A21|JTAG|
|VCCAUX|TDI|F5|JTAG|
|VCCAUX|TDO|E19|JTAG|
|VCCAUX|TMS|D4|JTAG|
|VCCAUX|VCCAUX|D12|VCCAUX|
|VCCAUX|VCCAUX|E18|VCCAUX|
|VCCAUX|VCCAUX|E5|VCCAUX|
|VCCAUX|VCCAUX|H11|VCCAUX|
|VCCAUX|VCCAUX|L4|VCCAUX|
|VCCAUX|VCCAUX|M19|VCCAUX|
|VCCAUX|VCCAUX|P11|VCCAUX|
|VCCAUX|VCCAUX|V18|VCCAUX|
|VCCAUX|VCCAUX|V5|VCCAUX|
|VCCAUX|VCCAUX|W11|VCCAUX|
|VCCINT|VCCINT|J10|VCCINT|
|VCCINT|VCCINT|J12|VCCINT|
|VCCINT|VCCINT|K11|VCCINT|
|VCCINT|VCCINT|K13|VCCINT|
|VCCINT|VCCINT|K9|VCCINT|
|VCCINT|VCCINT|L10|VCCINT|
|VCCINT|VCCINT|L12|VCCINT|
|VCCINT|VCCINT|L14|VCCINT|
|VCCINT|VCCINT|M11|VCCINT|
|VCCINT|VCCINT|M13|VCCINT|
|VCCINT|VCCINT|M9|VCCINT|
|VCCINT|VCCINT|N10|VCCINT|
|VCCINT|VCCINT|N12|VCCINT|
|VCCINT|VCCINT|N14|VCCINT|
|VCCINT|VCCINT|P13|VCCINT|



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

106 

**Spartan-3AN FPGA Family: Pinout Descriptions** 

## **User I/Os by Bank** 

Table 79 and Table 80 indicate how the user-I/O pins are distributed between the four I/O banks on the FGG484 package. The AWAKE pin is counted as a dual-purpose I/O. 

_Table  79:_ **User I/Os Per Bank for the XC3S700AN in the FGG484 Package** 

|**Package**<br>**Edge**|**I/O Bank**|**Maximum I/Os**|**All Possible I/O Pins by Type**|**All Possible I/O Pins by Type**|**All Possible I/O Pins by Type**|**All Possible I/O Pins by Type**|**All Possible I/O Pins by Type**|
|---|---|---|---|---|---|---|---|
||||**I/O**|**INPUT**|**DUAL**|**VREF**|**CLK**|
|Top|0|92|58|17|1|8|8|
|Right|1|94|33|15|30|8|8|
|Bottom|2|92|43|11|21|9|8|
|Left|3|94|61|17|0|8|8|
|**Total**||**372**|**195**|**60**|**52**|**33**|**32**|



_Table  80:_ **User I/Os Per Bank for the Discontinued XC3S1400AN[(1)] in the FGG484 Package** 

|**Package**<br>**Edge**|**I/O Bank**|**Maximum I/Os**|**All Possible I/O Pins by Type**|**All Possible I/O Pins by Type**|**All Possible I/O Pins by Type**|**All Possible I/O Pins by Type**|**All Possible I/O Pins by Type**|
|---|---|---|---|---|---|---|---|
||||**I/O**|**INPUT**|**DUAL**|**VREF**|**CLK**|
|Top|0|92|58|17|1|8|8|
|Right|1|94|33|15|30|8|8|
|Bottom|2|95|43|13|21|10|8|
|Left|3|94|61|17|0|8|8|
|**Total**||**375**|**195**|**62**|**52**|**34**|**32**|



## **Notes:** 

1. Xilinx has issued a discontinuation notice for the XC3S1400AN in the FG(G)484 package. See XCN13016: _Product Discontinuation Notice For Selected Spartan-3AN FPGA Products_ . 

## **Footprint Migration Differences** 

Table 81 summarizes the three footprint and functionality differences between the XC3S700AN and the XC3S1400AN FPGAs that can affect migration between devices available in the FGG484 package. All other pins unconditionally migrate between the Spartan-3AN devices available in the FGG484 package. 

Spartan-3AN FPGAs are pin compatible with the same density Spartan-3A FPGAs in the FG(G)484 package, although the Spartan-3A FPGAs require an external configuration source. 

In Table 81, the arrow (→) indicates that this pin can unconditionally migrate from the device on the left to the device on the right. Migration in the other direction is possible depending on how the pin is configured for the device on the right. 

_Table  81:_ **FGG484 XC3S700AN to XC3S1400AN[(1)] Footprint Migration/Differences** 

|**FGG484 Ball**|**Bank**|**XC3S700AN**|**Migration**|**XC3S1400AN (Discontinued)**|
|---|---|---|---|---|
|T8|2|N.C.|→|INPUT/VREF|
|U7|2|N.C.|→|INPUT|
|U16|2|N.C.|→|INPUT|
|**Number of Differences:**|||3||



## **Notes:** 

1. Xilinx has issued a discontinuation notice for the XC3S1400AN in the FG(G)484 package. See XCN13016: _Product Discontinuation Notice For Selected Spartan-3AN FPGA Products_ . 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

107 

**Spartan-3AN FPGA Family: Pinout Descriptions** 

## **FGG484 Footprint** 

## **Left Half of FGG484 Package (Top View)** 

**I/O:** Unrestricted, 195 general-purpose user I/O **INPUT:** Unrestricted, 60general-purpose input pin 62 **DUAL:** Configuration pins, 51 then possible user I/O **VREF:** User I/O or input 33voltage reference for bank 34 **CLK:** User I/O, input, or 32 clock buffer input **SUSPEND:** Dedicated SUSPEND and 2 dual-purpose AWAKE Power Management pins **CONFIG:** Dedicated 2 configuration pins **JTAG:** Dedicated JTAG 4 port pins **GND:** Ground 53 **VCCO:** Output voltage 24 supply for bank **VCCINT:** Internal core 15 supply voltage (+1.2V) **VCCAUX:** Auxiliary supply 10 voltage (+3.3V) 3 **N.C.:** Not connected ◆ (XC3S700AN only) 

|**A**<br>**B**<br>**C**<br>**D**<br>**E**<br>**F**<br>**G**<br>**H**<br>**J**<br>**K**<br>**L**<br>**M**<br>**N**<br>**P**<br>**R**<br>**T**<br>**U**<br>**V**<br>**W**<br>**Y**<br>**A**<br>**A**<br>**A**<br>**B**<br>**Bank 3**|**1**|**2**|**3**|**4**|**5**|**6**<br>**7**<br>**Bank 0**|**6**<br>**7**<br>**Bank 0**|**8**|**9**|**10**|**11**|
|---|---|---|---|---|---|---|---|---|---|---|---|
||**GND**|**I/O**<br>L36N_0<br>PUDC_B|**I/O**<br>L33P_0|**I/O**<br>L31P_0|**I/O**<br>L28N_0|**I/O**<br>L26N_0|**I/O**<br>L26P_0|**I/O**<br>L22N_0|**I/O**<br>L22P_0|**I/O**<br>L21P_0|**I/O**<br>L18N_0<br>GCLK7|
||**I/O**<br>L02P_3|**I/O**<br>L36P_0<br>VREF_0|**I/O**<br>L33N_0|**I/O**<br>L31N_0|VCCO_0|**I/O**<br>L28P_0|**GND**|**I/O**<br>L25P_0|**I/O**<br>L24P_0|VCCO_0|**I/O**<br>L19P_0<br>GCLK8|
||**I/O**<br>L01P_3|**I/O**<br>L02N_3|**GND**|**PROG_B**|**I/O**<br>L32P_0|**I/O**<br>L29P_0|**I/O**<br>L27N_0|**I/O**<br>L25N_0|**I/O**<br>L24N_0<br>VREF_0|**I/O**<br>L21N_0|**I/O**<br>L19N_0<br>GCLK9|
||**I/O**<br>L06P_3|**I/O**<br>L01N_3|**I/O**<br>L03P_3|**TMS**|**I/O**<br>L32N_0|**I/O**<br>L29N_0|**I/O**<br>L27P_0|**I/O**<br>L30N_0|**GND**|**I/O**<br>L23P_0|**I/O**<br>L20P_0<br>GCLK10|
||**I/O**<br>L06N_3|VCCO_3|**I/O**<br>L07N_3|**I/O**<br>L03N_3|VCCAUX|**I/O**<br>L35N_0|**I/O**<br>L34P_0|**INPUT**|**I/O**<br>L30P_0|**I/O**<br>L23N_0|**I/O**<br>L20N_0<br>GCLK11|
||**I/O**<br>L12N_3|**I/O**<br>L12P_3|**I/O**<br>L08P_3|**I/O**<br>L07P_3|**TDI**|**GND**|**I/O**<br>L35P_0|**I/O**<br>L34N_0|VCCO_0|**INPUT**|**GND**|
||**I/O**<br>L13N_3|**GND**|**I/O**<br>L13P_3|**I/O**<br>L08N_3|**I/O**<br>L05N_3|**I/O**<br>L05P_3|**INPUT**|**INPUT**<br>VREF_0|**INPUT**|**INPUT**|**INPUT**|
||**I/O**<br>L16N_3|**I/O**<br>L16P_3|**I/O**<br>L14N_3|**I/O**<br>L14P_3|**I/O**<br>L09P_3|**I/O**<br>L09N_3|**INPUT**<br>L04N_3<br>VREF_3|**INPUT**<br>L04P_3|**INPUT**<br>VREF_0|**INPUT**|VCCAUX|
||**I/O**<br>L17N_3<br>VREF_3|VCCO_3|**I/O**<br>L17P_3|**GND**|**I/O**<br>L10N_3|VCCO_3|**INPUT**<br>L11P_3|**INPUT**<br>VREF_3|**GND**|**VCCINT**|**GND**|
||**I/O**<br>L22P_3<br>LHCLK2|**I/O**<br>L20N_3|**I/O**<br>L20P_3|**I/O**<br>L18N_3|**I/O**<br>L18P_3|**I/O**<br>L10P_3|**INPUT**<br>L15P_3|**INPUT**<br>L11N_3|**VCCINT**|**GND**|**VCCINT**|
||**I/O**<br>L22N_3<br>IRDY2<br>LHCLK3|**GND**|**I/O**<br>L21N_3<br>LHCLK1|VCCAUX|**I/O**<br>L21P_3<br>LHCLK0|**GND**|**INPUT**<br>L19P_3|**INPUT**<br>L15N_3<br>VREF_3|**GND**|**VCCINT**|**GND**|
||**I/O**<br>L24P_3<br>LHCLK4|**I/O**<br>L24N_3<br>LHCLK5|**I/O**<br>L25P_3<br>TRDY2<br>LHCLK6|**I/O**<br>L25N_3<br>LHCLK7|**I/O**<br>L30P_3|**INPUT**<br>L23N_3|**INPUT**<br>L23P_3|**INPUT**<br>L19N_3|**VCCINT**|**GND**|**VCCINT**|
||**I/O**<br>L26P_3<br>VREF_3|VCCO_3|**I/O**<br>L26N_3|**I/O**<br>L30N_3|**INPUT**<br>L31N_3|**INPUT**<br>L31P_3|**INPUT**<br>L35P_3|**INPUT**<br>L27P_3|**INPUT**<br>L27N_3|**VCCINT**|**GND**|
||**I/O**<br>L28P_3|**I/O**<br>L28N_3|**I/O**<br>L29P_3|**GND**|**I/O**<br>L29N_3|VCCO_3|**INPUT**<br>L39P_3|**INPUT**<br>L35N_3|**GND**|**GND**|VCCAUX|
||**I/O**<br>L32P_3|**I/O**<br>L32N_3|**I/O**<br>L33P_3|**I/O**<br>L33N_3|**I/O**<br>L34P_3|**INPUT**<br>VREF_3|**INPUT**<br>L46P_3|**INPUT**<br>L39N_3|**INPUT**|**INPUT**|**INPUT**|
||**I/O**<br>L36P_3<br>VREF_3|**GND**|**I/O**<br>L36N_3|**I/O**<br>L34N_3|**I/O**<br>L40P_3|**INPUT**<br>L46N_3<br>VREF_3|**INPUT**<br>VREF_2|**INPUT**<br>VREF_2<br>◆|**INPUT**|**INPUT**<br>VREF_2|**INPUT**<br>VREF_2|
||**I/O**<br>L37P_3|**I/O**<br>L37N_3|**I/O**<br>L41P_3|**I/O**<br>L41N_3|**I/O**<br>L40N_3|**GND**|**INPUT**<br>◆|**INPUT**|VCCO_2|**INPUT**|**I/O**<br>L17P_2<br>GCLK12|
||**I/O**<br>L38P_3|VCCO_3|**I/O**<br>L38N_3|**I/O**<br>L43P_3|VCCAUX|**I/O**<br>L01P_2<br>M1|**INPUT**|**INPUT**<br>VREF_2|**I/O**<br>L09P_2<br>RDWR_B|**I/O**<br>L13P_2|**I/O**<br>L17N_2<br>GCLK13|
||**I/O**<br>L42P_3|**I/O**<br>L42N_3|**I/O**<br>L43N_3|**I/O**<br>L02P_2<br>M2|**I/O**<br>L01N_2<br>M0|**I/O**<br>L05P_2|**I/O**<br>L07P_2|**I/O**<br>L11P_2<br>VS1|**I/O**<br>L09N_2<br>VS2|**GND**|VCCAUX|
||**I/O**<br>L44P_3|**I/O**<br>L44N_3|**GND**|**I/O**<br>L02N_2<br>CSO_B|**I/O**<br>L05N_2|**I/O**<br>L07N_2|**I/O**<br>L10P_2|**I/O**<br>L11N_2<br>VS0|**I/O**<br>L14P_2<br>D7|**I/O**<br>L13N_2|**I/O**<br>L16P_2<br>D5|
||**I/O**<br>L45P_3|**I/O**<br>L45N_3|**I/O**<br>L03N_2|**I/O**<br>L04N_2|VCCO_2|**I/O**<br>L08P_2|**GND**|**I/O**<br>L12P_2|VCCO_2|**I/O**<br>L15P_2|**GND**|
||**GND**|**I/O**<br>L03P_2|**I/O**<br>L04P_2|**I/O**<br>L06P_2|**I/O**<br>L06N_2|**I/O**<br>L08N_2|**I/O**<br>L10N_2|**I/O**<br>L12N_2|**I/O**<br>L14N_2<br>D6|**I/O**<br>L15N_2|**I/O**<br>L16N_2<br>D4|
|||||||**Bank 2**||||DS557_4|_23_03091|



_Figure 23:_ **FGG484 Package Footprint (Top View)** 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

108 

**Spartan-3AN FPGA Family: Pinout Descriptions** 

|**12**|**13**<br>**14**|**13**<br>**14**|**15**<br>**16**<br>**17**<br>**Bank 0**|**15**<br>**16**<br>**17**<br>**Bank 0**|**15**<br>**16**<br>**17**<br>**Bank 0**|**18**|**19**|**20**|**21**|**22**<br>**GND**<br>**A**<br>**I/O**<br>L45P_1<br>A22<br>**B**<br>**I/O**<br>L44P_1<br>A20<br>**C**<br>**I/O**<br>L41N_1<br>**D**<br>**I/O**<br>L41P_1<br>**E**<br>**I/O**<br>L34P_1<br>A18<br>**F**<br>**I/O**<br>L30N_1<br>A15<br>**G**<br>**I/O**<br>L30P_1<br>A14<br>**H**<br>**I/O**<br>L26N_1<br>A11<br>**J**<br>**I/O**<br>L26P_1<br>A10<br>**K**<br>**I/O**<br>L21N_1<br>RHCLK1<br>**L**<br>**I/O**<br>L21P_1<br>RHCLK0<br>**M**<br>**I/O**<br>L18P_1<br>A4<br>**N**<br>**I/O**<br>L15N_1<br>VREF_1<br>**P**<br>**I/O**<br>L14N_1<br>**R**<br>**I/O**<br>L11N_1<br>**T**<br>**I/O**<br>L09P_1<br>**U**<br>**I/O**<br>L07N_1<br>**V**<br>**I/O**<br>L07P_1<br>**W**<br>**I/O**<br>L05P_1<br>**Y**<br>**I/O**<br>L01P_1<br>HDC<br>**A**<br>**A**<br>**GND**<br>**A**<br>**B**<br>**Bank 1**|
|---|---|---|---|---|---|---|---|---|---|---|
|**I/O**<br>L18P_0<br>GCLK6|**I/O**<br>L16N_0|**I/O**<br>L13N_0|**I/O**<br>L12N_0<br>VREF_0|**I/O**<br>L12P_0|**I/O**<br>L10N_0|**I/O**<br>L05N_0|**I/O**<br>L06N_0|**I/O**<br>L03N_0|**TCK**|**GND**|
|**GND**|**I/O**<br>L16P_0|VCCO_0|**I/O**<br>L13P_0|GND|**I/O**<br>L10P_0|VCCO_0|**I/O**<br>L06P_0<br>VREF_0|**I/O**<br>L03P_0|**I/O**<br>L45N_1<br>A23|**I/O**<br>L45P_1<br>A22|
|**I/O**<br>L17P_0<br>GCLK4|**I/O**<br>L15N_0|**I/O**<br>L09P_0|**I/O**<br>L11N_0|**I/O**<br>L08N_0|**I/O**<br>L07N_0|**I/O**<br>L05P_0|**I/O**<br>L02N_0|**GND**|**I/O**<br>L44N_1<br>A21|**I/O**<br>L44P_1<br>A20|
|VCCAUX|**I/O**<br>L15P_0|**GND**|**I/O**<br>L11P_0|**I/O**<br>L08P_0|**I/O**<br>L07P_0|**I/O**<br>L01N_0|**I/O**<br>L02P_0<br>VREF_0|**I/O**<br>L42N_1|**I/O**<br>L42P_1|**I/O**<br>L41N_1|
|**I/O**<br>L17N_0<br>GCLK5|**I/O**<br>L14N_0|**I/O**<br>L09N_0|**I/O**<br>L04P_0|**INPUT**|**I/O**<br>L01P_0|VCCAUX|**TDO**|**I/O**<br>L38P_1|VCCO_1|**I/O**<br>L41P_1|
|**INPUT**|**I/O**<br>L14P_0|VCCO_0|**I/O**<br>L04N_0|**INPUT**|**GND**|**I/O**<br>L40N_1|**I/O**<br>L40P_1|**I/O**<br>L38N_1|**I/O**<br>L34N_1<br>A19|**I/O**<br>L34P_1<br>A18|
|**INPUT**|**INPUT**|**INPUT**|**INPUT**|**INPUT**|**I/O**<br>L46N_1<br>A25|**I/O**<br>L46P_1<br>A24|**I/O**<br>L36P_1|**I/O**<br>L36N_1|**GND**|**I/O**<br>L30N_1<br>A15|
|**INPUT**<br>VREF_0|**INPUT**|**INPUT**|**INPUT**<br>L47N_1|**INPUT**<br>L47P_1<br>VREF_1|**INPUT**<br>L39P_1|**INPUT**<br>L39N_1|**I/O**<br>L37N_1|**I/O**<br>L33N_1<br>A17|**I/O**<br>L33P_1<br>A16|**I/O**<br>L30P_1<br>A14|
|**VCCINT**|**GND**|**GND**|**INPUT**<br>L43N_1<br>VREF_1|**INPUT**<br>L43P_1|VCCO_1|**I/O**<br>L37P_1|**GND**|**I/O**<br>L29N_1<br>A13|**I/O**<br>L29P_1<br>A12|**I/O**<br>L26N_1<br>A11|
|**GND**|**VCCINT**|**INPUT**<br>L35P_1<br>VREF_1|**INPUT**<br>L35N_1|**INPUT**<br>L31N_1|**I/O**<br>L32P_1|**I/O**<br>L32N_1|**I/O**<br>L25N_1<br>RHCLK7|**I/O**<br>L25P_1<br>IRDY1<br>RHCLK6|VCCO_1|**I/O**<br>L26P_1<br>A10|
|**VCCINT**|**GND**|**VCCINT **|**INPUT**<br>L31P_1|**INPUT**<br>L27N_1|**GND**|**I/O**<br>L28P_1|**I/O**<br>L28N_1|**I/O**<br>L22N_1<br>TRDY1<br>RHCLK3|**I/O**<br>L22P_1<br>RHCLK2|**I/O**<br>L21N_1<br>RHCLK1|
|**GND**|**VCCINT**|**GND**|**INPUT**<br>L27P_1<br>VREF_1|**INPUT**<br>L23N_1|**INPUT**<br>L23P_1|**I/O**<br>L24P_1<br>RHCLK4|VCCAUX|**I/O**<br>L24N_1<br>RHCLK5|**GND**|**I/O**<br>L21P_1<br>RHCLK0|
|**VCCINT**|**GND**|**VCCINT **|**INPUT**<br>L16P_1|**INPUT**<br>L16N_1<br>VREF_1|**I/O**<br>L20N_1<br>A9|**I/O**<br>L20P_1<br>A8|**I/O**<br>L19N_1<br>A7|**I/O**<br>L19P_1<br>A6|**I/O**<br>L18N_1<br>A5|**I/O**<br>L18P_1<br>A4|
|**INPUT**|**VCCINT**|**GND**|**INPUT**<br>L08P_1|**INPUT**<br>L08N_1|VCCO_1|**I/O**<br>L17N_1<br>A3|**GND**|**I/O**<br>L15P_1|VCCO_1|**I/O**<br>L15N_1<br>VREF_1|
|**INPUT**<br>VREF_2|**INPUT**<br>VREF_2|**INPUT**<br>VREF_2|**INPUT**<br>L04P_1|**INPUT**<br>L04N_1<br>VREF_1|**INPUT**<br>L12P_1|**INPUT**<br>L12N_1<br>VREF_1|**I/O**<br>L17P_1<br>A2|**I/O**<br>L13P_1|**I/O**<br>L14P_1|**I/O**<br>L14N_1|
|**GND**|**INPUT**|**INPUT**|**INPUT**<br>VREF_2|**INPUT**<br>VREF_2|**I/O**<br>L03P_1<br>A0|**I/O**<br>L03N_1<br>A1|**I/O**<br>L13N_1|**I/O**<br>L11P_1|**GND**|**I/O**<br>L11N_1|
|**I/O**<br>L20N_2<br>GCLK3|**I/O**<br>L26N_2<br>D3|VCCO_2|**INPUT**|**INPUT**<br>◆|**GND**|**SUSPEND**|**I/O**<br>L10N_1|**I/O**<br>L10P_1|**I/O**<br>L09N_1|**I/O**<br>L09P_1|
|**I/O**<br>L20P_2<br>GCLK2|**I/O**<br>L26P_2<br>INIT_B|**I/O**<br>L30P_2|**I/O**<br>L30N_2|**I/O**<br>L31N_2|**I/O**<br>L33N_2|VCCAUX|**I/O**<br>L06P_1|**I/O**<br>L06N_1|VCCO_1|**I/O**<br>L07N_1|
|**I/O**<br>L18P_2<br>GCLK14|**I/O**<br>L23P_2|**GND**|**I/O**<br>L25P_2|**I/O**<br>L31P_2|**I/O**<br>L34N_2|**I/O**<br>L33P_2|**I/O**<br>L02P_1<br>LDC1|**I/O**<br>L02N_1<br>LDC0|**I/O**<br>L05N_1|**I/O**<br>L07P_1|
|**I/O**<br>L18N_2<br>GCLK15|**I/O**<br>L21N_2|**I/O**<br>L23N_2|**I/O**<br>L25N_2|**I/O**<br>L27N_2|**I/O**<br>L28N_2<br>D1|**I/O**<br>L34P_2|**DONE**|**GND**|**I/O**<br>L01N_1<br>LDC2|**I/O**<br>L05P_1|
|**I/O**<br>L19P_2<br>GCLK0|VCCO_2|**I/O**<br>L22P_2|**I/O**<br>L24N_2<br>DOUT|**GND**|**I/O**<br>L28P_2<br>D2|VCCO_2|**I/O**<br>L32N_2|**I/O**<br>L36N_2<br>CCLK|**I/O**<br>L35N_2|**I/O**<br>L01P_1<br>HDC|
|**I/O**<br>L19N_2<br>GCLK1|**I/O**<br>L21P_2|**I/O**<br>L22N_2<br>MOSI<br>CSI_B|**I/O**<br>L24P_2<br>AWAKE|**I/O**<br>L27P_2|**I/O**<br>L29P_2|**I/O**<br>L29N_2|**I/O**<br>L32P_2|**I/O**<br>L36P_2<br>D0<br>DIN/MISO|**I/O**<br>L35P_2|**GND**|



## **Right Half of FGG484 Package (Top View)** 

**Bank 2** 

DS557_4_23_030911 

_Figure 23:_ **FGG484 Package Footprint (Top View)** 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

109 

**Spartan-3AN FPGA Family: Pinout Descriptions** 

## **FGG676: 676-Ball Fine-Pitch Ball Grid Array** 

The 676-ball fine-pitch ball grid array, FGG676, supports the XC3S1400AN FPGA. 

Table 82 lists all the FGG676 package pins. They are sorted by bank number and then by pin name. Pins that form a differential I/O pair appear together in the table. The table also shows the pin number for each pin and the pin type (as defined in Table 62). 

The XC3S1400AN has 17 unconnected balls, indicated as N.C. in Table 82 and Figure 24. 

An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at: www.xilinx.com/support/documentation/data_sheets/s3a_pin.zip. 

## **Pinout Table** 

_Table  82:_ **Spartan-3AN FGG676 Pinout** 

|**Bank**|**Pin Name**|**FGG676**<br>**Ball**|**Type**|
|---|---|---|---|
|0|IO_L01N_0|F20|I/O|
|0|IO_L01P_0|G20|I/O|
|0|IO_L02N_0|F19|I/O|
|0|IO_L02P_0/VREF_0|G19|VREF|
|0|IO_L05N_0|C22|I/O|
|0|IO_L05P_0|D22|I/O|
|0|IO_L06N_0|C23|I/O|
|0|IO_L06P_0|D23|I/O|
|0|IO_L07N_0|A22|I/O|
|0|IO_L07P_0|B23|I/O|
|0|IO_L08N_0|G17|I/O|
|0|IO_L08P_0|H17|I/O|
|0|IO_L09N_0|B21|I/O|
|0|IO_L09P_0|C21|I/O|
|0|IO_L10N_0|D21|I/O|
|0|IO_L10P_0|E21|I/O|
|0|IO_L11N_0|C20|I/O|
|0|IO_L11P_0|D20|I/O|
|0|IO_L12N_0|K16|I/O|
|0|IO_L12P_0|J16|I/O|
|0|IO_L13N_0|E17|I/O|
|0|IO_L13P_0|F17|I/O|
|0|IO_L14N_0|A20|I/O|
|0|IO_L14P_0/VREF_0|B20|VREF|
|0|IO_L15N_0|A19|I/O|
|0|IO_L15P_0|B19|I/O|
|0|IO_L16N_0|H15|I/O|
|0|IO_L16P_0|G15|I/O|
|0|IO_L17N_0|C18|I/O|
|0|IO_L17P_0|D18|I/O|



_Table  82:_ **Spartan-3AN FGG676 Pinout** _**(Cont’d)**_ 

|**Bank**|**Pin Name**|**FGG676**<br>**Ball**|**Type**|
|---|---|---|---|
|0|IO_L18N_0|A18|I/O|
|0|IO_L18P_0|B18|I/O|
|0|IO_L19N_0|B17|I/O|
|0|IO_L19P_0|C17|I/O|
|0|IO_L20N_0/VREF_0|E15|VREF|
|0|IO_L20P_0|F15|I/O|
|0|IO_L21N_0|C16|I/O|
|0|IO_L21P_0|D17|I/O|
|0|IO_L22N_0|C15|I/O|
|0|IO_L22P_0|D16|I/O|
|0|IO_L23N_0|A15|I/O|
|0|IO_L23P_0|B15|I/O|
|0|IO_L24N_0|F14|I/O|
|0|IO_L24P_0|E14|I/O|
|0|IO_L25N_0/GCLK5|J14|GCLK|
|0|IO_L25P_0/GCLK4|K14|GCLK|
|0|IO_L26N_0/GCLK7|A14|GCLK|
|0|IO_L26P_0/GCLK6|B14|GCLK|
|0|IO_L27N_0/GCLK9|G13|GCLK|
|0|IO_L27P_0/GCLK8|F13|GCLK|
|0|IO_L28N_0/GCLK11|C13|GCLK|
|0|IO_L28P_0/GCLK10|B13|GCLK|
|0|IO_L29N_0|B12|I/O|
|0|IO_L29P_0|A12|I/O|
|0|IO_L30N_0|C12|I/O|
|0|IO_L30P_0|D13|I/O|
|0|IO_L31N_0|F12|I/O|
|0|IO_L31P_0|E12|I/O|
|0|IO_L32N_0/VREF_0|D11|VREF|
|0|IO_L32P_0|C11|I/O|



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

110 

**Spartan-3AN FPGA Family: Pinout Descriptions** 

_Table  82:_ **Spartan-3AN FGG676 Pinout** _**(Cont’d)**_ 

|**Bank**|**Pin Name**|**FGG676**<br>**Ball**|**Type**|
|---|---|---|---|
|0|IO_L33N_0|B10|I/O|
|0|IO_L33P_0|A10|I/O|
|0|IO_L34N_0|D10|I/O|
|0|IO_L34P_0|C10|I/O|
|0|IO_L35N_0|H12|I/O|
|0|IO_L35P_0|G12|I/O|
|0|IO_L36N_0|B9|I/O|
|0|IO_L36P_0|A9|I/O|
|0|IO_L37N_0|D9|I/O|
|0|IO_L37P_0|E10|I/O|
|0|IO_L38N_0|B8|I/O|
|0|IO_L38P_0|A8|I/O|
|0|IO_L39N_0|K12|I/O|
|0|IO_L39P_0|J12|I/O|
|0|IO_L40N_0|D8|I/O|
|0|IO_L40P_0|C8|I/O|
|0|IO_L41N_0|C6|I/O|
|0|IO_L41P_0|B6|I/O|
|0|IO_L42N_0|C7|I/O|
|0|IO_L42P_0|B7|I/O|
|0|IO_L43N_0|K11|I/O|
|0|IO_L43P_0|J11|I/O|
|0|IO_L44N_0|D6|I/O|
|0|IO_L44P_0|C5|I/O|
|0|IO_L45N_0|B4|I/O|
|0|IO_L45P_0|A4|I/O|
|0|IO_L46N_0|H10|I/O|
|0|IO_L46P_0|G10|I/O|
|0|IO_L47N_0|H9|I/O|
|0|IO_L47P_0|G9|I/O|
|0|IO_L48N_0|E7|I/O|
|0|IO_L48P_0|F7|I/O|
|0|IO_L51N_0|B3|I/O|
|0|IO_L51P_0|A3|I/O|
|0|IO_L52N_0/PUDC_B|G8|DUAL|
|0|IO_L52P_0/VREF_0|F8|VREF|
|0|IP_0|A5|INPUT|
|0|IP_0|A7|INPUT|
|0|IP_0|A13|INPUT|
|0|IP_0|A17|INPUT|



_Table  82:_ **Spartan-3AN FGG676 Pinout** _**(Cont’d)**_ 

|**Bank**|**Pin Name**|**FGG676**<br>**Ball**|**Type**|
|---|---|---|---|
|0|IP_0|A23|INPUT|
|0|IP_0|C4|INPUT|
|0|IP_0|D12|INPUT|
|0|IP_0|D15|INPUT|
|0|IP_0|D19|INPUT|
|0|IP_0|E11|INPUT|
|0|IP_0|E18|INPUT|
|0|IP_0|E20|INPUT|
|0|IP_0|F10|INPUT|
|0|IP_0|G14|INPUT|
|0|IP_0|G16|INPUT|
|0|IP_0|H13|INPUT|
|0|IP_0|H18|INPUT|
|0|IP_0|J10|INPUT|
|0|IP_0|J13|INPUT|
|0|IP_0|J15|INPUT|
|0|IP_0/VREF_0|D7|VREF|
|0|IP_0/VREF_0|D14|VREF|
|0|IP_0/VREF_0|G11|VREF|
|0|IP_0/VREF_0|J17|VREF|
|0|N.C.|A24|N.C.|
|0|N.C.|B24|N.C.|
|0|N.C.|D5|N.C.|
|0|N.C.|E9|N.C.|
|0|N.C.|F18|N.C.|
|0|N.C.|E6|N.C.|
|0|N.C.|F9|N.C.|
|0|N.C.|G18|N.C.|
|0|VCCO_0|B5|VCCO|
|0|VCCO_0|B11|VCCO|
|0|VCCO_0|B16|VCCO|
|0|VCCO_0|B22|VCCO|
|0|VCCO_0|E8|VCCO|
|0|VCCO_0|E13|VCCO|
|0|VCCO_0|E19|VCCO|
|0|VCCO_0|H11|VCCO|
|0|VCCO_0|H16|VCCO|
|1|IO_L01N_1/LDC2|Y21|DUAL|
|1|IO_L01P_1/HDC|Y20|DUAL|
|1|IO_L02N_1/LDC0|AD25|DUAL|



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

111 

**Spartan-3AN FPGA Family: Pinout Descriptions** 

_Table  82:_ **Spartan-3AN FGG676 Pinout** _**(Cont’d)**_ 

|**Bank**|**Pin Name**|**FGG676**<br>**Ball**|**Type**|
|---|---|---|---|
|1|IO_L02P_1/LDC1|AE26|DUAL|
|1|IO_L03N_1/A1|AC24|DUAL|
|1|IO_L03P_1/A0|AC23|DUAL|
|1|IO_L04N_1|W21|I/O|
|1|IO_L04P_1|W20|I/O|
|1|IO_L05N_1|AC25|I/O|
|1|IO_L05P_1|AD26|I/O|
|1|IO_L06N_1|AB26|I/O|
|1|IO_L06P_1|AC26|I/O|
|1|IO_L07N_1/VREF_1|AB24|VREF|
|1|IO_L07P_1|AB23|I/O|
|1|IO_L08N_1|V19|I/O|
|1|IO_L08P_1|V18|I/O|
|1|IO_L09N_1|AA23|I/O|
|1|IO_L09P_1|AA22|I/O|
|1|IO_L10N_1|U20|I/O|
|1|IO_L10P_1|V21|I/O|
|1|IO_L11N_1|AA25|I/O|
|1|IO_L11P_1|AA24|I/O|
|1|IO_L12N_1|U18|I/O|
|1|IO_L12P_1|U19|I/O|
|1|IO_L13N_1|Y23|I/O|
|1|IO_L13P_1|Y22|I/O|
|1|IO_L14N_1|T20|I/O|
|1|IO_L14P_1|U21|I/O|
|1|IO_L15N_1|Y25|I/O|
|1|IO_L15P_1|Y24|I/O|
|1|IO_L17N_1|T17|I/O|
|1|IO_L17P_1|T18|I/O|
|1|IO_L18N_1|V22|I/O|
|1|IO_L18P_1|W23|I/O|
|1|IO_L19N_1|V25|I/O|
|1|IO_L19P_1|V24|I/O|
|1|IO_L21N_1|U22|I/O|
|1|IO_L21P_1|V23|I/O|
|1|IO_L22N_1|R20|I/O|
|1|IO_L22P_1|R19|I/O|
|1|IO_L23N_1/VREF_1|U24|VREF|
|1|IO_L23P_1|U23|I/O|
|1|IO_L25N_1/A3|R22|DUAL|



_Table  82:_ **Spartan-3AN FGG676 Pinout** _**(Cont’d)**_ 

|**Bank**|**Pin Name**|**FGG676**<br>**Ball**|**Type**|
|---|---|---|---|
|1|IO_L25P_1/A2|R21|DUAL|
|1|IO_L26N_1/A5|T24|DUAL|
|1|IO_L26P_1/A4|T23|DUAL|
|1|IO_L27N_1/A7|R17|DUAL|
|1|IO_L27P_1/A6|R18|DUAL|
|1|IO_L29N_1/A9|R26|DUAL|
|1|IO_L29P_1/A8|R25|DUAL|
|1|IO_L30N_1/RHCLK1|P20|RHCLK|
|1|IO_L30P_1/RHCLK0|P21|RHCLK|
|1|IO_L31N_1/TRDY1/RHCLK3|P25|RHCLK|
|1|IO_L31P_1/RHCLK2|P26|RHCLK|
|1|IO_L33N_1/RHCLK5|N24|RHCLK|
|1|IO_L33P_1/RHCLK4|P23|RHCLK|
|1|IO_L34N_1/RHCLK7|N19|RHCLK|
|1|IO_L34P_1/IRDY1/RHCLK6|P18|RHCLK|
|1|IO_L35N_1/A11|M25|DUAL|
|1|IO_L35P_1/A10|M26|DUAL|
|1|IO_L37N_1|N21|I/O|
|1|IO_L37P_1|P22|I/O|
|1|IO_L38N_1/A13|M23|DUAL|
|1|IO_L38P_1/A12|L24|DUAL|
|1|IO_L39N_1/A15|N17|DUAL|
|1|IO_L39P_1/A14|N18|DUAL|
|1|IO_L41N_1|K26|I/O|
|1|IO_L41P_1|K25|I/O|
|1|IO_L42N_1/A17|M20|DUAL|
|1|IO_L42P_1/A16|N20|DUAL|
|1|IO_L43N_1/A19|J25|DUAL|
|1|IO_L43P_1/A18|J26|DUAL|
|1|IO_L45N_1|M22|I/O|
|1|IO_L45P_1|M21|I/O|
|1|IO_L46N_1|K22|I/O|
|1|IO_L46P_1|K23|I/O|
|1|IO_L47N_1|M18|I/O|
|1|IO_L47P_1|M19|I/O|
|1|IO_L49N_1|J22|I/O|
|1|IO_L49P_1|J23|I/O|
|1|IO_L50N_1|K21|I/O|
|1|IO_L50P_1|L22|I/O|
|1|IO_L51N_1|G24|I/O|



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

112 

**Spartan-3AN FPGA Family: Pinout Descriptions** 

_Table  82:_ **Spartan-3AN FGG676 Pinout** _**(Cont’d)**_ 

_Table  82:_ **Spartan-3AN FGG676 Pinout** _**(Cont’d)**_ 

|**Bank**|**Pin Name**|**FGG676**<br>**Ball**|**Type**||**Bank**|**Pin Name**|**FGG676**<br>**Ball**|**Type**|
|---|---|---|---|---|---|---|---|---|
|1|IO_L51P_1|G23|I/O||1|IP_L44P_1/VREF_1|H26|VREF|
|1|IO_L53N_1|K20|I/O||1|IP_L48N_1|H24|INPUT|
|1|IO_L53P_1|L20|I/O||1|IP_L48P_1|H23|INPUT|
|1|IO_L54N_1|F24|I/O||1|IP_L52N_1/VREF_1|G25|VREF|
|1|IO_L54P_1|F25|I/O||1|IP_L52P_1|G26|INPUT|
|1|IO_L55N_1|L17|I/O||1|IP_L65N_1|B25|INPUT|
|1|IO_L55P_1|L18|I/O||1|IP_L65P_1/VREF_1|B26|VREF|
|1|IO_L56N_1|F23|I/O||1|VCCO_1|AB25|VCCO|
|1|IO_L56P_1|E24|I/O||1|VCCO_1|E25|VCCO|
|1|IO_L57N_1|K18|I/O||1|VCCO_1|H22|VCCO|
|1|IO_L57P_1|K19|I/O||1|VCCO_1|L19|VCCO|
|1|IO_L58N_1|G22|I/O||1|VCCO_1|L25|VCCO|
|1|IO_L58P_1/VREF_1|F22|VREF||1|VCCO_1|N22|VCCO|
|1|IO_L59N_1|J20|I/O||1|VCCO_1|T19|VCCO|
|1|IO_L59P_1|J19|I/O||1|VCCO_1|T25|VCCO|
|1|IO_L60N_1|D26|I/O||1|VCCO_1|W22|VCCO|
|1|IO_L60P_1|E26|I/O||2|IO_L01N_2/M0|AD4|DUAL|
|1|IO_L61N_1|D24|I/O||2|IO_L01P_2/M1|AC4|DUAL|
|1|IO_L61P_1|D25|I/O||2|IO_L02N_2/CSO_B|AA7|DUAL|
|1|IO_L62N_1/A21|H21|DUAL||2|IO_L02P_2/M2|Y7|DUAL|
|1|IO_L62P_1/A20|J21|DUAL||2|IO_L05N_2|Y9|I/O|
|1|IO_L63N_1/A23|C25|DUAL||2|IO_L05P_2|W9|I/O|
|1|IO_L63P_1/A22|C26|DUAL||2|IO_L06N_2|AF3|I/O|
|1|IO_L64N_1/A25|G21|DUAL||2|IO_L06P_2|AE3|I/O|
|1|IO_L64P_1/A24|H20|DUAL||2|IO_L07N_2|AF4|I/O|
|1|IP_L16N_1|Y26|INPUT||2|IO_L07P_2|AE4|I/O|
|1|IP_L16P_1|W25|INPUT||2|IO_L08N_2|AD6|I/O|
|1|IP_L20N_1/VREF_1|V26|VREF||2|IO_L08P_2|AC6|I/O|
|1|IP_L20P_1|W26|INPUT||2|IO_L09N_2|W10|I/O|
|1|IP_L24N_1/VREF_1|U26|VREF||2|IO_L09P_2|V10|I/O|
|1|IP_L24P_1|U25|INPUT||2|IO_L10N_2|AE6|I/O|
|1|IP_L28N_1|R24|INPUT||2|IO_L10P_2|AF5|I/O|
|1|IP_L28P_1/VREF_1|R23|VREF||2|IO_L11N_2|AE7|I/O|
|1|IP_L32N_1|N25|INPUT||2|IO_L11P_2|AD7|I/O|
|1|IP_L32P_1|N26|INPUT||2|IO_L12N_2|AA10|I/O|
|1|IP_L36N_1|N23|INPUT||2|IO_L12P_2|Y10|I/O|
|1|IP_L36P_1/VREF_1|M24|VREF||2|IO_L13N_2|U11|I/O|
|1|IP_L40N_1|L23|INPUT||2|IO_L13P_2|V11|I/O|
|1|IP_L40P_1|K24|INPUT||2|IO_L14N_2|AB7|I/O|
|1|IP_L44N_1|H25|INPUT||2|IO_L14P_2|AC8|I/O|



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

113 

**Spartan-3AN FPGA Family: Pinout Descriptions** 

_Table  82:_ **Spartan-3AN FGG676 Pinout** _**(Cont’d)**_ 

_Table  82:_ **Spartan-3AN FGG676 Pinout** _**(Cont’d)**_ 

|**Bank**|**Pin Name**|**FGG676**<br>**Ball**|**Type**||**Bank**|**Pin Name**|**FGG676**<br>**Ball**|**Type**|
|---|---|---|---|---|---|---|---|---|
|2|IO_L15N_2|AC9|I/O||2|IO_L35N_2|U15|I/O|
|2|IO_L15P_2|AB9|I/O||2|IO_L35P_2|V15|I/O|
|2|IO_L16N_2|W12|I/O||2|IO_L36N_2/D1|AE18|DUAL|
|2|IO_L16P_2|V12|I/O||2|IO_L36P_2/D2|AF18|DUAL|
|2|IO_L17N_2/VS2|AA12|DUAL||2|IO_L37N_2|AE19|I/O|
|2|IO_L17P_2/RDWR_B|Y12|DUAL||2|IO_L37P_2|AF19|I/O|
|2|IO_L18N_2|AF8|I/O||2|IO_L38N_2|AB16|I/O|
|2|IO_L18P_2|AE8|I/O||2|IO_L38P_2|AC16|I/O|
|2|IO_L19N_2/VS0|AF9|DUAL||2|IO_L39N_2|AE20|I/O|
|2|IO_L19P_2/VS1|AE9|DUAL||2|IO_L39P_2|AF20|I/O|
|2|IO_L20N_2|W13|I/O||2|IO_L40N_2|AC19|I/O|
|2|IO_L20P_2|V13|I/O||2|IO_L40P_2|AD19|I/O|
|2|IO_L21N_2|AC12|I/O||2|IO_L41N_2|AC20|I/O|
|2|IO_L21P_2|AB12|I/O||2|IO_L41P_2|AD20|I/O|
|2|IO_L22N_2/D6|AF10|DUAL||2|IO_L42N_2|U16|I/O|
|2|IO_L22P_2/D7|AE10|DUAL||2|IO_L42P_2|V16|I/O|
|2|IO_L23N_2|AC11|I/O||2|IO_L43N_2|Y17|I/O|
|2|IO_L23P_2|AD11|I/O||2|IO_L43P_2|AA17|I/O|
|2|IO_L24N_2/D4|AE12|DUAL||2|IO_L44N_2|AD21|I/O|
|2|IO_L24P_2/D5|AF12|DUAL||2|IO_L44P_2|AE21|I/O|
|2|IO_L25N_2/GCLK13|Y13|GCLK||2|IO_L45N_2|AC21|I/O|
|2|IO_L25P_2/GCLK12|AA13|GCLK||2|IO_L45P_2|AD22|I/O|
|2|IO_L26N_2/GCLK15|AE13|GCLK||2|IO_L46N_2|V17|I/O|
|2|IO_L26P_2/GCLK14|AF13|GCLK||2|IO_L46P_2|W17|I/O|
|2|IO_L27N_2/GCLK1|AA14|GCLK||2|IO_L47N_2|AA18|I/O|
|2|IO_L27P_2/GCLK0|Y14|GCLK||2|IO_L47P_2|AB18|I/O|
|2|IO_L28N_2/GCLK3|AE14|GCLK||2|IO_L48N_2|AE23|I/O|
|2|IO_L28P_2/GCLK2|AF14|GCLK||2|IO_L48P_2|AF23|I/O|
|2|IO_L29N_2|AC14|I/O||2|IO_L51N_2|AE25|I/O|
|2|IO_L29P_2|AD14|I/O||2|IO_L51P_2|AF25|I/O|
|2|IO_L30N_2/MOSI/CSI_B|AB15|DUAL||2|IO_L52N_2/CCLK|AE24|DUAL|
|2|IO_L30P_2|AC15|I/O||2|IO_L52P_2/D0/DIN/MISO|AF24|DUAL|
|2|IO_L31N_2|W15|I/O||2|IP_2|AA19|INPUT|
|2|IO_L31P_2|V14|I/O||2|IP_2|AB13|INPUT|
|2|IO_L32N_2/DOUT|AE15|DUAL||2|IP_2|AB17|INPUT|
|2|IO_L32P_2/AWAKE|AD15|PWR MGMT||2|IP_2|AB20|INPUT|
|2|IO_L33N_2|AD17|I/O||2|IP_2|AC7|INPUT|
|2|IO_L33P_2|AE17|I/O||2|IP_2|AC13|INPUT|
|2|IO_L34N_2/D3|Y15|DUAL||2|IP_2|AC17|INPUT|
|2|IO_L34P_2/INIT_B|AA15|DUAL||2|IP_2|AC18|INPUT|



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

114 

**Spartan-3AN FPGA Family: Pinout Descriptions** 

_Table  82:_ **Spartan-3AN FGG676 Pinout** _**(Cont’d)**_ 

_Table  82:_ **Spartan-3AN FGG676 Pinout** _**(Cont’d)**_ 

|**Bank**|**Pin Name**|**FGG676**<br>**Ball**|**Type**||**Bank**|**Pin Name**|**FGG676**<br>**Ball**|**Type**|
|---|---|---|---|---|---|---|---|---|
|2|IP_2|AD9|INPUT||3|IO_L05N_3|K8|I/O|
|2|IP_2|AD10|INPUT||3|IO_L05P_3|K9|I/O|
|2|IP_2|AD16|INPUT||3|IO_L06N_3|E4|I/O|
|2|IP_2|AF2|INPUT||3|IO_L06P_3|D3|I/O|
|2|IP_2|AF7|INPUT||3|IO_L07N_3|F4|I/O|
|2|IP_2|Y11|INPUT||3|IO_L07P_3|E3|I/O|
|2|IP_2/VREF_2|AA9|VREF||3|IO_L09N_3|G4|I/O|
|2|IP_2/VREF_2|AA20|VREF||3|IO_L09P_3|F5|I/O|
|2|IP_2/VREF_2|AB6|VREF||3|IO_L10N_3|H6|I/O|
|2|IP_2/VREF_2|AB10|VREF||3|IO_L10P_3|J7|I/O|
|2|IP_2/VREF_2|AC10|VREF||3|IO_L11N_3|F2|I/O|
|2|IP_2/VREF_2|AD12|VREF||3|IO_L11P_3|E1|I/O|
|2|IP_2/VREF_2|AF15|VREF||3|IO_L13N_3|J6|I/O|
|2|IP_2/VREF_2|AF17|VREF||3|IO_L13P_3|K7|I/O|
|2|IP_2/VREF_2|AF22|VREF||3|IO_L14N_3|F3|I/O|
|2|IP_2/VREF_2|Y16|VREF||3|IO_L14P_3|G3|I/O|
|2|N.C.|AA8|N.C.||3|IO_L15N_3|L9|I/O|
|2|N.C.|AC5|N.C.||3|IO_L15P_3|L10|I/O|
|2|N.C.|AC22|N.C.||3|IO_L17N_3|H1|I/O|
|2|N.C.|AD5|N.C.||3|IO_L17P_3|H2|I/O|
|2|N.C.|Y18|N.C.||3|IO_L18N_3|L7|I/O|
|2|N.C.|Y19|N.C.||3|IO_L18P_3|K6|I/O|
|2|N.C.|AD23|N.C.||3|IO_L19N_3|J4|I/O|
|2|N.C.|W18|N.C.||3|IO_L19P_3|J5|I/O|
|2|N.C.|Y8|N.C.||3|IO_L21N_3|M9|I/O|
|2|VCCO_2|AB8|VCCO||3|IO_L21P_3|M10|I/O|
|2|VCCO_2|AB14|VCCO||3|IO_L22N_3|K4|I/O|
|2|VCCO_2|AB19|VCCO||3|IO_L22P_3|K5|I/O|
|2|VCCO_2|AE5|VCCO||3|IO_L23N_3|K2|I/O|
|2|VCCO_2|AE11|VCCO||3|IO_L23P_3|K3|I/O|
|2|VCCO_2|AE16|VCCO||3|IO_L25N_3|L3|I/O|
|2|VCCO_2|AE22|VCCO||3|IO_L25P_3|L4|I/O|
|2|VCCO_2|W11|VCCO||3|IO_L26N_3|M7|I/O|
|2|VCCO_2|W16|VCCO||3|IO_L26P_3|M8|I/O|
|3|IO_L01N_3|J9|I/O||3|IO_L27N_3|M3|I/O|
|3|IO_L01P_3|J8|I/O||3|IO_L27P_3|M4|I/O|
|3|IO_L02N_3|B1|I/O||3|IO_L28N_3|M6|I/O|
|3|IO_L02P_3|B2|I/O||3|IO_L28P_3|M5|I/O|
|3|IO_L03N_3|H7|I/O||3|IO_L29N_3/VREF_3|M1|VREF|
|3|IO_L03P_3|G6|I/O||3|IO_L29P_3|M2|I/O|



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

115 

**Spartan-3AN FPGA Family: Pinout Descriptions** 

_Table  82:_ **Spartan-3AN FGG676 Pinout** _**(Cont’d)**_ 

|**Bank**|**Pin Name**|**FGG676**<br>**Ball**|**Type**|
|---|---|---|---|
|3|IO_L30N_3|N4|I/O|
|3|IO_L30P_3|N5|I/O|
|3|IO_L31N_3|N2|I/O|
|3|IO_L31P_3|N1|I/O|
|3|IO_L32N_3/LHCLK1|N7|LHCLK|
|3|IO_L32P_3/LHCLK0|N6|LHCLK|
|3|IO_L33N_3/IRDY2/LHCLK3|P2|LHCLK|
|3|IO_L33P_3/LHCLK2|P1|LHCLK|
|3|IO_L34N_3/LHCLK5|P3|LHCLK|
|3|IO_L34P_3/LHCLK4|P4|LHCLK|
|3|IO_L35N_3/LHCLK7|P10|LHCLK|
|3|IO_L35P_3/TRDY2/LHCLK6|N9|LHCLK|
|3|IO_L36N_3|R2|I/O|
|3|IO_L36P_3/VREF_3|R1|VREF|
|3|IO_L37N_3|R4|I/O|
|3|IO_L37P_3|R3|I/O|
|3|IO_L38N_3|T4|I/O|
|3|IO_L38P_3|T3|I/O|
|3|IO_L39N_3|P6|I/O|
|3|IO_L39P_3|P7|I/O|
|3|IO_L40N_3|R6|I/O|
|3|IO_L40P_3|R5|I/O|
|3|IO_L41N_3|P9|I/O|
|3|IO_L41P_3|P8|I/O|
|3|IO_L42N_3|U4|I/O|
|3|IO_L42P_3|T5|I/O|
|3|IO_L43N_3|R9|I/O|
|3|IO_L43P_3/VREF_3|R10|VREF|
|3|IO_L44N_3|U2|I/O|
|3|IO_L44P_3|U1|I/O|
|3|IO_L45N_3|R7|I/O|
|3|IO_L45P_3|R8|I/O|
|3|IO_L47N_3|V2|I/O|
|3|IO_L47P_3|V1|I/O|
|3|IO_L48N_3|T9|I/O|
|3|IO_L48P_3|T10|I/O|
|3|IO_L49N_3|V5|I/O|
|3|IO_L49P_3|U5|I/O|
|3|IO_L51N_3|U6|I/O|
|3|IO_L51P_3|T7|I/O|



_Table  82:_ **Spartan-3AN FGG676 Pinout** _**(Cont’d)**_ 

|**Bank**|**Pin Name**|**FGG676**<br>**Ball**|**Type**|
|---|---|---|---|
|3|IO_L52N_3|W4|I/O|
|3|IO_L52P_3|W3|I/O|
|3|IO_L53N_3|Y2|I/O|
|3|IO_L53P_3|Y1|I/O|
|3|IO_L55N_3|AA3|I/O|
|3|IO_L55P_3|AA2|I/O|
|3|IO_L56N_3|U8|I/O|
|3|IO_L56P_3|U7|I/O|
|3|IO_L57N_3|Y6|I/O|
|3|IO_L57P_3|Y5|I/O|
|3|IO_L59N_3|V6|I/O|
|3|IO_L59P_3|V7|I/O|
|3|IO_L60N_3|AC1|I/O|
|3|IO_L60P_3|AB1|I/O|
|3|IO_L61N_3|V8|I/O|
|3|IO_L61P_3|U9|I/O|
|3|IO_L63N_3|W6|I/O|
|3|IO_L63P_3|W7|I/O|
|3|IO_L64N_3|AC3|I/O|
|3|IO_L64P_3|AC2|I/O|
|3|IO_L65N_3|AD2|I/O|
|3|IO_L65P_3|AD1|I/O|
|3|IP_L04N_3/VREF_3|C1|VREF|
|3|IP_L04P_3|C2|INPUT|
|3|IP_L08N_3|D1|INPUT|
|3|IP_L08P_3|D2|INPUT|
|3|IP_L12N_3/VREF_3|H4|VREF|
|3|IP_L12P_3|G5|INPUT|
|3|IP_L16N_3|G1|INPUT|
|3|IP_L16P_3|G2|INPUT|
|3|IP_L20N_3/VREF_3|J2|VREF|
|3|IP_L20P_3|J3|INPUT|
|3|IP_L24N_3|K1|INPUT|
|3|IP_L24P_3|J1|INPUT|
|3|IP_L46N_3|V4|INPUT|
|3|IP_L46P_3|U3|INPUT|
|3|IP_L50N_3/VREF_3|W2|VREF|
|3|IP_L50P_3|W1|INPUT|
|3|IP_L54N_3|Y4|INPUT|
|3|IP_L54P_3|Y3|INPUT|



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

116 

**Spartan-3AN FPGA Family: Pinout Descriptions** 

_Table  82:_ **Spartan-3AN FGG676 Pinout** _**(Cont’d)**_ 

_Table  82:_ **Spartan-3AN FGG676 Pinout** _**(Cont’d)**_ 

|**Bank**|**Pin Name**|**FGG676**<br>**Ball**|**Type**||**Bank**|**Pin Name**|**FGG676**<br>**Ball**|**Type**|
|---|---|---|---|---|---|---|---|---|
|3|IP_L58N_3/VREF_3|AA5|VREF||GND|GND|C14|GND|
|3|IP_L58P_3|AA4|INPUT||GND|GND|C19|GND|
|3|IP_L62N_3|AB4|INPUT||GND|GND|C24|GND|
|3|IP_L62P_3|AB3|INPUT||GND|GND|F1|GND|
|3|IP_L66N_3/VREF_3|AE2|VREF||GND|GND|F6|GND|
|3|IP_L66P_3|AE1|INPUT||GND|GND|F11|GND|
|3|VCCO_3|AB2|VCCO||GND|GND|F16|GND|
|3|VCCO_3|E2|VCCO||GND|GND|F21|GND|
|3|VCCO_3|H5|VCCO||GND|GND|F26|GND|
|3|VCCO_3|L2|VCCO||GND|GND|H3|GND|
|3|VCCO_3|L8|VCCO||GND|GND|H8|GND|
|3|VCCO_3|P5|VCCO||GND|GND|H14|GND|
|3|VCCO_3|T2|VCCO||GND|GND|H19|GND|
|3|VCCO_3|T8|VCCO||GND|GND|J24|GND|
|3|VCCO_3|W5|VCCO||GND|GND|K10|GND|
|GND|GND|A1|GND||GND|GND|K17|GND|
|GND|GND|A6|GND||GND|GND|L1|GND|
|GND|GND|A11|GND||GND|GND|L6|GND|
|GND|GND|A16|GND||GND|GND|L11|GND|
|GND|GND|A21|GND||GND|GND|L13|GND|
|GND|GND|A26|GND||GND|GND|L15|GND|
|GND|GND|AA1|GND||GND|GND|L21|GND|
|GND|GND|AA6|GND||GND|GND|L26|GND|
|GND|GND|AA11|GND||GND|GND|M12|GND|
|GND|GND|AA16|GND||GND|GND|M14|GND|
|GND|GND|AA21|GND||GND|GND|M16|GND|
|GND|GND|AA26|GND||GND|GND|N3|GND|
|GND|GND|AD3|GND||GND|GND|N8|GND|
|GND|GND|AD8|GND||GND|GND|N11|GND|
|GND|GND|AD13|GND||GND|GND|N15|GND|
|GND|GND|AD18|GND||GND|GND|P12|GND|
|GND|GND|AD24|GND||GND|GND|P16|GND|
|GND|GND|AF1|GND||GND|GND|P19|GND|
|GND|GND|AF6|GND||GND|GND|P24|GND|
|GND|GND|AF11|GND||GND|GND|R11|GND|
|GND|GND|AF16|GND||GND|GND|R13|GND|
|GND|GND|AF21|GND||GND|GND|R15|GND|
|GND|GND|AF26|GND||GND|GND|T1|GND|
|GND|GND|C3|GND||GND|GND|T6|GND|
|GND|GND|C9|GND||GND|GND|T12|GND|



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

117 

**Spartan-3AN FPGA Family: Pinout Descriptions** 

_Table  82:_ **Spartan-3AN FGG676 Pinout** _**(Cont’d)**_ 

_Table  82:_ **Spartan-3AN FGG676 Pinout** _**(Cont’d)**_ 

|**Bank**|**Pin Name**|**FGG676**<br>**Ball**|**Type**||**Bank**|**Pin Name**|**FGG676**<br>**Ball**|**Type**|
|---|---|---|---|---|---|---|---|---|
|GND|GND|T14|GND||VCCINT|VCCINT|M17|VCCINT|
|GND|GND|T16|GND||VCCINT|VCCINT|N12|VCCINT|
|GND|GND|T21|GND||VCCINT|VCCINT|N13|VCCINT|
|GND|GND|T26|GND||VCCINT|VCCINT|N14|VCCINT|
|GND|GND|U10|GND||VCCINT|VCCINT|N16|VCCINT|
|GND|GND|U13|GND||VCCINT|VCCINT|P11|VCCINT|
|GND|GND|U17|GND||VCCINT|VCCINT|P13|VCCINT|
|GND|GND|V3|GND||VCCINT|VCCINT|P14|VCCINT|
|GND|GND|W8|GND||VCCINT|VCCINT|P15|VCCINT|
|GND|GND|W14|GND||VCCINT|VCCINT|R12|VCCINT|
|GND|GND|W19|GND||VCCINT|VCCINT|R14|VCCINT|
|GND|GND|W24|GND||VCCINT|VCCINT|R16|VCCINT|
|VCCAUX|SUSPEND|V20|PWR MGMT||VCCINT|VCCINT|T11|VCCINT|
|VCCAUX|DONE|AB21|CONFIG||VCCINT|VCCINT|T13|VCCINT|
|VCCAUX|PROG_B|A2|CONFIG||VCCINT|VCCINT|T15|VCCINT|
|VCCAUX|TCK|A25|JTAG||VCCINT|VCCINT|U12|VCCINT|
|VCCAUX|TDI|G7|JTAG||||||
|VCCAUX|TDO|E23|JTAG||||||
|VCCAUX|TMS|D4|JTAG||||||
|VCCAUX|VCCAUX|AB5|VCCAUX||||||
|VCCAUX|VCCAUX|AB11|VCCAUX||||||
|VCCAUX|VCCAUX|AB22|VCCAUX||||||
|VCCAUX|VCCAUX|E5|VCCAUX||||||
|VCCAUX|VCCAUX|E16|VCCAUX||||||
|VCCAUX|VCCAUX|E22|VCCAUX||||||
|VCCAUX|VCCAUX|J18|VCCAUX||||||
|VCCAUX|VCCAUX|K13|VCCAUX||||||
|VCCAUX|VCCAUX|L5|VCCAUX||||||
|VCCAUX|VCCAUX|N10|VCCAUX||||||
|VCCAUX|VCCAUX|P17|VCCAUX||||||
|VCCAUX|VCCAUX|T22|VCCAUX||||||
|VCCAUX|VCCAUX|U14|VCCAUX||||||
|VCCAUX|VCCAUX|V9|VCCAUX||||||
|VCCINT|VCCINT|K15|VCCINT||||||
|VCCINT|VCCINT|L12|VCCINT||||||
|VCCINT|VCCINT|L14|VCCINT||||||
|VCCINT|VCCINT|L16|VCCINT||||||
|VCCINT|VCCINT|M11|VCCINT||||||
|VCCINT|VCCINT|M13|VCCINT||||||
|VCCINT|VCCINT|M15|VCCINT||||||



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

118 

**Spartan-3AN FPGA Family: Pinout Descriptions** 

## **User I/Os by Bank** 

Table 83 indicates how the 502 available user-I/O pins are distributed between the four I/O banks on the FGG676 package. The AWAKE pin is counted as a dual-purpose I/O. 

_Table  83:_ **User I/Os Per Bank for the XC3S1400AN in the FGG676 Package** 

|**Package**<br>**Edge**|**I/O Bank**|**Maximum I/Os**|**All Possible I/O Pins by Type**|**All Possible I/O Pins by Type**|**All Possible I/O Pins by Type**|**All Possible I/O Pins by Type**|**All Possible I/O Pins by Type**|
|---|---|---|---|---|---|---|---|
||||**I/O**|**INPUT**|**DUAL**|**VREF**|**CLK**|
|Top|0|120|82|20|1|9|8|
|Right|1|130|67|15|30|10|8|
|Bottom|2|120|67|14|21|10|8|
|Left|3|132|97|18|0|9|8|
|**Total**||**502**|**313**|**67**|**52**|**38**|**32**|



## **Footprint Migration Differences** 

The XC3S1400AN is the only Spartan-3AN FPGA offered in the FGG676 package. The XC3S1400AN FPGA is pin compatible with the Spartan-3A XC3S1400A FPGA in the FG(G)676 package, although the Spartan-3A FPGA requires an external configuration source. 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

119 

**Spartan-3AN FPGA Family: Pinout Descriptions** 

## **FGG676 Footprint Left Half of FGG676 Package (Top View)** 

**I/O:** Unrestricted, 313 general-purpose user I/O 

**INPUT:** Unrestricted, 67 general-purpose input pin 

**DUAL:** Configuration pins, 51 then possible user I/O **SUSPEND:** Dedicated SUSPEND and 2 dual-purpose AWAKE Power Management pins 

**VREF:** User I/O or input 38 voltage reference for bank **CLK:** User I/O, input, or 32 clock buffer input **CONFIG:** Dedicated 2 configuration pins 

**JTAG:** Dedicated JTAG 4 port pins **GND:** Ground 77 **VCCO:** Output voltage 36 supply for bank **VCCINT:** Internal core 23 supply voltage (+1.2V) **VCCAUX:** Auxiliary supply 14 voltage **N.C.:** Not connected 17 

|**A**<br>**B**<br>**C**<br>**D**<br>**E**<br>**F**<br>**G**<br>**H**<br>**J**<br>**K**<br>**L**<br>**M**<br>**N**<br>**P**<br>**R**<br>**T**<br>**U**<br>**V**<br>**W**<br>**Y**<br>**A**<br>**A**<br>**A**<br>**B**<br>**A**<br>**C**<br>**A**<br>**D**<br>**A**<br>**E**<br>**A**<br>**F**<br>**Bank 3**|**1**|**2**|**3**|**4**<br>**5**|**4**<br>**5**|**6**|**7**<br>**8**<br>**9**<br>**Bank 0**|**7**<br>**8**<br>**9**<br>**Bank 0**|**7**<br>**8**<br>**9**<br>**Bank 0**|**10**|**11**|**12**|**13**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||**GND**|**PROG_B**|**I/O**<br>L51P_0|**I/O**<br>L45P_0|**INPUT**|**GND**|**INPUT**|**I/O**<br>L38P_0|**I/O**<br>L36P_0|**I/O**<br>L33P_0|**GND**|**I/O**<br>L29P_0|**INPUT**|
||**I/O**<br>L02N_3|**I/O**<br>L02P_3|**I/O**<br>L51N_0|**I/O**<br>L45N_0|VCCO_0|**I/O**<br>L41P_0|**I/O**<br>L42P_0|**I/O**<br>L38N_0|**I/O**<br>L36N_0|**I/O**<br>L33N_0|VCCO_0|**I/O**<br>L29N_0|**I/O**<br>L28P_0<br>GCLK10|
||**INPUT**<br>L04N_3<br>VREF_3|**INPUT**<br>L04P_3|**GND**|**INPUT**|**I/O**<br>L44P_0|**I/O**<br>L41N_0|**I/O**<br>L42N_0|**I/O**<br>L40P_0|**GND**|**I/O**<br>L34P_0|**I/O**<br>L32P_0|**I/O**<br>L30N_0|**I/O**<br>L28N_0<br>GCLK11|
||**INPUT**<br>L08N_3|**INPUT**<br>L08P_3|**I/O**<br>L06P_3|**TMS**|**N.C.**|**I/O**<br>L44N_0|**INPUT**<br>VREF_0|**I/O**<br>L40N_0|**I/O**<br>L37N_0|**I/O**<br>L34N_0|**I/O**<br>L32N_0<br>VREF_0|**INPUT**|**I/O**<br>L30P_0|
||**I/O**<br>L11P_3|VCCO_3|**I/O**<br>L07P_3|**I/O**<br>L06N_3|VCCAUX|**N.C.**|**I/O**<br>L48N_0|VCCO_0|**N.C.**|**I/O**<br>L37P_0|**INPUT**|**I/O**<br>L31P_0|VCCO_0|
||**GND**|**I/O**<br>L11N_3|**I/O**<br>L14N_3|**I/O**<br>L07N_3|**I/O**<br>L09P_3|**GND**|**I/O**<br>L48P_0|**I/O**<br>L52P_0<br>VREF_0|**N.C.**|**INPUT**|**GND**|**I/O**<br>L31N_0|**I/O**<br>L27P_0<br>GCLK8|
||**INPUT**<br>L16N_3|**INPUT**<br>L16P_3|**I/O**<br>L14P_3|**I/O**<br>L09N_3|**INPUT**<br>L12P_3|**I/O**<br>L03P_3|**TDI**|**I/O**<br>L52N_0<br>PUDC_B|**I/O**<br>L47P_0|**I/O**<br>L46P_0|**INPUT**<br>VREF_0|**I/O**<br>L35P_0|**I/O**<br>L27N_0<br>GCLK9|
||**I/O**<br>L17N_3|**I/O**<br>L17P_3|**GND**|**INPUT**<br>L12N_3<br>VREF_3|VCCO_3|**I/O**<br>L10N_3|**I/O**<br>L03N_3|**GND**|**I/O**<br>L47N_0|**I/O**<br>L46N_0|VCCO_0|**I/O**<br>L35N_0|**INPUT**|
||**INPUT**<br>L24P_3|**INPUT**<br>L20N_3<br>VREF_3|**INPUT**<br>L20P_3|**I/O**<br>L19N_3|**I/O**<br>L19P_3|**I/O**<br>L13N_3|**I/O**<br>L10P_3|**I/O**<br>L01P_3|**I/O**<br>L01N_3|**INPUT**|**I/O**<br>L43P_0|**I/O**<br>L39P_0|**INPUT**|
||**INPUT**<br>L24N_3|**I/O**<br>L23N_3|**I/O**<br>L23P_3|**I/O**<br>L22N_3|**I/O**<br>L22P_3|**I/O**<br>L18P_3|**I/O**<br>L13P_3|**I/O**<br>L05N_3|**I/O**<br>L05P_3|**GND**|**I/O**<br>L43N_0|**I/O**<br>L39N_0|VCCAUX|
||**GND**|VCCO_3|**I/O**<br>L25N_3|**I/O**<br>L25P_3|VCCAUX|**GND**|**I/O**<br>L18N_3|VCCO_3|**I/O**<br>L15N_3|**I/O**<br>L15P_3|**GND**|**VCCINT**|**GND**|
||**I/O**<br>L29N_3<br>VREF_3|**I/O**<br>L29P_3|**I/O**<br>L27N_3|**I/O**<br>L27P_3|**I/O**<br>L28P_3|**I/O**<br>L28N_3|**I/O**<br>L26N_3|**I/O**<br>L26P_3|**I/O**<br>L21N_3|**I/O**<br>L21P_3|**VCCINT**|**GND**|**VCCINT**|
||**I/O**<br>L31P_3|**I/O**<br>L31N_3|**GND**|**I/O**<br>L30N_3|**I/O**<br>L30P_3|**I/O**<br>L32P_3<br>LHCLK0|**I/O**<br>L32N_3<br>LHCLK1|**GND**|**I/O**<br>L35P_3<br>TRDY2<br>LHCLK6|VCCAUX|**GND**|**VCCINT **|**VCCINT**|
||**I/O**<br>L33P_3<br>LHCLK2|**I/O**<br>L33N_3<br>IRDY2<br>LHCLK3|**I/O**<br>L34N_3<br>LHCLK5|**I/O**<br>L34P_3<br>LHCLK4|VCCO_3|**I/O**<br>L39N_3|**I/O**<br>L39P_3|**I/O**<br>L41P_3|**I/O**<br>L41N_3|**I/O**<br>L35N_3<br>LHCLK7|**VCCINT**|**GND**|**VCCINT**|
||**I/O**<br>L36P_3<br>VREF_3|**I/O**<br>L36N_3|**I/O**<br>L37P_3|**I/O**<br>L37N_3|**I/O**<br>L40P_3|**I/O**<br>L40N_3|**I/O**<br>L45N_3|**I/O**<br>L45P_3|**I/O**<br>L43N_3|**I/O**<br>L43P_3<br>VREF_3|**GND**|**VCCINT**|**GND**|
||**GND**|VCCO_3|**I/O**<br>L38P_3|**I/O**<br>L38N_3|**I/O**<br>L42P_3|**GND**|**I/O**<br>L51P_3|VCCO_3|**I/O**<br>L48N_3|**I/O**<br>L48P_3|**VCCINT**|**GND**|**VCCINT**|
||**I/O**<br>L44P_3|**I/O**<br>L44N_3|**INPUT**<br>L46P_3|**I/O**<br>L42N_3|**I/O**<br>L49P_3|**I/O**<br>L51N_3|**I/O**<br>L56P_3|**I/O**<br>L56N_3|**I/O**<br>L61P_3|**GND**|**I/O**<br>L13N_2|**VCCINT**|**GND**|
||**I/O**<br>L47P_3|**I/O**<br>L47N_3|**GND**|**INPUT**<br>L46N_3|**I/O**<br>L49N_3|**I/O**<br>L59N_3|**I/O**<br>L59P_3|**I/O**<br>L61N_3|VCCAUX|**I/O**<br>L09P_2|**I/O**<br>L13P_2|**I/O**<br>L16P_2|**I/O**<br>L20P_2|
||**INPUT**<br>L50P_3|**INPUT**<br>L50N_3<br>VREF_3|**I/O**<br>L52P_3|**I/O**<br>L52N_3|VCCO_3|**I/O**<br>L63N_3|**I/O**<br>L63P_3|**GND**|**I/O**<br>L05P_2|**I/O**<br>L09N_2|VCCO_2|**I/O**<br>L16N_2|**I/O**<br>L20N_2|
||**I/O**<br>L53P_3|**I/O**<br>L53N_3|**INPUT**<br>L54P_3|**INPUT**<br>L54N_3|**I/O**<br>L57P_3|**I/O**<br>L57N_3|**I/O**<br>L02P_2<br>M2|**N.C.**|**I/O**<br>L05N_2|**I/O**<br>L12P_2|**INPUT**|**I/O**<br>L17P_2<br>RDWR_B|**I/O**<br>L25N_2<br>GCLK13|
||**GND**|**I/O**<br>L55P_3|**I/O**<br>L55N_3|**INPUT**<br>L58P_3|**INPUT**<br>L58N_3<br>VREF_3|**GND**|**I/O**<br>L02N_2<br>CSO_B|**N.C.**|**INPUT**<br>VREF_2|**I/O**<br>L12N_2|**GND**|**I/O**<br>L17N_2<br>VS2|**I/O**<br>L25P_2<br>GCLK12|
||**I/O**<br>L60P_3|VCCO_3|**INPUT**<br>L62P_3|**INPUT**<br>L62N_3|VCCAUX|**INPUT**<br>VREF_2|**I/O**<br>L14N_2|VCCO_2|**I/O**<br>L15P_2|**INPUT**<br>VREF_2|VCCAUX|**I/O**<br>L21P_2|**INPUT**|
||**I/O**<br>L60N_3|**I/O**<br>L64P_3|**I/O**<br>L64N_3|**I/O**<br>L01P_2<br>M1|**N.C.**|**I/O**<br>L08P_2|**INPUT**|**I/O**<br>L14P_2|**I/O**<br>L15N_2|**INPUT**<br>VREF_2|**I/O**<br>L23N_2|**I/O**<br>L21N_2|**INPUT**|
||**I/O**<br>L65P_3|**I/O**<br>L65N_3|**GND**|**I/O**<br>L01N_2<br>M0|**N.C.**|**I/O**<br>L08N_2|**I/O**<br>L11P_2|**GND**|**INPUT**|**INPUT**|**I/O**<br>L23P_2|**INPUT**<br>VREF_2|**GND**|
||**INPUT**<br>L66P_3|**INPUT**<br>L66N_3<br>VREF_3|**I/O**<br>L06P_2|**I/O**<br>L07P_2|VCCO_2|**I/O**<br>L10N_2|**I/O**<br>L11N_2|**I/O**<br>L18P_2|**I/O**<br>L19P_2<br>VS1|**I/O**<br>L22P_2<br>D7|VCCO_2|**I/O**<br>L24N_2<br>D4|**I/O**<br>L26N_2<br>GCLK15|
||**GND**|**INPUT**|**I/O**<br>L06N_2|**I/O**<br>L07N_2|**I/O**<br>L10P_2|**GND**|**INPUT**|**I/O**<br>L18N_2|**I/O**<br>L19N_2<br>VS0|**I/O**<br>L22N_2<br>D6|**GND**|**I/O**<br>L24P_2<br>D5|**I/O**<br>L26P_2<br>GCLK14|



**==> picture [157 x 10] intentionally omitted <==**

**----- Start of picture text -----**<br>
Bank 2<br>DS557-4_07_032309<br>**----- End of picture text -----**<br>


_Figure 24:_ **FGG676 Package Footprint (Top View)** 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

120 

**Spartan-3AN FPGA Family: Pinout Descriptions** 

|**14**|**15**|**16**|**17**|**18**<br>**19**<br>**Bank 0**|**18**<br>**19**<br>**Bank 0**|**20**|**21**|**22**|**23**|**24**|**25**|**26**<br>**GND**<br>**A**<br>**INPUT**<br>L65P_1<br>VREF_1<br>**B**<br>**I/O**<br>L63P_1<br>A22<br>**C**<br>**I/O**<br>L60N_1<br>**D**<br>**I/O**<br>L60P_1<br>**E**<br>**GND**<br>**F**<br>**INPUT**<br>L52P_1<br>**G**<br>**INPUT**<br>L44P_1<br>VREF_1<br>**H**<br>**I/O**<br>L43P_1<br>A18<br>**J**<br>**I/O**<br>L41N_1<br>**K**<br>**GND**<br>**L**<br>**I/O**<br>L35P_1<br>A10<br>**M**<br>**INPUT**<br>L32P_1<br>**N**<br>**I/O**<br>L31P_1<br>RHCLK2<br>**P**<br>**I/O**<br>L29N_1<br>A9<br>**R**<br>**GND**<br>**T**<br>**INPUT**<br>L24N_1<br>VREF_1<br>**U**<br>**INPUT**<br>L20N_1<br>VREF_1<br>**V**<br>**INPUT**<br>L20P_1<br>**W**<br>**INPUT**<br>L16N_1<br>**Y**<br>**GND**<br>**A**<br>**A**<br>**I/O**<br>L06N_1<br>**A**<br>**B**<br>**I/O**<br>L06P_1<br>**A**<br>**C**<br>**I/O**<br>L05P_1<br>**A**<br>**D**<br>**I/O**<br>L02P_1<br>LDC1<br>**A**<br>**E**<br>**GND**<br>**A**<br>**F**<br>**Bank 1**<br>DS557-4_08_030911|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**I/O**<br>L26N_0<br>GCLK7|**I/O**<br>L23N_0|**GND**|**INPUT**|**I/O**<br>L18N_0|**I/O**<br>L15N_0|**I/O**<br>L14N_0|**GND**|**I/O**<br>L07N_0|**INPUT**|**N.C.**|**TCK**|**GND**|
|**I/O**<br>L26P_0<br>GCLK6|**I/O**<br>L23P_0|VCCO_0|**I/O**<br>L19N_0|**I/O**<br>L18P_0|**I/O**<br>L15P_0|**I/O**<br>L14P_0<br>VREF_0|**I/O**<br>L09N_0|VCCO_0|**I/O**<br>L07P_0|**N.C.**|**INPUT**<br>L65N_1|**INPUT**<br>L65P_1<br>VREF_1|
|**GND**|**I/O**<br>L22N_0|**I/O**<br>L21N_0|**I/O**<br>L19P_0|**I/O**<br>L17N_0|**GND**|**I/O**<br>L11N_0|**I/O**<br>L09P_0|**I/O**<br>L05N_0|**I/O**<br>L06N_0|**GND**|**I/O**<br>L63N_1<br>A23|**I/O**<br>L63P_1<br>A22|
|**INPUT**<br>VREF_0|**INPUT**|**I/O**<br>L22P_0|**I/O**<br>L21P_0|**I/O**<br>L17P_0|**INPUT**|**I/O**<br>L11P_0|**I/O**<br>L10N_0|**I/O**<br>L05P_0|**I/O**<br>L06P_0|**I/O**<br>L61N_1|**I/O**<br>L61P_1|**I/O**<br>L60N_1|
|**I/O**<br>L24P_0|**I/O**<br>L20N_0<br>VREF_0|VCCAUX|**I/O**<br>L13N_0|**INPUT**|VCCO_0|**INPUT**|**I/O**<br>L10P_0|VCCAUX|**TDO**|**I/O**<br>L56P_1|VCCO_1|**I/O**<br>L60P_1|
|**I/O**<br>L24N_0|**I/O**<br>L20P_0|**GND**|**I/O**<br>L13P_0|**N.C.**|**I/O**<br>L02N_0|**I/O**<br>L01N_0|**GND**|**I/O**<br>L58P_1<br>VREF_1|**I/O**<br>L56N_1|**I/O**<br>L54N_1|**I/O**<br>L54P_1|**GND**|
|**INPUT**|**I/O**<br>L16P_0|**INPUT**|**I/O**<br>L08N_0|**N.C.**|**I/O**<br>L02P_0<br>VREF_0|**I/O**<br>L01P_0|**I/O**<br>L64N_1<br>A25|**I/O**<br>L58N_1|**I/O**<br>L51P_1|**I/O**<br>L51N_1|**INPUT**<br>L52N_1<br>VREF_1|**INPUT**<br>L52P_1|
|**GND**|**I/O**<br>L16N_0|VCCO_0|**I/O**<br>L08P_0|**INPUT**|**GND**|**I/O**<br>L64P_1<br>A24|**I/O**<br>L62N_1<br>A21|VCCO_1|**INPUT**<br>L48P_1|**INPUT**<br>L48N_1|**INPUT**<br>L44N_1|**INPUT**<br>L44P_1<br>VREF_1|
|**I/O**<br>L25N_0<br>GCLK5|**INPUT**|**I/O**<br>L12P_0|**INPUT**<br>VREF_0|VCCAUX|**I/O**<br>L59P_1|**I/O**<br>L59N_1|**I/O**<br>L62P_1<br>A20|**I/O**<br>L49N_1|**I/O**<br>L49P_1|**GND**|**I/O**<br>L43N_1<br>A19|**I/O**<br>L43P_1<br>A18|
|**I/O**<br>L25P_0<br>GCLK4|**VCCINT**|**I/O**<br>L12N_0|**GND**|**I/O**<br>L57N_1|**I/O**<br>L57P_1|**I/O**<br>L53N_1|**I/O**<br>L50N_1|**I/O**<br>L46N_1|**I/O**<br>L46P_1|**INPUT**<br>L40P_1|**I/O**<br>L41P_1|**I/O**<br>L41N_1|
|**VCCINT**|**GND**|**VCCINT**|**I/O**<br>L55N_1|**I/O**<br>L55P_1|VCCO_1|**I/O**<br>L53P_1|**GND**|**I/O**<br>L50P_1|**INPUT**<br>L40N_1|**I/O**<br>L38P_1<br>A12|VCCO_1|**GND**|
|**GND**|**VCCINT**|**GND**|**VCCINT**|**I/O**<br>L47N_1|**I/O**<br>L47P_1|**I/O**<br>L42N_1<br>A17|**I/O**<br>L45P_1|**I/O**<br>L45N_1|**I/O**<br>L38N_1<br>A13|**INPUT**<br>L36P_1<br>VREF_1|**I/O**<br>L35N_1<br>A11|**I/O**<br>L35P_1<br>A10|
|**VCCINT**|**GND**|**VCCINT**|**I/O**<br>L39N_1<br>A15|**I/O**<br>L39P_1<br>A14|**I/O**<br>L34N_1<br>RHCLK7|**I/O**<br>L42P_1<br>A16|**I/O**<br>L37N_1|VCCO_1|**INPUT**<br>L36N_1|**I/O**<br>L33N_1<br>RHCLK5|**INPUT**<br>L32N_1|**INPUT**<br>L32P_1|
|**VCCINT **|**VCCINT**|**GND**|VCCAUX|**I/O**<br>L34P_1<br>IRDY1<br>RHCLK6|**GND**|**I/O**<br>L30N_1<br>RHCLK1|**I/O**<br>L30P_1<br>RHCLK0|**I/O**<br>L37P_1|**I/O**<br>L33P_1<br>RHCLK4|**GND**|**I/O**<br>L31N_1<br>TRDY1<br>RHCLK3|**I/O**<br>L31P_1<br>RHCLK2|
|**VCCINT**|**GND**|**VCCINT**|**I/O**<br>L27N_1<br>A7|**I/O**<br>L27P_1<br>A6|**I/O**<br>L22P_1|**I/O**<br>L22N_1|**I/O**<br>L25P_1<br>A2|**I/O**<br>L25N_1<br>A3|**INPUT**<br>L28P_1<br>VREF_1|**INPUT**<br>L28N_1|**I/O**<br>L29P_1<br>A8|**I/O**<br>L29N_1<br>A9|
|**GND**|**VCCINT**|**GND**|**I/O**<br>L17N_1|**I/O**<br>L17P_1|VCCO_1|**I/O**<br>L14N_1|**GND**|VCCAUX|**I/O**<br>L26P_1<br>A4|**I/O**<br>L26N_1<br>A5|VCCO_1|**GND**|
|VCCAUX|**I/O**<br>L35N_2|**I/O**<br>L42N_2|**GND**|**I/O**<br>L12N_1|**I/O**<br>L12P_1|**I/O**<br>L10N_1|**I/O**<br>L14P_1|**I/O**<br>L21N_1|**I/O**<br>L23P_1|**I/O**<br>L23N_1<br>VREF_1|**INPUT**<br>L24P_1|**INPUT**<br>L24N_1<br>VREF_1|
|**I/O**<br>L31P_2|**I/O**<br>L35P_2|**I/O**<br>L42P_2|**I/O**<br>L46N_2|**I/O**<br>L08P_1|**I/O**<br>L08N_1|**SUSPEND**|**I/O**<br>L10P_1|**I/O**<br>L18N_1|**I/O**<br>L21P_1|**I/O**<br>L19P_1|**I/O**<br>L19N_1|**INPUT**<br>L20N_1<br>VREF_1|
|**GND**|**I/O**<br>L31N_2|VCCO_2|**I/O**<br>L46P_2|**N.C.**|**GND**|**I/O**<br>L04P_1|**I/O**<br>L04N_1|VCCO_1|**I/O**<br>L18P_1|**GND**|**INPUT**<br>L16P_1|**INPUT**<br>L20P_1|
|**I/O**<br>L27P_2<br>GCLK0|**I/O**<br>L34N_2<br>D3|**INPUT**<br>VREF_2|**I/O**<br>L43N_2|**N.C.**|**N.C.**|**I/O**<br>L01P_1<br>HDC|**I/O**<br>L01N_1<br>LDC2|**I/O**<br>L13P_1|**I/O**<br>L13N_1|**I/O**<br>L15P_1|**I/O**<br>L15N_1|**INPUT**<br>L16N_1|
|**I/O**<br>L27N_2<br>GCLK1|**I/O**<br>L34P_2<br>INIT_B|**GND**|**I/O**<br>L43P_2|**I/O**<br>L47N_2|**INPUT**|**INPUT**<br>VREF_2|**GND**|**I/O**<br>L09P_1|**I/O**<br>L09N_1|**I/O**<br>L11P_1|**I/O**<br>L11N_1|**GND**|
|VCCO_2|**I/O**<br>L30N_2<br>MOSI<br>CSI_B|**I/O**<br>L38N_2|**INPUT**|**I/O**<br>L47P_2|VCCO_2|**INPUT**|**DONE**|VCCAUX|**I/O**<br>L07P_1|**I/O**<br>L07N_1<br>VREF_1|VCCO_1|**I/O**<br>L06N_1|
|**I/O**<br>L29N_2|**I/O**<br>L30P_2|**I/O**<br>L38P_2|**INPUT**|**INPUT**|**I/O**<br>L40N_2|**I/O**<br>L41N_2|**I/O**<br>L45N_2|**N.C.**|**I/O**<br>L03P_1<br>A0|**I/O**<br>L03N_1<br>A1|**I/O**<br>L05N_1|**I/O**<br>L06P_1|
|**I/O**<br>L29P_2|**I/O**<br>L32P_2<br>AWAKE|**INPUT**|**I/O**<br>L33N_2|**GND**|**I/O**<br>L40P_2|**I/O**<br>L41P_2|**I/O**<br>L44N_2|**I/O**<br>L45P_2|**N.C.**|**GND**|**I/O**<br>L02N_1<br>LDC0|**I/O**<br>L05P_1|
|**I/O**<br>L28N_2<br>GCLK3|**I/O**<br>L32N_2<br>DOUT|VCCO_2|**I/O**<br>L33P_2|**I/O**<br>L36N_2<br>D1|**I/O**<br>L37N_2|**I/O**<br>L39N_2|**I/O**<br>L44P_2|VCCO_2|**I/O**<br>L48N_2|**I/O**<br>L52N_2<br>CCLK|**I/O**<br>L51N_2|**I/O**<br>L02P_1<br>LDC1|
|**I/O**<br>L28P_2<br>GCLK2|**INPUT**<br>VREF_2|**GND**|**INPUT**<br>VREF_2|**I/O**<br>L36P_2<br>D2|**I/O**<br>L37P_2|**I/O**<br>L39P_2|**GND**|**INPUT**<br>VREF_2|**I/O**<br>L48P_2|**I/O**<br>L52P_2<br>D0<br>DIN/MISO|**I/O**<br>L51P_2|**GND**|
||||||**Bank 2**||||||||



## **Right Half of FGG676 Package (Top View)** 

_Figure 24:_ **FGG676 Package Footprint (Top View)** 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

121 

**Spartan-3AN FPGA Family: Pinout Descriptions** 

## **Revision History** 

The following table shows the revision history for this document. 

|**Date**|**Version**|**Revision**|
|---|---|---|
|02/26/2007|1.0|Initial release.|
|08/16/2007|2.0|Updated for Production release of initial device. Noted that family is available in Pb-free packages only.|
|09/12/2007|2.0.1|Minor updates to text.|
|09/24/2007|2.1|Update thermal characteristics inTable 67.|
|12/12/2007|3.0|Updated to Production status with Production release of final family member, XC3S50AN. Noted that<br>non-Pb-free packages may be available for selected devices. Updated thermal characteristics in<br>Table 67. Updated links.|
|06/02/2008|3.1|AddPackage Overviewsection. Removed VREF and INPUT designations and diamond symbols on<br>unconnected N.C. pins for XC3S700AN FGG484 inTable 78andFigure 22and for XC3S1400AN<br>FGG676 inTable 82andFigure 23.|
|11/19/2009|3.2|Renamed package ‘Footprint Area’ to ‘Body Area’ throughout document. Noted inIntroductionthat<br>references to Pb-free package code also apply to the Pb package. Added Pb packages toTable 65and<br>Table 66. Changed Body Area of TQ144/TQG144 packages inTable 65. Corrected bank designation<br>for SUSPEND to VCCAUX. Noted that non-Pb-free (Pb) packages are available for selected devices.<br>UpdatedTable 79andFigure 22for I/O vs. Input pin counts.|
|12/02/2010|4.0|UpgradedNotice of Disclaimer.|
|04/01/2011|4.1|Updated the CLK description inTable 62. InTable 64, added device/package combinations for the<br>XC3S50AN and XC3S400AN in the FT(G)256 package and the XC3S1400AN in the FG(G)484<br>package. InTable 65, updated the maximum I/Os for the FG484/FGG484 packages, removed the<br>Mass column, and updated Note 1. InTable 65, changed the FTG256 link from PK115_FTG256<br>,<br>FGG676 link from PK111_FGG676<br>,and the TQG144 link from PK126_TQG144<br>.Completely replaced<br>the sectionFTG256: 256-Ball Fine-Pitch, Thin Ball Grid Arraywith new information on the added<br>device/package combinations and new figures and tables. Revised U16, U7, and T8 inTable 78. Added<br>Table 80andTable 81and updatedFigure 23.|
|06/11/2014|4.2|Xilinx has issued a discontinuation notice for the XC3S50AN in the FT(G)256 package and the<br>XC3S1400AN in the FG(G)484 package. SeeXCN13016<br>: _Product Discontinuation Notice For_<br>_Selected Spartan-3AN FPGA Products_. This customer notice is highlighted inTable 64with the<br>addition ofNote 2andTable 67with the addition ofNote 3. TheFTG256: 256-Ball Fine-Pitch, Thin Ball<br>Grid Array, page 79andFGG484: 484-Ball Fine-Pitch Ball Grid Array, page 100package sections have<br>been updated due to this discontinuation notice including addingNote 1toTable 71,Note 1to<br>Table 73,Note 1toTable 74,Note 1toTable 75, and a note aboveFTG256 Footprint (XC3S50AN)<br>Figure 20. TheFGG484: 484-Ball Fine-Pitch Ball Grid Array, page 100section is also updated with<br>links to the customer notice including addingNote 1toTable 80andNote 1toTable 81.<br>Also added data toTable 67for the XC3S400AN in the FTG676 package.<br>UpdatedNotice of Disclaimer.|



DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

122 

**Spartan-3AN FPGA Family: Pinout Descriptions** 

## **Notice of Disclaimer** 

The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of Xilinx’s limited warranty, please refer to Xilinx’s Terms of Sale which can be viewed at www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in such critical applications, please refer to Xilinx’s Terms of Sale which can be viewed at www.xilinx.com/legal.htm#tos. 

## **AUTOMOTIVE APPLICATIONS DISCLAIMER** 

XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III) USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN SUCH APPLICATIONS. 

DS557 (v4.2) June 12, 2014 **Product Specification** 

www.xilinx.com 

123
Updated at June 5, 2026
About Novapart

Novapart is a B2B electronic component broker specialising in stock shortages and cost reduction. We source hard-to-find parts and identify compliant alternatives across a catalogue of 410,000+ components from 500+ manufacturers.
Learn more →
Stock Shortage Specialist

When a component is unavailable, discontinued or has an unacceptable lead time, we tap into our network of vetted European and Asian distributors to source what you need — without compromising on quality or traceability.
Request a quote →
Compliant Alternatives

We identify pin-to-pin, electrically equivalent substitutes that meet the same certifications (RoHS, AEC-Q100, REACH) as your original specification — validated against datasheets, not just part numbers. Often at a lower cost.
BOM Analysis service →