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WFI32E01PE-I
WLAN Module, PCB Antenna, 2.5 GHz
⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
- Manufacturer: MICROCHIP
- Product type:
- SVHC: No SVHC (04-Feb-2026)
- Frequency RF: 2.5GHz
- Product Range: WFI32E01 Series
- Module Interface: CAN, CAN-FD, I2C, I2S, JTAG, SPI, SQI, UART, USB
- Module Applications: Radio, RF Communications, Wireless Connectivity WiFi
| Delivery and price | |
|---|---|
| Units per pack | 250 |
| Price | 4.41 € |
| Current stock | 10+ |
| Lead time | 30 days |
Datasheet
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S®<br>MICROCHIP<br>**----- End of picture text -----**<br>
## PIC32MZ W1 and WFI32E01 Family
## Del
## PIC32MZ1025W104 MCU and WFI32E01 Module with Wi-Fi® and Hardware-based Security Accelerator Data Sheet
## a
- INTRODUCTION - Four 64-bit accumulators . .
- The - Single-cycle MAC, saturating and fractional math is a generalPIC32MZpurpose, W1 Familylow-cost, (PIC32MZ1025W32-bit Microcontroller104132 devices)(MCU) « Kiadi:olfisienidisccrdicossendGhgrandfibectane with the Wi-Fi and network connectivity, hardware-based On-Chip Flash and SRAM security accelerator, transceiver and Power ManagementUnit * 1 MB Flash Program Memory (PMU). It supports interface to an External Front-End Module. * 64 KB Boot Program Flash The WFI32E01 is a fully RF certified wireless module that con* 256 KB SRAM (Program and Data) tains the PIC32MZ1025W104 SoC and an integrated Front¢ 64 KB Data Buffer (DBF) end Module (FEM) with following antenna options: * Dedicated Buffer for Peripherals * PCB Antenna (WFI32E01PC/WFI32E01PE) Power Management and System Recovery ¢ U.FL Connector (WFI32E01UC/WFI32E01UE) for External * Low-Power Modes (Dream and Sleep) Antenna + Integrated Power-on Reset (POR) and Brown-out Reset
- The PIC32MZ W1 Family supports rich set of standard PIC32 (BOR) peripherals such as Wi-Fi, Ethernet MAC, USB, CAN, CAN* Secondary Oscillator and Fail Safe Clock Switch FD, SPI, I?C, SQI, UART and JTAG. ¢ Fast Power-up and Brown-out Recovery TCP/IP based connectivity protocols along with SSL support Security enables a low-cost, low complexity system to obtain full-featured internet connectivity and reliable information exchange. * Hardware Accelerated Security Modes (with Built-in DMA Support)
- x
- PIC32MZ W1 Family FEATURES * CryptoTeEngine in Data with Encryption/decryption True Random Numberand Generator Authentication The following section lists the PIC32MZ1025W104 related (AGS, BES Shs Mls ane MAD) features. > AES Modes: .
- Wireless Interfaces - Electronic Codebook (ECB) - Cypher Block Chaining (CBC)
- * PHY: - Counter Mode (CTR)
- - ae ane b/g/n WLAN link - Cypher Feedback Mode (CFB) - Single spatial stream of 20 MHz crane! bandwidth - Output Feedback Mode (OFB) - External FEM support for Power Amplifier (PA), Low - Galois/Counter Mode (GCM) ae LED, WebsiteRES SREPey ¢ Hardware Accelerated Public Key Cryptography with Support for:
- - 2.4 GHz (2400 ~ 2483.5 MHz) ISM band =a : ;
- a ; -- 256-bit16-DSPECC/ECDH/ECDSA/Curve25519multipliers configuration - Infrastructure BSS luis rental - 256-bit Ed25519 ~ Seft-AP mosie functionality - 512-bit ECC/ECDH/ECDSA generation - Active and passive scanning - Transmit power control support over temperature and Clock Management voltage * 40 MHz Primary Oscillator (POSC)
- * Security: * 32.768 kHz Secondary Oscillator (SOSC) - WPA3 personal (SAE and PMF-802.11w) * Power-up Timer (PWRT) and Oscillator Start-up Timer - WPA2 personal, with options for WPA compatibility and (OST) PMF * Programmable PLLs and Oscillator Clock Sources
- - WEP * Fail-Safe Clock Monitor (FSCM)
- * Harmony Networking: * On-chip Clock Sources: - Out of box support for MPLAB® Harmony v3 TCP/IP - 8 MHz Fast RC (FRC) oscillator Stack - 32.768 kHz Low-Power RC (LPRC) oscillator
- - TLS v1.2 with symmetric/asymmetric crypto * Programmable PLLs and Oscillator Clock Sources acceleration ¢ Independent Watchdog Timer (WDT) and Deadman Timer
- 200 MHz, MIPS32® M-Class Microprocessor Core (DMT) » 16 KB I-Cache, 16 KB D-Cache * Gast ake-op aid Saat up + Fixed Mapping Translation (FMT) based MMU for * Support for Precise Reference Clocks to External Devices Optimum Embedded OS Execution
- * microMIPS™ Mode for Up to 35% Smaller Code Size * DSP-enhanced Core: eee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 1
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PIC32MZ W1 and WFI32E01 Family<br>seman<br>Direct Memory Access (DMA) Software and Tools Support<br>* Eight Channels with Automatic Data Size Detection * C/C++ Compiler with Native DSP/fractional<br>* Programmable 32-bit Cyclic Redundancy Check (CRC) + MPLAB™ Harmony Integrated Software Framework:<br>7 . cae<br>Advanced Analog Vid Aedoa and mTouch™ Middleware<br>* eee eee Bros— Express Logic ThreadX, FreeRTOS™<br>- 2 MSPS with two Sample and Hold (S&H) circuits (one OPENRTOS®, Micriym® uC/OS™ and SEGGER<br>dedicated and one shared) embos®<br>- Unitaetanelegins + Supports Over-the-Air (OTA) and Over-the-Host (OTH)<br>- Sleep and Idle mode operations Firmware Update Modes<br>- Multiple trigger sources Pack do ti Conditi<br>- Two digital comparators and two digital filters acKkage an perauing Conditions<br>- Supports Touch Interface a PaESSDE:<br>- Size-10x10x0.9mm<br>Cc ommunication- 20 Analogicati Channelssitetintertaces - 132-pin DQFN<br>* Operating conditions:<br>* Up to Two CAN Modules (CAN and CAN-FD) - 2.97V to 3.63V, -40°C to +105°C, DC to 200 MHz<br>- 2.0B Active with DeviceNet™ addressing support<br>¢ IEEE 1588 Precision Time Protocol (PTP)<br>¢ Up to Three UART Modules (10 Mbps): WFI32E01 MODULE FEATURES<br>- Supports RS-232, RS-485, LIN 2.1 and IrDA Protocols The following section lists the WFI32E01 module related fea-<br>* One Ethernet MAC Module (10/100 Mbps) with RMII Inter- tures, , which complements SoC features.<br>face and Dedicated DMA:<br>- Time synchronization support between Wi-Fi and Antneed Onti“Pp sons<br>Ethernet ¢ PCB Antenna Variants:<br>¢ Up to Two SPI (one 4-wire, one 3-wire) Modules with - WFI32E01PC<br>Speed up to 40 MHz - WFI32E01PE<br>* SQlI Configurable as an Additional SPI Module (40 MHz) * External Antenna Variants:<br>* One Full-Speed USB 2.0 OTG Interface with Dedicated - WFI32E01UC<br>DMA - WFI32E01UE<br>* Two I2C Modules (Up to 1 Mbaud) with SMBus Support Wireless Feature<br>Timers/Output Compare/Input Capture * On-board FEM/PA to Meet the TX Power Requirements<br>¢ Seven 16-bit or up to Three 32-bit Timers/Counters Security<br>* Four Output Compare (OC) Modules * Integrated Trust&GO<br>¢ Four Input Capture (IC) Modules Clock Management<br>* Low-power Precision Real-Time Clock and Calendar » Integrated 40 MHz POSC<br>(RTCC)<br>Input/Output Aevanesd ae<br>+ High Current Source/Sink (up to 25 mA) on All I/O Pins nalog “nanne's<br>* Configurable Open-Drain, Pull-up, Pull-down and Slew Input/Output<br>Rate Controls * 37 GPIO Pins<br>¢ External interrupts on all I/O Pins Package and Operating Conditions<br>* Peripheral Pin Select (PPS) to Enable Function Remap * Package:<br>* 64 GPIO Pins - 54-pin SMD package with Shield CAN<br>Peripheral Trigger Generator (PTG) - Size - 24.5 x 20.5x 2.5mm<br>* PTG with 8-bit User Command for Scheduling Complex * Operating conditions:<br>Sequences - 3.0V to 3.6V, -40°C to +85°C, DC to 200 MHz<br>Qualification and Class B Support Certifications<br>* Class B Safety Library, IEC 60730 ¢ WFI32E01 Module Certified to FCC, ISED and CE Radio<br>Debugger Development Support Regulations ;<br>¢ In-circuit and In-application Programming * RoHS and REACH Compliant<br>+ 4-wire MIPS® Enhanced JTAG Interface<br>¢ Unlimited Software, 8 Instruction and 4 Data Complex<br>Hardware Breakpoints<br>¢ IEEE 1149.2-Compatible (JTAG) Boundary Scan<br>¢ iFlowtrace functionality support:<br>- Off-chip Buffering of iFlowTrace Messages<br>**----- End of picture text -----**<br>
renner eee e rereerence eee eee DS70005425A-page 2 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
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ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 3
PIC32MZ W1 and WFI32E01 Family
## seman
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TABLE 3: PIN NAMES FOR 132-PIN PIC32MZ1025W104 SoC<br>**----- End of picture text -----**<br>
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132-PIN DQFN (TOP AND BOTTOM VIEW)<br>**----- End of picture text -----**<br>
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A72 Al<br>=<br>B60 =, B1<br>2yo3 “ee%es<br>,miR<br>%C<br>ve, mx<br>SAbs 2<br>OOOCOCOOCOCOCCSY<br>es 1OCB1/RB1<br>**----- End of picture text -----**<br>
Note 1: The RPn pins can be used by re-mappable peripherals. Refer to Section 13.4 “Peripheral Pin Select (PPS)” for details.
- 2: Every I/O port pin (RAX-RKx) can be used as a change notification pin (CNAx-CNKx). See 13.0 “I/O Ports” for more information. 3: Shaded pins are 5V tolerant.
- 4: Do not use Buck/MLDO output to drive any other device.
- 5: A58 and A59 pins can be configured as GPI as an alternate function.
- 6: Exact connection for each pin is available in the reference design package. Contact the Microchip Sales/Support Team for the package.
eee eee Preliminary Data Sheet © 2020 Microchip Technology Inc.
renner eee e rereerence DS70005425A-page 4
PIC32MZ W1 and WFI32E01 Family
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smn<br>**----- End of picture text -----**<br>
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**----- Start of picture text -----**<br>
TABLE 3: PIN NAMES FOR 132-PIN PIC32MZ1025W104 SoC<br>132-PIN DQFN (TOP AND BOTTOM VIEW)<br>A72 Al<br>B60 ms B1<br>wySo—“%ees<br>, mx<br>0, eX<br>ey, ee<br>x ‘oy AY 4<br>ae ferent an emmnw<br>AM [BUKBKIXTSCiBDSINCTT<br>[ao [SQICSCICVDTI7IRPADIOCAORAD=|<br>lso___[SabvovorzimPcenoccamcs<br>|<br>**----- End of picture text -----**<br>
- Note 1: |The RPn pins can be used by re-mappable peripherals. Refer to Section 13.4 “Peripheral Pin Select (PPS)” for details. 2: Every I/O port pin (RAX-RKx) can be used as a change notification pin (CNAx-CNKx). See 13.0 “I/O Ports” for more information. 3: Shaded pins are 5V tolerant.
- 4: Do not use Buck/MLDO output to drive any other device.
- 5: A58 and A59 pins can be configured as GPI as an alternate function.
- 6: Exact connection for each pin is available in the reference design package. Contact the Microchip Sales/Support Team for the package.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 5
|PIC32MZW1 and WFI32E01 Family||
|---|---|
|seman||
|Table of Contents||
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|1.0 Ordering INfOrMatiON «0.0...<br>eeeeececcceeeeeeeeeeeeeeseeneeeeeceeeeeaaeaaaeeeeeeseseeeceseeeeaeeeeeeeeeeeaeeeeeeeeeeceeeeeeeeeeeeaeeeseseeeeeteeeeeesesettteesesesseesseeeee|11|
|2.0 PIC32MZ1025W104 SoC DeSCription ..............ccescceecceeeeeceeeeececseceeeecaeeceececseecaeecaeecseeceaeeeseeceaeseseeeneeseaeseseseaeseeeeseesetetstetereeeeee|13|
|3.0 WFI32E01 Module DeSCription<br>..........cccccccccccecccceececeeeeeeeeeeeeeeeeeeeeeceaeeeeeeeeececeeeeeeeeececeeeeeeeceeececececececeeececececceesececececeeeeececeteeeesessseessee|2D|
|5.0 Flash Program Memory ............:cccccsseccesseeeeeseeceeseeeceeeecesueceeaeeeesaeeecsseeecesueeecaeeeesaeeeesseeeseeeesecseecessaeeseeseeeeseeesesseeesstteeessteeesssstteees|OL|
|BiO\MEMOFY ORGANIZATION:<br>up c.cts ieee cobbeaiioreesctbalbeclionnnsssbebbeubiorsnesscscieenecsnelbechsoeneensbietberblaenssecssebbechsseserssbuetberbterssecsseblechioeseccnseree|Lil|
|PIONRCS CESS<br>ser cccr ceeees eesti re<br>raceme ect ares ara trae eR<br>Sr<br>a<br>a Rr<br>a Earner<br>ETE aerearueairae OM||
|B.0'CPU Exceptions aind INTE ilipt COntOUe? .W.2....dccscercecencsoihecntoneechasebebharneonenarsiebubbansendisentoneisenesenhecneenensentvenbscnnennesesnvetsseneeneeseeneens|1D|
|9.0 Prefetch MOdule ...........cccccccesceceseseeeeeeeeeeeseeeeseneeeesenecesaeeeceeeceeaeecaeeeeesaeeseueeesesaeees eeaeeeseeesecaeeeseeeeseeaeeseeaeeeeeseeeesseeesttsetstteeeeeeses|13D|
|10.0 Direct Memory Access (DMA) Controller<br>..........ccccccccecceessecesseeeceeeeeseeeceaececnseeecsceueeeesseeeesaeesseaeeeeseeeesssaeeeeseeeesssseessseeeessteeesees|1414|
|11.0 Oscillator CONfIQguration .......... ccc cecccccesseeeesseecesseeeesseeecssaeecesaeecseeeceeesseeecaeeecssaeecesaeeeesseeecesaeeeeseeesesseeseseeeessseeetseeessseessstteees|105|
|1210) PUESPeed USB OnaMNS=6Gi (OMG) esti eset ccstnied ibsedat cock<br>aie Bd aha wietadel Hcl beaten Uae beta<br>ha wate oe|ABT.|
|13.0 WO Ports<br>2.2... ccecceecceeecceeceeeceeeseecenecsneceaeecseeceaeccaeecacecsaaeccaeeesaesaeecsecscecsaeecaeesaeeseaeeaasesneseaeeeseeseaseeaseceaeeeaeeseeseaeeeeereeeteetesseeeteeteees|213|
|14.0 Peripheral Trigger Generator (PTG)<br>.......ceeececceeeccessceceenseeeeeaeeceeeeeessaeecenaeeesesaeeeeaeesessueesseaeeeceaeesseaeesseeeeessseeessseeesseesssseesees<br>249||
|RUSSONU<br>TUN re rr<br>sm<br>rs<br>OO<br>roe aereeseaer eae|OO|
|16.0 Timer2/3, Timer4/5, ANd Time r6/7 ........ cece cccccceeeeeccccccceesescecccececsecssssecccessusesseecseseeccccseuusecccessuueseecccesseueecccssssssecccssssseeceessseseees|21D|
|FAA) ES AATRAPA TATA (CTIA)hse crc SIR at<br>ask ASSaidccd NE<br>on GESE<br>ck<br>SSEI<br>RE a<br>i|wa|
|18:0 Watchdog Timer (WDD)! sss<br>eraser rane eeieenneni eee eenEE:|ZO|
|ASLO<br>nput Capture: scenesseranmareenwsereecien ey varnenenene varmeneeeimne rae eran esee reneeernie|DOO|
|20:0 Output! Compare sssexzesseevcvesssereressarsereesensresseenscenseausseceseereea<br>eresnetiarucneuiansceeeewEees eeereset Eres erateeaes TeeseeeTENCE TET:ZOD<br>21.0 Serial Peripheral Interface (SPI) and Inter-IC Sound (I2S) sisruraueesonmueseouneea mmeuuee reaceeeeeeectiermenireed ZOE||
|22.0 Serial|\Quad Interface (SOI) wreceecwe: cee esaserry ey arveee eye yeeeeeeueeetear eeee urayeee aeerate peteoe eee ures coat even eEEreer:|CON|
|23.0 Inter-Integrated Circuit (I2C) 1s eee a ere os ermeene<br>ee oe ane te eto cee<br>eeae tueota<br>et eer<br>a eenoe eee eee|ODO|
|25.0 Real-Time Clock and Calendar (RTCC) ............cccccccssscccceeeeeeneeeceeeeeeneeeeeeeeesnaaeeeeeceseeeaeeceeeecseaaeeeesesesseeeeseesessssteeeeeeesssstteeeeeees|OAT|
|26.0 Asymmetric Crypto Engine ...............cccccccccssssseeceeeesssnaeseceessssnaneecensnessaeeeseceessueeeeeeeesssneseeeeeesescaeeeeeesesseceeeeeeessessneeeeesessssssscssseess|OOD|
|27.0 Symmetric Crypto Engine) ssssccressersccuveceurrosssruceucsrarsuveseurseursruy<br>cenavsraewersees pee erouewes exer reneseecevts preveueeurecresesreuseeeuressessueexecessmensmeceess|OOO|
|28:0 True Random'Number'Generator (TIRNG) ssccccevessuszvecsecesevsseusseseserneoesces<br>coveseneseeaeresreese Cots seesRRSeEEPORE BRR BRETT|OOO|
|29.0 12-bit High-Speed Successive Approximation Register (SAR)ADC ou.....eecececcceceessseeeesseeeeeeeeesseeecenseeeeeeeeessaeeeesseeessstseesssees|OG|
|30.0 Controller Area Network (CAN) ........::::cccccsssesseceeeeeeeeneenneeeeeeeeesaeeececenaeeeecececeneaeeeseeesceaaeeceesecennaaeeeeeeeseeeeeeseseessetteeeeeessssttetssteee|443|
|31.0 Controller Area Network-Flexible Data-Rate (CAN-FD) Module .00.............cecccceccccecessseeeeeeeeeeeseeeeeeeeeesseeeeeeeeeesessteeeeessessstteeeeeees|471|
|32.0 WI-FI Controller sssesesevsseusrssseneeeestorssersserseeessensvenisanennaion<br>tesseeseeesnges eeaeeeeeeaee niet eneeetssens eenseeeeeeeieReaeeeeee:O21|O21|
|33.0 Ethernet Controller ............ccccccccecsseceeseeeeseneeeeeneeeeeaeeeceaaeessaeeeesaeesceaeeceaeeeseaeecenseeeenaeeesenaeeseeaeeesenaeesseaeeseeaeesesaeeessteeetstseeseesttes|O2O|
|34.0 Enhanced Capacitive Voltage Divider (CVD) Controller ...........ccccccccccsscceeseseeeesseceesseeeceseeeeenaeeecseeecesaeeeseeeeesseeeeestseesstseessteees|DOD|
|35.0 Power Management<br>Unit(PMU) ...........cceeccccsseceesseecesseeeeeseeeceseecessseccesseeecssaeeceaueecesseeeeesseecesieeeesaeesecseecesseeesesseeeesteeeeesteeessssssDOO||
|36.0 Power-Saving Features ...............cccsssccccceessssnceeeeeecsssneneceeecessesssuseceesssanececeeseseaeeeeeeeessseaeeeececsssseaeseceeeesssceseceresessseeseeeesessssscesssseees|OO|
|37.0 Special Features oo...cccccccccccccsssseceeceeeeseneeeeeeeeseseeesaaeeeeeseeeeeeeceeeeaeeeeeeseeeeaeeeeeeeseneeaeeceeeeeseseaeeeeeseseseeeeeeseessssseeeeesssssttststeees|O13|
|ZBJOMMSUMICTON SEF<br>......-ncznekincthatherdienncastbbaltiesBhanceentthabhestieanenaneasnentthaiterdthsasnentbhatbectbenocesdbhettesthancnenchroMbacBhacecesdbbettenthesenenchnebtactheesseensanetiO29||
|39.0 Development SUPPOrt «0.0.0...ccccceececceeeseneeeeeeeeeeseaeeeeeeeecaaeeeecesaesasaeeeeeeeceseaeeeeeeseeseaeeececeeseceeeeeeeeeessseeeeeeeeeesetsseeesesssssttsssttees<br>OOT||
|40.0 Electrical Specifications<br>..............ccccccssssssccceeesssseeeceeesessneseceesesssaeecesceseessaeeeeeeeesesnaeseceeeessecaneeeeeesesseaeseeesesseseseeeeesessseseeeesssssessssss|OOO|
|41.0 Packaging INFOrmation<br>...........cceecccccccceeeneceeeeeeenneeeeeeeeceeeesaeeeeceecnseeeeeeeeaaaeeeeeeeceseaeeceseeseceeeeeeeseeeeeeaeeeeeeesesseeeeeesessssteeesessseessssss|OLD|
|Appendix A: Regulatory Approvals<br>...........ccccccccccccessseceeeeeeeeseeeeeneeeeeeeseseeceeseesaaeeeeeeseeseeeeeceeececeeeeeeeceesseeeeeeeeeesseseeeeeessssttseteesessesssssss<br>OOO||
|Appendix B: Document Revision History<br>..............ccccccccccceeceeeeseneeeeceeeeseeceeeeeeneeeeeeeeceeseeeeeeeeeceseeeeeeeeeeeseeeeeeeeeeseeseeeeeeessssttseeeesessssssesss|OOG|
|TNE: MIGFOCHIPNVED SHE...<br>ti ennnvensbabbechhenwnnrnibelilechbalilacthennseashballlaschhenateceballlesthennsenceballlanbeensneranbelbachhvennaesitelbechhenanascitalllesbienansccensae<br>OGM||
|Customer Change Notification SEPVICE<br>q................-0c.cc-nsereeennsernecnnsrerssenunsesenbarnecennansusenbannesnneansusnnbannesnnesnsnennannssensanenennsannesensaneseses|ODT|
|Customer SUPPOrt «0.0.0...cccceseeccceeesssseeeeceeeesseeeeecesesaueeeeceeeceeesuaueeecsaaueeecececsusuaeeeeecececseeeeeeseesesseeeeescesssseeeceseessstsseeseesessssseeesseesees|O91|
|WorldwideSalesandService<br>...............:csccseceseeesneeseeeseenesecensceescneenecseesseesesesenceseseeescenscenseceescensecenssenscesesesescesteesessensserseetesserseersesserss|OGD|
renner eee e rereerence eee eee DS70005425A-page 6 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family smn
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Referenced Sources ual”. These documents should be considered as the<br>This device data sheet is based on the following general reference for the operation of a particular mod-<br>individual sections of the “PIC32 Family Reference ule or device feature.<br>Manual” and “PIC32MZ W1 Family Reference Man-<br>browse the documentation section of the<br>Microchip website (www.microchip.com).<br>**----- End of picture text -----**<br>
- ¢ Section 5. “Flash Program Memory with Support for Live Update” (DS60001640) * Section 6. “Memory Organization and Permissions” (DS60001641)
- Section 7. “Resets” (DS60001118)
- Section 8. “Interrupts” (DS60001108)
- Section 9. “Prefetch Module for Devices with L1 CPU Cache” (DS60001649)
- Section 9. “Watchdog, Deadman, and Power-up Timers” (DS60001114)
- Section 10. “Power-Saving Modes” (DS60001130)
- Section 12. “I/O Ports” (DS60001120)
- ¢ Section 14. “Timers” (DS60001105)
- Section 15. “Input Capture” (DS60001122)
- * Section 16. “Output Compare” (DS60001111)
- Section 21. “UART” (DS60001107)
- Section 22. “12-bit High-Speed Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC)” (DS60001344)
- ¢ Section 23. “Serial Peripheral Interface (SPI)” (DS60001106) * Section 24. “Inter-Integrated Circuit (I2c)” (DS60001116)
- Section 27. “USB On-The-Go (OTG)” (DS61126)
- Section 29. “Real-Time Clock and Calendar (RTCC)” (DS60001125)
- * Section 31. “DMA Controller” (DS60001117) * Section 32. “Configuration” (DS60001124)
- Section 33. “Programming and Diagnostics” (DS60001129)
- Section 34. “Controller Area Network (CAN)” (DS60001154)
- ¢ Section 35. “Ethernet Controller” (DS60001155)
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- Section 42. “Oscillators with Enhanced PLL” (DS60001250)
- Section 46. “Serial Quad Interface (SQI)” (DS60001244)
- Section 49. “Crypto Engine and Random Number Generator (RNG)” (DS60001246)
- Section 50. “CPU for Devices with MIPS32® microAptiv™ and M-Class Cores” (DS60001192)
- Section 56. “Controller Area Network with Flexible Data-rate (CAN FD)” (DS60001549)
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## 1.0 ORDERING INFORMATION
This chapter provides the ordering information of the PIC32MZ1025W104 SoC and WFI32E01 module.
## 1.1 PIC32MZ1025W104 SoC Ordering Information
The following table describes the ordering information of the PIC32MZ1025W104 SoC.
TABLE 1-1: PIC32MZ1025W104 SOC ORDERING DETAILS
PIC32MZ1025W104 | 132-pin and DQFN | 32-bit MCU with Network Connec- |PIC32MZ1025W104132-V/NX (10x10x0.9 mm) tivity and Security Accelerator The following figure illustrates the details of PIC32MZ1025W104 SoC ordering information.
**==> picture [422 x 288] intentionally omitted <==**
**----- Start of picture text -----**<br>
FIGURE 1-1: PIC32MZ1025W104 SOC ORDERING INFORMATION<br>[ese |[wz][s0_a5][woo isa] fr [ax<br>Microchip Brand |<br>Architecture<br>Memory Size<br>10 = 1024 KB<br>RAM Size<br>25 = 256 KB<br>Family<br>W1 = WLAN<br>Key Feature Set<br>Pin Count<br>132 Pin Device<br>Packing Specification<br>Tray<br>Temperature Range<br>| = Induistrial (-40°C to +85°C)<br>V = Various (-40°C to +105°C)<br>Packaging Information<br>132-Lead (10x10x0.9 mm) DQFN<br>Pattern Information<br>QTP, SQTP, Code and Special Requirements<br>ES = Engineering Sample<br>**----- End of picture text -----**<br>
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## PIC32MZ W1 and WFI32E01 Family
## seman
## 1.2 WFI32E01 Module Ordering Information
The following table describes the ordering information of the WFI32E01 module.
TABLE 1-2: WF132E01 MODULE ORDERING INFORMATION
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**----- Start of picture text -----**<br>
Model No. Module SoC Description CertificationReguInIery Onerinig Cage<br>[WFIS2E01PEWFI32E01PC | PICS2MZT025W104132-VINX | WFIG2WFI32 E01 modmod ule w ithith PCPG B antenna and|| FC OC , ISE D,D, CECE |WFIS2E01PE-1|WFI32E01PC - |<br>Trust&GO<br>WF132E01UE WFI32E01 module with U.FL connector for |FCC, ISED, CE |WFI32E01UE - |<br>external antenna<br>WFI32E01UC WFI32E01 module with U.FL connectorfor |FCC, ISED, CE | [WFI32E01UC] [-] |<br>external antenna and Trust&GO<br>**----- End of picture text -----**<br>
The following figure illustrates the details of the WFI32E01 module ordering information.
## FIGURE 1-2: WF132E01 MODULE ORDERING INFORMATION
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**----- Start of picture text -----**<br>
ec}<br>**----- End of picture text -----**<br>
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**----- Start of picture text -----**<br>
Microchip Brand<br>Architecture<br>32 = Embedded 32-bit MCU Core<br>Family<br>E01 = WLAN Connectivity<br>Antenna<br>P = PCB Antenna<br>U = U.FL Connector<br>Encryption<br>E = Encryption<br>C = Trust&Go + Encryption<br>Temperature Range<br>| = Industrial (-40°C to +85°C)<br>FW Version/Custom Designations<br>**----- End of picture text -----**<br>
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## 2.0 PIC32MZ1025W104 SOC DESCRIPTION
## 2.1 Block Diagram
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**----- Start of picture text -----**<br>
DESCRIPTION The following figure illustrates the block diagram of the<br>core and peripheral modules in the<br>Note: This- data sheet summarizes- the features PIC32MZ1025W104 SoC.<br>of the PIC32MZ1025W104 SoC. It is not<br>intended to be a comprehensive refer-<br>ence source. To complement the informa-<br>tion in this data sheet, refer to the “P/C32<br>Family Reference Manual’, which is avail-<br>able from the Microchip website<br>(www.microchip.com/PIC32).<br>This chapter contains device-specific information for<br>PIC32MZ1025W104104 SoC.<br>FIGURE 2-1: PIC32MZ1025W104 SoC BLOCK DIAGRAM<br>XTAL_OUT/XTAL_IN X]<br>SOSCO/SOSCI PX<br>FRC/LPRC [X] Veo, Avoo, Vss,<br>Oscillators P <] MCLR<br>Timer<br>Precision Band Gap<br>SYSCLK Reference<br>PBxCLK<br>Generation<br><> [ae |<br>MIPS32® fe) @ Ss as<br>a 6 RAM RAM £s<br>o 3 Bank1| |Bank2] | & 2 )| ag<br>Bus<br>4<br>- tt 4 44<br>£9 4 13,14 110 712 16 T8 113 713 TH T2 112 T9 14 111 «112<br>7? a Vive vy vvy<br>T6 12 T5 T4 Io 18 iv T11<br>Vv 17<br>Peripheral Peripheral<br>ontroller Cache rs 2 5 Seu<br>| = Initiator T = Target<br>**----- End of picture text -----**<br>
This chapter contains device-specific information for PIC32MZ1025W104104 SoC.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 11
## PIC32MZ W1 and WFI32E01 Family
## seman
## 2.2 Function-wise Pinout Description
The following tables provide the function-wise pinout descriptions for the PIC32MZ1025W104 SoC and WFI32E01 module pins.
## TABLE 2-1: ADC PINOUT DESCRIPTION
|[Pinname [PinNumber[PinName _[PinNumber [Pe<br>[Twn<br>fANO<br>jose<br>[—<br>«(|=<br>—*i{|<br>[Analog __|ADAnalog InputChannels<br>jant_[aez_fani_fs<br>—+<br>[Analog __—|<br>(a<br>jana<br>fast sf SS<br>Sd<br>=iArto<br>jane<br>_[850_—*[AN’f2—~—~«d—=«*d<br>Analog<br>jans_feas—*aNs—ifs2?——S—S«<br>=**i** **A**ng ——*d<br>jane<br>[ee7faNe<br>‘(ae =i<br>=<br>nalog<br>jan7_[as7_fan7__(faa——«it—=«d<br>Analog ——_—=d<br>jans_[eas—ifans—ifar———S«d(<br>=iAng——*d<br>jane<br>[ass —faNS (48ST SC=*dAnalog<br>fata [asa<br>[——[——~+idr_—Araog<br>fant _feas [Si SSS~*dS~=*dAnalog —_—=d<br>javz_[aso [=<br>Sid<br>—=*d ao<br>janis [aes<br>SS<br>Sid<br>=iArto<br>ania<br>[pat<br>ania [4a<br>Analog<br>fants [ass<br>_faNIS—[a2———=idT<br>=iAnalog<br>janie _[eao[——*[—<br>+<br>[Analog __|<br>jani7 [ese<br>_[aNT?_—iat_——=«dSSS~*d<br>Analog =<br>janie [ese [SSS SSS*dS—=«*dnao<br>java [ass<br>**[**=<br>Sid =i log<br>fanaa [asi<br>ANAD_[45_—+[i__[<br>Analog ||
|---|
|fANNo<br>[Bai<br>[ANNO [ae<br>—‘(|—*dAnalog<br>fawn [aes<br>[annt [a2 ‘i<br>‘Analog<br>Legend:<br>Analog =Analog input<br>| = Input|
|TABLE 2-2:<br>OSCILLATOR PINOUT DESCRIPTION|
|Pin<br>Baar<br>Description|
|PTALIN, [A<br>[=<br>ids<br>__—«(A MHzPrimary Oscilator Crystalinput<br>petatour [aso<br>[=<br>[=<br>|__|— __|40 i Primary Oseilator Crystal Output |<br>Pn oR<br>OPee<br>SOSCI<br>A59<br>SOSCI<br>53<br>Input<br>Paa<br>SOSCO<br>A58<br>SOSCO<br>54<br>Output<br>rReri__[PPS___|REF|<br>[PPS [I<br>|—<br>[Reference GlockGeneratorinput _—_—|<br>freror_[pps__[reror___|pps__jo|—_|
|prero2_fpps__—'|Reroz_—ipps_—io—i[———+t<br>Reros_[pps__|ReFos<br>pps fo [—_|<br>[REFO4 ss[PPS)—s—“‘ié‘iTREFCC~—s[PPS [OS<br>C*”F Reference ClockGeneratorOutputs 1-4|
|Legend:<br>O=<br>Output<br>|=Input<br>PPS=PeripheralPinSelect|
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TABLE 2-3: IC¢1 THROUGH IC4 PINOUT DESCRIPTION
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**----- Start of picture text -----**<br>
||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|ict|PPS|SGA|
|icz|—SC«*qPPS—~sz)~—~S~=*diST___ Input Capture inputs 1-4|
|ics|Sides|ica|CST|Cd|
|ica|SiS|Citic|SCidPPS)|SSTOC|
|Legend:|SiSST|=|Schmitt|TriggerCittainput|withSCS)CMOS|levels|||=|InputCSCSPPS|=|Peripheral|Pin|Select|
|TABLE|2-4:|OC1|THROUGH|OC4|PINOUT|DESCRIPTION|
|Pin Name __||PinNumber||PinName|__| Pin Number||T¥P®_|TyPe|Description|
|PPS—=C«gOGT_—~C*«zgPPS’—=«d(O._—~«-__]|Output Compare|Outputs|14|
|oct|
|SCijoca—SiéidPs~—SsifSSC*dSSSC:t‘C*d|
|focs|SiS|
|oo:joca——S~=~iPPSSSC=i(ASSC~*‘iPPs~SSCidONC*d#S(“‘(‘CC“oe ee|
|ocrA_—-([pPS__—=*fOcrA|
|core|——=«iPPS——=«(OcrB|iPS[psi_—*r__—_—*(ST[ST|__|_||OutputCom|pareFautAinputpare|FautB Input‘||
|joorc___'|PPS_—‘[ooro_—‘|pPS___(ii____|ST|
|ocro|[Output|Compare FautCinput____—_—||
|Legend:|srsST|=|Schmitt|Trigger——ifocroinput|with|CMOS«PPSlevels|—i___—‘|STO|=|Output|[Output|Compare||=|InpFa|u|tlt|Input___—_—||
|PPS|=|Peripheral|Pin|Select|
|TABLE|2-5:|EXTERNAL|INTERRUPTS|PINOUT|DESCRIPTION|
|INTO|fe8oSSINTOO|Sd|[SSC*dST_—=sddetemmalinterupt]|
||PPS___[INT?___[PPS___—‘|___|ST____[€xternalinteruptt|
|INT!|SSCSSS|
|INT2_[PPS__—i(INT2__[PPSi|__‘(ST____|extemalinterupt2|
|_[PPS__(INT3__[PPS_—‘|____|ST____[€xternalinteruptS|
|INTs|
|—ifi___—‘(ST___[Extemalinterupt@|
|INTs|_‘pPS—=idINTA|[PPS|
|Legend:|ST|=|Schmitt|Trigger|input|with|CMOS|levels|||=|Input|PPS =|Peripheral|Pin|Select|
**----- End of picture text -----**<br>
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## PIC32MZ W1 and WFI32E01 Family
## seman
TABLE 2-6: PORTA THROUGH PORTC AND PORTK PINOUT DESCRIPTION
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**----- Start of picture text -----**<br>
|||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|[PORTA]|[Digital][ 0]|
|RAO|«(ee|Sd|«dt|[~——~*(vO_[DIGIST__[]|
|Ra2CdAS|
|Rasa|SCTCI|[SSCSC~i—SC~C~i‘O_f]|SSC|—SC~CS~O_ J DIGGisIST_ _|
|Ras—iete|
|SCT|SSC|~—S~«d_[ DiGi|_||
|RA7_*(Aa?SSSCd|
|ras|SSC|SCSCS~«~dON|IST _]|
|Ras|ier?ijaz2|iCT—SS|S|CiSC~S~OC*dIST._S~dO|is _||
|——Ssd([————~*diwo_—ifoiesT_||
|Raia|[eo|—«[—|
|Raise|
|SSCS*iO|GIST _||
|Reo|«ese|SCT|Sid|~——~*«z«©_|DIGIST_||PORTE|Digital v0|
|resists|
|SSC|—S~«*i_ fis _||
|Re1o|fase|SC|
|—Ssd[—~—S—~—~«(_|
|Ren|(ea|—s(—|SSC~dO_—ifGST_|fois _||
|Reis|feas|CC|SSSCSC~dO iS|
|Reafrets|jaca|~SSCidT—~SCS~iO_fiis _||
|Legend:|fasDIG =|Digital—irersinput|STfea_——~«i{r~—~S=«idiG@asT_=|Schmitt|Trigger|input|with|CMOS|levels|O|=|Output|||=|Input|
**----- End of picture text -----**<br>
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TABLE 2-6: PORTA THROUGH PORTC AND PORTK PINOUT DESCRIPTION (CONTINUED)
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**----- Start of picture text -----**<br>
||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Roo|ASC|Sid|—S~«*zO|DIGIT _[ PORTO|Digital V0|
|SCSSC~d—~SCSC~S~diO_[|
|Rot|es|DIG|_|
|reat|
|rcs|ips|CISCC= SSSSC~dO|Cif|
|Roa|iBto|SCI|SSCSCS~*O_—CfIGT._~——S~*i_— fics|
|Rosi?|
|SSC|—S~—O_ fis|_||
|Rom_fass|
|irc}|—(fs@—SC=*idO_—iGIsT_||
|Rois|[aes—«RCIs_—[s|——~=«diWO._—=«diGisT_||
|[PORTK]|[Digital]|[10]|
|RKO|«AMT|SSCS|[——=*d*O._[DIGIST__]]|
|Re|SC|[SSSC~«dO_—CDIGST_|]|
|Ke|fe2t|(SSC|[SSC~dO_[DIGT_|]|
|RKe—CidfASSSC*SSC~iSCSCS~*iON_~=C*dIGITT_|
|RKO|sea|SC|SSSC~dO|fC|_||
|Rese?|
|SSC|S~*iO_ [iG|_||
|exisLegend:|DIG[ass__—«iPkis =|Digital|input|STfea=|Schmitt——=«dtn)SSC=«idG@asT_Trigger|input with|CMOS|levels|O|=|Output|||=|Input|
**----- End of picture text -----**<br>
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## seman
TABLE 2-7: TIMER1 THROUGH TIMER7 AND RTCC PINOUT DESCRIPTION
|Trick<br>SPS<br>——=«dMGK——=«PPS—~=«zYSC*dgST.__|imer<br>EvternalClockinput<br>rack<br>___(PPS_—_—*«(T2ck_—_—*|PPS___—iii’__|ST___|Timer2<br>ExternalClockinput_____—<br>Tack<br>—_—+(pPs——=«dTSCK—~=«iPPS——=«it~—=«dST__|imerS<br>extemalGlockinput ——=d<br>rack<br>——=«dPPS——~S=*dtTHCK——~=«diPPS——=«ti_—=«dST___|<br>mera ExtemalGlockinput__——=d<br>Teck __(PPS__‘|TSCK [PPS<br>|l___|ST___|Timer ExternalClockinput___—<br>Teck<br>——«ipPs——=«(reck—_—=«iPPS_—‘|i__|ST___|Timer®Extemal<br>Clockinput__—_—<br>rex ___—‘|pps—~«dt7cK<br>—_—*PPS_—_—*ii__|ST___|mer7<br>extemalGlockinput _—_—=d|
|---|
|RToc<br>eas<br>SRTOO~«*diSDSC*~“‘~*ON’”CNC#*@CSSC~*C*dRT<br>CCOutput ock—SSSCSC~S~C~*<br>Legend:<br>ST = Schmitt Trigger input with CMOS levels<br>O = Output<br>| = Input|
|PPS=PeripheralPinSelect|
TABLE 2-8: UART1 (DEDICATED) PINOUT DESCRIPTION
uictsn ste Sd[SS~*rECSCSC*zST.__UART1] |A21 DIG UART1 Baud Clock oo inrsmurscuxU1RTSn/U1BCLK **f** ar tars pCle **a** rusto S **e** nd CTS) nput—_| luinx——set7_—SiquaRX—=«isOS~S~S~dYSCSCS*d lux STUART Recewe SSCS Legend: DIG = aanDigital input fuxST = SchmittieTrigger input«dSwith CMOS—«*dlevels «(ARTIO = OutputTransmit| = Input
TABLE 2-9: UART1 THROUGH UART3 PINOUT DESCRIPTION
|Description<br>PinName __| PinNumber |PinName __|PinNumber |T¥Pe__|TyPe|
|---|
|luictsn<br>PPS<br>——sjurorsn_—[PPS_—=«dt—SCS=*dST.—~C*«dqUARTVGTSinpat!——S<br>JUIRTSNUTCLK|PPS____|UIRTSn _[PPS_____[O_|DIG__|UART1 RTS OutputlUART! Baud Clock,<br>uiRxsPPS—SsquIRX—*pPs—=«i)~SS=*dST—_—C(UART#<br>Revove<br>ur<br>—iers idx ‘pps<br>—«(O—~«4dibIG—=«(UART<br>Transmit|
|luactsn<br>«PPS<br>———sjuacTsn_—[PPS_—=«it_—~S~=«sST’.——=«qUART@CTSinat!———S<br>JU2RTSN/UZBCLK|PPS___[U2RTSn<br>[PPS [0<br>|DIG__|UART2RTS Outpul/UART2 Baud Clock|<br>uaRx—sPPS—~=«(U2RX—=«PPS<br>=i) SS=*dST._—_C*(UANRT2Recene<br>CS<br>luarx__|PPS_—fuatx_pps__‘fo_‘[oIG__[UARTaTransmt|
|usctsn——s[PPS——=sjuscTsn_[PPS—=sii)—SC*~=*zST.——C*«zqUANRTSCTSimput——SSSCS~C*d<br>JUSRTSn/USBCLK|PPS<br>__[USRTSn__[PPS____|O<br>[DIG___[UART RTS OulpulUARTS Baud Clock,<br>luaRx—[PPS—=«USRX—«pPS—sfi_—~=«dST._—‘([UARTSReceve<br>lustx__|pps_—justx__|pps__‘fo<br>[OIG [ARTSTransmt<br>Legend:<br>DIG= Digital input<br>ST = Schmitt Trigger inputwith CMOS levels<br>O = Output<br>| = Input|
|PPS=PeripheralPinSelect|
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TABLE 2-10: SPI1 (DEDICATED) PINOUT DESCRIPTION
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|||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|SCK1|B11|SCK1|21|ie)|DIG/ST|Input/Output|
|scx:|fos|scar|aro|ovist|input|
|son|SATS|Css|[SidSC*dSS*dSTC*d(SPV]|
|Fs|Data|SSCS|
|A14|SS1/CS1|20|ie)|DIG/ST|Sync|(active-low)|
|sso$S1/CS1|awSossvesT|foo|vo __ovastSl|Syretactvern)|
|Legend:|DIG =|Digital|input|ST|=|Schmitt|Trigger|input|with|CMOS|levels|O|=|Output|||=|Input|
**----- End of picture text -----**<br>
TABLE 2-11: SPI1 THROUGH SPI 2 PINOUT DESCRIPTION
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|||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Pin Name|__||PinNumber|[Pin Name _||PinNumber||"vPe__[TyPe|Description|
|SCK1|B11|SCK1|21|ie)|DIG/ST|Input/Output|
|sox:|fo|focmr|aro|_forast|[mpwoupr|||
|son|‘ips|ison|—~=diPPS|Sd)|[SS«*dSTCd(SPINDatain]|SSCS|
|soor_—*([PPS——~sbo1_—sjPPS—=«dO~C*di@>IGS~—=*«d(SPNDatacotSSSSCS|
|SS1/CS1|PPS|SS1/CS1|PPS|VO|DIG/ST|(active-low)|
|siete|fasvcst|foes|io|foros|mem|||
|SCK2|A47|SCK2|43|VO|DIG/ST|Input/Output|
|coxa|aur|faces|fio|fovast|[mpaoupe|
|so2_—iipPS—=«d(so@—=édiPPSSSid)SSC*diST. ——~C*dSPIDatam—SCSC~S~SCSY|
|sooz___—‘iPes_—isooz__—sirs|
|PPS|$S2/CS2|PPS|ie)|DIG/ST|(active-low)|
|sses$S2/CS2|fers|fasacse|ers|=Ofio _fovast=«di>IG~—=*iSPI2DataOtaceon|SCS||
|Legend:|DIG =|Digital|input|ST|=|Schmitt|Trigger|input|with|CMOS|levels|O|=|Output|||=|Input|
|PPS|=|Peripheral|Pin|Select|
**----- End of picture text -----**<br>
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 17
## PIC32MZ W1 and WFI32E01 Family seman
## TABLE 2-12: 12C1 THROUGH I2C2 PINOUT DESCRIPTION
|Description<br>PinName_[PinNumber|Pin<br>Name_[Pin<br>Number|TvP°_|TyPe<br>Inter-Integrated Circuit 1|
|---|
|SCL1<br>SCL1<br>DIG/I2C/SMB__|12C1 Synchronous Serial Clock Input/Output|
|SDA1<br>SDA1<br>DIG/I2C/SMB_|12C1 Data Input/Output|
|Inter-Integrated Circuit 2|
|SCL2<br>Ais<br>[SC<br>ti(ié‘iTSsSs™sSYOSs[ DIGI2C/SMB_[I12C2 Synchronous Serial Clock Input/Output<br>SDA2<br>B40 (= SsDIGI2C/SMB<br>|12C2 Data Input/Output|
|Legend:<br>DIG = Digital input<br>O = Output<br>| = Input|
|TABLE 2-13:<br>USB PINOUT DESCRIPTION|
|Description<br>[PinName [PinNumber_[PinName [PinNumber |TyPe___|Type<br>USBVBUSInputSignal(5V);canbeleft|
|VBUS<br>A65<br>VBUS<br>4<br>open when USB not in use|
|¢<br>USB Internal Transceiver Supply|
|Voltage (3.3V). If the USB is not|
|used, this pin can be connected to|
|VSS. When connected to VSS, the|
|shared pin functions on USBID will|
|VUSB3V3<br>B54<br>not be available<br>ussOr |e——~«iO—=«d~——=*rS<br>D-‘aes——ijusBp- 5<br>—S~=*wi~C«dSSS~=*dSB<br>USBID<br>ussip<br>fy<br>S~*dE<br>«dS _ [USBOTS IDinput<br>USB transceiver interface output enable|
|USBOEN<br>A61<br>DIG<br>state<br>Veuson _[A62_____|veuson<br>[30<br>DIG___ [USBONsignalforextemalVBUSsource<br>Legend:<br>DIG = Digital input<br>ST = Schmitt Trigger input with CMOS levels<br>O = Output<br>| = Input|
|P = Power|
|TABLE 2-14:<br>CAN AND CAN-FD PINOUT DESCRIPTION|
|PIC32MZ1025W104<br>WFI32E01<br>Pin<br>Buffer<br>Description<br>PinName__|PinNumber_|PinName<br>__|Pin Number _|TvPe__|TyPe<br>CTTX<br>Pes<br>*[CTTx<br>Pes [Of_—*CANT BusTransmitPin<br>CIRX<br>Pes_—‘(ciRX—«iPPS.———=«i)~—SSS=«*ST____| CANT Bus Recetve Pin<br>cam<br>PPS<br>[o2tx__|PPs____—‘[O_|~[CANBusTransmit Pin<br>C2RX_|PPS__—ii____|ST____|CAN2 Bus Receive Pin|
|Legend:<br>ST = Schmitt Trigger input with CMOS levels<br>O = Output<br>| = Input|
|PPS=PeripheralPinSelect|
Note: The CAN1 bus supports only the CAN interface, and the CAN2 bus supports both the CAN and CAN-FD interfaces.
renner eee e rereerence eee eee DS70005425A-page 18 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
TABLE 2-15: ETHERNET RMII PINOUT DESCRIPTION
**==> picture [457 x 313] intentionally omitted <==**
**----- Start of picture text -----**<br>
|||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|PinName|__[PinNumber_|PinName|__[PinNumber|T¥Pe__[TyPe|Description|
|ERXDO—=«jASS—~SCSC*dERXDO—~*dgSS*~“~*é~iSCSC*‘“‘“*‘*dSS.~~—~C*dHemmet|
|ReceWve Data|—_—||
|ERXOT_‘(es7_—«d(ERXDT_——=«ditO—~=«iTSSSSC=*dST_[EthermetRecelve|
|Data|||
|ERXERR_(B5_——~=«*iERXERR—~«(f8_—S~=«dSS*S*~«*dST~~C*«*dStHemmetRecelve|
|ERXOV|_[A6_———~«dERXOV.———=«ditS|~SSC=*dSSCS*«dST!__thermet|Receive|DataError Valid ———=éd_||
|ETxo1_—((e2_——S—=ideTxt——=«dit3ETHCLKOUTero|SASSO _|B58__——~‘[ETH.CLKLOUTSC*dASS*dO——~C*diDIG~—~=*dthe[12~—S~=*d~S~*«*diIG—~=*dthemetTransmitDatat|ST_____[|Ethe|r|netmetTransmitDataoClock|Output (60|MH2)_||||
|ETXEN_([A69_———S(ETXEN—(B_—SSS*O|
|«(DIG|_—_—*Ethernet|TransmittEnable|
|Ewoc_([e4_—‘emoc|
||i?|o|_|DIG____|| Ethemet|Management|Data Clock||
|Legend:|DIG =|Digital|input|ST|=|Schmitt|Trigger|input|with|CMOS|levels|O|=|Output|||=|Input|
|TABLE|2-16:|SQI1|PINOUT|Description|
|sackPinName|[__|PinNumber_|PinName]|__|Pin Number|_|T¥P°__|TyPe|Description|
|sacso|faraped|[SCSC~—SCSC~C~O~~C~*zi]|fo|forest|[sarc|
|Bacsy|IG SSC~C*«*diS|CHIP Sees|CCS|
|SCOCSC~C*~dSC“C*~‘“*SC*S~SC“‘C;C*rO.C*‘ié|
|samo|fas|Cid|SS~dOSCS~*diIGS|~S—SCSCS~*éSQUCHp|Select|CS|
|—idge@SSCidSC~C—‘iSSCSC~iON~C~=*dz|
|sor|I|GT. —_C(SQDAtAIOVT|=i SN Datatn|]|—CSCSS|C|*d’S|
|sapaSAOCdSC*dSSSCSC~*~dIN~C=*d@|
|sapsLegend:|DIG—idBS =|Digital|inputCCCST|=|Schmitt|TriggerSCSC~N-—C*dzIGIST._—_Cé(SQNinput|with|CMOS|levels|IGS.O —_—=s(=|OutputSQNDM]Data]||=|Input|
**----- End of picture text -----**<br>
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 19
PIC32MZ W1 and WFI32E01 Family
## seman
TABLE 2-17: POWER, GROUND, AND VOLTAGE REFERENCE PINOUT DESCRIPTION
**==> picture [458 x 390] intentionally omitted <==**
**----- Start of picture text -----**<br>
||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|
|VPMULVDDP———=«*ATO|
|BOO|——S—SC~d—S~*d|[||nut Supply Voltage|(S.3V) to PMU|
|pmuvooiovewu|vooc|er|[>|LoInputBackup SupplyBattery VoltagVoltage|e|(3.3V)and toShould PMU|
|Be|Connected|to|Input|Supply|Volt-|
|ee|
|aoeBB|UK|_MDLO_OUTBKIX|fpB59|-|||||[EenectMLDO to Output VoltagAny External Circuit|e|(1.5V), for|
|posPMULVSENSEwussReOAMAZA3,A46, A67,A11,|A25, B3,|SS—=~dSCd|—SS|S|—=*dCS*~*d~SSC*d_—=S((|_| Buck OutputFeedbackcetVoltageto|External to|PMULC Fiter| ||
|Avooss|C«dBA|CO|SC*|SSSS=*d|[= _[USB Input Supply|Voltage (3.30)|_||
|SC~«dBASSSSSCSC*dSSSSCSC~SSSCSC~d|
|Aves|BAZ|C=|SS=*d|Cd[= _—~*[|A|naa|log|InputGroundSupply|Voltage (3.30) ||
|voors|acon feInput Supply Voltage (1.5V) from|
|OVODRFSCASABS|
|RXRRIQVoDIs|AADCI|[SCSCiSSCS~d]|SC*SSSC*dSSC*—=CdESDVIMputOC|Voltage|SV)|CC|
|RXRFET_VoDIs—«(BsSSSCCiSCCSCSC*iSSSCSC~d|
|Cd|C*'|
|RXRFEZVODTS—(es2CSC~idSSC~d|
|COC”!|
|SyN_SD_vbDIs|ASDC|Cd|SSCS~d|COC”!|
|SyYNvCO_voDIs_—+(ASSSC*dSSCSC~iSCSSCSC~dSSCi|
|CS”!|
|TALVODIs—iBOACSC~dSCSCSC~d|
|TXRIPAVODISrxR_UMXvopTs|(ese|[AACS]|SSSC~dSSCS~dCOCCOC|CS!C*'|
|BCC|
|spLvopis|CdCCSC*~SC~|d|P|COCCd|CS”!C*'|
|(=|
|2222|
|AFEVODIS|ARB|=|——«d|[= _|RF Supply Voltage (1.5V) from PMU|
|LVDIN|A52|Analog||Input|
|won|fase|fat [it|
|[eNDDBSC~GNDSSCCC*dC|
|Legend:|P=|Power|Analog|= Analog|input|COC||=|InputTC~d|TUCO|TTC|
**----- End of picture text -----**<br>
renner eee e rereerence eee eee DS70005425A-page 20 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
|TABLE 2-18:<br>JTAG, TRACE,AND PROGRAMMING/DEBUGGING PINOUT DESCRIPTION|
|---|
|Description<br>PinName ___|PinNumber_|PinName [Pin Number<br>_[TvPe_|TyPe|
|Tok<br>BASCTOK<br>«dA?<br>«dN._[ST__[TAG TestClock/Programming Clock Input_|<br>ror<br>«ASS<br>*dTOSC«*dAB<br>~*~ _=ST__|JTAG TestData/Programming Data Input_|<br>roo<br>——=*daS?——Ss=éd(TDO——=«éda®~—=SCS*«d~=*diDIG—_—=*(STAG<br>TestData Output=<br>™s_—‘ieay_——sdtwS——=«d#S—SSS«*d)SS=«dST’<br>[STAG TestModeSelectinput|
|TRouK BAT<br>SC*dSCSCSC~*dON~=*IGS ~—=Cd raceCock<br>SSC~“~*~*~*~S~C*d<br>moo<br>MSCSSC~iSCSCSC~dN<br>Ci CY<br>mor<br>ASDCCC~C~YN_C*d(@IS<br>CS<br>mo<br>eSCC~C~—SC*‘“;*~*~*rCC*‘IG'”C@d’|
|moe |e<br>rere set |srem<br>MCLR<br>A23<br>MCLR<br>26<br>ST<br>low)<br>Peciemuct last —[-<br>Ss ————=dY =i<br>|I@SP™ProgrammingGlock<br>PocientrY_[Aet——s[—<br>«(= ————*i'_'|St__|TestModeenty Clock<br>Pecaemucz|ss0___—‘pcca_——«i2——S—S=*d<br>«dS |IGSP™Programming Glock =<br>PoczenTRY [B50<br>[—<br>[=———i'__—'(ST__|TestModeenty<br>Clock i<br>Pecaemuca [pas<br>—«iipGos—ita?——SSS=«d<br>«ST. ICSP™ProgrammingGlock<br>Pocaentry |p4e_ «|<br>Ss———=dT——=dST_|Test<br>ModeEnty Glock<br>Pepvemuot fests[— sd<br>——_—*(_[DIGIST |ICSP™ProgrammingData<br>PeDieNTRY_[Bst_—S«[—<br>Ss SSSSCSCS~*dCSC*diST._[TestModeEntryData|
|PeozenTRY [eas<br>[— SSSSS—~*i~S=«*dST__[Test<br>ModeEntryData|
|Popaentry_|ase_—«|— Ss———«dYS—=*d(ST__|TestModetntyData<br>i<br>Legend:<br>DIG = Digital input<br>ST = Schmitt Trigger input with CMOS levels<br>O = Output<br>| = Input|
|PPS=PeripheralPinSelect|
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 21
PIC32MZ W1 and WFI32E01 Family
## seman
**==> picture [454 x 236] intentionally omitted <==**
**----- Start of picture text -----**<br>
TABLE 2-19: WI-FI© INTERFACE PINOUT DESCRIPTION<br>PIC32MZ1025W104 WFI32E01 Pin Buffer Description<br>PinName__|PinNumberRF_FE_1 =f|PinName _|Pin Number |TvPe_| Type<br>RF_FE_2 arr S*dO «CIT<br>RF_FE_3 pasaaa ——=«RELFE2SS*idO_IGISTDIGIST<br>RF_FE_5 aa Ci [SSSC~*~iO_DIGIST]<br>RF_FE_6 a a a (STS<br>RF_FET a a oe (Co (SSIS<br>RF_FE_8 Ae<br>ANALOG_TEST_(A3t_——«d[— «dO _DIGIST _|RF Front-End Control<br>«i ——S—S—~*dO | _[Analog Test Output<br>TSSI (Transmitter Signal Strength<br>IN_TSSI B27 Indication) Input<br>MBS_EXTRAAK [Bot_—«i[—<br>RXR_IN a asda———«*d |=]9SST Output Band Gap vottage)<br>TRLPAVOUT [ass Sd —«d (| Transmitter Output<br>Legend: DIG = Digital input ST = Schmitt Trigger input with CMOS levels O = Output | = Input<br>Note 1: A44 and A45 pins are used for controlling the FEM on the WFI32E01 module. Microchip recommends using these pins<br>as described in the reference design package. Contact the Microchip Sales/Support Team for the reference package.<br>**----- End of picture text -----**<br>
TABLE 2-20: _WI-FI® BLUETOOTH® COEXISTENCE")
PIC32MZ1025W104 WFI32E01 Pin Buffer Description Pinname __|PinNumber_|PinName ___([PinNumber _|TvPe _|TyPe C(BT_CLIKOUT [2a BT_CLK_OUTPTA_BT_ACTIVE Bt PTA_BT_ACTIVE C*(DD **IG** /ST—(| BlutoTH®Packet Traffic Clock Arbitra- Out PTA_BT_PRIO A24——=«(TALBT_PRIO[25__——*(O___|DIGIST_|tion (PTA) three-wire interface for Wi-Fi® and Bluetooth® co-exisPTA_WLAN_ACTIVE B19 PTA_WLAN_ACTIVE| 27 ie) DIG/ST tence Legend: DIG = Digital input ST = Schmitt Trigger input with CMOS levels O = Output | = Input Note 1: This feature is currently not supported and should not be used in an end-product design. Microchip plans to support this feature in the future.
renner eee e rereerence eee eee DS70005425A-page 22 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
TABLE 2-21: CVD PINOUT DESCRIPTION
**==> picture [421 x 273] intentionally omitted <==**
**----- Start of picture text -----**<br>
||||||||||
|---|---|---|---|---|---|---|---|---|
|[Pin|Name|[Pin|Number|[Pin|Name|[Pin Number _ Pin Type|Buffer Type|Description|
|fevoi|faery?|(SO|S*DIG|«(ADC CVD Controller Output|
|fevereves|fat|esi—ijewor2—i7—~—S=~s~*idie[-|SCS|
|fovea|[aso|—SSCid—Ss~—<C~SsUC‘izcMSC*d|
|fovos|[eas—ievos——OiaSSC~‘iOC*‘ézgOWGT’SC‘“‘*‘*‘*’—ifevos|sz|io|ios|—~«s|
|fevos_[ear_—ifevos—ias—~=S~=é‘iOC~*~*éisOGTSCSC*d|
|fevor__[asr—ievor—=«iw®—~SC~=~iO~*éisSSSC*d|
|jovos|ews|—ijows—ija7_—=S=isfO~—=*deSCS|
|jevos_fass—ijevos.—iws—S=~=“*éirO:COW#*#éd‘i®}I@jsSC*~C*‘*d|
|fevown|fase|[-|[SSCd—SsC~<CS~sUC*‘zcOIS]|
|fevon|CS|
|jovore|jes||-|~+(|-|—+ie|ioe|is|
|SsCi~r—SCC~<C~i!.C‘éziONS|
|evorsfovea|[eat[aweaso|-[-[-|—~i-~—|ie|—~dioe|SCSCd|
|_—iovois—ijaz——~—S=SiO~=édie|
|jovorsjevors|few[ass—ifevowa—iwa——~S~=éidf~*‘ziG’SCSC*di|-———~«if-~———~«dio.-—CiézosSCS|
|—ievowy—sda_—SC=~“‘iz£N’COW#*i*|
|fovoryfevers|[ese|Sg SSC*”Cd|
|—S«d-—SsS—~—CS?~—~*‘i|
|jevorsLegend:|[assessDIG =|Digital|inputif-[—|O+i=|Output|ie|ioe|CSSCS|
**----- End of picture text -----**<br>
TABLE 2-22: ENHANCED CVD PINOUT DESCRIPTION
**==> picture [434 x 273] intentionally omitted <==**
**----- Start of picture text -----**<br>
|||||||||||
|---|---|---|---|---|---|---|---|---|---|
|[Pin Name|[Pin Number||PinName|[Pin|Number _| Pin Type|Buffer Type|Description|
|fevori_[Aez——«[CVORT——«[3|OIG|«ADC CVD Controler RX Output|
|fevore_[est_—ifevore__'7——S=S=~diOS~*iSSCSC*d|
|fevers|fas|[- SS|[—SS—~d-C~C*‘ézgONS.]|
|—~—~S=«édiOS~*~éisOGs|
|fevorsfovors|[pao[eso|—-fevora|ia|SSCSCid|
|——=io—=idie|
|jovors|eer—‘fevors_f—jovor|s|2_——~ijo—=«ieiGSCSC*”(ae|SSCS|
|fevorr_[asr__jevor7__—ias——=S~=«éidiOS~S~*~éiss|
|—ijovore—ia7—=S=«diO~S~*di|
|fevors|[B46|SSCS|
|_jovora_|as_——=sijo—=idie|
|fovorejevorto|[ass[ase|[Ss SSdSSC~C~SNC~C‘zcOIGCSCS|
|~———Ss<«i?-—SCiézisSSC*d|
|fevers|jes|[-|«i=|CS|
|jovorta_aso[-|
|—~«i-~——S—~diO._Ciézos|
|jevortsfevoria|[eat[wo|—'fevorta-[-|~i[-faa|ie|ioe|Cd—+t|
|fovorts|—ifo—~=«zieGSCSC*d|
|jovorts|[ass|_ovoris|azo|—~ioe|SCS|
|fovori7|[|eseeo||—|—~i[-|ie|ioe|SCS|
|jovorte|—ifevori7_ai_——ijo—~=zisSC*d|
|jovorta|ess||—|—=—~i[-|ie|=i|SCS|
|Legend:|[aisDIG =|Digital|input[-|O|—~i-=|Output|io|ioe|SCS|
**----- End of picture text -----**<br>
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 23
PIC32MZ W1 and WFI32E01 Family
## seman
TABLE 2-22: ENHANCED CVD PINOUT DESCRIPTION (CONTINUED)
|rinName [Pin Number [PinName [PinNumber_|PinType<br>BufferType<br>Description<br>fevoro[as7_—sfovoTo.<br>«48<br>S*DIG<br>«(ADCCVDController TX Output<br>fevers_f**ea**r_—ifevorn,~—sias~SC~*~‘iOC*~*~éisO@’,SSCSC*d<br>jevora [<br>s<br>—ievora__—iez—~—~S~=éziO~*éiosSSSC*d<br>fevers [eso _ovors (2——sijo—=sdie<br>SSCS<br>fovea fa**st** fCSC—C~N-C*“‘zcOIC;”SCd’<br>fevers fe—ijevors—iy~=S=*~=“‘é‘idO™C*‘égOW@’SC*d<br>fevers [aca _fovors. is<br>—ijo joe —|<br>every es<br>_—ijovor7—«is<br>Si<br>~C*édi@ SCS<br>fevers _[ss7_—ifevors.~—sito~SS~*=~idSC*‘iGSSSSCd'<br>fevers _|ass__jovora<br>fe jo joe _—|<br>fevorio **[**e**s**e **—**ije**vor**io [2<br>**—**~**i**fo =i’SSCS<br>fever<br>a s<br>fe<br>n fe<br>' jo joe<br>—*s<br>fevoria_[e2—ifevora<br>fs —ijo iesSSCS<br>fevorrs [**a**a foots raja —=sdieSSCS<br>fovorta f s<br>—ifevorm its<br>—=s«dfo~C*idoGs<br>SSCS<br>fevorss fas<br>—ijevorss ite<br>—~SC=*éidOC~*~*éiso@sSSSC*d<br>fevorte [ea<br>—ifevors i?<br>—S—=iédfOS~S~*idGs<br>SSCS<br>ever? jes<br>i[—isi<br>ioe SCS”<br>vote[aa SC~r—SC‘“‘~;~*~*'~CV'C*CézNGS:~SSC*d<br>fevortsfos<br>i[-—~i-§~ —~«ie—ijes —=«d<br>fovorea [ao<br>-i[-—~i-~———~«ie—ijoe—=*”<br>evort_fee<br>[-<br>—S«i-—Ss—~sN-~C*‘ézcWS:<br>Cd<br>fevora [eo<br>|——-+i[-—~*+io—ies<br>—is<br>fevers fare<br>[-<br>~+([-<br>jo joe —t<br>Legend:<br>DIG= Digital input<br>O = Output|
|---|
|TABLE 2-23:<br>CTRT PINOUT DESCRIPTION|
|CC<br>[PinName<br>[Pinnumber_[PinName _[PinNumber|<br>[|<br>ferrrmo fess<br>fcTRTMO [41<br>[t<br>«ST<br>«|CTRExternal Trigger<br><< ———<br>Legend:<br>= ST = Schmitt Trigger input with CMOS levels<br>| = Input|
|TABLE 2-24:<br>PTG PINOUT DESCRIPTION|
|fprczs<br>«(PPS =iTG2s «(PPS ——*[O__[— | Peripheral TriggerGeneratoroutput|
|fercso_—+iPPs_——iercso___<br>fers —ijo—*i[-—S—*'F<br>erest_—i[pps__—ijeresi___<br>ppsio—(i[———izs<br>Legend:<br>O=<br>Output<br>PPS=PeripheralPinSelect|
renner eee e rereerence eee eee DS70005425A-page 24 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## 3.0 WFI32E01 MODULE DESCRIPTION
The WFI32E01 is a fully certified module that contains the PIC32MZ1025W104 SoC, an integrated FEM, and Trust&GO with following antenna options:
The Trust&GO is a pre-configured and pre-provisioned secure element of Microchip’s family of securityfocused devices. Figure 3-1 represents the WFI32E01 module block diagram.
- ¢ PCB antenna (WFI32E01PC/WFI32E01PE)
- ¢ U.FL connector (WFI32E01UC/WF132E01UE) for external antenna
## FIGURE 3-1: WFI32E01 MODULE BLOCK DIAGRAM
**==> picture [421 x 227] intentionally omitted <==**
**----- Start of picture text -----**<br>
WFI32E01 Module |¢——— WMCLR (Reset)<br>em stacicse™<br>PCB Antantenna POSC (40 MHz) q—_12-bit-bi ADC (12 Ch.)l<br>——— [| mmm) Ethernet (RMI!)<br>VY (am) 5?!<br>RF Front-end (aumm=> USB 2.0 OTG (FS)<br>Module and Pic32Mz1025w104 Soc hmmm ae<br>Matching Circuit — CVD<br>(mm) =CAN-FD<br>(am) CAN<br>Trust&GO (Optional) (mm ART<br>(mm) cPIO<br>—_—. Vo (3V3)<br>iw. SOS (32.768 kHz)<br>**----- End of picture text -----**<br>
© 2020 Microchip Technology Inc.
Preliminary Data Sheet
DS70005425A-page 25
PIC32MZ W1 and WFI32E01 Family
## seman
## 3.1 Pinout Details
The following figure illustrates the module pinout diagram.
**==> picture [438 x 469] intentionally omitted <==**
**----- Start of picture text -----**<br>
FIGURE 3-2: WFI32E01 MODULE PINOUT DIAGRAM<br>wo<br>&<br>Sa“<br>x &<br>eG<br>a 6<br>ee +8 5s<br>~~ << Q2z<br>N g£ & 2 Zz<br>Ww Wwyy =et mw a-! =<br>99 ge% 45 508 Ed al<br>6626622765556 6<br>DOSE eeooee<br>AN17 / CVD17 / CVDR17 / INTO / RPA10 MCLR<br>AN15/ANN1 / CVD15/ CVDR15 / RPA13 PTA_BT_PRIO / RPK6<br>SCK2 / RPA(1 BT_CLK_OUT/ RPK4<br>AN14 / ANNO / CVD14 / CVDR14 / RPA14 } SDO1/ RPC8<br>ANAO/ RPB12 ® GND<br>TMS / ANG / CVD6 / CVDR6 / RPB6 SCK1/ RPC6<br>TCK / PGC4 / AN8 / CVD8 / CVDR8 / RPB8 WFI32E01 _—___SPICS<br>/ RPA<br>TDI / PGD4/ ANS / CVD9 / CVDR9/ RPB9 SDI1/ RPC7<br>TDO / AN7 / CVD7 / CVDR7/ RPB7 CVDT7<br>/ ERXERR / RPC9<br>voD CVDT16/ EMDC / RPK14<br>VDD CVDT15<br>/ EMDIO / RPK13<br>PGD2/ ANS / CVDS / CVDRS/CvDT2/ RTCC/RPBS | Ey CVDT14 / ERXDV / RPK12<br>e<br>pets t eds ped deh off a fief is fis]<br>aSERBa~ o2aa&égqgpeereeag@axt= 5 5aeaeeaor82-¢e¢f@ERS!= erreeeBw<br>PZ ge = Ee:<br>Q 0 o 2 a > oo 2<br>SOSCI/PB15 3 2 > kK & ® OF A<br>o a 2 oi 0 Gi vu b<br>54]by} 5too¢ arfe~ >t 8~ ><br>~=SOSCO/PK15 8 6 3 5 8 8 zee<br>> 8 a o 8° o 23 3<br>a==<br>>oO x S E<br>3 a o a<br>z >6 a= 3<br>~ Oa =<br>an > 2<br>Bs:>:Z<x<br><<<br>Note 1: For details on the exact pin placement and dimensions, refer to 41.0 “Packaging Information”.<br>2: For pin descriptions, refer to Table 3-1.<br>**----- End of picture text -----**<br>
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TABLE 3-1: WFI32E01 MODULE PIN DESCRIPTION
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|||||||||
|---|---|---|---|---|---|---|---|
|ModulePin|||SoC|Pin|Pin|a|a|
|ramoee|||Mocoee ||Peeme|[yin]|neeton|
|p=|SOND’|SC—~—SCSCSCSCSC‘*S|
|ANe|«d(T SS~*dAraloginpot|
|fovea|«iO|—SC‘“‘“*S*~*|
|fevors||_|—~[ADCOVDeontoleroutut——SSCSC~S~S~SCSY|
|SOS|
|fevers||_|AA|D|C OVDeontoler™XCOVDeontolerRX_SSOSC~S|
|ovo|——=«fO—~[ADC CVD|
|OVDeontolerRXSSCSC~C~C~C~*|
|fovort__—~(|O|[ADCcontoleroutput——SSSCSC~—~“‘*~“‘—~*~*~*~*~S~*Y|
|fovoTe——«4fO—~fADCOVDeontolerT™x—SSCS~C~“—~*~*~*~*~—~S~S~SCS|
|VBUSON|[0|[USBON|signalfor extemal VBUS source|SSCS|
|a|[Aes|__|VBUS||__| USB VBUS|signal input|(V), can be left|open when USB|notin use _||
|SSC~—~sSCSCSCSCSCSCSY|
|je|_iasé—ifusso»|——~=«iWO~=«di Sets|
|fevoz|[©|[ADC OVD|contoleroutput|
|fevor2|SSCS|
||_|ADCOVDeontoler™XSSOSC~SCS|
|fevers|[0|_|ADCVDeontolerRX|SSCSC~“~*~S~SCS|
|jussID—SC~«dSSC*USB|
|OTE|Wit|SSCSC~—CSCSCSCSY|
|———SSSCSCS~CS|
|ETXEN|[0|[Ethernet|ransmitenable output|
|feRxoO___—«I___[EthemetRMllrecehedatabtOSSCSC~S~S~™|
|SSCS|
|feRxo1|____|I____||Ethernet RMll|receive databiet|
|SSC~—C—sSOSCC‘(|
|im|[—|—ifenn——S=~«di|Sidon|
|pest|||series termination resistor|
|————SSSOSCSC~S~SCS|
|fETXDI|____~[O|[Ethernet RMIltranemitdatabit|
**----- End of picture text -----**<br>
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TABLE 3-1: WFI32E01 MODULE PIN DESCRIPTION (CONTINUED)
|ModulePin | SoC Pin<br>Pin<br>—<br>ramoe | tangee |_Peeme |yin]<br>teton<br>4<br>Aa<br>[overs<br>———«fO—[ADCCVDoontrolerT™<br>fevxD0<br>[© | EthernetRMIreceivedatabitO<br>SSCS|
|---|
|FERXDV<br>[I | EthernetRMIreceivedatavali@<br>SSCS|
|fewDc<br>[|Ethemetmanagementdatacook——SSCSC~S~S~SCS|
|FERXERR<br>[I ___|EthernetRMllrecelveenor<br>SSCS|
|ee|
|fe<br>|<br>sien<br>SS~S~*~*RSCS*C*idongs<br>ss<br>SSC~—C—sSSOCCC‘(S|
|tooth® and Wi-Fi®coexistence”)|
|257<br>faze —*(MCLR<br>|__|Reset signal,Actvedow,requiresextemalROcraut<br>=|
|pe<br>fae<br>juix<br>«ilo _‘|UARTItanmt<br>—SSOSC~—CSCSCSCS~S~S™<br>oer<br>fuiex<br>Sid SC*dUARTHreeves<br>SSC~—“—S*S*S*S*~—C“‘—C—CSsSsCSCSCSY<br>rennereeeerereerence<br>eee<br>eee|
|DS70005425A-page28<br>PreliminaryDataSheet<br>©2020MicrochipTechnologyInc.|
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|||||||||
|---|---|---|---|---|---|---|---|
|TABLE|3-1:|WFI32E01|MODULE|PIN|DESCRIPTION|(CONTINUED)|
|ModulePin|||SoC|Pin|Pin|ae|
|firambe” [tance«GND ||Povame|[penGrund||[_____setton]|||
|SS|
|eS [-|[SsiGNDSS~*~RCSSC*dGmong—]|
|7|ss|SSC~—SSSOCSC‘*d|
|if|
|sa|ifeno.—S=«diP~~SCéd@ngSSC~—~—SSSCSCSCTCTCC.CC‘(C|
|fo|[—|[—SieNDSCSC~*~iSC*‘id@engS]|—*diNC|—SC*d_—|test|pad only fortactoyuse)|SSCS|
|SOS~—~—SSSCSCSCSCSCSCSSY|
|jo|[—|[end|——~«diP|Sided|sO|SCSC~C—sSSCSCCCSY|
|jovory_—~=«dfO—~«(ADC|
||_|ADCCVDeontwolerRX|
|fovort?|OVDcontolerouipt——SSCSC~“~*~*~“~*~S~S|
|interuptinput—SSSCS~S~S~SCS|
|into|——~S«*d~——=*di|Eterna|out|—SSSC~*~S~SCS|
|ANNT|«dt|=i Anloginput|
|fevers|«dO|—*ADC——SOCSC~—~—CSCSCVD|
|OvDeontolerRXSSSC~SCSCS|
|fevorts|[0|[ADCcontoleroupat——SSCSC~C~S~S~CS|
|ee|—————————————|
|_‘|I__[Analoginput————SSOSCSCS~SCS|
|ANNO|
|fovoré—~(O|[ADC|OVD|
|fovorté|[0|[__[ADCOVDeontolerRX]|contolerouipat———S|S|SSC~—~*~‘“‘~*~*~S~SSSCSC~C~S~C~C*S|
|ane|«dt|—~*dAnaloginput|SS|
|fovos|«df|—~[ADCSSCSC~—~—SCS OVD|
|SSCSC~S~S~S~S~SCS|
|OvORS__—*(fO|[ADCcontoleroutput——SSCSC~—~*~S~SCS OVDeontolerRX|
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## PIC32MZ W1 and WFI32E01 Family seman
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TABLE 3-1: WFI32E01 MODULE PIN DESCRIPTION (CONTINUED)<br>ModulePin | SoC Pin Pin Description<br>Number Number Type) P<br>47 B46 ITCK JTAG test cock/programming clock input<br>PGC4 Hh ICSP™ programming clock<br>CVD8 1O ~~ [ [ADC] [CVD] [controller] [output]<br>[CVD] [controller] [RX]<br>CVDR8 }O—— [| [ADC]<br>RPB8 Remappable peripheral(2)<br>48 A56 ‘To JTAG test data/programming data input<br>PGD4 ICSP™ programming data<br>CVD9 lo ADC CVD controller output<br>[CVD] [controller] [RX]<br>CVDRQ }O ~~ | [ADC]<br>RPB9 Remappable peripheral(2)<br>49 AST [TIO~=——i(itsté‘*ON':C*CU STAG ‘test data output<br>CVD7 1O == [ [ADC] [CVD] [controller] [output]<br>CVDR7 }O.|ADC CVD controller RX<br>RPB7 Remappable peripheral?)<br>52 B49 PGD2 ICSP™ programming data<br>CVD5 [os |ADC. CVD controller output<br>CVDR5 [O——_—-| ADC CVD controller RX<br>[CVD] [controller] [TX]<br>CVDT2 1O ~~ [ [ADC]<br>RTCC |O——_-| RTCC output clock<br>RPB5 Remappable peripheral(2)<br>53 A59 SOSCI [|_| Secondary oscillator input<br>PB15 || | PORTB digital input<br>54 A58 SOSCO lo Secondary oscillator output<br>PK15 ||| PORTK digital input<br>61-63) a ee ee Exposed GND pads, should be soldered on the host board<br>Note 1: Legend:<br>¢ | = Input pin<br>**----- End of picture text -----**<br>
¢ O = Output pin
- ¢ I/O = Input/Output pin
+ P = Power pin 2: These pins can be configured for any of the supported peripheral functions based on the user's requirement. For more details, refer to 13.4 “Peripheral Pin Select (PPS)”.
3: Every I/O port pin (RAx-RKx) can be used as a change notification pin (CNAx-CNKx). See 13.0 “I/O Ports” for more information.
- 4: Shaded pins are 5V tolerant pins.
- 5: Pins 26 through 30 are critical pins, and Microchip recommends to add series resistors in the host board.
- 6: For the placement of pins 55 through 63, refer to 41.2 “WFI32E01 Module Packaging Information”.
- 7: The PTA features is currently not supported and should not be used in an end-product design. Microchip plans to support this feature in the future.
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Note: For module related recommended operating values and electrical characteristics, refer to Section 40.2, WFI132E01 Module Electrical Specifications.
3.2 Basic Connection Requirement The WFI32E01 module requires attention to a minimal set of device pin connections before proceeding with development.
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FIGURE 3-3: WFI32E01 MODULE BASIC CONNECTIONS<br>**----- End of picture text -----**<br>
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+3.3V<br>C1 C2<br>22uF O.4uF<br>| | +3.3V<br>GND ao<br>+33 reve Ss se<br><_PGD2 > | 19> R R6<br>“0k vi WFIS2E01 peor ees Le, + ar<br>an 28) OLR EENREC<br>3 VBUSON/RPB1 ETXD4/RPC14ExDieCe [as RI<br>GND USBID/RPB2 ETH_CLK<_OUTIRFCI2 Le rr $<br><< RPB6 > e TMS/AN@RPBE EMDIOIRAETS<br>ERGB st SOSCI/PB15seems SCK 2/RPARpeySDait11 [28 RIT AQW22R RS<br>38 NC ANAGREBISAN17/RPA10<br>jiasiiim<br>GND<br>**----- End of picture text -----**<br>
Note 1: The mentioned resistance values are only for the guidance. For details on the application schematics, refer to the PIC32 WFI32E Curiosity Board User’s Guide (DS50003028).
3.2.1 POWER PINS 3.2.2 MASTER CLEAR (MCLR) PIN It is recommended to add a bulk and a decoupling The MCLR pin provides for two specific device capacitor at the input supply pin (VDD and GND pins) functions: of the WFI32E01 module. * Device! Rasat FIGURE 3-4: RECOMMENDED ¢ Device programming and debuggin coe oo ees a MODULE POWER Pulling the MCLR pin low generates a device Reset. SUPPLY CONNECTIONS Figure 3-5 illustrates a typical MCLR circuit. During device programming and debugging, the resistance and capacitance that can be added to the pin must WFI32E01 be considered. Device programmers and debuggers Module drive the MCLR pin. Consequently, specific voltage VpD levels (VIH and VIL) and fast signal transitions must c(t) colt) not be adversely affected. Therefore, specific values [2 uF i 0.1 uF of R and C need to be adjusted based on the appli= = cation and PCB requirements. GND GND For example, as_ illustrated in Figure 3-5, it is Note 1: Value of the C1 and C2 capacitors may vary based on recommended that capacitor C be isolated from the ine apblealiprorequiremment. MCLR pin during programming and debugging 2: The C1 and C2 capacitors should be placed close to operations the module pin. . reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 31
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PIC32MZ W1 and WFI32E01 Family<br>seman<br>Place the components illustrated in Figure 3-5 within « “Using MPLAB® REAL ICE™ Emulator” (poster)<br>one-quarter inch (6 mm) from the MCLR pin. (DS50001749)<br>FIGURE 3-5: EXAMPLE OF MCLR PIN a6 HIRG<br>CONNECTIONS Note: This is an optional interface for the<br>VD WFI32E01 module. JTAG can be used<br>based on the selection of the debugger<br>R¢ 10k R11) and programing interface.<br>0.1 pF)2 —-¢ 1ka MCLR The TMS,. TDO, TDI and; TCK pins. : are used for;<br>I WFI32E01 programming and debugging according to the Joint<br>l = Test Action Group (JTAG) standard. Pull-up resistors<br>are recommended on these lines for JTAG<br>2 Pecx!) functionality. For remappable functionality, the discrete<br>7 PGDx®) component value needs to be considered based on<br>Q 3 Niss application.<br>NC It is recommended to keep the trace length between<br>the JTAG connector and the JTAG pins on the<br>Note 1: 470Q<R1<1 kQ limits any current flowing into WFI32E01 module as short as possible. If the JTAG<br>MCLRMCLRpinfrom breakdown,the external duecapacitor to ElectrostaticC, in the Dischargeevent of cannienior Is. expesied te experience: an.ES0 ever a<br>(ESD) or Electrical Overstress(EOS). Ensure that the series resistor is recommended, with the value in the<br>MCLR pin VIH and VIL specifications are met without range of a few tens of Os, not to exceed 1000.<br>2: eBThelnfetieangesetscapacitorfrom Withbrief thecancitiieae Debug/Riegraninehglitchesbe sized orto topreventextend tals:unintentionalthe device- requirements.Refer. to. the'in theAC/DCrespectivemi characteristics- ; device._ specificationand_ __ .timingfor<br>Reset period during POR. information on capacitive loading limits and pin input<br>3: No pull-ups or bypass capacitors are allowed on voltage high (VIH) and input voltage low (VIL)<br>active debug/program PGCx and PGDx pins. requirements.<br>3.2.5 UNUSED I/O PINS<br>3.2.3 ICSP PINS Unused I/O pins should not be allowed to float as<br>The PGCx/PGECx and PGDx/PGEDx pins are used inputs. They can be configured as outputs and driven<br>for ICSP and debugging purposes. It is recom- to a logic-low state.<br>cla to hed eae ae PGD2 for the WFIS2E01 Alternatively, inputs can be reserved by connecting the<br>eee ie nen See UNe ean raneaNy pin to Vss through a 1 kQ to 10 kQ resistor and config-<br>Keep the trace length between the ICSP pins of the uring the pin as an input.<br>WFI32E01 module and the ICSP header as short as<br>possible. If the ICSP connector is expected to expe- 3.2.5.1 GPIO Pins/PPS Functions<br>rience an ESD event, a series resistor is recom- Most of the WFI32E01 module pins can be configured<br>mended with the value in the range of a few tens of as GPIOs pins or for PPS functionality. To find the func-<br>Qs, not to exceed 1000. tionality supported by each of these GPIOs, refer to<br>Ensure that the Communication Channel Select Table 3-1.<br>Seis wheal = ae ee It is recommended to add a series resistor on the host<br>impair tect ima IB 4 eriMPlad BEAL Kee™ dependsboard foronall theGPIOs.actualThepinvalueconfiguraof t heion.seriesTheseresire s toris-<br>: tors must be placed close to the module. Figure 3-10<br>For more information on MPLAB ICD 3/MPLAB ICD 4, illustrates the placement of series resistor.<br>and MPLAB REAL ICE in-circuit emulator connection<br>requirements, refer to the following documents avail-<br>able from the Microchip website.<br>*« “MPLAB® ICD4 In-Circuit Debugger Quick Start<br>Guide” (DS50002538)<br>« “MPLAB® ICD4 In-Circuit Debugger User's<br>Guide” (DS50002596)<br>* “Using MPLAB® ICD 3” (poster) (D$50001765)<br>* “MPLAB® ICD 3 Design Advisory” (DS50001764)<br>* “MPLAB® REAL ICE™ In-Circuit Debugger<br>User’s Guide” (DS50001616)<br>renner eee e rereerence eee eee<br>DS70005425A-page 32 Preliminary Data Sheet © 2020 Microchip Technology Inc.<br>**----- End of picture text -----**<br>
## PIC32MZ W1 and WFI32E01 Family
## smn
- 3.3 WFI32E01 Module Placement Guidelines
- * For any Wi-Fi product, the antenna placement affects the performance of the whole system. The antenna requires free space to radiate RF signals and it must not be surrounded by the ground plane. Thus, for best PCB antenna performance, the WFI32E01PC/WFI32E01PE module should be placed at the edge of the host board.
- The WFI32E01PC/WFI32E01PE module ground outline edge should be aligned with the edge of the host board ground plane (see Figure 3-6).
- extended beyond the minimum recommendation as aion. for the host board EMC and noise reduc-
- For best performance, keep metal structures and components (such as mechanical spacers, bumpon, and so on) at least 31.75 mm away from the PCB trace antenna as illustrated in Figure 3-6.
- * The antenna on the WFI32E01 module should not be placed in direct contact with or close proximity to plastic casing or objects. Keep a minimum clearance of 10 mm in all directions around the PCB antenna (see Figure 3-6).
- ¢« Alow-impedance ground plane for the WFI32E01 module will ensure the best radio performance (best range and lowest noise). The ground plane can be
**==> picture [425 x 368] intentionally omitted <==**
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FIGURE 3-6: WFI32E01PC/WFI32E01PE MODULE PLACEMENT (TOP VIEW)<br>Keepout area around antenna t<br>(approximately 31.75 mm) E Edge of the WFI32E01 Module<br>from metallic structures g<br>o 31 75 mm->|<br>| + <2°™™ — Edge of the Host PCB<br>Module Ground *) J<br>Outline 6.2 mm ; %<br>Edge of the TT amend 1 ("Jaz wd~<br>Host PCB<br>Ground Plane ° Edge of the Host<br>ONY PCB Ground Plane<br>Vv<br>Host PCB<br>Ground Plane<br>¢ The module should be flush mounted to the host<br>board (see Figure 3-7).<br>FIGURE 3-7: WFI32E01 MOUNTING GUIDELINES RECOMMENDATION (SIDE VIEW)<br>WFI132E01 Module<br>Host PCB Flush mounted on the host PCB<br>i (No Gap)<br>**----- End of picture text -----**<br>
## me
© 2020 Microchip Technology Inc. Preliminary Data Sheet
DS70005425A-page 33
## PIC32MZ W1 and WFI32E01 Family
## seman
- The WFI32E01UC/WFI32E01UE module on the ¢ APCB cutout is required under RF test point (see host board can be placed aligned to each other (see Figure 41-6). Figure 3-8). * Copper keepout areas are required on the top layer
- * Three Exposed GND pads (61-63) on the bottom of under voltage test points (55-60) (see Figure 41-6). the WFI32E01 module should be soldered to the host board (see Figure 41-6).
- FIGURE 3-8: WFI132E01UC/WFI32E01UE MODULE PLACEMENT (TOP VIEW) Edge of the WFI32E01 Module Edge of the Host PCB a &
- Host PCB va Ground Plane =
ES DS70005425A-page 34 Preliminary Data Sheet © 2020 Microchip Technology Inc.
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The following figure illustrates the examples of WFI32E01PC/WFI32E01PE module placement on a host board with a ground plane. Refer to Figure 3-6 for placement specific guidance.
FIGURE 3-9: EXAMPLES OF WFI32E01PC/WFI32E01PE MODULE PLACEMENTS ON THE HOST BOARD
**==> picture [309 x 217] intentionally omitted <==**
**----- Start of picture text -----**<br>
S S<br>Good Case Best Case<br>SS<br>Poor Case onde aco<br>:<br>es 4 At<br>Ss 8<br>Poor Case SS<br>SSSY No Copper Area Ground Plane<br>**----- End of picture text -----**<br>
## 3.4 WFI32E01 Module Routing Guidelines
- ¢ Use the multi-layer host board for routing signals on the inner layer and the bottom layer.
- ¢ The top layer (underneath the module) of the host board must be ground with as many GND vias as possible (see, Figure 3-10 and Figure 41-8).
- ¢ Avoid fan-out of the signals under the module or antenna area. Usea via to fan-out signals to the edge of the WFI32E01 module.
## PCB.
- ¢ USB differential pair signals are 902 impedance matched on the WFI32E01 module PCB and the same should be followed on the host board.
- SOSC crystal (32.768 kHz) on host board should be placed close to the WFI32E01 module and follow the shortest trace routing length with minimum number of vias (See, Figure 3-10 and Figure 3-11).
- ¢ For better GND connection to the WFI32E01 module, solder the exposed GND pads of the WFI32E01 module on the host board.
- ¢« For module GND pad, use a GND via of a minimum 10 mil (hole diameter) for good ground to all the layers and thermal conduction path.
- It is recommended to have a series resistor on the host board for all GPIOs. These resistors must be placed close to the WFI32E01 module. Refer to Figure 3-10 for the placement of the series resistor. Pin 26 through pin 30 on the WFI32E01 module are critical pins to have series resistors. For more details on these pins, refer to Table 3.
- ¢ All Ethernet TX and RX signals trace lengths (RMII interface) are matched on the WFI32E01 module
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## PIC32MZ W1 and WFI32E01 Family
## seman
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**----- Start of picture text -----**<br>
FIGURE 3-10: EXAMPLE OF THE HOST BOARD TOP LAYER<br>Module Outline<br>Host Board Outline No Signal or Via on<br>\ 70° A® lo GZ ° ZOEf 2, Antenna Side<br>eo“5 lo co em © _6jon?© 0 [dj 0°<br>> el 9° Oo os | °° i<br>oe aa e d Pp tes | Signals to Inner Layer from<br>Mounting PAD ° |9 boo . So © 0 © 2° ojo > Module Mounting PADs<br>ounting 4 > e ob oo o 00.0 0 do | a<br>on Host Board ~ill 5 a oe he lo ae<br>z | of Po < , “NN 5 ® ” MS x<br>SOSC is | 9] ae a ce @ . he |e = Continuous Ground<br>Crystal 4 >” = «ff mad 4 | with Distributed Via<br>Placement =~—_] Ie d Om y 3° | ><br>‘8 eat° e e i —-Q Signals Going Out from<br>oo | yo Z uid | P| <— | Module Mounting PADs<br>| 4 ° 0 0 %eo D q<br>| aa ° | | °<br>é tlWoosclccl- te JILE ' | ° qa<br>e Oo .<br>° - o ie aL |= o ieOe) AO, Series: Resistor;<br>in SIS! 26] (RABI Boe sal<br>7,<br>PCB Cutout for RF Test Point g Keepout Area for Test Points e Exposed GND Area<br>Note 1: For WFI32E01UC/UE module, edges of the host board and module can be aligned with continuous<br>ground and ground vias (see Figure 3-8).<br>2: For recommended WFI32E01 module footprint, refer to Figure 41-8.<br>FIGURE 3-11: PLACEMENT AND ROUTING OF SOSC CRYSTAL<br>32.768 kHz Crystal<br>Module,PADs<br>Routing at the 0<br>bottomJayer<br>**----- End of picture text -----**<br>
Note 1: For WFI32E01UC/UE module, edges of the host board and module can be aligned with continuous ground and ground vias (see Figure 3-8). 2: For recommended WFI32E01 module footprint, refer to Figure 41-8.
renner eee e rereerence eee eee DS70005425A-page 36 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
## 3.5 WFI32E01 Module RF Considerations
## 3.6 WFI32E01 Module Antenna Considerations
The overall performance of the system, RF and Wi-Fi is 3.6.1 PCB ANTENNA significantly affected by the product design, environment and application. The product designer must For the WFIS2E01PC/WFIS2E01PE module, the PCB ensure system level shielding (if required) and verify antenna is fabricated on the top copper layer and covthe performance of the product features and applicaered in solder mask. The layers below the antenna do tions. not have copper trace. It is recommended that the mod. . ae . _. Consider ule is mounted on the edge of the host board and to the following guidelines for optimal Wi-Fi perhave no PCB material below the antenna structure of formance: the module and no copper traces or planes on the host * The WFI32E01 module must be positioned in a board in that area. noise-free RF environment and must be kept far The following table lists the technical specification of away irony High requency clogk signals ame amy the PCB antenna and tested with the WFI32E01 mod. other sources of RF energy ded ule mounted on a Carrier/Evaluation Board. abject must not be shielded by any metal TABLE 3-2: PCB ANTENNA . SPECIFICATIONS ¢ Power supply must be clean and noise-free ¢ Make sure that the width of the traces routed to Specification GND, VDD rails are sufficiently large for handling peak TX current consumption. : : 2.51 dBi at 2450 MHz Note: The WFI32E01 module includes RF Efficiency (avg.) shielding on top of the board as a standard feature. 3.6.1.1 PCB Antenna Radiation Pattern The following figures illustrate the PCB antenna radiation pattern.
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FIGURE 3-12: PHI = 0 DEGREE ANTENNA RADIATION PATTERN<br>Odeg<br>Legend<br>——2400.00(MHz) 5-00dp<br>—— 2412. 00(MH2) tas<br>——2437.00[MHz2]<br>——2462.00(MHz) ; ae :<br>aioe bamet Se SS Sa’<br>——2500,00(MHz) yA ae CS SSS<br>ff a ve or on ae se “he % See<br>| are oe ee ee<br>A) if ol = OB 5s eh, eran Wh x<br>hyi / i : / enhese iS res oef * aneoes 4\ ite5 \fi ‘a<br>— |: : ah a<br>\ee aSa eeoe 4; a seeefY oP f<br>180deg<br>**----- End of picture text -----**<br>
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FIGURE 3-13: PHI = 90 DEGREE ANTENNA RADIATION PATTERN
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Legend Oees<br>—— 2400. 00(MHz2)<br>————2412.00(MHz])2437. 00(MHz] 5-008<br>—— 2500. 00(MHz) AB SS B00da_ ee<br>eee ont go y;<br>ty Coe _peeees 40,0008. SSK<br>7 A oy eet we<br>: ‘ f ¢ PF ss ODE, | : :<br>90deg ‘ae : : c. : : HM oN<br>3 i fer ~ oxy 7 sal : a Fal yo 3 Hg f<br>aay N Ma 7 ce ee eo / if ee.<br>180deg<br>**----- End of picture text -----**<br>
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FIGURE 3-14: THETA = 90 DEGREE ANTENNA RADIATION PATTERN
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Legend Odeg<br>——2400.00(MH2)<br>—— 2412.00(MH2) 5-004.<br>——2437,D0(MH2) <a<br>ip gee ie ae oS Wes. *<br>‘i i ee OO eo Wy<br>i i) : Me ae Pe ria. oa ‘ . We og<br>iW SO eee ets ee | 4<br>7<br>' | tig C) | any Ee 270deq<br>pT ‘ Me Ae 2 ae ee a eo ve | 2 ~<br>NX a : oe we A an<br>vi Pee — ES a a<br>180deqg<br>**----- End of picture text -----**<br>
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- PIC32MZ W1 and WFI32E01 Family
- smn 3.6.2 EXTERNAL ANTENNA PLACEMENT * The antenna should preferably be placed at a disRECOMMENDATIONS tance greater than 5 cm away from the module. The
- The following recommendations must be applied for Follevanig cBurSSneS Peaitiehinel fey Galt Snes the placement of the antenma andiits cable:, indication where the antenna must not be placed. i, These recommendations are based on an open-air
- ¢ The antenna cable must not be routed over circuits measurement and does not take into account an qanerating alschical. nalse-oniiie host heen iar metal shielding of the customer end-product. When 3 alongside or underneath the module. It is preferred a” is ’ thatthe cable Is routed straight oubof the module metal enclosure is used, the antenna can be located : closer to the WFI32E01UC/WFI32E01UE module.
- ¢ The antenna must not be placed in direct contact or in close proximity of the plastic casing/objects. Note: These are generic guidelines and it is rec-
- * Do not enclose the antenna within a metal shield. ommended that customers check and * Keep any components which may radiate noise, sigfine-tune the antenna positioning in the nals or harmonics within the 2.4 GHz to 2.5 GHz frefinal host product based on RF perforquency band away from the antenna and, if mance. possible, shield those components. Any noise radiThe following figure provides an indication on how the ated from the host board in this frequency band antenna cable should be routed depending on the locadegrades the sensitivity of the module. tion of the antenna with respect to the WFI32E01UC/ WFI32E01UE PCB, there are two possible options for the optimum routing of the cable.
FIGURE 3-15: WFI32E01UC/WFI32E01UE ANTENNA PLACEMENT GUIDELINES
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Preferred antenna 5<br>cable routing pi<br>direction<br>Preferred antenna i<br>cable routing ae<br>direction pene<br>5 cm ——_> 5 cm —————_><br>Antenna keep out area<br>Vv<br>**----- End of picture text -----**<br>
3.6.2.1 External Antennas It is permissible to use different antenna, provided the The WFI32E01UC/WFI32E01UE modules have an Seiae HEE ype, ERIC iaigaln feqpalar RSs Mian), uilfte-small surface rouat UiEL connector tor an exderand similar in-band and out-of-band characteristics are nal antenna connection. The choice of antenna is limpresent (refer to specification sheet for cutoff frequenited to the antenna types for which the module is tested aes). and approved. If other antenna types are used, the OEM installer must The WEI32E01UC/WEI32E01UE modules are conduct the necessary assessments and authorize the approved to use with the antennas listed in Table 3-3. antenna with respective regulatory agencies and ensure compliance.
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## PIC32MZ W1 and WFI32E01 Family seman
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TABLE 3-3: LIST OF APPROVED EXTERNAL ANTENNAS<br>Regulatory<br>Part Antenna | antenna Authority”ity (1 Cable Length/<br> Number Gaini Type FCC Rowan<br>Pi [RFAG2LOHT _—_—‘[Alead/Arstotle| 2 | Dipole | x | x | x |ts0mm |<br>[4 [RFDPAB7OS20IMLB301 |WALSIN<br>| 6 |RFDPRFDP A8 70920IMAB305__|70920IMAB302 | WALSIN 200 mm/ BlackGrey<br>7_[RFOPAS7OS10IMAB308__|WALSIN<br>RFA-02-C2M2 Alead/Aristotle 2 Dipole x x x |RP-SMA®)() to<br>U.FL cable length<br>of 100 mm<br>RFA-02-C2M2-SMA-D034 | Alead/Aristotle 2 Dipole x SMA to U.FL<br>cable length of<br>100 mm<br>10 |RN-SMA-S-RP Microchip 0.56 Dipole x x x |RP-SMA) to<br>U.FL cable length<br>of 100 mm<br>11 |RN-SMA-S Microchip 0.56 Dipole x SMA to U.FL<br>cable length of<br>100 mm<br>**----- End of picture text -----**<br>
- Note 1: ‘x’ denotes the antennas covered under the certification.
- 2: If the end-product using the Module is designed to have an antenna port that is accessible to the end-user than a unique (non-standard) antenna connector (as permissible by FCC) must be used (e.g., RP (Reverse Polarity)-SMA socket).
- 3: If an RF coaxial cable is used between the module RF output and the enclosure, than a unique (non-standard) antenna connector must be used in the enclosure wall to interface with antenna.
- 4: Contact the antenna vendor for detailed antenna specifications to review its suitability to the end-product operating environment and to identify alternatives.
3.7 WFI32E01 Module Reflow Profile flows, apply the module on the final flow. Information 3.7.1 CLEANING The WFI32E01 module was assembled using the IPC/ The Exposed GND pad helps to self-align the module, JEDEC J-STD-020 Standard lead free reflow profile. avoiding pad misalignment. The use of no clean solder The WFI32E01 module can be soldered to the host pastes is recommended. Full drying of no-clean paste board using standard leaded or lead free solder reflow fluxes as a result of the reflow process must be profiles. To avoid damaging the module, adhere to the ensured. This may require longer reflow profiles and/or following recommendations: peak temperatures toward the high end of the process ¢ For Solder Reflow Recommendations, refer to the window as recommended by the solder paste vendor. Solder Reflow Recommendation Application Note The uncured flux residues may lead to corrosion and/or (AN233). shorting in accelerated testing and possibly the field.
- ¢ Do not exceed a peak temperature (TP) of 250°C.
* Refer to the solder paste data sheet for specific 3.8 WFI32E01 Module Assembly reflow profile recommendations from the vendor. Considerations ¢ Use no-clean flux solder paste. ; ; * Do not wash as moisture can be trapped under the The WFI32E01 module IS assembled with an EMI shield. shield to ensure compliance with EMI emission and » Use only one flow. If the PCB requires multiple immunity rules. The EMI shield is made of a tin-plated renner eee e rereerence eee eee DS70005425A-page 42 Preliminary Data Sheet © 2020 Microchip Technology Inc.
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steel (SPTE) and is not hermetically sealed. Solutions such as IPA and similar solvents can be used to clean this module. Cleaning solutions containing acid must never be used on the module.
## 3.8.1 CONFORMAL COATING
The modules are not intended for use with a conformal coating and the customer assumes all risks (Such as the module reliability, performance degradation and so on) if a conformal coating is applied to the modules.
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- 4.0 CPU - Separate priority and vector generation. Note 1: This- data sheet summarizes- the fea-« iardWare.assisheommbined16-bit vector address is provided.withitheuse of HORE of the PIC32MZ W1 family of shadow register sets to reduce interrupt devices. It is not intended to be a latency during the prologue and epilogue of comprehensive reference source. To an interrupt ; complement the information in this data . . . sheet. refer to Section 50. “CPU for Devices with MIPS32® microAptiv™ - AnSPS interrupt arereturn eae with automated interrupt and M-Class Cores” (DS60001192) of impreses Inieruptiatengy:, = the “PIC32 Family Reference Manual”, - Supports optional interrupt chaining. which is available from the Microchip - Two memory-to-memory atomic read-modifywebsite (www.microchip.com/PIC32). write instructions (ASET and ACLR) eases
- 5: The Series § Warlor'lWielass CPL wars commonly used semaphore manipulation in . FeROlITGES are available at MCU applications. Interrupts are automati. cally disabled during the operation to main-
- www.imgtec.com . . : tain coherency.
- The MIPS32® M-Class Microprocessor Core is the ¢ MMU with simple FMT mechanism: heart of the PIC32MZ W1. The CPU fetches instruc- FMT performs virtual-to-physical address tions, decodes each instruction, fetches source opertranslation ands, axeoules eacdnsinustion! ang! writes Heireselts - Provides attributes for the different segments of instruction execution to the proper destinations. . . Key features ;include: * -Separate16 KbyteL14 waydata andset associativeinstruction caches:instruction cache ¢ 5-stage pipeline (Il-Cache) ¢ 32-bit address and data paths - 16 Kbyte 4 way set associative data cache (D« MIPS32 enhanced architecture (release 5): Cache) - Multiply-accumulate and multiply-subtract * Autonomous Multiply/Divide Unit (MDU): instructions - Maximum issue rate of one 32x32 multiply per clock
- - Targeted multiply instruction - Early-in iterative divide. Minimum 12 and - Zero/onedetectinstructions maximum 38 clock latency (dividend (rs) sign - WATT instruction extension-dependent) - Conditional move instructions (MOVN, MOVZ) . Pawer control: - Vectored interrupts - Minimum frequency: 0 MHz - Programmable exception vector base - Low-Power mode (triggered by WATT instruction) - Atomic interrupt enable/disable - Extensive use of local gated clocks - GPR shadow registers to minimize latency for » EJTAG debug ane hasieiasaaual trace: interrupt handlers - Support for single stepping
- - Bit field manipulation instructions - Virtual instruction and data address/value - Virtual memory support preskpaiits ;
- + microMIPS™ compatible instruction set:; - Hardware breakpoint supports both address ; . . match and address range triggering.
- - Improves code size density over MIPS32, while ; : : maintaining MIPS32 performance. - Eight instruction and four data complex
- - Supports all MIPS32 instructions (except branch. breakpointsi ® . . likely instructions) ¢ iFlowtrace~ version 2.0 support:
- - Fifteen additional 32-bit instructions and thirty° Rearime IpSHUBHES pieeran cuniel nine 16-bit instructions corresponding to com- Special events trace capability monly-used MIPS32 instructions - Two performance counters with 34 user-
- - Stack Pointer implicit in instruction selectable countable events - MIPS32 assembly and Application Binary Inter- Disabled if the processor enters Debug mode face (ABI) compatible - Program counter sampling
- ¢« MIPS32 ISA mode for legacy compatibility ¢ Eight watch registers: * MCU ASE 1(Application Specific Extension 1): - Instruction, data read, data write options - Increases the number of interrupt hardware - Address match masking options inputs from 6 to 8 for Vectored Interrupt (VI) « DSP ASE extension: mode, and from 63 to 255 for External - Native fractional format data type operations Interrupt Controller (EIC) mode. - Register Single Instruction Multiple Data (SIMD)
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## PIC32MZ W1 and WFI32E01 Family seman
operations (add, subtract, multiply, and shift)
- GPR-based shift
- - Bit manipulation - Compare-pick - DSP control access - Indexed-load
- Branch
- Multiplication of complex operands
- - Variable bit insertion and extraction - Virtual circular buffers - Arithmetic saturation and overflow handling - Zero-cycle overhead saturation and rounding operations
A block diagram of the PIC32MZ W1 processor core is shown in Figure 4-1.
## FIGURE 4-1: PIC32MZ W1 MICROPROCESSOR CORE BLOCK DIAGRAM
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ff OO "M-Class Microprocessor Core. To \<br>| |<br>SYS_CLK- | (MIPs32%micromips™), LI]microMIPS Controllerome |<br>|<br>|Execution Unit (1,2,4,8,162 A816 sets) MMU BIU |<br>| (FMT) <> System Bus<br>| Atomic/LdStALU/Shift Enhanced(with DSP MDU ASE) |<br>| DSP ASE |<br>D-Cache<br>| Controller |<br>| Debug/Profiling |<br>System System Break Points |<br>Interface Coprocessor iFlowtrace<br>Interrupt | PerformanceFast Debug ChannelCounters |<br>Interface Sampling Management |<br>Secure Debug<br>% 7<br>2-wire Debug<br>**----- End of picture text -----**<br>
4.1 Architecture Overview thirty-two 32-bit GPRs used for integer operations and . . The address calculation. Seven additional register file MIPS32 M-Class Microprocessor Core in ; shadow sets (containing 32 registers) are added to PIC32MZ W1 contains several logic blocks working minimize context switching overhead during interrupt/ together in parallel, providing an efficient high-perforexception processing. The register file consists of two mance computing engine. The following blocks are read ports and one write port and is fully bypassed to included with the core: minimize operation latency in the pipeline.
- Execution unit
- ° ss a gchaae it ach — lb pasiivicte nits )
- ¢ System control coprocessor (CPO)
- Memory Management Unit (MMU)
- Instruction/data cache controllers
- ¢ Power management
- Instructions and data caches
- microMIPS support
- Enhanced JTAG (EJTAG) controller
## 4.1.1 EXECUTION UNIT
The execution unit includes:
- ¢ 32-bit adder for calculating the data address ¢ Address unit for calculating the next instruction
- address
- ¢ Logic for branch determination and branch target address calculation
- e Load aligner
- Trap condition comparator
- Bypass multiplexers for avoiding stalls when executing instruction streams where data producing instructions are followed closely by results
The processor core execution unit implements a load/ store architecture with single-cycle Arithmetic Logic Unit (ALU) operations (logical, shift, add, subtract) and an autonomous multiply/divide unit. The core contains
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« Leading zero/one detect unit for implementing the ber shown (‘32’ of 32x32) represents the rs operand. CLZ and CLO instructions The second number (‘32’ of 32x32) represents the rt ¢ ALU for performing arithmetic and bitwise logical operand. * operations . The MDU supports execution of one multiply or Shifter and store aligner ; multiply-accumulate operation every clock cycle. * DSP ALU and logic block for performing DSP Divide operations are implemented with a simple 1-bitinstructions, such as arithmetic/shift/compare per-clock iterative algorithm. An early-in detection operations checks the sign extension of the dividend (rs) operand. 4.1.2 If rs is 8 bits wide, 23 iterations are skipped. For a 16MULTIPLY/DIVIDE UNIT bit wide rs, 15 iterations are skipped and for a 24-bit The processor core includes an MDU that contains a wide rs, 7 iterations are skipped. Any attempt to issue separate pipeline for multiply and divide operations, a subsequent MDU instruction while a divide is still and DSP ASE multiply instructions. This pipeline operactive causes an IU pipeline stall until the divide ates in parallel with the Integer Unit (IU) pipeline and operation is completed. does not stall when the IU pipeline stalls. This allows Table 4-1 lists the repeat rate (peak issue rate of cycles MDU operations to be partially masked by system stalls until the operation can be reissued) and latency (numand/or other integer unit instructions. ber of cycles until a result is available) for the processor The high-performance MDU consists of a 32x32 booth core multiply and divide instructions. The approximate recoded multiplier, four pairs of result/accumulation latency and repeat rates are listed in terms of pipeline registers (HI and LO), a divide state machine, and the clocks. necessary multiplexers and control logic. The first num-
## 4.1.2
TABLE 4-1: MIPS32® M-CLASS MICROPROCESSOR CORE HIGH-PERFORMANCE INTEGER MDU LATENCIES AND REPEAT RATES MSUB/MSUBU (HULO destination) [32 bits NUL (GPR destination 16 bits 32 bits pIv/DIvo 12114 124 16 bits 20/22 20/22 24 bits 28/30 28/30 32 bits 36/38 36/38 The MIPS architecture defines that the result of a The MDU also implements various shift instructions multiply or divide operation be placed in one of four operating on the HI/LO register and multiply instrucpairs of HI and LO registers. Using the Move-From-HI tions as defined in the DSP ASE. The MDU supports all (MFHI) and Move-From-LO (MFLO) instructions, these of the data types required for this purpose and includes values can be transferred to the GPR. three extra HI/LO registers as defined by the ASE. In addition to the HI/LO targeted operations, the Table 4-2 lists the latencies and repeat rates for the MIPS32 architecture also defines a Multiply instrucDSP multiply and dot-product operations. The approxition (MUL), which places the least significant results mate latencies and repeat rates are listed in terms of in the primary register file instead of the HI/LO regispipeline clocks. ter pair. By avoiding the explicit MFLO instruction required when using the LO register, and by supportTABLE 4-2: DSP-RELATED LATENCIES ing multiple destination registers, the throughput of AND REPEAT RATES multiply-intensive operations is increased. Two . . . Repeat other instructions, Multiply-Add (MADD) and Opcode Latency] pate Multiply-Subtract (MSUB), are used to perform the —————S————==—=—_—_— multiply-accumulate and multiply-subtract operations. Multiply and dot-product without The MADD instruction multiplies two numbers and then saturation after accumulation adds the product to the current contents of the HI and Multiply and dot-product with 5 1 LO registers. Similarly, the MSUB instruction multiplies saturation after accumulation two operands and then subtracts the product from the Multiply without accumulation HI and LO registers. The MADD and MSUB operations are commonly used in DSP algorithms. reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 47
## PIC32MZ W1 and WFI32E01 Family
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4.1.3 SYSTEM CONTROL disabled. Configuration information, such as cache COPROCESSOR (CP0) size and set associativity, and the presence of options In the MIPS architecture, CPO is responsible for the ie mnisroM FS = ales availabe by aooRBsing allies : : : registers, as listed in Table 4-3. Refer to the Series 5 ViNUalcols, the6: paiieleaexceptionESBScontrol hetisiauenianiasystem, the eensprocessor’s RGIS Warrior: M-class: CPU core resources‘ which: are availdiagnostics capability, the operating modes (Kernel, BEE SL Sr aaeeROn EN OFS Ilene, User and Debug) and whether interrupts are enabled or TABLE 4-3: COPROCESSOR 0 REGISTERS Register Register : (MPUony,SSSCSCSCS~C~*@d PO [index __[indexinto the TLB array UserLocal User information that can be written by privileged software and read through the RDHWR instruction. [6 [WirPag **e** Graind | ofControls 1 KB pagesthe number in the TLB (MPUof fxed (Le, only). wired) TLB entries (MPU ony). ——SSSSSC—=*S Non-privileged mode. —C—“‘*~C‘“‘C;*~* [8 [Count [Processorcyclecount. 2 extracting or inserting that bit from/to the Status register. set number to use when servicing such an interrupt. 3 exception. 4 | [RsamaeDs — [eaaha the tear og coUna ia aia ar We cnenramapn — 15 [PRID_____|Processoridentification andrevision CS renner eee e rereerence eee eee DS70005425A-page 48 Preliminary Data Sheet © 2020 Microchip Technology Inc.
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## TABLE 4-3: COPROCESSOR 0 REGISTERS (CONTINUED)
|Register|Register|Register|Register||'|
|---|---|---|---|---|---|
||16|||||
||23|||||
|2A——<br>25|||||es|
|||||(MPU only).||
|||31|Fess—||[Serene<br>erated||
## 4.2 Power Management
The processor core offers a number of power management features, including low-power design, active power management and power-down modes of operation. The core is a static design that supports slowing or halting the clocks, which reduces system power consumption during Idle periods.
## 4.2.2 LOCAL CLOCK GATING
The majority of the power consumed by the processor core is in the clock tree and clocking registers. The PIC32MZ W1 family makes extensive use of local gated-clocks to reduce this dynamic power consumption.
## 4.3 L1 Instruction and Data Caches
4.2.1 INSTRUCTION-CONTROLLED POWER MANAGEMENT 4.3.1 INSTRUCTION CACHE (I-CACHE) The mechanism for invoking Power-Down mode is The I-Cache is an On CoreneEMOny, block of 16 Kbytes. through execution of the WAIT/SLEEP instruction. For As the I-Cache is virtually indexed, the Virtual-tomore information on power management, see physical address translation occurs in parallel with the Section 36.0 “Power-Saving Features”. cache access rather than having to wait for the physical address translation. The tag holds 22 bits of physical address, a valid bit, and a lock bit. The Least Recently Used (LRU) replacement bits are stored in a separate array. reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 49
## PIC32MZ W1 and WFI32E01 Family seman
The I-Cache block also contains and manages the standard JTAG instructions, special instructions instruction line fill buffer. Besides accumulating data to defined in the EJTAG specification specify which be written to the cache, instruction fetches that referregisters are selected and how they are used. ence data in the line fill buffer are serviced either by a bypass of that data, or data coming from the external 4.5 MIPS DSP ASE Extension a He Series eee sarees The MIPS DSP ASE Revision 2 is an extension to the . MIPS32 architecture. This extension comprises new The processor core supports I-Cache locking. Cache integer instructions and states that include new HI/LO locking allows critical code or data segments to be accumulator register pairs and a DSP control register. locked into the cache on a per-line basis, enabling the This extension is crucial in a wide range of DSP, system programmer to maximize the efficiency of the multimedia, and DSP-like algorithms covering audio system cache. and video processing applications. The extension The cache locking function is always available on all supports native fractional format data type operations, |-Cache entries. Entries can then be marked as register SIMD operations, such as add, subtract, locked or unlocked on a per entry basis using the multiply, and shift. In addition, the extension includes CACHE instruction. the following features that are essential in making DSP algorithms computationally efficient: 4.3.2 DATA CACHE (D-CACHE) ¢ Support for multiplication of complex operands The D-Cache is an on-core memory block of ¢ Variable bit insertion and extraction 16 Kbytes. This virtually indexed, physically tagged * Implementation and use of virtual circular buffers cache is protected. As the D-Cache is virtually indexed, » Arithmetic saturation and overflow handling the virtual-to-physical address translation occurs in support parallel with the cache access. The tag holds 22 bits of . . physical address, a valid bit, and a lock bit. There is an ous cycle venice’ satanalia and nsereding additional array holding dirty bits and LRU replacement poisons algorithm bits for each set of the cache. . In addition. to |-Cache locking,; the processor core also 4.6 microMIPS ISA supports a D-Cache locking mechanism identical to the The processor core supports the microMIPS ISA, |-Cache. Critical data segments are locked into the which contains all MIPS32 ISA instructions (except for cache ona per-line basis. The locked contents can be branch-likely instructions) in a new 32-bit encoding updated on a store hit, but cannot be selected for scheme, with some of the commonly used instructions replacement on a cache miss. also available in 16-bit encoded format. This ISA The D-Cache locking function is always available on improves code density through the additional 16-bit all D-Cache entries. Entries can then be marked as instructions while maintaining a performance similar to locked or unlocked on a per-entry basis using the MIPS2 made: In mioMiPs meds, 1é-bi. or 32-bit CACHE instruction. instructions will be fetched and recoded to legacy MIPS32 instruction opcodes in the pipeline’s | stage, so 4.3.3 ATTRIBUTES that the processor core can have the same microAptiv The processor core I-Cache and D-Cache attributes UP microarchitecture. The microMIPS[_][instruction] are listed in the Configuration registers (see stream can be intermixed with 16-bit halfword or 32-bit Register 4-1 through Register 4-4). word size instructions on halfword or word boundaries, additional logic is in place to address the word mis4.4 EJTAG Debug Support alignment issues, thus minimizing performance loss. The processor core provides for an Enhanced JTAG (EJTAG) interface for use in the software debug of application and kernel code. In addition to standard User mode and Kernel modes of operation, the processor core provides a Debug mode that is entered after a debug exception (derived from a hardware breakpoint, single-step exception, and so on) is taken and continues until a Debug Exception Return (DERET) instruction is executed. During this time, the processor executes the debug exception handler routine.
The EJTAG interface operates through the Test Access Port (TAP), a serial communication port used for transferring test data in and out of the core. In addition to the
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## 4.7 M-Class Core Configuration
Register 4-1 through Register 4-4 show the default configuration of the M-Class core, which is included on the PIC32MZ W1.
## REGISTER 4-1: CONFIG: CONFIGURATION REGISTER; CPO REGISTER 16, SELECT 0
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Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0<br>ecey Seee ee ee<br>| a a<br>yg@a ROeeeUT: ORO CUT RAT RO Rt CT RO RO<br>ea ae[BETeee a ae<br>Legend: r = Reserved bit<br>R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’<br>-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown<br>**----- End of picture text -----**<br>
- bit 31 Reserved: This bit is hardwired to '1' to indicate the presence of the Config1 register. bit 30-25 Unimplemented: Read as ‘0’.
- bit 24 ISP: Instruction Scratch Pad RAM bit
- 0 = Instruction scratch pad RAM is not implemented
- bit 23 DSP: Data Scratch Pad RAM bit
- 0 = Data scratch pad RAM is not implemented
- bit 22 UDI: User-defined bit 0 = CorExtend user-defined instructions are not implemented
- bit 21 SB: SimpleBE bit 1 = Only simple byte enables are allowed on the internal bus interface
- bit 20 MDU: Multiply/Divide Unit bit 0 = Fast, high-performance MDU
- 1 = Iterative, area-efficient MDU
- bit 19 Unimplemented: Read as ‘0’ bit 18-17 MM[1:0]: Merge Mode bits 10 = Merging is allowed x1 = Reserved
- bit 16 BM: Burst Mode bit
- 0 = Burst order is sequential
- bit 15 BE: Endian Mode bit
- 0 = Little-endian
- bit 14-13 AT[1:0]: Architecture Type bits 00 = MIPS32
- bit 12-10 AR[2:0]: Architecture Revision Level bits 001 = MIPS32 release 2
- bit 9-7 MT[2:0]: MMU Type bits 011 = Fixed Mapping
- bit 6-3 Unimplemented: Read as ‘0’
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 51
PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 4-1: CONFIG: CONFIGURATION REGISTER; CPO REGISTER 16, SELECT 0 (CONTINUED)
- bit 2-0 KO[2:0]: KsegO Coherency Algorithm bits
- 011 = Cacheable, non-coherent, write-back, write allocate 010 = Uncached
- 001 = Cacheable, non-coherent, write-through, write allocate
- 000 = Cacheable, non-coherent, write-through, no write allocate
All other values are not used and mapped to other values. 100, 101, and 110 are mapped to 010. 111 is mapped to 010.
renner eee e rereerence eee eee DS70005425A-page 52 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
## REGISTER 4-2: CONFIG1L: CONFIGURATION REGISTER 1
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**----- Start of picture text -----**<br>
Bit Bit Bit Bit Bit Bit Bit Bit Bit<br>Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0<br>sivg LRT ROT ROT RO | RO TROT RO | RO<br>a a eeee<br>P Rt ROeePF Rt of RtRo | ROT RtRA TRRo<br>| ise PRO | ee ee Te<br>- pai [| voy] uo [ at] et] Ro | ma || [RO]<br>[| ro | pa ro |e ea|<br>Legend: r = Reserved bit<br>R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’<br>-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown<br>**----- End of picture text -----**<br>
- bit 31 Reserved: This bit is hardwired to a ‘1’ to indicate the presence of the Config2 register. bit 30-25 Unimplemented: Read as ‘0’ bit 24-22 IS[2:0]: Instruction Cache Sets bits Ox2: 256 Ox5 - 0x7: Reserved
- bit 21-19 IL[2:0]: Instruction-Cache Line bits 000 = No I-Cache present 011 = Contains instruction cache line size of 16 bytes 0x1, Ox2, 0x4 - 0x7: Reserved
- bit 18-16 IA[2:0: Instruction-Cache Associativity bits 0x00 - 0x02: Reserved 0x3: 4-way 0x4 - 0x7: Reserved
- bit 15-13 DS[2:0]: Data-Cache Sets bits Ox2: 256 0x5 - 0x7: Reserved
- bit 12-10 DL[2:0]: Data-Cache Line bits 0x0: No D-Cache present 0x3: 16 bytes 0x1, Ox2, 0x4 - 0x7: Reserved
- bit 9-7 DA[2:0]: Data-Cache Associativity bits 0x00 - 0x02: Reserved 0x3: 4-way 0x4 - 0x7: Reserved
- bit 6-5 Unimplemented: Read as ‘0’ bit 4 PC: Performance Counter bit 1 = The processor core contains
- bit 3 WR: Watch Register Presence bit 1 = No Watch registers are present
- 1 = The processor core contains performance counters
- bit 2 CA: Code Compression Implemented bit 0 = No MIPS 16e® present
- bit 1 EP: EJTAG Present bit
- 1 = Core implements EJTAG
- bit 0 FP: Floating Point Unit bit 0 = No FPU
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 53
PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 4-3: CONFIG3: CONFIGURATION REGISTER 3; CPO REGISTER 16, SELECT 3
|Bit|Bit|Bit|Bit<br>Bit|Bit<br>Bit<br>Bit<br>Bit|
|---|---|---|---|---|
|com|a<br> (AR {RE<br>Seen<br>ico<br>IsONEXT |||||
|pro|**P**_isaor™ue [_RxT__[_sep[s**e**p[Oi mC!<br>ee fet fs fe fe<br>fee<br>Pura [vec fv<br>[SO<br>S|~comm |<br>|<br>| COU||||
|Legend:|||r = Reserved bit|y = Value set from Configuration bits on POR|
|R = Readable bit|||W = Writable bit|U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR|||‘1’=Bitisset|‘0’=Bitiscleared<br>x=Bitisunknown|
bit 31 Reserved: This bit is hardwired as ‘1’ to indicate the presence of the Config4 register. bit 30-23 Unimplemented: Read as '0'
- bit 22-21 IPLW[1:0]: Width of the Status IPL and Cause RIPL bits 01 = |IPL and RIPL bits are 8-bits in width
- Others = Reserved
- bit 20-18 MMAR[2:0]: microMIPS Architecture Revision Level bits
- 000 = Release 1
- Others = Reserved
- bit 17 MCU: MIPS® MCU™ ASE Implemented bit 0 = MCU ASE is not implemented 1 = MCU ASE is implemented
- bit16 | ISAONEXC: ISA on Exception bit() 1 = microMIPS is used on entrance to an exception vector
- 0 = MIPS32 ISA is used on entrance to an exception vector
- bit 15-14 ISA[1:0]: Instruction Set Availability bits‘)
- 00 = Only MIPS32 is implemented
- 01 = Only microMIIPS is implemented
- 11 = Both MIPS32 and microMIPS are implemented; microMIPS is used when coming out of Reset
- 10 = Both MIPS32 and microMIPS are implemented; MIPS32 ISA used when coming out of Reset
- bit 13 ULRI: UserLocal Register Implemented bit 1 = UserLocal Coprocessor 0 register is implemented
- bit 12 RXI: RIE and XIE Implemented in PageGrain bit 0 = RIE and XIE bits are not implemented
- 1 =RIE and XIE bits are implemented
- bit 11 DSP2P: MIPS DSP ASE Revision 2 Presence bit 1 = DSP revision 2 is present
- bit 10 DSPP: MIPS DSP ASE Presence bit 1 = DSP is present
- bit 9 Unimplemented: Read as '0' bit 8 ITL: Indicates that iFlowtrace® hardware is present 1 =iFlowtrace® is implemented in the core
- bit 7 LPA: Denotes the presence of support for large physical addresses on MIPS64 processors. Not used by MIPS32 processors and returns zero on read.
- 0 = Large physical address support is not implemented
- bit 6 VEIC: External Vector Interrupt Controller bit
- 1 = Support for an external interrupt controller is implemented
- bit 5 VINT: Vector Interrupt bit
- 1 = Vector interrupts are implemented
Note 1: These bits are set based on the value of the BOOTISA Configuration bit (BCFGO[3]).
renner eee e rereerence eee eee DS70005425A-page 54 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## REGISTER 4-3: CONFIG3: CONFIGURATION REGISTER 3; CPO REGISTER 16, SELECT 3 (CONTINUED)
bit 4 Unimplemented: Read as '0' bit 3 CDMM: Common Device Memory Map bit 0 = CDMM is not implemented 1 = CDMM is implemented bit 2-1 Unimplemented: Read as '0' bit 0 TL: Trace Logic bit 1 = Trace logic is implemented Note 1: These bits are set based on the value of the BOOTISA Configuration bit (BCFGO[3]).
© 2020 Microchip Technology Inc. Preliminary Data Sheet
DS70005425A-page 55
PIC32MZ W1 and WFI32E01 Family
## seman
REGISTER 4-4: CONFIG5: CONFIGURATION REGISTER 5; CPO REGISTER 16, SELECT 5
Bit Bit Bit Bit Bit Bit Bit Bit Bit Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0 a a pe ee Oe Ee ee _ bE es ee Ee es esses Legend: r = Reserved R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 M: This bit is reserved to indicate that a Config5 register is present. With the current architectural definition, this bit should always read as a 0.
bit 30-1 Unimplemented: Read as '0' bit 0 NF: Nested Fault bit 1 = Nested Fault feature is implemented
REGISTER 4-5: CONFIG7: CONFIGURATION REGISTER 7; CPO REGISTER 16, SELECT 7
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**----- Start of picture text -----**<br>
Bit Bit Bit Bit Bit Bit Bit Bit Bit<br>Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0<br>[ae |! eS ee Ee Eee Se<br>8) eee [ee]<br>Legend:<br>R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’<br>-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown<br>**----- End of picture text -----**<br>
bit 31 WII: Wait IE Ignore bit 1 = Indicates that this processor will allow an interrupt to unblock a WAIT instruction bit 30-0 Unimplemented: Read as ‘0’
renner eee e rereerence eee eee DS70005425A-page 56 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
## 5.0 FLASH PROGRAM MEMORY
- Note: This data sheet summarizes the features of the PIC32MZ W1 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 5. Flash Programming (DS60001640) in the “PIC32MZ W1 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
: : : PIC32MZ W1 device contains an internal Flash program memory for executing user code, which includes the following features:
RTSP is performed by software, executing from either Flash or RAM memory. Information about RTSP techniques is available in Section 5. Flash Programming (DS60001640) in the “PIC32MZ W1 Family Reference Manual”. EJTAG is performed using the EJTAG port of the device and an EJTAG capable programmer. ; ; ; ; ICSP is performed using a serial data connection to the device and allows much faster programming times than RTSP.
The EJTAG and ICSP methods are described in the “PIC32 Flash Programming Specification” (DS60001145), which is available for download from the Microchip web site (www.microchip.com).
- ¢ Write protection for program and boot Flash
- ¢ Error-correction code (ECC) support
- Supports chip and page erase
- Supports Single Word, Quad Word and row program options
- « Flash page size is 4 Kbytes (1K Instruction Word (IW))
- ¢ Row size is 1 KB (256 IW)
The user can program this memory using the following methods:
- ¢ Run-Time Self-Programming (RTSP)
- Enhanced JTAG (EJTAG) programming
- ¢ In-Circuit Serial Programming™ (ICSP™)
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 57
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**----- Start of picture text -----**<br>
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PIC32MZ W1 and WFI32E01 Family
## smn
**==> picture [316 x 8] intentionally omitted <==**
**----- Start of picture text -----**<br>
REGISTER 5-1: NVMCON: PROGRAMMING CONTROL REGISTER<br>**----- End of picture text -----**<br>
**==> picture [448 x 164] intentionally omitted <==**
**----- Start of picture text -----**<br>
Range | 31/23/15/7 | 30/22/14/6 29/21/13/5 =| 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0<br>a a es ee<br>EEE ES ESS Es eee Ee Es es<br>Pwr [wren | wrerr® | woerr[— | — | = _| HToPw |<br>orc<br>Legend: HC = Hardware Set HC = Hardware Cleared<br>R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’<br>-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown<br>**----- End of picture text -----**<br>
bit 31-16 Unimplemented: Read as ‘0’
- bit15 | WR: Write Control Bit!
- 1 = Initiate a Flash operation. Hardware clears this bit when the operation completes. 0 = Flash operation complete or inactive. Note: This field can only be modified when WREN = 1, TEMP = 1, and the NVMKEY unlock sequence is satisfied.
- bit14. = WREN: Write Enable Bit")
- 1 = Enables writes to WR
- 0 = Disables writes to WR
- bit13 = WRERR: Write Error Bit!)
- 1 = Program or erase sequence does not complete successfully
- 0 = Program or erase sequence completed normally
- Note: Cleared by setting NVMOP == 0000b and initiating a Flash operation (WR).
- bit12 | LWVDERR: Low-voltage Detect Error Bit") The error is only captured for programming/erase operations (when WR= 1).
- 1 = Low-voltage is detected (possible data corruption if WRERR is set) 0 = Normal voltage is detected
- Note: Cleared by setting NVMOP == 0000b and initiating a Flash operation (WR).
- bit 11-9 Unimplemented: Read as ‘0’
- bit 8 HTDPGM: High Temperature Detected during Program/Erase Operation bit This status is only captured for programming/erase operations (when WR= 1). 1 = High temperature is detected (possible data corruption, verify operation) 0 = High temperature is not detected
- Note: Cleared by setting NVMOP == 0000b and initiating a Flash operation (WR)
- bit 7-4 Unimplemented: Read as ‘0’
- Note 1: These bits are only reset by a POR and are not affected by other Reset sources.
- 2: This operation results in a No Operation (NOP) when the Dynamic Flash ECC Configuration bits = 00 (FECCCON|[1:0] (CFGCONO[299:28])), which enables ECC at all times. For all other FECCCON[1:0] bit settings, this command will execute, but will not write the ECC bits for the Word and can cause DED errors if dynamic Flash ECC is enabled (FECCCON[1:0] = 01).
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 59
## PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 5-1: NVMCON: PROGRAMMING CONTROL REGISTER (CONTINUED)
bit 3-0 NVMOPJ[3:0]: NVM Operation bits These bits are only writable when WREN = 0.
- 1111 = Reserved
1000 = Reserved
0111 = Program erase operation: erase all of program Flash memory (all pages must be unprotected) 0110 = Upper program Flash memory erase operation: erases only the upper mapped region of program Flash (all pages in that region must be unprotected)
0101 = Lower program Flash memory erase operation: erases only the lower mapped region of program Flash (all pages in that region must be unprotected)
- 0100 = Page erase operation: erases page selected by NVMADDR,, if it is not write-protected 0011 = Row program operation: programs row selected by NVMADDR,, if it is not write-protected 0010 = Quad Word (256-bit) program operation: programs the 256-bit Flash Word selected by NVMADDR,, if it is not write-protected 0001 = Word program operation: programs Word selected by NVMADDER,, if it is not write-protected(2) 0000 = No operation
- Note 1: These bits are only reset by a POR and are not affected by other Reset sources.
- 2: This operation results in a No Operation (NOP) when the Dynamic Flash ECC Configuration bits = 00 (FECCCON[1:0] (CFGCONO[299:28])), which enables ECC at all times. For all other FECCCON[1:0] bit settings, this command will execute, but will not write the ECC bits for the Word and can cause DED errors if dynamic Flash ECC is enabled (FECCCON[1:0] = 01).
renner eee e rereerence eee eee DS70005425A-page 60 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
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**----- Start of picture text -----**<br>
REGISTER 5-2: NVMCON2: PROGRAMMING CONTROL2 REGISTER<br>**----- End of picture text -----**<br>
|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit|
|---|
|Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 |28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0|
|“i<br>ee<br>SS~—“—tCS*ésSC“‘“ SSS Cd<br>CdYCS|
|es<br>esG2)|
|° [>=] tewe J oreani_[vrei|<br>| SOOd)|
|Legend:<br>HC = Hardware Set<br>HC = Hardware Cleared|
|R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR<br>‘1’=Bitisset<br>‘0’=Bitiscleared<br>x=Bitisunknown|
- bit 31-28 ERS[3:0]: Erase Retry State
These bits are used by software to track the software state of the erase retry procedure in the event of a system Reset (MCLR) or brown out Reset event.
- bit 27-25 Unimplemented: Read as ‘0’
- bit 24 SLEEP: Power Down in Sleep bit 1 = Configures Flash for power down when the system is in Sleep mode
- 0 = Configures Flash for standby when the system is in Sleep mode
- Note: This field can only be modified when the NVMKEY unlock sequence is satisfied.
- bit 23-21 Unimplemented: Read as ‘0’
- bit 20-16 WS[4:0]: Flash Access Wait State Control for VREAD1 = 1 11111 = 31 wait states (32 total system clocks) 11110 = 30 wait states (31 total system clocks)
00010 = 2 wait states (3 total system clocks)
00001 = 1 wait state (2 total system clocks) 00000 = 0 wait state (1 total system clock)
- Note 1: When VREAD1 = 1, WSJ] only affects the panel containing NVMADDRJ].
- 2: This field can only be modified when the NVMKEY unlock sequence is satisfied.
- bit 15 Unimplemented: Read as ‘0’
- bit 14 TEMP: Operating Temperature Control bit
- 1 = Configures Flash for standard temperature, low latency reads
- 0 = Configures Flash for high temperature, high latency reads
- Note 1: When TEMP= 0, all NVMOP Operations are disabled because NVMWR cannot be written to ‘1’. 2: When TEMP= 0, firmware must adjust Flash wait state control at the system level. 3: This field can only be modified when NVMCON.WR == 0 and the NVMKEY unlock sequence is satisfied.
- bit 13 CREAD1: Compare Read of Logic 1 bit
- Compare read 1 causes all bits in a Flash Word (including ECC if it exists) to be evaluated during the read. If all bits are 1, the lowest Word in the Flash Word evaluates to 0x0000_0001, all other Words are 0x0001_ 0000. If any bit is 0, the read evaluates to Ox0000_0000 for all Words in the Flash Word.
- 1 = Compare read enabled, only if VREAD1 = 1
- 0 = Compare read disabled
- Note 1: When using erase retry in an ECC Flash system, CREAD1 = 1 must be used.
- 2: This field can only be modified when the NVMKEY unlock sequence is satisfied.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 61
## PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 5-2: NVMCON2: PROGRAMMING CONTROL2 REGISTER (CONTINUED)
- bit 12 VREAD1: Verify Read of Logic 1 Control bit 1 = Selects erase retry procedure with verify read
- 0 = Selects single erase without verify read
- Note 1: When VREAD1 = 1, Flash wait state control is from WS{] for the panel containing NVMADDRJ]. 2: Using erase retry and verify read procedure increase life of Flash panel(s).
- 3: This field can only be modified when NVMCON.WR == 0 and the NVMKEY unlock sequence is satisfied.
- bit 11 Unimplemented: Read as ‘0’ bit 10 Unimplemented: Read as ‘0’
- bit 9-8 RETRY[1:0]: Erase Retry Control bit, only used when VREAD1 = 1 11 = Erase strength for last retry cycle 10 = Erase strength for third retry cycle
- 01 = Erase strength for second retry cycle 00 = Erase strength for first retry cycle
- Note: This field can only be modified when NVMCON.WR == 0.
- bit 7-0 Unimplemented: Read as ‘0’
renner eee e rereerence eee eee DS70005425A-page 62 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
## REGISTER 5-3: NVMKEY: PROGRAMMING UNLOCK REGISTER
|Bit|Bit|Bit|Bit|Bit|Bit|Bit||Bit|Bit|
|---|---|---|---|---|---|---|---|---|---|
|Range | 31/23/15/7 |30/22/14/6 | 29/21/13/5 |28/20/12/4 |27/19/11/3 | 26/18/10/2|||||||25/17/9/1||24/16/8/0|
|:||||||||||
|v6<br>:||||||||||
|as<br>:||||||||||
|-<br>:||||||||||
|Legend:||||||||||
|R = Readable bit||W|= Writable bit|U|= Unimplemented bit, read as ‘0’|||||
|-n=ValueatPOR||‘1’|=Bitisset|‘0’|=Bitiscleared||x=|Bitisunknown||
bit 31-0 NVMKEY[31:0]: Unlock Register bits
These bits are write only and read ‘0’ on any read.
Note: This register is used as part of the unlock sequence to prevent inadvertent writes to the program Flash.
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REGISTER 5-4: NVMADDR: FLASH ADDRESS REGISTER
|Bit<br>Bit|Bit<br>Bit|Bit<br>Bit|Bit|Bit|Bit|
|---|---|---|---|---|---|
|Range | 31/23/15/7 |30/22/14/6 | 29/21/13/5 |28/20/12/4 |27/19/11/3 | 26/18/10/2||||25/17/9/1|24/16/8/0|
|—<br>:||||||
|as<br>:||||||
|-<br>:||||||
|Legend:||||||
|R = Readable bit|W = Writable bit|U = Unimplemented bit,||read as ‘0’||
|-n=ValueatPOR|‘1’=Bitisset|‘0’=Bitiscleared||x=Bitisunknown||
bit 31-0 _NVMADDR[31:0]: Flash (Word) Address bits
|NVMOP{[3:0] Selection|Flash Address Bits (NVMADDR[31:0])|Flash Address Bits (NVMADDR[31:0])|
|---|---|---|
||Address identifies the page to erase.||
||Address identifies the row to program.||
|DoubleWord program|Address identifies the 64-bit DWord to program.||
||NVMADDR[2:0] bits are ignored.||
|Quad DoubleWord program _||Address identifies the 256-bitQuad DWord|to program. NVMADDR[4:0]|
||bits are ignored.||
|Note1:<br>HardwarepreventswritingtothisregisterwhenNVMCON.WR=||1.|
- 2: For all other NVMOP[3:0] bit settings, the Flash address is ignored. See the NVMCON register (Register 5-1) for additional information on these bits.
- 3: The bits in this register are only reset by a POR and are not affected by other Reset sources.
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|REGISTER 5-5:|NVMDATAx: FLASH PROGRAM DATA REGISTER|NVMDATAx: FLASH PROGRAM DATA REGISTER|NVMDATAx: FLASH PROGRAM DATA REGISTER|(x = 0-7)||||
|---|---|---|---|---|---|---|---|
|Bit<br>Bit|Bit<br>Bit|Bit|Bit|Bit||Bit|Bit|
|Range | 31/23/15/7||30/22/14/6 | 29/21/13/5 |28/20/12/4|||27/19/11/3 | 26/18/10/2||25/17/9/1||24/16/8/0|
|:||||||||
|:||||||||
|:||||||||
||||||||||
|Legend:||||||||
|R = Readable bit|W = Writable bit||U = Unimplemented bit, read as ‘0’|||||
|-n=ValueatPOR|‘1’=Bitisset||‘0’=Bitiscleared||X=|Bitisunknown||
## bit 31-0 NVMDATAx[31:0]: Flash Programming Data bits
The value in this register is written to Flash when a program operation is commanded.
Single Double Word program (64-bit)
Writes NVMDATA1:NVMDATAO to the target Flash address defined in NVMADDR.
## Quad Double Word program (256-bit)
Writes NVMDATA7:NVMDATA6:NVMDATAS:NVMDATA4:NVMDATA3:NVMDATA2:NVMDATA1 :NVMDATAO to the target Flash address defined in NVMADDR. NVMDATAO contains the Least Significant Instruction Word.
Note: Hardware prevents writing to this register when NVMCON.WR= 1.
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## seman
## REGISTER 5-6: NVMSRCADDR: SOURCE DATA ADDRESS REGISTER
|Bit|Bit|Bit|Bit|Bit|Bit|Bit||Bit|Bit|
|---|---|---|---|---|---|---|---|---|---|
|Range | 31/23/15/7 |30/22/14/6 | 29/21/13/5 |28/20/12/4 |27/19/11/3 | 26/18/10/2|||||||25/17/9/1||24/16/8/0|
||||||||||||
|:||||||||||
|:||||||||||
|:||||||||||
|Legend:||||||||||
|R = Readable bit||W|= Writable bit|U|= Unimplemented bit,||read as ‘0’|||
|-n=ValueatPOR||‘1’|=Bitisset|‘0’|=Bitiscleared||x=|Bitisunknown||
- bit 31-0 _NVMSRCADDRJ[31:0]: Source Data (Word) Address bits This is the system physical Word address of the data (in DRM) to be programmed into the Flash when NVMCON.NVMOP is set to row programming.
- Note: Hardware prevents writing to this register when NVMCON.WR= 1.
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|REGISTER 5-7:|NVMPWPLT: FLASH PROGRAM WRITE PROTECT LOWER REGISTER|
|---|---|
|Range<br>31/23/15/7 =|30/22/14/6 |29/21/13/5 |28/20/12/4 |27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0||
|P wock [= | = | = | = | = | = | = |||
|Legend:||
|R = Readable bit|W = Writable bit<br>U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR|‘1’=Bitisset<br>‘0’=Bitiscleared<br>x=Bitisunknown|
- bit 31 ULOCK: NVMPWPLT Register Unlock bit 1 =NVMPWPLT register is not locked and can be modified
- 0 =NVMPWPLT register is locked and cannot be modified
- Note 1: This field can only be modified when the NVMKEY unlock sequence is satisfied.
- 2: This field can be cleared at the same time as writing to PWPLT[23:0].
- bit 30-24 Unimplemented: Read as ‘0’
- bit 23-0 PWPLT[23:0]: Flash Program Write Protect Less Than Address Pages at Flash addresses less than this value are write protected.
- Note 1: This field can only be modified when the NVMKEY unlock sequence is satisfied, and ULOCK = 1.
- 2: This is a byte address force to align to page boundaries.
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## PIC32MZ W1 and WFI32E01 Family
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**----- Start of picture text -----**<br>
REGISTER 5-8: NVMPWPGTE: FLASH PROGRAM WRITE PROTECT GREATER REGISTER<br>Range 31/23/15/7 = | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 24/16/8/0<br>Pwo [= | = | = | = | = | = | — |<br>Legend: r = Reserved<br>R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’<br>-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown<br>**----- End of picture text -----**<br>
bit 31 ULOCK: NVMPWPGTE Register Unlock bit
- 1 = NVMPWPGTE register is not locked and can be modified
- 0 = NVMPWPGTE register is locked and cannot be modified
- Note 1: This field can only be modified when the NVMKEY unlock sequence is satisfied.
- 2: This field can be cleared at the same time as writing to PWPGTE[23:0].
- bit 30-24 Unimplemented: Read as ‘0’
- bit 23-0 PWPGTE[23:0]: Flash Program Write Protect Address bits
Pages at Flash addresses greater than or equal to this value are write protected.
- Note 1: This field can only be modified when the NVMKEY unlock sequence is satisfied, and ULOCK = 1.
- 2: This is a byte address force to align to page boundaries.
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**----- Start of picture text -----**<br>
REGISTER 5-9: NVMLBWP: FLASH LOWER BOOT WRITE PROTECT REGISTER<br>Range 31/23/15/7 =| 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 24/16/8/0<br>| utock | = | = | Uv UT hh TCU TO<br>Legend: r = Reserved<br>R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’<br>-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared X = Bit is unknown<br>**----- End of picture text -----**<br>
- bit 31 ULOCK: Lower Boot Write Protect (LBWPn) Unlock bit 1 = LBWPn bits are not locked and can be modified 0 = LBWPn bits are locked and cannot be modified
- Note 1: This field can only be modified when the NVMKEY unlock sequence is satisfied. 2: This field can be cleared at the same time as writing to LBWP[msb:Isb].
- bit 30-24 Unimplemented: Read as ‘0’
- bit 23-0 LBWP[23:0]: Lower Boot Pages Write Protect bits
- LBWP)n] = 1: Erase and write protection for upper boot page n is enabled LBWP)[n] = 0: Erase and write protection for upper boot pagen is disabled
- Note: This field can only be modified when the NVMKEY unlock sequence is satisfied, and ULOCK = 1.
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REGISTER 5-10: NVMUBWP: FLASH UPPER BOOT WRITE PROTECT REGISTER
**==> picture [453 x 166] intentionally omitted <==**
**----- Start of picture text -----**<br>
Range 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 24/16/8/0<br>| wok [SS Se Ss eee ee ee<br>Legend: r = Reserved<br>R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’<br>-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown<br>**----- End of picture text -----**<br>
- bit 31 ULOCK: Upper Boot Write Protect (UBWPn) Register Unlock bit 1 = UBWPn bits are not locked and can be modified 0 = UBWPn bits are locked and cannot be modified
- Note 1: This field can only be modified when the NVMKEY unlock sequence is satisfied. 2: This field can be cleared at the same time as writing to UBWP[msb:Isb].
bit 30-24 Unimplemented: Read as ‘0’
- bit 23-0 UBWP[23:0]: Upper Boot Pages Write Protect bits UBWP)Jn] = 1: Erase and write protection for upper boot page n is enabled UBWP)In] = 0: Erase and write protection for upper boot pagen is disabled
- Note: This field can only be modified when the NVMKEY unlock sequence is satisfied, and ULOCK = 1.
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## PIC32MZ W1 and WFI32E01 Family
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## 6.0 MEMORY ORGANIZATION
## 6.1 Memory Layout
Note: This data sheet summarizes the features PIC32MZ W1 MCUs implement two address schemes: of the PIC32MZ W1 family of devices. It is virtual and physical. All hardware resources, such as not intended to be a comprehensive program memory, data memory and peripherals, are reference source. For detailed informalocated at their respective physical addresses. Virtual tion, refer to Section 6. “Memory Organiaddresses are exclusively used by the CPU to fetch zation and Permissions” (DS60001641) and execute instructions as well as access peripherals. in the “PIC32MZ W1 Family Reference Physical addresses are used by bus master peripherManual’, which is available from the als, such as DMA and the Flash controller, that access Microchip web site (www.microchip.com/ memory independently of the CPU. PIC32). The main memory maps for the PIC32MZ W1 device is : : PIC32MZ illustrated in Figure 6-1, which provides memory map memory W1 MCUs provide 4 GB of unified virtual information for boot Flash and boot alias. program,address space. All memory regions, including Table 6-1 provides memory map information for Speters, residedatain memory,this address SFRsspace and Configurationat their respectiveregiscial Function Registers (SFRs). unique addresses. The program and data memories can be optionally partitioned into user and kernel memories. In addition, PIC32MZ W1 device allows execution from data memory.
## Key features include:
- ¢ 32-bit native data width
- Separate User (KUSEG) and Kernel (KSEGO/ KSEG1) mode address space
- ¢« Separate boot Flash memory for protected code
- ¢ Robust bus exception handling to intercept runaway code
- Cacheable (KSEGO) and non-cacheable (KSEG1) address regions
- *« Read/Write permission access to predefined memory regions
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## PIC32MZ W1 and WFI32E01 Family
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**----- Start of picture text -----**<br>
FIGURE 6-1: MEMORY MAP FOR DEVICES WITH 1024 KBYTE OF PROGRAM MEMORY, 256<br>KBYTE RAM, AND 64 KBYTE DATA BUFFER (DBF)'":2)<br>**----- End of picture text -----**<br>
**==> picture [412 x 604] intentionally omitted <==**
**----- Start of picture text -----**<br>
Virtual Memory Map<br>OxFFFFFFFF<br>OxBEFEFFFF Physical Memory Map<br>zeserve!;<br>OxBFC58000OxBFC5FFFF | eet sehbiebbeal<br>Boot Flash (4)<br>0xBFC00000<br>Reserved<br>OxBF93FFFF (5)<br>SFRs<br>OxBF800000<br>OxBF7FFFFF<br>Recened _ 0x1FC58000<br>0xB0900000 Fa Ox1FC57FFF<br>OxBO8FFFFF Program Flash nae Boot Flash (4)<br>0xB0800000 (Peripherals) om<br>OxBO7FFFFF @ G) 0x1FC000000<br>OxBOOFFFFF @ Rbeoned 0x1F940000<br>Program Flash 6) 0x1F93FFFF<br>(CPU) SFRs<br>0xB0000000 0x1F800000<br>Reserved Ox1F7FFFFF<br>OxA004FFFF 0x10900000<br>Program Flash<br>0xA0040000 DBF 0x108FFFFF<br>OxA007FFFF npPeripherals ) 0x10800000<br>RAM() 0x107FFFFF<br>0xA0000000 0x100FFFFF<br>Reserved<br>Ox9FC57FFFOx9FC58000 | Resened | ened(CPU)<br>rm<br>Boot Flash 0x10000000<br>Ox9FC00000 0x00050000<br>0x0004FFFF<br>Ox908FFFFF0x90800000 Program(Peripherals)Flesh _ 0x0003FFFFx!<br>0x907FFFFF 9 3<br>Ox900FFFFF ® a<br>Program Flash = o 0x00000000<br>(CPU) a<br>0x90000000<br>0x80050000<br>0x8004FFFF<br>0x80040000 BF<br>0x8007FFFF<br>RAM®)<br>0x80000000<br>0x00000000<br>Note 1: Memory areas are not shown to scale.<br>2: The Cache and MMU (FMT) are initialized by compiler start-up code.<br>3: RAM memory is divided into two equal banks: RAM Bank 1 and RAM Bank 2 on a half boundary.<br>4: Refer to Figure 6-2.<br>5: Refer to Table 6-1.<br>**----- End of picture text -----**<br>
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## smn
**==> picture [216 x 418] intentionally omitted <==**
**----- Start of picture text -----**<br>
FIGURE 6-2: BOOT AND ALIAS<br>MEMORY MAP<br>Physical M Map”<br>ysical' memary Map<br>Ox1FC7FFFF<br>0x1FC57000<br>5 , (2)<br>Configuration Space<br>Ox1FC54FFF<br>Reserved<br>Upper Boot Alias<br>Reserved<br>Ox ECOFFF<br>0x1FCOFFFF<br>Lower Boot Alias,<br>oxircooooo |<br>Note 1: Memory areas are not shown to scale.<br>2: This calibration area space cannot be mod-<br>ie<br>fied by user.<br>3: Refer to Section 6.1.1 “Boot Flash And<br>Configuration” for more information.<br>**----- End of picture text -----**<br>
- 4: This configuration space cannot be used forTheseexecuting memorycode locationsin the areupper usedboot to initial-alias. ize Configuration registers (see Section 37.2 “Special Features Registers”.
**==> picture [160 x 9] intentionally omitted <==**
**----- Start of picture text -----**<br>
TABLE 6-1: SFR MEMORY MAP<br>**----- End of picture text -----**<br>
**==> picture [212 x 483] intentionally omitted <==**
**----- Start of picture text -----**<br>
Virtual Address<br>Peripheral;<br>Base<br>: ; OxBF900000<br>PORTK 0x0300<br>poe<br>en<br>CAN 0x2000<br>ae aceon<br>OMADMA foxioooOxi000 |<br>0xBF810000<br>Note 1: Refer to Section 6.3 “System Bus Arbi-<br>tration” for important legal information.<br>**----- End of picture text -----**<br>
- 2: This configuration space cannot be modified by the user.
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## PIC32MZ W1 and WFI32E01 Family
## seman
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**----- Start of picture text -----**<br>
TABLE 6-1: SFR MEMORY MAP<br>(CONTINUED)<br>:<br>0xBF800000<br>**----- End of picture text -----**<br>
## 6.1.1 BOOT FLASH AND CONFIGURATION
PIC32MZ W1 on device Reset, reads Boot Flash Configuration Word information before allowing system to boot.
Every time=device Reset or NMI event occurs, the CFGPG.CPUPG[1:0] bits are reset to ‘0’. This helps the user to strictly control some regions. Boot code to use the CFGPG registers to define regions that are only accessible by group 0. Once the boot code is finished with data or code operations, it must set the CFGPG.CPUPG[1:0] to a value other than ‘o’.
- Note 1: Refer to Section 6.3 “System Bus Arbitration” for important legal information.
- 2: This configuration space cannot be modified by the user.
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TABLE 6-1: BOOT FLASH CODE PROTECTION REGISTER SUMMARY MAP
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REGISTER 6-2: BFDEVCP: BOOT FLASH CODE PROTECTION REGISTER
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|Bit|Bit|Bit|Bit|Bit|Bit|Bit|Bit|Bit|
|Range|||31/23/15/7|| 30/22/14/6|||29/21/13/5|| 28/20/12/4|| 27/19/11/3|||26/18/10/2|25/17/9/1|24/16/8/0|
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bit 31-29 Unimplemented: Read as ‘0’ bit 28 CP: Code Protect bit 0 = Protection Disabled
1 = Protection Enabled
bit 27-0 Unimplemented: Read as ‘0’
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PIC32MZ W1 and WFI32E01 Family
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TABLE 6-3: BOOT FLASH SIGN REGISTER SUMMARY MAP
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REGISTER 6-4: BFDEVSIGN: BOOT FLASH SIGN REGISTER
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bit 31 SIGN: Flash SIGN bit 1 = Unsigned 0 = Signed
bit 30-0 Unimplemented: Read as ‘0’
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## PIC32MZ W1 and WFI32E01 Family
## seman
## 6.3 System Bus Arbitration
Note: The System Bus interconnect implements one or more instantiations of the SonicsSX® interconnect from Sonics, Inc. This document contains materials that are (c) 2003-2015 Sonics, Inc., and that constitute proprietary information of Sonics, Inc. SonicsSX is a registered trademark of Sonics, Inc. All such materials and trademarks are used under license from Sonics, Inc. As shown in the PIC32MZ W1 family block diagram (see Figure 2-1), there are multiple initiator modules (1 through 113) in the system that can access various target modules (T1 through T13). Table 6-3 lists the initiator and its corresponding access target. The System Bus supports simultaneous access to targets by initiators, so long as the initiators are accessing different targets. The System Bus will perform arbitration if multiple initiators attempt to access the same target.
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PIC32MZ W1 and WFI32E01 Family seman The System Bus arbitration scheme implements a non6.4 Permission Access and System programmable, Least Recently Serviced (LRS) priority, Bus Registers which provides Quality Of Service (QOS) for most initiators. However, some initiators can use Fixed High The System Bus on PIC32MZ W1 family of MCUs Priority (HIGH) arbitration to guarantee their access to provide access control capabilities for the transaction data. initiators on the System Bus. The arbitration scheme for the available initiators is The System Bus divides the entire memory space into shown in Table 6-4. 14 target regions and permits access to each target by initiators through permission groups. Four TABLE 6-4: INITIATOR ID AND QOS Permission Groups (0 through 3) can be assigned to | Name | wD | Qos | eachof theinitiatoothe **r** .s E **a** ndch permissioncan have groupexclusiveis independentor shared HIGH(1,2) Using the CFGPG register (see Register 37-6 in Flash Controller LRSM) Section 37.0 “Special Features”), Boot firmware can FlashDMA Controller [4A a(1.2) assignmake requestsa permission on thegroup Systemto Bus.each initiator, which can Read The available targets and their regions, as well as the DMA Read | 6 HIGH 2) associated control registers to assign protection, are DMA Write LRs() described and listed in Table 6-5. DMA Write | 8s HIGH'1,2) Register 6-5 through Register 6-12 are used for setting ICD - JTAG | =o] RS and controlling access permission groups and regions. To change these registers, they must be unlocked in faAbc.SS™~é<‘iTS*<‘ié“TSCS*#*dTSCtCRSSADC a LRS hardware.PGLOCK ConfigurationThe register bitlock(CFGCON[11]).is controlled bySettingthe PGLOCK prevents writes to the control registers; CAN-FD clearing PGLOCK allows writes. Crypto Engine To set or clear the PGLOCK bit, an unlock sequence Ethernet Write must be executed. Refer to Oscillators with Enhanced Ethernet Read PLL in the "PIC32 Family Reference Manual" for more details.
- Note 1: When accessing SRAM, the DMAPRI bit (CFGCONOJ6]), the FCPRI bit (CFGCONO[5]), and the EXLPRI bit (CFGCONO[7]) provide arbitration control for the DMA, FC, and CPU (when servicing an_ interrupt (EXL = _ §1)), respectively, by selecting the use of LRS or HIGH. When using HIGH, the DMA, FC, and CPU get arbitration preference over all initiators using LRS.
- 2: Using HIGH arbitration can have serious negative effects on other initiators. Therefore, it is recommended to not enable this type of arbitration for an initiator that uses significant system bandwidth. HIGH arbitration is intended to be used for low bandwidth applications that require low latency, such as LCC graphics applications.
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## PIC32MZ W1 and WFI32E01 Family
## seman
**==> picture [457 x 188] intentionally omitted <==**
**----- Start of picture text -----**<br>
REGISTER 6-5: SBTxELOG1: SYSTEM BUS TARGET ‘x’ ERROR LOG REGISTER 1<br>(‘x’ = 0-13)<br>Bit Bit Bit Bit Bit Bit Bit Bit Bit<br>Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 24/16/8/0<br>ae CODER]<br>x46<br>ge Ro [Ro | Ro | Ro | Ro OT ROT RT RT<br>19:8 INITID[7:0]<br>7p [RO [| Ro | Ro [| Ro | vo | ro {| Ro | Ro |<br>REGIONJ3:0] | CMD[2:0]<br>Legend: C = Clearable bit<br>R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’<br>-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared<br>**----- End of picture text -----**<br>
bit 31 MULTI: Multiple Permission Violations Status bit This bit is cleared by writing a ‘1’.
1 = Multiple errors have been detected
0 = No multiple errors have been detected
- bit 30-28 Unimplemented: Read as ‘0’
bit 27-24 CODE[3:0]: Error Code bits
Indicates the type of error that was detected. These bits are cleared by writing a ‘1’.
1111 = Reserved
1101 = Reserved
0011 = Permission violation
0010 = Reserved 0001 = Reserved 0000 = No error
bit 23-16 Unimplemented: Read as ‘0’
Note: Refer to Table 6-5 for the list of available targets and their descriptions.
renner eee e rereerence eee eee DS70005425A-page 90 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
REGISTER 6-5: SBTxELOG1: SYSTEM BUS TARGET ‘x’ ERROR LOG REGISTER 1 (‘x’ = 0-13) (CONTINUED)
bit 15-8 INITID[7:0]: Initiator ID of Requester bits
11111111 = Reserved
|||00010011 = Reserved|
|---|---|---|
|||00010010<br>= USB|
|||00010001 = SQI|
|||00010000 = Ethernet Read|
|||00001111 = Ethernet Write|
|||00001110 = Crypto Engine|
|||00001101 = CAN-FD|
|||00001100 = CAN|
|||00001011 =ADC|
|||00001010 = Wi-Fi|
|||00001001 =JTAG|
|||00001000<br>= DMA Write (DMAPRI (CFGCONOJ6]) = 1)|
|||00000111 = DMAWrite (DMAPRI (CFGCONO[6]) = 0)|
|||00000110 = DMA Read (DMAPRI (CFGCONOJ[6)) = 1)|
|||00000101 =DMA Read (DMAPRI (CFGCONDOJ[6)) = 0)|
|||00000100 =Flash Controller (FCPRI(CFGCONO[5)) = 0)|
|||00000011 =Flash Controller (FCPRI(CFGCONO[5]) = 0)|
|||00000010 = CPU (CPUPRI (CFGCONOJ7]) = 1)|
|||00000001 = CPU (CPUPRI (CFGCONOJ7]) = 0)|
|||00000000 = Reserved|
|bit|7-4|REGION[3:0]: Requested Region Number bits|
|||1111 - 0000 = Target’s region that reported a permission group violation|
|bit|3|Unimplemented: Read as ‘0’|
|bit||CMD[2:0]: Transaction Command ofthe Requester bits|
|||111 = Reserved|
|||110 = Reserved|
|||101 = Write (a non-posted write)|
|||100 = Reserved|
|||011 = Read (a locked read caused by a Read-Modify-Write transaction)|
|||010 = Read|
|||001 = Write|
|||000=Idle|
Note: Refer to Table 6-5 for the list of available targets and their descriptions.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 91
## PIC32MZ W1 and WFI32E01 Family
## seman
|REGISTER 6-6:|SBTxELOG2: SYSTEM BUSTARGET|SBTxELOG2: SYSTEM BUSTARGET|TARGET ‘x’ERRORLOG REGISTER2|TARGET ‘x’ERRORLOG REGISTER2|(‘x’ = 0-13)|
|---|---|---|---|---|---|
|Bit<br>Bit|Bit|Bit|Bit|Bit<br>Bit<br>Bit|Bit|
|Range | 31/23/15/7|| 30/22/14/6 |29/21/13/5 | 28/20/12/4|||| 27/19/11/3 | 26/18/10/2 | 25/17/9/1|24/16/8/0|
|—||||||
||EEE||Ee<br>Ee||Ee Ee Ee ee||
|a<br>—~t|<br>=|| = | = |||= | = [ = [ _ GRovPito)|||
|Legend:||||||
|R = Readable bit||W = Writable bit||U = Unimplemented bit, read as ‘0’||
|-n=ValueatPOR||‘1’=Bitisset||‘0’=Bitiscleared||
bit 31-3. Unimplemented: Read as ‘0’
bit 1-0 GROUP[1:0]: Requested Permissions Group bits 11 = Group 3 10 = Group 2 01 = Group 1 00 = Group 0
Note: Refer to Table 6-5 for the list of available targets and their descriptions.
**==> picture [457 x 201] intentionally omitted <==**
**----- Start of picture text -----**<br>
REGISTER 6-7: SBTxECON: SYSTEM BUS TARGET ‘x’ ERROR CONTROL REGISTER<br>(‘x’ = 0-13)<br>Bit Bit Bit Bit Bit Bit Bit Bit Bit<br>Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 24/16/8/0<br>“ip. | = | = | = | = | = [| = | ERR<br>aed<br>~{[ = | = | = | = | = [| = | = [| = |<br>ESE Ee Ee ee ee eee eee<br>Legend:<br>R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’<br>-n = Value at POR ‘1’ = Bitis set ‘0’ = Bit is cleared<br>**----- End of picture text -----**<br>
bit 31-25 Unimplemented: Read as ‘0’ bit 24 ERRP: Error Control bit
- 1 = Report protection group violation errors
- 0 = Do not report protection group violation errors
bit 23-0 Unimplemented: Read as ‘0’
Note: Refer to Table 6-5 for the list of available targets and their descriptions.
renner eee e rereerence eee eee DS70005425A-page 92 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
REGISTER 6-8: SBTxECLRS: SYSTEM BUS TARGET ‘x’ SINGLE ERROR CLEAR REGISTER
(‘x’ = 0-13)
|(‘x’ = 0-13)||||||
|---|---|---|---|---|---|
|Bit<br>Bit<br>Bit|Bit|Bit|Bit|Bit<br>Bit|Bit|
|Range | 31/23/15/7 | 30/22/14/6||29/21/13/5 | 28/20/12/4||| 27/19/11/3|| 26/18/10/2 | 25/17/9/1|24/16/8/0|
|EE<br>EEE|EE|Ee|ee|Ee ee ee||
|sate<br>fo<br>= | =|| = ||=|[| =|| = | =|[| = ||
|~[<br>= | = | = |<br>a<br>a<br>A<br>—t|<br>= | =<br>| = |||=~ <br> =|| =<br> | =|[| = | =<br>[| = |<br>[| = [| = _ | CLEAR||
|Legend:||||||
|R = Readable bit|W = Writable bit||U = Unimplemented bit, read as ‘0’|||
|-n=ValueatPOR|‘1’=Bitisset||‘0’=Bitiscleared|||
## bit 31-1 Unimplemented: Read as ‘0’
bit 0 CLEAR: Clear Single Error on Read bit Asingle error as reported via SBTxXELOG1 and SBTXELOG2 is cleared by a read of this register.
Note: Refer to Table 6-5 for the list of available targets and their descriptions.
REGISTER 6-9: SBTxECLRM: SYSTEM BUS TARGET ‘x’ MULTIPLE ERROR CLEAR REGISTER (‘x’ = 0-13)
||(‘x’ = 0-13)|||||
|---|---|---|---|---|---|
|Bit<br>Bit|Bit<br>Bit|Bit|Bit<br>Bit<br>Bit||Bit|
|Range | 31/23/15/7|| 30/22/14/6 |29/21/13/5 |28/20/12/4||| 27/19/11/3 | 26/18/10/2 | 25/17/9/1||24/16/8/0|
|“i-|[| = | = [||=|[| =<br>[| =<br>[| =|[||= ||
|vate<br>t=||<br>= | = ||=|| =<br>[| = | =|[||= ||
|~{[<br>= <br>- Le <br>**E**S|| = | = | <br> | we | vw |<br>ee<br>EE|= <br>vw <br>Ee|| =<br>[| = | =<br>[| <br> | vw<br>[| vw [ vw | <br> ee eee||= |<br> ro |<br>cura|
|Legend:||||||
|R = Readable bit|W = Writable bit||U = Unimplemented bit, read as ‘0’|||
|-n=ValueatPOR|‘1’?=Bitisset||‘0’=Bitiscleared|||
bit 31-1 Unimplemented: Read as ‘0’ bit 0 CLEAR: Clear Multiple Errors on Read bit
Multiple errors as reported via SBTxELOG1 and SBTxELOG2 is cleared by a read of this register.
Note: Refer to Table 6-5 for the list of available targets and their descriptions.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 93
PIC32MZ W1 and WFI32E01 Family
## seman
|REGISTER|6-10:|SBTxREGy: SYSTEM BUS TARGET ‘x’ REGION ‘y’ REGISTER|
|---|---|---|
|||(‘x’=0-13;‘y’=0-10)|
|Range|| 31/23/15/7 |30/22/14/6 |29/21/13/5 |28/20/12/4 | 27/19/11/3|| 31/23/15/7 |30/22/14/6 |29/21/13/5 |28/20/12/4 | 27/19/11/3|| 26/18/10/2 | 25/17/9/1|24/16/8/0|
|---|---|---|---|---|
|;<br>od<br>| 79|LRwo [ ewo [| rwo | rwo <br> eg|| rwo|| ewo | Ro | uo<br>ee||
|Legend:|||||
|R = Readable bit<br>W = Writable bit||U = Unimplemented bit, read as ‘0’|||
|-n = Value at POR<br>‘1’ = Bit is set||‘0’ = Bit is cleared|||
|bit 31-10|BASE[21:0]: Region BaseAddress bits||||
|bit 9|PRI: Region Priority Level bit||||
||1 =Level 2||||
||0 = Level 1||||
|bit 8|Unimplemented: Read as ‘0’||||
|bit 7-3|SIZE[4:0]: Region Size bits||||
||Permissionsfora region are onlyactive is theSIZE is non-zero.<br>11111 = Region size = 2(SIZE-1) x 49024 (bytes)||||
||00001 = Region size = 2(S'ZE- 1) x 1024 (bytes)||||
||00000 = Region is not present||||
|bit 2-0|Unimplemented: Read as ‘0’||||
|Note<br>1:|Refer to Table 6-5 for the list of available targets and their descriptions.||||
|2:|Forsome target regions, certain bits in this register are read-only with preset values. See Table 6-5 for||||
||moreinformation.||||
renner eee e rereerence eee eee DS70005425A-page 94 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
REGISTER 6-11: SBTxRDy: SYSTEM BUS TARGET ‘x’ REGION ‘y’ READ PERMISSIONS REGISTER (‘x’ = 0-13; ‘y’ = 0-10)
Bit Bit Bit Bit Bit Bit Bit Bit Bit Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 24/16/8/0 sate ~[ = | = | = | = | = [| = | = [| = | -° (= = = frerours [erour2 | Grourt | Grouro
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared
- bit 31-4 Unimplemented: Read as ‘0’
- bit 3 Group3: Group3 Read Permissions bits 1 = Privilege Group 3 has read permission
- 0 = Privilege Group 3 does not have read permission
- bit 2 Group2: Group2 Read Permissions bits 1 = Privilege Group 2 has read permission
- 0 = Privilege Group 2 does not have read permission
- bit 1 Group1: Group1 Read Permissions bits 1 = Privilege Group 1 has read permission
- 0 = Privilege Group 1 does not have read permission
- bit 0 Group0: Group0 Read Permissions bits 1 = Privilege Group 0 has read permission
- 0 = Privilege Group 0 does not have read permission
- Note 1: Refer to Table 6-5 for the list of available targets and their descriptions.
- 2: For some target regions, certain bits in this register are read-only with preset values. See Table 6-5 for more information.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 95
PIC32MZ W1 and WFI32E01 Family
## seman
REGISTER 6-12: SBTxWRy: SYSTEM BUS TARGET ‘x’ REGION ‘y’ WRITE PERMISSIONS REGISTER (‘x’ = 0-13; ‘y’ = 0-10)
|Bit<br>Bit|Bit|Bit|Bit|Bit<br>Bit<br>Bit|Bit|
|---|---|---|---|---|---|
|Range | 31/23/15/7 | 30/22/14/6 |29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1|||||24/16/8/0|
|sate||||||
|=|DESDE DESDE<br>SEs SEES|||||
|-||||||
|Legend:||||||
|R = Readable bit||W = Writable bit||U = Unimplemented bit, read as ‘0’||
|-n=ValueatPOR||‘1’=Bitisset||‘0’=Bitiscleared||
bit 31-4 Unimplemented: Read as ‘0’
|bit|3|Group3: Group 3 Write Permissions bits|
|---|---|---|
|||1 = Privilege Group 3 has write permission|
|||0 = Privilege Group 3 does not have write permission|
|bit|2|Group2: Group 2 Write Permissions bits|
|||1 = Privilege Group 2 has write permission|
|||0 = Privilege Group 2 does not have write permission|
|bit|1|Group1: Group 1 Write Permissions bits|
|||1 = Privilege Group 1 has write permission|
|||0 = Privilege Group 1 does not have write permission|
|bit|0|Group0: Group 0 Write Permissions bits|
|||1 = Privilege Group 0 has write permission|
|||0=PrivilegeGroup0doesnothavewritepermission|
- Note 1: Refer to Table 6-5 for the list of available targets and their descriptions. 2: For some target regions, certain bits in this register are read-only with preset values. See Table 6-5 for more information.
renner eee e rereerence eee eee DS70005425A-page 96 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
## 7.0 RESETS
The device Reset sources are as follows:
- Power-on Reset (POR)
- ats : Thisis datadata sheshe **e** tt summarizes: fe. the featuresal —— * Blaster lear REsencl
- of the PIC32MZ W1 family of devices. It is not intended to be a comprehensive refer* Software Reset (SWR) ence source. To complement the informa« Watchdog Timer Reset tion in this data sheet, refer to Section 7. ¢ Brown-out Reset (BOR) Resetamily Reference ee caamaaaeManual”, enwhich are oi?is avail*.. Configuration:: Mismatch able from the Microchip web site DeSean Ret Rese Ret Rese Rese Onalis) (www.microchip.com/PIC32). A simplified block diagram illustrated in Figure 7-1.
- The Reset module combines all Reset sources and controls the device master Reset signal, SYSRST.
- « Watchdog Timer Reset (WDTR)
- ¢ Brown-out Reset (BOR) *.. Configuration:: Mismatch Reset (CMR) DeSean Ret Rese Ret Rese Rese Onalis)
- A simplified block diagram of the Reset module is illustrated in Figure 7-1.
**==> picture [248 x 8] intentionally omitted <==**
**----- Start of picture text -----**<br>
FIGURE 7-1: SYSTEM RESET BLOCK DIAGRAM<br>**----- End of picture text -----**<br>
**==> picture [422 x 280] intentionally omitted <==**
**----- Start of picture text -----**<br>
MCLR<br>Xx} MCLR<br>Sleep or Idle e DMTR/WDTR<br>Time-out Time-out<br>DMT<br>Time-out<br>Voltage Regulator Enabled Timer qdPape SYSRST<br>VDD<br>xKS VDDDetectRise<br>Reset<br>Configuration<br>Mismatch<br>Reset CMR<br>Software Reset SWR<br>**----- End of picture text -----**<br>
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 97
## PIC32MZ W1 and WFI32E01 Family seman
**==> picture [265 x 637] intentionally omitted <==**
**----- Start of picture text -----**<br>
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renner eee e rereerence eee eee DS70005425A-page 98 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
## REGISTER 7-1: RCON: RESET CONTROL REGISTER
Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 25/17/9/1 24/16/8/0 PoRIO® [PORCORE™T| = |= | BCFGERR | BCFGFAIL_ | _NVMLTA | NVMEOL_| Po=POR | VBAT a a CO PexrR | Swe | owro | woro | sueep | ioe | sor | Por | Legend: HS = Hardware Set HC = Hardware Cleared R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
- bit31 PORIO: IO Voltage POR Flag bit")
- 1 = Power-up Reset occurs due to IO voltage 0 = Power-up Reset does not occur due to IO voltage Set by hardware at detection of an IO POR event.
- Note: | User may write this bit to '1'". Does not cause a POR_IO.
- bit30 | PORCORE: Core Voltage POR Flag bit!)
- 1 = Power-up Reset occurs due to core voltage 0 = Power-up Reset does not occur due to core voltage Set by hardware at detection of a core POR event.
- Note: | User may write this bit to '1'. Does not cause a POR_CORE.
- bit 29-28 Unimplemented: Read as ‘0’
- bit 27 BCFGERR: BCFG Error Flag bit 1 = BCFG error occurs
- 0 = BCFG error does not occur A primary BCFG value had an error but the secondary BCFG value was valid and used.
- bit 26 BCFGFAIL: BCFG Failure Flag bit 1 = BCFG failure occurs
- 0 = BCFG failure does not occur
- bit 25 NVMLTA: NVM Life Time Alert Flag bit 1 = NVM LTA error occurs 0 = NVM LTA error does not occur NVM Life Time Alert - due to charge leakage the NVM is nearing End of Life (EOL).
- bit 24 NVMEOL: NVM EOL Flag bit 1 = NVM EOL failure occurs
- 0 = NVM EOL failure does not occur NVM EOL - may not be visible since the part does not come out of Reset if the bit is asserted.
- bit 23-18 Unimplemented: Read as ‘0’
- bit 17 VBPOR: VBPOR Mode Flag bit
- 1 = VBAT domain POR occurs
- 0 = VBAT domain POR does not occur
- Note: User may write this bit to '1'. Does not cause a VBPOR event.
- bit 16 VBAT: VBAT Mode Flag bit 1 = POR exit from VBAT occurs. A true POR must be established with the valid VBAT voltage level on the VBAT pin.
- 0 = POR exit from VBAT does not occur
Note: | User may write this bit to '1'". Does not cause a VBAT event.
bit 15-11 Unimplemented: Read as '0'
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 99
## PIC32MZ W1 and WFI32E01 Family seman
|REGISTER 7-1:<br>RCON: RESET CONTROL REGISTER|REGISTER 7-1:<br>RCON: RESET CONTROL REGISTER|(CONTINUED)|
|---|---|---|
|bit10|| DPSLP: Deep Sleep Mode Flag bit!)||
||1 = Deep Sleep mode occurs||
||0 = Deep Sleep mode does not occur||
||Set by hardware at time of entry into Deep Sleep mode.||
||Note:<br>| Usermay write this bit to '1'. Does notcause|a DPSLP event.|
|bit 9|CMR: Configuration Mismatch Reset Flag bit||
||1 = Configuration mismatch Reset event occurs||
||0 = Configuration mismatch Reset event does notoccur||
||Note:<br>User may write this bit to '1'. Does notcause|a mismatch Reset.|
|bit 8|Unimplemented: Read as ‘0’||
|bit 7|EXTR: External Reset (MCLR) Pin Flag bit||
||1 = MCLR occurs||
||0 = MCLR does not occur||
||Note:<br>| Usermay write this bit to '1'. Does notcause|a MCLR.|
|bit 6|SWR: Software Reset Flag bit||
||1 = SWR is executed||
||0 = SWR is not executed||
||Note:<br>| Usermay write this bit to '1'. Does notcause|SWR.|
|bit 5|DMTO: Deadman TimerTime-Out Flag bit||
||1 = DMT time-out occurs and causes a Reset||
||0 = DMT time-out does not occur||
||Note:<br>| Usermaywrite this bit to '1'. Does notcause|DMT Reset.|
|bit4|WDTO: Watchdog Timer Time-Out Flag bit||
||1 = WDT time-out occurs and causes a Reset||
||0 = WDT time-out does not occur||
|bit 3|SLEEP: Wake from Sleep Flag bit||
||1 = Device is in Sleep mode||
||0 = Device is not in Sleep mode||
||Note:<br>| Usermay write this bit to '1'. Does not invoke|Sleep mode.|
|bit 2|IDLE: Wake from Idle Flag bit||
||1 = Device in Idle mode||
||0 = Device in not in Idle mode||
||Note:<br>| Usermaywrite this bit to '1'. Does not invoke|Idle mode.|
|bit 1|BOR: Brown-out Reset Flag bit!)||
||1 = Brown-out Reset occurs||
||0 = Brown-out Reset does not occur||
||Set by hardware at detection of<br>a BOR event.||
||Note:<br>| Usermay write this bit to '1'. Does notcause|a BOR.|
|bit0|POR: Power-On Reset Flag bit")||
||1 = Power-up Reset occurs||
||0 = Power-up Reset does not occur||
||Set by hardware at detection of<br>a POR event.||
||Note:<br>Usermaywritethisbitto'1'.Doesnotcause|aPOR.|
Note 1: User software must clear this bit to view the next detection.
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PIC32MZ W1 and WFI32E01 Family
smn
## REGISTER 7-2: RSWRST: SOFTWARE RESET REGISTER
|Bit|Bit<br>Bit|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit|
|---|---|---|
|Range|| 31/23/15/7 |30/22/14/6 ||29/21/13/5 |28/20/12/4 |27/19/11/3 | 26/18/10/2<br>25/17/9/1<br>24/16/8/0|
|psa <br>pee <br>oe|PS<br> SE<br> Eee|EE<br>EES<br>ee ee<br> ee ee EE|
|7:0|ee|12<br>SWRST"2 ||
|Legend:||HC = Hardware Cleared|
|R = Readable bit||W = Writable bit<br>U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR||‘1’=Bitisset<br>‘0’=Bitiscleared<br>x=Bitisunknown|
- bit 31-1 Unimplemented: Read as ‘0’ bit SWRST: Software Reset Trigger bit'"-2) 1 = Enable SWR event 0 = No effect
- Note 1: The system unlock sequence must be performed before the SWRST bit can be written. Refer to Oscillators with Enhanced PLL in the “PIC32 Family Reference Manual” for details. Once this bit is set, any read of the RSWRST register triggers a Reset.
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PIC32MZ W1 and WFI32E01 Family
## seman
REGISTER 7-3: RNMICON: NON-MASKABLE INTERRUPT (NMI) CONTROL REGISTER
|Bit|Bit|Bit|Bit|Bit|Bit|Bit|Bit|Bit|
|---|---|---|---|---|---|---|---|---|
|Range|| 31/23/15/7||30/22/14/6|| 29/21/13/5 |28/20/12/4|||27/19/11/3 | 26/18/10/2||25/17/9/1|24/16/8/0|
|“t=|||<br>=|| =<br>||=|| = [|= | oto||| wor ||
|oie<br>8|[sw|[rrr<br>wots|||||||
|-<br>:|||||||||
|-<br>:|||||||||
|Legend:|||||||||
|R = Readable bit|||W = Writable bit||U = Unimplemented bit, read as ‘0’||||
|-n=ValueatPOR|||‘1’=Bitisset||‘0’=Bitiscleared||x=Bitisunknown||
- bit 31-26 Unimplemented: Read as ‘0’
- bit 25 DMTO: Deadman Timer Time-Out Flag bit This causes a Reset when NMICNT expires. 1 = DMT time-out occurs and causes a NMI 0 = DMT time-out does not occur Note: | User may write this bit to '1'. Does cause a user initiated DMT NMI event and NMICNT start.
- bit 24 WDTR: Watchdog Timer Time-Out in Run Flag bit This may cause a Reset if NMICNT expires. 1 = WDT time-out occurs and causes a NMI 0 = WDT time-out does not occur Note: User may write this bit to '1'. Does cause a user initiated WDT NMI event and NMICNT start.
- bit 23 SWNMI: Software NMI Trigger bit 1 = Writing a ‘1’ to this bit causes an NMI to be generated 0 = Writing a ‘0’ to this bit does not have any effect
- bit 22-20 Unimplemented: Read as ‘0’ bit 19 GNMI: External/Generic NMI Event bit 1 = Generic NMI event is detected and causes an NMI 0 = Generic NMI event is not detected Note: User may write this bit to '1'". Does cause a user initiated External/Generic NMI event.
- bit 18 LVD: Low-voltage Detect Event bit 1 = LVD detects a Low-voltage condition and causes an NMI 0 =LVD does not detect a Low-voltage condition Note: | User may write this bit to '1'. Does cause a user initiated LVD NMI event.
- bit 17 CF: Clock Fail Detect bit (read/clearable by application) 1 = FSCM detects clock failure and causes an NMI 0 = FSCM does not detect clock failure Note 1: Writing a ‘1’ to the CF bit causes a user initiated clock failure NMI event, but does not actually cause a clock switch.
- 2: Reset when a valid clock switching sequence is initiated by the clock switch state machine set when clock fail detected.
- Note: Thesystem unlock sequence must be performed before the SWRST bit can be written. Refer to Oscillators with Enhanced PLL in the “PIC32 Family Reference Manual” for details.
- bit 16 WDTS: WDTS: Watch-Dog Timer Time-Out in Sleep Flag bit 1 = WDT time-out occurs during Sleep mode and causes a wake-up from sleep 0 = WDT time-out does not occur during Sleep mode
- Note: | User may write this bit to '1'. Does cause a user initiated WDT NMI event.
renner eee e rereerence eee eee DS70005425A-page 102 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
## REGISTER 7-3: RNMICON: NON-MASKABLE INTERRUPT (NMI) CONTROL REGISTER (CONTINUED)
- bit 15-0 NMICNT[15:0]: NMI Reset Counter bit
- This bit field specifies the reload value used by the NMI Reset counter. 1111111111111111-0000000000000001 = Number of SYSCLK cycles before a device Reset occurs), If the NMI event is cleared before the counter reached zero, then device Reset is not asserted. 0000000000000000 = No delay between NMI assertion and device Reset event
- Note 1: The system unlock sequence must be done before this register can be written. 2: When a WDT NMI event (when not in Sleep mode) or a DMT NMI event is triggered, the NMICNT starts decrementing. When NMICNT reaches zero, the device is Reset. This NMI Reset counter is only applicable to these two specific NMI events.
Note: |The system unlock sequence must be performed before the SWRST bit can be written. Refer to Oscillators with Enhanced PLL in the “PIC32 Family Reference Manual” for details.
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PIC32MZ W1 and WFI32E01 Family
DS70005425A-page 104
Preliminary Data Sheet © 2020 Microchip Technology Inc.
## PIC32MZ W1 and weri32E01 Family
## smn 8.0 CPU EXCEPTIONS AND The CPU handles interrupt events as part of the the excepINTERRUPT CONTROLLER tion ‘heared mechanism, whit is described in
The CPU handles interrupt events as part of the the exception ‘heared mechanism, whit is described in Section 8.1 “CPU Exceptions”. The Interrupt Controller module includes the following features:
- Note: This data sheet summarizes the features of the PIC32MZ W1 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet. refer to Section 8. “Interrupts” (DS60001108) and Section 50. “CPU for Devices with MIPS32® microAptiv™ and M-Class Cores” (DS60001192) of the “P/IC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
- PIC32MZ W1 device generates interrupt requests in response to interrupt events from peripheral modules. The Interrupt Controller module exists outside of the CPU and prioritizes the interrupt events before presenting them to the CPU.
- ;
- ¢ Up to 126 interrupt sources. . * Seven user selectable priority levels with four subpriority levels within a priority level
- + Fixed priority within a specified user sub-priority level
- ¢ Unique interrupt offset for each source
- Single vector mode with interrupt number status “registerfwifi”
- * Software can generate any peripheral interrupt * Seven shadow register sets that can be used for any priority level, eliminating software context switch and reducing interrupt latency
- * Five external interrupts with edge polarity control Figure 8-1 shows the block diagram for the Interrupt Controller and CPU exceptions.
**==> picture [445 x 7] intentionally omitted <==**
**----- Start of picture text -----**<br>
FIGURE 8-1: CPU EXCEPTIONS AND INTERRUPT CONTROLLER MODULE BLOCK DIAGRAM<br>**----- End of picture text -----**<br>
**==> picture [353 x 99] intentionally omitted <==**
**----- Start of picture text -----**<br>
2 Vector Number and Offset<br>s<br>io”<br>oci)®= Interrupt Controller Boos CPU Core<br>5 (Exception Handling)<br>~ic Shadow Set Number<br>SYSCLK<br>**----- End of picture text -----**<br>
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PIC32MZ W1 and wei32E01 Family
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|DS70005425A-page120<br>PreliminaryDataSheet<br>©2020MicrochipTechnologyInc.|||
## PIC32MZ W1 and wei32E01 Family smn
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## PIC32MZ W1 and wei32E01 Family seman
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## PIC32MZ W1 and weri32E01 Family
## seman
## REGISTER 8-1: INTCON: INTERRUPT CONTROL REGISTER
Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 24/16/8/0 a a a oA a Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-24 NMIKEY[7:0]: Non-maskable Interrupt Key bits When the correct key (0x4E) is written, a software NMI is generated. The status is indicated by the GNMI bit (RNMICON[19]).
|||bit (RNMICON[19]).|bit (RNMICON[19]).|
|---|---|---|---|
|bit|23-13|Unimplemented: Read as ‘0’||
|bit|12|MVEC: Multi-vector Configuration bit||
|||1 =|Interrupt Controller configured for Multi-vector mode|
|||0 =|Interrupt Controller configured for Single Vector mode|
|bit|11|Unimplemented: Read as ‘0’||
|bit|10-8|TPC[2:0]: Interrupt Proximity Timer Control bits||
|||111|= Interrupts ofgroup priority 7 or lower start the interrupt proximity timer|
|||110|= Interrupts ofgroup priority 6 or lower start the interrupt proximity timer|
|||101|= Interrupts of group priority 5 or lower start the interrupt proximity timer|
|||100|= Interrupts ofgroup priority 4 or lower start the interrupt proximity timer|
|||011|= Interrupts ofgroup priority 3 or lower start the interrupt proximity timer|
|||010|= Interrupts ofgroup priority 2 or lower start the interrupt proximity timer|
|||001|= Interrupts ofgroup priority 1 start the interrupt proximity timer|
|||000|= Disables interrupt proximity timer|
|bit|7-5|Unimplemented: Read as ‘0’||
|bit|4|INT4EP: External Interrupt<br>4 Edge Polarity Control bit||
|||1 =|Rising edge|
|||0 =|Falling edge|
|bit|3|INT3EP: External Interrupt 3 Edge Polarity Control bit||
|||1 =|Rising edge|
|||0 =|Falling edge|
|bit|2|INT2EP: External Interrupt<br>2 Edge Polarity Control bit||
|||1 =|Rising edge|
|||0 =|Falling edge|
|bit|1|INT1EP: External Interrupt<br>1 Edge Polarity Control bit||
|||1 =|Rising edge|
|||0 =|Falling edge|
|bit|0|INTOEP: External Interrupt<br>0 Edge Polarity Control bit||
|||1 =|Rising edge|
|||0=|Fallingedge|
renner eee e rereerence eee eee DS70005425A-page 124 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and weri32E01 Family
## smn
|REGISTER 8-2:|PRISS: PRIORITY SHADOW|PRISS: PRIORITY SHADOW|SELECT REGISTER|||
|---|---|---|---|---|---|
|Bit<br>Bit<br>Range | 31/23/15/7|Bit<br> |30/22/14/6|Bit<br>Bit<br>Bit<br> | 29/21/13/5 | 28/20/12/4 |27/19/11/3 |||Bit<br>Bit<br>Bit<br> 26/18/10/2 | 25/17/9/4 | 24/16/8/0||
|2||||||
|vase<br>:||||||
|-<br>:||||||
|-<br>° rissa<br>80||||||
|Legend:||||||
|R = Readable bit||W = Writable bit|U = Unimplemented||bit, read as ‘0’|
|-n=ValueatPOR||‘1’=Bitisset|‘0’=Bitiscleared||x=Bitisunknown|
- bit 31-28 PRI7SS[3:0]: Interrupt with Priority Level 7 Shadow Set bits!) 1xxx = Reserved (by default, an interrupt with a priority level of 7 uses Shadow Set 0) 0111 = Interrupt with a priority level of 7 uses Shadow Set 7 0110 = Interrupt with a priority level of 7 uses Shadow Set 6
- 0001 = Interrupt with a priority level of 7 uses Shadow Set 1 0000 = Interrupt with a priority level of 7 uses Shadow Set 0
- bit 27-24 PRI6SS[3:0]: Interrupt with Priority Level 6 Shadow Set bits!) 1xxx = Reserved (by default, an interrupt with a priority level of 6 uses Shadow Set 0) 0111 = Interrupt with a priority level of 6 uses Shadow Set 7 0110 = Interrupt with a priority level of 6 uses Shadow Set 6
- 0001 = Interrupt with a priority level of 6 uses Shadow Set 1 0000 = Interrupt with a priority level of 6 uses Shadow Set 0
- bit 23-20 PRI5SS[3:0]: Interrupt with Priority Level 5 Shadow Set bits") 1xxx = Reserved (by default, an interrupt with a priority level of 5 uses Shadow Set 0) 0111 = Interrupt with a priority level of 5 uses Shadow Set 7 0110 = Interrupt with a priority level of 5 uses Shadow Set 6
- 0001 = Interrupt with a priority level of 5 uses Shadow Set 1 0000 = Interrupt with a priority level of 5 uses Shadow Set 0
- bit 19-16 PRI4SS[3:0]: Interrupt with Priority Level 4 Shadow Set bits!) 1xxx = Reserved (by default, an interrupt with a priority level of 4 uses Shadow Set 0) 0111 = Interrupt with a priority level of 4 uses Shadow Set 7 0110 = Interrupt with a priority level of 4 uses Shadow Set 6
0001 = Interrupt with a priority level of 4 uses Shadow Set 1 0000 = Interrupt with a priority level of 4 uses Shadow Set 0
Note 1: These bits are ignored if the MVEC bit (INTCON[12]) = o.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 125
## PIC32MZ W1 and weri32E01 Family
## seman
|REGISTER 8-2:<br>PRISS: PRIORITYSHADOW SELECT REGISTER (CONTINUED)|REGISTER 8-2:<br>PRISS: PRIORITYSHADOW SELECT REGISTER (CONTINUED)|REGISTER 8-2:<br>PRISS: PRIORITYSHADOW SELECT REGISTER (CONTINUED)|REGISTER 8-2:<br>PRISS: PRIORITYSHADOW SELECT REGISTER (CONTINUED)|
|---|---|---|---|
|bit 15-12||PRI3SS[3:0]: Interrupt with Priority Level<br>3 Shadow Set bits!)||
|||1xxx = Reserved (by default, an interrupt with a priority level of|3 uses Shadow Set 0)|
|||0111 = Interrupt with a priority level of<br>3 uses Shadow Set 7||
|||0110<br>= Interrupt with a priority level of<br>3 uses Shadow Set 6||
|||0001 = Interrupt with a priority level of<br>3 uses Shadow Set 1||
|||0000 = Interrupt with a priority level of<br>3 uses Shadow Set 0||
|bit 11-8|||PRI2SS[3:0]: Interruptwith Priority Level<br>2ShadowSet bits!)||
|||1xxx = Reserved (by default, an interrupt with a priority level of|2 uses Shadow Set 0)|
|||0111 = Interrupt with a priority level of<br>2 uses Shadow Set 7||
|||0110 = Interrupt with a priority level of<br>2 uses Shadow Set 6||
|||0001 = Interrupt with a priority level of<br>2 uses Shadow Set 1||
|||0000 = Interrupt with a priority level of<br>2 uses Shadow Set 0||
|bit7-4||| PRI1SS[3:0]: Interruptwith Priority Level<br>1 Shadow Set bits‘)||
|||1xxx = Reserved (by default, an interrupt with a priority level of|1 uses Shadow Set 0)|
|||0111<br>= Interrupt with a priority level of<br>1 uses Shadow Set 7||
|||0110 = Interrupt with a priority level of<br>1 uses Shadow Set 6||
|||0001 = Interrupt with a priority level of<br>1 uses Shadow Set 1||
|||0000 = Interrupt with a priority level of<br>1 uses Shadow Set 0||
|bit 3-1||Unimplemented: Read as ‘0’||
|bit 0||SS0: Single Vector Shadow Register Set bit||
|||1 = Single vector is presented with a shadow set||
|||0 = Single vector is not presented with a shadow set||
|Note|1:|ThesebitsareignorediftheMVECbit(INTCON[12])=0.||
renner eee e rereerence eee eee DS70005425A-page 126 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and weri32E01 Family
ee
## REGISTER 8-3: INTSTAT: INTERRUPT STATUS REGISTER
|Bit<br>Bit|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit|
|---|---|
|Range | 31/23/15/7|| 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 |26/18/10/2 |25/17/9/1 | 24/16/8/0|
|poe Se<br>a<br>a<br>isp<br>( vo<br>| vo | uo OT uo | to TROT RO RO<br>— eee<br>=SRO<br>79<br>L Ro [| Ro |<br>Ro | Ro | Ro<br>[| Ro | RO | RO |<br>:||
|Legend:||
|R = Readable bit|W = Writable bit<br>U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR|‘1’=Bitisset<br>‘0’=Bitiscleared<br>X=Bitisunknown|
## bit 31-11 Unimplemented: Read as ‘0’
bit 10-8 SRIPL[2:0]: Requested Priority Level bits for Single Vector mode bits!) 111-000 = The priority level of the latest interrupt presented to the CPU bit 7-6 Unimplemented: Read as ‘0’ bit 7-0 SIRQ[7:0]: Last Interrupt Request Serviced Status bits 11111111-00000000 = The last interrupt request number serviced by the CPU
Note 1: This value should only be used when the Interrupt Controller is configured for Single Vector mode.
## REGISTER 8-4: IPTMR: INTERRUPT PROXIMITY TIMER REGISTER
|Bit|Bit|Bit|Bit|Bit|Bit|Bit|Bit|Bit|
|---|---|---|---|---|---|---|---|---|
|Range | 31/23/15/7|30/22/14/6|29/21/13/5 |28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1||||||||24/16/8/0|
|:|||||||||
|:|||||||||
|:|||||||||
|:|||||||||
|Legend:|||||||||
|R = Readable bit|||W = Writable bit||U = Unimplemented bit,||read as ‘0’||
|-n=ValueatPOR|||‘1’=Bitisset||‘0’=Bitiscleared||x=Bitisunknown||
bit31-0 IPTMR[31:0]: Interrupt Proximity Timer Reload bits
Used by the interrupt proximity timer as a reload value when the interrupt proximity timer is triggered by an interrupt event.
ee
© 2020 Microchip Technology Inc. Preliminary Data Sheet
DS70005425A-page 127
PIC32MZ W1 and weri32E01 Family
seman
## REGISTER 8-5: IFSx: INTERRUPT FLAG STATUS REGISTER
|Bit|Bit|Bit|Bit|Bit|Bit|Bit|Bit|Bit|
|---|---|---|---|---|---|---|---|---|
|Range| 31/23/15/7 | 30/22/14/6|||| 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2||||| 25/17/9/1|| 24/16/8/0|
|:|||||||||
|one<br>:|||||||||
|:|||||||||
|7<br>||||||||||
|Legend:|||||||||
|R = Readable bit|||W = Writable bit||U = Unimplemented bit, read as ‘0’||||
|-n=ValueatPOR|||‘1’=Bitisset||‘0’=Bitiscleared||xX=Bitisunknown||
bit 31-0 IFS31-IFSO: Interrupt Flag Status bits
1 = Interrupt request has occurred
0 = No interrupt request has occurred
Note: This register represents a generic definition of the IFSx register. Refer to Table 8-2 for the exact bit definitions.
REGISTER 8-6: IECx: INTERRUPT ENABLE CONTROL REGISTER
|Bit|Bit|Bit|Bit|Bit|Bit|Bit|Bit|Bit|Bit|
|---|---|---|---|---|---|---|---|---|---|
|Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1|||||||||24/16/8/0|
|:||||||||||
|:||||||||||
||:|||||||||
|:||||||||||
|Legend:||||||||||
|R =|Readable bit|||W = Writable bit||U = Unimplemented bit,||read as ‘0’||
|-n=|ValueatPOR|||‘1’=Bitisset||‘0’=Bitiscleared||x=Bitisunknown||
bit 31-0 IEC31-IECO: Interrupt Enable bits 1 = Interrupt is enabled
0 = Interrupt is disabled
Note: This register represents a generic definition of the IFSx register. Refer to Table 8-2 for the exact bit definitions.
renner eee e rereerence eee eee DS70005425A-page 128 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and weri32E01 Family
smn
## REGISTER 8-7: IPCx: INTERRUPT PRIORITY CONTROL REGISTER
Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0 a a a Ca) CE a C0 a a Oa) CE) a a a) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
- bit 28-26 IP3[2:0]: Interrupt Priority bits 111 = Interrupt priority is 7
010 = Interrupt priority is 2
001 = Interrupt priority is 1 000 = Interrupt is disabled
- bit 25-24 1$3[1:0]: Interrupt Subpriority bits 11 = Interrupt subpriority is 3
- 10 = Interrupt subpriority is 2
- 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0
- bit 23-21 Unimplemented: Read as ‘0’
- bit 20-18 IP2[2:0]: Interrupt Priority bits 111 = Interrupt priority is 7
010 = Interrupt priority is 2
001 = Interrupt priority is 1 000 = Interrupt is disabled
- bit 17-16 1I$2[1:0]: Interrupt Subpriority bits 11 = Interrupt subpriority is 3
- 10 = Interrupt subpriority is 2
- 01 = Interrupt subpriority is 1
- 00 = Interrupt subpriority is 0
- bit 15-13 Unimplemented: Read as ‘0’
- bit 12-10 1IP1[2:0]: Interrupt Priority bits 111 = Interrupt priority is 7
010 = Interrupt priority is 2
001 = Interrupt priority is 1
000 = Interrupt is disabled
Note: This register represents a generic definition of the IPCx register. Refer to Table 8-2 for the exact bit definitions.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 129
## PIC32MZ W1 and weri32E01 Family
## seman
## REGISTER 8-7: IPCx: INTERRUPT PRIORITY CONTROL REGISTER (CONTINUED)
|bit|9-8|1S1[1:0]: Interrupt Subpriority bits|
|---|---|---|
|||11 = Interrupt subpriority is 3|
|||10 = Interrupt subpriority is 2|
|||01 = Interrupt subpriority is 1|
|||00 = Interrupt subpriority is 0|
|bit|7-5|Unimplemented: Read as ‘0’|
|bit|4-2|IPO[2:0]: Interrupt Priority bits|
|||111 = Interrupt priority is 7|
|||010 = Interrupt priority is 2|
|||001 = Interrupt priority is 1|
|||000 = Interrupt is disabled|
|bit|1-0|ISO[1:0]: Interrupt Subpriority bits|
|||11 = Interrupt subpriority is 3|
|||10 = Interrupt subpriority is 2|
|||01 = Interrupt subpriority is 1|
|||00=Interruptsubpriorityis0|
Note: This register represents a generic definition of the IPCx register. Refer to Table 8-2 for the exact bit definitions.
renner eee e rereerence eee eee DS70005425A-page 130 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and weri32E01 Family
smn
REGISTER 8-8: OFFx: INTERRUPT VECTOR ADDRESS OFFSET REGISTER (x = 0-167)
|Bit<br>Bit<br>Range| 34/23/15/7|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br> |30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 |26/18/10/2 | 25/17/9/1<br>24/16/8/0|
|---|---|
|ws(=<br>=<br>=<br>=<br>EK||
|vate<br>~<br>| =|| = =F)|
|a<br>|||
|-2)||
|Legend:||
|R = Readable bit|W = Writable bit<br>U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR|‘1’=Bitisset<br>‘0’=Bitiscleared<br>x=Bitisunknown|
bit 31-16 Unimplemented: Read as ‘0’
bit 17-1 VOFF[17:1]: Interrupt Vector ‘x’ Address Offset bits bit 0 Unimplemented: Read as ‘0’
Note: x maynotbe continuous. Refer to Table 8-2 for available registers.
——— © 2020 Microchip Technology Inc. Preliminary Data Sheet
DS70005425A-page 131
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_————————————OOOO DS70005425A-page 132 Preliminary Data Sheet © 2020 Microchip Technology Inc.
## PIC32MZ W1 and WFI32E01 Family
## smn
## 9.0 PREFETCH MODULE
The prefetch module holds a subset of PFM in temporary holding spaces known as lines. Each line contains a tag and data field. Normally, the lines hold a copy of what is currently in memory to make instructions or data available to the CPU without Flash Wait states.
- Note: This data sheet summarizes the features of the PIC32MZ W1 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 9. “Prefetch Module for Devices with L1 CPU Cache” (DS60001649) in the “PIC32MZ W1 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
The following are key features of the prefetch module:
- 12x32 byte fully associative lines
- 4 lines for CPU instructions
- ¢ 4 lines for CPU data
- 4 lines for peripheral data
The prefetch module is a performance enhancing module that is included in the PIC32MZ W1 family of devices. When running at high-clock rates, Wait states must be inserted into Program Flash Memory (PFM) read transactions to meet the access meet the access the access access time of the of the the PFM. Wait states can be hidden to the core by prefetching and storing instructions in a temporary holding area that the CPU can access quickly. Although the data path to the CPU is 32 bits wide, the data path to the PFM is 256 bits wide. This wide data path provides the same bandwidth to the CPU as a 32-bit path running at eight times the frequency.
- 32 byte cache lines (256 bits) parallel memory fetch
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When running at high-clock rates, Wait states * True/pseudo LRU replacement policy<br>inserted into Program Flash Memory (PFM) ¢ Configurable predictive prefetch<br>to meet the access meet the access the access access time of the of the the PFM. + Flash ECC support<br>can be hidden to the core by prefetching oo ; .<br>instructions in a temporary holding area A simplified block diagram of the prefetch module is<br>CPU can access quickly. Although the data shown in Figure 9-1.<br>the CPU is 32 bits wide, the data path to the<br>bits wide. This wide data path provides the<br>to the CPU as a 32-bit path running at<br>the frequency.<br>9-1: PREFETCH MODULE BLOCK DIAGRAM<br>SYSCLK<br>Bus Control Teg Data<br>oO O<br>x PrefetchLine Control Buffer _ ><br>Program Flash Memory<br>**----- End of picture text -----**<br>
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FIGURE 9-1: PREFETCH MODULE BLOCK DIAGRAM<br>**----- End of picture text -----**<br>
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© 2020 Microchip Technology Inc. Preliminary Data Sheet
DS70005425A-page 133
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PIC32MZ W1 and WFI32E01 Family
## smn
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REGISTER 9-1: PRECON: PREFETCH MODULE CONTROL REGISTER<br>Bit Bit Bit Bit Bit Bit Bit Bit Bit<br>Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3| 26/18/10/2 | 25/17/9/1 | 24/16/8/0<br>8 2]<br>ern ren | TCHEEN<br>'° [= Trercrenv | ooneny | icney [= [PERCHECOH| BcHECOR | IGHECOR |<br>i a Ga<br>° [pemsecen|— | _pRereNnoy «SSCS<br>Legend: HC = Hardware Cleared —=HS = Hardware Set<br>R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’<br>S = Settable bit ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown<br>**----- End of picture text -----**<br>
bit 31-27 Unimplemented: Read as ‘0’
- bit 26, PERCHEEN: Peripheral Data Cache Enable bit 1 = Caching enabled
- 0 = Caching disabled (and all lines invalidated)
- bit 25 DCHEEN: Data Cache Enable bit 1 = Caching enabled 0 = Caching disabled (and all lines invalidated)
- bit 24 ICHEEN: Instruction Cache Enable bit 1 = Caching enabled
- 0 = Caching disabled (and all lines invalidated)
- bit 23 Unimplemented: Read as ‘0’
- bit 22 PERCHEINV: Manual Invalidate Control for Peripheral Data Cache 1 = Force invalidate cache/invalidate busy 0 = Cache invalidation follows CHECOH/invalid complete
- Note 1: PFB is included with iCache invalidate.
- 2: Hardware auto clears this bit when cache invalidate completes. Bits may clear at different times.
- bit 21 DCHEINV: Manual Invalidate Control for Data Cache 1 = Force invalidate cache/invalidate busy 0 = Cache invalidation follows CHECOH/invalid complete
- Note 1: PFB is included with iCache invalidate.
- 2: Hardware auto clears this bit when cache invalidate completes. Bits may clear at different times.
bit 20 ICHEINV: Manual Invalidate Control for Instruction Cache 1 = Force invalidate cache/invalidate busy 0 = Cache invalidation follows CHECOH/invalid complete
- Note 1: PFB is included with iCache invalidate.
- 2: Hardware auto clears this bit when cache invalidate completes. Bits may clear at different times.
bit 19 Unimplemented: Read as ‘0’
Note 1: For the Wait states to SYSCLK relationship, refer to 40.0 “Electrical Specifications”.
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## PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 9-1: PRECON: PREFETCH MODULE CONTROL REGISTER (CONTINUED)
|bit 18|PERCHECOH: Auto Cache Coherency Control for Peripheral Data Cache|
|---|---|
||1 =Auto invalidate cache on a programming event|
||0 = No auto invalidated cache on a programming event|
||Note:<br>|CHECOH must be stable before initiation ofprogramming to ensure correct inval-|
||idation of data.|
|bit 17|DCHECOH: Auto Cache Coherency Control for Data Cache|
||1 =Auto invalidate cache on a programming event|
||0 = No auto invalidated cache on a programming event|
||Note:<br>©CHECOH must bestable before initiation ofprogramming toensure correct invalidation ofdata.|
|bit 16|ICHECOH: Auto Cache Coherency Control for Instruction Cache|
||1 =Auto invalidate cache on a programming event|
||0 = No auto invalidated cache on a programming event|
||Note:<br>|CHECOH must bestable before initiation ofprogramming toensure correct invalidation ofdata.|
|bit 15-13|Unimplemented: Read as ‘0’|
|bit 12|CHEPERFEN: Cache Performance Counters Enable|
||1 = Performance counters is enabled|
||0 = Performance counters is disabled|
||Note:<br>Performance counters are reseton 0 to1 transition of this bit.|
|bit 11-9|Unimplemented: Read as ‘0’|
|bit 8|PFMAWSEN: Address Wait State Enable|
||Total Flash wait states areADRWS + PFMWS.|
||1 =Add 1 address Wait state - allowing for higher clock frequencies|
||0 =Add 0 address Wait states - allowing for higher performance at lower clock frequencies|
|bit 7|PFMSECEN: Flash Single-bit Error Corrected (SEC) Interrupt Enable bit|
||1 = Generate an interrupt when PFMSEC is set|
||0 = Do not generate an interruptwhen PFMSEC is set|
|bit 6|Unimplemented: Read as ‘0’|
|bit 5-4|PREFEN|[1:0]: Instruction Predictive Prefetch Enable|
||01 = Instruction predictive prefetch enabled for cacheable regions only|
||00 = Instruction predictive prefetch disabled|
||Other values are unavailable.|
|bit3-0 ||PFMWS[3:0]: PFMAccess Time Defined inTerms ofSYSCLKWait States bits!)|
||Total Flash Wait states areADRWS + PFMWS.|
||1111 = Fifteen Wait states|
||1110 = Fourteen Wait states|
||0001 = One Wait state|
||0000 = Zero Wait state|
||Note:<br>ThisisnottheWaitstateseenbytheCPU.|
Note 1: For the Wait states to SYSCLK relationship, refer to 40.0 “Electrical Specifications”.
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PIC32MZ W1 and WFI32E01 Family
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REGISTER 9-2: PRESTAT: PREFETCH MODULE STATUS REGISTER
|REGISTER 9-2:|PRESTAT: PREFETCH MODULE STATUS REGISTER||
|---|---|---|
|Bit<br>Bit<br>Range | 31/23/15/7|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br> |30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/4|Bit<br>24/16/8/0|
|—f|<br>=<br>| =<br>| =<br>[| = { Prmeo | rrusec | =<br>| =<br>pte |See<br>88 Se ee ee|||
|7<br>||||
|Legend:|HC = Hardware Cleared<br>HS = Hardware Set||
|R = Readable bit|W = Writable bit<br>U = Unimplemented bit, read as ‘0’||
|S=Settablebit|‘1’=Bitisset<br>‘0’=Bitiscleared<br>x=Bitisunknown||
## bit 31-28 Unimplemented: Read as ‘0’
- bit 27 PFMDED: Flash Double-bit Error Detected (DED) Status bit 1 =An error has occurred 0 =An error has not occurred
- Note: DED errors are reported in-band with the data using the bus error protocol. When reported for CPU reads they are seen as bus exception errors by the CPU.
- bit 26 PFMSEC: Flash Single-bit Error Corrected (SEC) Status bit
- 1 =A SEC error occurred when PFMSECCNT[7:0] was equal to zero
- 0 =ASEC error has not occurred Note: The error event is reported to the CPU via using the prefetch module interrupt event.
- bit 25-8 Unimplemented: Read as ‘0’
- bit 7-0 PFMSECCNT[7:0]: Flash SEC Count bits Decrements (by 1) its count value each time an SEC error occurs. Holds at zero. When an SEC error occurs when PFMSECCNT is Zero, the PFMSEC status is set. If PFMSECEN is also set, a pCache interrupt event is generated.
- Note: This field counts all SEC errors and is not limited to SEC errors on unique addresses.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 137
PIC32MZ W1 and WFI32E01 Family
ne
## REGISTER 9-3: PREHIT: PREFETCH MODULE HIT STATISTICS REGISTER
|Range | 34/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 |26/18/10/2 | 25/17/9/1<br>24/16/8/0<br>oe LRneo [RHO | anoo |amoo | Amoo | RNcO | RNCD | RCO ||
|---|
|Legend:<br>HC = Hardware Cleared<br>HS = Hardware Set|
|R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’|
|S=Settablebit<br>‘1’=Bitisset<br>‘0’=Bitiscleared<br>x=Bitisunknown|
- bit 31-0 CHEHIT[31:0]: Instruction Cache Hit Count bits When CHECON.CHEPERF = 1, CHEHIT increments once per iCache or PFB hit. Note: = CHEHIT is reset on 0 to 1 transition of CHECON.CHEPERF.
OOOO___ DS70005425A-page 138 Preliminary Data Sheet © 2020 Microchip Technology Inc.
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|||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|REGISTER|9-4:|PREMIS:|PREFETCH|MODULE|MISS|STATISTICS|REGISTER|
|Range|||34/23/15/7|| 30/22/14/6|||29/21/13/5|||28/20/12/4|||27/19/11/3|| 26/18/10/2|||25/17/9/1|24/16/8/0|
|—,|Lawoo_||awoo|| awoo|| amoo|[aco|| amoo|||awoo|||aNco|||
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Legend: HC = Hardware Cleared HS = Hardware Set<br>R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’<br>S = Settable bit ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown<br>**----- End of picture text -----**<br>
bit 31-0 CHEMIS[31:0]: Instruction Cache Miss Count bits
When CHECON.CHEPERF = 1, CHEMIS increments once per iCache or PFB miss. Note: CHEMIS is reset on 0 to 1 transition of CHECON.CHEPERF.
OOOO___ © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 139
PIC32MZ W1 and WFI32E01 Family
DS70005425A-page 140
Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
## 10.0 DIRECT MEMORY ACCESS ACCESS (DMA) CONTROLLER
- DIRECT MEMORY ACCESS ACCESS ¢ Fixed priority channel arbitration (DMA) CONTROLLER ¢ Flexible DMA channel operating modes: - Manual (software) or automatic (interrupt) DMA
- Note: This data sheet summarizes the features requests of the PIC32MZ W1 device. It is not - One-shot or Auto-repeat Block Transfer modes intended to be a comprehensive - Channel-to-channel chaining reference source. To complement the . . . _ : information in this data sheet, refer to ¢ Flexible DMA requests: Section 31. “Direct Memory Access - ADMA request can be selected from any of the (DMA)“PIC32 Controller”Family Reference(DS60001117)Manual”, whichin the - peripheralEach channelinterruptcan selectsourcesany (appropriate). is available from the Microchip web site observable interrupt as its DMA request source (www.microchip.com/PIC32). - ADMA transfer abort can be selected from any
- DMA Controller Controller .isis a bus master module module useful for - ofUptheto 2-byteperipheralpatterninterrupt(data)sourcesmatch transfer tertransfers between different devices without CPU mination
- intervention. The source and destination of a DMA : : can be any of the memory mapped modules ¢ Multiple DMA channel status interrupts:: in the device such device such such as SPI, UART, and and so on, or - DMA channel block transfer complete itself. Peripherals like SQI, ADC, and so on - Source empty or half empty
- dedicated DMA can also access the generic - Destination full or half full DMA. - DMA transfer aborted due to an external event
- following are key features of the the DMA Controller: - Invalid DMA address generated
- Eight identical channels: « DMA debug support features: Auto-increment source and destination - Most recent error address accessed by a DMA address registers channel Source and destination pointers - Most recent DMA channel to transfer data Memory to memory and memory to * CRC generation module:
The DMA Controller Controller .isis a bus master module module useful for data transfers between different devices without CPU intervention. The source and destination of a DMA transfer can be any of the memory mapped modules existent in the device such device such such as SPI, UART, and and so on, or memory itself. Peripherals like SQI, ADC, and so on with dedicated DMA can also access the generic system DMA. The following are key features of the the DMA Controller:
- Eight identical channels: - Auto-increment source and destination address registers
- - Source and destination pointers - Memory to memory and memory to peripheral transfers
- CRC module can be assigned to any of the available channels
- - CRC module is highly configurable
- « Automatic Word-size detection: - Transfer granularity, down to byte level - Bytes need not be word-aligned at source and destination
FIGURE 10-1: DMA BLOCK DIAGRAM
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INT Controller System IRQ<br>rT TTT TT TT i|<br>DMA |«@— SsYSCLK<br>||<br>| oY Bus ystem Bus + Bus Arbitration<br>| Interface<br>| ] lg |<br>| |<br>(DMACON) oe<br>| |<br>| Channel Priority |<br>|<br>**----- End of picture text -----**<br>
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ee DS70005425A-page 148 Preliminaryy Da Data Sheet © 2020 Microchipi i Technology Inc.
PIC32MZ W1 and WFI32E01 Family
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## REGISTER 10-1: DMACON: DMA CONTROLLER CONTROL REGISTER
|Bit|Bit<br>Bit|Bit|Bit|Bit|Bit<br>Bit<br>Bit|
|---|---|---|---|---|---|
|Range|| 31/23/15/7 | 30/22/14/6 |29/21/13/5 |28/20/12/4||28/20/12/4|| 27/19/11/3|| 26/18/10/2 | 25/17/9/1 | 24/16/8/0|
||SES BES|SENSES||BES|SESS sess|
||SS<br>ee|ET|EE|ee|ee<br>ee eee|
|°|[on [=|=|susreno|| omasusy|| — | — | — ||
|Legend:||||||
|R = Readable bit||W = Writable|bit|U = Unimplemented bit, read as ‘0’||
|-n=ValueatPOR||‘1’=Bitisset||‘0’=Bitiscleared<br>X=Bitisunknown||
bit 31-16 Unimplemented: Read as ‘0’
- bit 15 ON: DMA On bit 1 = DMA module is enabled 0 = DMA module is disabled
- bit 14-13 Unimplemented: Read as ‘0’
- bit 12 SUSPEND: DMA Suspend bit 1 = DMA transfers are suspended to allow CPU uninterrupted access to data bus 0 = DMA operates normally
- bit 11 DMABUSY: DMA Module Busy bit 1 = DMA module is active and is transferring data 0 = DMA module is disabled and not actively transferring data
- bit 10-0 Unimplemented: Read as ‘0’
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© 2020 Microchip Technology Inc. Preliminary Data Sheet
DS70005425A-page 149
PIC32MZ W1 and WFI32E01 Family
## ee
## REGISTER 10-2: DMASTAT: DMA STATUS REGISTER
|Bit<br>Bit<br>Bit|Bit<br>Bit<br>Bit<br>Bit<br>Bit|Bit|
|---|---|---|
|Range | 31/23/15/7 | 30/22/14/6|| 29/21/13/5 | 28/20/12/4 |27/19/11/3 | 26/18/10/2 | 25/17/9/1|24/16/8/0|
|TooLR<br>| uo | oC]<br>OC]<br>| CT]<br>]<br>“<br>[| RowR [| =<br>| = | = | = | = | = | <br>pene |Se<br>pe SE Se<br>ee ee||CY<br> = J|
|° (enc|||
|Legend:|||
|R = Readable bit|W = Writable bit<br>U = Unimplemented bit, read as ‘0’||
|-n=ValueatPOR|‘1’=Bitisset<br>‘0’=Bitiscleared<br>x=Bitisunknown||
bit 31 RDWR: Read/Write Status bit 1 =Last DMA bus access when an error was detected was a read 0 =Last DMA bus access when an error was detected was a write bit 30-3 Unimplemented: Read as ‘0’
bit 2-0 | DMACH[2:0]: DMA Channel bits These bits contain the value of the most recent active DMA channel when an error is detected.
REGISTER 10-3: DMAADDR: DMA ADDRESS REGISTER
|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit|Bit|
|---|---|
|Range| 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1|24/16/8/0|
|—————————————<br>}ante PRP Le |e |e ef ee |e |e<br>| ase B21 ne | ne |<br>ee ee<br>| ro | #2_1_ee<br>ke_[_eee fe |e |e||
|Legend:||
|R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’||
|-n=ValueatPOR<br>‘1’=Bitisset<br>‘0’=Bitiscleared<br>x=Bitisunknown||
bit 31-0 DMAADDR[31:0]: DMA Module Address bits These bits contain the address of the most recent DMA access when an error is detected. Note: |The DMAEADDR register will be cleared when its contents are read. If more than one error occurs at the same time, the read transaction will be recorded. Additional later transfers with an error will not update this register until it has been read or cleared.
ee DS70005425A-page 150 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family smn
|REGISTER 10-4:<br>DCRCCON: DMA CRC CONTROL REGISTER|REGISTER 10-4:<br>DCRCCON: DMA CRC CONTROL REGISTER|
|---|---|
|Bit|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit|
|Range|| 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 |27/19/11/3 |26/18/10/2 | 25/17/9/1 | 24/16/8/0|
|4|Se<br>ror)<br>sot [dro_|
|8|ete|
|°|[Tercen[ercare™[crore [| — | — | ———cRoHR<br>CS|
|Legend:||
|R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’||
|-n=ValueatPOR<br>‘1’=Bitisset<br>‘0’=Bitiscleared<br>x=Bitisunknown||
- bit 31-30 Unimplemented: Read as ‘0’
- bit 29-28 BYTO[1:0]: CRC Byte Order Selection bits
- 11 = Endian byte swap on half-word boundaries (in other words, source half-word order with reverse source byte order per half-word)
- 10 = Swap half-words on word boundaries (in other words, reverse source half-word order with source byte order per half-word)
- 01 = Endian byte swap on word boundaries (in other words, reverse source byte order)
- 00 = No swapping (i.e., source byte order)
- bit27 | WBO: CRC Write Byte Order Selection bit!)
- 1 = Source data is written to the destination re-ordered as defined by BYTO[1:0]
- 0 = Source data is written to the destination unaltered
- bit 26-25 Unimplemented: Read as ‘0’
- bit 24 BITO: CRC Bit Order Selection bit
- When CRCTYP (DCRCCONJS]) = 1 (CRC module is in IP Header mode):
- 1 = The IP header checksum is calculated Least Significant bit (LSb) first (in other words, reflected)
- 0 = The IP header checksum is calculated Most Significant bit (MSb) first (in other words, not reflected)
- When CRCTYP (DCRCCONJ5]) = 0 (CRC module is in LFSR mode):
- 1 = The LFSR CRC is calculated Least Significant bit first (in other words, reflected)
- 0 = The LFSR CRC is calculated Most Significant bit first (in other words, not reflected)
- bit 23-13 Unimplemented: Read as ‘0’ bit 12-8 PLEN[4:0]: Polynomial Length bits‘) When CRCTYP (DCRCCONJ5]) = 1 (CRC module is in IP Header mode): These bits are unused.
- When CRCTYP (DCRCCONJ5)) = 0 (CRC module is in LFSR mode): Denotes the length of the polynomial — 1.
- bit 7 CRCEN: CRC Enable bit
- 1 = CRC module is enabled and channel transfers are routed through the CRC module
- 0 = CRC module is disabled and channel transfers proceed normally
Note 1: When WBO = 1, unaligned transfers are not supported and the CRCAPP bit cannot be set.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 151
## PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 10-4: DDCRCCON: DMA CRC CONTROL REGISTER (CONTINUED) bit 6 CRCAPP: CRC Append Mode bit!)
|bit|6|CRCAPP: CRC AppendAppend Mode bit!)|CRCAPP: CRC AppendAppend Mode bit!)|
|---|---|---|---|
|||1 = DMAtransfers data from the source into the CRC but not to the destination. When a block transfer com-||
|||pletes the DMAwrites the calculated CRC value to the location given by CHxDSA.||
|||0 = DMA transfers data from the source through the CRC obeying WBO as|it writes the data to the|
|||destination.||
|bit|5|CRCTYP: CRC Type Selection bit||
|||1 = The CRC module calculates an IP header checksum||
|||0 = The CRC module calculates<br>a LFSR CRC||
|bit|4-3|Unimplemented: Read as ‘0’||
|bit|2-0|CRCCH[2:0]: CRC Channel Select bits||
|||111 = CRC is assigned to Channel 7||
|||110 = CRC is assigned to Channel 6||
|||101 = CRC is assigned to Channel 5||
|||100 = CRC is assigned to Channel 4||
|||011 = CRC is assigned to Channel 3||
|||010 = CRC is assigned to Channel 2||
|||001 = CRC is assigned to Channel 1||
|||000=CRCisassignedtoChannel0||
## Note 1: When WBO =
1, unaligned transfers are not supported and the CRCAPP bit cannot be set.
renner eee e rereerence eee eee DS70005425A-page 152 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
## REGISTER 10-5: DCRCDATA: DMA CRC DATA REGISTER
**==> picture [446 x 174] intentionally omitted <==**
**----- Start of picture text -----**<br>
Bit Bit Bit Bit Bit Bit Bit Bit Bit<br>Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0<br>:<br>:<br>,<br>|<br>Legend:<br>R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’<br>-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown<br>**----- End of picture text -----**<br>
## bit 31-0 DCRCDATA[31:0]: CRC Data Register bits
Writing to this register will seed the CRC generator. Reading from this register returns the current value of the CRC. Bits greater than PLEN will return ‘0’ on any read.
When CRCTYP (DCRCCONJ5]) = 1 (CRC module is in IP Header mode):
Only the lower 16 bits contain IP header checksum information. The upper 16 bits are always ‘0’. Data written to this register is converted and read back in 1’s complement form (in other words, current IP header checksum value).
When CRCTYP (DCRCCONJ5]) = 0 (CRC module is in LFSR mode): Bits greater than PLEN returns ‘0’ on any read.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 153
PIC32MZ W1 and WFI32E01 Family
seman
## REGISTER 10-6: DCRCXOR: DMA CRCXOR ENABLE REGISTER
|Bit|Bit|Bit|Bit|Bit|Bit|Bit|Bit|Bit|Bit|
|---|---|---|---|---|---|---|---|---|---|
|Range| 31/23/15/7 | 30/22/14/6|||||29/21/13/5 | 28/20/12/4 |27/19/11/3 | 26/18/10/2 | 25/17/9/1|||||| 24/16/8/0|
|:||||||||||
|:||||||||||
||:|||||||||
|:||||||||||
|Legend:||||||||||
|R =|Readable bit|||W = Writable bit||U = Unimplemented bit,||read as ‘0’||
|-n=|ValueatPOR|||‘1’=Bitisset||‘0’=Bitiscleared||x=Bitisunknown||
- bit 31-0 DCRCXOR[31:0]: CRC XOR Register bits
- When CRCTYP (DCRCCONJS}) = 1 (CRC module is in IP Header mode): This register is unused.
When CRCTYP (DCRCCONJ5]) = 0 (CRC module is in LFSR mode):
- 1 = Enable the XOR input to the Shift register
- 0 = Disable the XOR input to the Shift register; data is shifted in directly from the previous stage in the register
renner eee e rereerence eee eee DS70005425A-page 154 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
**==> picture [324 x 8] intentionally omitted <==**
**----- Start of picture text -----**<br>
REGISTER 10-7: DCHxCON: DMA CHANNEL x CONTROL REGISTER<br>**----- End of picture text -----**<br>
|Bit|Bit<br>Bit|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit|
|---|---|---|
|Range|| 31/23/15/7 |30/22/14/6|| 29/21/13/5 |28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0|
|:|||
|°<br>7<br>—[|[ensusy[=<br>FL RwO | Rwo <br>cHEN® | cHaeD|[cuirenen[=| cupaten[>< —_—'| CHHNSTT |<br> | Rwo | Rwo | uo | Ro | Rwo [ Rwo |<br> | cHcHN<br>[| cHAeEN |<br>| CHEDET |<br>CHPRIIO]|
|Legend:|||
|R = Readable bit||W = Writable bit<br>U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR||‘1’=Bitisset<br>‘0’=Bitiscleared<br>X=Bitisunknown|
- bit 31-24 CHPIGN[7:0]: Channel Register Data bits Pattern Terminate mode:
- Any byte matching these bits during a pattern match may be ignored during the pattern match determination when the CHPIGNEN bit is set. If a byte is read that is identical to this data byte, the pattern match logic will treat it as a “don’t care” when the pattern matching logic is enabled and the CHPIGEN bit is set.
- bit 23-16 Unimplemented: Read as ‘0’
- bit 15 CHBUSY: Channel Busy bit
- 1 = Channel is active or enabled
- 0 = Channel is inactive or disabled
- bit 14 Unimplemented: Read as ‘0’
- bit 13 CHPIGNEN: Enable Pattern Ignore Byte bit
- 1 = Treat any byte that matches the CHPIGN[7:0] bits as a “don’t care” when pattern matching is enabled 0 = Disable this feature
- bit 12 Unimplemented: Read as ‘0’
- bit 11 CHPATLEN: Pattern Length bit
- 1 =2 byte length
- 0 = 1 byte length
- bit 10-9 Unimplemented: Read as ‘0’ bit 8 CHCHNS: Chain Channel Selection bit!) 1 = Chain to channel lower in natural priority (CH1 is enabled by CH2 transfer complete) 0 = Chain to channel higher in natural priority (CH1 is enabled by CHO transfer complete)
- bit 7 CHEN: Channel Enable bit!) 1 = Channel is enabled
- 0 = Channel is disabled
- bit 6 CHAED: Channel Allow Events If Disabled bit 1 = Channel start/abort events are registered, even if the channel is disabled
- 0 = Channel start/abort events are ignored if the channel is disabled
- bit 5 CHCHN: Channel Chain Enable bit 1 =Allow channel to be chained 0 = Do not allow channel to be chained
- Note 1: The chain selection bit takes effect when chaining is enabled (in other words, CHCHN = 1). 2: When the channel is suspended by clearing this bit, the user application should poll the CHBUSY bit (if available on the device variant) to see when the channel is suspended, as it may take some clock cycles to complete a current transaction before the channel is suspended.
## mE
© 2020 Microchip Technology Inc. Preliminary Data Sheet
DS70005425A-page 155
## PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 10-7: DCHxCON: DMA CHANNEL x CONTROL REGISTER (CONTINUED)
bit 4 CHAEN: Channel Automatic Enable bit
|bit|4|CHAEN: Channel Automatic Enable bit|
|---|---|---|
|||1 = Channel is continuously enabled, and not automatically disabled after a block transfer is complete|
|||0 = Channel is disabled on block transfer complete|
|bit|3|Unimplemented: Read as ‘0’|
|bit|2|CHEDET: Channel Event Detected bit|
|||1 =An event has been detected|
|||0 = No events have been detected|
|bit|1-0|CHPRI[1:0]: Channel Priority bits|
|||11 = Channel has priority 3 (highest)|
|||10 = Channel has priority 2|
|||01 = Channel has priority 1|
|||00=Channelhaspriority0|
- Note 1: The chain selection bit takes effect when chaining is enabled (in other words, CHCHN = 1). 2: When the channel is suspended by clearing this bit, the user application should poll the CHBUSY bit (if available on the device variant) to see when the channel is suspended, as it may take some clock cycles to complete a current transaction before the channel is suspended.
renner eee e rereerence eee eee DS70005425A-page 156 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
**==> picture [366 x 8] intentionally omitted <==**
**----- Start of picture text -----**<br>
REGISTER 10-8: DCHxECON: DMA CHANNEL x EVENT CONTROL REGISTER<br>**----- End of picture text -----**<br>
**==> picture [454 x 153] intentionally omitted <==**
**----- Start of picture text -----**<br>
Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0<br>a ee<br>° _[Perorce | casort | paten | SiROEN [ AGEN [| — | — | — |<br>Legend: S = Settable bit<br>R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’<br>-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared X = Bit is unknown<br>**----- End of picture text -----**<br>
- bit 31-24 Unimplemented: Read as ‘0’ bit 23-16 CHAIRQ[7:0]: Channel Transfer Abort IRQ bits!)
11111111 = Interrupt 255 aborts any transfers in progress and set CHAIF flag
00000001 = Interrupt 1 aborts any transfers in progress and set CHAIF flag
- 00000000 = Interrupt O aborts any transfers in progress and set CHAIF flag
- bit 15-8 CHSIRQ[7:0]: Channel Transfer Start IRQ bits(") 11111111 = Interrupt 255 initiates a DMA transfer
- 00000001 = Interrupt 1 initiates a DMA transfer 00000000 = Interrupt 0 initiates a DMA transfer
- bit 7 CFORCE: DMA Forced Transfer bit 1 =A DMA transfer is forced to begin when this bit is written to a ‘1’ 0 = This bit always reads ‘0’
- bit 6 CABORT: DMA Abort Transfer bit 1 =A DMA transfer is aborted when this bit is written to a ‘1’ 0 = This bit always reads ‘0’
- bit 5 PATEN: Channel Pattern Match Abort Enable bit 1 =Abort transfer and clear CHEN on pattern match 0 = Pattern match is disabled
- bit 4 SIRQEN: Channel Start IRQ Enable bit 1 = Start channel cell transfer if an interrupt matching CHSIRQ occurs
- 0 = Interrupt number CHSIRQ is ignored and does not start a transfer
- bit 3 AIRQEN: Channel Abort IRQ Enable bit 1 = Channel transfer is aborted if an interrupt matching CHAIRQ occurs 0 = Interrupt number CHAIRQ is ignored and does not terminate a transfer
- bit 2-0 Unimplemented: Read as ‘0’
- Note 1: See Table 8-2 for the list of available interrupt IRQ sources.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 157
## PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 10-9: DCHxINT: DMA CHANNEL x INTERRUPT CONTROL REGISTER
|Bit|Bit<br>Bit<br>Bit<br>Bit||Bit|Bit||Bit|Bit|
|---|---|---|---|---|---|---|---|
|Range | 31/23/15/7 | 30/22/14/6 |29/21/13/5 | 28/20/12/4 |27/19/11/3||27/19/11/3 |||26/18/10/2|| 25/17/9/1 |||24/16/8/0|
|pai|EE ee|ee||||eo||
|ae<br>|||||||||
|ss|Se eS<br>Se|||||||
|:||||||||
|Legend:||||||||
|R = Readable bit<br>W = Writable bit||U =|Unimplemented bit, read|||as ‘0’||
|-n = Value at POR<br>‘1’ = Bit is set||‘0’ =|Bit is cleared||x =|Bit is unknown||
|bit 31-24|Unimplemented: Read as ‘0’|||||||
|bit 23|CHSDIE: Channel Source Done Interrupt Enable bit|||||||
||1 = Interrupt is enabled|||||||
||0 = Interrupt is disabled|||||||
|bit 22|CHSHIE: Channel Source Half Empty Interrupt Enable|bit||||||
||1 = Interrupt is enabled|||||||
||0 = Interrupt is disabled|||||||
|bit 21|CHDDIE: Channel Destination Done Interrupt Enable bit|||||||
||1 = Interrupt is enabled|||||||
||0 = Interrupt is disabled|||||||
|bit 20|CHDHIE: Channel Destination Half Full Interrupt Enable bit|||||||
||1 = Interrupt is enabled|||||||
||0 = Interrupt is disabled|||||||
|bit 19|CHBCIE: Channel Block Transfer Complete Interrupt Enable bit|||||||
||1 = Interrupt is enabled|||||||
||0 = Interrupt is disabled|||||||
|bit 18|CHCCIE: Channel Cell Transfer Complete Interrupt Enable||bit|||||
||1 = Interrupt is enabled|||||||
||0 = Interrupt is disabled|||||||
|bit 17|CHTAIE: Channel TransferAbort Interrupt Enable bit|||||||
||1 = Interrupt is enabled|||||||
||0 = Interrupt is disabled|||||||
|bit 16|CHERIE: Channel Address Error Interrupt Enable bit|||||||
||1 = Interrupt is enabled|||||||
||0 = Interrupt is disabled|||||||
|bit 15-8|Unimplemented: Read as ‘0’|||||||
|bit 7|CHSDIF: Channel Source Done Interrupt Flag bit|||||||
||1 = Channel Source Pointer has reached end of source (CHSPTR =|||CHSSIZ)||||
||0 = No interrupt is pending|||||||
|bit 6|CHSHIF: Channel Source Half Empty Interrupt Flag bit|||||||
||1 = Channel Source Pointer has reached midpoint of source (CHSPTR = CHSSIZ/2)|||||||
||0=Nointerruptispending|||||||
Meeeaa DS70005425A-page 158 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
## REGISTER 10-9: DCHxINT: DMA CHANNEL x INTERRUPT CONTROL REGISTER (CONTINUED)
- bit 5 CHDDIF: Channel Destination Done Interrupt Flag bit
- 1 = Channel Destination Pointer has reached end of destination (CHDPTR = CHDSIZ) 0 = No interrupt is pending
- bit 4 CHDHIF: Channel Destination Half Full Interrupt Flag bit 1 = Channel Destination Pointer has reached midpoint of destination (CHDPTR = CHDSIZ/2) 0 = No interrupt is pending
- bit 3 CHBCIF: Channel Block Transfer Complete Interrupt Flag bit 1 =A block transfer has been completed (the larger of CHSSIZ/CHDSIZ bytes has been transferred), or a pattern match event occurs
- 0 = No interrupt is pending
- bit 2 CHCCIF: Channel Cell Transfer Complete Interrupt Flag bit
- 1 =Acell transfer has been completed (CHCSIZ bytes have been transferred) 0 = No interrupt is pending
- bit 1 CHTAIF: Channel Transfer Abort Interrupt Flag bit 1 = An interrupt matching CHAIRQ has been detected and the DMA transfer has been aborted 0 = No interrupt is pending
- bit 0 CHERIF: Channel Address Error Interrupt Flag bit 1 =Achannel address error has been detected; either the source or the destination address is invalid 0 = No interrupt is pending
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 159
PIC32MZ W1 and WFI32E01 Family
seman
REGISTER 10-10: DCHxSSA: DMA CHANNEL x SOURCE START ADDRESS REGISTER
31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0
Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 CHSSAJ[31:0] Channel Source Start Address bits
Note: This must be the physical address of the source.
**==> picture [449 x 36] intentionally omitted <==**
**----- Start of picture text -----**<br>
REGISTER 10-11: DCHxDSA: DMA CHANNEL x DESTINATION START ADDRESS REGISTER<br>Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 24/16/8/0<br>**----- End of picture text -----**<br>
**==> picture [425 x 35] intentionally omitted <==**
**----- Start of picture text -----**<br>
Legend:<br>R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’<br>-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown<br>**----- End of picture text -----**<br>
bit 31-0 CHDSA[31:0]: Channel Destination Start Address bits
Note: This must be the physical address of the destination.
renner eee e rereerence eee eee DS70005425A-page 160 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
## REGISTER 10-12: DCHxSSIZ: DMA CHANNEL x SOURCE SIZE REGISTER
|Bit|Bit|Bit<br>Bit||Bit||Bit<br>Bit||Bit|Bit|
|---|---|---|---|---|---|---|---|---|---|
|Range|| 31/23/15/7 | 30/22/14/6 | 29/21/13/5 |||28/20/12/4 |27/19/11/3 |26/18/10/2 | 25/17/9/1 | 24/16/8/0|||||||
||BE|EE|ee||ee ee||ee||ee|
||BEE EE<br>EE||EE||Ee<br>Ee||Ee||ee|
|:||||||||||
|7<br>:||||||||||
|Legend:||||||||||
|R = Readable bit||W = Writable|bit||U =|Unimplemented bit, read||as ‘0’||
|-n = Value at POR||‘1’ = Bit is set|||‘0’ =|Bit is cleared|X = Bit is unknown|||
|bit 31-16|Unimplemented: Read as ‘0’|||||||||
|bit 15-0|CHSSIZ[15:0]: Channel Source Size bits|||||||||
||1111111111111111 = 65,535 byte source|||size||||||
||0000000000000010 = 2 byte source size|||||||||
||0000000000000001 = 1 byte source size|||||||||
||0000000000000000 = 65,536 byte source|||size||||||
|REGISTER|REGISTER 10-13:|DCHxDSIZ: DMA CHANNEL||x DESTINATION SIZE REGISTER||||||
|Bit|Bit|Bit<br>Bit||Bit|Bit<br>Bit|||Bit|Bit|
|Range|| 31/23/15/7|| 30/22/14/6 | 29/21/13/5 ||28/20/12/4 |27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0|||||||
|“|DES|SEN SEA|SEN||S-ASEASEAPsEws|||||
|—_<br>—~to|=|[| = | = |||= |||= | = |||= | = |||
|a<br>:||||CHDSIZ[15:8]||||||
|-<br>.||||CHDSIZ[7:0]||||||
|Legend:||||||||||
|R = Readable bit||W = Writable|bit||U =|Unimplemented bit, read||as ‘0’||
|-n=ValueatPOR||‘1’=Bitisset|||‘0’=|Bitiscleared|x=|Bitisunknown||
## REGISTER 10-13: DCHxDSIZ: DMA CHANNEL x DESTINATION SIZE REGISTER
bit 31-16 Unimplemented: Read as ‘0’
bit 15-O CHDSIZ[15:0]: Channel Destination Size bits 1111111111111111 = 65,535 byte destination size
0000000000000010 = 2 byte destination size 0000000000000001 = 1 byte destination size 0000000000000000 = 65,536 byte destination size
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 161
PIC32MZ W1 and WFI32E01 Family
## seman
REGISTER 10-14: DCHxSPTR: DMA CHANNEL x SOURCE POINTER REGISTER
|Bit|Bit<br>Bit<br>Bit|Bit|Bit<br>Bit<br>Bit|Bit|
|---|---|---|---|---|
|Range|| 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4|||27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0||
||ai||||
|isp <br>es|a<br>ee es<br> [RO<br>[| Ro [ Ro [ <br> ES<br>SS|Ro<br>[| ro [ Ro | Ro<br> Se||[| RO ||
|Legend:|||||
|R = Readable bit<br>W = Writable bit|||U = Unimplemented bit, read as ‘0’||
|-n=ValueatPOR<br>‘1’=Bitisset|||‘0’=Bitiscleared<br>x=Bitisunknown||
bit 31-16 Unimplemented: Read as ‘0’ bit 15-O CHSPTR[15:0]: Channel Source Pointer bits
1111111111111111 = Points to byte 65,535 of the source
0000000000000001 = Points to byte 1 of the source
0000000000000000 = Points to byte O of the source
Note: | When in Pattern Detect mode, this register is reset on a pattern detect.
REGISTER 10-15: DCHxDPTR: DMA CHANNEL x DESTINATION POINTER REGISTER
|Bit|Bit|Bit|Bit|Bit<br>Bit|Bit|Bit<br>Bit|
|---|---|---|---|---|---|---|
|Range|| 31/23/15/7|| 30/22/14/6 | 29/21/13/5 | 28/20/12/4 |27/19/11/3 |26/18/10/2|||26/18/10/2 | 25/17/9/1 | 24/16/8/0||
|‘|hE|Ee|ee|ee ee|eee eee ee||
|x6<br>7|||||||
||Pp Ro|| ROT oT||| RT<br>CHDPTR[15:8]||RTeR|
|SPsc<br>.|sc<br>CHDPTR[7:0]||||||
|Legend:|||||||
|R = Readable bit|||W = Writable bit|U = Unimplemented||bit, read as ‘0’|
|-n=ValueatPOR|||‘1’=Bitisset|‘0’=Bitiscleared||x=Bitisunknown|
bit 31-16 Unimplemented: Read as ‘0’
bit 15-O CHDPTR[15:0]: Channel Destination Pointer bits
1111111111111111 = Points to byte 65,535 of the destination
0000000000000001 = Points to byte 1 of the destination
0000000000000000 = Points to byte 0 of the destination
renner eee e rereerence eee eee DS70005425A-page 162 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
## REGISTER 10-16: DCHxCSIZ: DMA CHANNEL x CELL-SIZE REGISTER
|Bit<br>Bit|Bit<br>Bit|Bit<br>Bit<br>Bit|Bit|Bit|
|---|---|---|---|---|
|Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 |27/19/11/3 |26/18/10/2 | 25/17/9/1||||| 24/16/8/0|
|ee <br>pes|S|ee ee <br> Se|ee|||
|:|||||
|7<br>:|||||
|Legend:|||||
|R = Readable bit|W = Writable bit|U = Unimplemented bit, read as ‘0’|||
|-n=ValueatPOR|‘1’=Bitisset|‘0’=Bitiscleared|x=Bitisunknown||
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 CHCSIZ[15:0]: Channel Cell-Size bits 1111111111111111 = 65,535 bytes transferred on an event
0000000000000010 = 2 bytes transferred on an event 0000000000000001 = 1 byte transferred on an event 0000000000000000 = 65,536 bytes transferred on an event
## REGISTER 10-17: DCHxCPTR: DMA CHANNEL x CELL POINTER REGISTER
|Bit<br>Bit<br>Bit|Bit|Bit|Bit<br>Bit|Bit<br>Bit|
|---|---|---|---|---|
|Range | 31/23/15/7 | 30/22/14/6||29/21/13/5 | 28/20/12/4|||27/19/11/3 | 26/18/10/2|| 25/17/9/1 | 24/16/8/0|
|ee a<br>ee<br>pate|<br>ee <br>ig<br>EF RO [| ro<br>[| Ro<br>[| Ro<br>:|||ee<br>[| Ro | Ro|[| Ro<br>[| Ro ||
|| mo | eet se|| Se||ee||
|Legend:|||||
|R = Readable bit|W = Writable bit||U = Unimplemented bit,|read as ‘0’|
|-n=ValueatPOR|‘1’=Bitisset||‘0’=Bitiscleared|x=Bitisunknown|
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 CHCPTR[15:0]: Channel Cell Progress Pointer bits 1111111111111111 = 65,535 bytes have been transferred since the last event
0000000000000001 = 1 byte has been transferred since the last event 0000000000000000 = 0 bytes have been transferred since the last event
Note: When in Pattern Detect mode, this register is reset on a pattern detect.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 163
PIC32MZ W1 and WFI32E01 Family
seman
REGISTER 10-18: DCHxDAT: DMA CHANNEL x PATTERN DATA REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0 pt PS pee See eT : : Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’ bit 15-0 ©CHPDAT[15:0]: Channel Data Register bits
Pattern Terminate mode: Data to be matched must be stored in this register to allow terminate on match.
All other modes: Unused.
renner eee e rereerence eee eee DS70005425A-page 164 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
## 11.0 OSCILLATOR CONFIGURATION
- Note: This data sheet summarizes _ the features of the PIC32MZ W1 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 42. “Oscillators with Enhanced PLL” (DS60001250) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
The PIC32MZ W1 oscillator system has the following modules and features:
- ¢ Four external and internal oscillator options as clock sources
- Four on-chip PLLs with user-selectable input divider, multiplier and output divider to boost operating frequency on select internal and external oscillator sources
- On-chip user-selectable divisor postscaler on select oscillator sources
- ¢ Software-controllable switching between various clock sources
- « Dedicated on-chip PLL for USB, Wi-Fi/Ethernet and Bluetooth modules
- Flexible reference clock output
- ¢ Multiple clock branches for peripherals for better performance flexibility
* Clock switch/slew control with output divider A block diagram of the oscillator system is shown in Figure 11-1. The clock distribution is provided in Table 11-1.
## me
© 2020 Microchip Technology Inc.
Preliminary Data Sheet
DS70005425A-page 165
## PIC32MZ W1 and WFI32E01 Family ne
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**----- Start of picture text -----**<br>
pewPt ec ETHCLKOUT EN<br>| OR.a _ | . Ethernet Clock(ECLK)<br>FRC || - Ew BWSEL q | dl || EWBYPASS<br>Foose} ewrttrostoiva |<br>= " , | ewicik<br>| EWPLLREFDIV<br>EWICLK| an : f Four | WiFi Subsystem Clock (WCLK)<br>| oe i l<br>| EWPLLFBDIV ewaoses, | EWBYPASS<br>||<br>||<br>j| UsePt Posc FRC USB Clock (USBCLK)<br>|| | UFRCEN<br>posc_ || x- :—j »D &F 7. at a.- . | UBYPASS<br>| J q = d<br>| UPLLREFDIV ——- UPLLPOSTDIV1<br>| pen | ECLK<br>| Tt ! oe<br>| UPLLFBDIV MICU | - sik |<br>bo REFCLKI DJ | areal |<br>[svstemPtL Posc ! |<br>| |SPLLICLK PRG ROTRIM |<br>POsC, re |_ : a || LPRC | ON OE II<br> |, fe og »o an. mo > + [2x (N#M/512)] f>—x |<br>| = aaa) eS | sosc I REFCLKO |<br>| SPLLREFDIV SPLLPOSTDIV1 | SBYPASS! pay cik | Fe |<br>SPLLCLK | f—. I | RODIV |<br>| ey | SYSCLK | |<br>L SPLLFBDIV | UPLL<br>SPLL<br>ROSEL<br>Primary Oscillator<br>(Posc) SPL<br>om Xtal_in POSC SYSCLK<br>SsberAL Re logic<br>Rs USBCLK<br>we Xtal_out4) | |<br>— | Peripheral Bus Clock n |<br>a<br>| 8 Miz typicalTUN | ’ FRCDIV— BTPLL || oonS eae)— PBCLK ,|<br>Secondary Oscillator —Oscillatorcee | LPRC ||| myPBnDIV |||<br>(sosc) ———— | |<br>sosco sosc TTTTTT TTT<br>SOSCEN SOSCSEL Ect<br>—<br>sosci WCLK<br>FNOSC<br>Timer1, RTCC, WOT<br>t Bluetooth PLL 7 Timer1, RTCC<br>i] BTPLLICLK<br>Pose | sWiskt, | BTCLKOUTEN<br>Fe]i OO Se be P PO =Fou Bluetooth Clock (BTCLK)<br>FRC | oa s ad = |<br>BTICLK IeTPLLREFDIV BTPLLPOSTDIV | BIBYPASS<br>| - ] |<br>TT<br>| BTPLLFBDIV |<br>SSeSoe el<br>Notes: 1. Aseries resistor, Rs, may be required for AT strip cut crystals, or to eliminate clipping.<br>2. The internal feedback resistor, RF, is typically1 MQ.<br>3. Refer to Oscillators with Enhanced PLL (DS60001250) in the “PIC32 Family Reference Manual for help in determining the best<br>oscillator components.<br>4. Refer to 41.0 “Packaging Information” for frequency limitations.<br>**----- End of picture text -----**<br>
EE DS70005425A-page 166 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
SSS
TABLE 11-1: SYSTEM AND PERIPHERAL CLOCK DISTRIBUTION
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|---|
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eee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 167
PIC32MZ W1 and WFI32E01 Family
## SSS
TABLE 11-1: SYSTEM AND PERIPHERAL CLOCK DISTRIBUTION (CONTINUED)
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_————————————OOOO DS70005425A-page 168 Preliminary Data Sheet © 2020 Microchip Technology Inc.
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PIC32MZ W1 and WFI32E01 Family
smn
## REGISTER 11-1: OSCCON: CRU OSCILLATOR CONTROL REGISTER
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**----- Start of picture text -----**<br>
|||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Bit|Bit|Bit|Bit|Bit|Bit|Bit|Bit|Bit|
|:|
|er|ee|ee|ee|nn|
|||
|ee|
|a|EEE|Ne|ee|
|reuxtock[|—|||—|||suPen ||oF|||uFRCEN|||SoscEN|||OSWEN ||
|Legend:|HC|=|Hardware|Cleared|HS|=|Hardware|Set|
|R|=|Readable|bit|W|=|Writable|bit|U|=|Unimplemented|bit,|read|as|‘0’|
|-n|=|Value|at|POR|‘1’|=|Bit|is|set|‘0’|=|Bit|is|cleared|x|=|Bit|is|unknown|
|L|=|Value|set from|Configuration|bits|on|POR|
**----- End of picture text -----**<br>
- bit 31-27 Unimplemented: Read as ‘0’
- bit 26-24 FRCDIV[2:0]: Fast RC Clock Divider bits 000 = FRC divided by 1 (default value) 001 = FRC divided by 2 010 = FRC divided by 4 011 = FRC divided by 8 100 = FRC divided by 16 101 = FRC divided by 32 110 = FRC divided by 64 111 = FRC divided by 256
- bit 23 DRMEN: Enable Dream Mode bit 1 = When SLPEN = 1, DMA transfer complete causes Sleep mode to be entered 0 = DMA transfer has no effect
- bit 22 Unimplemented: Read as ‘0’ bit 21 WAKE2SPD: 2-Speed startup enabled in Sleep mode bit 1 = When the device exits Sleep mode, the SYS_CLK is from FRC until the selected clock is ready 0 = When the device exits Sleep mode, the SYS_CLK is from the selected clock
- bit 20-16 Unimplemented: Read as ‘0’
- bit 15-12 COSC[3:0]: Current Oscillator Selection bits (Read-only)
- 0000 = Fast RC Oscillator (FRC) divided by OSCCON.FRCDIV (supports FRC/16 and FRC/1) 0001 = System PLL (SPLL module) (input clock and divider set by SPLLCON) 0010 = Primary Oscillator (POSC) 0011 = USB PLL (UPLL module) (input clock and divider set by UPLLCON) 0100 = Secondary Oscillator (SOSC) 0101 = Low-Power RC Oscillator (LPRC) 0110 = BT PLL (input clock and divider set by BTPLLCON) 0111 = EWPLL Ethernet clock (input clock and divider set by EWPLLCON) 1000 = EWPLL Wi-Fi clock (input clock and divider set by EWPLLCON)
Note 1: Loaded with NOSC[3:0] at the completion of a successful clock switch.
2: Set to FRC value (0000) when FSCM detects a failure and switches clock to FRC.
Note: The system unlock sequence must be done before this register can be written.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 171
## PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 11-1: OSCCON: CRU OSCILLATOR CONTROL REGISTER (CONTINUED)
## bit 11-8 NOSC[3:0]: New Oscillator Selection bits
|bit|11-8|NOSC[3:0]: New Oscillator Selection bits|
|---|---|---|
|||0000 = FRC divided by OSCCON. FRCDIV (supports FRC/16 and FRC/1)|
|||0001 = SPLL module (input clock and divider set by SPLLCON)|
|||0010 = POSC|
|||0011 = UPLL mode (input clock divider set by UPLLCON), was POSC with PLL|
|||0100<br>= SOSC|
|||0101<br>=LPRC|
|||0110 = BT PLL (input clock and divider set by BTPLLCON)|
|||0111 = EWPLL Ethernet clock (input clock and divider set by EWPLLCON)|
|||1000 = EWPLL Wi-Fi clock (input clock and divider set by EWPLLCON)|
|bit|7|CLKLOCK: Clock Lock Enabled bit|
|||1 =All clock and PLL configuration registers are locked. These include OSCCON, OSCTRIM,|
|||SPLLCON, UPLLCON, and PBxDIV.|
|||0 = Clock and PLL selection registers are not locked, configurations may be modified|
|||Note 1:<br>Once set, this bit can only be cleared via a device Reset.|
|||2:<br>When active, this bit prevents writes to the following registers: NOSC[3:0], and OSWEN.|
|bit|6-5|Unimplemented: Read as ‘0’|
|bit|4|SLPEN: Enable Sleep Mode bit|
|||1 = When a WAIT instruction is executed, device enters Sleep mode|
|||0 = When a WAIT instruction is executed, device enters Idle mode|
|bit|3|CF: Clock Fail Detect bit (readable/writable/clearable by application)|
|||1 = FSCM detects clock failure|
|||0 = FSCM does not detect clock failure|
|||Note 1:<br>Writing a ‘1’ to this bitcauses a clock switching sequence to be initiated bythe clock switch state|
|||machine.|
|||2:<br>Resetwhen a valid clock switching sequence is initiated by the clock switch state machine.|
|||3:<br>This bit is set when clock fail event detected.|
|bit|2|UFRCEN: USB FRC Clock Enable bit|
|||1 = Enable FRC as the clock source for the USB clock source|
|||0 = Use the primary oscillator or UPLL as the USB clock source|
|bit|1|SOSCEN: 32 kHz Secondary (LP) Oscillator Enable bit|
|||1 = Enable SOSC|
|||0 = Disable SOSC|
|bit|0|OSWEN: Oscillator Switch Enable bit|
|||1 = Request oscillator switch to selection specified by NOSC[3:0] bits|
|||0 = Oscillator switch is complete|
|||Note1:<br>AWriteofvalue‘0’hasnoeffect.|
- 2: This bit is cleared by hardware after a successful clock switch; after redundant clock switch (NOSC = COSC) and when FSCM switches the oscillator to Fail-Safe Clock Source (FRC).
Note: The system unlock sequence must be done before this register can be written.
renner eee e rereerence eee eee DS70005425A-page 172 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
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**----- Start of picture text -----**<br>
REGISTER 11-2: OSCTUN: FRC TUNING REGISTER<br>**----- End of picture text -----**<br>
|Bit<br>Bit|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit|Bit|
|---|---|---|
|Range|31/23/15/7||30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1|24/16/8/0|
|Frese [ee <br>jis [ve <br>7:0<br>70|[nefoo fue fefev<br> [se {uo [ve fue {uo fue <br>|<br>ag|ve<br> {uo|
|Legend:|L = Value set from Configuration bits on POR||
|R = Readable bit|W = Writable bit<br>U = Unimplemented bit, read as ‘0’||
|-n=ValueatPOR|‘1’=Bitisset<br>‘0’=Bitiscleared<br>x=Bitisunknown||
bit 31-6 Unimplemented: Read as ‘0’
- bit 5-0 TUN[5:0]: Internal FRC Oscillator Tuning bits This bit field specifies the user tuning capability for the internal FRC oscillator. 011111 =Center frequency +2% 011110=
000001 =
- 000000 =Center frequency, oscillator is running at calibrated frequency (8MHz) 111111=
- 111110=
100001 =
100000 =Center frequency -2%
- Note 1: The system unlock sequence must be done before this register can be written.
- 2: OSCTUN functionality has been provided to help customers compensate for temperature effects on the FRC frequency over a wide range of temperatures. The tuning step size is an approximation, and is neither characterized nor tested.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 173
## PIC32MZ W1 and WFI32E01 Family
## seman
- REGISTER 11-3: SPLLCON: SPLL CONTROL REGISTER Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 24/16/8/0 SPuLReFoMa—|
- seus [seu [ | — |S
- Legend: L = Value set from Configuration bits on POR R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31 SPLL_BYP: SPLL Bypass bit; when this bit is set, the input clock REF bypasses PLL to PLLOUTx. Note: Recommendation is to setup SPLL first before setting up other PLLs especially when using SYSPLL for generating main system clock. Reset value must be 1, because PLL needs setup in SW for generating desired frequency.
- bit 30 SPLLICLK: Source Input Clock Selection bit: 0 = POSC is the SPLL input clock source 1 = FRC is the SPLL input clock source Note: The Reset value must be 1, because the POSC is not available upon Reset.
- bit 29-28 Unimplemented: Read as ‘0’ bit 27-22 SPLLREFDIV[5:0]: Reference Frequency Divide bit,1 ? SPLLDIVR ? 63, value of 0 is unused. bit 21-12 SPLLFBDIV[9:0]: PLL Feedback Divider bit, 16 ? SPLLFBDIV ? 1023, values of 0 to 15 are unused. bit 11 SPLLRST: System PLL Reset bit 1 =Assert the Reset to the SPLL 0 = De-assert the Reset to the SPLL
- bit 10 SPLLFLOCK: System PLL Force Lock bit 1 = Force the SPLL lock signal to be asserted 0 = Do not force the SPLL lock signal to be asserted
- bit 9-4 SPLLPOSTDIV1[5:0]: First Post Divide Value bit. 1 ? SPLLPOSTDIV1 ? 63, value of 0 is unused. bit 3 SPLLPWDN: PLL Power Down Register bit 1 = PLLis powered down 0 = PLLis active
- bit 2-0 SPLLBSWSEL[2:0]: PLL Bandwidth Select bit Use the frequency range that matches the PLL closed loop bandwidth as based on the reference frequency divided by REFDIV to be set to allow the PLL loop filter to work with the post-reference divider frequency.
Note: The system unlock sequence must be done before this register can be written.
renner eee e rereerence eee eee DS70005425A-page 174 Preliminary Data Sheet © 2020 Microchip Technology Inc.
——
PIC32MZ W1 and WFI32E01 Family
## REGISTER 11-4: UPLLCON: UPLL CONTROL REGISTER
Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 24/16/8/0 1 Legend: L = Value set from Configuration bits on POR R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
- bit 31 UPLL_BYP: UPLL Bypass; when this bit is set, the input clock REF bypasses PLL to PLLOUTx. Note: Recommendation is to setup SPLL first before setting up other PLLs especially when using SYSPLL for generating main system clock. Reset value must be 1, because PLL needs setup in SW for generating desired frequency.
bit 30-28 Unimplemented: Read as ‘0’
bit 29-28 Unimplemented: Read as ‘0’
- bit 27-22 UPLLREFDIV[5:0]: Reference Frequency Divide, 1 ? UPLLDIVR ? 63, value of 0 is unused. bit 21-12 UPLLFBDIV[9:0]: PLL Feedback Divider, 16 ? UPLLFBDIV ? 1023, values of0 to 15 are unused. bit 11 UPLLRST: USB PLL Reset 1 = Assert the reset to the UPLL 0 = De-assert the reset to the UPLL
- bit 10 UPLLFLOCK: USB PLL Force Lock 1 = Force the UPLL lock signal to be asserted 0 = Do not force the UPLL lock signal to be asserted
- bit 9-4 UPLLPOSTDIV1[5:0]: First Post Divide Value, 1 ? UPLLPOSTDIV1 ? 63, value of 0 is unused. bit 3 UPLLPWDN: PLL Power Down Register bit 1 = PLL is powered down 0 = PLL is active
- bit 11 UPLLRST: USB PLL Reset 1 = Assert the reset to the UPLL 0 = De-assert the reset to the UPLL
- bit 10 UPLLFLOCK: USB PLL Force Lock 1 = Force the UPLL lock signal to be asserted 0 = Do not force the UPLL lock signal to be asserted
bit2-0 |UPLLBSWSEL[2:0]: PLL Bandwidth Select Use the frequency range that matches the PLL closed loop bandwidth as based on the reference frequency divided by REFDIV to be set to allow the PLL loop filter to work with the post-reference divider frequency.
- Note: The system unlock sequence must be done before this register can be written.
SS © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 175
## PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 11-5: BTPLLCON: BTPLL CONTROL REGISTER
|Range | 31/23/15/7 |30/22/14/6 |29/21/13/5 | 28/20/12/4<br>27/19/11/3<br>26/18/10/2<br>|25/17/9/1 | 24/16/8/0|
|---|
|jereupve[ereucix| — [erououren| _—BTPLUREFOMA<br>||
|Legend:<br>L = Value set from Configuration bits on POR|
|R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR<br>‘1’=Bitisset<br>‘0’=Bitiscleared<br>x=Bitisunknown|
- bit 31 BTPLL_BYP: BTPLL Bypass; when this bit is set, the input clock REF bypasses PLL to PLLOUTx. Note: Recommendation is to setup SPLL first before setting up other PLLs especially when using SYSPLL for generating main system clock. Reset value must be 1, because PLL needs setup in SW for generating desired frequency.
- bit 30 BTPLLICLK: Source Input Clock Selection bit:
- 0 = POSC is the BTPLL input clock source
- 1 = FRC is the BTPLL input clock source
- Note: The Reset value must be 1, because the POSC is not available upon Reset.
- bit 29 Unimplemented: Read as ‘0’
- bit 28 BTCLKOUTEN: BT Clock Out pin Enable bit 1 = BT_CLK_OUT Pin is enabled 0 = BT_CLK_OUT Pin is disabled
- bit27-22 BTPLLREFDIV[5:0]: Reference Frequency Divide, 1 ? BTPLLDIVR? 63, value of 0 is unused. bit 21-12 BTPLLFBDIV[9:0]: PLL Feedback Divider, 16 ? BTPLLFBDIV ? 1023, values of 0 to 15 are unused. bit 11 BTPLLRST: BT PLL Reset 1 =Assert the reset to the BTPLL 0 = De-assert the reset to the BTPLL
- bit 10 BTPLLFLOCK: BT PLL Force Lock 1 = Force the BTPLL lock signal to be asserted 0 = Do not force the BTPLL lock signal to be asserted
- bit9-4 BTPLLPOSTDIV1[5:0]: First Post Divide Value, 1 ? BTPLLPOSTDIV1 ? 63, value of 0 is unused. bit 3 BTPLLPWDN: PLL Power Down Register bit 1 = PLLis powered down 0 = PLL is active
- bit2-0 BTPLLBSWSEL[2:0]: PLL Bandwidth Select Use the frequency range that matches the PLL closed loop bandwidth as based on the reference frequency divided by REFDIV to be set to allow the PLL loop filter to work with the post-reference divider frequency.
- Note: The system unlock sequence must be done before this register can be written.
renner eee e rereerence eee eee DS70005425A-page 176 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
**==> picture [286 x 8] intentionally omitted <==**
**----- Start of picture text -----**<br>
REGISTER 11-6: EWPLLCON: EWPLL CONTROL REGISTER<br>**----- End of picture text -----**<br>
**==> picture [462 x 174] intentionally omitted <==**
**----- Start of picture text -----**<br>
Bit Bit Bit Bit Bit Bit Bit Bit Bit<br>Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5| 28/20/12/4 27/19/11/3 26/18/10/2 | 25/17/9/1 | 24/16/8/0<br>°% [eweuevefeweucixk]<br>— [eTHoLKouTen| __—EWPLUREFOWBa) «|<br>:<br>:<br>:<br>Legend: L = Value set from Configuration bits on POR<br>R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’<br>-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown<br>**----- End of picture text -----**<br>
- bit 31 EWPLL_BYP: EWPLL Bypass; when this bit is set, the input clock REF bypasses PLL to PLLOUTx. Note: Recommendation is to setup SPLL first before setting up other PLLs especially when using SYSPLL for generating main system clock. Reset value must be 1, because PLL needs setup in SW for generating desired frequency.
- bit 30 EWPLLICLK: Source Input Clock Selection bit:
- 0 = POSC is the EWPLL input clock source
- 1 = FRC is the EWPLL input clock source
- Note: The Reset value must be 1, because the POSC is not available upon Reset. For Wi-Fi operation this bit must be set to 0. For Ethernet when providing reference clock to external PHY this bit must be set to 0.
- bit 29 Unimplemented: Read as ‘0’
- bit 28 ETHCLKOUTEN: Ethernet Clock Out pin Enable bit 1 = ETH_CLK_OUT pin is enabled
- 0 = ETH_CLK_OUT pin is disabled
- bit 27-22 EWPLLREFDIV[5:0]: Reference Frequency Divide, 1 ? EWPLLDIVR ? 63, value of 0 is unused. bit 21-12 EWPLLFBDIV[9:0]: PLL Feedback Divider, 16 ? EWPLLFBDIV ? 1023, values of 0 to 15 are unused.
- bit 11 EWPLLRST: EW PLL Reset
- 1 = Assert the reset to the EWPLL
- 0 = De-assert the reset to the EWPLL
- bit 10 EWPLLFLOCK: EW PLL Force Lock
- 1 = Force the EWPLL lock signal to be asserted
- 0 = Do not force the EWPLL lock signal to be asserted
- bit 9-4 EWPLLPOSTDIV1[5:0]: First Post Divide Value, 1 ? EWPLLPOSTDIV1 ? 63, value of 0 is unused.
- bit 3 EWPLLPWDN: PLL Power Down Register bit
- 1 = PLLis powered down
- 0 = PLLis active
- bit 2-0 EWPLLBSWSEL[2:0]: PLL Bandwidth Select
- Use the frequency range that matches the PLL closed loop bandwidth as based on the reference frequency divided by REFDIV to be set to allow the PLL loop filter to work with the post-reference divider frequency.
- Note: The system unlock sequence must be done before this register can be written.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 177
PIC32MZ W1 and WFI32E01 Family
## seman
|REGISTER 11-7:|REGISTER 11-7:|REFOxCON: REFERENCE|OSCILLATOR 1 CONTROL REGISTER||
|---|---|---|---|---|
|||(x = 1-4)|||
|Range|| 31/23/15/7||30/22/14/6 | 29/21/13/5 | 28/20/12/4 |27/19/11/3 | 26/18/10/2 | 25/17/9/1||24/16/8/0|
||a1c)|1c)|||
||PONTOS<br>|||ERP | = ___i|_C*DIVSWEN | ACTIVE _|||
||a|a|a<br>6-0)||
|Legend:||HC = Hardware|Cleared<br>HS = Hardware Set||
|R = Readable bit||W = Writable bit|U = Unimplemented bit, read as ‘0’||
|-n=ValueatPOR||‘1’=Bitisset|‘0’=Bitiscleared<br>x=Bitisunknown||
- bit 31 Unimplemented: Read as ‘0’ Reserved for expansion of RODIV[15]
- bit 30-16 RODIV[14:0] Reference Clock Divider bits
- Specifies 1/2 period of reference clock in the source clocks.
- 111111111111111 = REFO clock is base clock frequency divided by 65,534 (32,767 *2) 111111111111110 = REFO clock is base clock frequency divided by 65,532 (32,766 * 2)
000000000000011 = REFO clock is base clock frequency divided by 6 (3*2)
000000000000010 = REFO clock is base clock frequency divided by 4 (2*2) 000000000000001 = REFO clock is base clock frequency divided by 2 (1*2) 000000000000000 = REFO clock is same frequency as base clock (no divider)
- bit 15 ON: Output Enable bit
- 1 = Reference oscillator module enabled 0 = Reference oscillator module disabled
- bit 14 Unimplemented: Read as ‘0’ bit 13 SIDL: Peripheral Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode
- 0 = Continue module operation in Idle mode
- bit 12 OE: Reference Clock Output Enable bit 1 = Reference clock is driven out on REFO pin 0 = Reference clock is not driven out on REFO pin
- bit 11 RSLP: Reference Oscillator Run in Sleep bit 1 = Reference oscillator output continues to run in Sleep mode 0 = Reference oscillator output is disabled in Sleep mode Note: This bit is ignored when ROSEL[3:0] = (0000 or 0001).
- bit 10 Unimplemented: Read as ‘0’ bit 9 DIVSWEN: Clock RODIV/ROTRIM switch enabled 1 = Clock divider switching currently in progress 0 = Clock divider switching is completed
- bit 8 ACTIVE: Reference Clock Request Status bit
- 1 = Reference clock request is active (user should not update this REFOCON register) 0 = Reference clock request is not active (user can update this REFOCON register)
- bit 7-4 Unimplemented: Read as ‘0’ Note 1: ©REFOCON.ROSEL should not be written while the REFOCON.ACTIVE bit is “1” - undefined behavior will result. 2: REFOCON should not be written when REFOCON[ON] != REFOCON[ACTIVE] - undefined behavior will result..
renner eee e rereerence eee eee DS70005425A-page 178 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
## REGISTER 11-7: REFOXCON: REFERENCE OSCILLATOR 1 CONTROL REGISTER (x = 1-4) (CONTINUED)
- bit 3-0 ROSEL[3:0]: Reference Clock Source Select bits Select one of various clock sources to be used as the reference clock. 1012 - 1111 = Reserved 1011 = REFI Pin 1010 = BTPLL clock(2) 1001 = EWPLL Wi-Fi clock 1000 = EWPLL Ethernet clock 0111 = System PLL 0110 = USB PLL 0101 = SOSC 0100 = LPRC 0011 = FRC 0010 = POSC
- 0001 = Peripheral clock (reference clock reflects any peripheral clock switching) 0000 = System clock (reference clock reflects any device clock switching)
- Note 1: REFOCON.ROSEL should not be written while the REFOCON.ACTIVE bit is “1” - undefined behavior will result. 2: ©REFOCON should not be written when REFOCON[ON] != REFOCON[ACTIVE] - undefined behavior will result.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 179
PIC32MZ W1 and WFI32E01 Family
## seman
|REGISTER 11-8:|REGISTER 11-8:|REFOXTRIM:|REFERENCE OSCILLATOR 1 TRIM REGISTER (x = 1-4)|REFERENCE OSCILLATOR 1 TRIM REGISTER (x = 1-4)|REFERENCE OSCILLATOR 1 TRIM REGISTER (x = 1-4)|REFERENCE OSCILLATOR 1 TRIM REGISTER (x = 1-4)||
|---|---|---|---|---|---|---|---|
|Bit|Bit|Bit|Bit|Bit|Bit<br>Bit|Bit|Bit|
|Range|31/23/15/7 | 30/22/14/6|||29/21/13/5 | 28/20/12/4 | 27/19/11/3 |26/18/10/2 | 25/17/9/1||||| 24/16/8/0|
|:||||||||
|sso|**a**<br> |e_| se <br>ee||[ef|vo fo foo||foo fe||
||a|ee||||||
|Legend:||||||||
|R = Readable bit|||W = Writable bit||U = Unimplemented bit, read as ‘0’|||
|-n=ValueatPOR|||‘1’=Bitisset||‘0’=Bitiscleared|x=Bitisunknown||
bit 31-23 ROTRIM[8:0] Trim bits - Provides fractional additive to RODIV value for 1/2 period of REFO1 clock 0000 0000 0 =0/512 (0.0) divisor added to RODIV value 0000 0000 1 = 1/512 (0.001953125) divisor added to RODIV value 0000 0001 _0 = 2/512 (0.00390625) divisor added to RODIV value
100000000 = 256/512 (0.5000) divisor added to RODIV value
1111_1111_0 = 510/512 (0.99609375) divisor added to RODIV value 1111 1111 1 =511/512 (0.998046875) divisor added to RODIV value
Note: ROTRIM values greater than zero are only valid when RODIV values are greater than 0. bit 22-0 Unimplemented: Read as ‘0’
Note: REFOxTRIM should not be written when REFOXCON[ON] ! = REFOxCON[ACTIVE] - Undefined behavior will result.
renner eee e rereerence eee eee DS70005425A-page 180 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
|REGISTER 11-9:|PBxDIV: PERIPHERAL BUS|‘x’CLOCK DIVISOR CONTROL REGISTER (x = 1-6)|
|---|---|---|
|Bit<br>Bit|Bit<br>Bit|Bit<br>Bit<br>Bit<br>Bit<br>Bit|
|Range | 31/23/15/7|| 30/22/14/6 | 29/21/13/5 |28/20/12/4 | 27/19/11/3 |26/18/10/2 | 25/17/9/1<br>24/16/8/0||
|eeee<br>ee||ee|
|a|i||
|* [revo|[= [= [= | Peowroy[=<br>[| = | = |||
|a<br>es0)|||
|Legend:|||
|R = Readable bit|W = Writable bit|U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR|‘1’=Bitisset|‘0’=Bitiscleared<br>x=Bitisunknown|
- bit 31-16 Unimplemented: Read as ‘0’ bit 15 PBxDIVON: Peripheral Bus ‘x’ Output Clock Enable bit 1 = Output clock is enabled 0 = Output clock is disabled
- Note 1: PB1DIV[PB1DIVON] bit cannot be written to a ‘0’, as this clock is used by CRU.
- 2: PB6DIV[PB6DIVON] bit cannot be written to a ‘0’, as this clock is used by CPU. 3: PB3DIV[PB3DIVON] bit cannot be written to a ‘0’, as this clock is used by Wi-Fi subsystem. 4: PB4DIV[PB4DIVON] bit cannot be written to a ‘0’, as this clock is used by Deep Sleep Controller.
- bit 14-12 Unimplemented: Read as ‘0’ bit 11 PBDIVRDY: Peripheral Bus ‘x’ Clock Divisor Ready bit 1 = Clock divisor logic is not switching divisors and the PBxDIV[6:0] bits may be written 0 = Clock divisor logic is currently switching values and the PBxDIV[6:0] bits cannot be written
- bit 10-7 Unimplemented: Read as ‘0’ bit 6-0 PBDIV[6:0]: Peripheral Bus ‘x’ Clock Divisor Control bits 1111111 = PBCLKx is SYSCLK divided by 128 1111110 = PBCLKx is SYSCLK divided by 127
0000011 = PBCLKx is SYSCLK divided by 4 0000010 = PBCLKx is SYSCLK divided by 3 0000001 = PBCLKx is SYSCLK divided by 2 0000000 = PBCLKx is SYSCLK divided by 1
Note: The system unlock sequence must be done before this register can be written.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 181
## PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 11-10: SLEWCON: SLEW RATE CONTROL FOR CLOCK SWITCHING
REGISTER
**==> picture [451 x 184] intentionally omitted <==**
**----- Start of picture text -----**<br>
Bit Bit Bit Bit Bit Bit Bit Bit Bit<br>Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0<br>i OO<br>a<br>* =<br>oe<br>° ren<br>en sy<br>Legend: cfg- Configurable at Reset<br>R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’<br>-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown<br>**----- End of picture text -----**<br>
- bit 31-28 Unimplemented: Read as ‘0’
- bit 27-24 SLWDLY[3:0]: Number of clocks generated at each slew step for a clock switch 0000 = 1 clock is generated at each slew step 0001 = 2 clocks is generated at each slew step
1111 = 16 clocks is generated at each slew step
- bit 19-16 SYSDIV[3:0]: PBx Peripheral Clock Divisor Control bit
- 1111 = SYSCLK is divided by 16
- 1110 = SYSCLK is divided by 15
- 0010 = SYSCLK is divided by 3
- 0001 = SYSCLK is divided by 2 0000 = SYSCLK is not divided
- bit 15-11 Unimplemented: Read as ‘0’.
- bit 10-8 SLWDIV[2:0]: Slew Divisor Steps Control bits These bits control the maximum division steps used when slewing during a frequency change.
- 111 = Steps are divided by 128, 64, 32, 16, 8, 4, 2, and then no divisor 110 = Steps are divided by 64, 32, 16, 8, 4, 2, and then no divisor
- 101 = Steps are divided by 32, 16, 8, 4, 2, and then no divisor
- 100 = Steps are divided by 16, 8, 4, 2, and then no divisor
- 011 = Steps are divided by 8, 4, 2, and then no divisor
- 010 = Steps are divided by 4, 2, and then no divisor
- 001 = Steps are divided by 2, and then no divisor
- 000 = No divisor is used during slewing
Note: [Each divisor step lasts 4 clocks.
bit 7-3 Unimplemented: Read as ‘0’
- Note 1: The system unlock sequence must be done before this register can be written.
- 2: Updates to this register do not take affect until OSCCON[OSWEN] is set.
renner eee e rereerence eee eee DS70005425A-page 182 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
## REGISTER 11-10: SLEWCON: SLEW RATE CONTROL FOR CLOCK SWITCHING REGISTER (CONTINUED)
- bit 2 UPEN: Upward Slew Enable bit Enable clock slew for switching up to faster clocks
- 1 = Slewing enabled for switching to a higher frequency
- 0 = Slewing disabled for switching to a higher frequency
- bit 1 DNEN: Downward Slew Enable bit Enable clock slew for switching down to slower clocks
- 1 = Slewing enabled for switching to a lower frequency
- 0 = Slewing disabled for switching to a lower frequency
- bit 0 BUSY: Clock Switch Slewing Active Status bit (Read-only) 0 = Clock switch has reached its final value
- 1 = Clock frequency is actively slewed
- Note 1: The system unlock sequence must be done before this register can be written. 2: Updates to this register do not take affect until OSCCON[OSWEN] is set.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 183
PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 11-11: CLKSTAT: CLOCK STATUS REGISTER
|Range | 31/23/15/7 |30/22/14/6|29/21/13/5 |28/20/12/4 | 27/19/11/3 | 26/18/10/2|Range | 31/23/15/7 |30/22/14/6|29/21/13/5 |28/20/12/4 | 27/19/11/3 | 26/18/10/2|Range | 31/23/15/7 |30/22/14/6|29/21/13/5 |28/20/12/4 | 27/19/11/3 | 26/18/10/2|Range | 31/23/15/7 |30/22/14/6|29/21/13/5 |28/20/12/4 | 27/19/11/3 | 26/18/10/2|Range | 31/23/15/7 |30/22/14/6|29/21/13/5 |28/20/12/4 | 27/19/11/3 | 26/18/10/2|25/17/9/1|24/16/8/0|
|---|---|---|---|---|---|---|
|a|ee|es|||||
|a<br>|98|a|a<br>ee<br>ee<br>eee<br>avscarmar |reve oY[SPLAT|||ee<br>[SPLAT|ee<br>|EO|
|Legend:||HC = Hardware|Set|HC = Hardware Cleared|||
|R = Readable bit||W = Writable bit||U = Unimplemented bit, read as ‘0’|||
|-n=ValueatPOR||‘1’=Bitisset||‘0’=Bitiscleared|x=Bitisunknown||
bit 31-12 Unimplemented: Read as ‘0’
- bit 11 SYSCLKRDY: System Clock Ready Status bit 0 = SYSCLK is not stable and not ready 1 =SYSCLK is stable and ready
- bit 10 PB1CLKRDY: PB1 Clock Ready Status bit 0 = PB1CLK is not stable and not ready 1 = PB1CLK is stable and ready
- bit 9 SPLLALTRDY: System PLL Ready Status bit 0 = SPLL alternate output is not stable and not ready 1 = SPLL alternate output is stable and ready
- bit 8 WIFICLKRDY: Wi-Fi Clock Ready Status bit 0 = WIFICLK is not stable and not ready 1 = WIFICLK is stable and ready
- bit 7 ETHPLLRDY: ETHPLL Ready Status bit 0 = ETHPLL is not stable and not ready 1 = ETHPLL is stable and ready
- bit 6 BTPLLRDY: Bluetooth PLL Ready Status bit 0 = BTPLL is not stable and not ready 1 = BTPLL is stable and ready
- bit 5 LPRCRDY: LPRC Ready Status bit 0 = LPRC is not stable and not ready 1 = LPRC is stable and ready
- bit 4 SOSCRDY: SOSC Ready Status bit 0 = SOSC is not stable and not ready 1 = SOSC is stable and ready
- bit 3 UPLLRDY: USB PLL Ready Status bit 0 = UPLL is not stable and not ready 1 = UPLL is stable and ready
renner eee e rereerence eee eee DS70005425A-page 184 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
## REGISTER 11-11: CLKSTAT: CLOCK STATUS REGISTER (CONTINUED)
- bit 2 POSCRDY: Primary Oscillator Ready Status bit
- 0 = POSC is not stable and not ready
- 1 = POSC is stable and ready
- bit 1 SPLLRDY: System PLL Ready Status bit 0 = SPLL Primary output is not stable and not ready
- 1 = SPLL Primary output is stable and ready
- bit 0 FRCRDY: FRC Ready Status bit 0 = FRC is not stable and not ready
- 1 = FRC is stable and ready
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 185
PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 11-12: CLKDIAG: USER CLOCK DIAGNOSTICS CONTROL REGISTER
|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit|
|---|
|Range|31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 |26/18/10/2 | 25/17/9/1<br>24/16/8/0|
|TSCM<br>SCdTtiSC*édE:‘C‘(itéDCOC*SCUCéO):~C*ésG«C‘“‘(itséUOOC*dT«Ci“‘(wscos~C*ézE:C‘(‘<iéitSC*d(C‘(<‘i‘i‘iCd<br>ee a a<br>peeP**S**<br>oe S ET ET|
|° [= [etieutsror [uruisror | seusror |cerostor | Frostop |Soscsror |POScsToP ||
|Legend:|
|R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR<br>‘1’=Bitisset<br>‘0’=Bitiscleared<br>x=Bitisunknown|
- bit 31-15 Unimplemented: Read as ‘0’ bit 6 ETHPLLSTOP: ETHPLL Clock Stop Control bit 0 = ETHPLL clock source runs as normal 1 = ETHPLL clock source is stopped
- bit 5 UPLLSTOP: UPLL Clock Stop Control bit 0 = UPLL clock source runs as normal 1 = UPLL clock source is stopped
- bit 4 SPLLSTOP: SPLL Clock Stop Control bit 0 = SPLL clock source runs as normal 1 = SPLL clock source is stopped
- bit 3 LPRCSTOP: LPRC Clock Stop Control bit 0 =LPRC clock source runs as normal 1 = LPRC clock source is stopped
- bit 2 FRCSTOP: FRC Clock Stop Control bit 0 = FRC clock source runs as normal 1 = FRC clock source is stopped
- bit 1 SOSCSTOP: SOSC Clock Stop Control bit 0 = SOSC clock source runs as normal 1 = SOSC clock source is stopped
- bit 0 POSCSTOP: POSC Clock Stop Control bit 0 = POSC clock source runs as normal 1 = POSC clock source is stopped
- Note: The system unlock sequence must be done before this register can be written.
renner eee e rereerence eee eee DS70005425A-page 186 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and weri32E01 Family
## smn 12.0 FULL-SPEED USB ON-THE-GO The PIC32 USB module has the following features: (OTG) + USB full-speed support for host and and device Note 1: This data sheet summarizes the features * Low-speed host support support
- + USB full-speed support for host and and device * Low-speed host support support ‘ USOT sinoUPPO! * Integrated signaling resistors ¢ Integrated analog comparators for VBUS monitoring
- ¢ Integrated USB transceiver * Transaction handshaking performed by hardware ¢ Endpoint buffering anywhere in system RAM Integrated DMA to access system RAM and Flash Note: The implementation and use of the USB specifications, as well as other third-party specifications or technologies, may require licensing; including, but not limited to, USB Implementers Forum, Inc. (USBIF). The user is fully responsible for investigating and satisfying any applicable licensing obligations.
- 1: This data sheet summarizes the features of the PIC32MZ W1 of family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 27. “USB On-The-Go (OTG)” (DS61126) of the “PIC32 Family ReferMiersicrochipManual oowe Sitesite twwww.micro- from the chip.com/PIC32).
- 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 6.0 “Memory Organization” in this data sheet for device-specific register and bit information.
- The Universal Serial Bus (USB) module contains analog and digital components to provide a USB 2.0 full-speed and low-speed embedded host, full-speed device, and OTG implementation with minimum external components. This module in Host mode is intended for use as an embedded host and therefore does not implement a UHCI or OHCI controller.
The USB module consists of the following:
- Clock generator
- ¢ USB voltage comparators
- Transceiver
- Serial Interface Engine (SIE)
- « USB DMA controller ¢ Pull-up and pull-down resistors
- ¢ Register interface The interface diagram of the PIC32 USB OTG module is illustrated in Figure 12-1.
The clock generator provides the 48 MHz clock required for USB full-speed and _ low-speed communication. The voltage comparators monitor the voltage on the Vgys pin to determine the state of the bus. The transceiver provides the analog translation between the USB bus and the digital logic. The SIE is a state machine that transfers data to and from the endpoint buffers, and generates the hardware protocol for data transfers. The USB DMA controller transfers data between the data buffers in RAM and the SIE. The integrated pull-up and pull-down resistors eliminate the need for external signaling components. The register interface allows the CPU to configure and communicate with the module.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 187
## PIC32MZ W1 and weri32E01 Family
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## PIC32MZ W1 and weri32E01 Family
## seman
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|||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|REGISTER|12-1:|U1OTGIR:|USB|OTG|INTERRUPT|STATUS|REGISTER|
|Bit|Bit|Bit|Bit|Bit|Bit|Bit|Bit|Bit|
|Range|||31/23/15/7|||30/22/14/6|||29/21/13/5|||28/20/12/4|||27/19/11/3|| 26/18/10/2|||25/17/9/1|||24/16/8/0|
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Legend:
R = Readable bit W = Writable bit P = Programmable bit r = Reserved bit U = Unimplemented bit K = Write ‘1’ to clear -n = Bit Value at POR: (0, 1, x = unknown)
- bit 31-8 Unimplemented: Read as ‘0’
- bit 7 IDIF: ID State Change Indicator bit Write a ‘1’ to this bit to clear the interrupt. 1 = Change in ID state detected 0 = Nochange in ID state detected
- bit 6 T1MSECIF: 1 Millisecond Timer bit Write a ‘1’ to this bit to clear the interrupt. 1 =1 millisecond timer has expired 0 = 1 millisecond timer has not expired
- bit 5 LSTATEIF: Line State Stable Indicator bit Write a ‘1’ to this bit to clear the interrupt. 1 = USB line state is stable for 1 ms, but different from last time 0 = USB line state is not stable for 1 ms
- bit 4 ACTVIF: Bus Activity Indicator bit Write a ‘1’ to this bit to clear the interrupt. 1 =Activity on the D+, D-, ID or Vays pins has caused the device to wake up 0 = Activity has not been detected
- bit 3 SESVDIF: Session Valid Change Indicator bit Write a ‘1’ to this bit to clear the interrupt. 1 = Vgus voltage has dropped below the session end level
- 0 = Vgus voltage has not dropped below the session end level
- bit 2 SESENDIF: B-Device Vays Change Indicator bit Write a ‘1’ to this bit to clear the interrupt. 1 =Achange on the session end input was detected
- 0 = No change on the session end input was detected
- bit 1 Unimplemented: Read as ‘0’
- bit 0 VBUSVDIF: A-Device Vgys Change Indicator bit Write a ‘1’ to this bit to clear the interrupt. 1 = Change on the session valid input detected
- 0 = No change on the session valid input detected
renner eee e rereerence eee eee DS70005425A-page 192 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and weri32E01 Family
## smn
## REGISTER 12-2: U1OTGIE: USB OTG INTERRUPT ENABLE REGISTER
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Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0<br>a a | || | |g |<br>| oo eeGe ee e e ee nomeee B ee Seanee eeeaE ee<br>Legend:<br>R = Readable bit W = Writable bit P = Programmable bit r = Reserved bit<br>U = Unimplemented bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)<br>**----- End of picture text -----**<br>
bit 31-8 Unimplemented: Read as ‘0’
- bit 7 IDIE: ID Interrupt Enable bit 1 = ID interrupt enabled
- 0 = ID interrupt disabled
- bit 6 T1MSECIE: 1 Millisecond Timer Interrupt Enable bit 1 =1 millisecond timer interrupt enabled
- 0 = 1 millisecond timer interrupt disabled
- bit 5 LSTATEIE: Line State Interrupt Enable bit 1 = Line state interrupt enabled
- 0 = Line state interrupt disabled
- bit 4 ACTVIE: Bus Activity Interrupt Enable bit 1 = Bus activity interrupt enabled 0 = Bus activity interrupt disabled
- bit 3 SESVDIE: Session Valid Interrupt Enable bit 1 = Session valid interrupt enabled 0 = Session valid interrupt disabled
- bit 2 SESENDIE: B-Session End Interrupt Enable bit 1 = B-session end interrupt enabled 0 = B-session end interrupt disabled
- bit 1 Unimplemented: Read as ‘0’
- bit 0 VBUSVDIE: A-Vgys Valid Interrupt Enable bit 1 =A-Vepuys valid interrupt enabled 0 =A-Vepus valid interrupt disabled
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 193
## PIC32MZ W1 and weri32E01 Family
## seman
## REGISTER 12-3: U1OTGSTAT: USB OTG STATUS REGISTER
**==> picture [457 x 290] intentionally omitted <==**
**----- Start of picture text -----**<br>
Bit Bit Bit Bit Bit Bit Bit Bit Bit<br>Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0<br>us [= = == = =<br>pate | 2 ee<br>ee ee a<br>ro Po [[RO] | | [RO] stare [=|P| uoU0 TROsesvo_[sesendPRO [|| uo ROvausvo<br>Legend:<br>R = Readable bit W = Writable bit P = Programmable bit r = Reserved bit<br>U = Unimplemented bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)<br>bit 31-8 Unimplemented: Read as ‘0’<br>bit 7 ID: ID Pin State Indicator bit<br>1 = No cable is attached or a type B cable has been plugged into the USB receptacle<br>0 =A “type A” OTG cable has been plugged into the USB receptacle<br>bit 6 Unimplemented: Read as ‘0’<br>bit 5 LSTATE: Line State Stable Indicator bit<br>1 = USB line state (U1CON[SEO] and U1CON[JSTATE]) has been stable for the last 1 ms<br>0 = USB line state (U1 CON[SE0] and U1CON[JSTATE]) has not been stable for the last 1 ms<br>bit 4 Unimplemented: Read as ‘0’<br>**----- End of picture text -----**<br>
- bit 3 SESVD: Session Valid Indicator bit
- 1 = Veus voltage is above Session Valid on the A or B device
- 0 = Vgus voltage is below Session Valid on the A or B device
- bit 2 SESEND: B-Session End Indicator bit
- 1 = Vgus voltage is below Session Valid on the B device
- 0 = Vgus voltage is above Session Valid on the B device
- bit 1 Unimplemented: Read as ‘0’
- bit 0 VBUSVD: A-Vpys Valid Indicator bit 1 = Vgus voltage is above Session Valid on the A device
- 0 = Vgus voltage is below Session Valid on the A device
renner eee e rereerence eee eee DS70005425A-page 194 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and weri32E01 Family
smn
## REGISTER 12-4: U1OTGCON: USB OTG STATUS REGISTER
|Bit||Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit|Bit|Bit|
|---|---|---|---|---|
|Range|||31/23/15/7 |30/22/14/6 | 29/21/13/5 |28/20/12/4 | 27/19/11/3 |26/18/10/2 | 25/17/9/1 | 24/16/8/0|||
|ee <br>paste <br>pee|<br> | <br> ||ee ee<br>ee ee<br> WS<br>ee ee<br> SeSee ee|||
|-<br>||||||
Legend:
R = Readable bit W = Writable bit P = Programmable bit r = Reserved bit U = Unimplemented bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
bit 31-8 Unimplemented: Read as ‘0’
- bit 7 DPPULUP: D+ Pull-Up Enable bit 1 = D+ data line pull-up resistor is enabled 0 = D+ data line pull-up resistor is disabled
- bit 6 DMPULUP: D- Pull-Up Enable bit 1 = D- data line pull-up resistor is enabled 0 = D- data line pull-up resistor is disabled
- bit 5 DPPULDWN: D+ Pull-Down Enable bit 1 = D+ data line pull-down resistor is enabled 0 = D+ data line pull-down resistor is disabled
- bit 4 DMPULDWN: D- Pull-Down Enable bit 1 = D- data line pull-down resistor is enabled 0 = D- data line pull-down resistor is disabled
- bit 3 VBUSON: Vgus Power-on bit 1 = Vgus line is powered 0 = Vgus line is not powered
- bit 2 OTGEN: OTG Functionality Enable bit 1 = DPPULUP, DMPULUP, DPPULDWN and DMPULDWN bits are under software control 0 = DPPULUP, DMPULUP, DPPULDWN and DMPULDWN bits are under USB hardware control
- bit 1 VBUSCHG: Vays Charge Enable bit 1 = Vgus line is charged through a pull-up resistor 0 = Veus line is not charged through a resistor
- bit O VBUSDIS: Vpys Discharge Enable bit 1 = Vgus line is discharged through a pull-down resistor
- 0 = Vgus line is not discharged through a resistor
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 195
## PIC32MZ W1 and weri32E01 Family
## seman
## REGISTER 12-5: U1PWRC: USB POWER CONTROL REGISTER
- Bit Bit Bit Bit Bit Bit Bit Bit Bit
- Range 31/23/15/7 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0
- 2p pate | SS ee ee pes |S qe ee eo -° [uacteno [= ister | Usesusy™ | = [uss Pend | UsBPwe |
- Legend: HS = Cleared by hardware HW = Set by hardware R = Readable bit W = Writable bit P = Programmable bit r = Reserved bit U = Unimplemented bit K = Write ‘1’ to clear -n = Bit Value at POR: (0, 1, x = unknown) bit 31-8 Unimplemented: Read as ‘0’ bit 7 UACTPND: USB Activity Pending bit 1 = USB bus activity has been detected; but an interrupt is pending, it has not been generated yet 0 = An interrupt is not pending
- bit 6-5 |Unimplemented: Read as ‘0’ bit 4 USLPGRD: USB Sleep Entry Guard bit 1 = Sleep entry is blocked if USB bus activity is detected or if a notification is pending 0 = USB OTG module does not block Sleep entry
- bit 3 USBBUSY: USB OTG module Busy bit!) 1 = USB OTG module is active or disabled, but not ready to be enabled 0 = USB OTG module is not active and is ready to be enabled Note: When USBPWR = 0 and USBBUSY= 1, status from all other registers is invalid and writes to all USB OTG module registers produce undefined results.
- bit 2 Unimplemented: Read as ‘0’ bit 1 USUSPEND: USB Suspend Mode bit 1 = USB OTG module is placed in Suspend mode (The 48 MHz USB clock is gated off. The transceiver is placed in a low-power state.) 0 = USB OTG module operates normally
- bit 0 USBPWR: USB Operation Enable bit 1 = USB OTG module is turned on 0 = USB OTG module is disabled (Outputs held inactive, device pins not used by USB, analog features are shut down to reduce power consumption.)
Note 1: This bit is not available on all devices. Refer to the specific device data sheet for details.
renner eee e rereerence eee eee DS70005425A-page 196 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and weri32E01 Family
## smn
**==> picture [247 x 9] intentionally omitted <==**
**----- Start of picture text -----**<br>
REGISTER 12-6: U1IR: USB INTERRUPT REGISTER<br>**----- End of picture text -----**<br>
**==> picture [452 x 168] intentionally omitted <==**
**----- Start of picture text -----**<br>
Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 |26/18/10/2 | 25/17/9/1 24/16/8/0<br>es Se ee ee ee Ee eee ee<br>a reee<br>a | | | | || |<br>STALLIF | ATTACHIF) | RESUMEIF)) = IDLEIF | TRNIF®) SOFIF UERRIF()<br>Legend:<br>R = Readable bit W = Writable bit P = Programmable bit r= Reserved bit<br>U = Unimplemented bit K = Write ‘1’ to clear -n = Bit Value at POR: (0, 1, x = unknown)<br>**----- End of picture text -----**<br>
- bit 31-8 Unimplemented: Read as ‘0’ bit 7 STALLIF: STALL Handshake Interrupt bit Write a ‘1’ to this bit to clear the interrupt.
- 1 = In Host mode, a STALL handshake was received during the handshake phase of the transaction. In Device mode, a STALL handshake was transmitted during the handshake phase of the transaction.
- 0 = STALL handshake has not been sent
- bit 6 ATTACHIF: Peripheral Attach Interrupt bit)
- Write a ‘1’ to this bit to clear the interrupt.
- 1 = Peripheral attachment was detected by the USB OTG module
- 0 = Peripheral attachment was not detected
- bit 5 RESUMEIF: Resume Interrupt bit'2) Write a ‘1’ to this bit to clear the interrupt.
- 1 = K-State is observed on the D+ or D- pin for 2.5 us
- 0 = K-State is not observed
- bit 4 IDLEIF: Idle Detect Interrupt bit Write a ‘1’ to this bit to clear the interrupt.
- 1 = Idle condition detected (constant Idle state of 3 ms or more) 0 = No Idle condition detected
- bit 3 TRNIF: Token Processing Complete Interrupt bit’)
- Write a ‘1’ to this bit to clear the interrupt.
- 1 = Processing of current token is complete; a read of the U1STAT register provides endpoint information
- 0 = Processing of current token not complete
- bit 2 SOFIF: SOF Token Interrupt bit Write a ‘1’ to this bit to clear the interrupt. 1 = SOF token received by the peripheral or the SOF threshold reached by the host 0 = SOF token was not received nor threshold reached
- Note 1: This bit is valid only if the HOSTEN bit is set (see Register 12-11), there is no activity on the USB for 2.5 us, and the current bus state is not SEO.
- 2: When not in Suspend mode, this interrupt should be disabled.
- 3: Clearing this bit will cause the STAT FIFO to advance.
- 4: Only error conditions enabled through the U1EIE register will set this bit.
- 5: Device mode.
- 6: Host mode.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 197
## PIC32MZ W1 and weri32E01 Family
## seman
## REGISTER 12-6: U1IR: USB INTERRUPT REGISTER (CONTINUED) bit 1 UERRIF: USB Error Condition Interrupt bit'4) Write a ‘1’ to this bit to clear the interrupt.
- 1 = Unmasked Error condition has occurred 0 = Unmasked Error condition has not occurred
- bit 0 URSTIF: USB Reset Interrupt bit (Device mode)(®) 1 = Valid USB Reset has occurred 0 = No USB Reset has occurred DETACHIF: USB Detach Interrupt bit (Host mode)!®) 1 = Peripheral detachment was detected by the USB OTG module 0 = Peripheral detachment was not detected
- Note 1: This bit is valid only if the HOSTEN bit is set (see Register 12-11), there is no activity on the USB for 2.5 us, and the current bus state is not SEO.
- 2: When not in Suspend mode, this interrupt should be disabled. 3: Clearing this bit will cause the STAT FIFO to advance. 4: Only error conditions enabled through the U1EIE register will set this bit. 5: Device mode.
- 6: Host mode.
renner eee e rereerence eee eee DS70005425A-page 198 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and weri32E01 Family
## smn
## REGISTER 12-7: U1IE: USB INTERRUPT ENABLE REGISTER")
|REGISTER 12-7:<br>U1IE: USB INTERRUPT ENABLE REGISTER")||
|---|---|
|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit|Bit<br>Bit<br>Bit|
|Range<br>31/23/15/7 =| 30/22/14/6 |29/21/13/5 |28/20/12/4|27/19/11/3||26/18/10/2 |25/17/9/1 | 24/16/8/0|
|a ee eeeeee<br>ee<br>eeEeEeyEEeE—>EeE—EeE——E—————E—EE<br>8=Flac nc nuee[ car pee [oefm TO<br>STALLIE<br>ATTACHIE |RESUMEIE<br>IDLEIE<br>TRNIE<br>SOFIE<br>UERRIE||
|Legend:||
R = Readable bit W = Writable bit P=Programmable bit r= Reserved bit U = Unimplemented bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
- bit 31-8 Unimplemented: Read as ‘0’
- bit 7 STALLIE: STALL Handshake Interrupt Enable bit 1 = STALL interrupt enabled
- 0 = STALL interrupt disabled
- bit 6 ATTACHIE: ATTACH Interrupt Enable bit 1 = ATTACH interrupt enabled
- 0 = ATTACH interrupt disabled
- bit 5 RESUMEIE: RESUME Interrupt Enable bit 1 = RESUME interrupt enabled
- 0 = RESUME interrupt disabled
- bit 4 IDLEIE: Idle Detect Interrupt Enable bit 1 = Idle interrupt enabled
- 0 = Idle interrupt disabled
- bit 3 TRNIE: Token Processing Complete Interrupt Enable bit 1 = TRNIF interrupt enabled
- 0 = TRNIF interrupt disabled
- bit 2 SOFIE: SOF Token Interrupt Enable bit 1 = SOFIF interrupt enabled 0 = SOFIF interrupt disabled
- bit 1 UERRIE: USB Error Interrupt Enable bit 1 = USB Error interrupt enabled
- 0 = USB Error interrupt disabled
- bit 0 URSTIE: USB Reset Interrupt Enable bit(?) 1 = URSTIF interrupt enabled 0 = URSTIF interrupt disabled DETACHIE: USB Detach Interrupt Enable bit!) 1 = DATTCHIF interrupt enabled 0 = DATTCHIF interrupt disabled
- Note 1: Foran interrupt to propagate to the USBIF bit (IFS1[25]), the UERRIE bit (U1IE[1]) must be set.
- 2: Device mode.
- 3: Host mode.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 199
## PIC32MZ W1 and weri32E01 Family
## seman
**==> picture [332 x 8] intentionally omitted <==**
**----- Start of picture text -----**<br>
REGISTER 12-8: U1EIR: USB ERROR INTERRUPT STATUS REGISTER<br>**----- End of picture text -----**<br>
- Bit Bit Bit Bit Bit Bit Bit Bit Bit
- Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0
- ee eee ee ee ee ee eae ee nr cna a 8) Ep ee BTSEF BMXEF DMAEF"1) BTOEF!) DFN8EF CRC16EF PIDEF
- Legend: R = Readable bit W = Writable bit P = Programmable bit r = Reserved bit U = Unimplemented bit K = Write ‘1’ to clear -n = Bit Value at POR: (‘0’, ‘1’, x = unknown) bit 31-8 | Unimplemented: Read as ‘0’ bit 7 BTSEF: Bit Stuff Error Flag bit Write a ‘1’ to this bit to clear the interrupt. 1 = Packet rejected due to bit stuff error 0 = Packet accepted
- bit 6 BMXEF: Bus Matrix Error Flag bit Write a ‘1’ to this bit to clear the interrupt. 1 = The base address of the BDT or the address of an individual buffer pointed to by a BDT entry, is invalid.
- 0 = No address error
- bit 5 DMAEF: DMA Error Flag bit") Write a ‘1’ to this bit to clear the interrupt. 1 = USB DMA error condition detected 0 = No DMA error
- bit 4 BTOEF: Bus Turnaround Time-Out Error Flag bit?) Write a ‘1’ to this bit to clear the interrupt. 1 = Bus turnaround time-out has occurred 0 = No bus turnaround time-out
- bit 3 DFNS8EF: Data Field Size Error Flag bit Write a ‘1’ to this bit to clear the interrupt. 1 = Data field received is not an integral number of bytes 0 = Data field received is an integral number of bytes
- Note 1: This type of error occurs when the module’s request for the DMA bus is not granted in time to service the module’s demand for memory, resulting in an overflow or underflow condition, and/or the allocated buffer size is not sufficient to store the received data packet causing it to be truncated.
- 2: This type of error occurs when more than 16-bit-times of Idle from the previous End-of-Packet (EOP) has elapsed.
- 3: This type of error occurs when the module is transmitting or receiving data and the SOF counter has reached zero.
- 4: Device mode.
- 5: Host mode.
renner eee e rereerence eee eee DS70005425A-page 200 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and weri32E01 Family
## smn
|REGISTER 12-8:<br>U1EIR: USB ERROR INTERRUPT STATUS REGISTER (CONTINUED)|REGISTER 12-8:<br>U1EIR: USB ERROR INTERRUPT STATUS REGISTER (CONTINUED)|REGISTER 12-8:<br>U1EIR: USB ERROR INTERRUPT STATUS REGISTER (CONTINUED)|
|---|---|---|
|bit 2||CRC16EF: CRC16 Failure Flag bit|
|||Write a ‘1’ to this bit to clear the interrupt.|
|||1 = Data packet rejected due to CRC16 error|
|||0 = Data packet accepted|
|bit 1||CRC5EF: CRC5 Host Error Flag bit'?-4)|
|||Write a ‘1’ to this bit to clear the interrupt.|
|||1 = Token packet rejected due to CRC5 error|
|||0 = Token packet accepted|
|||EOFEF: EOF Error Flag bit!)|
|||1 = EOF error condition detected|
|||0 = No EOF error condition|
|bit 0||PIDEF: PID Check Failure Flag bit|
|||1 = PID check failed|
|||0 = PID check passed|
|Note|1:|This type of error occurswhen the module’s request for the DMAbus is not granted in time to|
|||service the module’s demand for memory, resulting in an overflow or underflow condition,|
|||and/or the allocated buffer size is not sufficient to store the received data packet causing it to|
|||be truncated.|
||2:|This type of error occurswhen more than 16-bit-times of Idle from the previous End-of-Packet|
|||(EOP) has elapsed.|
||3:|This type of error occurswhen the module is transmitting or receiving data and the SOF|
|||counter has reached zero.|
||4:|Device mode.|
||5:|Hostmode.|
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 201
## PIC32MZ W1 and weri32E01 Family
## seman
## REGISTER 12-9: U1EIE: USB ERROR INTERRUPT ENABLE REGISTER")
|Bit<br>Bit|Bit|Bit|Bit<br>Bit|Bit<br>Bit|Bit|
|---|---|---|---|---|---|
|Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 |26/18/10/2 | 25/17/9/1||||||24/16/8/0|
|ee <br>eer <br>8) PS|ee ee <br> cee<br> ee||a<br>ee<br>a a a Ga<br>eee|||
|BTSEE|BMXEE|DMAEE|BTOEE<br>DFN8EE|CRC16EE|PIDEE|
|Legend:||||||
|R = Readable bit|W = Writable bit||P = Programmable bit|r = Reserved bit||
|U=Unimplementedbit|-n=BitValueat|POR:(‘0’,|‘1’,x=Unknown)|||
**==> picture [158 x 11] intentionally omitted <==**
**----- Start of picture text -----**<br>
bit 31-8 | Unimplemented: Read as ‘0’<br>**----- End of picture text -----**<br>
- bit 7 BTSEE: Bit Stuff Error Interrupt Enable bit 1 = BTSEF interrupt enabled 0 = BTSEF interrupt disabled
- bit 6 BMXEE: Bus Matrix Error Interrupt Enable bit 1 = BMXEF interrupt enabled 0 = BMXEF interrupt disabled
- bit 5 DMAEE: DMA Error Interrupt Enable bit 1 = DMAEF interrupt enabled 0 = DMAEF interrupt disabled
- bit 4 BTOEE: Bus Turnaround Time-Out Error Interrupt Enable bit 1 = BTOEF interrupt enabled 0 = BTOEF interrupt disabled
- bit 3 DFN8EE: Data Field Size Error Interrupt Enable bit 1 = DFN8EF interrupt enabled 0 = DFN8EF interrupt disabled
- bit 2 CRC16EE: CRC16 Failure Interrupt Enable bit 1 = CRC16EF interrupt enabled 0 = CRC16EF interrupt disabled
- bit 1 CRCS5EE: CRC5 Host Error Interrupt Enable bit!?) 1 = CRC5SEF interrupt enabled 0 = CRC5SEF interrupt disabled EOFEE: EOF Error Interrupt Enable bit') 1 = EOF interrupt enabled 0 = EOF interrupt disabled
- Note 1: Foran interrupt to propagate USBIF bit (IFS1[25]), the UERRIE bit (U1IE[1]) must be set.
- 2: Device mode.
- 3: Host mode.
renner eee e rereerence eee eee DS70005425A-page 202 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and weri32E01 Family
## smn REGISTER 12-9: U1EIE: USB ERROR INTERRUPT ENABLE REGISTER") (CONTINUED)
- bit O PIDEE: PID Check Failure Interrupt Enable bit 1 = PIDEF interrupt enabled
- 0 = PIDEF interrupt disabled
- Note 1: Foran interrupt to propagate USBIF bit (IFS1[25]), the UERRIE bit (U1IE[1]) must be set. 2: Device mode.
- 3: Host mode.
**==> picture [251 x 11] intentionally omitted <==**
**----- Start of picture text -----**<br>
REGISTER 12-10: U1STAT: USB STATUS REGISTER")<br>**----- End of picture text -----**<br>
**==> picture [456 x 184] intentionally omitted <==**
**----- Start of picture text -----**<br>
Bit Bit Bit Bit Bit Bit Bit Bit Bit<br>Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0<br>a a OG<br>pe OE ee eee<br>oe Se ee<br>=<br>Legend:<br>R = Readable bit W = Writable bit P = Programmable bit r = Reserved bit<br>U = Unimplemented bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)<br>**----- End of picture text -----**<br>
- bit 31-8 Unimplemented: Read as ‘0’
- bit 7-4 ENDPT[3:0]: Encoded Number of Last Endpoint Activity bits (Represents the number of the BDT, updated by the last USB transfer.) 1111 = Endpoint 15 1110 = Endpoint 14
- 0001 = Endpoint 1 0000 = Endpoint0
- bit 3 DIR: Last BD Direction Indicator bit
- 1 = Last transaction was a TX
- 0 = Last transaction was a RX
- bit 2 PPBI: Ping-pong BD Pointer Indicator bit 1 = Last transaction was to the ODD BD bank
- 0 = Last transaction was to the EVEN BD bank
- bit 1-0 Unimplemented: Read as ‘0’
- Note 1: The U1STAT register is a window into a 4 byte FIFO maintained by the USB OTG module. U1STAT value is only valid when the TRNIF bit (U1IR[8]) is active. Clearing the TRNIF bit (U1IR[3]) advances the FIFO. Data in register is invalid when the TRNIF bit (U1IR[3]) = 0.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 203
## PIC32MZ W1 and weri32E01 Family
## seman
## REGISTER 12-11: U1CON: USB CONTROL REGISTER
**==> picture [454 x 140] intentionally omitted <==**
**----- Start of picture text -----**<br>
||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Bit|Bit|Bit|Bit|Bit|Bit|Bit|Bit|Bit|
|Range|31/23/15/7|||30/22/14/6|||29/21/13/5|||28/20/12/4|||27/19/11/3|| 26/18/10/2|| 25/17/9/1|| 24/16/8/0|
|ee ee|ee|eee|ee|ee|
|pe|qe|eee|
|8|pee|
|JSTATE|SEO|USBRST|||HOSTEN?)|| RESUME®)|||PPBRST|
**----- End of picture text -----**<br>
## Legend:
R = Readable bit W = Writable bit P = Programmable bit r = Reserved bit U = Unimplemented bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
bit 31-8 Unimplemented: Read as ‘0’
- bit 7 JSTATE: Live Differential Receiver JSTATE flag bit 1 = JSTATE detected on the USB 0 = No JSTATE detected
- bit 6 SEO: Live Single-Ended Zero flag bit 1 = Single-Ended Zero detected on the USB 0 = No Single-Ended Zero detected
- bit 5 PKTDIS: Packet Transfer Disable bit) 1 = Token and packet processing disabled (set upon SETUP token received) 0 = Token and packet processing enabled TOKBUSY: Token Busy Indicator bit'"5) 1 = Token being executed by the USB OTG module 0 = No token being executed
- bit 4 USBRST: Module Reset bit‘) 1 = USB Reset generated 0 = USB Reset terminated
- bit 3 HOSTEN: Host Mode Enable bit!) 1 = USB host capability enabled 0 = USB host capability disabled
- bit 2 RESUME: RESUME Signaling Enable bit'*) 1 = RESUME signaling activated 0 = RESUME signaling disabled
- Note 1: Software is required to check this bit before issuing another token command to the U1TOK register, see Register 12-15.
- 2: All host control logic is reset any time that the value of this bit is toggled.
- 3: Software must set RESUME for 10 ms if the part is a function, or for 25 ms if the part is a host, and then clear it to enable remote wake-up. In Host mode, the USB OTG module will append a low-speed EOP to the RESUME signaling when this bit is cleared.
- 4: Device mode.
- 5: Host mode.
renner eee e rereerence eee eee DS70005425A-page 204 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and weri32E01 Family
## smn
## REGISTER 12-11: U1CON: USB CONTROL REGISTER (CONTINUED)
bit 1 PPBRST: Ping-Pong Buffers Reset bit
- 1 = Reset all Even/Odd buffer pointers to the EVEN BD banks
- 0 = Even/Odd buffer pointers not being Reset
bit 0 USBEN: USB OTG Module Enable bit‘*)
- 1 = USB OTG module and supporting circuitry enabled
- 0 = USB OTG module and supporting circuitry disabled SOFEN: SOF Enable bit'®) 1 = SOF token sent every 1 ms 0 = SOF token disabled
- Note 1: Software is required to check this bit before issuing another token command to the U1TOK register, see Register 12-15.
- 2: All host control logic is reset any time that the value of this bit is toggled.
- 3: Software must set RESUME for 10 ms if the part is a function, or for 25 ms if the part is a host, and then clear it to enable remote wake-up. In Host mode, the USB OTG module will append a low-speed EOP to the RESUME signaling when this bit is cleared.
- 4: Device mode.
- 5: Host mode.
## REGISTER 12-12: U1ADDR: USB ADDRESS REGISTER
|Bit<br>Bit|Bit<br>Bit|Bit|Bit<br>Bit|Bit|Bit|
|---|---|---|---|---|---|
|Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 |25/17/9/1 |24/16/8/0||||||
|eeee<br>ee<br>Ga <br>8) eS|||a a<br>eee|||
||||||||
|Legend:||||||
|R = Readable bit|W = Writable bit<br>P =|Programmable bit<br>r = Reserved bit||||
|U=Unimplementedbit|-n=BitValueatPOR:(‘0’,‘1’,x|=Unknown)||||
bit 31-8 Unimplemented: Read as ‘0’
bit 7 LSPDEN: Low-Speed Enable Indicator bit 1 = Next token command to be executed at low-speed
- 0 = Next token command to be executed at full-speed
bit6-O | DEVADDR[6:0]: 7-bit USB Device Address bits
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 205
PIC32MZ W1 and weri32E01 Family
## seman
## REGISTER 12-13: U1FRML: USB FRAME NUMBER LOW REGISTER
|Bit<br>Bit|Bit<br>Bit<br>Bit<br>Bit|Bit|Bit|Bit|
|---|---|---|---|---|
|Range | 31/23/15/7|| 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 |25/17/9/1 |24/16/8/0||||
|ee ee ee<br>a<br>a<br>qe ee<br>8 pe eee|||||
|||||||
|Legend:|||||
|R = Readable bit|W = Writable bit<br>P = Programmable bit|r = Reserved bit|||
|U=Unimplementedbit|-n=BitValueatPOR:(‘0’,‘1’,x<br>=Unknown)||||
bit 31-8 Unimplemented: Read as ‘0’ bit 7-0 FRML[7:0]: 11-bit Frame Number Lower bits The register bits are updated with the current frame number whenever a SOF TOKEN is received.
## REGISTER 12-14: U1FRMH: USB FRAME NUMBER HIGH REGISTER
|Bit||Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit|
|---|---|---|
|Range|||31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 |27/19/11/3 |26/18/10/2 | 25/17/9/1 | 24/16/8/0|
|ta <br>ee <br>8||<br>|eSee<br>Seee|
|i||a|
## Legend:
R = Readable bit W = Writable bit P = Programmable bit r = Reserved bit U = Unimplemented bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
bit 31-3. Unimplemented: Read as ‘0’
bit 2-0 FRMH[2:0]: Upper 3 bits of the Frame Number bits The register bits are updated with the current frame number whenever a SOF TOKEN is received.
renner eee e rereerence eee eee DS70005425A-page 206 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and weri32E01 Family
## smn
## REGISTER 12-15: U1TOK: USB TOKEN REGISTER
|Bit<br>Bit<br>Bit|Bit<br>Bit<br>Bit|Bit|Bit|Bit|
|---|---|---|---|---|
|Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0|||||
|ee<br>re ee eee ee ee<br>eeee eeGee ce<br>8) ee|||||
|:|||||
|Legend:|||||
|R = Readable bit<br>W = Writable bit|P = Programmable bit|r = Reserved bit|||
|U=Unimplementedbit<br>-n=BitValueat|POR:(‘0’,‘1’,x<br>=Unknown)||||
bit 31-8 | Unimplemented: Read as ‘0’
- bit 7-4 PID[3:0]: Token Type Indicator bits‘)
- 0001 = OUT (TX) token type transaction
- 1001 = IN (RX) token type transaction
- 1101 = SETUP (TX) token type transaction
- Note: All other values are reserved and must not be used.
- bit 3-0 EP[3:0]: Token Command Endpoint Address bits The four bit value must specify a valid endpoint.
Note 1: All other values are reserved and must not be used.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 207
PIC32MZ W1 and weri32E01 Family
seman
## REGISTER 12-16: U1SOF: USB SOF THRESHOLD REGISTER
|Bit<br>Bit<br>Bit|Bit<br>Bit<br>Bit<br>Bit<br>Bit|Bit|
|---|---|---|
|Range | 31/23/15/7 |30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1||24/16/8/0|
|pa<br>eeee<br>8)Ee|ee ee<br>a<br>cna a a<br>eee||
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:<br>**----- End of picture text -----**<br>
Legend:
R = Readable bit W = Writable bit P = Programmable bit r = Reserved bit U = Unimplemented bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
bit31-8 | Unimplemented: Read as ‘0’
bit 7-0 CNT[7:0]: SOF Threshold Value bits Typical values of the threshold are: 0100 1010 = 64-byte packet 0010 1010 = 32-byte packet 0001 1010 = 16-byte packet 0001 0010 =8-byte packet
renner eee e rereerence eee eee DS70005425A-page 208 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and weri32E01 Family
smn
## REGISTER 12-17: U1BDTP1: USB BDT REGISTER
|Bit|Bit<br>Bit<br>Bit|Bit<br>Bit<br>Bit<br>Bit|Bit|
|---|---|---|---|
|Range||31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 |26/18/10/2 | 25/17/9/1||24/16/8/0|
|ee <br>0 <br>8)|ee ee eeee<br> Se<br>PE|ee<br>ee||
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**----- Start of picture text -----**<br>
i<br>**----- End of picture text -----**<br>
## Legend:
R = Readable bit W = Writable bit P = Programmable bit r = Reserved bit U =Unimplemented = -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) bit
bit 31-8 Unimplemented: Read as ‘0’
- bit 7-1 BDTPTRL[15:9]: BDT Base Address Low bits This 7-bit value provides address bits 15 through 9 of the BDT base address, which defines the BDT’s starting location in the system memory. The 32-bit BDT base address is 512 byte aligned.
bit 0 Unimplemented: Read as ‘0’
## REGISTER 12-18: U1BDTP2: USB BDT PAGE 2 REGISTER
|Bit||Bit||Bit||Bit||Bit||Bit||Bit||Bit|Bit|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Range|||31/23/15/7||30/22/14/6|30/22/14/6||29/21/13/5|29/21/13/5|||28/20/12/4|||27/19/11/3||26/18/10/2|26/18/10/2|||25/17/9/1|24/16/8/0|
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**----- Start of picture text -----**<br>
i<br>**----- End of picture text -----**<br>
Legend:
R = Readable bit W = Writable bit P = Programmable bit r = Reserved bit U = Unimplemented bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
## bit 31-8 | Unimplemented: Read as ‘0’
- bit 7-0 BDTPTRH[23:16]: BDT Base Address High bits This 8-bit value provides address bits 23 through 16 of the BDT base address, which defines the BDT’s starting location in the system memory.
The 32-bit BDT base address is 512 byte aligned.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 209
## PIC32MZ W1 and weri32E01 Family
## seman
## REGISTER 12-19: U1BDTP3: USB BDT PAGE 3 REGISTER
|Bit|Bit|Bit|Bit<br>Bit<br>Bit|Bit|Bit|Bit|
|---|---|---|---|---|---|---|
|Range|| 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 |26/18/10/2 | 25/17/9/1 | 24/16/8/0||||||
|°|(eorereusiayC—“—~stsSC‘*d||||||
|Legend:|||||||
|R = Readable bit||W = Writable bit|P = Programmable bit|r = Reserved bit|||
|U=Unimplementedbit||-n=BitValueat|POR:(‘0’,‘1’,x<br>=Unknown)||||
bit31-8 | Unimplemented: Read as ‘0’
bit 7-0 BDTPTRU[31:24]: BDT Base Address Upper bits This 8-bit value provides address bits 31 through 24 of the BDT base address, which defines the BDT’s starting location in the system memory.
The 32-bit BDT base address is 512 byte aligned.
renner eee e rereerence eee eee DS70005425A-page 210 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and weri32E01 Family
## smn
## REGISTER 12-20: U1CNFG1: USB CONFIGURATION 1 REGISTER
|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit|Bit|
|---|---|
|Range | 31/23/15/7 |30/22/14/6 | 29/21/13/5 |28/20/12/4|27/19/11/3|26/18/10/2| 25/17/9/1|24/16/8/0|
|°_[oteve|worwon|userez[uses[=[=|—||UAsuseno_||
## Legend:
R = Readable bit W = Writable bit P = Programmable bit r= Reserved bit
U = Unimplemented bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
- bit 31-8 Unimplemented: Read as ‘0’
- bit 7 UTEYE: USB Eye-Pattern Test Enable bit 1 = Eye-Pattern test enabled
- 0 = Eye-Pattern test disabled
- bit 6 UOEMON: USB OE Monitor Enable bit 1 = OE signal is active; it indicates intervals during which the D+/D- lines are driving 0 = OE signal is inactive
- bit 5 USBFRZ: Freeze in Debug Mode bit
- 1 = When emulator is in Debug mode, module freezes operation
- 0 = When emulator is in Debug mode, module continues operation
- bit 4 USBSIDL: Stop in Idle Mode bit
- 1 = Discontinue module operation when device enters Idle mode
- 0 = Continue module operation in Idle mode
- bit 3-1 Unimplemented: Read as ‘0’
- bit 0 UASUSPND: Automatic Suspend Enable bit
- 1 = USB OTG module automatically suspends upon entry to Sleep mode. See the USUSPEND bit (U1PWRC[1]) in Register 12-5.
- 0 = USB OTG module does not automatically suspend upon entry to Sleep mode. Software must use the USUSPEND bit (U1PWRC[1]) to suspend the module, including the USB 48 MHz clock
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mE<br>**----- End of picture text -----**<br>
© 2020 Microchip Technology Inc. Preliminary Data Sheet
DS70005425A-page 211
## PIC32MZ W1 and weri32E01 Family
## seman
## REGISTER 12-21: U1EP0-U1EP15: USB ENDPOINT CONTROL REGISTERS
**==> picture [456 x 140] intentionally omitted <==**
**----- Start of picture text -----**<br>
||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Bit|Bit|Bit|Bit|Bit|Bit|Bit|Bit|Bit|
|Range|||31/23/15/7|||30/22/14/6|||29/21/13/5|||28/20/12/4|||27/19/11/3|||26/18/10/2|||25/17/9/1|||24/16/8/0|
|ee|ee|ee|ee|ee|ee|
|pe|Ee|
|8|PE|
|°|[7 tse|[retavos [=|| EPconois|||EPRXEN|||EPTXEN|| EPSTALL|||EPHSHK ||
**----- End of picture text -----**<br>
Legend:
R = Readable bit W = Writable bit P = Programmable bit r = Reserved bit U = Unimplemented bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
## bit 31-8 Unimplemented: Read as ‘0’
- bit 7 LSPD: Low-Speed Direct Connection Enable bit (Host mode and U1EP0 only) 1 = Direct connection to a low-speed device enabled
- 0 = Direct connection to a low-speed device disabled; hub required with PRE_PID
- bit 6 RETRYDIS: Retry Disable bit (Host mode and U1EP0 only)
- 1 = Retry NAK’d transactions disabled
- 0 = Retry NAK’d transactions enabled; retry done in hardware
- bit 5 Unimplemented: Read as ‘0’
- bit 4 EPCONDIS: Bidirectional Endpoint Control bit lf EPTXEN = 1 and EPRXEN = 1: 1 = Disable endpoint n for control transfers; only TX and RX transfers are allowed 0 = Enable endpoint n for control (SETUP) transfers; TX and RX transfers are also allowed Otherwise, this bit is ignored.
- bit 3 EPRXEN: Endpoint Receive Enable bit
- 1 = Endpoint n receive enabled
- 0 = Endpoint n receive disabled
- bit 2 EPTXEN: Endpoint Transmit Enable bit 1 = Endpoint n transmit enabled
- 0 = Endpoint n transmit disabled
- bit 1 EPSTALL: Endpoint Stall Status bit 1 = Endpoint n is stalled 0 = Endpoint n is not stalled
- bit 0 EPHSHK: Endpoint Handshake Enable bit 1 = Endpoint handshake enabled 0 = Endpoint handshake disabled (typically used for isochronous endpoints)
renner eee e rereerence eee eee DS70005425A-page 212 Preliminary Data Sheet © 2020 Microchip Technology Inc.
## PIC32MZ W1 and WFI32E01 Family smn 13.0 I/O PORTS Some of the key features of the I/O ports are:
- ¢ Individual output pin open-drain enable/disable
- Noo **t** e: Thisis datadata cheatsheet summarizeshe the feaea **t** ures a . . . . :
- of the PIC32MZ W1 family of devices. It is ¢ Individualae eeeeinput pin weak Baepull-up and eepull-down not intended to be a comprehensive refer¢ Monitor selective inputs and generate interrupt ence source. To complement the :informawhen change‘ .in pin state is detected tion in this data sheet, refer to Section 12. * Operation during Sleep and Idle modes “110 Ports” (DS60001120) in the “PIC32 ¢ Fast bit manipulation using CLR, SET and INV Family Reference Manual”, which is availregisters able from the Microchip web site Figure 13-1 illustrates a block diagram of a typical (www.microchip.com/PIC32). multiplexed 1/O port.
General purpose I/O pins allow the PIC32MZ W1 family of devices to monitor and control other devices. To add flexibility and functionality, some pins are multiplexed with alternate function(s). These functions depend on which peripheral features are on the device. In general, when a peripheral is functioning, that pin may not be used as a GPIO pin.
**==> picture [447 x 409] intentionally omitted <==**
**----- Start of picture text -----**<br>
FIGURE 13-1: BLOCK DIAGRAM OF A TYPICAL MULTIPLEXED PORT STRUCTURE<br>Peripheral Module<br>Peripheral Module Enable<br>PIO [Module] PeripheralPeripheral OutputOutput DataEnable r— |<br>RD ODC 4<br>il PB2_CLK<br>PB2_CLK. | CK _<br>WR ODC q<br>RD TRIS a } | VO Cell<br>CK _<br>utput Multiplexers<br>WRTRIS a e Jui makin<br>CK _<br>EN @<br>WRWR PORTLAT D> <]<br>eat UA Po<br>Sleep (]@| Q cKDFa@ Le onDH |<br>PB2_CLK: ———e———_,<br>Peripheral Input <R| Synchronization<br>Peripheral Input Buffer<br>Legend: R= Peripheral input buffer types may vary. Refer to Table 3 for peripheral details.<br>Note: This block diagram is a general representation of a shared port/peripheral structure for illustration purposes only. The actual structure<br>for any specific port/peripheral combination may be different than it is shown here.<br>**----- End of picture text -----**<br>
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 213
## PIC32MZ W1 and WFI32E01 Family seman
## 13.1. Parallel I/O (PIO) Ports
## 13.1.3 1/0 PORT WRITE/READ TIMING
All port pins have up to 14 registers directly associated with their operation as digital I/O. The data direction register (TRISx) determines whether the pin is an input or an output. If the data direction bit is a ‘1’, then the pin is an input. All port pins are defined as inputs after a Reset. Reads from the latch (LATx) read the latch. Writes to the latch write the latch. Reads from the port (PORTx) read the port pins, while writes to the port pins write the latch. 13.1.1 OPEN-DRAIN CONFIGURATION
One instruction cycle is required between a port direction change or port write operation and a read operation of the same port. Typically this instruction would be an NoP. 13.1.4 INPUT CHANGE NOTIFICATION The input change notification function of the I/O ports allows the PIC32MZ W1 family of devices to generate interrupt requests to the processor in response to a detectchange-of-stateinput change-of-states on selected inputeve pi **n** s. Thisin Sleep featuremode, can when the clocks are disabled. Every I/O port pin can be selected (enabled) for generating an interrupt request on a change-of-state.
In addition to the PORTx, LATx, and TRISx registers for data control, some port pins can also be individually configured for either digital or open-drain output. This is controlled by the Open-Drain Control register, ODCx, associated with each port. Setting any of the bits configures the corresponding pin to act as an open-drain output.
controlled by the Open-Drain Control register, ODCx, Seven control registers are associated with the Change associated with each port. Setting any of the bits conNotice (CN) functionality of each I/O port. The CNENx/ figures the corresponding pin to act as an open-drain CNNEx registers contain the CN interrupt enable conoutput. trol bits for each of the input pins. Setting any of these The open-drain feature allows the generation of outbits enables a CN interrupt for the corresponding pins. puts higher than Vpp (for example, 5V) on any desired CNENx enables a mismatch CN interrupt condition 5V tolerant pins by using external pull-up resistors. The when the EDGEDETECT bit (CNCONx<11>) is not set. maximum open-drain voltage allowed is the same as When the EDGEDETECT bit is set, CNNEx controls the maximum VIH specification. For pin names, refer to the negative edge while CNENx controls the positive. Table 3. The CNSTATX/CNFx registers indicate the status of 13.1.2 CONFIGURING ANALOG AND changeEDGEDETECTnotice bit.basedIf the EDGEDETECTon the settingbit isofsettheto DIGITAL PORT PINS ‘0’, the CNSTATx register indicates whether a change The ANSELx register controls the operation of the occurred on the corresponding pin since the last read analog port pins. The port pins that are to function as of the PORTx bit. If the EDGEDETECT bit is set to ‘1’, analog inputs must have their corresponding ANSEL the CNFx register indicates whether a change has and TRIS bits set. In order to use port pins for I/O occurred and through the CNNEx/CNENx registers the functionality with digital modules, such as timers, edge type of the change that occurred is also indicated. UARTs, and so on, the corresponding ANSELx bit must Each I/O pin also has a weak pull-up and a weak be cleared. pull-down connected to it. The pull-ups act as a The ANSELx register has a default value of OxFFFF; current source or sink source connected to the pin, therefore, all pins that share analog functions are and eliminate the need for external resistors when analog (not digital) by default. push-button or keypad devices are connected. The if the TRIS bit|is cleared (output) while. the ANSELx bit; thepull-upsCNPUxand andpull-downsthe CNPDxare enabledregisters,separatelywhich containusing is set, the digital output level (VOH or VOL) is converted the control bits for each of the pins. Setting any of by an analog peripheral, such as the ADC module or the control bits enables the weak pull-ups and/or Comparator module. pull-downs for the corresponding pins. When the PORT register is read, all pins configured as analog input channels are read as cleared (a low level). wg gs . notification pins should always’ be Pins configured as digital inputs do not convert an disabled when theport pin is configured as analog input. Analog levels on any pin defined as a a digital output. digital input (including the ANx pins) can cause the input buffer to consume current that exceeds the An additional control register (CNCONx) is shown in device specifications. Register 13-3.
renner eee e rereerence eee eee DS70005425A-page 214 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family smn 13.2 Registers for Slew Rate Control PPS configuration provides an alternative to these Some choices by enabling peripheral set selection and their slew I/O pins can be configured for various types of placement on a wide range of I/O pins. By increasing rate control on its associated port. This is the pinout options available on a particular device, controlled by the Slew Rate Control bits in the users can better tailor the device to their entire withSRCONeach1x I/Oandport.SRCONOxThe slew registersrate control that areis associatedconfigured application,the device. rather than trimming the application to fit using the corresponding bit in each register, as shown . . . in Table 13-1. The PPS configuration feature operates over a fixed As subset of digital I/O pins. Users may independently an example, writing 0x0001, 0x0000 to SRCON1A map the input and/or output of most digital peripherals and SRCONOA, respectively, will enable slew rate to these I/O pins. PPS is performed in software and control on the RAO pin and sets the slew rate to the generally does not require the device to be reproslow edge rate. grammed. Hardware safeguards are included that preTABLE 13-1: SLEW RATE CONTROL BIT vent accidental or spurious changes to the peripheral SETTINGS") mapping once it has been established. 1 1 Slew rate control is enabled The number of available pins is dependent on the and is set to the slowest particular device and its pin count. Pins that support the edge rate. PPS feature include the designation “RPn” in their full 1 Slew rate control is enabled pin designation, where “RP” designates a remappable and is set to the slow edge peripheral and “n” is the remappable port number. rate. 1 Siamurate eanttal is enabled 13.4.2 AVAILABLE PERIPHERALS and is set to the medium The peripherals managed by the PPS are all digitaledge rate. only peripherals. These include general _ serial Slew rate control is disabled communications (UART, SPI, and CAN), general purand is set to the fastest pose timer clock inputs, timer-related peripherals (input edge rate. capture and output compare), interrupt-on-change Note 4: By default, all of the port pins are set to inputs, and reference clocks (input and output). the fastest edge rate. In comparison, some digital-only peripheral modules are never included in the PPS feature. This is because 13.3 CLR, SET, and INV Registers the peripheral's function requires special V/O circuitry on a specific port and cannot be easily connected to Every I/O module register has a corresponding CLR multiple pins. These modules include I2C among oth(clear), SET (set) and INV (invert) register designed to ers. A similar requirement excludes all modules with provide fast atomic bit manipulations. As the name of analog inputs, such as the ADC. the register implies, a value written to a SET, CLR or Akey difference between remappable and non-remapINV register effectively performs the implied operation, pable peripherals is that remappable peripherals are but only on the corresponding base register and only not associated with a default I/O pin. The peripheral bits specified as ‘1’ are modified. Bits specified as ‘0’ must always be assigned to a specific I/O pin before it are not modified. can be used. In contrast, non-remappable peripherals Reading SET, CLR and INV registers return undefined are always available on a default pin, assuming that the values. To see the affects ofa write operation to a SET, peripheral is active and not conflicting with another CLR or INV register, the base register must be read. peripheral. When a remappable peripheral is active on a given I/O 13.4 Peripheral Pin Select (PPS) pin, it takes priority over all other digital I/O and digital ap eee. ges. a eee Bee . esas. eres. communicatPriority is g **i** venon regardlessperipheralsof theassociatedtype of withperipheralthe thatpin. ing the largest possible set of peripheral features while . y i R 9 bl ioh 4 P a" a minimizing the conflict of features on I/O pins. The chalcpl inl ila eager = Erne lenge is: even greater on low pin-count: devices.: In an over any analog functions associated with the pin. application where more than one peripheral needs to be assigned to a single pin, inconvenient workarounds in application code or a complete redesign may be the only option. reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 215
## PIC32MZ W1 and WFI32E01 Family seman
13.4.3 CONTROLLING PERIPHERAL PIN SELECT PPS features are controlled through two sets of SFRs: one to map peripheral inputs, and one to map outputs. As they are separately controlled, a particular peripheral’s input and output (if the peripheral has both) can be placed on any selectable function pin without constraint.
The association of a peripheral to a peripheral-selectable pin is handled in two different ways, depending on whether an input or output is being mapped.
## 13.4.5 VIRTUAL INPUT PINS
Included in the input pin mappings are special inputs taken from nodes within the device. These nodes include outputs from built-in digital noise filters. These inputs may be used to filter a pin input before presenting that signal to another module like a ICAP or UART input. This is accomplished by configuring a particular module to use PTG30 or PTG31 (which come from the PTG module) instead of a device pin, using the mapping.
13.4.4 INPUT MAPPING
The inputs of the PPS options are mapped on the basis of the peripheral. That is, a control register associated with a peripheral dictates the pin it will be mapped to. The [pin name]R registers, where [pin name] refers to the peripheral pins listed in Table 13-2, are used to configure peripheral input mapping (see Register 13-1). Each register contains set of 4-bit fields. Programming these bit fields with an appropriate value maps the RPn pin with the corresponding value to that peripheral. For any given device, the valid range of values for any bit field is shown in Table 13-2.
For example, Figure 13-2 illustrates the remappable pin selection for the U1RX input.
**==> picture [187 x 20] intentionally omitted <==**
**----- Start of picture text -----**<br>
FIGURE 13-2: REMAPPABLE INPUT<br>EXAMPLE FOR U1RX<br>**----- End of picture text -----**<br>
**==> picture [238 x 216] intentionally omitted <==**
**----- Start of picture text -----**<br>
U1RXR<3:0><br>LX\Z 0<br>RPA2<br>Wd\Z 1<br>RPA10<br>NX] 2 U1RX input<br>RPB2 to peripheral<br>ee<br>ee<br>e e<br>XJKA n<br>RPn<br>Note: For input only, PPS functionality does not<br>have priority over TRISx settings. Therefore,<br>when configuring RPn pin for input, the<br>corresponding bit in the TRISx register must<br>also be configured for input (set to ‘1’).<br>**----- End of picture text -----**<br>
renner eee e rereerence eee eee DS70005425A-page 216 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family eC
TABLE 13-2: INPUT PIN SELECTION
|Peripheral Pin|[pin name]R SFR|[pin name]R bits|[pin name]R Value to RPn Pin Selection|
|---|---|---|---|
|INT4|INT4R|INT4R<3:0>|4’b0000 = RPAO|
|INTO<br>T1CK|INTOR<br>T1ICKR|INTOR<3:0><br>T1CKR<3:0>|4’b0001 = RPA4<br>4’b0010 = RPA12<br>4’b0011 = RPBO|
|T5CK|T5CKR|T5CKR<3:0>|4’b0100 = RPB4|
||||4’b0110 = RPB12|
|U3RX|U3RXR|U3RXR<3:0>|4’b0111 = RPCO|
|SDI1|SDR|SDI4R<3:0>|4’b1000 = RPC4|
|ECOL|ECOLR|ECOLR<3:0>|4’b1001 = RPC9<br>eae|
|ETXCLK|ETXCLKR|ETXCLKR<3:0>|4’b1011 = RPKO|
|REFI<br>OCFD|REFIR<br>OCFDR|REFIR<3:0><br>OCFDR<3:0>|4’b1100 = RPK4<br>4’b1100 = RPK8<br>4°b1101 = RPK12|
||||4’b1111 = Reserved|
|INT3|INT3R|INT3R<3:0>|4’b0000 = RPA1|
|T2CK|T2CKR|T2CKR<3:0>|4’b0001 = RPAS|
||||4’b0010 = RPA13|
|T6CK|T6CKR|T6CKR<3:0>|4°b0011 = RPB1|
||IC3R|IC3R<3:0>|4’b0100 = RPB5|
|U1CTS|U1CTSR|U1CTSR<3:0>|4'b0101 = RPB9Y|
||||4’b0110 = RPB13|
|U2RX|U2RXR|U2RXR<3:0>|4’b0111 = RPC1|
|SDI2|SDI2R|SDI2R<3:0>|4’b1000 = RPC5|
|FERXDS—[ERXDSR[ERXDSRe30>JAP<br>ERXD3<br>ERXD3R<br>ERXD3R<3:0>|||JAP cay<br>Wb1010 = RPC14|
|OCFC|OCFCR|OCFCR<3:0>|4’b1011 = RPK1|
||||4’b1100 = RPK5|
||||4’b1100 = RPKQ|
||||4’b1101 = RPK13|
||||4’b1111 = Reserved|
|INT2|INT2R|INT2R<3:0>|4’b0000 = RPA2|
|T3CK|T3CKR|T3CKR<3:0>|4’b0001 = RPA10|
||||4’b0010 = RPA14|
|T7CK|T7CKR|:<br>T7CKR<3:0>|4°b0014 = RPB2|
||IC1R|IC1R<3:0>|4’b0100 = RPB6|
|U1RX|U1RXR|U1RXR<3:0>|4'b0101 = RPB10|
||||4’b0110 = RB14|
|U2CTSn|U2CTSnR|U2CTSnR<3:0>|#b0111 = RPC2|
|C1RX|C1RXR|C1RXR<3:0>|4’b1000 = RPC6|
|ECRS[ECRSR[ECRSR<S.0>I ce<br>ECRS<br>ECRSR<br>ECRSR<3:0><br>aeai-Eeche||||
|ERXD2|ERXD2R|ERXD2R<3:0>|4’b1011 = RPK2|
|OCFB|OCFBR|OCFBR<3:0>|4’b1100 = RPK10<br>NLi=BE|
||||4’b1111=PTG30|
eee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 217
PIC32MZ W1 and WFI32E01 Family
## seman
TABLE 13-2: INPUT PIN SELECTION (CONTINUED)
|Peripheral|Pin|[pin name]R SFR|[pin name]R bits|[pin|name]R Value to RPn Pin Selection|
|---|---|---|---|---|---|
|INT1||INT1R|INT1R<3:0>|4’b0000|= RPA3|
|T4CK||T4CKR|TACKR<3:0>|4'b0001|= RPA11|
|||||4’b0010|= RPA15|
|||IC2R|IC2R<3:0>|JeDGA)|mie|
|U3CTSn||U3CTSnR|U3CTSnR<3:0>|4’b0100|= RPB7|
|||ben|,<br>eeehce>|4’b0101 <br>4’b0110|= RPB11<br> = Reserved|
|C2RX||C2RXR|C2RXR<3:0>|4’b0111|= RPC3|
|OCFA||OCFAR|OCFAR<3:0>|4’b1000|= RPC7|
|||||4’b1001|= RPC8|
|||||4’b1010|= RPC12|
|||||4’b1011|= RPK3|
|||||4’b1100|= RPK7|
|||||4’b1100|= RPK11|
|||||4’b1101|= Reserved|
|||||4’b1111|=PTG31|
——— DS70005425A-page 218
Preliminary Data Sheet
© 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
## 13.4.6 OUTPUT MAPPING
In contrast to inputs, the outputs of the PPS options are mapped on the basis of the pin. In this case, a control register associated with a particular pin dictates the peripheral output to be mapped. The RPnR registers (Register 13-2) are used to control output mapping. Like the [pin name]R registers, each register contains set of 4-bit fields. The value of the bit field corresponds to one of the peripherals, and that peripherals output is mapped to the pin (see Table 13-3 and Figure 13-3).
A null output is associated with the output register Reset value of iid‘0’. Thisaa is done to ensure that remappable outputs remain disconnected from all output pins by default.
## 13.4.7.1 Control Register Lock
Under normal operation, writes to the RPnR and [pin name]R registers are not allowed. Attempted writes appear to execute normally, but the contents of the registers remain unchanged. To change these registers, they must be unlocked in hardware. The register lock is controlled by the IOLOCK Configuration bit (CFGCONO<13>). Setting IOLOCK prevents writes to the control registers; clearing IOLOCK allows writes.
- snnengll aciecindingneicnsimmncnnnees Leiigneinens sequence: must4 be: executed.: Refer to a pl aoe rac allll PLL” in: the “PIC32. Family Reference Manual” for details.
## FIGURE 13-3: EXAMPLE OF MULTIPLEXING OF REMAPPABLE OUTPUT FOR RPAO
RPAOR<3:0>
**==> picture [169 x 113] intentionally omitted <==**
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Default<br>0<br>U1TX Output 1<br>U2RTS Output 2<br>RPAO<br>@ | Output Data<br>e<br>14<br>REFCLKO1<br>15<br>**----- End of picture text -----**<br>
- 13.4.7 CONTROLLING CONFIGURATION CHANGES
Some restrictions on peripheral remapping are needed to prevent accidental configuration changes as the peripheral remapping can be changed during run time. PIC32MZ W1 family of devices include two features to prevent alterations to the peripheral map:
- Control register lock sequence
- Configuration bit select lock
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 219
PIC32MZ W1 and WFI32E01 Family
## SSS
TABLE 13-3: OUTPUT PIN SELECTION
|500000|=|No Connect|
|---|---|---|
|ale||end|
|5’b10010|=|REFO1|
|Sein||STB|
|51500000|=|No Gonned|
|5'b00101|=|OC2|
|Pare <br>5’b10011|<br> =|ees<br> PTG29|
|5'b10110|=|ETXERR|
eee DS70005425A-page 220 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
SSS
TABLE 13-3: OUTPUT PIN SELECTION (CONTINUED)
|5700000|=|No Connect|
|---|---|---|
|5’b00101|=|OC3|
|51500000|=|No Connect|
|5’b00100|=|SS2|
eee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 221
PIC32MZ W1 and WFI32E01 Family —ne)
13.5 Function Priority for Device Pins Device pins have an associated priority order in which functionality is brought out on it. Availability of PPS functionality is impacted by this priority order. For example, if high-speed UART is enabled, pins PA6, PA7, PA8, and PAY are given priority to be used as UART pins instead of PORT pins.
Refer to 2.0 “PIC32MZ1025W104 SoC Description” forbers.mapping of device pin name to package pin numNote: Refer to corresponding reference
Refer to Table 13-4, Table 13-5, Table 13-6, and Table 13-7 for the priority in which functions are brought out on each device pin. TABLE 13-4: PRIORITY FOR DEVICE PINS PA(N) (N = 0-15) [____PinName | Functions in Pronty Order | __Relerence Peripheral |
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ES DS70005425A-page 222 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
SSS
TABLE 13-4: PRIORITY FOR DEVICE PINS PA(N) (N = 0-15) (CONTINUED) (___Pinname __| _ Functions Priory Order | __Reference Peripheral | SS ——_
eee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 223
PIC32MZ W1 and WFI32E01 Family
SSS
TABLE 13-4: PRIORITY FOR DEVICE PINS PA(N) (N = 0-15) (CONTINUED) fF ___Pinwiame | Functions m Priory rder | __Reference Peripheral __|
TABLE 13-5: PRIORITY FOR DEVICE PINS PB(N) (N = 0-15) [___PinName | Functions i Priory Order__| Reference Peripheral __|
eee DS70005425A-page 224 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
SSS
TABLE 13-5: PRIORITY FOR DEVICE PINS PB(N) (N = 0-15) (CONTINUED) fF __Pinname __| Functions im Priory Order__| Reference Peripheral
eee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 225
PIC32MZ W1 and WFI32E01 Family
SSS
TABLE 13-5: PRIORITY FOR DEVICE PINS PB(N) (N = 0-15) (CONTINUED) [___PinName ___| Functions inProrty Order | __Reference Peripheral |
|ee
eee DS70005425A-page 226 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
SSS
TABLE 13-6: PRIORITY FOR DEVICE PIN PC(N) (N = 0-15) fF ___PinName __| Functions mPrionty Order __Reference Peripheral
eee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 227
PIC32MZ W1 and WFI32E01 Family
SSS
TABLE 13-6: PRIORITY FOR DEVICE PIN PC(N) (N = 0-15) (CONTINUED) fF ___Piname ___| Functions im Pronty Order_| __Reference Peripheral
eee DS70005425A-page 228 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
SSS
TABLE 13-7: PRIORITY FOR DEVICE PIN PK(N) (N = 0-15) fF ___Pinname | _ Functions nPriorty Oder | __Refeence Peripheral
eee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 229
PIC32MZ W1 and WFI32E01 Family
## SSS
TABLE 13-7: PRIORITY FOR DEVICE PIN PK(N) (N = 0-15) (CONTINUED) | ___Pinniame ___| Functions in Priory Order | __Reference Peripheral __|
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eee DS70005425A-page 230 Preliminary Data Sheet © 2020 Microchip Technology Inc.
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## PIC32MZ W1 and WFI32E01 Family
## seman
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PIC32MZ W1 and WFI32E01 Family
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## REGISTER 13-1: = [pin name]R: PERIPHERAL PIN SELECT INPUT REGISTER
|Bit<br>Bit<br>Bit|Bit|Bit<br>Bit|Bit|Bit<br>Bit|
|---|---|---|---|---|
|Range | 31/23/15/7 |30/22/14/6 ||29/21/13/5 |28/20/12/4 |27/19/11/3 |||26/18/10/2|25/17/9/1<br>24/16/8/0|
|ee<br>ee ne ee ee<br>pee SE Se ee<br>ss SeSee|||ee<br>EE<br> eee||
|a<br>a<br>a|||||
|Legend:|||||
|R = Readable bit|W = Writable bit|U = Unimplemented bit,||read as ‘0’|
|-n=ValueatPOR|‘1’=Bitisset|‘0’=Bitiscleared||x=Bitisunknown|
bit 31-4 Unimplemented: Read as ‘0’
bit 3-0 [pin name]R<4:0>: Peripheral Pin Select Input bits Where [pin name] refers to the pins that are used to configure peripheral input mapping. See Table 13-2 for input pin selection values.
Note: Register values can only be changed if the IOLOCK Configuration bit (CFGCON<13>) = 0.
## REGISTER 13-2: RPnR: PERIPHERAL PIN SELECT OUTPUT REGISTER
|Bit|Bit<br>Bit||Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit|
|---|---|---|---|
|Range|| 31/23/15/7 |30/22/14/6|||29/21/13/5 |28/20/12/4 |27/19/11/3 | 26/18/10/2<br>25/17/9/1<br>24/16/8/0|
|pe <br>pie <br>ss|EE <br> SS<br> Sp||SE<br>ee<br>ee ee<br>ee ee|
|—|to =<br>| =|| =PP||
|Legend:||||
|R = Readable bit|||W = Writable bit<br>U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR|||‘1’=Bitisset<br>‘0’=Bitiscleared<br>x=Bitisunknown|
bit 31-4 Unimplemented: Read as ‘0’
bit 3-0 RPnR<4:0>: Peripheral Pin Select Output bits See Table 13-3 for output pin selection values.
Note: Register values can only be changed if the IOLOCK Configuration bit (CFGCON<13>) = 0.
renner eee e rereerence eee eee DS70005425A-page 246 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
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REGISTER 13-3: CNCONx: CHANGE NOTICE CONTROL FOR PORTx REGISTER (x = A/B/C/K)
|Bit|Bit<br>Bit|Bit|Bit|Bit<br>Bit<br>Bit<br>Bit|
|---|---|---|---|---|
|Range|| 31/23/15/7 |30/22/14/6 | 29/21/13/5 |28/20/12/4||28/20/12/4|27/19/11/3<br>26/18/10/2 | 25/17/9/1 | 24/16/8/0|
||eeee<br>ee eee eee||||
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|i|= A|nO||=)=|
|Legend:|||||
|R = Readable bit||W = Writable|bit|U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR||‘1’=Bitisset||‘0’=Bitiscleared<br>x=Bitisunknown|
bit 31-16 Unimplemented: Read as ‘0’
bit 15 ON: CN Control ON bit
1 = CNis enabled
0 = CN is disabled
- bit 14-12 Unimplemented: Read as ‘0’
bit 11 EDGEDETECT: Change Notification Style bit 1 = Edge style. Detect edge transitions (CNFx used for CN event). 0 = Mismatch style. Detect change from last PORTx read (CNSTATx used for CN event).
bit 10-0 Unimplemented: Read as ‘0’
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 247
PIC32MZ W1 and WFI32E01 Family
DS70005425A-page 248
Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
## 14.0 PERIPHERAL TRIGGER GENERATOR (PTG)
- PTG does not synchronize its clock sources. Use the withsame anotherclock modulesource for(forcoordinated example, ADC).operation of PTG PTG module has the following key features: -
The PTG provides a means to schedule complex highPTG module has the following key features: speed peripheral operations that would be difficult to - achieve using software. The PIC32MZ W1 device has * Multiple clock sources single PTG module. The PTG module uses thirty-two 8- * Four 16-bit general purpose timers bit commands, called as step, that the user writes to the * Two 16-bit general limit counters PTG Queue registers (PTGQUE0-PTGQUE7). Each * Configurable for rising or falling edge triggering 8-bit step is made up of a four bit command code and * PTG generated processor interrupts include: a four bit parameter field. The commands perform . . operations such as wait for an input trigger signal, gen~ (Retin ceaniig inate (pRaSsOr IMEX erate an output trigger signal, and wait for the timer. - poe on a step event in Single Step Ping - Interrupt on a PTG WDT time-out
- ¢ Receives trigger signals from following peripherals:
- ADC
- ICAP
- - OCMP
- Generates trigger or synchronize to following peripherals:
- ADC
- ICAP
- - OCMP
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 249
## PIC32MZ W1 and WFI32E01 Family
## eee
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FIGURE 14-1: PTG BLOCK DIAGRAM<br>**----- End of picture text -----**<br>
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## seman
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PIC32MZ W1 and WFI32E01 Family
## smn
## REGISTER 14-1: PTGCON: PTG CONTROL REGISTER
|Bit<br>Bit|Bit<br>Bit|Bit|Bit<br>Bit<br>Bit<br>Bit|
|---|---|---|---|
|Range |31/23/15/7||30/22/14/6 | 29/21/13/5 |28/20/12/4|||27/19/11/3 |26/18/10/2 | 25/17/9/1<br>24/16/8/0|
|:||||
|°<br>eres|||dren|
|° [Pree <br>-|[7 = |Presiot_[preroat™|revo_|_preswr_|<br>pressen®| prawis |<br>Pronsnc[ uo | uo | vo | Ro<br>|RO|||
|Legend:|HC = Hardware|Cleared|HS = Hardware Set|
|R = Readable bit|W = Writable bit||U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR|‘1’=Bitisset||‘0’=Bitiscleared<br>x=Bitisunknown|
- bit 31-19 PTGCLK<2:0>: PTG Module Clock Source Select bits‘) 111 = PTG module clock source will be REF_CLK 110 = PTG module clock source will be TMR7_CLK 101 = PTG module clock source will be TMR5_CLK 100 = PTG module clock source will be TMR3_CLK 011 = PTG module clock source will be TMR1_CLK 010 = PTG module clock source will be FRC_CLK 001 = PTG module clock source will be SYS_CLK 000 = PTG module clock source will be PB1_CLK
- bit 28-24 PTGDIV<4:0>: PTG Module Clock Prescaler (Divider) bits‘) 11111 = Divide by 32 11110 = Divide by 31
00001 = Divide by 2 00000 = Divide by 1
- bit 23-20 PTGPWD<3:0>: PTG Trigger Output Pulse Width bits‘)
1111 =All trigger outputs are 16 PTG clock cycles wide 1110 =All trigger outputs are 15 PTG clock cycles wide
0001 =All trigger outputs are 2 PTG clock cycles wide 0000 =All trigger outputs are 1 PTG clock cycle wide
- bit 19 Unimplemented: Read as ‘0’
- Note 1: These bits are read only when the module is executing step command (PTGSTRT = 1). 2: The PTGSSEN bit may only be written when in Debug mode, and will otherwise always read ‘0’. The PTGSSEN bit (internal) value is preserved independent of Debug mode.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 253
## PIC32MZ W1 and WFI32E01 Family seman
## REGISTER 14-1: PTGCON: PTG CONTROL REGISTER (CONTINUED) bit 18-16 PTGWDT<2:0>: PTG Watchdog Time-Out Count Value Select bits!)
- 111 = Watchdog will timeout after 512 PTG clocks 110 = Watchdog will timeout after 256 PTG clocks 101 = Watchdog will timeout after 128 PTG clocks 100 = Watchdog will timeout after 64 PTG clocks 011 = Watchdog will timeout after 32 PTG clocks 010 = Watchdog will timeout after 16 PTG clocks 001 = Watchdog will timeout after 8 PTG clocks 000 = Watchdog disabled
- bit 15 PTGON: Module Enable bit 1 = PTG module is enabled 0 = PTG module is disabled
- bit 14 Unimplemented: Read as '0' bit 13 PTGSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode (act as if in Sleep mode) 0 = Continue module operation when device enters Idle mode
- bit12 | PTGTOGL: TRIG Output Toggle Mode bit!) 1 = Toggle state of the PTGOx for each execution of the PTGTRIG command 0 = Each execution of the PTGTRIG command will generate a single PTGOx pulse determined by the value in the PTGPWDx bits
- bit 11 Unimplemented: Read as '0' bit 10 PTGSWT: Software Trigger bit This control bit enables the application software to interact with the PTG module via the “Wait for software trigger’ step commands (PTGCTRL SWTRGE or PTGCTRL SWTRGL). The PTGCTRL SWTRGE command is only sensitive to a 0 to 1 transition of the PTGSWT bit that occurs during execution of the command. The PTGCTRL SWTRGL command is sensitive to a logic 1 state of the PTGSWT bit that is present prior to and during, or occurs during, execution of the command. 1 = If the PTG state machine is executing the PTGCTRL SWTRGE command and PTGSWT = 0 prior to the bit set operation, the command will complete and execution will continue. If PTGSWT = 1 prior to the bit set operation, no action.
- If the PTG state machine is executing the PTGCTRL SWTRGL command, the command will complete and execution will continue irrespective of when the bit set operation occurred. 0 = No action other than to clear the bit'2).
- Note 1: Software may write ‘1’ to the PTGSWT bit to initiate the software trigger. Writing ‘0’ (at any time) will have no effect.
- 2: PTGSWT is automatically cleared by hardware when the PTGCTRL SWTRGE command completes after the associated step delay, if any (when the subsequent command starts). PTGSWT is not automatically cleared by hardware when the PTGCTRL SWTRGL command completes.
- 3: PTGSWT is cleared when PTGON = 0.
- bit 9 PTGSSEN: Enable Single Step bit!?) If in Debug mode:
- 1 = Enable command Single Step mode
- 0 = Disable command Single Step mode
Otherwise, the PTGSSEN bit will have no effect.
- Note: The PTGSSEN bit may only be written when in Debug mode, and will otherwise always read ‘0’.
- Note 1: These bits are read only when the module is executing step command (PTGSTRT = 1).
- 2: The PTGSSEN bit may only be written when in Debug mode, and will otherwise always read ‘0’. The PTGSSEN bit (internal) value is preserved independent of Debug mode.
## a
DS70005425A-page 254 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family smn
- REGISTER 14-1: PTGCON: PTG CONTROL REGISTER (CONTINUED) bit 8 PTGIVIS: Counter/Timer Internal Visibility Control bit!) 1 = SFR read of the PTGSDLIM, PTGCnLIM or PTGTnLIM registers will yield the contents of the corresponding internal timer/counter (PTGSD, PTGCn or PTGTn, respectively) 0 = SFR read of the PTGSDLIM, PTGCnLIM or PTGTnLIM registers will yield the contents of the associated SFR register, and represents the value previously written to the target register.
- The register read will be either the UPB or internal register as determined by the PTGSTART bit. Note 1: The PTGIVIS bit enables the user to “debug” the setup and operation of the PTG module in an application.
- bit 7 PTGSTRT: Start PTG Sequencer bit
- If not in Single Step mode:
- 1 = Start PTG sequencer and sequentially execute commands (Continuous mode)
- 0 = Stop PTG sequencer and place in Halt state
- If in Single Step mode:
- 1 = Start PTG sequencer and execute one step command, and then halt
- Note: Single step enable must be set (PTGSSEN = 1) prior to the bit set operation of PTGSTRT.
- 0 = Stop PTG sequencer and place in HALT state
- Note 1: In Single Step mode (PTGSSEN = 1), PTGSTRT is automatically cleared by hardware when the target command completes after the associated step delay, if any (when the subsequent command starts).
- 2: PTGSTRT is cleared when PTGON = 0.
- 3: This bit can be hardware clearable by the PTG WDT.
- bit 6 PTGWDTO: PTG State Machine Watchdog Timeout Status bit!)
- 1 = PTG state machine watchdog has timed out
- 0 = PTG state machine watchdog has not timed out
- Note: PTGWDTO is automatically set by hardware but must be cleared by the user or by disabling the module (PTGON = 0).
- bit 5 PTGBUSY: PTG State Machine Busy bit
- 1 = PTG state machine is running on the selected PTG clock source instructions - No SFR writes are allowed to PTGCLK and PTBDIV bit fields.
- 0 = PTG state machine is NOT running.
- Note: PTGBUSY is asserted when PTGON= 1 to indicate PTG is busy running, it will be cleared by HW once sequencer has completed all the tasks when PTGON is cleared.
- bit 4-2 Unimplemented: Read as '0' bit1-0 | PTGITM<1:0>: Selects PTG Input Trigger Command Operating Mode bits‘)
- 11 = Test input state once per step delay, exit when (level) true and complete command without step delay.
- 10 = Test input state once per step delay, exit when (level) true to step delay prior to command completion. 01 = Test input state continuously, exit when valid edge detected (during execution) and complete command without step delay.
- 00 = Test input state continuously, exit to step delay when valid edge detected (during execution), prior to command completion.
## Note 1:
- 1: These bits are read only when the module is executing step command (PTGSTRT = 1). 2: The PTGSSEN bit may only be written when in Debug mode, and will otherwise always read ‘0’. The PTGSSEN bit (internal) value is preserved independent of Debug mode.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 255
PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 14-2: PTGBTE: PTG BROADCAST TRIGGER ENABLE REGISTER
|Bit|Bit|Bit|Bit|Bit|Bit||Bit|Bit|Bit|
|---|---|---|---|---|---|---|---|---|---|
|Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4|||||27/19/11/3|26/18/10/2 | 25/17/9/1||||24/16/8/0|
|:||||||||||
|:||||||||||
|:||||||||||
|:||||||||||
|Legend:||||||||||
|R = Readable bit||W|= Writable bit||U = Unimplemented||bit, read as ‘0’|||
|-n=ValueatPOR||‘1’|=Bitisset||‘0’=Bitiscleared||x|=Bitisunknown||
bit 31-0 PTGBTE<31:0>: Broadcast Trigger Enable Register bits")
- Each bit corresponds to a individual trigger output. If a bit is set in the PTGBTE register, the corresponding individual trigger output will be generated if a step broadcast command is executed.
Note 1: These bits are read only when the module is executing step commands (PTGSTRT = 1).
renner eee e rereerence eee eee DS70005425A-page 256 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
## REGISTER 14-3: PTGHOLD: PTG HOLD REGISTER
|Bit<br>Bit|Bit|Bit|Bit<br>Bit|Bit<br>Bit|Bit|
|---|---|---|---|---|---|
|Range | 31/23/15/7 | 30/22/14/6 |||29/21/13/5 | 28/20/12/4 |27/19/11/3 | 26/18/10/2 | 25/17/9/1 ||||24/16/8/0|
|aea||||||
|ae (eT =|||=<br>=|=||
|:||||||
|:||||||
|Legend:||||||
|R = Readable bit||W = Writable bit|U = Unimplemented bit, read as ‘0’|||
|-n=ValueatPOR||‘1’=Bitisset|‘0’=Bitiscleared|x=Bitisunknown||
## bit 31-16 Unimplemented: Read as ‘0’
- bit 15-0 PTGHOLD<15:0>: General Purpose Hold Register bits!)
- Preserves a copy of user supplied data for re-initializing one of the following registers, PTGTOLIM, PTGT1LIM, PTGCOLIM, PTGC1LIM, PTGSDLIM, and PTGLO via a step command.
Note 1: These bits are read only when the module is executing step commands (PTGSTRT = 1).
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 257
PIC32MZ W1 and WFI32E01 Family
seman
## REGISTER 14-4: PTGTOLIM: PTG TIMERO LIMIT REGISTER
|Bit|Bit|Bit|Bit|Bit|Bit|Bit|Bit|Bit|
|---|---|---|---|---|---|---|---|---|
|Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 |27/19/11/3 | 26/18/10/2|||||||| 25/17/9/1|| 24/16/8/0|
|ae|||||||||
|a||eae|eeGe||a||||
|:|||||||||
|:|||||||||
|Legend:|||||||||
|R = Readable bit|||W = Writable bit||U = Unimplemented bit, read as ‘0’||||
|-n=ValueatPOR|||‘1’=Bitisset||‘0’=Bitiscleared||x=Bitisunknown||
bit 31-16 Unimplemented: Read as ‘0’ bit 15-0 PTGTOLIM<15:0>: PTG (GP) Timer0 Limit Register bits‘
General Purpose Timer0 Limit register (effective only with a “Wait for GP Timer0” step command).
Note 1: These bits are read only when the module is executing step commands (PTGSTRT = 1).
renner eee e rereerence eee eee DS70005425A-page 258 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
REGISTER 14-5: PTGT1LIM: PTG TIMER1 LIMIT REGISTER
|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit|
|---|
|Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 |27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0|
|aea<br>pase Se ee ee|
|:|
|:|
|Legend:|
|R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR<br>‘1’=Bitisset<br>‘0’=Bitiscleared<br>x=Bitisunknown|
bit 31-16 Unimplemented: Read as ‘0’ bit31-0 PTGT1LIM<15:0>: PTG (GP) Timer1Limit Register bits
General Purpose Timer1 Limit register (effective only with a “Wait for GP Timer1” step command).
Note 1: These bits are read only when the module is executing step commands (PTGSTRT = 1).
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 259
PIC32MZ W1 and WFI32E01 Family
seman
## REGISTER 14-6: PTGSDLIM: PTG STEP DELAY LIMIT REGISTER
|Bit<br>Bit|Bit<br>Bit|Bit<br>Bit|Bit<br>Bit|Bit|
|---|---|---|---|---|
|Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 |27/19/11/3 | 26/18/10/2 | 25/17/9/1||||| 24/16/8/0|
|ae|||||
|158<br>||||||
|7<br>||||||
|Legend:|||||
|R = Readable bit|W = Writable bit|U = Unimplemented bit, read as ‘0’|||
|-n=ValueatPOR|‘1’=Bitisset|‘0’=Bitiscleared|x=Bitisunknown||
- bit 31-6 Unimplemented: Read as ‘0’
bit 15-0 PTGSDLIM<15:0>: PTG Step Delay Limit Register bits‘)
Holds a PTG step delay value representing the number of additional PTG clocks between the start of a step command, and the completion of the step command.
A base delay of a command is one PTG clock period, and the PTG step delay value is added to this minimum command delay to create the total step command duration. That is, if PTGSDLIM = 0x0006, the resultant step command duration will be 7 PTG clocks.
Note 1: These bits are read only when the module is executing step commands (PTGSTRT = 1).
Meeeaa DS70005425A-page 260 Preliminary Data Sheet © 2020 Microchip Technology Inc.
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## smn
## REGISTER 14-7: PTGCOLIM: PTG COUNTER ‘0’ LIMIT REGISTER
|Bit<br>Bit<br>Bit<br>Bit|Bit<br>Bit<br>Bit<br>Bit|Bit|Bit<br>Bit<br>Bit<br>Bit|
|---|---|---|---|
|Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 |27/19/11/3 |26/18/10/2 | 25/17/9/1 | 24/16/8/0||||
|ae<br>a<br>pee Se|ee||eT|
|:||||
|:||||
|Legend:||||
|R = Readable bit|W = Writable bit||U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR|‘1’=Bitisset||‘0’=Bitiscleared<br>x=Bitisunknown|
## bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 PTGCOLIM<15:0>: PTG Counter ‘0’ Limit Register bits()
These bits can be used to specify the loop count for the PTGJMPCO step command, or as a general purpose counter limit register.
Note 1: These bits are read only when the module is executing step commands (PTGSTRT = 1).
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 261
PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 14-8: PTGC1LIM: PTG COUNTER ‘1’ LIMIT REGISTER
|Bit<br>Bit|Bit<br>Bit|Bit<br>Bit<br>Bit<br>Bit<br>Bit|
|---|---|---|
|Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 |27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0|||
|A (== == =<br>=<br>pase<br>qeSee ee|||
|:|||
|:|||
|Legend:|||
|R = Readable bit|W = Writable bit|U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR|‘1’=Bitisset|‘0’=Bitiscleared<br>X=Bitisunknown|
bit 31-16 Unimplemented: Read as ‘0’
bit 31-0 PTGC1LIM<31:0>: PTG Counter ‘1’ Limit Register bits(")
These bits can be used to specify the loop count for the PTGJMPC1 step command, or as a general purpose counter limit register.
Note 1: These bits are read only when the module is executing step commands (PTGSTRT = 1).
renner eee e rereerence eee eee DS70005425A-page 262 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
## REGISTER 14-9: PTGADJ: PTG ADJUST REGISTER
|Bit<br>Bit|Bit|Bit|Bit|Bit<br>Bit|Bit|Bit|
|---|---|---|---|---|---|---|
|Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 |27/19/11/3 |26/18/10/2|||||| 25/17/9/1|| 24/16/8/0|
|aees|es|ee a||Ga|||
|||||||||
|Legend:|||||||
|R = Readable bit||W = Writable bit||U = Unimplemented bit, read as ‘0’|||
|-n=ValueatPOR||‘1’=Bitisset||‘0’=Bitiscleared|x=Bitisunknown||
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 PTGADJ<15:0>: PTG Adjust Register bits!)
Aregister that is used by the PTGADD step command to adjust the contents of one ofthe following registers, PTGTOLIM, PTGT1LIM, PTGCOLIM, PTGC1LIM, PTGSDLIM, and PTGLO. The PTGADD step command adds the contents of the PTGADJ<15:0> register to the target register, and then writes it back to the target register.
Note 1: These bits are read only when the module is executing step commands (PTGSTRT = 1).
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 263
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seman
## REGISTER 14-10: PTGLO: PTG LITERAL REGISTER
|Bit<br>Bit|Bit|Bit|Bit<br>Bit|Bit|Bit|Bit|
|---|---|---|---|---|---|---|
|Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 |27/19/11/3 | 26/18/10/2|||||| 25/17/9/1|| 24/16/8/0|
|ae|||||||
|a ee|eae|ee|a||||
|:|||||||
|:|||||||
|Legend:|||||||
|R = Readable bit||W = Writable bit|U = Unimplemented bit, read as ‘0’||||
|-n=ValueatPOR||‘1’=Bitisset|‘0’=Bitiscleared||x=Bitisunknown||
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 PTGLO<15:0>: PTG Literal Register bits')
This register holds the 16-bit literal value that is strobed when the PTGCTRL STRBLO command is executed.
Note 1: These bits are read only when the module is executing step commands (PTGSTRT = 1).
renner eee e rereerence eee eee DS70005425A-page 264 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
## REGISTER 14-11: PTGQPTR: PTG STEP QUEUE POINTER REGISTER
|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit|
|---|
|Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 |27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0|
|pst SP ee<br>pp SS<br>Se See ee<br>se SS ye<br>ee ee|
|i<br>a|
|Legend:|
|R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR<br>‘1’=Bitisset<br>‘0’=Bitiscleared<br>x=Bitisunknown|
## bit 31-5 Unimplemented: Read as ‘0’
bit 4-0 | PTGQPTR<4:0>: PTG Step Queue Pointer Register bits!) This register points to the currently active step command in the step queue.
Note 1: These bits are read only when the module is executing step commands (PTGSTRT = 1).
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 265
PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 14-12: PTGQUEn: PTG STEP QUEUE ‘n’ REGISTER (‘n’ = 0-7)
Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0 :
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
## bit 31-24 STEP[4n+3]<7:0>: STEP[4n+3] Command Byte bits()
- A queue location for storage of the STEP[4n+3] command byte.
- bit 23-16 STEP[4n+2]<7:0>: STEP[4n+2] Command Byte bits!)
- A queue location for storage of the STEP[4n+2] command byte.
- bit 15-8 STEP[4n+1]<7:0>: STEP[4n+1] Command Byte bits!
- A queue location for storage of the STEP[4n+1] command byte.
- bit 7-0 | STEP[4n]<7:0>: STEP[4n] Command Byte bits!) A queue location for storage of the STEP command byte.
Note 1: These bits are read only when the module is executing step commands (PTGSTRT = 1).
renner eee e rereerence eee eee DS70005425A-page 266 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
SSS
TABLE 14-2: PTG OUTPUT DESCRIPTION
Note: PTGO28 to PTGO31 are available on PPS. Refer to Table 13-3.
eee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 267
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DS70005425A-page 268
Preliminary Data Sheet © 2020 Microchip Technology Inc.
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- 15.0 TIMER1 The following modes are supported by Timer1: : :
- Note: This data sheet summarizes the ¢ Synchronous Internal Timer mode features of the PIC32MZ W1 family of - SynchTOS USESES IntTiS | SeeGated Tieerd eee devices. It is not intended to be a ¢ Synchronous External Timer mode comprehensive reference source. To « Asynchronous External Timer mode complement the information in this data Timer has the following key features: sheet, refer to Section 14. “Timers” (D$60001105) in the “PIC32 Family * Selectable clock prescaler Reference Manual”, which is available ¢ Timer operation during Sleep and Idle modes from the Microchip web site ¢ Fast bit manipulation using CLR, SET and (www.microchip.com/PIC32). registers
- PIC32MZ W1 device features one synchronous/ ° Raynchrenaus mee a mee a a be uses mitre mitre BOSC asynchronous 16-bit2 timer that can operate as a to function as a real-time.. clock free-running interval timer for various timing applications . ADS (CVD) event trigger trigger and counting external events. This timer can also be * Timer can be used as a wake wake up source from used with the low-power SOSC for real-time clock appliSleep mode cations.
- Selectable clock prescaler
- ¢ Timer operation during Sleep and Idle modes ¢ Fast bit manipulation using CLR, SET and INV registers
- ° Raynchrenaus mee a mee a a be uses mitre mitre BOSC to function as a real-time.. clock
- . ADS (CVD) event trigger trigger * Timer can be used as a wake wake up source from the Sleep mode
**==> picture [206 x 8] intentionally omitted <==**
**----- Start of picture text -----**<br>
FIGURE 15-1: TIMER1 BLOCK DIAGRAM<br>**----- End of picture text -----**<br>
**==> picture [432 x 244] intentionally omitted <==**
**----- Start of picture text -----**<br>
V ~ ee LLL<br>: Equal r 7<br>Trigger to ADC | 16-bit Comparator || TSYNC‘ ||<br>Reset TMR1 |<br>| a |<br>T1IF 0 L 4<br>o | 7-7 T TTT TT<br>TGATE TECS <p =<br>i ; ON<br>sosco [\“ 0 ><br>| | T1CK>1 Gate +) Prescaler<br>| /\ Syne | 410 1, 8, 64, 256<br>| NA | LPRC+2<br>SOBs xX | PB1_CLK<br>SOSCEN") - my 2<br>es | TCKPS<1:0><br>Note 1: The default state of the SOSCEN bit (OSCCON<1>) during a device Reset is controlled by the SOSCEN bit in<br>Configuration Word and CFGCON4.<br>**----- End of picture text -----**<br>
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 269
## seman
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**----- Start of picture text -----**<br>
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PIC32MZ W1 and WFI32E01 Family
## smn
## REGISTER 15-1: T1CON: TYPE A TIMER CONTROL REGISTER
|Bit|Bit|Bit|Bit|Bit|Bit<br>Bit<br>Bit<br>Bit|
|---|---|---|---|---|---|
|Range|| 31/23/15/7 | 30/22/14/6 |||29/21/13/5 | 28/20/12/4 |27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0|||
|=|pon|= ||sm|twos||Ro<br>|<br> [we [| CTeCSet>|
|°|[Freate[=||toxescte [=<br>tevnc [tes[=|||
|Legend:||||||
|R = Readable bit|||W = Writable bit||U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR|||‘1’=Bitisset||‘0’=Bitiscleared<br>x=Bitisunknown|
bit 31-16 Unimplemented: Read as ‘0’
- bit 15 ON: TMR1 bit 1 = TMR71 is enabled 0 = TMR71 is disabled
- bit 14 Unimplemented: Read as ‘0’ bit 13 SIDL: Stop in Idle Mode bit 1 = Discontinue operation when device enters Idle mode 0 = Continue operation even in Idle mode
- bit 12 TWDIS: Asynchronous Timer Write Disable bit 1 = Writes to TMR1 are ignored until pending write operation completes 0 = Back-to-back writes are enabled (legacy asynchronous timer functionality)
- bit 11 TWIP: Asynchronous Timer Write in Progress bit In Asynchronous Timer mode: 1 = Asynchronous write to TMR1 register in progress 0 = Asynchronous write to TMR1 register complete In Synchronous Timer mode: This bit is read as ‘0’.
- bit 10 Unimplemented: Read as ‘0’ bit 9-8 TECS<1:0>: TMR1 Extended Clock Select bits 11= Reserved 10=LPRC 01= T1CK pin 00= SOSC
- bit 7 TGATE: Timer Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled
- bit 6 Unimplemented: Read as ‘0’
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 271
## PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 15-1: T1CON: TYPE A TIMER CONTROL REGISTER (CONTINUED)
- bit 5-4 TCKPS<1:0>: Timer Input Clock Prescale Select bits
- 11 = 1:256 prescale value
- 10 = 1:64 prescale value
- 01 = 1:8 prescale value
- 00 = 1:1 prescale value
- bit 3 Unimplemented: Read as ‘0’ bit 2 TSYNC: Timer External Clock Input Synchronization Selection bit When TCS = 1:
- 1 = External clock input is synchronized
- 0 = External clock input is not synchronized When TCS = 0: This bit is ignored.
- bit 1 TCS: Timer Clock Source Select bit 1 = External clock from TECS 0 = Internal peripheral clock
- bit 0 Unimplemented: Read as ‘0’
renner eee e rereerence eee eee DS70005425A-page 272 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
- 16.0 TIMER2/3, TIMER4/5, AND Three 32-bit synchronous timers are available by TIMERG6/7 combining Timer2 with Timer3, Timer4 with Timer5, Timer6 with Timer7.
- Note: This data sheet summarizes the features The 32-bit timers can operate in one of three modes: of the PIC32MZ W1 family of devices. It is a: : :
- not intended to be a comprehensive refer* Synchronous Internal 32-bit. Timer mode. ence source. To complement the informa¢ Synchronous Internal act Gulsad Timer mode tion in this data sheet, refer to Section 14. * Synchronous External 32-bit Timer mode “Timers” (DS60001105) of the “P/C32 These timers have the following key features: Family Reference Manual”, which is avail: . :
- able from the Microchip web site * Selectable. clock; prescaler; (www.microchip.com/PIC32). * Timers operational during CPU Idle mode * Time base for input capture and output compare
- synchronous 16-bit timers (default) that can operate * ADC event trigger (Timer3 and Timer5 only) as @ free-free-runninging intinlerval | tiamer ffor variousi timitiming + Fast bit. manipulation: : using' CLR, SET, and INV applications and counting external events. . registers
- The following modes are supported: * Synchronous Internal 16-bit Timer mode * Synchronous Internal 16-bit Gated Timer mode ¢ Synchronous External 16-bit Timer mode FIGURE 16-1: TIMER2 THROUGH TIMER7 BLOCK DIAGRAM (16-BIT) V
- Equal fi
- °
- TXIFx EventventFlFlag _— | <p
- 1 a TGATE
- TGATE es ON
- TxCK xX > x1 Syne 1,2, 4, 8, 16,
- eet Prescaler
- PB1_CLK oy ad00 32, 64, 256 3
- TCKPS
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 273
## PIC32MZ W1 and WFI32E01 Family
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seman<br>**----- End of picture text -----**<br>
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**----- Start of picture text -----**<br>
FIGURE 16-2: TIMER2/3, TIMER4/5, AND TIMER6/7, BLOCK DIAGRAM (32-BIT)<br>Reset>| tury”! Tyrx?<br>oe<br>r q MS Half Word {) Ls Half Word<br>| ADC Event Trigger Equal 32-bit Comparator<br>a<br>PRy) ' pRx(t)<br>TyIF Event Flag!) ° _— |<br><p<br>1 - TGATE<br>TGATE 1s<br>ON<br>Txck(") S<] => xi<br>reeGate 1,Prescaler2,4, 8, 16,<br>PB1_CL a 1000 32, 64, 256<br>3<br>TCKPS<br>Note 1: In this diagram, ‘x’ represents Timer2, 4, or 6, and ‘y’ represents Timer3, 5, or 7.<br>**----- End of picture text -----**<br>
renner eee e rereerence eee eee DS70005425A-page 274 Preliminary Data Sheet © 2020 Microchip Technology Inc.
smn
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## PIC32MZ W1 and WFI32E01 Family
## seman
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PIC32MZ W1 and WFI32E01 Family
## smn
## REGISTER 16-1: TxCON: TYPE B TIMER CONTROL REGISTER (x = 2-7)
|Bit|Bit|Bit|Bit|Bit<br>Bit<br>Bit<br>Bit<br>Bit|
|---|---|---|---|---|
|Range|31/23/15/7 | 30/22/14/6||| 29/21/13/5 | 28/20/12/4 |27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0||
|ae||=DO|||
|° _[Freare™||||rexpscaost)|[re<br>tos|
|Legend:|||||
|R = Readable bit|||W = Writable bit|U = Unimplemented bit, read as ‘0’|
|-n=Value|atPOR||‘1’=Bitisset|‘0’=Bitiscleared<br>x=Bitisunknown|
|bit 31-16|Unimplemented: Read as ‘0’|
|---|---|
|bit 15|ON: Timer On bit!)|
||1 = Module is enabled|
||0 = Module is disabled|
|bit 14|Unimplemented: Read as ‘0’|
|bit 13|SIDL: Stop in Idle Mode bit(?)|
||1 = Discontinue operation when device enters Idle mode|
||0 = Continue operation even in Idle mode|
|bit 12-8|Unimplemented: Read as ‘0’|
|bit 7|TGATE: Timer Gated TimeAccumulation Enable bit")|
||When TCS = 1:|
||This bit is ignored and is read as ‘0’.|
||When TCS= 0:|
||1 = Gated time accumulation is enabled|
||0 = Gated time accumulation is disabled|
|bit6-4|| TCKPS<2:0>: Timer Input Clock Prescale Select bits!)|
||111 = 1:256 prescale value|
||110 = 1:64 prescale value|
||101 = 1:32 prescale value|
||100 = 1:16 prescale value|
||011 = 1:8 prescale value|
||010 = 1:4 prescale value|
||001 = 1:2 prescale value|
||000 = 1:1 prescale value|
|bit 3|T32: 32-Bit Timer Mode Select bit)|
||1 = Odd numbered and even numbered timers form a 32-bit timer|
||0=Oddnumberedandevennumberedtimersformseparate16-bittimers|
- bit 2 Unimplemented: Read as ‘0’ Note 1: While operating in 32-bit mode, this bit has no effect for odd numbered timers (Timer1, Timer3, Timer5, and Timer7). All timer functions are set through the even numbered timers.
- 2: While operating in 32-bit mode, this bit must be cleared on odd numbered timers to enable the 32-bit timer in Idle mode.
- 3: This bit is available only on even numbered timers (Timer2, Timer4, and Timer6).
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 277
## PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 16-1: TxCON: TYPE B TIMER CONTROL REGISTER (x = 2-7) (CONTINUED)
- bit 1 TCS: Timer Clock Source Select bit!) 1 = External clock from TxCK pin 0 = Internal peripheral clock
- bit 0 Unimplemented: Read as ‘0’
- Note 1: While operating in 32-bit mode, this bit has no effect for odd numbered timers (Timer1, Timer3, Timer5, and Timer7). All timer functions are set through the even numbered timers.
- 2: While operating in 32-bit mode, this bit must be cleared on odd numbered timers to enable the 32-bit timer in Idle mode.
- 3: This bit is available only on even numbered timers (Timer2, Timer4, and Timer6).
renner eee e rereerence eee eee DS70005425A-page 278 Preliminary Data Sheet © 2020 Microchip Technology Inc.
## PIC32MZ W1 and WFI32E01 Family
## smn 17.0 DEADMAN TIMER (DMT) The DMT DMT is typically used in mission critical and safety
17.0 DEADMAN TIMER (DMT) The DMT DMT is typically used in mission critical and safety critical applications, where any single failure of the Note: This data sheet summarizes the features software functionality and sequencing must be of the PIC32MZ W1 family of devices. It is detected. not intended to be a comprehensive The DMT is enabled by setting the reference source. To complement the CFGCON2.DMTEN Configuration register bit or information in this data sheet, refer to DMTCON.ON register bit. Adevice Reset is required to Section 9. “Watchdog, Deadman, and disable the DMT Power-up Timers” (DS60001114) in the Oo “PIC32 Family Reference Manual”, which DMT has the following key features: is available from the Microchip web site * 32-bit configurable count-limit based upon (www.microchip.com/PIC32). counting instructions fetched The primary function of DMT is to reset the processor ° dcahmcian asin Se ee ; in the event of a software malfunction. The DMT is a * Two instruction sequence to clear timer free-running instruction fetch timer, which is clocked * 32-bit configurable window to clear timer whenever an instruction fetch occurs until a count ¢ Timer “instruction fetched” counter may be read match occurs. Instructions are not fetched when the Figure 17-1 shows the block diagram of the DMT modprocessor is in Sleep mode. ule The DMT consists of a 32-bit counter with a time-out count match value as specified by the DMTCNT[4:0] bits in the CFGCON2 Configuration register.
**==> picture [195 x 8] intentionally omitted <==**
**----- Start of picture text -----**<br>
FIGURE 17-1: DMT BLOCK DIAGRAM<br>**----- End of picture text -----**<br>
**==> picture [443 x 350] intentionally omitted <==**
**----- Start of picture text -----**<br>
Improper Sequence Flag ) ) |)<br>ON<br>Instruction Fetched Strobe<br>S|} ie<br>a<br>Proper Clear Sequence Flag )<br>_ )) DMT Count Reset Load )) | DMT Event<br>to NMI()<br>System Reset d><br>Window Interval Open<br>Note 1: DMT Max Count is controlled by the DMTCNT[4:0] bits in the CFGCON2 Configuration register.<br>2: DMT Window Interval is controlled by the DMTINTV[2:0] bits in the CFGCON2 Configuration register.<br>3: Refer to 7.0 “Resets” for more information.<br>**----- End of picture text -----**<br>
**==> picture [459 x 19] intentionally omitted <==**
**----- Start of picture text -----**<br>
reer reer rereeee eee ee<br>© 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 279<br>**----- End of picture text -----**<br>
## seman
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renner eee e rereerence eee eee DS70005425A-page 280 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
|REGISTER|REGISTER|17-1:<br>DMTCON: DEADMAN TIMER CONTROL REGISTER|17-1:<br>DMTCON: DEADMAN TIMER CONTROL REGISTER|17-1:<br>DMTCON: DEADMAN TIMER CONTROL REGISTER|||
|---|---|---|---|---|---|---|
|Bit Range<br>9||Bit<br>Bit<br>Bit<br>Bit<br>31/23/15/7 |30/22/14/6 |29/21/13/5|28/20/12/4|Bit<br>Bit<br>Bit<br>Bit<br> |27/19/11/3|26/18/10/2 | 25/17/9/1 | 24/16/8/0||||
|||Poo=<br>| = | = | =|||=<br>| = | =<br>[|||= ||
|||a<br>ee ee es|||||
||||ON|||||
|Legend:|||y = Value set from Configuration bits on|||POR|
|R = Readable bit<br>W = Writable bit|||U =|Unimplemented bit, read as ‘0’|||
|-n = Value|at|POR<br>‘1’ = Bit is set|‘0’ =|Bit is cleared|x = Bit is unknown||
|bit 31-16||Unimplemented: Read as ‘0’|||||
|bit 15||ON: DMT Module Enable bit!)|||||
|||1 = DMT module is enabled|||||
|||0 = DMT module is disabled|||||
|||The Reset value of this bit is determined by the setting of the DMTEN bit (CFGCON2<3>).|||||
|bit 13-0||Unimplemented: Read as ‘0’|||||
|Note<br>1:|This bit only has control when DMTEN (CFGCON2<3>) = 0.||||||
|REGISTER||17-2:<br>DMTPRECLR: DEADMAN TIMER PRECLEAR REGISTER|||||
|Bit Range<br>g||Bit<br>Bit<br>Bit<br>Bit<br>31/23/15/7 |30/22/14/6 |29/21/13/5|28/20/12/4|Bit<br>Bit<br>Bit<br>Bit<br> |27/19/11/3|26/18/10/2 | 25/17/9/1 | 24/16/8/0||||
|ee <br>pose||ee ee ee<br>ee<br> YE ES Ee<br>EE EEEES|||||
|:|||||||
|Legend:|||||||
|R = Readable bit<br>W = Writable bit|||U =|Unimplemented bit, read as ‘0’|||
|-n = Value|at|POR<br>‘1’ = Bit is set|‘0’ =|Bit is cleared|x = Bit is unknown||
|bit 31-16||Unimplemented: Read as ‘0’|||||
|bit 15-8||STEP1<7:0>: Preclear Enable bits|||||
|||01000000 = Enables the DMT preclear (Step 1)|||||
|||All other write patterns = Set BAD1 flag.|||||
|||These bits are cleared when a DMT Reset event occurs.||STEP1<7:0> is also|cleared if the||
|||STEP2<7:0> bits are loaded with the correct value in the||correct sequence.|||
|bit7-0||Unimplemented:Readas‘0’|||||
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 281
PIC32MZ W1 and WFI32E01 Family
## seman
|REGISTER 17-3:|DMTCLR: DEADMAN TIMER CLEAR REGISTER||
|---|---|---|
|Bit Range<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>9<br>31/23/15/7 | 30/22/14/6 |29/21/13/5|28/20/12/4 |27/19/11/3|26/18/10/2||Bit<br>Bit<br> | 25/17/9/1 | 24/16/8/0|
|a<br>pote eee ee<br>a<br>eeee eeer||ee|
|-<br>||||
|Legend:|||
|R = Readable bit|W = Writable bit<br>U = Unimplemented bit,|read as ‘0’|
|-n=ValueatPOR|‘1’=Bitisset<br>‘0’=Bitiscleared|x=Bitisunknown|
bit 31-8 Unimplemented: Read as ‘0’ bit 7-0 STEP2<7:0>: Clear Timer bits 00001000 = Clears STEP1<7:0>, STEP2<7:0> and the DMT if, and only if, preceded by correct loading of STEP1<7:0> bits in the correct sequence. The write to these bits may be verified by reading DMTCNT and observing the counter being reset.
All other write patterns = Set BAD2 bit, the value of STEP1<7:0> will remain unchanged, and the new value being written STEP2<7:0> will be captured. These bits are also cleared when a DMT Reset event occurs. If the STEP2<7:0> bits are written without preceding with a correct loading of STEP1<7:0> bits, the BAD1 bit is set.
renner eee e rereerence eee eee DS70005425A-page 282 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
**==> picture [455 x 178] intentionally omitted <==**
**----- Start of picture text -----**<br>
REGISTER 17-4: DMTSTAT: DEADMAN TIMER STATUS REGISTER<br>Bit Range Bit Bit Bit Bit Bit Bit Bit Bit<br>9 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0<br>ee ee ee ee ee ee ee<br>ee ee ee ee ee<br>ps Se eo ee<br>-© [sant [ab Pomrevenr[CNP<br>Legend: HC = Hardware Cleared HS = Hardware Set<br>R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’<br>-n = Value at POR ‘17’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown<br>**----- End of picture text -----**<br>
- bit 31-8 Unimplemented: Read as ‘0’ bit 7 BAD1: Bad STEP1<7:0> Value Detect bit 1 = Incorrect STEP1<7:0> value or out of sequence write to STEP2<7:0> is detected 0 = Incorrect STEP1<7:0> value is not detected
- bit 6 BAD2: Bad STEP2<7:0> Value Detect bit 1 = Incorrect STEP2<7:0> value is detected
- 0 = Incorrect STEP2<7:0> value is not detected
- bit 5 DMTEVENT: DMT Event bit
- 1 = DMT event is detected (counter expired or bad STEP1<7:0> or STEP2<7:0> value is entered prior to counter increment)
- 0 = DMT even is not detected
- bit 4-1 Unimplemented: Read as ‘0’ bit 0 WINOPN: DMT Clear Window bit 1 = DMT clear window is open 0 = DMT clear window is not open
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 283
PIC32MZ W1 and WFI32E01 Family
seman
REGISTER 17-5: DMTCNT: DEADMAN TIMER COUNT REGISTER
|Bit Range<br>Bit<br>9<br>31/23/15/7|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br> |30/22/14/6 |29/21/13/5 |28/20/12/4|27/19/11/3 |26/18/10/2 | 25/17/9/1 | 24/16/8/0|
|---|---|
|| size<br>RD LR)<br>ee OU<br>16<br>[Ro<br>[| Ro | Ro<br>[| Ro<br>[| Ro [ RO [ RO | RO |<br>:ee<br>v7<br>~ RO [ Ro | Ro [ Ro<br>[| RO | RO | RO<br>[| RO |||
|Legend:||
|R = Readable bit|W = Writable bit<br>U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR|‘1’=Bitisset<br>‘0’=Bitiscleared<br>x=Bitisunknown|
bit 31-0 COUNTER<31:0>: Read current contents of DMT counter
REGISTER 17-6: DMTPSCNT: POST STATUS CONFIGURE DMT COUNT STATUS REGISTER Bit Range Bit Bit Bit Bit Bit Bit Bit Bit g 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0 a | ase | ROL Re | eee Ee eg OL RO ROT ROT ROT ROT ROT RO TRO pro [RO Ree | ed ed Legend: y = Value set from Configuration bits on POR R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 PSCNT<31:0>: DMT Instruction Count Value Configuration Status bits This is always the value of the DMTCNT<4:0> bits in the CFGCON2 Configuration register.
_————————————OOOO DS70005425A-page 284 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
|REGISTER|17-7:<br>DMTPSINTV: POST STATUS CONFIGURE DMT INTERVAL STATUS REGISTER|
|---|---|
|Bit Range<br>9|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>31/23/15/7 |30/22/14/6 |29/21/13/5|28/20/12/4 |27/19/11/3|26/18/10/2 | 25/17/9/1 | 24/16/8/0|
|—————————————<br>o16<br>[RO<br>[| Ro | Ro<br>[| Ro<br>[| RO [ RO<br>[| RO<br>[| RO |<br>:||
|| ise <br>pro|| RO<br>ee<br> [RR RO<br>ee|
|Legend:|y = Value setfrom Configuration bits on POR|
|R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’||
|-n=Valueat|POR<br>‘1’=Bitisset<br>‘0’=Bitiscleared<br>x=Bitisunknown|
bit 31-0 PSINTV<31:0>: DMT Window Interval Configuration Status bits This is always the value of the DMTINTV<2:0> bits in the CFGCON2 Configuration register.
OOOO___ © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 285
PIC32MZ W1 and WFI32E01 Family
DS70005425A-page 286
Preliminary Data Sheet © 2020 Microchip Technology Inc.
- PIC32MZ W1 and WFI32E01 Family
- smn 18.0 WATCHDOG TIMER (WDT) The key features of the WDT module are: . .
- Note: ofThis thedataPIC32MZsheet W1summarizesfamily of devices.the featuresIt is *. ConfigurationUp BMGto 32Oe COREEfi or softwareTADble tiEecontrolleder1 PeEAesperiod not intended to be a comprehensive ¢ Can wake the device from Sleep or Idle mode reference source. To complement the ¢ Independent Run and Sleep mode counters information in this data sheet, refer to Sec¢ WDT may use alternate clock source and tion 9. “Watchdog, Deadman, and postscaler for Run mode counter Power-up Timers” (DS60001114) in the * Independent 5-bit postscalers for Run and Sleep “PIC32 Family Reference Manual”, which mode counters is available from the Microchip web site = Geyrreeses erescberdiene: exesitiesl (www.microchip.com/PIC32). * Two clock sources
- When enabled, the WDT operates from the internal ¢ Windowed WDT LPRC clock source and can be used to detect system Note: When the CPU is running on the same software malfunctions by resetting the device if the WDT ;is not cleared periodicallyii :in software. Various. clock or clock frequency as the WDT WDT time-out: periods. can be selected using. the WDT (LPRC), the lowest pre-scale values: may postscaler.[The][WDT][can][also][be][used][to][wake][the] not allow the CPU to have: enough. time to . reset the WDT before it expires.
- device from Sleep or Idle mode. FIGURE 18-1: WDT BLOCK DIAGRAM PB1_CLKLPRC es Clock
- WDTCLRKEY<15:0> = 0x5743 32 ON
- Wake B | 0 at WDT Event —ON WDT Counter Reset 1 _ | NV
- Reset Event Power Save
RUNDIV<4:0> (WDTCON<12:8>)
Note 1: Refer to 7.0 “Resets” for more information.
## 18.1 WDT Configuration
The WDT is configured using the following config register bits/fields:
- Window size (CFGCON2.FWINSZ[1:0])
- ¢ Windowing disable (CFGCON2.WINDIS)
- ¢ Post-scaler selection (CFGCON2.WDTPS[4:0])
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 287
PIC32MZ W1 and WFI32E01 Family
## seman
## 18.2 WDT Control Registers
TABLE 18-1: WDT REGISTER MAP
**==> picture [456 x 316] intentionally omitted <==**
**----- Start of picture text -----**<br>
g is<br>2 ro o 2}<br>oF Lo 2 2<br><3} 66 |e 4<br>3 L£ e2 = 31/15| 30/14 | 29/13 |28/12| 27/11 |26/10] 25/9 | 24/8 | 23/7 | 22/6 | 21/5 | 20/4 | 19/3 | 18/2 | 17/1 16/0 a<x<br>&<br>eT sol ON] —[— |] RUNDWeao> «| — | — |] — | — ] — | — | — WoTwinenfnx00|<br>Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.<br>Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and OxC, respectively. See<br>13.0 “I/O Ports” for more information.<br>REGISTER 18-1: WDTCON: WATCHDOG TIMER CONTROL REGISTER<br>Bit Bit Bit Bit Bit Bit Bit Bit Bit<br>Range | 31/23/15/7 | 30/22/14/6 |29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 24/16/8/0<br>:<br>:<br>fon |RN<br>—t = [| = | = | = | = | = [= {| worwnen |<br>Legend: y = Values set from Configuration bits on POR<br>R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’<br>-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown<br>**----- End of picture text -----**<br>
REGISTER 18-1: WDTCON: WATCHDOG TIMER CONTROL REGISTER
## bit 31-16 WDTCLRKEY<16:0>: Watchdog Timer Clear Key bits
To clear the WDT to prevent a time-out, software must write the value 0x5743 to this location using a single 16-bit write. bit15 ON: Watchdog Timer Enable bit') 1 = WDT is enabled 0 = WDT is disabled bit 14-13 Unimplemented: Read as ‘0’ bit 12-8 RUNDIV<4:0>: Watchdog Timer Postscaler Value bits On Reset, these bits are set to the values of the WDTPS<4:0> Configuration bits in CFGCON2. bit 7-1 Unimplemented: Read as ‘0’ bit 0 WDTWINEN: Watchdog Timer Window Enable bit 1 = Enable windowed WDT 0 = Disable windowed WDT
Note 1: This bit only has control when the WDTEN bit (CFGCON2<23>) = 0.
renner eee e rereerence eee eee DS70005425A-page 288 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
## 19.0 INPUT CAPTURE
- -
- Note: This data sheet summarizes the features of the PIC32MZ W1 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 15. “Input Capture” (DS60001122) of the “PIC32 Family Reference Manual”, which _ is available(SsaaLetathe oP) web site
- The input capture module is useful in applications requiring frequency (period) and pulse measurement. . .
- This Time moduleBase registerscaptureswhenthe 16-bitan eventvalueoccursof theatselectedthe ICx pin.
- The* Captureinput captureevery rising_moduleandhasfalling the. followingedge features: * Capture every 4" and 16" rising edge ¢ Capture timer values based on internal or external clocks
- ¢ TMR2 or TMR3 time-based selection
- Device wakes up from capture pin during Sleep and Idle modes
- + Interrupt on input capture event ¢ 4-word FIFO buffer for capture values; interrupt optionally generated after 1, 2, 3, or 4 buffer locations are filled
- ¢ Input capture can also be used to provide additional sourcesN of external. interrupts
- * Capability to trigger PTG
**==> picture [252 x 8] intentionally omitted <==**
**----- Start of picture text -----**<br>
FIGURE 19-1: INPUT CAPTURE BLOCK DIAGRAM<br>**----- End of picture text -----**<br>
**==> picture [417 x 305] intentionally omitted <==**
**----- Start of picture text -----**<br>
|<br>|| Specified/Every| FEDGE ICM<2:0>.<br>Edge Mode 110 |<br>| AX |<br>| PB3_CLK<br>| Prescaler Mode 101 | timerx(@ Timery@)<br>(16th Rising Edge) ee 2 —— L —4<br>| £<br>| C32/ICTMR MZ u |<br>Prescaler Mode 100 |<br>| (4th Rising Edge) I )<br>FIFO Control a<br>| ft Capture Event [socom To CPUIPTG<br>| Rising Edge Mode 011 |<br>| icx() Kx]“ ft J |<br>| P|<br>l Falling Edge Mode} 010 rT FIFO<br>| x [<br>ICI<1:0> |<br>| Edge Detection 001 ICM<2:0> |<br>| Mode |<br>| f xX IN | Set Flag ICxIF()<br>| Wake-upSleep/idieMode (In IFSx Register)<br>| ra |<br>bee eeeeee eee eee eee<br>Note 1: An‘x’ina signal, register or bit name denotes the number of the capture channel.<br>2: See Table 19-1 for TimerX and TimerY selections.<br>**----- End of picture text -----**<br>
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 289
PIC32MZ W1 and WFI32E01 Family
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The timer source for each input capture module depends on the setting of the IC_ACLK bit in the CFGCONDO register. The available configurations are shown in Table 19-1.
When IC_ACLK= 0, all ICAP may choose between the same 2 timer sources. When IC_ACLK = 1, groups of ICAP may choose between a variation of timer sources.
TABLE 19-1: ICAP CLOCK SOURCES
|eee|.<br>eee|X(MSB)<br>clock/data|Y(MSB)<br>clock/data|
|---|---|---|---|
|jOSSCSC~sICAPT-SSCTWRSYTMR||||
|1|ICAP 1-2|TMR5|TMR4|
||ICAP3-4|TMR7|TMR6|
renner eee e rereerence eee eee DS70005425A-page 290 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
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## PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 19-1: ICXCON: INPUT CAPTURE x CONTROL REGISTER
|Bit|Bit<br>Bit<br>Bit|Bit||Bit|Bit|Bit|Bit|
|---|---|---|---|---|---|---|---|
|Range|31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 |27/19/11/3 |26/18/10/2 ||||||25/17/9/1 | 24/16/8/0||
||a<br>ee<br>ee|||||ee|ee||
||hE<br>EE EE<br>Ee||Ee||ee|ee<br>eee||
|| 70|[on [= | so [| <br>| RA}<br>dno}|— | <br> 9||— ||— |Fenée[ c32__<br>de Lo|||
|Legend:||||||||
|R = Readable bit<br>W = Writable bit|||U =|Unimplemented bit||||
|-n = BitValue at POR: (‘0’, ‘1’,<br>x<br>= unknown)|||P =|Programmable bit<br>r = Reserved bit||||
|bit 31-16|Unimplemented: Read as ‘0’|||||||
|bit 15|ON: Input Capture Module Enable bit|||||||
||1 = Module is enabled|||||||
||0 = Disable and Reset module, disable clocks, disable||interrupt generation and allow SFR modifications|||||
|bit 14|Unimplemented: Read as ‘0’|||||||
|bit 13|SIDL: Stop in Idle Control bit|||||||
||1 = Halt in CPU Idle mode|||||||
||0 = Continue to operate in CPU Idle mode|||||||
|bit12-10|Unimplemented: Read as ‘0’|||||||
|bit 9|FEDGE: First Capture Edge Select bit (only|used in mode||6, ICM<2:0> = 110)||||
||1 = Capture rising edge first|||||||
||0 = Capture falling edge first|||||||
|bit 8|C32: 32-bit Capture Select bit|||||||
||1 = 32-bit timer resource capture|||||||
||0 = 16-bit timer resource capture|||||||
|bit 7|ICTMR: Timer Select bit (Does not affect timer selectionwhen C32 (ICXCON<8>)|||||is ‘1’)()||
||0 = Timery is the counter source for capture|||||||
||1 = Timerx is the counter source for capture|||||||
|bit 6-5|ICI<1:0>: Interrupt Control bits|||||||
||11 =<br>Interrupt on every fourth capture event|||||||
||10 =<br>Interrupt on every third capture event|||||||
||01 =<br>Interrupt on every second capture event|||||||
||00 =<br>Interrupt on every capture event|||||||
|bit 4|ICOV: Input Capture Overflow Status Flag bit (read-only)|||||||
||1 = Input capture overflow is occurred|||||||
||0 = No input capture overflow is occurred|||||||
|bit 3|ICBNE: Input Capture Buffer Not Empty Status bit (read-only)|||||||
||1 = Input capture buffer is not empty; at least one more capture value can be read|||||||
||0 = Input capture buffer is empty|||||||
|bit 2-0|ICM<2:0>: Input Capture Mode Select bits|||||||
||111 =<br>Interrupt-Only mode (only supported|while in Sleep||mode or Idle mode)||||
||110 = Simple Capture Event mode — every|edge, specified edge first and every edge thereafter||||||
||101 = Prescaled Capture Event mode — every sixteenth rising edge|||||||
||100 = Prescaled Capture Event mode — every fourth rising edge|||||||
||011 = Simple Capture Event mode — every|rising edge||||||
||010 = Simple Capture Event mode — every|falling edge||||||
||001 = Edge Detect mode — every edge (rising and falling)|||||||
||000=<br>InputCapturemoduleisdisabled|||||||
Note 1: Refer to Table 19-1 for TimerX and TimerY selections.
renner eee e rereerence eee eee DS70005425A-page 292 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
## 20.0 OUTPUT COMPARE
- OUTPUT COMPARE The output compare module has the following features: . .
- Note: This data sheet summarizes the features ¢ Multiple output compare modules in a device of the PIC32MZ W1 device. It is not . Pprogramme islee treinterrupt t generationti on compare intended to be a comprehensive refera ence source. To complement the informa* Single and Dual Compare modes tion in this data sheet, refer to Section 16. ¢ Single and continuous output pulse generation “Output Compare” (DS60001111) in the * Glitchless Pulse Width Modulation (PWM) mode PIC32 Family Reference Manual”, which - with fault protection input
- is available from the Microchip web site - oo : :
- (www.microchip.com/PIC32). - without fault protection input ¢ Interrupt on output compare/PWM event
- output compare module is used to generate a ¢ Interrupt on PWMfault detect condition pulse or a a train of pulses pulses in response to selected * Programmable selection of 16-bit or 32-bit time
- base events. bases
The output compare module is used to generate a single pulse or a a train of pulses pulses in response to selected time base events.
For all modes of operation, the output compare module * Can operate from either of two available 16-bit compares the values stored in the OCxR and/or the time bases or a single 32-bit time base OCxRS registers to the value in the selected timer. * ADC event trigger When a match occurs, the output compare module * Capability to triqger PTG generates an event based on the selected mode of P y 99 operation. Operating modes are determined by setting the OCxM bits. Note that the OCxM bits must be switched through the OCxM = 000, before the next mode is selected.
## FIGURE 20-1: OUTPUT COMPARE MODULE BLOCK DIAGRAM
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cs|<br>| Set Flag bit OCxIF() |<br>|Trigger to PTG/Trigger to ADC |<br>|| , xMW.v |<br>\/ (1) fe) SA |<br>a|| ———/L | cos utput OutputEnableS$ _Q| OutputeeeLogic Enable (1) ||<br>OCFA<br>| Mode Select SZ |<br>| ZA oes |<br>| fi OCTSEL OCFCOCFD |<br>| |<br>16 16<br>| |<br>pO _ — _— — ee eee eee<br>PBCLK3 Timerx(2) TimerY (2) Timerx'2)— TimerY(?)<br>Rollover Rollover<br>Note 1: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels,<br>1 through 4.<br>2: Refer to Table 20-1 for TimerX and TimerY selections.<br>reer reer rereeee eee ee<br>© 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 293<br>**----- End of picture text -----**<br>
PIC32MZ W1 and WFI32E01 Family seman
The timer source for each output compare module depends on the setting of the OC_ACLK bit in the CFGCONDO register. The available configurations are shown in Table 20-1.
When OC_ACLK = 0, all OCMP may choose between the same 2 timer sources. When OC_ACLK= 1, groups of OCMP may choose between a variation of timer sources.
TABLE 20-1: OCMP CLOCK SOURCES
||Oc_ACLK|OCMP Instance|X(MSB)<br>Clock/Data|Y(MSB)<br>Clock/Data|
|---|---|---|---|---|
|jo<br>1|SSCSC™~SCPTACR<br>OCMP1-2<br>TMRS5<br>TMR4||||
|||OCMP3-4|TMR7|TMR6|
OOOO___ DS70005425A-page 294 Preliminary Data Sheet © 2020 Microchip Technology Inc.
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PIC32MZ W1 and WFI32E01 Family
## seman
|REGISTER 20-1:|OCxCON: OUTPUT COMPARE ‘x’CONTROL REGISTER (x=1-4)|OCxCON: OUTPUT COMPARE ‘x’CONTROL REGISTER (x=1-4)|
|---|---|---|
|Bit<br>Bit|Bit<br>Bit<br>Bit|Bit<br>Bit<br>Bit<br>Bit|
|Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 |27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0|||
|— foo|[| = | sm |<br>=~|{| = |<br>=~<br>[| =<br>[| = ||
|°<br>(P=TT|TT =<br>cc<br>ocr|fects]CMa|
|Legend:|||
|R = Readable bit|W = Writable bit|U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR|‘1’=Bitisset|‘0’=Bitiscleared<br>x=Bitisunknown|
- bit 31-16 Unimplemented: Read as ‘0’
- bit 15 ON: Output Compare Peripheral On bit 1 = Output compare peripheral is enabled 0 = Output compare peripheral is disabled
- bit 14 Unimplemented: Read as ‘0’ bit 13 SIDL: Stop in Idle Mode bit 1 = Discontinue operation when CPU enters Idle mode 0 = Continue operation in Idle mode
- bit12-6 Unimplemented: Read as ‘0’ bit 5 OC32: 32-bit Compare Mode bit 1 = OCxR<31:0> and/or OCxRS<31:0> are used for comparisons to the 32-bit timer source 0 = OCxR<15:0> and OCxRS<15:0> are used for comparisons to the 16-bit timer source
- bit 4 OCFLT: PWM Fault Condition Status bit") 1 = PWM Fault condition has occurred (cleared in hardware only) 0 = No PWM Fault condition has occurred
- bit 3 OCTSEL: Output Compare Timer Select bit'2) 1 = TimerY is the clock source for this output compare module 0 = TimerX is the clock source for this output compare module
- bit 2-0 OCM<2:0>: Output Compare Mode Select bits 111 = PWM mode on OCx; fault pin is enabled 110 = PWM mode on OCx; fault pin is disabled 101 = Initialize OCx pin low; generate continuous output pulses on OCx pin 100 = Initialize OCx pin low; generate single output pulse on OCx pin 011 = Compare event toggles OCx pin 010 = Initialize OCx pin high; compare event forces OCx pin low 001 = Initialize OCx pin low; compare event forces OCx pin high 000 = Output compare peripheral is disabled but continues to draw current
- Note 1: This bit is only used when OCM<2:0> = ‘111’. It is read as ‘0’ in all other modes.
- 2: Refer to Table 20-1 for TimerX and TimerY selections.
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PIC32MZ W1 and WFI32E01 Family<br>smn<br>21.0 SERIAL PERIPHERAL The following are key features of the the SPI module:<br>INTERFACE (SPI) AND * Native 32-bit peripheral bus architecture, scalable<br>INTER-IC SOUND (I7S) toeSeS 16-bittete ae and 8-bita eea ee ee<br>**----- End of picture text -----**<br>
- The following are key features of the the SPI module: * Native 32-bit peripheral bus architecture, scalable toeSeS 16-bittete ae and 8-bita eea ee ee
- « Master and Slave mode support
**==> picture [434 x 593] intentionally omitted <==**
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Note: This data sheet summarizes the features * Full-duplex operation with 8/16/32-bit<br>of the PIC32MZ W1 device. It is not communication<br>intended to be a comprehensive refer- * Status bit to indicate activity of SPI<br>ence source. To complement the informa- ¢ Four different clock formats<br>tion in this data sheet, refer to Section 23. + Interrupt event on every byte/half-word/word<br>“Serial Peripheral Interface (SPI)” received<br>(DS60001106) in the “PIC32 Family Refer- * Separate transmit and receive buffer events<br>ence Manual”, which is available from the + Framed SPI protocol support<br>a web site (www.microchip.com/ * DMA support<br>) ¢« SDO pin disable option<br>SPI/I2S module is a a synchronous serial interface that is * 16 byte deep enhanced buffer operation<br>useful for communicating communicating with external peripherals and * Persistent Interrupt events based on internal<br>other MCU devices, as well as digital audio devices. status bits<br>These peripheral devices may be Serial EEPROMs, *« Enhanced FSYNC operation<br>Shift registers, display drivers, « Audio CODEC support<br>ADCs, and so on. = 2s protocol<br>SPI1 has two paths to device pins. One using PPS - Left justified<br>(slower operation) and another using dedicated pins - Right justified<br>(faster operation). The dedicated pins can operate ata - PCM<br>maximum of 40 MHz whereas PPS pins (slower SPI)<br>can operate up to 20 20 MHz. SPI2 supports single path to<br>device pins using PPS.<br>FIGURE 21-1: SPI/I2S MODULE BLOCK DIAGRAM<br>—_———y et<br>| Data Bus<br>Read ee<br>r—-- il — os Write—--4F FIFOs Share Address SPIXBUF<br>| SPIXRXB FIFO SPIxTXB FIFO a<br>||<br>||<br>LH _— — —— Al<br>/\ \ / —Transmit<br>Receive— /\ \/<br>x}—_><br>x] <a<br>SDOx Shift MCLKSEL<br>Control<br>Slave Select Clock Edge<br>SSx/FsYnc | Syne Control REFCLKO1<br>xi + Baud Rate<br>ae PB3_CLK<br>Note: Access SPIXTXB and SPIxRXB FIFOs via SPIXBUF register. MSTEN<br>**----- End of picture text -----**<br>
SPI/I2S module is a a synchronous serial interface that is useful for communicating communicating with external peripherals and other MCU devices, as well as digital audio devices. These peripheral devices may be Serial EEPROMs, Shift registers, display drivers,
ADCs, and so on. SPI1 has two paths to device pins. One using PPS (slower operation) and another using dedicated pins (faster operation). The dedicated pins can operate ata maximum of 40 MHz whereas PPS pins (slower SPI) can operate up to 20 20 MHz. SPI2 supports single path to device pins using PPS.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 297
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|DS70005425A-page298|||PreliminaryDataSheet|©2020MicrochipTechnologyInc.|
PIC32MZ W1 and WFI32E01 Family
## smn
## REGISTER 21-1: SPIxCON: SPI CONTROL REGISTER
|Bit<br>Bit|Bit|Bit|Bit|Bit<br>Bit|Bit<br>Bit|
|---|---|---|---|---|---|
|vase<br>[2818ees<br>ET||||||
|° [on|[=] sot||bisspo®"|| wopes2_| monet|| swp| cKee|
|Legend:||||||
|R = Readable bit||W = Writable|bit|U = Unimplemented bit,|read as ‘0’|
|-n=ValueatPOR||‘1’=Bitisset||‘0’=Bitiscleared|X=Bitisunknown|
- bit 31 FRMEN: Framed SPI Support bit
- 1 = Framed SPI support is enabled (SSx pin used as FSYNC input/output)
- 0 = Framed SPI support is disabled
- bit 30 FRMSYNC: Frame Sync Pulse Direction Control on SSx pin bit (Framed SPI mode only) 1 = Frame sync pulse input (Slave mode)
- 0 = Frame sync pulse output (Master mode)
- bit 29 FRMPOL: Frame Sync/Slave Select Polarity bit (Framed SPI or Master Transmit modes only) 1 = Frame pulse or SSx pin is active-high 0 = Frame pulse or SSx is active-low
- bit 28 MSSEN: Master Mode Slave Select Enable bit__ 1 = Slave select SPI support is enabled. The SS pin is automatically driven during transmission in Master mode. Polarity is determined by the FRMPOL bit.
- 0 = Slave select SPI support is disabled.
- bit 27 FRMSYPW: Frame Sync Pulse Width bit 1 = Frame sync pulse is one character wide
- 0 = Frame sync pulse is one clock wide
- bit 26-24 FRMCNT<2:0>: Frame Sync Pulse Counter bits. Controls the number of data characters transmitted per pulse. This bit is only valid in Framed mode.
- 111 = Reserved
- 110 = Reserved
- 101 = Generates a frame sync pulse on every 32 data characters
- 100 = Generates a frame sync pulse on every 16 data characters
- 011 = Generates a frame sync pulse on every 8 data characters
- 010 = Generates a frame sync pulse on every 4 data characters
- 001 = Generates a frame sync pulse on every 2 data characters
- 000 = Generates a frame sync pulse on every data character
- bit23 MCLKSEL: Master Clock Enable bit")
- 1 = REFCLKO‘1 is used by the Baud Rate Generator
- 0 = PBCLK3 is used by the Baud Rate Generator
- bit 22-18 Unimplemented: Read as ‘0’
- Note 1: This bit can only be written when the ON bit = 0. Refer to Section 40.0 “Electrical Specifications” for maximum clock frequency requirements.
- 2: This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI mode (FRMEN = 1).
- 3: When AUDEN= 1, the SPI/I2S module functions as if the CKP bit is equal to ‘1’, regardless of the actual value of the CKP bit.
- 4: This bit present for legacy compatibility and is superseded by PPS functionality on these devices (see Section 13.4 “Peripheral Pin Select (PPS)” for more information).
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 299
## PIC32MZ W1 and WFI32E01 Family seman
|REGISTER 21-1:<br>SPIxCON: SPI CONTROL REGISTER (CONTINUED)|REGISTER 21-1:<br>SPIxCON: SPI CONTROL REGISTER (CONTINUED)|REGISTER 21-1:<br>SPIxCON: SPI CONTROL REGISTER (CONTINUED)|
|---|---|---|
|bit 17||SPIFE: Frame Sync Pulse Edge Select bit (Framed SPI mode only)|
|||1 = Frame synchronization pulse coincides with the first bit clock|
|||0 = Frame synchronization pulse precedes the first bit clock|
|bit16|||ENHBUF: Enhanced Buffer Enable bit!)|
|||1 = Enhanced Buffer mode is enabled|
|||0 = Enhanced Buffer mode is disabled|
|bit 15||ON: SPI/I2S Module On bit|
|||1 = SPI/I?S module is enabled|
|||0 = SPI/I?S module is disabled|
|bit 14||Unimplemented: Read as ‘0’|
|bit 13||SIDL: Stop in Idle Mode bit|
|||1 = Discontinue operation when CPU enters in Idle mode|
|||0 = Continue operation in Idle mode|
|bit12||DISSDO: Disable SDOx pin bit"4)|
|||1 = SDOx pin is not used by the module. Pin is controlled by associated PORT register.|
|||0 = SDOx pin is controlled by the module|
|bit 11-10||MODE<32,16>: 32/16-Bit Communication Select bits|
|||WhenAUDEN=<br>1:|
|||MODE32<br>MODE16<br>Communication|
|||1<br>1<br>24-bit Data, 32-bit FIFO, 32-bit Channel/64-bit Frame|
|||1<br>0<br>32-bit Data, 32-bit FIFO, 32-bit Channel/64-bit Frame|
|||0<br>1<br>16-bit Data, 16-bit FIFO, 32-bit Channel/64-bit Frame|
|||0)<br>0)<br>16-bit Data, 16-bit FIFO, 16-bit Channel/32-bit Frame|
|||WhenAUDEN=<br>0:|
|||MODE32<br>MODE16<br>Communication|
|||1<br>x<br>32-bit|
|||0<br>1<br>16-bit|
|||0)<br>0)<br>8-bit|
|bit 9||SMP: SPI Data Input Sample Phase bit|
|||Master mode (MSTEN=<br>1):|
|||1 = Input data sampled at end of data output time|
|||0 = Input data sampled at middle of data output time|
|||Slave mode (MSTEN=<br>0):|
|||SMP value is ignored when SPI is used in Slave mode. The module always uses SMP = 0.|
|bit 8||CKE: SPI Clock Edge Select bit(2)|
|||1 = Serial output data changes on transition from active clock state to Idle clock state (see CKP bit)|
|||0 = Serial output data changes on transition from Idle clock state to active clock state (see CKP bit)|
|bit 7||SSEN: Slave Select Enable (Slave mode) bit|
|||1 = SSx pin is used for Slave mode|
|||0 = SSx pin is not used for Slave mode, pin is controlled by the port function.|
|bit6||CKP: Clock Polarity Select bit’)|
|||1 =<br>Idle state for clock is a high level; active state is a low level|
|||0 =<br>Idle state for clock is a low level; active state is a high level|
|bit 5||MSTEN: Master Mode Enable bit|
|||1 =<br>Master mode|
|||0 = Slave mode|
|Note|1:|This bit can only be written when the ON bit = 0. Refer to Section 40.0 “Electrical Specifications” for|
|||maximum clock frequency requirements.|
||2:|This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI|
|||mode (FRMEN=<br>1).|
||3:|WhenAUDEN= 1, the SPI/I2S module functionsas iftheCKP bit isequal to ‘1’, regardless ofthe actual|
|||value of the CKP bit.|
||4:|This bit present for legacy compatibility and is superseded by PPS functionality on these devices (see|
|||Section13.4“PeripheralPinSelect(PPS)”formoreinformation).|
renner eee e rereerence eee eee DS70005425A-page 300 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
## REGISTER 21-1: SPIxCON: SP! CONTROL REGISTER (CONTINUED)
- bit 4 DISSDI: Disable SDI bit)
- 1 = SDI pin is not used by the SPI module (pin is controlled by PORT function) 0 = SDI pin is controlled by the SPI module
- bit 3-2 STXISEL<1:0>: SPI Transmit Buffer Empty Interrupt Mode bits 11 = Interrupt is generated when the buffer is not full (has one or more empty elements)
- 10 = Interrupt is generated when the buffer is empty by one-half or more 01 = Interrupt is generated when the buffer is completely empty 00 = Interrupt is generated when the last transfer is shifted out of SPISR and transmit operations are complete
- bit 1-0 SRXISEL<1:0>: SPI Receive Buffer Full Interrupt Mode bits
- 11 = Interrupt is generated when the buffer is full
- 10 = Interrupt is generated when the buffer is full by one-half or more 01 = Interrupt is generated when the buffer is not empty 00 = Interrupt is generated when the last word in the receive buffer is read (in other words buffer is empty)
- Note 1: This bit can only be written when the ON bit = 0. Refer to Section 40.0 “Electrical Specifications” for maximum clock frequency requirements.
- 2: This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI mode (FRMEN = 1).
- 3: When AUDEN = 1, the SPI/I2S module functions as if the CKP bit is equal to ‘1’, regardless of the actual value of the CKP bit.
- 4: This bit present for legacy compatibility and is superseded by PPS functionality on these devices (see Section 13.4 “Peripheral Pin Select (PPS)” for more information).
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 301
## PIC32MZ W1 and WFI32E01 Family
## seman
REGISTER 21-2: SPIxCON2: SP! CONTROL REGISTER 2
|Range|| 31/23/15/7 | 30/22/14/6 |29/21/13/5 | 28/20/12/4|27/19/11/3<br>26/18/10/2 |25/17/9/1 |24/16/8/0|
|---|---|---|
||Se<br>Se ee<br>ee|ee<br>ee<br>eee ee|
||hn ES<br>ee|ee<br>ee eee ee|
|a|SPISGNEXT|— | — |FRMERREN | SPIROVEN |SPITUREN|IGNROV|IGNTUR|<br> era eeee<br>ee||
|Legend:|||
|R=Readablebit<br>W=Writablebit||U=Unimplementedbit,readas‘0’|
## bit 31-16 Unimplemented: Read as ‘0’
- bit 15 SPISGNEXT: Sign Extend Read Data from the RX FIFO bit 1 = Data from RX FIFO is sign extended 0 = Data from RX FIFO is not sign extended
- bit 14-13 Unimplemented: Read as ‘0’ bit 12 FRMERREN: Enable Interrupt Events via FRMERR bit 1 = Frame error overflow generates error events 0 = Frame error does not generate error events
- bit 11 SPIROVEN: Enable Interrupt Events via SPIROV bit 1 = Receive overflow generates error events 0 = Receive overflow does not generate error events
- bit 10 SPITUREN: Enable Interrupt Events via SPITUR bit 1 = Transmit underrun generates error events 0 = Transmit underrun does not generates error events
- bit 9 IGNROV: Ignore Receive Overflow bit (for audio data transmissions) 1 =A ROV is not a critical error; during ROV data in the FIFO is not overwritten by receive data 0 =A ROV is a critical error which stop SPI operation
- bit 8 IGNTUR: Ignore Transmit Underrun bit (for audio data transmissions) 1 =A TUR is not a critical error and zeros are transmitted until the SPIxTXB is not empty 0 =A TUR is a critical error which stop SPI operation
- bit 7 AUDEN: Enable Audio CODEC Support bit!) 1 = Audio protocol is enabled 0 = Audio protocol is disabled
- bit 6-5 Unimplemented: Read as ‘0’ bit 3 AUDMONO: Transmit Audio Data Format bit!) 1 = Audio data is mono (each data word is transmitted on both left and right channels) 0 = Audio data is stereo
- bit 2 Unimplemented: Read as ‘0’ bit 1-0 | AUDMOD<1:0>: Audio Protocol Mode bit!:2) 11 = PCM/DSP mode 10 = Right Justified mode 01 = Left Justified mode 00 = |S mode
- Note 1: This bit can only be written when the ON bit = 0. 2: This bit is only valid for AUDEN = 1.
renner eee e rereerence eee eee DS70005425A-page 302 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
## REGISTER 21-3: SPIxSTAT: SP! STATUS REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0 giogae Le RROROT ROR p auo |OSvo | uo | Ro | PRO Po BELO 15:8 Po | uo | vo |rcons] ro | uo | vo | RO | = river [seeusy | — | | smu | ° [-sewr[spirov_[ sree [| — | sermee | — | serrer | sPiRer_| Legend: C = Clearable bit HS = Set in hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
## bit 31-29 Unimplemented: Read as ‘0’
bit 28-24 RXBUFELM<4:0>: Receive Buffer Element Count bits (valid only when ENHBUF = 1) bit 23-21 Unimplemented: Read as ‘0’
- bit 20-16 TXBUFELM<4:0>: Transmit Buffer Element Count bits (valid only when ENHBUF = 1)
- bit 15-13 Unimplemented: Read as ‘0’
- bit 12 FRMERR: SPI Frame Error status bit
- 1 = Frame error is detected 0 = No Frame error is detected
- This bit is only valid when FRMEN = 1.
- bit 11 SPIBUSY: SPI Activity Status bit 1 = SPI peripheral is currently busy with some transactions 0 = SPI peripheral is currently idle
- bit 10-9 Unimplemented: Read as ‘0’
- bit 8 SPITUR: Transmit Under Run bit 1 = Transmit buffer has encountered an Underrun condition 0 = Transmit buffer has no Underrun condition This bit is only valid in Framed Sync mode; the Underrun condition must be cleared by disabling/re-enabling the module.
- bit 7 SRMT: Shift Register Empty bit (valid only when ENHBUF = 1)
- 1 = When SPI module shift register is empty
- 0 = When SPI module shift register is not empty
- bit 6 SPIROV: Receive Overflow Flag bit 1 =A new data is completely received and discarded. The user software has not read the previous data in the SPIXBUF register.
- 0 = No overflow has occurred This bit is set in hardware; can only be cleared (= 0) in software.
- bit 5 SPIRBE: RX FIFO Empty bit (valid only when ENHBUF = 1) 1 = RX FIFO is empty (CRPTR = SWPTR)
- 0 = RX FIFO is not empty (CRPTR # SWPTR)
- bit 4 Unimplemented: Read as ‘0’
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 303
## PIC32MZ W1 and WFI32E01 Family
## seman
**==> picture [409 x 281] intentionally omitted <==**
**----- Start of picture text -----**<br>
|||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|REGISTER|21-3:|SPIxSTAT:|SP!|STATUS|REGISTER|(CONTINUED)|
|bit|3|SPITBE:|SPI|Transmit|Buffer|Empty|Status|bit|
|1|=|Transmit|buffer,|SPIXTXB|is|empty|
|0|=|Transmit|buffer,|SPIxXTXB|is|not|empty|
|Automatically|set|in|hardware|when|SPI|transfers|data|from|SPIXTXB|to|SPIXSR.|
|Automatically|cleared|in|hardware|when|SPIxBUF|is|written|to,|loading|SPIxTXB.|
|bit|2|Unimplemented:|Read|as|‘0’|
|bit|1|SPITBF:|SPI|Transmit|Buffer|Full|Status|bit|
|1|=|Transmit|is|not|yet|started,|SPITXB|is|full|
|0|=|Transmit|buffer|is|not|full|
|Standard|Buffer|mode:|
|Automatically|set|in|hardware|when|the|core|writes|to|the|SPIBUF|location,|loading|SPITXB.|
|Automatically|cleared|in|hardware|when|the|SPI|module|transfers|data|from|SPITXB|to|SPISR.|
|Enhanced|Buffer|mode:|
|Set when|CWPTR|+|1|=|SRPTR;|cleared|otherwise|
|bit|0|SPIRBF:|SPI|Receive|Buffer|Full|Status|bit|
|1|=|Receive|buffer,|SPIxRXB|is|full|
|0|=|Receive|buffer,|SPIXRXB|is|not|full|
|Standard|Buffer|mode:|
|Automatically|set|in|hardware|when|the|SPI|module|transfers|data|from|SPIXSR|to|SPIxRXB.|
|Automatically|cleared|in|hardware|when|SPIXBUF|is|read|from,|reading|SPIxRXB.|
|Enhanced|Buffer|mode:|
|Set when|SWPTR|+|1|=|CRPTR,;|cleared|otherwise|
**----- End of picture text -----**<br>
renner eee e rereerence eee eee DS70005425A-page 304 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
© 2020 Microchip Technology Inc.
Preliminary Data Sheet
DS70005425A-page 305
PIC32MZ W1 and WFI32E01 Family
DS70005425A-page 306
Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
## 22.0 SERIAL QUAD INTERFACE (SQl)
- Supports Single, Dual, and Quad Lane modes
- ¢ Supports Single Data Rate (SDR) mode
- Programmable command sequence
**==> picture [436 x 455] intentionally omitted <==**
**----- Start of picture text -----**<br>
Note: This data sheet summarizes the features * Does not support Execute-in-Place (XIP) over<br>of the PIC32MZ W1 device. It is not SQI interface<br>intended to be a _ comprehensive .<br>reference source. To complement the ¢ Data transfer:<br>information in this data sheet, refer to F Programmed VO mode (PIO)<br>Section 46. “Serial Quad Interface - Buffer descriptor DMA<br>(SQI)”, (DS60001244) in the “P/IC32 * Supports SPI Mode 0 and Mode 3<br>Family Reference Manual”, which is * Programmable Clock Polarity (CPOL) and Clock<br>available from the Microchip web site Phase (CPHA) bits<br>(www.microchip.com/PIC32). * Supports up to two chip selects<br>SQI module is a synchronous serial interface that * Supports up to four bytes of Flash address<br>access to serial Flash memories and other ¢ Programmable interrupt thresholds<br>devices. The SQI module supports Single Lane * 32-byte transmit data buffer<br>to SPI), Dual Lane, and Quad Lane modes. * 32-byte receive data buffer<br>following are key features of the SQI module: ¢ A-word controller buffer<br>22-1: SQI MODULE BLOCK DIAGRAM<br>PB3_CLK(2)<br>REFCLKO2") nx<br>(TBC) oe Control oo sGIbs<br>; Buffer 7<br>Iy I —X SQID1<br>II<br>1<br>!<br>Control and —X SQiD2<br>Status 7ransmit<br>Registers HX] saps<br>(PIO) 7 SQI Master<br>L Interface Xx] SQICLK<br>Receive x] Seiaee<br>Bus Master DMA Buffer _<br>—X] Saicst<br>Note 1: When configuring the REFCLKO2 clock source, a value of ‘0’ for the ROTRIM<8:0> bits must be selected.<br>2: This clock source is only used for SQI Special Function Register (SFR) access.<br>**----- End of picture text -----**<br>
The SQI module is a synchronous serial interface that provides access to serial Flash memories and other serial devices. The SQI module supports Single Lane (identical to SPI), Dual Lane, and Quad Lane modes. The following are key features of the SQI module:
**==> picture [235 x 8] intentionally omitted <==**
**----- Start of picture text -----**<br>
FIGURE 22-1: SQI MODULE BLOCK DIAGRAM<br>**----- End of picture text -----**<br>
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 307
## seman
**==> picture [457 x 671] intentionally omitted <==**
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## smn
**==> picture [459 x 671] intentionally omitted <==**
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## PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 22-1: SQI1CFG: SQ] CONFIGURATION REGISTER
|Bit<br>Bit<br>Bit|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit|
|---|---|
|Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0||
|4<br>eTsense<br>23:16a<br>ee<br>ee<br>ee||
|8 eT|arse<br>owe|
|° (=|ser foro [ora[MODE|
|Legend:|HC = Hardware Cleared<br>_r = Reserved|
|R = Readable bit|W = Writable bit<br>U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR|‘1’=Bitisset<br>‘0’=Bitiscleared<br>x=Bitisunknown|
- bit 31-26 Unimplemented: Read as ‘0’ bit 25-24 CSEN<1:0>: Chip Select Output Enable bits 11 = Chip Select 0 and Chip Select 1 are used 10 = Chip Select 1 is used (Chip Select 0 is not used) 01 = Chip Select 0 is used (Chip Select 1 is not used) 00 = Chip Select 0 and Chip Select 1 are not used
- bit 23 SQIEN: SQI Enable bit 1 = SQI module is enabled 0 = SQI module is disabled
- bit 22 Unimplemented: Read as ‘0’ bit 21-20 DATAEN<1:0>: Data Output Enable bits 11 = Reserved 10 = SQID3-SQIDO outputs are enabled 01 = SQID1 and SQIDO data outputs are enabled 00 = SQIDO data output is enabled
- bit 19 CONFIFORST: Control FIFO Reset bit 1 =A reset pulse is generated clearing the control FIFO 0 =A reset pulse is not generated
- bit 18 RXFIFORST: Receive FIFO Reset bit 1 =Areset pulse is generated clearing the receive FIFO 0 =A reset pulse is not generated
- bit 17 TXFIFORST: Transmit FIFO Reset bit 1 =A reset pulse is generated clearing the transmit FIFO 0 =A reset pulse is not generated
- bit 16 RESET: Software Reset Select bit This bit is automatically cleared by the SQI module. All of the internal state machines and FIFO pointers are reset by this reset pulse. 1 =Areset pulse is generated 0 =A reset pulse is not generated
- bit 15 Unimplemented: Read as ‘0’ bit 14-13 Reserved: Must be programmed as ‘0’
Note 1: This bit must be programmed as ‘1’.
renner eee e rereerence eee eee DS70005425A-page 310 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
## REGISTER 22-1: SQI1CFG: SQ] CONFIGURATION REGISTER (CONTINUED) bit12 | BURSTEN: Burst Configuration bit)
|||1 = Burst is enabled|
|---|---|---|
|||0 = Burst is not enabled|
|bit|11|Reserved: Must be programmed as ‘0’|
|bit|10|HOLD: Hold bit|
|||In Single Lane or Dual Lane mode, this bit is used to drive the SQID3 pin, which can be used for devices|
|||with a HOLD input pin. The meaning of the values for this bit will depend on the device to which SQID3 is|
|||connected.|
|bit|9|WP: Write Protect bit|
|||In Single Lane or Dual Lane mode, this bit is used to drive the SQID2 pin, which can be used with devices|
|||with a write-protect pin. The meaning of the values for this bit will depend on the device to which SQID2 is|
|||connected.|
|bit|8-6|Unimplemented: Read as ‘0’|
|bit|5|LSBF: Data Format Select bit|
|||1 = LSB is sent or received first|
|||0 = MSB is sent or received first|
|bit4|4|CPOL: Clock Polarity Select bit|
|||1 =Active-low SQICLK (SQICLK high is the Idle state)|
|||0 =Active-high SQICLK (SQICLK low is the Idle state)|
|bit|3|CPHA: Clock Phase Select bit|
|||1 = SQICLK starts toggling at the start of the first data bit|
|||0 = SQICLK starts toggling at the middle of the first data bit|
|bit|2-0|MODE<2:0>: Mode Select bits|
|||111 = Reserved|
|||100 = Reserved|
|||011 = Reserved|
|||010 = DMA mode is selected|
|||001 = CPU mode is selected (the module is controlled by the CPU in PIO mode.|
|||000=Reserved|
Note 1: This bit must be programmed as ‘1’.
reer reer rereeee reer rereeeeeee
reer reer rereeee reer rereeeeeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 311
## PIC32MZ W1 and WFI32E01 Family
## seman
**==> picture [257 x 9] intentionally omitted <==**
**----- Start of picture text -----**<br>
REGISTER 22-2: SQI1CON: SQI CONTROL REGISTER<br>**----- End of picture text -----**<br>
|Bit|Bit<br>Bit<br>Bit<br>Bit|Bit<br>Bit<br>Bit<br>Bit||Bit|Bit||Bit|Bit|
|---|---|---|---|---|---|---|---|---|
|Range | <br>rg<br>ae|31/23/15/7 | 30/22/14/6 |29/21/13/5 | 28/20/12/4 | <br>=<br>=O<br>a<br>a a||27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0<br>CO =<br>a<br>Boa||||||
|‘8<br>[7= Poassert| Devseiio> | LANEMODE<10> ||||||||OMDINIT=10> |||
|:|||||||||
|:|||||||||
|Legend:|r = Reserved||||||||
|R = Readable bit<br>W = Writable bit|||U|= Unimplemented bit, read as ‘0’|||||
|-n = Value|at POR<br>‘1’ = Bit is set||‘0’ = Bit is cleared|||x =|Bit is unknown||
|bit 31-26|Unimplemented: Read as ‘0’||||||||
|bit 25|Reserved: Must be programmed as ‘0’||||||||
|bit 24|SCHECK: Flash Status Check bit||||||||
||1 = Check the status of the Flash||||||||
||0 = Do not check the status of the Flash||||||||
|bit 23|Unimplemented: Read as ‘0’||||||||
|bit 22|DASSERT: Chip SelectAssert bit||||||||
||1 = Chip Select is deasserted after transmission or reception of the specified number of bytes||||||||
||0 = Chip Select is not deasserted after transmission or||reception of the specified|||number of bytes|||
|bit 21-20|DEVSEL<1:0>: SQI Device Select bits||||||||
||11 = Reserved||||||||
||10 = Reserved||||||||
||01 = Select Device 1||||||||
||00 = Select Device 0||||||||
|bit 19-18|LANEMODE<1:0>: SQI Lane Mode Select bits||||||||
||11 = Reserved||||||||
||10 = Quad Lane mode||||||||
||01 = Dual Lane mode||||||||
||00 = Single Lane mode||||||||
|bit 17-16|CMDINIT<1:0>: Command Initiation Mode Select bits||||||||
||If it is Transmit, commands are initiated based on a write to the transmit||||register or the contents ofTX|||TX|
||FIFO. IfCMDINIT is Receive, commands are initiated based on reads to||||the read register or RX FIFO||||
||availability.||||||||
||11 = Reserved||||||||
||10 = Receive||||||||
||01 = Transmit||||||||
||00 =Idle||||||||
|bit 15-O|TXRXCOUNT<15:0>: Transmit/Receive Count|bits|||||||
||Thesebitsspecifythetotalnumberofbytestotransmitorreceive(basedonCMDINIT).||||||||
renner eee e rereerence eee eee DS70005425A-page 312 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
## REGISTER 22-3: SQI1CLKCON: SQI CLOCK CONTROL REGISTER
|Bit<br>Bit<br>Bit<br>Bit|Bit|Bit<br>Bit|Bit<br>Bit|
|---|---|---|---|
|Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4|||27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0||
|23:16<br>pa SS eee|||we|
|:||||
|—|<br>= | = [ = [|=|[| =<br>[| =|[ smasie | oe|
|Legend:||||
|R = Readable bit<br>W = Writable bit||U = Unimplemented bit, read as ‘0’||
|-n=ValueatPOR<br>‘1’=Bitisset||‘0’=Bitiscleared|x=Bitisunknown|
bit 31-19 Unimplemented: Read as ‘0’
- bit 18-8 CLKDIV<10:0>: SQI Clock Tsai Frequency Select bit!) 10000000000 = Base clock TBC is divided by 2048 01000000000 = Base clock TBC is divided by 1024 00100000000 = Base clock TBC is divided by 512 00010000000 = Base clock TBC is divided by 256 00001000000 = Base clock TBC is divided by 128 00000100000 = Base clock TBC is divided by 64 00000010000 = Base clock TBC is divided by 32 00000001000 = Base clock TBC is divided by 16 00000000100 = Base clock TBC is divided by 8 00000000010 = Base clock TBC is divided by 4 00000000001 = Base clock TBC is divided by 2 00000000000 = Base clock TBC
- Setting these bits to ‘00000000000’ specifies the highest frequency of the SQI clock.
- bit 7-2 Unimplemented: Read as ‘0’
- bit 1 STABLE: Tsal Clock Stable Select bit This bit is set to ‘1’ when the SQI clock, Tsal, is stable after writing a ‘1’ to the EN bit. 1 = Tsal clock is stable 0 = Tsal clock is not stable
- bit 0 EN: Tsal Clock Enable Select bit
- When clock oscillation is stable, the SQI module will set the STABLE bit to ‘1’. 1 = Enable the SQI clock (Tsal) (when clock oscillation is stable, the SQI module sets the STABLE bit to ‘1’) 0 = Disable the SQI clock (Tsal) (the SQI module should stop its clock to enter a low power state); SFRs can still be accessed, as they use PB3_CLK
Note 1: Refer to 40.0 “Electrical Specifications” for the maximum clock frequency specifications.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 313
## PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 22-4: SQI1CMDTHR: SQI COMMAND THRESHOLD REGISTER
|Bit<br>Bit|Bit|Bit|Bit|Bit<br>Bit<br>Bit|Bit|
|---|---|---|---|---|---|
|Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 |27/19/11/3 | 26/18/10/2 | 25/17/9/1 ||||||24/16/8/0|
|us (Fe<br>=<br>=<br>=<br>= =<br>pase<br>qeSee ee||||||
|:||||||
|:||||||
|Legend:||||||
|R = Readable bit||W = Writable bit||U = Unimplemented bit, read as ‘0’||
|-n=ValueatPOR||‘1’=Bitisset||‘0’=Bitiscleared<br>X=Bitisunknown||
## bit 31-13 Unimplemented: Read as ‘0’
bit 15-8 TXCMDTHR<7:0>: Transmit Command Threshold bits
In transmit initiation mode, the SQI module performs a transmit operation when transmit command threshold bytes are present in the TX FIFO. These bits should usually be set to ‘1’ for normal Flash commands, and set to a higher value for page programming. For 16-bit mode, the value should be a multiple of 2. bit7-0 | RXCMDTHR<7:0>: Receive Command Threshold bits!)
In receive initiation mode, the SQI module attempts to perform receive operations to fetch the receive command threshold number of bytes in the receive buffer. If space for these bytes is not present in the FIFO, the SQI will not initiate a transfer. For 16-bit mode, the value should be a multiple of2.
If software performs any reads, thereby reducing the FIFO count, hardware would initiate a receive transfer to make the FIFO count equal to the value in these bits. If software would not like any more words latched into the FIFO, command initiation mode needs to be changed to Idle before any FIFO reads by software.
Note 1: These bits should only be programmed whena receive is not active (i.e., during Idle mode or a transmit).
renner eee e rereerence eee eee DS70005425A-page 314 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
## REGISTER 22-5: SQI1INTTHR: SQI INTERRUPT THRESHOLD REGISTER
|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit|
|---|
|Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 |27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0<br>[ooEpa<br>pase SeSe ee|
|:|
|:|
|Legend:|
|R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR<br>‘1’=Bitisset<br>‘0’=Bitiscleared<br>x=Bitisunknown|
## bit 31-13 Unimplemented: Read as ‘0’
- bit 15-8 TXINTTHR<7:0>: Transmit Interrupt Threshold bits
- A transmit interrupt is set when the transmit FIFO has more space than the set number of bytes. For 16-bit mode, the value should be a multiple of 2.
- bit 7-0 RXINTTHR<7:0>: Receive Interrupt Threshold bits
- Areceive interrupt is set when the receive FIFO count is larger than or equal to the set number of bytes. For 16-bit mode, the value should be multiple of 2.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 315
## PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 22-6: SQIINTEN: SQI INTERRUPT ENABLE REGISTER
Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4| 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0 | PTCOMPIE | BDDONETE | GONTHRIE | Legend: HS = Hardware Set R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
|bit|31-12|Unimplemented: Read as ‘0’|
|---|---|---|
|bit|11|DMAEIE: DMA Bus Error Interrupt Enable bit|
|||1 = Interrupt is enabled|
|||0 = Interrupt is disabled|
|bit|10|PKTCOMPIE: DMA Buffer Descriptor Packet Complete Interrupt Enable bit|
|||1 = Interrupt is enabled|
|||0 = Interrupt is disabled|
|bit|9|BDDONEIE: DMA Buffer Descriptor Done Interrupt Enable bit|
|||1 = Interrupt is enabled|
|||0 = Interrupt is disabled|
|bit|8|CONTHRIE: Control Buffer Threshold Interrupt Enable bit|
|||1 = Interrupt is enabled|
|||0 = Interrupt is disabled|
|bit|7|CONEMPTYIE: Control Buffer Empty Interrupt Enable bit|
|||1 = Interrupt is enabled|
|||0 = Interrupt is disabled|
|bit|6|CONFULLIE: Control Buffer Full Interrupt Enable bit|
|||This bit enables an interruptwhen the receive FIFO buffer is full.|
|||1 = Interrupt is enabled|
|||0 = Interrupt is disabled|
|bit|5|RXTHRIE: Receive Buffer Threshold Interrupt Enable bit|
|||1 = Interrupt is enabled|
|||0 = Interrupt is disabled|
|bit4|4|RXFULLIE: Receive Buffer Full Interrupt Enable bit|
|||1 = Interrupt is enabled|
|||0 = Interrupt is disabled|
|bit|3|RXEMPTYIE: Receive Buffer Empty Interrupt Enable bit|
|||1 = Interrupt is enabled|
|||0 = Interrupt is disabled|
|bit|2|TXTHRIE: Transmit Threshold Interrupt Enable bit|
|||1 = Interrupt is enabled|
|||0 = Interrupt is disabled|
|bit|1|TXFULLIE: Transmit Buffer Full Interrupt Enable bit|
|||1 = Interrupt is enabled|
|||0 = Interrupt is disabled|
|bit|0|TXEMPTYIE: Transmit Buffer Empty Interrupt Enable bit|
|||1 = Interrupt is enabled|
|||0=Interruptisdisabled|
renner eee e rereerence eee eee DS70005425A-page 316 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
## REGISTER 22-7: SQIHINTSTAT: SQI INTERRUPT STATUS REGISTER
**==> picture [445 x 187] intentionally omitted <==**
**----- Start of picture text -----**<br>
Bit Bit Bit Bit Bit Bit Bit Bit Bit<br>Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0<br>Sd<br>aie | SS Se ee<br>15:8 DMA PKT BD CON<br>EIF COMPIF DONEIF THRIF<br>70|<br>Legend: HS = Hardware Set<br>R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’<br>-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown<br>**----- End of picture text -----**<br>
bit 31- Unimplemented: Read as ‘0’ 12
- bit 11 DMAEIF: DMA Bus Error Interrupt Flag bit 1 = DMA bus error has occurred
- 0 = DMA bus error has not occurred
- bit10 |PKTCOMPIF: DMA Buffer Descriptor Processor Packet Completion Interrupt Flag bit
- 1 = DMABD packet is complete
- 0 = DMABD packet is in progress
- bit 9 BDDONEIF: DMA Buffer Descriptor Done Interrupt Flag bit
- 1 = DMABBD process is done
- 0 = DMABBD process is in progress
- bit 8 CONTHRIF: Control Buffer Threshold Interrupt Flag bit
- 1 = The control buffer has more than THRES words of space available
- 0 = The control buffer has less than THRES words of space available
- bit 7 CONEMPTYIF: Control Buffer Empty Interrupt Flag bit
- 1 = Control buffer is empty
- 0 = Control buffer is not empty
- bit 6 CONFULLIF: Control Buffer Full Interrupt Flag bit
- 1 = Control buffer is full
- 0 = Control buffer is not full
- bit5 | RXTHRIF: Receive Buffer Threshold Interrupt Flag bit") 1 = Receive buffer has more than RXINTTHR words of space available
- 0 = Receive buffer has less than RXINTTHR words of space available
- bit 4 RXFULLIF: Receive Buffer Full Interrupt Flag bit 1 = Receive buffer is full
- 0 = Receive buffer is not full
- bit 3 RXEMPTYIF: Receive Buffer Empty Interrupt Flag bit 1 = Receive buffer is empty 0 = Receive buffer is not empty
- Note 1: This bit will be set to a ‘1’, immediately after a POR until a read request on the System Bus is received.
- 2: The bits in the register are cleared by writing a '1' to the corresponding bit position.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 317
## PIC32MZ W1 and WFI32E01 Family
## seman
|REGISTER 22-7:<br>SQI1INTSTAT: SQI INTERRUPT STATUS REGISTER (CONTINUED)|REGISTER 22-7:<br>SQI1INTSTAT: SQI INTERRUPT STATUS REGISTER (CONTINUED)|
|---|---|
|bit 2|TXTHRIF: Transmit Buffer Threshold Interrupt Flag bit|
||1 = Transmit buffer has more than TXINTTHR words ofspace available|
||0 = Transmit buffer has less than TXINTTHR words of space available|
|bit 1|TXFULLIF: Transmit Buffer Full Interrupt Flag bit|
||1 = The transmit buffer is full|
||0 = The transmit buffer is not full|
|bit 0|TXEMPTYIF: Transmit Buffer Empty Interrupt Flag bit|
||1 = The transmit buffer is empty|
||0=Thetransmitbufferhascontent|
- Note 1: This bit will be set to a ‘1’, immediately after a POR until a read request on the System Bus is received. 2: The bits in the register are cleared by writing a '1' to the corresponding bit position.
renner eee e rereerence eee eee DS70005425A-page 318 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
## REGISTER 22-8: SQI1TXDATA: SQI TRANSMIT DATA BUFFER REGISTER
|Bit|Bit|Bit|Bit|Bit|Bit|Bit|Bit|Bit|
|---|---|---|---|---|---|---|---|---|
|Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 |27/19/11/3 | 26/18/10/2 | 25/17/9/1||||||||| 24/16/8/0|
|:|||||||||
|:|||||||||
|:|||||||||
|:|||||||||
|Legend:|||||||||
|R = Readable bit||W|= Writable bit|U|= Unimplemented bit, read as ‘0’||||
|-n=ValueatPOR||‘1’|=Bitisset|‘0’|=Bitiscleared|x|=Bitisunknown||
- bit31-0 TXDATA<31:0>: Transmit Command Data bits
- Data is loaded into this register before being transmitted. Prior to the data transfer, the data in TXDATA is loaded into the shift register (SFDR).
Multiple writes to TXDATA can occur while a transfer is in progress. There can be a maximum of eight commands that can be queued.
## REGISTER 22-9: SQI1RXDATA: SQI RECEIVE DATA BUFFER REGISTER
|Bit|Bit|Bit|Bit|Bit|Bit<br>Bit<br>Bit<br>Bit|
|---|---|---|---|---|---|
|Range|| 31/23/15/7|| 30/22/14/6|| 29/21/13/5 | 28/20/12/4|||27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0|
|ging|Fe RO|RO|RO<br>RO||ROT ROT ROR|
|sie<br>:|| RO|| ro|| Ro ||Ro|| Ro | Ro | ROT RO|
|ie<br>:|( RO|[| ro|[| ro [||ro|[| ro [| Ro | Ro [ Ro ||
|7|(Ro|[| ro|| ro ||Ro|[| ro [| Ro | Ro [ Ro ||
|Legend:||||||
|R = Readable bit|||W = Writable bit||U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR|||‘1’=Bitisset||‘0’=Bitiscleared<br>x=Bitisunknown|
- bit31-0 RXDATA<31:0>: Receive Data Buffer bits
- At the end of a data transfer, the data in the shift register is loaded into the RXDATA register. This register works like a FIFO. The depth of the receive buffer is eight words.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 319
PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 22-10: SQI1STAT1: SQI STATUS REGISTER 1
|Bit|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit|
|---|---|
|Range|| 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 |27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0|
|\<br>o16 <br>8Sr<br>pe <br>yn<br>°|EE<br>ee ee ee ee ee ee<br>eee<br> Lo | uo | Ro | Ro [ RO<br>[| RO | RO [ RO |<br>Sr<br>irorreessos<br> Se<br>LL ve | vo [ Ro<br>[| Ro | Ro | RO [ RO | RO |<br> (FONTS|
|Legend:||
|R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’||
|-n=ValueatPOR<br>‘1’=Bitisset<br>‘0’=Bitiscleared<br>x=Bitisunknown||
bit 31-22 Unimplemented: Read as ‘0’ bit 21-16 TXFIFOFREE<5:0>: Transmit FIFO Available Word Space bits bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 RXFIFOCNT<5:0>: Number of words of read data in the FIFO
renner eee e rereerence eee eee DS70005425A-page 320 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
## REGISTER 22-11: SQI1STAT2: SQI STATUS REGISTER 2
**==> picture [459 x 111] intentionally omitted <==**
**----- Start of picture text -----**<br>
||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|
|Range|31/23/15/7|30/22/14/6|| 29/21/13/5|| 28/20/12/4|| 27/19/11/3|| 26/18/10/2|||25/17/9/1|||24/16/8/0|
|a= EeEe|Eee|
|||se |aSS Se___|__|_)|oe|
|oe|oF|ES|ET|conrvaticesSSS|
|conavait<o>|||sais_[|saioz_||saint|_[|sao [—|||RwNn|||Tov _||
**----- End of picture text -----**<br>
## Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-18 Unimplemented: Read as ‘0’
- bit 17-16 CMDSTAT<1:0>: Current Command Status bits
- These bits indicate the current command status. 11 = Reserved 10 = Receive 01 = Transmit 00 =Idle
- bit 15-12 Unimplemented: Read as ‘0’
- bit 11-7 CONAVAIL<4:0>: Control FIFO Space Available bits These bits indicate the available control Word space. 11111 = 32 bytes are available 11110 = 31 bytes are available
- 00001 = 1 byte is available 00000 = No bytes are available
- bit 6 SQID3: SQID3 Status bit 1 = Data is present on SQID3
- 0 = Data is not present on SQID3
- bit 5 SQID2: SQID2 Status bit 1 = Data is present on SQID2 0 = Data is not present on SQID2
- bit 4 SQID1: SQID1 Status bit 1 = Data is present on SQID1
- 0 = Data is not present on SQID1
- bit 3 SQIDO: SQIDO Status bit 1 = Data is present on SQIDO
- 0 = Data is not present on SQIDO
- bit 2 Unimplemented: Read as ‘0’
- bit 1 RXUN: Receive FIFO Underflow Status bit 1 = Receive FIFO Underflow has occurred
- 0 = Receive FIFO underflow has not occurred
- bit 0 TXOV: Transmit FIFO Overflow Status bit 1 = Transmit FIFO overflow has occurred 0 = Transmit FIFO overflow has not occurred
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 321
## PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 22-12: SQI1BDCON: SQI BUFFER DESCRIPTOR CONTROL REGISTER
|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit|
|---|
|Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 |27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0|
|paEe<br>pie<br>qeSee ee<br>pss SS Se ee|
|° (estar<br>nt [Maen|
|Legend:|
|R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR<br>‘1’=Bitisset<br>‘0’=Bitiscleared<br>X=Bitisunknown|
## bit 31-3. Unimplemented: Read as ‘0’ bit 2 START: Buffer Descriptor Processor Start bit
- 1 = Start the buffer descriptor processor
- 0 = Disable the buffer descriptor processor
- bit 1 POLLEN: Buffer Descriptor Poll Enable bit 1 = BDP poll is enabled
- 0 = BDP poll is not enabled
- bit 0 DMAEN: DMA Enable bit 1 = DMAis enabled 0 = DMA is disabled
REGISTER 22-13: SQI1BDCURADD: SQI BUFFER DESCRIPTOR CURRENT ADDRESS REGISTER
|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit|
|---|
|Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 |27/19/11/3 |26/18/10/2 | 25/17/9/1 | 24/16/8/0|
|jorge PRORR<br>} care Ret re |e |<br>ee ee<br>eee<br>| ro - Be tee | ne | oe ee|
|Legend:|
|R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR<br>‘1’=Bitisset<br>‘0’=Bitiscleared<br>x=Bitisunknown|
## bit 31-0 BDCURRADDR<31:0>: Current Buffer Descriptor Address bits
- These bits contain the address of the current descriptor being processed by the Buffer Descriptor Processor.
renner eee e rereerence eee eee DS70005425A-page 322 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
|REGISTER 22-14:|SQI1BDBASEADD: SQI BUFFER|SQI1BDBASEADD: SQI BUFFER|DESCRIPTOR BASE ADDRESS REGISTER|DESCRIPTOR BASE ADDRESS REGISTER|
|---|---|---|---|---|
|Bit<br>Bit|Bit<br>Bit|Bit|Bit<br>Bit<br>Bit|Bit|
|Legend:|||||
|R = Readable bit|W = Writable bit||U = Unimplemented bit, read as ‘0’||
|-n=ValueatPOR|‘1’=Bitisset||‘0’=Bitiscleared<br>x=Bitis|unknown|
- bit 31-0 _BDADDR<31:0>: DMA Base Address bits
These bits contain the physical address of the root buffer descriptor. This register should be updated only when the DMAis idle.
## REGISTER 22-15: SQI1BDSTAT: SQi BUFFER DESCRIPTOR STATUS REGISTER
|Bit<br>Bit|Bit|Bit|Bit|Bit<br>Bit<br>Bit|Bit|
|---|---|---|---|---|---|
|EE <br>| 26,|p|EE|Ee Ee **e**e ee ee eee<br>—<br>— ee<br>—<br>a||||
|Legend:||||||
|R = Readable bit||W = Writable bit||U = Unimplemented bit, read as ‘0’||
|-n=ValueatPOR||‘1’=Bitisset||‘0’=Bitiscleared<br>x=Bitisunknown||
- bit 31-22 Unimplemented: Read as ‘0’
- bit 21-18 BDSTATE<3:0>: DMA Buffer Descriptor Processor State Status bits These bits return the current state of the buffer descriptor processor:
- 5 = Fetched buffer descriptor is disabled
- 4 = Descriptor is done
- 3 = Data phase
- 2 = Buffer descriptor is loading
- 1 = Descriptor fetch request is pending 0 = Idle
bit 17 DMASTART: DMA Buffer Descriptor Processor Start Status bit 1 = DMA has started
- 0 = DMAhas not started
- bit 16 DMAACTV: DMA Buffer Descriptor Processor Active Status bit 1 = Buffer Descriptor Processor is active
- 0 = Buffer Descriptor Processor is idle
- bit 15-0 _BDCON<15:0>: DMA Buffer Descriptor Control Word bits These bits contain the current buffer descriptor control word.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 323
## PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 22-16: SQI1BDPOLLCON: SQI BUFFER DESCRIPTOR POLL CONTROL REGISTER
|Range|| 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 |27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0|
|---|---|
||es ee eG|
||esee|
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared X = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 _POLLCON<15:0>: Buffer Descriptor Processor Poll Status bits
These bits indicate the number of cycles the BDP would wait before refetching the descriptor control word if the previous descriptor fetched was disabled.
REGISTER 22-17: SQI1BDTXDSTAT: SQ] BUFFER DESCRIPTOR DMA TRANSMIT STATUS REGISTER
**==> picture [529 x 166] intentionally omitted <==**
**----- Start of picture text -----**<br>
Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0<br>aaa=<br>aa a<br>BES BES SES SES SES BES SEs sss<br>Legend:<br>R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’<br>-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown<br>**----- End of picture text -----**<br>
bit 31-29 Unimplemented: Read as ‘0’
bit 28-25 TXSTATE<3:0>: Current DMA Transmit State Status bits
These bits provide information on the current DMA receive states. bit 24-21 Unimplemented: Read as ‘0’
bit 20-16 TXBUFCNT<4:0>: DMA Buffer Byte Count Status bits
These bits provide information on the internal FIFO space.
bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 TXCURBUFLEN<X<7:0>: Current DMA Transmit Buffer Length Status bits These bits provide the length of the current DMA transmit buffer.
renner eee e rereerence eee eee DS70005425A-page 324 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
## REGISTER 22-18: SQI1BDRXDSTAT: SQI BUFFER DESCRIPTOR DMA RECEIVE STATUS REGISTER
|Bit<br>Bit<br>Bit|Bit|Bit|Bit<br>Bit|Bit<br>Bit|
|---|---|---|---|---|
|Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4||||27/19/11/3 | 26/18/10/2 ||25/17/9/1 | 24/16/8/0|
|ae<br>a<br>a<br>a<br>=<br>23716<br>pee SS<br>Ee<br>ee<br>pss Se eee|||||
|:|||||
|Legend:|||||
|R = Readable bit|W = Writable bit||U = Unimplemented bit, read as ‘0’||
|-n=ValueatPOR|‘1’=Bitisset||‘0’=Bitiscleared|x=Bitisunknown|
bit 31-29 Unimplemented: Read as ‘0’
bit 28-25 RXSTATE<3:0>: Current DMA Receive State Status bits
These bits provide information on the current DMA receive states.
- bit 24-21 Unimplemented: Read as ‘0’
bit 20-16 RXBUFCNT<4:0>: DMA Buffer Byte Count Status bits
These bits provide information on the internal FIFO space.
- bit 15-8 Unimplemented: Read as ‘0’
bit 7-0 RXCURBUFLEN<7:0>: Current DMA Receive Buffer Length Status bits These bits provide the length of the current DMA receive buffer.
## REGISTER 22-19: SQI1THR: SQ]l THRESHOLD CONTROL REGISTER
|Bit<br>Bit<br>Bit<br>Bit<br>Bit|Bit<br>Bit|Bit<br>Bit|
|---|---|---|
|Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 |27/19/11/3|27/19/11/3 |26/18/10/2 | 25/17/9/1 | 24/16/8/0||
|er ee<br>ee ee ee<br>pp SE SS ee<br>pe Seee||EEE<br>ee|
|i<br>a=|||
|Legend:|||
|R = Readable bit<br>W = Writable bit|U = Unimplemented|bit, read as ‘0’|
|-n=ValueatPOR<br>‘1’=Bitisset|‘0’=Bitiscleared|X=Bitisunknown|
bit 31-5 Unimplemented: Read as ‘0’
bit 4-0 THRES<4:0>: SQI Control Threshold Value bits The SQI control threshold interrupt is asserted when the amount of space indicated by THRES<4:0> is available in the SQI control buffer.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 325
## PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 22-20: SQI1INTSIGEN: SQI INTERRUPT SIGNAL ENABLE REGISTER
Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0 15:8 PKT BD CON jo [== ase [ae [ate [ae EMPTYISE FULLISE THRISE FULLISE EMPTYISE THRISE FULLISE EMPTYISE Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-12 Unimplemented: Read as ‘0’
- bit 11 DMAEISE: DMA Bus Error Interrupt Signal Enable bit 1 = Interrupt signal is enabled 0 = Interrupt signal is disabled
- bit 10 PKTDONEISE: Receive Error Interrupt Signal Enable bit 1 = Interrupt signal is enabled 0 = Interrupt signal is disabled
- bit 9 BDDONEISE: Transmit Error Interrupt Signal Enable bit 1 = Interrupt signal is enabled
- 0 = Interrupt signal is disabled
- bit 8 CONTHRISE: Control Buffer Threshold Interrupt Signal Enable bit 1 = Interrupt signal is enabled 0 = Interrupt signal is disabled
- bit 7 CONEMPTYISE: Control Buffer Empty Interrupt Signal Enable bit 1 = Interrupt signal is enabled 0 = Interrupt signal is disabled
- bit 6 CONFULLISE: Control Buffer Full Interrupt Signal Enable bit 1 = Interrupt signal is enabled 0 = Interrupt signal is disabled
- bit 5 RXTHRISE: Receive Buffer Threshold Interrupt Signal Enable bit 1 = Interrupt signal is enabled 0 = Interrupt signal is disabled
- bit 4 RXFULLISE: Receive Buffer Full Interrupt Signal Enable bit 1 = Interrupt signal is enabled 0 = Interrupt signal is disabled
- bit 3 RXEMPTYISE: Receive Buffer Empty Interrupt Signal Enable bit 1 = Interrupt signal is enabled 0 = Interrupt signal is disabled
- bit 2 TXTHRISE: Transmit Buffer Threshold Interrupt Signal Enable bit 1 = Interrupt signal is enabled 0 = Interrupt signal is disabled
- bit 1 TXFULLISE: Transmit Buffer Full Interrupt Signal Enable bit 1 = Interrupt signal is enabled 0 = Interrupt signal is disabled
- bit 0 TXEMPTYISE: Transmit Buffer Empty Interrupt Signal Enable bit 1 = Interrupt signal is enabled 0 = Interrupt signal is disabled
renner eee e rereerence eee eee DS70005425A-page 326 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
## REGISTER 22-21: SQI1TAPCON: SQI TAP CONTROL REGISTER
|Bit<br>Bit<br>Bit<br>Bit|Bit<br>Bit<br>Bit|Bit<br>Bit|
|---|---|---|
|Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 ||28/20/12/4 |27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0||
|Se eeee<br>pase<br>eS|ee<br>ee|ee|
|8 Eee<br>eens|||
|-<br>:|||
|Legend:|||
|R = Readable bit<br>W = Writable|bit<br>U = Unimplemented|bit, read as ‘0’|
|-n=ValueatPOR<br>‘1’=Bitisset|‘0’=Bitiscleared|x=Bitisunknown|
bit 31-14 Unimplemented: Read as ‘0’
- bit 13-8 CLKINDLY<5:0>: SQI Clock Input Delay bits
- These bits are used to add fractional delays to SQI Clock Input while sampling the incoming data. 111111 = 64 taps added on clock input 111110 = 63 taps added on clock input
000001 = 2 taps added on clock input 000000 =1 tap added on clock input
- bit 7-4 DATAOUTDLY<3:0>: SQI Data Output Delay bits
- These bits are used to add fractional delays to SQI Data Output while writing the data to the Flash. 1111 = 16 taps added on clock output 1110 = 15 taps added on clock output
0001 = 2 taps added on clock output 0000 =1 tap added on clock output
- bit 3-0 CLKOUTDLY<3:0>: SQI Clock Output Delay bits
- These bits are used to add fractional delays to SQI Clock Output while writing the data to the Flash. 1111 = 16 taps added on clock output 1110 = 15 taps added on clock output
0001 = 2 taps added on clock output 0000 =1 tap added on clock output
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 327
PIC32MZ W1 and WFI32E01 Family
## ee
## REGISTER 22-22: SQI1MEMSTAT: SQI MEMORY STATUS REGISTER
|Bit<br>Bit|Bit|Bit|Bit|Bit|Bit<br>Bit<br>Bit|
|---|---|---|---|---|---|
|Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 |27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0||||||
|psi SS|See|||||
|8 =||starros[startvrecio><br>| stareytes<t0>||||
|:||||||
|:||||||
|Legend:||||||
|R = Readable bit||W = Writable bit||U = Unimplemented bit, read as ‘0’||
|-n=ValueatPOR||‘1’=Bitisset||‘0’=Bitiscleared|x=Bitisunknown|
## bit 31-21 Unimplemented: Read as ‘0’
- bit 20 STATPOS: Status Bit Position in Flash bit Indicates the BUSY bit position in the Flash Status register. This bit is added to support all Flash types (with BUSY bit at 0 and at 7).
- 1 = BUSY bit position is bit 7 in status register
- 0 = BUSY bit position is bit 0 in status register
- bit 19-18 STATTYPE<1:0>: Status Command/Read Lane Mode bits 11 = Reserved
- 10 = Status command and read are executed in Quad Lane mode 01 = Status command and read are executed in Dual Lane mode
- 00 = Status command and read are executed in Single Lane mode
- bit 17-16 STATBYTES<1:0>: Number of Status Bytes bits
- 11 = Reserved
- 10 = Status command/read is 2 bytes long 01 = Status command/read is 1 byte long 00 = Reserved
- bit 15-8 STATDATA<7:0>: Status Data bits These bits contain the status value of the Flash device
bit 7-0 STATCMD<7:0>: Status Command bits The status check command is written into these bits
ee
DS70005425A-page 328
Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
## 23.0 INTER-INTEGRATED CIRCUIT (I7C)
- Note: This data sheet summarizes the feateres rf Ne RISEN ue” Hany ‘at devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 24. “InterIntegrated Circuit (I2C)” (DS60001116) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/ PIC32).
The I2C module provides. complete hardware support for both Slave and Multi-Master modes of the I?C serial communication standard.
Each I2C module has a 2-pin interface: » SCix Bin is aloek
¢« SDAx pin is data
- Each I?C module offers the following key features: - |?C interface supporting both master and slave operation
- + I?C Slave mode supports 7-bit and 10-bit addressing + ?C Master mode supports 7-bit and 10-bit addressing 2 _ ;
- ¢ I*C port allows bidirectional transfers between master and slaves
- * Serial clock synchronization for the I2C Port can be used as a handshake mechanism to Suspend and Resume Serial Transfer (SCLREL control)
- - 2c supports multi-master operation; detects bus collision and arbitrates accordingly
- Provides support for Slave mode address bit uniteki
- SMbus support
- Supports up to 1 MHz operation
## TABLE 23-1: 12C PB CLOCK MAPPING
||Ic|Instance|PB|Clock|
|---|---|---|---|---|
|12C1|||PB2_CLK||
|I2C2|||PB3_CLK||
Figure 23-1 illustrates the 12C module connection diagram.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 329
PIC32MZ W1 and WFI32E01 Family
## seman
**==> picture [422 x 569] intentionally omitted <==**
**----- Start of picture text -----**<br>
FIGURE 23-1: 12 CONNECTION DIAGRAM<br>Internal<br>Data Bus<br>I2CxRCV ><br>Read<br>MZ<br>SCLxx] > K<br>wa I2CxRSRPe<br>Xx ><br>SDAx Address Match :<br>Write Read<br>Read<br>Bit Detect<br>Write<br>ST Start and Stop <|<br><| Bit Generation I2CxSTAT rm al<br>> Read<br>Detect =Cc<br>S “i<br>< Acknowledge ><br>pa< I GenerationStretchingClock _ ; Read<br>Write<br>LSB e;<br>P Read<br>><br><| BRG Down Counter <| I2CxBRG rss |<br>Read<br>PB2_CLK/PB3_CLK<br>**----- End of picture text -----**<br>
renner eee e rereerence eee eee DS70005425A-page 330 Preliminary Data Sheet © 2020 Microchip Technology Inc.
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|©2020|MicrochipTechnologyInc.<br>PreliminaryData||Sheet||DS70005425A-page331|
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PIC32MZ W1 and WFI32E01 Family
## smn
**==> picture [456 x 180] intentionally omitted <==**
**----- Start of picture text -----**<br>
REGISTER 23-1: I2CxCON: I2C CONTROL REGISTER<br>Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0<br>= i ee a a ee ee a<br>P= Pc [sce [Ben | spant | sBcbe | AHEN | DHEN<br>[on [| — | sil soxre. [strict [atom | DIssiw | SMEN |<br>Legend: HC = Hardware Cleared<br>R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’<br>-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown<br>**----- End of picture text -----**<br>
- bit 31-23 Unimplemented: Read as ‘0’ bit 22 PCIE: Stop Condition Interrupt Enable bit (I2C Slave mode only)
- 1 = Enable interrupt on detection of Stop condition
- 0 = Stop detection interrupts are disabled
- bit 21 SCIE: Start Condition Interrupt Enable bit (l2C Slave mode only) 1 = Enable interrupt on detection of Start or Restart conditions
- 0 = Start detection interrupts are disabled
- bit 20 BOEN: Buffer Overwrite Enable bit (I? Slave mode only) 1 = I2CxRCV is updated and ACK is generated for a received address/data byte, ignoring the state of the I2COV bit (IZCxSTAT<6>)only if the RBF bit (I2CxSTAT<2>) = 0
- 0 = I2CxRCV is only updated when the I2COV bit (IZCxSTAT<6>) is clear
- bit 19 SDAHT: SDA Hold Time Selection bit 1 = Minimum of 300 ns hold time on SDA after the falling edge of SCL
- 0 = Minimum of 100 ns hold time on SDA after the falling edge of SCL
- Note: This bit is not supported for 1 MHz.
- bit 18 SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only)
- 1 = Enable slave bus collision interrupts
- 0 = Slave bus collision interrupts are disabled
- bit 17 AHEN: Address Hold Enable bit (Slave mode only) 1 = Following the 8th falling edge of SCL for a matching received address byte; SCKREL bit will be cleared and the SCL will be held low.
- 0 = Address holding is disabled
- bit 16 DHEN: Data Hold Enable bit (2c Slave mode only)
- 1 = Following the 8th falling edge of SCL for a received data byte; slave hardware clears the SCKREL bit and SCL is held low
- 0 = Data holding is disabled
- bit 15 ON: I7C Enable bit
- 1 = Enables the I2C module and configures the SDA and SCL pins as serial port pins
- 0 = Disables the I2C module; all Ic pins are controlled by PORT functions
- bit 14 Unimplemented: Read as ‘0’
- bit 13 SIDL: Stop in Idle Mode bit
- 1 = Discontinue module operation when device enters Idle mode
- 0 = Continue module operation in Idle mode
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 333
## PIC32MZ W1 and WFI32E01 Family seman
|REGISTER 23-1:<br>I2CxCON: I2C CONTROL REGISTER (CONTINUED)|REGISTER 23-1:<br>I2CxCON: I2C CONTROL REGISTER (CONTINUED)|||
|---|---|---|---|
|bit 12|SCLREL: SCLx Release Control bit (when operating as ae slave)|||
||In I2C Slave mode only; module resetand (ON = 0) sets SCLREL= 1.|||
||If STREN = 0:|||
||1 = Release clock|||
||0 = Force clock low (clock stretch)|||
||Bit is automatically cleared to ‘0’ at beginning of slave transmission.|||
||If STREN = 1:|||
||1 = Release clock|||
||0 = Holds clock low (clock stretch)|||
||Usermay program this bit to ‘0’ to force a clock stretch at the next SCLx low. Bit is automatically cleared to|||
||‘0’ at beginning of slave transmission; automatically cleared to ‘0’ at end of slave||reception.|
|bit 11|STRICT: Strict I2C Reserved Address Rule Enable bit|||
||1 =<br>Strict reserved addressing isenforced. Devicedoes not respond to reserved address space orgenerate|||
||addresses in reserved address space.|||
||0 = Strict IC reserved address rule is not enabled|||
|bit 10|A10M: 10-bit Slave Address bit|||
||1 = 12CxADD is a 10-bit slave address|||
||0 = I2CxADD is a 7-bit slave address|||
|bit 9|DISSLW: Disable Slew Rate Control bit|||
||1 = Slew rate control is disabled|||
||0 = Slew rate control is enabled|||
|bit 8|SMEN: SMBus Input Levels bit|||
||1 = Enable I/O pin thresholds compliant with SMBus specification|||
||0 = Disable SMBus input thresholds|||
|bit 7|GCEN: General Call Enable bit (when operating as 2c slave)|||
||1 = Enable interruptwhen a general call address is received in the I2CxRSR|||
||(module is enabled for reception)|||
||0 = General call address is disabled|||
|bit6|STREN: SCLx Clock Stretch Enable bit (when operating as 2c slave)|||
||Used in conjunction with SCLREL bit.|||
||1 = Enable software or receive clock stretching|||
||0 = Disable software or receive clock stretching|||
|bit 5|ACKDT:Acknowledge Data bit (when operating as ae master, applicable during||master receive)|
||Value that is transmitted when the software initiates an Acknowledge sequence.|||
||1 = SendNACK during acknowledge|||
||0 = SendACK during acknowledge|||
|bit4|ACKEN: Acknowledge Sequence Enable bit|||
||(when operating as ae master, applicable during master receive)|||
||1 = InitiateAcknowledge sequence on SDAx and SCLx pins and transmit|ACKDT|data bit.|
||Hardware clear at end of masterAcknowledge sequence.|||
||0 =Acknowledge sequence not in progress|||
|bit 3|RCEN: Receive Enable bit (when operating as me master)|||
||1 = Enables Receive mode for I2C. Hardware clear atend of eighth bit ofmaster||receive data byte.|
||0 = Receive sequence not in progress|||
|bit2|PEN: Stop Condition Enable bit (when operating as 2c master)|||
||1 = Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end|ofmaster Stop sequence.||
||0 = Stop condition not in progress|||
|bit 1|RSEN: Repeated Start Condition Enable bit (when operating as 2c master)|||
||1 = Initiate repeated Start condition on SDAxand SCLx pins. Hardware clear atend ofmasterrepeated Start|||
||sequence.|||
||0 = Repeated Start condition not in progress|||
|bit 0|SEN: Start Condition Enable bit (when operating as ae master)|||
||1 = Initiate Start condition on SDAx and SCLx pins. Hardware clear at end|ofmaster Start sequence.||
||0=Startconditionnotinprogress|||
renner eee e rereerence eee eee DS70005425A-page 334 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
|REGISTER 23-2:|1I2CxSTAT: I2C STATUS REGISTER|||
|---|---|---|---|
|Bit<br>Bit|Bit<br>Bit<br>Bit|Bit<br>Bit<br>Bit|Bit|
|Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 |27/19/11/3||27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0||
|ee<br>ee ee ee ee<br>esee ee||||
|8<br>[Packstar|[tester [ack | — | — (| ect | costar |||ano10 ||
|° [wea|[woo [ oa [| e | s | aw | rer |||tor ||
|Legend:|HS = HardwareSet|HC = Hardware Cleared<br>SC = Software Cleared||
|R = Readable bit|W = Writable bit|U = Unimplemented bit, read as ‘0’||
|-n=ValueatPOR|‘1’=Bitisset|‘0’=Bitiscleared<br>C=Clearable|bit|
- bit 31-16 Unimplemented: Read as ‘0’
- bit 15 ACKSTAT: Acknowledge Status bit (when operating as 12C master, applicable to master transmit operation)
- 1 = NACK received from slave
- 0 =ACK received from slave
- Hardware set or cleared at the end of slave acknowledge.
- bit 14 TRSTAT: Transmit Status bit (when operating as 2c master, applicable to master transmit operation) 1 = Master transmit is in progress (8 bits + ACK) 0 = Master transmit is not in progress
- Hardware set at beginning of master transmission. Hardware cleared at the end of slave acknowledge.
- bit 13 ACKTIM: Acknowledge Time Status bit (Valid in I2C Slave mode only) 1 = 17C bus is in an Acknowledge sequence, set on the eight falling edge of SCL clock 0 = Not an Acknowledge sequence, cleared on 9th rising edge of SCL clock
- bit 12-11 Unimplemented: Read as ‘0’
- bit 10 BCL: Master Bus Collision Detect bit 1 =A bus collision is detected during a master operation
- 0 = No collision Hardware set at detection of bus collision.
- bit 9 GCSTAT: General Call Status bit
- 1 = General call address is received
- 0 = General call address is not received
- Hardware set when address matches general call address. Hardware cleared at stop detection.
- bit 8 ADD10: 10-bit Address Status bit 1 = 10-bit address is matched
- 0 = 10-bit address is not matched Hardware set at match of 2nd byte of matched 10-bit address. Hardware cleared at stop detection.
- bit 7 IWCOL: Write Collision Detect bit 1 =An attempt to write the I2CxTRN register failed because the 12C module is busy 0 = No collision Hardware set at occurrence of write to I2CxTRN while busy (cleared by software).
- bit 6 I2COV: Receive Overflow Flag bit 1 =A byte is received while the I2CxRCV register is still holding the previous byte 0 = No overflow Hardware set at attempt to transfer I2CxRSR to I2CxRCV (cleared by software).
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 335
## PIC32MZ W1 and WFI32E01 Family
## seman
**==> picture [428 x 308] intentionally omitted <==**
**----- Start of picture text -----**<br>
||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|REGISTER|23-2:|12CxSTAT:|I2C|STATUS|REGISTER|(CONTINUED)|
|bit|5|D_A:|Data/Address|bit (when|operating|as|2c|slave)|
|1|=|Indicates|that|the|last|byte|received|is|data|
|0|=|Indicates|that|the|last|byte|received|is|device|address|
|Hardware|cleared|at|device|address|match.|Hardware|set|by|reception|of|slave|byte.|
|bit|4|P:|Stop|bit|
|1|=|Indicates|that|a|Stop|bit|is|detected|last|
|0|=|Stop|bit|is|not|detected|last|
|Hardware|set|or|cleared|when|start,|repeated|start|or|stop|detected.|
|bit|3|S:|Start|bit|
|1|=|Indicates|that|a|start|(or|repeated|start)|bit|is|detected|last|
|0|=|Start|bit|is|not|detected|last|
|Hardware|set|or|cleared|when|start,|repeated|start|or|stop|detected.|
|bit 2|R_W:|Read/Write|Information|bit|(when|operating|as|ae|slave)|
|1|=|Read|—|indicates|data|transfer|is|output from|slave|
|0|=|Write|—|indicates|data|transfer|is|input|to|slave|
|Hardware|set|or cleared|after|reception|of|12C|device|address|byte.|
|bit|1|RBF:|Receive|Buffer|Full|Status|bit|
|1|=|Receive|complete,|I2CxRCV|is|full|
|0|=|Receive|not|complete,|I2CxRCV|is|empty|
|Hardware|set when|I2CxRCV|is|written|with|received|byte.|Hardware|cleared|when|software|
|reads|I2CxRCV.|
|bit|0|TBF:|Transmit|Buffer|Full|Status|bit|
|1|=|Transmit|in|progress,|I2CxTRN|is|full|
|0|=|Transmit|complete,|I2CxTRN|is|empty|
|Hardware|set when|software|writes|I2CxTRN.|Hardware|cleared|at|completion|of data|transmission.|
**----- End of picture text -----**<br>
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PIC32MZ W1 and WFI32E01 Family
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To compute the Baud Rate Generator (BRG) reload value, use the formula in Equation 23-1:
## EQUATION 23-1: BRG RELOAD VALUE CALCULATION
I2CxBRG -ff_llars| Trap) PBCLK | _ 2
TABLE 23-4: 12C CLOCK RATE WITH BRG
|aa||Approximate Fsc,<br>I2CxBRG<br>(two rollovers of<br>BFG) (kHz)|
|---|---|---|
|so|fox? [ior[400||
|||0xoc2|
|Note|1:|The typical value of the Pulse Gobbler|
|||Delay (PGD) is 104 ns. Refer to the I2Cx|
|||Bus<br>Data<br>Timing<br>Requirements<br>in|
|||Table 40-28<br>and<br>Table 40-29<br>for<br>more|
|||information.|
|Note:||Equation 23-1 and Table 23-4 are|
|||provided as design<br>guidelines.<br>Due<br>to|
|||system-dependent<br>parameters,<br>the|
|||actual baud rate may differ slightly. Test-|
|||ing is required to confirm that the actual|
|||baud<br>rate<br>meets<br>the<br>system<br>require-|
|||ments. Otherwise, the value of the I2Cx-|
|||BRGregistermayneedtobeadjusted.|
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© 2020 Microchip Technology Inc. Preliminary Data Sheet
DS70005425A-page 337
PIC32MZ W1 and WFI32E01 Family
DS70005425A-page 338
Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
## 24.0 UART
- UART To enable High-speed mode on UART1, CFGCON1.HSUARTEN register bit needs to be set.
- Note: This data sheet summarizes the features UART2 and UART3 are only available through PPS of the PIC32MZ W1 family of devices. It is pads (I/O remap), therefore can achieve up to 5 Mbps not intended to be a comprehensive speed. reference SOUICE. To complement the The primary features of theUART module are: Sectioninformation21.in“UART”this data(DS60001107)sheet, refer toin + Full-duplex, 8-bit; or 9-bit; data transmission. the “PIC32 Family Reference Manual”, ¢ Even, odd or no parity options (for 8-bit data) which is available from the Microchip web * One or two stop bits Site Guwncmieroehipcon Ies2). ¢ Hardware flow control option with CTS and RTS
- Universal Asynchronous Receiver Transmitter pins module is one of the serial I/O modules avail¢ Fully integrated baud rate generator with 16-bit
- in the PIC32MZ W1 W1 family of devices. The UART prescaler
- full-duplex, asynchronous communication channel channel * Supports Up to 10 Mbps communicates with peripheral devices and per; ; ; computers through protocols, such as RS-232, Note: Baud clock of 160 MHz is required to obtain LIN, and IrDA®. The module also supports 10 Mbps speed.
- hardware flow control option, with UxCTS ¢ Four clock source inputs, asynchronous UxRTS pins, and also includes an IrDA encoder clocking decoder. * 8-character deep transmit data buffer device has three UART modules (UART 1-3). ¢ 8-character deep receive data buffer supports high-speed operation up to 10 Mbps . : . :
- fOrPPS pins. On|PPS pins UART (143) speed is Parity, framing and buffer sialiies error detection to 5 Mbps. All three UARTs are capable of 2-pin 2-pin * IrDA encoder and decoder logic UxRX) or 4-pin 4-pin (UxRX, UxTX, UxRTS, UxCTS) * 16x baud clock output for IrDA support * Support for interrupt on address detect
- 24-1: UART SIMPLIFIED BLOCK DIAGRAM PB1_CL o a ae S<]— Hardware | LX] UxRTSIBCLKx Flow Control | OE ~
- Se ai DX] UxcTs
The Universal Asynchronous Receiver Transmitter (UART) module is one of the serial I/O modules avail¢ able in the PIC32MZ W1 W1 family of devices. The UART isa full-duplex, asynchronous communication channel channel * that communicates with peripheral devices and personal computers through protocols, such as RS-232, RS-485, LIN, and IrDA®. The module also supports the hardware flow control option, with UxCTS ¢ and UxRTS pins, and also includes an IrDA encoder and decoder. * The device has three UART modules (UART 1-3). ¢ UART1 supports high-speed operation up to 10 Mbps . 6h fOrPPS pins. On|PPS pins UART (143) speed is limited to 5 Mbps. All three UARTs are capable of 2-pin 2-pin * (UxTX, UxRX) or 4-pin 4-pin (UxRX, UxTX, UxRTS, UxCTS) * operation. * FIGURE 24-1: UART SIMPLIFIED BLOCK DIAGRAM
Note 1: The PB clock PB1_CLK is used by UART3. The PB clock PB3_CLK is used by UART1 and UART2.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 339
## seman
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PIC32MZ W1 and WFI32E01 Family
## smn
## REGISTER 24-1: UxMODE: UARTx MODE REGISTER
|Bit|Bit|Bit|Bit|Bit<br>Bit<br>Bit||Bit|Bit|
|---|---|---|---|---|---|---|---|
|Range|| 31/23/15/7|30/22/14/6|29/21/13/5 |28/20/12/4|27/19/11/3 | 26/18/10/2||||25/17/9/1||24/16/8/0|
|UM|(Fa|=||=||=||
|‘8|[sen [actve||[| — ||— | — |<br>akseiao||||ovros ||
|8|on [=||sien [atsmo[||||CUNO||
|,||||||||
|Legend:||||||||
|R = Readable bit|||W = Writable bit|U = Unimplemented bit, read|as|‘0’||
|-n = Value at POR|||‘{’=Bitis setat|Reset<br>‘0’ = Bit is cleared at Reset||||
|HC=HardwareCleared|||HS=Hardware|Set<br>x=BitisunknownatReset||||
Example: R/W - 0 indicates the bit is both readable and writable, and reads ‘0’ after a Reset.
bit 31-24 Unimplemented: Read as ‘0’
- bit 23 SLPEN: Run during Sleep Enable bit 1 = UART BRG clock runs during Sleep mode
- 0 =UART BRG clock is turned off during Sleep mode
- Note: This assumes that the UART is not driven by system clock that is turned off during sleep.
- bit 22 ACTIVE: UART Running Status bit 1 = UART clock request is active
- 0 = UART clock request is not active
- bit 21-19 Unimplemented: Read as ‘0’
- bit 18-17 CLK_SEL: UARTx Baud Clock Selection bits 11 = UART BRG clock is the external REFO1 clock. 10 = UART BRG clock is the external FRC clock. 01 =UART BRG clock is the external SYS clock. 00 = UART BRG clock is the internal UPBM clock
- Note 1: These bits can only be changed when UxMODE.ON = 0.
- 2: Aclock frequency of 160 MHz is required for obtaining 10 Mbps speed.
- bit 16 OVFDIS: Run during Overflow Condition Mode bit 1 = When OERR is detected, shift register continues to run to remain synchronized 0 = When OERR is detected, shift register stops accepting new data
- bit 15 ON: UARTx Enable bit
- 1 = UARTx is enabled; UARTx pins are controlled by UARTx as defined by UEN<1:0> and UTXEN control bits.
- 0 = UARTx is disabled; all VARTx pins are controlled by corresponding bits in the control bits PORTx, TRISx and LATx registers; UARTx power consumption is minimal.
- bit 14 Unimplemented: Read as ‘0’
- bit 13 SIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode
- Note 1: These bits are present for legacy compatibility, and are superseded by PPS functionality on these devices. For additional information, see Section 13.4 “Peripheral Pin Select (PPS)”.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 341
## PIC32MZ W1 and WFI32E01 Family
## seman
|REGISTER 24-1:<br>UxMODE: UARTx MODE REGISTER (CONTINUED)|REGISTER 24-1:<br>UxMODE: UARTx MODE REGISTER (CONTINUED)|||
|---|---|---|---|
|bit 12|IREN: IrDA Encoder and Decoder Enable bit|||
||1<br>= IrDA enabled|||
||0<br>= IrDA disabled|||
||Note:<br>This feature is only available for Standard mode (UXMODE.BRGH=|‘0’).||
|bit 11|RTSMD: Mode Selection for UxRTS Pin bit|||
||1 =UxRTS pin in Simplex mode|||
||0<br>= UxRTS pin in Flow Control mode|||
|bit 10|Unimplemented: Read as ‘0’|||
|bit9-8|| UEN<1:0>: UARTx Enable bits!)|||
||11<br>= UxTX, UxRX and UxBCLK pins are enabled and used; UxCTS pin is controlled by corresponding bits|||
||in the PORTx register|||
||10<br>= UxTX, UxRX, UxCTS and UxRTS pins are enabled and used|||
||01<br>=UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by corresponding bits|||
||in the PORTX register|||
||00 =UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/UxBCLK pins are controlled by cor-|||
||responding bits in the PORTx register|||
|bit 7|WAKE: Enable Wake-up on Start bit Detect During Sleep Mode bit|||
||1<br>= Wake-up is enabled|||
||0<br>= Wake-up is disabled|||
||Note:<br>Hardware clear has priority over software.|||
|bit 6|LPBACK: UARTx Loopback Mode Enable bit|||
||1<br>= Enabled|||
||0<br>= Disabled|||
|bit 5|ABAUD: Auto Baud Enable bit|||
||1<br>= Enable baud rate measurement on the next character — requires reception|of|a SYNCH field (55h);|
||cleared in hardware upon completion|||
||0<br>= Baud rate measurement disabled or completed|||
|bit 4|RXINV: Receive Polarity Inversion bit|||
||1<br>= RX Idle state is ‘0’|||
||0<br>= RX Idle state is ‘1’|||
|bit 3|BRGH: High Baud Rate Enable bit|||
||1<br>= UxBRG generates 4 shift clocks per bit period (4x baud clock, High-speed mode)|||
||0<br>= UxBRG generates 16 shift clocks per bit period (16x baud clock, Standard|mode)||
|bit 2-1|PDSEL<1:0>: Parity and Data Selection bits|||
||11 = 9-bit data, no parity|||
||10 = 8-bit data, odd parity|||
||01 = 8-bit data, even parity|||
||00 = 8-bit data, no parity|||
|bit 0|STSEL: Stop Selection bit|||
||1 = 2 Stop bits|||
||0 =<br>1 Stop bit|||
|Note|1:<br>These bits are present for legacy compatibility, and are superseded by PPS functionality on these devices.|||
||Foradditionalinformation,seeSection13.4“PeripheralPinSelect(PPS)”.|||
renner eee e rereerence eee eee DS70005425A-page 342 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
## REGISTER 24-2: UxSTA: UARTx STATUS AND CONTROL REGISTER
Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 25/17/9/1 24/16/8/0 ise [ee awe Tawa ave fewone [awe Pa Fa ng ee eee ene ee | pe fe fo Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘{’=Bitis setat Reset ‘0’= Bit is cleared at Reset HC = Hardware Cleared HS = Hardware Set x = Bit is unknown at Reset
Example: R/W - 0 indicates the bit is both readable and writable, and reads ‘0’ after a Reset.
- bit 31-24 MASK<7:0>: Address Match Mask bits
- Used to mask the UxSTAT.ADM_ADDRJ7:0] bits. For ADM_MASK[In]: 1 =ADM_ADDR)Jn] is used to detect the address match 0 =ADM_ADDR)Jn] is not used to detect the address match
- bit 23-16 ADDR<7:0>: Address Detect Task Offload bits
- Used with UxSTAT.ADM_EN to offload the task of detecting the address character from the processor during Address Detect mode.
- bit 15-14 UTXISEL<1:0>: Transmission Interrupt Mode Selection bits
- 11 = Reserved, do not use
- 10 = Interrupt is persistent when the transmit buffer is empty
- (The Transmit Shift register may or may not be empty.)
- 01 = Interrupt is persistent when both the transmit buffer and Transmit Shift register are empty
- (This indicates that all characters have been transmitted).
- 00 = Interrupt is persistent when the transmit buffer is not full
- (This means there is space for at least one character in the transmit buffer).
- bit 13 UTXINV: Transmit Polarity Inversion bit If UxMODE.IREN = 0:
1 = TX ldle state is ‘0’
- 0 = TX Idle state is ‘1’
- If UXMODE.IREN = 1:
1 = IrDA encoded TX Idle state is ‘1’ 0 = IrDA encoded TX Idle state is ‘0’
- bit12 —_URXEN: Receive Enable bit")
- 1 = Receive enabled, characters seen on the RX pin and captured by the UARTx 0 = Receive disabled, the RX pin is ignored by the UARTx. RX pin is controlled by PORT.
- bit11 — UTXBRK: Transmit Break bit 1 = Send SYNCH BREAK on next transmission — Start bit, followed by twelve ‘0’ bits, followed by Stop bit; cleared by hardware upon completion 0 = SYNCH BREAK transmission disabled or completed
- bit10 = UTXEN: Transmit Enable bit
- 1 = UARTX transmitter is enabled. UxTX pin is controlled by UARTx (if ON = 1)
- 0 = UARTX transmitter is disabled. Any pending transmission is aborted and buffer is reset
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 343
## PIC32MZ W1 and WFI32E01 Family
## seman
|REGISTER 24-2:<br>UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)|REGISTER 24-2:<br>UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)|REGISTER 24-2:<br>UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)|
|---|---|---|
|bit 9|UTXBF: Transmit Buffer Full Status bit||
||1<br>=|Transmit buffer is full|
||0<br>=|Transmit buffer is not full, at least one more character can be written|
|bit 8|TRMT: Transmit Shift Register Empty bit||
||1<br>=|Transmit shift register is empty and transmit buffer is empty (The last transmission has completed)|
||0 =|Transmit shift register is not empty, a transmission is in progress or queued|
|bit7-6|URXISEL<1:0>: Receive Interrupt Mode Selection bit||
||11|= Reserved, do not use|
||10|= Interrupt is persistentwhen the receive buffer has 6 or more data characters|
||01|= Interrupt is persistentwhen the receive buffer has 4 or more data characters|
||00|=Interrupt ispersistent<br>when the receive bufferhas 1 ormoredata characters (in otherwords, notempty)|
|bit 5|ADDEN: Address Character Detect bit (Bit 8 of received data = 1)||
||1 =|Address Detect mode is enabled. If 9-bit mode is not selected, this control bit has no effect.|
||0 =|Address Detect mode is disabled|
|bit 4|RIDLE: Receiver Idle bit||
||1 =|Receiver is idle|
||0 =|Receiver is active|
|bit 3|PERR: Parity Error Status bit||
||1 =|Parity error has been detected for the current character (Character at the top ofthe receive FIFO)|
||0 =|Parity error has not been detected|
|bit 2|FERR: Framing Error Status bit||
||1 =|Framing error has been detected for the current character (Character at the top of the receive FIFO)|
||0 =|Framing error has not been detected|
|bit 1|OERR: Receive Buffer Overrun Error Status bit||
||1 =|Receive buffer has overflowed|
||0 =|Receive buffer has not overflowed|
||Note<br>1: When RUNOVF=<br>0, clearing a previously setOERR bit (1 ? 0 transition) resets the receiver buf-||
|||fer and the RSR to the empty state.|
|||2: When RUNOVF=<br>1, clearing a previously set OERR bit (1 ? 0 transition) does not reset the|
|||receive buffer or RSR.|
|bit 0|URXDA: Receive Buffer Data Available bit||
||1 =|Receive buffer has data, at least one more character can be read|
||0=|Receivebufferisempty|
Note 1: Clearing UxSTAT.RXEN will not reset the receive buffer. Clearing UxMODE.ON will reset the receive buffer.
renner eee e rereerence eee eee DS70005425A-page 344 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
## 24.2 Receive and Transmit Timing for UART Module
Figure 24-2 and Figure 24-3 illustrate the typical receive and transmit timing for the UART module.
**==> picture [495 x 526] intentionally omitted <==**
**----- Start of picture text -----**<br>
FIGURE 24-2: UART RECEPTION<br>IIIl<br>|Char 1 | Char 2-4 | | Char 5-10 | Char 11-13 |<br>I I I I I I<br>Read to 5 5 5 5 | |<br>UxRXREG<br>Start 1 Stop Start 2 Stop 4 Start5 — Stop 10 Start 11 Stop 13<br>URX — XX XXX><br>RIDLE a a<br>Cleared by<br>OERR aff Software<br>7395 Cleared by<br>UxRXIF ee ee rn ee \ rs a «(Software<br>URXISEL = 00<br>Cleared by<br>ia Software<br>UxRXIF ee %<br>URXISEL = 01<br>UxRXIF ee ge le rs<br>URXISEL = 10<br>FIGURE 24-3: UART TRANSMISSION (8-BIT OR 9-BIT DATA)<br>8 into TxBUF<br>Write to<br>UxTXREG<br>TSR<br>BCLK/16 7 TT Pull from Buffer<br>(Shift Clock) \<br>UxTX ) XX [_Stop]<br>UTXISELUxTXIF = 00 ya Va<br>UTXISELUxTXIF.= 01 ———,a<br>UxTXIF ———<br>UTXISEL = 10 a<br>**----- End of picture text -----**<br>
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 345
PIC32MZ W1 and WFI32E01 Family
DS70005425A-page 346
Preliminary Data Sheet © 2020 Microchip Technology Inc.
## PIC32MZ W1 and WFI32E01 Family smn 25.0 REAL-TIME CLOCK AND ¢ Alarm intervals are configurable for half of of a second, CALENDAR (RTCC) one second, 10 seconds, one seconds, one one minute, 10 minutes,
- ¢ Alarm intervals are configurable for half of of a second, one second, 10 seconds, one seconds, one one minute, 10 minutes, one hour, one day, one week, one month, and one year.
- ¢ Alarm repeat with decrementing counter ¢ Alarm with indefinite repeat: Chime * Year range: 2000-2099 » Leap year correction ¢« BCD format for smaller firmware. overhead * Optimized for long-term battery operation * Fractional second synchronization * User calibration of the clock frequency with parinelic euke-celluet
- ° See within £2.64 seconds error per month * Calibrates up to 260 ppm of crystal error ¢ Uses external 32.768 kHz crystal or 32.768 kHz internal oscillator
- Note: This data sheet summarizes the features of the PIC32MZ W1 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 29. “Real-Time Clock and Calendar (RTCC)” (DS60001125) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
- The RTCC module is intended for applications in which accurate time must be maintained for extended periods of time with minimal or no CPU intervention. Lowpower optimization provides extended battery lifetime while keeping track of time.
The following are key features of the the RTCC module:
- The following are key features of the the RTCC module: * Alarm pulse or seconds clock output on RTCC pin * Time: hours, minutes, and seconds The RTCC reference clock is obtained from either the + 24-hour format (military time) SOSC or LPRC oscillator. The user is responsible to . Visibility of half d _ enable the oscillator using the OSCCON[SOSCEN] bit isi Hliy-o one-half second perio if the SOSC is used.
- ¢ Provides calendar: weekday, date, month, and year
**==> picture [201 x 8] intentionally omitted <==**
**----- Start of picture text -----**<br>
FIGURE 25-1: RTCC BLOCK DIAGRAM<br>**----- End of picture text -----**<br>
**==> picture [430 x 303] intentionally omitted <==**
**----- Start of picture text -----**<br>
RTCCLKSEL<1:0><br>32.768 kHz Input from :<br>Secondary Oscillator (SOSC)<br>32.768 kHz Input from —><br>Internal Oscillator (LPRC) TRTC<br>ee eee | |<br>| | |<br>[ercotiner<br>| Jeera RTCA | p><br>| Aa Z |<br>Event<br>!_<br>|1 |<br>| ALRMVAL |<=> WKDAY<br>| | | | HR, MIN, SEC<br>| [Repeat ouer Jee!|||<br>| : RTCC Interrupt<br>|| RTCC Interrupt Logic Algom Pulse S NZxX<br>RTCC Pin<br>| | RTCOE<br>bee ees|<br>RTCOUTSEL<1:0><br>**----- End of picture text -----**<br>
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 347
## seman
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|DS70005425A-page348<br>PreliminaryDataSheet|©2020MicrochipTechnologyInc.|
PIC32MZ W1 and WFI32E01 Family
smn
REGISTER 25-1: RTCCON: REAL-TIME CLOCK AND CALENDAR CONTROL REGISTER
|Bit|Bit||Bit|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit|
|---|---|---|---|---|
|Range|31/23/15/7|30/22/14/6|||29/21/13/5| 28/20/12/4 |27/19/11/3 |26/18/10/2|25/17/9/1<br>24/16/8/0|
|“St**o**|=|||=|| = | =<br>| =<br>| = J<br>case|
|||||||
|8|[wt|||soarcs<br>[rrcoursere® ||
|°|_[Rrcourser<o>@[Rrcctxon®<br>| — | — | RTOWREN®| RTcsyNc [HALrsEC®] RTCOE |||||
|Legend:|||||
|R = Readable bit||||W = Writable bit<br>U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR||||‘1’=Bitisset<br>‘0’=Bitiscleared<br>x=Bitisunknown|
## bit 31-26 Unimplemented: Read as ‘0’
bit 25-16 CAL<9:0>: Real-Time Clock Drift Calibration bits, which contain a signed 10-bit integer value 0111111111 = Maximum positive adjustment, adds 511 real-time clock pulses every one minute
0000000001 = Minimum positive adjustment, adds 1 real-time clock pulse every one minute 0000000000 = No adjustment 1111111111 = Minimum negative adjustment, subtracts 1 real-time clock pulse every one minute
- 1000000000 = Maximum negative adjustment, subtracts 512 real-time clock pulses every one minute
- bit15 | ON: RTCC On bit!)
- 1 = RTCC module is enabled 0 = RTCC module is disabled
- bit 14 Unimplemented: Read as ‘0’ bit13 SIDL: Stop in Idle Mode bit 1 = Disables RTCC operation when CPU enters Idle mode 0 = Continue normal operation when CPU enters Idle mode
bit 12-11 Unimplemented: Read as ‘0’
- bit 10-9 RTCCLKSEL<1:0>: RTCC Clock Select bits When a new value is written to these bits, the Seconds Value register should also be written to properly reset the clock prescalers in the RTCC. 11 = Reserved 10 = Reserved 01 =RTCC uses the external 32.768 kHz SOSC 00 = RTCC uses the internal 32.768 kHz LPRC
- Note 1: The ON bit is only writable when RTCWREN = 1. 2: Requires RTCOE = 1 (RTCCON<O>) for the output to be active.
- 3: The RTCWREN bit can be set only when the Write sequence is enabled.
- 4: This bit is read-only. It is cleared to ‘0’ on a write to the seconds bit fields (RTCTIME<14:8>).
- 5: This bit is undefined when RTCCLKSEL<1:0> = 00 (LPRC is the clock source). 6: This register is reset only on a POR.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 349
## PIC32MZ W1 and WFI32E01 Family
## seman
|REGISTER 25-1:<br>RTCCON: REAL-TIME CLOCK AND CALENDAR CONTROL REGISTER|REGISTER 25-1:<br>RTCCON: REAL-TIME CLOCK AND CALENDAR CONTROL REGISTER|REGISTER 25-1:<br>RTCCON: REAL-TIME CLOCK AND CALENDAR CONTROL REGISTER|
|---|---|---|
|||(CONTINUED)|
|bit 8-7||RTCOUTSEL<1:0>: RTCC Output Data Select bits!)|
|||11 = Reserved|
|||10 = Reserved|
|||01 = Seconds Clock is presented on the RTCC pin|
|||00 = Alarm Pulse is presented on the RTCC pin when the alarm interrupt is triggered|
|bit 6||RTCCLKON: RTCC Clock Enable Status bit"®)|
|||1 = RTCC Clock is actively running|
|||0 = RTCC Clock is not running|
|bit 5-4||Unimplemented: Read as ‘0’|
|bit 3||RTCWREN: Real-Time Clock Value Registers Write Enable bit'*)|
|||1 = Real-Time Clock Value registers can be written to by the user|
|||0 = Real-Time Clock Value registers are locked outfrom being written to by the user|
|bit 2||RTCSYNC: Real-Time Clock Value Registers Read Synchronization bit|
|||1 = Real-time clock value registers can change while reading (due to a rollover ripple that results in an invalid|
|||data read). Ifthe register is read twice and results in thesame data, the data can be assumed to be valid.|
|||0 = Real-time clock value registers can be read without concern abouta rollover ripple|
|bit 1||HALFSEC: Half-Second Status bit'4)|
|||1 = Second half period of a second|
|||0 =<br>First half period of<br>a second|
|bit 0||RTCOE: RTCC Output Enable bit|
|||1 = RTCC output is enabled|
|||0 = RTCC output is disabled|
|Note|1:|TheON bit is only writable when RTCWREN=<br>1.|
||2:|Requires RTCOE = 1 (RTCCON<O>) for the output to be active.|
||3:|The RTCWREN bit can be set only when the Write sequence is enabled.|
||4:|This bit is read-only. It is cleared to ‘0’ on a write to the seconds bit fields (RTCTIME<14:8>).|
||5:|This bit is undefined when RTCCLKSEL<1:0> = 00 (LPRC is the clock source).|
||6:|ThisregisterisresetonlyonaPOR.|
renner eee e rereerence eee eee DS70005425A-page 350 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
## REGISTER 25-2: RTCALRM: REAL-TIME CLOCK ALARM CONTROL REGISTER
|Bit<br>Bit<br>Bit|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit|
|---|---|
|a<br>ee<br>ee<br>Pawo | Rwo <br>15:8<br>186 aneneer cree|es<br>ee<br> | rwo |<br>Ro | Rwo | Ro | Rwo | RWO |<br> — pet [aesaS|
|Legend:||
|R = Readable bit|W = Writable bit<br>U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR|‘1’=Bitisset<br>‘0’=Bitiscleared<br>x=Bitisunknown|
## bit 31-16 Unimplemented: Read as ‘0’ bit15 | ALRMEN: Alarm Enable bit*-2)
- 1 = Alarm is enabled 0 = Alarm is disabled
- bit14. | CHIME: Chime Enable bit(?)
- 1 = Chime is enabled — ARPT<7:0> is allowed to rollover from 0x00 to OxFF
- 0 = Chime is disabled - ARPT<7:0> stops once it reaches 0x00
- bit13 PIV: Alarm Pulse Initial Value bit'2) When ALRMEN= 0, PIV is writable and determines the initial value of the Alarm Pulse. When ALRMEN= 1, PIV is read-only and returns the state of the Alarm Pulse.
- bit 12 ALRMSYNC: Alarm Sync bit
- 1 = ARPT</7:0> and ALRMEN may change as a result of a half second rollover during a read. The ARPT must be read repeatedly until the same value is read twice. This must be done since multiple
- bits may be changing.
- 0 = ARPT<7:0> and ALRMEN can be read without concerns of rollover because the prescaler is more than 32 real-time clocks away from a half-second rollover
- bit 11-8 AMASK<3:0>: Alarm Mask Configuration bits'?)
- 0000 = Every half-second
- 0001 = Every second
- 0010 = Every 10 seconds
- 0011 = Every minute
- 0100 = Every 10 minutes
- 0101 = Every hour
- 0110 = Once a day
- 0111 = Once a week
- 1000 = Once a month
- 1001 = Once a year (except when configured for February 29, once every four years) 1010 = Reserved
- 1011 = Reserved 11xx = Reserved
- Note 1: Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT<7:0> = 00 and CHIME = 0.
- 2: This field should not be written when the RTCC ON bit = ‘1’ (RTCCON<15>) and ALRMSYNC= 1. 3: This register is reset only on a POR.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 351
PIC32MZ W1 and WFI32E01 Family
## seman
REGISTER 25-2: RTCALRM: REAL-TIME CLOCK ALARM CONTROL REGISTER (CONTINUED) bit 7-0 | ARPT<7:0>: Alarm Repeat Counter Value bits!)
11111111 = Alarm will trigger 256 times
- 00000000 = Alarm will trigger one time The counter decrements on any alarm event. The counter only rolls over from 0x00 to OxFF if CHIME = 1.
- Note 1: Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT<7:0> = 00 and CHIME = 0.
- 2: This field should not be written when the RTCC ON bit = ‘1’ (RTCCON<15>) and ALRMSYNC = 1. 3: This register is reset only on a POR.
ES DS70005425A-page 352 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
## REGISTER 25-3: RTCTIME: REAL-TIME CLOCK TIME VALUE REGISTER
**==> picture [446 x 166] intentionally omitted <==**
**----- Start of picture text -----**<br>
Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0<br>a ee<br>Legend:<br>R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’<br>-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared X = Bit is unknown<br>**----- End of picture text -----**<br>
bit 31-28 HR10<3:0>: Binary-Coded Decimal Value of Hours bits, 10 digits; contains a value from 0 to 2 bit 27-24 HR01<3:0>: Binary-Coded Decimal Value of Hours bits, 1 digit; contains a value from 0 to 9 bit 23-20 MIN10<3:0>: Binary-Coded Decimal Value of Minutes bits, 10 digits; contains a value from 0 to 5 bit 19-16 MIN01<3:0>: Binary-Coded Decimal Value of Minutes bits, 1 digit; contains a value from 0 to 9 bit 15-12 SEC10<3:0>: Binary-Coded Decimal Value of Seconds bits, 10 digits; contains a value from 0 to 5 bit 11-8 SEC01<3:0>: Binary-Coded Decimal Value of Seconds bits, 1 digit; contains a value from 0 to 9 bit 7-0 Unimplemented: Read as ‘0’
Note: This register is only writable when RTCWREN = 1 (RTCCON<3>).
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 353
PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 25-4: RTCDATE: REAL-TIME CLOCK DATE VALUE REGISTER
Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0 a a a Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-28 YEAR10<3:0>: Binary-Coded Decimal Value of Years bits, 10 digits bit 27-24 YEAR01<3:0>: Binary-Coded Decimal Value of Years bits, 1 digit bit 23-20 MONTH10<3:0>: Binary-Coded Decimal Value of Months bits, 10 digits; contains a value from 0 to 1 bit 19-16 MONTH01<3:0>: Binary-Coded Decimal Value of Months bits, 1 digit; contains a value from 0 to 9 bit 15-12 DAY10<3:0>: Binary-Coded Decimal Value of Days bits, 10 digits; contains a value from 0 to 3 bit 11-8 DAY01<3:0>: Binary-Coded Decimal Value of Days bits, 1 digit; contains a value from 0 to 9 bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 WDAY01<3:0>: Binary-Coded Decimal Value of Weekdays bits,1 digit; contains a value from 0 to 6
Note: This register is only writable wnen RTCWREN = 1 (RTCCON<3>).
renner eee e rereerence eee eee DS70005425A-page 354 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
## REGISTER 25-5: ALRMTIME: ALARM TIME VALUE REGISTER
Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0 a ee Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-28 HR10<3:0>: Binary Coded Decimal value of hours bits, 10 digits; contains a value from 0 to 2 bit 27-24 HR01<3:0>: Binary Coded Decimal value of hours bits, 1 digit; contains a value from 0 to 9 bit 23-20 MIN10<3:0>: Binary Coded Decimal value of minutes bits, 10 digits; contains a value from 0 to 5 bit 19-16 MIN01<3:0>: Binary Coded Decimal value of minutes bits, 1 digit; contains a value from 0 to 9 bit 15-12 SEC10<3:0>: Binary Coded Decimal value of seconds bits, 10 digits; contains a value from 0 to 5 bit 11-8 SEC01<3:0>: Binary Coded Decimal value of seconds bits, 1 digit; contains a value from 0 to 9 bit 7-0 Unimplemented: Read as ‘0’
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 355
PIC32MZ W1 and WFI32E01 Family
## seman
|REGISTER 25-6:|ALRMDATE: ALARM DATE|ALRMDATE: ALARM DATE|ALRMDATE: ALARM DATE|VALUE REGISTER||
|---|---|---|---|---|---|
|Range | 31/23/15/7|| 30/22/14/6 |29/21/13/5||28/20/12/4 =|27/19/11/3 |26/18/10/2 | 25/17/9/1 | 24/16/8/0|||
|a|a|ee||||
|a|a|a||a||
|Legend:||||||
|R = Readable bit||W = Writable|bit|U = Unimplemented bit, read as ‘0’||
|-n=ValueatPOR||‘1’=Bitisset||‘0’=Bitiscleared|x=Bitisunknown|
bit 31-24 Unimplemented: Read as ‘0’ bit 23-20 MONTH10<3:0>: Binary Coded Decimal value of months bits, 10 digits; contains a value from 0 to 1 bit 19-16 MONTH01<3:0>: Binary Coded Decimal value of months bits, 1 digit; contains a value from 0 to 9 bit 15-12 DAY10<3:0>: Binary Coded Decimal value of days bits, 10 digits; contains a value from 0 to 3 bit 11-8 DAY01<3:0>: Binary Coded Decimal value of days bits, 1 digit; contains a value from 0 to 9 bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 WDAY01<3:0>: Binary Coded Decimal value of weekdays bits, 1 digit; contains a value from 0 to 6
renner eee e rereerence eee eee DS70005425A-page 356 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
## 26.0 ASYMMETRIC CRYPTO ENGINE
The ney iio Gives EOltis prohidies \nalairene acceleration to support Public Key (PK) cryptography functions, needed during authentication and key negotiation sessions. The PK Crypto Engine is based on a scalable array of dual-field processing elements that can be used to execute all operations and algorithms required for PK crypto-systems.
The Asymmetric Crypto Engine supports the following:
- Algorithms
- 256/512-bit crypto engines
- °° Elliptic-curveiit curve viecryptographyvaline ecbH)(ECC aa mene
- . Elliptic Curve Digital Signature Algorithm
- - 256-bit Ed25519
- ¢ Applications:
- Digital signature applications
- - Digital right management
- IPSec - Internet Key Exchange (IKE)
- Transport Layer Security/Secure Sockets Layer (TLS/SSL) gateways
- The following are key features of the Asymmetric Crypto Engine: yP g -
- Supports microcode based sequence
- ¢ Dedicated DMA for write back from crypto memory to shared memory
- Flexible microcode update using the crypto engine SRAM
The asymmetric crypto module interfaces with three memory modules as shown in Table 26-1.
**==> picture [203 x 71] intentionally omitted <==**
**----- Start of picture text -----**<br>
RBBEE GH ASVMMEIRE Carle<br>MEMORIES<br>Shared Crypto RAM 304 (Words) x 64 (Bits)<br>(SCM)<br>**----- End of picture text -----**<br>
1440 (Words) x 18 (Bits) Tightly coupled memory 256 (Words) x 64 (Bits)
- Key exchange protocol
## FIGURE 26-1: ASYMMETRIC CRYPTO ENGINE BLOCK DIAGRAM
**==> picture [459 x 385] intentionally omitted <==**
**----- Start of picture text -----**<br>
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## PIC32MZ W1 and WFI32E01 Family
## seman
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|rennereeeerereerence<br>eee||eee|
|DS70005425A-page358<br>PreliminaryDataSheet||©2020MicrochipTechnologyInc.|
PIC32MZ W1 and WFI32E01 Family
## smn
## REGISTER 26-1: PKCONFIG: PUBLIC KEY CRYPTO ENGINE CONFIGURATION REGISTER
|Bit<br>Bit|Bit<br>Bit|Bit|Bit|Bit|Bit|Bit|
|---|---|---|---|---|---|---|
|Range | 31/23/15/7 ||30/22/14/6 | 29/21/13/5 ||28/20/12/4 |27/19/11/3 | 26/18/10/2 | 25/17/9/1||||| 24/16/8/0|
|eeee<br>23:16a|ee|ee<br>aa|||||
|i<br>a|a||||||
|i|Cn||||||
|Legend:|||||||
|R = Readable bit|W = Writable|bit|U = Unimplemented bit, read as ‘0’||||
|-n=ValueatPOR|‘1’=Bitisset||‘0’=Bitiscleared||x=Bitisunknown||
- bit 31-21 Unimplemented: Read as ‘0’
- bit 20-16 OPPTRC<4:0>: Operand Pointer C(1:2) When executing primitive arithmetic operations, this pointer defines the location where the result is stored in memory.
- bit 15-13 Unimplemented: Read as ‘0’
- bit 12-8 OPPTRB<4:0>: Operand Pointer B{"-2) When executing primitive arithmetic operations, this pointer defines where operand B is located in memory.
- bit 7-5 Unimplemented: Read as ‘0’ bit4-0 | OPPTRA<4:0>: Operand Pointer A't:2) When executing primitive arithmetic operations, this pointer defines where operand A is located in memory.
- Note 1: When executing primitive arithmetic operations, pointers define locations where operands and results are stored in the shared crypto memory. Even locations only can be accessed with pointers. Relationship between pointers and location numbers: OpPtr[4:0] = LocationNumber[4:0]
- Depending on the operand size, pointers are mapped to corresponding addresses: OpPtr[4:0] = A[9:5] in 256-bit configuration OpPtr[4:0] = A[10:6] in 512-bit configuration OpPtr[4:0] = A[11:7] in 1024-bit configuration OpPtr[4:0] = A[12:8] in 2048-bit configuration OpPtr[4:0] = A[13:9] in 4096-bit configuration
- 2: DH supports only up to 512-bit configuration.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 359
PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 26-2: PKCOMMAND: PUBLIC KEY CRYPTO ENGINE COMMAND REGISTER
**==> picture [450 x 167] intentionally omitted <==**
**----- Start of picture text -----**<br>
Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0<br>| ste [tees [one —| ron |<br>a a es<br>Legend:<br>R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’<br>-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown<br>**----- End of picture text -----**<br>
- bit 31 CALCR2:
This bit indicates if the module has to calculate R? mod N for the next operation. This bit must be set to '1' when a new prime number has been programmed. This bit is automatically cleared when R? mod N has been calculated.
- 1 = Forces the module to re-calculate R? mod N
- 0 = No effect
- bit 30 SIGNB: Sign of parameter B in equation y2 = x3+Ax+B 1 =B is negative 0 = Bis positive
bit 29 SIGNA: Sign of parameter Ain equation y2 = x3+Ax+B 1 =Ais negative
- 0 =Ais positive
bit 28-16 Unimplemented: Read as ‘0’
renner eee e rereerence eee eee DS70005425A-page 360 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
## REGISTER 26-2: PKCOMMAND: PUBLIC KEY CRYPTO ENGINE COMMAND REGISTER (CONTINUED)
- bit 15-8 OPSIZE<7:0>: Size of operands in shared crypto memory
- This field defines the size (= number of 64-bit double words) of the operands for the current operation. Possible values are limited by the maximum supported operand size. Arbitrary data/key size from 128 up to 4096 are supported: 0x02 (02d) ? 128-bit Data/Key size
## 0x40 (64d) ? 4096-bit Data/Key size
## RSA-DSA:
* 0x10 ? 1024-bit RSA-DSA
- 0x20 ? 2048-bit RSA-DSA
- 0x40 ? 4096-bit RSA-DSA
> ECC-ECDSA- Prime Field F(p)
* 0x04 ? 256-bit (Curves P-192, P-224 and P-256)
- 0x06 ? 384-bit (Curve P-384)
- Ox0A ? 640-bit (Curve P-521)
- ECC-ECDSA- Binary Field F(2m)
- 0x04 ? 256-bit (Curve K-163 and K-233)
- 0x06 ? 384-bit (Curve K-283)
- ¢ 0x08 ? 512-bit (Curve K-409)
- Ox0A ? 640-bit (Curve K-571)
## Curve25519-Ed25519:
- ¢ 0x04 ? 256-bit
Note:
Depending on the configuration, the following sizes are supported:
- ¢ 4 Xers: 0x01, 0x02, 0x4, Ox6... ? 64, 128 and multiples of 128 bits
- 16 Xers: 0x01, 0x02, 0x4, Ox8... ? 64, 128, 256 and multiples of 256 bits
- 64 Xers: 0x02, 0x04, Ox8, 0x10... ? 128, 256, 512 and multiples of 512 bits
- ¢ 256 Xers: 0x04, 0x08, 0x10, 0x20... ? 256, 512, 1024 and multiples of 1024 bits, except 256 bits exponentiation based operations (RSA, CRT, DSA, RM and Ed25519) which are not supported
bit 7
## FIELD:
- 0 = Field is F(p)
- 1 = Field is F(2m)
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 361
## PIC32MZ W1 and WFI32E01 Family
## seman
REGISTER 26-2: PKCOMMAND: PUBLIC KEY CRYPTO ENGINE COMMAND REGISTER (CONTINUED) bit6-O OPERATIONK<6:0>: Primitive Arithmetic Operations F(p) and F(2m) [6:4] = 0x0 [3:0] = 0x0 ? Reserved 0x1 ? Modular Addition C =A +B mod N 0x2 ? Modular Subtraction C =A- B mod N 0x3 ? Modular Multiplication (Odd N) C =A* B mod N 0x4 ? Modular Reduction (Odd N) C = B mod N 0x5 ? Modular Division (Odd N) C = A/B mod N Ox6 ? Modular Inversion (Odd N) C = 1/B mod N 0x7 ? Reserved 0x8 ? Multiplication (F(p) only) C =A*B Ox9 ? Modular Inversion (Even N and F(p) only)) C = 1/B mod N OxA ? Modular Reduction (Even N and F(p) only) others ? Reserved C=BmodN High-level RSA, CRT and DSA Operations - F(p) only ([7] forced to '0') [6:4] = 0x1 [3:0] = 0x0 ? Modular Exponentiation (C=A*B mod N) 0x1 ? Private Key Generation 0x2 ? CRT - Key Parameter Generation 0x3 ? CRT - Decryption 0x4 ? RSA - Encryption 0x5 ? RSA - Decryption 0x6 ? RSA - Signature Generation Ox7 ? RSA - Signature Verification 0x8 ? DSA - Key Gen 0x9 ? DSA - Signature Generation OxA ? DSA - Signature Verification OxC ? SRP - Client session key generation others ? Reserved
renner eee e rereerence eee eee DS70005425A-page 362 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
## REGISTER 26-2: PKCOMMAND: PUBLIC KEY CRYPTO ENGINE COMMAND REGISTER (CONTINUED)
Primitive ECC and Check Point Operations F(p) and F(2m) [6:4] = 0x2 [3:0] = 0x0 ? Point Doubling (Projective coordinates) 0x1 ? Point Addition (Projective coordinates) Ox2 ? Point Multiplication (Projective coordinates) 0x3 ? Check_AB (ECDSA) 0x4 ? Check_n (ECDSA) 0x5 ? Check_Couple_Less_Prime (ECDSA) 0x6 ? Check_Point_On_Curve Ox7 ? Reserved Ox8 ? Curve25519 Point Multiplication 0x9 ? Ed25519 Xrecover OxA ? Ed25519 ScalarMult OxB ? Ed25519 CheckValid OxC ? Check_Point_On_Curve Ed25519 others ? Reserved
High-level ECC - ECDSA Operations F(p) and F(2m) [6:4] = 0x3 [3:0] = High-level ECC - ECDSA Operations F(p) and F(2m) [6:4] = 0x3 [3:0] = 0x0 ? ECDSA- Signature Generation 0x1 ? ECDSA - Signature Verification 0x2 ? ECDSA- Domain Parameters Validation 0x3 ? EC-KCDSA- Public Key Generation 0x4 ? EC-KCDSA - Signature Generation 0x5 ? EC-KCDSA- Signature Verification others ? Reserved [6:4] = 0x4,0x5, 0x6, Ox7 ? Reserved
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 363
## PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 26-3: PKCONTROL: PUBLIC KEY CRYPTO ENGINE CONTROL REGISTER
|Bit<br>Bit|Bit|Bit|Bit|Bit<br>Bit|Bit|Bit|
|---|---|---|---|---|---|---|
|Range | 31/23/15/7|| 30/22/14/6|| 29/21/13/5 | 28/20/12/4|||27/19/11/3 | 26/18/10/2|| 25/17/9/1 | 24/16/8/0||
|—|<br>=|| =|[| = [|=|[| = [| =|[| =|| starr|
|Legend:|||||||
|R = Readable bit||W = Writable bit||U = Unimplemented bit,|read as ‘0’||
|-n=ValueatPOR||‘1’=Bitisset||‘0’=Bitiscleared|X=Bitisunknown||
## bit 31-1 Unimplemented: Read as ‘0’
bit 0 START:
The START signal is activated when all data and key inputs have been loaded in the external Shared Crypto Memory and are available for processing. This signal is active high and is sampled on the rising edge of clock. When this signal goes high, the PK Command present in the PKCOMMAND register is initiated and executed. The START signal is ignored when the core is already processing data and is automatically cleared when the operation is finished.
renner eee e rereerence eee eee DS70005425A-page 364 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family smn
**==> picture [456 x 192] intentionally omitted <==**
**----- Start of picture text -----**<br>
REGISTER 26-4: PKSTATUS: PUBLIC KEY CRYPTO ENGINE STATUS REGISTER<br>Bit Bit Bit Bit Bit Bit Bit Bit Bit<br>Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0<br>EE EE EE Ee ee ee eee sy<br>15:8 Poouo | uo | oT Ro] Ro | Ro | ROT<br>Po | = |= Pie | Noninv | Pasinval | sicinval | — |<br>|<br>Legend:<br>R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’<br>-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown<br>**----- End of picture text -----**<br>
## bit 31-17 Unimplemented: Read as ‘0’
- bit 16 BUSY: This status signal indicates that the core is processing data. This signal is active high and goes low when the This status signal indicates that the core is processing data. This signal is active high and goes low when the selected algorithm is finished.
- bit 15-13 Unimplemented: Read as ‘0’
- bit 12 PRIME: Primality Test Result bit
- After the Miller-Rabin primality test, this flag is:
- Set to 'o' when the random number under test is probably prime
- ¢ Cleared to '1' when the random number under test is composite
- bit 11 NONINV: Not Invertible bit This flag is set to '1' when executing a modular inversion (PKCOMMANDJ[3:0] = 0x6 or 0x9) if the operand is not invertible.
- bit 10 PABINVAL: Status signal set to '1' when parametersA and B are not valid, i.e 4A*+ 27B? = 0. This flag is updated after execution of the Check AB command.
- bit 9 SIGINVAL: This flag indicates if the signature can be accepted or must be rejected. This flag is set to '1' when the signature is not valid and is updated after execution of the ECDSA Generation, ECDSA Verification, DSAGeneration, DSAVerification, and Ed25519 CheckValid commands.
- bit 8 Unimplemented: Read as ‘0’ bit 7 PNINVAL: Status signal set to '1' wnen Parameter n is not valid. This flag is updated after execution of the Check_n command.
- bit 6 CPLINVAL: Status signal set to ''1' when couple x, y is not valid (i.e. not smaller than the prime). This flag is updated after execution of the CheckCoupleLess Prime command.
- bit 5 PXINF: Status signal set to '1' when Point Px is at the infinity. This flag is updated after execution of an ECC operation.
- bit 4 PXNOC: Status signal set to '1' when Point Px is not on the defined EC. This flag is updated after execution of the Check Point OnCurve command.
- bit 3-0 EADDR<3:0>: Fail Address bits Address of the last point detected as not on curve, not valid or at the infinity.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 365
PIC32MZ W1 and WFI32E01 Family
## seman
REGISTER 26-5: PKVERSION: PUBLIC KEY CRYPTO ENGINE VERSION REGISTER
|Bit<br>Bit<br>Bit|Bit|Bit|Bit<br>Bit<br>Bit|Bit|
|---|---|---|---|---|
|Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4||||27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0||
|ee ee eee<br>ee<br>pate SS eo<br>| sePRO<br>yy<br>RO | Ro [ Ro<br>[| <br>:||ee ee<br>ee<br> Ro<br>[| Ro | RO [ RO||| RO ||
|Legend:|||||
|R = Readable bit|W = Writable bit||U = Unimplemented bit, read as ‘0’||
|-n=ValueatPOR|‘1’=Bitisset||‘0’=Bitiscleared<br>x=Bitisunknown||
## bit 31-16 Unimplemented: Read as ‘0’
bit 15-8 HWVER: Hardware Version bits Version of crypto hardware to be read via CPU interface.
- bit 7-0 SWVER: Software Version bits
Version of Crypto software to be read via CPU interface.
renner eee e rereerence eee eee DS70005425A-page 366 Preliminary Data Sheet © 2020 Microchip Technology Inc.
- PIC32MZ W1 and WFI32E01 Family
- smn 27.0 SYMMETRIC CRYPTO ENGINE The Symmetric Crypto Engine processes the data rate on the basis of the following factors:
- Note: This data sheet summarizes the * Which algorithm/engine is in use features of the PIC32MZ W1 family of . . : JE0IGSS. "TH 1S BBE InkeidEd @ be a . Whether the algorithms/engines are used in parallel comprehensive reference source. To SPIN SSeS complement the information in this data * Demand on source and destination memories by sheet, refer to Section 49. “Crypto other parts of the system (CPU, DMA, and so on.) Engine (CE) and Random Number * The speed of PB5_CLK, which drives the Generator (RNG)” (DS60001246) in Symmetric Crypto Engine the “PIC32 Family Reference Manual’, Table 27-1 shows typical performance for various which is available from the Microchip engines. web site (www.microchip.com/PIC32).
- The Symmetric; Crypto Engineoois intended to TABLE 27-1: SYMMETRICPERFORMANCECRYPTO ENGINE accelerate applications that need cryptographic funcmodule, software overhead is reduced and actions, Engine/ Factor Maximum Mbps such as encryption, decryption, and authentication Algorithm | (Mbps/MHz) | (PB5_CLK= 100 MHz) tions.can execute By execm **u** ting thesech more quickly. functions in the hardware Ss The Symmetric Crypto Engine uses an_ internal descriptor-based DMA for efficient programming of [TOES = 66 —t—“‘<‘T COC‘ COC‘*@d the Security Association (SA) data and packet pointJAES-128 /90 |900 | ers (allowing scatter/gather data fetching). An intellilowenginesstatebasedmachineon theschedulesprotocoltheselectionSymmetricand packetCrypto boundaries. The hardware engines can perform the encryption and authentication in sequence or in paralll,
- The following are key features of the Symmetric Crypto Engine: * Bulk ciphers. and hash engines. . Integrated CRDMAto off-load processing:
- Buffer Descriptor (BD) -based
- - Secure association per buffer descriptor
- * Some functions can execute in parallel
Note: When using the engines sequentially, the throughput degrades. Throughput is also negatively affected by other bus activity, specifically if the CPU and/or peripherals have high activity to the same SRAM target as the CRDMA.
Bulk ciphers that are handled by the Symmetric Crypto Engine include:
¢ AES:
- 128-bit, 192-bit, and 256-bit key sizes
- CBC, ECB, CTR, CFB, and OFB modes
- DES/TDES: - CBC, ECB, CFB, and OFB modes
Authentication engines that are available through the Symmetric Crypto Engine include:
- SHA-1
- SHA-256
- ¢ MD-5
- « AES-GCM
- « AES-CBC
- ¢ HMAC operation (for all authentication engines)
- ¢ SFR interface:
- 32-bit Read/Write only
- - No 8-bit or 16-bit access
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 367
PIC32MZ W1 and WFI32E01 Family
FIGURE 27-1: SYMMETRIC CRYPTO ENGINE BLOCK DIAGRAM
**==> picture [374 x 124] intentionally omitted <==**
**----- Start of picture text -----**<br>
INB Packet<br>System FIFO RD<br>Bus<br>DMA Crypto a<br>Controller FSM 8<br>fe} a<br>System<br>FIFO WR<br>PB5_CLK<br>**----- End of picture text -----**<br>
DS70005425A-page 368
Preliminary Data Sheet
© 2020 Microchip Technology Inc.
## smn
**==> picture [459 x 670] intentionally omitted <==**
**----- Start of picture text -----**<br>
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PIC32MZ W1 and WFI32E01 Family
## seman
REGISTER 27-1: CEVER: CRYPTO ENGINE REVISION, VERSION, AND ID REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0 jorge RO SO | sre BP Lee | ke | Oe eee | ise Ret ee |e | ee te ee | ro | Bet ne | ge |e ee | ee [| ne |g Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-24 REVISION<7:0>: Crypto Engine Revision bits bit 23-16 VERSION<7:0>: Crypto Engine Version bits bit 15-0 ID<15:0>: Crypto Engine Identification bits
renner eee e rereerence eee eee DS70005425A-page 370 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
## REGISTER 27-2: CECON: CRYPTO ENGINE CONTROL REGISTER
|Bit<br>Bit|Bit|Bit|Bit<br>Bit<br>Bit<br>Bit<br>Bit|
|---|---|---|---|
|Range | 31/23/15/7 ||30/22/14/6 |29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0|||
|°<br>[swaroen | swrst| swaPen [||||— | — | s0ecusT | BDPPLEN| DMAEN||
|Legend:|||HC = Hardware Cleared|
|R = Readable bit||W = Writable bit|U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR||‘1’=Bitisset|‘0’=Bitiscleared<br>x=Bitisunknown|
- bit 31-8 Unimplemented: Read as ‘0’
- bit 7 SWAPOEN: Swap Output Data Enable bit
- 1 = Output data is byte swapped when written by dedicated DMA 0 = Output data is not byte swapped when written by dedicated DMA
- bit 6 SWRST: Software Reset bit
- 1 = Initiate a software reset of the Crypto Engine 0 = Normal operation
- bit 5 SWAPEN: Input Data Swap Enable bit 1 = Input data is byte swapped when read by dedicated DMA 0 = Input data is not byte swapped when read by dedicated DMA
- bit 4-3 Unimplemented: Read as ‘0’
- bit 2 BDPCHST: Buffer Descriptor Processor (BDP) Fetch Enable bit This bit should be enabled only after all DMA descriptor programming is completed. 1 = BDP descriptor fetch is enabled 0 = BDP descriptor fetch is disabled
- bit 1 BDPPLEN: Buffer Descriptor Processor Poll Enable bit This bit should be enabled only after all DMA descriptor programming is completed.
- 1 = Poll for descriptor until valid bit is set 0 = Do not poll
- bit 0 DMAEN: DMA Enable bit 1 = Crypto Engine DMA is enabled 0 = Crypto Engine DMA is disabled
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 371
## PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 27-3: CEBDADDR: CRYPTO ENGINE BUFFER DESCRIPTOR REGISTER
|Bit<br>Bit<br>Bit|Bit|Bit<br>Bit<br>Bit|Bit<br>Bit|
|---|---|---|---|
|Range | 31/23/15/7 | 30/22/14/6|| 29/21/13/5 | 28/20/12/4 |27/19/11/3 | 26/18/10/2||| 25/17/9/1 | 24/16/8/0|
|SS<br>| aarp | BP Lee | ke | <br>ig FRO T Ro<br>[| ro<br>|||ee eee<br> Ro [ ro | Ro<br>[| Ro [ Ro |||
|7<br>| Ro | ro<br>||[| Ro ||ro [ ro | Ro|[ ro | Ro ||
|Legend:||||
|R = Readable bit|W = Writable bit|U = Unimplemented bit,|read as ‘0’|
|-n=ValueatPOR|‘1’=Bitisset|‘0’=Bitiscleared|X=Bitisunknown|
bit 31-0 _BDPADDR<31:0>: Current Buffer Descriptor Process Address Status bits These bits contain the current descriptor address that is being processed by the BDP.
## REGISTER 27-4: CEBDPADDR: CRYPTO ENGINE BUFFER DESCRIPTOR PROCESSOR REGISTER
|Bit<br>Bit|Bit|Bit<br>Bit|Bit<br>Bit<br>Bit<br>Bit|
|---|---|---|---|
|Range | 31/23/15/7 <br>soeLRM<br>:|| 30/22/14/6 <br>| RM|| 29/21/13/5 | 28/20/12/4 <br>| RM<br>| RW||27/19/11/3 |26/18/10/2 | 25/17/9/1 | 24/16/8/0<br>| RM<br>| RW | RMD | RMCO|
|:||||
|:||||
|:||||
|Legend:||||
|R = Readable bit||W = Writable bit|U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR||‘1’=Bitisset|‘0’=Bitiscleared<br>x=Bitisunknown|
bit31-0 BASEADDR<31:0>: Buffer Descriptor Base Address bits
These bits contain the physical address of the first buffer descriptor in the buffer descriptor chain. When enabled, the Crypto DMA begins fetching buffer descriptors from this address.
renner eee e rereerence eee eee DS70005425A-page 372 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## ee
REGISTER 27-5: CESTAT: CRYPTO ENGINE STATUS REGISTER
|Bit|Bit<br>Bit<br>Bit|Bit|Bit|Bit|Bit<br>Bit|
|---|---|---|---|---|---|
|Range|| 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4|||27/19/11/3 |26/18/10/2|26/18/10/2|| 25/17/9/1 | 24/16/8/0|
|siog<br>||LF ROE RO TRO TROT ROT|||ROT ROT ROT||
|o16 <br>8 <br>ig <br>||Lo |<br>vo | Ro | <br> =<br> FRO | Ro | RO<br>[||Ro<br>[| RO<br>[| <br>ostarecaios<br> RO | RO |||RO<br>[| RO [ RO |<br>start [ACTIVE_|<br>RO | RO<br>[| RO |||
|ro<br>:|(FRO ft Ro | RO [|Ro|| Ro<br>[||RO|{| RO | RO ||
|Legend:||||||
|R = Readable bit<br>W = Writable bit|||U = Unimplemented bit,||read as ‘0’|
|-n=ValueatPOR<br>‘1’=Bitisset|||‘0’=Bitiscleared||x=Bitisunknown|
bit 31-29 ERRMODE<2:0>: Internal Error Mode Status bits
111 = Reserved 110 = Reserved 101 = Reserved 100 = Reserved 011 = CEK operation 010 = KEK operation 001 = Preboot authentication 000 = Normal operation
- bit 28-26 ERROP<2:0>: Internal Error Operation Status bits
111 = Reserved 110 = Reserved 101 = Reserved 100 = Authentication 011 = Reserved 010 = Decryption 001 = Encryption 000 = Reserved
- bit 25-24 ERRPHASE<1:0>: Internal Error Phase of DMA Status bits 11 = Destination data 10 = Source data 01 = Security Association (SA) access 00 = Buffer Descriptor (BD) access
- bit 23-22 Unimplemented: Read as ‘0’
- bit 21-18 BDSTATE<3:0>: Buffer Descriptor Processor State Status bits The current state of the BDP: 1111 = Reserved
0111 = Reserved 0110 = SA[fetch] 0101 = Fetch BDP is disabled 0100 = Descriptor is done 0011 = Data phase 0010 = BDP is loading 0001 = Descriptor fetch request is pending 0000 = BDP is idle bit 17 START: DMA Start Status bit 1 = DMA start has occurred 0 = DMA start has not occurred
## oe
© 2020 Microchip Technology Inc. Preliminary Data Sheet
DS70005425A-page 373
PIC32MZ W1 and WFI32E01 Family
## REGISTER 27-5: CESTAT: CRYPTO ENGINE STATUS REGISTER (CONTINUED)
- bit 16 ACTIVE: Buffer Descriptor Processor Status bit
- 1 = BDP is active
- 0 = BDP is idle
- bit 15-O BDCTRL<15:0>: Descriptor Control Word Status bits These bits contain the Control Word for the current BD.
DS70005425A-page 374
Preliminary Data Sheet
© 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
## REGISTER 27-6: CEINTSRC: CRYPTO ENGINE INTERRUPT SOURCE REGISTER
|Bit|Bit|Bit|Bit|Bit|Bit<br>Bit<br>Bit<br>Bit|
|---|---|---|---|---|---|
|Range|| 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4|||||27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0|
|7||Ro<br>| RO |<br>| Ro | RO |<br>Po<br>reiki [cee [PEN ||||||
|Legend:||||||
|R = Readable bit|||W = Writable bit||U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR|||‘1’=Bitisset||‘0’=Bitiscleared<br>x=Bitisunknown|
- bit 31-4 Unimplemented: Read as ‘0’
- bit 3 AREIF: Access Response Error Interrupt bit 1 = Error occurred trying to access memory outside the Crypto Engine
- 0 = No error has occurred
- bit 2 PKTIF: DMA Packet Completion Interrupt Status bit 1 = DMA packet was completed
- 0 = DMA packet was not completed
- bit 1 CBDIF: BD Transmit Status bit
- 1 = Last BD transmit was processed
- 0 = Last BD transmit has not been processed
- bit O PENDIF: Crypto Engine Interrupt Pending Status bit
- 1 = Crypto Engine interrupt is pending (this value is the resultof an OR of all interrupts in the Crypto Engine) 0 = Crypto Engine interrupt is not pending
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PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 27-7: CEINTEN: CRYPTO ENGINE INTERRUPT ENABLE REGISTER
|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit|
|---|
|Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 |27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0|
|pa ES<br>eee|
|pss SS<br>ee ee|
|° (oe<br>arieerie [rie [Pennie ||
|Legend:|
|R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR<br>‘1’=Bitisset<br>‘0’=Bitiscleared<br>x=Bitisunknown|
bit 31-4 Unimplemented: Read as ‘0’
- bit 3 AREIE: Access Response Error Interrupt Enable bit 1 = Access response error interrupts are enabled
- 0 = Access response error interrupts are not enabled
- bit 2 PKTIE: DMA Packet Completion Interrupt Enable bit 1 = DMA packet completion interrupts are enabled 0 = DMA packet completion interrupts are not enabled
- bit 1 BDPIE: DMA Buffer Descriptor Processor Interrupt Enable bit 1 = BDP interrupts are enabled 0 = BDP interrupts are not enabled
- bit 0 PENDIE: Master Interrupt Enable bit!)
- 1 = Crypto Engine interrupts are enabled
- 0 = Crypto Engine interrupts are not enabled
Note 1: The PENDIE bit is a global enable bit and must be enabled together with the other interrupts desired.
renner eee e rereerence eee eee DS70005425A-page 376 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
## REGISTER 27-8: CEPOLLCON: CRYPTO ENGINE POLL CONTROL REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0 pee[ooteeeSe Se ee eepee |
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
- bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 BDPPLCON<15:0>: Buffer Descriptor Processor Poll Control bits
- These bits determine the number of SYSCLK cycles that the crypto DMA would wait before refetching the descriptor control word if the BD fetched was disabled.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 377
PIC32MZ W1 and WFI32E01 Family
## seman
REGISTER 27-9: CEHDLEN: CRYPTO ENGINE HEADER LENGTH REGISTER
|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit|
|---|
|Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 |27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0|
|pa ES<br>eee<br>pase<br>qeSee<br>ee<br>pss SeSe ee|
|:|
|Legend:|
|R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR<br>‘1’=Bitisset<br>‘0’=Bitiscleared<br>x=Bitisunknown|
bit 31-8 Unimplemented: Read as ‘0’ bit 7-0 HDRLEN<7:0>: DMA Header Length bits For every packet, skip this length of locations and start filling the data.
REGISTER 27-10: CETRLLEN: CRYPTO ENGINE TRAILER LENGTH REGISTER
|Bit<br>Bit|Bit<br>Bit<br>Bit|Bit<br>Bit<br>Bit<br>Bit|
|---|---|---|
|Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 |27/19/11/3||27/19/11/3 |26/18/10/2 | 25/17/9/1 | 24/16/8/0|
|pa | 2 Se<br>eo<br>pee ee Ee ee<br>EEE<br>ps Se<br>ee|||
|:|||
|Legend:|||
|R = Readable bit|W = Writable bit|U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR|‘1’=Bitisset|‘0’=Bitiscleared<br>x=Bitisunknown|
bit 31-8 Unimplemented: Read as ‘0’ bit 7-0 TRLRLEN<7:0>: DMA Trailer Length bits For every packet, skip this length of locations at the end of the current packet and start putting the next packet.
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smn
## 27.2 Crypto Engine Buffer Descriptors
Host software creates a linked list of BDs and the hardware updates them. Table 27-3 provides a list of the Crypto Engine BDs, followed by format descriptions of each BD (see Figure 27-2 to Figure 27-9).
## TABLE 27-3: CRYPTO ENGINE BUFFER DESCRIPTORS
**==> picture [406 x 20] intentionally omitted <==**
**----- Start of picture text -----**<br>
pst] — ‘[sarercHenf — [| — | tast_80 | Lem _[PkT_nt_eN|c80_INT_eN|<br>**----- End of picture text -----**<br>
Note 1: The BD must be allocated in memory on a 64-bit boundary.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 379
## PIC32MZ W1 and WFI32E01 Family
## seman
## FIGURE 27-2: FORMAT OF BD_CTRL
**==> picture [432 x 436] intentionally omitted <==**
**----- Start of picture text -----**<br>
Bit Bit Bit Bit Bit Bit Bit Bit Bit<br>Panes [DESCENT — | CRY. MODE2O> | — | — | — |<br>a aEN _EN<br>bit 31 DESC_EN: Descriptor Enable<br>1 = The descriptor is owned by hardware. After processing the BD, hardware resets this bit to ‘0’.<br>0 = The descriptor is owned by software<br>bit 30 Unimplemented: Must be written as ‘0’<br>bit 29-27 CRY_MODE<2:0>: Crypto Mode<br>111 = Reserved<br>110 = Reserved<br>101 = Reserved<br>100 = Reserved<br>011 = CEK operation<br>010 = KEK operation<br>001 = Preboot authentication<br>000 = Normal operation<br>bit 22 SA_FETCH_EN: Fetch Security Association From External Memory<br>1 = Fetch SA from the SA pointer. This bit needs to be set to ‘1’ for every new packet.<br>0 = Use current fetched SA or the internal SA<br>bit 21-20 Unimplemented: Must be written as ‘0’<br>bit 19 LAST_BD: Last Buffer Descriptors<br>1 = Last BD in the chain<br>0 = More BDs in the chain<br>After the last BD, the CEBDADDR goes to the base address in CEBDPADDR.<br>bit 18 LIFM: Last In Frame<br>In case of Receive Packets (from H/W-> Host), this field is filled by the Hardware to indicate whether the<br>packet goes across multiple BDs. In case of transmit packets (from Host -> H/W), this field indicates<br>whether this BD is the last in the frame.<br>bit 17 PKT_INT_EN: Packet Interrupt Enable<br>Generate an interrupt after processing the current BD, if it is the end of the packet.<br>bit 16 CBD_INT_EN: CBD Interrupt Enable<br>Generate an interrupt after processing the current BD.<br>bit15-O BD_BUFLEN<15:0>: Buffer Descriptor Length<br>This field contains the length of the buffer and is updated with the actual length filled by the receiver.<br>**----- End of picture text -----**<br>
**==> picture [457 x 19] intentionally omitted <==**
**----- Start of picture text -----**<br>
renner eee e rereerence eee eee<br>DS70005425A-page 380 Preliminary Data Sheet © 2020 Microchip Technology Inc.<br>**----- End of picture text -----**<br>
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FIGURE 27-3: FORMAT OF BD_SADDR
|Bit|Bit|Bit|Bit|Bit|Bit|Bit|Bit|Bit|
|---|---|---|---|---|---|---|---|---|
|Range|31/23/15/7|30/22/14/6|29/21/13/5|28/20/12/4|27/19/11/3|26/18/10/2|25/17/9/1|24/16/8/0|
bit31-0 BD_SAADDR<31:0>: Security Association IP Session Address The sessions’ SA pointer has the keys and IV values.
FIGURE 27-4: FORMAT OF BD_SRCADDR
|Bit|Bit|Bit|Bit|Bit|Bit|Bit|Bit<br>Bit|
|---|---|---|---|---|---|---|---|
|Range|31/23/15/7|30/22/14/6|29/21/13/5|28/20/12/4|27/19/11/3|26/18/10/2|25/17/9/1<br>24/16/8/0|
|Pareyp<br>SCSC™C~™~™~CSCCSCRSRCADDRTIS<br>CS||||||||
## bit31-0 _BD_SRCADDR: Buffer Source Address
The source address of the buffer that needs to be passed through the PE-CRDMA for encryption or authentication. This address must be on a 32-bit boundary.
FIGURE 27-5: FORMAT OF BD_DSTADDR
**==> picture [432 x 42] intentionally omitted <==**
**----- Start of picture text -----**<br>
Bit Bit Bit Bit Bit Bit Bit Bit Bit<br>Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0<br>poreTTBODSTADDRGI<br>**----- End of picture text -----**<br>
bit 31-0 _BD_DSTADDR: Buffer Destination Address
The destination address of the buffer that needs to be passed through the PE-CRDMA for encryption or authentication. This address must be on a 32-bit boundary.
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PIC32MZ W1 and WFI32E01 Family
## seman
FIGURE 27-6: FORMAT OF BD_NXTADDR
|Bit|Bit|Bit|Bit|Bit|Bit|Bit|Bit|Bit|
|---|---|---|---|---|---|---|---|---|
|Range|31/23/15/7|30/22/14/6|29/21/13/5|28/20/12/4|27/19/11/3|26/18/10/2|25/17/9/1|24/16/8/0|
bit 31-0 BD_NXTADDR: Next BD Pointer Address Has Next Buffer Descriptor The next buffer can be a next segment of the previous buffer or a new packet. This address must be on a 64-bit boundary.
FIGURE 27-7: FORMAT OF BD_UPDPTR
**==> picture [433 x 123] intentionally omitted <==**
**----- Start of picture text -----**<br>
Bit Bit Bit Bit Bit Bit Bit Bit Bit<br>Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0<br>PareSSCSC™C™~™CSCSCSCRLUPDADDRDIS | SSCS<br>bit 31-0 _BD_UPDADDR: UPD Address Location<br>The update address has the location where the CRDMA results are posted. The updated results are<br>the ICV values, key output values as needed.<br>**----- End of picture text -----**<br>
FIGURE 27-8: FORMAT OF BD_MSG_LEN
**==> picture [429 x 124] intentionally omitted <==**
**----- Start of picture text -----**<br>
Bit Bit Bit Bit Bit Bit Bit Bit Bit<br>Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0<br>Para]SC™~™~™CCCCCCCCCCSSGLENGTINCTDSSSCSC“‘“S*S*S*S~S~*Y<br>bit 31-0 _MSG_LENGTH: Total Message Length<br>Total message length for the hash and HMAC algorithms in bytes. Total number of crypto bytes in<br>case of GCM algorithm (LEN-C).<br>**----- End of picture text -----**<br>
Meeeaa DS70005425A-page 382 Preliminary Data Sheet © 2020 Microchip Technology Inc.
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FIGURE 27-9: FORMAT OF BD_ENC_OFF
|Bit|Bit|Bit|Bit|Bit|Bit|Bit|Bit|Bit|
|---|---|---|---|---|---|---|---|---|
|Range|31/23/15/7|30/22/14/6|29/21/13/5|28/20/12/4|27/19/11/3|26/18/10/2|25/17/9/1|24/16/8/0|
- bit31-0 ENCR_OFFSET: Encryption Offset
- Encryption offset for the multi-task test cases (both encryption and authentication). The number of AAD bytes in the case of GCM algorithm (LEN-A).
## 27.3. Security Association Structure
Table 27-4 shows the SA structure. The Crypto Engine uses the SA to determine the settings for processing a
BDP. The SA contains:
- « Which algorithm to use
- ¢ Whether to use engines in parallel (for both authentication and encryption/decryption)
- ¢ The size of the key
- ¢ Authentication key
- ¢ Encryption/decryption key
- ¢ Authentication Initialization Vector (IV)
- ¢ Encryption IV
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PIC32MZ W1 and WFI32E01 Family
seman
|TABLE 27-4:<br>CRYPTO ENGINE SA STRUCTURE<br>es<br>31/23/15/7<br>30/22/14/6<br>29/21/13/5<br>28/20/12/4<br>27/19/11/3<br>SAcTRL<br>[ota]<br>— S|Sd SCVERIFY | — «| NORX <br>asef__tNC__| voaby | Fe | macs | —|TABLE 27-4:<br>CRYPTO ENGINE SA STRUCTURE<br>es<br>31/23/15/7<br>30/22/14/6<br>29/21/13/5<br>28/20/12/4<br>27/19/11/3<br>SAcTRL<br>[ota]<br>— S|Sd SCVERIFY | — «| NORX <br>asef__tNC__| voaby | Fe | macs | —|TABLE 27-4:<br>CRYPTO ENGINE SA STRUCTURE<br>es<br>31/23/15/7<br>30/22/14/6<br>29/21/13/5<br>28/20/12/4<br>27/19/11/3<br>SAcTRL<br>[ota]<br>— S|Sd SCVERIFY | — «| NORX <br>asef__tNC__| voaby | Fe | macs | —|TABLE 27-4:<br>CRYPTO ENGINE SA STRUCTURE<br>es<br>31/23/15/7<br>30/22/14/6<br>29/21/13/5<br>28/20/12/4<br>27/19/11/3<br>SAcTRL<br>[ota]<br>— S|Sd SCVERIFY | — «| NORX <br>asef__tNC__| voaby | Fe | macs | —|26/18/10/2<br>25/17/9/1<br>24/16/8/0<br> | OREN | ICVONLY | IRFLAG |<br> | — | — | Alco _|26/18/10/2<br>25/17/9/1<br>24/16/8/0<br> | OREN | ICVONLY | IRFLAG |<br> | — | — | Alco _|26/18/10/2<br>25/17/9/1<br>24/16/8/0<br> | OREN | ICVONLY | IRFLAG |<br> | — | — | Alco _|
|---|---|---|---|---|---|---|
|SA_AUTHKEY1|||||||
|SA_AUTHKEY2|||||||
|SA_AUTHKEYS|||||||
|SA_AUTHKEYA|||||||
|SA_AUTHKEYS|||||||
|SA_AUTHKEYG|||||||
|SA_AUTHKEYS|||||||
|SA_ENCKEY1|||||||
|SALENOKEYS<br>31:24|||||||
|SA_ENOKEYA|||||||
|SA_ENOKEYS|||||||
|SA_ENCKEYE|||||||
|rennereeeerereerence||eee||eee|||
|DS70005425A-page|384|Preliminary|DataSheet|©2020|MicrochipTechnologyInc.||
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TABLE 27-4: CRYPTO ENGINE SA STRUCTURE (CONTINUED)
|TABLE 27-4:<br>te <br>SA_ENCKEY7|27-4:<br>|CRYPTO<br> ||CRYPTO ENGINE SA STRUCTURESTRUCTURE<br> ar|aan <br>31/23/15/7<br>30/22/14/6|SA STRUCTURESTRUCTURE (CONTINUED)<br> ane|un | tn[is<br>29/21/13/5<br>28/20/12/4<br>27/19/11/3|[is | tn [<br>26/18/10/2<br>25/17/9/1|24/16/8/0|
|---|---|---|---|---|---|---|
|SA_ENCKEYE|||||||
|SA_AUTHIVA|||||||
|SA_AUTHIVE|||||||
|SAAUTHI|||||||
|SA_AUTHIVA|||||||
|SA_AUTHIVE|||||||
|SA_AUTHIV6|||||||
|SA_AUTHIV?|||||||
|SAAUTHIVE||31:24||||||
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 385
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seman
|TABLE 27-4:<br>CRYPTO ENGINE SASTRUCTURE (CONTINUED)<br>[te | in|ses[nine|ns[tin <br>31/23/15/7<br>30/22/14/6<br>29/21/13/5<br>28/20/12/4<br>27/19/11/3<br>SAENCT<br>[31-24|TABLE 27-4:<br>CRYPTO ENGINE SASTRUCTURE (CONTINUED)<br>[te | in|ses[nine|ns[tin <br>31/23/15/7<br>30/22/14/6<br>29/21/13/5<br>28/20/12/4<br>27/19/11/3<br>SAENCT<br>[31-24|TABLE 27-4:<br>CRYPTO ENGINE SASTRUCTURE (CONTINUED)<br>[te | in|ses[nine|ns[tin <br>31/23/15/7<br>30/22/14/6<br>29/21/13/5<br>28/20/12/4<br>27/19/11/3<br>SAENCT<br>[31-24|TABLE 27-4:<br>CRYPTO ENGINE SASTRUCTURE (CONTINUED)<br>[te | in|ses[nine|ns[tin <br>31/23/15/7<br>30/22/14/6<br>29/21/13/5<br>28/20/12/4<br>27/19/11/3<br>SAENCT<br>[31-24|TABLE 27-4:<br>CRYPTO ENGINE SASTRUCTURE (CONTINUED)<br>[te | in|ses[nine|ns[tin <br>31/23/15/7<br>30/22/14/6<br>29/21/13/5<br>28/20/12/4<br>27/19/11/3<br>SAENCT<br>[31-24|[atin[an<br>26/18/10/2|[an |tn<br>25/17/9/1<br>24/16/8/0|
|---|---|---|---|---|---|---|
|SA_ENOIV2|||||||
|SA_ENOIVS|||||||
|SA_ENGIVA|||||||
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Figure 27-10 shows the SA control word structure.
The Crypto Engine fetches different structures for different flows and ensures that hardware fetches minimum words from SA required for processing. The structure is ready for hardware optimal data fetches.
## FIGURE 27-10: FORMAT OF SA_CTRL
|Bit|Bit|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit|Bit|
|---|---|---|---|
|Range|31/23/15/7|30/22/14/6<br>29/21/13/5<br>28/20/12/4<br>27/19/11/3<br>26/18/10/2<br>25/17/9/1|24/16/8/0|
|Pree <br>Paste|| — | — | VERIFY | — | NO-RX | OREN |ICVONLY| <br>|ic|woapy|re|Fass|—|—|—|||IRFLAG |<br>Alco|
- bit 31-30 Reserved: Initialize to zero.
- bit 29 VERIFY: NIST Procedure Verification Setting 1 = NIST procedures are to be used
- 0 = Do not use NIST procedures
- Note: The bit value shall be zero for the device.
- bit 28 Reserved: Initialize to zero.
- bit 27 NO_RX: Receive DMA Control Setting 1 = Only calculate ICV for authentication calculations 0 = Normal processing
- bit 26 OR_EN: OR Register Bits Enable Setting 1 = OR the register bits with the internal value of the CSR register 0 = Normal processing
- bit 25 ICVONLY: Incomplete Check Value Only Flag This affects the SHA-1 algorithm only. It has no effect on the AES algorithm. 1 = Only three words of the HMAC result are available 0 =All results from the HMAC result are available
- bit 24 IRFLAG: Immediate Result of Hash Setting This bit is set when the immediate result for hashing is requested.
- 1 = Save the immediate result for hashing 0 = Do not save the immediate result
- bit 23 LNC: Load New Keys Setting 1 = Load a new set of keys for encryption and authentication
- 0 = Do not load new keys
- bit 22 LOADIV: Load IV Setting 1 = Load the IV from this SA 0 = Use the next IV
- bit 21 FB: First Block Setting This bit indicates that this is the first block of data to feed the IV value. 1 = Indicates this is the first block of data 0 = Indicates this is not the first block of data
- bit 20 FLAGS: Incoming/Outgoing Flow Setting
- 1 = SAis associated with an outgoing flow
- 0 = SAis associated with an incoming flow
- bit 19-17 Reserved: Initialize to zero.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 387
## PIC32MZ W1 and WFI32E01 Family
## seman
## Figure 27-10: FORMAT OF SA_CTRL (CONTINUED)
bit 16-10 ALGO<6:0>: Type of Algorithm to Use 1xxxxxx = HMAC 1 x1lxxxxx = SHA-256 xxlxxxx = SHA1 xxx1lxxx = MD5 xxxxlxx = AES xxxxx1lx = TDES xxxxxx1 = DES bit 9 ENC: Type of Encryption Setting 1 = Encryption 0 = Decryption bit 8-7 KEYSIZE<1:0>: Size of Keys in SA_AUTHKEYx or SA_LENCKEYx 11 = Reserved; do not use 10 = 256 bits 01 = 192 bits 00 = 128 bits!) bit 6-4 MULTITASK<2:0>: How to Combine Parallel Operations in the Crypto Engine 111 = Parallel pass (decrypt and authenticate incoming data in parallel) 101 = Pipe pass (encrypt the incoming data, and then perform authentication on the encrypted data) 011 = Reserved 010 = Reserved 001 = Reserved 000 = Encryption or authentication or decryption (no pass) bit 3-0 CRYPTOALGO<3:0>: Mode of operation for the Crypto Algorithm 1111 = Reserved 1110 =AES_GCM _ (for AES processing) 1101 =RCTR (for AES processing) 1100 =RCBC_MAC (for AES processing) 1011 = ROFB (for AES processing) 1010 =RCFB (for AES processing) 1001 = RCBC (for AES processing) 1000 = RECB (for AES processing) 0111 = TOFB (for Triple-DES processing) 0110 = TCFB (for Triple-DES processing) 0101 = TCBC (for Triple-DES processing) 0100 = TECB (for Triple-DES processing) 0011 = OFB (for DES processing) 0010 =CFB (for DES processing) 0001 = CBC (for DES processing) 0000 = ECB (for DES processing) Note 1: This setting does not alter the size of SA-AUTHKEYx or SA_ENCKEY*x in the SA, only the number of bits of SA_AUTHKEYx and SA_ENCKEY*x that are used.
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Note 1: IV size for AES GCM is restricted to 96 bits. 2: Supports 32-bit counter mode only. 3: IV value is expected in big endian format. Example: 12 byte IV Value: with SA_PTR = 0x00002000 - IV value desired = 0x11223344_ 55667788 _99aabbcc - In the SA Structure IV will be starting at (32-bit) word offset [25] SYSTEM ADDR: DATA: 0x00002064: 0x11223344 0x00002068: 0x55667788 0x0000206C: O0x99aabbcc 4: Hash results are posted in big endian format as below. Example: 16 byte hash result with UPD_PTR (BD[5]) = 0x00003000 Hash actual result: 0x00010203_04050607_08090a0b_OcOd0e0f SYSTEM ADDR: DATA 0x00003000: 0x00010203 0x00003004: 0x04050607 0x00003008: 0x08090a0b 0x0000300C: 0x0c0d0e0f
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## PIC32MZ W1 and WFI32E01 Family smn 28.0 TRUE RANDOM NUMBER To select a a 42-bit (in this case maximal length) LFSR, it GENERATOR (TRNG) pega
To select a a 42-bit (in this case maximal length) LFSR, it pega x42+ x41 + x20+x19+ 1 ES ec ria gs:
Note: This data sheet summarizes the features of the PIC32MZ W1 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 49. hea i pee (DS60001246) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). The Random Number Generator (RNG) core implements a thermal noise-based, TRNG and a cryptographically secure Pseudo-Random Number Generator (PRNG).
- RNGNUMGEN1 = SEED-Low
- * RNGNUMGEN2 = SEED-High * RNGPOLY1 = 0x00C0_0003 * RNGPOLY2 = 0x0000_0000 * RRGEEr Galeen ean The RNG’s bus clock is gated when the RNG Peripheral Module Disable (PMD) bit is set. When the PMD is set, the RNG cannot be read or written. TABLE 28-1: RNG BLOCK DIAGRAM
The TRNG uses multiple ring oscillators and the inherent thermal noise of integrated circuits to generate true random numbers that can initialize the PRNG. The PRNG is a flexible Linear-Feedback Shift Register (LFSR), which is capable of displaying a maximal length LFSR of up to 64-bits.
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**----- Start of picture text -----**<br>
System Bus<br>SFR PRNG<br>PB5_CLK<br>TRNG<br>BIAS Correctorector<br>Edge Comparator<br>Ring Ring<br>Oscillator Oscillator<br>**----- End of picture text -----**<br>
The key features of the RNG are:
* TRNG: - Up to 50 Mbps of random bits - Multi-ring oscillator-based design bie Ls - Built-in bias corrector
* PRNG: - LFSR-based
- Up to 64-bit polynomial length
- Programmable polynomial
- TRNG can be seed value
To start using the PRNG, it is necessary to set the initial seed value, the length of the polynomial, and the polynomial equation.
The initial seed value is set by writing to the RNGNUMGEN1 and RNGNUMGEN2 registers, which are also the registers where the random value is read. The initial seed value can also be loaded from the TRNG by writing a'1' to the LOAD bit (RNGCON<12>). This action transfers the current value in the RNGSEEDx registers to the corresponding RNGNUMGENx registers. The polynomial length for the LFSR is set by writing the length (in bits) to the PLEN<7:0> bits (RNGCON<7:0>) RNGPOLY1 and RNGPOLY2 control the feedback taps of the polynomial. The PRNG uses a reverse shift LFSR to reverse the bit positions, and largest tap of the polynomial is assigned to bit 0. The length (PLEN[7:0] in RNGCON) defines the feedback position.
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PIC32MZ W1 and WFI32E01 Family
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REGISTER 28-1: RNGVER: RANDOM NUMBER GENERATOR VERSION REGISTER
|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit|
|---|
|Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 |27/19/11/3 | 26/18/10/2 | 25/17/9/1<br>24/16/8/0|
|jorge PRS TRO<br>ee<br>a<br>| asap BP Lee [ne |e ee eee<br>| ise Ret ke | ee | ee ee<br>| ro P Bet ne | ge | eo fe | ee [ee ||
|Legend:|
|R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR<br>‘1’=Bitisset<br>‘0’=Bitiscleared<br>x=Bitisunknown|
bit 31-16 ID<15:0>: Block Identification bits bit 15-8 VERSION<7:0>: Block Version bits bit 7-0 REVISION<7:0>: Block Revision bits
a ©2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 393
## PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 28-2: RNGCON: RANDOM NUMBER GENERATOR CONTROL REGISTER
Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 27/19/11/3 26/18/10/2 | 25/17/9/1 | 24/16/8/0 aai | 25 ape **e** slses — eis —[ecnooe [ete —[ Perea [Teeer | Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-13 Unimplemented: Read as ‘0’
bit 12 LOAD: Device Select bit
- This bit is self-clearing and is used to load the seed from the TRNG (random value) as a seed to the PRNG.
- bit 11 TRNGMODE: TRNG Mode Selection bit
- 1 = Use ring oscillators with bias corrector 0 = Use ring oscillators with XOR tree Note: — Enabling this bit will generate numbers with a more even distribution of randomness.
- bit 10 CONT: PRNG Number Shift Enable bit 1 = PRNG random number is shifted every cycle 0 = PRNG random number is shifted when the previous value is removed
- bit 9 PRNGEN: PRNG Operation Enable bit 1 = PRNG operation is enabled 0 = PRNG operation is not enabled
- bit 8 TRNGEN: TRNG Operation Enable bit 1 = TRNG operation is enabled 0 = TRNG operation is not enabled
- bit 7-0 PLEN<7:0>: PRNG Polynomial Length bits These bits contain the length of the polynomial used for the PRNG.
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## REGISTER 28-3: RNGPOLYx: RANDOM NUMBER GENERATOR POLYNOMIAL REGISTER ‘x’
(‘x’ = 1 or 2)
|Range|||31/23/15/7|||30/22/14/6|||29/21/13/5|||28/20/12/4||27/19/11/3|27/19/11/3|||26/18/10/2|||25/17/9/1|||24/16/8/0|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|||||||||||||||||||
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit31-0 POLY<31:0>: PRNG LFSR Polynomial MSB/LSB bits (RNGPOLY1 = LSB, RNGPOLY2 = MSB)
## REGISTER 28-4: RNGNUMGENx: RANDOM NUMBER GENERATOR REGISTER ‘x’ (‘x’ = 1 or 2)
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**----- Start of picture text -----**<br>
Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0<br>|<br>|<br>Legend:<br>**----- End of picture text -----**<br>
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit31-0 RNG<31:0>: Current PRNG MSB/LSB Value bits (RNGNUMGEN1 = LSB, RNGNUMGEN2 = MSB)
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## seman
REGISTER 28-5: RNGSEEDx: TRUE RANDOM NUMBER GENERATOR SEED REGISTER ‘x’
|REGISTER 28-5:|RNGSEEDx: TRUE RANDOM NUMBER GENERATOR SEED REGISTER ‘x’|
|---|---|
||(‘x’ = 1 or 2)|
|Bit<br>Bit|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit|
|Range | 31/23/15/7|| 30/22/14/6 | 29/21/13/5 | 28/20/12/4 |27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0|
|} etge PRO<br>RO TR ae<br>} sie-—R2_]_ee | re |_pg ee fe |_ee ee<br>| sePe Le | me<br>Oe<br>ee ee<br>ee||
|Legend:||
|R = Readable bit|W = Writable bit<br>U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR|‘1’=Bitisset<br>‘0’=Bitiscleared<br>x=Bitisunknown|
bit31-0 SEED<31:0>: TRNG MSB/LSB Value bits (RNGSEED1 = LSB, RNGSEED2 = MSB)
REGISTER 28-6: RNGCNT: TRUE RANDOM NUMBER GENERATOR COUNT REGISTER
|Bit<br>Bit<br>Bit<br>Bit<br>Bit|Bit<br>Bit<br>Bit<br>Bit|
|---|---|
|Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 |27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0||
|ae<br>a<br>a<br>pee SE ee <br>eeee|EEEEEES|
|ee S92||
|Legend:||
|R = Readable bit<br>W = Writable bit|U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR<br>‘1’=Bitisset|‘0’=Bitiscleared<br>x=Bitisunknown|
bit 31-7 Unimplemented: Read as ‘0’ bit 6-0 RCNT<6:0>: Number of Valid TRNG MSB 32 bits
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PIC32MZ W1 and WFI32E01 Family smn 29.0 12-BIT HIGH-SPEED The feature can be used to make single-ended or difSUCCESSIVE APPROXIMATION hat gerne a cay a yt hese a REGISTER asic eature provides an analog front-end for (SAR) ADC capacitive touch screen application. Note: This data sheet summarizes the features The module enables the digital comparator to set its of the PIC32MZ W1 family of devices. It is interrupt flag flag if the the capacitance drop detected is greater not intended to be a comprehensive than a threshold value to decide if a touch event is hapreference source. To complement the pening or not on pad. Then the interrupt can wake up information in this data sheet, refer to the CPU during idle or sleep or to signal the running Section 22. “12-bit High-Speed software to branch to a different routine because of the the Successive Approximation Register touch event on pad.
Note: This data sheet summarizes the features The module enables the digital comparator to set its of the PIC32MZ W1 family of devices. It is interrupt flag flag if the the capacitance drop detected is greater not intended to be a comprehensive than a threshold value to decide if a touch event is hapreference source. To complement the pening or not on pad. Then the interrupt can wake up information in this data sheet, refer to the CPU during idle or sleep or to signal the running Section 22. “12-bit High-Speed software to branch to a different routine because of the the Successive Approximation Register touch event on pad. (SAR) ADC” (DS60001344) in the “P/C32 Family Reference Manual’, which is 29.1 Activation Sequence available from the Microchip web site (www.microchip.com/PIC32). Step 1: Write all the essential ADC configuration The ADC is designed to support power conversion,and Sie imeiaeing) the ae Eesti Bosker HABE general use applications. The PIC32MZ W1 supports com docks crup as given below: two 12-bit ADC modules, one dedicated ADC * ADCCONT, keeping the ON bit = 0 SARCORE and one shared ADC SARCORE. * ADCCON2, especially paying attention to SAR ADC includes the following key features: ADCDIV<6:0> and SAMC<9:0> « ADCANCON, keeping all analog enables ANENx * 12-bit resolution bit = 0, WKUPCLKCNT bit = 0xA * Two ADC modules with dedicated sample and * ADCCON3, keeping all DIGEN5x = 0, especially hold (S&H) circuits paying attention to ADCSEL<1:0>, and ¢ Single-ended and/or differential inputs CONCLKDIV <5:0> * Can operate during Sleep mode * ADCxTIME, ADCDIVx<6:0>, and SAMCx<9:0> ¢ Supports touch sense applications ¢ ADCTRGMODE, ADCIMCONx, ADCTRGSNS, * Two digital comparators ADCCSSx, ADCGIRQENx, ADCTRGx, * Two digital filters supporting two modes: ADCBASE - Oversampling mode Step 2: Set the ON bit to ‘1’, which enables the - Averaging mode ADC control clock. * Designed for general purpose applications Step 3: Wait for the interrupt or polls the status bit The 12-bit HS SAR ADC has one dedicated ADC BGVRRDY = 1, which signals that the device analog module (ADC1) and one shared ADC module environment (band gap) is ready. (ADC2). The dedicated ADC module uses a single Step 4: Set the ANENx bit to ‘1’ for each of the ADC input and is intended for high-speed and precise SAR cores to be used. Sampling: Gh time-sensitive of fansient InpUuls. The Step 5: Wait for the interrupt or polls the warm-up the shared ADC module incorporates a multiplexer . : . on the finput to facilitatee a larger group of inputs,: with: ready bits: WKRDYx = 1, which signals that the slower sampling,: and provides: flexible; automated respective ADC SAR cores are ready to operate. scanning option through the input scan logic. Step 6: Set the DIGENx bit to ‘1’, which enables the For each ADC module, the analog inputs are aistel eheany i) \iveinineshetely begin bipeeseina connected to the S&H capacitor. The clock, sampling DSNED SASS Ta aaa A ETT. time, and output data resolution for each ADC The throughput rate is calculated, as shown in module can be set independently. The ADC module Equation 29-1. Refer 40.0 “Electrical performs the conversion of the input analog signal Specifications” for more information. based on the configurations set in the registers. When conversion is complete, the final result is EQUATION 29-1: ADC THROUGHPUT RATE stored in the result buffer for the specific analog input and is passed to the digital filter and digital T comparator if configured to use data from this FIP = ——_42___ particular sample. (samp * Tconr) Basic CVD provides a touch interface based on selfWhere, capacitance touch sensing. The ADC module supports oo, CVD feature by using the shared ADC core to perform T'[4p][=][the][frequency][of][ the][individual][ ADC][module] a modified scan of all second and third class channels. reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 397
## PIC32MZ W1 and WFI32E01 Family
## seman
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FIGURE 29-1: ADC BLOCK DIAGRAM<br>‘alate of gh2) aK<br>ANO pt \ Jog !\ geron| Pad & Sqo"<br>ANBO (RH—10 ! AVop = AVss ADCSEL<1:0><br>NIC =e xX xX Tok<br>SHOALT<1:0> 1] | CONCLKDIV<5:0><br>(ADCTRGMODE<17:16>) || ! VREFSEL<2:0> yO<br>!\ | pats 777 Tani] — ADCDIV<6:0> Ta<br>I i (ADCOTIME<22:16>)<br>ANNO BX} _|<br>I ! ||<br>(ADCIMCONt<1>)DIFFO<1> u| | 1\ ! (ADCCON2<6:0>)ADCDIV<6:0>‘<br>1I Vix AN1 II<br>\ ° 1<br>l | \ i}<br>\ \eLog ant4 \ |<br>IVREF (AN20) md ! I<br>IVTEMP (AN21) RW J! HRIANIS ! |<br>! | cvD |<br>ANN1 Bt ! | Capacitoritor L ---- ---------<br>lI|<br>l [|]<br>DIFFx<1> I!<br>(ADCIMCONy<z>)x=1to 19 ee|<br>Z y=1to2, TT 74<br>= 3 to 31 (Odd numbers) | ADCDATAO \<br>ee!<br>!I ADCDATA23 |<br>Le<br>Digital Filter Data<br>n<br>=)<br>a<br>Digital_ Comparator Interrupt/Event =<br>Triggers, a<br>Scan Control Logic aA<br>Capacitive Voltage .<br>;<br>Trigger Divider (CVD)<br>Status and Control<br>Registers<br>**----- End of picture text -----**<br>
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PIC32MZ W1 and WFI32E01 Family
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**----- Start of picture text -----**<br>
FIGURE 29-2: S&H BLOCK DIAGRAM<br>**----- End of picture text -----**<br>
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**----- Start of picture text -----**<br>
rs |<br>| ADC1 |<br>ANO &K 00 I y<br>ANAO 01 |<br>ANBO® 10 | I<br>N/C RH4 11 SoI 2” 2 l<br>] SAR | ,<br>SHOALT<1:0> Se Oo I<br>(ADCTRGMODE<17:16) | I<br>I I<br>ANNO &X | I<br>|I<br>II<br>: | I<br>DIFFO<1> re|<br>(ADCIMCON1<1>)<br>\ | ADC2 |<br>AN1 | |<br>||<br>||<br>IVREF (AN20)-———o . | |<br>IVTemp (AN21)——o , | |<br>| |<br>(ADCCON2<28:26>)CVDCPL<2:0> 3 AN15 | I<br>CVDEN o ; |<br>(ADCCON1<11>)<br>| | |<br>ns i SAR ,<br>| CVD<br>OC oO<br>i ee ee ee | |<br>ANN1 al ["] | Capacitor [| J || ||<br>DIFFx<1><br>**----- End of picture text -----**<br>
© 2020 Microchip Technology Inc. Preliminary Data Sheet
DS70005425A-page 399
## PIC32MZ W1 and WFI32E01 Family
## seman
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FIGURE 29-3: FIFO BLOCK DIAGRAM<br>ADCID<2:0><br>FEN<br>(ADCFSTAT<31>)<br>| socero |. DATA<31:0><br>ADCx ID Converted Data<br>ADCOEN |<br>(ADCFSTAT<24>) a<br>L | FRDY<br>ADC1 f | | iat (ADCFSTAT<22>) |<br>FIFO (16 Words) 4 available in<br>| FIFO FIEN |<br>aa ine (ADCFSTAT<23>) |<br>—— Interrupt<br>a FCNT<7:0><br>(ADCFSTAT<15:8>)<br>a er Number of data in FIFO<br>**----- End of picture text -----**<br>
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PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 29-1: ADCCON1: ADC CONTROL REGISTER 1
|Bit<br>Range ||Bit<br> 34/23/15/7|Bit<br>Bit<br> | 30/22/14/6 |29/21/13/5 ||Bit<br>Bit<br>Bit<br>Bit<br>Bit<br> 28/20/12/4 |27/19/11/3|<br>26/18/10/2<br>25/17/9/1<br>24/16/8/0|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br> 28/20/12/4 |27/19/11/3|<br>26/18/10/2<br>25/17/9/1<br>24/16/8/0|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br> 28/20/12/4 |27/19/11/3|<br>26/18/10/2<br>25/17/9/1<br>24/16/8/0|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br> 28/20/12/4 |27/19/11/3|<br>26/18/10/2<br>25/17/9/1<br>24/16/8/0|
|---|---|---|---|---|---|---|
|oS|||||||
|vate<br>:|||||||
|8<br>on<br>> Le <br>ee ee||sion<br> | CRO|even eva | Fsvurs | ScaNen<br> ROTROT RwO | OOO||||
|Legend:||HS = Hardware Set|HC = Hardware Cleared||||
|R = Readable bit||W = Writable bit|U = Unimplemented bit, read as ‘0’||||
|-n = Value at POR||‘1’ = Bit is set|‘0’ = Bit is cleared|x = Bit is unknown|||
|bit 31-24|Unimplemented: Read as ‘0’||||||
|bit 23|FRACT: Fractional Data Output Format bit||||||
||1 = Fractional||||||
||0 = Integer||||||
|bit 22-21|SELRES<1:0>: SharedADC (ADC2) Resolution bits||||||
||11 = 12 bits (default)||||||
||10 = 10 bits||||||
||01<br>=8<br>bits||||||
||00<br>=6<br>bits||||||
||Note:|Changing the resolution of|theADC does not shift|the result in the corresponding ADCDATAx|||
|||register. The result will still occupy 12 bits, with the corresponding lower|||unused bits|set to ‘0’.|
|||For example, a resolution of 6<br>bits will result||in ADCDATAx<5:0>|being set to|‘0’, and|
|||ADCDATAx<11:6>holdingtheresult.|||||
- bit 20-16 STRGSRC<4:0>: Scan Trigger Source Select bits 11111 = Reserved
01101 = Reserved 01100 = Comparator 2 (COUT) 01011 = Comparator 1 (COUT) 01010 = OCMP5 01001 = OCMP3 01000 = OCMP1 00111 = TMR5 match 00110 = TMR3 match 00101 = TMR1 match 00100 = INTO External interrupt 00011 = Reserved 00010 = Global level software trigger (GLSWTRG) 00001 = Global software edge trigger (GSWTRG) 00000 = No Trigger bit 15 ON: ADC Module Enable bit 1 =ADC module is enabled 0 =ADC module is disabled Note: The ON bit should be set only after the ADC module has been configured. bit 14 Unimplemented: Read as ‘0’
renner eee e rereerence eee eee DS70005425A-page 404 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
## REGISTER 29-1: ADCCON1: ADC CONTROL REGISTER 1 (CONTINUED)
|bit|13|SIDL: Stop in Idle Mode bit||
|---|---|---|---|
|||1 = Discontinue module operation when device enters Idle mode||
|||0 = Continue module operation in Idle mode||
|bit|12|Unimplemented: Read as ‘0’||
|bit|11|CVDEN: Capacitive Voltage Division Enable bit||
|||1 = CVD operation is enabled||
|||0 = CVD operation is disabled||
|bit|10|FSYDMA: Fast Synchronous DMASystem Clock bit||
|||1 = Fast synchronous DMAsystem clock is enabled||
|||0 = Fast synchronous DMAsystem clock is disabled||
|bit|9|FSYUPB: Fast Synchronous UPB Clock bit||
|||1 = Fast synchronous UPB clock is enabled||
|||0 = Fast synchronous UPB clock is disabled||
|bit|8-7|Unimplemented: Read as ‘0’||
|bit|6-4|IRQVS<2:0>: Interrupt Vector Shift bits||
|||To determine interrupt vector address, this bit specifies the amount of left shift done to theARDYx status||
|||bits in theADCDSTAT1 and ADCDSTATZ2 registers, prior to adding with theADCBASE register.||
|||Interrupt Vector Address = Read Value ofADCBASE and Read Value ofADCBASE= Value written|to|
|||ADCBASE + x << IRQVS<2:0>, where<br>‘x’ is the smallest active input ID from the ADCDSTAT1|or|
|||ADCDSTAT2 registers (which has highest priority).||
|||111 = Shift x left 7 bit position||
|||110 = Shift x left 6 bit position||
|||101 = Shift x left 5 bit position||
|||100 = Shift x left 4 bit position||
|||011 = Shift x left 3 bit position||
|||010 = Shift x left 2 bit position||
|||001 = Shift x left 1 bit position||
|||000=Shiftxleft0bitposition||
- bit 3 STRGLWVL: Scan Trigger High Level/Positive Edge Sensitivity bit 1 = Scan trigger is high level sensitive. Once STRIG mode is selected (TRGSRCx<4:0> in the ADCTRGx register), the scan trigger will continue for all selected analog inputs, until the STRIG option is removed.
- 0 = Scan trigger is positive edge sensitive. Once STRIG mode is selected (TRGSRCx<4:0> in the ADCTRGx register), only a single scan trigger will be generated, which will complete the scan of all selected analog inputs.
bit 2-0 DMABL<2:0>: DMA to System RAM Buffer Length Size Defines the number of locations in system memory allocated per analog input for DMA interface use.
- As each output data is 16-bit wide, one location consists of 2 bytes. Therefore the actual size reserved in the system RAM follows the formula: RAM Buffer Length in bytes = 2(paBL+1)
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 405
## PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 29-2: ADCCON2: ADC CONTROL REGISTER 2
|Bit Range<br>Bit|Bit|Bit|Bit<br>Bit|Bit<br>Bit<br>Bit|
|---|---|---|---|---|
|31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 |26/18/10/2||||26/18/10/2 | 25/17/9/1 | 24/16/8/0|
|:|||||
|:|||||
|® [poveien | rerrcren | cosien [| — | enxonvaT| — | — | — ||||||
|° Ee<br>nave<br>—SF|||||
|Legend:|HS = Hardware Set||HC = Hardware Cleared|r= Reserved|
|R = Readable bit|W = Writable bit||U = Unimplemented bit, read as ‘0’||
|-n=ValueatPOR|‘1’=Bitisset||‘0’=Bitiscleared|x=Bitisunknown|
- bit 31 BGVRRDY: Band Gap Voltage/ADC Reference Voltage Status bit 1 = Both band gap voltage and ADC reference voltages (VREF) are ready 0 = Either or both band gap voltage and ADC reference voltages (VREF) are not ready
- Data processing is valid only after BGVRRDY is set by hardware, so the application code must check that the BGVRRDY bit is set to ensure data validity. This bit set to ‘0’ when ON (ADCCON1<15>) = 0.
- bit 30 REFFLT: Band Gap/VREF/AVDD BOR Fault Status bit 1 = Fault in band gap or the VREF voltage while the ON bit (ADCCON1<15>) was set. Most likely a band gap or VREF fault will be caused by a BOR of the analog VDD supply.
- 0 = Band gap and VREF voltage are working properly This bit is cleared when the ON bit (ADCCON1<15>) = 0 and the BGVRRDY bit = 1.
- bit 29 EOSRDY: End of Scan Interrupt Status bit
- 1 =All analog inputs are considered for scanning through the scan trigger (all analog inputs specified in the ADCCSS1 and ADCCSS82 registers) have completed scanning
- 0 = Scanning has not completed
- This bit is cleared when ADCCON2<31:24> are read in software.
- bit 28-26 CVDCPL<2:0>: Capacitor Voltage Divider (CVD) Setting bits 111 =7* 2.5 pF = 17.5 pF 110 =6*2.5 pF = 15 pF 101 =5* 2.5 pF = 12.5 pF 100 =4*2.5 pF = 10 pF 011 =3*2.5 pF =7.5 pF 010 =2*2.5pF =5 pF 001 =1%* 2.5 pF = 2.5 pF 000 =0*2.5pF = 0 pF
- bit 25-16 SAMC<9:0>: Sample Time for the Shared ADC (ADC2) bits 1111111111 = 1025 TAD7
0000000001 =3 TAD7
0000000000 = 2 TAD7
- Where TAD7 = period of the ADC conversion clock for the Shared ADC (ADC2) controlled by the ADCDIV<6:0> bits.
- bit 15 BGVRIEN: Band Gap/VREF Voltage Ready Interrupt Enable bit 1 = Interrupt will be generated when the BGVRDDY bit is set 0 = No interrupt is generated when the BGVRRDY bit is set
renner eee e rereerence eee eee DS70005425A-page 406 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
## REGISTER 29-2: ADCCON2: ADC CONTROL REGISTER 2 (CONTINUED)
|bit|14|REFFLTIEN: Band Gap/VREF Voltage Fault Interrupt Enable bit|
|---|---|---|
|||1 = Interrupt will be generated when the REFFLT bit is set|
|||0 = No interrupt is generated when the REFFLT bit is set|
|bit|13|EOSIEN: End of Scan Interrupt Enable bit|
|||1 = Interrupt will be generated when EOSRDY bit is set|
|||0 = No interrupt is generated when the EOSRDY bit is set|
|bit|12|Unimplemented: Read as ‘0’|
|bit|11|ENXCNVRT: Enable External Conversion Request Interface|
|||Setting this bit will enable another module (such as the PTG) to specify and request conversion ofan|
|||ADC input.|
|||Note:<br>The external module (such as the PTG) is responsible for asserted only the propertrigger sig-|
|||nals. This ADC module has no method to block specific trigger requests from the external|
|||module.|
|bit|10-7|Unimplemented: Read as ‘0’|
|bit|6-0|ADCDIV<6:0>: Division Ratio for the Shared SARADC Core Clock bits|
|||1111111 = 254 * Ta = TAD2|
|||0000011<br>=6* TQ= TAD2|
|||0000010 = 4* TQ= TAD2|
|||0000001<br>=2* TQ= TAD2|
|||0000000=Reserved|
The ADCDIV<6:0> bits divide the ADC control clock (Tg) to generate the clock for the shared SAR ADC.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 407
## PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 29-3: ADCCON3: ADC CONTROL REGISTER 3
Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 24/16/8/0 Power [| — | — | — | — | — | — | 2 I6eNo_ | Legend: HS = Hardware Set HC = Hardware Cleared r= Reserved R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
- bit 31-30 ADCSEL<1:0>: Analog-to-Digital Clock Source (T,,,) bits 00 = Peripheral Bus Clock
01 = FRC Clock
- 10 = REFO3 Clock Output
11 = System Clock (SYS_CLK)
- bit 29-24 CONCLKDIV<5:0>: Analog-to-Digital Control Clock (TQ) Divider bits 111111 =64* TcLK=TaQ
- 000011 =4* TCLK=TQ 000010 =3* TCLK=TQ
- 000001 =2* TCLK=TQ 000000 = TCLK= TQ
- bit 23 DIGEN7: Shared ADC (ADC2) Digital Enable bit 1 =ADC2 is digital enabled 0 = ADC2 is digital disabled
- bit 22-17 Unimplemented: Read as ‘0’
- bit 16 DIGENO: ADC1 Digital Enable bit 1 =ADC‘1 is digital enabled 0 =ADC1 is digital disabled
- bit 15-13 VREFSEL<2:0>: Voltage Reference (VREF) Input Selection bits VREFSELG0>[—ADRers _ | ADREr |
- bit 12 TRGSUSP: Trigger Suspend bit 1 = Triggers are blocked from starting a new analog-to-digital conversion, but the ADC module is not disabled 0 = Triggers are not blocked
- bit 11 UPDIEN: Update Ready Interrupt Enable bit 1 = Interrupt will be generated when the UPDRDY bit is set by hardware 0 = No interrupt is generated
- bit 10 UPDRDY: ADC Update Ready Status bit 1 = ADC SFRs can be updated
- 0 =ADC SFRs cannot be updated
- Note: This bit is only active while the TRGSUSP bit is set and there are no more running conversions of any ADC modules.
renner eee e rereerence eee eee DS70005425A-page 408 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
## REGISTER 29-3: ADCCON3: ADC CONTROL REGISTER 3 (CONTINUED)
- bit 9 SAMP: Class 2 and Class 3 Analog Input Sampling Enable bit(t-2.5-4) 1 =ADC S&H amplifier is sampling
- 0 = ADC S&H amplifier is holding
- Note 1: The SAMP bit has the highest priority and setting this bit will keep the S&H circuit in Sample mode until the bit is cleared. Also, usage of the SAMP bit will cause settings of SAMC<9:0> bits (ADCCON2<25:16>) to be ignored.
- 2: The SAMP bit only connects Class 2 and Class 3 analog inputs to the shared ADC. All Class 1 analog inputs are not affected by the SAMP bit.
- 3: The SAMP bit is not a self-clearing bit and it is the responsibility of application software to first clear this bit and only after setting the RQCNVRT bit to start the analog-to-digital conversion.
- 4: Normally, when the SAMP and RQCNVRT bits are used by software routines, all TRGSRCx<4:0> bits and STRGSRC<4:0> bits should be set to ‘00000’ to disable all external hardware triggers and prevent them from interfering with the software-controlled sampling command signal SAMP and with the software-controlled trigger RQCNVRT.
- bit 8 RQCNVRT: Individual ADC Input Conversion Request bit This bit and its associated ADINSEL<5:0> bits enable the user to individually request an analog-to-digital conversion of an analog input through software.
- 1 = Trigger the conversion of the selected ADC input as specified by the ADINSEL<5:0> bits 0 = Do not trigger the conversion
- Note: This bit is automatically cleared in the next ADC clock cycle.
- bit 7 GLSWTRG: Global Level Software Trigger bit
- 1 = Trigger conversion for ADC inputs that have selected the GLSWTRG bit as the trigger signal, either through the associated TRGSRC<4:0> bits in the ADCTRGx registers or through the STRGSRC<4:0> bits in the ADCCON1 register
- 0 = Do not trigger an analog-to-digital conversion
- bit 6 GSWTRG: Global Software Trigger bit
- 1 = Trigger conversion for ADC inputs that have selected the GSWTRG bit as the trigger signal, either through the associated TRGSRC<4:0> bits in the ADCTRGx registers or through the STRGSRC<4:0> bits in the ADCCON1 register
- 0 = Do not trigger an analog-to-digital conversion
- Note: This bit is automatically cleared in the next ADC clock cycle.
- bit 5-0 ADINSEL<5:0>: Analog Input Select bits These bits select the analog input to be converted when the RQCNVRT bit is set. As a general rule:
111111 = Reserved
101101 = Reserved 101100 = MAX_AN_INPUT + 2 = IVTEMP 101011 = MAX_AN_INPUT + 1 = IVREF 101010 = MAX_AN_INPUT = AN[MAX_AN_INPUT]
000001 =AN1
000000 =ANO
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 409
PIC32MZ W1 and WFI32E01 Family
seman
## REGISTER 29-4: ADCTRGMODE: ADC TRIGGERING MODE FOR DEDICATED ADC REGISTER
|Range||34/23/15/7||30/22/14/6 | 29/21/13/5|30/22/14/6 | 29/21/13/5|| 28/20/12/4 | 27/19/11/3|| 28/20/12/4 | 27/19/11/3|| 26/18/10/2 | 25/17/9/1|24/16/8/0|
|---|---|---|---|---|---|---|---|
||Po-|| =<br>||=|| = ||= | = | =||| = ||
|,pe|a a<br> ee||rea|a|ee|ee||
|—f|=|| = ||=|| =<br>||=|| = | =|{|SsanPeno ||
|Legend:||||||||
|R = Readable bit||W = Writable bit||U = Unimplemented bit, read as ‘0’||||
|-n=ValueatPOR||‘1’=Bitisset||‘0’=Bitiscleared||x=Bitisunknown||
bit 31-26 Unimplemented: Read as ‘0’
bit 17-16 SHOALT<1:0>: ADC1 Analog Input Select bits
11 = Reserved
10 = Reserved
- 01 =AN45
- 00 =ANO
- bit 15-9 Unimplemented: Read as ‘0’
- bit 8 STRGENO: ADC1 Presynchronized Triggers bit 1 = ADC1 uses presynchronized triggers
- 0 = ADC1 does not use presynchronized triggers
- bit 7-1 Unimplemented: Read as ‘0’
bit O SSAMPENO: ADC1 Synchronous Sampling bit 1 =ADC1 uses synchronous sampling for the first sample after being idle or disabled 0 = ADC1 does not use synchronous sampling
renner eee e rereerence eee eee DS70005425A-page 410 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
REGISTER 29-5: ADCIMCON1: ADC INPUT MODE CONTROL REGISTER 1
**==> picture [444 x 166] intentionally omitted <==**
**----- Start of picture text -----**<br>
|||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|31/23/15/7|||30/22/14/6|| 29/21/13/5|| 28/20/12/4|| 27/19/11/3|| 26/18/10/2|||25/17/9/1|24/16/8/0|
|||
|||
|Legend:|
|R|=|Readable|bit|W|=|Writable|bit|U|=|Unimplemented|bit,|read|as|‘0’|
|-n|=|Value|at|POR|‘1’|=|Bit|is|set|‘0’|=|Bit|is|cleared|x|=|Bit|is|unknown|
**----- End of picture text -----**<br>
**==> picture [201 x 423] intentionally omitted <==**
**----- Start of picture text -----**<br>
|||||||||
|---|---|---|---|---|---|---|---|
|bit|31|DIFF15:|AN15|Mode|bit|
|1|=AN15|is|using|Differential|mode|
|0|= AN15|is|using|Single-ended|mode|
|bit|30|SIGN:15 AN15|Signed|Data|Mode|bit|
|1|=AN15|is|using|Signed|Data|mode|
|0|=AN15|is|using|Unsigned|Data|mode|
|bit|29|DIFF14:|AN14|Mode|bit|
|1|=AN14|is|using|Differential|mode|
|0|= AN14|is|using|Single-ended|mode|
|bit|28|SIGN14: AN14|Signed|Data|Mode|bit|
|1|=AN14|is|using|Signed|Data|mode|
|0|=AN14|is|using|Unsigned|Data|mode|
|bit|27|DIFF13:|AN13|Mode|bit|
|1|= AN13|is|using|Differential|mode|
|0|= AN13|is|using|Single-ended|mode|
|bit|26|SIGN13:|AN13|Signed|Data|Mode|bit|
|1|=AN13|is|using|Signed|Data|mode|
|0|= AN13|is|using|Unsigned|Data|mode|
|bit|25|DIFF12:|AN12|Mode|bit|
|1|=AN12|is|using|Differential|mode|
|0|=AN12|is|using|Single-ended|mode|
|bit|24|SIGN12:|AN12|Signed|Data|Mode|bit|
|1|=AN12|is|using|Signed|Data|mode|
|0|= AN12|is|using|Unsigned|Data|mode|
|bit|23|DIFF11:|AN11|Mode|bit|
|1|=AN11|is|using|Differential|mode|
|0|=AN11|is|using|Single-ended|mode|
|bit|22|SIGN11:|AN11|Signed|Data|Mode|bit|
|1|=AN11|is|using|Signed|Data|mode|
|0|= AN11|is|using|Unsigned|Data|mode|
|bit|21|DIFF10:|AN10|Mode|bit|
|1|=AN10|is|using|Differential|mode|
|0|= AN10|is|using|Single-ended|mode|
**----- End of picture text -----**<br>
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 411
## PIC32MZ W1 and WFI32E01 Family
## seman
**==> picture [404 x 632] intentionally omitted <==**
**----- Start of picture text -----**<br>
||||||||||
|---|---|---|---|---|---|---|---|---|
|REGISTER|29-5:|ADCIMCON1: ADC|INPUT|MODE|CONTROL|REGISTER|1|(CONTINUED)|
|bit|20|SIGN10:|AN10|Signed|Data|Mode|bit|
|1|=AN10|is|using|Signed|Data|mode|
|0|= AN10|is|using|Unsigned|Data|mode|
|bit|19|DIFF9:|AN9|Mode|bit|
|1|=AN$9|is|using|Differential|mode|
|0|=AN$Q|is|using|Single-ended|mode|
|bit|18|SIGN9:|AN9|Signed|Data|Mode|bit|
|1|= ANQ|is|using|Signed|Data|mode|
|0|=AN$9|is|using|Unsigned|Data|mode|
|bit|17|DIFF8:|AN|8|Mode|bit|
|1|=AN8|is|using|Differential|mode|
|0|=AN8|is|using|Single-ended|mode|
|bit|16|SIGN8:|AN8|Signed|Data|Mode|bit|
|1|= AN|is|using|Signed|Data|mode|
|0|= AN8|is|using|Unsigned|Data|mode|
|bit|15|DIFF7:|AN7|Mode|bit|
|1|=AN7|is|using|Differential|mode|
|0|= AN7|is|using|Single-ended|mode|
|bit|14|SIGN7:|AN7|Signed|Data|Mode|bit|
|1|=AN7|is|using|Signed|Data|mode|
|0|=AN7|is|using|Unsigned|Data|mode|
|bit|13|DIFF6:|AN6|Mode|bit|
|1|=AN6|is|using|Differential|mode|
|0|= ANG|is|using|Single-ended|mode|
|bit|12|SIGN6:|AN6|Signed|Data|Mode|bit|
|1|= ANG|is|using|Signed|Data|mode|
|0|= AN6|is|using|Unsigned|Data|mode|
|bit|11|DIFF5:|AN5|Mode|bit|
|1|= AN5|is|using|Differential|mode|
|0|= AN5|is|using|Single-ended|mode|
|bit|10|SIGN5:|AN5|Signed|Data|Mode|bit|
|1|= AN5|is|using|Signed|Data|mode|
|0|=ANb5|is|using|Unsigned|Data|mode|
|bit|9|DIFF4:|AN4|Mode|bit|
|1|= AN4|is|using|Differential|mode|
|0|= AN4|is|using|Single-ended|mode|
|bit|8|SIGN4:|AN4|Signed|Data|Mode|bit|
|1|= AN4|is|using|Signed|Data|mode|
|0|= AN4|is|using|Unsigned|Data|mode|
|bit|7|DIFF3:|AN3|Mode|bit|
|1|= AN3|is|using|Differential|mode|
|0|= AN3|is|using|Single-ended|mode|
|bit|6|SIGN3:|AN3|Signed|Data|Mode|bit|
|1|= AN3|is|using|Signed|Data|mode|
|0|= AN3|is|using|Unsigned|Data|mode|
|bit|5|DIFF2:|AN2|Mode|bit|
|1|=AN2|is|using|Differential|mode|
|0|= ANZ|is|using|Single-ended|mode|
**----- End of picture text -----**<br>
renner eee e rereerence eee eee DS70005425A-page 412 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
|REGISTER|29-5: ADCIMCON1: ADC INPUT MODE CONTROL REGISTER 1 (CONTINUED)|
|---|---|
|bit4|SIGN2: AN2 Signed Data Mode bit|
||1 =AN2 is using Signed Data mode|
||0 =AN2 is using Unsigned Data mode|
|bit 3|DIFF1: AN1 Mode bit|
||1 =AN1 is using Differential mode|
||0 =AN1 is using Single-ended mode|
|bit 2|SIGN1: AN1 Signed Data Mode bit|
||1 =AN1 is using Signed Data mode|
||0 =AN1 is using Unsigned Data mode|
|bit 1|DIFFO: ANO Mode bit|
||1 =AN0O is using Differential mode|
||0 =ANO is using Single-ended mode|
|bit 0|SIGNO: ANO Signed Data Mode bit|
||1 =ANDO is using Signed Data mode|
||0=ANOisusingUnsignedDatamode|
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 413
PIC32MZ W1 and WFI32E01 Family
## seman
REGISTER 29-6: ADCIMCON2: ADC INPUT MODE CONTROL REGISTER 2
||31/23/15/7 |30/22/14/6 |29/21/13/5|31/23/15/7 |30/22/14/6 |29/21/13/5|29/21/13/5 | 28/20/12/4 |27/19/11/3 |26/18/10/2 | 25/17/9/1|24/16/8/0|
|---|---|---|---|---|
||DES|SES|SEN BES EEN BEN ESEsSETsS||
||ES|eS|Se Ee eee eee eee|eee|
||DESDE||SES SENSE SSESSSEsDSs||
|Legend:|||||
|R = Readable bit||W = Writable|bit<br>U = Unimplemented bit, read as ‘0’||
|-n=Value|atPOR|‘1’=Bitisset|‘0’=Bitiscleared<br>x=Bitisunknown||
- bit 31-8 Unimplemented: Read as ‘0’ bit 7 DIFF19: AN19 Mode bit 1 =AN19 is using Differential mode 0 =AN19 is using Single-ended mode
- bit 6 SIGN19: AN19 Signed Data Mode bit 1 =AN19 is using Signed Data mode 0 = AN19 is using Unsigned Data mode
- bit 5 DIFF18: AN18 Mode bit 1 =AN‘18 is using Differential mode 0 = AN18 is using Single-ended mode
- bit 4 SIGN18: AN18 Signed Data Mode bit 1 =AN18 is using Signed Data mode 0 = AN18 is using Unsigned Data mode
- bit 3 DIFF17: AN17 Mode bit 1 = AN‘17 is using Differential mode 0 = AN17 is using Single-ended mode
- bit 2 SIGN17: AN17 Signed Data Mode bit 1 = AN{17 is using Signed Data mode 0 = AN17 is using Unsigned Data mode
- bit 1 DIFF16: AN16 Mode bit 1 =AN16 is using Differential mode 0 =AN16 is using Single-ended mode
- bit 0 SIGN16: AN16 Signed Data Mode bit 1 =AN‘16 is using Signed Data mode 0 = AN16 is using Unsigned Data mode
renner eee e rereerence eee eee DS70005425A-page 414 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
REGISTER 29-7: ADCGIRQEN1: ADC GLOBAL INTERRUPT ENABLE REGISTER 1
|REGISTER 29-7: ADCGIRQEN1: ADC GLOBAL INTERRUPT ENABLE REGISTER 1|REGISTER 29-7: ADCGIRQEN1: ADC GLOBAL INTERRUPT ENABLE REGISTER 1|REGISTER 29-7: ADCGIRQEN1: ADC GLOBAL INTERRUPT ENABLE REGISTER 1||
|---|---|---|---|
|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Range| 341/23/15/7 | 30/22/14/6 |29/21/13/5 | 28/20/12/4 |27/19/11/3 | 26/18/10/2 | 25/17/9/1|||Bit<br>24/16/8/0|
|8 eno<br>| acenis[ Asien? | AGIENTO||||
|:||||
|:||||
|Legend:||||
|R = Readable bit|W = Writable bit|U = Unimplemented bit, read as ‘0’||
|-n=ValueatPOR|‘1’=Bitisset|‘0’=Bitiscleared<br>x=Bitisunknown||
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 AGIEN<19:0>: ADC Global Interrupt Enable bits
1 = Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data is ready (indicated by the ARDYx bit (‘x’ = 31-0) of the ADCDSTAT1 register) 0 = Interrupts are disabled
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 415
## PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 29-8: ADCCSS1: ADC COMMON SCAN SELECT REGISTER 1
|Bit Range|Bit<br>31/23/15/7 ||Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br> 30/22/14/6 |29/21/13/5 |28/20/12/4 |27/19/11/3 |26/18/10/2 | 25/17/9/1|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br> 30/22/14/6 |29/21/13/5 |28/20/12/4 |27/19/11/3 |26/18/10/2 | 25/17/9/1|Bit<br>24/16/8/0|
|---|---|---|---|---|
|pw|EB|EE<br>EE|||
|6|Fe||=<br>fesse [ests | essi7_||csste_||
|:|||||
|:|||||
|Legend:|||||
|R = Readable bit||W = Writable bit|U = Unimplemented bit, read as ‘0’||
|-n=Value|atPOR|‘1’=Bitisset|‘0’=Bitiscleared<br>x=Bitisunknown||
## bit 31-20 Unimplemented: Read as ‘0’ bit 19-0 | CSS<19:0>: Analog Common Scan Select bits: 2)
- 1 = Select ANx for input scan
- 0 = Skip ANx for input scan
- Note 1: In addition to setting the appropriate bits in this register, Class 1 and Class 2 analog inputs must select the STRIG input as the trigger source if they are to be scanned through the CSSx bits. Referto the bit descriptions in the ADCTRGx registers for selecting the STRIG option.
- 2: IfaClass 1 or Class 2 input is included in the scan by setting the CSSx bit to ‘1’ and by setting the TRGSRCx<4:0> bits to STRIG mode (‘0b11), the user application must ensure that no other triggers are generated for that input using the RQCNVRT bit in the ADCCONS3 register or the hardware input or any digital filter. Otherwise, the scan behavior is unpredictable.
renner eee e rereerence eee eee DS70005425A-page 416 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
## REGISTER 29-9: ADCDSTAT1: ADC DATA READY STATUS REGISTER 1
|REGISTER 29-9: ADCDSTAT1: ADC DATA READY STATUS REGISTER 1|REGISTER 29-9: ADCDSTAT1: ADC DATA READY STATUS REGISTER 1|REGISTER 29-9: ADCDSTAT1: ADC DATA READY STATUS REGISTER 1||
|---|---|---|---|
|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/4|||Bit<br>24/16/8/0|
|Ee<br>eee|eee ee|||
|=<br>8 =|=|arovio | arovis | ARDYI7 | ARDYT6 |||
||||||
|-<br>:||||
|Legend:|HS = Hardware Set|HC = Hardware Cleared||
|R = Readable bit|W = Writable bit|U = Unimplemented bit, read as ‘0’||
|-n=ValueatPOR|‘1’=Bitisset|‘0’=Bitiscleared<br>x=Bitisunknown||
bit 31-20 Unimplemented: Read as ‘0’
bit19-0 ARDY<19:0>: Conversion Data Ready for Corresponding Analog Input Ready bits 1 = This bit is set when converted data is ready in the data register
0 = This bit is cleared when the associated data register is read
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 417
## PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 29-10: ADCCMPENx: ADC DIGITAL COMPARATOR ‘x’ ENABLE REGISTER
|(‘*x’|= 1 OR 2)|||
|---|---|---|---|
|Bit<br>Bit<br>Range| 34/23/15/7|Bit<br>Bit<br> | 30/22/14/6 | 29/21/13/5|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br> | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/4 | 24/16/8/0||
|w=|>= f=||= | =<br>[| - ||- |- ||
|a<br>°eT<br>erst | cwrets| omet7| oMpete_|||||
|a<br>:||||
|-<br>2||||
|Legend:||||
|R = Readable bit|W = Writable bit|U = Unimplemented bit, read as ‘0’||
|-n=ValueatPOR|‘1’=Bitisset|‘0’=Bitiscleared<br>x=Bitisunknown||
bit 31-20 Unimplemented: Read as ‘0’ bit 31-0 CMPE<19:0>: ADC Digital Comparator ‘x’ Enable bits'"-2)
- These bits enable conversion results corresponding to the analog input to be processed by the digital comparator. CMPEO enables ANO, CMPE1 enables AN1, and so on.
- Note 1: CMPEx =ANx, where ‘x’ = 0-19 (Digital Comparator inputs are limited to ANO through AN19).
- 2: Changing the bits in this register while the Digital Comparator is enabled (ENDCMP = 1), can result in unpredictable behavior.
## a
DS70005425A-page 418
Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
REGISTER 29-11: ADCCMPx: ADC DIGITAL COMPARATOR ‘x’ LIMIT VALUE REGISTER
|(‘x’ =|1 OR 2)||||
|---|---|---|---|---|
|31/23/15/7 | 30/22/14/6 |29/21/13/5 |28/20/12/4|27/19/11/3|26/18/10/2 | 25/17/9/1||||24/16/8/0|
|||||||
|Legend:|||||
|R = Readable bit|W = Writable bit|U = Unimplemented bit, read as ‘0’|||
|-n=ValueatPOR|‘1’=Bitisset|‘0’=Bitiscleared|x=Bitisunknown||
- bit 31-16 | DCMPHI<15:0>: Digital Comparator ‘x’ High Limit Value bits't-2-5) These bits store the high limit value, which is used by digital comparator for comparisons with ADC converted data.
- bit 15-0 | DCMPLO<15:0>: Digital Comparator ‘x’ Low Limit Value bits‘*:2-9) These bits store the low limit value, which is used by digital comparator for comparisons with ADC converted data.
- Note 1: Changing theses bits while the Digital Comparator is enabled (ENDCMP = 1) can result in unpredictable behavior.
- 2: The format of the limit values should match the format of the ADC converted value in terms of sign and fractional settings.
- 3: For Digital Comparator 0 used in CVD mode, the DCMPHI<15:0> and DCMPLO<15:0> bits must always be specified in signed format, as the CVD output data is differential and is always signed.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 419
## PIC32MZ W1 and WFI32E01 Family
## seman
|REGISTER 29-12: ADCFLTRx: ADC DIGITAL FILTER ‘x’ REGISTER (‘x’ = 1 OR 2)|REGISTER 29-12: ADCFLTRx: ADC DIGITAL FILTER ‘x’ REGISTER (‘x’ = 1 OR 2)|REGISTER 29-12: ADCFLTRx: ADC DIGITAL FILTER ‘x’ REGISTER (‘x’ = 1 OR 2)|
|---|---|---|
|Bit<br>Bit<br>Bit<br>Bit<br>Range | 34/23/15/7 | 30/22/14/6 | 29/21/13/5||Bit<br>Bit<br>Bit<br>Bit<br>Bit<br> | 28/20/12/4 |27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0|
|:|||
|ee<br>ee ee|||
|:|||
|:|||
|Legend:|HS = Hardware Set|HC = Hardware Cleared|
|R = Readable bit|W = Writable bit|U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR|‘1’=Bitisset|‘0’=Bitiscleared<br>x=Bitisunknown|
- bit 31 AFEN: Digital Filter ‘x’ Enable bit 1 = Digital filter is enabled
- 0 = Digital filter is disabled and the AFRDY status bit is cleared
- bit 30 DATA16EN: Filter Significant Data Length bit
- 1 =All 16 bits of the filter output data are significant
- 0 = Only the first 12 bits are significant, followed by four zeros Note: This bit is significant only if DFMODE = 1 (Averaging mode) and FRACT (ADCCON1<23>) = 1 (Fractional Output mode).
- bit DFMODE: ADC Filter Mode bit
- 1 = Filter ‘x’ works in Averaging mode
- 0 = Filter ‘x’ works in Oversampling Filter mode (default)
- bit 28-26 OVRSAM<2:0>: Oversampling Filter Ratio bits If DFMODE is ‘0’:
- 111 = 128 samples (shift sum 3 bits to right, output data is in 15.1 format) 110 = 32 samples (shift sum 2 bits to right, output data is in 14.1 format)
- 101 = 8 samples (shift sum 1 bit to right, output data is in 13.1 format) 100 = 2 samples (shift sum 0 bits to right, output data is in 12.1 format) 011 = 256 samples (shift sum 4 bits to right, output data is 16 bits) 010 = 64 samples (shift sum 3 bits to right, output data is 15 bits) 001 = 16 samples (shift sum 2 bits to right, output data is 14 bits) 000 = 4 samples (shift sum 1 bit to right, output data is 13 bits)
If DFMODE is ‘1’:
- 111 = 256 samples (256 samples to be averaged)
- 110 = 128 samples (128 samples to be averaged)
- 101 = 64 samples (64 samples to be averaged) 100 = 32 samples (32 samples to be averaged) 011 = 16 samples (16 samples to be averaged) 010 = 8 samples (8 samples to be averaged) 001 = 4 samples (4 samples to be averaged) 000 = 2 samples (2 samples to be averaged)
- bit 25 AFGIEN: Digital Filter ‘x’ Interrupt Enable bit 1 = Digital filter interrupt is enabled and is generated by the AFRDY status bit 0 = Digital filter is disabled
renner eee e rereerence eee eee DS70005425A-page 420 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
## REGISTER 29-12: ADCFLTRx: ADC DIGITAL FILTER ‘x’ REGISTER (‘x’ = 1 OR 2) (CONTINUED)
- bit 24 AFRDY: Digital Filter ‘x’ Data Ready Status bit 1 = Data is ready in the FLTRDATA<15:0> bits
0 = Data is not ready
Note: This bit is cleared by reading the FLTRDATA<15:0> bits or by disabling the Digital Filter module (by setting AFEN to ‘0’).
- bit 23-21 Unimplemented: Read as ‘0’
- bit 20-16 CHNLID<4:0>: Digital Filter Analog Input Selection bits These bits specify the analog input to be used as the oversampling filter data source. 11111 = Reserved
01100 = Reserved 01011 =AN11
00010 =AN2 00001 =AN1 00000 =ANO
- Note: Only the first 12 analog inputs, Class 1 (ANO-AN11) and Class 2 (AN5-AN11), can usea digital filter.
- bit 15-O FLTRDATA<15:0>: Digital Filter ‘x’ Data Output Value bits The filter output data is as per the fractional format set in the FRACT bit (ADCCON1<23>). The FRACT bit should not be changed while the filter is enabled. Changing the state of the FRACT bit after the operation of the filter ended will not update the value of the FLTRDATA<15:0> bits to reflect the new format.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 421
## PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 29-13: ADCTRG1: ADC TRIGGER SOURCE 1 REGISTER
|Bit<br>Range|Bit<br> | 31/23/15/7|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br> |30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 ||Bit<br>Bit<br>Bit<br>Bit<br>Bit<br> |30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 ||Bit<br>Bit<br>Bit<br>Bit<br>Bit<br> |30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 ||Bit<br> 25/17/9/1|Bit<br>24/16/8/0|
|---|---|---|---|---|---|---|
|“t=|||<br>=<br>||= ||TResres<si>|||
|—|| =|tf =<br>J|= ff|TRGsRoat>|||
|~|fos|| =<br>||eT|TtRGRONHO>|||
|—t||=|[| = ||= ||tResreo<so>|||
|Legend:|||||||
|R = Readable bit||W = Writable bit|U = Unimplemented bit,|read as ‘0’|||
|-n=ValueatPOR||‘7=Bitisset|‘0’=Bitiscleared|x=Bitisunknown|||
bit 31-29 Unimplemented: Read as ‘0’ bit 28-24 TRGSRC3<4:0>: Trigger Source for Conversion of Analog Input AN3 Select bits 11111 = Reserved
01101 = Reserved 01100 = Comparator 2 (COUT) 01011 = Comparator 1 (COUT) 01010 = OCMP5
01001 = OCMP3
01000 = OCMP1
00111 = TMR5 match
00110 = TMR3 match
00101 = TMR1 match
00100 = INTO External interrupt
00011 =STRIG
00010 = Global level software trigger (GLSWTRG)
00001 = Global software edge Trigger (GSWTRG) 00000 = No Trigger
For STRIG, in addition to setting the trigger, it also requires programming of the STRGSRC<4:0> bits (ADCCON1<20:16>) to select the trigger source, and requires the appropriate CSS bits to be set in the ADCCSSx registers.
bit 23-21 Unimplemented: Read as ‘0’ bit 20-16 TRGSRC2<4:0>: Trigger Source for Conversion of Analog Input AN2 Select bits See bits 28-24 for bit value definitions.
- bit 15-13 Unimplemented: Read as ‘0’
bit 12-8 TRGSRC1<4:0>: Trigger Source for Conversion of Analog Input AN1 Select bits See bits 28-24 for bit value definitions.
bit 7-5 Unimplemented: Read as ‘0’
bit 4-0 TRGSRC0<4:0>: Trigger Source for Conversion of Analog Input ANO Select bits See bits 28-24 for bit value definitions.
renner eee e rereerence eee eee DS70005425A-page 422 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
REGISTER 29-14: ADCTRG2: ADC TRIGGER SOURCE 2 REGISTER
|Bit<br>Bit<br>Range | 34/23/15/7|Bit<br> | 30/22/14/6|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br> | 29/21/13/5 |28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br> | 29/21/13/5 |28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1|Bit<br>24/16/8/0|
|---|---|---|---|---|
|“t=|tf =|||= |<br>TRGSRET<HO||
|ee<br>a|a||aSS||
|fo<br>=|fo =|fT|= fT<br>TRGSROSK4O>||
|—t<br>=|| =|||= [To<br>tResRea||
|Legend:|||||
|R = Readable bit|W = Writable bit||U = Unimplemented bit, read as ‘0’||
|-n=ValueatPOR|‘1’=Bitisset||‘0’=Bitiscleared<br>x=Bitisunknown||
## bit 31-29 Unimplemented: Read as ‘0’
bit 28-24 TRGSRC7<4:0>: Trigger Source for Conversion of Analog Input AN7 Select bits 11111 = Reserved
01101 = Reserved 01100 = Comparator 2 (COUT) 01011 = Comparator 1 (COUT) 01010 = OCMP5
01001 = OCMP3
01000 = OCMP1 00111 = TMR5 match 00110 = TMR3 match 00101 = TMR1 match 00100 = INTO External interrupt 00011 = STRIG
00010 = Global level software trigger (GLSWTRG)
00001 = Global software edge Trigger (GSWTRG)
00000 = No Trigger
- For STRIG, in addition to setting the trigger, it also requires programming of the STRGSRC<4:0> bits (ADCCON1<20:16>) to select the trigger source, and requires the appropriate CSS bits to be set in the ADCCSSx registers.
- bit 23-21 Unimplemented: Read as ‘0’
bit 20-16 TRGSRC6<4:0>: Trigger Source for Conversion of Analog Input AN6 Select bits See bits 28-24 for bit value definitions.
- bit 15-13 Unimplemented: Read as ‘0’
bit 12-8 TRGSRC5<4:0>: Trigger Source for Conversion of Analog Input AN5 Select bits See bits 28-24 for bit value definitions.
- bit 7-5 Unimplemented: Read as ‘0’
bit 4-0 TRGSRC4<4:0>: Trigger Source for Conversion of Analog Input AN4 Select bits See bits 28-24 for bit value definitions.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 423
PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 29-15: ADCCMPCON1: ADC DIGITAL COMPARATOR 1 CONTROL REGISTER
**==> picture [444 x 159] intentionally omitted <==**
**----- Start of picture text -----**<br>
Bit Bit Bit Bit Bit Bit Bit Bit Bit<br>Range | 34/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 24/16/8/0<br>:<br>—:<br>asaaa<br>-:<br>Legend: HS = Hardware Set HC = Hardware Cleared<br>R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’<br>-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown<br>**----- End of picture text -----**<br>
- bit 31-16 CVDDATA<15:0>: CVD Data Status bits
In CVD mode, these bits obtain the CVD differential output data (subtraction of CVD positive and negative measurement), whenever a digital comparator interrupt is generated. The value in these bits is compliant with the FRACT bit (ADCCON1<23>) and is always signed.
- bit 15-14 Unimplemented: Read as ‘0’
- bit 13-8 AINID<5:0>: Digital Comparator 0 Analog Input Identification (ID) bits Whena digital comparator event occurs (DCMPED = 1), these bits identify the analog input being monitored by digital comparator 0.
- Note: In normal ADC mode, only analog inputs <31:0> can be processed by the digital comparator 0. The digital comparator 0 also supports the CVD mode, in which all Class 2 and Class 3 analog inputs may be stored in the AINID<5:0> bits.
111111 = Reserved
101101 = Reserved
101100 =AN44 is being monitored
101011 =AN43 is being monitored
- 000001 =ANT1 is being monitored
000000 =ANDO is being monitored
- bit 7 ENDCMP: Digital Comparator 0 Enable bit
- 1 = Digital comparator 0 is enabled
- 0 = Digital comparator 0 is not enabled, and the DCMPED status bit (ADCCMPOCON<5>) is cleared
- bit 6 DCMPGIEN: Digital Comparator 0 Global Interrupt Enable bit 1 =A Digital comparator 0 interrupt is generated when the DCMPED status bit (ADCCMPOCON<5>) is set 0 =A Digital comparator 0 interrupt is disabled
- bit 5 DCMPED: Digital Comparator 0 “Output True” Event Status bit The logical conditions under which the digital comparator gets “True” are defined by the IEBTWN, IEHIHI, IEHILO, IELOHI, and IELOLO bits.
- Note: This bit is cleared by reading the AINID<5:0> bits or by disabling the Digital Comparator module (by setting ENDCMP to ‘o’).
- 1 = Digital comparator O output true event has occurred (output of comparator is ‘1’)
- 0 = Digital comparator 0 output is false (output of comparator is ‘0’)
renner eee e rereerence eee eee DS70005425A-page 424 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
REGISTER 29-15: ADCCMPCON1: ADC DIGITAL COMPARATOR 1 CONTROL REGISTER (CONTINUED)
- bit 4 IEBTWN: Between Low/High Digital Comparator 0 Event bit 1 = Generate a digital comparator event when DCMPLO<15:0> bits < DATA<31:0> bits < DCMPHI<15:0> bits
- 0 = Do not generate a digital comparator event
- bit 3 IEHIHI: High/High Digital Comparator 0 Event bit 1 = Generate a digital comparator 0 event when DCMPHI<15:0> bits are less than or equal to DATA<31:0> bits
- 0 = Do not generate an event
- bit 2 IEHILO: High/Low Digital Comparator 0 Event bit
- 1 = Generate a digital comparator 0 event when DATA<31:0> bits are less than DCMPHI<15:0> bits 0 = Do not generate an event
- bit 1 IELOHI: Low/High Digital Comparator 0 Event bit 1 = Generate a digital comparator 0 event when DCMPLO<15:0> bits are less than or equal to DATA<31:0> bits
- 0 = Do not generate an event
- bit O IELOLO: Low/Low Digital Comparator 0 Event bit 1 = Generate a digital comparator 0 event when DATA<31:0> bits are less than DCMPLO<15:0> bits 0 = Do not generate an event
SS © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 425
PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 29-16: ADCCMPCON2: ADC DIGITAL COMPARATOR 2 CONTROL REGISTER
|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Range | 34/23/15/7 | 30/22/14/6 | 29/21/13/5 |28/20/12/4 | 27/19/11/3 |26/18/10/2 | 25/17/9/1|Bit<br>24/16/8/0|
|---|---|
|a<br>a<br>a<br>a<br>a<br>es ee Ge||
|-<br>en<br>a<br>a a||
|-<br>:||
|Legend:<br>HS = Hardware Set<br>HC = Hardware Cleared||
|R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’||
|-n=ValueatPOR<br>‘1’=Bitisset<br>‘0’=Bitiscleared<br>x=Bitisunknown||
## bit 31-13 Unimplemented: Read as ‘0’
- bit 12-8 AINID<4:0>: Digital Comparator 1 Analog Input Identification (ID) bits
- Whena digital comparator event occurs (DCMPED = 1), these bits identify the analog input being monitored by the digital comparator.
Note: Only analog inputs <31:0> can be processed by the Digital Comparator 1
11111 = Reserved 11110 = Reserved
0001 0011 =AN19 is being monitored
- 00001 =AN1 is being monitored
00000 =ANO is being monitored
- bit 7 ENDCMP: Digital Comparator 1 Enable bit
- 1 = Digital comparator 1 is enabled
- 0 = Digital comparator 1 is not enabled, and the DCMPED status bit (ADCCMPxCON<5>) is cleared
- bit 6 DCMPGIEN: Digital Comparator 1 Global Interrupt Enable bit 1 =A Digital comparator 1 interrupt is generated when the DCMPED status bit (ADCCMPxCON<5>) is set 0 =A Digital comparator 1 interrupt is disabled
- bit 5 DCMPED: Digital Comparator 1 “Output True” Event Status bit The logical conditions under which the digital comparator gets “True” are defined by the IEBTWN, IEHIHI, IEHILO, IELOHI and IELOLO bits.
- Note: This bit is cleared by reading the AINID<5:0> bits (ADCCMPOCON<13:8>) or by disabling the Digital Comparator module (by setting ENDCMP to ‘o’).
- 1 = Digital comparator 1 output true event has occurred (output of comparator is ‘1’)
- 0 = Digital comparator 1 output is false (output of comparator is ‘0’)
- bit 4 IEBTWN: Between Low/High Digital Comparator 1 Event bit 1 = Generate a digital comparator event when the DCMPLO<15:0> bits < DATA<31:0> bits < DCMPHI<15:0> bits
- 0 = Do not generate a digital comparator event
- bit 3 IEHIHI: High/High Digital Comparator 1 Event bit 1 = Generate a digital comparator 1 event when the DCMPHI<15:0> bits are less than or equal to DATA<31:0> bits
- 0 = Do not generate an event
renner eee e rereerence eee eee DS70005425A-page 426 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
## REGISTER 29-16: ADCCMPCONz2: ADC DIGITAL COMPARATOR 2 CONTROL REGISTER (CONTINUED)
- bit 2 IEHILO: High/Low Digital Comparator 1 Event bit
- 1 = Generate a digital comparator 1 event when the DATA<31:0> bits are less than DCMPHI<15:0> bits 0 = Do not generate an event
- bit 1 IELOHI: Low/High Digital Comparator 1 Event bit 1 = Generate a digital comparator 1 event when the DCMPLO<15:0> bits are less than or equal to DATA<31:0> bits
- 0 = Do not generate an event
- bit 0 IELOLO: Low/Low Digital Comparator 1 Event bit
- 1 = Generate a digital comparator 1 event when the DATA<31:0> bits are less than DCMPLO<15:0> bits 0 = Do not generate an event
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 427
## PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 29-17: ADCFSTAT: ADC FIFO STATUS REGISTER
|Bit<br>Range|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br> | 31/23/15/7 |30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3|| 26/18/10/2|Bit<br>Bit<br>Bit<br>| 26/18/10/2 | 25/17/9/1<br>24/16/8/0|Bit<br>Bit<br>Bit<br>| 26/18/10/2 | 25/17/9/1<br>24/16/8/0|Bit<br>Bit<br>Bit<br>| 26/18/10/2 | 25/17/9/1<br>24/16/8/0|Bit<br>Bit<br>Bit<br>| 26/18/10/2 | 25/17/9/1<br>24/16/8/0|
|---|---|---|---|---|---|---|
|a|=OO||||||
|a<br>‘6<br>| sePO]<br>a|[ [Fen |Froy_[FwroverR|—<br>| — | — | — | — |<br>PO] |<br>eee<br>PF RO |RO<br>0<br>uo<br>|RO<br>|<br>Prien [| = | = | = ) = |<br>—AbCDBOS||||||
|Legend:|HS = Hardware Set<br>HC = Hardware Cleared||||||
|R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit,||read as ‘0’|||||
|-n = Value at POR<br>‘1’ = Bit is set<br>‘0’ = Bit is cleared|||x = Bit is unknown||||
|bit 31|FEN: FIFO Enable bit||||||
||1 = FIFO is enabled||||||
||0 = FIFO is disabled; no data is being saved into the FIFO||||||
|bit 30-25|Unimplemented: Read as ‘0’||||||
|bit 24|ADCOEN: First class channel (0) Enable bit||||||
||1 = Converted output data of first class channel (0) is stored in the||FIFO||||
||0 = Converted output data of first class channel (0) is not stored|in|the FIFO||||
||Note:<br>While using FIFO, the output data is additionally stored in the|||respective output data register|||
||(ADCDATAQO).||||||
|bit 23|FIEN: FIFO Interrupt Enable bit||||||
||1 = FIFO interrupts are enabled; an interrupt is generated once the FRDY|||bit|is set||
||0 = FIFO interrupts are disabled||||||
|bit 22|FRDY: FIFO Data Ready Interrupt Status bit||||||
||1 = FIFO has data to be read||||||
||0 = No data is available in the FIFO||||||
||Note:<br>This bit is cleared when the FIFO output data in ADCFIFO has||||been|read and there is no|
||additional data ready in the FIFO (that is, the FIFO is|empty).|||||
|bit 21|FWROVERR: FIFO Write Overflow Error Status bit||||||
||1 = Awrite overflow error in the FIFO has occurred (circular FIFO)||||||
||0 = Awrite overflow error in the FIFO has not occurred||||||
||Note:<br>This bit is cleared afterADCFSTAT<23:16> are read|by software.|||||
|bit 15-8|FCNT<7:0>: FIFO Data Entry Count Status bits||||||
||The value in these bits indicates the number of data entries in the||FIFO.||||
|bit 7|FSIGN: FIFO Sign Setting bit||||||
||This bit reflects the sign of data stored in theADCFIFO register.||||||
|bit 6-3|Unimplemented: Read as ‘0’||||||
|bit 2-0|ADCID<z2:0>: First class channel (0) Identifier bits||||||
||These bits specify the first class channel whose data is stored in|the FIFO.|||||
||111 = Reserved||||||
||110 = Reserved||||||
||101 = Reserved||||||
||100=Reserved||||||
000 = Converted data of first class channel (0) is stored in FIFO
renner eee e rereerence eee eee DS70005425A-page 428 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
## REGISTER 29-18: ADCFIFO: ADC FIFO DATA REGISTER
|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Range | 34/23/15/7 |30/22/14/6 | 29/21/13/5 |28/20/12/4 |27/19/11/3 |26/18/10/2 | 25/17/9/1<br>24/16/8/0|
|---|
|givg (ROT Ro | RO | ROT ROT ROT ROT RO<br>Jattee<br>EY<br>saig FRO [| ro | Ro<br>[| ro<br>[| Ro | Ro [ Ro |<br>Ro |<br>pie |SSS ee<br>ig FRO [| Ro<br>[| ro | ro | Ro | Ro | Ro | RO |<br>ee|
|Legend:|
|R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR<br>‘1’=Bitisset<br>‘0’=Bitiscleared<br>x=Bitisunknown|
bit 31-0 DATA<31:0>: FIFO Data Output Value bits!2)
Note 1: When an alternate input is used as the input source for a dedicated ADC module, the data output is still read from the Primary input Data Output register.
2: Reading the ADCDATAx register value after changing the FRACT bit converts the data into the format specified by FRACT bit.
Note: When an alternate input is used as the input source for a dedicated ADC module, the data output is still read from the Primary Input Data Output register.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 429
PIC32MZ W1 and WFI32E01 Family
## seman
REGISTER 29-19: ADCBASE: ADC BASE REGISTER
|REGISTER 29-19: ADCBASE: ADC BASE REGISTER|REGISTER 29-19: ADCBASE: ADC BASE REGISTER|REGISTER 29-19: ADCBASE: ADC BASE REGISTER||
|---|---|---|---|
|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 |28/20/12/4 |27/19/11/3 |26/18/10/2 | 25/17/9/4|||Bit<br>24/16/8/0|
|A(Fe<br>=<br>pa Se ee<br>EE||||
|:||||
|:||||
|Legend:||||
|R = Readable bit<br>W = Writable bit|U = Unimplemented bit, read as ‘0’|||
|-n=ValueatPOR<br>‘1’=Bitisset|‘0’=Bitiscleared<br>x=Bitis|unknown||
bit31-0 | Unimplemented: Read as ‘0’ bit15-0 ADCBASE<15:0>: ADC ISR Base Address bits
This register, when read, contains the base address of the user's ADC ISR jump table. The interrupt vector address is determined by the IRQVS<2:0> bits of the ADCCON1 register specifying the amount of left shift done to the ARDYx status bits in the ADCDSTAT1 register, prior to adding with ADCBASE register. Interrupt vector address = Read value of[ADCBASE] Read value of ADCBASE = Value written to ADCBASE + x << IRQVS<2:0>, where ‘x’ is the smallest active analog input ID from the ADCDSTAT1 register (which has highest priority).
renner eee e rereerence eee eee DS70005425A-page 430 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
## REGISTER 29-20: ADCDMAST: ADC DMA STATUS REGISTER
**==> picture [447 x 121] intentionally omitted <==**
**----- Start of picture text -----**<br>
Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 24/16/8/0<br>omen | — | — | — | — | — | — | Reroen |<br>Pwrovrerr| — | — | — | — | — | — | rer<br>Powaonten| — | — | — | — | — | — | RAFoen_|<br>a es es es<br>**----- End of picture text -----**<br>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
- bit 31 DMAEN: DMA Interface Enable bit
- 1 = DMA interface is enabled
- 0 = DMA interface is disabled
- When DMAEN == 0, no data is being saved into the DMA FIFO, no SRAM writes occur and the DMA interface logic is being kept in Reset state.
- bit 30-25 Unimplemented: Read as ‘0’
- bit 24 RBFOIEN: RAM Buffer B FULL Interrupt Enable for channel 0.
- 1 = Interrupts are enabled and generated when the RBFx Status bit is set
- 0 = Interrupts are disabled
- bit 23 WROVRERR: Write Overflow Error in the DMA FIFO; set by hardware, cleared by hardware after a software read of the ADDMAST register.
- Note: |The write always occurs and the old data is being replaced with new data because the software missed reading the old data on time.
- bit 22-17 Unimplemented: Read as ‘0’
- bit 16 RBFO: RAM Buffer B FULL status bit for channel 0. This bit is self-clearing upon being read by software.
- bit 15 DMACNTEN: DMA Buffer Sample Count Enable bit
- The DMA interface will save the current sample count for each buffer in the table starting at the ADCCNTB address after each sample write into the corresponding buffer in the SRAM.
- bit14-9 Unimplemented: Read as ‘0’
- bit 8 RAFOIEN: RAM BufferA FULL Interrupt Enable for channel 0.
- 1 = Interrupts are enabled and generated when the RAFx Status bit is set
- 0 = Interrupts are disabled
- bit 7-1 Unimplemented: Read as ‘0’
- bit 0 RAFO: RAM BufferA FULL status bit for channel 0. This bit is self-clearing upon being read by software.
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PIC32MZ W1 and WFI32E01 Family
## seman
REGISTER 29-21: ADCCNTB: ADC CHANNEL SAMPLE COUNT BASE ADDRESS REGISTER
|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Range | 314/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 |27/19/11/3 |26/18/10/2|Bit<br>Bit<br>Bit<br>26/18/10/2 | 25/17/9/1<br>24/16/8/0|
|---|---|
|potas|e<br>J are PROT ee | ee | ee <br>| se Pet ee | me | ree <br>| ro Pe<br>se | ee | ee|UW<br> ee<br> ee<br> ee|
|Legend:||
|R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’||
|-n=ValueatPOR<br>‘1’=Bitisset<br>‘0’=Bitiscleared|x=Bitisunknown|
bit31-0 ADCCNTB<31:0>: ADC Channel Count Base Address: SRAM address for the DMA interface at which to save the first class channel bufferA sample count values into the System RAM. If first class channel x, x = 0...6, is ready with a new available sample data, and the DMA interface is currently saving data for channel x to RAM Buffer z (where z == 0 means BufferA and z == 1 means Buffer B, z depending on x), then the DMA interface will increment (+1) the 1 byte count value stored at System RAM address (ADCCNTB + 2*x + z). ADCCNTB works in conjunction with ADDMAB. The DMA interface will use ADCCNTB to save the buffer sample counts only if ADDMAST.DMA_CNT_EN is set to 1.
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REGISTER 29-22: ADCDMAB: ADC DMA BASE ADDRESS REGISTER
|REGISTER 29-22: ADCDMAB: ADC DMA BASE ADDRESS REGISTER|REGISTER 29-22: ADCDMAB: ADC DMA BASE ADDRESS REGISTER|
|---|---|
|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Range | 34/23/15/7 | 30/22/14/6 |29/21/13/5 | 28/20/12/4 |27/19/11/3|26/18/10/2 | 25/17/9/1<br>24/16/8/0||
|gpog<br>LF ROT ROT|ROT RO<br>| ROT ROOT ROT RO|
|aig<br>( RO |<br>Ro<br>| <br>:|ro | Ro [ Ro | Ro | Ro | RO ||
|isp<br>LF RO | Ro ||Ro | RO | RO | RO | ROR|
|vo (RO<br>Ro | <br>:|ROT ROT RO | ROT ROR|
|Legend:||
|R = Readable bit<br>W = Writable bit|U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR<br>‘1’=Bitisset|‘0’=Bitiscleared<br>x=Bitisunknown|
- bit31-0 _ADDMAB<31:0>: BASE ADDRESS for the DMA interface at which to save first class channels data into the System RAM. If first class channel x, x = 0...6, is ready with a new available sample data, and the DMAI interface is currently saving data for channel x to RAM Buffer z (where z == 0 means BufferA and z == 1 means Buffer B, z depending on x), and the current DMA x-counter value is y (y depending on x), then the DMA interface will store the 2-byte output data value at System RAM address (ADDMAB + (2*x + z)*2(0MABL*1) + 9*y Also, if ADDMAST.DMA_CNT_EN is set to 1, the DMA interface will store without delay the value y itself at the System RAM address (ADCCNTB + 2*x + 2).
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PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 29-23: ADCTRGSNS: ADC TRIGGER LEVEL/EDGE SENSITIVITY REGISTER
|Bit Range<br>Bit<br>31/23/15/7|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br> |30/22/14/6 | 29/21/13/5 |28/20/12/4 |27/19/11/3 |26/18/10/2 | 25/17/9/1|Bit<br>24/16/8/0|
|---|---|---|
|pw EA EEE EE eeEE<br>pe<br>ee eee<br>are a a a Ge<br>ee|||
|:|||
|Legend:|||
|R = Readable bit|W = Writable bit<br>U = Unimplemented bit, read as ‘0’||
|-n=ValueatPOR|‘1’=Bitisset<br>‘0’=Bitiscleared<br>x=Bitisunknown||
- bit 31-8 Unimplemented: Read as ‘0’
- bit 17-0 LVL<7:0>: Trigger Level and Edge Sensitivity bits
- 1 =Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as the trigger signal remains high)
- 0 = Analog input is sensitive to the positive edge of its trigger (this is the value after a Reset)
- Note 1: When an alternate input is used as the input source for a dedicated ADC module, the data output is still read from the Primary input Data Output register.
- 2: Reading the ADCDATAx register value after changing the FRACT bit converts the data into the format specified by FRACT bit.
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## REGISTER 29-24: ADCOTIME: DEDICATED ADC1 TIMING REGISTER
31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 24/16/8/0 eR a ae ee ee eeos Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
- bit 31-26 Unimplemented: Read as ‘0’
- bit 25-24 SELRES<1:0>:ADC1 Resolution Select bits 11 = 12 bits 10 = 10 bits 01 = 8 bits 00 = 6 bits
- Note: | Changing the resolution of the ADC does not shift the result in the corresponding ADCDATAx register. The result will still occupy 12 bits, with the corresponding lower unused bits set to ‘0’. For example, a resolution of 6 bits will result in ADCDATAx<5:0> being set to ‘0’, and ADCDATAx<11:6> holding the result.
- bit 23 BCHEND: If set to 1 and ifADDMAST.DMAEN[==][1,][the][output][data][of][first][class][channel][0,] will be saved by the DMA interface to the System RAM. If set to 0, this first class channel output data can be retrieved only via ADC SFRs.
- bit 22-16 ADCDIV<6:0>: ADC1 Clock Divisor bits These bits divide the ADC control clock with period T, to generate the clock for ADC1 (T,py). 1111111 = 254 * Ta =Tap4
0000011 =6* TQ=Tyyy
0000010 =4* TQ=Tyapy
0000001 =2* TQ=Tyapy
- 0000000 = Reserved
- bit 15-10 | Unimplemented: Read as ‘0’
bit 9-0 SAMC<9:0>: ADC1 Sample Time bits Where Tapp = period of the ADC conversion clock for the dedicated ADC controlled by the ADCDIV<6:0> bits. 1111111111 = 1025 Tapy
0000000001 =3 Tapy
0000000000 =2 Tapy
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## PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 29-25: ADCANCON: ADC ANALOG WARM-UP CONTROL REGISTER
**==> picture [494 x 602] intentionally omitted <==**
**----- Start of picture text -----**<br>
|||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Bit|Range|Bit|Bit|Bit|Bit|Bit|Bit|Bit|Bit|
|31/23/15/7|||30/22/14/6|| 29/21/13/5|| 28/20/12/4 | 27/19/11/3|| 26/18/10/2|||25/17/9/1|24/16/8/0|
|4|eT|
|ctrcixentsis|
|a=|
|&|
|werovy|[==rv|
|owen|[ann]|
|Legend:|HS|=|Hardware|Set|HC|=|Hardware|Cleared|
|R|=|Readable|bit|W|=|Writable|bit|U|=|Unimplemented|bit,|read|as|‘0’|
|-n|=|Value|at|POR|‘1’|=|Bit|is|set|‘0’|=|Bit|is|cleared|x|=|Bit|is|unknown|
|bit|31-28|||Unimplemented:|Read|as|‘0’|
|bit|27-24|WKUPCLKCNT<3:0>:|Wake-up|Clock|Count|bits|
|These|bits|represent|the|number|of|ADC|clocks|required|to|warm-up|the|ADC|module|before|it|can|
|perform|conversion.|Although|the|clocks|are|specific|to|each ADC,|the|WKUPCLKCNT|bit|is|common|to|
|all|ADC|modules.|
|1111|= 2"|=|32,768|clocks|
|0110|=|2°|=|64|clocks|
|0101|=|2°|=|32|clocks|
|0100|=|24|=|16|clocks|
|0011|=|24|=|16|clocks|
|0010|=|24|=|16|clocks|
|0001|=|24|=|16|clocks|
|0000|=|24|=|16|clocks|
|bit|23|WKIEN7:|Shared ADC|(ADC2)|Wake-up|Interrupt|Enable|bit|
|1|=|Enable|interrupt|and|generate|interrupt|when|the|WKRDY2|status|bit|is|set|
|0|=|Disable|interrupt|
|bit 22-17|||Unimplemented:|Read|as|‘0’|
|bit|16|WKIENO:|ADC1|Wake-up|Interrupt|Enable|bit|
|1|=|Enable|interrupt|and|generate|interrupt|when|the|WKRDYx|status|bit|is|set|
|0|=|Disable|interrupt|
|bit|15|WKRDY?7:|Shared|ADC|(ADC2)|Wake-up|Status|bit|
|1|= ADC2 Analog|and|bias|circuitry|ready|after|the wake-up|count|number|2QWKUPEXP|clocks|after|setting|
|ANEN2|to|‘1’|
|0|= ADC2 Analog|and|bias|circuitry|is|not|ready|
|Note:|This|bit|is|cleared|by|hardware when|the ANEN2|bit|is|cleared.|
|bit|14-9|Unimplemented:|Read|as|‘0’|
|bit|8|WKRDYO0:|ADC1|Wake-up|Status|bit|
|1|= ADC1|Analog|and|bias|circuitry|ready|after|the wake-up|count|number 2WKUPEXP|clocks|after|setting|
|ANEN‘1|to|‘1’|
|0|=ADC1|Analog|and|bias|circuitry|is|not|ready|
|Note:|These|bits|are|cleared|by|hardware|when|the ANENx|bit|is|cleared.|
**----- End of picture text -----**<br>
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## REGISTER 29-25: ADCANCON: ADC ANALOG WARM-UP CONTROL REGISTER (CONTINUED)
bit 7 ANEN7: Shared ADC (ADC2) Analog and Bias Circuitry Enable bit
1 =Analog and bias circuitry enabled. Once the analog and bias circuit is enabled, the ADC module needs a warm-up time, as defined by the WKUPCLKCNT<3:0> bits.
0 = Analog and bias circuitry disabled
bit 6-1 Unimplemented: Read as ‘0’
bit 0 ANENO: ADC1 Analog and Bias Circuitry Enable bits
1 =Analog and bias circuitry enabled. Once the analog and bias circuit is enabled, the ADC module needs a warm-up time, as defined by the WKUPCLKCNT<3:0> bits. 0 = Analog and bias circuitry disabled
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PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 29-26: ADCSYSCFG0: ADC SYSTEM CONFIGURATION REGISTER 0
|REGISTER 29-26: ADCSYSCFG0: ADC SYSTEM CONFIGURATION REGISTER 0||
|---|---|
|BitRange<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit|Bit|
|31/23/15/7 | 30/22/14/6 | 29/21/13/5 |28/20/12/4 |27/19/11/3 |26/18/10/2 | 25/17/9/1|24/16/8/0|
|a a<br>ee [ et | et | et | et | et | et | mt | <br>pf ants [Anta |_anis_|_awiz_|_aNTT_| ANTO_| ANO ||rt<br> ANS|
|Pf an [ane [ans [ana [ans [ana | ANT ||AND|
|Legend:<br>y = POR value is determined by the specific device||
|R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’||
|-n=ValueatPOR<br>‘1’=Bitisset<br>‘0’=Bitiscleared<br>x=Bitisunknown||
bit 31-20 Unimplemented: Read as ‘0’
bit 19-0 AN<19:0>: ADC Analog Input bits
These bits reflect the system configuration and are updated during boot-up time. By reading these readonly bits, the user application can determine whether or not an analog input in the device is available.
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## REGISTER 29-27: ADCDATAx: ADC OUTPUT DATA REGISTER (‘x’ = 0 TO 23)
|REGISTER 29-27: ADCDATAx: ADC OUTPUT DATA REGISTER (‘x’ = 0 TOTO 23)|REGISTER 29-27: ADCDATAx: ADC OUTPUT DATA REGISTER (‘x’ = 0 TOTO 23)|
|---|---|
|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 |28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1<br>24/16/8/0||
|siog FRO<br>ROT|ROT RO<br>ROT ROT ROT RO|
|| acne | R2_|_ee |e [|_eg [ee<br>ne | _pe ee<br>isp<br>FL RO | Ro | ro | ro [ Ro | Ro | Ro | RO |||
|——||
|Legend:||
|R = Readable bit<br>W = Writable bit|U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR<br>‘1’=Bitisset|‘0’=Bitiscleared<br>x=Bitisunknown|
- bit 31-0 DATA<31:0>: ADC Converted Data Output bits
- Note 1: When an alternate input is used as the input source for a dedicated ADC module, the data output is still read from the Primary input Data Output register.
- 2: Reading the ADCDATAx register value after changing the FRACT bit converts the data into the format specified by FRACT bit.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 439
PIC32MZ W1 and WFI32E01 Family
DS70005425A-page 440
Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
## 30.0 CONTROLLER AREA NETWORK (CAN)
## receive message FIFO
- NETWORK (CAN) - User-defined priority levels for message FIFOs used for transmission
- Note: This data sheet summarizes the - 16 acceptance filters for message filtering features of the PIC32MZ W1 family of - Three acceptance filter mask registers for devices. It is not intended to be a message filtering comprehensive reference source. To F ; sheet,complementrefer to[the] Section[information] : 34.oo“Controllerin this, data -+eAutomatic; responsea eeto: remote transmit request Area Network (CAN)” (DS60001154) in + Additional features: the “PIC32 Family Reference Manual”, - Loopback, Listen All Messages and Listen which is available from the Microchip Only modes for self-test, system diagnostics web site (www.microchip.com/PIC32). and bus monitoring
- ~ Low-Power Operating mades - CAN module is a bus master on the PIC32 System Bus
- - Buffers stored in volatile memory (SRAM) . . .
- - Dedicated time-stamp timer - Data-only Message Reception mode ’ ie .
- - Low pulse filter on receive lines for noise immunity
- Figure 30-1 illustrates the general structure of the CAN Hapalile :
The PIC32MZ W1 device supports one CAN module. The CAN module has the following key features: ;
- Slandanis camaplianee: - Full CAN 2.0B compliance - Programmable bit: nals prin tl Mibps
- « Message reception and transmission:
- 16 message FIFOs
- > Eat PMS Gall Weve Mpls S2imeasades fara total of 512 messages
- FIFO can be a transmit message FIFO ora
## FIGURE 30-1: CAN MODULE BLOCK DIAGRAM
**==> picture [358 x 276] intentionally omitted <==**
**----- Start of picture text -----**<br>
C1TX<br>xX] ~q— ps2 clk<br>16 Filters<br>3 Masks<br>C1RX CPU<br>x CAN Module<br>System Bus<br>Message<br>Buffer Size<br>9 System RAM up to 8 bytes<br>8<br>|<br>3<br>: SS<br>i<br>a<br>2<br>=)oo FIFOO FIFO1 —------------— FIFO15<br>Aeee<br>CAN Message FIFO (up to 16 FIFOs)<br>**----- End of picture text -----**<br>
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 441
## PIC32MZ W1 and WFI32E01 Family
## seman
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|©|2020Microchip|TechnologyInc.||PreliminaryDataSheet||DS70005425A-page443|
## PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 30-1: C1CON: CAN MODULE CONTROL REGISTER
|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit|Bit|
|---|---|
|Range | 31/23/15/7 |30/22/14/6 |29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0||
|ae<br>a a ==||
|‘© [~~ crmoneas<br>«cance[sO<br>dO||
|® [ont =<br>soe = onsy = =rd|rd|
|i<br>a a a a||
|Legend:<br>HC = Hardware Cleared S = Settable bit||
|R = Readable bit<br>W = Writable bit<br>P = Programmable bit<br>r = Reserved bit||
|U=Unimplementedbit<br>-n=BitValueatPOR:(‘0’,‘1’,x=Unknown)||
bit 31-28 Unimplemented: Read as ‘0’
- bit 27 ABAT: Abort All Pending Transmissions bit
1 = Signal all transmit buffers to abort transmission
0 = Module will clear this bit when all transmissions aborted
- bit 26-24 REQOP<2:0>: Request Operation Mode bits 111 = Set Listen All Messages mode
110 = Reserved - Do not use 101 = Reserved - Do not use 100 = Set Configuration mode
- 011 = Set Listen Only mode
- 010 = Set Loopback mode 001 = Set Disable mode 000 = Set Normal Operation mode
- bit 23-21 OPMOD<2:0>: Operation Mode Status bits 111 = Module is in Listen All Messages mode
- 110 = Reserved 101 = Reserved 100 = Module is in Configuration mode 011 = Module is in Listen Only mode
- 010 = Module is in Loopback mode
- 001 = Module is in Disable mode 000 = Module is in Normal Operation mode
bit 20 CANCAP: CAN Message Receive Time Stamp Timer Capture Enable bit 1 = CANTMR value is stored on valid message reception and is stored with the message
- 0 = Disable CAN message receive time stamp timer capture and stop CANTMR to conserve power
- bit 19-16 Unimplemented: Read as ‘0’ bit15 ON: CAN On bit!)
- 1 = CAN module is enabled
- 0 = CAN module is disabled
- bit 14 Unimplemented: Read as ‘0’
- Note 1: Ifthe user application clears the ON bit, it may take a number of cycles before the CAN module completes the current transaction and responds to the request. The user application should poll the CANBUSY bit to verify that the request has been honored.
renner eee e rereerence eee eee DS70005425A-page 444 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
## REGISTER 30-1: C1CON: CAN MODULE CONTROL REGISTER (CONTINUED)
|bit|13|SIDLE: CAN Stop in Idle bit|
|---|---|---|
|||1 = CAN Stops operation when system enters Idle mode|
|||0 = CAN continues operation when system enters Idle mode|
|bit|12|Unimplemented: Read as ‘0’|
|bit|11|CANBUSY: CAN Module is Busy bit|
|||1 = The CAN module is active|
|||0 = The CAN module is completely disabled|
|bit|10-5|Unimplemented: Read as ‘0’|
|bit|4-0|DNCNT<4:0>: Device Net Filter Bit Number bits|
|||10011-11111= Invalid Selection (compare up to 18-bits ofdata with EID)|
|||10010 = Compare up to data byte 2 bit 6 with EID17 (CiIRXFn<17>)|
|||00001 = Compare up to data byte 0 bit 7 with EIDO (CiIRXFn<0>)|
|||00000=Donotcomparedatabytes|
- Note 1: Ifthe user application clears the ON bit, it may take a number of cycles before the CAN module completes the current transaction and responds to the request. The user application should poll the CANBUSY bit to verify that the request has been honored.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 445
## PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 30-2: C1CFG: CAN BAUD RATE CONFIGURATION REGISTER
Range 31/23/15/7 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0 [= __| EE **e** ee a a | Legend: HC = Hardware Clear S = Settable bit R = Readable bit W = Writable bit P = Programmable bit r = Reserved bit U = Unimplemented bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
## bit 31-23 Unimplemented: Read as ‘0’
bit 22 WAKFIL: CAN Bus Line Filter Enable bit 1 = Use CAN bus line filter for wake-up
- 0 = CAN bus line filter is not used for wake-up
- bit 21-19 Unimplemented: Read as ‘0’ bit 18-16 SEG2PH<2:0>: Phase Buffer Segment 2 bits'-4) 111 =Lengthis 8x Ta
- 000 =Lengthis 1x Ta
- bit15 | SEG2PHTS: Phase Segment 2 Time Select bit'") 1 = Freely programmable 0 = Maximum of SEG1PH or Information Processing Time, whichever is greater
- bit14 | SAM: Sample of the CAN Bus Line bit!) 1 = Bus line is sampled three times at the sample point 0 = Bus line is sampled once at the sample point
- bit 13-11 SEG1PH<2:0>: Phase Buffer Segment 1 bits!4) 111 =Lengthis 8x Ta
## 000 = Length is 1x Ta
- Note 1: SEG2PH < SEG1PH. If SEG2PHTS is clear, SEG2PH will be set automatically.
- 2: 3 Time bit sampling is not allowed for BRP < 2.
- 3: SJW < SEG2PH.
- 4: The Time Quanta per bit must be greater than 7 (that is, TQBIT > 7).
- 5: This register can only be modified when the CAN module is in Configuration mode (OPMOD<2:0> (C1CON<23:21>) = 100).
renner eee e rereerence eee eee DS70005425A-page 446 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
REGISTER 30-2: C1CFG: CAN BAUD RATE CONFIGURATION REGISTER (CONTINUED) bit 10-8 _PRSEG<2:0>: Propagation Time Segment bits'4) 111 =Length is 8x Ta
- 000 =Lengthis 1x Ta
- bit 7-6 | SJW<1:0>: Synchronization Jump Width bits) 11 =Length is 4x Ta 10 =Length is 3 x Ta 01 = Length is 2 x Ta 00 =Length is 1 x Ta
- bit 5-0 BRP<5:0>: Baud Rate Prescaler bits 111111 = Ta = (2 x 64)/TPB2_CLK 111110 = TQ = (2 x 63)/TPB2_CLK 000001 = TQ = (2 x 2)/TPB2_CLK 000000 = TQ = (2 x 1)/TPB2_CLK
- Note 1: SEG2PH < SEG1PH. If SEG2PHTS is clear, SEG2PH will be set automatically. 2: 3 Time bit sampling is not allowed for BRP < 2. 3: SJW < SEG2PH.
- 4: The Time Quanta per bit must be greater than 7 (that is, TQBIT > 7).
- 5: This register can only be modified when the CAN module is in Configuration mode (OPMOD<2:0> (C1CON<23:21>) = 100).
## me
© 2020 Microchip Technology Inc. Preliminary Data Sheet
DS70005425A-page 447
## PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 30-3: C1INT: CAN INTERRUPT REGISTER
|Bit<br>Range|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br> | 34/23/15/7 | 30/22/14/6 |29/21/13/5 | 28/20/12/4 |27/19/11/3 |26/18/10/2 | 25/17/9/1<br>24/16/8/0|
|---|---|
|%||"wre | wake | cerRie | Senne| Reove | —<br>7. — | —|
|6aT|aT<br>oie<br>erwrie [re[ee ||
|°|[ower [war [cerrif |Serr<br>[ peor | — | —<br>7. — ||
|°|(ea<br>noi erie<br>ee [TF ||
|Legend:||
|R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’||
|-n=ValueatPOR<br>‘1’=Bitisset<br>‘0’=Bitiscleared<br>x=Bitisunknown||
- bit 31 IVRIE: Invalid Message Received Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled
- bit 30 WAKIE: CAN Bus Activity Wake-up Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled
- bit 29 CERRIE: CAN Bus Error Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled
- bit 28 SERRIE: System Error Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled
- bit 27 RBOVIE: Receive Buffer Overflow Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled
- bit 26-20 Unimplemented: Read as ‘0’ bit 19 MODIE: Mode Change Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled
- bit 18 CTMRIE: CAN Timestamp Timer Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled
- bit 17 RBIE: Receive Buffer Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled
- bit 16 TBIE: Transmit Buffer Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled
- bit 15 IVRIF: Invalid Message Received Interrupt Flag bit 1 =An invalid messages interrupt has occurred 0 =An invalid message interrupt has not occurred
Note 1: This bit can only be cleared by turning the CAN module off and on by clearing or setting the ON bit (C1CONK<15>).
renner eee e rereerence eee eee DS70005425A-page 448 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
## REGISTER 30-3: C1INT: CAN INTERRUPT REGISTER (CONTINUED)
## bit 14 WAKIF: CAN Bus Activity Wake-up Interrupt Flag bit 1 =A bus wake-up activity interrupt has occurred
- 0 =A bus wake-up activity interrupt has not occurred
- bit 13 CERRIF: CAN Bus Error Interrupt Flag bit 1 =ACAN bus error has occurred 0 =ACAN bus error has not occurred
- bit 12 SERRIF: System Error Interrupt Flag bit 1 =Asystem error occurred (typically an illegal address was presented to the System Bus) 0 =A system error has not occurred
- bit 11 RBOVIF: Receive Buffer Overflow Interrupt Flag bit 1 =Areceive buffer overflow has occurred 0 =A receive buffer overflow has not occurred
- bit 10-4 Unimplemented: Read as ‘0’ bit 3 MODIF: CAN Mode Change Interrupt Flag bit 1 =ACAN module mode change has occurred (OPMOD<z2:0> has changed to reflect REQOP) 0 =A CAN module mode change has not occurred
- bit 2 CTMRIF: CAN Timer Overflow Interrupt Flag bit 1 =A CAN timer (CANTMR) overflow has occurred 0 =A CAN timer (CANTMR) overflow has not occurred
- bit 1 RBIF: Receive Buffer Interrupt Flag bit 1 =A receive buffer interrupt is pending 0 =A receive buffer interrupt is not pending
- bit 0 TBIF: Transmit Buffer Interrupt Flag bit 1 =A transmit buffer interrupt is pending 0 =A transmit buffer interrupt is not pending
Note 1: This bit can only be cleared by turning the CAN module off and on by clearing or setting the ON bit (C1CON<15>).
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 449
## PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 30-4: C1VEC: CAN INTERRUPT CODE REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 24/16/8/0 pw SE pie SS eS eee a a a a 7:0 1 a 2 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-13 Unimplemented: Read as ‘0’
bit 12-8 FILHIT<4:0>: Filter Hit Number bit 11111 = Filter 31 11110 = Filter 30
00001 = Filter 1
00000 = Filter 0
bit 7 Unimplemented: Read as ‘0’ bit6-O ICODE<6:0>: Interrupt Flag Code bits!) 1001000-1111111 = Reserved
1001000 = Invalid Message Received (IVRIF) 1000111 = CAN Module Mode Change (MODIF) 1000110 = CAN Timestamp Timer (CTMRIF) 1000101 = Bus Bandwidth Error (SERRIF) 1000100 =Address Error Interrupt (SERRIF) 1000011 = Receive FIFO Overflow Interrupt (RBOVIF) 1000010 = Wake-up interrupt (WAKIF) 1000001 = Error Interrupt (CERRIF) 1000000 = No interrupt 0100000-0111111 = Reserved 0011111 = FIFO31 interrupt (CIFSTAT<31> set) 0011110 = FIFO30 interrupt (CIFSTAT<30> set)
0000001 = FIFO1 interrupt (CIFSTAT<1> set) 0000000 = FIFOO interrupt (CIFSTAT<O> set)
Note 1: These bits are only updated for enabled interrupts.
renner eee e rereerence eee eee DS70005425A-page 450 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
## REGISTER 30-5: C1TREC: CAN TRANSMIT/RECEIVE ERROR COUNT REGISTER
**==> picture [449 x 69] intentionally omitted <==**
**----- Start of picture text -----**<br>
||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Range|||31/23/15/7|||30/22/14/6|| 29/21/13/5|||28/20/12/4|||27/19/11/3|||26/18/10/2|||25/17/9/1|24/16/8/0|
|||=|||||=|||||=|||=~|||=|[||=|||
|ST|
|80x|xe|twars|||RxWaRN|||EWARN|
**----- End of picture text -----**<br>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-22 Unimplemented: Read as ‘0’ bit 21 TXBO: Transmitter in Error State Bus OFF (TERRCNT = 256) bit 20 TXBP: Transmitter in Error State Bus Passive (TERRCNT = 128) bit 19 RXBP: Receiver in Error State Bus Passive (RERRCNT = 128) bit 18 TXWARN: Transmitter in Error State Warning (128 > TERRCNT = 96) bit 17 RXWARN: Receiver in Error State Warning (128 > RERRCNT = 96) bit 16 EWARN: Transmitter or Receiver is in Error State Warning bit 15-8 TERRCNT<7:0>: Transmit Error Counter bit 7-0 RERRCNT<7:0>: Receive Error Counter
## REGISTER 30-6: C1FSTAT: CAN FIFO STATUS REGISTER
Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bitis set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 FIFOIP<31:0>: FIFOx Interrupt Pending bits
1 = One or more enabled FIFO interrupts are pending
- 0 = No FIFO interrupts are pending
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 451
PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 30-7: C1RXOVF: CAN RECEIVE FIFO OVERFLOW STATUS REGISTER
|Bit|Bit|Bit|Bit|Bit|Bit|Bit|Bit|Bit|
|---|---|---|---|---|---|---|---|---|
|Range|31/23/15/7|| 30/22/14/6 | 29/21/13/5||| 28/20/12/4 | 27/19/11/3|||26/18/10/2|| 25/17/9/1 | 24/16/8/0||
|:|||||||||
|:|||||||||
|:|||||||||
|:|||||||||
|Legend:|||||||||
|R = Readable bit||W = Writable bit||U = Unimplemented bit, read as ‘0’|||||
|-n=ValueatPOR||‘1’=Bitisset||‘0’=Bitiscleared||x=Bitisunknown|||
bit 31-0 RXOVF<31:0>: FIFOx Receive Overflow Interrupt Pending bit 1 = FIFO has overflowed 0 = FIFO has not overflowed
## REGISTER 30-8: C1TMR: CAN TIMER REGISTER
|Bit|Bit||Bit|Bit||Bit|Bit||Bit|Bit|Bit|
|---|---|---|---|---|---|---|---|---|---|---|---|
|Range ||31/23/15/7|| 30/22/14/6 | 29/21/13/5|||| 28/20/12/4 | 27/19/11/3||||26/18/10/2||| 25/17/9/1 | 24/16/8/0||
|sos<br>:||||||||||||
|:||||||||||||
|:||||||||||||
|:||||||||||||
|Legend:||||||||||||
|R = Readable bit||W|= Writable bit||U|= Unimplemented bit, read|||as ‘0’|||
|-n=ValueatPOR||‘1’|=Bitisset||‘0’|=Bitiscleared||x=Bitisunknown||||
- bit 31-0 CANTS<15:0>: CAN Time Stamp Timer bits
- This is a free-running timer that increments every CANTSPRE system clocks when the CANCAP bit (CiCON<20>) is set.
- bit 15-0 CANTSPRE<15:0>: CAN Time Stamp Timer Prescaler bits 1111 1111 1111 1111 =CAN Time Stamp (CANTS) timer increments every 65,535 system clocks
0000 0000 0000 0000 = CAN Time Stamp (CANTS) timer increments every system clock
- Note 1: C1TMRwill be frozen when CANCAP = 0. 2: The C1TMR prescaler count will be reset on any write to C1TMR (CANTSPRE will be unaffected).
renner eee e rereerence eee eee DS70005425A-page 452 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
## REGISTER 30-9: C1RXMN: CAN ACCEPTANCE FILTER MASK ‘n’ REGISTER (‘n’ = 0-2)
Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0 | Pinos SCdC CCITT , Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
- bit 31-21 SID<10:0>: Standard Identifier bits
- 1 = Include bit, SIDx, in filter comparison 0 = Bit SIDx is ‘don’t care’ in filter operation
- bit 20 Unimplemented: Read as ‘0’ bit 19 MIDE: Identifier Receive Mode bit
- 1 = Match only message types (standard/extended address) that correspond to the EXID bit in filter
- 0 = Match either standard or extended address message if filters match (that is, if (Filter SID) = (Message SID) or if (FILTER SID/EID) = (Message SID/EID))
- bit 18 Unimplemented: Read as ‘0’
- bit 17-0 EID<17:0>: Extended Identifier bits
- 1 = Include bit, EIDx, in filter comparison 0 = Bit EIDx is ‘don’t care’ in filter operation
Note: This register can only be modified when the CAN module is in Configuration mode (OPMOD<2:0> (C1CON<23:21>) = 100).
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 453
PIC32MZ W1 and WFI32E01 Family
## seman
REGISTER 30-10: C1FLTCONO: CAN FILTER CONTROL REGISTER 0
|Bit|Bit<br>Bit<br>Bit||Bit|Bit|Bit<br>Bit|Bit<br>Bit|Bit|
|---|---|---|---|---|---|---|---|
|Range | 31/23/15/7 |30/22/14/6 |29/21/13/5 | 28/20/12/4 | 27/19/11/3||||||26/18/10/2 | 25/17/9/1 | 24/16/8/0|||
|:||||||||
|:||||||||
|:||||||||
|:||||||||
|Legend:||||||||
|R = Readable bit<br>W = Writable bit||U|= Unimplemented bit, read as ‘0’|||||
|-n = Value at POR<br>‘1’ = Bit is set||‘0’|= Bit is cleared||x = Bit|is unknown||
|bit 31|FLTEN3: Filter 3 Enable bit|||||||
||1 = Filter is enabled|||||||
||0 = Filter is disabled|||||||
|bit 30-29|MSEL3<1:0>: Filter<br>3 Mask Select|bits||||||
||11 = Acceptance Mask 3 selected|||||||
||10 = Acceptance Mask 2 selected|||||||
||01 = Acceptance Mask 1 selected|||||||
||00 = Acceptance Mask 0 selected|||||||
|bit 28-24|FSEL3<4:0>: FIFO Selection bits|||||||
||11111 = Message matching filter is|stored|in FIFO buffer 31|||||
||11110 = Message matching filter is|stored|in FIFO buffer 30|||||
||00001 = Message matching filter is|stored|in FIFO buffer 1|||||
||00000 = Message matching filter is|stored|in FIFO buffer 0|||||
|bit 23|FLTENZ2: Filter 2 Enable bit|||||||
||1 = Filter is enabled|||||||
||0 = Filter is disabled|||||||
|bit 22-21|MSEL2<1:0>: Filter<br>2 Mask Select|bits||||||
||11 = Acceptance Mask 3 selected|||||||
||10 = Acceptance Mask 2 selected|||||||
||01 = Acceptance Mask 1 selected|||||||
||00 = Acceptance Mask 0 selected|||||||
|bit 20-16|FSEL2<4:0>: FIFO Selection bits|||||||
||11111 = Message matching filter is|stored|in FIFO buffer 31|||||
||11110 = Message matching filter is|stored|in FIFO buffer 30|||||
||00001 = Message matching filter is|stored|in FIFO buffer 1|||||
||00000 = Message matching filter is|stored|in FIFO buffer 0|||||
|bit 15|FLTEN1: Filter<br>1 Enable bit|||||||
||1 = Filter is enabled|||||||
||0 = Filter is disabled|||||||
|Note:|The bits in this register can only be|modified if the corresponding filter enable (FLTENn) bit is ‘0’.||||||
|rennereeeerereerence||eee|||eee|||
|DS70005425A-page454||PreliminaryDataSheet||||©2020MicrochipTechnologyInc.||
PIC32MZ W1 and WFI32E01 Family
smn
## REGISTER 30-10: C1FLTCONO: CAN FILTER CONTROL REGISTER 0 (CONTINUED)
|bit|14-13|MSEL1<1:0>: Filter<br>1 Mask Select bits|
|---|---|---|
|||11 = Acceptance Mask 3 selected|
|||10 = Acceptance Mask 2 selected|
|||01 = Acceptance Mask 1 selected|
|||00 = Acceptance Mask 0 selected|
|bit|12-8|FSEL1<4:0>: FIFO Selection bits|
|||11111 = Message matching filter is stored in FIFO buffer 31|
|||11110 = Message matching filter is stored in FIFO buffer 30|
|||00001 = Message matching filter is stored in FIFO buffer 1|
|||00000 = Message matching filter is stored in FIFO buffer 0|
|bit|7|FLTENO: Filter 0 Enable bit|
|||1 = Filter is enabled|
|||0 = Filter is disabled|
|bit|6-5|MSELO0<1:0>: Filter<br>0 Mask Select bits|
|||11 = Acceptance Mask 3 selected|
|||10 = Acceptance Mask 2 selected|
|||01 = Acceptance Mask 1 selected|
|||00 = Acceptance Mask 0 selected|
|bit|4-0|FSEL0<4:0>: FIFO Selection bits|
|||11111 = Message matching filter is stored in FIFO buffer 31|
|||11110 = Message matching filter is stored in FIFO buffer 30|
|||00001 = Message matching filter is stored in FIFO buffer 1|
|||00000=MessagematchingfilterisstoredinFIFObuffer0|
Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 455
## PIC32MZ W1 and WFI32E01 Family
## seman
|REGISTER 30-11:|C1FLTCON1: CAN|C1FLTCON1: CAN|FILTER CONTROL REGISTER 1|FILTER CONTROL REGISTER 1|FILTER CONTROL REGISTER 1|FILTER CONTROL REGISTER 1|||
|---|---|---|---|---|---|---|---|---|
|Bit<br>Bit||Bit|Bit|Bit|Bit|Bit|Bit|Bit|
|Range<br>31/23/15/7||30/22/14/6 |29/21/13/5 | 28/20/12/4 | 27/19/11/3|||||26/18/10/2|| 25/17/9/1 | 24/16/8/0||
|:|||||||||
|:|||||||||
|:|||||||||
|:|||||||||
|Legend:|||||||||
|R = Readable bit||W = Writable bit||U = Unimplemented bit, read as ‘0’|||||
|-n=ValueatPOR||‘1’=Bitisset||‘0’=Bitiscleared||x=Bitisunknown|||
bit 31 FLTEN7: Filter 7 Enable bit
1 = Filter is enabled
0 = Filter is disabled bit 30-29 MSEL7<1:0>: Filter 7 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 28-24 FSEL7<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message matching filter is stored in FIFO buffer 30
00001 = Message matching filter is stored in FIFO buffer 1 00000 = Message matching filter is stored in FIFO buffer 0 bit 23 FLTEN6: Filter 6 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 22-21 MSEL6<1:0>: Filter 6 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 20-16 FSEL6<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message matching filter is stored in FIFO buffer 30 00001 = Message matching filter is stored in FIFO buffer 1 00000 = Message matching filter is stored in FIFO buffer 0 bit 15 FLTENS: Filter 17 Enable bit 1 = Filter is enabled 0 = Filter is disabled
Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
renner eee e rereerence eee eee DS70005425A-page 456 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
## REGISTER 30-11: C1FLTCON1: CAN FILTER CONTROL REGISTER 1 (CONTINUED)
bit 14-13 MSEL5<1:0>: Filter 5 Mask Select bits
- 11 = Acceptance Mask 3 selected
- 10 = Acceptance Mask 2 selected
- 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected
- bit 12-8 FSEL5<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message matching filter is stored in FIFO buffer 30 00001 = Message matching filter is stored in FIFO buffer 1 00000 = Message matching filter is stored in FIFO buffer 0
- bit 7 FLTEN4: Filter 4 Enable bit 1 = Filter is enabled 0 = Filter is disabled
- bit6-5 = MSEL4<1:0>: Filter4 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected
- bit4-O0 | FSEL4<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message matching filter is stored in FIFO buffer 30 00001 = Message matching filter is stored in FIFO buffer 1 00000 = Message matching filter is stored in FIFO buffer 0
Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 457
PIC32MZ W1 and WFI32E01 Family
## seman
REGISTER 30-12: C1FLTCON2: CAN FILTER CONTROL REGISTER 2
|Bit|Bit<br>Bit<br>Bit||Bit|Bit|Bit|Bit|Bit|
|---|---|---|---|---|---|---|---|
|Range|31/23/15/7<br>| 30/22/14/6 | 29/21/13/5 |||28/20/12/4 | 27/19/11/3|||26/18/10/2 | 25/17/9/1 | 24/16/8/0|||
|:||||||||
|:||||||||
|:||||||||
|:||||||||
|Legend:||||||||
|R = Readable bit<br>W = Writable bit|||U = Unimplemented bit, read as ‘0’|||||
|-n = Value|at POR<br>‘1’ = Bit is set||‘0’ = Bit is cleared||x = Bit is unknown|||
|bit 31|FLTEN11: Filter 11 Enable bit|||||||
||1 = Filter is enabled|||||||
||0 = Filter is disabled|||||||
|bit 30-29|MSEL11<1:0>: Filter 11 Mask Select bits|||||||
||11 =Acceptance Mask 3 selected|||||||
||10 =Acceptance Mask 2 selected|||||||
||01 =Acceptance Mask 1 selected|||||||
||00 =Acceptance Mask 0 selected|||||||
|bit 28-24|FSEL11<4:0>: FIFO Selection bits|||||||
||11111 = Message matching filter is|stored in FIFO buffer 31||||||
||11110 = Message matching filter is|stored in FIFO buffer 30||||||
||00001 = Message matching filter is|stored in FIFO buffer 1||||||
||00000 = Message matching filter is|stored in FIFO buffer 0||||||
|bit 23|FLTEN10: Filter 10 Enable bit|||||||
||1 = Filter is enabled|||||||
||0 = Filter is disabled|||||||
|bit 22-21|MSEL10<1:0>: Filter 10 Mask Select bits|||||||
||11 =Acceptance Mask 3 selected|||||||
||10 =Acceptance Mask 2 selected|||||||
||01 =Acceptance Mask 1 selected|||||||
||00 =Acceptance Mask 0 selected|||||||
|bit 20-16|FSEL10<4:0>: FIFO Selection bits|||||||
||11111 = Message matching filter is|stored in FIFO buffer 31||||||
||11110 = Message matching filter is|stored in FIFO buffer 30||||||
||00001 = Message matching filter is|stored in FIFO buffer 1||||||
||00000 = Message matching filter is|stored in FIFO buffer 0||||||
|bit 15|FLTENG: Filter<br>9 Enable bit|||||||
||1 = Filter is enabled|||||||
||0 = Filter is disabled|||||||
|Note:|The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.|||||||
|rennereeeerereerence||eee|||eee|||
|DS70005425A-page458||PreliminaryDataSheet|||©2020MicrochipTechnologyInc.|||
PIC32MZ W1 and WFI32E01 Family
smn
## REGISTER 30-12: C1FLTCON2: CAN FILTER CONTROL REGISTER 2 (CONTINUED)
|bit|14-13|MSEL9<1:0>: Filter<br>9 Mask Select bits|
|---|---|---|
|||11 =Acceptance Mask 3 selected|
|||10 =Acceptance Mask 2 selected|
|||01 =Acceptance Mask 1 selected|
|||00 =Acceptance Mask 0 selected|
|bit|12-8||FSEL9<4:0>: FIFO Selection bits|
|||11111 = Message matching filter is stored in FIFO buffer 31|
|||11110 = Message matching filter is stored in FIFO buffer 30|
|||00001 = Message matching filter is stored in FIFO buffer 1|
|||00000 = Message matching filter is stored in FIFO buffer 0|
|bit|7|FLTENS8: Filter 8 Enable bit|
|||1 = Filter is enabled|
|||0 = Filter is disabled|
|bit|6-5|MSEL8<1:0>: Filter<br>8 Mask Select bits|
|||11 =Acceptance Mask 3 selected|
|||10 =Acceptance Mask 2 selected|
|||01 =Acceptance Mask 1 selected|
|||00 =Acceptance Mask 0 selected|
|bit|4-0|FSEL8<4:0>: FIFO Selection bits|
|||11111 = Message matching filter is stored in FIFO buffer 31|
|||11110 = Message matching filter is stored in FIFO buffer 30|
|||00001 = Message matching filter is stored in FIFO buffer 1|
|||00000=MessagematchingfilterisstoredinFIFObuffer0|
Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 459
PIC32MZ W1 and WFI32E01 Family
## seman
REGISTER 30-13: C1FLTCON3: CAN FILTER CONTROL REGISTER 3
|Bit|Bit<br>Bit<br>Bit|Bit|Bit|Bit|Bit|Bit|
|---|---|---|---|---|---|---|
|Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3|||||26/18/10/2|| 25/17/9/1 | 24/16/8/0||
|:|||||||
|:|||||||
|:|||||||
|:|||||||
|Legend:|||||||
|R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’|||||||
|-n = Value at POR<br>‘1’ = Bit is set<br>‘0’||= Bit is cleared||x = Bit is unknown|||
|bit 31|FLTEN15: Filter 15 Enable bit||||||
||1 = Filter is enabled||||||
||0 = Filter is disabled||||||
|bit 30-29|MSEL15<1:0>: Filter 15 Mask Select bits||||||
||11 =Acceptance Mask 3 selected||||||
||10 =Acceptance Mask 2 selected||||||
||01 =Acceptance Mask 1 selected||||||
||00 =Acceptance Mask 0 selected||||||
|bit 28-24|FSEL15<4:0>: FIFO Selection bits||||||
||11111 = Message matching filter is stored in FIFO buffer 31||||||
||11110 = Message matching filter is stored in FIFO buffer 30||||||
||00001 = Message matching filter is stored in FIFO buffer 1||||||
||00000 = Message matching filter is stored in FIFO buffer 0||||||
|bit 23|FLTEN14: Filter 14 Enable bit||||||
||1 = Filter is enabled||||||
||0 = Filter is disabled||||||
|bit 22-21|MSEL14<1:0>: Filter 14 Mask Select bits||||||
||11 =Acceptance Mask 3 selected||||||
||10 =Acceptance Mask 2 selected||||||
||01 =Acceptance Mask 1 selected||||||
||00 =Acceptance Mask 0 selected||||||
|bit 20-16|FSEL14<4:0>: FIFO Selection bits||||||
||11111 = Message matching filter is stored in FIFO buffer 31||||||
||11110 = Message matching filter is stored in FIFO buffer 30||||||
||00001 = Message matching filter is stored in FIFO buffer 1||||||
||00000 = Message matching filter is stored in FIFO buffer 0||||||
|bit 15|FLTEN13: Filter 13 Enable bit||||||
||1 = Filter is enabled||||||
||0=Filterisdisabled||||||
Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
|rennereeeerereerence|eee|eee|
|---|---|---|
|DS70005425A-page460|PreliminaryDataSheet|©2020MicrochipTechnologyInc.|
PIC32MZ W1 and WFI32E01 Family
smn
## REGISTER 30-13: C1FLTCON3: CAN FILTER CONTROL REGISTER 3 (CONTINUED)
|bit|14-13|MSEL13<1:0>: Filter 13 Mask Select bits|
|---|---|---|
|||11 =Acceptance Mask 3 selected|
|||10 =Acceptance Mask 2 selected|
|||01 =Acceptance Mask 1 selected|
|||00 =Acceptance Mask 0 selected|
|bit|12-8|FSEL13<4:0>: FIFO Selection bits|
|||11111 = Message matching filter is stored in FIFO buffer 31|
|||11110 = Message matching filter is stored in FIFO buffer 30|
|||00001 = Message matching filter is stored in FIFO buffer 1|
|||00000 = Message matching filter is stored in FIFO buffer 0|
|bit|7|FLTEN12: Filter 12 Enable bit|
|||1 = Filter is enabled|
|||0 = Filter is disabled|
|bit|6-5|MSEL12<1:0>: Filter 12 Mask Select bits|
|||11 =Acceptance Mask 3 selected|
|||10 =Acceptance Mask 2 selected|
|||01 =Acceptance Mask 1 selected|
|||00 =Acceptance Mask 0 selected|
|bit|4-0|FSEL12<4:0>: FIFO Selection bits|
|||11111 = Message matching filter is stored in FIFO buffer 31|
|||11110 = Message matching filter is stored in FIFO buffer 30|
|||00001 = Message matching filter is stored in FIFO buffer 1|
|||00000=MessagematchingfilterisstoredinFIFObuffer0|
Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 461
PIC32MZ W1 and WFI32E01 Family
seman
## REGISTER 30-14: C1RXFn: CAN ACCEPTANCE FILTER ‘n’ REGISTER7 (‘n’ = 0-15)
Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 24/16/8/0 eo CC CO OdYSCOC‘i ITS , Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
## bit 31-21 SID<10:0>: Standard Identifier bits
1 = Message address bit SIDx must be ‘1’ to match filter
0 = Message address bit SIDx must be ‘0’ to match filter bit 20 Unimplemented: Read as ‘0’ bit 19 EXID: Extended Identifier Enable bits 1 = Match only messages with extended identifier addresses 0 = Match only messages with standard identifier addresses bit 18 Unimplemented: Read as ‘0’ bit17-0 EID<17:0>: Extended Identifier bits 1 = Message address bit EIDx must be ‘1’ to match filter 0 = Message address bit EIDx must be ‘0’ to match filter
Note: This register can only be modified when the filter is disabled (FLTENn = 0).
renner eee e rereerence eee eee DS70005425A-page 462 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
## REGISTER 30-15: C1FIFOBA: CAN MESSAGE BUFFER BASE ADDRESS REGISTER
**==> picture [440 x 77] intentionally omitted <==**
**----- Start of picture text -----**<br>
|||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Range|||31/23/15/7|||30/22/14/6|||29/21/13/5|| 28/20/12/4|||27/19/11/3|| 26/18/10/2|||25/17/9/1|24/16/8/0|
|,|
**----- End of picture text -----**<br>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
- bit 31-2 C1FIFOBA<29:0>: CAN FIFO Base Address bits
- These bits define the base address of all message buffers. Individual message buffers are located based on the size of the previous message buffers. This address is a physical address. Note that bits <1:0> are read-only and read ‘0’, forcing the messages to be 32-bit word-aligned in device RAM.
- bit 1-0 Unimplemented: Read as ‘0’
- Note 1: This bit is unimplemented and will always read ‘0’, which forces word-alignment of messages. 2: This register can only be modified when the CAN module is in Configuration mode (OPMOD<2:0> (C1CONK<23:21>) = 100).
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 463
PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 30-16: C1FIFOCONn: CAN FIFO CONTROL REGISTER ‘n’ (‘n’ = 0-15)
|Bit|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit|
|---|---|
|Range|| 31/23/15/7 | 30/22/14/6 | 29/21/13/5 |28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1<br>24/16/8/0|
|pee <br>23:16<br>pe|EB Eee<br> SeEe|
|°|[>= Trreset [une [oow®T=<br>-— | - | —|
|:||
|Legend:||
|R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’||
|-n=ValueatPOR<br>‘1’=Bitisset<br>‘0’=Bitiscleared<br>x=Bitisunknown||
bit 31-21 Unimplemented: Read as ‘0’
bit 20-16 FSIZE<4:0>: FIFO Size bits!)
11111 = FIFO is 32 messages deep
00010 = FIFO is 3 messages deep
00001 = FIFO is 2 messages deep
- 00000 = FIFO is 1 message deep
- bit 15 Unimplemented: Read as ‘0’ bit 14 FRESET: FIFO Reset bits
- 1 = FIFO will be reset when bit is set, cleared by hardware when FIFO is reset. After setting, the user application should poll whether this bit is clear before taking any action
- 0 = No effect
- bit 13 UINC: Increment Head/Tail bit TXEN = 1: (FIFO configured as a Transmit FIFO) When this bit is set, the FIFO head will increment by a single message TXEN = 0: (FIFO configured as a Receive FIFO) When this bit is set, the FIFO tail will increment by a single message
- bit12 | DONLY: Store Message Data Only bit") TXEN = 1: (FIFO configured as a Transmit FIFO) This bit is not used and has no effect. TXEN = 0: (FIFO configured as a Receive FIFO) 1 = Only data bytes will be stored in the FIFO 0 = Full message is stored, including identifier
- bit 11-8 Unimplemented: Read as ‘0’ bit 7 TXEN: TX/RX Buffer Selection bit
- 1 = FIFO is a Transmit FIFO 0 = FIFO is a Receive FIFO
- Note 1: These bits can only be modified when the CAN module is in Configuration mode (OPMOD<2:0> bits (C1CON<23:21>) = 100).
- 2: This bit is updated when a message completes (or aborts) or when the FIFO is reset.
- 3: This bit is reset on any read of this register or when the FIFO is reset.
renner eee e rereerence eee eee DS70005425A-page 464 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
**==> picture [436 x 361] intentionally omitted <==**
**----- Start of picture text -----**<br>
|||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|REGISTER|30-16:|C1FIFOCONn:|CAN|FIFO|CONTROL|REGISTER|‘n’|(‘n’|=|0-15)|(CONTINUED)|
|bit 6|TXABAT:|Message Aborted|bit!)|
|1|=|Message was|aborted|
|0|=|Message|completed|successfully|
|bit|5|TXLARB:|Message|Lost Arbitration|bit‘)|
|1|=|Message|lost|arbitration|while|being|sent|
|0|=|Message|did|not|lose|arbitration|while|being|sent|
|bit 4|TXERR:|Error|Detected|During|Transmission|bit)|
|1|=A|bus|error|occurred|while|the|message|was|being|sent|
|0|=A|bus|error|did|not|occur|while|the|message|was|being|sent|
|bit|3|TXREQ:|Message|Send|Request|
|TXEN|=|1:|(FIFO|configured|as|a|Transmit|FIFO)|
|Setting|this|bit|to|‘1’|requests|sending|a|message.|
|The|bit|will|automatically|clear when|all|the|messages|queued|in|the|FIFO|are|successfully|sent.|
|Clearing|the|bit|to|‘0’|while|set|(‘1’)|will|request|a|message|abort.|
|TXEN|=|0:|(FIFO|configured|as|a|Receive|FIFO)|
|This|bit|has|no|effect.|
|bit|2|RTREN:|Auto|RTR|Enable|bit|
|1|=|When|a|remote|transmit|is|received,|TXREQ|will|be|set|
|0|=|When|a|remote|transmit|is|received,|TXREQ|will|be|unaffected|
|bit|1-0|TXPR<1:0>:|Message|Transmit|Priority|bits|
|11|=|Highest|Message|Priority|
|10|=|High|Intermediate|Message|Priority|
|01|=|Low|Intermediate|Message|Priority|
|00|=|Lowest|Message|Priority|
|Note|1:|These|bits|can|only|be|modified|when|the|CAN|module|is|in|Configuration|mode|(OPMOD<2:0>|bits|
|(C1CON<23:21>)|=|100).|
|2:|This|bit|is|updated|when|a|message|completes|(or|aborts)|or|when|the|FIFO|is|reset.|
|3:|This|bit|is|reset|on|any|read|of|this|register|or when|the|FIFO|is|reset.|
**----- End of picture text -----**<br>
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 465
## PIC32MZ W1 and WFI32E01 Family
## seman
**==> picture [371 x 10] intentionally omitted <==**
**----- Start of picture text -----**<br>
REGISTER 30-17: C1FIFOINTn: CAN FIFO INTERRUPT REGISTER ‘n’ (‘n’ = 0-15)<br>**----- End of picture text -----**<br>
|Bit|Bit<br>Bit<br>Bit|Bit<br>Bit<br>Bit<br>Bit<br>Bit|
|---|---|---|
|Range||31/23/15/7|30/22/14/6|29/21/13/5|||28/20/12/4| 27/19/11/3 | 26/18/10/2<br>25/17/9/1<br>24/16/8/0|
|4|ence<br>HADrIE [TXEMPTVIE_|||
|8|eT|ove [exo<br>Rxnatrie | RxNEMPTviE_||
|i|a<br>aBG||
|8|TTT<br>ROVE RXFULLIE | RXHALIFCT | RXNEMPTVIFO |||
|Legend:|||
|R = Readable bit<br>W = Writable bit||U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR<br>‘1’=Bitisset||‘0’=Bitiscleared<br>x=Bitisunknown|
bit 31-27 Unimplemented: Read as ‘0’
- bit 26 TXNFULLIE: Transmit FIFO Not Full Interrupt Enable bit 1 = Interrupt enabled for FIFO not full 0 = Interrupt disabled for FIFO not full
- bit 25 TXHALFIE: Transmit FIFO Half Full Interrupt Enable bit 1 = Interrupt enabled for FIFO half full 0 = Interrupt disabled for FIFO half full
- bit 24 TXEMPTYIE: Transmit FIFO Empty Interrupt Enable bit 1 = Interrupt enabled for FIFO empty 0 = Interrupt disabled for FIFO empty
- bit 23-20 Unimplemented: Read as ‘0’ bit 19 RXOVFLIE: Overflow Interrupt Enable bit 1 = Interrupt enabled for overflow event 0 = Interrupt disabled for overflow event
- bit 18 RXFULLIE: Full Interrupt Enable bit 1 = Interrupt enabled for FIFO full 0 = Interrupt disabled for FIFO full
- bit 17 RXHALFIE: FIFO Half Full Interrupt Enable bit 1 = Interrupt enabled for FIFO half full 0 = Interrupt disabled for FIFO half full
- bit 16 RXNEMPTYIE: Empty Interrupt Enable bit 1 = Interrupt enabled for FIFO not empty 0 = Interrupt disabled for FIFO not empty
- bit 15-11 Unimplemented: Read as ‘0’ bit10 | TXNFULLIF: Transmit FIFO Not Full Interrupt Flag bit!) TXEN = 1: (FIFO configured as a Transmit Buffer) 1 = FIFO is not full 0 = FIFO is full TXEN = 0: (FIFO configured as a Receive Buffer) Unused, reads ‘0’
Note 1: This bit is read-only and reflects the status of the FIFO.
renner eee e rereerence eee eee DS70005425A-page 466 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
|REGISTER 30-17:<br>C1FIFOINTn: CAN FIFO INTERRUPT REGISTER ‘n’ (‘n’ = 0-15) (CONTINUED)|REGISTER 30-17:<br>C1FIFOINTn: CAN FIFO INTERRUPT REGISTER ‘n’ (‘n’ = 0-15) (CONTINUED)|REGISTER 30-17:<br>C1FIFOINTn: CAN FIFO INTERRUPT REGISTER ‘n’ (‘n’ = 0-15) (CONTINUED)|
|---|---|---|
|bit9|TXHALFIF: FIFO Transmit FIFO Half Empty Interrupt Flag bit!)||
||TXEN = 1: (FIFO configured as|a Transmit Buffer)|
||1 = FIFO is < half full||
||0 = FIFO is > half full||
||TXEN=<br>0: (FIFO configured as|a Receive Buffer)|
||Unused, reads ‘0’||
|bit 8|TXEMPTYIF: Transmit FIFO Empty Interrupt Flag bit!)||
||TXEN = 1: (FIFO configured as|a Transmit Buffer)|
||1 = FIFO is empty||
||0 = FIFO is not empty, at least|1 message queued to be transmitted|
||TXEN=<br>0: (FIFO configured as|a Receive Buffer)|
||Unused, reads ‘0’||
|bit 7-4|Unimplemented: Read as ‘0’||
|bit 3|RXOVEFLIF: Receive FIFO Overflow Interrupt Flag bit||
||TXEN=<br>1: (FIFO configured as|a Transmit Buffer)|
||Unused, reads ‘0’||
||TXEN=<br>0: (FIFO configured as|a Receive Buffer)|
||1 = Overflow event has occurred||
||0 = No overflow event occurred||
|bit 2|RXFULLIF: Receive FIFO Full|Interrupt Flag bit)|
||TXEN=<br>1: (FIFO configured as|a Transmit Buffer)|
||Unused, reads ‘0’||
||TXEN=<br>0: (FIFO configured as|a Receive Buffer)|
||1 = FIFO is full||
||0 = FIFO is not full||
|bit 1|RXHALFIF: Receive FIFO Half|Full Interrupt Flag bit")|
||TXEN=<br>1: (FIFO configured as|a Transmit Buffer)|
||Unused, reads ‘0’||
||TXEN=<br>0: (FIFO configured as|a Receive Buffer)|
||1 = FIFO is > half full||
||0 = FIFO is < half full||
|bit 0|RXNEMPTYIF: Receive Buffer|Not Empty Interrupt Flag bit‘)|
||TXEN=<br>1: (FIFO configured as|a Transmit Buffer)|
||Unused, reads ‘0’||
||TXEN=<br>0: (FIFO configured as|a Receive Buffer)|
||1 = FIFO is not empty, has at least<br>1 message||
||0=FIFOisempty||
Note 1: This bit is read-only and reflects the status of the FIFO.
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PIC32MZ W1 and WFI32E01 Family
## seman
REGISTER 30-18: C1FIFOUAn: CAN FIFO USER ADDRESS REGISTER ‘n’ (‘n’ = 0-15)
|Bit|Bit||Bit|Bit|Bit|Bit||Bit|Bit|Bit|
|---|---|---|---|---|---|---|---|---|---|---|
|Range | 31/23/15/7 | 30/22/14/6 |29/21/13/5 | 28/20/12/4 | 27/19/11/3|||||||| 26/18/10/2||| 25/17/9/1|24/16/8/0|
|31:24|||||||||||
|—<br>2|||||||||||
|:|||||||||||
|-<br>||||||||||||
|Legend:|||||||||||
|R = Readable bit||W|= Writable bit|U|= Unimplemented bit, read|||as ‘0’|||
|-n=ValueatPOR||‘1?|=Bitisset|‘0’|=Bitiscleared||x=Bitisunknown||||
- bit 31-2 C1FIFOUAn<29:0>: CAN FIFO User Address bits
- TXEN = 1: (FIFO configured as a transmit buffer)
- A read of this register will return the address where the next message is to be written (FIFO head). TXEN = 0: (FIFO configured as a receive buffer)
- A read of this register will return the address where the next message is to be read (FIFO tail).
- bit 1-0 Unimplemented: Read as ‘0’
- Note 1: This bit will always read ‘0’, which forces byte-alignment of messages. 2: This register is not guaranteed to read correctly in Configuration mode, and should only be accessed when the module is not in Configuration mode.
REGISTER 30-19: C1FIFOCIn: CAN MODULE MESSAGE INDEX REGISTER ‘n’ (‘n’ = 0-15)
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Bit Bit Bit Bit Bit Bit Bit Bit Bit<br>Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 24/16/8/0<br>en ee ee ee<br>pate | SS ee ee<br>p88 | See ee<br>- e a Ca a<br>Legend:<br>R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’<br>-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown<br>**----- End of picture text -----**<br>
bit 31-5 Unimplemented: Read as ‘0’ bit4-0 C1FIFOCIn<4:0>: CAN Side FIFO Message Index bits
- TXEN = 1: (FIFO configured as a transmit buffer) A read of this register will return an index to the message that the FIFO will next attempt to transmit. TXEN = 0: (FIFO configured as a receive buffer) A read of this register will return an index to the message that the FIFO will use to save the next message.
renner eee e rereerence eee eee DS70005425A-page 468 Preliminary Data Sheet © 2020 Microchip Technology Inc.
## PIC32MZ W1 and WFI32E01 Family smn 31.0 CONTROLLER AREA * Message reception: NETWORK-FLEXIBLE DATA- Maximum of 16 flexible filter and Mask RATE (CAN-FD) MODULE Oecd:
- Message reception: - Maximum of 16 flexible filter and Mask Oecd:
- - FIFO depth up to 32 - Message depth up to 32 bytes
- Note: This data sheet summarizes the - Message depth up to 32 bytes features of the PIC32MZ W1 family of - Each object can be configured to filter either: devices. It is not intended to be a * Standard ID + first 2 data bytes comprehensive reference source. To . Extended ID complement the information in this data sheet, refer to Section 56. Controller - All filter objects can be used as filter plus Area Network with Flexible Data-rate mask (CAN FD) (DS60001549) in the “P/C32 - 32-bit time stamp Family Reference Manual’, which is ¢ Special features: available from the Microchip web site - Selective wake-up, and transceiver standby (www.microchip.com/PIC32). control
- ¢ Special features: - Selective wake-up, and transceiver standby control
- - Minimum of 4 time quanta per bit time - Message objects and filters are located in SRAM; size: minimum 2 KB
- - Low-Power Operating mode - Bus health diagnostics and error counters - Disable mode - Loopback mode (internal and external) - Listen Only mode - Configuration mode - Restricted Operation mode
The PIC32MZ W1 device supports one CAN-FD module. The CAN-FD module supports the following key features:
- Compliance: - Full CAN 2.0B (ISO11898-1:2015) - CAN-FD 1.0 - Supports up to 64 data bytes - Arbitration Bit Rate up to 1 Mbps - FD Bit Rate up to 8 Mbps
- Message objects:
- Maximum of 15 FIFOs, configurable as transmit or receive FIFOs
- One Transmit Queue (TXQ)
- Transmit event FIFO with time stamp
- Message transmission:
- Programmable automatic retransmission attempts: unlimited, 3 attempts, or disabled
- Message transmission prioritization:
- ¢ Based on priority bit field ¢ Message with lowest ID gets transmitted first using a TXQ
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 469
PIC32MZ W1 and WFI32E01 Family
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FIGURE 31-1: CAN-FD BLOCK DIAGRAM<br>C2TX TX Handler Timestamping<br>xXVN<br>=) Interrupt Control<br>C2RX RX Handler<br>XxXnal E Handling Di ti<br>Eliten ana'haske rror Handling Diagnostics<br>Device RAM<br>TEF TXQ FIFO 1 FIFO 15<br>Message Message Message Message<br>Object 0 Object 0 Object 0 Object 0<br>Message Message Message Message<br>Object 31 Object 31 Object 31 Object 31<br>**----- End of picture text -----**<br>
Se DS70005425A-page 470 Preliminary Data Sheet © 2020 Microchip Technology Inc.
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PIC32MZ W1 and WFI32E01 Family
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PIC32MZ W1 and WFI32E01 Family
## smn
## REGISTER 31-1: CFD2CON: CAN CONTROL REGISTER
Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0 | | 88 ao ee | Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Settable bit C = Clearable bit x = Bit is unknown at Reset ‘1’ = Bit is set at Reset ‘0’ = Bit is cleared at Reset HC = Hardware clear HS = Set by Hardware only
- bit 31-28 TXBWS<3:0>: Transmit Bandwidth Sharing bits Delay between two consecutive transmissions (in arbitration bit times) 0000 = No delay 0001 =2 0010 =4 0011 =8 0100 =16 0101 =32 0110 =64 0111 = 128 1000 = 256 1001 =512 1010 = 1024 1011 = 2048 1111-1100 = 4096
- bit 27 ABAT: Abort All Pending Transmissions bit
- 1 = Signal all transmit buffers to abort transmission
- 0 = Module clears this bit when all transmissions are aborted
- bit 26-24 REQOP<2:0>: Request Operation Mode bits
- 000 = Set Normal CAN-FD mode; supports mixing of full CAN-FD and classic CAN 2.0 frames 001 = Set Disable mode
010 = Set Internal Loopback mode
- 011 = Set Listen Only mode
- 100 = Set Configuration mode
- 101 = Set External Loopback mode
- 110 = Set Normal CAN 2.0 mode; error frames on CAN-FD frames
- 111 = Set Restricted Operation mode
Note 1: These bits can only be modified in Configuration mode (OPMOD = 100).
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 481
## PIC32MZ W1 and WFI32E01 Family seman
## REGISTER 31-1: CFD2CON: CAN CONTROL REGISTER (CONTINUED) bit 23-21 OPMOD<2:0>: Operation Mode Status bits
**==> picture [412 x 565] intentionally omitted <==**
**----- Start of picture text -----**<br>
|||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|000|=|Module|is|in|Normal|CAN-FD|mode;|supports|mixing|of|full|CAN-FD|and|classic|CAN|2.0|
|frames|
|001|=|Module|is|in|Disable|mode|
|010|=|Module|is|in|Internal|Loopback|mode|
|011|=|Module|is|in|Listen|Only|mode|
|100|=|Module|is|in|Configuration|mode|
|101|=|Module|is|in|External|Loopback|mode|
|110|=|Module|is|Normal|CAN|2.0|mode;|error frames|on|CAN-FD|frames|
|111|=|Module|is|Restricted|Operation|mode|
|bit20|TXQEN:|Enable|Transmit|Queue|bit!)|
|1|=|Enables TXQ|and|reserves|space|in|RAM|
|0|=|Don’t|reserve|space|in|RAM|for TXQ|
|Note:|Changes|only|in|Configuration|mode,|since|it|changes|the|addresses|in|RAM.|
|bit19|STEF:|Store|in|Transmit|Event|FIFO|bit!)|
|1|=|Save|transmitted|messages|in|TEF|
|0|=|Don’t|save|transmitted|messages|in|TEF|
|Note:|Changes|only|in|Configuration|mode,|since|it|changes|the|addresses|in|RAM.|
|bit|18|SERR2LOM:|Transition|to|Listen|Only|Mode|on|System|Error|pit")|
|1|=|Transition|to|Listen|Only|Mode|
|0|=|Transition|to|Restricted|Operation|Mode|
|bit17|ESIGM:|Transmit|ESI|in|Gateway|Mode|bit(")|
|1|=|ESl|is|transmitted|as|recessive|when|ESI|of|message|is|high|or|CAN|controller|error|passive|
|0|=|ESI|reflects|error|status|of|CAN|controller|
|bit16|RTXAT:|Restrict|Retransmission|Attempts|bit!)|
|1|=|Restricted|retransmission|attempts,|use CIFIFOCONm.TXAT|
|0|=|Unlimited|number|of|retransmission|attempts,|CiIFIFOCONm.TXAT|is|ignored|
|bit|15|ON:|Enable|bit|
|1|=|CAN|module|is|enabled|
|0|=|CAN|module|is|disabled|
|bit|14|Unimplemented:|Read|as|‘0’|
|bit|13|SIDL:|Stop|in|Idle|Control|bit|
|1|=|Stop|module|operation|in|Idle|mode|
|0|=|Don’t|stop|module|operation|in|Idle|mode|
|bit|12|BRSDIS:|Bit|Rate|Switching|Disable|bit|
|1|=|Bit|Rate|Switching|is|Disabled,|regardless|of|BRS|in|the|Transmit|Message|Object|
|0|=|Bit|Rate|Switching|depends|on|BRS|in|the|Transmit|Message|Object’|
|bit|11|BUSY:|CAN|Module|is|Busy|bit|
|1|=|The|CAN|module|is|active|
|0|=|The|CAN|module|is|inactive|
|bit|10-9|WEFT<1:0>:|Selectable|Wake-up|Filter|Time|bits|
|00|=|TOOFILTER|
|01|=|TO1FILTER|
|10|=|T10FILTER|
|11|=T11FiLTER|
|bit|8|WAKFIL:|Enable|CAN|Bus|Line Wake-up|Filter|bit!)|
|1|=|Use|CAN|bus|line|filter|for wake-up|
|0|=|CAN|bus|line|filter|is|not|used|for wake-up|
**----- End of picture text -----**<br>
Note 1: These bits can only be modified in Configuration mode (OPMOD = 100).
renner eee e rereerence eee eee DS70005425A-page 482 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
## REGISTER 31-1: CFD2CON: CAN CONTROL REGISTER (CONTINUED)
- bit 7 CLKSELO: Module Clock Source Select bit")
- 1 = PB2_CLK is selected
- 0 = ETHPLL is selected
- bit 6 PXEDIS: Protocol Exception Event Detection Disabled bit) A recessive “res bit” following a recessive FDF bit is called a Protocol Exception. 1 = Protocol Exception is treated as a Form Error. 0 = If a Protocol Exception is detected, the CAN enters Bus Integrating state.
- bit 5 ISOCRCEN: Enable ISO CRC in CAN-FD Frames bit!) 1 = Include Stuff Bit Count in CRC Field and use Non-Zero CRC Initialization Vector 0 = Do not include Stuff Bit Count in CRC Field and use CRC Initialization Vector with all zeros
- bit 4-0 DNCNT<4:0>: Device Net Filter Bit Number bits 10011-11111 = Invalid Selection (compare up to 18-bits of data with EID) 10010 = Compare up to data byte 2 bit 6 with EID17
- 00001 = Compare up to data byte 0 bit 7 with EIDO 00000 = Do not compare data bytes
Note 1: These bits can only be modified in Configuration mode (OPMOD = 100).
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 483
PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 31-2: CFD2NBTCFG: NOMINAL BIT TIME CONFIGURATION REGISTER
|Bit<br>Bit|Bit|Bit|Bit<br>Bit|Bit<br>Bit<br>Bit|
|---|---|---|---|---|
|Range<br>31/23/15/7<br>ToeLR<br>:|30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 |24/16/8/0<br>| wo | RW] RMO | WO | RW<br>| RW | RWO|||||
|:|||||
|oe||||—sSC~C~tCY|
|°Ee<br>vc<br>—Csts™SSCSCS|||||
|Legend:|||||
|R = Readable bit|W = Writable bit||U = Unimplemented bit, read as ‘0’||
|S = Settable bit|C = Clearable bit||x = Bit is unknown at Reset||
|‘1’=BitissetatReset|‘0’=Bitiscleared|atReset|HC=Hardwareclear<br>HS=|SetbyHardwareonly|
## bit 31-24 BRP<7:0>: Baud Rate Prescaler bits
- 0000 0000 =Ta = 1/Fsys
- bit 23-16 TSEG1<7:0>: Time Segment 1 bits (Propagation Segment + Phase Segment 1) 1111 1111 =Length is 256 xT@
- 0000 0000 =Lengbth is 1x Ta
- bit 15 Unimplemented: Read as ‘0’
- bit 14-8 TSEG2<6:0>: Time Segment 2 bits (Phase Segment 2) 111 1111 =Length is 128 xX Tg
## 000 0000 =Lengthis1XT@
- bit 7 Unimplemented: Read as ‘0’
- bit 6-0 SJWJ[6:0]: Synchronization Jump Width bits 111 1111 =Length is 128 x Tg
- 000 0000 =Length is 1x T@
- Note: This register can only be modified in Configuration mode (OPMOD = 100).
Meeeaa DS70005425A-page 484 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
## REGISTER 31-3: CFD2DBTCFG: DATA BIT TIME CONFIGURATION REGISTER
|Bit<br>Bit|Bit|Bit<br>Bit<br>Bit<br>Bit<br>Bit|Bit|
|---|---|---|---|
|Range | 31/23/15/7 | 30/22/14/6 |29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1<br>24/16/8/0<br>Poo,LRM] RM] RW | RMO | RWO | RWO | RWO | RW |<br>:||||
|ee<br>a|a|aCS||
|i<br>a|a a =|||
|° (a||||
|Legend:||||
|R = Readable bit|W = Writable bit|U = Unimplemented bit, read as ‘0’||
|S = Settable bit|C = Clearable bit|x = Bit is unknown at Reset||
|‘1’=BitissetatReset|‘0’=Bitiscleared|atReset<br>HC=Hardwareclear<br>HS=SetbyHardwareonly||
bit 31-24 BRP<7:0>: Baud Rate Prescaler bits
- 1111 1111 = Ta a 256/Fsys
- 0000 0000 =Ta = 1/Fsys
- bit 23-21 Unimplemented: Read as ‘0’
- bit 20-16 TSEG1<4:0>: Time Segment 1 bits (Propagation Segment + Phase Segment 1) 1 1111 =Length is 32x Ta
## 0 0000 =Lengthis 1xTq
- bit 15-12 Unimplemented: Read as ‘0’
- bit 11-8 TSEG2<3:0>: Time Segment 2 bits (Phase Segment 2) 1111 =Length is 16x Tq
## 0000 =Lengthis 1X T@
- bit 7-4 Unimplemented: Read as ‘0’
- bit 3-0 SJWJ[6:0]: Synchronization Jump Width bits 1111 =Length is 16x Ta
## 0000 =Lengthis 1x Tq
Note: This register can only be modified in Configuration mode (OPMOD = 100).
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 485
## PIC32MZ W1 and WFI32E01 Family
## seman
REGISTER 31-4: CFD2TDC: TRANSMITTER DELAY COMPENSATION REGISTER
**==> picture [454 x 199] intentionally omitted <==**
**----- Start of picture text -----**<br>
|||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Bit|Bit|Bit|Bit|Bit|Bit|Bit|Bit|Bit|
|Range|||31/23/15/7|| 30/22/14/6|||29/21/13/5|||28/20/12/4|||27/19/11/3|||26/18/10/2|||25/17/9/1|24/16/8/0|
|“ere|
|sorter|||
|ee|a|a|a|=|
|°C|
|ose|—“—sSOSSCSCSCSCST|
|i|a|a|
|Legend:|
|R|=|Readable|bit|W|=|Writable|bit|U|=|Unimplemented|bit,|read|as|‘0’|
|S|=|Settable|bit|C|=|Clearable|bit|x|=|Bit|is|unknown|at|Reset|
|‘1’|=|Bit|is|set|at|Reset|‘0’|=|Bit|is|cleared|at|Reset|| HC|=|Hardware|clear|HS|=|Set|by|Hardware|only|
**----- End of picture text -----**<br>
bit 31-26 Unimplemented: Read as ‘0’
**==> picture [400 x 300] intentionally omitted <==**
**----- Start of picture text -----**<br>
|||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|bit|25|EDGFLTEN:|Enable|Edge|Filtering|during|Bus|Integration|state|bit|
|1|=|Edge|Filtering|enabled,|according|to|1SO011898-1:2015|
|0|=|Edge|Filtering|disabled|
|bit|24|SID11EN:|Enable|12-Bit|SID|in|CAN-FD|Base|Format|Messages|bit|
|1|=|RRS|is|used|as|SID11|in|CAN-FD|base|format|messages:|SID[11:0]|=|{SID[10:0],|SID11}|
|0|=|Don’t|use|RRS;|SID[10:0]|according|to|1S011898-1:2015|
|bit|23-18|Unimplemented:|Read|as|‘0’|
|bit|17-16|TDCMOD<1:0>:|Transmitter|Delay|Compensation|Mode|bits;|Secondary|Sample|Point|(SSP)|
|10-11|Auto;|measure|delay|and|add|CFD2DBTCFG.TSEG1;|add|TDCO.|
|01|=|Manual;|Don’t|measure,|use|TDCV|+|TDCO|from|register|
|00|=|Disable|
|bit|15|Unimplemented:|Read|as|‘0’|
|bit|14-8|TDCO<6:0>:|Transmitter|Delay|Compensation|Offset|bits;|Secondary|Sample|Point|(SSP)|
|Two’s|complement;|offset|can|be|positive,|zero,|or|negative.|
|011|1111=63x|Tsys_CLK|
|000|0000|=0|Xx Tsys|CLK|
|111|1111|=-64x|Tsys_cLK|
|bit|7-6|Unimplemented:|Read|as|‘0’|
|bit|5-0|TDCV<5:0>:|Transmitter|Delay|Compensation|Value|bits;|Secondary|Sample|Point|(SSP)|
|11|1111=63x|Tsys|CLK|
|00|0000|=0x|Tsys_CLK|
**----- End of picture text -----**<br>
Note: This register can only be modified in Configuration mode (OPMOD = 100).
renner eee e rereerence eee eee DS70005425A-page 486 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
## REGISTER 31-5: CFD2TBC: CAN TIME BASE COUNTER REGISTER
|Bit|Bit|Bit|Bit|Bit<br>Bit|Bit|Bit|Bit|
|---|---|---|---|---|---|---|---|
|Range | 31/23/15/7 |30/22/14/6 |29/21/13/5 |28/20/12/4 | 27/19/11/3 | 26/18/10/2 <br>Foo,LRM] RM ] RWO | RMO ] RWO | RWO <br>:||||||| 25/17/9/1<br>24/16/8/0<br> | RWO | RW |||
|:||||||||
|:||||||||
|:||||||||
|Legend:||||||||
|R = Readable bit||W = Writable bit||U = Unimplemented bit, read as ‘0’||||
|S = Settable bit||C = Clearable bit||x = Bit is unknown at Reset||||
|‘1’=Bitissetat|Reset|‘0’=BitisclearedatReset||HC=Hardwareclear<br>HS=|Setby|Hardwareonly||
- bit 31-0 TBC: CAN Base Counter bits This is a free running timer that increments every TBCPRE clock when TBCENis set.
- Note 1: The TBC will be stopped and reset when TBCEN = 0 to save power. 2: The TBC prescaler count will be reset on any write to CFD2TBC (TBCPRE will be unaffected).
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 487
PIC32MZ W1 and WFI32E01 Family seman
## REGISTER 31-6: CFD2TSCON: CAN TIME STAMP CONTROL REGISTER
|Bit<br>Bit<br>Bit<br>Bit<br>Range | 31/23/15/7 | 30/22/14/6 |29/21/13/5 ||Bit<br>Bit<br>Bit<br>Bit<br>Range | 31/23/15/7 | 30/22/14/6 |29/21/13/5 ||Bit<br> 28/20/12/4|Bit<br> 28/20/12/4|27/19/11/<br>3|27/19/11/<br>3|Bit<br>26/18/10/2|Bit<br> | 25/17/9/1|Bit<br>24/16/8/0|
|---|---|---|---|---|---|---|---|---|
|an|a||||||||
|6eT|eT<br>ses | tseor [teen_|||||||||
|ee|a<br>aoe||||||||
|:|||||||||
|Legend:|||||||||
|R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit,|||||read|as ‘0’|||
|S = Settable bit<br>C = Clearable bit||X = Bit is unknown at Reset|||||||
|‘1’ = Bit is set at Reset<br>‘0’ = Bit is cleared at Reset<br>HC =|||Hardware|clear||HS = Set by|Hardware only||
|bit 31-19|Unimplemented: Read as ‘0’||||||||
|bit 18|TSRES: Time Stamp res bit (FD Frames only)||||||||
||1 = at sample point of the bit following the|FDF|bit.||||||
||0 = at sample point of SOF||||||||
|bit 17|TSEOF: Time Stamp EOF bit||||||||
||1 = Time Stamp when frame is taken valid|(11898-1 10.7):|||||||
||* RX no error until last but one bit of EOF)||||||||
||* TX no error until the end of EOF||||||||
||0 = Time Stamp at “beginning” of Frame:||||||||
||¢<br>Classical Frame: at sample point ofSOF||||||||
||¢<br>FD Frame: see TSRES bit.||||||||
|bit 16|TBCEN: Time Base Counter Enable bit||||||||
||1 = Enable TBC||||||||
||0 = Stop and resetTBC||||||||
|bit 15-10|Unimplemented: Read as ‘0’||||||||
|bit 9-0|TBCPRE<9:0>: CAN Time Base Counter Prescaler bits||||||||
||1023=TBCincrementsevery1024clocks||||||||
0 = TBC increments every 1 clock
renner eee e rereerence eee eee DS70005425A-page 488 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
## REGISTER 31-7: CFD2VEC: INTERRUPT CODE REGISTER
Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0 a SS t™—™—CCCSOXCOESSSC“*‘“*~*~* =f, aaa aoS Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Settable bit C = Clearable bit x = Bit is unknown at Reset ‘1’ = Bit is set at Reset ‘0’ = Bit is cleared at Reset HC = Hardware clear HS = Set by Hardware only
- bit 31 Unimplemented: Read as ‘0’
- bit 30-24 RXCODE<6:0>: Receive Interrupt Flag Code bits!)
- 1000001-1111111 = Reserved
1000000 = No interrupt 0100000-0111111 = Reserved 0011111 = FIFO 31 interrupt (RFIF[31] set)
0000010 = FIFO 2 interrupt (RFIF[2] set)
0000001 = FIFO 1 interrupt (RFIF[1] set)
0000000 = Reserved. FIFO 0 cannot receive.
- bit 23 Unimplemented: Read as ‘0’
bit 22-16 TXCODE<6:0>: Transmit Interrupt Flag Code bits!) 1000001-1111111 = Reserved 1000000 = No interrupt 0100000-0111111 = Reserved 0011111 = FIFO 31 interrupt (TFIF[31] set)
0000001 = FIFO 1 interrupt (TFIF[1] set) 0000000 = FIFO O interrupt (TFIF[O] set)
- bit 15-13 Unimplemented: Read as ‘0’
bit 12-8 FILHIT<4:0>: Filter Hit Number bits") 11111 = Filter 31 11110 = Filter 30
00001 = Filter 1
00000 = Filter0
bit 7 Unimplemented: Read as ‘0’ Note 1: CFD2VEC: If multiple interrupts are pending, the interrupt with the highest number will be indicated.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 489
## PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 31-7: CFD2VEC: INTERRUPT CODE REGISTER (CONTINUED) bit6-0 ICODE<6:0>: Interrupt Flag Code bits!)
- 1001011-1111111 = Reserved
- 1001010 = Transmit attempt interrupt (any bit in CiTXATIF set) 1001001 = Transmit event FIFO interrupt (any bit in CiTEFIF set) 1001000 = Invalid message occurred (IVMIF/IE)
- 1000111 = CAN Module Mode Change Occurred (MODIF/IE) 1000110 = CAN Timer Overflow (CTMRIF/IE)
- 1000101 = RX/TX MAB Overflow/Underflow (RX: message received before previous message is saved to memory; TX: cannot feed TX MAB fast enough to transmit consistent data.) (SERRIF/IE) 1000100 = Address error interrupt (illegal FIFO address presented to system) (SERRIF/IE) 1000011 = Receive FIFO overflow interrupt (any bit in CIRXOVIF set) 1000010 = Wake-up interrupt (WAKIF/WAKIE) 1000001 = Error interrupt (CERRIF/IE) 1000000 = No interrupt 0100000-0111111 = Reserved 0011111 = FIFO 31 interrupt (TFIF[31] or RFIF[31] set)
0000001 = FIFO 1 interrupt (TFIF[1] or RFIF[1] set) 0000000 = FIFOO interrupt (TFIF[O] set)
Note 1: CFD2VEC: If multiple interrupts are pending, the interrupt with the highest number will be indicated.
renner eee e rereerence eee eee DS70005425A-page 490 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## ——
## REGISTER 31-8: CFD2INT: INTERRUPT REGISTER
Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 24/16/8/0 Sere mone [rece [exe [xe er oie race [exe [xr _| Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Settable bit C = Clearable bit X = Bit is unknown at Reset
- bit 31 IVMIE: Invalid Message Interrupt Enable bit
- bit 30 WAKIE: Bus Wake Up Activity Interrupt Enable bit
- bit 29 CERRIE: CAN Bus Error Interrupt Enable bit bit 28 SERRIE: System Error Interrupt Enable bit
- bit 27 RXOVIE: Receive Buffer Overflow Interrupt Enable bit
- bit 26 TXATIE: Transmit Attempt Interrupt Enable bit
- bit 25 SPICRCIE: SPI CRC Error Interrupt Enable bit
- bit 24 ECCIE: ECC Error Interrupt Enable bit
- bit 23-21 Unimplemented: Read as ‘o’
- bit 20 TEFIE: Transmit Event FIFO Interrupt Enable bit
- bit 19 MODIE: Mode Change Interrupt Enable bit bit 18 TBCIE: CAN Timer Interrupt Enable bit
- bit 17 RXIE: Receive Object Interrupt Enable bit
- bit 16 TXIE: Transmit Object Interrupt Enable bit bit15 — IVMIF: Invalid Message Interrupt Flag bit!) bit14 | WAKIF: Bus Wake Up Activity Interrupt Flag bit!) bit13 | CERRIF: CAN Bus Error Interrupt Flag bit(") bit 12 SERRIF: System Error Interrupt Flag bit!) 1 =Asystem error occurred (collision on dual-port RAM) 0 = No system error occurred
- bit 11 RXOVIF: Receive Object Overflow Interrupt Flag bit 1 = Receive object overflow occurred
- 0 = No receive object overflow has occurred
- bit 10 TXATIF: Transmit Attempt Interrupt Flag bit bit 9 SPICRCIF: SPI CRC Error Interrupt Flag bit bit 8 ECCIF: ECC Error Interrupt Flag bit
- bit 7-5 Unimplemented: Read as ‘0’
Note 1: CFDZ2INT: Flags are set by hardware and cleared by application.
SS © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 491
## PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 31-8: CFD2INT: INTERRUPT REGISTER (CONTINUED)
|bit|4|TEFIF: Transmit Event FIFO Interrupt Flag bit|
|---|---|---|
|||1 = Receive buffer overflow occurred|
|||0 = No receive buffer overflow has occurred|
|bit|3|MODIF: CAN Mode Change Interrupt Flag bit")|
|||1 = CAN Module mode change occurred (OPMOD has changed to reflect REQOP)|
|||0 = No mode change occurred|
|bit2|2|TBCIF: CAN Timer Overflow Interrupt Flag bit")|
|||1 = TBC has overflowed|
|||0 = TBC does not overflow|
|bit|1|RXIF: Receive Object Interrupt Flag bit|
|||1 = Receive object interrupt is pending|
|||0 = No receive object interrupt is pending|
|bit|0|TXIF: Transmit Object Interrupt Flag bit|
|||1 = Transmit object interrupt is pending|
|||0=Notransmitobjectinterruptispending|
Note 1: CFD2INT: Flags are set by hardware and cleared by application.
renner eee e rereerence eee eee DS70005425A-page 492 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
## REGISTER 31-9: CFD2RXIF: RECEIVE INTERRUPT STATUS REGISTER
|Bit<br>Bit<br>Bit|Bit|Bit<br>Bit|Bit|Bit<br>Bit|
|---|---|---|---|---|
|Range | 31/23/15/7 |30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3||||26/18/10/2 | 25/17/9/1<br>24/16/8/0||
|_— , Re | he ||Re|| ee | ee||<br>oe|| Re | Bo|
|a<br>RO | Re ||eo|| me | me|| ee|| ee|e|
|isn<br>| ROT Ro ||Ro OT Ro OT Ro||| Ro|| Ro TRO|
|yo<br>FE Ro | Ro | ro<br>| ro<br>[| ro<br>{| ro<br>[| Ro [| vo |<br>ia|||||
|Legend:|||||
|R = Readable bit<br>W = Writable bit||U = Unimplemented bit, read as ‘0’|||
|S = Settable bit<br>C = Clearable bit||x = Bit is unknown at Reset|||
|‘1’=BitissetatReset<br>‘0’=Bitiscleared|atReset|HC=Hardwareclear|HS=SetbyHardwareonly||
Legend:
## bit 31-1 RFIF<31:1>: Receive FIFO Interrupt Pending bits(
1 = One or more enabled receive FIFO interrupts are pending
0 = No enabled receive FIFO interrupts are pending bit O Unimplemented: Read as ‘0’
Note 1: CFD2RXIF: FIFO: RFIF = ‘or of enabled RXFIFO flags; (flags need to be cleared in FIFO register)
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 493
PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 31-10: CFD2RXOVIF: RECEIVE OVERFLOW INTERRUPT STATUS REGISTER
|Bit|Bit|Bit|Bit|Bit<br>Bit<br>Bit<br>Bit<br>Bit|
|---|---|---|---|---|
|Range|| 31/23/15/7|| 30/22/14/6 |29/21/13/5||| 28/20/12/4 | 27/19/11/3 |26/18/10/2 | 25/17/9/1<br>24/16/8/0|
|ging<br>:|(| ROT RO TRO|||TROT ROT ROT RO TROT|
|saig|(| RO|[| Ro<br>[||ro|| ro | Ro | Ro | Ro | Ro ||
|isp<br>:|LF RO|| Ro ||Ro|| Ro | RO OT RO | RO | RO|
|no|FRO] Ro | Ro | Ro OT Ro OT Ro |RO<br>OOOO?<br>SSC~—“‘“S*S*~*~*S*S*S*~é—é‘iSC“‘ SY||||
|Legend:|||||
|R = Readable bit||W = Writable bit||U = Unimplemented bit, read as ‘0’|
|S = Settable bit||C = Clearable bit||x = Bit is unknown at Reset|
|‘1’=Bitis|setatReset|‘0’=Bitiscleared|atReset|HC=Hardwareclear<br>HS=SetbyHardwareonly|
bit 31-1 |RFOVIF<31:1>: Receive FIFO Overflow Interrupt Pending bits(") 1 = Interrupt is pending 0 = Interrupt is not pending bit 0 Unimplemented: Read as ‘0’
Note 1: CFD2RXOVIF: FIFO: RFOVIF (flag needs to be cleared in FIFO register)
renner eee e rereerence eee eee DS70005425A-page 494 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
## REGISTER 31-11: CFD2TXIF: TRANSMIT INTERRUPT STATUS REGISTER
|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit|
|---|
|Range | 31/23/15/7 |30/22/14/6 |29/21/13/5 | 28/20/12/4 | 27/19/11/3 |26/18/10/2 | 25/17/9/1 | 24/16/8/0|
|gio<br>FL RO<br>RO TRO TRO CT ROT ROT RO TRO<br>[siaEI<br>sate<br>RO | Ro | Ro | RO OT ROT Ro<br>Ro TRO<br>ee<br>isp<br>LF RO<br>ROT RO | Ro | ROT Ro TRO TR<br>peSE<br>79<br>| Ro<br>[| ro [ ro [ ro [ Ro<br>[| Ro [ Ro [| Ro |<br>Ep<br>Oe|
|Legend:|
|R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’|
|S = Settable bit<br>C = Clearable bit<br>x = Bit is unknown at Reset|
|‘1’=BitissetatReset<br>‘0’=BitisclearedatReset<br>HC=Hardwareclear<br>HS=SetbyHardwareonly|
- bit 31-0 TFIF<31:0>: Transmit FIFO/TXQ() Interrupt Pending bits") 1 = One or more enabled transmit FIFO/TXQ interrupts are pending
- 0 = No enabled transmit FIFO/TXQ interrupts are pending
- Note 1: CFD2TXIF: FIFO: TFIF = ‘or’ of the enabled TXFIFO flags; (flags need to be cleared in FIFO register) 2: TFIF[O] is for the Transmit Queue.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 495
## PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 31-12: CFD2TXATIF: TRANSMIT ATTEMPT INTERRUPT STATUS REGISTER
|Bit|Bit|Bit||Bit|Bit<br>Bit||Bit|Bit||Bit|
|---|---|---|---|---|---|---|---|---|---|---|
|Range|31/23/15/7|30/22/14/6|29/21/13/5||28/20/12/4<br>27/19/11/3|26/18/10/2||25/17/9/1||24/16/8/0|
|31-24|poof RO]|||ROU] RO | Ro||||Ro CT RO||OT|RO|
|ee|ee||||||||||
|sg|| RO | Ro||||Ro|TRO TROT||RO|RO||RO|
|nm <br>||(Ro | ro||[||ro|[| ro | Ro|[|Ro | Ro||[||Ro ||
|Legend:|||||||||||
|R = Readable bit||W = Writable|bit||U = Unimplemented bit, read|as ‘0’|||||
|S = Settable bit||C = Clearable bit|||x = Bit is unknown at Reset||||||
|‘1’=Bitis|setatReset|‘0’=Bitiscleared||atReset|HC=Hardwareclear|HS|=SetbyHardwareonly||||
- bit 31-0 TFATIF<31:0>: Transmit FIFO/TXQ() Attempt Interrupt Pending bits!) 1 = Interrupt is pending 0 = Interrupt is not pending
- Note 1: CFD2TXATIF: FIFO: TFATIF (flag needs to be cleared in FIFO register) 2: TFATIF[O] is for the Transmit Queue.
renner eee e rereerence eee eee DS70005425A-page 496 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
## REGISTER 31-13: CFD2TXREQ: TRANSMIT REQUEST REGISTER
|Bit|Bit|Bit|Bit|Bit<br>Bit|Bit|Bit|Bit|
|---|---|---|---|---|---|---|---|
|Range|31/23/15/7|30/22/14/6|29/21/13/5|28/20/12/4<br>27/19/11/3|26/18/10/2|25/17/9/1|24/16/8/0|
||S'/HC-0|SM/HC-0|SM™/HC-0|S™/HC-0<br>S™/HC-0|S™/HC-0|SM/HC-0|SM/HC-0|
|S4-84<br>,||||||||
|||||TXREQ<31:24>||||
|—<br>:|s(™Hc-0|| sMHc-0 ||sMHc-0|| syHc-0 | sMHc-0 ||sMHc-0 | sMHc-0 | sHC-0|||
|||||TXREQ<23:16>||||
|158<br>,|S(/HC-0|sMHe-0 ||sMHc-0|| sM@Hc-0 | sMxHc-0 ||sMHc-0 | sMHc-0 | sHC-0|||
|||||TXREQ<15:8>||||
|~<br>:|s(Hc-0|| sM@Hc-0 ||sMHc-0|| sHc-0 | sMHc-0 ||sMHc-0 | sMHc-0 | s/HC-0|||
|||||TXREQ<7:0>||||
|Legend:||||||||
|R = Readable bit||W = Writable bit||U = Unimplemented bit, read as ‘0’||||
|S = Settable bit||C = Clearable bit||x = Bit is unknown at Reset||||
|‘1’=BitissetatReset||‘0’=BitisclearedatReset||HC=Hardwareclear<br>HS=SetbyHardwareonly||||
- bit31-1 TXREQ<31:1>: Message Send Request bits TXEN = 1 (Object configured as a Transmit Object) Setting this bit to ‘1’ requests sending a message. The bit is automatically cleared when the message(s) queued in the object is (are) successfully sent. This bit can not be used for aborting a transmission. TXEN = 0 (Object configured as a Receive Object) This bit has no effect.
- bit 0 TXREQ<0>: Transmit Queue Message Send Request bit Setting this bit to ‘1’ requests sending a message. The bit is automatically cleared when the message(s) queued in the object is (are) successfully sent. This bit can not be used for aborting a transmission.
- Note 1: The TXREQ|[x] bit represents the corresponding FIFO[x] message.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 497
## PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 31-14: CFD2FIFOBA: MESSAGE MEMORY BASE ADDRESS REGISTER
|BitRange<br>Bit<br>9<br>31/23/15/7|BitRange<br>Bit<br>9<br>31/23/15/7|BitRange<br>Bit<br>9<br>31/23/15/7|Bit<br>30/22/14/6|Bit<br>29/21/13/5|Bit<br>29/21/13/5|Bit<br>Bit<br>28/20/12/4<br>27/19/11/3|Bit<br>26/18/10/2|Bit<br>26/18/10/2|Bit<br>25/17/9/1|Bit<br>24/16/8/0|
|---|---|---|---|---|---|---|---|---|---|---|
|||||||RIW-0|||||
|v4<br>,|||||||||||
|||||||FIFOBA<31:24>|||||
|||R/W-0|RIW-0||R/W-0|R/W-0<br>R/W-0|RIW-0||||
|is<br>:|||||||||||
|||||||FIFOBA<23:16>|||||
|,|||||||||||
|||||||FIFOBA<15:8>|||||
|||R/W-0|RIW-0||R/W-0|R/W-0|||u-0l)|u-o()|
|70<br>:|||||||||||
|||||||FIFOBA<7:0>|||||
|Legend:|||||||||||
|R = Readable bit|||W = Writable bit|||U = Unimplemented bit, read|as ‘0’||||
|S = Settable bit|||C = Clearable bit|||x = Bit is unknown at Reset|||||
|‘1’=Bit|issetat|Reset|‘0’=Bitiscleared||atReset|HC=Hardwareclear|HS=|Setby|Hardwareonly||
bit31-0 FIFOBA<31:0>: Message Memory Base Address bits Defines the base address for Transmit Event FIFO followed by the message objects.
- Note 1: CFD2FIFOBA: Bits[1:0] are forced to ‘0’ to be word aligned.
- 2: CFD2FIFOBA: This register can only be modified in Configuration mode (OPMOD = 100).
renner eee e rereerence eee eee DS70005425A-page 498 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
**==> picture [351 x 8] intentionally omitted <==**
**----- Start of picture text -----**<br>
REGISTER 31-15: CFD2TXQCON: TRANSMIT QUEUE CONTROL REGISTER<br>**----- End of picture text -----**<br>
**==> picture [453 x 199] intentionally omitted <==**
**----- Start of picture text -----**<br>
|||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Bit|Bit|Bit|Bit|Bit|Bit|Bit|Bit|Bit|
|Range|||31/23/15/7|||30/22/14/6|||29/21/13/5|| 28/20/12/4|||27/19/11/3|||26/18/10/2|||25/17/9/1|24/16/8/0|
|:|
|ee|A|2|
|15:8|-|.|
|eT|
|reser]|rxrea®|[unc|||
|°|en|ee|ce|xan|
|Legend:|
|R|=|Readable|bit|W|=|Writable|bit|U|=|Unimplemented|bit,|read|as|‘0’|
|S|=|Settable|bit|C|=|Clearable|bit|x|=|Bit|is|unknown|at|Reset|
|‘1’|=|Bit|is|set|at|Reset|‘0’|=|Bit|is|cleared|at|Reset|| HC|=|Hardware|clear|HS|=|Set|by|Hardware|only|
**----- End of picture text -----**<br>
## bit 31-29 PLSIZE<2:0>: Payload Size bits!)
000 = 8 data bytes
- 001 = 12 data bytes
- 010 = 16 data bytes 011 = 20 data bytes
- 100 = 24 data bytes 101 = 32 data bytes 110 = 48 data bytes 111 = 64 data bytes
- bit 28-14 FSIZE<4:0>: FIFO Size bits!) 0_ 0000 = FIFO is 1 Message deep
- 00001 = FIFO is 2 Messages deep 00002 = FIFO is 3 Messages deep
- 11111 = FIFO is 32 Messages deep
- bit 23 Unimplemented: Read as ‘0’
- bit 22-21 TXAT<1:0>: Retransmission Attempts bits This feature is enabled when CFD2CON.RTXAT is set.
- 00 = Disable retransmission attempts
- 01 = Three retransmission attempts
- 10 = Unlimited number of retransmission attempts
- 11 = Unlimited number of retransmission attempts
- Note: Application must be able to change these bits in Normal mode. This can be used to go back on the bus after bus off to check if transmission works again.
- bit 20-16 TXPRI<4:0>: Message Transmit Priority bits 00000 = Lowest Message Priority
## il1111 = Highest Message Priority
- Note 1: These bits can only be modified in Configuration mode (OPMOD = 100).
- 2: This bit is updated when a message completes (or aborts) or when the FIFO is reset.
- 3: FRESET is set while in Configuration mode and is automatically cleared in Normal mode.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 499
## PIC32MZ W1 and WFI32E01 Family seman
|REGISTER 31-15:<br>CFD2TXQCON: TRANSMIT QUEUE CONTROL REGISTER (CONTINUED)|REGISTER 31-15:<br>CFD2TXQCON: TRANSMIT QUEUE CONTROL REGISTER (CONTINUED)|REGISTER 31-15:<br>CFD2TXQCON: TRANSMIT QUEUE CONTROL REGISTER (CONTINUED)|
|---|---|---|
|bit 15-11||Unimplemented: Read as ‘0’|
|bit10|||FRESET: FIFO Reset bit'*)|
|||1 = FIFO is resetwhen the bit is set and cleared by hardware when FIFO is reset. User should poll|
|||whether this bit is clear, before taking any action.|
|||0 = No effect|
|bit 9||TXREQ: Message Send Request bit(2)|
|||1 = Requests sending a message; the bit is automatically cleared when all the messages queued|
|||in theTXQ are successfully sent|
|||0 = Clearing the bit to ‘0’ while set (‘1’) requests a message abort.|
|bit 8||UINC: Increment Head/Tail bit|
|||When this bit is set, the FIFO head increments by a single message.|
|bit 7||TXEN: TX Enable|
|||1 = Transmit Message Queue. This bit always reads 1.|
|bit 6-5||Unimplemented: Read as ‘0’|
|bit 4||TXATIE: TransmitAttempts Exhausted Interrupt Enable bit|
|||1 = Enable interrupt|
|||0 = Disable interrupt|
|bit 3||Unimplemented: Read as ‘0’|
|bit 2||TXQEIE: Transmit Queue Empty Interrupt Enable bit|
|||1 = Interrupt enabled forTXQ empty|
|||0 = Interrupt disabled forTXQ empty|
|bit 1||Unimplemented: Read as ‘0’|
|bit 0||TXQNIE: Transmit Queue Not Full Interrupt Enable bit|
|||1 = Interrupt enabled forTXQ not full|
|||0 = Interrupt disabled forTXQ not full|
|Note|1:|These bits can only be modified in Configuration mode (OPMOD = 100).|
||2:|This bit is updated when a message completes (or aborts) orwhen the FIFO is reset.|
||3:|FRESETissetwhileinConfigurationmodeandisautomaticallyclearedinNormalmode.|
renner eee e rereerence eee eee DS70005425A-page 500 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
## REGISTER 31-16: CFD2TXQSTA: TRANSMIT QUEUE STATUS REGISTER
**==> picture [449 x 130] intentionally omitted <==**
**----- Start of picture text -----**<br>
||||||||||
|---|---|---|---|---|---|---|---|---|
|Bit|Bit|Bit|Bit|Bit|Bit|Bit|Bit|Bit|
|Range ||31/23/15/7|| 30/22/14/6|| 29/21/13/5 |28/20/12/4||27/19/11/3|||26/18/10/2|25/17/9/1|24/16/8/0|
|15:8|7|
|oS|
|a|a|a a|
|°|[reasr®|Trxtars@ 3] Terk]|xa|||«d~SXOEF|«SCN _|
**----- End of picture text -----**<br>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Settable bit C = Clearable bit x = Bit is unknown at Reset ‘{’=Bitis set at Reset ‘0’ = Bit is cleared at Reset HC = Hardware clear HS = Set by Hardware only
- bit 31-13 Unimplemented: Read as ‘0’ bit 12-8 TXQCI<4:0>: Transmit Queue Message Index bits(") A read of this register returns an index to the message that the FIFO attempts to transmit next.
- bit 7 TXABT: Message Aborted Status bit'*2) 1 = Message is aborted 0 = Message completed successfully
- bit 6 TXLARB: Message Lost Arbitration Status bit'*-2)
- 1 = Message lost arbitration while being sent
- 0 = Message does not loose arbitration while being sent
- bit 5 TXERR: Error Detected During Transmission bit’:2)
- 1 =Abus error occurs while the message is being sent
- 0 =A bus error does not occur while the message is being sent
- bit 4 TXATIF: Transmit Attempts Exhausted Interrupt Pending bit 1 = Interrupt is pending
- 0 = Interrupt is not pending
- bit 3 Unimplemented: Read as ‘0’
- bit 2 TXQEIF: Transmit Queue Empty Interrupt Flag bit 1 = TXQ is empty
- 0 = TXQ is not empty, at least 1 message queued to be transmitted
- bit 1 Unimplemented: Read as ‘0’ bit 0 TXQNIF: Transmit Queue Not Full Interrupt Flag bit 1 = TXQ is not full 0 = TXQis full
- Note 1: TXQCI<4:0> gives a zero-indexed value to the message in the TXQ. If the TXQ is 4 messages deep (FSIZE=5’h03) TXQCI will take on a value of 0 to 3 depending on the state of the TXQ.
- 2: This bit is reset on any read of this register or when the TXQ is reset.
- 3: This bit is updated when a message completes (or aborts) or when the TXQ is reset.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 501
## PIC32MZ W1 and WFI32E01 Family
## seman
REGISTER 31-17: CFD2FIFOCONm: FIFO CONTROL REGISTER m, (m = 1 to 15) Bit Bit Bit Bit Bit Bit Bit Bit Bit ear C—~—“—~s~CSCSCSPRDN 15:8 a cc ee ee | Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Settable bit C = Clearable bit x = Bit is unknown at Reset ‘1’ = Bit is set at Reset ‘0’ = Bit is cleared at Reset HC = Hardware clear HS = Set by Hardware only
bit 31-29 PLSIZE<2:0>: Payload Size bits!)
- 000 = 8 data bytes
- 001 = 12 data bytes
- 010 = 16 data bytes 011 = 20 data bytes
- 100 = 24 data bytes
- 101 = 32 data bytes
- 110 = 48 data bytes 111 = 64 data bytes
bit 28-24 FSIZE<4:0>: FIFO Size bits!) 0 0000 = FIFO is 1 Message deep 0 0001 = FIFO is 2 Messages deep 0 0002 = FIFO is 3 Messages deep
11111 = FIFO is 32 Messages deep
bit 23 Unimplemented: Read as ‘0’
- bit 22-21 TXAT<1:0>: Retransmission Attempts bits This feature is enabled when CFD2.RTXAT is set.
- 00 = Disable retransmission attempts
- 01 = Three retransmission attempts
- 10 = Unlimited number of retransmission attempts
- 11 = Unlimited number of retransmission attempts
- Note: Application must be able to change these bits in Normal mode. This can be used to go back on the bus after bus off to check if transmission works again.
- bit 20-16 TXPRI<4:0>: Message Transmit Priority bits 00000 = Lowest Message Priority
11111 = Highest Message Priority
bit 15-11 Unimplemented: Read as ‘0’
- Note 1: These bits can only be modified in Configuration mode (OPMOD = 100).
- 2: This bit is updated when a message completes (or aborts) or when the FIFO is reset.
- 3: FRESET is set while in Configuration mode and is automatically cleared in Normal mode.
renner eee e rereerence eee eee DS70005425A-page 502 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
|REGISTER 31-17:<br>CFD2FIFOCONm: FIFO CONTROL REGISTER m, (m = 1 to 15) (CONTINUED)|REGISTER 31-17:<br>CFD2FIFOCONm: FIFO CONTROL REGISTER m, (m = 1 to 15) (CONTINUED)|REGISTER 31-17:<br>CFD2FIFOCONm: FIFO CONTROL REGISTER m, (m = 1 to 15) (CONTINUED)|
|---|---|---|
|bit10 | FRESET: FIFO Reset bit'*)|||
||1 = FIFO is resetwhen the bit is set and cleared by hardware when FIFO is reset. User should poll whether||
||this bit is clear, before taking any action.||
||0 = No effect||
|bit 9|TXREQ: Message Send Request bit")||
||TXEN= 1 (FIFO configured as a Transmit FIFO)||
||1 = Requests sending a message; the bit is automatically clearedwhen all the messages queued in the FIFO||
||are successfully sent||
||0 = Clearing the bit to ‘0’ while set (‘1’) requests|a message abort|
||TXEN= 0 (FIFO configured as a Receive FIFO)||
||This bit has no effect.||
|bit 8|UINC: Increment Head/ Tail bit||
||TXEN = 1 (FIFO configured as a Transmit FIFO)||
||When this bit is set, the FIFO head increments by a single message||
||TXEN = 0 (FIFO configured as a Receive FIFO)||
||When this bit is set, the FIFO tail increments by a single message||
|bit 7|TXEN: TX/RX Buffer Selection bit?)||
||1 = Transmit Message Object||
||0 = Receive Message Object||
|bit 6|RTREN: Auto RTR Enable bit||
||1 = When a remote transmit is received, TXREQ|is set|
||0 = When a remote transmit is received, TXREQ|is unaffected|
|bit 5|RXTSEN: Received Message Time Stamp Enable bit")||
||1 = Capture time stamp in received message object in RAM||
||0 = Capture time stamp is not captured||
||Note:<br>|Change only in Configuration mode, since it is used for address calculation.||
|bit 4|TXATIE: TransmitAttempts Exhausted Interrupt Enable bit||
||1 = Enable interrupt||
||0 = Disable interrupt||
|bit 3|RXOVIE: Overflow Interrupt Enable bit||
||1 = Interrupt enabled for overflow event||
||0 = Interrupt disabled for overflow event||
|bit 2|TFERFFIE: Transmit/Receive FIFO Empty/Full Interrupt Enable bit||
||TXEN= 1 (FIFO configured as a Transmit FIFO)||
||Transmit FIFO Empty Interrupt Enable||
||1 = Interrupt enabled for FIFO empty||
||0 = Interrupt disabled for FIFO empty||
||TXEN= 0 (FIFO configured as a Receive FIFO)||
||Receive FIFO Full Interrupt Enable||
||1 = Interrupt enabled for FIFO full||
||0 = Interrupt disabled for FIFO full||
|bit 1|TFHRFHIE: Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit||
||TXEN= 1 (FIFO configured as a Transmit FIFO)||
||Transmit FIFO Half Empty Interrupt Enable||
||1 = Interrupt enabled for FIFO halfempty||
||0 = Interrupt disabled for FIFO halfempty||
||TXEN= 0 (FIFO configured as a Receive FIFO)||
||Receive FIFO Half Full Interrupt Enable||
||1 = Interrupt enabled for FIFO half full||
||0=InterruptdisabledforFIFOhalffull||
- Note 1: These bits can only be modified in Configuration mode (OPMOD = 100). 2: This bit is updated when a message completes (or aborts) or when the FIFO is reset. 3: FRESET is set while in Configuration mode and is automatically cleared in Normal mode.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 503
## PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 31-17: CFD2FIFOCONm: FIFO CONTROL REGISTER m, (m = 1 to 15) (CONTINUED)
- bit 0 TFNREFNIE: Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit TXEN = 1 (FIFO configured as a Transmit FIFO) Transmit FIFO Not Full Interrupt Enable
- 1 = Interrupt enabled for FIFO not full
- 0 = Interrupt disabled for FIFO not full TXEN = 0 (FIFO configured as a Receive FIFO) Receive FIFO Not Empty Interrupt Enable
- 1 = Interrupt enabled for FIFO not empty
- O = Interrupt disabled for FIFO not empty
- Note 1: These bits can only be modified in Configuration mode (OPMOD = 100). 2: This bit is updated when a message completes (or aborts) or when the FIFO is reset.
- 3: FRESET is set while in Configuration mode and is automatically cleared in Normal mode.
renner eee e rereerence eee eee DS70005425A-page 504 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
## REGISTER 31-18: CFD2FIFOSTAm: FIFO STATUS REGISTER m, (m = 1 to 15)
|Range|| 31/23/15/7 | 30/22/14/6 | 29/21/13/5 |28/20/12/4|28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0|
|---|---|---|
||Ss<br>eS<br>ee|ee<br>ee eee eee ea|
||aa||
||a a||
|Legend:|||
|R = Readable bit<br>W = Writable bit||U = Unimplemented bit, read as ‘0’|
|S=Settablebit<br>C=Clearablebit||x=BitisunknownatReset|
- bit 31-13 Unimplemented: Read as ‘0’
- bit 4-0 FIFOCI<4:0>: FIFO Message Index bits TXEN = 1 (FIFO configured as a Transmit Buffer)
- A read of this register returns an index to the message that the FIFO attempts to transmit next. TXEN = 0 (FIFO configured as a Receive Buffer) A read of this register returns an index to the message that the FIFO uses to save the next message.
- bit 7 TXABT: Message Aborted Status bit 1 = Message is aborted
- 0 = Message completed successfully
- bit 6 TXLARB: Message Lost Arbitration Status bit 1 = Message lost arbitration while being sent 0 = Message does not loose arbitration while being sent
- bit 5 TXERR: Error Detected During Transmission bit 1 =A bus error occurs while the message is being sent 0 = Abus error does not occur while the message is being sent
- bit 4 TXATIF: Transmit Attempts Exhausted Interrupt Pending bit TXEN = 1 (FIFO configured as a Transmit Buffer) 1 = Interrupt is pending 0 = Interrupt is not pending TXEN = 0 (FIFO configured as a Receive Buffer) Unused, reads ‘0’
- bit 3 RXOVIF: Receive FIFO Overflow Interrupt Flag bit TXEN = 1 (FIFO configured as a Transmit Buffer) Unused, reads ‘0’ TXEN = 0 (FIFO configured as a Receive Buffer) 1 = Overflow event has occurred 0 = No overflow event occurred
- Note 1: FIFOCI<4:0> gives a zero-indexed value to the message in the FIFO. If the FIFO is 4 messages deep (FSIZE=5°h03) FIFOCI will take on a value of 0 to 3 depending on the state of the FIFO.
- 2: This bit is reset on any read of this register or when the TXQ is reset.
- 3: This bit is updated when a message completes (or aborts) or when the FIFO is reset.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 505
## PIC32MZ W1 and WFI32E01 Family
## seman
**==> picture [438 x 387] intentionally omitted <==**
**----- Start of picture text -----**<br>
|||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|REGISTER|31-18:|CFD2FIFOSTAm:|FIFO|STATUS|REGISTER|m,|(m|=|1|to|15)|(CONTINUED)|
|bit|2|TFERFFIF:|Transmit/Receive|FIFO|Empty/Full|Interrupt|Flag|bit|
|TXEN =|1|(FIFO|configured|as|a|Transmit|FIFO)|
|Transmit|FIFO|Empty|Interrupt|Flag|
|1|=|FIFO|is|empty|
|0|=|FIFO|is|not|empty,|at|least|1|message|queued|to|be|transmitted|
|TXEN|=|0|(FIFO|configured|as|a|Receive|FIFO)|
|Receive|FIFO|Full|Interrupt|Flag|
|1|=|FIFO|is|full|
|0|=|FIFO|is|not|full|
|bit|1|TFHRFHIF:|Transmit/Receive|FIFO|Half|Empty/Half|Full|Interrupt|Flag|bit|
|TXEN =|1|(FIFO|configured|as|a|Transmit|FIFO)|
|Transmit|FIFO|Half|Empty|Interrupt|Flag|
|1|=|FIFO|is|<=|half|full|
|0|=|FIFO|is|>|half|full|
|TXEN=0|(FIFO|configured|as|a|Receive|FIFO)|
|Receive|FIFO|Half|Full|Interrupt|Flag|
|1|=|FIFO|is|>=|half|full|
|0|=|FIFO|is|<|half|full|
|bit|0|TFNRENIF:|Transmit/Receive|FIFO|Not|Full/Not|Empty|Interrupt|Flag|bit|
|TXEN =|1|(FIFO|configured|as|a|Transmit|FIFO)|
|Transmit|FIFO|Not|Full|Interrupt|Flag|
|1|=|FIFO|is|not|full|
|0|=|FIFO|is|full|
|TXEN|=|0|(FIFO|configured|as|a|Receive|FIFO)|
|Receive|FIFO|Not|Empty|Interrupt|Flag|
|1|=|FIFO|is|not|empty,|has|at|least|1|message|
|0|=|FIFO|is|empty|
|Note|1:|FIFOCI<4:0>|gives|a|zero-indexed|value|to|the|message|in|the|FIFO.|If|the|FIFO|is|4|messages|deep|
|(FSIZE=5°h03)|FIFOCI|will|take|on|a|value|of|0|to|3|depending|on|the|state|of the|FIFO.|
**----- End of picture text -----**<br>
- 2: This bit is reset on any read of this register or when the TXQ is reset.
- 3: This bit is updated when a message completes (or aborts) or when the FIFO is reset.
renner eee e rereerence eee eee DS70005425A-page 506 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
## REGISTER 31-19: CFD2TEFCON: TRANSMIT EVENT FIFO CONTROL REGISTER
|Range|| 31/23/15/7 | 30/22/14/6 | 29/21/13/5 |28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0|
|---|---|
||a<br>a<br>a<br>=|
||a<br>a|
||a<br>a=|
||Derren<br>|<br>terovie [Terrie | TerHie | TeFNEIE ||
|Legend:||
|R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’||
|S=Settablebit<br>C=Clearablebit<br>x=BitisunknownatReset||
- bit 31-29 Unimplemented: Read as ‘0’
- bit 28-24 FSIZE<4:0>: FIFO Size bits!) 00000 = FIFO is 1 message deep
- 00001 = FIFO is 2 messages deep 00002 = FIFO is 3 messages deep
## 11111 = FIFO is 32 messages deep
- bit 23-11 Unimplemented: Read as ‘0’ bit 10 FRESET: FIFO Reset bit 1 = FIFO is reset when the bit is set and cleared by hardware. The user should poll this bit is clear before taking any action.
- 0 = No effect
- bit 9 Unimplemented: Read as ‘0’ bit 8 UINC: Increment Tail bit When this bit is set, the FIFO tail increments by a single message.
- bit 7-6 Unimplemented: Read as ‘0’ bit 5 TEFTSEN: Transmit Event FIFO Time Stamp Enable bit!)
- 1 = Time stamp elements in TEF 0 = Don’t time stamp elements in TEF
- bit 4 Unimplemented: Read as ‘0’ bit 3 TEFOVIE: Transmit Event FIFO Overflow Interrupt Enable bit 1 = Interrupt enabled for overflow event 0 = Interrupt disabled for overflow event
- bit 2 TEFFIE: Transmit Event FIFO Full Interrupt Enable bit 1 = Interrupt enabled for FIFO full 0 = Interrupt disabled for FIFO full
- bit 1 TEFHIE: Transmit Event FIFO Half Full Interrupt Enable bit 1 = Interrupt enabled for FIFO half full 0 = Interrupt disabled for FIFO half full
- bit 0 TEFNEIE: Transmit Event FIFO Not Empty Interrupt Enable bit 1 = Interrupt enabled for FIFO not empty 0 = Interrupt disabled for FIFO not empty
- Note 1: CFD2TEFCON: These bits can only be modified in Configuration Mode (OPMOD = 100).
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 507
PIC32MZ W1 and WFI32E01 Family
## seman
REGISTER 31-20: CFD2TEFSTA: TRANSMIT EVENT FIFO STATUS REGISTER
|Bit<br>Bit<br>Bit|Bit|Bit<br>Bit<br>Bit|Bit|Bit|
|---|---|---|---|---|
|Range| 31/23/15/7 |30/22/14/6 |29/21/13/5||||28/20/12/4| 27/19/11/3 | 26/18/10/2|25/17/9/1|24/16/8/0|
|poetBe ee<br>ee<br>ae<br>pee Se<br>eo|||||
|70<br>a A||2<br>1|1|1|
|Legend:|||||
|R = Readable bit<br>W = Writable bit||U = Unimplemented bit, read as ‘0’|||
|S = Settable bit<br>C = Clearable bit||x = Bit is unknown at Reset|||
|‘1’=BitissetatReset<br>‘0’=Bitiscleared|atReset|HC=Hardwareclear<br>HS=SetbyHardwareonly|||
|bit|31-4|Unimplemented: Read as ‘0’|
|---|---|---|
|bit|3|TEFOVIF: Transmit Event FIFO Overflow Interrupt Flag bit'?)|
|||1 = Overflow event has occurred|
|||0 = No overflow event occurred|
|bit2|2|TEFFIF: Transmit Event FIFO Full Interrupt Flag bit(t)|
|||1 = FIFO is full|
|||0 = FIFO is not full|
|bit|1|TEFHIF: Transmit Event FIFO Half Full Interrupt Flag bit")|
|||1 = FIFO is >= half full|
|||0 = FIFO is < half full|
|bit|0|TEFNEIF: Transmit Event FIFO Not Empty Interrupt Flag bit")|
|||1 = FIFO is not empty, has at least<br>1 message|
|||0=FIFOisempty|
- Note 1: CFD2TEFSTA: This bit is read only and reflects the status of the FIFO. 2: TEFOVIF bit is cleared by FIFO Reset.
renner eee e rereerence eee eee DS70005425A-page 508 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
REGISTER 31-21: CFD2FIFOUAm: FIFO USER ADDRESS REGISTER m, (m = 1 to 15)
|Bit|Bit|Bit|Bit|Bit|Bit||Bit|Bit|Bit|
|---|---|---|---|---|---|---|---|---|---|
|Range | 31/23/15/7|||30/22/14/6 |29/21/13/5||| 28/20/12/4|| 27/19/11/3 |26/18/10/2|||| 25/17/9/1 | 24/16/8/0||
|31:24<br>CE||||4||||||
|23:16||||7||||||
|15:8<br>[es oe|||||||ti|||
|7:0|||||1|||||
|Legend:||||||||||
|R = Readable bit||W = Writable bit||U = Unimplemented bit, read as ‘0’||||||
|S = Settable bit||C = Clearable bit||X = Bit is unknown at Reset||||||
|‘1’=BitissetatReset||‘0’=Bitiscleared|atReset|HC=Hardwareclear||HS=|Setby|Hardwareonly||
- bit 31-0 FIFOUA<31:0>: FIFO User Address bits!)
- TXEN= 1 (FIFO configured as a Transmit Buffer) A read of this register returns the address where the next message is to be written (FIFO head). TXEN= 0 (FIFO configured as a Receive Buffer) A read of this register returns the address where the next message is to be read (FIFO tail).
- Note 1: This register is not guaranteed to read correctly in Configuration mode and should only be accessed when the module is not in Configuration mode.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 509
PIC32MZ W1 and WFI32E01 Family
## seman
REGISTER 31-22: CFD2TEFUA: TRANSMIT EVENT FIFO USER ADDRESS REGISTER
|Bit|Bit|Bit|Bit|Bit<br>Bit||Bit|Bit|Bit|
|---|---|---|---|---|---|---|---|---|
|Range|| 31/23/15/7||30/22/14/6 |29/21/13/5||| 28/20/12/4 | 27/19/11/3 |26/18/10/2 ||||25/17/9/1 | 24/16/8/0||
|31:24<br>joie|<br>23:16<br>ae|1<br>|<br>EE<br>gg<br> |S<br>ES<br>tee||||||||
|15:8||7||||:|||
|7:0||||1|||||
|Legend:|||||||||
|R = Readable bit||W = Writable bit||U = Unimplemented bit, read as ‘0’|||||
|S = Settable bit||C = Clearable bit||x = Bit is unknown at Reset|||||
|‘1’=Bitis|setatReset|‘0’=Bitiscleared|atReset|HC=Hardwareclear|HS=|SetbyHardwareonly|||
bit 31-0 TEFUA<31:0>: Transmit Event FIFO User Address bits!) A read of this register returns the address where the next event is to be read (FIFO tail).
Note 1: This register is not guaranteed to read correctly in Configuration mode and should only be accessed when the module is not in Configuration mode.
renner eee e rereerence eee eee DS70005425A-page 510 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
REGISTER 31-23: CFD2TXQUA: TRANSMIT QUEUE USER ADDRESS REGISTER
|Bit|Bit|Bit|Bit|Bit<br>Bit||Bit<br>Bit|Bit|
|---|---|---|---|---|---|---|---|
|Range | 31/23/15/7|||30/22/14/6 |29/21/13/5||| 28/20/12/4 | 27/19/11/3 |26/18/10/2 | 25/17/9/1 | 24/16/8/0||||
|31:24<br>4<br>[sie|Sea||||||||
|23:16||||7||||
|15:8<br>pe|ea|||||ee||
|7:0||||1||||
|Legend:||||||||
|R = Readable bit||W = Writable bit||U = Unimplemented bit, read as ‘0’||||
|S = Settable bit||C = Clearable bit||X = Bit is unknown at Reset||||
|‘1’=BitissetatReset||‘0’=Bitiscleared|atReset|HC=Hardwareclear|HS=|SetbyHardwareonly||
- bit 31-0 TXQUA<31:0>: TXQ User Address bits!")
- A read of this register returns the address where the next message is to be written (TXQ head).
- Note 1: This register is not guaranteed to read correctly in Configuration mode and should only be accessed when the module is not in Configuration mode.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 511
PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 31-24: CFD2TREC: TRANSMIT/RECEIVE ERROR COUNT REGISTER
|Bit|Bit|Bit|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit|
|---|---|---|---|
|Range|| 31/23/15/7 ||30/22/14/6 |29/21/13/5 | 28/20/12/4 | 27/19/11/3 |26/18/10/2 | 25/17/9/1 | 24/16/8/0||
|933-16<br>|<br>asePRP<br>| ro|PF uo | vo | ri | Ro |<br>| Ro | Ro | RO | RO |<br>P=<br>x80 txer exer |TxWarn |RXWARN|EWARN|<br>PRP ee | ne **|e** eeLe | n**e** **|e**<br> [Be tee [ee<br>ee | e|||
|Legend:||||
|R = Readable bit||W = Writable bit|U = Unimplemented bit, read as ‘0’|
|S = Settable bit||C = Clearable bit|X = Bit is unknown at Reset|
|‘1’=Bitis|setatReset|‘0’=Bitiscleared|atReset<br>HC=Hardwareclear<br>HS=SetbyHardwareonly|
bit 31-22 Unimplemented: Read as ‘0’ bit 21 TXBO: Transmitter in Error State Bus Off bit (TERRCNT > 255) In Configuration mode, TXBO is set, since the module is not on the bus. bit 20 TXBP: Transmitter in Error State Bus Passive bit (TERRCNT > 127) bit 19 RXBP: Receiver in Error State Bus Passive bit (RERRCNT > 127) bit 18 TXWARN: Transmitter in Error State Warning bit (128 > TERRCNT > 95) bit 17 RXWARN: Receiver in Error State Warning bit (128 > RERRCNT > 95) bit 16 EWARN: Transmitter or Receiver is in Error State Warning bit bit 15-8 TERRCNT<7:0>: Transmit Error Counter bits bit 7-0 RERRCNT<7:0>: Receive Error Counter bits
renner eee e rereerence eee eee DS70005425A-page 512 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
REGISTER 31-25: CFD2BDIAGO: BUS DIAGNOSTICS REGISTER 0
|BitRange<br>Bit<br>9°!<br>34/23/1517|Bit<br>Bit<br>30/22/14/6 | 29/21/13/5|Bit<br>28/20/12/4|Bit<br>27/19/11/3|Bit<br>26/18/10/2|Bit<br>26/18/10/2|Bit<br>25/17/9/1|Bit<br>24/16/8/0|
|---|---|---|---|---|---|---|---|
||||||||||
|,||||||||
|||DRERRCNT<7:0>||||||
|:||||||||
|:||||||||
|Legend:||||||||
|R = Readable bit|W = Writable bit|U = Unimplemented bit, read||as ‘0’||||
|S = Settable bit|C = Clearable bit|x = Bit is unknown at Reset||||||
|‘1’=BitissetatReset|‘0’=BitisclearedatReset|HC=Hardware|clear|HS=|Setby|Hardwareonly||
bit 31-24 DTERRCNT<7:0>: Data Bit Rate Transmit Error Counter bits bit 23-16 DRERRCNT<7:0>: Data Bit Rate Receive Error Counter bits bit 15-8 NTERRCNT<7:0>: Nominal Bit Rate Transmit Error Counter bits bit 7-0 NRERRCNT<7:0>: Nominal Bit Rate Receive Error Counter bits
- Note 1: Errors are captured in the nominal error bit register bits when the bits are transmitted with nominal bit rate (In a CAN 2.0 frame or a CAN-FD frame with BRS = 0).
- 2: Errors are captured in the data phase error bit register bits when the bits are transmitted with data bit rate (In a CAN 2.0 frame or a CAN-FD frame with BRS = 1).
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 513
## PIC32MZ W1 and WFI32E01 Family seman
## REGISTER 31-26: CFD2BDIAG1: BUS DIAGNOSTICS REGISTER 1
|Bit|Bit|Bit||Bit|Bit|Bit||Bit<br>Bit<br>Bit|
|---|---|---|---|---|---|---|---|---|
|Range|| 31/23/15/7 |30/22/14/6 |||29/21/13/5||28/20/12/4|27/19/11/3||26/18/10/2<br>25/17/9/1<br>24/16/8/0|
|31:24|Pbtomm | esi |||2)<br> DORCERR®||(2)<br>(2)<br>(2)<br>(2)<br> |DSTUFERR®[DFORMERR™|<br>__— _[DBITIERR® |DBITOERR™||||
|'8|[Fxeorre||| — |NORCERRT|NORCERRT||[NSTUFERR|[NFORMERR|||NACKERR™|NBITIERR™|NBITOERR ||
|:|||||||||
|vo<br>:|[|_RW||||||||
|Legend:|||||||||
|R = Readable bit||W = Writable|bit||U = Unimplemented bit, read as||‘0’||
|S = Settable bit||C = Clearable||bit|x = Bit is unknown at Reset||||
|‘1’=BitissetatReset||‘0’=Bitiscleared||atReset|HC=Hardware|clear|HS=SetbyHardwareonly||
bit 31 DLCMM: DLC Mismatch bit
During a transmission or reception, the specified DLC is larger than the PLSIZE of the FIFO element.
- bit 30 ESI: ESI flag of a received CAN-FD message is set. bit 29 DCRCERR: The CRC check sum of a received message is incorrect in the data phase. The CRC of an incoming message does not match with the CRC calculated from the received data. (2)
- bit 28 DSTUFERR: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed.)
- bit 27 DFORMERR: A fixed format part of a received frame has the wrong format.(2)
- bit 26 Unimplemented: Read as ‘0’ bit 25 DBIT1ERR: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value ‘1’), but the monitored bus value is dominant.()
- bit 24 DBITOERR: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value ‘0’), but the monitored bus value is recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed).2)
- bit 23 TXBOERR: Device went to bus-off (and auto-recovered) bit 22 Unimplemented: Read as ‘0’ bit 21 NCRCERR: The CRC check sum of a received message is incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data.(")
- bit20 | NSTUFERR: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed.')
- bit 19 NFORMERR: A fixed format part of a received frame has the wrong format.) bit 18 NACKERR: Transmitted message is not acknowledged.") bit 17 NBIT1ERR: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value ‘1’), but the monitored bus value is dominant.
- Note 1: Errors are captured in the nominal error bit register bits when the bits are transmitted with Nominal bit rate (In a CAN 2.0 frame or a CAN-FD frame with BRS = 0).
- 2: Errors are captured in the data phase error bit register bits when the bits are transmitted with data bit rate (In a CAN 2.0 frame or a CAN-FD frame with BRS = 1).
renner eee e rereerence eee eee DS70005425A-page 514 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family smn
- bit 16 NBITOERR: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value ‘0’), but the monitored bus value is recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed).(1)
- bit 15-0 EFMSGCNT<15:0>: Error Free Message Counter bits
- Note 1: Errors are captured in the nominal error bit register bits when the bits are transmitted with Nominal bit rate (In a CAN 2.0 frame or a CAN-FD frame with BRS = 0).
- 2: Errors are captured in the data phase error bit register bits when the bits are transmitted with data bit rate (In a CAN 2.0 frame or a CAN-FD frame with BRS= 1).
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**----- Start of picture text -----**<br>
REGISTER 31-27: CFD2FLTCONm: FILTER CONTROL REGISTER m, (m = 0 to 3, n= 0 to 31)<br>Bit Range Bit Bit Bit Bit Bit Bit Bit Bit<br>9 31/23/15/7 | 30/22/14/6 | 29/21/13/5 |28/20/12/4) 27/19/11/3 | 26/18/10/2 25/17/9/1 | 24/16/8/0<br>—S———SPaOSSCSCSCS<br>“ars [ = [ —- |<br>° om = [= [—s—SwPDSSSC~*”<br>a SC a<br>a<br>**----- End of picture text -----**<br>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Settable bit C = Clearable bit X = Bit is unknown at Reset ‘1’ = Bit is set at Reset ‘0’ = Bit is cleared at Reset HC = Hardware clear HS = Set by Hardware only
bit 7, 15, 23, FLTENn: Enable Filter n to Accept Messages bits 31 1 = Filter is enabled
0 = Filter is disabled
bit 4-0, 12-8, FnBP<4:0>: Pointer to Object when Filter n hits bits 20-16, 28-24 11111 = Message matching filter is stored in Object 31 1_1110 = Message matching filter is stored in Object 30
0.0010 = Message matching filter is stored in Object 2 00001 = Message matching filter is stored in Object 1 00000 = Reserved. Object 0 is the TX Queue and can’t receive messages.
- Note 1: CFD2FLTCON: These bits can only be modified if the corresponding filter is disabled (FLTEN = 0). 2: CFD2FLTCON: Maximum value of m is configured using the numberoffilters module parameter (m = number of filters/4 - 1)
## mE
© 2020 Microchip Technology Inc. Preliminary Data Sheet
DS70005425A-page 515
PIC32MZ W1 and WFI32E01 Family
## seman
REGISTER 31-28: CFD2FLTOBJm: FILTER OBJECT REGISTER m, (m = 0 to 15)
|BitRange<br>9|Bit<br>Bit<br>Bit<br>31/23/15/7|30/22/14/6 |29/21/13/5|Bit<br>Bit<br>Bit<br>31/23/15/7|30/22/14/6 |29/21/13/5|Bit<br>Bit<br>Bit<br>31/23/15/7|30/22/14/6 |29/21/13/5|Bit<br>Bit<br>Bit<br>|28/20/12/4| 27/19/11/3 | 26/18/10/2|Bit<br>Bit<br>25/17/9/1 | 24/16/8/0|
|---|---|---|---|---|---|
|“=||exe sonS—~SCSOVNSS||||
|:||||||
|:||||||
|-<br>|||||||
|Legend:||||||
|R = Readable bit||W = Writable bit||U = Unimplemented bit, read as ‘0’||
|S = Settable bit||C = Clearable bit||x = Bit is unknown at Reset||
|‘1’=Bitissetat|Reset|‘0’=Bitiscleared|atReset|HC=Hardwareclear<br>HS=SetbyHardwareonly||
bit 31 Unimplemented: Read as ‘0’ bit 30 EXIDE: Extended Identifier Enable bit If MIDE = 1: 1 = Match only messages with extended identifier addresses 0 = Match only messages with standard identifier addresses bit 29 $1ID11: Standard identifier filter bit bit 28-11 EID<17:0>: Extended Identifier filter bits In DeviceNet mode, these are the filter bits for the first 2 data bytes bit 10-0 SID<10:0>: Standard Identifier filter bits
Note: These registers can only be changed when the filter is disabled (CFD2FLTCON.FLTENm = 0).
renner eee e rereerence DS70005425A-page 516
eee eee Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
ee
REGISTER 31-29: CFD2MASKm: MASK REGISTER m, (m = 0 to 15)
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|||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Bit Range|Bit|Bit|Bit|Bit|Bit|Bit|Bit|Bit|
|9|31/23/15/7 | 30/22/14/6|| 29/21/13/5||28/20/12/4||27/19/11/3 ||26/18/10/2|25/17/9/1|24/16/8/0|
|[=|ie|son SCOTTISCSCSC~*|
|53-16:|
|:|
|:|
|Legend:|
|R|=|Readable|bit|W|=|Writable|bit|U|=|Unimplemented|bit,|read|as|‘0’|
|S|=|Settable|bit|C|=|Clearable|bit|x|=|Bit|is|unknown|at|Reset|
|‘1’|=|Bit|is|set|at|Reset|‘0’|=|Bit|is|cleared|at|Reset|HC|=|Hardware|clear|HS|=|Set|by|Hardware|only|
|bit|31|Unimplemented:|Read|as|‘0’|
|bit|30|MIDE:|Identifier|Receive|Mode|bit|
|1|=|Match|only|message|types|(standard|or|extended|address)|that|correspond|to|EXIDE|bit|in|filter|
|0|=|Match|either|standard|or|extended|address|message|if|filters|match|
|(if|(Filter|SID)|=|(Message|SID)|or|if|(Filter|SID/EID)|=|(Message|SID/EID))|
|bit|29|MSID11:|Standard|Identifier|Mask|bit|
|bit|28-11|MEID<17:0>:|Extended|Identifier|Mask|bits|
|In|DeviceNet|mode,|these|are|the|mask|bits|for|the|first|2|data|bytes|
|bit|10-0|MSID<10:0>:|Standard|Identifier|Mask|bits|
|Note:|These|registers|can|only|be changed|when|the|filter|is|disabled|(CFD2FLTCON.FLTENm =|0).|
**----- End of picture text -----**<br>
ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 517
PIC32MZ W1 and WFI32E01 Family
DS70005425A-page 518
Preliminary Data Sheet © 2020 Microchip Technology Inc.
## PIC32MZ W1 and WFI32E01 Family smn 32.0 WI-FI CONTROLLER * Control frame generation like Request to Send
- 32.0 WI-FI CONTROLLER * Control frame generation like Request to Send (RTS), Clear to Send (CTS), acknowledgment
- PIC32MZ W1 supports on-chip IEEE 802.11b/g/n compliant Single Input Single Output (SISO) WLAN inter32.2 Baseband Processor (BBP)/PHY face with integrated transceivers. Wireless Local Area Network (WLAN) block comprises of on-chip Base PIC32MZ W1 WLAN PHY is designed to achieve reliBand Processor (BBP)/MAC and RF transceiver. able and power-efficient physical layer communication. Key features of the WLAN sub-system include: me W1 IEEE 802.11 PHY supports the following ¢ IEEE 802.11b/g/n 2.4 GHz, single stream (1x1) 20 ign . MHz ¢ Single antenna 1x1 stream in 20 MHz channels.
- * Capability to operate in one of the following * Supports IEEE 802.11b DSSS-CCK and IEEE modes: SoftAP or STA 802.11g OFDM
- * Supports IEEE 802.11 WEP, WPA, WPA2, WPA3 * 802.11n MCSO-7 in 20 MHz security ¢ Support for both short guard and long guard inter-
- * Transmit Power Control (TPC) and regulatory val support ¢ IEEE 802.11n mixed mode operation
- * High MAC throughput via hardware accelerated * Per packet TX TX power control A-MSDU/A-MPDU « Advanced channel estimation/equalization, auto-
- Per packet TX TX power control
- « Advanced channel estimation/equalization, automatic gain control, Clear Channel Assessment (CCA), carrier/symbol recovery and frame detection
- Hardware support for immediate block acknowledgment and Reduced Interframe Spacing (RIFS)
- * Baseband implements hardware-based calibration mechanism intended to reduce test time and
- The radio architecture in PIC32MZ W1 is based on a direct conversion topology employing a fully integrated synthesizer. The receiver has an on-chip LNA, while the transmitter utilizes an on-chip pre-driver for the SReTanr es eke RPRSeatresare: RPRSeatresare: ¢ Ultra low-power direct conversion architecture * Fractional-N synthesizer
tures supported in the software, refer to the Software Release Notes.
32.1 Media Access Control (MAC) SReTanr es The WLAN MAC subsystem along with software stack eke RPRSeatresare: RPRSeatresare: executing in PIC32MZ W1 implements the MAC func¢ Ultra low-power direct conversion architecture tions in compliance with IEEE 802.11n specifications. * Fractional-N synthesizer 802.11 WLAN MAC hardware is responsible for sharing * Fast power up/down time access of the common wireless medium between dif* On-chip Power Management Unit (PMU) ferent WLAN devices. The design is optimized for best + Integrated LNA and diversity feature performance by moving memory intensive and time * On-chip calibration (TX/RX /Q phase/amplitude critical functionality to the hardware. Some of the feamismatch, LOFT, VCO, filter) tures which are part of the MAC hardware are: ~ Fastseiiion DGoffsel cancellation . nueeee to the Enea 7 « Receive RF RSSI for better interference handling . a data integrity (positive acknowledgment, * Support for PA pre-distortion
- ¢ Support for power management
- Inter frame spacing required between transmission of wireless frames
- ¢ Network allocation vector to take care of virtual carrier-sensing mechanism
- Implementation of the time critical back-off timers
- ¢ Encryption and decryption using the cipher engine (TKIP/CCMP)
- ¢ CCMP and TKIP replay detection
- Fragmentation
- ¢ Aggregation/De-aggregation
- Checking for Sequence number and duplicate packet detection
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 519
PIC32MZ W1 and WFI32E01 Family
DS70005425A-page 520
Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
## 33.0 ETHERNET CONTROLLER
- Supports both manual and automatic flow control
- RAM descriptor-based DMA operation for both receive and transmit path
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Note: This data sheet summarizes the receive and transmit path<br>features of the PIC32MZ W1 family of + Fully configurable interrupts<br>devices. It is not intended to be a ; . —_<br>comprehensive: reference source. To * Configurable receive packet filtering<br>complement the information in this data - CRC check<br>sheet, refer to Section 35. “Ethernet - 64-byte pattern match<br>Controller” (DS60001155) in the “PIC32 - Broadcast, multicast and unicast packets<br>Family Reference Manual”, which is - Magic Packet™<br>available from the Microchip web site<br>(www.microchip.com/PIC32). _ abs Eeesh fable<br>- Runt packet<br>The Ethernet Controller is a bus master module that * Supports packet payload checksum calculation<br>interfaces with an off-chip Physical Layer (PHY) to * Supports various hardware statistics counters<br>implement a complete a complete complete Ethernet node in a system. » PIC32MZ W1 can supply reference clock to save<br>Key features of the Ethernet Controller include: crystal cost in PHY<br>* Supports 10/100 Mbps data transfer rates Figure 33-1 illustrates a block diagram of the Ethernet<br>* Supports full-duplex and half-duplex operation Controller.<br>* Supports RMII PHY interface<br>FIGURE 33-1: ETHERNET CONTROLLER BLOCK DIAGRAM<br>|<br>||<br>°<br>||<br>|TX Flow Control l<br>2||<br>€ RMII<br>eB | | RX Flow<br>| fo) Control<br>RXxDMA|@=]Ww RX BM |<br>||<br>|| MAG -——» External<br>REF_CLK Bet<br>Fx BGs Ko RX Filter RX Function<br>||<br>||<br>| |<br>isa3 K—)| ControlDMA | MACandControl<br>5 Registers EthernetDMA |<br>6 | | egisters<br>é) .~ ooo ______ pl<br>ra — Host IF<br>Ethernet Controller ree ore<br>**----- End of picture text -----**<br>
The Ethernet Controller is a bus master module that interfaces with an off-chip Physical Layer (PHY) to implement a complete a complete complete Ethernet node in a system. Key features of the Ethernet Controller include:
- Supports 10/100 Mbps data transfer rates
- Supports full-duplex and half-duplex operation
- Supports RMII PHY interface
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 521
PIC32MZ W1 and WFI32E01 Family
ne
Table 33-1 and Table 33-2 show two interfaces and the associated pins that can be used with the Ethernet Controller.
|by selected<br>interface can be used by|
|---|
|otherperipherals.|
|TABLE|33-1:<br>RMII|MODE DEFAULT INTERFACE SIGNALS (FMIIEN = 0, FETHIO = 1)|
|---|---|---|
|J|PinName||<br>scription|
|TABLE 33-2:<br>RMII <br>(Piname||MODE ALTERNATE INTERFACE SIGNALS (FMIIEN = 0, FETHIO = 0)<br>|<br>(scription<br>Cid|
OOOO___ DS70005425A-page 522 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
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PIC32MZ W1 and WFI32E01 Family
## smn
|REGISTER 33-1:|ETHCON1: ETHERNET CONTROLLER CONTROL REGISTER 1|ETHCON1: ETHERNET CONTROLLER CONTROL REGISTER 1|
|---|---|---|
|Bit<br>Bit<br>Bit<br>Range | 34/23/15/7 |30/22/14/6||Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br> | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0|
|:|||
|:|||
|8<br>foo|sierts||
|° aorors||wanestro|
|Legend:|||
|R = Readable bit||W = Writable bit<br>U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR||‘1’=Bitisset<br>‘0’=Bitiscleared<br>x=Bitisunknown|
- bit 31-16 PTV<15:0>: PAUSE Timer Value bits
PAUSE timer value used for flow control. This register should only be written when RXEN (ETHCON1<8>) is not set. These bits are only used for flow control operations.
- bit 15 ON: Ethernet ON bit
- 1 = Ethernet module is enabled
- 0 = Ethernet module is disabled
- bit 14 Unimplemented: Read as ‘0’ bit 13 SIDL: Ethernet Stop in Idle Mode bit
- 1 = Ethernet module transfers are paused during Idle mode
- 0 = Ethernet module transfers continue during Idle mode
- bit 12-10 Unimplemented: Read as ‘0’
- bit 9 TXRTS: Transmit Request to Send bit
- 1 =Activate the TX logic and send the packet(s) defined in the TX Ethernet Descriptor Table (EDT) 0 = Stop transmit (when cleared by software) or transmit done (when cleared by hardware)
- After the bit is written with a ‘1’, it clears to a ‘0’ whenever the transmit logic has finished transmitting the requested packets in the EDT. If a ‘0’ is written by the CPU, the transmit logic finishes the current packet’s transmission and then stops any further.
- This bit only affects TX operations.
- bit 8 RXEN: Receive Enable bit!) 1 = Enable RX logic, packets are received and stored in the RX buffer as controlled by the filter configuration
- 0 = Disable RX logic, no packets are received in the RX buffer
- This bit only affects RX operations.
- bit 7 AUTOFC: Automatic Flow Control bit 1 = Automatic flow control is enabled 0 = Automatic flow control is disabled
- Setting this bit enables automatic flow control. If set, the full and empty watermarks are used to automatically enable and disable the flow control, respectively. When the number of received buffers BUFCNT (ETHSTAT<16:23>) rises to the full watermark, flow control is automatically enabled. When the BUFCNT falls to the empty watermark, flow control is automatically disabled. This bit is only used for flow control operations and affects both TX and RX operations.
- bit 6-5 Unimplemented: Read as ‘0’ Note 1: It is not recommended to clear the RXEN bit and then make changes to any RX related field/register. The Ethernet Controller must be reinitialized (ON cleared to ‘0’), and then the RX changes applied.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 525
## PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 33-1: ETHCON1: ETHERNET CONTROLLER CONTROL REGISTER 1 (CONTINUED)
bit 4 MANFC: Manual Flow Control bit
1 = Manual flow control is enabled
0 = Manual flow control is disabled
- Setting this bit enables manual flow control. If set, the flow control logic sends a PAUSE frame using the PAUSE timer value in the PTV register. It then resends a PAUSE frame every 128 * PTV<15:0>/2 TX clock cycles until the bit is cleared. Note: For 10 Mbps operation, TX clock runs at 2.5 MHz. For 100 Mbps operation, TX clock runs at 25 MHz.
When this bit is cleared, the flow control logic automatically sends a PAUSE frame with a 0x0000 PAUSE timer value to disable flow control.
This bit is only used for flow control operations and affects both TX and RX operations. bit 3-1 Unimplemented: Read as ‘0’ bit 0 BUFCDEC: Descriptor Buffer Count Decrement bit
The BUFCDEC bit is a write-1 bit that reads as ‘0’. When written with a ‘1’, the BUFCNT decrements by one. If BUFCNT is incremented by the RX logic at the same time that this bit is written, the BUFCNT value remains unchanged. Writing a ‘0’ does not have any effect. This bit is only used for RX operations.
- Note 1: It is not recommended to clear the RXEN bit and then make changes to any RX related field/register. The Ethernet Controller must be reinitialized (ON cleared to ‘0’), and then the RX changes applied.
renner eee e rereerence eee eee DS70005425A-page 526 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
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REGISTER 33-2: ETHCON2: ETHERNET CONTROLLER CONTROL REGISTER 2
|REGISTER 33-2:<br>ETHCON2: ETHERNET CONTROLLER CONTROL REGISTER 2|REGISTER 33-2:<br>ETHCON2: ETHERNET CONTROLLER CONTROL REGISTER 2|REGISTER 33-2:<br>ETHCON2: ETHERNET CONTROLLER CONTROL REGISTER 2|REGISTER 33-2:<br>ETHCON2: ETHERNET CONTROLLER CONTROL REGISTER 2|REGISTER 33-2:<br>ETHCON2: ETHERNET CONTROLLER CONTROL REGISTER 2|
|---|---|---|---|---|
|BitRange<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>31/23/15/7 |30/22/14/6 |29/21/13/5 |28/20/12/4 |27/19/11/3 |26/18/10/2 | 25/17/9/1<br>24/16/8/0|||||
|i|a||||
|°|ifpxeurszaoe——“‘iSSS<br>SOS CT<br>Ud)<br>Sd||||
|Legend:|||||
|R = Readable bit||W = Writable bit|U = Unimplemented bit, read|as ‘0’|
|-n=Value|atPOR|‘1’=Bitisset|‘0’=Bitiscleared<br>x=|Bitisunknown|
## bit 31-11 Unimplemented: Read as ‘0’
bit 10-4 RXBUFSZ<6:0>: RX Data Buffer Size for All RX Descriptors (in 16-byte increments) bits 1111111 = RX data buffer size for descriptors is 2032 bytes
1100000 = RX data buffer size for descriptors is 1536 bytes
0000011 = RX data buffer size for descriptors is 48 bytes 0000010 = RX data buffer size for descriptors is 32 bytes 0000001 = RX data buffer size for descriptors is 16 bytes 0000000 = Reserved
bit 3-0 Unimplemented: Read as ‘0’
Note 1: This register is only used for RX operations.
- 2: The bits in this register may only be changed while the RXEN bit (ETHCON1<8>) = 0.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 527
PIC32MZ W1 and WFI32E01 Family
## seman
**==> picture [456 x 186] intentionally omitted <==**
**----- Start of picture text -----**<br>
REGISTER 33-3: ETHTXST: ETHERNET CONTROLLER TX PACKET DESCRIPTOR START<br>ADDRESS REGISTER<br>Bit Bit Bit Bit Bit Bit Bit Bit Bit<br>Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 24/16/8/0<br>:<br>—_:<br>_:<br>-<br>° [smo<br>——“—*~s*s*—S—S—C—sésSC“( Sd<br>Legend:<br>R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’<br>-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared X = Bit is unknown<br>**----- End of picture text -----**<br>
## bit 31-2 TXSTADDR<31:2>: Starting Address of First Transmit Descriptor bits
This register should not be written while any transmit, receive or DMA operations are in progress. This address must be 4-byte aligned (bits 1-0 must be ‘00’).
- bit 1-O Unimplemented: Read as ‘0’
- Note 1: This register is only used for TX operations. 2: This register will be updated by hardware with the last descriptor used by the last successfully transmitted packet.
## REGISTER 33-4: ETHRXST: ETHERNET CONTROLLER RX PACKET DESCRIPTOR START
**==> picture [454 x 173] intentionally omitted <==**
**----- Start of picture text -----**<br>
ADDRESS REGISTER<br>Bit Bit Bit Bit Bit Bit Bit Bit Bit<br>Range | 34/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 24/16/8/0<br>:<br>—_:<br>es:<br>-<br>iexsapornees—“—sS*SsSsSSSSCCCCCCCCC<br>° ( SO Sd] Se Sd<br>Legend:<br>R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’<br>-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown<br>**----- End of picture text -----**<br>
## bit 31-2 RXSTADDR<31:2>: Starting Address of First Receive Descriptor bits
- This register should not be written while any transmit, receive or DMA operations are in progress. This address must be 4-byte aligned (bits 1-0 must be ‘00’).
- bit 1-O Unimplemented: Read as ‘0’
- Note 1: This register is only used for RX operations.
- 2: This register will be updated by hardware with the last descriptor used by the last successfully transmitted packet.
renner eee e rereerence eee eee DS70005425A-page 528 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
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REGISTER 33-5: ETHHT0: ETHERNET CONTROLLER HASH TABLE 0 REGISTER
|Bit<br>Bit<br>Bit<br>Range |31/23/15/7 | 30/22/14/6|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br> | 29/21/13/5 | 28/20/12/4 |27/19/11/3 | 26/18/10/2 | 25/17/9/1|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br> | 29/21/13/5 | 28/20/12/4 |27/19/11/3 | 26/18/10/2 | 25/17/9/1|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br> | 29/21/13/5 | 28/20/12/4 |27/19/11/3 | 26/18/10/2 | 25/17/9/1|Bit<br>24/16/8/0|
|---|---|---|---|---|
|:|||||
|:|||||
|:|||||
|:|||||
|Legend:|||||
|R = Readable bit|W = Writable bit|U = Unimplemented bit, read as ‘0’|||
|-n=ValueatPOR|‘1’=Bitisset|‘0’=Bitiscleared|x=Bitisunknown||
bit 31-0 HT<31:0>: Hash Table Bytes 0-3 bits
- Note 1: This register is only used for RX operations.
- 2: The bits in this register may only be changed while the RXEN bit (ETHCON1<8>) = 0 or the HTEN bit (ETHRXFC<15>) = 0.
**==> picture [448 x 191] intentionally omitted <==**
**----- Start of picture text -----**<br>
REGISTER 33-6: ETHHT1: ETHERNET CONTROLLER HASH TABLE 1 REGISTER<br>Bit Range Bit Bit Bit Bit Bit Bit Bit Bit<br>31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0<br>:<br>:<br>:<br>:<br>Legend:<br>R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’<br>-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown<br>**----- End of picture text -----**<br>
bit 31-0 HT<63:32>: Hash Table Bytes 4-7 bits
- Note 1: This register is only used for RX operations.
- 2: The bits in this register may only be changed while the RXEN bit (ETHCON1<8>) = 0 or the HTEN bit (ETHRXFC<15>) = 0.
me
© 2020 Microchip Technology Inc. Preliminary Data Sheet
DS70005425A-page 529
PIC32MZ W1 and WFI32E01 Family
## seman
|REGISTER|33-7:|ETHPMM0: ETHERNET CONTROLLER PATTERN MATCH MASK 0 REGISTER|ETHPMM0: ETHERNET CONTROLLER PATTERN MATCH MASK 0 REGISTER|ETHPMM0: ETHERNET CONTROLLER PATTERN MATCH MASK 0 REGISTER|ETHPMM0: ETHERNET CONTROLLER PATTERN MATCH MASK 0 REGISTER|ETHPMM0: ETHERNET CONTROLLER PATTERN MATCH MASK 0 REGISTER|
|---|---|---|---|---|---|---|
|BitRange|Bit||Bit<br>Bit|Bit<br>Bit|Bit<br>Bit|Bit|
||31/23/15/7|||30/22/14/6 |29/21/13/5 |28/20/12/4 | 27/19/11/3 |26/18/10/2 | 25/17/9/1|||| 24/16/8/0|
|:|||||||
|v6<br>:|||||||
|ca<br>:|||||||
|-<br>:|||||||
|Legend:|||||||
|R = Readable bit|||W = Writable bit|U = Unimplemented bit, read as ‘0’|||
|-n=Valueat|POR||‘1’=Bitisset|‘0’=Bitiscleared|x=Bitisunknown||
bit 31-24 PMM<31:24>: Pattern Match Mask3 bits bit 23-16 PMM<23:16>: Pattern Match Mask 2 bits bit 15-8 PMM<15:8>: Pattern Match Mask 1 bits bit 7-0 PMM<7:0>: Pattern Match Mask0 bits
- Note 1: This register is only used for RX operations. 2: The bits in this register may only be changed while the RXEN bit (ETHCON1<8>) = 0 or the PMMODE bit (ETHRXFC<11:8>) = 0.
REGISTER 33-8: ETHPMM1: ETHERNET CONTROLLER PATTERN MATCH MASK 1 REGISTER
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**----- Start of picture text -----**<br>
Bit Range. Bit Bit Bit Bit Bit Bit Bit oencashi<br>31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1<br>:<br>a:<br>es:<br>":<br>Legend:<br>R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’<br>-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown<br>**----- End of picture text -----**<br>
bit 31-24 PMM<63:56>: Pattern Match Mask7 bits bit 23-16 PMM<55:48>: Pattern Match Mask6 bits bit 15-8 PMM<47:40>: Pattern Match Mask 5 bits bit 7-0 PMM<39:32>: Pattern Match Mask 4 bits
- Note 1: This register is only used for RX operations. 2: The bits in this register may only be changed while the RXEN bit (ETHCON1<8>) = 0 or the PMMODE bit (ETHRXFC<11:8>) = 0.
renner eee e rereerence eee eee DS70005425A-page 530 Preliminary Data Sheet © 2020 Microchip Technology Inc.
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REGISTER 33-9: ETHPMCS: ETHERNET CONTROLLER PATTERN MATCH CHECKSUM REGISTER
|REGISTER|REGISTER|REGISTER||
|---|---|---|---|
|Bit Range<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>31/23/15/7 |30/22/14/6 |29/21/13/5 |28/20/12/4 |27/19/11/3 |26/18/10/2 | 25/17/9/1|||Bit<br>24/16/8/0|
|96<br>pt<br>|Se||||
|_<br>|||||
|-<br>:||||
|Legend:||||
|R = Readable bit<br>W = Writable bit||U = Unimplemented bit, read as ‘0’||
|-n=ValueatPOR<br>‘1’=Bitisset||‘0’=Bitiscleared<br>x=Bitisunknown||
bit 31-16 Unimplemented: Read as ‘0’ bit 15-8 PMCS<15:8>: Pattern Match Checksum1 bits bit 7-0 PMCS<7:0>: Pattern Match Checksum 0 bits
- Note 1: This register is only used for RX operations. 2: The bits in this register may only be changed while the RXEN bit (ETHCON1<8>) = 0 or the PMMODE bit (ETHRXFC<11:8>) = 0.
REGISTER 33-10: ETHPMO: ETHERNET CONTROLLER PATTERN MATCH OFFSET REGISTER
|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Range | 34/23/15/7 | 30/22/14/6 |29/21/13/5 |28/20/12/4 |27/19/11/3 | 26/18/10/2|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Range | 34/23/15/7 | 30/22/14/6 |29/21/13/5 |28/20/12/4 |27/19/11/3 | 26/18/10/2|Bit<br> | 25/17/9/1|Bit<br> | 24/16/8/0|
|---|---|---|---|
|en<br>ee a A<br>pte<br>|SS<br>eo eo||||
|_<br>2||||
|:||||
|Legend:||||
|R = Readable bit|W = Writable bit<br>U = Unimplemented bit, read as ‘0’|||
|-n=ValueatPOR|‘1’=Bitisset<br>‘0’=Bitiscleared|x=Bitisunknown||
bit31-16 Unimplemented: Read as ‘0’ bit 15-0 PMO<15:0>: Pattern Match Offset 1 bits
- Note 1: This register is only used for RX operations. 2: The bits in this register may only be changed while the RXEN bit (ETHCON1<8>) = 0 or the PMMODE bit (ETHRXFC<11:8>) = 0.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 531
## PIC32MZ W1 and WFI32E01 Family
## seman
|REGISTER 33-11:<br>ETHRXFC: ETHERNET CONTROLLER RECEIVE FILTER CONFIGURATION|REGISTER 33-11:<br>ETHRXFC: ETHERNET CONTROLLER RECEIVE FILTER CONFIGURATION|REGISTER 33-11:<br>ETHRXFC: ETHERNET CONTROLLER RECEIVE FILTER CONFIGURATION|REGISTER 33-11:<br>ETHRXFC: ETHERNET CONTROLLER RECEIVE FILTER CONFIGURATION|
|---|---|---|---|
||REGISTER|||
|Bit<br>Range|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br> | 341/23/15/7 | 30/22/14/6<br>29/21/13/5 =|28/20/12/4 |27/19/11/3 | 26/18/10/2 |25/17/9/1 |24/16/8/0|||
|pa)|| SS Se ee|Ee||
|as<br>®|[owten [wren [—~*«| NoTem |<br>—~SSC*MMODEGO>|||
|-<br>:||||
|Legend:||||
|R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’||||
|-n = Value at POR<br>‘1’ = Bit is set<br>‘0’ = Bit is cleared|||x = Bit is unknown|
|bit 31-16|Unimplemented: Read as ‘0’|||
|bit 15|HTEN: Enable Hash Table Filtering bit|||
||1 = Enable Hash Table Filtering|||
||0 = Disable Hash Table Filtering|||
|bit 14|MPEN: Magic Packet Enable bit|||
||1 = Enable magic packet filtering|||
||0 = Disable magic packet filtering|||
|bit 13|Unimplemented: Read as ‘0’|||
|bit 12|NOTPM: Pattern Match Inversion bit|||
||1 = Pattern match checksum must not match for a successful pattern match|to occur||
||0 = Pattern match checksum must match for a successful pattern match to occur|||
||This bitdetermines whether pattern match checksum must match in order for a successful pattern match to|||
||occur.|||
|Note<br>1:|XOR = True when either one or the other conditions are true, but not both.|||
|2:|This hash table filter match is active regardless of the value of the HTEN bit.|||
|3:|This magic packet filter match is active regardless of the value of the MPEN bit.|||
|Note<br>1:|This register is only used for RX operations.|||
|2:|ThebitsinthisregistermayonlybechangedwhiletheRXENbit(ETHCON1<8>)=||0.|
renner eee e rereerence eee eee DS70005425A-page 532 Preliminary Data Sheet © 2020 Microchip Technology Inc.
**==> picture [457 x 446] intentionally omitted <==**
**----- Start of picture text -----**<br>
PIC32MZ W1 and WFI32E01 Family<br>smn<br>REGISTER 33-11: ETHRXFC: ETHERNET CONTROLLER RECEIVE FILTER CONFIGURATION<br>REGISTER (CONTINUED)<br>bit 11-8 PMMODE<3:0>: Pattern Match Mode bits<br>1001 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND<br>(Packet = Magic Packet)(1:3)<br>1000 = Pattern match is successful if (NO<br>TPM = 1 XOR Pattern Match Checksum matches) AND<br>(Hash Table Filter match)'"1)<br>0111 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND<br>(Destination Address = Broadcast Address)()<br>0110 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND<br>(Destination Address = Broadcast Address)\")<br>0101 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND<br>(Destination Address = Unicast Address)"")<br>0100 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND<br>(Destination Address = Unicast Address) \)<br>0011 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches)AND<br>(Destination Address = Station Address)"")<br>0010 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND<br>(Destination Address = Station Address)"<br>0001 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches)(")<br>0000 = Pattern Match is disabled; pattern match is always unsuccessful<br>bit 7 CRCERREN: CRC Error Collection Enable bit<br>1 = The received packet CRC must be invalid for the packet to be accepted<br>0 = Disable CRC Error Collection filtering<br>This bit allows the user to collect all packets that have an invalid CRC.<br>bit 6 CRCOKEN: CRC OK Enable bit<br>1 = The received packet CRC must be valid for the packet to be accepted<br>0 = Disable CRC filtering<br>This bit allows the user to reject all packets that have an invalid CRC.<br>bit 5 RUNTERREN: Runt Error Collection Enable bit<br>1 = The received packet must be a runt packet for the packet to be accepted<br>0 = Disable Runt Error Collection filtering<br>This bit allows the user to collect all packets that are runt packets. For this filter, a runt packet is defined as<br>any packet with a size of less than 64 bytes (when CRCOKEN= 0) or any packet with a size of less than<br>64 bytes that has a valid CRC (when CRCOKEN = 1).<br>**----- End of picture text -----**<br>
- bit 4 RUNTEN: Runt Enable bit
- 1 = The received packet must not be a runt packet for the packet to be accepted 0 = Disable Runt filtering
- This bit allows the user to reject all runt packets. For this filter, a runt packet is defined as any packet with a size of less than 64 bytes.
- bit 3 UCEN: Unicast Enable bit
- 1 = Enable unicast filtering
- 0 = Disable unicast filtering
- This bit allows the user to accept all unicast packets whose Destination Address matches the Station Address.
- Note 1: XOR = True when either one or the other conditions are true, but not both. 2: This hash table filter match is active regardless of the value of the HTEN bit.
- 3: This magic packet filter match is active regardless of the value of the MPEN bit.
- Note 1: This register is only used for RX operations.
- 2: The bits in this register may only be changed while the RXEN bit (ETHCON1<8>) = 0.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 533
## PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 33-11: ETHRXFC: ETHERNET CONTROLLER RECEIVE FILTER CONFIGURATION REGISTER (CONTINUED)
|||REGISTER (CONTINUED)|
|---|---|---|
|bit|2|NOTMEEN: Not Me Unicast Enable bit|
|||1 = Enable not me unicast filtering|
|||0 = Disable not me unicast filtering|
|||This bit allows the user to accept all unicast packets whose destination address does not match the station|
|||address.|
|bit|1|MCEN: Multicast Enable bit|
|||1 = Enable multicast filtering|
|||0 = Disable multicast filtering|
|||This bit allows the user to accept all multicast address packets.|
|bit|0|BCEN: Broadcast Enable bit|
|||1 = Enable broadcast filtering|
|||0 = Disable broadcast filtering|
|||Thisbitallowstheusertoacceptallbroadcastaddresspackets.|
- Note 1: XOR = True when either one or the other conditions are true, but not both. 2: This hash table filter match is active regardless of the value of the HTEN bit. 3: This magic packet filter match is active regardless of the value of the MPEN bit.
- Note 1: This register is only used for RX operations. 2: The bits in this register may only be changed while the RXEN bit (ETHCON1<8>) = 0.
renner eee e rereerence eee eee DS70005425A-page 534 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
## REGISTER 33-12: ETHRXWM: ETHERNET CONTROLLER RECEIVE WATERMARKS REGISTER
|BitRange|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>31/23/15/7 |30/22/14/6 |29/21/13/5 |28/20/12/4 |27/19/11/3 |26/18/10/2 | 25/17/9/1 ||Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>31/23/15/7 |30/22/14/6 |29/21/13/5 |28/20/12/4 |27/19/11/3 |26/18/10/2 | 25/17/9/1 ||Bit<br> 24/16/8/0|
|---|---|---|---|
|pa|EeEe|||
|:||||
|pose|EEE|Se||
|:||||
|Legend:||||
|R = Readable bit||W = Writable bit<br>U = Unimplemented bit, read as ‘0’||
|-n=Valueat|POR|‘1’=Bitisset<br>‘0’=Bitiscleared<br>x=Bitisunknown||
- bit 31-24 Unimplemented: Read as ‘0’
bit 23-16 RXFWM<7:0>: Receive Full Watermark bits
The software controlled RX buffer full watermark pointer is compared against the RX BUFCNT to determine the Full Watermark condition for the FWMARK interrupt and for enabling flow control when automatic flow control is enabled. The full watermark pointer should always be greater than the empty watermark pointer.
- bit 15-8 Unimplemented: Read as ‘0’
- bit 7-0 RXEWM<7:0>: Receive Empty Watermark bits
The software controlled RX buffer empty watermark pointer is compared against the RX BUFCNT to determine the Empty Watermark condition for the EWMARK interrupt and for disabling flow control when automatic flow control is enabled. The empty watermark pointer should always be less than the full watermark pointer.
Note: This register is only used for RX operations.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 535
## PIC32MZ W1 and WFI32E01 Family seman
## REGISTER 33-13: ETHIEN: ETHERNET CONTROLLER INTERRUPT ENABLE REGISTER
**==> picture [455 x 150] intentionally omitted <==**
**----- Start of picture text -----**<br>
Range | 31/23/15/7 30/22/14/6 | 29/21/13/5 |28/20/12/4) 27/19/11/3 | 26/18/10/2 25/17/9/1 24/16/8/0<br>Se ee ee ee ee ee ee eee<br>a a ee ee ee ee ee eee<br>= xeusee[Rxeusee [Ear| FMarKE?? |<br>RXDONEIE® | PKTPENDIE® | RxACTIE® | _— | TKOONEIET| TXABORTIEW | RXBUFNAIE®! | RXOVFLIVIE® |<br>Legend:<br>R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’<br>-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown<br>**----- End of picture text -----**<br>
- bit 31-15 Unimplemented: Read as ‘0’ bit14 | TXBUSEIE: Transmit BVCI Bus Error Interrupt Enable bit!) 1 = Enable TXBUS error interrupt
- 0 = Disable TXBUS error interrupt
- bit13. RXBUSEIE: Receive BVCI Bus Error Interrupt Enable bit) 1 = Enable RXBUS error interrupt 0 = Disable RXBUS error interrupt
- bit 12-10 Unimplemented: Read as ‘0’ bit 9 EWMARKIE: Empty Watermark Interrupt Enable bit(2) 1 = Enable EWMARK interrupt 0 = Disable EWMARK interrupt
- bit 8 FWMARKIE: Full Watermark Interrupt Enable bit'2) 1 = Enable FWMARK interrupt 0 = Disable FWMARK interrupt
- bit 7 RXDONEIE: Receiver Done Interrupt Enable bit'2) 1 = Enable RXDONE interrupt
- 0 = Disable RXDONE interrupt
- bit 6 PKTPENDIE: Packet Pending Interrupt Enable bit!) 1 = Enable PKTPEND interrupt 0 = Disable PKTPEND interrupt
- bit 5 RXACTIE: RX Activity Interrupt Enable bit 1 = Enable RXACT interrupt
- 0 = Disable RXACT interrupt
- bit 4 Unimplemented: Read as ‘0’ bit 3 TXDONEIE: Transmitter Done Interrupt Enable bit!) 1 = Enable TXDONE interrupt 0 = Disable TXDONE interrupt
- bit 2 TXABORTIE: Transmitter Abort Interrupt Enable bit!) 1 = Enable TXABORT interrupt 0 = Disable TXABORT interrupt
- bit 1 RXBUFNAIE: Receive Buffer Not Available Interrupt Enable bit’) 1 = Enable RXBUFNA interrupt 0 = Disable RXBUFNA interrupt
- bit 0 RXOVFLWIE: Receive FIFO Overflow Interrupt Enable bit!2) 1 = Enable RXOVFLW interrupt 0 = Disable RXOVFLW interrupt
- Note 1: This bit is only used for TX operations.
- 2: This bit is only used for RX operations.
renner eee e rereerence eee eee DS70005425A-page 536 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
**==> picture [459 x 204] intentionally omitted <==**
**----- Start of picture text -----**<br>
REGISTER 33-14: ETHIRQ: ETHERNET CONTROLLER INTERRUPT REQUEST<br>REGISTER<br>Bit Range Bit Bit Bit Bit Bit Bit Bit Bit<br>31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 24/16/8/0<br>8 = Frese Prous [eva r ear<br>° _[Rxoone [pxtpenb@| rxact® | — | TxDone [TxABORT™] RXBUFNA® | RXOVELWE)|<br>Legend:<br>R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’<br>-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown<br>**----- End of picture text -----**<br>
- bit 31-15 Unimplemented: Read as ‘0’
- bit 14 TXBUSE: Transmit BVCI Bus Error Interrupt bit!)
- 1 = BVCI bus error has occurred
- 0 = BVCI bus error has not occurred This bit is set when the TX DMA encounters a BVCI bus error during a memory access. It is cleared by either a Reset or CPU write of a ‘1’ to the CLR register.
- bit 13 RXBUSE: Receive BVCI Bus Error Interrupt bit(?)
- 1 = BVCI bus error has occurred
- 0 = BVCI bus error has not occurred
- This bit is set when the RX DMA encounters a BVCI Bus error during a memory access. It is cleared by either a Reset or CPU write of a ‘1’ to the CLR register.
- bit 12-10 Unimplemented: Read as ‘0’
- bit 9 EWMARK: Empty Watermark Interrupt bit?) 1 = Empty watermark pointer reached
- 0 = No interrupt pending
- This bit is set when the RX descriptor buffer count is less than or equal to the value in the RXEWM bit (ETHRXWM<0:7>) value. It is cleared by BUFCNT bit (ETHSTAT<16:23>) being incremented by hardware. Writing a ‘0’ or a ‘1’ has no effect.
- bit 8 FWMARK: Full Watermark Interrupt bit'2)
- 1 = Full Watermark pointer reached
- 0 = No interrupt pending
This bit is set when the RX descriptor buffer count is greater than or equal to the value in the RXFWM bit (ETHRXWM<16:23>) field. It is cleared by writing the BUFCDEC (ETHCON1<0>) bit to decrement the BUFCNT counter. Writing a ‘0’ or a ‘1’ has no effect.
- Note 1: This bit is only used for TX operations.
- 2: This bit is are only used for RX operations.
- 3: It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or clearing any bits in this register should only be done for debug/test purposes.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 537
## PIC32MZ W1 and WFI32E01 Family seman
|REGISTER|33-14:<br>ETHIRQ: ETHERNET CONTROLLER INTERRUPT REQUEST||||
|---|---|---|---|---|
||REGISTER (CONTINUED)||||
|bit 7|RXDONE: Receive Done Interrupt bit(2)||||
||1 = RX packetwas successfully received||||
||0 = No interrupt pending||||
||This bit is setwheneveran RX packet is successfully received. It is cleared by either|a Reset orCPU write|||
||ofa ‘1’ to the CLR register.||||
|bit 6|PKTPEND: Packet Pending Interrupt bit!?)||||
||1 = RX packet pending in memory||||
||0 = RX packet is not pending in memory||||
||This bit is setwhen the BUFCNT counter has a value other than ‘o’. It is cleared by|either a Reset or by|||
||writing the BUFCDEC bit to decrement the BUFCNT counter. Writing a ‘0’ or a ‘1’ has no||effect.||
|bit 5|RXACT: ReceiveActivity Interrupt bit(2)||||
||1 = RX packet data was successfully received||||
||0 = No interrupt pending||||
||This bit is setwhenever RX packet data is stored in the RXBM FIFO. It is cleared by either||a Reset orCPU||
||write ofa ‘1’ to the CLR register.||||
|bit 4|Unimplemented: Read as ‘0’||||
|bit 3|TXDONE: Transmit Done Interrupt bit")||||
||1 = TX packetwas successfully sent||||
||0 = No interrupt pending||||
||This bit is setwhen the presentTXpacketcompletes transmission, and the transmit status||vector is loaded||
||into the first descriptor used for the packet. It is cleared by either a Reset orCPU write of||a ‘1’ to the CLR||
||register.||||
|bit2|TXABORT: Transmit Abort Condition Interrupt bit()||||
||1 = TXAbort condition occurred on the lastTX packet||||
||0 = No interrupt pending||||
||This bit is setwhen the MAC aborts the transmission of a TX packet for one ofthe following reasons:||||
||« Jumbo TX packet abort||||
||¢<br>Underrun abort||||
||«<br>Excessive defer abort||||
||¢<br>Late collision abort||||
||*<br>Excessive collisions abort||||
||This bit is cleared by either<br>a Reset or CPU write of a ‘1’ to the CLR register.||||
|bit 1|RXBUFNA: Receive Buffer NotAvailable Interrupt bit'2)||||
||1 = RX BD NotAvailable condition has occurred||||
||0 = No interrupt pending||||
||This bit is set by<br>a RX BD Overrun condition. It is cleared by either<br>a Reset or<br>a CPU write of|||a ‘1’ to the|
||CLR register.||||
|bit 0|RXOVFLW: Receive FIFO Over Flow Error bit’)||||
||1 = RX FIFO Overflow Error condition has occurred||||
||0 = No interrupt pending||||
||RXOVFLW is set by the RXBM Logic for an RX FIFO Overflow condition. It is cleared|by either||a Reset or|
||CPUwriteofa‘1’totheCLRregister.||||
- Note 1: This bit is only used for TX operations.
- 2: This bit is are only used for RX operations.
- 3: It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or clearing any bits in this register should only be done for debug/test purposes.
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## smn
## REGISTER 33-15: ETHSTAT: ETHERNET CONTROLLER STATUS REGISTER
**==> picture [453 x 179] intentionally omitted <==**
**----- Start of picture text -----**<br>
Bit Bit Bit Bit Bit Bit Bit Bit Bit<br>Range | 34/23/15/7 30/22/14/6 29/21/13/5 | 28/20/12/4 | 27/19/11/3 |26/18/10/2 | 25/17/9/1 | 24/16/8/0<br>Po= | —|— {| | {| — {| — { — | — | = __<br>—|<br>mo | Et Et _<br>° _[etsusy®" | txeusv® [axeusye7[— | — | — | — | — |<br>Legend:<br>R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’<br>-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown<br>**----- End of picture text -----**<br>
bit 31-24 Unimplemented: Read as ‘0’ bit 23-16 BUFCNT<7:0>: Packet Buffer Count bits")
- Number of packet buffers received in memory. Once a packet has been successfully received, this register is incremented by hardware based on the number of descriptors used by the packet. Software decrements the counter (by writing to the BUFCDEC bit (ETHCON1<0>) for each descriptor used) after a packet has been read out of the buffer. The register does not roll over (OxFF to 0x00) when hardware tries to increment the register and the register is already at OxFF. Conversely, the register does not roll under (0x00 to OxFF) when software tries to decrement the register and the register is already at Ox0000. When software attempts to decrement the counter at the same time that the hardware attempts to increment the counter, the counter value remains unchanged.
- When this register value reaches OxFF, the RX logic halts (only if automatic flow control is enabled) awaiting software to write the BUFCDEC bit in order to decrement the register below OxFF.
- If automatic flow control is disabled, the RXDMA continues processing and the BUFCNT saturates at a value of OxFF.
- When this register is non-zero, the PKTPEND status bit is set and an interrupt may be generated, depending on the value of the ETHIEN bit <PKTPENDIE> register.
When the ETHRXST register is written, the BUFCNT counter is automatically cleared to 0x00.
- Note: BUFCNT is not cleared when ONis set to ‘0’. This enables software to continue to utilize and decrement this count.
- bit 15-8 Unimplemented: Read as ‘0’
- bit 7 ETHBUSY: Ethernet Module Busy bit'®)
- 1 = Ethernet logic turns on (ON (ETHCON1<15>) = 1) or is completing a transaction
- 0 = Ethernet logic is idle
- This bit indicates that the module has been turned on or is completing a transaction after being turned off.
- Note 1: This bit is only used for RX operations.
- 2: This bit is only affected by TX operations.
- 3: This bit is only affected by RX operations.
- 4: This bit is affected by TX and RX operations.
- 5: This bit is set when the ON bit (ETHCON1<15>) = 1.
- 6: This bit is cleared when the ON bit (ETHCON1<15>) = 0.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 539
## PIC32MZ W1 and WFI32E01 Family
## seman
- REGISTER 33-15: ETHSTAT: ETHERNET CONTROLLER STATUS REGISTER (CONTINUED) bit 6 TXBUSY: Transmit Busy bit!?-®)
- 1 = TX logic is receiving data
- 0 = TX logic is idle
- This bit indicates that a packet is currently being transmitted. A change in this status bit is not necessarily reflected by the TXDONE interrupt, as TX packets may be aborted or rejected by the MAC.
- bit 5 RXBUSY: Receive Busy bit'*-®)
- 1 = RX logic is receiving data
- 0 = RX logic is idle
- This bit indicates that a packet is currently being received. A change in this status bit is not necessarily reflected by the RXDONE interrupt, as RX packets may be aborted or rejected by the RX filter.
- bit 4-0 Unimplemented: Read as ‘0’
- Note 1: This bit is only used for RX operations.
- 2: This bit is only affected by TX operations.
- 3: This bit is only affected by RX operations.
- 4: This bit is affected by TX and RX operations.
- 5: This bit is set when the ON bit (ETHCON1<15>) = 1.
- 6: This bit is cleared when the ON bit (ETHCON1<15>) = 0.
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## REGISTER 33-16: ETHRXOVFLOW: ETHERNET CONTROLLER RECEIVE OVERFLOW STATISTICS
## REGISTER
|REGISTER|REGISTER|REGISTER|
|---|---|---|
|BitRange<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>31/23/15/7 |30/22/14/6 |29/21/13/5 |28/20/12/4 |27/19/11/3 |26/18/10/2 | 25/17/9/1 | 24/16/8/0|||
|are<br>eere|ee <br> ee|ee ee<br> ee eaeCe a a|
|_<br>||||
|70<br>:|||
|Legend:|||
|R = Readable bit||W = Writable bit<br>U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR||‘1’=Bitisset<br>‘0’=Bitiscleared<br>x=Bitisunknown|
## bit 31-16 Unimplemented: Read as ‘0’ bit 15-0 RXOVFLWCNT<15:0>: Dropped Receive Frames Count bits
Increment counter for frames accepted by the RX filter and subsequently dropped due to internal receive error (RXFIFO overrun). This event also sets the RXOVFLW bit (ETHIRQ<0>) Interrupt flag.
- Note 1: This register is only used for RX operations.
- 2: This register is automatically cleared by hardware after a read operation, unless the byte enables for bytes 0/1 are ‘0’.
- 3: It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or clearing any bits in this register should only be done for debug/test purposes.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 541
## PIC32MZ W1 and WFI32E01 Family
## seman
**==> picture [449 x 204] intentionally omitted <==**
**----- Start of picture text -----**<br>
REGISTER 33-17: ETHFRMTXOK: ETHERNET CONTROLLER FRAMES TRANSMITTED OK<br>STATISTICS REGISTER<br>Bit Bit Bit Bit Bit Bit Bit Bit Bit<br>Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 24/16/8/0<br>wm Fe T= = = = = LE PE<br>pe SS ee<br>:<br>:<br>Legend:<br>R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’<br>-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown<br>**----- End of picture text -----**<br>
## bit 31-16 Unimplemented: Read as ‘0’
bit15-O FRMTXOKCNT<15:0>: Frame Transmitted OK Count bits Increment counter for frames successfully transmitted.
- Note 1: This register is only used for TX operations. 2: This register is automatically cleared by hardware after a read operation, unless the byte enables for bytes 0/1 are ‘0’.
- 3: It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or clearing any bits in this register should only be done for debug/test purposes.
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## REGISTER 33-18: ETHSCOLFRM: ETHERNET CONTROLLER SINGLE COLLISION FRAMES
STATISTICS REGISTER
|STATISTICS REGISTER|STATISTICS REGISTER|STATISTICS REGISTER|STATISTICS REGISTER|
|---|---|---|---|
|BitRange<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>31/23/15/7 |30/22/14/6 |29/21/13/5 | 28/20/12/4 |27/19/11/3 |26/18/10/2 | 25/17/9/1 | 24/16/8/0||||
|eere|ee|ee eaeCe a a||
|:||||
|:||||
|Legend:||||
|R = Readable bit||W = Writable bit|U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR||‘1’=Bitisset|‘0’=Bitiscleared<br>x=Bitisunknown|
- bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 SCOLFRMCNT<15:0>: Single Collision Frame Count bits Increment count for frames that were successfully transmitted on the second try.
- Note 1: This register is only used for TX operations.
- 2: This register is automatically cleared by hardware after a read operation, unless the byte enables for bytes 0/1 are ‘0’.
- 3: It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or clearing any bits in this register should only be done for debug/test purposes.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 543
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## seman
## REGISTER 33-19: ETHMCOLFRM: ETHERNET CONTROLLER MULTIPLE COLLISION FRAMES STATISTICS REGISTER
|mn<br>Range|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>:<br>31/23/15/7 |30/22/14/6 |29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>:<br>31/23/15/7 |30/22/14/6 |29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1|Bit<br>24/16/8/0|
|---|---|---|---|
|ww“ <br>paws|eT = =<br> SB Se|=<br>=<br>= LE<br> eee||
|158<br>:||||
||||||
|Legend:||||
|R = Readable bit<br>W = Writable bit||U = Unimplemented bit, read as ‘0’||
|-n=Value|atPOR<br>‘1’=Bitisset|‘0’=Bitiscleared<br>x=Bitisunknown||
bit 31-16 Unimplemented: Read as ‘0’ bit 15-0 MCOLFRMCNT<15:0>: Multiple Collision Frame Count bits Increment count for frames that were successfully transmitted after there was more than one collision.
- Note 1: This register is only used for TX operations. 2: This register is automatically cleared by hardware after a read operation, unless the byte enables for bytes 0/1 are ‘0’.
- 3: It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or clearing any bits in this register should only be done for debug/test purposes.
a
DS70005425A-page 544
Preliminary Data Sheet © 2020 Microchip Technology Inc.
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## smn
## REGISTER 33-20: ETHFRMRXOK: ETHERNET CONTROLLER FRAMES RECEIVED OK
|STATISTICS REGISTER|
|---|
|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 |27/19/11/3 | 26/18/10/2 | 25/17/9/1<br>24/16/8/0|
|aeOO<br>pe ES<br>ee ee|
|:|
|:|
|Legend:|
|R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR<br>‘1’=Bitisset<br>‘0’=Bitiscleared<br>x=Bitisunknown|
## bit 31-16 Unimplemented: Read as ‘0’
bit15-O FRMRXOKCNT<15:0>: Frames Received OK Count bits
- Increment count for frames received successfully by the RX filter. This count is not incremented if there is a Frame Check Sequence (FCS) or alignment error.
- Note 1: This register is only used for RX operations.
- 2: This register is automatically cleared by hardware after a read operation, unless the byte enables for bytes 0/1 are ‘0’.
- 3: It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or clearing any bits in this register should only be done for debug/test purposes.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 545
## PIC32MZ W1 and WFI32E01 Family
## seman
|REGISTER 33-21:|ETHFCSERR: ETHERNET CONTROLLER FRAME CHECK SEQUENCE ERROR|ETHFCSERR: ETHERNET CONTROLLER FRAME CHECK SEQUENCE ERROR|ETHFCSERR: ETHERNET CONTROLLER FRAME CHECK SEQUENCE ERROR|
|---|---|---|---|
||STATISTICS REGISTER|||
|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Range | 341/23/15/7 | 30/22/14/6 |29/21/13/5 | 28/20/12/4 | 27/19/11/3 |26/18/10/2 | 25/17/9/1|||Bit<br> |24/16/8/0|
|pas Se ee||||
|:||||
|:||||
|Legend:||||
|R = Readable bit|W = Writable bit|U = Unimplemented bit, read as ‘0’||
|-n=ValueatPOR|‘1’=Bitisset|‘0’=Bitiscleared<br>x=Bitisunknown||
## bit 31-16 Unimplemented: Read as ‘0’
- bit 15-0 FCSERRCNT<15:0>: FCS Error Count bits
- Increment count for frames received with FCS error and the frame length in bits is an integral multiple of 8 bits.
- Note 1: This register is only used for RX operations.
- 2: This register is automatically cleared by hardware after a read operation, unless the byte enables for bytes 0/1 are ‘0’.
- 3: It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or clearing any bits in this register should be only done for debug/test purposes.
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## REGISTER 33-22: ETHALGNERR: ETHERNET CONTROLLER ALIGNMENT ERRORS STATISTICS REGISTER
|REGISTER|||||
|---|---|---|---|---|
|Bit<br>Bit<br>Bit<br>Range | 34/23/15/7 | 30/22/14/6|Bit<br>Bit<br>Bit<br>Bit<br> |29/21/13/5 |28/20/12/4 | 27/19/11/3 | 26/18/10/2||Bit<br> | 25/17/9/1|Bit<br> | 24/16/8/0|
|en<br>a<br>pee eS|||||
|:|||||
|:|||||
|Legend:|||||
|R = Readable bit|W = Writable bit|U = Unimplemented bit, read as ‘0’|||
|-n=ValueatPOR|‘1’=Bitisset|‘0’=Bitiscleared|x=Bitisunknown||
## bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 ALGNERRCNT<15:0>: Alignment Error Count bits
- Increment count for frames with alignment errors. Note that an alignment error is a frame that has an FCS error and the frame length in bits is not an integral multiple of 8 bits (dribble nibble).
- Note 1: This register is only used for RX operations. 2: This register is automatically cleared by hardware after a read operation, unless the byte enables for bytes 0/1 are ‘0’.
- 3: It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or clearing any bits in this register should be only done for debug/test purposes.
## me
© 2020 Microchip Technology Inc. Preliminary Data Sheet
DS70005425A-page 547
PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 33-23: EMAC1CFG1: ETHERNET CONTROLLER MAC CONFIGURATION 1 REGISTER
Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 27/N9/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Se ee ee ee ee ee eee ee = = = = RESET RMCS RFUN TMCS TFUN = ee ee i a RESET ce ee | ee | P= Reo ack | TxPAUSE | RXPAUSE | PASSALL | RXENABLE | Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
## bit 31-16 Unimplemented: Read as ‘0’
- bit 15 SOFTRESET: Soft Reset bit Setting this bit puts the MACMII in Reset. Its default value is ‘1’.
- bit 14 SIMRESET: Simulation Reset bit
- Setting this bit causes a Reset to the random number generator within the transmit function.
- bit 13-12 Unimplemented: Read as ‘0’
- bit 11 RESETRMCS: Reset MCS/RX bit Setting this bit puts the MAC control sub-layer/receive domain logic in Reset.
- bit 10 RESETRFUN: Reset RX Function bit Setting this bit puts the MAC receive function logic in Reset.
- bit 9 RESETTMCS: Reset MCS/TX bit Setting this bit puts the MAC Control Sub-layer/TX domain logic in Reset.
- bit 8 RESETTFUN: Reset TX Function bit
- Setting this bit puts the MAC transmit function logic in Reset.
- bit 7-5 Unimplemented: Read as ‘0’ bit 4 LOOPBACK: MAC Loopback mode bit 1 = MAC transmit interface is loop backed to the MAC Receive interface 0 = MAC normal operation
- bit 3 TXPAUSE: MAC TX Flow Control bit 1 = PAUSE flow control frames are allowed to be transmitted 0 = PAUSE flow control frames are blocked
- bit 2 RXPAUSE: MAC RX Flow Control bit 1 = The MAC acts upon received PAUSE flow control frames
- 0 = Received PAUSE flow control frames are ignored
- bit 1 PASSALL: MAC Pass all Receive Frames bit 1 = The MAC accepts all frames regardless of type (normal vs. control) 0 = The received Control frames are ignored
- bit 0 RXENABLE: MAC Receive Enable bit 1 = Enable the MAC receiving of frames 0 = Disable the MAC receiving of frames
- Note: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 8-bit accesses are not allowed and are ignored by the hardware.
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## REGISTER 33-24: EMAC1CFG2: ETHERNET CONTROLLER MAC CONFIGURATION 2 REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit Range | 341/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 25/16/8/0 pa |e ee 15:8 aEXCESS BPNOBK NOBKee : Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
## bit 31-15 Unimplemented: Read as ‘0’
- bit 14 EXCESSDER: Excess Defer bit
- 1 = MAC defers to carrier indefinitely as per the standard
- 0 = MAC aborts when the excessive deferral limit is reached
- bit 13 BPNOBKOFF: Backpressure/No Backoff bit
- 1 = MAC after incidentally causing a collision during backpressure, immediately retransmits without backoff reducing the chance of further collisions and ensuring transmit packets get sent
- 0 = MAC does not remove the backoff
- bit 12 NOBKOFF: No Backoff bit
- 1 = Following a collision, the MAC immediately retransmits rather than using the Binary Exponential Backoff algorithm as specified in the standard
- 0 = Following a collision, the MAC uses the Binary Exponential Backoff algorithm
bit 11-10 Unimplemented: Read as ‘0’
- bit 9 LONGPRE: Long Preamble Enforcement bit
- 1 = MAC only allows receive packets which contain preamble fields less than 12 bytes in length
- 0 = MAC allows any length preamble as per the standard
- bit 8 PUREPRE: Pure Preamble Enforcement bit 1 = MAC verifies the content of the preamble to ensure it contains 0x55 and is error-free. A packet with errors in its preamble is discarded
- 0 = MAC does not perform any preamble checking
- bit 7 AUTOPAD: Automatic Detect Pad Enable bit!)
- 1 = MAC automatically detects the type of frame, either tagged or untagged, by comparing the two octets following the source address with 0x8100 (VLAN Protocol ID) and pad accordingly
- 0 = MAC does not perform automatic detection
- Note 1: Table 33-4 provides a description of the pad function based on the configuration of this register.
- 2: This bit is ignored if the PADENABLE bit is cleared.
- 3: This bit is used in conjunction with the AUTOPAD and VLANPAD bits.
- 4: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 8-bit accesses are not allowed and are ignored by the hardware.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 549
## PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 33-24: EMAC1CFG2: ETHERNET CONTROLLER MAC CONFIGURATION 2 REGISTER (CONTINUED)
- bit 6 VLANPAD: VLAN Pad Enable bit!) 1 = MAC pads all short frames to 64 bytes and append a valid CRC
- 0 = MAC does not perform padding of short frames
- bit 5 PADENABLE: Pad/CRC Enable bit(":) 1 = MAC pads all short frames
- 0 = Frames presented to the MAC havea valid length
- bit 4 CRCENABLE: CRC Enable’ bit 1 = MAC appends a CRC to every frame whether padding was required or not. Must be set if the PADENABLE bit is set.
- 0 = Frames presented to the MAC have a valid CRC
- bit 3 DELAYCRC: Delayed CRC bit This bit determines the number of bytes, if any, of proprietary header information that exist on the front of the IEEE 802.3 frames.
- 1 = Four bytes of header (ignored by the CRC function) 0 = No proprietary header
- bit 2 HUGEFRM: Huge Frame enable bit 1 = Frames of any length are transmitted and received
- 0 = Huge frames are not allowed for receive or transmit
- bit 1 LENGTHCK: Frame Length checking bit
- 1 = Both transmit and receive frame lengths are compared to the length/type field. If the length/type field represents a length then the check is performed. Mismatches are reported on the transmit/receive statistics vector.
- 0 = Length/type field check is not performed
- bit 0 FULLDPLX: Full-Duplex Operation bit 1 = MAC operates in Full-Duplex mode
- 0 = MAC operates in Half-Duplex mode
- Note 1: Table 33-4 provides a description of the pad function based on the configuration of this register. 2: This bit is ignored if the PADENABLE bit is cleared.
- 3: This bit is used in conjunction with the AUTOPAD and VLANPAD bits.
- 4: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 8-bit accesses are not allowed and are ignored by the hardware.
## TABLE 33-4: PAD OPERATION
**==> picture [447 x 68] intentionally omitted <==**
**----- Start of picture text -----**<br>
Any» Sid «ito ————_~[No pad, check CRC<br>Any 1 1 If untagged: Pad to 60 Bytes, append CRC<br>If VLAN tagged: Pad to 64 Bytes, append CRC<br>**----- End of picture text -----**<br>
renner eee e rereerence eee eee DS70005425A-page 550 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
## REGISTER 33-25: EMAC1IPGT: ETHERNET CONTROLLER MAC BACK-TO-BACK INTERPACKET GAP REGISTER
|Bit<br>Bit<br>Bit<br>Range | 34/23/15/7 | 30/22/14/6 | 29/21/13/5|Bit<br>Bit<br>| 29/21/13/5 | 28/20/12/4|||Bit<br>Bit<br>OBit<br>Bit<br> 27/19/11/3 |26/18/10/2 | 25/17/9/1 | 24/16/8/0|
|---|---|---|---|
|peatSe<br>ee<br>pa<br>| }See<br>ose pSyp<br>eee||||
|° =||sieterso>s—“—sS™S™SCCSCSCSCS||
|Legend:||||
|R = Readable bit|W = Writable bit||U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR|‘1’=Bitisset||‘0’=Bitiscleared<br>x=Bitisunknown|
## bit31-7 | Unimplemented: Read as ‘0’
- bit 6-0 B2BIPKTGP<6:0>: Back-to-Back Interpacket Gap bits
This is a programmable field representing the nibble time offset of the minimum possible period between the end of any transmitted packet, to the beginning of the next. In Full-Duplex mode, the register value should be the desired period in nibble times minus 3. In Half-Duplex mode, the register value should be the desired period in nibble times minus 6. In Full-Duplex mode, the recommended setting is 0x15 (21d), which represents the minimum IPG of 0.96 us (in 100 Mbps) or 9.6 us (in 10 Mbps). In Half-Duplex mode, the recommended setting is 0x12 (18d), which also represents the minimum IPG of 0.96 us (in 100 Mbps) or 9.6 us (in 10 Mbps).
- Note: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 8-bit accesses are not allowed and are ignored by the hardware.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 551
## PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 33-26: EMAC1IPGR: ETHERNET CONTROLLER MAC NON-BACK-TO-BACK
|INTERPACKET GAP REGISTER|
|---|
|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Range<br>31/23/15/7 |30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 |25/17/9/1 | 24/16/8/0|
|a<br>ne<br>pa SSS Se<br>eee|
|aCC|
|° (=<br>sectemsos—C—SCSCS|
|Legend:|
|R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR<br>‘1’=Bitisset<br>‘0’=Bitiscleared<br>x=Bitisunknown|
bit 31-15 Unimplemented: Read as ‘0’ bit14-8 NB2BIPKTGP1<6:0>: Non-Back-to-Back Interpacket Gap Part 1 bits This is a programmable field representing the optional carrierSense window referenced in Section 4.2.3.2.1 “Deference” of the IEEE 802.3 Specification. \f carrier is detected during the timing of IPGR1, the MAC defers to carrier. If, however, carrier becomes after IPGR1, the MAC continues timing IPGR2 and transmits, knowingly causing a collision, thus ensuring fair access to medium. Its range of values is 0x0 to IPGR2. Its recommend value is OxC (12d).
- bit 7 Unimplemented: Read as ‘0’
- bit 6-0 NB2BIPKTGP2<6:0>: Non-Back-to-Back Interpacket Gap Part 2 bits This is a programmable field representing the non-back-to-back Inter-Packet-Gap. Its recommended value is 0x12 (18d), which represents the minimum IPG of 0.96 Us (in 100 Mbps) or 9.6 us (in 10 Mbps).
Note: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 8-bit accesses are not allowed and are ignored by the hardware.
renner eee e rereerence eee eee DS70005425A-page 552 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
## REGISTER 33-27: EMAC1CLRT: ETHERNET CONTROLLER MAC COLLISION WINDOW/RETRY LIMIT REGISTER
**==> picture [456 x 179] intentionally omitted <==**
**----- Start of picture text -----**<br>
Bit Bit Bit Bit Bit Bit Bit Bit Bit<br>Range | 34/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0<br>kn<br>pas Ee eee<br>A a a<br>° aT<br>Legend:<br>R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’<br>-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown<br>**----- End of picture text -----**<br>
## bit 31-14 Unimplemented: Read as ‘0’
- bit 13-8 CWINDOW<5:0>: Collision Window bits
- This is a programmable field representing the slot time or collision window during which collisions occur in properly configured networks. Since the collision window starts at the beginning of transmission, the preamble and SFD is included. Its default of 0x37 (55d) corresponds to the count of frame bytes at the end of the window.
- bit 7-4 Unimplemented: Read as ‘0’
- bit 3-0 RETX<3:0>: Retransmission Maximum bits
- This is a programmable field specifying the number of retransmission attempts following a collision before aborting the packet due to excessive collisions. The Standard specifies the maximum number of attempts (attemptLimit) to be OxF (15d). Its default is ‘OxF’.
- Note: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 8-bit accesses are not allowed and are ignored by the hardware.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 553
PIC32MZ W1 and WFI32E01 Family
## seman
|REGISTER 33-28:|EMAC1MAXF: ETHERNET CONTROLLER MAC MAXIMUM FRAME LENGTH|EMAC1MAXF: ETHERNET CONTROLLER MAC MAXIMUM FRAME LENGTH|EMAC1MAXF: ETHERNET CONTROLLER MAC MAXIMUM FRAME LENGTH|
|---|---|---|---|
||REGISTER|||
|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Range | 34/23/15/7 | 30/22/14/6 | 29/21/13/5 |28/20/12/4|||Bit<br>Bit<br>Bit<br>Bit<br> | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0|
|aa<br>a<br>pa SS||eee||
|:||||
|:||||
|Legend:||||
|R = Readable bit||W = Writable bit|U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR||‘1’=Bitisset|‘0’=Bitiscleared<br>x=Bitisunknown|
## bit 31-16 Unimplemented: Read as ‘0’
## bit 15-0 |MACMAXF<15:0>: Maximum Frame Length bits“)
These bits reset to OXO5EE, which represents a maximum receive frame of 1518 octets. An untagged maximum size Ethernet frame is 1518 octets. A tagged frame adds four octets for a total of 1522 octets. If a shorter/longer maximum length restriction is desired, program this 16-bit field.
- Note 1: Ifa proprietary header is allowed, this bit should be adjusted accordingly. For example, if 4-byte headers are prepended to frames, MACMAXF could be set to 1527 octets. This would allow the maximum VLAN tagged frame plus the 4-byte header.
Note: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 8-bit accesses are not allowed and are ignored by the hardware.
renner eee e rereerence eee eee DS70005425A-page 554 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
REGISTER 33-29: EMAC1SUPP: ETHERNET CONTROLLER MAC PHY SUPPORT REGISTER
|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Range | 341/23/15/7 |30/22/14/6|29/21/13/5|28/20/12/4| 27/19/11/3 |26/18/10/2|25/17/9/1|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Range | 341/23/15/7 |30/22/14/6|29/21/13/5|28/20/12/4| 27/19/11/3 |26/18/10/2|25/17/9/1|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Range | 341/23/15/7 |30/22/14/6|29/21/13/5|28/20/12/4| 27/19/11/3 |26/18/10/2|25/17/9/1|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Range | 341/23/15/7 |30/22/14/6|29/21/13/5|28/20/12/4| 27/19/11/3 |26/18/10/2|25/17/9/1|Bit<br>24/16/8/0|
|---|---|---|---|---|
|8|eT|sere sree|||
|Legend:|||||
|R = Readable bit<br>W = Writable bit||U = Unimplemented|bit, read as ‘0’||
|-n = Value|at POR<br>‘1’ = Bit is set|‘0’ = Bit is cleared|x = Bit is|unknown|
|bit 31-12|Unimplemented: Read as ‘0’||||
|bit 14|RESETRMII: Reset RMII Logic bit!)||||
||1 = Reset the MAC RMII module||||
||0 = Normal operation||||
|bit 10-9|Unimplemented: Read as ‘0’||||
|bit 8|SPEEDRMII: RMII Speed bit!)||||
||This bit configures the reduced MII logic for the|current operating speed.|||
||1 = RMI is running at 100 Mbps||||
||0 = RMIl is running at 10 Mbps||||
|bit7-0|Unimplemented:Readas‘0’||||
- Note 1: This bit is only used for the RMII module. 2: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 8-bit accesses are not allowed and are ignored by the hardware.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 555
PIC32MZ W1 and WFI32E01 Family
## seman
REGISTER 33-30: EMAC1TEST: ETHERNET CONTROLLER MAC TEST REGISTER
|Bit<br>Bit<br>Bit<br>Range| 34/23/15/7 |30/22/14/6|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br> |29/21/13/5|28/20/12/4|27/19/11/3 |26/18/10/2<br>25/17/9/1|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br> |29/21/13/5|28/20/12/4|27/19/11/3 |26/18/10/2<br>25/17/9/1|Bit<br>24/16/8/0|
|---|---|---|---|
|we (ee<br>= <br>ee ee <br>oss SE ||= =<br> a a <br>ee|=<br>=<br> a<br>a<br>ES|SS|
|°ee<br>est [recreational |||||
|Legend:||||
|R = Readable bit|W = Writable bit|U = Unimplemented bit, read as ‘0’||
|-n=ValueatPOR|‘1’=Bitisset|‘0’=Bitiscleared<br>x=Bitisunknown||
- bit 31-3. Unimplemented: Read as ‘0’ bit 2 TESTBP: Test Backpressure bit 1 = MAC asserts backpressure on the link. Backpressure causes preamble to be transmitted, raising carrier sense. A transmit packet from the system is sent during backpressure.
- 0 = Normal operation
- bit 1 TESTPAUSE: Test PAUSE bit")
- 1 = MAC control sub-layer inhibits transmissions, just as if a PAUSE receive control frame with a non-zero pause time parameter was received
- 0 = Normal operation
- bitO | SHRTQNTA: Shortcut PAUSE Quanta bit!) 1 = MAC reduces the effective PAUSE Quanta from 64 byte-times to 1 byte-time 0 = Normal operation
- Note 1: This bit is only used for testing purposes. 2: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 8-bit accesses are not allowed and are ignored by the hardware
renner eee e rereerence eee eee DS70005425A-page 556 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## ee
## REGISTER 33-31: EMAC1SA0: ETHERNET CONTROLLER MAC STATION ADDRESS 0 REGISTER
|Bit<br>Bit<br>Range | 31/23/15/7|Bit<br>30/22/14/6|Bit<br>Bit<br>29/21/13/5 | 28/20/12/4|Bit<br>Bit<br>29/21/13/5 | 28/20/12/4|Bit<br>Bit<br>Bit<br>Bit<br> |27/19/11/3 |26/18/10/2 | 25/17/9/1 |24/16/8/0|Bit<br>Bit<br>Bit<br>Bit<br> |27/19/11/3 |26/18/10/2 | 25/17/9/1 |24/16/8/0|
|---|---|---|---|---|---|
|a <br>ee<br>a||a|ea<br>a|||
|:||||||
|:||||||
|Legend:||||P = Programmable bit||
|R = Readable bit||W = Writable bit||U = Unimplemented bit,|read as ‘0’|
|-n=ValueatPOR||‘1’=Bitis|set|‘0’=Bitiscleared|x=Bitisunknown|
## bit 31-16 Unimplemented: Read as ‘0’
- bit 15-8 STNADDR6<7:0>: Station Address Octet 6 bits
These bits hold the sixth transmitted octet of the station address.
- bit 7-0 STNADDRS5<7:0>: Station Address Octet 5 bits These bits hold the fifth transmitted octet of the station address.
- Note 1: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 8-bit accesses are not allowed and are ignored by the hardware.
- 2: This register is loaded at Reset from the factory preprogrammed station address.
## EE,
© 2020 Microchip Technology Inc. Preliminary Data Sheet
DS70005425A-page 557
PIC32MZ W1 and WFI32E01 Family
ee
REGISTER 33-32: EMAC1SA1: ETHERNET CONTROLLER MAC STATION ADDRESS 1 REGISTER
|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Range | 34/23/15/7 | 30/22/14/6 |29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/4|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Range | 34/23/15/7 | 30/22/14/6 |29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/4|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Range | 34/23/15/7 | 30/22/14/6 |29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/4|Bit<br>24/16/8/0|
|---|---|---|---|
|pst SS|See|ee||
|=<br>|||||
|7-0<br>|||||
|Legend:||P = Programmable bit||
|R = Readable bit|W = Writable bit|U = Unimplemented bit, read as ‘0’||
|-n=ValueatPOR|‘1’=Bitisset|‘0’=Bitiscleared<br>x=Bitisunknown||
bit 31-16 Unimplemented: Read as ‘0’
- bit 15-8 STNADDR4<7:0>: Station Address Octet 4 bits These bits hold the fourth transmitted octet of the station address.
- bit 7-0 STNADDR3<7:0>: Station Address Octet 3 bits These bits hold the third transmitted octet of the station address.
- Note 1: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 8-bit accesses are not allowed and are ignored by the hardware.
- 2: This register is loaded at Reset from the factory preprogrammed station address.
ee DS70005425A-page 558 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
REGISTER 33-33: EMAC1SA2: ETHERNET CONTROLLER MAC STATION ADDRESS 2 REGISTER
|Bit<br>Range|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>31/23/15/7 | 30/22/14/6 |29/21/13/5 |28/20/12/4 |27/19/11/3 |26/18/10/2|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>31/23/15/7 | 30/22/14/6 |29/21/13/5 |28/20/12/4 |27/19/11/3 |26/18/10/2|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>31/23/15/7 | 30/22/14/6 |29/21/13/5 |28/20/12/4 |27/19/11/3 |26/18/10/2|Bit<br> | 25/17/9/1|Bit<br> | 24/16/8/0|
|---|---|---|---|---|---|
|:||||||
|:||||||
|Legend:|||P = Programmable bit|||
|R = Readable bit||W = Writable bit|U = Unimplemented bit,|read as ‘0’||
|-n=ValueatPOR||‘1’=Bitisset|‘0’=Bitiscleared|x=Bitisunknown||
- bit 31-16 Reserved: Maintain as ‘0’; ignore read
- bit 15-8 STNADDR2<7:0>: Station Address Octet 2 bits These bits hold the second transmitted octet of the station address.
- bit 7-0 STNADDR1<7:0>: Station Address Octet 1 bits These bits hold the most significant (first transmitted) octet of the station address.
- Note 1: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers). 8-bit accesses are not allowed and are ignored by the hardware.
- 2: This register is loaded at Reset from the factory preprogrammed station address.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 559
PIC32MZ W1 and WFI32E01 Family
DS70005425A-page 560
Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family smn 34.0 ENHANCED CAPACITIVE * Oversampling/threshold support VOLTAGE DIVIDER (CVD) ¢ Provision to enable an interrupt when complete or CONTROLLER when threshold exceeded The PIC32MZ W1 device; contains; a hardware CVD fyingThe fourthedescriptorsexact touchenablelocationthe quickly,user softwarewhile toavoidingidenticontroller, which supports enhanced CVD Self+Mutual the need to scan the entire RX/TX set. For example: measurements. The enhanced CVD controller offDescriptor 1 could be configured to scan all RX inputs loads the CPU by performing CVD scans with together while driving all TX outputs together. The softprogrammable phase timing and oversampling. Also, ware can pre-load the next descriptor to scan the the enhanced CVD _ controller calculates the screen in two halves, and the following descriptors to measurement deltas and detects the touches based on each scan either the left or right halves in two halves. thresholds. While the hardware moves through the descriptors, the Key features of the ENHANCED CVD controller software can follow it and update used descriptors to include: continue the search based on the results of prior scans.
- Self measurement for basic touch detection.
- ¢« AddCap control to optimize sensitivity on systems with small sample capacitors.
- Support for busing of multiple RX inputs and/or TX outputs for detecting touch over larger areas and algorithmically searching for touch location.
- ¢ Four Scan Descriptors control the scan settings to enable SW controlled search algorithms by loading the next scan parameters while one is in progress.
- Oversampling of measurements to increase signal-to-noise ratio.
- ¢ Ability to control sequencing order of RX and TX scanning.
- ¢ Programmable thresholding to limit the data to the CPU to only those which exceed set threshold.
- Supports a maximum of 16 RX/TX channels for touch measurements.
The enhanced CVD controls the ADC core in a simplified mode that supports only the needs of CVD. The enhanced CVD controls the pin functions also. The RX and TX pins connect to a matrix of button electrodes or a touch screen/touch pad electrode grid. The capacitance of these electrodes will be measured to determine a touch or an approach.
Each RX/TX pin is assigned to an RX/TX index via SFRs. Each scan can span multiple RX/TX indexes enabling the user to scan multiple RX inputs in parallel, or drive mulitple TX outputs in parallel. This is useful for doing full-panel touch detection (IE: for wakeup event).
## 34.1 SCAN DESCRIPTORS
The enhanced CVD supports four scan descriptors as part of the register set. Each descriptor indicates:
- RX indexes to be scanned,
- ¢ TX indexes to be driven,
- ¢ Number of RX indexes to scan at one time
- ¢ Number of TX indexes to scan at one time
- ¢ Independent enable for Self (RX-drive) and Self + Mutual modes
- ¢ Channel timing Control
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 561
## PIC32MZ W1 and WFI32E01 Family
Figure 34-1 illustrates a block diagram of the enhanced CVD controller.
**==> picture [440 x 224] intentionally omitted <==**
**----- Start of picture text -----**<br>
FIGURE 34-1: ENHANCED CVD CONTROLLER BLOCK DIAGRAM<br>Enhanced CVD Trigger<br>ADC Results<br>Abt Core Pins with RX Function} | Pins with TX Function<br>~- eee eee “ih ! —_—— — —-Hee<br>EEE EEE ED<br>BEREEEE<br>EERE EEE<br>EERE EE SE<br>See EE<br>BE mt<br>**----- End of picture text -----**<br>
DS70005425A-page 562
Preliminary Data Sheet
© 2020 Microchip Technology Inc.
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## seman
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PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 34-1: CVDCON: CVD CONTROL REGISTER
**==> picture [453 x 622] intentionally omitted <==**
**----- Start of picture text -----**<br>
|||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Bit Range|Bit|Bit|Bit|Bit|Bit|Bit|Bit|Bit|
|31/23/15/7|||30/22/14/6|| 29/21/13/5|| 28/20/12/4|||27/19/11/3|| 26/18/10/2|||25/17/9/1|||24/16/8/0|
|[on|[=||siot_[orner|||sowren|[||—|||sort|||swrric ||
|‘8|sre [==|=|even|rroen|||Frotioe|||
|:|
|°|eT|akseitos|TRESS|
|Legend:|HC|=|Hardware|Cleared|HS|=|Hardware|Set|
|R|=|Readable|bit|W|=|Writable|bit|U|=|Unimplemented|bit,|read|as|‘0’|
|-n|=|Value|at|POR|‘1’|=|Bit|is|set|‘0’|=|Bit|is|cleared|x|=|Bit|is|unknown|
|bit|31|ON:|Enables|the|state|machine|to|scan|enabled|scan|descriptors|upon|next|trigger.|Before|turning|ON|
|from|1’b1|to|1’b0,|the|Scan|Enable|bits|of|all|descriptors|should|be|cleared|and|the|ENHANCED|CVD|
|controller|should|either|be allowed|to|finish|any|scan|in|progress,|or should|be|instructed|to|abort the|scan|
|with|the ABORT|bit.|
|bit|30|Unimplemented:|Read|as|‘0’|
|bit|29|SIDL:|Stop|in|Idle|Mode|bit|
|1|=|CVD|controller|halts|when|device|enters|Idle|mode|
|0|=|CVD|controller|continues|running|in|Idle|mode|
|bit|28|ORDER:|RX/TX|Loop|Order|
|1|=|Scan|all|requested|TX|indexes,|then|increment|RX|index|and|continue|
|0|=|Scan|all|requested|RX|indexes,|then|increment|TX|index|and|continue|
|bit|27|SDWREN:|Scan|Descriptor|Write|Enable|
|1|=|Enables|writes|to|the|scan|descriptors|
|0|=|Prevents|writes|to|the|scan|descriptors|
|bit|26|Unimplemented:|Read|as|‘0’|
|bit|25|ABORT:|
|1|=Abort|the|current|scan|
|0|=|CVD|controller|continues|with|the|current|scan|
|Note:|The|controller|will|move|on|to|the|next|enabled|Scan|Descriptor|if there|is|one,|else|it|will|go|
|idle.|Cleared|by|hardware.|
|bit|24|SWTRIG:|Software|Trigger|control|
|1|=|Starts|scan|manually|
|0|=|Continue|without|the|scan|
|Note:|Cleared|by|hardware.|
|bit|23|THSTR:|Threshold|Store|Mode|
|1|=|Store|only|results|which|exceed|the|programmed|threshold|for|the|Scan|Descriptor|
|0|=|Store|all|results|in|FIFO|
|bit|22-20|Unimplemented:|Read|as|‘0’|
|bit|19|CVDIEN:|Global|Interrupt|Enable|
|1|=|Enables|the|FIFO|and|scan|descriptor|interrupts|
|0|=|Disables|the|FIFO|and|scan|descriptor|interrupts|
|bit|18|FIFOTHIEN:|FIFO|Threshold|Interrupt|Enable|
|1|=|Controller|will|assert|an|interrupt when|the|FIFO|threshold|is|met|
|0|=|Controller|will|not|assert|an|interrupt when|the|FIFO|threshold|is|met|
**----- End of picture text -----**<br>
renner eee e rereerence eee eee DS70005425A-page 566 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
## REGISTER 34-1: CVDCON: CVD CONTROL REGISTER (CONTINUED)
bit 17-8 FIFOTH<9:0>: Threshold for the results FIFO that will cause an interrupt and watermark FIFOWM status bit assertion.
- bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 CLKSEL<1:0>: Clock Select for CVD 00 = pB2_clk 01=FRC 02 =LPRC 03 = REFO1
- bit 3-0 TRIGSEL<3:0>: Selects one of 15 external trigger inputs to start scanning. 0000 = SFR controlled software trigger 0001 = TMR1 event 0010 = TMR2 event 0011 = TMR3 event 0100 = TMR4 event 0101 = TMR5devent 0110 = TMR6 event 0111 = TMR7 event 1000 = Reserved 1001 = Reserved 1010 = PTGO9 1011 =
1111 = Reserved
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 567
PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 34-2: CVDADC: CVD ADC CONFIGURATION REGISTER
|BitRange<br>Bit|Bit<br>Bit|Bit|Bit<br>Bit<br>Bit<br>Bit|
|---|---|---|---|
|31/23/15/7 |30/22/14/6 |29/21/13/5 |28/20/12/4||||27/19/11/3 |26/18/10/2 | 25/17/9/1<br>24/16/8/0|
|po<br>EB|Ee||ee|
|° (eT<br>teen<br>oirrren [<br>setrescio> |||||
|Legend:||||
|R = Readable bit|W = Writable bit||U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR|‘1’=Bitisset||‘0’=Bitiscleared<br>x=Bitisunknown|
|bit|31-4|Unimplemented: Read as ‘0’|
|---|---|---|
|bit|3|DIGEN7: SharedADC (ADC2) Digital Enable bit (Differential Mode Select fromADC con-|
|||troller)|
|||1 =ADC2 is digital enabled|
|||0 =ADC2 is digital disabled|
|bit2|2|DIFFPEN: Control differential mode operation of ANNO|
|||1=ANNO (Differential) enabled|
|||o=ANNO (Differential) disabled|
|bit|1-0|SELRES<1:0>: SharedADC (ADC2) Resolution bits|
|||11 = 12 bits (default)|
|||10 = 10 bits|
|||01 = 8 bits|
|||00 = 6 bits|
|||Note:<br>Changing the resolution oftheADC does not shift the result in the correspondingADCDATAx|
|||register. The result will still occupy 12 bits, with the corresponding lowerunused bits setto ‘0’.|
|||For example, a resolution of 6 bits will result inADCDATAx<5:0> being set to '0', and|
|||ADCDATAx<11:6>holdingtheresult.|
renner eee e rereerence eee eee DS70005425A-page 568 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
## REGISTER 34-3: CVDSTAT: CVD STATUS REGISTER
|Range | 34/23/15/7 | 30/22/14/6 |29/21/13/5 | 28/20/12/4 | 27/19/11/3 |26/18/10/2 | 25/17/9/1|| 24/16/8/0|
|---|---|
|} ta} Seteo-ReoWe PCBFOMT POT<br>TFiFoFuLL| Firowm | FiromT | — | — | — |‘FIFOGNT<oe>__|<br>4g<br>LF RO |<br>Ro | Ro | Ro<br>[| Ro<br>{| Ro [ Ro<br>[| Rt |||
|en<br>ee<br>15:8 [=P spaint |Spaone | soasusy[— |_SD3INT_| SDSD0NE <br>Po | ee | awnso [mmo | awa | vo [runes | ro <br>[=<br>[ soant|sp2n0ne | spasusy | — | sb1nT_| SD1DONE|| SDSBUSY|<br> | no<br> | SDIBUSY||
|Legend:<br>HC = Hardware Cleared<br>HS = Hardware Set||
|R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’||
|-n=ValueatPOR<br>‘1’=Bitisset<br>‘0’=Bitiscleared<br>x=Bitisunknown||
- bit 31 FIFOFULL: The Results FIFO is full. 1 = FIFOis full. 0 = Not full
- bit 30 FIFOWM:
- 1 = FIFO has reached the programmed FIFOTHRESH threshold
- 0 = FIFO has not reached the programmed FIFOTHRESH threshold
- bit 29 FIFOMT:
- 1 = FIFO is empty
- 0 = FIFO is not empty
bit 28-26 Unimplemented: Read as 0
- bit 25-16 FIFOCNT: Results FIFO word count: Indicates the number of words in the Results FIFO. bit 15 Unimplemented: Read as 0 bit 14 SD4INT: 1 = Scan Descriptor 4 has caused an interrupt 0 = Scan Descriptor 4 has not caused an interrupt
- bit 13 SD4DONE: 1 = Scan Descriptor 4 has completed
- 0 = Scan Descriptor 4 has not completed
- bit 12 SD4BUSY: 1 = Scan Descriptor 4 is in progress 0 = Scan Descriptor 4 is not in progress
- bit 11 Unimplemented: Read as 0 bit210 SD3NT: 1 = Scan Descriptor 3 has caused an interrupt 0 = Scan Descriptor 3 has not caused an interrupt
- bit 9 SD3DONE: Core will set this bit if Scan Descriptor 3 has completed at least once. Core will clear this bit upon receiving next trigger for Scan Descriptor 3.
- bit 8 SD3BUSY: 1 = Scan Descriptor 3 is in progress 0 = Scan Descriptor 3 is not in progress
- bit 7 Unimplemented: Read as 0 bit 6 SD2NT: 1 = Scan Descriptor 2 has caused an interrupt 0 = Scan Descriptor 2 has not caused an interrupt
- bit 5 SD2DONE: Core will set this bit if Scan Descriptor 2 has completed at least once. Core will clear this bit upon receiving next trigger for Scan Descriptor 2.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 569
## PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 34-3: CVDSTAT: CVD STATUS REGISTER (CONTINUED)
|bit|4|SD2BUSY:||
|---|---|---|---|
|||1 = Scan Descriptor 2 is in progress||
|||0 = Scan Descriptor 2 is not in progress||
|bit|3|Unimplemented: Read as 0||
|bit|2|SD1NT:||
|||1 = Scan Descriptor 1 has caused an interrupt||
|||0 = Scan Descriptor 1 has not caused an interrupt||
|bit|1|SD1DONE: Core will set this bit if Scan Descriptor|1 has completed at least once. Core will clear this bit|
|||upon receiving next trigger for Scan Descriptor 1.||
|bit|0|SD1BUSY:||
|||1 = Scan Descriptor 1 is in progress||
|||0=ScanDescriptor1isnotinprogress||
renner eee e rereerence eee eee DS70005425A-page 570 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
## REGISTER 34-4: CVDRESOH: CVD RESULTS POS FIFO READ REGISTER
|REGISTER 34-4:<br>CVDRESOH:|REGISTER 34-4:<br>CVDRESOH:|CVD RESULTS POS FIFO READ REGISTER|CVD RESULTS POS FIFO READ REGISTER|
|---|---|---|---|
|Bit<br>Bit<br>Bit<br>Range | 31/23/15/7 | 30/22/14/6||Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br> |29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/41 | 24/16/8/0||
|_<br>EE<br>isg<br>F Uo |<br>ft<br>= [|ee <br>uo<br>=|ee<br>| uo<br>[| =<br>[||ee ee ee<br>oT RT RO<br>| RO TRO<br> = fo<br>Pose|
|Legend:||||
|R = Readable bit||W = Writable bit|U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR||‘1’=Bitisset|‘0’=Bitiscleared<br>X=Bitisunknown|
bit 31-12 Unimplemented: Read as ‘0’
bit11-0 POS<11:0>: The accumulated result of the positive-side measurements Since the controller supports up to 64x oversampling, each polarity can accumulate up to 12 bits.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 571
PIC32MZ W1 and WFI32E01 Family
## seman
|REGISTER 34-5:|CVDRESOL: CVD RESULTS NEG FIFO READ REGISTER|CVDRESOL: CVD RESULTS NEG FIFO READ REGISTER|||
|---|---|---|---|---|
|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Range |31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 |27/19/11/3 | 26/18/10/2|||Bit<br> | 25/17/9/4|Bit<br>24/16/8/0|
|15:8<br>a a<br>Ca<br>|roPe tne | ne fe||pro<br>| RO |<br>| RO |<br>|RO<br> ete fee|||
|Legend:|||||
|R = Readable bit|W = Writable bit|U = Unimplemented bit,|read as ‘0’||
|-n=ValueatPOR|‘1’=Bitisset|‘0’=Bitiscleared|x=Bitisunknown||
bit 31-12 Unimplemented: Read as ‘0’ bit11-0 | NEG<11:0>: The accumulated result of the negative-side measurements Since the controller supports up to 64x oversampling, each polarity can accumulate up to 12 bits.
renner eee e rereerence eee eee DS70005425A-page 572 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
## REGISTER 34-6: CVDRES0OD: CVD RESULTS DESCRIPTOR FIFO READ REGISTER
**==> picture [456 x 178] intentionally omitted <==**
**----- Start of picture text -----**<br>
Bit Range Bit Bit Bit Bit Bit Bit Bit Bit<br>31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0<br>grog FRO RO ROT ROT ROT | ROT RO<br>[TINEA<br>SSCSC~—~— | CSN<br>sie LF RO | Ro [| Ro | Ro | ro [| vo | Ro | Ro |<br>RKINDEXRO>SSSC~‘SC<br>Pp | CTT<br>ig «OE ROT RO | Ro | Ro | ROT Ro TRO RO<br>Ee<br>Legend:<br>R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’<br>-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown<br>**----- End of picture text -----**<br>
bit 31-27 TXINDEX<4:0>: Transmit Index for this result. If the Stride of the Scan Descriptor was more than one, the Transmit Index indicates the first one of the group. bit 26 Unimplemented: Read as ‘0’ bit 25-24 SDNUM: Scan Descriptor Number that generated this result
bit 23-19 RXINDEX<4:0>: Receive Index for this result. If the Stride of the Scan Descriptor was more than one, the Receive Index indicates the first one of the group. bit 18 Unimplemented: Read as ‘0’ bit 17-0 DELTA<17:0>: The delta of the accumulated results of the negative-side and positive-side measurements. Since the controller supports up to 64x oversampling, each polarity can accumulate up to 12 bits. Note: Reading this register increments the FIFO read pointer, destroying the data in the previous two registers for NEG and POS absolute values. If the NEG and POS values are desired, those registers should be read BEFORE this one. If the absolute values are not required, bandwidth can be saved by reading only this descriptor register.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 573
PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 34-7: CVDRxN: CVD RECEIVE INDEX N CONFIGURATION n = 0-3
Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 24/16/8/0 RAN OC—“*~“S*sSCS PORNO SC“C~‘“CS*S*SC~*S a a a PN RAS OOCOC—C“~*S*S*SCSCS Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
- bit 31-30 Unimplemented: Read as ‘0’
bit 29-24 RXAN[4n+3][5:0]: ANx/CVDR channel to use for RX Index 4n+3 bit 23-22 Unimplemented: Read as ‘0’
bit 21-16 RXAN[4n+2][5:0]: ANx/CVDR channel to use for RX Index 4n+2 bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RXAN[4n+1][5:0]: ANx/CVDR channel to use for RX Index 4n+1 bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RXAN[4n+0][5:0]: ANx/CVDR channel to use for RX Index 4n+0
renner eee e rereerence eee eee DS70005425A-page 574 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
|REGISTER 34-8:<br>CVDTXn: CVD TRANSMIT INDEX n CONFIG n = 0-3<br>Bit Range<br>Bit<br>Pan<br>fia<br>|a<br>31/23/15/7<br>|30/22/14/6 |29/21/13/5 |28/20/12/4 | 27/19/11/3 |26/18/10/2 | 25/17/9/1<br>Ne<br>SC~—C~CSCSY|
|---|
|PSN<br>CCSC~“‘~C~*|
|SO<br>CS—C—C“—SCSCSCSY|
|PsTANG<br>50>|
|Legend:|
|R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR<br>‘1’=Bitisset<br>‘0’=Bitiscleared<br>x=Bitisunknown|
bit 31-30 Unimplemented: Read as ‘0’ bit 29-24 TXAN[4n+3][5:0]: ANx/CVDR channel to use for TX Index 4n+3 bit 23-22 Unimplemented: Read as ‘0’ bit21-16 TXAN[4n+2][5:0]: ANx/CVDR channel to use for TX Index 4n+2 bit 15-14. Unimplemented: Read as ‘0’ bit 13-8 TXAN[4n+1][5:0]: ANx/CVDR channel to use for TX Index 4n+1 bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 TXAN[4n+0][5:0]: ANx/CVDR channel to use for TX Index 4n+0
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 575
## PIC32MZ W1 and WFI32E01 Family
## ee
|REGISTER|34-9:|CVDSDnC1:|CVD SCAN DESCRIPTOR n CONTROL 1, n = 0-3|CVD SCAN DESCRIPTOR n CONTROL 1, n = 0-3|CVD SCAN DESCRIPTOR n CONTROL 1, n = 0-3|||
|---|---|---|---|---|---|---|---|
|Bit Range|.<br>;<br>;<br>;<br>;<br>;<br>;<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>31/23/15/7 |30/22/14/6 |29/21/13/5 |28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1||||||Bit<br>24/16/8/0|
|Pog LRM<br>:||T Rwo|[ Rwo [ RWO fT RwO [ RWO fT RwO [ RWO ||||||
|vie<br>:||||||||
|-<br>:||||||||
|-<br>:||||||||
|Legend:||||||||
|R = Readable bit|||W = Writable bit||U = Unimplemented bit, read|as ‘0’||
|-n=ValueatPOR|||‘1’=Bitisset||‘0’=Bitiscleared<br>x=|Bitisunknown||
- bit 31-8 SDnTH<23:0>: Scan Descriptor Threshold
The accumulators are subtracted after all oversampling is completed. The result of that subtraction is compared to this threshold to generate an interrupt and/or store data to the FIFO based on the configuration.
- bit 7-0 SDnOVRSAMP<7:0>: Scan Descriptor Over Sampling Determines the amount of oversampling done on each measurement. 0 = Only one measurement
- 1 = Two measurements accumulated
- 255 = 256 measurements accumulated
## oe
DS70005425A-page 576
Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
## REGISTER 34-10: CVDSDnC2: CVD SCAN DESCRIPTOR n CONTROL 2, n = 0-3
Range | 34/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
- bit 31-30 SDnTXSTRIDE<3:2>: Scan Descriptor TX Index Stride Determines the number of TX Indexes included in a single measurement. 4h0: One TX Index 4’bF: 16TX Indexes
- bit 29-24 SDnTXEND<5:0>: Scan Descriptor TX Index End Determines the last TX index to include in a scan. One the TX index pointer, which is incremented by the SDnTXSTRIDE+1 value, meets or exceeds this value, the TX loop of the scan is complete.
- bit 23-22 SDnRXSTRIDE<3:2>: Scan Descriptor TX Index Stride Determines the number of TX Indexes included in a single measurement. 4h0: One TX Index 4bF: 16TX Indexes
- bit21-16 SDnTXBEG<5:0>: Scan Descriptor TX Index Start Determines the first TX index to include in a scan.
- bit 15-14 SDnRXSTRIDE<3:2>: Scan Descriptor RX Index Stride Determines the number of TX Indexes included in a single measurement. 4h0: One TX Index 4’bF: 16TX Indexes
- bit 13-8 SDnRXEND<5:0>: Scan Descriptor RX Index End Determines the last RX index to include in a scan. One the RX index pointer, which is incremented by the SDnRXSTRIDE+1 value, meets or exceeds this value, the RX loop of the scan is complete.
- bit 7-6 SDnRXSTRIDE<1:0>: Scan Descriptor RX Index Stride Determines the number of RX Indexes included in a single measurement. 4’hO: One RX Index 4VhF: 16 TX Indexes
- bit 5-0 SDnRXBEG<5:0>: Scan Descriptor RX Index Start Determines the first RX index to include in a scan.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 577
## PIC32MZ W1 and WFI32E01 Family seman
|REGISTER 34-11:<br>CVDSDnC3: CVD SCAN DESCRIPTOR n CONTROL 3, n = 0-3|
|---|
|Range<br>31/23/15/7<br>| 30/22/14/6<br>29/21/13/5 |28/20/12/4 | 27/19/11/3 | 26/18/10/2 |25/17/9/1 |24/16/8/0|
|[_SDnENTo] |S «|SS «|SDBUF|SDnINTEN|SDnSELF|SDnMUT|<br>ee a ee<br>a|
|a0|
|° C=<br>ncatimeses><br>—SSSCSCSCSCS|
|Legend:<br>HC = Hardware Cleared<br>HS = Hardware Set|
|R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR<br>‘1’=Bitisset<br>‘0’=Bitiscleared<br>x=Bitisunknown|
bit 31-30 SDnEN<1:0>: Scan Descriptor Enable Mode
00 = Scan Descriptor Disabled
- 01 = Execute Scan Descriptor one time only, then clear the enable.
||01 = Execute Scan Descriptor one time only, then clear the enable.|
|---|---|
||10 = Execute the Scan Descriptor, but keep enabled. Move on to next enabled descriptors.|
||11 = Execute the Scan Descriptor in a loop until a threshold match is detected, then clear the enable and|
||move on to next enabled descriptors.|
|bit 29-28|Unimplemented: Read as ‘0’|
|bit 27|SDnBUF: Scan Descriptor CVD Buffer Enable|
||1 = CVD buffer output used as sharedADC (ADC2) input.|
||0 = CVD buffer output not used as shared ADC (ADC2) input|
|bit 26|SDnINTEN: Scan Descriptor Interrupt Enable|
||1 = Scan Descriptor creates an interrupt if the accumulator threshold is met|
||0 = Scan descriptor does not create an interrupt|
|bit 25|SDnSELF: Scan Descriptor Mutual Mode|
||1 = Self Measurement Mode; RX outputs are part ofCVD measurement and are driven|
||0 = No Self Measurement; RX outputs are not part ofCVD measurements|
|bit 24|SDnMUT: Scan Descriptor Mutual Mode|
||1 = Mutual Measurement Mode; TX outputs are part ofCVD measurement and are driven|
||0 = No Mutual Measurement Mode; TX outputs are not part ofCVD measurements|
|bit 23-20|Unimplemented: Read as ‘0’|
|bit 19|CVDEN: Capacitive Voltage Division Enable bit|
||1 = CVD operation is enabled|
||0 = CVD operation is disabled|
|bit 18-16|CVDCPL<2:0>: Capacitor Voltage Divider (CVD) Setting bits|
||111 =7%* 2.5 pF = 17.5 pF|
||110=6*<br>2.5 pF = 15 pF|
||101 =5* 2.5 pF = 12.5 pF|
||100=4*<br>2.5 pF = 10 pF|
||011 =3%*2.5 pF =7.5 pF|
||010=2*2.5<br>pF=5 pF|
||001=1*2.5 pF =2.5 pF|
||000=0*2.5<br>pF =0 pF|
|bit 15|Unimplemented: Read as ‘0’|
|bit14-8|SDnACQTIME<6:0>: Scan DescriptorAcquire Time|
||Time for which CVD waits forADC voltage to settle.|
|bit7|Unimplemented:Readas‘0’|
renner eee e rereerence eee eee DS70005425A-page 578 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
REGISTER 34-11: CVDSDnC3: CVD SCAN DESCRIPTOR n CONTROL 3, n = 0-3 (CONTINUED) bit 6-0 SDnCHGTIME<6:0>: Scan Descriptor Charge Time
Time for which CVD remains in the charging state for internal/external capacitors and for TX outputs.
© 2020 Microchip Technology Inc.
Preliminary Data Sheet
DS70005425A-page 579
PIC32MZ W1 and WFI32E01 Family
seman
## REGISTER 34-12: CVDSDnT2: CVD SCAN DESCRIPTOR n TIME 2, n = 1-4
|Range | 31/23/15/7 |30/22/14/6 |29/21/13/5 | 28/20/12/4 | 27/19/11/3 |26/18/10/2 | 25/17/9/1<br>24/16/8/0|Range | 31/23/15/7 |30/22/14/6 |29/21/13/5 | 28/20/12/4 | 27/19/11/3 |26/18/10/2 | 25/17/9/1<br>24/16/8/0|
|---|---|
||=frre<br>—“—sS™SsSCSCS|
||=f<br>CO™~™C*C‘SSDQWRTIMSSS|
||=<br>ncn<br>SO~—~—CSCSCSY|
||=f<br>OC™~™C*C*SSDNGONTIMESEG>CS|
|Legend:||
|R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’||
|-n = Value at POR<br>‘1’ = Bit is set<br>‘0’ = Bit is cleared<br>x = Bit is unknown||
|bit 31|Unimplemented: Read as ‘0’|
|bit 30-24|SDnPOLTIME<6:0>: Scan Descriptor Polarity Time|
||Controls the number of cycles the state machine waits in the POLARITY state before taking the second|
||polarity measurement ofan RX/TX pair|
|bit 23|Unimplemented: Read as ‘0’|
|bit 22-16|SDnOVRTIME<6:0>: Scan Descriptor Oversample Time|
||Controls the number of cycles the state machine waits in the OVERSAMP state before taking the next|
||oversampling measurement ofan RX/TX pair.|
|bit 15|Unimplemented: Read as ‘0’|
|bit 14-8|SDnCHNTIME<6:0>: Scan Descriptor Channel Time|
||Controls the number of cycles the state machine waits in the RXCHAN orTXCHAN state before moving to|
||the next RX/TX pair.|
|bit 7|Unimplemented: Read as ‘0’|
|bit 6-0|SDnCONTIME<6:0>: Scan Descriptor Charge Time|
||Controls the number of cycles the state machine waits in the CONVERT state waiting fortheADC sample|
||data. It must be ensured that theADC will assert End-Of-Convert (EOC) before the CONVERT state timer|
||expires.|
renner eee e rereerence eee eee DS70005425A-page 580 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
© 2020 Microchip Technology Inc.
Preliminary Data Sheet
DS70005425A-page 581
PIC32MZ W1 and WFI32E01 Family
DS70005425A-page 582
Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
## 35.0 POWER MANAGEMENT UNIT (PMU)
This section describes PMU features of the PIC32MZ W1 devices. These devices offer various method to monitor and program the MLDO and provides unified control to various LDOs present in the device.
Key features of PMU include:
- « Provides lO mapped SPI interface for programming MLDO.
- Controls LDOs of the peripherals and voltage reference PLL regulator output voltage for optimal performance for various devices operating mode.
- « Provides register locking feature to avoid accidental writes to the critical PMU control registers.
- ¢ Provides WOFF mode and WCM retention mode to support Power-Saving modes.
- ¢ Maintain Wi-Fi Context Memory (WCM) and provides memory mapped CPU access over fast peripheral bus.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 583
## seman
**==> picture [458 x 671] intentionally omitted <==**
**----- Start of picture text -----**<br>
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PIC32MZ W1 and WFI32E01 Family
## smn
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**----- Start of picture text -----**<br>
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PIC32MZ W1 and WFI32E01 Family
—ne)
## REGISTER 35-1: PMUSPICTRL: PMU SPI CONTROL REGISTER
Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 26/18/10/2 25/17/9/1 | 24/16/8/0 oe PRMMECDPRWLHEO Tua [vo | uo | uo} v0 | Rima | [at per [erst[ol Legend: HC = Hardware Set HS = Hardware Cleared L=Lockable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- bit 31 SPIRST: PMU SPI Register Chain Reset bit 1 = Asserts Reset to PMU module which in turn resets the SPI registers. Automatically cleared in hardware. 0 = No effect
Note: This bit must be enabled only when PMUSPISTATUS.SPIRDY = 1. bit 30 PMUCRST: PMU Controller Soft Reset bit 1 =Asserts Reset to PMU controller SPI FSM. Automatically cleared in hardware. 0 = No effect Note: This bit must be enabled only when PMUSPISTATUS.SPIRDY = 1. bit 29-25 Unimplemented: Read as ‘0’ bit 24 CMD: SPI Command bit 1 = SPI read command
0 = SPI write command
bit 23-16 SPIADDR<7:0>: 8-bit SPI Address bit
bit 5-0 SPIWDATA<15:0>: 16-bit SPI Write Data bit
ES DS70005425A-page 586 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family smn
**==> picture [458 x 203] intentionally omitted <==**
**----- Start of picture text -----**<br>
REGISTER 35-2: PMUSPISTAT: PMU SPI CONTROL REGISTER<br>Bit Bit Bit Bit Bit Bit Bit Bit Bit<br>Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0<br>og (| ee eee<br>pave Se TS | ee ee<br>pee PE eee eH a ee<br>re~0 ee ee ee eeee|R-0<br>Legend:<br>R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’<br>-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown<br>**----- End of picture text -----**<br>
- bit 31-16 SPIRDATA<15:0>: SPI Read Data. Valid only if SPIRDY = 1. bit 15-8 ©SPIRADDR<7:0>: SPI Read Address. Valid only if PMUSPICTRL.CMD = 0 and SPIRDY = 1.
- bit 7 SPIRDY: SPI Ready Flag
- 1 = SPI transaction is complete or PMU Controller is ready for next SP! command.
- 0 = SPI transaction in progress or PMU controller is busy.
- Note: Awrite to PMUSPICTRL register is ignored if SPIRDY = 0. Software must confirm SPRDY = 1 before posting a read or write transaction to the PMU via a write to PMUSPICTRL register.
- bit 6-1 Unimplemented: 0
bit 0 SPIERR: SPI Command Terminated With Error bit
- 1 = SPI transaction is terminated
- 0 = No termination and next command can be applied.
- Note 1: SPIERR status is ignored if SPIRDY = 0. Software must confirm SPIERR = 0 before acknowledging command completion or commencing next transaction.
- 2: Awrite to PMUSPICTRL register is ignored if SPIERR = 1. Software must confirm SPIERR = 0 before posting a read or write transaction to the PMU via a write to PAUSPICTRL register.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 587
PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 35-3: PMUCLKCTRL: PMU CLOCK CONTROL REGISTER
|Bit<br>Bit|Bit|Bit|Bit<br>Bit<br>Bit||Bit<br>Bit|
|---|---|---|---|---|---|
|Range<br>31/23/15/7|30/22/14/6 | 29/21/13/5 | 28/20/12/4 |27/19/11/3 |26/18/10/2||||25/17/9/1 |24/16/8/0||
|3128<br>“|<br>wemret||wupoorF ||=|| =<br>[| = | =|||= | = ||
|“ ESE|ES||eeeee|||
|anO||||||
|:||||||
|Legend:||||||
|R = Readable bit|W = Writable bit||U = Unimplemented bit, read as ‘0’|||
|-n=ValueatPOR|‘1’=Bitisset||‘0’=Bitiscleared<br>L=Lockablebit|||
- bit 31 WCMRET: Wi-Fi Context Memory Retention Mode bit 1 = WCM is kept in Retention mode in Sleep mode 0 = WCM in Normal mode
- bit 30 WLDOOFF: Wi-Fi LDO Control bit 1 = WLDO is turned OFF in Sleep mode 0 = WLDO is kept ON in Sleep mode
- bit 29-16 Unimplemented: Read as ‘0’ bit 15-8 Unimplemented: Read as ‘0’ bit 7-6 SPISRC<1:0>: SPI Clock Selection bit bit 5-0 SPICLKDIV<5:0>: SPI Clock Divider bit n = SPI clock = SPISRC clock/n -- default = 0x02 1 = Invalid (functionality is not guaranteed)
- 0 = Clock disabled (if programmed 0 then SPIRDY forced to 0 to defer the CPU from posting SPI transaction.
Note 1: Maximum SPI clock = System Clock / 2 but capped at 2OMHz gated by PMU SPI speed.
renner eee e rereerence eee eee DS70005425A-page 588 Preliminary Data Sheet © 2020 Microchip Technology Inc.
——
PIC32MZ W1 and WFI32E01 Family
REGISTER 35-4: PMUMODECTRL(N): PMU MODE CONTROL REGISTER, WHERE N =1 TO 4
**==> picture [456 x 424] intentionally omitted <==**
**----- Start of picture text -----**<br>
||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Range|31/23/15/7|30/22/14/6|| 29/21/13/5|||28/20/12/4|| 27/19/11/3 | 26/18/10/2|| 25/17/9/1|| 24/16/8/0|
|oe Le|eae [vee|RO|||Reo|| RO ||RO|
|[00|ee|a|ee|
|pa|SeEy|
|oe||e|ee|
|aec|
|Legend:|
|R|=|Readable|bit|W|=|Writable|bit|U|=|Unimplemented|bit,|read|as|‘0’|
|-n|=|Value|at|POR|‘1’|=|Bit|is|set|‘0’|=|Bit|is|cleared|L|=|Lockable|bit|
|bit|31|Unimplemented:|Read|as|‘0’|
|bit|30|MLDOEN:|MLDO|Enable|Register|bit|
|1|=|MLDO|enabled|
|0|=|MLDO|disabled|
|Note:|This|bit|is|only|writable|when|CFGCONO.PMULOCK|=|0.|
|bit|29|Unimplemented:|Read|as|‘0’|
|bit|28-24|VREG1CTRL<4:0>:|VREG1|Output Voltage|Control|bit|
|Note:|This|field|is|only writable|when|CFGCONO.PMULOCK|=|0.|
|bit|23-21|Unimplemented:|Read|as|‘0|
|bit|20-16|VREG1CTRL<4:0>:|VREG2|Output|Voltage|Control|bit|
|Note:|This|field|is|only|writable|when|CFGCONO.PMULOCK|=|0.|
|bit|15-13|Unimplemented:|Read|as|‘0|
|bit|12-8|VREG1CTRL<4:0>:|VREG3|Output|Voltage|Control|bit|
|Note:|This|field|is|only writable|when|CFGCONO.PMULOCK|=|0.|
|bit|7-5|Unimplemented:|Read|as|‘0|
|bit|4-0|VREG1CTRL<4:0>:|VREG4|Output|Voltage|Control|bit|
|Note:|This|field|is|only writable|when|CFGCONO.PMULOCK|=|0.|
**----- End of picture text -----**<br>
SS © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 589
PIC32MZ W1 and WFI32E01 Family
seman
## REGISTER 35-5: PMUOVERCTRL: PMU OVERRIDE CONTROL REGISTER
|Bit<br>Bit|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit|
|---|---|
|Range<br>31/23/15/7|30/22/14/6 | 29/21/13/5 | 28/20/12/4 |27/19/11/3 |26/18/10/2 |25/17/9/1 |24/16/8/0|
|31:24a<br>i<br>ee<br>ee<br>23:16 SN<br>ee<br>ee eee eee||
|mp<br>=|T= T= T= T= T= T- 7-|
|ne||
|Legend:||
|R = Readable bit|W = Writable bit<br>U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR|‘1’=Bitisset<br>‘0’=Bitiscleared<br>L=Lockablebit|
- bit 31-23 Unimplemented: Read as ‘0’
bit 22 PHWC: Power-up Hardware Control Enable 1 = Enabled 0 = Disabled
bit 21-0 Unimplemented: Read as ‘0’
renner eee e rereerence eee eee DS70005425A-page 590 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
## REGISTER 35-6: PMUCMODE: PMU CURRENT MODE REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0 Tree | ioo || emt|e| uo |eeRo | ro | ro | RO | RO | [= [emoen [= ovrctocrnteo 23:16 pus [uo | ue | Ro | a SO P oro | RO | RO | RO 68 a | Ro | Ro | RO | RO a a a ee ~0 eeee | Ro | Ro | RO | RO Se a a Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘7 = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
- bit 31 Unimplemented: Read as ‘0’ bit 30 CMLDOEN: MLDO Enable Status Register bit 1 = MLDO enabled 0 = MLDO disabled
- bit 29 Unimplemented: Read as ‘0’
- bit 28-24 CVREG1OCTRL<4:0>: VREG1 output voltage control status
- bit 23-21 Unimplemented: Read as ‘0’
- bit 20-15 CVREG2OCTRL<4:0>: VREG2 output voltage control status
- bit 15-13 Unimplemented: Read as ‘0’
- bit12-8 CVREG3O0CTRL<4:0>: VREG3 output voltage control status
- bit 7-5 Unimplemented: Read as ‘0’
- bit 4-0 CVREG40CTRL<4:0>: VREG4 output voltage control status
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 591
PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 35-7: PMUSTATUS: PMU STATUS REGISTER
|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit|
|---|
|Range | 31/23/15/7 | 30/22/14/6 |29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1<br>24/16/8/0|
|31:24 a<br>re i<br>eeee<br>Fase [eefee ee fee fefeefe<br>23:16 a i ee<br>ne [ee fe fe fefeeee<br>15:8 a a<br>ee<br>Fue [uo [ro [ vo | uo | vo | uo | vo<br>raee<br>ee ee ee ee|
|Legend:|
|R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR<br>‘7’=Bitisset<br>‘0’=Bitiscleared<br>x=Bitisunknown|
## bit 31-6 | Unimplemented: Read as ‘0’
bit 5 WCMRM: WCM has entered or begin to enter the retention mode. Accesses are blocked. 1 = WCM in Retention mode or beginning to enter the retention mode. Accesses are blocked. 0 = WCM out of Retention mode and can be accessed.
bit 4-0 Unimplemented: Read as ‘0’
renner eee e rereerence eee eee DS70005425A-page 592 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
REGISTER 35-8: PMUSEQ(n): PMU SEQUENCE REGISTER
|Bit|Bit|Bit|Bit|Bit|Bit|Bit|Bit|Bit|
|---|---|---|---|---|---|---|---|---|
|Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 |27/19/11/3 | 26/18/10/2|||||||| 25/17/9/1|24/16/8/0|
|31:24|||||||||
|:|||||||||
|15:8|||||||||
|7:0|||||||||
|Legend:|||||||||
|R = Readable bit||W|= Writable bit|U|= Unimplemented bit, read as ‘0’||||
|cfg=ConfigurableatReset||‘1’|=Bitisset|‘0’=Bitis||cleared|||
|bit|31-16|SPIDATA<15:0>: SPI Data|
|---|---|---|
|||SPI read data compare ifCMD = 1|
|||SPI write data if CMD = 0|
|bit|15-8|SPIADDR<7:0>: SPI Address|
|||SPI read address if CMD = 1|
|||SPI write address ifCMD = 0|
|bit|7|CMD: SPI Command bit|
|||1 = SPI read command|
|||0 = SPI write command|
|bit|6|CMPBVAL: Command to set the compare bit value in read sequence|
|||1 = Compare for bit value 1. Bit value of zero in SPIDATA is ignored for comparison.|
|||0 = Compare for bit value 0. Bit value ofone in SPIDATA is ignored for comparison|
|bit|5-0|DELAY<5:0>:Delay|
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 593
PIC32MZ W1 and WFI32E01 Family
seman
## REGISTER 35-9: PMUCFG: PMU CONFIGURATION REGISTER
|Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit|
|---|
|Range | 31/23/15/7 |30/22/14/6 |29/21/13/5 | 28/20/12/4 |27/19/11/3 | 26/18/10/2<br>25/17/9/1<br>24/16/8/0|
|enOO|
|SS SS<br>ee<br>ee ee<br>eee|
|“<br>Ee ee ee SSS|
|7:0SS|
|Legend:|
|R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’|
|cfg=ConfigurableatReset<br>‘1’=Bitisset<br>‘0’=Bitiscleared|
bit 31-7 Unimplemented: Read as ‘0’
bit 5-0 DELAY<5:0>: Delay
renner eee e rereerence eee eee DS70005425A-page 594 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
REGISTER 35-10: PMUWCMCMD: PMU WI-FI CONTEXT MEMORY COMMAND REGISTER
|‘<br>Bit<br>Bit<br>pes|‘<br>,<br>Bit<br>Bit<br>Bit<br>30/22/14/6|29/21/13/5 arka|‘<br>,<br>Bit<br>Bit<br>Bit<br>30/22/14/6|29/21/13/5 arka|Bit<br>‘<br>Bit<br> ako 26/18/10/2|;<br>Bit<br>25/17/9/1|:<br>Bit<br>24/16/8/0|
|---|---|---|---|---|---|
|*<br>[wove[ew|[ew [=<br>wewroy[==|||f=|=|
|23:16 es||||||
|i<br>a|nn|||||
|7:0||||||
|Legend:||||||
|R = Readable bit|W = Writable bit||U = Unimplemented bit, read as ‘0’|||
|-n=ValueatPOR|‘1’=Bitisset||‘0’=Bitiscleared|x=Bitisunknown||
- bit 31 MODE: PMU WCM Operating Mode 0 = Direct addressing. The PMU memory is accessed using memory mapped address PMUWCM address space over Fast PB1 at System Clock. The PMUWCMCMD.WCMCLKDIV is ignored. 1 = Indirect addressing. The PMU memory is accessed using PMUCWCMD, PMUWCMDATA, and PMUWCMRDDATA registers. (Low Power mode)
- bit 30 CMD: PMU WCM Command bit
- 1 = WCM read command (using PMUWCMCMD.WCMADDR, PMUWCMRDDATA registers) 0 = WCM write command (using PAUWCMCMD.WCMADDR, PMUWCMWRDATA registers)
- bit 29 Unimplemented: Read as ‘0’ bit 28 WCMRDY: PMU WCM Ready Flag 1 = PMU WCM transaction is complete or PMU WCM is ready for next WCM command. 0 = PMU WCM transaction in progress or WCM is busy
- bit 27-19 Unimplemented: Read as ‘0’
bit 18-16 WCMCLKDIV: WCM Clock Divider WCMCLK = SYS_CLK/2emelkdiv
- bit 15-11. Unimplemented: Read as ‘0’ bit 10-0 WCMADDR<10:0>: PMU WCM Address in Indirect Addressing Mode
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 595
PIC32MZ W1 and WFI32E01 Family
ee
**==> picture [451 x 203] intentionally omitted <==**
**----- Start of picture text -----**<br>
REGISTER 35-11: PMUWCMWDATA: PMU WI-FI CONTEXT MEMORY WRITE REGISTER<br>Bit Bit Bit Bit Bit Bit Bit Bit Bit<br>Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0<br>31:24<br>23:16<br>15:8<br>7:0<br>Legend:<br>R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’<br>-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown<br>**----- End of picture text -----**<br>
bit31-0 WDATA<31:0>: PMU WCM Write Data
ee DS70005425A-page 596 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
ee
## REGISTER 35-12: PMUWCMRDATA: PMU WI-FI CONTEXT MEMORY READ REGISTER
|Bit|Bit|Bit|Bit|Bit||Bit|Bit|Bit|Bit|
|---|---|---|---|---|---|---|---|---|---|
|Range |31/23/15/7 | 30/22/14/6 |29/21/13/5 | 28/20/12/4|||||| 27/19/11/3 |26/18/10/2 ||||25/17/9/1|24/16/8/0|
|31:24||||||||||
|:||||||||||
|15:8||||||||||
|7:0||||||||||
|Legend:||||||||||
|R = Readable bit||W|= Writable bit||U|= Unimplemented bit, read as ‘0’||||
|-n=ValueatPOR||‘1’|=Bitisset||‘0’|=Bitiscleared|x|=Bitisunknown||
bit31-0 RDATA<31:0>: PMU WCM Read Data
ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 597
PIC32MZ W1 and WFI32E01 Family
DS70005425A-page 598
Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family smn 36.0 POWER-SAVING FEATURES * There can be a wake-up delay based on the Thiis section—describesby power-saving—features eefor if the . oscillator5h Selection : methodsPIC32MZ andW1 modesdevices.thatTheseallow devicesthe userofferto balancevarious oog naleee : aw eee. emer. endE power consumption with device performance. In all of * BOR circuit remains operative during Sleep mode the methods and modes described in this section, ¢ WDT, if enabled, is not automatically cleared prior to power-saving is controlled by software. entering Sleep mode * Some peripherals can continue to operate at limited 36.1 Power-Saving with CPU Running functionality in Sleep mode. These peripherals When the CPU :is running,; power consumption; can be signal,includeWDT,I/O pins ADC,thatUARTdetect anda changeperipheralsin thethatinputuse controlled by reducing the CPU clock frequency, an external clock input or the internal LPRC lowering the speed of PBCLK6, or selecting a lower oscillator (for example, RTCC, Timer1 and Input power clock source (LPRC or SOSC). Capture). In addition, the Peripheral Bus Scaling mode is available ¢ I/O pins continue to sink or source current in the for each peripheral bus where peripherals are clocked at same manner as they do when the device is not in reduced speed by selecting a higher divider for the Sleep mode associated PBCLKx, or by selectively disabling the clock The processor will exit, or wake-up, from sleep on one completely. of the following events: 36.1.1 Wi-Fi POWER-SAVE MODE WITH * On any interrupt from an enabled source that is MCU IN RUN MODE operating in Sleep mode. The interrupt priority must . ; ; Wi-Fi be greater than the current CPU priority. W1 device.subsystemWi-Fi subsystemis one of thehasperipheral Sleep modeof PIC32MZcontroller * On any form. of device Reset (SMC) module to control Wi-Fi low-power states and * Ona WDT ane-oe modes (WSM and WDS). Entry into WOFF mode is * Wake on Wi-Fi data packet controlled outside of Wi-Fi subsystem. If the interrupt priority is lower than or equal to the When the CPU is running, Wi-Fi Sleep Mode (WSM) current priority, the CPU will remain halted, but the and Wi-Fi Deep Sleep Mode (WDS) can be enable to peripheral bus clocks will start running and the device reduce device the power consumption. will enter into Idle mode. TABLE 36-1: WI-Fl POWER-SAVE MODE The device enters Dream mode when the DRMEN bit WITH MCU IN RUN MODE (OSCCON<23>) and SLPEN bit (OSCCON<4>) are CPU State MCU Mode Wi-Fi—_ PowerMode Save setDreamand modea WAIT:includesinstructionthe followingis executed.; characteristics:a (Asynchronous) ¢ While entering Sleep mode, CRU monitors the piRUN )CDACCOCOOCTRUN DMA transfer status.us. If anyar DMAtransaction: is in progress, CPU will enter idle mode until the DMA transfer is complete. « When the CPU is in Sleep mode, and an interrupt 36.2. Power-Saving: with. CPU Halted triggersuntil the DMA,DMA transferthen CPUis complete.enters idleOnmodecomple-again Peripherals and the CPU can be Halted or disabled to tion, CPU switches back to Sleep mode. (In this further reduce power consumption. case interrupt priority is high enough to trigger a DMA but not to wake-up the core). 36.2.1 SLEEP MODE Sleep mode has the lowest power consumption of the device power-saving operating modes. The CPU and most peripherals are halted and the associated clocks are disabled. Select peripherals can continue to operate in Sleep mode and can be used to wake the device from sleep. See the individual peripheral module sections for descriptions of behavior in Sleep mode. The device enters Sleep mode when the SLPEN bit (OSCCON<4>) is set and a WAIT instruction is executed. Sleep mode includes the following characteristics: reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 599
PIC32MZ W1 and WFI32E01 Family seman 36.2.1.1 Wi-Fi Power-Save Mode with MCU 36.3 Wi-Fi Power Save Modes in Sleep/DreamP Mode Wi-Fi Sleep Mode Controller (SMC) will take over the Sleep/Dream mode, device can be configured with trols once WDS/WSM mode is triggered.SMC will autobelow Wi-Fi Power mode to reduce the power conmatically periodically switch between Run, Sleep and sumption. Snooze states in Sleep modes. All the wait times TABLE 36-2: WI-FI POWER-SAVE MODE related to Sleep and Snooze states are programmable. WITH MCU IN SLEEP/DREAM In PIC32MZ W1 Wi-Fi subsystem share CPU with MCU MODE therefore Wi-Fi Run mode can't be complete until MCU sow | BE Wi-Fi@ Power- | Wi-Fi® Powerisin Run mode. The Wi-Fi Run mode will force the MCU State | Mode Save Mode Save Mode to be in Run mode.For intermediate state Snooze, CPU _ (Synchronous) | (Asynchronous) involvementFi packets. is not required to process the incoming WiDream Synchronous mode: MCU sleep entry force the Wi-Fi wor (SMC) into Sleep mode and vice-versa. The MCU sleep exit force the Wi-Fi (SMC) to exit and vice-versa. 36.2.2 IDLE MODE Asynchronous mode: Entry into Sleep mode for Wi-Fi In Idle mode, the CPU is halted; however, all clocks are (ONO) carte intapemiont ite MEH Siap mone : : : - entry. The MCU wakeup (non Wi-Fi) can be indepenstill enabled. This allows peripherals to continue to ee . . operate. Peripherals: can be satindividually configured: to dent of. the Wi-Fi poweriesave modes if configured Halt when entering. Idle by setting; theirP respective: SIDL accordingly.: However,. Wi-Fi (SMC) wakeup to Run . * : mode will force MCU into Run mode. bit. latency, when exiting Idle mode, is very low due to the CPU oscillator source remaining active. MCU sleep entry forces Wi-Fi (SMC) into Sleep if not The device: enters Idle mode when the SLPEN bit; already in Sleep: mode but not true vice versa. Wi-Fi; (OSCCON<4>) is clear and a WAIT instruction is aes fs Gees — nS eae re executed. in Run mode but not true vice versa. The processor: will. wake or exit from Idle mode on the Lalas (Sue) ewer eave Ieee Steet Hass) nes following[events:] the following internal states: * On any interrupt event for which the interrupt source ° Runstates ; ; is enabled. The priority of the interrupt event must - Wi-Fi subsystem can transmit or receive any be greater than the current priority of the CPU. If the of Wi-Fi packets. (Both TX and RX are active) priority of the interrupt event is lower than or equal * Sleep state: to current priority of the CPU, the CPU will remain - Wi-Fi subsystem cannot transmit or receive halted and the device will remain in Idle mode. any of Wi-Fi Wi-Fi packets.(Both TX TX and RX are
- Wi-Fi subsystem cannot transmit or receive any of Wi-Fi Wi-Fi packets.(Both TX TX and RX are inactive)
- On any form of device Reset
- ¢ Ona WDT time-out interrupt
- Snooze state:
- ¢ Wake on Wi-Fi data packet - Snooze is a transient state, the Wi-Fi subsystem will transition into and out of while in
- 36.2.2.1 Wi-Fi Power-Save Mode with MCU either WSM or WDS Mode.TX is inactive and in IDLE Mode RX is active.
- When the CPU is in halted state and MCU is in the idle - Entering/Existing to snooze state is depenstate, device can be configured with below Wi-Fi power dent on the sleep duration or wakeup for mode to reduce the power consumption. TBTT configuration. 36.3.1 WSM: Wi-Fi SLEEP MODE
- TABLE 36-3: Wit CU IN ae MODE. + Faster recovery from the Sleep mode « WSM can put Wi-Fi (SMC) to sleep independently
- CPU | MCU Wi-Fi Power Wi-Fi Power without: putting MCU into Sleep mode_ State | Mode Save Mode Save Mode * During the WSM-sleep: state,. the RF is in Sleep (Synchronous) | (Asynchronous) mode, POSC is ON, RF internal LDOs, PLL and * RAM and Wi-Fi register contents are retained * On wakeup, CPU will continue execution from the next instruction at which it went to sleep
- ¢« Wakeup source from WSM:
- renner eee e rereerence eee eee DS70005425A-page 600 Preliminary Data Sheet © 2020 Microchip Technology Inc.
- PIC32MZ W1 and WFI32E01 Family
- smn - Wake on WSM sleep duration complete 36.3.3 WOFF: Wi-Fi POWER-OFF MODE - When Wi-Fi data is available from access * WOFF mode where the complete Wi-Fi point sub-system power is shut off and all the configu-
- - On user request, MCU can trigger exist of ration registers and memory contents are lost. Wi-Fi (SMC) Sleep mode * WOFF can use WCM memory before triggering
- * Customer need to use Software User Guide API WOFF mode for retained any context that needs to enable WSM mode. to be retained. oan ce
- 36.3.2 * Re-initialization of Wi-Fi subsystem required in WDS: Wi-Fi DEEP SLEEP MODE case data are not retained in the WCM memory.
- * Lowest power consuming Sleep state and favor* On Wakeup, CPU will continue execution from the able for longer sleep duration next instruction at which it went to sleep.
- * The RF is powered down completely including pri* Wakeup source from WOFF: mary oscillator (POSC), RF internal LDOs, PLL - There is no wakeup source for WOFF, softane TRA ene ware has to reinitialize Wi-Fi subsystem.
- * If primary oscillator has any system peripheral * The device:enters WORE mode when the request apart from Wi-Fi (SMC) than device will WLDOOFF bit (PMUCLKCTRL<30>) is set. always enter into WSM even if system request WDS mode. é F
- * SMC can exist in either WDS Sleep state or 36.4 PeripheralP Module Disable Snooze state The Peripheral Module Disable (PMD) registers
- * WDS can put SMC to sleep independently without provide a method to disable a peripheral module by putting system into Sleep mode stopping all clock sources supplied to that module.
- ¢« RAM and Wi-Fi register contents are retained Sane a ana IS anor the appropriate ¢ On Wakeup, CPU will continue execution from the Se yee eae ae nee ae eee next :instruction. at which1it went to sleep consumption. . state. The . control and status. registers associated with the peripheral are also disabled, so
- * Wakeup source from WDS: writes to those registers do not have effect and read - Wake on WSM sleep duration complete values are invalid. - When Wi-Fi data is available from access To disable a peripheral, the associated PMDx bit must point be set to ‘1’. To enable a peripheral, the associated
- - On user request, MCU can trigger exist of PMDx bit must be cleared (default). See Table 36-1 for Wi-Fi (SMC) Sleep mode more information.
- iito enableigWSMAamode. Note: Disablingui a peripheral module: while: it’s ON bit is set, may result in undefined behavior. The ON bit for the associated peripheral module must be cleared prior to disable a module via the PMDx bits.
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TABLE 36-1: PERIPHERAL MODULE DISABLE BITS AND LOCATIONS<br>Peripheral PMDx Bit Name Register Name and Bit Location<br>ADC SARO ADCSAROMD PMD1<0><br>PLDV PLVD1MD PMD1<4><br>Shared ADC SAR ADCSARSHRMD PMD1<7><br>RTCC RTCC1MD PMD1<16><br>Asymmetric crypto BA414MD PMD1<23><br>Crypto CRYPT1MD PMD1<24><br>Random Number Generator RNG1MD PMD1<26><br>reer reer rereeee eee ee<br>© 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 601<br>**----- End of picture text -----**<br>
PIC32MZ W1 and WFI32E01 Family
SSS
TABLE 36-1: PERIPHERAL MODULE DISABLE BITS AND LOCATIONS (CONTINUED)
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PIC32MZ W1 and WFI32E01 Family
ee
REGISTER 36-4: PMD1: PERIPHERAL MODULE DISABLE 1 REGISTER
|Bit|Bit<br>Bit|Bit||Bit|Bit|Bit|Bit|Bit|
|---|---|---|---|---|---|---|---|---|
|Range|31/23/15/7<br>30/22/14/6 |29/21/13/5 |28/20/12/4 | 27/19/11/3 |26/18/10/2 |25/17/9/1 ||||||||24/16/8/0|
|SF<br>sain [enti<br>erveri ||||||||||
|e|eaatewo[|<br>mat [tect |||||||||
|°|[voor|||||[cin|||
|°|[aocsarsuawo> — ||—|||—|| —|| — ||— |Abcsarowo||
|Legend:|||||||||
|R = Readable bit<br>W = Writable bit|||U = Unimplemented bit, read as ‘0’||||||
|-n = Value at POR<br>‘1’ = Bit is set|||‘0’ = Bit is cleared|||L = Lockable bit|||
|bit 31-30|Unimplemented: Read as ‘0’||||||||
|bit 29|SQI1MD: SQI Module Disable bit||||||||
||1 = Disabled||||||||
||0 = Enabled||||||||
|bit 28-27|Unimplemented: Read as ‘0’||||||||
|bit 26|RNG1MD: RNG1 Module Disable bit||||||||
||1 = Disabled||||||||
||0 = Enabled||||||||
|bit 25|Unimplemented: Read as ‘0’||||||||
|bit 24|CRYPT1MD: CRYPTO1 Module Disable||bit||||||
||1 = Disabled||||||||
||0 = Enabled||||||||
|bit 23|BA414MD: Asymmetric Crypto Module Disable bit||||||||
||1 = Disabled||||||||
||0 = Enabled||||||||
|bit 22-20|Unimplemented: Read as ‘0’||||||||
|bit 19|DMA1MD: DMA Controller Module|Disable bit|||||||
||1 = Disabled||||||||
||0 = Enabled||||||||
|bit 18-17|Unimplemented: Read as ‘0’||||||||
|bit 16|RTCC1MD: RTCC Module Disable|bit|||||||
||1 = Disabled||||||||
||0 = Enabled||||||||
|bit 15|CVD1MD: CVD Module Disable bit||||||||
||1 = Disabled||||||||
||0 = Enabled||||||||
|bit 14-12|Unimplemented: Read as ‘0’||||||||
|bit 11|PTGMD: PTG Module Disable bit||||||||
||1 = Disabled||||||||
||0 = Enabled||||||||
|bit 10-9|Unimplemented: Read as ‘0’||||||||
|bit 8|ADC1MD: ADC Controller Module|Disable bit|||||||
||1 = Disabled||||||||
||0=Enabled||||||||
oe
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## REGISTER 36-4: PMD1: PERIPHERAL MODULE DISABLE 1 REGISTER (CONTINUED)
|bit|7|ADCSARSHRMND: Shared ADC SAR Core Module Disable bit|
|---|---|---|
|||1 = When disabled, the correspondingADC SAR SHARED will be disabled.|
|||0 = Enabled|
|bit|6-5|Unimplemented: Read as ‘0’|
|bit|4|PLVD1MD: PLVD Module Disable bit|
|||1 = When disabled, the corresponding PLVD will be disabled.|
|||0 = Enabled|
|bit|3-1|Unimplemented: Read as ‘0’|
|bit|0|ADCSAROMD: ADC SAR Core 0 Module Disable bit|
|||1 = When disabled, the correspondingADC SAR will be disabled.|
|||0=Enabled|
SS © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 605
PIC32MZ W1 and WFI32E01 Family
## seman
REGISTER 36-5: PMD2: PERIPHERAL MODULE DISABLE 2 REGISTER
|Bit|Bit<br>Bit|Bit|Bit|Bit|Bit|Bit|Bit|
|---|---|---|---|---|---|---|---|
|Range|| 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 |27/19/11/3 | 26/18/10/2 |25/17/9/1 |24/16/8/0|||||||
|*|[Trerouwo | Rerosmo| Reroam> | Rerowo||||—|| — ||— | — |||
|i||||||||
|®|(eT<br>J ecctno| ocsino [oem oct ||||||||
|i|a<br>a=|||||||
|Legend:||||||||
|R = Readable bit<br>W = Writable bit||U = Unimplemented bit, read as ‘0’||||||
|-n = Value at POR<br>‘1’ = Bit is set||‘0’ =|Bit is cleared||L = Lockable bit|||
|bit 31-28|REFOnMD: Reference (Clock) Out n Module Disable bit|||||||
||1 = Disabled|||||||
||o = Enabled|||||||
|bit 27-23|Unimplemented: Read as ‘0’|||||||
|bit 22-16|TnMD: Timer n Module Disable|bit||||||
||1 = Disabled|||||||
||0 = Enabled|||||||
|bit 15-12|Unimplemented: Read as ‘0’|||||||
|bit 11-8||OCnMD: Output Compare n Module Disable bit|||||||
||1 = Disabled|||||||
||0 = Enabled|||||||
|bit 7-4|Unimplemented: Read as ‘0’|||||||
|bit 3-0|ICnMD: Input Capture n Module Disable bit|||||||
||1 = Disabled|||||||
||o=Enabled|||||||
Meeeaa DS70005425A-page 606 Preliminary Data Sheet © 2020 Microchip Technology Inc.
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REGISTER 36-6: PMD3: PERIPHERAL MODULE DISABLE 3 REGISTER
|Bit|Bit|Bit<br>Bit|Bit||Bit|Bit|Bit|Bit|Bit|
|---|---|---|---|---|---|---|---|---|---|
|Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5||||||28/20/12/4|||27/19/11/3|26/18/10/2 | 25/17/9/1|||24/16/8/0|
||8|||Freanano||canimo[est||||
||a|a<br>On||||||||
||i|||||||||
||i|a<br>aOT||||||||
|Legend:||||||||||
|R =|Readable bit<br>W = Writable bit||||U = Unimplemented bit, read as ‘0’|||||
|-n =|Value at POR<br>‘1’ = Bit is set||||‘0’ = Bit is cleared||L = Lockable bit|||
|bit 31-29||Unimplemented: Read as ‘0’||||||||
|bit 28-27||CANnMD: CAN Module Disable|bit|||||||
|||1 = Disabled||||||||
|||0 = Enabled||||||||
|bit 26-25||Unimplemented: Read as ‘0’||||||||
|bit 24||USB1MD: USB Module Disable|bit|||||||
|||1 = Disabled||||||||
|||0 = Enabled||||||||
|bit 23-18||Unimplemented: Read as ‘0’||||||||
|bit 17||12C1MD: I2C 1 Module Disable bit||||||||
|||1 = Disabled||||||||
|||0 = Enabled||||||||
|bit 16||I2COMD: I2C 0 Module Disable bit||||||||
|||1 = Disabled||||||||
|||0 = Enabled||||||||
|bit 15-13||Unimplemented: Read as ‘0’||||||||
|bit 12||W24GMD: WiFi Module Disable|bit|||||||
|||1 = Disabled||||||||
|||0 = Enabled||||||||
|bit 11-10||Unimplemented: Read as ‘0’||||||||
|bit 9||SPI2MD: SPI 2 Module Disable|bit|||||||
|||1 = Disabled||||||||
|||0 = Enabled||||||||
|bit 8||SPI1MD: SPI 1 Module Disable|bit|||||||
|||1 = Disabled||||||||
|||0 = Enabled||||||||
|bit 7-5||Unimplemented: Read as ‘0’||||||||
|bit 4||ETH1MD: Ethernet Module Disable||bit||||||
|||1 = Disabled||||||||
|||0 = Enabled||||||||
|bit3||Unimplemented:Readas‘0’||||||||
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 607
PIC32MZ W1 and WFI32E01 Family
## REGISTER 36-6: PMD3: PERIPHERAL MODULE DISABLE 3 REGISTER (CONTINUED)
- bit 2-0 UnMD: UART Module Disable bit 1 = Disabled
- 0 = Enabled
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Preliminary Data Sheet
© 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
## 36.5.1 CONTROLLING CONFIGURATION CHANGES
Peripherals can be disabled during run time, some restrictions on disabling peripherals are needed to prevent accidental configuration changes. PIC32MZ W1 devices include Control Register Lock sequence to prevent alterations to enabled or disabled peripherals.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 609
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Preliminary Data Sheet © 2020 Microchip Technology Inc.
## PIC32MZ W1 and WFI32E01 Family smn 37.0 SPECIAL FEATURES * Configuration Control Register1(CFGCON1(L))1(CFGCON1(L))(CFGCON1(L))
- Configuration Control Register1(CFGCON1(L))1(CFGCON1(L))(CFGCON1(L)) provides control, selection and locking for various features of the device.
- Note: This data sheet summarizes the features features of the device. of the PIC32MZ W1 family of devices. - Debug port and feature configuration However, it is not intended to be a - USB port control comprehensive reference source. To complement[the][information] in this data - USB trim bits sheet, refer to Section 32. - CFGCOND locking control “Configuration” (DS60001124) and - Class B functionality enable Section 33. “Programming and - High-speed UART enable Diagnostics” (DS60001129) in the “PIC32 - Ethernet RMII enable cia aaeceesiie MEME, SAND Ee + Configuration Control Register 2 (CFGCON2(L)) available from the Microchip web site : : : : CAN GRE= . BERTIE) featuresprovides ofcontrol, the devicsel **e** .ction and locking for various W1 devices include several features - DMT enable and configuration
- to maximize application flexibility and reliabil- WDT enable and configuration
- and minimize cost through elimination of external - Clock monitoring and control
- components. These are: . . . Flexible;; device;; configuration;; ; -- 2-SpeedOscillatorstartupenableenabledand configurationin Sleep Mode bit Joint Test Action Test Action Action Group (JTAG) interface - SYSPLL/EWPLL Postdiv2 programming In-Circuit Serial Programming™(ICSP™) * Configuration Control Register 4 (CFGCONA(L)) Internal temperature sensor provides control, selection and locking for various features of the device.
- Configuration Bits - Deep sleep modules control
- PIC32MZ W1 device provides several user - SOSC configuration control
PIC32MZ W1 devices include several features intended to maximize application flexibility and reliability and minimize cost through elimination of external components. These are: * Flexible;; device;; configuration;; ; ¢ Joint Test Action Test Action Action Group (JTAG) interface * In-Circuit Serial Programming™(ICSP™) * Internal temperature sensor 37.1 Configuration Bits This PIC32MZ W1 device provides several user writable configuration registers related to the configuration and operation of the system. + Permission Group Configuration Register (CFGPG) defines the permission group.
- ¢ User Unique ID Register (USERID(L)) provides the end user with a 16-bit ID field that maybe read out directly through the JTAG interface via the USERID JTAG instruction.
- System Key Register (SYSKEY) defines the system key.
- Device and Revision ID Register (DEVID) defines the device and revision ID.
- Configuration Control Register 3 (CFGCON3) provides control, selection and locking for various features of the device.
- ¢ Configuration Control Register 0 (CFGCONO(L)) provides control, selection and locking for various features of the device. The registers those are marked with (L) are loadable from Flash.
- ICAP clock selection
- - OCMP clock selection
- PPS register locking
- PMD register locking
- CFGPG register locking
- Config register locking
- USB diagnostics enable
- USB suspend sleep enable
- JTAG port enable and configuration
- iFlowtrace port enable
- - Flash ECC control
- DMA, CPU, FC
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 611
## seman
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|DS70005425A-page612|||||PreliminaryDataSheet|||©2020MicrochipTechnologyInc.|
PIC32MZ W1 and WFI32E01 Family
## smn
|REGISTER 37-1:|CFGCONO(L):|CONFIGURATION CONTROL REGISTER 0|||
|---|---|---|---|---|
|Bit<br>Bit<br>Range | 31/23/15/7||Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>Bit<br>|30/22/14/6| 29/21/13/5 |28/20/12/4|<br>27/19/11/3<br>26/18/10/2 | 25/17/9/1|||Bit<br>24/16/8/0|
|31:24 [=|[etaTrsr||Feccconeto> __[ETHPLLHWMO |BTPLLHw® |SPLLHwnD||[UPLLWHD|
|a|||||
|15:8 [_oraLockera> | Totock [Pwotock| Petock | pwutock |"|||— | Uusessen|||
|m<br>°<br>[reaper|[owaerr[Fore [=| stacen | troen[=|_TOOEN_|||||
|Legend:|||||
|R = Readable bit|W = Writable bit|U = Unimplemented bit, read as ‘0’|||
|-n=ValueatPOR|‘1’=Bitisset|‘0’=Bitiscleared<br>L=Lockablebit|||
- bit 31 Unimplemented: Read as ‘0’ bit 30 ETHTPSF: Ethernet TX SOF enabled for CTR measurements 1 = TPSF is enabled in CTR measurement 0 = RPSF is enabled in CTR measurement
- bit 29-28 FECCCON: Flash ECC Controls 11 =ECC and Dynamically ECC Disabled
- 10 = ECC and Dynamically ECC Disabled 01 = Dynamically ECC Enabled
- 00 = ECC Enabled (NVMOP = Word Programming disabled)
- bit 27 ETHPLLHWMD: EWPLL Hardware Control Mode for power down and Reset 1 = Power Down and Reset are generated by hardware
- 0 = Power Down and Reset are generated by software using corresponding PLLCON register bits
- bit 26 BTPLLHWMD: BTPLL Hardware Control Mode for power down and Reset 1 = Power Down and Reset are generated by hardware 0 = Power Down and Reset are generated by software using corresponding PLLCON register bits
- bit 25 SPLLHWMD: SPLL Hardware Control Mode for power down and Reset 1 = Power Down and Reset are generated by hardware 0 = Power Down and Reset are generated by software using corresponding PLLCON register bits
- bit 24 UPLLHWMD: UPLL Hardware Control Mode for power down and Reset 1 = Power Down and Reset are generated by hardware 0 = Power Down and Reset are generated by software using corresponding PLLCON register bits
- bit 23 PCM: Prefetch I/D Cacheable Mode 1 = Always enabled. Can be further enabled/disabled by Prefetch module SFR registers. 0 = The cache-ability is controlled by the MIPS CPU via HPROT[3]. This feature is not available on all the MIPS cores.
- bit 22 Unimplemented: Read as ‘0’ bit 20-21 CANFDDIV: CAN-FD Back-up Clock Divider 0 = Divide-by 2 1 = Divide-by 2
- 2 = Divide-by 4 3 = Divide-by 8
bit 18-19 Unimplemented: Read as ‘0’
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 613
## PIC32MZ W1 and WFI32E01 Family seman
**==> picture [424 x 606] intentionally omitted <==**
**----- Start of picture text -----**<br>
||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|REGISTER|37-1:|CFGCONO(L):|CONFIGURATION|CONTROL|REGISTER|0|(CONTINUED)|
|bit|17|IC_ACLK:|ICAP Alternate|Clock|Selection|
|1|=|ICAP|Modules|use|an|alternative|timer|pair|as|their|timebase|clock|
|0|=|All|ICAP|Modules|use|timer2/timer3|as|their|timebase|clock|
|bit|16|OC_ACLK:|OCMP Alternate|Clock|Selection|
|1|=|OCMP|Modules|use|an|alternative|timer|pair|as|their|timebase|clock|
|0|=|All|OCMP|Modules|use|timer2/timer3|as|their|timebase|clock|
|bit|15-14|CFGLOCK[1:0]:|Configuration|Register|Lock|
|11|=All|NVR|memory|self-writes,|Boot|Configuration|(BCFGO)|and|System|Configuration|registers|
|(CFG*|and|USERID)|are|locked|and|can|not|be|written|-|CFGLOCK|value|can|not|be|changed.|
|10|=All|NVR|memory|self-writes,|Boot|Configuration|(BCFGO)|and|System|Configuration|registers|
|(CFG*|and|USERID)|are|locked|and|can|not|be|written|-|CFGLOCK|value|can|be|changed.|
|01|=|Reserved|for|future|use|
|00|=All|NVR|memory|self-writes,|Boot|Configuration|(BCFGO)|and|System|Configuration|registers|
|(CFG*|and|USERID)|are|not|locked|and|can|be|written|-|CFGLOCK|value|can|be|changed.|
|bit|13|IOLOCK:|IO|Lock|
|1|=|10|Remap|SFR|bits|are|locked|and|cannot|be|modified|
|0|=|10|Remap|SFR|are|not|locked|and|can|be|modified|
|bit|12|PMDLOCK:|Peripheral|Module|Disable|(PMD)|Lock|
|1|=|PMDx|SFR|bits|are|locked|and|cannot|be|modified|
|0|=|PMDx|SFR|bits|are|not|locked|and|can|be|modified|
|bit|11|PGLOCK:|Permission|Group|Lock|
|1|=|CFGPG|SFR|bits|are|locked|and|cannot|be|modified|
|0|=|CFGPG|SFR|bits|are|not|locked|and|can|be|modified|
|bit|10|PMULOCK:|PMU|Controller|Register|Lock|
|1|=|PMU|SFR|bits|are|locked|and|cannot|be|modified|
|0|=|PMU|SFR|bits|are|not|locked|and|can|be|modified|
|bit|9|Unimplemented:|Read|as|‘0’|
|bit|8|USBSSEN:|USB|Suspend|Sleep|Enable|
|Enables|features|for|USB|PHY|FREF|Clock|shutdown|in|SUSPEND|Mode.|
|1|=|USB|FREF|clock|is|shut|down|when|suspend|mode|is|active.|
|0|=|USB|FREF|clock|continues|to|run|when|suspend|mode|is|active.|
|bit|7|EXLPRI:|CPU|arbitration|Priority|to|SRAM|when|servicing|an|Interrupt|(i.e.|EXL=1)|
|1|=|CPU|gets|High|Priority|access|to|SRAM1,|SRAM2|
|0|=|CPU|uses|Least|Recently|Serviced|Arbitration|(same|as|other|initiators)|
|bit|6|DMAPRI:|DMAR|and|DMAW|arbitration|Priority|to|SRAM|
|1|=|DMA|gets|High|Priority|access|to|SRAM1,|SRAM2|
|0|=|DMA|uses|Least|Recently|Serviced|Arbitration|(same|as|other|initiators)|
|bit|5|FCPRI:|FC|arbitration|Priority|to|SRAM|
|1|=|FC|gets|High|Priority|access|to|SRAM1,|SRAM2|
|0|=|FC|uses|Least|Recently|Serviced|Arbitration|(same|as|other|initiators)|
|bit|4|Unimplemented:|Read|as|‘0’|
|bit|3|JTAGEN:|JTAG|Enable|
|1|=|JTAG|Port|Enabled|
|0|=|JTAG|Port|Disabled|
|bit|2|TROEN:|Trace|Output|Enable|
|1|=|Start|Trace|Clock|and|enable|Trace|Outputs|(Trace|Probe|must|be|present)|
|0|=|Stop|Trace|Clock|and|disable|Trace|Outputs|
|bit|1|Unimplemented:|Read|as|‘0’|
|bit|0|TDOEN:|TDO|enable|for|2-wire|JTAG|
|1|=|2-wire|JTAG|protocol|uses|TDO|
|0|=|2-wire|JTAG|protocol|does|not|use TDO|
**----- End of picture text -----**<br>
renner eee e rereerence eee eee DS70005425A-page 614 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
## REGISTER 37-2: CFGCON1(L): CONFIGURATION CONTROL REGISTER 1
|Bit<br>Bit<br>Range | 31/23/15/7|re<br>14/6|Bit<br>29/21/13/5|Bit<br>29/21/13/5|seas<br>A|Bit<br>27/19/11/3|Bit<br>Bit<br> |26/18/10/2 | 25/17/9/1|Bit<br>24/16/8/0|
|---|---|---|---|---|---|---|---|
|31:24 a||||||||
|23:16||||||||
|:||||||||
|7:0 a||||||||
|Legend:||||||||
|R = Readable bit|W = Writable||bit|U = Unimplemented bit,||read as ‘0’||
|-n=ValueatPOR|‘1’=Bitisset|||‘0’=Bitis|cleared|L=Lockablebit||
bit 32-29 Unimplemented: Read as ‘0’
bit 28-24 WDTPS<4:0>: Watchdog Timer Post-scale Select Sleep bits
10100 = 1:1048576 10011 = 1:524288 10010 = 1:262144 10001 = 1:131072 10000 = 1:65536 01111 = 1:32768 01110 = 1:16384 01101 = 1:8192 01100 = 1:4096 01011 = 1:2048 01010 = 1:1024 01001 = 1:512 01000 = 1:256 00111 = 1:128 00110 = 1:64 00101 = 1:32 00100 = 1:16 00011 = 1:8 00010 = 1:4 00001 = 1:2 00000 = 1:1
- bit 23-20 USBDPTRIM<3:0>: USB DP Rise/Fall Trim fuse bits
- bit 19-16 USBDMTRIM<3:0>: USB DM Rise/Fall Trim fuse bits
- bit 15 HSUARTEN: UART1 High Speed Mode Enable
- 1 = UART‘1 is driven from/to dedicated pins, resulting in the highest possible maximum baud rate 0 = UART‘1 is driven through PPS (I/O remap), resulting in a lower maximum baud rate
- bit 14 SMCLR: Selects CRU handling of MCLR Control 1 = Legacy mode (system clear does not reset all state of device) 0 = MCLR causes a faux POR
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 615
## PIC32MZ W1 and WFI32E01 Family seman
|REGISTER 37-2:<br>CFGCON1(L): CONFIGURATION CONTROL REGISTER 1 (CONTINUED)|REGISTER 37-2:<br>CFGCON1(L): CONFIGURATION CONTROL REGISTER 1 (CONTINUED)|
|---|---|
|bit 13|HSSPIEN: High Speed Mode Enable (SPI-1)|
||1 = SPI1 is driven from/to dedicated pins, resulting in the highest interface speed|
||0 = SPI1 is driven through PPS (I/O remap), resulting in a lower interface speed|
|bit 12|VBUSIO: USB VBUS_ON Selection bit|
||1 =VBUS_ON pin is controlled by the USB Module|
||0 = VBUS_ON pin is controlled by the Port Function|
|bit 11|USBIDIO: USB USBID Selection bit|
||1 = USBID pin is controlled by the USB Module|
||0 = USBID pin is controlled by the Port Function|
|bit 10|CLASSBDIS: Disable CLASSB Device Functionality|
||0 = CLASSB functions enabled|
||1 = CLASSB functions disabled|
|bit 9|ETHEXEREF: Exclusive Ethernet PHY Reference Clock Enable|
||0 = Ethernet clock out will be used as PHY reference clock|
||1 = PHY reference clock is made available on Ethernet Exclusive clock out|
|bit 8|FMIIEN: Ethernet1 MII Enable|
||1 = 18-pin 25MHz Media Independent Interface is enabled|
||0 = 10-pin 50MHz Reduced Media Independent Interface is enabled|
|bit 7-6|Unimplemented: Read as ‘0’|
|bit 5|TRCEN: Trace Enable|
||1 =Trace features in the CPU are enabled|
||0 =Trace features in the CPU are disabled|
|bit 4-3|ICESEL<1:0>: In-Circuit Emulator/Debugger Communication Channel Select bits|
||11 = PGC1/PGD1 pair is used|
||10 = PGC2/PGD2 pair is used|
||01 =Reserved|
||00 = PGC4/PGD4 pair is used|
|bit 2|Unimplemented: Read as ‘0’|
|bit 1-0|DEBUG<1:0>: Background Debugger Enable bits (forced to ‘11’ if code-protect is enabled)|
||1x = Debugger is disabled|
||Ox=Debuggerisenabled|
renner eee e rereerence eee eee DS70005425A-page 616 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
|REGISTER 37-3:|CFGCON2(L): CONFIGURATION CONTROL REGISTER 2|CFGCON2(L): CONFIGURATION CONTROL REGISTER 2|CFGCON2(L): CONFIGURATION CONTROL REGISTER 2|CFGCON2(L): CONFIGURATION CONTROL REGISTER 2|||
|---|---|---|---|---|---|---|
|Bit<br>Bit|Bit|Bit<br>Bit|Bit|Bit|Bit|Bit|
|Range | 31/23/15/7||30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3|||26/18/10/2 | 25/17/9/1 | 24/16/8/0|||
|31:24|||||||
|:|||||||
|15:8|||||||
|7”<br>i|||||||
|Legend:|||||||
|R = Readable bit|W = Writable bit|U = Unimplemented bit, read||as ‘0’|||
|-n=ValueatPOR|‘1’=Bitisset|‘0’=Bitiscleared||L=Lockablebit|||
- bit 31 DMTEN: Dead Man Timer Enable bit 1 = DMT enabled
- 0 = DMT disabled (control is placed on the DMTCON.ON bit)
- bit 30-26 DMTCNT<4:0>: Dead Man Timer Count Select bits 00000 = Counter value is 28 00001 = Counter value is 29
10100 = Counter value is 228 10101 = Counter value is 229 10110 = Counter value is 2° 10111 = Counter value is 2°" 11000 - 11111= Reserved
- bit 25-24 WDTWINSZ<1:0>: Watchdog Timer Window Size bits
- 00 = Window size is 75%
- 01 = Window size is 50% 10 = Window size is 37.5%
- 11 = Window size is 25%
- bit 23 WDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on the SWDTEN bit)
- bit 22 WINDIS: Windowed Watchdog Timer Disable bit 1 = Standard WDT selected; windowed WDT disabled 0 = Windowed WDT enabled
- bit 21 WDTSPGM: Watchdog Timer Stop during Flash Programming bit
- 1 = WDT stops during NVR programming (legacy)
- 0 = WDT runs during NVR programming (for read/execute while programming Flash systems)
**==> picture [457 x 2] intentionally omitted <==**
**----- Start of picture text -----**<br>
a<br>**----- End of picture text -----**<br>
©2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 617
## PIC32MZ W1 and WFI32E01 Family
## ee
|REGISTER 37-3:<br>CFGCON2(L): CONFIGURATION CONTROL REGISTER 2 (CONTINUED)|REGISTER 37-3:<br>CFGCON2(L): CONFIGURATION CONTROL REGISTER 2 (CONTINUED)|
|---|---|
|bit 20-16|WDTPS<4:0>: Watchdog Timer Post-scale Select Run bits|
||10100 = 1:1048576|
||10011 = 1:524288|
||10010 = 1:262144|
||10001 = 1:131072|
||10000 = 1:65536|
||01111 = 1:32768|
||01110 = 1:16384|
||01101 = 1:8192|
||01100 = 1:4096|
||01011 = 1:2048|
||01010 = 1:1024|
||01001 =1:512|
||01000 = 1:256|
||00111 = 1:128|
||00110 = 1:64|
||00101 = 1:32|
||00100 = 1:16|
||00011 = 1:8|
||00010 = 1:4|
||00001 = 1:2|
||00000 = 1:1|
|bit 15|FSCMEN: Fail-Safe Clock Monitor Enable|
||1 = FSCM Enabled|
||0 = FSCM Disabled|
|bit 14|CKSWEN: Software Clock Switching Enable|
||1 = Software Clock Switching Enabled|
||0 = Software Clock Switching Disabled|
|bit 13|WAKE2SPD: 2-Speed startup enabled in Sleep mode bit|
||1 =When the device EXITS Sleep Mode, the SYS_CLK will be from FRC until the selected clock is ready|
||0 =When the device EXITS Sleep Mode, the SYS_CLK will be from the selected clock.|
|bit 12|SOSCSEL: SOSC Selection Configuration bit|
||1 = Crystal (SOSCI/SOSCO) mode|
||0 = Digital (SCLKI) mode|
|bit 11-10|WDTRMCS<1:0>: WDT RUN Mode Clock Select|
||11 =LPRC|
||10 = Module PB clock|
||01 = Module PB clock|
||00 = Module PB clock|
|bit 9-8|POSCMOD<1:0>: Primary Oscillator Configuration bits|
||11 = Primary oscillator disabled|
||10 = HS oscillator mode selected|
||01 = HS oscillator mode selected|
||00 = HS oscillator mode selected|
|bit 7-6|Unimplemented: Read as ‘0’|
|bit 5-3|DMTINTV<2:0>: Dead Man Timer Count Window Interval bits|
||000 = Window/interval value is zero counter value|
||001 = Window/interval value is 1/2 counter value|
||010 = Window/interval value is 1/4 counter value|
||011 = Window/interval value is 1/8 counter value|
||100 = Window/interval value is 1/16 counter value|
||101 = Window/interval value is 1/32 counter value|
||110 = Window/interval value is 1/64 counter value|
||111 = Window/interval value is 1/128 counter value|
|bit2-0|Unimplemented:Readas‘0’|
ee DS70005425A-page 618 Preliminary Data Sheet © 2020 Microchip Technology Inc.
——
PIC32MZ W1 and WFI32E01 Family
## REGISTER 37-4: CFGCON3: CONFIGURATION CONTROL REGISTER 3
|Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 |26/18/10/2 | 25/17/9/1<br>24/16/8/0|Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 |26/18/10/2 | 25/17/9/1<br>24/16/8/0|Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 |26/18/10/2 | 25/17/9/1<br>24/16/8/0|
|---|---|---|
|eeee<br>ee|ee ee ee <br>ee ee|ee<br> ee ee<br>ee|
|Legend:|||
|R = Readable bit|W = Writable bit|U = Unimplemented bit, read as ‘0’|
|-n=ValueatPOR|‘1’=Bitisset|‘0’=Bitiscleared<br>x=Bitisunknown|
bit 31-18 Unimplemented: Read as ‘0’
- bit 17-12 BTPLLPOSTDIV2[5:0]: BTPLL Post Divider bits for controlling auxiliary second PLL clock output. 1 <xPLLPOSTDIV2 < 63 , value of 0 is unused.
- bit 11-6 SPLLPOSTDIV2[5:0]: SPLL Post Divider bits for controlling auxiliary second PLL clock output. 1 <xPLLPOSTDIV2 < 63 , value of 0 is unused.
- bit 5-0 ETHPLLPOSTDIV2[5:0]: EWPLL Post Divider bits for controlling second PLL clock output for Wi-Fi block. 1 <xPLLPOSTDIV2 < 63 , value of 0 is unused.
SS © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 619
PIC32MZ W1 and WFI32E01 Family
seman
## REGISTER 37-5: CFGCON4(L): CONFIGURATION CONTROL REGISTER 4
|Bit<br>Bit|Bit|Bit|Bit<br>Bit<br>Bit|Bit|Bit|
|---|---|---|---|---|---|
|Range | 31/23/15/7 |30/22/14/6|29/21/13/5|||| 28/20/12/4 | 27/19/11/3 | 26/18/10/2|25/17/9/1|| 24/16/8/0|
|inO||||||
|“ ES|EE ee<br>ee ee|||eee||
|i||||||
|70<br>:||||||
|Legend:||||||
|R = Readable bit|W = Writable bit||U = Unimplemented bit, read as ‘0’|||
|-n=ValueatPOR|‘1’=Bitisset||‘0’=Bitiscleared<br>L=Lockablebit|||
bit 31 Unimplemented: Read as ‘0’ bit 30 SOSCEN: Low-Power (Secondary) Oscillator Enable bit 1 = Enable low-power (secondary) oscillator, also at Reset
0 = Disable low-power (secondary) oscillator bit 29-8 | Unimplemented: Read as ‘0’ bit 7-0 SOSCCFG<7:0>: SOSC Configuration bits
renner eee e rereerence eee eee DS70005425A-page 620 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
|REGISTER|37-6:|CFGPG: PERMISSION GROUP CONFIGURATION|CFGPG: PERMISSION GROUP CONFIGURATION|CFGPG: PERMISSION GROUP CONFIGURATION|CFGPG: PERMISSION GROUP CONFIGURATION|REGISTER|REGISTER|||
|---|---|---|---|---|---|---|---|---|---|
|Bit|Bit|Bit|Bit|Bit|Bit||Bit|Bit|Bit|
|Range | 31/23/15/7 |30/22/14/6 |29/21/13/5|||29/21/13/5|| 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 |24/16/8/0||||||
|en||||||||||
|:||||||||||
|.<br>15:8|R/W/L-0|R/W/L-O|R/W/L-0|R/W/L-O|R/W/L-0O|R/WI/L-O||R/W/L-O|R/WI/L-O|
|7:0||||||||||
||ICDJPG<1:0>||DMAPG<1:0>||FCPG<1:0>|||CPUPG<1:0>||
|Legend:||||||||||
|R = Readable bit||W = Writable|bit|U = Unimplemented bit, read as ‘0’||||||
|-n=ValueatPOR||‘1’=Bitisset||‘0’=Bitiscleared||L=|Lockable|bit||
- bit 31-24 Unimplemented: Read as ‘0’
- bit 23-22 USBPG<1:0>: USB Permission Group bits 11 = Initiator is assigned to Permission Group 3 10 = Initiator is assigned to Permission Group 2 01 = Initiator is assigned to Permission Group 1 00 = Initiator is assigned to Permission Group 0
- bit 21-20 SQIPG<1:0>: SQI Permission Group bits 11 = Initiator is assigned to Permission Group 3 10 = Initiator is assigned to Permission Group 2 01 = Initiator is assigned to Permission Group 1 00 = Initiator is assigned to Permission Group 0
- bit 19-18 ETHPG<1:0>: ETH Permission Group bits 11 = Initiator is assigned to Permission Group 3 10 = Initiator is assigned to Permission Group 2 01 = Initiator is assigned to Permission Group 1 00 = Initiator is assigned to Permission Group 0
- bit 17-16 CRY1PG<1:0>: CRY1 Permission Group bits 11 = Initiator is assigned to Permission Group 3 10 = Initiator is assigned to Permission Group 2 01 = Initiator is assigned to Permission Group 1 00 = Initiator is assigned to Permission Group 0
- bit 15-14 CAN2PG<1:0>: CAN2 Permission Group bits 11 = Initiator is assigned to Permission Group 3 10 = Initiator is assigned to Permission Group 2 01 = Initiator is assigned to Permission Group 1 00 = Initiator is assigned to Permission Group 0
- bit 13-12 CAN1PG<1:0>: CAN1 Permission Group bits 11 = Initiator is assigned to Permission Group 3 10 = Initiator is assigned to Permission Group 2 01 = Initiator is assigned to Permission Group 1 00 = Initiator is assigned to Permission Group 0
- Note: The CPU as System Bus Initiator will use the permission group indicated in the GuestID bits of the CPU core. These bits change based on some CPU operations, such as interrupts. Refer to Series 5 Warrior M- class CPU core resources which is available at: www.imgtec.com.
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PIC32MZ W1 and WFI32E01 Family
## seman
## REGISTER 37-6: CFGPG: PERMISSION GROUP CONFIGURATION REGISTER
**==> picture [452 x 383] intentionally omitted <==**
**----- Start of picture text -----**<br>
|||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|bit|11-10|ADCPG<1:0>: ADC|Permission|Group|bits|
|11|=|Initiator|is|assigned|to|Permission|Group|3|
|10|=|Initiator|is|assigned|to|Permission|Group|2|
|01|=|Initiator|is|assigned|to|Permission|Group|1|
|00|=|Initiator|is|assigned|to|Permission|Group|0|
|bit|9-8|WIFIPG<1:0>:|Wi-Fi|Permission|Group|bits|
|11|=|Initiator|is|assigned|to|Permission|Group|3|
|10|=|Initiator|is|assigned|to|Permission|Group|2|
|01|=|Initiator|is|assigned|to|Permission|Group|1|
|00|=|Initiator|is|assigned|to|Permission|Group|0|
|bit|7-6|ICDJPG<1:0>:|ICD-JTAG|Permission|Group|bits|
|11|=|Initiator|is|assigned|to|Permission|Group|3|
|10 =|Initiator|is|assigned|to|Permission|Group|2|
|01|=|Initiator|is|assigned|to|Permission|Group|1|
|00|=|Initiator|is|assigned|to|Permission|Group|0|
|bit|5-4|DMAPG<1:0>:|DMA|Permission|Group|bits|
|11|=|Initiator|is|assigned|to|Permission|Group|3|
|10|=|Initiator|is|assigned|to|Permission|Group|2|
|01|=|Initiator|is|assigned|to|Permission|Group|1|
|00|=|Initiator|is|assigned|to|Permission|Group|0|
|bit|3-2|FCPG<1:0>:|FC|Permission|Group|bits|
|11|=|Initiator|is|assigned|to|Permission|Group|3|
|10|=|Initiator|is|assigned|to|Permission|Group|2|
|01|=|Initiator|is|assigned|to|Permission|Group|1|
|00|=|Initiator|is|assigned|to|Permission|Group|0|
|bit|1-0|CPUPG<1:0>:|CPU|(Code)|Permission|Group|bits|
|11|=|Initiator|is|assigned|to|Permission|Group|3|
|10|=|Initiator|is|assigned|to|Permission|Group|2|
|01 =|Initiator|is|assigned|to|Permission|Group|1|
|00|=|Initiator|is|assigned|to|Permission|Group|0|
|Note:|The|CPU|as|System|Bus|Initiator|will|use|the|permission|group|indicated|in|the|GuestID|bits|of|the|CPU|
|core.|These|bits|change|based|on|some|CPU|operations,|such|as|interrupts.|Refer|to|Series|5|Warrior M-|
|class|CPU|core|resources which|is|available|at:|www.imgtec.com.|
**----- End of picture text -----**<br>
renner eee e rereerence eee eee DS70005425A-page 622 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
ee
REGISTER 37-7: DEVID: DEVICE AND REVISION ID REGISTER
|Bit<br>Bit|Bit<br>Bit<br>Bit<br>Bit<br>Bit|Bit<br>Bit|
|---|---|---|
|Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 |27/19/11/3 | 26/18/10/2||| 25/17/9/1<br>24/16/8/0|
|} orae RRR RR Soe<br>| asae PAL RL |e te TR |<br>ig<br>FL RT RT RE RE RE RTRR|||
|1 LR |<br>:|rR<br>[|<br>rk<br>|<br>rR |<br>rR |<br>rR|{| R<br>[| R ||
|Legend:|||
|R = Readable bit|W = Writable bit<br>U = Unimplemented bit,|read as ‘0’|
|-n=ValueatPOR|‘1’=Bitisset<br>‘0’=Bitiscleared|x=Bitisunknown|
bit 31-28 VER<3:0>: Revision Identifier bits bit27-0 DEVID<27:0>: Device ID
ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 623
PIC32MZ W1 and WFI32E01 Family
seman
REGISTER 37-8: USERID(L): USER UNIQUE ID REGISTER
|Bit<br>Bit|Bit|Bit|Bit|Bit|Bit|Bit|Bit|
|---|---|---|---|---|---|---|---|
|Range | 31/23/15/7 | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 |26/18/10/2 | 25/17/9/1 | 24/16/8/0||||||||
|a||||||||
|pee Se|||oe|||||
|15:8||||||||
|:||||||||
|Legend:||||||||
|R = Readable bit|W = Writable bit||U = Unimplemented bit,||read as ‘0’|||
|-n=ValueatPOR|‘1’=Bitisset||‘0’=Bitiscleared||L=Lockablebit|||
bit 31-16 Unimplemented: Read as 'O' bit 15-O | USERID: User unique ID, readable using the JTAG USERID instruction.
REGISTER 37-9: SYSKEY: SYSTEM KEY REGISTER
|Bit|Bit|Bit|Bit|Bit||Bit|Bit|||Bit|Bit|
|---|---|---|---|---|---|---|---|---|---|---|---|
|Range | 31/23/15/7|||30/22/14/6 |29/21/13/5 | 28/20/12/4|||| 27/19/11/3 |26/18/10/2 |||||25/17/9/1||24/16/8/0|
|31:24||||||||||||
|23-16||||||||||||
|15:8||||||||||||
|7:0||||||||||||
|Legend:||||||||||||
|R = Readable bit||W|= Writable bit||U|= Unimplemented bit, read||||as ‘0’||
|-n=ValueatPOR||‘1’|=Bitisset||‘0’|=Bitiscleared||x|=Bitisunknown|||
bit31-0 SYSKEY: System Key Keys are written to this register as part of a sequence to unlock system critical registers.
renner eee e rereerence eee eee DS70005425A-page 624 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
**==> picture [459 x 318] intentionally omitted <==**
**----- Start of picture text -----**<br>
TABLE 37-2: BOOT CONFIGURATION SUMMARY<br>3 a<br>aai0100 |BCFGO&Zz so]esse|a= aBINFO-31/15too= |||30/14== [sen]|| 29/13=| | 28/42em=]|| 27/11== ||[26/10=]= |=] =[ | 25/9 = |[=] 24/8 | = 23/7= [=]||=[22/6] 21/5== [=|=]|20/4] Joconse)19/3= |[=]18/2]= | fc171= ||ounce=16/0 [p00=<br>Legend: x = unknown value on Reset; — = Reserved, read as ‘0’. Reset values are shown in hexadecimal.<br>REGISTER 37-10: BCFGO: BOOT CONFIGURATION 0 REGISTER<br>Bit Bit Bit Bit Bit Bit Bit Bit Bit<br>Range 31/23/15/7 = | 30/22/14/6 | 29/21/13/5 | 28/20/12/4 | 27/19/11/3 | 26/18/10/2 | 25/17/9/1 | 24/16/8/0<br>r | Refg | RO | Reig | Refg | RO | RO | RO | RO |<br>mo LR| RO | Reo | [Roo]<br>painrovarioof| | RO | RO | RO | RO |<br>jaro — | sien | cp | — | — | — | — |<br>| tse | —B2—SO _}_R e_}_Ro_}_Ro_{O_}_RO_|_Ro_ } _no_}_ko_Ro_}_o _ }{ _Ro _}_80_|_fo__<br>yo (RO | Ro TRO | RO | Ret | RO | Rete | Ret<br>° =<br>ois = resemone | aunsw_ |<br>Legend:<br>R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’<br>cfg = Configurable at Reset ‘1’ = Bit is set ‘0’ = Bit is cleared<br>**----- End of picture text -----**<br>
- bit 31 BINFOVALIDO: First 256-bit BCFG Information Valid
- 1 = Untrusted, Flash values ignored and safe values used
- 0 = Trusted, loaded from Flash
- Note: This bit to be programmed to Zero for proper device operation
- bit 30 Unimplemented: Read as ‘0’
- bit 29 SIGN: Flash SIGN bit
- 1 = Unsigned
- 0 = Signed
- bit 28 CP: Boot Code Protect
- 0 = Protection Disabled
- 1 = Protection Enabled
- bit 27-4 Unimplemented: Read as ‘0’
- bit 3 BOOTISA: Boot ISA Selection
- 1 = Boot code and exception code is MIPS32
- 0 = Boot code and exception code is microMIPS
- Note: |The BOOTISA bit does not determine the initial ISA for boots using EJTAGBOOT, but only for normal (non-debug) CPU boots. The initial ISA for boots using EJTAGBOOT is determined by the ECR.ISAOnDebug EJTAG register bit.
- bit 2 Unimplemented: Read as ‘0’
- bit 1 PCSCMODE: PCHE Single Cache Mode
- 1 = PCHE ICache only. CPU instructions (code, data) go to PCHE ICache only.
- 0 = PCHE ICache and DCache. CPU opcodes go to PCEHE ICache port and data goes to PCHE DCache port.
- bit 0 BUHSW: This bit is programmed to ‘0’ only.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 625
## PIC32MZ W1 and WFI32E01 Family seman
**==> picture [450 x 360] intentionally omitted <==**
**----- Start of picture text -----**<br>
37.3. On-Chip Voltage Regulator FIGURE 37-1: BLOCK DIAGRAM OF<br>The core and digital2 Ff logicF for all PIC32MZ W1 devices. PROGRAMMING,DEBUGGING AND TRACE<br>is designed to operate at a nominal 1.2V. To simplify PORTS<br>system designs, devices in the PIC32MZ W1 family<br>incorporate an on-chip regulator providing the required<br>core logici voltage from VDD. PGEC1 x7<br>37.3.1. ON-CHIP REGULATOR AND POR PGED1 |XSZ<br>It takes a fixed delay for the on-chip regulator to generate Controlleresp |<br>an output. During this time, designated as TPU, code PGEC2 hx]<br>executiondevice resumesis disabled.operationTPU isafterappliedanyeverypower-down,time the PGED2 N<Nx]<br>including Sleep mode.<br>ICESEL<br>37.3.2 ON-CHIP REGULATOR AND AND BOR<br>PIC32MZ W1 devices also have a simple brown-out TD! |X]<br>capability. If the voltage supplied to the regulator is TDO hx] JTAG — c<br>inadequate to maintain a regulated level, the regulator tek SJ Controller —<br>Reset circuitry will generate a Brown-out Reset. This =<br>event is captured captured by the BOR flag the BOR flag BOR flag flag bit (RCON<1>). The (RCON<1>). The The T™s [x]<br>brown-out voltage levels are specific in Section 40.1.1<br>37.4 On-chip Temperature Sensor Sensor TRCLK Xx]<br>PIC32MZ W1 devices include a temperature sensor TRDO [X(<br>that provides accurate measurement of a device’s TRD1 NX] Instruction Trace<br>junction temperature (see Section 40.1.2 “AC S Controller<br>Characteristics and Timing Parameters” for more TRD2 |X"<br>information). TRD3 hx]<br>The temperature sensor is connected to the ADC<br>module and can be measured using the shared S&H DEBUG <1:0><br>**----- End of picture text -----**<br>
37.3.2 ON-CHIP REGULATOR AND AND BOR PIC32MZ W1 devices also have a simple brown-out capability. If the voltage supplied to the regulator is inadequate to maintain a regulated level, the regulator Reset circuitry will generate a Brown-out Reset. This event is captured captured by the BOR flag the BOR flag BOR flag flag bit (RCON<1>). The (RCON<1>). The The brown-out voltage levels are specific in Section 40.1.1 37.4 On-chip Temperature Sensor Sensor PIC32MZ W1 devices include a temperature sensor that provides accurate measurement of a device’s junction temperature (see Section 40.1.2 “AC Characteristics and Timing Parameters” for more information). The temperature sensor is connected to the ADC module and can be measured using the shared S&H circuit (see Section 29.0 “12-bit High-Speed Successive Approximation Register (SAR) ADC” for more information).
## 37.5 Programming and Diagnostics
PIC32MZ W1 devices provide a complete range of programming and diagnostic features that can increase the flexibility of any application using them. These features allow system designers to include:
- ¢ Simplified field programmability using two-wire In-Circuit Serial Programming™ (ICSP™) interfaces
- Debugging using ICSP
- « Programming and debugging capabilities using the EJTAG extension of JTAG
- ¢ JTAG boundary scan testing for device and board diagnostics
- Programming and debugging capability using Trace controller
renner eee e rereerence eee eee DS70005425A-page 626 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
## 38.0 INSTRUCTION SET
The PIC32MZ W1 family supports both the microMIPS and MIPS32 instruction sets. Therefore all firmware must be written using microMIPS instructions, MIPS32 instructions, or a combination of both.
As dynamic switching between microMIPS and MIPS32 is possible (using the JALX and JALX32 instructions), the user need to only specify the ISA to be used for the first instruction after boot. During a normal boot, the CPU fetches its first instruction from the reset vector at OxBFCO_0000. The ISA for this instruction is specified using the BCFGO.BOOTISA bit. On a blank device, the reset value of the BCFGO.BOOTISA is ‘1’, which places the device in MIPS32 instruction mode on exit from reset. However, it is assumed that on programming of the boot code, the BCFGO.BOOTISA bit is also programmed at the same time to match the instruction set of the boot code. The PIC32MZ W1 device family does not support the following features:
- Core extend instructions
* Coprocessor 2 instructions
Note: Refer to “MIPS32® Architecture for Programmers Volume Il: The MIPS32® Instruction Set” for more information.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 627
PIC32MZ W1 and WFI32E01 Family
NOTES:
© 2020 Microchip Technology Inc.
DS70005425A-page 628
Preliminary Data Sheet
PIC32MZ W1 and WFI32E01 Family smn 39.0 DEVELOPMENT SUPPORT 39.1 MPLABX Integrated Development The PIC® MCUs and dsPIC® Digital Signal Controllers Environment Software (DSC) are supported with a full range of software and The MPLAB X IDE is a single, unified Graphical User hardware development tools: Interface (GUI) for Microchip and third-party software, - Integrated Development Environment and parses development tool that runs on Win- MPLAB® X IDE Software dows~, Linux and Mac OS* X. Based on the NetBeans ° : : IDE, MPLAB X IDE is an entirely new IDE with a host a ean een of free software components and plug-ins for high- MPLAB XC Compiler performance application development and debugging. - MPASM™ Assembler Moving between tools and upgrading from software - MPLINK™ Object Linker/ simulators to hardware debugging and programming MPLIB™ Object Librarian tools is simple with the seamless user interface. - MPLAB Assembler/Linker/Librarian for With complete project management, visual call graphs, Various Device Families a configurable watch window and a feature-rich editor * Simulators that includes code completion and context menus, - MPLAB X X SIM Software Simulator MPLAB x IDE is flexible and friendly enough for new ¢ Emulators users.: With: the ability<<a: to support multiple; tools on , multiple projects with simultaneous debugging, MPLAB - MPLAB REAL ICE™ In-Circuit Emulator X IDE is also suitable for the needs of experienced ¢ In-Circuit Debuggers (ICD)/Programmers users.
- MPLAB Assembler/Linker/Librarian for Various Device Families
- * Simulators - MPLAB X X SIM Software Simulator
- ¢ Emulators ,
- - MPLAB REAL ICE™ In-Circuit Emulator
- ¢ In-Circuit Debuggers (ICD)/Programmers - MPLAB ICD 3/MPLAB ICD 4 - PRC EESjf™ SICit 7M 2
- Feature-Rich Editor: ¢ Color syntax highlighting : :
- * Smart code completion makes suggestions and provides hints as you type
- * Automatic code formatting based on user-defined rules
- Device Programmers - MPLAB PM3 Device: Programmer
- * Low-Cost Demonstration/Development Boards, Evaluation Kits and Starter Kits
- ¢ Third-party development tools
- Live parsing
User-Friendly, Customizable Interface:
- ¢ Fully customizable interface: toolbars, toolbar buttons, windows, window placement, etc.
- Call graph window
Project-Based Workspaces:
- ¢ Multiple projects
- « Multiple tools
- ¢ Multiple configurations
- Simultaneous debugging sessions
- File History and Bug Tracking:
- ¢ Local file history feature
- ¢ Built-in support for Bugzilla issue tracker
me © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 629
PIC32MZ W1 and WFI32E01 Family seman 39.2 MPLAB XC Compilers 39.4. MPLINK Object Linker/ The MPLAB XC Compilers are complete ANSI C MPLIB Object Librarian compilers for all of Microchip's 8, 16, and 32-bit MCU The MPLINK Object Linker combines relocatable and DSC devices. These compilers provide powerful objects created by the MPASM Assembler. It can link integration capabilities, superior code optimization and relocatable objects from precompiled libraries, using ease of use. MPLAB XC Compilers run on Windows, directives from a linker script. Pane ey eer ae
The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When aroutine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include:
For easy source level debugging,; the compilers; provide; debug information that is optimized to the MPLAB X IDE. The free MPLAB XC Compiler editions support all devices and commands, with no time or memory restrictions, and offer sufficient code optimization for Iabieeeniareralraated
¢ Efficient linking of single libraries instead of many MPLAB XC Compilers include an assembler, linker and smaller files utilities. The assembler generates relocatable object + Enhanced code maintainability by grouping files that can then be archived or linked with other relorelated modules together catable object files and archives to create an execut. . . . . i : able ¢ Flexible creation of libraries with easy module file. MPLAB XC Compiler uses the assembler to listi | t deleti d extract produce its object file. Notable features of the assemSURG PEP Coen, Seden ABE execu bler include: . ; . ; 39.5 MPLAB Assembler, Linker and ¢ Support for the entire device instruction set 3 e : ¢ Support for fixed-point; ; and floating-point; ; data Librarian- for Various Device * Command-line_ interface Families * Rich directive set MPLAB Assembler produces relocatable machine MPLS wa. and ds evices. ompiler SDE Ganipsibliy uses the assembler to produce its object file. The 39.3 assembler generates relocatable object files that can MPASM Assembler then be archived or linked with other relocatable object The MPASM Assembler is a full-featured, universal files and archives to create an Seauiebe file. Notable macro assembler for PIC10/12/16/18 MCUs. ATONE aN TEES ASSN SINE The MPASM Assembler generates relocatable object * Support for the eniite device Instruction ae files for the MPLINK Object Linker, Intel® standard HEX * Support for fixed-point and floating-point data files, MAP files to detail memory usage and symbol * Command-line interface reference, absolute LST files that contain source lines * Rich directive set and generated machine code, and COFF files for * Flexible macro language debugging.TheialMPASM Assembler features include: * MPLABX IDE compatibility
- ¢ Integration into MPLAB X IDE projects
- ¢ User-defined macros to streamline
- assembly code
- ¢ Conditional assembly for multipurpose source files
- ¢ Directives that allow complete control over the assembly process
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PIC32MZ W1 and WFI32E01 Family smn 39.6 MPLAB X SIM Software Simulator 39.8 MPLAB ICD 3 and MPLAB ICD 4 The MPLAB X SIM Software Simulator allows code In-Circuit Debugger System developmenting in a PC-hosted environment by simulatThe MPLAB ICD 3 and MPLABICD4 In-Circuit Debugthe PIC MCUs and dsPIC DSCs on an instruction ger are Microchip’s most cost-effective, high-speed level. On any given instruction, the data areas can be hardware debugger/programmer for Microchip Flash examined or modified and stimuli can be applied from DSC and MCU devices. It debugs and programs PIC a comprehensive stimulus controller. Registers can be Flash MCUs and dsPIC DSCs with the powerful, yet logged to files for further run-time analysis. The trace easy-to-use GUI of the MPLAB IDE. buffer and logic analyzer display extend the power of The MPLAB ICD 3 or MPLAB ICD4 In-Circuit Debugthe simulator to record and track program execution, : . . actions on I/O, , most peripherals and internal registers. ger paoatie BS ROOnEwM Ione PO Bei 4 Highspeed The MPLAB X SIM Software Simulator; fully supports viaUSBa 2.0Microchipinterfacedebugand can(RJ-11)be connectedconnector to(compatiblethe target symbolic debugging using the MPLAB XC Compilers, with MPLAB ICD 2 and MPLAB REAL ICE systems). and the MPASM and MPLAB Assemblers. The softMPLAB ICD 3 and MPLAB ICD4 supports all MPLAB ware simulator offers the flexibility to develop and ICD 2 headers. debug code outside of the hardware laboratory environment, making it an excellent, economical software 39.9 PICkit 3 and PICkit 4 In-Circuit development tool. Debugger/Programmer 39.7 MPLAB REAL ICE In-Circuit The MPLAB PICkit 3 and PICkit4 In-Circuit Debugger/ Emulator System Programmer are hardware debugger/programmer for the vroe en ICE erta emulator ace; pointPIC and usingdsPIC the powerfulFlash MCUs GUI atof thea most MPLABaffordableIDE. price Se ee eee Sal The MPLAB PICkit 3 or PICkit 4 is connected to the PC Microchip Flash DSC and MCU devices. It debugs and : . programs all 8, 16 and 32-bit; MCU, and DSC devices. using a full-speed: USB: interface: and can be connected with the easy-to-use, powerful GUI of the MPLAB X IDE to the target via a Microchip debug (RJ-11) connector , : (compatible with MPLAB ICD 3, MPLAB ICD 4 and The emulator is connected to the design engineer’s MPLAB REAL ICE). The connector uses two device PC using a high-speed USB 2.0 interface and is /O pins and the Reset line to implement In-Circuit connected to the target with either a connector Debugging and In-Circuit Serial Programming™ compatible with in-circuit debugger systems (RJ-11) (ICSP™). or with the new high-speed, noise tolerant, LowMan Differential Signal (LVDS) interconnection 39.10 MPLAB PM3 Device Programmer The emulator is field upgradable through future firmware The MPLAB PMS Device Programmer is a universal, downloads in MPLAB X IDE. MPLAB REAL ICE offers CE compliant device programmer with programmable significant advantages over competitive emulators voltage verification at VDDMIN and VDDMAX for including full-speed emulation, run-time variable maximum reliability. It features a large LCD display watches, trace analysis, complex breakpoints, logic (128 x 64) for menus and error messages, and a modprobes, a ruggedized probe interface and long (up to ular, detachable socket assembly to support various three meters) interconnection cables. package types. The ICSP cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices, and incorporates an MMC card for file storage and data applications.
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## PIC32MZ W1 and WFI32E01 Family seman
## 39.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits
A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards supporta variety offeatures, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various MCU applications.
39.12 Third-Party Development Tools Microchip also offers a great collection of tools from third-party vendors. These tools are carefully selected to offer good value and unique functionality.
- Device Programmers and Gang Programmers from companies, such as SoftLog and CCS
- Software Tools from companies, such as Gimpel and Trace Systems
- Protocol Analyzers from companies, such as Saleae and Total Phase
- Demonstration Boards from companies, such as MikroElektronika, Digilent® and Olimex
- + Embedded Ethernet Solutions from companies such as EZ Web Lynx, WlZnet and IPLogika®
In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip hasa line of evaluation kits and demonstration software for analog filter design, KEELO@® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more.
Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board.
Check the Microchip website (www.microchip.com) for the complete list of demonstration, development and evaluation kits.
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## PIC32MZ W1 and WFI32E01 Family smn 40.0 ELECTRICAL SPECIFICATIONS
This chapter provides the electrical specifications and characteristics of the PIC32MZ W1 SoC and WFI32E01 module.
## 40.1 PIC32MZ W1 Electrical Specifications
The absolute maximum ratings for the PIC32MZ W1 devices are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these or any other conditions, above the parameters indicated in the operation listings of this specification, is not implied.
## Absolute Maximum Ratings
|Ambient temperature Under DiaS................ccceeceeecccccecceececensceaeeeeceeeceeeesessessssessaseeeeeeseeeceeseesssssessteeesseeees<br>40°C to +105°C|
|---|
|StOrage tSMPSratune cecseeccveccrmarcvevesmeeneuevaneeanvennemmewecmenemerenuenvien<br>meeeereeneeecareureneerinmeeeveneess HOO CAO F150°C|
|Voltage on VDD with respect tO VSS oo...ccccccecceecessecesssseeeeseesseeceeesssseseceesesssesessrtteeeerestssessestsssesessesss<br>70.3V to +4.0V|
|Voltage on any pin that is not5V tolerant, with respect toNSS)©EC) Ce) (VDD + 0.3V)|
|Voltage on any 5V tolerant pin with respect to VSswhen VDD =DBS) oencctttenteittttatinciincs<br>LO3V6 (VDD + 0.3V)|
|Voltage on any 5V tolerant pin with respect to Vsswhen VDD < 2.3V03) ooocececcesesseseeseesesesseseeeees -0.3V to +5.25V|
|Voltage on D+ or D- pin with respect to VUSB3V3.............cceceeceeeeeeeeseeeeeeeeeteseeteetsessessssessseeees<br>70.3V to (VUSB3V3 + 0.3V)|
|Voltage on VBUS with respect to VSS ooo...<br>ieeecceceeesssceeceeeesseceessneeseeseesseeeeeeceeeesesessssstttmtttssesseeeeeseeeess “O.3V to +5.25V|
|Maximumrcurréent OUb OT/V/SS) PINS)teececocuenerweninteenenniiitd<br>onenwenn idseens<br>ewoeuiewereenbeerereeieaeremeeemeeee 240 IMA|
|Maximum current intoVDD pin(s)@) veceseaeeaaeeeaneeeeeecccecenecsuueeeaeeeeceeececeseneceesesesesaeeecseeeeeeceeseeeseeesssesststtttteseeeeeeeeeee240MA|
|Maximum currentsunk/sourced byany4x I/O pin'4) aleesSleennale3RUS3 MinnaleianaDBotUNE2 con saleRRUtSBinealee GoUMe2Ginte ennSieZEI 2 Einex'anenestealil<br>OMTIAN|
|Maximum currentsunk/sourced byany 8x I/O pirn4) ooo.eeecececesecececeeececseseseeeseseeesveseveveesveveesveveteeetetsesereeeereeeee25 MA|
|MaximumrGurrent SUNK DY SIiP OMSvccscerssarsimanennmenenennecmx**n**nn<br>rencenaeremneremennnmen nes100 TMA|
|Maximum currentsourced by all POrts ey occceecseessessesseeesesessesenssesevsessstesesetsessesseesessessevetsstesteetseeetseteseeseeeeeee 150 mA|
|ESD Qualification:|
|Human Body Model (HBM) (JEDEC JS-001-2017) o.....ceecccceececcceccceceecceeeeeeeeseeceeeeeeceseeeesaeeeeeeeeeseetestseestsetseesesess»<br>2000V|
|Changed Device Model (CDM) (JEDEC JS-002-2018) oo...ccccccccccccceseeeecseeeeeeceeeeeeeneeeeceeeesseeeetseeestatsessesesseeee<br>OOOV|
- Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions, above those indicated in the operation listings of this specification, is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
- 2: The maximum allowable current is a function of the device maximum power dissipation.
- 3: See Table 3 for the pin names of the 5V tolerant pins.
- 4: Characterized, but not tested. Refer to parameters DO10 and DO20 for the 4x and 8x I/O pin lists.
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## TABLE 40-1: THERMAL OPERATING CONDITIONS
|Industrial Temperature Devices||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
|Operating junction temperature range|TJ||-40||||||+125||°C|
|Operating ambient temperature range|TA||-40||||||+105||aC|
|Power dissipation:|||PINT||+ Pi/o||||||Ww|
|Internal chip power dissipation:||||||||||||
|PINT = VDD x (IDD — 2 IOH)||||||||||||
|/O pin power dissipation:||||||||||||
|Pio = X (({VDD — VOH} x IOH) + & (VOL x IOL))||||||||||||
|Maximum allowed power dissipation|||(TJ —||TA)/OJA|||||||
|TABLE 40-2:<br>THERMAL PACKAGING CHARACTERISTICS||||||||||||
|Package thermal resistance, 132-pin DQFN (10x10x0.9mm)<br>a||||ee|||ee|||ee|eee|
|Note<br>1:<br>Junction to ambient thermal resistance, Theta-JA (9JA) numbers are||||achieved by||||package||simulations.||
|TABLE 40-3:<br>RECOMMENDED OPERATING CONDITIONS||||||||||||
||Standard Operating Conditions:||||||2.97V to 3.63V|||||
|DC CHARACTERISTICS|(unless otherwise stated)|||||||||||
||Operating temperature|||-40°C||<TA<+105°C||||||
|rocTo[vo<br>|Suppyvoltage”<br>———=Ss(ao7|ss|ifs||||it|||||Cis|
|GNDDB|Common EDP ground|Vss<br>Vss|||Vss||||Vv||||
|reference||||||||||||
|Note<br>1:<br>Overall functional device operation atVBORMIN < VDD < VDDMIN is|||guaranteed,||||but not||characterized. All|||
|deviceAnalog modules, such asADC, etc., will function, but with degraded||||||performance below VDDMIN.||||||
|40.1.1<br>DC CHARACTERISTICS||||||||||||
|TABLE 40-4:<br>POR ELECTRICAL CHARACTERISTICS||||||||||||
||Standard Operating Conditions: 2.97V to||||||||3.63V|||
|DC CHARACTERISTICS|(unless otherwise stated)|||||||||||
||Operating temperature|||-40°C <TA<+105°C||TA<+105°C||||||
|DC16<br>VPOR<br>VDD start voltage|5||||Vv|||||||
|to ensure internal||||||||||||
|POR signal ()||||||||||||
|DC17<br>SVDD<br>VDD rise rate|0.03|0.115|||Vims|||110-28.7 ms at 3.3V||||
|to ensure internal||||||||||||
|PORsignal||||||||||||
## 40.1.1 DC CHARACTERISTICS
Note 1: This is the limit to which VDD must be lowered to ensure POR.
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## TABLE 40-5: BOR ELECTRICAL CHARACTERISTICS
**==> picture [454 x 125] intentionally omitted <==**
**----- Start of picture text -----**<br>
DC CHARACTERISTICS (unless otherwise stated)<br>pecumemane ca vcenceme<br>edBO10 ee Operating temperature -40°C <TA<+105°C<br>poreNote 1:[erVBORParameters TremorBORare eventfor design on VpbDguidance transitiononly andPP{2.75are not tested in2.8manufacturing.V<br>2: Overall functional device operation at VBORMIN < VDD < VDDMIN is tested, but not characterized. All device<br>Analog modules, such as ADC, etc., will function, but with degraded performance below VDDMIN.<br>**----- End of picture text -----**<br>
**==> picture [455 x 220] intentionally omitted <==**
**----- Start of picture text -----**<br>
TABLE 40-6: OPERATING CURRENT (IDpD, RF = OFF)(")(2)<br>CHARACTERISTICS (unless otherwise stated)<br>oneDC Operating—<——,temperature -40°C ee< TA< +105°C<br>[param.No.|Typ.©) [wax__|units__|Conditims<br>ooze [7 [SSCA SC*d@SWPRV SSCS<br>[oeata_ 12 |= mA 40. MHz (POSCinHSmode)<br>focaza_f23 «f= [———S*dtmA—=«*dtGOMHz(POSCinHS]<br>joozsa_ mode +SPLU) SSCS<br>joczs fa[28 [——«d———S—=*dmA_—_—=«*TOO] —~[— [mA |80MHz(POSCinHSmode+SPLU<br>—«[———~—=*dimA_—_—=«<br>joozs [a2 MHz (POSCInHS mode+SPL =<br>SPL]<br>jocas [45 [= [mA [202 0 M Hz2 (POS GC in HSHSmo mo de +SPL]<br>Note 1: Adevice’s IDD supply current is mainly a function of the operating voltage and frequency. Other factors,<br>such as PBCLK (Peripheral Bus Clock) frequency, number of peripheral modules enabled, internal code<br>execution pattern, execution from Program Flash memory vs. SRAM, I/O pin loading and switching rate,<br>oscillator type, as well as, temperature, can have an impact on the current consumption.<br>**----- End of picture text -----**<br>
- 2: The test conditions for IDD measurements are as follows:
- ¢ CPU, Flash Panel and SRAM data memory are operational.
- ¢ All peripheral modules are disabled (ON bit = 0) but the associated PMD bit is cleared.
- ¢ Sysclk: PBCLK= 1:2.
- ¢ WDT and FSCM are disabled.
- ¢ All I/O pins are configured as inputs and pulled to Vss.
- MCLR = Vpb.
- 3: Data in the “Typical” column is at 3.3V, 25°C unless otherwise stated.
- 4: This parameter is characterized, but not tested in manufacturing.
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PIC32MZ W1 and WFI32E01 Family —ne)
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**----- Start of picture text -----**<br>
TABLE 40-7: IDLE CURRENT (IIDLE, RF = OFF)<br>CHARACTERISTICS (unless otherwise stated)<br>eeDC | —_———, see<br>Param No [ye [wax [unitsOperating temperature[Conditions-40°C < TA< +105°C SSSCSCS~C~*<br>ooso ef SSSA CdR)<br>oost «dt [—SC~*S*S*~*~*diMAA~C~*dO] SOSC~C~—SCSC*YHZ (POSG NHS OGE)——SSCSC~*Y<br>jocsa—ifat_——«dt—<br>—«t————~dimA~—~=«diSOMH2(POSCinHS<br>focssocse fas(28S Sim(mA =[6000 MHz MHZ(POSCinHSmode+ (POSCinHSmodemode + SPL) S+S P LUM)L —————*S——S—=*=i<br>ocss—«a8SS*SSC*diA~~=«*dQOMHz<br>focss (POS in HSmode +SPL] =i<br>Note1: __[s8__[—The test conditions for IIDLE_|mA__|200current measurements MHzare (POSCinHSmodeas follows: +SPL] ——SSC—=*S<br>**----- End of picture text -----**<br>
- Sysclk: PBCLK= 1:1.
- CPU in Idle mode (CPU core Halted).
- ¢ All peripheral modules are disabled (ON bit = 0), but the associated PMD bit is cleared.
- ¢« WDT and FSCM are disabled.
- ¢ All I/O pins are configured as inputs and pulled to Vss.
- MCLR = Vpp.
- 2: Data in the “Typical” column is at 3.3V, TA=25°C unless otherwise stated.
- 3: This parameter is characterized, but not tested in manufacturing.
**==> picture [460 x 199] intentionally omitted <==**
**----- Start of picture text -----**<br>
TABLE 40-8: POWER-DOWN CURRENT (IPD)<br>CHARACTERISTICS (unless otherwise stated)<br>aeDC —————-- song<br>Param.No. [We [Max [UnitsOperating temperature[Conations -40°C < TA < +105°C<br>cae [eSSCdACSCSSOSCS~SCS<br>aA<br>a<br>a<br>poate [5 SSSS*dA «(WT current wor SOS~—~SCSY<br>foceae[8 ‘(| mA__|RTOG + Timert with 32 KHz Crystal AIRToS™<br>jocase [5 SS«dSSC~*mAC«*ADAMS<br>Note 1: The test conditions for IPD current measurements are as follows:<br>**----- End of picture text -----**<br>
- ¢ All peripheral modules and clocks shut down (ON = 0, PMDx = 1)
- ¢ CPU clock is disabled.
- ¢ All I/Os are configured as inputs and pulled low.
- ¢ WDT and FSCM are disabled.
- 2: Data in the “Typical” column is at 3.3V, TA=25°C unless otherwise stated.
- 3: The A current is the additional current consumed when the module is enabled. This current should be added to the base IPD current.
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PIC32MZ W1 and WFI32E01 Family smn
|TABLE|TABLE|40-9:|I/O PIN INPUT SPECIFICATIONS|I/O PIN INPUT SPECIFICATIONS||||
|---|---|---|---|---|---|---|---|
|||||Standard Operating Conditions: 2.97Vto 3.63V (unless otherwise||||
|DC CHARACTERISTICS||||stated)||||
|||||Operating temperature|-40°C <TA<+105°C|||
|||VIL|Input low voltage|||||
|DI10|||I/O pins|Vss|0.2* VpD||V||
|DI18|||SDAx, SCLx|Vss|0.3*Vop||V|SMBus disabled"*)|
|DI19|||SDAx, SCLx|Vss|0.8|V|SMBus enabled(4)|
|||VIH|Input high voltage|||||
|DI20|||I/O pins not 5V-tolerant|0.80 *VoD|VbD|V|(4)|
||||/O pins 5V-tolerant with||0.80 *Vop|5.5|Vv|(4)|
||||PMP|||||
||||I/O pins 5\V-tolerant|0.80 *VpD|5.5:|V||
|DI28a|||SDAx, SCLxon non-5V_—_‘|0.80 *VoD||VppD|V|SMBus disabled")|
||||tolerant pins|||||
|DI29a|||SDAx, SCLx on non-5V|2.3|VDD|V|SMBus enabled,|
||||tolerant pins||||2.3V <VPIN < 5.5(4)|
|DI28b|||SDAx, SCLx on 5V|0.80 *Vpb|55|V|SMBus disabled"*)|
||||tolerant pins|||||
|DI29b|||SDAx, SCLx on 5V<br>tolerant pins|2.3|55|Vv|SMBus enabled,<br>2.3V < VPIN < 5.5(4)|
|DI30||IcCNPU||Change notification<br>pull-up current||-40|yA|VDD = 3.3V, VPIN =<br>Vss')|
|DI31||ICNPD|Change notification<br>pull-down current(4)|40||yA|VDD = 3.3V, VPIN = VDD|
|||NL|Inputleakage current’)|||||
|DI50|||/O ports||+1|yA|Vss < VPIN < VDD,|
||||||||Pin at high-impedance|
|DI51|||Analog input pins||+1|yA|Vss < VPIN < VDD,|
||||||||Pin at high-impedance|
|DI55|||MCLRI?)||+1|uA||Vss<VPIN<VDD|
|DI56|||XTAL_IN||+1|yA|Vss < VPIN <VDD,|
||||||||HS mode|
|Note|1:|Datainthe“Typ.”columnisat3.3V,||+25°Cunlessotherwise|stated.|||
- 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.
- 3: Negative current is defined as current sourced by the pin.
- 4: This parameter is characterized, but not tested in manufacturing.
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## PIC32MZ W1 and WFI32E01 Family
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TABLE 40-10: I/O PINOUTPUT SPECIFICATIONS
||||Standard Operating Conditions: 2.97V to 3.63V|Standard Operating Conditions: 2.97V to 3.63V|Standard Operating Conditions: 2.97V to 3.63V|Standard Operating Conditions: 2.97V to 3.63V||||
|---|---|---|---|---|---|---|---|---|---|
|DC CHARACTERISTICS|||(unless otherwise||stated)|||||
||||Operating temperature -40°C|||< TA< +105°C||||
||Symbol|| Characteristic|min. /typ. (Max. unitsConditions|||||||
|||Output low voltage||||||||
|||I/O pins:||||||||
|||4x sink driver pins -||0.4|Vv|loL<br>< 10 mA, VDD|=||3.3V|
|||RA2-RA10, RA12-RA15, RBO-||||||||
|||RB13, RC9-RC12, RKO-RK12||||||||
|DO10||VoL|Outputlowvoltage||||||||
|||I/O pins:||||||||
|||8x sink driver pins -<br>RAO, RA1, RA11, RCO,||0.4|Vv|loL < 15 mA,VDD|_<br> =3.3V||3.3V|
|||RC1,RC8, RC9, RC13, RC14,||||||||
|||RC15, RK13, RK14||||||||
|||Output high voltage||||||||
|||I/O pins:||||||||
|||4x source driver pins -|2.4||Vv|IOH > -10 mA, VDD||= 3.3V||
|||RA2-RA10, RA12-RA15, RBO-||||||||
|||RB13, RC9-RC12, RKO-RK12||||||||
|DO20_|=|VOH|Outputhigh voltage||||||||
|||I/O pins:||||||||
|||8x source driver pins -<br>RAO, RA1, RA11, RCO,|2.4||V|_<br>IOH<br>>-15 mA,VDD<br>= 3.3V||||
|||RC1,RC8, RC9, RC13, RC14,||||||||
|||RC15, RK13, RK14||||||||
|DO20a|Outputhigh voltage<br>I/O pins:<br>4x sourcedriverpins -<br>RA2-RA10, RA12-RA15, RBO-<br>RB13, RC9-RC12, RKO-RK12_—<br>|VoH1 —_|Outputhigh voltage<br>I/O pins:<br>8xsource driverpins -<br>RAO, RA1, RA11, RCO,||45 |— <br>20 |— <br>|9-9<br>as |— <br>20 J|—||[— <br> [— <br> |— <br> |—||v<br>|lon>-14ma, voo=<br> |v | IOH=-12mA,VDD=<br>_<br>¥<br>A 2<br>REEE<br> |v | loH>-22mA,VoD=<br> |v | IOH2-18mA,VDD=|||=3.3v<br>=3.3V<br>Bee<br>=3.3V<br>=3.3V||
|||RC1,RC8, RCY, RC13, RC14,|3.0||V|IOH > -10 mA, VDD||= 3.3V||
|||RC15,RK13,RK14||||||||
Note 1: Parameters are characterized, but not tested in manufacturing.
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## 40.1.2 AC CHARACTERISTICS AND TIMING PARAMETERS
The information contained in this section defines the PIC32MZ W1 device AC characteristics and timing parameters.
## FIGURE 40-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
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Load Condition 1 — for all pins except XTAL_OUT<br>Vpbp/2<br>RL<br>Pj CL * RL=4640<br>in Ty * C, =50 pF for all pins except XTAL_OUT<br>Vss * C, = 12 pF for XTAL_OUT output<br>**----- End of picture text -----**<br>
TABLE 40-11: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS
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||||||||||
|---|---|---|---|---|---|---|---|---|
|Standard|Operating|Conditions:|2.97V|to|3.63V|
|AC|CHARACTERISTICS|(unless|otherwise|stated)|
|Operating|temperature|-40°C|< TA<|+105°C|
|DOS6||CL|All|I/O|pins|(except|pins|50|pF|
|used|as|CxOUT)|
|D088|[es|| SOLx, SDAx|—[-___[400for|[in Fe mode|
**----- End of picture text -----**<br>
Note 1: Data in the “Typ.” column is at 3.3V, +25°C unless otherwise stated.
SS © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 639
## PIC32MZ W1 and WFI32E01 Family
## seman
FIGURE 40-2: CRYSTAL OSCILLATOR TIMING CHARACTERISTICS
|||||i'+— 0S20—>:|-0S30,|-0S30,|.<br>_OS31_|_OS31_|||
|---|---|---|---|---|---|---|---|---|---|---|
|XTAL_IN SJ \<br>Fk<br>\ FV|||||'|RL <br>mm<br>1||RF<br>—||\|
|||||||‘|"0s30<br>‘||OS31||
|TABLE|TABLE|40-12:|CRYSTAL OSCILLATOR TIMING REQUIREMENTS||||||||
|||||||Standard Operating Conditions: 2.97V to 3.63V|||||
|AC CHARACTERISTICS||||||(unless otherwise stated)|||||
|||||||Operating temperature|||-40°C < TA< +105°C||
|FOSTS[Fose|||[Primary oscillator crystalfrequency)<br>Frequency stability — temperature and|||[— <br>-20|[40|[— <br>20|[MHz <br>ppm|[—|
|||||aging(*)|||||||
|OS15||||Secondary oscillatorcrystalfrequency)||—|| 32.768|I—||kHz||Sosc|
|||||Frequency stability —- temperature and||-100||100||ppm||
|||||aging")|||||||
|OS20||Tosc|||Tosc|||1/Fosc|||See parameter|
|||||||||||0S$13 for Fosc|
|||||||||||value|
|OS40_|=|TosT|||Oscillator start-up timer period|||1024||Tosc||
|||||(Only applies to HS, HSPLL and Sosc|||||||
|||||Clock Oscillator modes)|||||||
|OS42|||Gm||External oscillator transconductance|||16||HA/V||VDD = 3.3V,|
|||||||||||TA = +25°C|
|||Cosco|||XTAL_OUT pin capacitive load||||12|pF|VDD = 3.3V,|
|||||||||||TA = +25°C|
|Note|1:|Crystal||oscillatorrequirements:|||||||
TABLE 40-12: CRYSTAL OSCILLATOR TIMING REQUIREMENTS
- Crystal load capacitance = 12 pF
- ESR = 50Q
- ¢ Maximum Drive level = 200 pW
- 2: Correct oscillator and associated components selection are critical to meet these specifications.
- 3: This parameter is characterized, but not tested in manufacturing.
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PIC32MZ W1 and WFI32E01 Family
smn
## TABLE 40-13: SYSTEM TIMING REQUIREMENTS
Standard Operating Conditions: 2.97V to 3.63V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C < TA< +105°C jossi[Fsvs [Systemfrequency[DC [— «(200 MHz |— TABLE 40-14: PLL CLOCK TIMING SPECIFICATIONS Standard Operating Conditions: 2.97V to 3.63V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C < TA< +105°C _[40___|MHz_| BTPLL mode OS60_ [Fn |PLLinputfrequencyrange [@ [— OS52_ =| TLOCK PLL start-up time (lock time) 256xR |us R = Divide reference period PLL output frequency range 116 ==|— [200 [MHz | Non-bypass mode
## TABLE 40-14: PLL CLOCK TIMING SPECIFICATIONS
Note 1: These parameters are characterized, but not tested in manufacturing.
## TABLE 40-15: INTERNAL FRC ACCURACY
Standard Operating Conditions: 2.97V to 3.63V AC CHARACTERISTICS (unless otherwise stated) Operating temperature-40°C < TA < +105°C
Internal FRC Accuracy @ 8.00 MHz'") roo [enc —s«dOS [SOO OC[SOOC~—SSOCC] Note 1: Frequency calibrated at +25°C and 3.3V. The TUN bits (OSCTUN<5:0>) can be used to compensate for temperature drift.
TABLE 40-16: INTERNAL LPRC ACCURACY
Standard Operating Conditions: 2.97V to 3.63V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C < TA< +105°C Internal LPRC @ 32.768 kHz")
Note 1: Change of LPRC frequency as VDD changes.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 641
## PIC32MZ W1 and WFI32E01 Family
## seman
|FIGURE 40-3:|FIGURE 40-3:|1/0 TIMING CHARACTERISTICS|1/0 TIMING CHARACTERISTICS|||||
|---|---|---|---|---|---|---|---|
||/O Pin|||||||
||(Input)|||||||
||||DBs|||||
|||||DI40||||
||/O Pin|||||||
|(Output)||v\||||||
|||— =|D031|||||
|Note: Referto||Figure 40-1 forload conditions.|D032|||||
|TABLE|TABLE 40-17:|I/O TIMING REQUIREMENTS||||||
|||Standard|Operating Conditions: 2.97V to|||3.63V||
|AC CHARACTERISTICS<br>(unless otherwise||||stated)||||
|||Operating|temperature||-40°C <TA< +105°C|||
|DO31||TioR|—|Portoutputrisetime<br>I/O pins:|I—|{—|{— ~—{95|{ns|| CLoap = 50pF|
|||4x source driver pins -<br>RA2-RA10, RA12-RA15, RBO-RB13,|||||CLOAD = 20 pF|
|||RC9-RC12, RKO-RK12||||||
|||I/O pins:||||||
|||8x source driver pins -||||||
|||RAO, RA1, RA11, RCO, RC1,RC8,|||||CLOAD = 20 pF|
|||RC9, RC13, RC14, RC15, RK13,||||||
|||RK14||||||
|D032||TioF||Portoutputfalltime<br>I/O pins:|—|||— |95 |ns||ns||Cioap=50 pF|
|||4x source driver pins -<br>RA2-RA10, RA12-RA15, RBO-RB13,||||ns|CLOAD = 20 pF|
|||RC9-RC12, RKO-RK12||||||
|||I/O pins:||||||
|||8x source driver pins -||||||
|||RAO, RA1, RA11, RCO, RC1,RC8,||||ns|CLOAD = 20 pF|
|||RC9, RC13, RC14, RC15, RK13,||||||
|||RK14||||||
## TABLE 40-17: I/O TIMING REQUIREMENTS
Note 1: Data inthe “Typ.” column is at 3.3V, +25°C unless otherwise stated. 2: This parameter is characterized, but not tested in manufacturing.
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PIC32MZ W1 and WFI32E01 Family
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FIGURE 40-4: POWER-ON RESET TIMING CHARACTERISTICS<br>Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL and LPRC)<br>VDD<br>me ; 4 (Note 2)<br>; (TPMUDLY) (TSYSDLY)<br>1 ' SY01 _ SY02 :<br>1 ——_—_———_> <-><br>Power-up(Note 2) Sequence WjjYYyyHNNV 5<br>soo rt CPU Starts Fetching Code<br>(TPU)<br>(Note 1)<br>Clock Sources = (HS, HSPLL and Sosc)<br>VDD<br>VPOR (Note 2)<br>(TPMUDLY) (TSYSDLY)<br>1 : SY01 : _SY02 |<br>1 >—!_!_—_* =><br><> —— ~¢#— CPU Starts Fetching<br>SYyoo ' : SY10 ' ' Code<br>(TPU) (TOsT)<br>(Note 1)<br>Note 1: The power-up period will be extended if the power-up sequence completes before the device exits from BOR (VDD<br>< VBORMmax).<br>2: SY01 is negligible when PMU is retained in MLDO mode.<br>**----- End of picture text -----**<br>
© 2020 Microchip Technology Inc.
Preliminary Data Sheet
DS70005425A-page 643
## PIC32MZ W1 and WFI32E01 Family
## seman
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FIGURE 40-5: EXTERNAL RESET TIMING CHARACTERISTICS<br>Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL and LPRC)<br>MCLR \ /:<br><———> |<br>' TMCLR 11<br>, (SY20) * |<br>BOR= allpwr_valid_mv \} z 5<br>—'<br>,TBOR ', (TSYSDLY)<br>1 (SY30)_—' sYo1: Sy02:<br>Reset Sequence— Es;<br>(TeMUDLY) '~¢—— CPU Starts Fetching Code<br>Clock Sources = (POSC and SOSC) ' ' (TSYSDLY)<br>; ' SY01, . SY02<br>1 1 ‘ = —<? _<br>(TPMUDLY) <> '~t——. CPU Starts Fetching<br>' TOST Code<br>(SY10)<br>**----- End of picture text -----**<br>
## TABLE 40-18: RESETS TIMING
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Standard Operating Conditions: 2.97V to 3.63V<br>AC CHARACTERISTICS (unless otherwise stated)<br>Operating temperature -40°C < TA< +105°C<br>SY00 |TPU Power-up period 400 us<br>internal voltage regulator enabled<br>SY02 | TSYSDLY | System delay period: 1 us +<br>time required to reload device con- 8 SYSCLK<br>figuration fuses plus SYSCLK cycles<br>delay before first instruction is<br>fetched.<br>Note 1: These parameters are characterized, but not tested in manufacturing.<br>2: Data in the “Typ” column is at 3.3V, +25°C unless otherwise stated.<br>**----- End of picture text -----**<br>
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**----- Start of picture text -----**<br>
AC CHARACTERISTICS<br>**----- End of picture text -----**<br>
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PIC32MZ W1 and WFI32E01 Family
## smn
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FIGURE 40-6: TIMER1-TIMER7 TIMING CHARACTERISTICS<br>!|<br>TxCK || |<br>| | | | | |<br>x10 —>! +111 —» | |<br>| | |<br>1x15 +! 120 —> |<br>= 0s60 ——______» |<br>TMRx X l<br>Note: Refer to Figure 40-1 for load conditions.<br>TABLE 40-19: TIMER1 TIMING REQUIREMENTS")<br>Standard Operating Conditions: 2.97V to 3.63V<br>AC CHARACTERISTICS (unless otherwise stated)<br>Operating temperature -40°C < TA< +105°C<br>TA10 TTXH TxCK Synchronous, | [(12.5 ns or 1 T5841 cx)/N] ns Must also<br>high time _| with pres- + 20 ns ~ meet<br>caler parameter<br>TA15(°)<br>Asynchro- 10 ns<br>nous,<br>with pres-<br>caler<br>TA11 TTXL TxCKlow time withSynchronous,pres- | [(12.5+ 20 nsns or 1 Tpp4 ~cx)/N] ns Mustmeet also<br>caler parameter<br>TA15'9)<br>Asynchro- 10 ns<br>nous,<br>with pres-<br>caler<br>TA15 TTXP TxCK Synchronous, | [(Greater of 20 ns or ns VDD > 2.97V<br>input with pres- 2 Test cix)/N] + 30 ns (3)<br>period caler ~<br>Asynchro- 20 ns VDD > 2.97V<br>nous,<br>with pres-<br>caler<br>OS60 FT1 SOSCI/T1CK oscillator 32.768 50 kHz<br>input frequency range<br>(oscillator enabled by set-<br>ting TCS bit (T1CON<1>))<br>TA20 TCKEXTMRL | clockDelayedgefrom toexternaltimer TxCK 1 Tpp1 ~cLK<br>increment<br>Note 1: Timer’ is a TypeA timer.<br>2: This parameter is characterized, but not tested in manufacturing.<br>3: N= Prescale Value (1, 8, 64, 256).<br>**----- End of picture text -----**<br>
## TABLE 40-19: TIMER1 TIMING REQUIREMENTS")
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 645
## PIC32MZ W1 and WFI32E01 Family
## seman
TABLE 40-20: TIMER2-TIMER7 TIMING REQUIREMENTS
||||Standard Operating Conditions: 2.97V to 3.63V|Standard Operating Conditions: 2.97V to 3.63V|Standard Operating Conditions: 2.97V to 3.63V|Standard Operating Conditions: 2.97V to 3.63V|Standard Operating Conditions: 2.97V to 3.63V|||
|---|---|---|---|---|---|---|---|---|---|
|AC CHARACTERISTICS|||(unless otherwise stated)|||||||
||||Operating temperature||-40°C <TA< +105°C|||||
|TB10|TtxH|TxCK <br>high|= |Synchro-<br>nous, with|[(12.5 nsor1Tpp1 cix)/N] +<br>25 ns<br>~||||Must also <br>meet||N = pres-<br>cale value|
|||time|prescaler|||||parame-|| (1, 2, 4, 8,|
|||||||||terTB15|| 16, 32, 64,|
|TB11.|TtxL = |TxCK|||=[Synchro- =|[(12.5 nsor 1 Tpat cix)/NI +<br>~|||||Must also||299)|
|||low|nous, with|25 ns||||meet||
|||time|prescaler|||||parame-||
|||||||||terTB15||
|TB15|TtxP|TxCK||Synchro-|[(Greater of||||VDD >||
|||input<br>nous, with<br>period |prescaler||[(25 ns or 2Tpe1 crx)/N] +<br>30 ns||||2.97V||
|TB20|TCKEXT-|Delay||from external||1|Tpp1|cLK<br>~|||
||MRL|TXCK|clock edge to|||||||
|||timerincrement||||||||
Note 1: These parameters are characterized, but not tested in manufacturing.
## a
DS70005425A-page 646
Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
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FIGURE 40-7: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS<br>ICxa ee ee<br>'<—IC10 —*! '=— 1011!<br>'-————_ 1c15 ——><br>Note: Refer to Figure 40-1 for load conditions.<br>**----- End of picture text -----**<br>
## TABLE 40-21: INPUT CAPTURE MODULE TIMING REQUIREMENTS
||||Standard Operating Conditions: 2.97V to 3.63V|Standard Operating Conditions: 2.97V to 3.63V|Standard Operating Conditions: 2.97V to 3.63V|||
|---|---|---|---|---|---|---|---|
|AC CHARACTERISTICS|||(unless otherwise stated)|||||
||||Operating temperature||-40°C <TA< +105°C|||
|1C10|TecL|ICx input|lowtime|[(12.5 ns or <br>/N] + 25 ns|1 Tpp4 cx)<br>~|Must also |N = prescale<br>meet<br>value(1,4,16)||
|||||||parameter||
|||||||IC15.||
|1C11|TecH|ICx input|high time|[(12.5 ns or|1 Tpg4 crx)<br>~|Must also||
|||||/N] + 25 ns||meet||
|||||||parameter||
|||||||IC15.||
|1C15|TecP|ICx input|period|[(25 ns or 2|Tpg1 cx)<br>~|||
|||||/N]+50ns||||
Note 1: These parameters are characterized, but not tested in manufacturing.
## FIGURE 40-8: OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS
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**----- Start of picture text -----**<br>
(Output Compareocx f1; ;a \<br>or PWM mode) OC11 —»; 1e— OC10 -»: je<br>**----- End of picture text -----**<br>
Note: Refer to Figure 40-1 for load conditions.
## TABLE 40-22: OUTPUT COMPARE MODULE TIMING REQUIREMENTS
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**----- Start of picture text -----**<br>
Standard Operating Conditions: 2.97V to 3.63V<br>AC CHARACTERISTICS (unless otherwise stated)<br>Operating temperature -40°C < TA< +105°C<br>OC10 OCx output fall time I— +s {|—~————sd{—_~—s[ns_—_s[ See parameter D032<br>OC11 OCx output rise time — ss f|— [ns See parameter DO31<br>Note 1: These parameters are characterized, but not tested in manufacturing.<br>**----- End of picture text -----**<br>
2: Data in the “Typ.” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
OOOO___ © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 647
## PIC32MZ W1 and WFI32E01 Family
## seman
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FIGURE 40-9: SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS<br>**----- End of picture text -----**<br>
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**----- Start of picture text -----**<br>
SCKx ' y<br>; SP11 | SP10 | SP21 SP20<br>(CKPSCKx = 1)‘FYi Sf i," iFi<br>, SP35 SP20 , SP21<br>i 1 1<br>SP31 | SP30<br>| SP40'SP41!<br>Note: Refer to Figure 40-1 for load conditions.<br>TABLE 40-23: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS<br>Standard Operating Conditions: 2.97V to 3.63V<br>AC CHARACTERISTICS (unless otherwise stated)<br>Operating temperature -40°C < TA< +105°C<br>fsPi0<br>[Teck [SCKxoutputiowtime™™teow[— [— [ns [— [——i]<br>SP15__ | Tsck SPI clock speed I— |— ‘| 40_—| MHz | SPI1 on RPC6<br>20 MHz | SPI1 and SPI2 on other<br>0<br>SP20 SCKx output fall time) _— ss |— ss [— ss [ns See parameter DO32<br>SP21 SCKx output rise time) — — f|— [= [ns See parameter DO31<br>SP30 SDOx data output fall time) _— — f|— ss [— ns See parameter DO32<br>SP31 SDOx data output rise time!) _— ss |— ss [— srs See parameter DO31<br>SP35 | TscH2doV, |SDOx data output valid after 7 VDD > 2.97V<br>TscL2doV |SCKx edge<br>SP40 | TdiV2scH, | Setup time of SDIx data input 5<br>TdiV2scL_ | to SCKx edge<br>SP41 TscH2diL, | Hold time of SDIx data input 5<br>TscL2diL to SCKx edge<br>Note 1: These parameters are characterized, but not tested in manufacturing.<br>2: Data in the “Typ.” column is at 3.3V, +25°C unless otherwise stated.<br>3: The minimum clock period for SCKx is 25 ns. Therefore, the clock generated in Master mode must not<br>violate this specification.<br>**----- End of picture text -----**<br>
## TABLE 40-23: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS
4: Assumes 10 pF load on all SPIx pins. 5: To achieve maximum data rate, VDD must be > 3.3V, the SMP bit (SPIxCON<9>) must be equal to ‘1’.
renner eee e rereerence eee eee DS70005425A-page 648 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
|FIGURE 40-10:<br>SPIx MODULE MASTER|FIGURE 40-10:<br>SPIx MODULE MASTER|FIGURE 40-10:<br>SPIx MODULE MASTER|MODE|(CKE|= 1) TIMING CHARACTERISTICS|= 1) TIMING CHARACTERISTICS|
|---|---|---|---|---|---|---|
||; SP36<br>'<br>,||||||
|SCKX|||||||
|(CKP|= 0)<br>ro<br>ft<br>‘i||||/|\|
||,<br>1<br>'<br>SP11<br>1)<br>SP10|1|||SP21|SP20|
|SCKx<br>yt<br>A<br>(CKP =1)<br>ty<br>;<br>1<br>'<br>'<br>' 'SP35<br>oy<br>i|||||Ni<br>7<br>‘<br>fi<br>is<br>SP20<br>—-SP21||
||mot<br>inl Ta||||||
||sa<br>SP30,5P31||||||
||sp4g)<br>1-SPAt,||||||
|Note:|Refer to Figure 40-1 for load conditions.||||||
|TABLE 40-24:<br>SPIlx MODULE MASTER||MODE (CKE= 1) TIMING||||REQUIREMENTS|
||||Standard Operating Conditions: 2.97V to 3.63V||||
|AC CHARACTERISTICS|||(unless otherwise stated)||||
||||Operating temperature|||-40°C <TA< +105°C|
|SPIO[Teol___[SCKxoutputiowtime™)——[tsw2[—|||||[—|insfi|
|SP15_<br>SP20<br>SP21<br>SP30<br>SP31||Tsck<br>SPI clockspeed<br>SCKx output falltime)<br>SCKx output risetime!)<br>SDOxdata output falltime) <br>SDOx data output risetime)—||I—<br>=|— — _|40<br>fe ee<br>—<br>|—<br>|— <br>— [—<br>|—<br> —|—<br>|—<br>—<br>|—<br>|—|||[MHz<br>[SPI1 on RPC6<br>aieSPI1 and SPI2onotherI/O<br> Ins |See parameter DO32<br>Ins |See parameter DO31<br>Ins |See parameter DO32<br> Ins |See parameter DO31|
|SP35||TscH2doV,<br>|SDOx data output valid after||||7|VDD > 2.97V|
||TscL2doV<br>|SCKx edge||||||
|SP36||TdoV2sc,<br>|SDOx data output setup to||||7||
||TdoV2scL<br>|first SCKx edge||||||
|SP40||TdiV2scH,<br>|Setup time of SDIx data input|||7|||VDD > 2.97V|
||TdiV2scL_<br>|to SCKx edge||||||
|SP41||TscH2diL,<br>|Hold time of SDIx data input|||7|||VDD > 2.97V|
||TscL2diL<br>|toSCKxedge||||||
TABLE 40-24: SPIlx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 649
## PIC32MZ W1 and WFI32E01 Family
## seman
TABLE 40-24: SPIlx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS (CONTINUED)
||||Standard Operating Conditions: 2.97V to 3.63V|
|---|---|---|---|
|AC CHARACTERISTICS|||(unless otherwise stated)|
||||Operating temperature<br>-40°C < TA< +105°C|
|Note|1:|Theseparametersarecharacterized,butnottestedinmanufacturing.||
- 2: Data in the “Typ.” column is at 3.3V, +25°C unless otherwise stated.
- 3: The minimum clock period for SCKx is 25 ns. Therefore, the clock generated in Master mode must not violate this specification.
- 4: Assumes 10 pF load on all SPIx pins.
- 5: To achieve the maximum data rate, VDD must be = 3.3V and the SMP bit (SPIXCON<9>) must be equal to
FIGURE 40-11: SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS
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**----- Start of picture text -----**<br>
‘SP50 + 1 _SP52<br>SCKX ' = Ba<br>(CKP = 0) / \ / \ ( /' \<br>,<br>SP7T 1 SP70 SP73. SP72 ;<br>(CKP=1) | ri * :<br>‘SP35. SP72 — SP73<br>‘1©'1SP30'SP31_aSP51<br>SP40:. spay:<br>Note: Refer to Figure 40-1 for load conditions.<br>TABLE 40-25: SPIlx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS<br>Standard Operating Conditions: 2.97V to 3.63V<br>AC CHARACTERISTICS (unless otherwise stated)<br>Operating temperature -40°C < TA < +105°C<br>SP15__ | Tsck SPI clock speed I— |— [40 | MHz |SPI1 on RPC6<br>20 MHz |SPI1 and SPI2 on<br>other I/O<br>SP72 SCKx input fall time i— |— |[— [ns | See parameter DO32<br>SP73 SCKx input rise time I— |— [— [ns | See parameter DO31<br>renner eee e rereerence eee eee<br>DS70005425A-page 650 Preliminary Data Sheet © 2020 Microchip Technology Inc.<br>**----- End of picture text -----**<br>
PIC32MZ W1 and WFI32E01 Family
## smn
## TABLE 40-25: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS (CONTINUED)
||||Standard Operating Conditions:|Standard Operating Conditions:|Standard Operating Conditions:|2.97V to 3.63V|
|---|---|---|---|---|---|---|
|AC CHARACTERISTICS|||(unless otherwise stated)||||
||||Operating temperature -40°C < TA<|||< +105°C|
|SP30<br>SP31||SDOxdata output falltime<br>SDOxdata output risetime)|I— +—s—«{— ~=|—<br>I— sss[— Ss [—||[ns___|See parameterDO32<br> ss|ns_s<br>See parameterDO31||
|SP35|TscH2doV,||SDOx data output valid after||rh||VDD > 2.97V|
||TscL2doV|SCKx edge|||||
|SP40|TdiV2scH, ||Setup time of SDIx data input|5||ns||
||TdiV2scL|to SCKx edge|||||
|SP41|TscH2diL,|Hold time ofSDIx data input|5||||
||TscL2diL|to SCKx edge|||||
|SP50||TssL2scH,||SSx J toSCKx tT orSCKx input||55||||
||TssL2scL||||||
|SP51|TssH2doZ|SSx fT toSDOx output|2.5|12|||
|||high-impedance (3)|||||
|SP52|TscH2ssH|SSx after SCKx edge||15|||
||TscL2ssH||||||
Note 1: These parameters are characterized, but not tested in manufacturing.
- 2: Data in the “Typ.” column is at 3.3V, +25°C unless otherwise stated.
- 3: The minimum clock period for SCKx is 25 ns.
- 4: Assumes 10 pF load on all SPIx pins.
**==> picture [397 x 264] intentionally omitted <==**
**----- Start of picture text -----**<br>
FIGURE 40-12: SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS<br>38x SP60 ; ;<br>\e ( —,<br>'" SP50_: ' ! SP52 '<br>SCKx :—' ‘ 1 1 my e<br>(CKP = 0) fot fh Ne f ) \i /' Nt1 1:<br>| SP71': SP70= SP73 SP72<br>SCKx UN X. A<br>(CKP = 1) 1 ox : ro, a ma i<br>' ' ' f SP72 SP73 '<br>to SP30,SP31 SP51<br>SP40_)' | SP41)'<br>Note: Refer to Figure 40-1 for load conditions.<br>**----- End of picture text -----**<br>
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 651
## PIC32MZ W1 and WFI32E01 Family seman
**==> picture [456 x 374] intentionally omitted <==**
**----- Start of picture text -----**<br>
TABLE 40-26: SPIlx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS<br>Standard Operating Conditions: 2.97V to 3.63V<br>AC CHARACTERISTICS (unless otherwise stated)<br>Operating temperature -40°C < TA < +105°C<br>SP15— | Tsck SPI clock speed I— ===|— [40 | MHz_ |SPI1 on RPC6<br>20 MHz |SPI1 and SPI2 on<br>other I/O<br>SP73_|TscR___|<br>SP30 SCKx input rise time a Ce<br>SDOx data output fall time() i— [— |[— Ins | See parameter DO32<br>SP31 SDOx data output rise time) — = |— {= [ns See parameter DO31<br>SP35 TscH2doV, | [SDOx] [data] [output] [valid] [after] 10 VDD > 2.97V<br>TscL2doV |SCKx edge<br>SP40 TdiV2scH, | Setup time of SDIx data input<br>TdiV2scL | to SCKx edge<br>SP41 TscH2diL, | Hold time of SDIx data input 7<br>TscL2diL | to SCKx edge<br>SP50 ‘| TssL2scH, | SSx J to SCKx J or SCKx 7 input |55<br>TssL2scL<br>SP51 TssH2doZ | SSx fT to SDOx output 2.5) 12<br>high-impedance(4)<br>SP52 TscH2ssH | SSx 7 after SCKx Edge 10<br>TscL2ssH<br>SP60 TssL2doV |SDOx Data Output Valid after 12.5<br>SSx Edge<br>**----- End of picture text -----**<br>
- Note 1: These parameters are characterized, but not tested in manufacturing.
- 2: Data in the “Typ.” column is at 3.3V, +25°C unless otherwise stated.
- 3: The minimum clock period for SCKx is 25 ns.
- 4: Assumes 10 pF load on all SPIx pins.
renner eee e rereerence eee eee DS70005425A-page 652 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
## smn
**==> picture [446 x 447] intentionally omitted <==**
**----- Start of picture text -----**<br>
FIGURE 40-13: SQI SERIAL INPUT TIMING CHARACTERISTICS<br>SQICSO SS [ /<br>-TscKH > Tsoxt Tok»<br>SQICLK ST \ Sf \ Sf<br>TDIH<br><—Tois<br>sar] Kee XD Oo = CK _|<br>FIGURE 40-14: SQI SERIAL OUTPUT TIMING CHARACTERISTICS<br>SQICSO f<br>\¢—Teo<br>SQICS1 §§<br>TCES<br>> TCHH ¢TSCKH PHt-TSOKL ToLk ——>}¢TceH TCHS le<br>SQICLK T\ / \ sf \<br>soo le /f }¢TooH<br>cofXe<br>OX OS OC = OC<br>TABLE 40-27: SQI TIMING REQUIREMENTS<br>Standard Operating Conditions: 2.97V to 3.63V<br>AC CHARACTERISTICS (unless otherwise stated)<br>Operating temperature -40°C < TA< +105°C<br>SQi0_ |Fc.k Serial clock frequency (1/Tsal) |— |— [80 [MHz |Serial Flash mode<br>$Q13 Serial clock rise time — _|— |[— I[ns | See parameter DO31<br>SQ14 Serial clock fall time — _|— = [|— [ns _ | See parameter DO32<br>**----- End of picture text -----**<br>
Note 1: These parameters are characterized, but not tested in manufacturing.
- 2: Data in the “Typ.” column is at 3.3V, +25°C unless otherwise stated.
- 3: Assumes 10 pF load on all SQIx pins
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 653
## PIC32MZ W1 and WFI32E01 Family seman
**==> picture [434 x 300] intentionally omitted <==**
**----- Start of picture text -----**<br>
FIGURE 40-15: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)<br>tIM3O'! +S 'IM33.¢ ot<br>SDAx mt / \ ae<br>Start Condition Stop Condition<br>Note: Refer to Figure 40-1 for load conditions.<br>FIGURE 40-16: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE)<br>IM20 > *r4— ‘IMI ; oe M21<br>yy " <—IM10—» v<br>IM IM26 «> ae ;<br>‘> IM10 ' +> M25 —1M33—— '<br>SDAx ; —\, -Seuas ,<br>—+1M40—— “<—IM40— Mas<br>COTY] Mim ata%atas'ataatatatatatatatatatatatetatates hl ’ FEGH aS<br>**----- End of picture text -----**<br>
Note: Refer to Figure 40-1 for load conditions.
**==> picture [342 x 10] intentionally omitted <==**
**----- Start of picture text -----**<br>
TABLE 40-28: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE)<br>**----- End of picture text -----**<br>
**==> picture [455 x 253] intentionally omitted <==**
**----- Start of picture text -----**<br>
Standard Operating Conditions: 2.97V to 3.63V<br>AC CHARACTERISTICS (unless otherwise stated)<br>Operating temperature -40°C < TA< +105°C<br>IM10 —_|TLo:scL [Clock low time |100 kHz mode |TPBCLK*(BRG +2) |— = jus [—ss<br>400 KHz mode [Tescik*(BRG+2)[—__|us__[-—————_~d<br>{MHz mode™ [Track (BRG+2)[— us [- [——————*d]<br>M11 [THI:scL Clock high time [100 kHz mode [TPBcLK*(BRG+2) |— = Jus f——s—ssiSYT<br>400 KHz mode |Trsctk"(BRG+2)[—_|us__[-————_—t<br>MHz mode) [Trscik™(BRG*2)[— us [-——————~d<br>IM20 |TF:scL fall|SDAxandSCLx [100kHzmode ———sS*s[[— 300s [ns_—s| Cis specified to be<br>time 400 kHz mode [20+ 0.1 CB 300 [ns | from 10 to 400 pF<br>TMHzmode™[— «ATO<br>IM21 (ns<br>|TR:scL |SDAxandSCLx [100kHzmode —S*{1000—|[ns_~—_—s|Cis[— specified to be<br>rise time 400 kHz mode 120+ 0.1 CB 300 [ns | from 10 to 400 pF<br>TMHzmode™}— «(S00<br>IM25 (ns<br>[Tsu:DaT |Data input 100kHzmode [250 = = = = |—_—s|[ns_—<br>——=«d—__‘|ns__|<br>setup time faooKHzmode [100<br>TMHzmode 7100S<br>—idins<br>**----- End of picture text -----**<br>
renner eee e rereerence eee eee DS70005425A-page 654 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
**==> picture [458 x 404] intentionally omitted <==**
**----- Start of picture text -----**<br>
smn<br>TABLE 40-28: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) (CONTINUED)<br>CHARACTERISTICS (unless otherwise stated)<br>eeAC |Operating temperature——,-40°C eyo< TA< +105°C<br>a<br>IM26[THDDaT [Datainput [100KHzmode [Os [— iS<br>——SC«dOA<br>IM30 iMHzmode Jo «ds<br>TSU:STA |Start condition /100 kHz mode |TPBcLK*(BRG+2) |— — us Only relevant for<br>eS [=]<br>setuptime [400 kHz mode |TPacLK™(BRG+2) [— [us __|Repeated Start<br>IM31__|THD:sTA hold|Start condition [100 kHz mode [TpBcLK*(BRG+2)|— — [us _|After this period, the<br>time [400 kHz mode |TPBCLK*(BRG+2) [— — fuss first clock pulse is<br>eS Se<br>TEIM33__[Tsu:sTo |Stop condition [100 kHz mode |TPBCLK*(BRG+2)|— — [uss<br>[iSee<br>M34 MHz mode [Teck (BRG+2) [= [us __|<br>[THD:sTo |Stop condition [100 kHz mode |TPBCLK*(BRG+2)|— —[ns_—_<br>hold tim e [400 KHz mode [TPBCLK*(BRG<br>h +2) [—__|ns__|<br>clock 400KHzmode [———~«iaoo[ns —SSSSCS~S™<br>pe PS ee iMHzmode@)————S—*iSSOee =eSefs =<br>M45 rsd SSSSCSC—~*™<br>|TeF:sDA [Bus free time |100kHzmode[47 = = = |— [us __[<br>[bus] [must] [be] [free]<br>400 KHzmode [13 =< [__|us__|the] The amount of time<br>jivs0_Note 1: [68BRG[Busis the valuecapaciiveloadingof the I“C Baud __——«4[—-—=—=—~—~S~S~«*dAOO_—=__|Rate Generator. transmissionSee parametercanDOSS start|<br>2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).<br>**----- End of picture text -----**<br>
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 655
PIC32MZ W1 and WFI32E01 Family
## seman
**==> picture [424 x 308] intentionally omitted <==**
**----- Start of picture text -----**<br>
FIGURE 40-17: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)<br>Poot pelS8ty | tm a [llpeit]<br>oy to 115335 hos<br>Start Stop<br>Condition Condition<br>Note: Refer to Figure 40-1 for load conditions.<br>FIGURE 40-18: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)<br>IS20—-» — 'e—_1S11—_2! ' = — 1s21<br>yt tn ‘e—1S10 —e us<br>—|s30—— 1826 + rn ;<br>'— 1831 <= ' +> 1S25 —. 1S33<+— '<br>SDAx ; sae ff \<br>—1s40—— —1S40 '<—|s45<br>SDAX BVI So<br>**----- End of picture text -----**<br>
FIGURE 40-18: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)
Note: Refer to Figure 40-1 for load conditions.
TABLE 40-29: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE)
**==> picture [444 x 241] intentionally omitted <==**
**----- Start of picture text -----**<br>
Standard Operating Conditions: 2.97V to 3.63V<br>AC CHARACTERISTICS (unless otherwise stated)<br>Operating temperature -40°C < TA< +105°C<br>1S10 TLO:SCL | Clock low 100 kHz mode 47 us PBCLK must operate at<br>time a minimum of 800 kHz<br>400 kHz mode 13 us PBCLK must operate at<br>a minimum of 3.2 MHz<br>(1)<br>1S11 THI:SCL | Clock high 100 kHz mode 4.0 us PBCLK must operate at<br>time a minimum of 800 kHz<br>400 kHz mode us PBCLK must operate at<br>a minimum of 3.2 MHz<br>(1)<br>Is20.|Tr:scL |SDAxand — | 100 kHz mode I——«|{300—s|[ns_—s| Cis specified to be<br>ae 400 kHz mode 20+ 0.1 CB foie ter<br>**----- End of picture text -----**<br>
renner eee e rereerence eee eee DS70005425A-page 656 Preliminary Data Sheet © 2020 Microchip Technology Inc.
——
PIC32MZ W1 and WFI32E01 Family
|TABLE 40-29:<br>I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) (CONTINUED)|
|---|
|ee<br>ea<br>AC<br>CHARACTERISTICS<br>(unless otherwise stated)<br>Operating temperature<br>-40°C <TA< +105°C<br>aed|
|IS21.<br>|TR:scL<br>|SDAxand<br>[|100kHzmode<br>|— ~~ [1000 [ns _ |CBis specifiedtobe<br>P| feee<br>i525<br>[Tovar<br>[Datainput<br>[100KHzmode [260_—‘([—__[ns__<br>eo<br>= ==<br>Miz mode" [100<br>|—_|ns__|<br>(S26<br>|THoDAT<br>[Datainput<br>|T00KHzmode<br>[0<br>[—_|ns__<br>aa<br>————ee<br>1S30<br>TSU:STA |Startcondition/100kHzmode<br>[4700s [—_—s[ns_—s Onlyrelevantfor<br>setuptime<br>[400kHzmode<br>[600<br>#$|[—<br>[ns |Repeated Startcondition<br>aa<br>ee<br>1831<br>|THD:sta<br>|Startcondition|100kHzmode<br>{4000 ==|— —<br>|ns__|Afterthisperiod,thefirst<br>hold time<br>[400kHzmode<br>[600=<br>[—_—s_[ns_—sidclockpulse isgenerated<br>ee<br>ie|
|is34_[THD:sto<br>|Stopcondition] 100kHzmode<br>[4000 = |—_—s_[ns_||
|Fimizmode<br>[250 |__[ns__|<br>1840<br>|Taa:scL<br>[Outputvalid |100kHzmode<br>|0<br>{3500 |ns_ ||
|FiMHzmode” fo<br>___[350_|[ns__|<br>1S45<br>TBF:SDA |Busfreetime [100kHzmode =—s 4.7<br>ss [— sus<br>Theamount oftimethe<br>|400kHzmode = 1.3<br>lus busmustbefree before|
|start<br>jiss0__[Cs<br>[BusCapacitiveLoading ——‘[——‘(4oo_<br>fer [—<br>—————_—id<br>Note<br>1:<br>Maximumpincapacitance=10pFforallI2Cxpins(for<br>1MHzmodeonly).|
SS © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 657
## PIC32MZ W1 and WFI32E01 Family
## seman
FIGURE 40-19: CANx MODULE I/O TIMING CHARACTERISTICS
|fontaath|fontaath|Old Value|Vé|||'|NewValue|
|---|---|---|---|---|---|---|---|
|||CA10 CAN||||||
|CiRx Pin||f||||||
|(input)||N||||'||
||||CA20|||||
|TABLE 40-30:||CANx MODULE I/O TIMING|REQUIREMENTS|||||
||||Standard Operating Conditions: 2.97V to 3.63V|||||
|AC CHARACTERISTICS|||(unless otherwise stated)|||||
||||Operating temperature||-40°C <TA< +105°C|||
|CA10<br>CA11||Portoutput fall time<br>Portoutput risetime|—|—<br>—[—|[—<br>[—|[ns <br>Ins||See parameter DO32<br> |See parameterDO31||
|CA20||TCWF|Pulse width to trigger|700|||||
|||CAN wake-up filter (CAN only)||||||
|CA20_||TCWF|Pulse width to trigger|700|||||
|||CAN wake-up filter||||||
|||(CAN-FDOnly)||||||
## TABLE 40-30: CANx MODULE I/O TIMING REQUIREMENTS
Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in the “Typ” column is at 3.3V, +25°C unless otherwise stated.
renner eee e rereerence eee eee DS70005425A-page 658 Preliminary Data Sheet © 2020 Microchip Technology Inc.
## PIC32MZ W1 and WFI32E01 Family
## smn
## TABLE 40-31: ADC MODULE SPECIFICATIONS)
|||||Standard Operating|Conditions: 2.97V to 3.63V|Conditions: 2.97V to 3.63V|Conditions: 2.97V to 3.63V|Conditions: 2.97V to 3.63V|
|---|---|---|---|---|---|---|---|---|
|AC CHARACTERISTICS||||(unless otherwise stated)|||||
|||||Operating temperature||-40°C <TA<|+105°C||
|Device||Supply|||||||
|Reference Inputs|||||||||
|ADOS|||VREFH ||Reference voltage||AVDD||V||
||||high||||||
|ADO6|||VREFL||Reference voltage||AVss|||Vv||
||||low||||||
|ADO7||VREF|Absolute reference||AVDD-—0.3|AVDD + 0.3||Vv||
||||voltage (VREFH —||||||
||||VREFL)||||||
|Analog Input|||||||||
|AD12||VINH-||Full-Scale input|VREFL|VREFH||Vv||
|||VINL|span||||||
|AD13||VINL|Absolute VINL input||AVss|VREFL||Vv||
||||voltage||||||
|AD14|||VINH|Absolute VINH input||AVss|VREFH||V||
||||voltage||||||
|ADC Accuracy|||||||||
|AD20c|||NR|Resolution||12|||Selectable 6, 8, 10, 12 res-|
|||||||||olution ranges|
|AD21c||| INL|Integral nonlinearity|+3|||LSb|VINL=AVSS = VREFL = OV,|
|||||||||AVDD = VREFH = 3.3V|
|AD22c|||DNL|Differential nonlin-|+1|||LSb|VINL =AVSS = VREFL = OV,|
||||earity|||||AVDD = VREFH = 3.3V|
|AD23c_|||GERR|Gain error|+8|||LSb|VINL =AVSS = VREFL = OV,|
|||||||||AVDD = VREFH = 3.3V|
|AD24c_|||EOFF|Offset error|+4|||LSb|VINL=AVSss = OV,|
|||||||||AVDD = 3.3V|
|Dynamic Performance|||||||||
|AD31b|||SINAD ||Signal to noiseand|67||||Single-ended(2)()|
||||distortion||||||
|AD34b|||ENOB ||Effective number of|10.5|||||
||||bits||||||
|Note|1:<br>These parameters are not characterized or tested in||||manufacturing.||||
||2:<br>Theseparametersarecharacterized,butnottestedinmanufacturing.||||||||
- 3: Characterized with a 1 kHz sine wave.
- 4: The ADC module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless otherwise stated, module functionality is guaranteed, but not characterized.
reer reer rereeee eee ee © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 659
PIC32MZ W1 and WFI32E01 Family
—ne)
TABLE 40-32: ANALOG-TO-DIGITAL CONVERSION TIMING REQUIREMENTS
|Standard Operating Conditions: 2.97V to 3.63V|
|---|
|Operatingtemperature-40°C <TA<+105°C<br>[symbot_[charactenstis _____—_|ain._[Typ._[Max. [Units |conatons.<br>[tye<br>[ADCcontrolerclockpeiod ———SSSSS=«dSSSC*dTO<br>«dssSQS—S<br>[aoc<br>[SARADCcore clockperiod __——=~=S~S~*~«diBTrans<br>fouyoye [Ouyece<br>—SSSCSC~=“~*~‘~*~*dABS:~C*idSN’SC*d‘SIS<br>=SC=éd@M™®SCSCSC*|
|fseles=10,rest=10<br>[oor [233 [as [MSPS|—<br>[seres=01,rest=8<br>**[**0.01 **[**28 _|4a7s_[w**SPS**|**—**<br>[sees=00,rest=6<br>oot<br>35<br>[5833 [M<br>[|
|fseles=1O,rest=10<br>|<br>2 SSS—iy™<br>fseressO1rest=8<br>|<br>0S~=~id SSCS<br>fseres=00,rest=6<br>| 8 SSS~dSCS<br>SCS|
|fseres=10,rest=10<br>| 2 —S=~«deSs<br>fseres=O1rest=8<br>|<br>—St0S~dSCd SSCS<br>jsetes=00,rest=6<br>|<br><8~—S~=~s ye=SdSSCS<br>‘Tscp [Sep**a**rationimebetweencommand «| —=SsS~—~S~—sns Ss SSC*d<br>Tome _[S mpietime<br>——SS—«*d<br>Btn [—<br>infinite‘|S<br>Toss<br>[Conversioncomplstetosamplestat ——([—_—'jo—=«d——Sidns<br>~—<——SC—=*™<br>Twarmup [Wake-uptimeforanaiog<br>SSS SS~dSSCdsSs<br>End-Of-Sample<br>en_async_samp= 1<br>(4+/-0.5)<br>ns<br>ee<br>reer ee<br>Note<br>1:<br>These parameters are characterized, but not tested in manufacturing.|
|2:<br>TheADC module is functional atVBORMIN < VDD < VDDMIN, but with degraded performance. Unless|
|otherwisestated,modulefunctionalityisguaranteed,butnotcharacterized.|
ES DS70005425A-page 660 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
smn
**==> picture [430 x 166] intentionally omitted <==**
**----- Start of picture text -----**<br>
FIGURE 40-1: PROGRAMMABLE LOW-VOLTAGE DETECT ELECTRICAL CHARACTERISTICS<br>VDD apse ale head (LVDIF can be<br>(LVDIF set by hardware)VLvb t VLHYS _ “= .{:' cleared in software)<br>LVDIF<br>**----- End of picture text -----**<br>
TABLE 40-33: PLVD ELECTRICAL CHARACTERISTICS
|DC Specifications|DC Specifications|DC Specifications|Standard Operating Conditions: 2.97V to 3.63V||
|---|---|---|---|---|
||||(unless otherwise stated)||
||||Operating temperature<br>-40°C< TA< +105°C||
|Vid|||LVDvoltageon<br>Vootransition|[LVDL=0100<br>gu [sez lV<br>|<br>[LvDL=0101<br>sa<br>|sses |v |SSSSCSCSC~S||
|Note|1:|jvor=o1t Jaese facet_jaose fv |<br>Production tested at T, = 25°C. These parameters are characterized, but not tested in||—S—~™<br> manufacturing.|
||2:|LVDL=1000toLVDL=1011arenotsupported.|||
OOOO___ © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 661
## PIC32MZ W1 and WFI32E01 Family
## seman
## TABLE 40-34: TEMPERATURE SENSOR SPECIFICATIONS
|||||Standard Operating Conditions"): 2.97V to 3.63V|Standard Operating Conditions"): 2.97V to 3.63V|Standard Operating Conditions"): 2.97V to 3.63V|
|---|---|---|---|---|---|---|
|AC CHARACTERISTICS||||(unless otherwise stated)|||
|||||Operating temperature<br>-40°C <TA<|TA< +105°C||
|Ts10[vis|Ts10[vis|[Rateofchange[—||re[mvc<br>[—|||
|Note<br>1:|The temperature sensor is functional atVBORMIN < VDD < VDDMIN, butwith degraded performance. Unless||||||
||otherwise stated, module functionality is tested, but not characterized.||||||
|TABLE|40-35:|USB OTG ELECTRICAL SPECIFICATIONS|||||
|||||Standard Operating Conditions: 2.97V to 3.63V|||
|AC CHARACTERISTICS||||(unless otherwise stated)|||
|||||Operating temperature|-40°C <TA< +105°C||
|USB313|||VUsB3v3|||USB voltage|3.0<br>3.6|V|Voltage on VUSB3Vv3|
|||||||must be in this range for|
|||||||proper USB operation|
|Low-Speed and Full-Speed Modes|||||||
|USB316<br>USB318|VDIFS|||inputhighvoltageforUSBbufler<br>Differential input sensitivity|bufler [20 [— _|— lV <br>0.2<br>V||[-<br>The difference between|
|||||||D+ and D- must exceed|
|||||||this value while VCM is|
|||||||met|
|USB321||VOL||Voltage output low|0.3|V|1.425 kQ load|
|||||||connected to VUSB3V3|
|USB322|||VOH||Voltage output high|2.8<br>3.6|Vv|14.25 kQ load|
|||||||connectedtoground|
**==> picture [181 x 22] intentionally omitted <==**
**----- Start of picture text -----**<br>
Ts10[vis [Rateofchange[—<br>**----- End of picture text -----**<br>
## TABLE 40-35: USB OTG ELECTRICAL SPECIFICATIONS
## AC CHARACTERISTICS
Note 1: These parameters are characterized, but not tested in manufacturing.
renner eee e rereerence eee eee DS70005425A-page 662 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
**==> picture [457 x 4] intentionally omitted <==**
**----- Start of picture text -----**<br>
smn<br>**----- End of picture text -----**<br>
TABLE 40-36: ETHERNET MODULE SPECIFICATIONS
**==> picture [456 x 249] intentionally omitted <==**
**----- Start of picture text -----**<br>
Standard Operating Conditions: 2.97V to 3.63V<br>AC CHARACTERISTICS (unless otherwise stated)<br>Operating temperature -40°C <TA<+105°C<br>RMIlI Timing Requirements<br>ET1__ [Reference clock frequency a Cc el<br>ETI2ETI3_ETXDx,[ReferenceETEN,ciockdutyeycleSetup and Hold———SSSC~iSNSCSC*‘*‘iEC*‘“‘“wUTSR’TOC*C(Mtime a OCIS CSd<br>ET14 |ERXDx, ERXDV,ERXERR SetupandHoldtime [5 [— [12 [ns [— |<br>FIGURE 40-20: ETHERNET AC TIMING DIAGRAM<br><—_—Tcy—+|<br>CLK<br>_ TDOUT<br>DataOut<br><—Ts TH—>|<br>**----- End of picture text -----**<br>
SS © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 663
## PIC32MZ W1 and WFI32E01 Family
## seman
FIGURE 40-21: EJTAG/JTAG TIMING CHARACTERISTICS
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¢—_——_ TtcKeye ————> 1 1<br>L$I TTckhi g h gl| TTcklow ;I +>Lg, 1<br>] I ! i |<br>WA \ 4 XI<br>TCK | “| »~<br>u | ial 1<br>Tr I<br>I<br>TDI : i<br>|rw >,| Ipot! >| 1<br>' Ttsetup 'TThold! I — Tr I<br>1 lf I I<br>14 I I<br>TDO 1<br>T: + :<br>TRST* TOW| J TTDOout Tree<br>)<br>|<br>i|>i Tr~~1 1 [| Defined [| Undefined<br>**----- End of picture text -----**<br>
TABLE 40-37: EJTAG/JTAG TIMING REQUIREMENTS
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**----- Start of picture text -----**<br>
Standard Operating Conditions: 2.97V to 3.63V<br>AC CHARACTERISTICS (unless otherwise stated)<br>Operating temperature -40°C < TA< +105°C<br>TOK cycle time 25 [— [ns [—- [SCS]<br>EJ4 TTSETUP TAP signals setup time before |5<br>rising TCK<br>EJ5 TTHOLD TAP signals hold time after 3<br>rising TCK<br>EJ6 TTDOOUT TDO output delay time from a)<br>falling TCK<br>EJ7 TTDOZSTATE |TDO 3-state delay time from 5<br>falling TCK<br>EJ9 TRF TAP signals rise/fall time, all<br>input and output<br>Note 1: These parameters are characterized, but not tested in manufacturing.<br>**----- End of picture text -----**<br>
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## smn
## 40.1.3 AC AND DC CHARACTERISTICS GRAPHS
Note: The graphs provided are a statistical summary based on a limited number of samples and are provided for design guidance purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs, the data presented may be outside the specified operating range (for example, outside specified power supply range) and therefore, outside the warranted range.
## FIGURE 40-22: VOH — 4x DRIVER PINS
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VOH (V)<br>__ -0.030 N\<br>Zootzz -0.025 | | | |Nf<br>Soot > | rECK<br>-0.015 |<br>n-------{[ absolute Maximum _poovsssov poe Neeson<br>0.000<br>0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50<br>VoL - 4x DRIVER PINS<br>VOL (V)<br>Zon 0.030 ||<br>~ 0.025<br>Sow<br>0.020 7<br>ia fee<br>ry |.<br>0.000<br>0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50<br>**----- End of picture text -----**<br>
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**----- Start of picture text -----**<br>
FIGURE 40-23: VoL - 4x DRIVER PINS<br>**----- End of picture text -----**<br>
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PIC32MZ W1 and WFI32E01 Family
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**----- Start of picture text -----**<br>
FIGURE 40-24: VOH — 8x DRIVER PINS<br>VOH (V)<br>eeee<br>— -0.050<br>0.000<br>0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50<br>FIGURE 40-25: VoL — 8x DRIVER PINS<br>VOL (V)<br>a<br>Z|<br>= [0.050] ae eee eee<br>Zoot “Z|| | | | |<br>0.030 por Absolute Moxinuma [~~<br>0.000<br>0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50<br>**----- End of picture text -----**<br>
DS70005425A-page 666
Preliminary Data Sheet
© 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
FIGURE 40-26: TYPICAL TEMPERATURE SENSOR VOLTAGE
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1.450 | |<br>1.350<br>1.250<br>1.150<br>1.050<br>_rack<br>@ 0.950<br>D<br>A<br>> 0.850<br>><br>0.750<br>0.650<br>0.450<br>-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100110 120130<br>Temperature (Celsius)<br>**----- End of picture text -----**<br>
40.1.4 RF CHARACTERISTICS For details on the RF _ performance, refer to Section 40.2.3 “Radio Performance”.
© 2020 Microchip Technology Inc.
Preliminary Data Sheet
DS70005425A-page 667
## PIC32MZ W1 and WFI32E01 Family seman 40.2 WFI32E01 Module Electrical Specifications
The absolute maximum ratings for the WFI32E01 module are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these or any other conditions, above the parameters indicated in the operation listings of this specification, is not implied.
Note: All the electrical specification of the PIC32MZ W1 applies to the WFI32E01 module as well unless specified explicitly.
Absolute Maximum Ratings Ambient temperature Under DIAS «0... cccccceccccsssseesseeeeeeesesssansssseeeeeceececeeceeeessssssssssessseeseseesssssssseteee40°C to +85°C Storage temperature 0.0... cece ccccssssseecessesseececesseeeeecessaeaeesaeececeesaeseecesseaeeceesssaeeseeeestsesesesseeeesesses 40°C to +125°C Voltage on VDD with respect to GND 000.0... cece ceceeeeeceessssssneeseeeceeeeescesssnserseesseeesseeeeeseeessssssssstrssseeeees “O.3V to +4.0V Voltage on VBUS with respect tO GND 0.0... ccc cccccceseessseeeeeceeesesesesstseessseeeeeeeteeseseeesttttttseeeeeee 7O0.3V to +5.25V Maximum currentiout Of GND pil (S)) iccsictecadiscnicisvnssdonedatlaedtdivedorootamddoreenisindMaiiinmestnmdiieewiie Mander MA Maximum current into VDD pin(s)(?) mineaeia ote Ble Ebtasmasle GIMP natch baie ebe TE OP nate ale icc nnn ese aA Ba ein SES EP a OM ESD Qualification: Human Body Model (HBM) (JEDEC JS-001-2017) oo... eeeececcececeeececeeeeeaeeeeneeceeseeeesaeesesaeeseaeeceeseeeestseeesaeeteeeeesees+2000V Changed Device Model (CDM) (JEDEC JS-002-2018). 2... .ecceeecccceccceececceeseeeeeaeeeceaeeeeaaeeeeaeeeceaeeeseseetesteeeeseeeseseeees:DOOV
Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions, above those indicated in the operation listings of this specification, is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2: The maximum allowable current is a function of the device’s maximum power dissipation.
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TABLE 40-38: RECOMMENDED OPERATING CONDITIONS<br>Symbol [Parameter Min. [Typ Max, Unit<br>[vo [Power supply input votage<br>**----- End of picture text -----**<br>
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**----- Start of picture text -----**<br>
40.2.1 DC CHARACTERISTICS<br>**----- End of picture text -----**<br>
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**----- Start of picture text -----**<br>
TABLE 40-39: WI-FI@ CURRENT<br>Standard Operating Conditions: 3.0V to 3.6V<br>DC CHARACTERISTICS (unless otherwise stated)<br>Operating temperature -40°C < TA< +85°C<br>Device States Code Rate see em) (TyP.) Current (Typ.) (mA)*)<br>PFOS™~”:”:””:C«*BOTT802.11b 11TMSMbps COSSOSCSC*~“‘CSC™*SC*sW@™~S=“‘CN™SC#C*C*C‘(‘SC#@S'<br>On_Transmit‘) 802.11g g 6 Mbpsi<br>802.119<br>802.1in 64MGSO Mbps<br>802.11n MCS7<br>802.11b 1 Mbps a<br>802.11b 11 Mbps a<br>6<br>on Receive 802.11 6 Mbps a<br>- 802. 11g 64 Mbps a 2<br>802.11 MCSO a<br>802.11n MCS7 a<br>Note 1: Measured along with RF matching network and FEM circuit (assume 50Q impedance).<br>2: The test conditions for IDD measurements are as follows:<br>¢ CPU, Flash Panel and SRAM data memory are operational.<br>* CPU is in Wi-Fi RF Test mode.<br>* All peripheral modules are disabled (ON bit = 0) but the associated PMD bit is cleared.<br>¢ WDT and FSCM are disabled.<br>¢ All I/O pins are configured as inputs and pulled to Vss.<br>¢ MCLR = VDD.<br>3: Data in the “Typ.” column is at 3.3V, 25°C unless otherwise stated.<br>4: This parameter is characterized, but not tested in manufacturing.<br>5: Tested at channel 7 in Fixed Mode Gain.<br>Note: For details on the DC characteristics, refer to 40.1.1 “DC Characteristics”.<br>40.2.2 AC CHARACTERISTICS AND<br>TIMING PARAMETERS<br>Note: _Fordetails on the AC Characteristics and Timing Parameters, refer to Section 40.1.2 “AC Characteristics<br>and Timing Parameters”.<br>**----- End of picture text -----**<br>
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## PIC32MZ W1 and WFI32E01 Family
—ne)
## 40.2.3 RADIO PERFORMANCE
This section describes the Wi-Fi radio specifications and performance characteristics.
## TABLE 40-40: RADIO SPECIFICATIONS
|TABLE 40-40:<br>RADIO SPECIFICATIONS<br>Feaure<br>___—_—=(Deserption—SSC~“‘“~*~“‘*~*S*S*S*S*~*S*S~“CS*~S~S~S~S~*Y|
|---|
## 40.2.3.1 Receiver Performance
The following table provides the receiver performance characteristics of the WFI32E01 module.
TABLE 40-41: RECEIVER PERFORMANCE CHARACTERISTICS")
|tee|<br>RF<br>CHARACTERISTICS<br>(unless otherwise stated)<br>Operating temperature -40°C <TA<+85°C<br>Parameter___———‘(Deseripion _—_——(Min”—=*(Typ. (Max.__unt_|<br>Frequency<br>SSCS™~SCSC~sdTSSC«S=«di<br>TC|
|---|
|ssMbpsosss STSSS~=~—SSSC*dSSCSC~*<br>‘iMbpsdsss_SiSS—=~dSC|
|feMbpsOFOM——=Si«—SsS~=~—OSCSSSSC*d<br>2Mopsorom——sd[-~—S=~i<br>SC SSSC*”|
|[24MbpsoFOM<br>it —~—=«d88s<br>[S6MopsOFOM—SSC«SS~=~rSSSC*dSCSC~*<br>[48MopsOFOM——Si«dtSS~=~i<br>I SC*dSSCSC=*”<br>[S4MopsOFOM<br>[= ——=dia|
|Mesa<br>SSC~SC“C~‘~‘~*r<br>':SOSC*“‘z]”OC*’<br>Mess<br>SSC~=~—SC~“‘~‘i<br>I'SCd<br>Mess<br>SSC~sSC“‘*‘“‘;é*rI''=«S~C*dSC*'<br>wes?<br>SSC~=~sSCi*é‘“‘*r['”~<br>SSC‘ SSCSC~*|
|[eMbpsOFOM<br>«2SSCdSSSC~dSCSCS~S**~**™<br>[S4MopsOFOM<br>«(7s [=<br>«di ——— *F<br>IMesoSOC~—SSSC*idCC~=~—SC~C~*'<br>Dc<br>a|
ES DS70005425A-page 670 Preliminary Data Sheet © 2020 Microchip Technology Inc.
PIC32MZ W1 and WFI32E01 Family
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smn<br>TABLE 40-41: RECEIVER PERFORMANCE CHARACTERISTICS") (CONTINUED)<br>Standard Operating Conditions: 3.0V to 3.6V<br>RF CHARACTERISTICS (unless otherwise stated)<br>——————‘[Descrpon<br>Parameter Operating temperature -40°C < TA< +85°C<br>Adjacent Channel 1 Mbps DSSS (30 MHz(in.off- | 44.5 [Typ. [Max [Un<br>Rejection set)<br>11 Mbps DSSS (25 MHz off- | 39.5<br>set)<br>6 Mbps OFDM (25 MHz off- | 41.5<br>set)<br>54 Mbps OFDM (25 MHz off- | 24.5<br>set)<br>MCS 0 — 20 MHz Bandwidth | 35.5<br>(25 MHz offset)<br>MCS 7 — 20 MHz Bandwidth | 20.5<br>(25 MHz offset)<br>**----- End of picture text -----**<br>
- Note 1: Measured after RF matching network and FEM output (assume 5092 impedance).
- 2: RF performance is ensured at 3.3V, 25°C, with a 2-3 dB change at boundary conditions.
- 3: The availability of some specific channels and/or operational frequency bands are country-dependent and should be programmed in the host product at the factory to match the intended destination. Regulatory bodies prohibit exposing the settings to the end user. This requirement needs to be taken care of via host implementation.
- 4: The host product manufacturer must ensure that the RF behavior adheres to the certification (for example, FCC, ISED) requirements when the module is installed in the final host product.
## 40.2.3.2 Transmitter Performance
The following table provides the transmitter performance characteristics of the WFI32E01 module.
## TABLE 40-42: TRANSMITTER PERFORMANCE CHARACTERISTICS
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Standard Operating Conditions: 3.0V to 3.6V<br>RF CHARACTERISTICS (unless otherwise stated)<br>Operating temperature -40°C <TA<+85°C<br>Frequency SS~*dTP «dT<br>**----- End of picture text -----**<br>
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## PIC32MZ W1 and WFI32E01 Family
## seman
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**----- Start of picture text -----**<br>
TABLE 40-42: TRANSMITTER PERFORMANCE CHARACTERISTICS (CONTINUED)<br>Standard Operating Conditions: 3.0V to 3.6V<br>RF CHARACTERISTICS (unless otherwise stated)<br>Operating temperature -40°C < TA<+85°C<br>Output power" 702.1% [MESO a<br>(Bandwth at 20 MHz) |S a<br>es<br>MCS 4 —<br>MOST es<br>Transmit Power Control (TPC) +1.5(2)a<br>Accuracy<br>**----- End of picture text -----**<br>
- Note 1: Measured at IEEE 802.11 specification compliant EVM/Spectral mask.
- 2: Measured after RF matching network and FEM output (assume 50Q impedance).
- 3: RF performance is ensured at 3.3V, 25°C, with a 2-3 dB change at boundary conditions.
- 4: With respect to TX power, different (higher/lower) RF output power settings may be used for specific antennas and/or enclosures, in which case re-certification may be required.
- 5: The availability of some specific channels and/or operational frequency bands are country-dependent and should be programmed in the host product at the factory to match the intended destination. Regulatory bodies prohibit exposing the settings to the end user. This requirement needs to be taken care of via host implementation.
- 6: The host product manufacturer must ensure that the RF behavior adheres to the certification (for example, FCC, ISED) requirements when the module is installed in the final host product.
- 7: FCC Radiated Emission limits (Restricted Band).
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PIC32MZ W1 and weri32E01 Family
## 41.0 PACKAGING INFORMATION
This chapter provides the information on package markings, dimension and _ footprint of the PIC32MZ1025W104 SoC and WFI32E01 module.
## 41.1 PIC32MZ1025W104 SoC Packaging Information
41.1.1 PIC32MZ1025W104 SOC PACKAGE MARKING
## FIGURE 41-1: PIC32MZ1025W104 SOC PACKAGE MARKINGS
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**----- Start of picture text -----**<br>
132-Lead DQFN (10x10x0.9 mm) Example<br>O O<br>® Pic ® Pic<br>XXXXXXXXKX MZ1025W104<br>XXXXXXXXXKX 132<br>XXXXXXXXXKX<br>YYWWNNN YYWWNNN<br>Legend: XX...X Customer-specific information<br>Y Year code (last digit of calendar year)<br>YY Year code (last 2 digits of calendar year)<br>Www Week code (week of January 1 is week ‘01’)<br>NNN Alphanumeric traceability code<br>Pb-free JEDEC designator for Matte Tin (Sn)<br>* This package is Pb-free. The Pb-free JEDEC designator (e3)<br>can be found on the outer packaging for this package.<br>Note: In the event the full Microchip part number cannot be marked on one line, it will<br>be carried over to the next line, thus limiting the number of available<br>characters for customer-specific information.<br>**----- End of picture text -----**<br>
© 2020 Microchip Technology Inc. Preliminary Data Sheet
DS70005425A-page 673
## PIC32MZ W1 and weri32E01 Family
41.1.2 PIC32MZ1025W104 SOC PACKAGING DIMENSION This section provides the package dimension details of PIC32MZ1025W104.
Note: For the most current package drawings, see the Microchip Packaging Specification located at http://www.microchip.com/packaging.
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**----- Start of picture text -----**<br>
FIGURE 41-2: PIC32MZ1025W104 SOC PACKAGE DRAWINGS<br>2X<br>[0.10]C| [D]<br>1 § 8 [B|<br>NOTE feg ¢ | SEE<br>OFT DETAIL C %<br>rm ; yy,RN “ fhB)<br>ary A a re B<br>(DATUM B) ;<br>(DATUM A) | ;<br>2x BIS | B31 :<br>Se ee A =:<br>ay 28 a. [SJo.10[c| !<br>[0.10]C| TOP VIEW<br>—|-{B[o.8[c]<br>SEATING<br>4xP PLANE<br>.<br>“$ |———. D2 g 3 SIDE VIEW<br>4XP y *, P VUUYVUUUUUJUUUUUUUUUoojo0comoDDDoO0 Gs op Lb<br>“Bo aq” / DETAILA<br>PS aq<br>PDD | aga _t<br>E2 = coosaf-—- f ag CO CT [e]<br>SRO Ljos<br>aN SS aq (k) : !<br>BAN 35 St<br>ANS‘ R- wodoo00007qRES Hw lose<br>NOTE Ns NENA 00000 e a a CI a<br>1 3Ke \ SEE DETAIL8 B 1<br>DETAILA<br>BOTTOM VIEW<br>**----- End of picture text -----**<br>
© 2020 Microchip Technology Inc.
DS70005425A-page 674
Preliminary Data Sheet
PIC32MZ W1 and wei32E01 Family
## smn
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**----- Start of picture text -----**<br>
FIGURE 41-3: PIC32MZ1025W104 SOC PACKAGE DRAWINGS - CONTD.,<br>SEATINGPLANE Arar} ~ yt SesSSSS “CZereosOSyp<br>DETAIL C At (A3) Reo, sor<br>(ROTATED 90° CW) Fe,~ PK? SSS”Lr<br>[eR] noaadg<br>1. Ain 0 IN po<br>_| _ 132X b ~L Fi<br>0.10M[c[ AB] Na<br>DETAIL B 0.05)<br>MILLIMETERS<br>Number of Terminals PN |432,<br>Terminals in Outer Row A<br>Terminals in Inner Row B PNB{ [OO]<br>Pitch 0.50 BSC<br>Pitch Between Rows | eR | 0.65 BSC<br>Overall Height PA | 080 | 0.85 | 0.90_|<br>[Standoff AT | 0.00 T0071 0.05<br>Mold Cap Height pA2 | 055 | 0.60 _ | 0.65_|<br>Base Thickness 0.25 REF<br>Overall Length | D | 10.00 BSC<br>Mold Cap Length 9.73 BSC<br>Exposed Pad Length<br>Overall Width 10.00 BSC<br>Mold Cap Width 9.73 BSC<br>Exposed Pad Width<br>Terminal Length, Outer Row<br>Terminal Length, Inner Row<br>Terminal Width pb | 017 | 0.22 | 0.27__|<br>Terminal-to-Exposed-Pad 0.20 MIN REF<br>Notes: Corner Chamfer PP ft 024 | 042 | 0.60__|<br>1. Pin 1 visual index feature may vary, but must be located within the hatched area.<br>2. Package is punch singulated<br>**----- End of picture text -----**<br>
3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
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## PIC32MZ W1 and weri32E01 Family
## seman
## 41.1.3 PIC32MZ1025W104 SOC RECOMMENDED FOOTPRINT
The following figure illustrates the recommended footprint for the PIC32MZ1025W104.
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**----- Start of picture text -----**<br>
FIGURE 41-4: RECOMMENDED FOOTPRINT FOR THE PIC32MZ1025W104<br>[-———_ C1|<br>1-13 =] |<br>| oe] |<br>az2 !<br>| Jor © aa |<br>@ B60 Y2 G2<br>-—_<br>-—--© *fFS++agsdeooooonoa0000UU000T000N0000<br>Bt = im) a=> !<br>dD Oo 000 0 0 — =<br>Ss eS EV<br>ov 22 00000 0 — - |<br>C2 C4 Y3 —F SD ljo00000| aS4<br>oP e20000; a<br>SSPD looooo0 0d a<br>Go Sa eS } ($1)<br>D> 000000) a X2<br>— P=)<br>SILK =puapossancnsa ini} — |<br> SCREEN ——~ rt| | x1 v1<br>ETI X3 os<br>RECOMMENDED LAND PATTERN<br>Po Cimension Limits] MIN | NOM_|_MAX_|<br>innerContactPad Spacing | C4 | 8.16 |<br>|JinnerOuter ContactContact PadPad WidthWidth (x60)(x72) || xix2_[| || 0.300.30_|fInner[Outer CoCo ntact Pad LengthPad Length (x72)(x60) | Y i2 | [[0.59] | 0.78 ||<br>|Optional Center Pad Width | X3_ | | 5.60 [inner Pad Rowto OuterPadRow | G2] 0.20 [| |<br>[Optional|OuterCenterPadLength| Y3_ | | 5.60_|{Contact Pad to Contact Pad (x68) | G3_| 0.20 [| |<br>|Outer ContactPad Spacing | C1 | | 9.93 | {Contact Pad to Contact Pad (x56) | G4 | 0.20 | |<br>inner ContactPad SpacingContactPad Spacing | c3C2 | 9.938.16 | Thermal|fThermalviapitch ViaDiameter CP| EV V | 030tc JTT<br>Notes:<br>1. Dimensioning and tolerancing per ASME Y14.5M<br>BSC: Basic Dimension. Theoretically exact value shown without tolerances.<br>2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during<br>reflow process<br>**----- End of picture text -----**<br>
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## 41.2 WFI32E01 Module Packaging Information
41.2.1 WFI32E01 MODULE PACKAGE MARKING
FIGURE 41-5: WFI32E01 MODULE PACKAGE MARKINGS
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**----- Start of picture text -----**<br>
XXXXXKXKXXXKXKXKXKXKXKKK WF132E01PC WFI32E01PE<br>XXXXXXKXXXXKXXKXKXKKK FCC ID: 2ADHKWFI32E01 FCC ID: 2ADHKWFI132E01<br>XXXXXXKXXXKXXXKXKXKXKK IC: 20266-WF132E01 IC: 20266-WF132E01<br>YYWWNNN 2050NNN 2050NNN<br>v XX 9 CE v CE<br>WFI132E01UC WFI32E01UE<br>FCC ID: 2ADHKWFI32E01 FCC ID: 2ADHKWF132E01<br>IC: 20266-WF132E01 IC: 20266-WF132E01<br>2050NNN 2050NNN<br>v cE v CE<br>Legend:<br>XX....X Module part number and version and regulatory designator<br>YY: Year code (last 2 digits of calendar year)<br>Www Week code (week of January 1 is week "01")<br>NNN Alphanumeric traceability code<br>**----- End of picture text -----**<br>
_OOOOOOeeOOOOOOOOOOeOEOOEOeOEOEOoOoeseEeee_OO © 2020 Microchip Technology Inc. Preliminary Data Sheet DS70005425A-page 677
DS70005425A-page 677
## PIC32MZ W1 and weri32E01 Family
## seman
## 41.2.2 WF132E01 MODULE PACKAGING DIMENSION
Note: | Module dimensions mentioned in the following figure are applicable to the PCB antenna and U.FL connector variants.
**==> picture [413 x 488] intentionally omitted <==**
**----- Start of picture text -----**<br>
FIGURE 41-6: 54-PIN RF MODULE WITH SHIELD (6YX) - 20.5X24.5 MM [MODULE]<br>[27 }0.10|<br>[D] A2<br>UFL | El ™”<br>CONNECTOR +<br>es] |(ST<br>[E|<br>E1<br>2x<br>———EE<br>2x D1 he (A3) 4<br>[>] 0.25] (0.74) A<br>TOP VIEW SEATING<br>woos. 88988 2» . Pics<br>" wives 3 3 END VIEW<br>1 aa i Doopooost——| E L<br>ai 14<br>6.61NG= ea6 = 5.46<br>7.48 IE 74 54 =| 7.23 5AXb<br>“TIE Ko j a an [o.10@[C TATE)<br>coe14.09“Tele axoadK, = 8i 00 :<br>41 =i<br>EI OES<< —| iial | 15.58<br>1.50 aconooie 1.00<br>— 2.00<br>q8<br><o 2<br>BOTTOM VIEW<br>Notes:<br>1. All dimensions are in millimeter.<br>2. Pins 55-60 are used only for factory testing purpose.<br>**----- End of picture text -----**<br>
3. Pins 61-63 are used as GND PADs.
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PIC32MZ W1 and wei32E01 Family
**==> picture [457 x 4] intentionally omitted <==**
**----- Start of picture text -----**<br>
smn<br>**----- End of picture text -----**<br>
FIGURE 41-7: 54-PIN RF MODULE WITH SHIELD (6YX) - 20.5X24.5 MM [MODULE]
**==> picture [374 x 443] intentionally omitted <==**
**----- Start of picture text -----**<br>
SO ao of<br>> oN<br>> o oy<br>“Se = SS<br>2S) S A<br>So ><br>kos ><br>kos> >><br>ins cS<br>eS eS<br>> ~ AEos<br>IS<br>SS<br>™!Sa<br>MILLIMETERS<br>| Cimension Limits] MIN | NOM | MAX_|<br>Number of Terminals<br>Overall Height<br>PCB Thickness | A2 | 0.70 | 0.80 | 0.90__|<br>Shield Height 1.70 REF<br>UFL Connector Height 1.25 REF<br>Overall Length | D | 20.50 BSC<br>Overall Width | E | 24.50 BSC<br>Shield Length 18.70 18.80 18.90<br>Shield Width 16.90 17.00 17.10<br>Terminal Width |b | 0.50 | 0.60 | 0.70 |<br>Terminal Length pt {| 070 | 080 | 0.90 |<br>**----- End of picture text -----**<br>
me
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## PIC32MZ W1 and weri32E01 Family
## 41.2.3 WFI32E01 MODULE RECOMMENDED FOOTPRINT
**==> picture [441 x 513] intentionally omitted <==**
**----- Start of picture text -----**<br>
FIGURE 41-8: RECOMMENDED MODULE FOOTPRINT ON THE HOST BOARD<br>gx a %<br>tv = 2<br>wo—p--L} | -__,<br>| ' | | | MODULE OUTLINE<br>POINT17.34 CURE T ESOU T || _ | ,'I | | |}| a|<br>—-—+—1] Hooo0gee0qea<br>|S | 1 --J—-— 15.58<br>14.07 12gOo | Ooo | ,<br>|<br>o 1.27<br>:<br>8.74 ——-—+ f}—--——-—_- ol<br>—- -—<br>6.81631 —-— 1 @) |-— 7.23<br>ia VW Pe ____<br>4,50 ON ee ere<br>3.18 —-—@--- im—-— Ja 4.50<br>ole > E50) 005 : | i 5 on<br>food bo coo coos oT _<br>Paik Til || anLil | :<br>858 855 & 285 88<br>RECOMMENDED LAND PATTERN<br>a<br>1.20 1.30 —| rT B60 Xe » Cl [— 0.70<br>2.42 {a 0 en > 100 [<br>1.00 mi vr S +<br>L_| Lag od Cin<br>| boo<br>RF TEST COPPER COPPER EXPOSED GROUND PADS TERMINAL<br>POINT CUTOUT KEEPOUT KEEPOUT (SOLDER MASK DIMENSION) PAD<br>Notes:<br>1. All dimensions are in millimeter.<br>2. Pins 55-60 are used only for factory testing purpose.<br>3. Pins 61-63 are used as GND PADs.<br>**----- End of picture text -----**<br>
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## PIC32MZ W1 and WFI32E01 Family smn APPENDIX A: REGULATORY require additional testing or equipment authorization APPROVALS for the transmitter function provided by that specific module or limited module device. The WFI32E01PC module has received regulatory The user must comply with all of the instructions proapproval from the following countries: vided by the Grantee, which indicate installation and/or ¢ United States/FCC ID: 2ADHKWFI32E01 operating conditions necessary for compliance.
* Canada/ISED - IC: 20266-WFI32E01 ~ HVIN: WFI32E01PC
- PMN: WFI32E01
* Europe/CE The WFI32E01PE module has received regulatory approval from the following countries:
* United States/ECC ID: 2ADHKWEFI32E01 * Canada/ISED
- IC: 20266-WFI32E01 - HVIN: WFI32E01PE - PMN: WFI32E01
* Europe/Ce The WFI32E01UC module has received regulatory approval from the following countries:
“hinted; SalesCGE: 2}DHRWEIBZEG
- Canada/ISED
- IC: 20266-WFI32E01
- - HVIN: WFI32E01UC
- PMN: WEI32E01
*« Europe/CE Te EASE Ree ens MES Meee Merman approval from the following countries:
¢ United States/FCC ID: 2ADHKWFI32E01 » Canada/ISED - IC: 20266-WFI32E01 - HVIN: WFI32E01UE - PMN: WEI32E01
- Europe/CE
## A.1 United States
The WFI32E01PC/WFI132E01PE/WF1I32E01UC/
WFI32E01UE modules have received Federal Communications Commission (FCC) CFR47 Telecommunications, Part 15 Subpart C “Intentional Radiators” single-modular approval in accordance with Part 15.212 Modular Transmitter approval. Single-modular transmitter approval is defined as a complete RF transmission sub-assembly, designed to be incorporated into another device, that must demonstrate compliance with FCC rules and policies independent of any host. A transmitter with a modular grant can be installed in different end-use products (referred to as a host, host product, or host device) by the grantee or other equipment manufacturer, then the host product may not
The host product itself is required to comply with all other applicable FCC equipment authorizations regulations, requirements and equipment functions that are not associated with the transmitter module portion. For example, compliance must be demonstrated: to regulations for other transmitter components within a host product; to requirements for unintentional radiators (Part 15 Subpart B), such as digital devices, computer peripherals, radio receivers, etc.; and to additional authorization: requirements; for the: non-transmitter; functions on the transmitter module (i-e., Suppliers Declaration of Conformity (SDoC) or certification) as appropriate (for example, Bluetooth and Wi-Fi transmitter modules may also contain digital logic functions). A1.1 LABELING AND USER INFORMATION REQUIREMENTS The WFI32E01PC/WFI32E01PE/WFI32E01UC/ WFI32E01UE modules have been labeled with its own FCC ID number, and if the FCC ID is not visible when the module is installed inside another device, then the outside of the finished product into which the module is installed must also display a label referring to the enclosed module. This exterior label can use wording . as follows: For the WFI32E01PC/WFI32E01PE/WFI32E01UC/ WFI32E01UE: Contains: Transmitter: Module FCC ID: 2ADHKWFI32E01 = Contains FCC ID: 2ADHKWFI32E01 This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation
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PIC32MZ W1 and WFI32E01 Family seman A user’s manual for the finished product should include A.1.3 APPROVED ANTENNAS Dieter arin aeTee To maintain modular approval in the United States, only This equipment has been tested and found to comply the antenna types that have been tested shall be used. with the limits for a Class B digital device, pursuant to It is permissible to use different antenna, provided the part 15 of the FCC Rules. These limits are designed same antenna type, antenna gain (equal to or less to provide reasonable protection against harmful than), with similar in-band and out-of band characterisinterference in a residential installation. This equiptics (refer to specification sheet for cutoff frequencies). ment generates, uses and can radiate radio freFor WFI32E01PC/WFI32E01PE, the approval is quency energy, and if not installed and used in received using the integral PCB antenna. accordance with the instructions, may cause harmful interference to radio communications. However, For WFIS2E01UC/WFI32E01UE, approved antennas there is no guarantee that interference will not occur are listed in the Table 3-3. in a particular installation. If this equipment does A14 MODULE INTEGRATION IN THE cause harmful interference to radio or television reception, which can be determined by turning the HOST PRODUCT equipmentoff and on, the user is encouraged to try to Host products are to ensure continued compliance as correct the interference by one or more of the followper KDB 996369 Module Integration Guide. ing measures: ‘ sa As1:5 HELPFUL WEB SITES ¢ Reorient or relocate the receiving antenna * Increase the separation between the equipment Federal Communications Commission (FCC): and receiver https://www.fcc.gov/ * Connect the equipment into an outlet on a circuit FCC Office of Engineering and Technology (OET) Labdifferent from that to which the receiver is conoratory Division Knowledge Database (KDB): nected https://apps.fcc.gov/oetcf/kdb/index.cfm ¢ Consult the dealer or an experienced radio/TV technician for help A.2 Canada Additional information on labeling and user information The WFI32E01PC/WF132E01 PE/WFI32E01UC/ requirements for Part 15 devices can be found in KDB WF1I32E01UE modules have been certified for use in Publication 784748, which is available at the FCC Canada under Innovation, Science and Economic Office of Engineering and Technology (OET) LaboraDevelopment Canada (ISED, formerly Industry Cantory Division Knowledge Database (KDB) ada) Radio Standards Procedure (RSP) RSP-100, https://apps.fcc.gov/oetcf/kdb/index.cfm Radio Standards Specification (RSS) RSS-Gen and RSS-247. Modular approval permits the installation of A.1.2 RF EXPOSURE a module in a host device without the need to recertify All transmitters regulated by FCC must comply with RF the device. exposure requirements. KDB 447498 General RF Exposure Guidance provides guidance in determining A.2.1 LABELING AND USER whether proposed or existing transmitting facilities, INFORMATION REQUIREMENTS operations or devices comply with limits for human Labeling Requirements (from RSP-100, Issue 12, Secexposure to Radio Frequency (RF) fields adopted by tion 5): The host product shall be properly labeled to the Federal Communications Commission (FCC). identify the module within the host device. From the FCC Grant: Power output output listed is conducted. The Innovation, Science and Economic Development Single Modular Approval. This module is granted for Canada certification label of a module shall be clearly use in mobile only configuration as described in this visible at all times when installed in the host product, filing. otherwise the host device must be labeled to display Approval is limited to OEM installation only. the Innovation, Science and Economic Development : . The antenna(s) used for this transmitter must be Canadaby the wordcertifica“Con **t** ionains”,numberor similarof the wordmodule,expressingprecededthe installed to provide a separation distance of at least same meaning, as follows: 8 cm from all persons and must not be co-located or operating in conjunction with any other antenna or transmitter, except in accordance with FCC multi-transmitter product procedures. OEM integrators and end-users must be provided with specific operating instructions for satisfying RF exposure compliance requirements.
From the FCC Grant: Power output output listed is conducted. Single Modular Approval. This module is granted for use in mobile only configuration as described in this filing.
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## PIC32MZ W1 and WFI32E01 Family
## smn
For the WFI32E01PC/WFI32E01PE/WFI32E01UC/ Immediately following the above notice, the manufacWFI32E01UE: turer shall provide a list of all antenna types approved for use with the transmitter, indicating the maximum permissible antenna gain (in dBi) and required impedUser Manual Notice for License-Exempt Radio Apparaance for each. tus (from Section 8.4 RSS-Gen, Issue 5, March 2019): User manuals for license-exempt radio apparatus shall A.2.2 RF EXPOSURE contain the following or equivalent notice in a conspicAll transmitters regulated by the Innovation, Science uous location in the user manual or alternatively on the and Economic Development Canada (ISED) must device or both: comply with RF exposure requirements listed in This device contains license-exempt transmitRSS-102 - Radio Frequency (RF) Exposure Compliter(s)/receiver(s) that comply with Innovation, ance of Radio communication Apparatus (All FreScience and Economic Development Canada’s quency Bands). license-exempt RSS(s). Operation is subject to This transmitter is restricted for use with a specific the following two conditions: antenna tested in this application for certification, and 1. This device may not cause interference; must not be co-located or operating in conjunction with 2. This. device must accept any ;interference, **a** ccordanceny other withantenI **n** novation,a or transmittScienc **e** rs,and exE **c** eptonomicin including interference that may cause undesired Development Canada multi-transmitter guidelines. operation of the device. . L’emetteur/récepteur; . exempt de licence; contenu Theexposuremodulecomplianceantenna mustseparationbe installeddistanceto meetof “20thecm”RF dans le présent appareil est conforme aux CNR and any additional testing and authorization process as d’Innovation, Sciences et Développement required. The host integrator installing this module into économique Canada applicables aux appareils their product must ensure that the final composite prodradio exempts de licence. L’exploitation est uct complies with the ISED requirements by a technical autorisée aux deux conditions suivantes: assessment. 1. L'appareil ne doit pas produire de brouillage; L'antenne du module doit étre installé pour répondre a 2. L’appareil doit accepter tout brouillage la conformité en matiére d'exposition RF distance de radioélectrique subi, méme si le brouillage est séparation de 20 "cm" et tout d'autres tests et processusceptible d’en compromettre le fonctionnesus d'autorisation au besoin. L'héte integrator I'installament. tion de ce module dans leur produit final doit s'assurer ' ' que le produit est conforme a la composite Exigences Transmitter Antenna (From Section 6.8 RSS-GEN, ISED par une évaluation technique. Issue 5, March 2019): User manuals, for transmitters shall display the following notice in a conspicuous locaA2.3 APPROVED ANTENNAS ili For WFI32E01PC/WFI32E01PE, the approval is This radio transmitter [IC: 20266-WFI32E01] has received using the integral PCB antenna. BEET SPRIOvEtiY NSyauEn) EETeNoe ae eee: For WFI32E01UC/WFI32E01UE, approved antennas nomic Development Canada to operate with the : : antenna types listed below, with. the maximum are listed in the Table 3-3. permissible gain indicated. Antenna types not A2.4 HELPFUL WEBSITES included in this list that have a gain greater than ; : ; the maximum gain indicated for any type listed Innovation, Science and Economic Development Canare strictly prohibited for use with this device. ada (ISED): http://www.ic.gc.ca/ Le présent émetteur radio [IC: 20266-WFI32E01] a été approuve par Innovation, Sciences et Développement économique Canada pour fonctionner avec les types d'antenne énumérés cidessous et ayant un gain admissible maximal. Les types d'antenne non inclus dans cette liste, et dont le gain est supérieur au gain maximal indiqué pour tout type figurant sur la liste, sont strictement interdits pour I'exploitation de I'émetteur.
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## PIC32MZ W1 and WFI32E01 Family seman
## A.3 Europe
The WFI32E01PC/WFI32E01PE/WFI32E01UC/ WFI32E01UE modules are Radio Equipment Directive (RED) assessed, CE marked, and have been manufactured and tested with the intention of being integrated into a final product. The WFI32E01PC/WFI32E01PE/WFI32E01UC/ WFI32E01UE modules have been tested to RED 2014/53/EU Essential Requirements mentioned in the following European Compliance table.
## A.3.2 CONFORMITY ASSESSMENT
From ETSI Guidance Note EG 203367, section 6.1 Non-radio products are combined with a radio product: If the manufacturer of the combined equipment installs the radio product in a host non-radio product in equivalent assessment conditions (i.e., host equivalent to the one used for the assessment of the radio product) and according to the installation instructions for the radio product, then no additional assessment of the combined equipment against article 3.2 of the RED is required.
TABLE A-1: EUROPEAN COMPLIANCE A.3.3 APPROVED ANTENNAS Certification Standards For WFI32E01PC/WFI32E01PE, the approval is received using the integral PCB antenna. Health EN 62314 For _WFI32E01UC/WFIS2E01UE, the approval .is - Electro Magnetic EN 301 489-1 3.1(b) received using the antennas listed in Table 3-3. Compatibility (EMC) | EN 301 489-17 A.3.3.1 SIMPLIFIED EU DECLARATION OF EN 300 328 CONFORMITY The ETSI provides guidance on modular devices in Hereby, Microchip Technology Inc. declares that the “Guide to the application of harmonised standards covradio equipment type WFIS2E01 PC/WFIS2E01 PE/ . ering Article 3.1(b) and Article 3.2 of the Directive WFIS2E01UCMWFIS2E01UE is in compliance with 2014/53/EU RED to multi-radio and combined radio Diteriive AUIS SaiEU. and non-radio equipment’ document available at The full text of the EU declaration of conformity for this http://www.etsi.org/deliver/etsi_eg/203300_203399/20 product is available at http://www.micro3367/01.01.01_60/eg_203367v010101p.pdf. chip.com/PIC32MZW1 (available under Documents > Certifications). Note: To maintain conformance to the standards listed in the preceding European CompliA.3.4 HELPFUL WEBSITES ance table, themodule accordance[with][the][installation] shall be installed[instruc-] in Aunderstanding document thatthecanuse beof Shortused Rangeas a startingDevicespoint(SRD)in tions in this data sheet and shall not be in Europe is the European Radio Communications modified. When integrating a radio modCommittee (ERC) Recommendation 70-03 E, which ule into a completed product, the integracan be downloaded from the European Communicator becomes the manufacturer of the final tions Committee (ECC) at: http://www.ecodocdb.dk/. product and is therefore responsible for og ’ . . . Additional helpful web sites are: demonstrating compliance of the final product with the essential requirements ¢ Radio Equipment Directive (2014/53/EU): against the RED. https://ec.europa.eu/growth/single-market/euroA.3.1 pean-standards/harmonised-standards/red_en LABELING AND USER ¢ European Conference of Postal and TelecommuINFORMATION REQUIREMENTS nications Administrations (CEPT): The label on the final product, which contains the http://www.cept.org WFI32E01PC/WFI32E01PE/WFI32E01UC/ * European Telecommunications Standards InstiWFI32E01UE modules must follow CE marking tute (ETSI): http://www.etsi.org requirements. * The Radio Equipment Directive Compliance Association (REDCA): http://www.redca.eu/
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smn
## A.4 Other Regulatory Jurisdictions
- ¢ For information on the approvals received from the other countries’ jurisdictions, which are not covered here, are available in the http://www.microchip.com/PIC32MZW1 (available under Documents > Certifications).
- If the customer needs another regulatory jurisdiction certification or to recertify the module for other reasons, contact Microchip for the required utilities and documentation.
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## APPENDIX B: DOCUMENT REVISION HISTORY
## Revision A (September 2020)
This is the initial version of this document.
© 2020 Microchip Technology Inc.
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## smn
## THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet f F : browser, the web site contains the following information:
- ¢ Product Support — Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software
- General Technical Support — Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing
## CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels:
* Distributor or Representative . « Local: SalesooOffice ; * Field Application Engineer (FAE) * RECS Spa Customers should contact their distributor, representative or Field Application Engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document.
Technical support is available through the web site at: http://microchip.com/support
- ¢ Business of Microchip — Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives
## CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification’ and follow the registration instructions.
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## samme| Note the following details of the code protection feature on Microchip devices:
- . Microchip products meet the specifications contained in their particular Microchip Data Sheet.
- . Microchip believes that its family of products is secure when used in the intended manner and under normal conditions. . There are dishonest and possibly illegal methods being used in attempts to breach the code protection features of the Microchip devices. We believe that these methods require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Attempts to breach these code protection features, most likely, cannot be accomplished without violating Microchip's intellectual property rights.
- . Microchip is willing to work with any customer who is concerned about the integrity of its code.
- . Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code. Code protection does not mean that we are guaranteeing the product is "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may havea right to sue for relief under that Act.
Information contained in this publication is provided for the sole Trademarks purpose of designing with and using Microchip products. InforThe Microchip name and logo, the Microchip logo, Adaptec, mation regarding device applications and the like is provided —= nme eran gy Ang chipkK IT, omls fox year ieee ; ee and ern lee py ee flexPWR,chip ogo, HELDO,CryptoMemory, IGLOO, JukeBlox,CryptoRF, KeeLog,dsPIC, Kleer,FlashFlex, LANCheck, with your respons! a ity to ensure that your application meets LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, your specifications. Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, THIS INFORMATION IS PROVIDED BY MICROCHIP "AS IS". Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, MICROCHIP MAKES NO REPRESENTATIONS OR WARSST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, WRIRAN **T** IT **E** SN GAANY Ki BAHETHER EXPRESS ORM FLED, areloghctoretttvadlecnaileso ececily Teeandlogy lneogpordiedl OR ORAL, STATUTORY OR OTHERWISE, the U.S.A. and other countries. RELATED TO THE INFORMATION INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF NONAPT, ClockWorks, The Embedded Control Solutions Company, INFRINGEMENT, MERCHANTABILITY, AND FITNESS FORA EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load, PARTICULAR PURPOSE OR WARRANTIES RELATED TO Intell MOS, Libero, motorBench, mTouch, Powermite 3, Precision ITS Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, CONDITION, QUALITY, OR PERFORMANCE. SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, IN TimePictra, TimeProvider, Vite, WinPath, and ZL are registered NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDItrademarks of Microchip Technology Incorporated in the U.S.A. RECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any WHATSOEVER RELATED TO THE INFORMATION OR ITS thee —— oo Sey USE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS ryptoAuthentication, CryptoAutomotive, CryploCompanion; : d CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial ARE FORESEEABLE. TO THE FULLEST EXTENT Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF, ALL CLAIMS IN ANY WAY RELATED TO THE INFORMATION MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, OR ITS USE WILL NOT EXCEED THE AMOUNT OF FEES, IF OmniscientPICtail, PowerSmart,Code Generation,PureSilicon,PICDEM,QMatrix,PICDEM.net,REAL ICE, PICkit,Ripple ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP Blocker, SAM-ICE, Serial Quad I/O, SMART-LS., SQ, FOR THE INFORMATION. UseofMicrochip devices in life supSuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, port and/or safety applications is entirely at the buyer's risk, and USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and the buyer agrees to defend, indemnify and hold harmless ZENA are trademarks of Microchip Technology Incorporated in the . P A , U.S.A. and other countries. Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or SQTP is a service mark of Microchip Technology Incorporated in otherwise, under any Microchip intellectual property rights the U.S.A. unless otherwise stated. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany Il GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their respective companies.
© 2020, Microchip Technology Incorporated, All Rights Reserved.
For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality.
ISBN: 978-1-5224-6586-7
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## xX
## sna!
## Worldwide Sales and Service
## **e** eeener AMERICAS
## ee
## ASIA/PACIFIC
## ASIA/PACIFIC
## EUROPE
Corporate Office Australia - Sydney India - Bangalore Austria - Wels 2355 West Chandler Blvd. Tel: 61-2-9868-6733 Tel: 91-80-3090-4444 Tel: 43-7242-2244-39 Chandler, AZ 85224-6199 China - Beijing India - New Delhi Fax: 43-7242-2244-393 Tel: 480-792-7200 Tel: 86-10-8569-7000 Tel: 91-11-4160-8631 Denmark - Copenhagen renee eel China - Chengdu India - Pune Tel: 45-4485-5910 Leal ae deo Tel: 86-28-8665-5511 Tel: 91-20-4121-0141 Fax: 45-4485-2829 http://www.microchip.com/ ; . support China - Chongqing Japan - Osaka en canonn www.microchip.comWeb Address: Tel:China86-23-8980-9588- Dongguan Tel:Japan81-6-6- Tokyo 152-7160 Franceel alParis, aetlanta Tel:; 86-769-8702-9880 Tel: 81-3-6880- 3770 Tel:Fax:33-1-69-53-63-2033-1-69-30-90-79 Duluth, GA China - Guangzhou Korea - Daegu ; Tel: 678-957-9614 Tel: 86-20-8755-8029 Tel: 82-53-744-4301 Germany - Garching Fax: 678-957-1455 China - Hangzhou Bercai-'Seciil Tel: 49-8931-9700 Austin, TX Tel: 86-57 1-8792-8115 Tel: 82-2-554-7200 Germany - Haan Tel:Bostonel: 512 mLO257-3370t= Tel:ChinaP 852-2943-5100Hong Kong SAR MalaysiaTel: 60-3-7651-7906? - Kuala Lumpur Tel:Germany49-2129-3766400Heilbronn; Westborough, MA ChinaP - Nanjinges Malaysia3 - Penang Tel: 49-7131-72400 Tel: 774-760-0087 Tel: 86-25-8473-2460 Tel: 60-4-227-8870 Germany - Karlsruhe Fax: 774-760-0088 China - Qingdao Philippines - Manila Li Maa Chicago Tel: 86-532-8502-7355 Tel: 63-2-634-9065 Germany - Munich Itasca, IL China - Shanghai Singapore c-ai ee Tel: 630-285-0071 Tel: 86-21-3326-8000 Tel: 65-6334-8870 a See ET ene Gee NOTS China - Shenyang Taiwan - Hsin Chu ly a Dallas Tel: 86-24-2334-2829 Tel: 886-3-577-8366 else _— Addison, TX . : Israel - Ra’anana i leeFax: SeSA -Pe ChinaTel: 86-755-8864-2200- Shenzhen TaiwanTel: 886-7-213-7830- Kaohsiung Bie: 972-818-2924 Italy - Milan . Seaovi, Tel:China 86-186-6233-1526 - Suzhou TaiwanTel: 886-2-2508-8600- Taipei Tws nmax: a 0331-74261 peel39~poaiae Tel:4 248-848-4000 China - Wuhan Thailand - Bangkok Tel: 86-27-5980-5300 Tel: 66-2-694-1351 Italy - Padova Tel:Houston,281-894-5983 TX ChiIna - xiAlan _letnam - ———Ho 1Min Tel: 39-049-7625286 I **ndi** anapol **i** s Tel: 86-29-8833-7252 Tel: 84-28-5448-2100 ear are oa Noblesville, :31-416Tel: IN =aee Fax: 31-416-690340 Fax:317-773-8323317-773-5453 China: - Zhuhai; Tel:Norway47-7288-4388- Trondheim Tel: 317-536-2380 Tel: 86-756-3210040 Poland - Warsaw Los Angeles Tel: 48-22-3325737 tet pag ae Romania - Bucharest Tel: 949-462-9523 Tel: 40-21-407-87-50 Tel:Fax:951-273-7800949-462-9608 Spain:. Basie. Raleigh,; NC Tel:Fax:34-91-708-08-9034-91-708-08-91 Tel: 919-844-7510 Rew vers Dv Tel:Sweden46-31-704-60-40- Gothenberg Tel: 631-435-6000 Sweden - Stockholm San Jose, CA Tel: 46-8-5090-4654 Tel:Tel: 408-735-9110408-436-4270 UK - Wokingham: Tel: 44-118-921-5800 Canada - Toronto Fax: 44-118-921-5820 Tel: 905-695-1980 Fax: 905-695-2078 DS70005425A-page 692 © 2020 Microchip Technology Inc. 02/28/20
Updated at March 31, 2026
Microchip Technology Inc. is a leading global provider of smart, connected, and secure embedded control solutions. Known for enabling engineers to design with confidence, the company delivers a comprehensive product portfolio that reduces total system costs and accelerates time to market across the industrial, automotive, communications, and computing sectors. Our extensive selection of Microchip components highlights the manufacturer's strength in both discrete semiconductors and advanced wireless connectivity. We carry a robust lineup of highly efficient single MOSFETs and Schottky diodes tailored for demanding power management and switching applications. Alongside these essential discretes, engineers can source a wide array of ready-to-use networking modules, prominently featuring Bluetooth and WLAN adapters that streamline the development of modern IoT and connected devices. Rounding out the offering is a diverse range of Microchip integrated circuits and specialized components. This includes versatile I/O expanders for simplified system integration, precision timing solutions such as MEMS oscillators and pulse generators, as well as AC/DC LED driver ICs and sub-2.4GHz RF transceivers. Backed by Microchip's renowned commitment to exceptional quality and reliable performance, these components provide scalable, dependable building blocks for complex electronic designs.
About Novapart
Novapart is a B2B electronic component broker specialising in stock shortages and cost reduction. We source hard-to-find parts and identify compliant alternatives across a catalogue of 410,000+ components from 500+ manufacturers.
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When a component is unavailable, discontinued or has an unacceptable lead time, we tap into our network of vetted European and Asian distributors to source what you need — without compromising on quality or traceability.
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We identify pin-to-pin, electrically equivalent substitutes that meet the same certifications (RoHS, AEC-Q100, REACH) as your original specification — validated against datasheets, not just part numbers. Often at a lower cost.
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