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VN3205N3-G
Power MOSFET, N Channel, 50 V, 1.2 A, 0.3 ohm, TO-92, Through Hole
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- Manufacturer: MICROCHIP
- Product type: Single MOSFETs
- Transistor Polarity:N Channel; Continuous Drain Current Id:1.2A; Drain Source Voltage Vds:50V; On Resistance Rds(on):0.3ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:2.4V; P
- MSL: -
- SVHC: No SVHC (04-Feb-2026)
- No. of Pins: 3Pins
- Channel Type: N Channel
- Product Range: -
- Qualification: -
- Power Dissipation: 1W
- Transistor Mounting: Through Hole
- Rds(on) Test Voltage: 10V
- Transistor Case Style: TO-92
- Drain Source Voltage Vds: 50V
- Operating Temperature Max: 150°C
- Continuous Drain Current Id: 1.2A
- Drain Source On State Resistance: 0.3ohm
- Gate Source Threshold Voltage Max: 2.4V
| Delivery and price | |
|---|---|
| Units per pack | 1000 |
| Price | 0.94 € |
| Current stock | 50+ |
| Lead time | 30 days |
Datasheet
_**Su ertex inc. p**_ **VN3205** ## **N-Channel Enhancement-Mode Vertical DMOS FETs** ## **Features** - Free from secondary breakdown - Low power drive requirement - Ease of paralleling - Low CISS and fast switching speeds - Excellent thermal stability - Integral source-drain diode - High input impedance and high gain ## **Applications** - Motor controls ## **General Description** This enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally induced secondary breakdown. - Converters - Amplifiers Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. - Switches - Power supply circuits - Drivers (relays, hammers, solenoids, lamps, - memories, displays, bipolar transistors, etc.) **Ordering Information Product Summary Part Number Package Option Packing BVDSS/BVDGS RDS(ON) VGS(th)** VN3205N3-G 3-Lead TO-92 1000/Bag **(V) (max) (Ω) (max) (V)** 50 0.3 2.4 VN3205N3-G P002 VN3205N3-G P003 **Pin Configuration** VN3205N3-G P005 3-Lead TO-92 2000/Reel VN3205N3-G P013 VN3205N3-G P014 **DRAIN SOURCE** VN3205N8-G 3-Lead TO-243AA (SOT-89) 2000/Reel **GATE** VN3205NW Die in wafer form --- **TO-92 (N3)** VN3205NJ Die on adhesive tape --VN3205ND Die in waffle pack --- **DRAIN** _For packaged products, -G indicates package is RoHS compliant (‘Green’). TO-92 taping specifications and winding styles per EIA-468 Standard._ **SOURCE** ~~==~~ _Devices in Wafer / Die form are RoHS compliant (‘Green’)._ we **DRAIN** _Refer to Die Specification VF32 for layout and dimensions._ **GATE TO-243AA (SOT-89) (N8) Absolute Maximum Ratings Parameter Value Product Marking** Drain-to-source voltage BVDSS **SiVN** YY = Year Sealed Drain-to-gate voltage BVDGS **3 2 0 5** WW = Week Sealed Gate-to-source voltage ±20V **YYW W** = “Green” Packaging ~~———~~ Operating and storage temperature -55[O] C to +150[O] C _Package may or may not include the following marks: Si or_ ~~Oo~~ , _Absolute Maximum Ratings are those values beyond which damage to the device may_ **TO-92 (N3)** _occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground._ **VN2LW** W = Code for week sealed W = Code for week sealed **VN2LW** = “Green” Packaging _Package may or may not include the following marks: Si or_ ~~LE] —~~ **TO-243AA (SOT-89) (N8)** ## **Typical Thermal Resistance** |**Package**<br>3-Lead TO-92|**_θja_**<br>132OC/W| |---|---| |3-Lead TO-243AA(SOT-89)|133OC/W| _**Supertex inc. www.supertex.com**_ _Doc.# DSFP-VN3205 C101612_ **VN3205** ## **Thermal Characteristics** |**Package**|**ID**<br>**(continuous)* (A)**|**ID**<br>**(pulsed) (A)**|**Power Dissipation**<br>**@TC = 25OC (W)**|**IDR**<br>**_†_(A)**|**IDRM**<br> **(A)**| |---|---|---|---|---|---| |TO-92|1.2|8.0|1.0|1.2|8.0| |TO-243AA|1.5|8.0|1.6 _(TA = 25O)_|1.5|8.0| ## _**Notes:**_ - _ID (continuous) is limited by max rated Tj, Ta = 25[O] C._ - _Total for package._ - _Mounted on FR5 board, 25mm x 25mm x 1.57mm._ ## **Electrical Characteristics** _[(T] j[= 25][O][C unless otherwise specified) ]_ **==> picture [542 x 383] intentionally omitted <==** **----- Start of picture text -----**<br> Sym Parameter Min Typ Max Units Conditions<br>BVDSS Drain-to-Source breakdown voltage 50 - - V VGS = 0V, ID = 10mA<br>VGS(th) Gate threshold voltage 0.8 - 2.4 V VGS = VDS, ID = 10mA<br>ΔVGS(th) Change in VGS(th) with temperature - -4.3 -5.5 mV/ [O] C VGS = VDS, ID = 10mA<br>IGSS Gate body leakage current - 1.0 100 nA VGS = ±20V, VDS = 0V<br>- - 10 µA VGS = 0V, VDS = Max Rating<br>IDSS Zero Gate voltage drain current - - 1.0 mA VDS = 0.8 Max Rating,<br>VGS = 0V, TA = 125 [O] C<br>ID(ON) ON-state Drain current 3.0 14 - A VGS = 10V, VDS = 5.0V<br>TO-92 - - 0.45 VGS = 4.5V, ID = 1.5A<br>R Static Drain-to-Source TO-243AA - - 0.45 Ω VGS = 4.5V, ID = 0.75A<br>DS(ON) ON-state resistance TO-92 - - 0.3 VGS = 10V, ID = 3.0A<br>TO-243AA - - 0.3 VGS = 10V, ID = 1.5A<br>ΔRDS(ON) Change in RDS(ON) with temperature - 0.85 1.2 %/ [O] C VGS = 10V, ID = 3.0A<br>GFS Forward transconductance 1.0 1.5 - mho VDS = 25V, ID = 2.0A<br>CISS Input capacitance - 220 300 VGS = 0V,<br>COSS Common Source output capacitance - 70 120 pF VDS = 25V,<br>CRSS Reverse transfer capacitance - 20 30 f = 1.0MHz<br>td(ON) Turn-on delay time - - 10<br>t Rise time - - 15 VDD = 25V,<br>td(OFF)r Turn-off delay time - - 25 ns RID = 2.0A,GEN = 10Ω<br>t Fall time - - 25<br>f<br>VSD Diode forward voltage drop - - 1.6 V VGS = 0V, ISD = 1.5A<br>trr Reverse recovery time - 300 - ns VGS = 0V, ISD = 1.0A<br>**----- End of picture text -----**<br> ## _**Notes:**_ _1. All D.C. parameters 100% tested at 25[O] C unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)_ _2. All A.C. parameters sample tested._ ## **Switching Waveforms and Test Circuit** **==> picture [420 x 108] intentionally omitted <==** **----- Start of picture text -----**<br> 10V 90% VDD<br>INPUT 10% GeneratorPulse RL<br>0V OUTPUT<br>t t<br>(ON) (OFF) RGEN<br>td(ON) tr td(OFF) tf<br>VDD INPUT D.U.T.<br>10% 10%<br>OUTPUT<br>0V 90% 90%<br>**----- End of picture text -----**<br> _**Supertex inc.**_ _Doc.# DSFP-VN3205 C101612_ _**www.supertex.com**_ 2 **VN3205** ## **Typical Performance Curves** **==> picture [226 x 635] intentionally omitted <==** **----- Start of picture text -----**<br> 20 Output Characteristics<br>16 VGS = 10V<br>12 8V<br>8.0<br>6V<br>4.0<br>4V<br>3V<br>0<br>0 10 20 30 40 50<br>VDS (volts)<br>Transconductance vs. Drain Current<br>5.0<br>VDS = 25V<br>4.0<br>3.0<br> TA = -55 [O] C<br>25 [O] C<br>2.0<br>125 [O] C<br>1.0<br>0<br>0 2.0 4.0 6.0 8.0 10<br>ID (amperes)<br>Maximum Rated Safe Operating Area<br>10<br>TO-243AA<br>TO-92 (pulsed) (pulsed)<br>1.0<br>TO-243AA (DC)<br>TO-92 (DC)<br>0.1<br>TC = 25 [O] C<br>0.01<br>0 1.0 10 100<br> VDS (volts)<br>(amperes)<br>ID<br>(seimens)<br>FS<br>G<br>(amperes)<br>ID<br>**----- End of picture text -----**<br> **==> picture [228 x 637] intentionally omitted <==** **----- Start of picture text -----**<br> Saturation Characteristics<br>20<br>16 VGS = 10V<br>12 8V<br>8.0 6V<br>4.0 4V<br>3V<br>0 0 2.0 4.0 6.0 8.0 10<br>VDS (volts)<br>Power Dissipation vs. Case Temperature<br>3.2<br>2.4<br>TO-243AA<br>1.6 ( TA = 25°C)<br>TO-92<br>0.8<br>0<br>0 25 50 75 100 125 150<br>TC ( [O] C)<br>Thermal Response Characteristics<br>1.0<br>0.8<br>TO-243AA<br>TA = 25 [O] C<br>PD = 1.6W<br>0.6<br>0.4<br>0.2 TO-92<br>TC = 25 [O] C<br>PD = 1.0W<br>0<br>0.001 0.01 0.1 1.0 10<br>tp (seconds)<br>(amperes)<br>ID<br>(watts)<br>D<br>P<br>Thermal Resistance (normalized)<br>**----- End of picture text -----**<br> _**Supertex inc.**_ _Doc.# DSFP-VN3205 C101612_ _**www.supertex.com**_ 3 **VN3205** ## **Typical Performance Curves** _**(cont.)**_ **==> picture [191 x 407] intentionally omitted <==** **----- Start of picture text -----**<br> BVDSS Variation with Temperature<br>1.1<br>1.0<br>0.9<br>-50 0 50 100 150<br>Tj ( [O] C)<br>Transfer Characteristics<br>10<br>VDS =25V<br>8.0<br>6.0<br>4.0<br>2.0<br>0<br>0 2.0 4.0 6.0 8.0 10<br>V<br>GS (volts)<br>TA = -55OC<br>25OC<br>125OC<br> (normalized)<br>DSS<br>BV<br>(amperes)<br>ID<br>**----- End of picture text -----**<br> **==> picture [196 x 193] intentionally omitted <==** **----- Start of picture text -----**<br> Capacitance vs. Drain-to-Source Voltage<br>400<br>f = 1MHz<br>300<br>CISS<br>200<br>100<br>CRSS<br>0<br>0 10 20 30 40<br>VDS (volts)<br>COSS<br>C (picofarads)<br>**----- End of picture text -----**<br> **==> picture [214 x 409] intentionally omitted <==** **----- Start of picture text -----**<br> On-Resistance vs. Drain Current<br>1.0<br>VGS = 4.5V<br>0.8<br>VGS = 10V<br>0.6<br>0.4<br>0.2<br>0<br>0 4.0 8.0 12 16 20<br>ID (amperes)<br>V(th) and RDS Variation with Temperature<br>1.6<br>1.2<br>RDS(ON) @ 10V, 3.0A<br>1.1 1.4<br>1.0 1.2<br>0.9 1.0<br>VGS(th) @ 1.0mA<br>0.8 0.8<br>0.7 0.6<br>-50 0 50 100 150<br>Tj ( [O] C)<br> (ohms)<br>DSS(ON)<br>R<br>(normalized) (normalized)<br>GS(th) DS(ON)<br>V R<br>**----- End of picture text -----**<br> **==> picture [190 x 192] intentionally omitted <==** **----- Start of picture text -----**<br> Gate Drive Dynamic Characteristics<br>10<br>8.0 VDS = 10V<br>VDS = 40V<br>6.0<br>325 pF<br>4.0<br>2.0<br>215 pF<br>0<br>0 1.0 2.0 3.0 4.0 5.0<br>QG (nanocoulombs)<br>(volts)<br>GS<br>V<br>**----- End of picture text -----**<br> _**Supertex inc.**_ _Doc.# DSFP-VN3205 C101612_ _**www.supertex.com**_ 4 **VN3205** ## **3-Lead TO-92 Package Outline (N3)** **==> picture [295 x 219] intentionally omitted <==** **----- Start of picture text -----**<br> D<br>A<br>Seating<br>Plane 1 2 3<br>L<br>b c<br>e1<br>e<br>**----- End of picture text -----**<br> **==> picture [131 x 138] intentionally omitted <==** **----- Start of picture text -----**<br> Front View<br>E<br>E1<br>1 3<br>2<br>Bottom View<br>**----- End of picture text -----**<br> **==> picture [61 x 11] intentionally omitted <==** **----- Start of picture text -----**<br> Side View<br>**----- End of picture text -----**<br> **==> picture [542 x 74] intentionally omitted <==** **----- Start of picture text -----**<br> Symbol A b c D E E1 e e1 L<br>MIN .170 .014 [†] .014 [†] .175 .125 .080 .095 .045 .500<br>Dimensions<br>NOM - - - - - - - - -<br>(inches)<br>MAX .210 .022 [†] .022 [†] .205 .165 .105 .105 .055 .610*<br>**----- End of picture text -----**<br> _JEDEC Registration TO-92. * This dimension is not specified in the JEDEC drawing._ _† This dimension differs from the JEDEC drawing._ ## _**Drawings not to scale.**_ _**Supertex Doc.#:** DSPD-3TO92N3, Version E041009._ _**Supertex inc. www.supertex.com**_ _Doc.# DSFP-VN3205 C101612_ 5 **VN3205** ## **3-Lead TO-243AA (SOT-89) Package Outline (N8)** **==> picture [217 x 195] intentionally omitted <==** **----- Start of picture text -----**<br> D<br>D1<br>E H<br>1 2 3<br>L<br>b b1<br>e<br>e1<br>**----- End of picture text -----**<br> ## **Top View** **==> picture [85 x 162] intentionally omitted <==** **----- Start of picture text -----**<br> C<br>E1<br>A<br>**----- End of picture text -----**<br> ## **Side View** **==> picture [542 x 73] intentionally omitted <==** **----- Start of picture text -----**<br> Symbol A b b1 C D D1 E E1 e e1 H L<br>MIN 1.40 0.44 0.36 0.35 4.40 1.62 2.29 2.00 [†] 3.94 0.73 [†]<br>Dimensions 1.50 3.00<br>NOM - - - - - - - - - -<br>(mm) BSC BSC<br>MAX 1.60 0.56 0.48 0.44 4.60 1.83 2.60 2.29 4.25 1.20<br>**----- End of picture text -----**<br> _JEDEC Registration TO-243, Variation AA, Issue C, July 1986._ _**†** This dimension differs from the JEDEC drawing_ _**Drawings not to scale** ._ _**Supertex Doc. #:** DSPD-3TO243AAN8, Version F111010._ _(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.)_ _**Supertex inc.**_ does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate “product liability indemnification insurance agreement.” _**Supertex inc.**_ does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the _**Supertex inc.**_ (website: http//www.supertex.com) > ©2013 _**Supertex inc.**_ All rights reserved. Unauthorized use or reproduction is prohibited. _**Supertex inc.**_ 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 _**www.supertex.com**_ _Doc.# DSFP-VN3205 C101612_ 6
Updated at April 29, 2026
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